From 95e3303f7cc56ca3e1197d49acdb2ac157ae423e Mon Sep 17 00:00:00 2001 From: Sivaprasad Addepalli Date: Thu, 14 Sep 2023 12:50:57 +0530 Subject: embeddedsw : Updated SRCREV for 2023.2_5147 xilffs: Fix compilation warning usb: usbpsu: fix HIS_RETURN violation Updated changelog for cpu, versal_plm and other components tmr_inject: Fix style issues in the driver sources tmr_manager: Correct the syntax for xlnx, mask-rst-value property sw_services:xilpki:Fixed doxygen warnings sw_services:xilsecure: Avoid returning XST_SUCCESS incase of glitch sw_services: xilocp: Avoid returning XST_SUCCESS incase of glitch scugic: Fixed source code-format issue. scugic: Include xplatform_info.h for all processors scugic: Fix HIS_COMF violations scugic: Fix MISRA C violation for Rule 14.4 scugic: Fix MISRA-C violation for Rule 10.3 sw_services:xilsecure:Removed NO_EFFECT coverity warning fix. nandpsu: Update the clock node qspipsu: Update the clock node uartpsu: Update the clock node iicps: Update the clock node lib: standalone: Add the clocking to the standalone v_hdmitxss1: added tx compliance changes v_hdmirxss1: added tx compliance values v_hdmiphy1: Added new registers openamp: apps: zynqmp_r5: freertos: Remove call to vPortEnableInterrupt() cframe: Fixed MISRA-C violation 8.13 cframe: Fixed MISRA-C violation 4.6 cframe: Fixed MISRA-C violation 7.2 cframe: Fixed MISRA-C violation 10.4 cframe: Fixed MISRA-C violation 10.1 trngpsx: add SDT support sdps: Update YAML with Versal NET eMMC compatible sdps: Add support to read Tap configurations sw_services:xilplmi:Remove redundant code Xilloader: PCR security review comments xilocp: Fixed Security review comments for OCP BSP: riscv: Fix definitions for hpmevent registers xilpm: Update SSIT temperature propagation xilpm: versal: server: Fix sub-system restart on vek280 iicps: Fix doxygen warnings mipicsiss: Removing linker script usb: usbpsu: src: fix HIS_VOCF metric violation usb: usbpsu: src: fix MISRA C-2012 Rule 10.3 violation sw_services: xilsecure: Removed unused code of TRNG in xilsecure library sw_Services: xilsecure: Restricted XSecure_EccRandInit API to VersalNet sw_services: xilsecure: Use CacheInvalidate as per ARM recommendations xilpm: versal_common: server: Add missing code while integrating into Rigel workflow Signed-off-by: Siva Addepalli --- meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 27fd42c0..2d006765 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass @@ -8,7 +8,7 @@ ESW_BRANCH[2023.2] = "xlnx_rel_v2023.2-next" BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" -ESW_REV[2023.2] = "5829c0d9de3f9c3d05163fed983c09b5a22ee276" +ESW_REV[2023.2] = "79ba04717ca52a460438f4ec2da12186248adf97" SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" -- cgit v1.2.3-54-g00ecf