56 files changed, 4246 insertions, 0 deletions
diff --git a/recipes-devtools/binutils/binutils-cross-canadian_2.24.bbappend b/recipes-devtools/binutils/binutils-cross-canadian_2.24.bbappend
new file mode 100644
index 00000000..e42e7a60
--- /dev/null
+++ b/recipes-devtools/binutils/binutils-cross-canadian_2.24.bbappend
@@ -0,0 +1 @@
+require binutils-microblaze-${PV}.inc
diff --git a/recipes-devtools/binutils/binutils-cross_2.24.bbappend b/recipes-devtools/binutils/binutils-cross_2.24.bbappend
new file mode 100644
index 00000000..e42e7a60
--- /dev/null
+++ b/recipes-devtools/binutils/binutils-cross_2.24.bbappend
@@ -0,0 +1 @@
+require binutils-microblaze-${PV}.inc
diff --git a/recipes-devtools/binutils/binutils-crosssdk_2.24.bbappend b/recipes-devtools/binutils/binutils-crosssdk_2.24.bbappend
new file mode 100644
index 00000000..e42e7a60
--- /dev/null
+++ b/recipes-devtools/binutils/binutils-crosssdk_2.24.bbappend
@@ -0,0 +1 @@
+require binutils-microblaze-${PV}.inc
diff --git a/recipes-devtools/binutils/binutils-microblaze-2.24.inc b/recipes-devtools/binutils/binutils-microblaze-2.24.inc
new file mode 100644
index 00000000..71b50ee8
--- /dev/null
+++ b/recipes-devtools/binutils/binutils-microblaze-2.24.inc
@@ -0,0 +1,11 @@
+# Add MicroBlaze Patches
+FILESEXTRAPATHS_append := "${THISDIR}/files:"
+SRC_URI_append += " \
+                file://Add-wdc.ext.clear-and-wdc.ext.flush.patch \
+                file://Add-mlittle-endian-and-mbig-endian.patch \
+                file://Disable-the-warning-message-for-eh_frame_hdr.patch \
+                file://Fix-relaxation-of-assembler-resolved-reference.patch \
+                file://Fixup-debug_loc-sections-after-linker-relaxati.patch \
+                file://upstream-change-to-garbage-collection-s.patch \
+                "
diff --git a/recipes-devtools/binutils/binutils_2.24.bbappend b/recipes-devtools/binutils/binutils_2.24.bbappend
new file mode 100644
index 00000000..e42e7a60
--- /dev/null
+++ b/recipes-devtools/binutils/binutils_2.24.bbappend
@@ -0,0 +1 @@
+require binutils-microblaze-${PV}.inc
diff --git a/recipes-devtools/binutils/files/Add-mlittle-endian-and-mbig-endian.patch b/recipes-devtools/binutils/files/Add-mlittle-endian-and-mbig-endian.patch
new file mode 100644
index 00000000..984fda3f
--- /dev/null
+++ b/recipes-devtools/binutils/files/Add-mlittle-endian-and-mbig-endian.patch
@@ -0,0 +1,64 @@
+From: nagaraju <nmekala@xilix.com>
+Date: Tue, 19 Mar 2013 17:18:23 +0530
+Subject: Add mlittle-endian and mbig-endian flags
+Added support in gas for mlittle-endian and mbig-endian flags
+as options.
+Updated show usage for MicroBlaze specific assembler options
+to include new entries.
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ gas/config/tc-microblaze.c |    9 +++++++++
+ 1 file changed, 9 insertions(+)
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 872737b..b241743 100644
+--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
+@@ -37,6 +37,8 @@
+ 
+ #define OPTION_EB (OPTION_MD_BASE + 0)
+ #define OPTION_EL (OPTION_MD_BASE + 1)
+#define OPTION_LITTLE (OPTION_MD_BASE + 2)
+#define OPTION_BIG (OPTION_MD_BASE + 3)
+ 
+ void microblaze_generate_symbol (char *sym);
+ static bfd_boolean check_spl_reg (unsigned *);
+@@ -1824,6 +1826,8 @@ struct option md_longopts[] =
+ {
+   {"EB", no_argument, NULL, OPTION_EB},
+   {"EL", no_argument, NULL, OPTION_EL},
+  {"mlittle-endian", no_argument, NULL, OPTION_LITTLE},
+  {"mbig-endian", no_argument, NULL, OPTION_BIG},
+   { NULL,          no_argument, NULL, 0}
+ };
+ 
+@@ -2457,9 +2461,11 @@ md_parse_option (int c, char * arg ATTRIBUTE_UNUSED)
+   switch (c)
+     {
+     case OPTION_EB:
+    case OPTION_BIG:
+       target_big_endian = 1;
+       break;
+     case OPTION_EL:
+    case OPTION_LITTLE:
+       target_big_endian = 0;
+       break;
+     default:
+@@ -2474,6 +2480,9 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
+   /*  fprintf(stream, _("\
+       MicroBlaze options:\n\
+       -noSmall         Data in the comm and data sections do not go into the small data section\n")); */
+  fprintf (stream, _(" MicroBlaze specific assembler options:\n"));
+  fprintf (stream, "  -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu"));
+  fprintf (stream, "  -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu"));
+ }
+ 
+ 
+-- 
+1.7.9.5
diff --git a/recipes-devtools/binutils/files/Add-wdc.ext.clear-and-wdc.ext.flush.patch b/recipes-devtools/binutils/files/Add-wdc.ext.clear-and-wdc.ext.flush.patch
new file mode 100644
index 00000000..cb58f603
--- /dev/null
+++ b/recipes-devtools/binutils/files/Add-wdc.ext.clear-and-wdc.ext.flush.patch
@@ -0,0 +1,67 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 8 May 2013 11:03:36 +1000
+Subject: Add wdc.ext.clear and wdc.ext.flush insns
+Added two new instructions, wdc.ext.clear and wdc.ext.flush,
+to enable MicroBlaze to flush an external cache, which is
+used with the new coherency support for multiprocessing.
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ opcodes/microblaze-opc.h  |    5 ++++-
+ opcodes/microblaze-opcm.h |    6 +++---
+ 2 files changed, 7 insertions(+), 4 deletions(-)
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index e9da12a..dd56ab5 100644
+--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
+@@ -91,6 +91,7 @@
+ #define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */  
+ #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
+#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
+ 
+ /* New Mask for msrset, msrclr insns.  */
+@@ -101,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 289
+#define MAX_OPCODES 291
+ 
+ struct op_code_struct
+ {
+@@ -174,7 +175,9 @@ struct op_code_struct
+   {"wic",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+   {"wdc",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+   {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
+  {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+  {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 124cdec..8e531f9 100644
+--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
+@@ -31,9 +31,9 @@ enum microblaze_instr
+   idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+   ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, 
+-  wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+-  brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+-  bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar,
+  br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned,
+  blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+   bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh, 
+-- 
+1.7.9.5
diff --git a/recipes-devtools/binutils/files/Disable-the-warning-message-for-eh_frame_hdr.patch b/recipes-devtools/binutils/files/Disable-the-warning-message-for-eh_frame_hdr.patch
new file mode 100644
index 00000000..f6616a1b
--- /dev/null
+++ b/recipes-devtools/binutils/files/Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -0,0 +1,33 @@
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Fri, 22 Jun 2012 01:20:20 +0200
+Subject: Disable the warning message for eh_frame_hdr
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Upstream-Status: Pending
+---
+ bfd/elf-eh-frame.c |    9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
+index a75d806..de69cef 100644
+--- a/bfd/elf-eh-frame.c
+++ b/bfd/elf-eh-frame.c
+@@ -913,9 +913,12 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
+   goto success;
+ 
+  free_no_table:
+-  (*info->callbacks->einfo)
+-    (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
+-     abfd, sec);
+  /* FIXME: Remove the microblaze specifics when relaxing gets fixed.  */
+  if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
+    (*info->callbacks->einfo)
+      (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
+       abfd, sec);
+  }
+   hdr_info->table = FALSE;
+   if (sec_info)
+     free (sec_info);
+-- 
+1.7.9.5
diff --git a/recipes-devtools/binutils/files/Fix-relaxation-of-assembler-resolved-reference.patch b/recipes-devtools/binutils/files/Fix-relaxation-of-assembler-resolved-reference.patch
new file mode 100644
index 00000000..fb3ff355
--- /dev/null
+++ b/recipes-devtools/binutils/files/Fix-relaxation-of-assembler-resolved-reference.patch
@@ -0,0 +1,75 @@
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Tue, 14 Feb 2012 01:00:22 +0100
+Subject: Fix relaxation of assembler resolved references
+Upstream-Status: Pending
+---
+ bfd/elf32-microblaze.c     |   39 +++++++++++++++++++++++++++++++++++++++
+ gas/config/tc-microblaze.c |    1 +
+ 2 files changed, 40 insertions(+)
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 502e3c9..9de2479 100644
+--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
+@@ -1906,6 +1906,45 @@ microblaze_elf_relax_section (bfd *abfd,
+           irelscanend = irelocs + o->reloc_count;
+           for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+             {
+              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
+                {
+                  unsigned int val;
+
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+
+                  /* This was a PC-relative instruction that was completely resolved.  */
+                  if (ocontents == NULL)
+                    {
+                     if (elf_section_data (o)->this_hdr.contents != NULL)
+                         ocontents = elf_section_data (o)->this_hdr.contents;
+                     else
+                       {
+                         /* We always cache the section contents.
+                            Perhaps, if info->keep_memory is FALSE, we
+                            should free them, if we are permitted to.  */
+
+                         if (o->rawsize == 0)
+                             o->rawsize = o->size;
+                         ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
+                         if (ocontents == NULL)
+                             goto error_return;
+                         if (!bfd_get_section_contents (abfd, o, ocontents,
+                                                         (file_ptr) 0,
+                                                         o->rawsize))
+                              goto error_return;
+                         elf_section_data (o)->this_hdr.contents = ocontents;
+                       }
+                   }
+
+                  irelscan->r_addend -= calc_fixup (irelscan->r_addend
+                                                    + isym->st_value, sec);
+                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
+                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+                                                     irelscan->r_addend);
+              }
+              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
+                  fprintf(stderr, "Unhandled NONE 64\n");
+              }
+               if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+                 {
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index b241743..7dd5895 100644
+--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
+@@ -2169,6 +2169,7 @@ md_apply_fix (fixS *   fixP,
+       else
+        fixP->fx_r_type = BFD_RELOC_NONE;
+       fixP->fx_addsy = section_symbol (absolute_section);
+      fixP->fx_done = 0;
+     }
+   return;
+ }
+-- 
+1.7.9.5
diff --git a/recipes-devtools/binutils/files/Fixup-debug_loc-sections-after-linker-relaxati.patch b/recipes-devtools/binutils/files/Fixup-debug_loc-sections-after-linker-relaxati.patch
new file mode 100644
index 00000000..51ba11c4
--- /dev/null
+++ b/recipes-devtools/binutils/files/Fixup-debug_loc-sections-after-linker-relaxati.patch
@@ -0,0 +1,228 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 4 Feb 2013 12:15:22 +1000
+Subject: Fixup debug_loc sections after linker relaxation
+Adds a new reloctype R_MICROBLAZE_32_NONE, used for passing
+reloc info from the assembler to the linker when the linker
+manages to fully resolve a local symbol reference.
+This is a workaround for design flaws in the assembler to
+linker interface with regards to linker relaxation.
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ bfd/bfd-in2.h              |  5 +++++
+ bfd/elf32-microblaze.c     | 45 +++++++++++++++++++++++++++++++++++++--------
+ bfd/libbfd.h               |  1 +
+ bfd/reloc.c                |  6 ++++++
+ binutils/readelf.c         |  4 ++++
+ gas/config/tc-microblaze.c |  3 +++
+ include/elf/microblaze.h   |  1 +
+ 7 files changed, 57 insertions(+), 8 deletions(-)
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 41f7a68..b8c73b0 100644
+--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
+@@ -5190,6 +5190,11 @@ value relative to the read-write small data area anchor  */
+ expressions of the form "Symbol Op Symbol"  */
+   BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+ 
+/* This is a 32 bit reloc that stores the 32 bit pc relative
+value in two words (with an imm instruction).  No relocation is 
+done here - only used for relaxing  */
+  BFD_RELOC_MICROBLAZE_32_NONE,
+
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  No relocation is
+ done here - only used for relaxing  */
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index d94ac32..7cd0195 100644
+--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
+@@ -177,6 +177,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+           FALSE),              /* PC relative offset?  */
+ 
+    /* This reloc does nothing.  Used for relaxation.  */
+   HOWTO (R_MICROBLAZE_32_NONE,        /* Type.  */
+          0,                   /* Rightshift.  */
+          2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
+          32,                  /* Bitsize.  */
+          TRUE,                        /* PC_relative.  */
+          0,                   /* Bitpos.  */
+          complain_overflow_bitfield,  /* Complain on overflow.  */
+          NULL,                  /* Special Function.  */
+          "R_MICROBLAZE_32_NONE",/* Name.  */
+          FALSE,               /* Partial Inplace.  */
+          0,                   /* Source Mask.  */
+          0,                   /* Dest Mask.  */
+          FALSE),              /* PC relative offset?  */
+
+    HOWTO (R_MICROBLAZE_64_NONE,        /* Type.  */
+           0,                   /* Rightshift.  */
+           2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
+@@ -532,7 +546,10 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+     case BFD_RELOC_NONE:
+       microblaze_reloc = R_MICROBLAZE_NONE;
+       break;
+-    case BFD_RELOC_MICROBLAZE_64_NONE:
+    case BFD_RELOC_MICROBLAZE_32_NONE:
+      microblaze_reloc = R_MICROBLAZE_32_NONE;
+      break;
+     case BFD_RELOC_MICROBLAZE_64_NONE:
+       microblaze_reloc = R_MICROBLAZE_64_NONE;
+       break;
+     case BFD_RELOC_32:
+@@ -1851,14 +1868,22 @@ microblaze_elf_relax_section (bfd *abfd,
+                }
+              break;
+            case R_MICROBLAZE_NONE:
+           case R_MICROBLAZE_32_NONE:
+              {
+                /* This was a PC-relative instruction that was
+                   completely resolved.  */
+                int sfix, efix;
+               unsigned int val;
+                bfd_vma target_address;
+                target_address = irel->r_addend + irel->r_offset;
+                sfix = calc_fixup (irel->r_offset, 0, sec);
+                efix = calc_fixup (target_address, 0, sec);
+
+                /* Validate the in-band val.  */
+                val = bfd_get_32 (abfd, contents + irel->r_offset);
+                if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
+                    fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
+                }
+                irel->r_addend -= (efix - sfix);
+                /* Should use HOWTO.  */
+                microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
+@@ -1906,12 +1931,16 @@ microblaze_elf_relax_section (bfd *abfd,
+           irelscanend = irelocs + o->reloc_count;
+           for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+             {
+-              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
+              if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
+                 {
+                   unsigned int val;
+ 
+                   isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                  /* hax: We only do the following fixup for debug location lists.  */
+                  if (strcmp(".debug_loc", o->name))
+                    continue;
+
+                   /* This was a PC-relative instruction that was completely resolved.  */
+                   if (ocontents == NULL)
+                     {
+@@ -1936,15 +1965,15 @@ microblaze_elf_relax_section (bfd *abfd,
+                        }
+                    }
+ 
+-                  irelscan->r_addend -= calc_fixup (irelscan->r_addend
+-                                                    + isym->st_value, sec);
+                   val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
+                  if (val != irelscan->r_addend) {
+                       fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
+                  }
+
+                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
+                   microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+                                                      irelscan->r_addend);
+               }
+-              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
+-                  fprintf(stderr, "Unhandled NONE 64\n");
+-              }
+               if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+                 {
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+@@ -2004,7 +2033,7 @@ microblaze_elf_relax_section (bfd *abfd,
+                              elf_section_data (o)->this_hdr.contents = ocontents;
+                            }
+                        }
+-                     irelscan->r_addend -= calc_fixup (irel->r_addend
+                     irelscan->r_addend -= calc_fixup (irelscan->r_addend
+                                                        + isym->st_value,
+                                                        0,
+                                                        sec);
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index 1381803..034efb8 100644
+--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
+@@ -2513,6 +2513,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_32_ROSDA",
+   "BFD_RELOC_MICROBLAZE_32_RWSDA",
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+  "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 25c089c..3d2a8a8 100644
+--- a/bfd/reloc.c
+++ b/bfd/reloc.c
+@@ -6048,6 +6048,12 @@ ENUMDOC
+   This is a 32 bit reloc for the microblaze to handle
+   expressions of the form "Symbol Op Symbol"
+ ENUM
+  BFD_RELOC_MICROBLAZE_32_NONE
+ENUMDOC
+  This is a 32 bit reloc that stores the 32 bit pc relative
+  value in two words (with an imm instruction).  No relocation is
+  done here - only used for relaxing
+ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+diff --git a/binutils/readelf.c b/binutils/readelf.c
+index 19b46c9..81a027c 100644
+--- a/binutils/readelf.c
+++ b/binutils/readelf.c
+@@ -10547,6 +10547,10 @@ is_none_reloc (unsigned int reloc_type)
+       return reloc_type == 0;
+     case EM_AARCH64:
+       return reloc_type == 0 || reloc_type == 256;
+    case EM_MICROBLAZE:
+      return reloc_type == 30 /* R_MICROBLAZE_32_NONE.  */
+             || reloc_type == 0 /* R_MICROBLAZE_NONE.  */
+             || reloc_type == 9; /* R_MICROBLAZE_64_NONE.  */
+     case EM_XTENSA_OLD:
+     case EM_XTENSA:
+       return (reloc_type == 0      /* R_XTENSA_NONE.  */
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 7dd5895..884819f 100644
+--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
+@@ -2166,6 +2166,8 @@ md_apply_fix (fixS *   fixP,
+         moves code around due to relaxing.  */
+       if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
+        fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
+      else if (fixP->fx_r_type == BFD_RELOC_32)
+       fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
+       else
+        fixP->fx_r_type = BFD_RELOC_NONE;
+       fixP->fx_addsy = section_symbol (absolute_section);
+@@ -2387,6 +2389,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+   switch (fixp->fx_r_type)
+     {
+     case BFD_RELOC_NONE:
+    case BFD_RELOC_MICROBLAZE_32_NONE:
+     case BFD_RELOC_MICROBLAZE_64_NONE:
+     case BFD_RELOC_32:
+     case BFD_RELOC_MICROBLAZE_32_LO:
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index c4d9821..72771e8 100644
+--- a/include/elf/microblaze.h
+++ b/include/elf/microblaze.h
+@@ -58,6 +58,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+   RELOC_NUMBER (R_MICROBLAZE_TLSDTPREL64, 27)   /* TLS Offset Within TLS Block */
+   RELOC_NUMBER (R_MICROBLAZE_TLSGOTTPREL32, 28) /* TLS Offset From Thread Pointer */
+   RELOC_NUMBER (R_MICROBLAZE_TLSTPREL32, 29)    /* TLS Offset From Thread Pointer */
+  RELOC_NUMBER (R_MICROBLAZE_32_NONE, 30)
+    
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+ 
+-- 
+1.8.5.1
diff --git a/recipes-devtools/binutils/files/upstream-change-to-garbage-collection-s.patch b/recipes-devtools/binutils/files/upstream-change-to-garbage-collection-s.patch
new file mode 100644
index 00000000..aa571d45
--- /dev/null
+++ b/recipes-devtools/binutils/files/upstream-change-to-garbage-collection-s.patch
@@ -0,0 +1,38 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 27 Feb 2013 13:56:11 +1000
+Subject: upstream change to garbage collection sweep causes mb regression
+Upstream change for PR13177 now clears the def_regular during gc_sweep of a
+section. (All other archs in binutils/bfd/elf32-*.c received an update
+to a warning about unresolvable relocations - this warning is not present
+in binutils/bfd/elf32-microblaze.c, but this warning check would not
+prevent the error being seen)
+The visible issue with this change is when running a c++ application
+in Petalinux which links libstdc++.so for exception handling it segfaults
+on execution.
+This does not occur if static linking libstdc++.a, so its during the
+relocations for a shared lib with garbage collection this occurs
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ bfd/elflink.c | 1 -
+ 1 file changed, 1 deletion(-)
+diff --git a/bfd/elflink.c b/bfd/elflink.c
+index 99b7ca1..415d714 100644
+--- a/bfd/elflink.c
+++ b/bfd/elflink.c
+@@ -11909,7 +11909,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data)
+ 
+       inf = (struct elf_gc_sweep_symbol_info *) data;
+       (*inf->hide_symbol) (inf->info, h, TRUE);
+-      h->def_regular = 0;
+       h->ref_regular = 0;
+       h->ref_regular_nonweak = 0;
+     }
+-- 
+1.8.5.1
diff --git a/recipes-devtools/gcc/files/0001-Patch-microblaze-Enable-DWARF-exception-handling-sup.patch b/recipes-devtools/gcc/files/0001-Patch-microblaze-Enable-DWARF-exception-handling-sup.patch
new file mode 100644
index 00000000..d6549cad
--- /dev/null
+++ b/recipes-devtools/gcc/files/0001-Patch-microblaze-Enable-DWARF-exception-handling-sup.patch
@@ -0,0 +1,158 @@
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Subject: [PATCH 1/8] [Patch, microblaze]: Enable DWARF exception handling
+ support.
+Changelog
+2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+            David Holsgrove <david.holsgrove@xilinx.com>
+ * common/config/microblaze/microblaze-common.c: Remove
+   TARGET_EXCEPT_UNWIND_INFO definition.
+ * config/microblaze/microblaze-protos.h: Add
+   microblaze_eh_return prototype.
+ * gcc/config/microblaze/microblaze.c: (microblaze_must_save_register,
+   microblaze_expand_epilogue, microblaze_return_addr): Handle
+   calls_eh_return
+   (microblaze_eh_return): New function.
+ * gcc/config/microblaze/microblaze.h: Define RETURN_ADDR_OFFSET,
+   EH_RETURN_DATA_REGNO, MB_EH_STACKADJ_REGNUM, EH_RETURN_STACKADJ_RTX,
+   ASM_PREFERRED_EH_DATA_FORMAT
+ * gcc/config/microblaze/microblaze.md: Define eh_return pattern.
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Upstream-Status: Pending
+diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
+index 07a71fb..6c25a76 100644
+--- a/gcc/common/config/microblaze/microblaze-common.c
+++ b/gcc/common/config/microblaze/microblaze-common.c
+@@ -37,7 +37,4 @@ static const struct default_options microblaze_option_optimization_table[] =
+ #undef  TARGET_OPTION_OPTIMIZATION_TABLE
+ #define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table
+ 
+-#undef TARGET_EXCEPT_UNWIND_INFO
+-#define TARGET_EXCEPT_UNWIND_INFO  sjlj_except_unwind_info
+-
+ struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
+diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
+index 34be76f..201390b 100644
+--- a/gcc/config/microblaze/microblaze-protos.h
+++ b/gcc/config/microblaze/microblaze-protos.h
+@@ -54,6 +54,7 @@ extern bool microblaze_tls_referenced_p (rtx);
+ extern int symbol_mentioned_p (rtx);
+ extern int label_mentioned_p (rtx);
+ extern bool microblaze_cannot_force_const_mem (enum machine_mode, rtx);
+extern void microblaze_eh_return (rtx op0);
+ #endif  /* RTX_CODE */
+ 
+ /* Declare functions in microblaze-c.c.  */
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index c121c2b..5f4bc60 100644
+--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
+@@ -1896,6 +1896,11 @@ microblaze_must_save_register (int regno)
+   if (frame_pointer_needed && (regno == HARD_FRAME_POINTER_REGNUM))
+     return 1;
+ 
+  if (crtl->calls_eh_return
+      && regno == MB_ABI_SUB_RETURN_ADDR_REGNUM) {
+    return 1;
+  }
+
+   if (!crtl->is_leaf)
+     {
+       if (regno == MB_ABI_SUB_RETURN_ADDR_REGNUM)
+@@ -1923,6 +1928,13 @@ microblaze_must_save_register (int regno)
+        return 1;
+     }
+ 
+  if (crtl->calls_eh_return
+      && (regno == EH_RETURN_DATA_REGNO (0)
+          || regno == EH_RETURN_DATA_REGNO (1)))
+    {
+      return 1;
+    }
+
+   return 0;
+ }
+ 
+@@ -2939,6 +2951,12 @@ microblaze_expand_epilogue (void)
+       emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
+     }
+ 
+  if (crtl->calls_eh_return)
+    emit_insn (gen_addsi3 (stack_pointer_rtx,
+                           stack_pointer_rtx,
+                           gen_rtx_raw_REG (SImode,
+                                            MB_EH_STACKADJ_REGNUM)));
+
+   emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST +
+                                                    MB_ABI_SUB_RETURN_ADDR_REGNUM)));
+ }
+@@ -3166,10 +3184,13 @@ microblaze_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
+   if (count != 0)
+     return NULL_RTX;
+ 
+-  return gen_rtx_PLUS (Pmode,
+-                      get_hard_reg_initial_val (Pmode,
+-                                                MB_ABI_SUB_RETURN_ADDR_REGNUM),
+-                      GEN_INT (8));
+  return get_hard_reg_initial_val (Pmode,
+                                   MB_ABI_SUB_RETURN_ADDR_REGNUM);
+}
+
+void microblaze_eh_return (rtx op0)
+{
+  emit_insn (gen_movsi(gen_rtx_MEM(Pmode, stack_pointer_rtx), op0));
+ }
+ 
+ /* Queue an .ident string in the queue of top-level asm statements.
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index bc4d9a1..074b78e 100644
+--- a/gcc/config/microblaze/microblaze.h
+++ b/gcc/config/microblaze/microblaze.h
+@@ -184,6 +184,21 @@ extern enum pipeline_type microblaze_pipe;
+ #define INCOMING_RETURN_ADDR_RTX                       \
+   gen_rtx_REG (VOIDmode, GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
+ 
+/* Specifies the offset from INCOMING_RETURN_ADDR_RTX and the actual return PC.  */
+#define RETURN_ADDR_OFFSET (8)
+
+/* Describe how we implement __builtin_eh_return.  */
+#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? MB_ABI_FIRST_ARG_REGNUM + (N) : INVALID_REGNUM)
+
+#define MB_EH_STACKADJ_REGNUM  MB_ABI_INT_RETURN_VAL2_REGNUM
+#define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, MB_EH_STACKADJ_REGNUM)
+
+/* Select a format to encode pointers in exception handling data.  CODE
+   is 0 for data, 1 for code labels, 2 for function pointers.  GLOBAL is
+   true if the symbol may be affected by dynamic relocations.  */
+#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
+  ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr)
+
+ /* Use DWARF 2 debugging information by default.  */
+ #define DWARF2_DEBUGGING_INFO
+ #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 3618cad..4e7fe3b 100644
+--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
+@@ -2221,3 +2221,13 @@
+   [(set_attr "type"     "arith")
+   (set_attr "mode"      "SI")
+   (set_attr "length"    "4")])
+
+; This is used in compiling the unwind routines.
+(define_expand "eh_return"
+  [(use (match_operand 0 "general_operand" ""))]
+  ""
+  "
+{
+  microblaze_eh_return(operands[0]);
+  DONE;
+}")
+-- 
+1.7.5.4
diff --git a/recipes-devtools/gcc/files/0002-Patch-microblaze-Add-4-byte-implementation-for-atomi.patch b/recipes-devtools/gcc/files/0002-Patch-microblaze-Add-4-byte-implementation-for-atomi.patch
new file mode 100644
index 00000000..aefa13b0
--- /dev/null
+++ b/recipes-devtools/gcc/files/0002-Patch-microblaze-Add-4-byte-implementation-for-atomi.patch
@@ -0,0 +1,157 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Subject: [PATCH 2/8] [Patch, microblaze]: Add 4 byte implementation for
+ atomic builtin
+By providing this initial atomic implementation, gcc is able to generate the other atomic
+builtins by using a __sync_compare_and_swap loop
+Add __sync_lock_test_and_set 4 byte atomic builtin
+Changelog
+2013-03-18  David Holsgrove <david.holsgrove@xilinx.com>
+ * gcc/config/microblaze/sync.md: New file.
+ * gcc/config/microblaze/microblaze.md: Add UNSPEC_SYNC_CAS,
+   UNSPEC_SYNC_XCHG and include sync.md.
+ * gcc/config/microblaze/microblaze.c: Add print_operand 'y'.
+ * gcc/config/microblaze/constraints.md: Add memory_contraint
+   'Q' which is a single register.
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
+index c6fbc98..c9c1649 100644
+--- a/gcc/config/microblaze/constraints.md
+++ b/gcc/config/microblaze/constraints.md
+@@ -70,3 +70,8 @@
+   "Double word operand."
+   (and (match_code "mem")
+        (match_test "double_memory_operand (op, GET_MODE (op))")))
+
+(define_memory_constraint "Q"
+  "Memory operand which is a single register."
+  (and (match_code "mem")
+       (match_test "GET_CODE ( XEXP (op, 0)) == REG")))
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 5f4bc60..1562e60 100644
+--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
+@@ -2130,6 +2130,7 @@ microblaze_initial_elimination_offset (int from, int to)
+    't'  print 't' for EQ, 'f' for NE
+    'm'  Print 1<<operand.
+    'i'  Print 'i' if MEM operand has immediate value
+   'y'  Print 'y' if MEM operand is single register
+    'o' Print operand address+4
+    '?' Print 'd' if we use a branch with delay slot instead of normal branch.
+    'h'  Print high word of const_double (int or float) value as hex
+@@ -2300,6 +2301,15 @@ print_operand (FILE * file, rtx op, int letter)
+        rtx op4 = adjust_address (op, GET_MODE (op), 4);
+        output_address (XEXP (op4, 0));
+       }
+    else if (letter == 'y')
+      {
+        rtx mem_reg = XEXP (op, 0);
+        if (GET_CODE (mem_reg) == REG)
+        {
+            register int regnum = REGNO (mem_reg);
+            fprintf (file, "%s", reg_names[regnum]);
+        }
+      }
+     else
+       output_address (XEXP (op, 0));
+ 
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 4e7fe3b..55cc730 100644
+--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
+@@ -41,6 +41,8 @@
+   (UNSPEC_CMP          104)    ;; signed compare
+   (UNSPEC_CMPU         105)    ;; unsigned compare
+   (UNSPEC_TLS           106)    ;; jump table
+  (UNSPEC_SYNC_CAS     107)    ;; Represent atomic compare swap.
+  (UNSPEC_SYNC_XCHG    108)    ;; Represent atomic exchange.
+ ])
+ 
+ 
+@@ -2231,3 +2233,5 @@
+   microblaze_eh_return(operands[0]);
+   DONE;
+ }")
+
+(include "sync.md")
+diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
+new file mode 100644
+index 0000000..0923825
+--- /dev/null
+++ b/gcc/config/microblaze/sync.md
+@@ -0,0 +1,65 @@
+;; Machine description for Xilinx MicroBlaze synchronization instructions.
+;; Copyright (C) 2011, 2012
+;; Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+(define_insn "sync_compare_and_swapsi"
+  [(set (match_operand:SI 0 "register_operand" "=&d")                  ;; retval
+        (match_operand:SI 1 "nonimmediate_operand" "+Q"))              ;; mem
+    (set (match_dup 1)
+       (unspec
+           [(match_operand:SI 2 "register_operand" "d")        ;; oldval
+            (match_operand:SI 3 "register_operand" "d")]       ;; newval
+                            UNSPEC_SYNC_CAS))
+   (clobber (match_scratch:SI 4 "=&d"))]                       ;; scratch
+  ""
+  {
+    output_asm_insn ("addc \tr0,r0,r0", operands);
+    output_asm_insn ("lwx  \t%0,%y1,r0", operands);
+    output_asm_insn ("addic\t%4,r0,0", operands);
+    output_asm_insn ("bnei \t%4,.-8", operands);
+    output_asm_insn ("cmp  \t%4,%0,%2", operands);
+    output_asm_insn ("bnei \t%4,.+16", operands);
+    output_asm_insn ("swx  \t%3,%y1,r0", operands);
+    output_asm_insn ("addic\t%4,r0,0", operands);
+    output_asm_insn ("bnei \t%4,.-28", operands);
+    return "";
+  }
+)
+
+(define_insn "sync_test_and_setsi"
+  [(set (match_operand:SI 0 "register_operand" "=&d")          ;; retval
+       (match_operand:SI 1 "nonimmediate_operand" "+Q"))       ;; mem
+   (set (match_dup 1)
+       (unspec
+         [(match_operand:SI 2 "register_operand" "d")]         ;; value
+         UNSPEC_SYNC_XCHG))
+   (clobber (match_scratch:SI 3 "=&d"))]                       ;; scratch
+  ""
+  {
+    output_asm_insn ("addc \tr0,r0,r0", operands);
+    output_asm_insn ("lwx  \t%0,%y1,r0", operands);
+    output_asm_insn ("addic\t%3,r0,0", operands);
+    output_asm_insn ("bnei \t%3,.-8", operands);
+    output_asm_insn ("swx  \t%2,%y1,r0", operands);
+    output_asm_insn ("addic\t%3,r0,0", operands);
+    output_asm_insn ("bnei \t%3,.-20", operands);
+    return "";
+  }
+)
+-- 
+1.7.5.4
diff --git a/recipes-devtools/gcc/files/0003-Patch-microblaze-Extend-jump-insn-to-accept-bri-to-S.patch b/recipes-devtools/gcc/files/0003-Patch-microblaze-Extend-jump-insn-to-accept-bri-to-S.patch
new file mode 100644
index 00000000..998dfa03
--- /dev/null
+++ b/recipes-devtools/gcc/files/0003-Patch-microblaze-Extend-jump-insn-to-accept-bri-to-S.patch
@@ -0,0 +1,35 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Subject: [PATCH 3/8] [Patch, microblaze]: Extend jump insn to accept bri to
+ SYMBOL_REFS
+Current insn checks if operand is a REG - if so, uses br
+else it bri to %l0 - using a label_ref print operand
+Check if operand is a SYMBOL_REF, and if so, use %0
+Changelog
+2013-03-18  David Holsgrove <david.holsgrove@xilinx.com>
+ * gcc/config/microblaze/microblaze.md (jump):
+   Account for jumps to SYMBOL_REFs.
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 55cc730..49d8f01 100644
+--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
+@@ -1729,6 +1729,8 @@
+   {
+     if (GET_CODE (operands[0]) == REG)
+         return "br%?\t%0";
+    else if (GET_CODE (operands[0]) == SYMBOL_REF)
+        return "bri%?\t%0";
+     else       
+         return "bri%?\t%l0";
+   }
+-- 
+1.7.5.4
diff --git a/recipes-devtools/gcc/files/0004-Patch-microblaze-Add-TARGET_ASM_OUTPUT_MI_THUNK-to-s.patch b/recipes-devtools/gcc/files/0004-Patch-microblaze-Add-TARGET_ASM_OUTPUT_MI_THUNK-to-s.patch
new file mode 100644
index 00000000..5d2665eb
--- /dev/null
+++ b/recipes-devtools/gcc/files/0004-Patch-microblaze-Add-TARGET_ASM_OUTPUT_MI_THUNK-to-s.patch
@@ -0,0 +1,116 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Subject: [PATCH 4/8] [Patch, microblaze]: Add TARGET_ASM_OUTPUT_MI_THUNK to
+ support varargs thunk
+Without this macro, generic gcc generates a less efficient thunk
+that calls function instead of jumping to it. The generic code
+does not support varargs and produces an error message on compilation;
+ error: generic thunk code fails for method
+ 'virtual void C::f(const char*, ...)' which uses '...'
+Changelog
+2013-03-18  David Holsgrove <david.holsgrove@xilinx.com>
+ * gcc/config/microblaze/microblaze.c: Add microblaze_asm_output_mi_thunk
+   and define TARGET_ASM_OUTPUT_MI_THUNK and TARGET_ASM_CAN_OUTPUT_MI_THUNK
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 1562e60..7418e49 100644
+--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
+@@ -3005,6 +3005,74 @@ microblaze_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x ATTRIBUTE_UNUSED,
+ }
+ 
+ static void
+microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+                               HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
+                               tree function)
+{
+  rtx this_rtx, insn, funexp;
+
+  reload_completed = 1;
+  epilogue_completed = 1;
+
+  /* Mark the end of the (empty) prologue.  */
+  emit_note (NOTE_INSN_PROLOGUE_END);
+
+  /* Find the "this" pointer.  If the function returns a structure,
+     the structure return pointer is in MB_ABI_FIRST_ARG_REGNUM.  */
+  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
+    this_rtx = gen_rtx_REG (Pmode, (MB_ABI_FIRST_ARG_REGNUM + 1));
+  else
+    this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM);
+
+  /* Apply the constant offset, if required.  */
+  if (delta)
+    emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
+
+  /* Apply the offset from the vtable, if required.  */
+  if (vcall_offset)
+  {
+    rtx vcall_offset_rtx = GEN_INT (vcall_offset);
+    rtx tmp = gen_rtx_REG (Pmode, MB_ABI_TEMP1_REGNUM);
+
+    emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
+
+    rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
+    emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
+
+    emit_insn (gen_addsi3 (this_rtx, this_rtx, tmp));
+  }
+
+  /* Generate a tail call to the target function.  */
+  if (!TREE_USED (function))
+  {
+    assemble_external (function);
+    TREE_USED (function) = 1;
+  }
+  funexp = XEXP (DECL_RTL (function), 0);
+
+  if (flag_pic)
+  {
+    rtx scratch = gen_rtx_REG (Pmode, MB_ABI_TEMP2_REGNUM);
+    rtx reg = microblaze_legitimize_address(funexp, scratch, FUNCTION_MODE);
+    emit_move_insn (scratch, reg);
+    funexp = scratch;
+  }
+
+  emit_insn (gen_jump (funexp));
+
+  /* Run just enough of rest_of_compilation.  This sequence was
+     "borrowed" from rs6000.c.  */
+  insn = get_insns ();
+  shorten_branches (insn);
+  final_start_function (insn, file, 1);
+  final (insn, file, 1);
+  final_end_function ();
+
+  reload_completed = 0;
+  epilogue_completed = 0;
+}
+
+static void
+ microblaze_globalize_label (FILE * stream, const char *name)
+ {
+   fputs ("\t.globl\t", stream);
+@@ -3532,6 +3600,12 @@ microblaze_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x
+ #undef TARGET_SECONDARY_RELOAD
+ #define TARGET_SECONDARY_RELOAD                microblaze_secondary_reload
+ 
+#undef  TARGET_ASM_OUTPUT_MI_THUNK
+#define TARGET_ASM_OUTPUT_MI_THUNK      microblaze_asm_output_mi_thunk
+
+#undef  TARGET_ASM_CAN_OUTPUT_MI_THUNK
+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK  hook_bool_const_tree_hwi_hwi_const_tree_true
+
+ #undef TARGET_SCHED_ADJUST_COST
+ #define TARGET_SCHED_ADJUST_COST       microblaze_adjust_cost
+ 
+-- 
+1.7.5.4
diff --git a/recipes-devtools/gcc/files/0005-Patch-microblaze-Add-fstack-usage-support.patch b/recipes-devtools/gcc/files/0005-Patch-microblaze-Add-fstack-usage-support.patch
new file mode 100644
index 00000000..ee3cb9db
--- /dev/null
+++ b/recipes-devtools/gcc/files/0005-Patch-microblaze-Add-fstack-usage-support.patch
@@ -0,0 +1,30 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Subject: [PATCH 5/8] [Patch, microblaze]: Add -fstack-usage support
+Changelog
+2013-03-18  David Holsgrove <david.holsgrove@xilinx.com>
+ * gcc/config/microblaze/microblaze.c (microblaze_expand_prologue):
+   Add check for flag_stack_usage to enable -fstack-usage support
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 7418e49..4417289 100644
+--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
+@@ -2790,6 +2790,9 @@ microblaze_expand_prologue (void)
+ 
+   fsiz = compute_frame_size (get_frame_size ());
+ 
+  if (flag_stack_usage)
+    current_function_static_stack_size = fsiz;
+
+   /* If this function is a varargs function, store any registers that
+      would normally hold arguments ($5 - $10) on the stack.  */
+   if (((TYPE_ARG_TYPES (fntype) != 0
+-- 
+1.7.5.4
diff --git a/recipes-devtools/gcc/files/0006-Patch-microblaze-Remove-SECONDARY_MEMORY_NEEDED.patch b/recipes-devtools/gcc/files/0006-Patch-microblaze-Remove-SECONDARY_MEMORY_NEEDED.patch
new file mode 100644
index 00000000..923756a5
--- /dev/null
+++ b/recipes-devtools/gcc/files/0006-Patch-microblaze-Remove-SECONDARY_MEMORY_NEEDED.patch
@@ -0,0 +1,35 @@
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Subject: [PATCH 6/8] [Patch, microblaze]: Remove SECONDARY_MEMORY_NEEDED
+MicroBlaze doesn't have restrictions that would force us to
+reload regs via memory. Don't define SECONDARY_MEMORY_NEEDED.
+Fixes an ICE when compiling OpenSSL for linux.
+Changelog
+2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ * gcc/config/microblaze/microblaze.h: Remove SECONDARY_MEMORY_NEEDED
+   definition.
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@xilinx.com>
+Upstream-Status: Pending
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 074b78e..add69e8 100644
+--- a/gcc/config/microblaze/microblaze.h
+++ b/gcc/config/microblaze/microblaze.h
+@@ -422,9 +422,6 @@ extern enum reg_class microblaze_regno_to_class[];
+          || GET_MODE (X) == VOIDmode)                                  \
+         ? (GR_REGS) : (CLASS))))
+ 
+-#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)                  \
+-  (GET_MODE_CLASS (MODE) == MODE_INT)
+-
+ /* Stack layout; function entry, exit and calling.  */
+ 
+ #define STACK_GROWS_DOWNWARD
+-- 
+1.7.5.4
diff --git a/recipes-devtools/gcc/files/0007-Patch-microblaze-Add-SIZE_TYPE-and-PTRDIFF_TYPE-to-m.patch b/recipes-devtools/gcc/files/0007-Patch-microblaze-Add-SIZE_TYPE-and-PTRDIFF_TYPE-to-m.patch
new file mode 100644
index 00000000..33aee3a7
--- /dev/null
+++ b/recipes-devtools/gcc/files/0007-Patch-microblaze-Add-SIZE_TYPE-and-PTRDIFF_TYPE-to-m.patch
@@ -0,0 +1,39 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Subject: [PATCH 7/8] [Patch, microblaze]: Add SIZE_TYPE and PTRDIFF_TYPE to
+ microblaze.h
+Fixes warnings like;
+warning: format '%zX' expects argument of type 'size_t',
+but argument 3 has type 'unsigned int' [-Wformat]
+Changelog
+2013-03-18  David Holsgrove <david.holsgrove@xilinx.com>
+ * gcc/config/microblaze/microblaze.h: Define SIZE_TYPE
+   and PTRDIFF_TYPE.
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index add69e8..367e986 100644
+--- a/gcc/config/microblaze/microblaze.h
+++ b/gcc/config/microblaze/microblaze.h
+@@ -228,6 +228,12 @@ extern enum pipeline_type microblaze_pipe;
+ #define STRICT_ALIGNMENT        1
+ #define PCC_BITFIELD_TYPE_MATTERS 1
+ 
+#undef SIZE_TYPE
+#define SIZE_TYPE "unsigned int"
+
+#undef PTRDIFF_TYPE
+#define PTRDIFF_TYPE "int"
+
+ #define CONSTANT_ALIGNMENT(EXP, ALIGN)                                 \
+   ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)  \
+    && (ALIGN) < BITS_PER_WORD                                          \
+-- 
+1.7.5.4
diff --git a/recipes-devtools/gcc/files/0008-Patch-microblaze-Add-branch_compare-instruction.patch b/recipes-devtools/gcc/files/0008-Patch-microblaze-Add-branch_compare-instruction.patch
new file mode 100644
index 00000000..4da74f3f
--- /dev/null
+++ b/recipes-devtools/gcc/files/0008-Patch-microblaze-Add-branch_compare-instruction.patch
@@ -0,0 +1,224 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Subject: [PATCH 8/8] [Patch, microblaze]: Add branch_compare instruction
+To facilitate optimization pass understanding of the conditional
+branch for microblaze, remove the UNSPEC'd signed_compare /
+unsigned_compare instructions, and replace with a complete
+branch_compare which will output_asm_insn the correct cmp/cmpu
+depending on comparison code and signed / unsigned.
+We then return the correct branch instruction.
+cbranchsi now calls an expanded microblaze_expand_conditional_branch
+function which will carry out compare against zero, compare EQ/NE,
+and all other compares appropriately.
+-funroll-loops optimization pass can now proceed
+Changelog
+2013-03-19  David Holsgrove <david.holsgrove@xilinx.com>
+ * gcc/config/microblaze/predicates.md: Add cmp_op predicate.
+ * gcc/config/microblaze/microblaze.md: Add branch_compare
+   instruction which uses cmp_op predicate and emits cmp insn
+   before branch.
+ * gcc/config/microblaze/microblaze.c
+   (microblaze_emit_compare): Rename to
+   microblaze_expand_conditional_branch and consolidate logic.
+   (microblaze_expand_conditional_branch): emit branch_compare
+   insn instead of handling cmp op separate from branch insn.
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 4417289..84b58bf 100644
+--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
+@@ -3336,65 +3336,45 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
+   emit_move_insn (mem, fnaddr);
+ }
+ 
+-/* Emit instruction to perform compare.  
+-   cmp is (compare_op op0 op1).  */
+-static rtx
+-microblaze_emit_compare (enum machine_mode mode, rtx cmp, enum rtx_code *cmp_code)
+/* Generate conditional branch -- first, generate test condition,
+   second, generate correct branch instruction.  */
+
+void
+microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[])
+ {
+-  rtx cmp_op0 = XEXP (cmp, 0);
+-  rtx cmp_op1 = XEXP (cmp, 1);
+  enum rtx_code code = GET_CODE (operands[0]);
+  rtx cmp_op0 = operands[1];
+  rtx cmp_op1 = operands[2];
+  rtx label1 = operands[3];
+   rtx comp_reg = gen_reg_rtx (SImode);
+-  enum rtx_code code = *cmp_code;
+-  
+  rtx condition;
+
+   gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
+ 
+   /* If comparing against zero, just test source reg.  */
+-  if (cmp_op1 == const0_rtx) 
+-    return cmp_op0;
+  if (cmp_op1 == const0_rtx)
+    {
+      comp_reg = cmp_op0;
+      condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
+      emit_jump_insn (gen_condjump (condition, label1));
+    }
+ 
+-  if (code == EQ || code == NE)
+  else if (code == EQ || code == NE)
+     {
+       /* Use xor for equal/not-equal comparison.  */
+       emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
+      condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
+      emit_jump_insn (gen_condjump (condition, label1));
+     }
+-  else if (code == GT || code == GTU || code == LE || code == LEU)
+-    {
+-      /* MicroBlaze compare is not symmetrical.  */
+-      /* Swap argument order.  */
+-      cmp_op1 = force_reg (mode, cmp_op1);
+-      if (code == GT || code == LE) 
+-        emit_insn (gen_signed_compare (comp_reg, cmp_op0, cmp_op1));
+-      else
+-        emit_insn (gen_unsigned_compare (comp_reg, cmp_op0, cmp_op1));
+-      /* Translate test condition.  */
+-      *cmp_code = swap_condition (code);
+-    }
+-  else /* if (code == GE || code == GEU || code == LT || code == LTU) */
+  else
+     {
+      /* Generate compare and branch in single instruction. */
+       cmp_op1 = force_reg (mode, cmp_op1);
+-      if (code == GE || code == LT) 
+-        emit_insn (gen_signed_compare (comp_reg, cmp_op1, cmp_op0));
+-      else
+-        emit_insn (gen_unsigned_compare (comp_reg, cmp_op1, cmp_op0));
+      condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
+      emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
+     }
+-
+-  return comp_reg;
+ }
+ 
+-/* Generate conditional branch -- first, generate test condition,
+-   second, generate correct branch instruction.  */
+-
+-void
+-microblaze_expand_conditional_branch (enum machine_mode mode, rtx operands[])
+-{
+-  enum rtx_code code = GET_CODE (operands[0]);
+-  rtx comp;
+-  rtx condition;
+-
+-  comp = microblaze_emit_compare (mode, operands[0], &code);
+-  condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp, const0_rtx);
+-  emit_jump_insn (gen_condjump (condition, operands[3]));
+-}
+ 
+ void
+ microblaze_expand_conditional_branch_sf (rtx operands[])
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 49d8f01..9c1e1a3 100644
+--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
+@@ -1624,28 +1624,6 @@
+   (set_attr "length"   "4")]
+ )              
+ 
+-(define_insn "signed_compare"
+-  [(set (match_operand:SI 0 "register_operand" "=d")
+-       (unspec
+-               [(match_operand:SI 1 "register_operand" "d")
+-                (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMP))]
+-  ""
+-  "cmp\t%0,%1,%2"
+-  [(set_attr "type"    "arith")
+-  (set_attr "mode"     "SI")
+-  (set_attr "length"   "4")])
+-
+-(define_insn "unsigned_compare"
+-  [(set (match_operand:SI 0 "register_operand" "=d")
+-       (unspec 
+-               [(match_operand:SI 1 "register_operand" "d")
+-                (match_operand:SI 2 "register_operand" "d")] UNSPEC_CMPU))]
+-  ""
+-  "cmpu\t%0,%1,%2"
+-  [(set_attr "type"    "arith")
+-  (set_attr "mode"     "SI")
+-  (set_attr "length"   "4")])
+-
+ ;;----------------------------------------------------------------
+ ;; Setting a register from an floating point comparison. 
+ ;;----------------------------------------------------------------
+@@ -1719,6 +1697,47 @@
+    (set_attr "length"  "4")]
+ )
+ 
+(define_insn "branch_compare"
+  [(set (pc)
+        (if_then_else (match_operator:SI 0 "cmp_op"
+                                         [(match_operand:SI 1 "register_operand" "d")
+                                          (match_operand:SI 2 "register_operand" "d")
+                                         ])
+                      (label_ref (match_operand 3))
+                      (pc)))
+  (clobber(reg:SI R_TMP))]
+  ""
+  {
+    operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
+    enum rtx_code code = GET_CODE (operands[0]);
+
+    if (code == GT || code == LE)
+      {
+        output_asm_insn ("cmp\tr18,%z1,%z2", operands);
+        code = swap_condition (code);
+      }
+    else if (code == GTU || code == LEU)
+      {
+        output_asm_insn ("cmpu\tr18,%z1,%z2", operands);
+        code = swap_condition (code);
+      }
+    else if (code == GE || code == LT)
+      {
+        output_asm_insn ("cmp\tr18,%z2,%z1", operands);
+      }
+    else if (code == GEU || code == LTU)
+      {
+        output_asm_insn ("cmpu\tr18,%z2,%z1", operands);
+      }
+
+    operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx);
+    return "b%C0i%?\tr18,%3";
+  }
+  [(set_attr "type"     "branch")
+   (set_attr "mode"     "none")
+   (set_attr "length"   "12")]
+)
+
+ ;;----------------------------------------------------------------
+ ;; Unconditional branches
+ ;;----------------------------------------------------------------
+diff --git a/gcc/config/microblaze/predicates.md b/gcc/config/microblaze/predicates.md
+index 5fd1bd4..2c23291 100644
+--- a/gcc/config/microblaze/predicates.md
+++ b/gcc/config/microblaze/predicates.md
+@@ -119,3 +119,7 @@
+ ;; Test for valid PIC call operand
+ (define_predicate "call_insn_plt_operand"
+   (match_test "PLT_ADDR_P (op)"))
+
+;; Return if the code of this rtx pattern is a comparison.
+(define_predicate "cmp_op"
+  (match_code "gt,ge,gtu,geu,lt,le,ltu,leu"))
+-- 
+1.7.5.4
diff --git a/recipes-devtools/gcc/files/Patch-microblaze-Fix-bswaphi2-implementation.patch b/recipes-devtools/gcc/files/Patch-microblaze-Fix-bswaphi2-implementation.patch
new file mode 100644
index 00000000..b39dc4db
--- /dev/null
+++ b/recipes-devtools/gcc/files/Patch-microblaze-Fix-bswaphi2-implementation.patch
@@ -0,0 +1,44 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Subject: [PATCH] [Patch, microblaze]: Fix bswaphi2 implementation
+MicroBlaze insn swaph swaps the contents of register rA
+as two halfwords placing result in rD;
+(rD)[0:15]  <- (rA)[16:31]
+(rD)[16:31] <- (rA)[0:15]
+gcc bswaphi2 is intended to reverse the order of the bytes
+in the half integer in rA
+(rD)[8:15]  <- (rA)[0:7]
+(rD)[7:0]   <- (rA)[8:15]
+(rD)[24:31] <- (rA)[16:23]
+(rD)[16:23] <- (rA)[24:31]
+Correct microblaze bswaphi2 insn pattern to be a
+swapb followed by swaph
+Reported-by: Nathan Rossi <nathan.rossi@xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index ae4ade7..c7485fc 100644
+--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
+@@ -367,7 +367,8 @@
+   [(set (match_operand:HI 0 "register_operand" "=r")
+         (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
+   "TARGET_REORDER"
+-  "swaph %0, %1"
+  "swapb %0, %1
+   swaph %0, %0"
+ )
+ 
+ ;;----------------------------------------------------------------
+-- 
+1.7.1
diff --git a/recipes-devtools/gcc/files/Patch-microblaze-cstoresf4-add-mode-and-ordered_comp.patch b/recipes-devtools/gcc/files/Patch-microblaze-cstoresf4-add-mode-and-ordered_comp.patch
new file mode 100644
index 00000000..934e7fa9
--- /dev/null
+++ b/recipes-devtools/gcc/files/Patch-microblaze-cstoresf4-add-mode-and-ordered_comp.patch
@@ -0,0 +1,44 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Subject: [PATCH] [Patch, microblaze]: cstoresf4, add mode and
+ ordered_comparison_operator
+Add SImode to comparison operator, prevents ICE during combine
+rtl pass with error message;
+internal compiler error: in simplify_subreg, at simplify-rtx.c:5725
+Use ordered_comparison_operator predicate to limit operators to
+those fcmp can handle, and letting compiler reorder insns to
+accomodate unordered as necessary
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/config/microblaze/microblaze.md |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 786dabb..e9b032b 100644
+--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
+@@ -1650,7 +1650,7 @@
+ ;;----------------------------------------------------------------
+ (define_insn "cstoresf4"
+    [(set (match_operand:SI 0 "register_operand" "=r")
+-        (match_operator 1 "comparison_operator"
+        (match_operator:SI 1 "ordered_comparison_operator"
+              [(match_operand:SF 2 "register_operand" "r")
+               (match_operand:SF 3 "register_operand" "r")]))]
+   "TARGET_HARD_FLOAT"
+@@ -1679,7 +1679,7 @@
+ 
+ (define_expand "cbranchsf4"
+   [(set (pc)
+-       (if_then_else (match_operator 0 "comparison_operator"
+       (if_then_else (match_operator 0 "ordered_comparison_operator"
+                       [(match_operand:SF 1 "register_operand")
+                        (match_operand:SF 2 "register_operand")])
+                      (label_ref (match_operand 3 ""))
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gcc/files/gcc-Cherry-pick-mainline-patch-to-resolve-MB-k.patch b/recipes-devtools/gcc/files/gcc-Cherry-pick-mainline-patch-to-resolve-MB-k.patch
new file mode 100644
index 00000000..1cdc4029
--- /dev/null
+++ b/recipes-devtools/gcc/files/gcc-Cherry-pick-mainline-patch-to-resolve-MB-k.patch
@@ -0,0 +1,110 @@
+Subject: Cherry-pick mainline patch to resolve MB kernel panic
+Cherry-pick backend optimization patch from gcc HEAD which 'resolves' a kernel
+panic for microblaze when compiled with -Os
+Upstream HEAD (soon to be gcc 4.9) does not exhibt this error any longer,
+and this patch when applied as a workaround on the 4.8 branch also hides the
+kernel panic resulting from incorrect branch-delay slot filling.
+        * tree-ssa-threadedge.c (thread_around_empty_block): Remove
+        checks for the number of predecessors and successors allowed.
+        * tree-ssa-threadupdate.c (mark_threaded_blocks): Ignore requests
+        which require copying a joiner block if there is a request which
+        is a subpath that requires no joiner block copying.
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Backport
+---
+ gcc/tree-ssa-threadedge.c   |    8 -------
+ gcc/tree-ssa-threadupdate.c |   49 ++++++++++++++++++++++++++++++++++++++-----
+ 2 files changed, 44 insertions(+), 13 deletions(-)
+diff --git a/gcc/tree-ssa-threadedge.c b/gcc/tree-ssa-threadedge.c
+index b31e961..ab58ae8 100644
+--- a/gcc/tree-ssa-threadedge.c
+++ b/gcc/tree-ssa-threadedge.c
+@@ -761,14 +761,6 @@ thread_around_empty_block (edge taken_edge,
+   gimple stmt;
+   tree cond;
+ 
+-  /* This block must have a single predecessor (E->dest).  */
+-  if (!single_pred_p (bb))
+-    return NULL;
+-
+-  /* This block must have more than one successor.  */
+-  if (single_succ_p (bb))
+-    return NULL;
+-
+   /* This block can have no PHI nodes.  This is overly conservative.  */
+   if (!gsi_end_p (gsi_start_phis (bb)))
+     return NULL;
+diff --git a/gcc/tree-ssa-threadupdate.c b/gcc/tree-ssa-threadupdate.c
+index 0e4cbc9..cf8df8e 100644
+--- a/gcc/tree-ssa-threadupdate.c
+++ b/gcc/tree-ssa-threadupdate.c
+@@ -1146,17 +1146,56 @@ mark_threaded_blocks (bitmap threaded_blocks)
+   edge e;
+   edge_iterator ei;
+ 
+  /* It is possible to have jump threads in which one is a subpath
+     of the other.  ie, (A, B), (B, C), (C, D) where B is a joiner
+     block and (B, C), (C, D) where no joiner block exists.
+
+     When this occurs ignore the jump thread request with the joiner
+     block.  It's totally subsumed by the simpler jump thread request.
+
+     This results in less block copying, simpler CFGs.  More improtantly,
+     when we duplicate the joiner block, B, in this case we will create
+     a new threading opportunity that we wouldn't be able to optimize
+     until the next jump threading iteration. 
+
+     So first convert the jump thread requests which do not require a
+     joiner block.  */
+   for (i = 0; i < threaded_edges.length (); i += 3)
+     {
+       edge e = threaded_edges[i];
+-      edge *x = XNEWVEC (edge, 2);
+ 
+-      e->aux = x;
+-      THREAD_TARGET (e) = threaded_edges[i + 1];
+-      THREAD_TARGET2 (e) = threaded_edges[i + 2];
+-      bitmap_set_bit (tmp, e->dest->index);
+      if (threaded_edges[i + 2] == NULL)
+       {
+         edge *x = XNEWVEC (edge, 2);
+
+         e->aux = x;
+         THREAD_TARGET (e) = threaded_edges[i + 1];
+         THREAD_TARGET2 (e) = NULL;
+         bitmap_set_bit (tmp, e->dest->index);
+       }
+     }
+ 
+
+  /* Now iterate again, converting cases where we threaded through
+     a joiner block, but ignoring those where we have already
+     threaded through the joiner block.  */
+  for (i = 0; i < threaded_edges.length (); i += 3)
+    {
+      edge e = threaded_edges[i];
+
+      if (threaded_edges[i + 2] != NULL
+         && threaded_edges[i + 1]->aux == NULL)
+       {
+         edge *x = XNEWVEC (edge, 2);
+
+         e->aux = x;
+         THREAD_TARGET (e) = threaded_edges[i + 1];
+         THREAD_TARGET2 (e) = threaded_edges[i + 2];
+         bitmap_set_bit (tmp, e->dest->index);
+       }
+    }
+
+
+   /* If optimizing for size, only thread through block if we don't have
+      to duplicate it or it's an otherwise empty redirection block.  */
+   if (optimize_function_for_size_p (cfun))
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gcc/gcc-cross-canadian_4.8.bbappend b/recipes-devtools/gcc/gcc-cross-canadian_4.8.bbappend
new file mode 100644
index 00000000..e28b4dd0
--- /dev/null
+++ b/recipes-devtools/gcc/gcc-cross-canadian_4.8.bbappend
@@ -0,0 +1 @@
+require gcc-microblaze-4.8.inc
diff --git a/recipes-devtools/gcc/gcc-cross-initial_4.8.bbappend b/recipes-devtools/gcc/gcc-cross-initial_4.8.bbappend
new file mode 100644
index 00000000..e28b4dd0
--- /dev/null
+++ b/recipes-devtools/gcc/gcc-cross-initial_4.8.bbappend
@@ -0,0 +1 @@
+require gcc-microblaze-4.8.inc
diff --git a/recipes-devtools/gcc/gcc-cross_4.8.bbappend b/recipes-devtools/gcc/gcc-cross_4.8.bbappend
new file mode 100644
index 00000000..e28b4dd0
--- /dev/null
+++ b/recipes-devtools/gcc/gcc-cross_4.8.bbappend
@@ -0,0 +1 @@
+require gcc-microblaze-4.8.inc
diff --git a/recipes-devtools/gcc/gcc-crosssdk-initial_4.8.bbappend b/recipes-devtools/gcc/gcc-crosssdk-initial_4.8.bbappend
new file mode 100644
index 00000000..e28b4dd0
--- /dev/null
+++ b/recipes-devtools/gcc/gcc-crosssdk-initial_4.8.bbappend
@@ -0,0 +1 @@
+require gcc-microblaze-4.8.inc
diff --git a/recipes-devtools/gcc/gcc-crosssdk_4.8.bbappend b/recipes-devtools/gcc/gcc-crosssdk_4.8.bbappend
new file mode 100644
index 00000000..e28b4dd0
--- /dev/null
+++ b/recipes-devtools/gcc/gcc-crosssdk_4.8.bbappend
@@ -0,0 +1 @@
+require gcc-microblaze-4.8.inc
diff --git a/recipes-devtools/gcc/gcc-microblaze-4.8.inc b/recipes-devtools/gcc/gcc-microblaze-4.8.inc
new file mode 100644
index 00000000..675ecaf0
--- /dev/null
+++ b/recipes-devtools/gcc/gcc-microblaze-4.8.inc
@@ -0,0 +1,16 @@
+# Add MicroBlaze Patches
+FILESEXTRAPATHS_append := "${THISDIR}/files:"
+SRC_URI_append += " \
+                file://0001-Patch-microblaze-Enable-DWARF-exception-handling-sup.patch \
+                file://0002-Patch-microblaze-Add-4-byte-implementation-for-atomi.patch \
+                file://0003-Patch-microblaze-Extend-jump-insn-to-accept-bri-to-S.patch \
+                file://0004-Patch-microblaze-Add-TARGET_ASM_OUTPUT_MI_THUNK-to-s.patch \
+                file://0005-Patch-microblaze-Add-fstack-usage-support.patch \
+                file://0006-Patch-microblaze-Remove-SECONDARY_MEMORY_NEEDED.patch \
+                file://0007-Patch-microblaze-Add-SIZE_TYPE-and-PTRDIFF_TYPE-to-m.patch \
+                file://0008-Patch-microblaze-Add-branch_compare-instruction.patch \
+                file://Patch-microblaze-Fix-bswaphi2-implementation.patch \
+                file://Patch-microblaze-cstoresf4-add-mode-and-ordered_comp.patch \
+                file://gcc-Cherry-pick-mainline-patch-to-resolve-MB-k.patch \
+                "
diff --git a/recipes-devtools/gcc/gcc-runtime_4.8.bbappend b/recipes-devtools/gcc/gcc-runtime_4.8.bbappend
new file mode 100644
index 00000000..e28b4dd0
--- /dev/null
+++ b/recipes-devtools/gcc/gcc-runtime_4.8.bbappend
@@ -0,0 +1 @@
+require gcc-microblaze-4.8.inc
diff --git a/recipes-devtools/gcc/gcc_4.8.bbappend b/recipes-devtools/gcc/gcc_4.8.bbappend
new file mode 100644
index 00000000..e28b4dd0
--- /dev/null
+++ b/recipes-devtools/gcc/gcc_4.8.bbappend
@@ -0,0 +1 @@
+require gcc-microblaze-4.8.inc
diff --git a/recipes-devtools/gcc/libgcc_4.8.bbappend b/recipes-devtools/gcc/libgcc_4.8.bbappend
new file mode 100644
index 00000000..e28b4dd0
--- /dev/null
+++ b/recipes-devtools/gcc/libgcc_4.8.bbappend
@@ -0,0 +1 @@
+require gcc-microblaze-4.8.inc
diff --git a/recipes-devtools/gdb/files/0001-Add-initial-port-of-linux-gdbserver.patch b/recipes-devtools/gdb/files/0001-Add-initial-port-of-linux-gdbserver.patch
new file mode 100644
index 00000000..5c195538
--- /dev/null
+++ b/recipes-devtools/gdb/files/0001-Add-initial-port-of-linux-gdbserver.patch
@@ -0,0 +1,471 @@
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Mon, 6 Feb 2012 10:28:29 +1000
+Subject: Add initial port of linux gdbserver
+add gdb_proc_service_h to gdbserver microblaze-linux
+gdbserver needs to initialise the microblaze registers
+other archs use this step to run a *_arch_setup() to carry out all
+architecture specific setup - may need to add in future
+ * add linux-ptrace.o to gdbserver configure
+ * Update breakpoint opcode
+ * fix segfault on connecting gdbserver
+ * add microblaze_linux_memory_remove_breakpoint
+ * add set_solib_svr4_fetch_link_map_offsets
+ * add set_gdbarch_fetch_tls_load_module_address
+ * Force reading of r0 as 0, prevent stores
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+Upstream-Status: Pending
+---
+ gdb/configure.host                   |    3 +
+ gdb/gdbserver/linux-microblaze-low.c |  228 ++++++++++++++++++++++++++++++++++
+ gdb/microblaze-linux-tdep.c          |   30 ++++-
+ gdb/microblaze-tdep.c                |   35 ++++++
+ gdb/microblaze-tdep.h                |    3 +-
+ gdb/regformats/reg-microblaze.dat    |   39 ++++++
+ 6 files changed, 336 insertions(+), 2 deletions(-)
+ create mode 100644 gdb/gdbserver/linux-microblaze-low.c
+ create mode 100644 gdb/regformats/reg-microblaze.dat
+diff --git a/gdb/configure.host b/gdb/configure.host
+index 85f4491..98b0f43 100644
+--- a/gdb/configure.host
+++ b/gdb/configure.host
+@@ -47,6 +47,7 @@ i[34567]86*)          gdb_host_cpu=i386 ;;
+ m68*)                  gdb_host_cpu=m68k ;;
+ m88*)                  gdb_host_cpu=m88k ;;
+ mips*)                 gdb_host_cpu=mips ;;
+microblaze*)           gdb_host_cpu=microblaze ;;
+ powerpc* | rs6000)     gdb_host_cpu=powerpc ;;
+ sparcv9 | sparc64)     gdb_host_cpu=sparc ;;
+ s390*)                 gdb_host_cpu=s390 ;;
+@@ -126,6 +127,8 @@ mips*-*-netbsd* | mips*-*-knetbsd*-gnu)
+                        gdb_host=nbsd ;;
+ mips64*-*-openbsd*)    gdb_host=obsd64 ;;
+ 
+microblaze*-*linux*)   gdb_host=linux ;;
+
+ powerpc-*-aix* | rs6000-*-*)
+                        gdb_host=aix ;;
+ powerpc*-*-freebsd*)   gdb_host=fbsd ;;
+diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c
+new file mode 100644
+index 0000000..279df9f
+--- /dev/null
+++ b/gdb/gdbserver/linux-microblaze-low.c
+@@ -0,0 +1,228 @@
+/* GNU/Linux/Microblaze specific low level interface, for the remote server for
+   GDB.
+   Copyright (C) 1995-2013 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#include "server.h"
+#include "linux-low.h"
+
+#include <asm/ptrace.h>
+#include <sys/procfs.h>
+#include <sys/ptrace.h>
+
+#include "gdb_proc_service.h"
+
+static int microblaze_regmap[] =
+ {PT_GPR(0),     PT_GPR(1),     PT_GPR(2),     PT_GPR(3),
+  PT_GPR(4),     PT_GPR(5),     PT_GPR(6),     PT_GPR(7),
+  PT_GPR(8),     PT_GPR(9),     PT_GPR(10),    PT_GPR(11),
+  PT_GPR(12),    PT_GPR(13),    PT_GPR(14),    PT_GPR(15),
+  PT_GPR(16),    PT_GPR(17),    PT_GPR(18),    PT_GPR(19),
+  PT_GPR(20),    PT_GPR(21),    PT_GPR(22),    PT_GPR(23),
+  PT_GPR(24),    PT_GPR(25),    PT_GPR(26),    PT_GPR(27),
+  PT_GPR(28),    PT_GPR(29),    PT_GPR(30),    PT_GPR(31),
+  PT_PC,         PT_MSR,        PT_EAR,        PT_ESR,
+  PT_FSR
+  };
+
+#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
+
+/* Defined in auto-generated file microblaze-linux.c.  */
+void init_registers_microblaze (void);
+extern const struct target_desc *tdesc_microblaze;
+
+static int
+microblaze_cannot_store_register (int regno)
+{
+  if (microblaze_regmap[regno] == -1 || regno == 0)
+    return 1;
+
+  return 0;
+}
+
+static int
+microblaze_cannot_fetch_register (int regno)
+{
+  return 0;
+}
+
+static CORE_ADDR
+microblaze_get_pc (struct regcache *regcache)
+{
+  unsigned long pc;
+
+  collect_register_by_name (regcache, "pc", &pc);
+  return (CORE_ADDR) pc;
+}
+
+static void
+microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
+{
+  unsigned long newpc = pc;
+
+  supply_register_by_name (regcache, "pc", &newpc);
+}
+
+/* dbtrap insn */
+/* brki r16, 0x18; */
+static const unsigned long microblaze_breakpoint = 0xba0c0018;
+#define microblaze_breakpoint_len 4
+
+static int
+microblaze_breakpoint_at (CORE_ADDR where)
+{
+  unsigned long insn;
+
+  (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
+  if (insn == microblaze_breakpoint)
+    return 1;
+  /* If necessary, recognize more trap instructions here.  GDB only uses the
+     one.  */
+  return 0;
+}
+
+static CORE_ADDR
+microblaze_reinsert_addr (struct regcache *regcache)
+{
+  unsigned long pc;
+  collect_register_by_name (regcache, "r15", &pc);
+  return pc;
+}
+
+#ifdef HAVE_PTRACE_GETREGS
+
+static void
+microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
+{
+  int size = register_size (regcache->tdesc, regno);
+
+  memset (buf, 0, sizeof (long));
+
+  if (size < sizeof (long))
+    collect_register (regcache, regno, buf + sizeof (long) - size);
+  else
+    collect_register (regcache, regno, buf);
+}
+
+static void
+microblaze_supply_ptrace_register (struct regcache *regcache,
+                           int regno, const char *buf)
+{
+  int size = register_size (regcache->tdesc, regno);
+
+  if (regno == 0) {
+    unsigned long regbuf_0 = 0;
+    /* clobbering r0 so that it is always 0 as enforced by hardware */
+    supply_register (regcache, regno, (const char*)&regbuf_0);
+  } else {
+      if (size < sizeof (long))
+        supply_register (regcache, regno, buf + sizeof (long) - size);
+      else
+        supply_register (regcache, regno, buf);
+  }
+}
+
+/* Provide only a fill function for the general register set.  ps_lgetregs
+   will use this for NPTL support.  */
+
+static void microblaze_fill_gregset (struct regcache *regcache, void *buf)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]);
+}
+
+static void
+microblaze_store_gregset (struct regcache *regcache, const void *buf)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    supply_register (regcache, i, (char *) buf + microblaze_regmap[i]);
+}
+
+#endif /* HAVE_PTRACE_GETREGS */
+
+static struct regset_info microblaze_regsets[] = {
+#ifdef HAVE_PTRACE_GETREGS
+  { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
+  { 0, 0, 0, -1, -1, NULL, NULL },
+#endif /* HAVE_PTRACE_GETREGS */
+  { 0, 0, 0, -1, -1, NULL, NULL }
+};
+
+static struct regsets_info microblaze_regsets_info =
+  {
+    microblaze_regsets, /* regsets */
+    0, /* num_regsets */
+    NULL, /* disabled_regsets */
+  };
+
+static struct usrregs_info microblaze_usrregs_info =
+  {
+    microblaze_num_regs,
+    microblaze_regmap,
+  };
+
+static struct regs_info regs_info =
+  {
+    NULL, /* regset_bitmap */
+    &microblaze_usrregs_info,
+    &microblaze_regsets_info
+  };
+
+static const struct regs_info *
+microblaze_regs_info (void)
+{
+  return &regs_info;
+}
+
+static void
+microblaze_arch_setup (void)
+{
+  current_process ()->tdesc = tdesc_microblaze;
+}
+
+struct linux_target_ops the_low_target = {
+  microblaze_arch_setup,
+  microblaze_regs_info,
+  microblaze_cannot_fetch_register,
+  microblaze_cannot_store_register,
+  NULL, /* fetch_register */
+  microblaze_get_pc,
+  microblaze_set_pc,
+  (const unsigned char *) &microblaze_breakpoint,
+  microblaze_breakpoint_len,
+  microblaze_reinsert_addr,
+  0,
+  microblaze_breakpoint_at,
+  NULL,
+  NULL,
+  NULL,
+  NULL,
+  microblaze_collect_ptrace_register,
+  microblaze_supply_ptrace_register,
+};
+
+void
+initialize_low_arch (void)
+{
+  init_registers_microblaze ();
+
+  initialize_regsets_info (&microblaze_regsets_info);
+}
+\ No newline at end of file
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 99fc497..69c333e 100644
+--- a/gdb/microblaze-linux-tdep.c
+++ b/gdb/microblaze-linux-tdep.c
+@@ -37,6 +37,22 @@
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
+ 
+static int microblaze_debug_flag = 0;
+
+static void
+microblaze_debug (const char *fmt, ...)
+{
+  if (microblaze_debug_flag)
+    {
+       va_list args;
+
+       va_start (args, fmt);
+       printf_unfiltered ("MICROBLAZE LINUX: ");
+       vprintf_unfiltered (fmt, args);
+       va_end (args);
+    }
+}
+
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, 
+                                           struct bp_target_info *bp_tgt)
+@@ -46,20 +62,27 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   int val;
+   int bplen;
+   gdb_byte old_contents[BREAKPOINT_MAX];
+  struct cleanup *cleanup;
+ 
+   /* Determine appropriate breakpoint contents and size for this address.  */
+   bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+   if (bp == NULL)
+     error (_("Software breakpoints not implemented for this target."));
+ 
+  /* Make sure we see the memory breakpoints.  */
+  cleanup = make_show_memory_breakpoints_cleanup (1);
+   val = target_read_memory (addr, old_contents, bplen);
+ 
+   /* If our breakpoint is no longer at the address, this means that the
+      program modified the code on us, so it is wrong to put back the
+      old value.  */
+   if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
+-    val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
+  {
+      val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
+      microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
+  }
+ 
+  do_cleanups (cleanup);
+   return val;
+ }
+ 
+@@ -135,6 +158,11 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+   /* Trampolines.  */
+   tramp_frame_prepend_unwinder (gdbarch,
+                                &microblaze_linux_sighandler_tramp_frame);
+
+  /* Enable TLS support.  */
+  set_gdbarch_fetch_tls_load_module_address (gdbarch,
+                                             svr4_fetch_objfile_link_map);
+
+ }
+ 
+ /* -Wmissing-prototypes */
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index dcf556f..079d34e 100644
+--- a/gdb/microblaze-tdep.c
+++ b/gdb/microblaze-tdep.c
+@@ -157,6 +157,39 @@ microblaze_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
+   return sp;
+ }
+ 
+static int
+microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+                                   struct bp_target_info *bp_tgt)
+{
+  CORE_ADDR addr = bp_tgt->placed_address;
+  const unsigned char *bp;
+  int val;
+  int bplen;
+  gdb_byte old_contents[BREAKPOINT_MAX];
+  struct cleanup *cleanup;
+
+  /* Determine appropriate breakpoint contents and size for this address.  */
+  bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+  if (bp == NULL)
+    error (_("Software breakpoints not implemented for this target."));
+
+  /* Make sure we see the memory breakpoints.  */
+  cleanup = make_show_memory_breakpoints_cleanup (1);
+  val = target_read_memory (addr, old_contents, bplen);
+
+  /* If our breakpoint is no longer at the address, this means that the
+     program modified the code on us, so it is wrong to put back the
+     old value.  */
+  if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
+  {
+    val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
+    microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
+  }
+
+  do_cleanups (cleanup);
+  return val;
+}
+
+ static const gdb_byte *
+ microblaze_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, 
+                               int *len)
+@@ -707,6 +740,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   /* Stack grows downward.  */
+   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+ 
+  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
+
+   set_gdbarch_breakpoint_from_pc (gdbarch, microblaze_breakpoint_from_pc);
+ 
+   set_gdbarch_frame_args_skip (gdbarch, 8);
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index ff4515e..9fdbda7 100644
+--- a/gdb/microblaze-tdep.h
+++ b/gdb/microblaze-tdep.h
+@@ -115,6 +115,7 @@ enum microblaze_regnum
+ 
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+    Only used for native debugging.  */
+-#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}
+#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
+#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
+ 
+ #endif /* microblaze-tdep.h */
+diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
+new file mode 100644
+index 0000000..a5dd0a0
+--- /dev/null
+++ b/gdb/regformats/reg-microblaze.dat
+@@ -0,0 +1,39 @@
+name:microblaze
+expedite:r1,pc
+32:r0
+32:r1
+32:r2
+32:r3
+32:r4
+32:r5
+32:r6
+32:r7
+32:r8
+32:r9
+32:r10
+32:r11
+32:r12
+32:r13
+32:r14
+32:r15
+32:r16
+32:r17
+32:r18
+32:r19
+32:r20
+32:r21
+32:r22
+32:r23
+32:r24
+32:r25
+32:r26
+32:r27
+32:r28
+32:r29
+32:r30
+32:r31
+32:pc
+32:msr
+32:ear
+32:esr
+32:fsr
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0002-Initial-port-of-core-reading-support.patch b/recipes-devtools/gdb/files/0002-Initial-port-of-core-reading-support.patch
new file mode 100644
index 00000000..f0020ed4
--- /dev/null
+++ b/recipes-devtools/gdb/files/0002-Initial-port-of-core-reading-support.patch
@@ -0,0 +1,378 @@
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Fri, 18 May 2012 11:49:50 +1000
+Subject: Initial port of core reading support
+Added support for reading notes in linux core dumps
+Support for reading of PRSTATUS and PSINFO information for rebuilding
+".reg" sections of core dumps at run time.
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+Upstream-Status: Pending
+---
+ bfd/elf32-microblaze.c      |   64 ++++++++++++++++++++++++++++++
+ gdb/configure.tgt           |    2 +-
+ gdb/microblaze-linux-tdep.c |   56 +++++++++++++++++++++++++++
+ gdb/microblaze-tdep.c       |   90 +++++++++++++++++++++++++++++++++++++++++++
+ gdb/microblaze-tdep.h       |   28 ++++++++++++++
+ 5 files changed, 239 insertions(+), 1 deletion(-)
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 8aafe72..365546c 100644
+--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
+@@ -668,6 +668,67 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
+   return _bfd_elf_is_local_label_name (abfd, name);
+ }
+ 
+/* Support for core dump NOTE sections.  */
+static bfd_boolean
+microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
+{
+  int offset;
+  unsigned int size;
+
+  switch (note->descsz)
+    {
+      default:
+        return FALSE;
+
+      case 228:         /* Linux/MicroBlaze */
+        /* pr_cursig */
+        elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
+
+        /* pr_pid */
+        elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
+
+        /* pr_reg */
+        offset = 72;
+        size = 50 * 4;
+
+        break;
+    }
+
+  /* Make a ".reg/999" section.  */
+  return _bfd_elfcore_make_pseudosection (abfd, ".reg",
+                                          size, note->descpos + offset);
+}
+
+static bfd_boolean
+microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
+{
+  switch (note->descsz)
+    {
+      default:
+        return FALSE;
+
+      case 128:         /* Linux/MicroBlaze elf_prpsinfo */
+        elf_tdata (abfd)->core->program
+         = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16);
+        elf_tdata (abfd)->core->command
+         = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80);
+    }
+
+  /* Note that for some reason, a spurious space is tacked
+     onto the end of the args in some (at least one anyway)
+     implementations, so strip it off if it exists.  */
+
+  {
+    char *command = elf_tdata (abfd)->core->command;
+    int n = strlen (command);
+
+    if (0 < n && command[n - 1] == ' ')
+      command[n - 1] = '\0';
+  }
+
+  return TRUE;
+}
+
+ /* The microblaze linker (like many others) needs to keep track of
+    the number of relocs that it decides to copy as dynamic relocs in
+    check_relocs for each symbol. This is so that it can later discard
+@@ -3499,4 +3560,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+ #define elf_backend_size_dynamic_sections       microblaze_elf_size_dynamic_sections
+ #define elf_backend_add_symbol_hook            microblaze_elf_add_symbol_hook
+ 
+#define elf_backend_grok_prstatus               microblaze_elf_grok_prstatus
+#define elf_backend_grok_psinfo                 microblaze_elf_grok_psinfo
+
+ #include "elf32-target.h"
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index 720d3d3..1285aac 100644
+--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
+@@ -339,7 +339,7 @@ mep-*-*)
+ 
+ microblaze*-linux-*|microblaze*-*-linux*)
+        # Target: Xilinx MicroBlaze running Linux
+-       gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o microblaze-rom.o \
+       gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o microblaze-rom.o glibc-tdep.o \
+                        monitor.o dsrec.o solib-svr4.o symfile-mem.o linux-tdep.o"
+        gdb_sim=../sim/microblaze/libsim.a
+        ;;
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 69c333e..9dc4f85 100644
+--- a/gdb/microblaze-linux-tdep.c
+++ b/gdb/microblaze-linux-tdep.c
+@@ -32,6 +32,7 @@
+ #include "regset.h"
+ #include "solib-svr4.h"
+ #include "microblaze-tdep.h"
+#include "glibc-tdep.h"
+ #include "trad-frame.h"
+ #include "frame-unwind.h"
+ #include "tramp-frame.h"
+@@ -139,6 +140,43 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame =
+   microblaze_linux_sighandler_cache_init
+ };
+ 
+const struct microblaze_gregset microblaze_linux_core_gregset;
+
+static void
+microblaze_linux_supply_core_gregset (const struct regset *regset,
+                                   struct regcache *regcache,
+                                   int regnum, const void *gregs, size_t len)
+{
+  microblaze_supply_gregset (&microblaze_linux_core_gregset, regcache,
+                             regnum, gregs);
+}
+
+static void
+microblaze_linux_collect_core_gregset (const struct regset *regset,
+                                    const struct regcache *regcache,
+                                    int regnum, void *gregs, size_t len)
+{
+  microblaze_collect_gregset (&microblaze_linux_core_gregset, regcache,
+                              regnum, gregs);
+}
+
+static void
+microblaze_linux_supply_core_fpregset (const struct regset *regset,
+                                    struct regcache *regcache,
+                                    int regnum, const void *fpregs, size_t len)
+{
+  /* FIXME.  */
+  microblaze_supply_fpregset (regcache, regnum, fpregs);
+}
+
+static void
+microblaze_linux_collect_core_fpregset (const struct regset *regset,
+                                     const struct regcache *regcache,
+                                     int regnum, void *fpregs, size_t len)
+{
+  /* FIXME.  */
+  microblaze_collect_fpregset (regcache, regnum, fpregs);
+}
+ 
+ static void
+ microblaze_linux_init_abi (struct gdbarch_info info,
+@@ -146,6 +184,10 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ {
+   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ 
+  tdep->gregset = regset_alloc (gdbarch, microblaze_linux_supply_core_gregset,
+                                microblaze_linux_collect_core_gregset);
+  tdep->sizeof_gregset = 200;
+
+   linux_init_abi (info, gdbarch);
+ 
+   set_gdbarch_memory_remove_breakpoint (gdbarch,
+@@ -159,6 +201,20 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+   tramp_frame_prepend_unwinder (gdbarch,
+                                &microblaze_linux_sighandler_tramp_frame);
+ 
+  /* BFD target for core files.  */
+  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
+  else
+    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
+
+
+  /* Shared library handling.  */
+  set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
+  set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
+
+  set_gdbarch_regset_from_core_section (gdbarch,
+                                       microblaze_regset_from_core_section);
+
+   /* Enable TLS support.  */
+   set_gdbarch_fetch_tls_load_module_address (gdbarch,
+                                              svr4_fetch_objfile_link_map);
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 079d34e..cfc227d 100644
+--- a/gdb/microblaze-tdep.c
+++ b/gdb/microblaze-tdep.c
+@@ -146,6 +146,14 @@ microblaze_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
+   return sp;
+ }
+ 
+static CORE_ADDR
+microblaze_store_arguments (struct regcache *regcache, int nargs,
+                           struct value **args, CORE_ADDR sp,
+                           int struct_return, CORE_ADDR struct_addr)
+{
+  error (_("store_arguments not implemented"));
+  return sp;
+}
+ 
+ static CORE_ADDR
+ microblaze_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
+@@ -570,6 +578,12 @@ microblaze_frame_base_address (struct frame_info *next_frame,
+   return cache->base;
+ }
+ 
+static const struct frame_unwind *
+microblaze_frame_sniffer (struct frame_info *next_frame)
+{
+  return &microblaze_frame_unwind;
+}
+
+ static const struct frame_base microblaze_frame_base =
+ {
+   &microblaze_frame_unwind,
+@@ -698,6 +712,70 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+   return dwarf2_to_reg_map[reg];
+ }
+ 
+
+void
+microblaze_supply_gregset (const struct microblaze_gregset *gregset,
+                        struct regcache *regcache,
+                        int regnum, const void *gregs)
+{
+  unsigned int *regs = gregs;
+  if (regnum >= 0)
+    regcache_raw_supply (regcache, regnum, regs + regnum);
+
+  if (regnum == -1) {
+    int i;
+
+    for (i = 0; i < 50; i++) {
+      regcache_raw_supply (regcache, i, regs + i);
+    }
+  }
+}
+
+
+void
+microblaze_collect_gregset (const struct microblaze_gregset *gregset,
+                         const struct regcache *regcache,
+                         int regnum, void *gregs)
+{
+   /* FIXME.  */
+}
+
+void
+microblaze_supply_fpregset (struct regcache *regcache,
+                         int regnum, const void *fpregs)
+{
+   /* FIXME.  */
+}
+
+void
+microblaze_collect_fpregset (const struct regcache *regcache,
+                          int regnum, void *fpregs)
+{
+   /* FIXME.  */
+}
+
+
+/* Return the appropriate register set for the core section identified
+   by SECT_NAME and SECT_SIZE.  */
+
+const struct regset *
+microblaze_regset_from_core_section (struct gdbarch *gdbarch,
+                                     const char *sect_name, size_t sect_size)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+  microblaze_debug ("microblaze_regset_from_core_section, sect_name = %s\n", sect_name);
+
+  if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
+    return tdep->gregset;
+
+  if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
+    return tdep->fpregset;
+
+  microblaze_debug ("microblaze_regset_from_core_section returning null :-( \n");
+  return NULL;
+}
+
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+@@ -713,6 +791,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   tdep = XMALLOC (struct gdbarch_tdep);
+   gdbarch = gdbarch_alloc (&info, tdep);
+ 
+  tdep->gregset = NULL;
+  tdep->sizeof_gregset = 0;
+  tdep->fpregset = NULL;
+  tdep->sizeof_fpregset = 0;
+
+   set_gdbarch_long_double_bit (gdbarch, 128);
+ 
+   set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
+@@ -761,6 +844,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   dwarf2_append_unwinders (gdbarch);
+   frame_unwind_append_unwinder (gdbarch, &microblaze_frame_unwind);
+   frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
+  //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
+
+  /* If we have register sets, enable the generic core file support.  */
+  if (tdep->gregset) {
+      set_gdbarch_regset_from_core_section (gdbarch,
+                                          microblaze_regset_from_core_section);
+  }
+ 
+   return gdbarch;
+ }
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 9fdbda7..7de4463 100644
+--- a/gdb/microblaze-tdep.h
+++ b/gdb/microblaze-tdep.h
+@@ -22,8 +22,22 @@
+ 
+ 
+ /* Microblaze architecture-specific information.  */
+struct microblaze_gregset
+{
+   unsigned int gregs[32];
+   unsigned int fpregs[32];
+   unsigned int pregs[16];
+};
+
+ struct gdbarch_tdep
+ {
+  int dummy;           // declare something.
+
+  /* Register sets.  */
+  struct regset *gregset;
+  size_t sizeof_gregset;
+  struct regset *fpregset;
+  size_t sizeof_fpregset;
+ };
+ 
+ struct microblaze_frame_cache
+@@ -118,4 +132,18 @@ enum microblaze_regnum
+ #define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
+ #define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
+ 
+extern void microblaze_supply_gregset (const struct microblaze_gregset *gregset,
+                                    struct regcache *regcache,
+                                    int regnum, const void *gregs);
+extern void microblaze_collect_gregset (const struct microblaze_gregset *gregset,
+                                     const struct regcache *regcache,
+                                     int regnum, void *gregs);
+extern void microblaze_supply_fpregset (struct regcache *regcache,
+                                     int regnum, const void *fpregs);
+extern void microblaze_collect_fpregset (const struct regcache *regcache,
+                                      int regnum, void *fpregs);
+
+extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch,
+                                     const char *sect_name, size_t sect_size);
+
+ #endif /* microblaze-tdep.h */
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0003-Initial-support-for-native-gdb.patch b/recipes-devtools/gdb/files/0003-Initial-support-for-native-gdb.patch
new file mode 100644
index 00000000..8281352e
--- /dev/null
+++ b/recipes-devtools/gdb/files/0003-Initial-support-for-native-gdb.patch
@@ -0,0 +1,494 @@
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Fri, 20 Jul 2012 15:18:35 +1000
+Subject: Initial support for native gdb
+microblaze: Follow PPC method of getting setting registers
+using PTRACE PEEK/POKE
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Upstream-Status: Pending
+---
+ gdb/Makefile.in                |    4 +-
+ gdb/config/microblaze/linux.mh |    9 +
+ gdb/microblaze-linux-nat.c     |  431 ++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 442 insertions(+), 2 deletions(-)
+ create mode 100644 gdb/config/microblaze/linux.mh
+ create mode 100644 gdb/microblaze-linux-nat.c
+diff --git a/gdb/Makefile.in b/gdb/Makefile.in
+index 3fd5425..e5781f2 100644
+--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
+@@ -821,7 +821,7 @@ config/rs6000/nm-rs6000.h top.h bsd-kvm.h gdb-stabs.h reggroups.h \
+ annotate.h sim-regno.h dictionary.h dfp.h main.h frame-unwind.h        \
+ remote-fileio.h i386-linux-tdep.h vax-tdep.h objc-lang.h \
+ sentinel-frame.h bcache.h symfile.h windows-tdep.h linux-tdep.h \
+-gdb_usleep.h jit.h xml-syscall.h microblaze-tdep.h \
+gdb_usleep.h jit.h xml-syscall.h microblaze-tdep.h microblaze-linux-tdep.h \
+ psymtab.h psympriv.h progspace.h bfin-tdep.h ia64-hpux-tdep.h \
+ amd64-darwin-tdep.h charset-list.h \
+ config/djgpp/langinfo.h config/djgpp/nl_types.h darwin-nat.h \
+@@ -1481,7 +1481,7 @@ ALLDEPFILES = \
+        m68kbsd-nat.c m68kbsd-tdep.c \
+        m68klinux-nat.c m68klinux-tdep.c \
+        m88k-tdep.c m88kbsd-nat.c \
+-       microblaze-tdep.c microblaze-linux-tdep.c \
+       microblaze-tdep.c microblaze-linux-nat.c microblaze-linux-tdep.c \
+        mingw-hdep.c \
+        mips-linux-nat.c mips-linux-tdep.c \
+        mips-irix-tdep.c \
+diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
+new file mode 100644
+index 0000000..a4eaf54
+--- /dev/null
+++ b/gdb/config/microblaze/linux.mh
+@@ -0,0 +1,9 @@
+# Host: Microblaze, running Linux
+
+NAT_FILE= config/nm-linux.h
+NATDEPFILES= inf-ptrace.o fork-child.o \
+       microblaze-linux-nat.o proc-service.o linux-thread-db.o \
+       linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
+NAT_CDEPS = $(srcdir)/proc-service.list
+
+LOADLIBES = -ldl $(RDYNAMIC)
+diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
+new file mode 100644
+index 0000000..e9b8c9c
+--- /dev/null
+++ b/gdb/microblaze-linux-nat.c
+@@ -0,0 +1,431 @@
+/* Microblaze GNU/Linux native support.
+
+   Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free
+   Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#include "defs.h"
+#include "arch-utils.h"
+#include "dis-asm.h"
+#include "frame.h"
+#include "trad-frame.h"
+#include "symtab.h"
+#include "value.h"
+#include "gdbcmd.h"
+#include "breakpoint.h"
+#include "inferior.h"
+#include "regcache.h"
+#include "target.h"
+#include "frame.h"
+#include "frame-base.h"
+#include "frame-unwind.h"
+#include "dwarf2-frame.h"
+#include "osabi.h"
+
+#include "gdb_assert.h"
+#include "gdb_string.h"
+#include "target-descriptions.h"
+#include "opcodes/microblaze-opcm.h"
+#include "opcodes/microblaze-dis.h"
+
+#include "linux-nat.h"
+#include "target-descriptions.h"
+
+#include <sys/user.h>
+#include <sys/utsname.h>
+#include <sys/procfs.h>
+#include <sys/ptrace.h>
+
+/* Prototypes for supply_gregset etc. */
+#include "gregset.h"
+
+#include "microblaze-tdep.h"
+
+#include <elf/common.h>
+#include "auxv.h"
+
+/* Defines ps_err_e, struct ps_prochandle.  */
+#include "gdb_proc_service.h"
+
+/* On GNU/Linux, threads are implemented as pseudo-processes, in which
+   case we may be tracing more than one process at a time.  In that
+   case, inferior_ptid will contain the main process ID and the
+   individual thread (process) ID.  get_thread_id () is used to get
+   the thread id if it's available, and the process id otherwise.  */
+
+int
+get_thread_id (ptid_t ptid)
+{
+  int tid = TIDGET (ptid);
+  if (0 == tid)
+    tid = PIDGET (ptid);
+  return tid;
+}
+
+#define GET_THREAD_ID(PTID)    get_thread_id (PTID)
+
+/* Non-zero if our kernel may support the PTRACE_GETREGS and
+   PTRACE_SETREGS requests, for reading and writing the
+   general-purpose registers.  Zero if we've tried one of
+   them and gotten an error.  */
+int have_ptrace_getsetregs = 1;
+
+static int
+microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
+{
+  int u_addr = -1;
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
+     interface, and not the wordsize of the program's ABI.  */
+  int wordsize = sizeof (long);
+
+  /* General purpose registers occupy 1 slot each in the buffer.  */
+  if (regno >= MICROBLAZE_R0_REGNUM
+      && regno <= MICROBLAZE_FSR_REGNUM)
+    u_addr = (regno * wordsize);
+
+  return u_addr;
+}
+
+
+static void
+fetch_register (struct regcache *regcache, int tid, int regno)
+{
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  /* This isn't really an address.  But ptrace thinks of it as one.  */
+  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
+  int bytes_transferred;
+  unsigned int offset;         /* Offset of registers within the u area.  */
+  char buf[MAX_REGISTER_SIZE];
+
+  if (regaddr == -1)
+  {
+    memset (buf, '\0', register_size (gdbarch, regno));   /* Supply zeroes */
+    regcache_raw_supply (regcache, regno, buf);
+    return;
+  }
+
+  /* Read the raw register using sizeof(long) sized chunks.  On a
+     32-bit platform, 64-bit floating-point registers will require two
+     transfers.  */
+  for (bytes_transferred = 0;
+       bytes_transferred < register_size (gdbarch, regno);
+       bytes_transferred += sizeof (long))
+  {
+    long l;
+
+    errno = 0;
+    l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
+    regaddr += sizeof (long);
+    if (errno != 0)
+    {
+      char message[128];
+      sprintf (message, "reading register %s (#%d)",
+               gdbarch_register_name (gdbarch, regno), regno);
+      perror_with_name (message);
+    }
+    memcpy (&buf[bytes_transferred], &l, sizeof (l));
+  }
+
+  /* Now supply the register.  Keep in mind that the regcache's idea
+     of the register's size may not be a multiple of sizeof
+     (long).  */
+  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
+  {
+    /* Little-endian values are always found at the left end of the
+       bytes transferred.  */
+    regcache_raw_supply (regcache, regno, buf);
+  }
+  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+  {
+    /* Big-endian values are found at the right end of the bytes
+       transferred.  */
+    size_t padding = (bytes_transferred - register_size (gdbarch, regno));
+    regcache_raw_supply (regcache, regno, buf + padding);
+  }
+  else
+    internal_error (__FILE__, __LINE__,
+                    _("fetch_register: unexpected byte order: %d"),
+                    gdbarch_byte_order (gdbarch));
+}
+
+/* This function actually issues the request to ptrace, telling
+   it to get all general-purpose registers and put them into the
+   specified regset.
+
+   If the ptrace request does not exist, this function returns 0
+   and properly sets the have_ptrace_* flag.  If the request fails,
+   this function calls perror_with_name.  Otherwise, if the request
+   succeeds, then the regcache gets filled and 1 is returned.  */
+static int
+fetch_all_gp_regs (struct regcache *regcache, int tid)
+{
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  gdb_gregset_t gregset;
+
+  if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
+  {
+    if (errno == EIO)
+    {
+      have_ptrace_getsetregs = 0;
+      return 0;
+    }
+    perror_with_name (_("Couldn't get general-purpose registers."));
+  }
+
+  supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
+
+  return 1;
+}
+
+
+/* This is a wrapper for the fetch_all_gp_regs function.  It is
+   responsible for verifying if this target has the ptrace request
+   that can be used to fetch all general-purpose registers at one
+   shot.  If it doesn't, then we should fetch them using the
+   old-fashioned way, which is to iterate over the registers and
+   request them one by one.  */
+static void
+fetch_gp_regs (struct regcache *regcache, int tid)
+{
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  int i;
+
+  if (have_ptrace_getsetregs)
+    if (fetch_all_gp_regs (regcache, tid))
+      return;
+
+  /* If we've hit this point, it doesn't really matter which
+     architecture we are using.  We just need to read the
+     registers in the "old-fashioned way".  */
+  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
+    fetch_register (regcache, tid, i);
+}
+
+
+static void
+store_register (const struct regcache *regcache, int tid, int regno)
+{
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  /* This isn't really an address.  But ptrace thinks of it as one.  */
+  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
+  int i;
+  size_t bytes_to_transfer;
+  char buf[MAX_REGISTER_SIZE];
+
+  if (regaddr == -1)
+    return;
+
+  /* First collect the register.  Keep in mind that the regcache's
+     idea of the register's size may not be a multiple of sizeof
+     (long).  */
+  memset (buf, 0, sizeof buf);
+  bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
+  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
+  {
+    /* Little-endian values always sit at the left end of the buffer.  */
+    regcache_raw_collect (regcache, regno, buf);
+  }
+  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+  {
+    /* Big-endian values sit at the right end of the buffer.  */
+    size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
+    regcache_raw_collect (regcache, regno, buf + padding);
+  }
+
+  for (i = 0; i < bytes_to_transfer; i += sizeof (long))
+  {
+    long l;
+
+    memcpy (&l, &buf[i], sizeof (l));
+    errno = 0;
+    ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
+    regaddr += sizeof (long);
+
+    if (errno != 0)
+    {
+      char message[128];
+      sprintf (message, "writing register %s (#%d)",
+               gdbarch_register_name (gdbarch, regno), regno);
+      perror_with_name (message);
+    }
+  }
+}
+
+/* This function actually issues the request to ptrace, telling
+   it to store all general-purpose registers present in the specified
+   regset.
+
+   If the ptrace request does not exist, this function returns 0
+   and properly sets the have_ptrace_* flag.  If the request fails,
+   this function calls perror_with_name.  Otherwise, if the request
+   succeeds, then the regcache is stored and 1 is returned.  */
+static int
+store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
+{
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  gdb_gregset_t gregset;
+
+  if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
+    {
+      if (errno == EIO)
+      {
+        have_ptrace_getsetregs = 0;
+        return 0;
+      }
+      perror_with_name (_("Couldn't get general-purpose registers."));
+    }
+
+  fill_gregset (regcache, &gregset, regno);
+
+  if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
+    {
+      if (errno == EIO)
+      {
+        have_ptrace_getsetregs = 0;
+        return 0;
+      }
+      perror_with_name (_("Couldn't set general-purpose registers."));
+    }
+
+  return 1;
+}
+
+/* This is a wrapper for the store_all_gp_regs function.  It is
+   responsible for verifying if this target has the ptrace request
+   that can be used to store all general-purpose registers at one
+   shot.  If it doesn't, then we should store them using the
+   old-fashioned way, which is to iterate over the registers and
+   store them one by one.  */
+static void
+store_gp_regs (const struct regcache *regcache, int tid, int regno)
+{
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  int i;
+
+  if (have_ptrace_getsetregs)
+    if (store_all_gp_regs (regcache, tid, regno))
+      return;
+
+  /* If we hit this point, it doesn't really matter which
+     architecture we are using.  We just need to store the
+     registers in the "old-fashioned way".  */
+  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
+    store_register (regcache, tid, i);
+}
+
+
+/* Fetch registers from the child process.  Fetch all registers if
+   regno == -1, otherwise fetch all general registers or all floating
+   point registers depending upon the value of regno.  */
+
+static void
+microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
+                                   struct regcache *regcache, int regno)
+{
+  /* Get the thread id for the ptrace call.  */
+  int tid = GET_THREAD_ID (inferior_ptid);
+
+  if (regno == -1)
+    fetch_gp_regs (regcache, tid);
+  else
+    fetch_register (regcache, tid, regno);
+}
+
+/* Store registers back into the inferior.  Store all registers if
+   regno == -1, otherwise store all general registers or all floating
+   point registers depending upon the value of regno.  */
+
+static void
+microblaze_linux_store_inferior_registers (struct target_ops *ops,
+                                   struct regcache *regcache, int regno)
+{
+  /* Get the thread id for the ptrace call.  */
+  int tid = GET_THREAD_ID (inferior_ptid);
+
+  if (regno >= 0)
+    store_register (regcache, tid, regno);
+  else
+    store_gp_regs (regcache, tid, -1);
+}
+
+/* Wrapper functions for the standard regset handling, used by
+   thread debugging.  */
+
+void
+fill_gregset (const struct regcache *regcache,
+             gdb_gregset_t *gregsetp, int regno)
+{
+  microblaze_collect_gregset (NULL, regcache, regno, gregsetp);
+}
+
+void
+supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
+{
+  microblaze_supply_gregset (NULL, regcache, -1, gregsetp);
+}
+
+void
+fill_fpregset (const struct regcache *regcache,
+             gdb_fpregset_t *fpregsetp, int regno)
+{
+  /* FIXME. */
+}
+
+void
+supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
+{
+  /* FIXME. */
+}
+
+static const struct target_desc *
+microblaze_linux_read_description (struct target_ops *ops)
+{
+  CORE_ADDR microblaze_hwcap = 0;
+
+  if (target_auxv_search (ops, AT_HWCAP, &microblaze_hwcap) != 1)
+    return NULL;
+
+  return NULL;
+}
+
+
+void _initialize_microblaze_linux_nat (void);
+
+void
+_initialize_microblaze_linux_nat (void)
+{
+  struct target_ops *t;
+
+  /* Fill in the generic GNU/Linux methods.  */
+  t = linux_target ();
+
+  /* Add our register access methods.  */
+  t->to_fetch_registers = microblaze_linux_fetch_inferior_registers;
+  t->to_store_registers = microblaze_linux_store_inferior_registers;
+
+  t->to_read_description = microblaze_linux_read_description;
+
+  /* Register the target.  */
+  linux_nat_add_target (t);
+}
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0004-Robustify-inline-function-support.patch b/recipes-devtools/gdb/files/0004-Robustify-inline-function-support.patch
new file mode 100644
index 00000000..24759d73
--- /dev/null
+++ b/recipes-devtools/gdb/files/0004-Robustify-inline-function-support.patch
@@ -0,0 +1,42 @@
+From: "Edgar E. Iglesias" <edgar@axis.com>
+Date: Mon, 27 Feb 2012 06:28:00 +0100
+Subject: Robustify inline function support
+Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
+Upstream-Status: Pending
+---
+ gdb/blockframe.c   |    3 ++-
+ gdb/inline-frame.c |    3 +++
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+diff --git a/gdb/blockframe.c b/gdb/blockframe.c
+index d5787f1..80e40a3 100644
+--- a/gdb/blockframe.c
+++ b/gdb/blockframe.c
+@@ -78,7 +78,8 @@ get_frame_block (struct frame_info *frame, CORE_ADDR *addr_in_block)
+        inline_count--;
+ 
+       bl = BLOCK_SUPERBLOCK (bl);
+-      gdb_assert (bl != NULL);
+      if (!bl)
+        return NULL;
+     }
+ 
+   return bl;
+diff --git a/gdb/inline-frame.c b/gdb/inline-frame.c
+index 2773814..c3a77ad 100644
+--- a/gdb/inline-frame.c
+++ b/gdb/inline-frame.c
+@@ -230,6 +230,9 @@ inline_frame_sniffer (const struct frame_unwind *self,
+       cur_block = BLOCK_SUPERBLOCK (cur_block);
+     }
+ 
+  if (depth == 0)
+    return 0;
+
+   /* Check how many inlined functions already have frames.  */
+   for (next_frame = get_next_frame (this_frame);
+        next_frame && get_frame_type (next_frame) == INLINE_FRAME;
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0005-Fix-debug-message-when-register-is-unavailable.patch b/recipes-devtools/gdb/files/0005-Fix-debug-message-when-register-is-unavailable.patch
new file mode 100644
index 00000000..67520f4c
--- /dev/null
+++ b/recipes-devtools/gdb/files/0005-Fix-debug-message-when-register-is-unavailable.patch
@@ -0,0 +1,40 @@
+From: Nathan Rossi <nathan.rossi@petalogix.com>
+Date: Tue, 8 May 2012 18:11:17 +1000
+Subject: Fix debug message when register is unavailable
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+Upstream-Status: Pending
+---
+ gdb/frame.c |   13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+diff --git a/gdb/frame.c b/gdb/frame.c
+index 4b8ab60..7ad7cb3 100644
+--- a/gdb/frame.c
+++ b/gdb/frame.c
+@@ -979,12 +979,19 @@ frame_unwind_register_value (struct frame_info *frame, int regnum)
+          else
+            {
+              int i;
+-             const gdb_byte *buf = value_contents (value);
+             const gdb_byte *buf = NULL;
+             if (value_entirely_available(value)) {
+               buf = value_contents (value);
+             }
+ 
+              fprintf_unfiltered (gdb_stdlog, " bytes=");
+              fprintf_unfiltered (gdb_stdlog, "[");
+-             for (i = 0; i < register_size (gdbarch, regnum); i++)
+-               fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
+             if (buf != NULL) {
+               for (i = 0; i < register_size (gdbarch, regnum); i++)
+                 fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
+             } else {
+               fprintf_unfiltered (gdb_stdlog, "unavailable");
+             }
+              fprintf_unfiltered (gdb_stdlog, "]");
+            }
+        }
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0006-Add-slr-and-shr-regs-and-little-endian-breakpoint.patch b/recipes-devtools/gdb/files/0006-Add-slr-and-shr-regs-and-little-endian-breakpoint.patch
new file mode 100644
index 00000000..53020f9d
--- /dev/null
+++ b/recipes-devtools/gdb/files/0006-Add-slr-and-shr-regs-and-little-endian-breakpoint.patch
@@ -0,0 +1,80 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 26 Nov 2012 17:39:17 +1000
+Subject: Add slr and shr regs and little-endian breakpoint
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ gdb/microblaze-tdep.c             |   10 ++++++++--
+ gdb/microblaze-tdep.h             |    6 ++++--
+ gdb/regformats/reg-microblaze.dat |    2 ++
+ 3 files changed, 14 insertions(+), 4 deletions(-)
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index cfc227d..a245169 100644
+--- a/gdb/microblaze-tdep.c
+++ b/gdb/microblaze-tdep.c
+@@ -74,7 +74,8 @@ static const char *microblaze_register_names[] =
+   "rpc",  "rmsr", "rear", "resr", "rfsr", "rbtr",
+   "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
+   "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
+-  "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi"
+  "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
+  "rslr", "rshr"
+ };
+ 
+ #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
+@@ -202,10 +203,15 @@ static const gdb_byte *
+ microblaze_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, 
+                               int *len)
+ {
+  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+   static gdb_byte break_insn[] = MICROBLAZE_BREAKPOINT;
+  static gdb_byte break_insn_le[] = MICROBLAZE_BREAKPOINT_LE;
+ 
+   *len = sizeof (break_insn);
+-  return break_insn;
+  if (byte_order == BFD_ENDIAN_BIG)
+    return break_insn;
+  else
+    return break_insn_le;
+ }
+ 
+ /* Allocate and initialize a frame cache.  */
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 7de4463..23dc77a 100644
+--- a/gdb/microblaze-tdep.h
+++ b/gdb/microblaze-tdep.h
+@@ -56,7 +56,7 @@ struct microblaze_frame_cache
+   int fp_regnum;
+ 
+   /* Offsets to saved registers.  */
+-  int register_offsets[57];    /* Must match MICROBLAZE_NUM_REGS.  */
+  int register_offsets[59];    /* Must match MICROBLAZE_NUM_REGS.  */
+ 
+   /* Table of saved registers.  */
+   struct trad_frame_saved_reg *saved_regs;
+@@ -121,7 +121,9 @@ enum microblaze_regnum
+   MICROBLAZE_RTLBX_REGNUM,
+   MICROBLAZE_RTLBSX_REGNUM,
+   MICROBLAZE_RTLBLO_REGNUM,
+-  MICROBLAZE_RTLBHI_REGNUM
+  MICROBLAZE_RTLBHI_REGNUM,
+  MICROBLAZE_SLR_REGNUM,
+  MICROBLAZE_SHR_REGNUM
+ };
+ 
+ /* All registers are 32 bits.  */
+diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
+index a5dd0a0..bd8a438 100644
+--- a/gdb/regformats/reg-microblaze.dat
+++ b/gdb/regformats/reg-microblaze.dat
+@@ -37,3 +37,5 @@ expedite:r1,pc
+ 32:ear
+ 32:esr
+ 32:fsr
+32:slr
+32:shr
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0007-Fix-relaxation-of-assembler-resolved-references.patch b/recipes-devtools/gdb/files/0007-Fix-relaxation-of-assembler-resolved-references.patch
new file mode 100644
index 00000000..3aaaf0ab
--- /dev/null
+++ b/recipes-devtools/gdb/files/0007-Fix-relaxation-of-assembler-resolved-references.patch
@@ -0,0 +1,62 @@
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Tue, 14 Feb 2012 01:00:22 +0100
+Subject: Fix relaxation of assembler resolved references
+Upstream-Status: Pending
+---
+ bfd/elf32-microblaze.c |   39 +++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 365546c..61926a4 100644
+--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
+@@ -1967,6 +1967,45 @@ microblaze_elf_relax_section (bfd *abfd,
+           irelscanend = irelocs + o->reloc_count;
+           for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+             {
+              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
+                {
+                  unsigned int val;
+
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+
+                  /* This was a PC-relative instruction that was completely resolved.  */
+                  if (ocontents == NULL)
+                    {
+                     if (elf_section_data (o)->this_hdr.contents != NULL)
+                         ocontents = elf_section_data (o)->this_hdr.contents;
+                     else
+                       {
+                         /* We always cache the section contents.
+                            Perhaps, if info->keep_memory is FALSE, we
+                            should free them, if we are permitted to.  */
+
+                         if (o->rawsize == 0)
+                             o->rawsize = o->size;
+                         ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
+                         if (ocontents == NULL)
+                             goto error_return;
+                         if (!bfd_get_section_contents (abfd, o, ocontents,
+                                                         (file_ptr) 0,
+                                                         o->rawsize))
+                              goto error_return;
+                         elf_section_data (o)->this_hdr.contents = ocontents;
+                       }
+                   }
+
+                  irelscan->r_addend -= calc_fixup (irelscan->r_addend
+                                                    + isym->st_value, sec);
+                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
+                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+                                                     irelscan->r_addend);
+              }
+              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
+                  fprintf(stderr, "Unhandled NONE 64\n");
+              }
+               if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+                 {
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0008-Fixup-debug_loc-sections-after-linker-relaxation.patch b/recipes-devtools/gdb/files/0008-Fixup-debug_loc-sections-after-linker-relaxation.patch
new file mode 100644
index 00000000..95fc629b
--- /dev/null
+++ b/recipes-devtools/gdb/files/0008-Fixup-debug_loc-sections-after-linker-relaxation.patch
@@ -0,0 +1,195 @@
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Wed, 15 Feb 2012 13:53:02 +0100
+Subject: Fixup debug_loc sections after linker relaxation
+Adds a new reloctype R_MICROBLAZE_32_NONE, used for passing
+reloc info from the assembler to the linker when the linker
+manages to fully resolve a local symbol reference.
+This is a workaround for design flaws in the assembler to
+linker interface with regards to linker relaxation.
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Upstream-Status: Pending
+---
+ bfd/bfd-in2.h            |    5 +++++
+ bfd/elf32-microblaze.c   |   45 +++++++++++++++++++++++++++++++++++++--------
+ bfd/libbfd.h             |    1 +
+ bfd/reloc.c              |    6 ++++++
+ include/elf/microblaze.h |    1 +
+ 5 files changed, 50 insertions(+), 8 deletions(-)
+ mode change 100644 => 100755 bfd/elf32-microblaze.c
+ mode change 100644 => 100755 include/elf/microblaze.h
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 524e97e..17a5769 100644
+--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
+@@ -5125,6 +5125,11 @@ value relative to the read-write small data area anchor  */
+ expressions of the form "Symbol Op Symbol"  */
+   BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+ 
+/* This is a 32 bit reloc that stores the 32 bit pc relative
+value in two words (with an imm instruction).  No relocation is 
+done here - only used for relaxing  */
+  BFD_RELOC_MICROBLAZE_32_NONE,
+
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  No relocation is
+ done here - only used for relaxing  */
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+old mode 100644
+new mode 100755
+index 61926a4..c44c76f
+--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
+@@ -177,6 +177,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+           FALSE),              /* PC relative offset?  */
+ 
+    /* This reloc does nothing.  Used for relaxation.  */
+   HOWTO (R_MICROBLAZE_32_NONE,        /* Type.  */
+          0,                   /* Rightshift.  */
+          2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
+          32,                  /* Bitsize.  */
+          TRUE,                        /* PC_relative.  */
+          0,                   /* Bitpos.  */
+          complain_overflow_bitfield,  /* Complain on overflow.  */
+          NULL,                  /* Special Function.  */
+          "R_MICROBLAZE_32_NONE",/* Name.  */
+          FALSE,               /* Partial Inplace.  */
+          0,                   /* Source Mask.  */
+          0,                   /* Dest Mask.  */
+          FALSE),              /* PC relative offset?  */
+
+    HOWTO (R_MICROBLAZE_64_NONE,        /* Type.  */
+           0,                   /* Rightshift.  */
+           2,                   /* Size (0 = byte, 1 = short, 2 = long).  */
+@@ -532,7 +546,10 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+     case BFD_RELOC_NONE:
+       microblaze_reloc = R_MICROBLAZE_NONE;
+       break;
+-    case BFD_RELOC_MICROBLAZE_64_NONE:
+    case BFD_RELOC_MICROBLAZE_32_NONE:
+      microblaze_reloc = R_MICROBLAZE_32_NONE;
+      break;
+     case BFD_RELOC_MICROBLAZE_64_NONE:
+       microblaze_reloc = R_MICROBLAZE_64_NONE;
+       break;
+     case BFD_RELOC_32:
+@@ -1912,14 +1929,22 @@ microblaze_elf_relax_section (bfd *abfd,
+                }
+              break;
+            case R_MICROBLAZE_NONE:
+           case R_MICROBLAZE_32_NONE:
+              {
+                /* This was a PC-relative instruction that was
+                   completely resolved.  */
+                int sfix, efix;
+               unsigned int val;
+                bfd_vma target_address;
+                target_address = irel->r_addend + irel->r_offset;
+                sfix = calc_fixup (irel->r_offset, 0, sec);
+                efix = calc_fixup (target_address, 0, sec);
+
+                /* Validate the in-band val.  */
+                val = bfd_get_32 (abfd, contents + irel->r_offset);
+                if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
+                    fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
+                }
+                irel->r_addend -= (efix - sfix);
+                /* Should use HOWTO.  */
+                microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
+@@ -1967,12 +1992,16 @@ microblaze_elf_relax_section (bfd *abfd,
+           irelscanend = irelocs + o->reloc_count;
+           for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+             {
+-              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
+              if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
+                 {
+                   unsigned int val;
+ 
+                   isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+                  /* hax: We only do the following fixup for debug location lists.  */
+                  if (strcmp(".debug_loc", o->name))
+                    continue;
+
+                   /* This was a PC-relative instruction that was completely resolved.  */
+                   if (ocontents == NULL)
+                     {
+@@ -1997,15 +2026,15 @@ microblaze_elf_relax_section (bfd *abfd,
+                        }
+                    }
+ 
+-                  irelscan->r_addend -= calc_fixup (irelscan->r_addend
+-                                                    + isym->st_value, sec);
+                   val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
+                  if (val != irelscan->r_addend) {
+                       fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
+                  }
+
+                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
+                   microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+                                                      irelscan->r_addend);
+               }
+-              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
+-                  fprintf(stderr, "Unhandled NONE 64\n");
+-              }
+               if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+                 {
+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+@@ -2065,7 +2094,7 @@ microblaze_elf_relax_section (bfd *abfd,
+                              elf_section_data (o)->this_hdr.contents = ocontents;
+                            }
+                        }
+-                     irelscan->r_addend -= calc_fixup (irel->r_addend
+                     irelscan->r_addend -= calc_fixup (irelscan->r_addend
+                                                        + isym->st_value,
+                                                        0,
+                                                        sec);
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index 857d1ea..5c627fe 100644
+--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
+@@ -2492,6 +2492,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_32_ROSDA",
+   "BFD_RELOC_MICROBLAZE_32_RWSDA",
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+  "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index b59ca00..c9c547e 100644
+--- a/bfd/reloc.c
+++ b/bfd/reloc.c
+@@ -6001,6 +6001,12 @@ ENUMDOC
+   This is a 32 bit reloc for the microblaze to handle
+   expressions of the form "Symbol Op Symbol"
+ ENUM
+  BFD_RELOC_MICROBLAZE_32_NONE
+ENUMDOC
+  This is a 32 bit reloc that stores the 32 bit pc relative
+  value in two words (with an imm instruction).  No relocation is
+  done here - only used for relaxing
+ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+old mode 100644
+new mode 100755
+index c4d9821..72771e8
+--- a/include/elf/microblaze.h
+++ b/include/elf/microblaze.h
+@@ -58,6 +58,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+   RELOC_NUMBER (R_MICROBLAZE_TLSDTPREL64, 27)   /* TLS Offset Within TLS Block */
+   RELOC_NUMBER (R_MICROBLAZE_TLSGOTTPREL32, 28) /* TLS Offset From Thread Pointer */
+   RELOC_NUMBER (R_MICROBLAZE_TLSTPREL32, 29)    /* TLS Offset From Thread Pointer */
+  RELOC_NUMBER (R_MICROBLAZE_32_NONE, 30)
+    
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+ 
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0009-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/recipes-devtools/gdb/files/0009-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
new file mode 100644
index 00000000..cb58f603
--- /dev/null
+++ b/recipes-devtools/gdb/files/0009-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
@@ -0,0 +1,67 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 8 May 2013 11:03:36 +1000
+Subject: Add wdc.ext.clear and wdc.ext.flush insns
+Added two new instructions, wdc.ext.clear and wdc.ext.flush,
+to enable MicroBlaze to flush an external cache, which is
+used with the new coherency support for multiprocessing.
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ opcodes/microblaze-opc.h  |    5 ++++-
+ opcodes/microblaze-opcm.h |    6 +++---
+ 2 files changed, 7 insertions(+), 4 deletions(-)
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index e9da12a..dd56ab5 100644
+--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
+@@ -91,6 +91,7 @@
+ #define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */  
+ #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
+#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
+ 
+ /* New Mask for msrset, msrclr insns.  */
+@@ -101,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 289
+#define MAX_OPCODES 291
+ 
+ struct op_code_struct
+ {
+@@ -174,7 +175,9 @@ struct op_code_struct
+   {"wic",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+   {"wdc",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+   {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
+  {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+  {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 124cdec..8e531f9 100644
+--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
+@@ -31,9 +31,9 @@ enum microblaze_instr
+   idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+   ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, 
+-  wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+-  brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+-  bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar,
+  br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned,
+  blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+   bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh, 
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0010-revert-master-rebase-changes-to-gdbserver.patch b/recipes-devtools/gdb/files/0010-revert-master-rebase-changes-to-gdbserver.patch
new file mode 100644
index 00000000..edd6a5a7
--- /dev/null
+++ b/recipes-devtools/gdb/files/0010-revert-master-rebase-changes-to-gdbserver.patch
@@ -0,0 +1,160 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 22 Jul 2013 11:16:05 +1000
+Subject: revert master-rebase changes to gdbserver
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ gdb/gdbserver/Makefile.in            |    4 +++
+ gdb/gdbserver/configure.srv          |    7 +++++
+ gdb/gdbserver/linux-microblaze-low.c |   53 +++++-----------------------------
+ 3 files changed, 18 insertions(+), 46 deletions(-)
+diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
+index 08db2cc..aa76959 100644
+--- a/gdb/gdbserver/Makefile.in
+++ b/gdb/gdbserver/Makefile.in
+@@ -143,6 +143,7 @@ SFILES=     $(srcdir)/gdbreplay.c $(srcdir)/inferiors.c $(srcdir)/dll.c \
+        $(srcdir)/linux-ia64-low.c $(srcdir)/linux-low.c \
+        $(srcdir)/linux-m32r-low.c \
+        $(srcdir)/linux-m68k-low.c $(srcdir)/linux-mips-low.c \
+       $(srcdir)/linux-microblaze-low.c \
+        $(srcdir)/linux-ppc-low.c \
+        $(srcdir)/linux-s390-low.c \
+        $(srcdir)/linux-sh-low.c $(srcdir)/linux-sparc-low.c \
+@@ -336,6 +337,7 @@ clean:
+        rm -f i386-avx.c i386-avx-linux.c
+        rm -f amd64-avx.c amd64-avx-linux.c
+        rm -f i386-mmx.c i386-mmx-linux.c
+       rm -f microblaze-linux.c
+        rm -f x32.c x32-linux.c
+        rm -f x32-avx.c x32-avx-linux.c
+        @$(MAKE) $(FLAGS_TO_PASS) DO=$@ "DODIRS=$(SUBDIRS)" subdir_do
+@@ -616,6 +618,8 @@ mips64-linux.c : $(srcdir)/../regformats/mips64-linux.dat $(regdat_sh)
+        $(SHELL) $(regdat_sh) $(srcdir)/../regformats/mips64-linux.dat mips64-linux.c
+ mips64-dsp-linux.c : $(srcdir)/../regformats/mips64-dsp-linux.dat $(regdat_sh)
+        $(SHELL) $(regdat_sh) $(srcdir)/../regformats/mips64-dsp-linux.dat mips64-dsp-linux.c
+microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh)
+       $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c
+ powerpc-32.c : $(srcdir)/../regformats/rs6000/powerpc-32.dat $(regdat_sh)
+        $(SHELL) $(regdat_sh) $(srcdir)/../regformats/rs6000/powerpc-32.dat powerpc-32.c
+ powerpc-32l.c : $(srcdir)/../regformats/rs6000/powerpc-32l.dat $(regdat_sh)
+diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
+index 271a0fe..57bd3a4c 100644
+--- a/gdb/gdbserver/configure.srv
+++ b/gdb/gdbserver/configure.srv
+@@ -201,6 +201,13 @@ case "${target}" in
+                        srv_linux_usrregs=yes
+                        srv_linux_thread_db=yes
+                        ;;
+  microblaze*-*-linux*)        srv_regobj=microblaze-linux.o
+                       srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
+                       srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
+                       srv_linux_regsets=yes
+                       srv_linux_usrregs=yes
+                       srv_linux_thread_db=yes
+                       ;;
+   powerpc*-*-linux*)   srv_regobj="powerpc-32l.o"
+                        srv_regobj="${srv_regobj} powerpc-altivec32l.o"
+                        srv_regobj="${srv_regobj} powerpc-cell32l.o"
+diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c
+index 279df9f..cba5d6f 100644
+--- a/gdb/gdbserver/linux-microblaze-low.c
+++ b/gdb/gdbserver/linux-microblaze-low.c
+@@ -43,7 +43,6 @@ static int microblaze_regmap[] =
+ 
+ /* Defined in auto-generated file microblaze-linux.c.  */
+ void init_registers_microblaze (void);
+-extern const struct target_desc *tdesc_microblaze;
+ 
+ static int
+ microblaze_cannot_store_register (int regno)
+@@ -108,7 +107,7 @@ microblaze_reinsert_addr (struct regcache *regcache)
+ static void
+ microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
+ {
+-  int size = register_size (regcache->tdesc, regno);
+  int size = register_size (regno);
+ 
+   memset (buf, 0, sizeof (long));
+ 
+@@ -122,7 +121,7 @@ static void
+ microblaze_supply_ptrace_register (struct regcache *regcache,
+                            int regno, const char *buf)
+ {
+-  int size = register_size (regcache->tdesc, regno);
+  int size = register_size (regno);
+ 
+   if (regno == 0) {
+     unsigned long regbuf_0 = 0;
+@@ -158,7 +157,7 @@ microblaze_store_gregset (struct regcache *regcache, const void *buf)
+ 
+ #endif /* HAVE_PTRACE_GETREGS */
+ 
+-static struct regset_info microblaze_regsets[] = {
+struct regset_info target_regsets[] = {
+ #ifdef HAVE_PTRACE_GETREGS
+   { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
+   { 0, 0, 0, -1, -1, NULL, NULL },
+@@ -166,41 +165,11 @@ static struct regset_info microblaze_regsets[] = {
+   { 0, 0, 0, -1, -1, NULL, NULL }
+ };
+ 
+-static struct regsets_info microblaze_regsets_info =
+-  {
+-    microblaze_regsets, /* regsets */
+-    0, /* num_regsets */
+-    NULL, /* disabled_regsets */
+-  };
+-
+-static struct usrregs_info microblaze_usrregs_info =
+-  {
+-    microblaze_num_regs,
+-    microblaze_regmap,
+-  };
+-
+-static struct regs_info regs_info =
+-  {
+-    NULL, /* regset_bitmap */
+-    &microblaze_usrregs_info,
+-    &microblaze_regsets_info
+-  };
+-
+-static const struct regs_info *
+-microblaze_regs_info (void)
+-{
+-  return &regs_info;
+-}
+-
+-static void
+-microblaze_arch_setup (void)
+-{
+-  current_process ()->tdesc = tdesc_microblaze;
+-}
+-
+ struct linux_target_ops the_low_target = {
+-  microblaze_arch_setup,
+-  microblaze_regs_info,
+  init_registers_microblaze,
+  microblaze_num_regs,
+  microblaze_regmap,
+  NULL,
+   microblaze_cannot_fetch_register,
+   microblaze_cannot_store_register,
+   NULL, /* fetch_register */
+@@ -218,11 +187,3 @@ struct linux_target_ops the_low_target = {
+   microblaze_collect_ptrace_register,
+   microblaze_supply_ptrace_register,
+ };
+-
+-void
+-initialize_low_arch (void)
+-{
+-  init_registers_microblaze ();
+-
+-  initialize_regsets_info (&microblaze_regsets_info);
+-}
+\ No newline at end of file
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0011-Patch-microblaze-Add-mb-singlestepping.patch b/recipes-devtools/gdb/files/0011-Patch-microblaze-Add-mb-singlestepping.patch
new file mode 100644
index 00000000..51b2e36e
--- /dev/null
+++ b/recipes-devtools/gdb/files/0011-Patch-microblaze-Add-mb-singlestepping.patch
@@ -0,0 +1,196 @@
+From: "Edgar E. Iglesias" <edgar@axis.com>
+Date: Fri, 24 Feb 2012 11:52:30 +0100
+Subject: Add mb singlestepping.
+Fix prologue analysis for little-endian.
+Always provide a frame base.
+Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
+Conflicts:
+        gdb/microblaze-tdep.c
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ gdb/microblaze-tdep.c |  117 +++++++++++++++++++++++++++++++++++++++++++++++--
+ 1 file changed, 114 insertions(+), 3 deletions(-)
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index a245169..9c9f3a9 100644
+--- a/gdb/microblaze-tdep.c
+++ b/gdb/microblaze-tdep.c
+@@ -282,6 +282,8 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+   int flags = 0;
+   int save_hidden_pointer_found = 0;
+   int non_stack_instruction_found = 0;
+  int n_insns;
+  unsigned int *insn_block;
+ 
+   /* Find the start of this function.  */
+   find_pc_partial_function (pc, &name, &func_addr, &func_end);
+@@ -321,11 +323,17 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+                    name, paddress (gdbarch, func_addr), 
+                    paddress (gdbarch, stop));
+ 
+  /* Do a block read to minimize the transaction with the Debug Agent */
+  n_insns = (stop == func_addr) ? 1 : ((stop - func_addr) / INST_WORD_SIZE);
+  insn_block = calloc(n_insns, sizeof(unsigned long));
+
+  target_read_memory (func_addr, (void*) insn_block, n_insns * INST_WORD_SIZE );
+
+   for (addr = func_addr; addr < stop; addr += INST_WORD_SIZE)
+     {
+       insn = microblaze_fetch_instruction (addr);
+       op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
+-      microblaze_debug ("%s %08lx\n", paddress (gdbarch, pc), insn);
+      microblaze_debug ("%s %08lx op=%x r%d r%d imm=%d\n", paddress (gdbarch, addr), insn, op, rd, ra, imm);
+ 
+       /* This code is very sensitive to what functions are present in the
+         prologue.  It assumes that the (addi, addik, swi, sw) can be the 
+@@ -449,7 +457,7 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+      part of the prologue.  */
+   if (save_hidden_pointer_found)
+     prologue_end_addr -= INST_WORD_SIZE;
+-
+    free(insn_block);
+   return prologue_end_addr;
+ }
+ 
+@@ -523,6 +531,7 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
+ 
+   func = get_frame_func (next_frame);
+ 
+  cache->base = get_frame_register_unsigned (next_frame, gdbarch_sp_regnum (gdbarch));
+   cache->pc = get_frame_address_in_block (next_frame);
+ 
+   return cache;
+@@ -539,7 +548,7 @@ microblaze_frame_this_id (struct frame_info *next_frame, void **this_cache,
+   if (cache->base == 0)
+     return;
+ 
+-  (*this_id) = frame_id_build (cache->base, cache->pc);
+  (*this_id) = frame_id_build (cache->base, get_frame_pc (next_frame));
+ }
+ 
+ static struct value *
+@@ -682,6 +691,107 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
+   return (TYPE_LENGTH (type) == 16);
+ }
+ 
+int
+microblaze_software_single_step (struct frame_info *frame)
+{
+  struct gdbarch *arch = get_frame_arch (frame);
+  struct address_space *aspace = get_frame_address_space (frame);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
+  static char le_breakp[] = MICROBLAZE_BREAKPOINT_LE;
+  static char be_breakp[] = MICROBLAZE_BREAKPOINT;
+  enum bfd_endian byte_order = gdbarch_byte_order (arch);
+  char *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp;
+  int ret = 0;
+
+  /* Save the address and the values of the next_pc and the target */
+  static struct sstep_breaks
+  {
+    CORE_ADDR address;
+    bfd_boolean valid;
+    /* Shadow contents.  */
+    char data[INST_WORD_SIZE];
+  } stepbreaks[2];
+  int ii;
+
+  if (1)
+    {
+      CORE_ADDR pc;
+      long insn;
+      enum microblaze_instr minstr;
+      bfd_boolean isunsignednum;
+      enum microblaze_instr_type insn_type;
+      short delay_slots;
+      int imm;
+      bfd_boolean immfound = FALSE;
+
+      /* Set a breakpoint at the next instruction */
+      /* If the current instruction is an imm, set it at the inst after */
+      /* If the instruction has a delay slot, skip the delay slot */
+      pc = get_frame_pc (frame);
+      insn = microblaze_fetch_instruction (pc);
+      minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
+      if (insn_type == immediate_inst)
+       {
+         int rd, ra, rb;
+         immfound = TRUE;
+         minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
+         pc = pc + INST_WORD_SIZE;
+         insn = microblaze_fetch_instruction (pc);
+         minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
+       }
+      stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE;
+      if (insn_type != return_inst) {
+       stepbreaks[0].valid = TRUE;
+      } else {
+       stepbreaks[0].valid = FALSE;
+      }
+
+      microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn);
+      /* Now check for branch or return instructions */
+      if (insn_type == branch_inst || insn_type == return_inst) {
+       int limm;
+       int lrd, lra, lrb;
+       int ra, rb;
+       bfd_boolean targetvalid;
+       bfd_boolean unconditionalbranch;
+       microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm);
+       if (lra >= 0 && lra < MICROBLAZE_NUM_REGS)
+         ra = get_frame_register_unsigned (frame, lra);
+       else
+         ra = 0;
+       if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS)
+         rb = get_frame_register_unsigned (frame, lrb);
+       else
+         rb = 0;
+       stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch);
+        microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
+       if (unconditionalbranch)
+         stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */
+       if (targetvalid && (stepbreaks[0].valid == FALSE ||
+                           (stepbreaks[0].address != stepbreaks[1].address))
+                       && (stepbreaks[1].address != pc)) {
+         stepbreaks[1].valid = TRUE;
+       } else {
+         stepbreaks[1].valid = FALSE;
+       }
+      } else {
+       stepbreaks[1].valid = FALSE;
+      }
+
+      /* Insert the breakpoints */
+      for (ii = 0; ii < 2; ++ii)
+        {
+
+          /* ignore invalid breakpoint. */
+          if (stepbreaks[ii].valid) {
+            insert_single_step_breakpoint (arch, aspace, stepbreaks[ii].address);
+            ret = 1;
+         }
+       }
+    }
+    return ret;
+}
+
+ static void
+ microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
+ {
+@@ -832,6 +942,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
+ 
+   set_gdbarch_breakpoint_from_pc (gdbarch, microblaze_breakpoint_from_pc);
+  set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+ 
+   set_gdbarch_frame_args_skip (gdbarch, 8);
+ 
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0012-Added-Backtrace-support-to-GDB.patch b/recipes-devtools/gdb/files/0012-Added-Backtrace-support-to-GDB.patch
new file mode 100644
index 00000000..b6bbe497
--- /dev/null
+++ b/recipes-devtools/gdb/files/0012-Added-Backtrace-support-to-GDB.patch
@@ -0,0 +1,146 @@
+From: nagaraju <nmekala@xilix.com>
+Date: Tue, 3 Sep 2013 12:09:47 +0530
+Subject: Added Backtrace support to GDB
+Added backtrace support without debugging information, Earlier backtrace used to work only when debug information is avialable.
+Previous pc & sp values are calculated incorrectly due to which backtrace was failing.
+In this patch, previous frame sp & pc values are calculated correctly in microblaze_frame_cache function
+and supplied them to microblaze_frame_prev_register function
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Upstream-Status: Pending
+---
+ gdb/microblaze-tdep.c |   44 ++++++++++++++++++++++++++++++--------------
+ gdb/microblaze-tdep.h |    5 +++--
+ 2 files changed, 33 insertions(+), 16 deletions(-)
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 9c9f3a9..f4b48a6 100644
+--- a/gdb/microblaze-tdep.c
+++ b/gdb/microblaze-tdep.c
+@@ -226,6 +226,7 @@ microblaze_alloc_frame_cache (void)
+   /* Base address.  */
+   cache->base = 0;
+   cache->pc = 0;
+  cache->saved_sp = 0;
+ 
+   /* Frameless until proven otherwise.  */
+   cache->frameless_p = 1;
+@@ -347,6 +348,7 @@ microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
+          cache->frameless_p = 0; /* Frame found.  */
+          save_hidden_pointer_found = 0;
+          non_stack_instruction_found = 0;
+         cache->register_offsets[rd] = -imm;
+          continue;
+        }
+       else if (IS_SPILL_SP(op, rd, ra))
+@@ -508,6 +510,7 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
+   return start_pc;
+ }
+ 
+enum { REG_UNAVAIL = (CORE_ADDR) -1 };
+ /* Normal frames.  */
+ 
+ static struct microblaze_frame_cache *
+@@ -515,7 +518,7 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
+ {
+   struct microblaze_frame_cache *cache;
+   struct gdbarch *gdbarch = get_frame_arch (next_frame);
+-  CORE_ADDR func;
+  CORE_ADDR current_pc;
+   int rn;
+ 
+   if (*this_cache)
+@@ -529,10 +532,18 @@ microblaze_frame_cache (struct frame_info *next_frame, void **this_cache)
+   for (rn = 0; rn < gdbarch_num_regs (gdbarch); rn++)
+     cache->register_offsets[rn] = -1;
+ 
+-  func = get_frame_func (next_frame);
+  cache->pc = get_frame_func (next_frame);
+  current_pc = get_frame_pc (next_frame);
+
+  if (cache->pc)
+    microblaze_analyze_prologue (gdbarch, cache->pc, current_pc,
+                                cache);
+ 
+   cache->base = get_frame_register_unsigned (next_frame, gdbarch_sp_regnum (gdbarch));
+-  cache->pc = get_frame_address_in_block (next_frame);
+  cache->saved_sp = cache->base + cache->framesize;
+
+  cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM] = cache->base;
+  cache->register_offsets[MICROBLAZE_SP_REGNUM] = cache->saved_sp;
+ 
+   return cache;
+ }
+@@ -548,7 +559,7 @@ microblaze_frame_this_id (struct frame_info *next_frame, void **this_cache,
+   if (cache->base == 0)
+     return;
+ 
+-  (*this_id) = frame_id_build (cache->base, get_frame_pc (next_frame));
+  (*this_id) = frame_id_build (cache->base, cache->pc);
+ }
+ 
+ static struct value *
+@@ -558,18 +569,23 @@ microblaze_frame_prev_register (struct frame_info *this_frame,
+   struct microblaze_frame_cache *cache =
+     microblaze_frame_cache (this_frame, this_cache);
+ 
+-  if (cache->frameless_p)
+  if ((regnum == MICROBLAZE_SP_REGNUM &&
+      cache->register_offsets[MICROBLAZE_SP_REGNUM])
+      || (regnum == MICROBLAZE_FP_REGNUM &&
+      cache->register_offsets[MICROBLAZE_SP_REGNUM]))
+
+     return frame_unwind_got_constant (this_frame, regnum,
+                                       cache->register_offsets[MICROBLAZE_SP_REGNUM]);
+
+  if (regnum == MICROBLAZE_PC_REGNUM)
+     {
+-      if (regnum == MICROBLAZE_PC_REGNUM)
+-        regnum = 15;
+-      if (regnum == MICROBLAZE_SP_REGNUM)
+-        regnum = 1;
+-      return trad_frame_get_prev_register (this_frame,
+-                                          cache->saved_regs, regnum);
+      regnum = 15;
+      return frame_unwind_got_memory (this_frame, regnum,
+                                      cache->register_offsets[MICROBLAZE_PREV_PC_REGNUM]);
+     }
+-  else
+-    return trad_frame_get_prev_register (this_frame, cache->saved_regs,
+-                                        regnum);
+
+  return trad_frame_get_prev_register (this_frame, cache->saved_regs,
+                                       regnum);
+ 
+ }
+ 
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 23dc77a..cf24ed4 100644
+--- a/gdb/microblaze-tdep.h
+++ b/gdb/microblaze-tdep.h
+@@ -57,6 +57,7 @@ struct microblaze_frame_cache
+ 
+   /* Offsets to saved registers.  */
+   int register_offsets[59];    /* Must match MICROBLAZE_NUM_REGS.  */
+  CORE_ADDR saved_sp;
+ 
+   /* Table of saved registers.  */
+   struct trad_frame_saved_reg *saved_regs;
+@@ -80,11 +81,11 @@ enum microblaze_regnum
+   MICROBLAZE_R12_REGNUM,
+   MICROBLAZE_R13_REGNUM,
+   MICROBLAZE_R14_REGNUM,
+-  MICROBLAZE_R15_REGNUM,
+  MICROBLAZE_R15_REGNUM, MICROBLAZE_PREV_PC_REGNUM = MICROBLAZE_R15_REGNUM,
+   MICROBLAZE_R16_REGNUM,
+   MICROBLAZE_R17_REGNUM,
+   MICROBLAZE_R18_REGNUM,
+-  MICROBLAZE_R19_REGNUM,
+  MICROBLAZE_R19_REGNUM, MICROBLAZE_FP_REGNUM = MICROBLAZE_R19_REGNUM,
+   MICROBLAZE_R20_REGNUM,
+   MICROBLAZE_R21_REGNUM,
+   MICROBLAZE_R22_REGNUM,
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0013-microblaze-Handle-framless-functions-in-determining-.patch b/recipes-devtools/gdb/files/0013-microblaze-Handle-framless-functions-in-determining-.patch
new file mode 100644
index 00000000..70dcbe43
--- /dev/null
+++ b/recipes-devtools/gdb/files/0013-microblaze-Handle-framless-functions-in-determining-.patch
@@ -0,0 +1,40 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Thu, 7 Nov 2013 16:58:48 +1000
+Subject: microblaze: Handle framless functions in determining
+ prev reg
+Add check for cache->frameless_p in microblaze_frame_prev_register
+to handle frameless functions, and correct the behaviour of using
+'next' to step through debugging
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+Upstream-Status: Pending
+---
+ gdb/microblaze-tdep.c |   10 ++++++++++
+ 1 file changed, 10 insertions(+)
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index f4b48a6..a85adea6 100644
+--- a/gdb/microblaze-tdep.c
+++ b/gdb/microblaze-tdep.c
+@@ -577,6 +577,16 @@ microblaze_frame_prev_register (struct frame_info *this_frame,
+      return frame_unwind_got_constant (this_frame, regnum,
+                                        cache->register_offsets[MICROBLAZE_SP_REGNUM]);
+ 
+  if (cache->frameless_p)
+    {
+      if (regnum == MICROBLAZE_PC_REGNUM)
+        regnum = 15;
+      if (regnum == MICROBLAZE_SP_REGNUM)
+        regnum = 1;
+      return trad_frame_get_prev_register (this_frame,
+            cache->saved_regs, regnum);
+    }
+
+   if (regnum == MICROBLAZE_PC_REGNUM)
+     {
+       regnum = 15;
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/files/0014-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch b/recipes-devtools/gdb/files/0014-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
new file mode 100644
index 00000000..78067c87
--- /dev/null
+++ b/recipes-devtools/gdb/files/0014-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
@@ -0,0 +1,31 @@
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 16 Dec 2013 16:37:32 +1000
+Subject: microblaze: Add build_gdbserver=yes to top level configure.tgt
+For Microblaze linux toolchains, set the build_gdbserver=yes
+to allow driving gdbserver configuration from the upper level
+This patch has been absorbed into the original patch to add
+linux gdbserver support for Microblaze.
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Upstream-Status: Pending
+---
+ gdb/configure.tgt |    1 +
+ 1 file changed, 1 insertion(+)
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index 1285aac..6ea10a2 100644
+--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
+@@ -342,6 +342,7 @@ microblaze*-linux-*|microblaze*-*-linux*)
+        gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o microblaze-rom.o glibc-tdep.o \
+                        monitor.o dsrec.o solib-svr4.o symfile-mem.o linux-tdep.o"
+        gdb_sim=../sim/microblaze/libsim.a
+       build_gdbserver=yes
+        ;;
+ microblaze*-*-*)
+        # Target: Xilinx MicroBlaze running standalone
+-- 
+1.7.9.5
diff --git a/recipes-devtools/gdb/gdb-cross-canadian_7.6.2.bbappend b/recipes-devtools/gdb/gdb-cross-canadian_7.6.2.bbappend
new file mode 100644
index 00000000..db1e3127
--- /dev/null
+++ b/recipes-devtools/gdb/gdb-cross-canadian_7.6.2.bbappend
@@ -0,0 +1 @@
+require gdb-microblaze-${PV}.inc
diff --git a/recipes-devtools/gdb/gdb-cross_7.6.2.bbappend b/recipes-devtools/gdb/gdb-cross_7.6.2.bbappend
new file mode 100644
index 00000000..db1e3127
--- /dev/null
+++ b/recipes-devtools/gdb/gdb-cross_7.6.2.bbappend
@@ -0,0 +1 @@
+require gdb-microblaze-${PV}.inc
diff --git a/recipes-devtools/gdb/gdb-microblaze-7.6.2.inc b/recipes-devtools/gdb/gdb-microblaze-7.6.2.inc
new file mode 100644
index 00000000..9f30eb9a
--- /dev/null
+++ b/recipes-devtools/gdb/gdb-microblaze-7.6.2.inc
@@ -0,0 +1,22 @@
+# MicroBlaze does not support LTTng UST
+LTTNGUST_microblaze = ""
+# Add MicroBlaze Patches
+FILESEXTRAPATHS_append := "${THISDIR}/files:"
+SRC_URI_append += " \
+                file://0001-Add-initial-port-of-linux-gdbserver.patch \
+                file://0002-Initial-port-of-core-reading-support.patch \
+                file://0003-Initial-support-for-native-gdb.patch \
+                file://0004-Robustify-inline-function-support.patch \
+                file://0005-Fix-debug-message-when-register-is-unavailable.patch \
+                file://0006-Add-slr-and-shr-regs-and-little-endian-breakpoint.patch \
+                file://0007-Fix-relaxation-of-assembler-resolved-references.patch \
+                file://0008-Fixup-debug_loc-sections-after-linker-relaxation.patch \
+                file://0009-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \
+                file://0010-revert-master-rebase-changes-to-gdbserver.patch \
+                file://0011-Patch-microblaze-Add-mb-singlestepping.patch \
+                file://0012-Added-Backtrace-support-to-GDB.patch \
+                file://0013-microblaze-Handle-framless-functions-in-determining-.patch \
+                file://0014-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch \
+                "
diff --git a/recipes-devtools/gdb/gdb_7.6.2.bbappend b/recipes-devtools/gdb/gdb_7.6.2.bbappend
new file mode 100644
index 00000000..db1e3127
--- /dev/null
+++ b/recipes-devtools/gdb/gdb_7.6.2.bbappend
@@ -0,0 +1 @@
+require gdb-microblaze-${PV}.inc
diff --git a/recipes-devtools/gnu-config/files/microblazeel.patch b/recipes-devtools/gnu-config/files/microblazeel.patch
new file mode 100644
index 00000000..2b8249d5
--- /dev/null
+++ b/recipes-devtools/gnu-config/files/microblazeel.patch
@@ -0,0 +1,68 @@
+From fb456b34ef4aa02b95dc6be69aaa66fa94a844fb Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 10 Oct 2012 04:33:17 +0000
+Subject:        * config.sub (microblazeel): New.
+        * testsuite/config-sub.data: Add a test case.
+Signed-off-by: Ben Elliston <bje@gnu.org>
+Upstream-Status: Backport [Not part of 2012-08-14]
+---
+diff --git a/config.sub b/config.sub
+index bdda9e4..826e4c6 100755
+--- a/config.sub
+++ b/config.sub
+@@ -156,7 +156,7 @@ case $os in
+        -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\
+        -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \
+        -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \
+-       -apple | -axis | -knuth | -cray | -microblaze)
+       -apple | -axis | -knuth | -cray | -microblaze*)
+                os=
+                basic_machine=$1
+                ;;
+@@ -273,7 +273,7 @@ case $basic_machine in
+        | le32 | le64 \
+        | lm32 \
+        | m32c | m32r | m32rle | m68000 | m68k | m88k \
+-       | maxq | mb | microblaze | mcore | mep | metag \
+       | maxq | mb | microblaze | microblazeel | mcore | mep | metag \
+        | mips | mipsbe | mipseb | mipsel | mipsle \
+        | mips16 \
+        | mips64 | mips64el \
+@@ -389,7 +389,8 @@ case $basic_machine in
+        | lm32-* \
+        | m32c-* | m32r-* | m32rle-* \
+        | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \
+-       | m88110-* | m88k-* | maxq-* | mcore-* | metag-* | microblaze-* \
+       | m88110-* | m88k-* | maxq-* | mcore-* | metag-* \
+       | microblaze-* | microblazeel-* \
+        | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \
+        | mips16-* \
+        | mips64-* | mips64el-* \
+@@ -788,7 +789,7 @@ case $basic_machine in
+                basic_machine=ns32k-utek
+                os=-sysv
+                ;;
+-       microblaze)
+       microblaze*)
+                basic_machine=microblaze-xilinx
+                ;;
+        mingw64)
+diff --git a/testsuite/config-sub.data b/testsuite/config-sub.data
+index fafbca1..9bd2cd5 100644
+--- a/testsuite/config-sub.data
+++ b/testsuite/config-sub.data
+@@ -99,8 +99,11 @@ mep                          mep-unknown-elf
+ metag-linux                    metag-unknown-linux-gnu
+ metag                          metag-unknown-none
+ microblaze-elf                 microblaze-unknown-elf
+microblazeel-elf               microblazeel-unknown-elf
+ microblaze-linux               microblaze-unknown-linux-gnu
+microblazeel-linux             microblazeel-unknown-linux-gnu
+ microblaze                     microblaze-unknown-none
+microblazeel                   microblazeel-unknown-none
+ mingw32ce                      arm-unknown-mingw32ce
+ mingw64                                x86_64-pc-mingw64
+ mips64octeonel-elf             mips64octeonel-unknown-elf
+---
diff --git a/recipes-devtools/gnu-config/gnu-config_20120814.bbappend b/recipes-devtools/gnu-config/gnu-config_20120814.bbappend
new file mode 100644
index 00000000..0a9331cb
--- /dev/null
+++ b/recipes-devtools/gnu-config/gnu-config_20120814.bbappend
@@ -0,0 +1,6 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+# Apply patch to add "microblazeel" support to gnu-config
+SRC_URI += "file://microblazeel.patch"
diff --git a/recipes-devtools/qemu/files/HACK_target-arm_Harcode_the_SCU_offset.patch b/recipes-devtools/qemu/files/HACK_target-arm_Harcode_the_SCU_offset.patch
new file mode 100644
index 00000000..68c8dfaa
--- /dev/null
+++ b/recipes-devtools/qemu/files/HACK_target-arm_Harcode_the_SCU_offset.patch
@@ -0,0 +1,22 @@
+From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Date: Fri, 15 Feb 2013 07:08:24 +0000
+Subject: HACK: target-arm: Harcode the SCU offset
+Becuase the QOM framework to drive this from a property isnt there yet.
+Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+---
+diff --git a/target-arm/cpu.c b/target-arm/cpu.c
+index 496a59f..705688b 100644
+--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
+@@ -531,7 +531,7 @@ static void cortex_a9_initfn(Object *obj)
+     {
+         ARMCPRegInfo cbar = {
+             .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
+-            .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
+            .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = 0xf8f00000,
+             .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
+         };
+         define_one_arm_cp_reg(cpu, &cbar);
+--
diff --git a/recipes-devtools/qemu/files/HACK_zynq_slcr_Bring_SLCR_out_of_reset_in_kernel_state.patch b/recipes-devtools/qemu/files/HACK_zynq_slcr_Bring_SLCR_out_of_reset_in_kernel_state.patch
new file mode 100644
index 00000000..527422b5
--- /dev/null
+++ b/recipes-devtools/qemu/files/HACK_zynq_slcr_Bring_SLCR_out_of_reset_in_kernel_state.patch
@@ -0,0 +1,48 @@
+From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Date: Wed, 27 Mar 2013 02:00:09 +0000
+Subject: HACK: zynq_slcr: Bring SLCR out of reset in kernel state
+Reset the zynq_slcr into something more closely resembling the post
+FSBL handoff state. Needed to keep the Linux clock framework happy.
+I can only apply this patch (in its current form), to the workarounds
+branch but I am RFCing it, as if there are any other things I should
+be changing, let me know! I'll factor them into a real solution.
+Cc: sorenb@xilinx.com
+Cc: michal.simek@xilinx.com
+Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+---
+diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
+index 872ba3f..8f3e614 100644
+--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
+@@ -243,19 +243,19 @@ static void zynq_slcr_reset(DeviceState *d)
+ 
+     s->lockval = 1;
+     /* 0x100 - 0x11C */
+-    s->pll[ARM_PLL_CTRL] = 0x0001A008;
+-    s->pll[DDR_PLL_CTRL] = 0x0001A008;
+-    s->pll[IO_PLL_CTRL] = 0x0001A008;
+    s->pll[ARM_PLL_CTRL] = 0x00028008;
+    s->pll[DDR_PLL_CTRL] = 0x00020008;
+    s->pll[IO_PLL_CTRL] = 0x0001e008;
+     s->pll[PLL_STATUS] = 0x0000003F;
+-    s->pll[ARM_PPL_CFG] = 0x00014000;
+-    s->pll[DDR_PLL_CFG] = 0x00014000;
+-    s->pll[IO_PLL_CFG] = 0x00014000;
+    s->pll[ARM_PPL_CFG] = 0x000fa220;
+    s->pll[DDR_PLL_CFG] = 0x0012c220;
+    s->pll[IO_PLL_CFG] = 0x001452c0;
+ 
+     /* 0x120 - 0x16C */
+-    s->clk[ARM_CLK_CTRL] = 0x1F000400;
+    s->clk[ARM_CLK_CTRL] = 0x1F000200;
+     s->clk[DDR_CLK_CTRL] = 0x18400003;
+     s->clk[DCI_CLK_CTRL] = 0x01E03201;
+-    s->clk[APER_CLK_CTRL] = 0x01FFCCCD;
+    s->clk[APER_CLK_CTRL] = 0x01ed044d;
+     s->clk[USB0_CLK_CTRL] = s->clk[USB1_CLK_CTRL] = 0x00101941;
+     s->clk[GEM0_RCLK_CTRL] = s->clk[GEM1_RCLK_CTRL] = 0x00000001;
+     s->clk[GEM0_CLK_CTRL] = s->clk[GEM1_CLK_CTRL] = 0x00003C01;
+--
diff --git a/recipes-devtools/qemu/files/hw-net-xilinx_axienet.c-Add-phy-soft-reset-bit-clear.patch b/recipes-devtools/qemu/files/hw-net-xilinx_axienet.c-Add-phy-soft-reset-bit-clear.patch
new file mode 100644
index 00000000..9bc7a564
--- /dev/null
+++ b/recipes-devtools/qemu/files/hw-net-xilinx_axienet.c-Add-phy-soft-reset-bit-clear.patch
@@ -0,0 +1,29 @@
+From 425580f9241098c9ef554a33b80153624b1e0318 Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan.rossi@xilinx.com>
+Date: Wed, 9 Apr 2014 11:15:25 +1000
+Subject: [PATCH] hw/net/xilinx_axienet.c: Add phy soft reset bit clearing
+* Clear the BMCR Reset when writing to registers.
+Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
+---
+ hw/net/xilinx_axienet.c | 3 +++
+ 1 file changed, 3 insertions(+)
+diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
+index 3eb7715..d9c15df 100644
+--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
+@@ -142,6 +142,9 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
+             phy->regs[regnum] = data;
+             break;
+     }
+
+    /* Unconditionally clear regs[BMCR][BMCR_RESET] */
+    phy->regs[0] &= ~0x8000;
+ }
+ 
+ static void
+-- 
+1.9.0
diff --git a/recipes-devtools/qemu/files/qom_object_c_Split_out_object_and_class_caches.patch b/recipes-devtools/qemu/files/qom_object_c_Split_out_object_and_class_caches.patch
new file mode 100644
index 00000000..b64a8391
--- /dev/null
+++ b/recipes-devtools/qemu/files/qom_object_c_Split_out_object_and_class_caches.patch
@@ -0,0 +1,101 @@
+Subject: [qom,v1,1/1] qom/object.c: Split out object and class caches.
+From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Message-Id: <23ad4a5a9283ffcf4fc384832f369df46db18ef6.1385612379.git.peter.crosthwaite@xilinx.com>
+To: qemu-devel@nongnu.org,
+        aliguori@us.ibm.com,
+        pbonzini@redhat.com
+Cc: afaerber@suse.de
+Date: Wed, 27 Nov 2013 20:27:33 -0800
+The object-cast and class-cast caches cannot be shared because class
+caching is conditional on the target type not being an interface and
+object caching is unconditional. Leads to a bug when a class cast
+to an interface follows an object cast to the same interface type:
+FooObject = FOO(obj);
+FooClass = FOO_GET_CLASS(obj);
+Where TYPE_FOO is an interface. The first (object) cast will be
+successful and cache the casting result (i.e. TYPE_FOO will be cached).
+The second (class) cast will then check the shared cast cache
+and register a hit. The issue is, when a class cast hits in the cache
+it just returns a pointer cast of the input class (i.e. the concrete
+class).
+When casting to an interface, the cast itself must return the
+interface class, not the concrete class. The implementation of class
+cast caching already ensures that the returned cast result is only
+a pointer cast before caching. The object cast logic however does
+not have this check.
+Resolve by just splitting the object and class caches.
+Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
+Upstream-Status: Pending [Pulled from upstream mailing list]
+---
+include/qom/object.h |  3 ++-
+ qom/object.c         | 13 +++++++------
+ 2 files changed, 9 insertions(+), 7 deletions(-)
+diff --git a/include/qom/object.h b/include/qom/object.h
+index a275db2..5f78847 100644
+--- a/include/qom/object.h
+++ b/include/qom/object.h
+@@ -358,7 +358,8 @@ struct ObjectClass
+     Type type;
+     GSList *interfaces;
+ 
+-    const char *cast_cache[OBJECT_CLASS_CAST_CACHE];
+    const char *object_cast_cache[OBJECT_CLASS_CAST_CACHE];
+    const char *class_cast_cache[OBJECT_CLASS_CAST_CACHE];
+ 
+     ObjectUnparent *unparent;
+ };
+diff --git a/qom/object.c b/qom/object.c
+index fc19cf6..21b5a0b 100644
+--- a/qom/object.c
+++ b/qom/object.c
+@@ -458,7 +458,7 @@ Object *object_dynamic_cast_assert(Object *obj, const char *typename,
+     Object *inst;
+ 
+     for (i = 0; obj && i < OBJECT_CLASS_CAST_CACHE; i++) {
+-        if (obj->class->cast_cache[i] == typename) {
+        if (obj->class->object_cast_cache[i] == typename) {
+             goto out;
+         }
+     }
+@@ -475,9 +475,10 @@ Object *object_dynamic_cast_assert(Object *obj, const char *typename,
+ 
+     if (obj && obj == inst) {
+         for (i = 1; i < OBJECT_CLASS_CAST_CACHE; i++) {
+-            obj->class->cast_cache[i - 1] = obj->class->cast_cache[i];
+            obj->class->object_cast_cache[i - 1] =
+                    obj->class->object_cast_cache[i];
+         }
+-        obj->class->cast_cache[i - 1] = typename;
+        obj->class->object_cast_cache[i - 1] = typename;
+     }
+ 
+ out:
+@@ -547,7 +548,7 @@ ObjectClass *object_class_dynamic_cast_assert(ObjectClass *class,
+     int i;
+ 
+     for (i = 0; class && i < OBJECT_CLASS_CAST_CACHE; i++) {
+-        if (class->cast_cache[i] == typename) {
+        if (class->class_cast_cache[i] == typename) {
+             ret = class;
+             goto out;
+         }
+@@ -568,9 +569,9 @@ ObjectClass *object_class_dynamic_cast_assert(ObjectClass *class,
+ #ifdef CONFIG_QOM_CAST_DEBUG
+     if (class && ret == class) {
+         for (i = 1; i < OBJECT_CLASS_CAST_CACHE; i++) {
+-            class->cast_cache[i - 1] = class->cast_cache[i];
+            class->class_cast_cache[i - 1] = class->class_cast_cache[i];
+         }
+-        class->cast_cache[i - 1] = typename;
+        class->class_cast_cache[i - 1] = typename;
+     }
+ out:
+ #endif
diff --git a/recipes-devtools/qemu/qemu_1.7.0.bbappend b/recipes-devtools/qemu/qemu_1.7.0.bbappend
new file mode 100644
index 00000000..a06eefef
--- /dev/null
+++ b/recipes-devtools/qemu/qemu_1.7.0.bbappend
@@ -0,0 +1,9 @@
+QEMU_TARGETS += "microblazeel"
+FILESEXTRAPATHS_append := "${THISDIR}/files:"
+SRC_URI_append += " \
+                file://HACK_target-arm_Harcode_the_SCU_offset.patch \
+                file://HACK_zynq_slcr_Bring_SLCR_out_of_reset_in_kernel_state.patch \
+                file://qom_object_c_Split_out_object_and_class_caches.patch \
+                file://hw-net-xilinx_axienet.c-Add-phy-soft-reset-bit-clear.patch \
+                "