1 files changed, 0 insertions, 143 deletions

diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch
deleted file mode 100644
index e468563b..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch
+++ /dev/null
@@ -1,143 +0,0 @@
-From 9f9cd8a67975d0973bf5d0dd0bdf6e0bff168774 Mon Sep 17 00:00:00 2001
-From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Mar 2015 04:05:15 -0700
-Subject: [PATCH 07/15] net: cadence_gem: Split state struct and type into
- header
-
-To allow using the device with modern SoC programming conventions. The
-state struct needs to be visible to embed the device in SoC containers.
-
-Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
-Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
----
- hw/net/cadence_gem.c         |   43 +-----------------------------------
- include/hw/net/cadence_gem.h |   49 ++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 50 insertions(+), 42 deletions(-)
- create mode 100644 include/hw/net/cadence_gem.h
-
-diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
-index 5994306..dafe914 100644
---- a/hw/net/cadence_gem.c
-+++ b/hw/net/cadence_gem.c
-@@ -24,8 +24,7 @@
- 
- #include <zlib.h> /* For crc32 */
- 
--#include "hw/sysbus.h"
--#include "net/net.h"
-+#include "hw/net/cadence_gem.h"
- #include "net/checksum.h"
- 
- #ifdef CADENCE_GEM_ERR_DEBUG
-@@ -141,8 +140,6 @@
- #define GEM_DESCONF6      (0x00000294/4)
- #define GEM_DESCONF7      (0x00000298/4)
- 
--#define CADENCE_GEM_MAXREG        (0x00000640/4) /* Last valid GEM address */
--
- /*****************************************/
- #define GEM_NWCTRL_TXSTART     0x00000200 /* Transmit Enable */
- #define GEM_NWCTRL_TXENA       0x00000008 /* Transmit Enable */
-@@ -349,44 +346,6 @@ static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
-     desc[1] |= R_DESC_1_RX_SAR_MATCH;
- }
- 
--#define TYPE_CADENCE_GEM "cadence_gem"
--#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM)
--
--typedef struct CadenceGEMState {
--    SysBusDevice parent_obj;
--
--    MemoryRegion iomem;
--    NICState *nic;
--    NICConf conf;
--    qemu_irq irq;
--
--    /* GEM registers backing store */
--    uint32_t regs[CADENCE_GEM_MAXREG];
--    /* Mask of register bits which are write only */
--    uint32_t regs_wo[CADENCE_GEM_MAXREG];
--    /* Mask of register bits which are read only */
--    uint32_t regs_ro[CADENCE_GEM_MAXREG];
--    /* Mask of register bits which are clear on read */
--    uint32_t regs_rtc[CADENCE_GEM_MAXREG];
--    /* Mask of register bits which are write 1 to clear */
--    uint32_t regs_w1c[CADENCE_GEM_MAXREG];
--
--    /* PHY registers backing store */
--    uint16_t phy_regs[32];
--
--    uint8_t phy_loop; /* Are we in phy loopback? */
--
--    /* The current DMA descriptor pointers */
--    uint32_t rx_desc_addr;
--    uint32_t tx_desc_addr;
--
--    uint8_t can_rx_state; /* Debug only */
--
--    unsigned rx_desc[2];
--
--    bool sar_active[4];
--} CadenceGEMState;
--
- /* The broadcast MAC address: 0xFFFFFFFFFFFF */
- static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
- 
-diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
-new file mode 100644
-index 0000000..12de820
---- /dev/null
-+++ b/include/hw/net/cadence_gem.h
-@@ -0,0 +1,49 @@
-+#ifndef CADENCE_GEM_H_
-+
-+#define TYPE_CADENCE_GEM "cadence_gem"
-+#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM)
-+
-+#include "net/net.h"
-+#include "hw/sysbus.h"
-+
-+#define CADENCE_GEM_MAXREG        (0x00000640/4) /* Last valid GEM address */
-+
-+typedef struct CadenceGEMState {
-+    /*< private >*/
-+    SysBusDevice parent_obj;
-+
-+    /*< public >*/
-+    MemoryRegion iomem;
-+    NICState *nic;
-+    NICConf conf;
-+    qemu_irq irq;
-+
-+    /* GEM registers backing store */
-+    uint32_t regs[CADENCE_GEM_MAXREG];
-+    /* Mask of register bits which are write only */
-+    uint32_t regs_wo[CADENCE_GEM_MAXREG];
-+    /* Mask of register bits which are read only */
-+    uint32_t regs_ro[CADENCE_GEM_MAXREG];
-+    /* Mask of register bits which are clear on read */
-+    uint32_t regs_rtc[CADENCE_GEM_MAXREG];
-+    /* Mask of register bits which are write 1 to clear */
-+    uint32_t regs_w1c[CADENCE_GEM_MAXREG];
-+
-+    /* PHY registers backing store */
-+    uint16_t phy_regs[32];
-+
-+    uint8_t phy_loop; /* Are we in phy loopback? */
-+
-+    /* The current DMA descriptor pointers */
-+    uint32_t rx_desc_addr;
-+    uint32_t tx_desc_addr;
-+
-+    uint8_t can_rx_state; /* Debug only */
-+
-+    unsigned rx_desc[2];
-+
-+    bool sar_active[4];
-+} CadenceGEMState;
-+
-+#define CADENCE_GEM_H_
-+#endif
--- 
-1.7.10.4
-