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-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0006-net-cadence_gem-Clean-up-variable-names.patch269
1 files changed, 0 insertions, 269 deletions
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0006-net-cadence_gem-Clean-up-variable-names.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0006-net-cadence_gem-Clean-up-variable-names.patch
deleted file mode 100644
index 53453ca9..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0006-net-cadence_gem-Clean-up-variable-names.patch
+++ /dev/null
@@ -1,269 +0,0 @@
1From 7c37c0a33c598fe0dcb015aa4d48712e33e21a8b Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:14 -0700
4Subject: [PATCH 06/15] net: cadence_gem: Clean up variable names
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9In preparation for migrating the state struct and type cast macro to a public
10header. The acronym "GEM" on it's own is not specific enough to be used in a
11more global namespace so preface with "cadence". Fix the capitalisation of
12"gem" in the state type while touching the typename. Also preface the
13GEM_MAXREG macro as this will need to migrate to public header.
14
15Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
16Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
17Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
18---
19 hw/net/cadence_gem.c | 70 +++++++++++++++++++++++++-------------------------
20 1 file changed, 35 insertions(+), 35 deletions(-)
21
22diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
23index 55b6293..5994306 100644
24--- a/hw/net/cadence_gem.c
25+++ b/hw/net/cadence_gem.c
26@@ -141,7 +141,7 @@
27 #define GEM_DESCONF6 (0x00000294/4)
28 #define GEM_DESCONF7 (0x00000298/4)
29
30-#define GEM_MAXREG (0x00000640/4) /* Last valid GEM address */
31+#define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */
32
33 /*****************************************/
34 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
35@@ -350,9 +350,9 @@ static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
36 }
37
38 #define TYPE_CADENCE_GEM "cadence_gem"
39-#define GEM(obj) OBJECT_CHECK(GemState, (obj), TYPE_CADENCE_GEM)
40+#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM)
41
42-typedef struct GemState {
43+typedef struct CadenceGEMState {
44 SysBusDevice parent_obj;
45
46 MemoryRegion iomem;
47@@ -361,15 +361,15 @@ typedef struct GemState {
48 qemu_irq irq;
49
50 /* GEM registers backing store */
51- uint32_t regs[GEM_MAXREG];
52+ uint32_t regs[CADENCE_GEM_MAXREG];
53 /* Mask of register bits which are write only */
54- uint32_t regs_wo[GEM_MAXREG];
55+ uint32_t regs_wo[CADENCE_GEM_MAXREG];
56 /* Mask of register bits which are read only */
57- uint32_t regs_ro[GEM_MAXREG];
58+ uint32_t regs_ro[CADENCE_GEM_MAXREG];
59 /* Mask of register bits which are clear on read */
60- uint32_t regs_rtc[GEM_MAXREG];
61+ uint32_t regs_rtc[CADENCE_GEM_MAXREG];
62 /* Mask of register bits which are write 1 to clear */
63- uint32_t regs_w1c[GEM_MAXREG];
64+ uint32_t regs_w1c[CADENCE_GEM_MAXREG];
65
66 /* PHY registers backing store */
67 uint16_t phy_regs[32];
68@@ -385,7 +385,7 @@ typedef struct GemState {
69 unsigned rx_desc[2];
70
71 bool sar_active[4];
72-} GemState;
73+} CadenceGEMState;
74
75 /* The broadcast MAC address: 0xFFFFFFFFFFFF */
76 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
77@@ -395,7 +395,7 @@ static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
78 * One time initialization.
79 * Set masks to identify which register bits have magical clear properties
80 */
81-static void gem_init_register_masks(GemState *s)
82+static void gem_init_register_masks(CadenceGEMState *s)
83 {
84 /* Mask of register bits which are read only */
85 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
86@@ -430,7 +430,7 @@ static void gem_init_register_masks(GemState *s)
87 * phy_update_link:
88 * Make the emulated PHY link state match the QEMU "interface" state.
89 */
90-static void phy_update_link(GemState *s)
91+static void phy_update_link(CadenceGEMState *s)
92 {
93 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
94
95@@ -450,7 +450,7 @@ static void phy_update_link(GemState *s)
96
97 static int gem_can_receive(NetClientState *nc)
98 {
99- GemState *s;
100+ CadenceGEMState *s;
101
102 s = qemu_get_nic_opaque(nc);
103
104@@ -483,7 +483,7 @@ static int gem_can_receive(NetClientState *nc)
105 * gem_update_int_status:
106 * Raise or lower interrupt based on current status.
107 */
108-static void gem_update_int_status(GemState *s)
109+static void gem_update_int_status(CadenceGEMState *s)
110 {
111 if (s->regs[GEM_ISR]) {
112 DB_PRINT("asserting int. (0x%08x)\n", s->regs[GEM_ISR]);
113@@ -495,7 +495,7 @@ static void gem_update_int_status(GemState *s)
114 * gem_receive_updatestats:
115 * Increment receive statistics.
116 */
117-static void gem_receive_updatestats(GemState *s, const uint8_t *packet,
118+static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
119 unsigned bytes)
120 {
121 uint64_t octets;
122@@ -586,7 +586,7 @@ static unsigned calc_mac_hash(const uint8_t *mac)
123 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT,
124 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT
125 */
126-static int gem_mac_address_filter(GemState *s, const uint8_t *packet)
127+static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
128 {
129 uint8_t *gem_spaddr;
130 int i;
131@@ -636,7 +636,7 @@ static int gem_mac_address_filter(GemState *s, const uint8_t *packet)
132 return GEM_RX_REJECT;
133 }
134
135-static void gem_get_rx_desc(GemState *s)
136+static void gem_get_rx_desc(CadenceGEMState *s)
137 {
138 DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr);
139 /* read current descriptor */
140@@ -660,7 +660,7 @@ static void gem_get_rx_desc(GemState *s)
141 */
142 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
143 {
144- GemState *s;
145+ CadenceGEMState *s;
146 unsigned rxbufsize, bytes_to_copy;
147 unsigned rxbuf_offset;
148 uint8_t rxbuf[2048];
149@@ -810,7 +810,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
150 * gem_transmit_updatestats:
151 * Increment transmit statistics.
152 */
153-static void gem_transmit_updatestats(GemState *s, const uint8_t *packet,
154+static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
155 unsigned bytes)
156 {
157 uint64_t octets;
158@@ -856,7 +856,7 @@ static void gem_transmit_updatestats(GemState *s, const uint8_t *packet,
159 * gem_transmit:
160 * Fish packets out of the descriptor ring and feed them to QEMU
161 */
162-static void gem_transmit(GemState *s)
163+static void gem_transmit(CadenceGEMState *s)
164 {
165 unsigned desc[2];
166 hwaddr packet_desc_addr;
167@@ -976,7 +976,7 @@ static void gem_transmit(GemState *s)
168 }
169 }
170
171-static void gem_phy_reset(GemState *s)
172+static void gem_phy_reset(CadenceGEMState *s)
173 {
174 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
175 s->phy_regs[PHY_REG_CONTROL] = 0x1140;
176@@ -1004,7 +1004,7 @@ static void gem_phy_reset(GemState *s)
177 static void gem_reset(DeviceState *d)
178 {
179 int i;
180- GemState *s = GEM(d);
181+ CadenceGEMState *s = CADENCE_GEM(d);
182
183 DB_PRINT("\n");
184
185@@ -1032,13 +1032,13 @@ static void gem_reset(DeviceState *d)
186 gem_update_int_status(s);
187 }
188
189-static uint16_t gem_phy_read(GemState *s, unsigned reg_num)
190+static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num)
191 {
192 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]);
193 return s->phy_regs[reg_num];
194 }
195
196-static void gem_phy_write(GemState *s, unsigned reg_num, uint16_t val)
197+static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
198 {
199 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val);
200
201@@ -1072,10 +1072,10 @@ static void gem_phy_write(GemState *s, unsigned reg_num, uint16_t val)
202 */
203 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
204 {
205- GemState *s;
206+ CadenceGEMState *s;
207 uint32_t retval;
208
209- s = (GemState *)opaque;
210+ s = (CadenceGEMState *)opaque;
211
212 offset >>= 2;
213 retval = s->regs[offset];
214@@ -1120,7 +1120,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
215 static void gem_write(void *opaque, hwaddr offset, uint64_t val,
216 unsigned size)
217 {
218- GemState *s = (GemState *)opaque;
219+ CadenceGEMState *s = (CadenceGEMState *)opaque;
220 uint32_t readonly;
221
222 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
223@@ -1226,7 +1226,7 @@ static NetClientInfo net_gem_info = {
224 static int gem_init(SysBusDevice *sbd)
225 {
226 DeviceState *dev = DEVICE(sbd);
227- GemState *s = GEM(dev);
228+ CadenceGEMState *s = CADENCE_GEM(dev);
229
230 DB_PRINT("\n");
231
232@@ -1248,18 +1248,18 @@ static const VMStateDescription vmstate_cadence_gem = {
233 .version_id = 2,
234 .minimum_version_id = 2,
235 .fields = (VMStateField[]) {
236- VMSTATE_UINT32_ARRAY(regs, GemState, GEM_MAXREG),
237- VMSTATE_UINT16_ARRAY(phy_regs, GemState, 32),
238- VMSTATE_UINT8(phy_loop, GemState),
239- VMSTATE_UINT32(rx_desc_addr, GemState),
240- VMSTATE_UINT32(tx_desc_addr, GemState),
241- VMSTATE_BOOL_ARRAY(sar_active, GemState, 4),
242+ VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
243+ VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32),
244+ VMSTATE_UINT8(phy_loop, CadenceGEMState),
245+ VMSTATE_UINT32(rx_desc_addr, CadenceGEMState),
246+ VMSTATE_UINT32(tx_desc_addr, CadenceGEMState),
247+ VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
248 VMSTATE_END_OF_LIST(),
249 }
250 };
251
252 static Property gem_properties[] = {
253- DEFINE_NIC_PROPERTIES(GemState, conf),
254+ DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
255 DEFINE_PROP_END_OF_LIST(),
256 };
257
258@@ -1277,7 +1277,7 @@ static void gem_class_init(ObjectClass *klass, void *data)
259 static const TypeInfo gem_info = {
260 .name = TYPE_CADENCE_GEM,
261 .parent = TYPE_SYS_BUS_DEVICE,
262- .instance_size = sizeof(GemState),
263+ .instance_size = sizeof(CadenceGEMState),
264 .class_init = gem_class_init,
265 };
266
267--
2681.7.10.4
269
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-06-08 11:25:52 +0000