1 files changed, 0 insertions, 56 deletions

diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0002-target-arm-cpu64-Add-support-for-cortex-a53.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0002-target-arm-cpu64-Add-support-for-cortex-a53.patch
deleted file mode 100644
index 290f2870..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0002-target-arm-cpu64-Add-support-for-cortex-a53.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From a69dfd5611a5671ff6163d3368d3628152251b04 Mon Sep 17 00:00:00 2001
-From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Mar 2015 04:05:11 -0700
-Subject: [PATCH 02/15] target-arm: cpu64: Add support for cortex-a53
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Similar to a53, but with different L1 I cache policy, phys addr size and
-different cache geometries. The cache sizes is implementation
-configurable, but use these values (from Xilinx MPSoC) as a default
-until cache size configurability is added.
-
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
----
- target-arm/cpu64.c |   16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
-diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
-index 3eb58c6..728d9a7 100644
---- a/target-arm/cpu64.c
-+++ b/target-arm/cpu64.c
-@@ -149,6 +149,21 @@ static void aarch64_a57_initfn(Object *obj)
-     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
- }
- 
-+static void aarch64_a53_initfn(Object *obj)
-+{
-+    ARMCPU *cpu = ARM_CPU(obj);
-+
-+    aarch64_axx_initfn(cpu);
-+
-+    cpu->dtb_compatible = "arm,cortex-a53";
-+    cpu->midr = 0x410fd034;
-+    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
-+    cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
-+    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
-+    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
-+    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
-+}
-+
- #ifdef CONFIG_USER_ONLY
- static void aarch64_any_initfn(Object *obj)
- {
-@@ -176,6 +191,7 @@ typedef struct ARMCPUInfo {
- 
- static const ARMCPUInfo aarch64_cpus[] = {
-     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
-+    { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
- #ifdef CONFIG_USER_ONLY
-     { .name = "any",         .initfn = aarch64_any_initfn },
- #endif
--- 
-1.7.10.4
-