1 files changed, 114 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot/u-boot-xlnx/microblaze_Fix_coding_style_for_bootb.patch b/recipes-bsp/u-boot/u-boot-xlnx/microblaze_Fix_coding_style_for_bootb.patch
new file mode 100644
index 00000000..09648c10
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot-xlnx/microblaze_Fix_coding_style_for_bootb.patch
@@ -0,0 +1,114 @@
+From: Michal Simek <michal.simek@xilinx.com>
+Subject: [U-BOOT PATCH 1/3] microblaze: Fix coding style for bootb
+Fix this weird untested code to be able to other changes.
+Signed-off-by: Michal Simek <michal.simek@xilinx.com>
+---
+ arch/microblaze/lib/bootm.c | 81 ++++++++++++++++++++++++---------------------
+ 1 file changed, 43 insertions(+), 38 deletions(-)
+diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
+index 7da683d..6c4fa60 100644
+--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
+@@ -91,52 +91,57 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
+ #if defined(CONFIG_CMD_BOOTB)
+ int do_bootb_kintex7(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+ {
+-       u32 FrameBuffer[8];
+-    u32 BootAddress = simple_strtoul(argv[1], NULL, 16);
+-       u32 Index = 0;
+-    u32 Count;
+-    
+-    if (argc < 2)
+       u32 framebuffer[8];
+       u32 bootaddress = simple_strtoul(argv[1], NULL, 16);
+       u32 index = 0;
+       u32 count;
+
+       if (argc < 2)
+               return -1;
+
+       if ((bootaddress < CONFIG_SYS_FLASH_BASE) ||
+           (bootaddress > (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)))
+                return -1;
+-    
+-    if ((BootAddress <  CONFIG_SYS_FLASH_BASE) || (BootAddress > (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)))
+-    {
+-        return -1;
+-    }
+ 
+-    /*
+       /*
+         * Create the data to be written to the ICAP.
+         */
+-       FrameBuffer[Index++] = XHI_DUMMY_PACKET;
+-       FrameBuffer[Index++] = XHI_SYNC_PACKET;
+-       FrameBuffer[Index++] = XHI_NOOP_PACKET;
+-    FrameBuffer[Index++] = 0x30020001;                        /* Type 1 write to WBSTAR */
+-    FrameBuffer[Index++] = BootAddress;
+-    FrameBuffer[Index++] = 0x30008001;                        /* Type 1 Write to CMD */
+-    FrameBuffer[Index++] = XHI_CMD_IPROG;
+-       FrameBuffer[Index++] = XHI_NOOP_PACKET;
+-
+-     /*
+-         * Fill the FIFO with as many words as it will take (or as many as we have to send).
+-         */
+-       while(Index > XHwIcap_GetWrFifoVacancy(HWICAP_BASEADDR));
+-       for (Count = 0; Count < Index; Count++)
+-    {
+-       XHwIcap_FifoWrite(HWICAP_BASEADDR, FrameBuffer[Count]);
+-       }
+-
+-    /*
+       framebuffer[index++] = XHI_DUMMY_PACKET;
+       framebuffer[index++] = XHI_SYNC_PACKET;
+       framebuffer[index++] = XHI_NOOP_PACKET;
+       framebuffer[index++] = 0x30020001; /* Type 1 write to WBSTAR */
+       framebuffer[index++] = bootaddress;
+       framebuffer[index++] = 0x30008001; /* Type 1 Write to CMD */
+       framebuffer[index++] = XHI_CMD_IPROG;
+       framebuffer[index++] = XHI_NOOP_PACKET;
+
+       /*
+        * Fill the FIFO with as many words as it will take
+        * (or as many as we have to send).
+        */
+       while (index > XHwIcap_GetWrFifoVacancy(HWICAP_BASEADDR))
+               ;
+       for (count = 0; count < index; count++)
+               XHwIcap_FifoWrite(HWICAP_BASEADDR, framebuffer[count]);
+
+
+       /*
+         * Start the transfer of the data from the FIFO to the ICAP device.
+         */
+        XHwIcap_StartConfig(HWICAP_BASEADDR);
+ 
+-       while ((XHwIcap_ReadReg(HWICAP_BASEADDR,XHI_CR_OFFSET)) & XHI_CR_WRITE_MASK);
+-    
+-       while (XHwIcap_IsDeviceBusy(HWICAP_BASEADDR) != 0);
+-       while (XHwIcap_ReadReg(HWICAP_BASEADDR, XHI_CR_OFFSET) & XHI_CR_WRITE_MASK);
+-    
+-    /* The code should never get here sice the FPGA should reset */
+-    return -1;
+       while ((XHwIcap_ReadReg(HWICAP_BASEADDR, XHI_CR_OFFSET)) &
+              XHI_CR_WRITE_MASK)
+               ;
+
+       while (XHwIcap_IsDeviceBusy(HWICAP_BASEADDR) != 0)
+               ;
+       while (XHwIcap_ReadReg(HWICAP_BASEADDR, XHI_CR_OFFSET) &
+              XHI_CR_WRITE_MASK)
+               ;
+
+       /* The code should never get here sice the FPGA should reset */
+       return -1;
+ }
+ 
+ U_BOOT_CMD(
+-- 
+1.8.2.1

diff --git a/recipes-bsp/u-boot/u-boot-xlnx/microblaze_Fix_coding_style_for_bootb.patch b/recipes-bsp/u-boot/u-boot-xlnx/microblaze_Fix_coding_style_for_bootb.patch new file mode 100644 index 00000000..09648c10 --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-xlnx/microblaze_Fix_coding_style_for_bootb.patch
@@ -0,0 +1,114 @@
	1	From: Michal Simek <michal.simek@xilinx.com>
	2	Subject: [U-BOOT PATCH 1/3] microblaze: Fix coding style for bootb
	3
	4	Fix this weird untested code to be able to other changes.
	5
	6	Signed-off-by: Michal Simek <michal.simek@xilinx.com>
	7	---
	8	arch/microblaze/lib/bootm.c \| 81 ++++++++++++++++++++++++---------------------
	9	1 file changed, 43 insertions(+), 38 deletions(-)
	10
	11	diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
	12	index 7da683d..6c4fa60 100644
	13	--- a/arch/microblaze/lib/bootm.c
	14	+++ b/arch/microblaze/lib/bootm.c
	15	@@ -91,52 +91,57 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
	16	#if defined(CONFIG_CMD_BOOTB)
	17	int do_bootb_kintex7(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	18	{
	19	- u32 FrameBuffer[8];
	20	- u32 BootAddress = simple_strtoul(argv[1], NULL, 16);
	21	- u32 Index = 0;
	22	- u32 Count;
	23	-
	24	- if (argc < 2)
	25	+ u32 framebuffer[8];
	26	+ u32 bootaddress = simple_strtoul(argv[1], NULL, 16);
	27	+ u32 index = 0;
	28	+ u32 count;
	29	+
	30	+ if (argc < 2)
	31	+ return -1;
	32	+
	33	+ if ((bootaddress < CONFIG_SYS_FLASH_BASE) \|\|
	34	+ (bootaddress > (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)))
	35	return -1;
	36	-
	37	- if ((BootAddress < CONFIG_SYS_FLASH_BASE) \|\| (BootAddress > (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)))
	38	- {
	39	- return -1;
	40	- }
	41
	42	- /*
	43	+ /*
	44	* Create the data to be written to the ICAP.
	45	*/
	46	- FrameBuffer[Index++] = XHI_DUMMY_PACKET;
	47	- FrameBuffer[Index++] = XHI_SYNC_PACKET;
	48	- FrameBuffer[Index++] = XHI_NOOP_PACKET;
	49	- FrameBuffer[Index++] = 0x30020001; /* Type 1 write to WBSTAR */
	50	- FrameBuffer[Index++] = BootAddress;
	51	- FrameBuffer[Index++] = 0x30008001; /* Type 1 Write to CMD */
	52	- FrameBuffer[Index++] = XHI_CMD_IPROG;
	53	- FrameBuffer[Index++] = XHI_NOOP_PACKET;
	54	-
	55	- /*
	56	- * Fill the FIFO with as many words as it will take (or as many as we have to send).
	57	- */
	58	- while(Index > XHwIcap_GetWrFifoVacancy(HWICAP_BASEADDR));
	59	- for (Count = 0; Count < Index; Count++)
	60	- {
	61	- XHwIcap_FifoWrite(HWICAP_BASEADDR, FrameBuffer[Count]);
	62	- }
	63	-
	64	- /*
	65	+ framebuffer[index++] = XHI_DUMMY_PACKET;
	66	+ framebuffer[index++] = XHI_SYNC_PACKET;
	67	+ framebuffer[index++] = XHI_NOOP_PACKET;
	68	+ framebuffer[index++] = 0x30020001; /* Type 1 write to WBSTAR */
	69	+ framebuffer[index++] = bootaddress;
	70	+ framebuffer[index++] = 0x30008001; /* Type 1 Write to CMD */
	71	+ framebuffer[index++] = XHI_CMD_IPROG;
	72	+ framebuffer[index++] = XHI_NOOP_PACKET;
	73	+
	74	+ /*
	75	+ * Fill the FIFO with as many words as it will take
	76	+ * (or as many as we have to send).
	77	+ */
	78	+ while (index > XHwIcap_GetWrFifoVacancy(HWICAP_BASEADDR))
	79	+ ;
	80	+ for (count = 0; count < index; count++)
	81	+ XHwIcap_FifoWrite(HWICAP_BASEADDR, framebuffer[count]);
	82	+
	83	+
	84	+ /*
	85	* Start the transfer of the data from the FIFO to the ICAP device.
	86	*/
	87	XHwIcap_StartConfig(HWICAP_BASEADDR);
	88
	89	- while ((XHwIcap_ReadReg(HWICAP_BASEADDR,XHI_CR_OFFSET)) & XHI_CR_WRITE_MASK);
	90	-
	91	- while (XHwIcap_IsDeviceBusy(HWICAP_BASEADDR) != 0);
	92	- while (XHwIcap_ReadReg(HWICAP_BASEADDR, XHI_CR_OFFSET) & XHI_CR_WRITE_MASK);
	93	-
	94	- /* The code should never get here sice the FPGA should reset */
	95	- return -1;
	96	+ while ((XHwIcap_ReadReg(HWICAP_BASEADDR, XHI_CR_OFFSET)) &
	97	+ XHI_CR_WRITE_MASK)
	98	+ ;
	99	+
	100	+ while (XHwIcap_IsDeviceBusy(HWICAP_BASEADDR) != 0)
	101	+ ;
	102	+ while (XHwIcap_ReadReg(HWICAP_BASEADDR, XHI_CR_OFFSET) &
	103	+ XHI_CR_WRITE_MASK)
	104	+ ;
	105	+
	106	+ /* The code should never get here sice the FPGA should reset */
	107	+ return -1;
	108	}
	109
	110	U_BOOT_CMD(
	111	--
	112	1.8.2.1
	113
	114