diff options
Diffstat (limited to 'meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch')
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch | 126 |
1 files changed, 126 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch new file mode 100644 index 00000000..02940e2f --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch | |||
@@ -0,0 +1,126 @@ | |||
1 | From 90b6f833bd59f89d4192a3dc787fc2c9115b9c00 Mon Sep 17 00:00:00 2001 | ||
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | ||
3 | Date: Sat, 26 Aug 2017 19:21:48 -0700 | ||
4 | Subject: [PATCH] Add new bit-field instructions | ||
5 | |||
6 | This patches adds new bsefi and bsifi instructions. BSEFI- The | ||
7 | instruction shall extract a bit field from a register and place it | ||
8 | right-adjusted in the destination register. The other bits in the | ||
9 | destination register shall be set to zero BSIFI- The instruction shall | ||
10 | insert a right-adjusted bit field from a register at another position in | ||
11 | the destination register. The rest of the bits in the destination | ||
12 | register shall be unchanged | ||
13 | |||
14 | ChangeLog: | ||
15 | |||
16 | 2016-02-03 Nagaraju Mekala <nagaraju.mekala@xilinx.com> | ||
17 | |||
18 | * microblaze.md (Update): Added new patterns | ||
19 | |||
20 | Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> | ||
21 | Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> | ||
22 | Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> | ||
23 | Upstream-Status: Pending | ||
24 | --- | ||
25 | gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++++++++++ | ||
26 | 1 file changed, 73 insertions(+) | ||
27 | |||
28 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | ||
29 | index 61d6412dac..7a00629922 100644 | ||
30 | --- a/gcc/config/microblaze/microblaze.md | ||
31 | +++ b/gcc/config/microblaze/microblaze.md | ||
32 | @@ -980,6 +980,8 @@ | ||
33 | (set_attr "mode" "DI") | ||
34 | (set_attr "length" "20,20,20")]) | ||
35 | |||
36 | + | ||
37 | + | ||
38 | ;;---------------------------------------------------------------- | ||
39 | ;; Data movement | ||
40 | ;;---------------------------------------------------------------- | ||
41 | @@ -1774,6 +1776,7 @@ | ||
42 | (set_attr "length" "28")] | ||
43 | ) | ||
44 | |||
45 | + | ||
46 | ;;---------------------------------------------------------------- | ||
47 | ;; Setting a register from an integer comparison. | ||
48 | ;;---------------------------------------------------------------- | ||
49 | @@ -2473,4 +2476,74 @@ | ||
50 | DONE; | ||
51 | }") | ||
52 | |||
53 | +(define_expand "extvsi" | ||
54 | + [(set (match_operand:SI 0 "register_operand" "r") | ||
55 | + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") | ||
56 | + (match_operand:SI 2 "immediate_operand" "I") | ||
57 | + (match_operand:SI 3 "immediate_operand" "I")))] | ||
58 | +"TARGET_HAS_BITFIELD" | ||
59 | +" | ||
60 | +{ | ||
61 | + unsigned HOST_WIDE_INT len = UINTVAL (operands[2]); | ||
62 | + unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]); | ||
63 | + | ||
64 | + if ((len == 0) || (pos + len > 32) ) | ||
65 | + FAIL; | ||
66 | + | ||
67 | + ;;if (!register_operand (operands[1], VOIDmode)) | ||
68 | + ;; FAIL; | ||
69 | + if (operands[0] == operands[1]) | ||
70 | + FAIL; | ||
71 | + if (GET_CODE (operands[1]) == ASHIFT) | ||
72 | + FAIL; | ||
73 | +;; operands[2] = GEN_INT(INTVAL(operands[2])+1 ); | ||
74 | + emit_insn (gen_extv_32 (operands[0], operands[1], | ||
75 | + operands[2], operands[3])); | ||
76 | + DONE; | ||
77 | +}") | ||
78 | + | ||
79 | +(define_insn "extv_32" | ||
80 | + [(set (match_operand:SI 0 "register_operand" "=r") | ||
81 | + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") | ||
82 | + (match_operand:SI 2 "immediate_operand" "I") | ||
83 | + (match_operand:SI 3 "immediate_operand" "I")))] | ||
84 | + "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0) | ||
85 | + && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)" | ||
86 | + "bsefi %0,%1,%2,%3" | ||
87 | + [(set_attr "type" "bshift") | ||
88 | + (set_attr "length" "4")]) | ||
89 | + | ||
90 | +(define_expand "insvsi" | ||
91 | + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") | ||
92 | + (match_operand:SI 1 "immediate_operand" "I") | ||
93 | + (match_operand:SI 2 "immediate_operand" "I")) | ||
94 | + (match_operand:SI 3 "register_operand" "r"))] | ||
95 | + "TARGET_HAS_BITFIELD" | ||
96 | + " | ||
97 | +{ | ||
98 | + unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); | ||
99 | + unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); | ||
100 | + | ||
101 | + if (len <= 0 || pos + len > 32) | ||
102 | + FAIL; | ||
103 | + | ||
104 | + ;;if (!register_operand (operands[0], VOIDmode)) | ||
105 | + ;; FAIL; | ||
106 | + | ||
107 | + emit_insn (gen_insv_32 (operands[0], operands[1], | ||
108 | + operands[2], operands[3])); | ||
109 | + DONE; | ||
110 | +}") | ||
111 | + | ||
112 | +(define_insn "insv_32" | ||
113 | + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") | ||
114 | + (match_operand:SI 1 "immediate_operand" "I") | ||
115 | + (match_operand:SI 2 "immediate_operand" "I")) | ||
116 | + (match_operand:SI 3 "register_operand" "r"))] | ||
117 | + "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0 | ||
118 | + && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32" | ||
119 | + "bsifi %0, %3, %1, %2" | ||
120 | + [(set_attr "type" "bshift") | ||
121 | + (set_attr "length" "4")]) | ||
122 | + | ||
123 | (include "sync.md") | ||
124 | -- | ||
125 | 2.14.2 | ||
126 | |||