diff options
Diffstat (limited to 'meta-microblaze/recipes-devtools/gcc/gcc/0024-Patch-microblaze-Add-new-bit-field-instructions.patch')
-rw-r--r-- | meta-microblaze/recipes-devtools/gcc/gcc/0024-Patch-microblaze-Add-new-bit-field-instructions.patch | 162 |
1 files changed, 162 insertions, 0 deletions
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc/0024-Patch-microblaze-Add-new-bit-field-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc/0024-Patch-microblaze-Add-new-bit-field-instructions.patch new file mode 100644 index 00000000..590cb38c --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc/0024-Patch-microblaze-Add-new-bit-field-instructions.patch | |||
@@ -0,0 +1,162 @@ | |||
1 | From 50f5f8341ba39f2e12eef4a149e59f71f032f7d3 Mon Sep 17 00:00:00 2001 | ||
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | ||
3 | Date: Tue, 10 Nov 2020 09:51:24 +0530 | ||
4 | Subject: [PATCH 24/54] [Patch, microblaze]: Add new bit-field instructions | ||
5 | |||
6 | This patches adds new bsefi and bsifi instructions. | ||
7 | BSEFI- The instruction shall extract a bit field from a | ||
8 | register and place it right-adjusted in the destination register. | ||
9 | The other bits in the destination register shall be set to zero | ||
10 | BSIFI- The instruction shall insert a right-adjusted bit field | ||
11 | from a register at another position in the destination register. | ||
12 | The rest of the bits in the destination register shall be unchanged | ||
13 | |||
14 | Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> | ||
15 | --- | ||
16 | gcc/config/microblaze/microblaze.c | 5 ++ | ||
17 | gcc/config/microblaze/microblaze.h | 2 + | ||
18 | gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++ | ||
19 | 3 files changed, 80 insertions(+) | ||
20 | |||
21 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | ||
22 | index 4710def18cf..14c652325a8 100644 | ||
23 | --- a/gcc/config/microblaze/microblaze.c | ||
24 | +++ b/gcc/config/microblaze/microblaze.c | ||
25 | @@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay; | ||
26 | /* Set to one if the targeted core has the CLZ insn. */ | ||
27 | int microblaze_has_clz = 0; | ||
28 | |||
29 | +/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */ | ||
30 | +int microblaze_has_bitfield = 0; | ||
31 | + | ||
32 | /* Which CPU pipeline do we use. We haven't really standardized on a CPU | ||
33 | version having only a particular type of pipeline. There can still be | ||
34 | options on the CPU to scale pipeline features up or down. :( | ||
35 | @@ -1850,6 +1853,8 @@ microblaze_option_override (void) | ||
36 | { | ||
37 | if (TARGET_AREA_OPTIMIZED_2) | ||
38 | microblaze_pipe = MICROBLAZE_PIPE_8; | ||
39 | + if (TARGET_BARREL_SHIFT) | ||
40 | + microblaze_has_bitfield = 1; | ||
41 | } | ||
42 | |||
43 | if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) | ||
44 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h | ||
45 | index 8a668278337..857cb1cd9d0 100644 | ||
46 | --- a/gcc/config/microblaze/microblaze.h | ||
47 | +++ b/gcc/config/microblaze/microblaze.h | ||
48 | @@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[]; | ||
49 | |||
50 | extern int microblaze_no_unsafe_delay; | ||
51 | extern int microblaze_has_clz; | ||
52 | +extern int microblaze_has_bitfield; | ||
53 | extern enum pipeline_type microblaze_pipe; | ||
54 | |||
55 | #define OBJECT_FORMAT_ELF | ||
56 | @@ -63,6 +64,7 @@ extern enum pipeline_type microblaze_pipe; | ||
57 | /* Do we have CLZ? */ | ||
58 | #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz) | ||
59 | |||
60 | +#define TARGET_HAS_BITFIELD (TARGET_BARREL_SHIFT && microblaze_has_bitfield) | ||
61 | /* The default is to support PIC. */ | ||
62 | #define TARGET_SUPPORTS_PIC 1 | ||
63 | |||
64 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | ||
65 | index c407a81c51e..3e6e2b9276d 100644 | ||
66 | --- a/gcc/config/microblaze/microblaze.md | ||
67 | +++ b/gcc/config/microblaze/microblaze.md | ||
68 | @@ -982,6 +982,8 @@ | ||
69 | (set_attr "mode" "DI") | ||
70 | (set_attr "length" "20,20,20")]) | ||
71 | |||
72 | + | ||
73 | + | ||
74 | ;;---------------------------------------------------------------- | ||
75 | ;; Data movement | ||
76 | ;;---------------------------------------------------------------- | ||
77 | @@ -1776,6 +1778,7 @@ | ||
78 | (set_attr "length" "28")] | ||
79 | ) | ||
80 | |||
81 | + | ||
82 | ;;---------------------------------------------------------------- | ||
83 | ;; Setting a register from an integer comparison. | ||
84 | ;;---------------------------------------------------------------- | ||
85 | @@ -2489,4 +2492,74 @@ | ||
86 | DONE; | ||
87 | }") | ||
88 | |||
89 | +(define_expand "extvsi" | ||
90 | + [(set (match_operand:SI 0 "register_operand" "r") | ||
91 | + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") | ||
92 | + (match_operand:SI 2 "immediate_operand" "I") | ||
93 | + (match_operand:SI 3 "immediate_operand" "I")))] | ||
94 | +"" | ||
95 | +" | ||
96 | +{ | ||
97 | + unsigned HOST_WIDE_INT len = UINTVAL (operands[2]); | ||
98 | + unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]); | ||
99 | + | ||
100 | + if ((len == 0) || (pos + len > 32) ) | ||
101 | + FAIL; | ||
102 | + | ||
103 | + ;;if (!register_operand (operands[1], VOIDmode)) | ||
104 | + ;; FAIL; | ||
105 | + if (operands[0] == operands[1]) | ||
106 | + FAIL; | ||
107 | + if (GET_CODE (operands[1]) == ASHIFT) | ||
108 | + FAIL; | ||
109 | +;; operands[2] = GEN_INT(INTVAL(operands[2])+1 ); | ||
110 | + emit_insn (gen_extv_32 (operands[0], operands[1], | ||
111 | + operands[2], operands[3])); | ||
112 | + DONE; | ||
113 | +}") | ||
114 | + | ||
115 | +(define_insn "extv_32" | ||
116 | + [(set (match_operand:SI 0 "register_operand" "=r") | ||
117 | + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") | ||
118 | + (match_operand:SI 2 "immediate_operand" "I") | ||
119 | + (match_operand:SI 3 "immediate_operand" "I")))] | ||
120 | + "TARGET_BARREL_SHIFT && (UINTVAL (operands[2]) > 0) | ||
121 | + && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)" | ||
122 | + "bsefi %0,%1,%2,%3" | ||
123 | + [(set_attr "type" "bshift") | ||
124 | + (set_attr "length" "4")]) | ||
125 | + | ||
126 | +(define_expand "insvsi" | ||
127 | + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") | ||
128 | + (match_operand:SI 1 "immediate_operand" "I") | ||
129 | + (match_operand:SI 2 "immediate_operand" "I")) | ||
130 | + (match_operand:SI 3 "register_operand" "r"))] | ||
131 | + "" | ||
132 | + " | ||
133 | +{ | ||
134 | + unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); | ||
135 | + unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); | ||
136 | + | ||
137 | + if (len <= 0 || pos + len > 32) | ||
138 | + FAIL; | ||
139 | + | ||
140 | + ;;if (!register_operand (operands[0], VOIDmode)) | ||
141 | + ;; FAIL; | ||
142 | + | ||
143 | + emit_insn (gen_insv_32 (operands[0], operands[1], | ||
144 | + operands[2], operands[3])); | ||
145 | + DONE; | ||
146 | +}") | ||
147 | + | ||
148 | +(define_insn "insv_32" | ||
149 | + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") | ||
150 | + (match_operand:SI 1 "immediate_operand" "I") | ||
151 | + (match_operand:SI 2 "immediate_operand" "I")) | ||
152 | + (match_operand:SI 3 "register_operand" "r"))] | ||
153 | + "TARGET_BARREL_SHIFT && UINTVAL (operands[1]) > 0 | ||
154 | + && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32" | ||
155 | + "bsifi %0, %3, %1, %2" | ||
156 | + [(set_attr "type" "bshift") | ||
157 | + (set_attr "length" "4")]) | ||
158 | + | ||
159 | (include "sync.md") | ||
160 | -- | ||
161 | 2.17.1 | ||
162 | |||