diff options
Diffstat (limited to 'meta-microblaze/recipes-devtools/gcc/gcc-10/0061-Author-Nagaraju-nmekala-xilinx.com.patch')
-rw-r--r-- | meta-microblaze/recipes-devtools/gcc/gcc-10/0061-Author-Nagaraju-nmekala-xilinx.com.patch | 479 |
1 files changed, 0 insertions, 479 deletions
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0061-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0061-Author-Nagaraju-nmekala-xilinx.com.patch deleted file mode 100644 index 690bc727..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0061-Author-Nagaraju-nmekala-xilinx.com.patch +++ /dev/null | |||
@@ -1,479 +0,0 @@ | |||
1 | From e1b8cfe6c0b4a0bd90ecbd3e85ae7114df21b6cc Mon Sep 17 00:00:00 2001 | ||
2 | From: Nagaraju <nmekala@xilinx.com> | ||
3 | Date: Thu, 18 Apr 2019 16:00:37 +0530 | ||
4 | Subject: [PATCH 61/62] Author: Nagaraju <nmekala@xilinx.com> Date: Wed Apr | ||
5 | 17 14:11:00 2019 +0530 | ||
6 | |||
7 | [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default | ||
8 | By default MB-64 is generatting barrel-shift instructions. It has been | ||
9 | removed from default. Barrel-shift instructions will be generated only if | ||
10 | barrel-shifter is enabled. Similarly to double instructions as well. | ||
11 | |||
12 | Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> | ||
13 | --- | ||
14 | gcc/config/microblaze/microblaze.c | 2 +- | ||
15 | gcc/config/microblaze/microblaze.md | 269 +++++++++++++++++++++++++++++++++--- | ||
16 | 2 files changed, 252 insertions(+), 19 deletions(-) | ||
17 | |||
18 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | ||
19 | index 33d183e..c321b03 100644 | ||
20 | --- a/gcc/config/microblaze/microblaze.c | ||
21 | +++ b/gcc/config/microblaze/microblaze.c | ||
22 | @@ -3868,7 +3868,7 @@ microblaze_expand_divide (rtx operands[]) | ||
23 | emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); | ||
24 | |||
25 | if (TARGET_MB_64) { | ||
26 | - emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); | ||
27 | + emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4))); | ||
28 | emit_insn (gen_adddi3 (regt1, regt1, operands[2])); | ||
29 | } | ||
30 | else { | ||
31 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | ||
32 | index 8bd175f..b5b60fb 100644 | ||
33 | --- a/gcc/config/microblaze/microblaze.md | ||
34 | +++ b/gcc/config/microblaze/microblaze.md | ||
35 | @@ -545,7 +545,7 @@ | ||
36 | [(set (match_operand:DF 0 "register_operand" "=d") | ||
37 | (plus:DF (match_operand:DF 1 "register_operand" "d") | ||
38 | (match_operand:DF 2 "register_operand" "d")))] | ||
39 | - "TARGET_MB_64" | ||
40 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
41 | "dadd\t%0,%1,%2" | ||
42 | [(set_attr "type" "fadd") | ||
43 | (set_attr "mode" "DF") | ||
44 | @@ -555,7 +555,7 @@ | ||
45 | [(set (match_operand:DF 0 "register_operand" "=d") | ||
46 | (minus:DF (match_operand:DF 1 "register_operand" "d") | ||
47 | (match_operand:DF 2 "register_operand" "d")))] | ||
48 | - "TARGET_MB_64" | ||
49 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
50 | "drsub\t%0,%2,%1" | ||
51 | [(set_attr "type" "frsub") | ||
52 | (set_attr "mode" "DF") | ||
53 | @@ -565,7 +565,7 @@ | ||
54 | [(set (match_operand:DF 0 "register_operand" "=d") | ||
55 | (mult:DF (match_operand:DF 1 "register_operand" "d") | ||
56 | (match_operand:DF 2 "register_operand" "d")))] | ||
57 | - "TARGET_MB_64" | ||
58 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
59 | "dmul\t%0,%1,%2" | ||
60 | [(set_attr "type" "fmul") | ||
61 | (set_attr "mode" "DF") | ||
62 | @@ -575,7 +575,7 @@ | ||
63 | [(set (match_operand:DF 0 "register_operand" "=d") | ||
64 | (div:DF (match_operand:DF 1 "register_operand" "d") | ||
65 | (match_operand:DF 2 "register_operand" "d")))] | ||
66 | - "TARGET_MB_64" | ||
67 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
68 | "ddiv\t%0,%2,%1" | ||
69 | [(set_attr "type" "fdiv") | ||
70 | (set_attr "mode" "DF") | ||
71 | @@ -585,7 +585,7 @@ | ||
72 | (define_insn "sqrtdf2" | ||
73 | [(set (match_operand:DF 0 "register_operand" "=d") | ||
74 | (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] | ||
75 | - "TARGET_MB_64" | ||
76 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
77 | "dsqrt\t%0,%1" | ||
78 | [(set_attr "type" "fsqrt") | ||
79 | (set_attr "mode" "DF") | ||
80 | @@ -594,7 +594,7 @@ | ||
81 | (define_insn "floatdidf2" | ||
82 | [(set (match_operand:DF 0 "register_operand" "=d") | ||
83 | (float:DF (match_operand:DI 1 "register_operand" "d")))] | ||
84 | - "TARGET_MB_64" | ||
85 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
86 | "dbl\t%0,%1" | ||
87 | [(set_attr "type" "fcvt") | ||
88 | (set_attr "mode" "DF") | ||
89 | @@ -603,7 +603,7 @@ | ||
90 | (define_insn "fix_truncdfdi2" | ||
91 | [(set (match_operand:DI 0 "register_operand" "=d") | ||
92 | (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] | ||
93 | - "TARGET_MB_64" | ||
94 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
95 | "dlong\t%0,%1" | ||
96 | [(set_attr "type" "fcvt") | ||
97 | (set_attr "mode" "DI") | ||
98 | @@ -1299,6 +1299,34 @@ | ||
99 | (set_attr "mode" "DI") | ||
100 | (set_attr "length" "4")]) | ||
101 | |||
102 | +(define_insn "*movdi_internal2_bshift" | ||
103 | + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") | ||
104 | + (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] | ||
105 | + "TARGET_MB_64 && TARGET_BARREL_SHIFT" | ||
106 | + { | ||
107 | + switch (which_alternative) | ||
108 | + { | ||
109 | + case 0: | ||
110 | + return "addlk\t%0,%1,r0"; | ||
111 | + case 1: | ||
112 | + case 2: | ||
113 | + if (GET_CODE (operands[1]) == CONST_INT && | ||
114 | + (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) | ||
115 | + return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; | ||
116 | + else | ||
117 | + return "addlik\t%0,r0,%1"; | ||
118 | + case 3: | ||
119 | + case 4: | ||
120 | + return "ll%i1\t%0,%1"; | ||
121 | + case 5: | ||
122 | + case 6: | ||
123 | + return "sl%i0\t%z1,%0"; | ||
124 | + } | ||
125 | + } | ||
126 | + [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") | ||
127 | + (set_attr "mode" "DI") | ||
128 | + (set_attr "length" "4,4,12,4,8,4,8")]) | ||
129 | + | ||
130 | (define_insn "*movdi_internal2" | ||
131 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") | ||
132 | (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] | ||
133 | @@ -1312,7 +1340,15 @@ | ||
134 | case 2: | ||
135 | if (GET_CODE (operands[1]) == CONST_INT && | ||
136 | (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) | ||
137 | - return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; | ||
138 | + { | ||
139 | + operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
140 | + output_asm_insn ("addlik\t%0,r0,%h1", operands); | ||
141 | + output_asm_insn ("addlik\t%2,r0,32", operands); | ||
142 | + output_asm_insn ("addlik\t%2,%2,-1", operands); | ||
143 | + output_asm_insn ("beaneid\t%2,.-8", operands); | ||
144 | + output_asm_insn ("addlk\t%0,%0,%0", operands); | ||
145 | + return "addlik\t%0,%0,%j1 #li => la"; | ||
146 | + } | ||
147 | else | ||
148 | return "addlik\t%0,r0,%1"; | ||
149 | case 3: | ||
150 | @@ -1386,7 +1422,7 @@ | ||
151 | (define_insn "movdi_long_int" | ||
152 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | ||
153 | (match_operand:DI 1 "general_operand" "i"))] | ||
154 | - "TARGET_MB_64" | ||
155 | + "TARGET_MB_64 && TARGET_BARREL_SHIFT" | ||
156 | "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; | ||
157 | [(set_attr "type" "no_delay_arith") | ||
158 | (set_attr "mode" "DI") | ||
159 | @@ -1653,6 +1689,33 @@ | ||
160 | ;; movdf_internal | ||
161 | ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT | ||
162 | ;; | ||
163 | +(define_insn "*movdf_internal_64_bshift" | ||
164 | + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") | ||
165 | + (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] | ||
166 | + "TARGET_MB_64 && TARGET_BARREL_SHIFT" | ||
167 | + { | ||
168 | + switch (which_alternative) | ||
169 | + { | ||
170 | + case 0: | ||
171 | + return "addlk\t%0,%1,r0"; | ||
172 | + case 1: | ||
173 | + return "addlk\t%0,r0,r0"; | ||
174 | + case 2: | ||
175 | + case 4: | ||
176 | + return "ll%i1\t%0,%1"; | ||
177 | + case 3: | ||
178 | + { | ||
179 | + return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; | ||
180 | + } | ||
181 | + case 5: | ||
182 | + return "sl%i0\t%1,%0"; | ||
183 | + } | ||
184 | + gcc_unreachable (); | ||
185 | + } | ||
186 | + [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") | ||
187 | + (set_attr "mode" "DF") | ||
188 | + (set_attr "length" "4,4,4,16,4,4")]) | ||
189 | + | ||
190 | (define_insn "*movdf_internal_64" | ||
191 | [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") | ||
192 | (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] | ||
193 | @@ -1669,7 +1732,13 @@ | ||
194 | return "ll%i1\t%0,%1"; | ||
195 | case 3: | ||
196 | { | ||
197 | - return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; | ||
198 | + operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
199 | + output_asm_insn ("addlik\t%0,r0,%h1", operands); | ||
200 | + output_asm_insn ("addlik\t%2,r0,32", operands); | ||
201 | + output_asm_insn ("addlik\t%2,%2,-1", operands); | ||
202 | + output_asm_insn ("beaneid\t%2,.-8", operands); | ||
203 | + output_asm_insn ("addlk\t%0,%0,%0", operands); | ||
204 | + return "addlik\t%0,%0,%j1 #li => la"; | ||
205 | } | ||
206 | case 5: | ||
207 | return "sl%i0\t%1,%0"; | ||
208 | @@ -1789,11 +1858,21 @@ | ||
209 | "TARGET_MB_64" | ||
210 | { | ||
211 | ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) | ||
212 | -if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) | ||
213 | +if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) | ||
214 | { | ||
215 | emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); | ||
216 | DONE; | ||
217 | } | ||
218 | +else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) | ||
219 | + { | ||
220 | + emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2])); | ||
221 | + DONE; | ||
222 | + } | ||
223 | +else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) | ||
224 | + { | ||
225 | + emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2])); | ||
226 | + DONE; | ||
227 | + } | ||
228 | else | ||
229 | FAIL; | ||
230 | } | ||
231 | @@ -1803,7 +1882,7 @@ else | ||
232 | [(set (match_operand:DI 0 "register_operand" "=d,d") | ||
233 | (ashift:DI (match_operand:DI 1 "register_operand" "d,d") | ||
234 | (match_operand:DI 2 "arith_operand" "I,d")))] | ||
235 | - "TARGET_MB_64" | ||
236 | + "TARGET_MB_64 && TARGET_BARREL_SHIFT" | ||
237 | "@ | ||
238 | bsllli\t%0,%1,%2 | ||
239 | bslll\t%0,%1,%2" | ||
240 | @@ -1811,6 +1890,51 @@ else | ||
241 | (set_attr "mode" "DI,DI") | ||
242 | (set_attr "length" "4,4")] | ||
243 | ) | ||
244 | + | ||
245 | +(define_insn "ashldi3_const" | ||
246 | + [(set (match_operand:DI 0 "register_operand" "=&d") | ||
247 | + (ashift:DI (match_operand:DI 1 "register_operand" "d") | ||
248 | + (match_operand:DI 2 "immediate_operand" "I")))] | ||
249 | + "TARGET_MB_64" | ||
250 | + { | ||
251 | + operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
252 | + | ||
253 | + output_asm_insn ("orli\t%3,r0,%2", operands); | ||
254 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
255 | + output_asm_insn ("addlk\t%0,%1,r0", operands); | ||
256 | + | ||
257 | + output_asm_insn ("addlik\t%3,%3,-1", operands); | ||
258 | + output_asm_insn ("beaneid\t%3,.-8", operands); | ||
259 | + return "addlk\t%0,%0,%0"; | ||
260 | + } | ||
261 | + [(set_attr "type" "multi") | ||
262 | + (set_attr "mode" "DI") | ||
263 | + (set_attr "length" "20")] | ||
264 | +) | ||
265 | + | ||
266 | +(define_insn "ashldi3_reg" | ||
267 | + [(set (match_operand:DI 0 "register_operand" "=&d") | ||
268 | + (ashift:DI (match_operand:DI 1 "register_operand" "d") | ||
269 | + (match_operand:DI 2 "register_operand" "d")))] | ||
270 | + "TARGET_MB_64" | ||
271 | + { | ||
272 | + operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
273 | + output_asm_insn ("andli\t%3,%2,31", operands); | ||
274 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
275 | + output_asm_insn ("addlk\t%0,r0,%1", operands); | ||
276 | + /* Exit the loop if zero shift. */ | ||
277 | + output_asm_insn ("beaeqid\t%3,.+24", operands); | ||
278 | + /* Emit the loop. */ | ||
279 | + output_asm_insn ("addlk\t%0,%0,r0", operands); | ||
280 | + output_asm_insn ("addlik\t%3,%3,-1", operands); | ||
281 | + output_asm_insn ("beaneid\t%3,.-8", operands); | ||
282 | + return "addlk\t%0,%0,%0"; | ||
283 | + } | ||
284 | + [(set_attr "type" "multi") | ||
285 | + (set_attr "mode" "DI") | ||
286 | + (set_attr "length" "28")] | ||
287 | +) | ||
288 | + | ||
289 | ;; The following patterns apply when there is no barrel shifter present | ||
290 | |||
291 | (define_insn "*ashlsi3_with_mul_delay" | ||
292 | @@ -1944,11 +2068,21 @@ else | ||
293 | "TARGET_MB_64" | ||
294 | { | ||
295 | ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) | ||
296 | -if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) | ||
297 | +if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) | ||
298 | { | ||
299 | emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); | ||
300 | DONE; | ||
301 | } | ||
302 | +else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) | ||
303 | + { | ||
304 | + emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2])); | ||
305 | + DONE; | ||
306 | + } | ||
307 | +else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) | ||
308 | + { | ||
309 | + emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2])); | ||
310 | + DONE; | ||
311 | + } | ||
312 | else | ||
313 | FAIL; | ||
314 | } | ||
315 | @@ -1958,7 +2092,7 @@ else | ||
316 | [(set (match_operand:DI 0 "register_operand" "=d,d") | ||
317 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | ||
318 | (match_operand:DI 2 "arith_operand" "I,d")))] | ||
319 | - "TARGET_MB_64" | ||
320 | + "TARGET_MB_64 && TARGET_BARREL_SHIFT" | ||
321 | "@ | ||
322 | bslrai\t%0,%1,%2 | ||
323 | bslra\t%0,%1,%2" | ||
324 | @@ -1966,6 +2100,51 @@ else | ||
325 | (set_attr "mode" "DI,DI") | ||
326 | (set_attr "length" "4,4")] | ||
327 | ) | ||
328 | + | ||
329 | +(define_insn "ashrdi3_const" | ||
330 | + [(set (match_operand:DI 0 "register_operand" "=&d") | ||
331 | + (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | ||
332 | + (match_operand:DI 2 "immediate_operand" "I")))] | ||
333 | + "TARGET_MB_64" | ||
334 | + { | ||
335 | + operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
336 | + | ||
337 | + output_asm_insn ("orli\t%3,r0,%2", operands); | ||
338 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
339 | + output_asm_insn ("addlk\t%0,%1,r0", operands); | ||
340 | + | ||
341 | + output_asm_insn ("addlik\t%3,%3,-1", operands); | ||
342 | + output_asm_insn ("beaneid\t%3,.-8", operands); | ||
343 | + return "srla\t%0,%0"; | ||
344 | + } | ||
345 | + [(set_attr "type" "arith") | ||
346 | + (set_attr "mode" "DI") | ||
347 | + (set_attr "length" "20")] | ||
348 | +) | ||
349 | + | ||
350 | +(define_insn "ashrdi3_reg" | ||
351 | + [(set (match_operand:DI 0 "register_operand" "=&d") | ||
352 | + (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | ||
353 | + (match_operand:DI 2 "register_operand" "d")))] | ||
354 | + "TARGET_MB_64" | ||
355 | + { | ||
356 | + operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
357 | + output_asm_insn ("andli\t%3,%2,31", operands); | ||
358 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
359 | + output_asm_insn ("addlk\t%0,r0,%1", operands); | ||
360 | + /* Exit the loop if zero shift. */ | ||
361 | + output_asm_insn ("beaeqid\t%3,.+24", operands); | ||
362 | + /* Emit the loop. */ | ||
363 | + output_asm_insn ("addlk\t%0,%0,r0", operands); | ||
364 | + output_asm_insn ("addlik\t%3,%3,-1", operands); | ||
365 | + output_asm_insn ("beaneid\t%3,.-8", operands); | ||
366 | + return "srla\t%0,%0"; | ||
367 | + } | ||
368 | + [(set_attr "type" "multi") | ||
369 | + (set_attr "mode" "DI") | ||
370 | + (set_attr "length" "28")] | ||
371 | +) | ||
372 | + | ||
373 | (define_expand "ashrsi3" | ||
374 | [(set (match_operand:SI 0 "register_operand" "=&d") | ||
375 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") | ||
376 | @@ -2083,11 +2262,21 @@ else | ||
377 | "TARGET_MB_64" | ||
378 | { | ||
379 | ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) | ||
380 | -if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) | ||
381 | +if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) | ||
382 | { | ||
383 | emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); | ||
384 | DONE; | ||
385 | } | ||
386 | +else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) | ||
387 | + { | ||
388 | + emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2])); | ||
389 | + DONE; | ||
390 | + } | ||
391 | +else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) | ||
392 | + { | ||
393 | + emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2])); | ||
394 | + DONE; | ||
395 | + } | ||
396 | else | ||
397 | FAIL; | ||
398 | } | ||
399 | @@ -2097,7 +2286,7 @@ else | ||
400 | [(set (match_operand:DI 0 "register_operand" "=d,d") | ||
401 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | ||
402 | (match_operand:DI 2 "arith_operand" "I,d")))] | ||
403 | - "TARGET_MB_64" | ||
404 | + "TARGET_MB_64 && TARGET_BARREL_SHIFT" | ||
405 | "@ | ||
406 | bslrli\t%0,%1,%2 | ||
407 | bslrl\t%0,%1,%2" | ||
408 | @@ -2106,6 +2295,50 @@ else | ||
409 | (set_attr "length" "4,4")] | ||
410 | ) | ||
411 | |||
412 | +(define_insn "lshrdi3_const" | ||
413 | + [(set (match_operand:DI 0 "register_operand" "=&d") | ||
414 | + (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | ||
415 | + (match_operand:DI 2 "immediate_operand" "I")))] | ||
416 | + "TARGET_MB_64" | ||
417 | + { | ||
418 | + operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
419 | + | ||
420 | + output_asm_insn ("orli\t%3,r0,%2", operands); | ||
421 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
422 | + output_asm_insn ("addlk\t%0,%1,r0", operands); | ||
423 | + | ||
424 | + output_asm_insn ("addlik\t%3,%3,-1", operands); | ||
425 | + output_asm_insn ("beaneid\t%3,.-8", operands); | ||
426 | + return "srll\t%0,%0"; | ||
427 | + } | ||
428 | + [(set_attr "type" "multi") | ||
429 | + (set_attr "mode" "DI") | ||
430 | + (set_attr "length" "20")] | ||
431 | +) | ||
432 | + | ||
433 | +(define_insn "lshrdi3_reg" | ||
434 | + [(set (match_operand:DI 0 "register_operand" "=&d") | ||
435 | + (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | ||
436 | + (match_operand:DI 2 "register_operand" "d")))] | ||
437 | + "TARGET_MB_64" | ||
438 | + { | ||
439 | + operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
440 | + output_asm_insn ("andli\t%3,%2,31", operands); | ||
441 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
442 | + output_asm_insn ("addlk\t%0,r0,%1", operands); | ||
443 | + /* Exit the loop if zero shift. */ | ||
444 | + output_asm_insn ("beaeqid\t%3,.+24", operands); | ||
445 | + /* Emit the loop. */ | ||
446 | + output_asm_insn ("addlk\t%0,%0,r0", operands); | ||
447 | + output_asm_insn ("addlik\t%3,%3,-1", operands); | ||
448 | + output_asm_insn ("beaneid\t%3,.-8", operands); | ||
449 | + return "srll\t%0,%0"; | ||
450 | + } | ||
451 | + [(set_attr "type" "multi") | ||
452 | + (set_attr "mode" "SI") | ||
453 | + (set_attr "length" "28")] | ||
454 | +) | ||
455 | + | ||
456 | (define_expand "lshrsi3" | ||
457 | [(set (match_operand:SI 0 "register_operand" "=&d") | ||
458 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") | ||
459 | @@ -2233,7 +2466,7 @@ else | ||
460 | (eq:DI | ||
461 | (match_operand:DI 1 "register_operand" "d") | ||
462 | (match_operand:DI 2 "register_operand" "d")))] | ||
463 | - "TARGET_MB_64" | ||
464 | + "TARGET_MB_64 && TARGET_PATTERN_COMPARE" | ||
465 | "pcmpleq\t%0,%1,%2" | ||
466 | [(set_attr "type" "arith") | ||
467 | (set_attr "mode" "DI") | ||
468 | @@ -2245,7 +2478,7 @@ else | ||
469 | (ne:DI | ||
470 | (match_operand:DI 1 "register_operand" "d") | ||
471 | (match_operand:DI 2 "register_operand" "d")))] | ||
472 | - "TARGET_MB_64" | ||
473 | + "TARGET_MB_64 && TARGET_PATTERN_COMPARE" | ||
474 | "pcmplne\t%0,%1,%2" | ||
475 | [(set_attr "type" "arith") | ||
476 | (set_attr "mode" "DI") | ||
477 | -- | ||
478 | 2.7.4 | ||
479 | |||