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authorSai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>2020-06-05 10:27:02 -0700
committerSai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>2020-08-11 23:47:26 -0700
commit034a12cf2ab08a0a9e724ba644667c82556ff09a (patch)
treeeaedda6f78f8bb94e40149cba8ef022d087377be /meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10
parent1c4692b7e478de2f75541fe26ed7d019e24c889b (diff)
downloadmeta-xilinx-034a12cf2ab08a0a9e724ba644667c82556ff09a.tar.gz
gcc-9*: Upgrade gcc from 9.2->10.1
Upgrade microblaze recipes to use gcc-10 instead of gcc-9. This patch only ensures the builds are not broken It doesnt validate the gcc-microblaze functionality Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
Diffstat (limited to 'meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10')
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch35
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch31
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch119
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch35
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch35
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch118
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch43
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch67
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch28
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-side-effects.patch68
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch40
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch33
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch48
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch41
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch26
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0015-Patch-microblaze-Disable-fivopts-by-default.patch42
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0016-Patch-microblaze-Removed-moddi3-routinue.patch160
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch101
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0018-Patch-microblaze-Add-optimized-lshrsi3.patch81
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0019-Patch-microblaze-Modified-trap-instruction.patch29
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch206
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0021-Patch-microblaze-Add-cbranchsi4_reg.patch159
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch58
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch47
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch63
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch72
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch193
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch142
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch69
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch36
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch45
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0031-Patch-microblaze-Add-new-bit-field-instructions.patch120
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch247
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0033-Fixing-the-bug-in-the-bit-field-instruction.patch48
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch32
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0035-Fixing-the-issue-with-the-builtin_alloc.patch44
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch49
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch80
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch38
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0039-Intial-commit-of-64-bit-Microblaze.patch804
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch83
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0041-Intial-commit-for-64bit-MB-sources.patch2463
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0042-re-arrangement-of-the-compare-branches.patch268
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch28
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch73
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0045-Fixed-issues-like.patch70
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0046-Fixed-below-issues.patch307
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0047-Added-double-arith-instructions.patch135
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch37
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch256
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch25
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0051-fixing-the-typo-errors-in-umodsi3-file.patch29
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch68
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch25
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch29
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch59
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0055-microblaze_linker_script_xilinx_ld.patch16
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch47
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-fix-the-lto-wrapper-issue-on-windows.patch36
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch47
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch87
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch87
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch51
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch466
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch51
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Author-Nagaraju-nmekala-xilinx.com.patch479
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch466
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Author-Nagaraju-nmekala-xilinx.com.patch479
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch41
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch107
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch41
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch44
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0064-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch77
73 files changed, 10309 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
new file mode 100644
index 00000000..28247daa
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
@@ -0,0 +1,35 @@
1From 23e6126392ab228c1d6483c02ffc32b15f00777e Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 11 Jan 2017 13:13:57 +0530
4Subject: [PATCH 01/63] LOCAL]: Testsuite - builtins tests require fpic
5 Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
6
7Conflicts:
8
9 gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
10---
11 gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 8 ++++++++
12 1 file changed, 8 insertions(+)
13
14diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
15index acb9eac..363ce07 100644
16--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
17+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
18@@ -48,6 +48,14 @@ if { [istarget *-*-eabi*]
19 lappend additional_flags "-Wl,--allow-multiple-definition"
20 }
21
22+<<<<<<< HEAD
23+=======
24+if [istarget "microblaze*-*-linux*"] {
25+ lappend additional_flags "-Wl,-zmuldefs"
26+ lappend additional_flags "-fPIC"
27+}
28+
29+>>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic
30 foreach src [lsort [find $srcdir/$subdir *.c]] {
31 if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
32 c-torture-execute [list $src \
33--
342.7.4
35
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
new file mode 100644
index 00000000..8e4a2a32
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
@@ -0,0 +1,31 @@
1From e9c8884f473eae307945ceabaa1ff03278236c23 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 11 Jan 2017 14:31:10 +0530
4Subject: [PATCH 02/63] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This
5 particular testcase fails with a timeout. Instead, fail it at compile-time
6 for microblaze. This speeds up the testsuite without removing it from the
7 FAIL reports.
8
9Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
10---
11 gcc/testsuite/g++.dg/opt/memcpy1.C | 4 ++++
12 1 file changed, 4 insertions(+)
13
14diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C
15index 3862756..db9f990 100644
16--- a/gcc/testsuite/g++.dg/opt/memcpy1.C
17+++ b/gcc/testsuite/g++.dg/opt/memcpy1.C
18@@ -4,6 +4,10 @@
19 // { dg-do compile }
20 // { dg-options "-O" }
21
22+#if defined (__MICROBLAZE__)
23+#error "too slow on mb. Investigate."
24+#endif
25+
26 typedef unsigned char uint8_t;
27 typedef uint8_t uint8;
28 __extension__ typedef __SIZE_TYPE__ size_t;
29--
302.7.4
31
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
new file mode 100644
index 00000000..ef994457
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
@@ -0,0 +1,119 @@
1From fb4b4d4ecba04859d52a653d7c453df92014dc38 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 11 Jan 2017 15:28:38 +0530
4Subject: [PATCH 03/63] [LOCAL]: Testsuite - explicitly add -fivopts for tests
5 that depend on it (test gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt.c doesnt
6 exist in 4.6 branch)
7
8Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
9
10Conflicts:
11 gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
12---
13 gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C | 2 +-
14 gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C | 2 +-
15 gcc/testsuite/gcc.dg/tree-ssa/loop-2.c | 2 +-
16 gcc/testsuite/gcc.dg/tree-ssa/loop-4.c | 2 +-
17 gcc/testsuite/gcc.dg/tree-ssa/loop-5.c | 2 +-
18 gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c | 2 +-
19 gcc/testsuite/gcc.dg/tree-ssa/pr19590.c | 2 +-
20 gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +-
21 8 files changed, 8 insertions(+), 8 deletions(-)
22
23diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
24index 438db88..ede883e 100644
25--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
26+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
27@@ -1,5 +1,5 @@
28 /* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */
29-/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
30+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */
31
32 void test (int *b, int *e, int stride)
33 {
34diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
35index 07ff1b7..a09710c 100644
36--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
37+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
38@@ -1,5 +1,5 @@
39 // { dg-do compile }
40-// { dg-options "-O2 -fdump-tree-ivopts-details" }
41+// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" }
42
43 class MinimalVec3
44 {
45diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
46index bda2516..22c8a5d 100644
47--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
48+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
49@@ -1,7 +1,7 @@
50 /* A test for strength reduction and induction variable elimination. */
51
52 /* { dg-do compile } */
53-/* { dg-options "-O1 -fdump-tree-optimized" } */
54+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
55 /* { dg-require-effective-target size32plus } */
56
57 /* Size of this structure should be sufficiently weird so that no memory
58diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
59index f0770ab..65d74c8 100644
60--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
61+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
62@@ -1,7 +1,7 @@
63 /* A test for strength reduction and induction variable elimination. */
64
65 /* { dg-do compile } */
66-/* { dg-options "-O1 -fdump-tree-optimized" } */
67+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
68 /* { dg-require-effective-target size32plus } */
69
70 /* Size of this structure should be sufficiently weird so that no memory
71diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
72index 5f42857..9bc86ee 100644
73--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
74+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
75@@ -1,7 +1,7 @@
76 /* A test for induction variable merging. */
77
78 /* { dg-do compile } */
79-/* { dg-options "-O1 -fdump-tree-optimized" } */
80+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
81
82 void foo(long);
83
84diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
85index 50d86a0..1e3eacd 100644
86--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
87+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
88@@ -1,5 +1,5 @@
89 /* { dg-do compile } */
90-/* { dg-options "-O2 -fopt-info-loop-missed" } */
91+/* { dg-options "-O2 -fivopts -fopt-info-loop-missed" } */
92 extern void g(void);
93
94 void
95diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
96index 2c6cfc6..648e6e6 100644
97--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
98+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
99@@ -1,5 +1,5 @@
100 /* { dg-do compile } */
101-/* { dg-options "-O2 -fdump-tree-ivopts" } */
102+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */
103
104 void vnum_test8(int *data)
105 {
106diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
107index e911bfc..5d3e7e0 100644
108--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
109+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
110@@ -1,5 +1,5 @@
111 /* { dg-do compile } */
112-/* { dg-options "-Os -fdump-tree-optimized" } */
113+/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */
114
115 /* Slightly changed testcase from PR middle-end/40815. */
116 void bar(char*, char*, int);
117--
1182.7.4
119
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
new file mode 100644
index 00000000..a575b518
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
@@ -0,0 +1,35 @@
1From 38022a87b01cf2e36b605d4f6d0faab22a0d2f44 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 11 Jan 2017 15:46:28 +0530
4Subject: [PATCH 04/63] [LOCAL]: For dejagnu static testing on qemu, suppress
5 warnings about multiple definitions from the test function and libc in line
6 with method used by powerpc. Dynamic linking and using a qemu binary which
7 understands sysroot resolves all test failures with builtins
8
9Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
10---
11 gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ----
12 1 file changed, 4 deletions(-)
13
14diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
15index 363ce07..56b1a9a 100644
16--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
17+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
18@@ -48,14 +48,10 @@ if { [istarget *-*-eabi*]
19 lappend additional_flags "-Wl,--allow-multiple-definition"
20 }
21
22-<<<<<<< HEAD
23-=======
24 if [istarget "microblaze*-*-linux*"] {
25 lappend additional_flags "-Wl,-zmuldefs"
26- lappend additional_flags "-fPIC"
27 }
28
29->>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic
30 foreach src [lsort [find $srcdir/$subdir *.c]] {
31 if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
32 c-torture-execute [list $src \
33--
342.7.4
35
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
new file mode 100644
index 00000000..18fd6dec
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
@@ -0,0 +1,35 @@
1From a7dfb5f158f16f88b30aabe903c4fb088889eeef Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 11 Jan 2017 15:50:35 +0530
4Subject: [PATCH 05/63] [Patch, testsuite]: Add MicroBlaze to target-supports
5 for atomic buil. .tin tests
6
7MicroBlaze added to supported targets for atomic builtin tests.
8
9Changelog/testsuite
10
112014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
12
13 * gcc/testsuite/lib/target-supports.exp: Add microblaze to
14 check_effective_target_sync_int_long.
15
16Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
17---
18 gcc/testsuite/lib/target-supports.exp | 1 +
19 1 file changed, 1 insertion(+)
20
21diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
22index cda0f3d..0a69659e 100644
23--- a/gcc/testsuite/lib/target-supports.exp
24+++ b/gcc/testsuite/lib/target-supports.exp
25@@ -6829,6 +6829,7 @@ proc check_effective_target_sync_int_long { } {
26 && [check_effective_target_arm_acq_rel])
27 || [istarget bfin*-*linux*]
28 || [istarget hppa*-*linux*]
29+ || [istarget microblaze*-*linux*]
30 || [istarget s390*-*-*]
31 || [istarget powerpc*-*-*]
32 || [istarget crisv32-*-*] || [istarget cris-*-*]
33--
342.7.4
35
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
new file mode 100644
index 00000000..b428d121
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
@@ -0,0 +1,118 @@
1From 7f0a129701ce9809d79ea4618f3293062bd24bbf Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:18 -0700
4Subject: [PATCH] Testsuite - explicitly add -fivopts for tests that depend on
5 it
6
7Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
8Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
9Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
10Upstream-Status: Pending
11---
12 gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C | 2 +-
13 gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C | 2 +-
14 gcc/testsuite/gcc.dg/tree-ssa/loop-2.c | 2 +-
15 gcc/testsuite/gcc.dg/tree-ssa/loop-4.c | 2 +-
16 gcc/testsuite/gcc.dg/tree-ssa/loop-5.c | 2 +-
17 gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c | 2 +-
18 gcc/testsuite/gcc.dg/tree-ssa/pr19590.c | 2 +-
19 gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +-
20 8 files changed, 8 insertions(+), 8 deletions(-)
21
22diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
23index 438db88204..ede883eb28 100644
24--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
25+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
26@@ -1,5 +1,5 @@
27 /* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */
28-/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
29+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */
30
31 void test (int *b, int *e, int stride)
32 {
33diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
34index eb72581390..02f3ea4a7d 100644
35--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
36+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
37@@ -1,5 +1,5 @@
38 // { dg-do compile }
39-// { dg-options "-O2 -fdump-tree-ivopts-details" }
40+// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" }
41
42 class MinimalVec3
43 {
44diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
45index bda2516735..22c8a5dcff 100644
46--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
47+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
48@@ -1,7 +1,7 @@
49 /* A test for strength reduction and induction variable elimination. */
50
51 /* { dg-do compile } */
52-/* { dg-options "-O1 -fdump-tree-optimized" } */
53+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
54 /* { dg-require-effective-target size32plus } */
55
56 /* Size of this structure should be sufficiently weird so that no memory
57diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
58index f0770abdbb..65d74c8e62 100644
59--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
60+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
61@@ -1,7 +1,7 @@
62 /* A test for strength reduction and induction variable elimination. */
63
64 /* { dg-do compile } */
65-/* { dg-options "-O1 -fdump-tree-optimized" } */
66+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
67 /* { dg-require-effective-target size32plus } */
68
69 /* Size of this structure should be sufficiently weird so that no memory
70diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
71index 5f42857fe1..9bc86ee0d2 100644
72--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
73+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
74@@ -1,7 +1,7 @@
75 /* A test for induction variable merging. */
76
77 /* { dg-do compile } */
78-/* { dg-options "-O1 -fdump-tree-optimized" } */
79+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
80
81 void foo(long);
82
83diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
84index 3c8ee06016..db192a657f 100644
85--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
86+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
87@@ -1,5 +1,5 @@
88 /* { dg-do compile } */
89-/* { dg-options "-O2 -Wunsafe-loop-optimizations" } */
90+/* { dg-options "-O2 -fivopts -Wunsafe-loop-optimizations" } */
91 extern void g(void);
92
93 void
94diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
95index 2c6cfc6f83..648e6e67e8 100644
96--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
97+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
98@@ -1,5 +1,5 @@
99 /* { dg-do compile } */
100-/* { dg-options "-O2 -fdump-tree-ivopts" } */
101+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */
102
103 void vnum_test8(int *data)
104 {
105diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
106index e911bfcd52..5d3e7e0801 100644
107--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
108+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
109@@ -1,5 +1,5 @@
110 /* { dg-do compile } */
111-/* { dg-options "-Os -fdump-tree-optimized" } */
112+/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */
113
114 /* Slightly changed testcase from PR middle-end/40815. */
115 void bar(char*, char*, int);
116--
1172.14.2
118
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
new file mode 100644
index 00000000..e4a86dc4
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
@@ -0,0 +1,43 @@
1From e23b1a424cfd852f7a33f29c0b80d867ca533c3b Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 11 Jan 2017 16:20:01 +0530
4Subject: [PATCH 06/63] [Patch, testsuite]: Update MicroBlaze strings test for
5 new scan-assembly output resulting in use of $LC label
6
7ChangeLog/testsuite
8
92014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
10
11 * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update
12 to include $LC label.
13
14Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
15---
16 gcc/testsuite/gcc.target/microblaze/others/strings1.c | 6 ++++--
17 1 file changed, 4 insertions(+), 2 deletions(-)
18
19diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
20index 7a63faf..0403b7b 100644
21--- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c
22+++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
23@@ -1,13 +1,15 @@
24 /* { dg-options "-O3" } */
25
26+/* { dg-final { scan-assembler "\.rodata*" } } */
27+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */
28+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */
29+
30 #include <string.h>
31
32-/* { dg-final { scan-assembler "\.rodata*" } } */
33 extern void somefunc (char *);
34 int testfunc ()
35 {
36 char string2[80];
37-/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,.LC*" } } */
38 strcpy (string2, "hello");
39 somefunc (string2);
40 }
41--
422.7.4
43
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
new file mode 100644
index 00000000..8c43de05
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
@@ -0,0 +1,67 @@
1From c210044f15df2433438b6b74e5c2bcf79458c2e4 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 16:14:15 +0530
4Subject: [PATCH 07/63] [Patch, testsuite]: Allow MicroBlaze .weakext pattern
5 in regex match Extend regex pattern to include optional ext at the end of
6 .weak to match the MicroBlaze weak label .weakext
7
8ChangeLog/testsuite
9
102014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
11
12 * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler
13 pattern to take optional ext after .weak.
14 * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise.
15
16Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
17
18Conflicts:
19
20 gcc/testsuite/g++.dg/abi/rtti3.C
21---
22 gcc/testsuite/g++.dg/abi/rtti3.C | 4 ++--
23 gcc/testsuite/g++.dg/abi/thunk3.C | 2 +-
24 gcc/testsuite/g++.dg/abi/thunk4.C | 2 +-
25 3 files changed, 4 insertions(+), 4 deletions(-)
26
27diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C
28index 0cc7d3e..f284cd9 100644
29--- a/gcc/testsuite/g++.dg/abi/rtti3.C
30+++ b/gcc/testsuite/g++.dg/abi/rtti3.C
31@@ -3,8 +3,8 @@
32
33 // { dg-require-weak "" }
34 // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } }
35-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } }
36-// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
37+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } }
38+// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
39 // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } }
40 // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } }
41
42diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C
43index f2347f7..dcec8a7 100644
44--- a/gcc/testsuite/g++.dg/abi/thunk3.C
45+++ b/gcc/testsuite/g++.dg/abi/thunk3.C
46@@ -1,5 +1,5 @@
47 // { dg-require-weak "" }
48-// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
49+// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
50 // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
51
52 struct Base
53diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C
54index 6e8f124..d1d34fe 100644
55--- a/gcc/testsuite/g++.dg/abi/thunk4.C
56+++ b/gcc/testsuite/g++.dg/abi/thunk4.C
57@@ -1,6 +1,6 @@
58 // { dg-require-weak "" }
59 // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } }
60-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
61+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
62 // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
63
64 struct Base
65--
662.7.4
67
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
new file mode 100644
index 00000000..d02be316
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
@@ -0,0 +1,28 @@
1From 283d8576d2599b3c38814e7c70e3f36ed51df9da Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 16:34:27 +0530
4Subject: [PATCH 08/63] [Patch, testsuite]: Add MicroBlaze to
5 check_profiling_available Testsuite, add microblaze*-*-* target in
6 check_profiling_available inline with other archs setting
7 profiling_available_saved to 0
8
9Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
10---
11 gcc/testsuite/lib/target-supports.exp | 1 +
12 1 file changed, 1 insertion(+)
13
14diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
15index 0a69659e..d47819c 100644
16--- a/gcc/testsuite/lib/target-supports.exp
17+++ b/gcc/testsuite/lib/target-supports.exp
18@@ -678,6 +678,7 @@ proc check_profiling_available { test_what } {
19 || [istarget m68k-*-elf]
20 || [istarget m68k-*-uclinux*]
21 || [istarget mips*-*-elf*]
22+ || [istarget microblaze*-*-*]
23 || [istarget mmix-*-*]
24 || [istarget mn10300-*-elf*]
25 || [istarget moxie-*-elf*]
26--
272.7.4
28
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-side-effects.patch
new file mode 100644
index 00000000..ae24c080
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-side-effects.patch
@@ -0,0 +1,68 @@
1From 1905061b279e6fe5fd9861fc490fd4075edac4a8 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 16:41:43 +0530
4Subject: [PATCH 09/63] [Patch, microblaze]: Fix atomic side effects. In
5 atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions
6 during optimization. Previously, the outputs were considered unused; this
7 generated assembly code with undefined side effects after invocation of the
8 atomic.
9
10Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
11Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
12
13Conflicts:
14 gcc/config/microblaze/microblaze.md
15---
16 gcc/config/microblaze/microblaze.md | 3 +++
17 gcc/config/microblaze/sync.md | 21 +++++++++++++--------
18 2 files changed, 16 insertions(+), 8 deletions(-)
19
20diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
21index 183afff..7a40c53 100644
22--- a/gcc/config/microblaze/microblaze.md
23+++ b/gcc/config/microblaze/microblaze.md
24@@ -43,6 +43,9 @@
25 (UNSPEC_TLS 106) ;; jump table
26 (UNSPEC_SET_TEXT 107) ;; set text start
27 (UNSPEC_TEXT 108) ;; data text relative
28+ (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool)
29+ (UNSPECV_CAS_VAL 202) ;; compare and swap (val)
30+ (UNSPECV_CAS_MEM 203) ;; compare and swap (mem)
31 ])
32
33 (define_c_enum "unspec" [
34diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
35index 6f16ca6..bebab5c 100644
36--- a/gcc/config/microblaze/sync.md
37+++ b/gcc/config/microblaze/sync.md
38@@ -18,14 +18,19 @@
39 ;; <http://www.gnu.org/licenses/>.
40
41 (define_insn "atomic_compare_and_swapsi"
42- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output
43- (match_operand:SI 1 "register_operand" "=&d") ;; val output
44- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
45- (match_operand:SI 3 "register_operand" "d") ;; expected value
46- (match_operand:SI 4 "register_operand" "d") ;; desired value
47- (match_operand:SI 5 "const_int_operand" "") ;; is_weak
48- (match_operand:SI 6 "const_int_operand" "") ;; mod_s
49- (match_operand:SI 7 "const_int_operand" "") ;; mod_f
50+ [(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output
51+ (unspec_volatile:SI
52+ [(match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
53+ (match_operand:SI 3 "register_operand" "d") ;; expected value
54+ (match_operand:SI 4 "register_operand" "d")] ;; desired value
55+ UNSPECV_CAS_BOOL))
56+ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output
57+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL))
58+ (set (match_dup 2)
59+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM))
60+ (match_operand:SI 5 "const_int_operand" "") ;; is_weak
61+ (match_operand:SI 6 "const_int_operand" "") ;; mod_s
62+ (match_operand:SI 7 "const_int_operand" "") ;; mod_f
63 (clobber (match_scratch:SI 8 "=&d"))]
64 ""
65 {
66--
672.7.4
68
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
new file mode 100644
index 00000000..07a43177
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
@@ -0,0 +1,40 @@
1From 65bc1969bd652df4bf9d01d30547a947da293550 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 16:45:45 +0530
4Subject: [PATCH 10/63] [Patch, microblaze]: Fix atomic boolean return value.
5 In atomic_compare_and_swapsi, fix boolean return value. Previously, it
6 contained zero if successful and non-zero if unsuccessful.
7
8Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
9Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
10---
11 gcc/config/microblaze/sync.md | 7 ++++---
12 1 file changed, 4 insertions(+), 3 deletions(-)
13
14diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
15index bebab5c..72eac09 100644
16--- a/gcc/config/microblaze/sync.md
17+++ b/gcc/config/microblaze/sync.md
18@@ -34,15 +34,16 @@
19 (clobber (match_scratch:SI 8 "=&d"))]
20 ""
21 {
22- output_asm_insn ("addc \tr0,r0,r0", operands);
23+ output_asm_insn ("add \t%0,r0,r0", operands);
24 output_asm_insn ("lwx \t%1,%y2,r0", operands);
25 output_asm_insn ("addic\t%8,r0,0", operands);
26 output_asm_insn ("bnei \t%8,.-8", operands);
27- output_asm_insn ("cmp \t%0,%1,%3", operands);
28- output_asm_insn ("bnei \t%0,.+16", operands);
29+ output_asm_insn ("cmp \t%8,%1,%3", operands);
30+ output_asm_insn ("bnei \t%8,.+20", operands);
31 output_asm_insn ("swx \t%4,%y2,r0", operands);
32 output_asm_insn ("addic\t%8,r0,0", operands);
33 output_asm_insn ("bnei \t%8,.-28", operands);
34+ output_asm_insn ("addi \t%0,r0,1", operands);
35 return "";
36 }
37 )
38--
392.7.4
40
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
new file mode 100644
index 00000000..b9ba239f
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
@@ -0,0 +1,33 @@
1From 4e4409f10b450ec9254e69445ffeb8d116906d16 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 16:50:17 +0530
4Subject: [PATCH 11/63] [Patch, microblaze]: Fix the Microblaze crash with
5 msmall-divides flag Compiler is crashing when we use msmall-divides and
6 mxl-barrel-shift flag. This is because when use above flags
7 microblaze_expand_divide function will be called for division operation. In
8 microblaze_expand_divide function we are using sub_reg but MicroBlaze doesn't
9 have subreg register due to this compiler was crashing. Changed the logic to
10 avoid sub_reg call
11
12Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
13---
14 gcc/config/microblaze/microblaze.c | 3 +--
15 1 file changed, 1 insertion(+), 2 deletions(-)
16
17diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
18index 55c1bec..ae45038 100644
19--- a/gcc/config/microblaze/microblaze.c
20+++ b/gcc/config/microblaze/microblaze.c
21@@ -3715,8 +3715,7 @@ microblaze_expand_divide (rtx operands[])
22 mem_rtx = gen_rtx_MEM (QImode,
23 gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
24
25- insn = emit_insn (gen_movqi (regqi, mem_rtx));
26- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0)));
27+ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
28 jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
29 JUMP_LABEL (jump) = div_end_label;
30 LABEL_NUSES (div_end_label) = 1;
31--
322.7.4
33
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
new file mode 100644
index 00000000..fc47bae6
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
@@ -0,0 +1,48 @@
1From 6dbeb53f0185dd587ece39d624d193768633a7ab Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 16:52:56 +0530
4Subject: [PATCH 12/63] [Patch, microblaze]: Added ashrsi3_with_size_opt Added
5 ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os
6 optimization is used. lshrsi3_with_size_opt is being removed as it has
7 conflicts with unsigned int variables
8
9Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
10---
11 gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
12 1 file changed, 21 insertions(+)
13
14diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
15index 7a40c53..3d2636e 100644
16--- a/gcc/config/microblaze/microblaze.md
17+++ b/gcc/config/microblaze/microblaze.md
18@@ -1508,6 +1508,27 @@
19 (set_attr "length" "4,4")]
20 )
21
22+(define_insn "*ashrsi3_with_size_opt"
23+ [(set (match_operand:SI 0 "register_operand" "=&d")
24+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
25+ (match_operand:SI 2 "immediate_operand" "I")))]
26+ "(INTVAL (operands[2]) > 5 && optimize_size)"
27+ {
28+ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
29+
30+ output_asm_insn ("ori\t%3,r0,%2", operands);
31+ if (REGNO (operands[0]) != REGNO (operands[1]))
32+ output_asm_insn ("addk\t%0,%1,r0", operands);
33+
34+ output_asm_insn ("addik\t%3,%3,-1", operands);
35+ output_asm_insn ("bneid\t%3,.-4", operands);
36+ return "sra\t%0,%0";
37+ }
38+ [(set_attr "type" "arith")
39+ (set_attr "mode" "SI")
40+ (set_attr "length" "20")]
41+)
42+
43 (define_insn "*ashrsi_inline"
44 [(set (match_operand:SI 0 "register_operand" "=&d")
45 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
46--
472.7.4
48
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch
new file mode 100644
index 00000000..3b4b4c70
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch
@@ -0,0 +1,41 @@
1From 53ab5a3fec283aeb9d2efeb632d423b774192e65 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 17:50:03 +0530
4Subject: [PATCH 13/63] [Patch, microblaze]: Fixed missing save of r18 in
5 fast_interrupt. Register 18 is used as a clobber register, and must be stored
6 when entering a fast_interrupt. Before this fix, register 18 was only saved
7 if it was used directly in the interrupt function.
8
9However, if the fast_interrupt function called a function that used
10r18, the register would not be saved, and thus be mangled
11upon returning from the interrupt.
12
13Changelog
14
152014-02-27 Klaus Petersen <klauspetersen@gmail.com>
16
17 * gcc/config/microblaze/microblaze.c: Check for fast_interrupt in
18 microblaze_must_save_register.
19
20Signed-off-by: Klaus Petersen <klauspetersen@gmail.com>
21Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
22---
23 gcc/config/microblaze/microblaze.c | 2 +-
24 1 file changed, 1 insertion(+), 1 deletion(-)
25
26diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
27index ae45038..c834b49 100644
28--- a/gcc/config/microblaze/microblaze.c
29+++ b/gcc/config/microblaze/microblaze.c
30@@ -2043,7 +2043,7 @@ microblaze_must_save_register (int regno)
31 {
32 if (df_regs_ever_live_p (regno)
33 || regno == MB_ABI_MSR_SAVE_REG
34- || (interrupt_handler
35+ || ((interrupt_handler || fast_interrupt)
36 && (regno == MB_ABI_ASM_TEMP_REGNUM
37 || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM)))
38 return 1;
39--
402.7.4
41
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch
new file mode 100644
index 00000000..889a1e69
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch
@@ -0,0 +1,26 @@
1From cbf1854e3569122ee1143e6716ff68275c26aced Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 10:57:19 +0530
4Subject: [PATCH 14/63] [Patch, microblaze]: Use bralid for profiler calls
5 Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
6
7---
8 gcc/config/microblaze/microblaze.h | 2 +-
9 1 file changed, 1 insertion(+), 1 deletion(-)
10
11diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
12index fa0806e..0a435b8 100644
13--- a/gcc/config/microblaze/microblaze.h
14+++ b/gcc/config/microblaze/microblaze.h
15@@ -486,7 +486,7 @@ typedef struct microblaze_args
16
17 #define FUNCTION_PROFILER(FILE, LABELNO) { \
18 { \
19- fprintf (FILE, "\tbrki\tr16,_mcount\n"); \
20+ fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n"); \
21 } \
22 }
23
24--
252.7.4
26
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0015-Patch-microblaze-Disable-fivopts-by-default.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0015-Patch-microblaze-Disable-fivopts-by-default.patch
new file mode 100644
index 00000000..0ada80eb
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0015-Patch-microblaze-Disable-fivopts-by-default.patch
@@ -0,0 +1,42 @@
1From 604cae83ce9d2942568178966f69614acbbcbefd Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 11:10:21 +0530
4Subject: [PATCH 15/63] [Patch, microblaze]: Disable fivopts by default Turn
5 off ivopts by default. Interferes with cse.
6
7Changelog
8
92013-03-18 Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
11 * gcc/common/config/microblaze/microblaze-common.c
12 (microblaze_option_optimization_table): Disable fivopts by default.
13
14Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
15Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
16---
17 gcc/common/config/microblaze/microblaze-common.c | 9 +++++++++
18 1 file changed, 9 insertions(+)
19
20diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
21index c30bdef..9b6ef21 100644
22--- a/gcc/common/config/microblaze/microblaze-common.c
23+++ b/gcc/common/config/microblaze/microblaze-common.c
24@@ -24,6 +24,15 @@
25 #include "common/common-target.h"
26 #include "common/common-target-def.h"
27
28+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
29+static const struct default_options microblaze_option_optimization_table[] =
30+ {
31+ /* Turn off ivopts by default. It messes up cse. */
32+ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
33+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
34+ { OPT_LEVELS_NONE, 0, NULL, 0 }
35+ };
36+
37 #undef TARGET_DEFAULT_TARGET_FLAGS
38 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
39
40--
412.7.4
42
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0016-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0016-Patch-microblaze-Removed-moddi3-routinue.patch
new file mode 100644
index 00000000..87bc1668
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0016-Patch-microblaze-Removed-moddi3-routinue.patch
@@ -0,0 +1,160 @@
1From 14ddb3217fbb84c48903124ec6a3614b4707630d Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 17:36:16 +0530
4Subject: [PATCH 16/63] [Patch, microblaze]: Removed moddi3 routinue Using the
5 default moddi3 function as the existing implementation has many bugs
6
7Signed-off-by:Nagaraju <nmekala@xilix.com>
8
9Conflicts:
10 libgcc/config/microblaze/moddi3.S
11---
12 libgcc/config/microblaze/moddi3.S | 121 ----------------------------------
13 libgcc/config/microblaze/t-microblaze | 3 +-
14 2 files changed, 1 insertion(+), 123 deletions(-)
15 delete mode 100644 libgcc/config/microblaze/moddi3.S
16
17diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
18deleted file mode 100644
19index abfe4fc..0000000
20--- a/libgcc/config/microblaze/moddi3.S
21+++ /dev/null
22@@ -1,121 +0,0 @@
23-###################################
24-#
25-# Copyright (C) 2009-2019 Free Software Foundation, Inc.
26-#
27-# Contributed by Michael Eager <eager@eagercon.com>.
28-#
29-# This file is free software; you can redistribute it and/or modify it
30-# under the terms of the GNU General Public License as published by the
31-# Free Software Foundation; either version 3, or (at your option) any
32-# later version.
33-#
34-# GCC is distributed in the hope that it will be useful, but WITHOUT
35-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
36-# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
37-# License for more details.
38-#
39-# Under Section 7 of GPL version 3, you are granted additional
40-# permissions described in the GCC Runtime Library Exception, version
41-# 3.1, as published by the Free Software Foundation.
42-#
43-# You should have received a copy of the GNU General Public License and
44-# a copy of the GCC Runtime Library Exception along with this program;
45-# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
46-# <http://www.gnu.org/licenses/>.
47-#
48-# modsi3.S
49-#
50-# modulo operation for 64 bit integers.
51-#
52-#######################################
53-
54-
55-/* An executable stack is *not* required for these functions. */
56-#ifdef __linux__
57-.section .note.GNU-stack,"",%progbits
58-.previous
59-#endif
60-
61- .globl __moddi3
62- .ent __moddi3
63-__moddi3:
64- .frame r1,0,r15
65-
66-#Change the stack pointer value and Save callee saved regs
67- addik r1,r1,-24
68- swi r25,r1,0
69- swi r26,r1,4
70- swi r27,r1,8 # used for sign
71- swi r28,r1,12 # used for loop count
72- swi r29,r1,16 # Used for div value High
73- swi r30,r1,20 # Used for div value Low
74-
75-#Check for Zero Value in the divisor/dividend
76- OR r9,r5,r6 # Check for the op1 being zero
77- BEQID r9,$LaResult_Is_Zero # Result is zero
78- OR r9,r7,r8 # Check for the dividend being zero
79- BEQI r9,$LaDiv_By_Zero # Div_by_Zero # Division Error
80- BGEId r5,$La1_Pos
81- XOR r27,r5,r7 # Get the sign of the result
82- RSUBI r6,r6,0 # Make dividend positive
83- RSUBIC r5,r5,0 # Make dividend positive
84-$La1_Pos:
85- BGEI r7,$La2_Pos
86- RSUBI r8,r8,0 # Make Divisor Positive
87- RSUBIC r9,r9,0 # Make Divisor Positive
88-$La2_Pos:
89- ADDIK r4,r0,0 # Clear mod low
90- ADDIK r3,r0,0 # Clear mod high
91- ADDIK r29,r0,0 # clear div high
92- ADDIK r30,r0,0 # clear div low
93- ADDIK r28,r0,64 # Initialize the loop count
94- # First part try to find the first '1' in the r5/r6
95-$LaDIV1:
96- ADD r6,r6,r6
97- ADDC r5,r5,r5 # left shift logical r5
98- BGEID r5,$LaDIV1
99- ADDIK r28,r28,-1
100-$LaDIV2:
101- ADD r6,r6,r6
102- ADDC r5,r5,r5 # left shift logical r5/r6 get the '1' into the Carry
103- ADDC r4,r4,r4 # Move that bit into the Mod register
104- ADDC r3,r3,r3 # Move carry into high mod register
105- rsub r18,r7,r3 # Compare the High Parts of Mod and Divisor
106- bnei r18,$L_High_EQ
107- rsub r18,r6,r4 # Compare Low Parts only if Mod[h] == Divisor[h]
108-$L_High_EQ:
109- rSUB r26,r8,r4 # Subtract divisor[L] from Mod[L]
110- rsubc r25,r7,r3 # Subtract divisor[H] from Mod[H]
111- BLTi r25,$LaMOD_TOO_SMALL
112- OR r3,r0,r25 # move r25 to mod [h]
113- OR r4,r0,r26 # move r26 to mod [l]
114- ADDI r30,r30,1
115- ADDC r29,r29,r0
116-$LaMOD_TOO_SMALL:
117- ADDIK r28,r28,-1
118- BEQi r28,$LaLOOP_END
119- ADD r30,r30,r30 # Shift in the '1' into div [low]
120- ADDC r29,r29,r29 # Move the carry generated into high
121- BRI $LaDIV2 # Div2
122-$LaLOOP_END:
123- BGEI r27,$LaRETURN_HERE
124- rsubi r30,r30,0
125- rsubc r29,r29,r0
126- BRI $LaRETURN_HERE
127-$LaDiv_By_Zero:
128-$LaResult_Is_Zero:
129- or r29,r0,r0 # set result to 0 [High]
130- or r30,r0,r0 # set result to 0 [Low]
131-$LaRETURN_HERE:
132-# Restore values of CSRs and that of r29 and the divisor and the dividend
133-
134- lwi r25,r1,0
135- lwi r26,r1,4
136- lwi r27,r1,8
137- lwi r28,r1,12
138- lwi r29,r1,16
139- lwi r30,r1,20
140- rtsd r15,8
141- addik r1,r1,24
142- .end __moddi3
143-
144diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
145index 96959f0..8d954a4 100644
146--- a/libgcc/config/microblaze/t-microblaze
147+++ b/libgcc/config/microblaze/t-microblaze
148@@ -1,8 +1,7 @@
149-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3
150+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
151
152 LIB2ADD += \
153 $(srcdir)/config/microblaze/divsi3.S \
154- $(srcdir)/config/microblaze/moddi3.S \
155 $(srcdir)/config/microblaze/modsi3.S \
156 $(srcdir)/config/microblaze/muldi3_hard.S \
157 $(srcdir)/config/microblaze/mulsi3.S \
158--
1592.7.4
160
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch
new file mode 100644
index 00000000..ca1c2d1c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch
@@ -0,0 +1,101 @@
1From 032e50c1b267306338cff4d136db88f08350de72 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 14:41:58 +0530
4Subject: [PATCH 17/63] [Patch, microblaze]: Add INIT_PRIORITY support Added
5 TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.
6
7These macros allows users to control the order of initialization
8of objects defined at namespace scope with the init_priority
9attribute by specifying a relative priority, a constant integral
10expression currently bounded between 101 and 65535 inclusive.
11
12Lower numbers indicate a higher priority.
13
14Changelog
15
162013-11-26 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
17
18 * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor,
19 microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and
20 TARGET_ASM_DESTRUCTOR.
21
22Signed-off-by:nagaraju <nmekala@xilix.com>
23Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
24---
25 gcc/config/microblaze/microblaze.c | 53 ++++++++++++++++++++++++++++++++++++++
26 1 file changed, 53 insertions(+)
27
28diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
29index c834b49..c54b96b 100644
30--- a/gcc/config/microblaze/microblaze.c
31+++ b/gcc/config/microblaze/microblaze.c
32@@ -2642,6 +2642,53 @@ print_operand_address (FILE * file, rtx addr)
33 }
34 }
35
36+/* Output an element in the table of global constructors. */
37+void
38+microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
39+{
40+ const char *section = ".ctors";
41+ char buf[16];
42+
43+ if (priority != DEFAULT_INIT_PRIORITY)
44+ {
45+ sprintf (buf, ".ctors.%.5u",
46+ /* Invert the numbering so the linker puts us in the proper
47+ order; constructors are run from right to left, and the
48+ linker sorts in increasing order. */
49+ MAX_INIT_PRIORITY - priority);
50+ section = buf;
51+ }
52+
53+ switch_to_section (get_section (section, 0, NULL));
54+ assemble_align (POINTER_SIZE);
55+ fputs ("\t.word\t", asm_out_file);
56+ output_addr_const (asm_out_file, symbol);
57+ fputs ("\n", asm_out_file);
58+}
59+
60+/* Output an element in the table of global destructors. */
61+void
62+microblaze_asm_destructor (rtx symbol, int priority)
63+{
64+ const char *section = ".dtors";
65+ char buf[16];
66+ if (priority != DEFAULT_INIT_PRIORITY)
67+ {
68+ sprintf (buf, ".dtors.%.5u",
69+ /* Invert the numbering so the linker puts us in the proper
70+ order; constructors are run from right to left, and the
71+ linker sorts in increasing order. */
72+ MAX_INIT_PRIORITY - priority);
73+ section = buf;
74+ }
75+
76+ switch_to_section (get_section (section, 0, NULL));
77+ assemble_align (POINTER_SIZE);
78+ fputs ("\t.word\t", asm_out_file);
79+ output_addr_const (asm_out_file, symbol);
80+ fputs ("\n", asm_out_file);
81+}
82+
83 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
84 is used, so that we don't emit an .extern for it in
85 microblaze_asm_file_end. */
86@@ -3981,6 +4028,12 @@ microblaze_starting_frame_offset (void)
87 #undef TARGET_ATTRIBUTE_TABLE
88 #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table
89
90+#undef TARGET_ASM_CONSTRUCTOR
91+#define TARGET_ASM_CONSTRUCTOR microblaze_asm_constructor
92+
93+#undef TARGET_ASM_DESTRUCTOR
94+#define TARGET_ASM_DESTRUCTOR microblaze_asm_destructor
95+
96 #undef TARGET_IN_SMALL_DATA_P
97 #define TARGET_IN_SMALL_DATA_P microblaze_elf_in_small_data_p
98
99--
1002.7.4
101
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0018-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0018-Patch-microblaze-Add-optimized-lshrsi3.patch
new file mode 100644
index 00000000..de35f286
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0018-Patch-microblaze-Add-optimized-lshrsi3.patch
@@ -0,0 +1,81 @@
1From 6db9d068e32a424ac04c27e963d1e58cb3ef8bdf Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 15:23:57 +0530
4Subject: [PATCH 18/63] [Patch, microblaze]: Add optimized lshrsi3 When barrel
5 shifter is not present, the immediate value is greater than #5 and
6 optimization is -OS, the compiler will generate shift operation using loop.
7
8Changelog
9
102013-11-26 David Holsgrove <david.holsgrove@xilinx.com>
11
12 * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn
13
14ChangeLog/testsuite
15
162014-02-12 David Holsgrove <david.holsgrove@xilinx.com>
17
18 * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.
19
20Signed-off-by:Nagaraju <nmekala@xilix.com>
21Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
22---
23 gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
24 .../gcc.target/microblaze/others/lshrsi_Os_1.c | 13 +++++++++++++
25 2 files changed, 34 insertions(+)
26 create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
27
28diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
29index 3d2636e..aa2eda3 100644
30--- a/gcc/config/microblaze/microblaze.md
31+++ b/gcc/config/microblaze/microblaze.md
32@@ -1618,6 +1618,27 @@
33 (set_attr "length" "4,4")]
34 )
35
36+(define_insn "*lshrsi3_with_size_opt"
37+ [(set (match_operand:SI 0 "register_operand" "=&d")
38+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
39+ (match_operand:SI 2 "immediate_operand" "I")))]
40+ "(INTVAL (operands[2]) > 5 && optimize_size)"
41+ {
42+ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
43+
44+ output_asm_insn ("ori\t%3,r0,%2", operands);
45+ if (REGNO (operands[0]) != REGNO (operands[1]))
46+ output_asm_insn ("addk\t%0,%1,r0", operands);
47+
48+ output_asm_insn ("addik\t%3,%3,-1", operands);
49+ output_asm_insn ("bneid\t%3,.-4", operands);
50+ return "srl\t%0,%0";
51+ }
52+ [(set_attr "type" "multi")
53+ (set_attr "mode" "SI")
54+ (set_attr "length" "20")]
55+)
56+
57 (define_insn "*lshrsi_inline"
58 [(set (match_operand:SI 0 "register_operand" "=&d")
59 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
60diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
61new file mode 100644
62index 0000000..32a3be7
63--- /dev/null
64+++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
65@@ -0,0 +1,13 @@
66+/* { dg-options "-Os -mno-xl-barrel-shift" } */
67+
68+void testfunc(void)
69+{
70+ unsigned volatile int z = 8192;
71+ z >>= 8;
72+}
73+/* { dg-final { scan-assembler-not "\bsrli" } } */
74+/* { dg-final { scan-assembler "\ori\tr18,r0" } } */
75+/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
76+/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */
77+/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */
78+/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */
79--
802.7.4
81
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0019-Patch-microblaze-Modified-trap-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0019-Patch-microblaze-Modified-trap-instruction.patch
new file mode 100644
index 00000000..dc9b61cf
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0019-Patch-microblaze-Modified-trap-instruction.patch
@@ -0,0 +1,29 @@
1From 614bacc058b94c7b12cd40fde1b19b4709870f3b Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 15:42:15 +0530
4Subject: [PATCH 19/63] [Patch, microblaze]: Modified trap instruction The
5 instruction was wrongly written to brki r0,-1 it should be bri r0. Modified
6 with the correct instruction
7
8Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
9 :Ajit Agarwal <ajitkum@xilinx.com>
10---
11 gcc/config/microblaze/microblaze.md | 2 +-
12 1 file changed, 1 insertion(+), 1 deletion(-)
13
14diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
15index aa2eda3..3c80760 100644
16--- a/gcc/config/microblaze/microblaze.md
17+++ b/gcc/config/microblaze/microblaze.md
18@@ -2348,7 +2348,7 @@
19 (define_insn "trap"
20 [(trap_if (const_int 1) (const_int 0))]
21 ""
22- "brki\tr0,-1"
23+ "bri\t0"
24 [(set_attr "type" "trap")]
25 )
26
27--
282.7.4
29
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
new file mode 100644
index 00000000..b60a4e95
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
@@ -0,0 +1,206 @@
1From 372bbc75146166df9b82ca5e8f236971b7cef16e Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 16:42:44 +0530
4Subject: [PATCH 20/63] [Patch, microblaze]: Reducing Stack space for arguments
5 Currently in Microblaze target stack space for arguments in register is being
6 allocated even if there are no arguments in the function. This patch will
7 optimize the extra 24 bytes that are being allocated.
8
9Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
10 :Ajit Agarwal <ajitkum@xilinx.com>
11
12ChangeLog:
132015-04-17 Nagaraju Mekala <nmekala@xilix.com>
14 Ajit Agarwal <ajitkum@xilinx.com>
15
16 *microblaze.c (microblaze_parm_needs_stack, microblaze_function_parms_need_stack): New
17 *microblaze.c (REG_PARM_STACK_SPACE): Modify
18---
19 gcc/config/microblaze/microblaze-protos.h | 1 +
20 gcc/config/microblaze/microblaze.c | 134 +++++++++++++++++++++++++++++-
21 gcc/config/microblaze/microblaze.h | 4 +-
22 3 files changed, 136 insertions(+), 3 deletions(-)
23
24diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
25index 1f5ca80..6647cbc 100644
26--- a/gcc/config/microblaze/microblaze-protos.h
27+++ b/gcc/config/microblaze/microblaze-protos.h
28@@ -59,6 +59,7 @@ extern int symbol_mentioned_p (rtx);
29 extern int label_mentioned_p (rtx);
30 extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
31 extern void microblaze_eh_return (rtx op0);
32+int microblaze_reg_parm_stack_space(tree fun);
33 #endif /* RTX_CODE */
34
35 /* Declare functions in microblaze-c.c. */
36diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
37index c54b96b..0ce9d13 100644
38--- a/gcc/config/microblaze/microblaze.c
39+++ b/gcc/config/microblaze/microblaze.c
40@@ -2065,6 +2065,138 @@ microblaze_must_save_register (int regno)
41 return 0;
42 }
43
44+static bool
45+microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type)
46+{
47+ enum machine_mode mode;
48+ int unsignedp;
49+ rtx entry_parm;
50+
51+ /* Catch errors. */
52+ if (type == NULL || type == error_mark_node)
53+ return true;
54+
55+ if (TREE_CODE (type) == POINTER_TYPE)
56+ return true;
57+
58+ /* Handle types with no storage requirement. */
59+ if (TYPE_MODE (type) == VOIDmode)
60+ return false;
61+
62+ /* Handle complex types. */
63+ if (TREE_CODE (type) == COMPLEX_TYPE)
64+ return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))
65+ || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)));
66+
67+ /* Handle transparent aggregates. */
68+ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
69+ && TYPE_TRANSPARENT_AGGR (type))
70+ type = TREE_TYPE (first_field (type));
71+
72+ /* See if this arg was passed by invisible reference. */
73+ if (pass_by_reference (get_cumulative_args (args_so_far),
74+ TYPE_MODE (type), type, true))
75+ type = build_pointer_type (type);
76+
77+ /* Find mode as it is passed by the ABI. */
78+ unsignedp = TYPE_UNSIGNED (type);
79+ mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
80+
81+/* If there is no incoming register, we need a stack. */
82+ entry_parm = microblaze_function_arg (args_so_far, mode, type, true);
83+ if (entry_parm == NULL)
84+ return true;
85+
86+ /* Likewise if we need to pass both in registers and on the stack. */
87+ if (GET_CODE (entry_parm) == PARALLEL
88+ && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
89+ return true;
90+
91+ /* Also true if we're partially in registers and partially not. */
92+ if (function_arg_partial_bytes (args_so_far, mode, type, true) != 0)
93+ return true;
94+
95+ /* Update info on where next arg arrives in registers. */
96+ microblaze_function_arg_advance (args_so_far, mode, type, true);
97+ return false;
98+ }
99+
100+static bool
101+microblaze_function_parms_need_stack (tree fun, bool incoming)
102+{
103+ tree fntype, result;
104+ CUMULATIVE_ARGS args_so_far_v;
105+ cumulative_args_t args_so_far;
106+ int num_of_args = 0;
107+
108+ /* Must be a libcall, all of which only use reg parms. */
109+ if (!fun)
110+ return true;
111+
112+ fntype = fun;
113+ if (!TYPE_P (fun))
114+ fntype = TREE_TYPE (fun);
115+
116+ /* Varargs functions need the parameter save area. */
117+ if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
118+ return true;
119+
120+ INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0);
121+ args_so_far = pack_cumulative_args (&args_so_far_v);
122+
123+ /* When incoming, we will have been passed the function decl.
124+ * It is necessary to use the decl to handle K&R style functions,
125+ * where TYPE_ARG_TYPES may not be available. */
126+ if (incoming)
127+ {
128+ gcc_assert (DECL_P (fun));
129+ result = DECL_RESULT (fun);
130+ }
131+ else
132+ result = TREE_TYPE (fntype);
133+
134+ if (result && aggregate_value_p (result, fntype))
135+ {
136+ if (!TYPE_P (result))
137+ result = build_pointer_type (result);
138+ microblaze_parm_needs_stack (args_so_far, result);
139+ }
140+
141+ if (incoming)
142+ {
143+ tree parm;
144+ for (parm = DECL_ARGUMENTS (fun);
145+ parm && parm != void_list_node;
146+ parm = TREE_CHAIN (parm))
147+ if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
148+ return true;
149+ }
150+ else
151+ {
152+ function_args_iterator args_iter;
153+ tree arg_type;
154+
155+ FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
156+ {
157+ num_of_args++;
158+ if (microblaze_parm_needs_stack (args_so_far, arg_type))
159+ return true;
160+ }
161+ }
162+
163+ if (num_of_args > 3) return true;
164+
165+ return false;
166+}
167+
168+int microblaze_reg_parm_stack_space(tree fun)
169+{
170+ if (microblaze_function_parms_need_stack (fun,false))
171+ return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD;
172+ else
173+ return 0;
174+}
175+
176 /* Return the bytes needed to compute the frame pointer from the current
177 stack pointer.
178
179@@ -3411,7 +3543,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
180 emit_insn (gen_indirect_jump (temp2));
181
182 /* Run just enough of rest_of_compilation. This sequence was
183- "borrowed" from rs6000.c. */
184+ "borrowed" from microblaze.c. */
185 insn = get_insns ();
186 shorten_branches (insn);
187 final_start_function (insn, file, 1);
188diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
189index 0a435b8..346e47b 100644
190--- a/gcc/config/microblaze/microblaze.h
191+++ b/gcc/config/microblaze/microblaze.h
192@@ -434,9 +434,9 @@ extern struct microblaze_frame_info current_frame_info;
193
194 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
195
196-#define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
197+#define REG_PARM_STACK_SPACE(FNDECL) microblaze_reg_parm_stack_space(FNDECL)
198
199-#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
200+#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
201
202 #define STACK_BOUNDARY 32
203
204--
2052.7.4
206
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0021-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0021-Patch-microblaze-Add-cbranchsi4_reg.patch
new file mode 100644
index 00000000..c79f9552
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0021-Patch-microblaze-Add-cbranchsi4_reg.patch
@@ -0,0 +1,159 @@
1From 1c226901aec38e2e824177418dcd82b6cd49ffca Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 17:04:37 +0530
4Subject: [PATCH 21/63] [Patch, microblaze]: Add cbranchsi4_reg This patch
5 optimizes the generation of pcmpne/pcmpeq instruction if the compare
6 instruction has no immediate values.For the immediate values the xor
7 instruction is generated
8
9Signed-off-by: Nagaraju Mekala <nmekala@xilix.com>
10Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
11
12ChangeLog:
132015-01-13 Nagaraju Mekala <nmekala@xilix.com>
14 Ajit Agarwal <ajitkum@xilinx.com>
15
16 *microblaze.md (cbranchsi4_reg): New
17 *microblaze.c (microblaze_expand_conditional_branch_reg): New
18
19Conflicts:
20
21 gcc/config/microblaze/microblaze-protos.h
22---
23 gcc/config/microblaze/microblaze-protos.h | 2 +-
24 gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c | 2 +-
25 gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c | 2 +-
26 gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c | 2 +-
27 gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c | 2 +-
28 gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c | 14 +++++++-------
29 gcc/testsuite/gcc.target/microblaze/isa/vanilla.c | 12 ++++++------
30 gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c | 2 +-
31 8 files changed, 19 insertions(+), 19 deletions(-)
32
33diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
34index 6647cbc..bdc9b69 100644
35--- a/gcc/config/microblaze/microblaze-protos.h
36+++ b/gcc/config/microblaze/microblaze-protos.h
37@@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *);
38 extern bool microblaze_expand_move (machine_mode, rtx *);
39 extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx);
40 extern void microblaze_expand_divide (rtx *);
41-extern void microblaze_expand_conditional_branch (machine_mode, rtx *);
42+extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
43 extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
44 extern void microblaze_expand_conditional_branch_sf (rtx *);
45 extern int microblaze_can_use_return_insn (void);
46diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
47index 4041a24..ccc6a46 100644
48--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
49+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
50@@ -6,5 +6,5 @@ void float_func ()
51 {
52 /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
53 if (f2 <= f3)
54- print ("le");
55+ f2 = f3;
56 }
57diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
58index 3902b83..1dd5fe6 100644
59--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
60+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
61@@ -6,5 +6,5 @@ void float_func ()
62 {
63 /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
64 if (f2 < f3)
65- print ("lt");
66+ f2 = f3;
67 }
68diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
69index 8555974..d6f80fb 100644
70--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
71+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
72@@ -6,5 +6,5 @@ void float_func ()
73 {
74 /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
75 if (f2 == f3)
76- print ("eq");
77+ f1 = f2 + f3;
78 }
79diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
80index 79cc5f9..d117724 100644
81--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
82+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
83@@ -5,5 +5,5 @@ void float_func(float f1, float f2, float f3)
84 /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
85 /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
86 if(f1==f2 && f1<=f3)
87- print ("f1 eq f2 && f1 le f3");
88+ f2 = f3;
89 }
90diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
91index ebfb170..7582297 100644
92--- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
93+++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
94@@ -5,17 +5,17 @@ volatile float f1, f2, f3;
95 void float_func ()
96 {
97 /* { dg-final { scan-assembler-not "fcmp" } } */
98- if (f2 <= f3)
99- print ("le");
100+ if (f2 <= f3)
101+ f1 = f3;
102 else if (f2 == f3)
103- print ("eq");
104+ f1 = f3;
105 else if (f2 < f3)
106- print ("lt");
107+ f1 = f3;
108 else if (f2 > f3)
109- print ("gt");
110+ f1 = f3;
111 else if (f2 >= f3)
112- print ("ge");
113+ f1 = f3;
114 else if (f2 != f3)
115- print ("ne");
116+ f1 = f3;
117
118 }
119diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
120index 1d6ba80..532c035 100644
121--- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
122+++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
123@@ -74,16 +74,16 @@ void float_cmp_func ()
124 {
125 /* { dg-final { scan-assembler-not "fcmp" } } */
126 if (f2 <= f3)
127- print ("le");
128+ f1 = f3;
129 else if (f2 == f3)
130- print ("eq");
131+ f1 = f3;
132 else if (f2 < f3)
133- print ("lt");
134+ f1 = f3;
135 else if (f2 > f3)
136- print ("gt");
137+ f1 = f3;
138 else if (f2 >= f3)
139- print ("ge");
140+ f1 = f3;
141 else if (f2 != f3)
142- print ("ne");
143+ f1 = f3;
144
145 }
146diff --git a/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c b/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
147index fdcde1f..580b4db 100644
148--- a/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
149+++ b/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
150@@ -5,4 +5,4 @@ void trap ()
151 __builtin_trap ();
152 }
153
154-/* { dg-final { scan-assembler "brki\tr0,-1" } } */
155\ No newline at end of file
156+/* { dg-final { scan-assembler "bri\t0" } } */
157--
1582.7.4
159
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
new file mode 100644
index 00000000..c3822d06
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
@@ -0,0 +1,58 @@
1From 791d65feae4f3cab47833579bc6f523e54194cbd Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 17:11:04 +0530
4Subject: [PATCH 22/63] [Patch,microblaze]: Inline Expansion of fsqrt builtin.
5 The changes are made in the patch for the inline expansion of the fsqrt
6 builtin with fqrt instruction. The sqrt math function takes double as
7 argument and return double as argument. The pattern is selected while
8 expanding the unary op through expand_unop which passes DFmode and the DFmode
9 pattern was not there returning zero. Thus the sqrt math function is not
10 inlined and expanded. The pattern with DFmode argument is added. Also the
11 source and destination argument is not same the DF through two different
12 consecutive registers with lower 32 bit is the argument passed to sqrt and
13 the higher 32 bit is zero. If the source and destinations are different the
14 DFmode 64 bits registers is not set properly giving the problem in runtime.
15 Such changes are taken care in the implementation of the pattern for DFmode
16 for inline expansion of the sqrt.
17
18ChangeLog:
192015-06-16 Ajit Agarwal <ajitkum@xilinx.com>
20 Nagaraju Mekala <nmekala@xilinx.com>
21
22 * config/microblaze/microblaze.md (sqrtdf2): New
23 pattern.
24
25Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
26 Nagaraju Mekala nmekala@xilinx.com
27---
28 gcc/config/microblaze/microblaze.md | 14 ++++++++++++++
29 1 file changed, 14 insertions(+)
30
31diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
32index 3c80760..1fb5582 100644
33--- a/gcc/config/microblaze/microblaze.md
34+++ b/gcc/config/microblaze/microblaze.md
35@@ -451,6 +451,20 @@
36 (set_attr "mode" "SF")
37 (set_attr "length" "4")])
38
39+(define_insn "sqrtdf2"
40+ [(set (match_operand:DF 0 "register_operand" "=d")
41+ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
42+ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
43+ {
44+ if (REGNO (operands[0]) == REGNO (operands[1]))
45+ return "fsqrt\t%0,%1";
46+ else
47+ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
48+ }
49+ [(set_attr "type" "fsqrt")
50+ (set_attr "mode" "SF")
51+ (set_attr "length" "4")])
52+
53 (define_insn "fix_truncsfsi2"
54 [(set (match_operand:SI 0 "register_operand" "=d")
55 (fix:SI (match_operand:SF 1 "register_operand" "d")))]
56--
572.7.4
58
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
new file mode 100644
index 00000000..a314170f
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
@@ -0,0 +1,47 @@
1From 2c4a1d46e4f1b2342f899d6741d09dbf7cc87aa2 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 17:33:31 +0530
4Subject: [PATCH 23/63] [Patch] OPT: Update heuristics for loop-invariant for
5 address arithme. .tic.
6
7The changes are made in the patch to update the heuristics
8for loop invariant for address arithmetic. The heuristics is
9changed to calculate the estimated register pressure cost when
10ira based register pressure is not enabled. The estimated
11register pressure cost modifies the existing calculation cost
12associated to perform the Loop invariant code motion for address
13arithmetic.
14
15ChangeLog:
162015-06-17 Ajit Agarwal <ajitkum@xilinx.com>
17 Nagaraju Mekala <nmekala@xilinx.com>
18
19 * loop-invariant.c (gain_for_invariant): update the
20 heuristics for estimate_reg_pressure_cost.
21
22Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
23 Nagaraju Mekala nmekala@xilinx.com
24---
25 gcc/loop-invariant.c | 6 ++----
26 1 file changed, 2 insertions(+), 4 deletions(-)
27
28diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
29index b880ead..fd7a019 100644
30--- a/gcc/loop-invariant.c
31+++ b/gcc/loop-invariant.c
32@@ -1465,10 +1465,8 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
33
34 if (! flag_ira_loop_pressure)
35 {
36- size_cost = (estimate_reg_pressure_cost (new_regs[0] + regs_needed[0],
37- regs_used, speed, call_p)
38- - estimate_reg_pressure_cost (new_regs[0],
39- regs_used, speed, call_p));
40+ size_cost = estimate_reg_pressure_cost (regs_needed[0],
41+ regs_used, speed, call_p);
42 }
43 else if (ret < 0)
44 return -1;
45--
462.7.4
47
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
new file mode 100644
index 00000000..a786ba09
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
@@ -0,0 +1,63 @@
1From c2b64f2f7a06231d8da0a53c6761939583ac56da Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 18:07:24 +0530
4Subject: [PATCH 24/63] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
5 insn definitions Change adddi3 to handle DI immediates as the second operand,
6 this requires modification to the output template however reduces the need to
7 specify seperate templates for 16-bit positive/negative immediate operands.
8 The use of 32-bit immediates for the addi and addic instructions is handled
9 by the assembler, which will emit the imm instructions when required. This
10 conveniently handles the optimizable cases where the immediate constant value
11 does not need the higher half words of the operands upper/lower words.
12
13Change the constraints of the subdi3 instruction definition such that it
14does not match the second operand as an immediate value. This is because
15there is no definition to handle this case nor is it possible to
16implement purely with instructions as microblaze does not provide an
17instruction to perform a forward arithmetic subtraction (it only
18provides reverse 'rD = IMM - rA').
19
20Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
21---
22 gcc/config/microblaze/microblaze.md | 13 ++++++-------
23 1 file changed, 6 insertions(+), 7 deletions(-)
24
25diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
26index 1fb5582..216219b 100644
27--- a/gcc/config/microblaze/microblaze.md
28+++ b/gcc/config/microblaze/microblaze.md
29@@ -502,17 +502,16 @@
30 ;; Adding 2 DI operands in register or reg/imm
31
32 (define_insn "adddi3"
33- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
34- (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d")
35- (match_operand:DI 2 "arith_operand32" "d,P,N")))]
36+ [(set (match_operand:DI 0 "register_operand" "=d,d")
37+ (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
38+ (match_operand:DI 2 "arith_operand" "d,i")))]
39 ""
40 "@
41 add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
42- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0
43- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1"
44+ addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
45 [(set_attr "type" "darith")
46 (set_attr "mode" "DI")
47- (set_attr "length" "8,8,12")])
48+ (set_attr "length" "8,8")])
49
50 ;;----------------------------------------------------------------
51 ;; Subtraction
52@@ -549,7 +548,7 @@
53 (define_insn "subdi3"
54 [(set (match_operand:DI 0 "register_operand" "=&d")
55 (minus:DI (match_operand:DI 1 "register_operand" "d")
56- (match_operand:DI 2 "arith_operand32" "d")))]
57+ (match_operand:DI 2 "register_operand" "d")))]
58 ""
59 "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
60 [(set_attr "type" "darith")
61--
622.7.4
63
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
new file mode 100644
index 00000000..98310b36
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
@@ -0,0 +1,72 @@
1From c7e5c253b1e7800bc5ec8cc69850118ed938e22f Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 18:18:41 +0530
4Subject: [PATCH 25/63] [Patch, microblaze]: Update ashlsi3 & movsf patterns
5 This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand
6 of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal
7 patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our
8 instruction doesn't support so using gen_int_mode function
9
10Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
11 :Ajit Agarwal <ajitkum@xilinx.com>
12
13ChangeLog:
142016-01-07 Nagaraju Mekala <nmekala@xilix.com>
15 Ajit Agarwal <ajitkum@xilinx.com>
16
17 *microblaze.md (ashlsi3_with_mul_nodelay,
18 ashlsi3_with_mul_delay,
19 movsf_internal):
20 Updated the patterns to use gen_int_mode function
21 *microblaze.c (print_operand):
22 updated the 'F' case to use "unsinged int" instead
23 of HOST_WIDE_INT_PRINT_HEX
24---
25 gcc/config/microblaze/microblaze.c | 2 +-
26 gcc/config/microblaze/microblaze.md | 10 ++++++++--
27 2 files changed, 9 insertions(+), 3 deletions(-)
28
29diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
30index 0ce9d13..7669668 100644
31--- a/gcc/config/microblaze/microblaze.c
32+++ b/gcc/config/microblaze/microblaze.c
33@@ -2608,7 +2608,7 @@ print_operand (FILE * file, rtx op, int letter)
34 unsigned long value_long;
35 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op),
36 value_long);
37- fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long);
38+ fprintf (file, "0x%08x", (unsigned int) value_long);
39 }
40 else
41 {
42diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
43index 216219b..4bc209c 100644
44--- a/gcc/config/microblaze/microblaze.md
45+++ b/gcc/config/microblaze/microblaze.md
46@@ -1368,7 +1368,10 @@
47 (match_operand:SI 2 "immediate_operand" "I")))]
48 "!TARGET_SOFT_MUL
49 && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)"
50- "muli\t%0,%1,%m2"
51+ {
52+ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
53+ return "muli\t%0,%1,%2";
54+ }
55 ;; This MUL will not generate an imm. Can go into a delay slot.
56 [(set_attr "type" "arith")
57 (set_attr "mode" "SI")
58@@ -1380,7 +1383,10 @@
59 (ashift:SI (match_operand:SI 1 "register_operand" "d")
60 (match_operand:SI 2 "immediate_operand" "I")))]
61 "!TARGET_SOFT_MUL"
62- "muli\t%0,%1,%m2"
63+ {
64+ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
65+ return "muli\t%0,%1,%2";
66+ }
67 ;; This MUL will generate an IMM. Cannot go into a delay slot
68 [(set_attr "type" "no_delay_arith")
69 (set_attr "mode" "SI")
70--
712.7.4
72
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
new file mode 100644
index 00000000..ba80ce45
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
@@ -0,0 +1,193 @@
1From c3b633b0ee8d228a7d70a02b574822aba9a0fd93 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 19:50:34 +0530
4Subject: [PATCH 26/63] [Patch, microblaze]: 8-stage pipeline for microblaze
5 This patch adds the support for the 8-stage pipeline. The new 8-stage
6 pipeline reduces the latencies of float & integer division drastically
7
8Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
9
10ChangeLog:
112016-01-18 Nagaraju Mekala <nmekala@xilix.com>
12
13 *microblaze.md (define_automaton mbpipe_8): New
14
15 *microblaze.c (microblaze_option_override): Update
16 Updated the logic to generate only when MB version is 10.0
17
18 *microblaze.h (pipeline_type): Update
19 Update the enum with MICROBLAZE_PIPE_8
20
21 *microblaze.opt (mxl-frequency): New
22 New flag added for 8-stage pipeline
23---
24 gcc/config/microblaze/microblaze.c | 13 ++++++
25 gcc/config/microblaze/microblaze.h | 3 +-
26 gcc/config/microblaze/microblaze.md | 79 +++++++++++++++++++++++++++++++++++-
27 gcc/config/microblaze/microblaze.opt | 4 ++
28 4 files changed, 96 insertions(+), 3 deletions(-)
29
30diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
31index 7669668..ae7d5dd 100644
32--- a/gcc/config/microblaze/microblaze.c
33+++ b/gcc/config/microblaze/microblaze.c
34@@ -1848,6 +1848,19 @@ microblaze_option_override (void)
35 "%<-mcpu=v8.30.a%>");
36 TARGET_REORDER = 0;
37 }
38+ ver = ver_int - microblaze_version_to_int("v10.0");
39+ if (ver < 0)
40+ {
41+ if (TARGET_AREA_OPTIMIZED_2)
42+ warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater");
43+ }
44+ else
45+ {
46+ if (TARGET_AREA_OPTIMIZED_2)
47+ microblaze_pipe = MICROBLAZE_PIPE_8;
48+ if (TARGET_BARREL_SHIFT)
49+ microblaze_has_bitfield = 1;
50+ }
51
52 if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
53 error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>");
54diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
55index 346e47b..bf7f3b4 100644
56--- a/gcc/config/microblaze/microblaze.h
57+++ b/gcc/config/microblaze/microblaze.h
58@@ -27,7 +27,8 @@
59 enum pipeline_type
60 {
61 MICROBLAZE_PIPE_3 = 0,
62- MICROBLAZE_PIPE_5 = 1
63+ MICROBLAZE_PIPE_5 = 1,
64+ MICROBLAZE_PIPE_8 = 2
65 };
66
67 #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001
68diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
69index 4bc209c..b7c16ac 100644
70--- a/gcc/config/microblaze/microblaze.md
71+++ b/gcc/config/microblaze/microblaze.md
72@@ -35,6 +35,7 @@
73 (R_GOT 20) ;; GOT ptr reg
74 (MB_PIPE_3 0) ;; Microblaze 3-stage pipeline
75 (MB_PIPE_5 1) ;; Microblaze 5-stage pipeline
76+ (MB_PIPE_8 2) ;; Microblaze 8-stage pipeline
77 (UNSPEC_SET_GOT 101) ;;
78 (UNSPEC_GOTOFF 102) ;; GOT offset
79 (UNSPEC_PLT 103) ;; jump table
80@@ -82,7 +83,7 @@
81 ;; bshift Shift operations
82
83 (define_attr "type"
84- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
85+ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap"
86 (const_string "unknown"))
87
88 ;; Main data type used by the insn
89@@ -224,6 +225,80 @@
90 ;;-----------------------------------------------------------------
91
92
93+
94+;;----------------------------------------------------------------
95+;; Microblaze 8-stage pipeline description (v10.0 and later)
96+;;----------------------------------------------------------------
97+
98+(define_automaton "mbpipe_8")
99+(define_cpu_unit "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8")
100+
101+(define_insn_reservation "mb8-integer" 1
102+ (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith")
103+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
104+ "mb8_issue,mb8_iu,mb8_wb")
105+
106+(define_insn_reservation "mb8-special-move" 2
107+ (and (eq_attr "type" "move")
108+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
109+ "mb8_issue,mb8_iu*2,mb8_wb")
110+
111+(define_insn_reservation "mb8-mem-load" 3
112+ (and (eq_attr "type" "load,no_delay_load")
113+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
114+ "mb8_issue,mb8_iu,mb8_wb")
115+
116+(define_insn_reservation "mb8-mem-store" 1
117+ (and (eq_attr "type" "store,no_delay_store")
118+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
119+ "mb8_issue,mb8_iu,mb8_wb")
120+
121+(define_insn_reservation "mb8-mul" 3
122+ (and (eq_attr "type" "imul,no_delay_imul")
123+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
124+ "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb")
125+
126+(define_insn_reservation "mb8-div" 30
127+ (and (eq_attr "type" "idiv")
128+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
129+ "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb")
130+
131+(define_insn_reservation "mb8-bs" 2
132+ (and (eq_attr "type" "bshift")
133+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
134+ "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb")
135+
136+(define_insn_reservation "mb8-fpu-add-sub-mul" 1
137+ (and (eq_attr "type" "fadd,frsub,fmul")
138+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
139+ "mb8_issue,mb8_fpu,mb8_wb")
140+
141+(define_insn_reservation "mb8-fpu-fcmp" 3
142+ (and (eq_attr "type" "fcmp")
143+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
144+ "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb")
145+
146+(define_insn_reservation "mb8-fpu-div" 24
147+ (and (eq_attr "type" "fdiv")
148+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
149+ "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb")
150+
151+(define_insn_reservation "mb8-fpu-sqrt" 23
152+ (and (eq_attr "type" "fsqrt")
153+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
154+ "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb")
155+
156+(define_insn_reservation "mb8-fpu-fcvt" 1
157+ (and (eq_attr "type" "fcvt")
158+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
159+ "mb8_issue,mb8_fpu,mb8_wb")
160+
161+(define_insn_reservation "mb8-fpu-fint" 2
162+ (and (eq_attr "type" "fint")
163+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
164+ "mb8_issue,mb8_fpu,mb8_wb")
165+
166+
167 ;;----------------------------------------------------------------
168 ;; Microblaze 5-stage pipeline description (v5.00.a and later)
169 ;;----------------------------------------------------------------
170@@ -470,7 +545,7 @@
171 (fix:SI (match_operand:SF 1 "register_operand" "d")))]
172 "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
173 "fint\t%0,%1"
174- [(set_attr "type" "fcvt")
175+ [(set_attr "type" "fint")
176 (set_attr "mode" "SF")
177 (set_attr "length" "4")])
178
179diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
180index 2e46941..d23f376 100644
181--- a/gcc/config/microblaze/microblaze.opt
182+++ b/gcc/config/microblaze/microblaze.opt
183@@ -133,3 +133,7 @@ Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE).
184
185 mxl-mode-xilkernel
186 Target
187+
188+mxl-frequency
189+Target Mask(AREA_OPTIMIZED_2)
190+Use 8 stage pipeline (frequency optimization)
191--
1922.7.4
193
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch
new file mode 100644
index 00000000..330b5494
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch
@@ -0,0 +1,142 @@
1From 650cbdea7bc810e2bd0ebc5eb5647ed513498670 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 18 Jan 2017 11:08:40 +0530
4Subject: [PATCH 27/63] [Patch,rtl Optimization]: Better register pressure
5 estimate for loop . .invariant code motion
6
7Calculate the loop liveness used for regs for calculating the register pressure
8in the cost estimation. Loop liveness is based on the following properties.
9We only need to find the set of objects that are live at the birth or the header
10of the loop. We don't need to calculate the live through the loop by considering
11live in and live out of all the basic blocks of the loop. This is based on the
12point that the set of objects that are live-in at the birth or header of the loop
13will be live-in at every node in the loop.
14
15If a v live is out at the header of the loop then the variable is live-in at every node
16in the loop. To prove this, consider a loop L with header h such that the variable v
17defined at d is live-in at h. Since v is live at h, d is not part of L. This follows i
18from the dominance property, i.e. h is strictly dominated by d. Furthermore, there
19exists a path from h to a use of v which does not go through d. For every node p in
20the loop, since the loop is strongly connected and node is a component of the CFG,
21there exists a path, consisting only of nodes of L from p to h. Concatenating these
22two paths proves that v is live-in and live-out of p.
23
24Calculate the live-out and live-in for the exit edge of the loop. This patch considers
25liveness for not only the loop latch but also the liveness outside the loops.
26
27ChangeLog:
282016-01-22 Ajit Agarwal <ajitkum@xilinx.com>
29
30 * loop-invariant.c
31 (find_invariants_to_move): Add the logic of regs_used based
32 on liveness.
33 * cfgloopanal.c
34 (estimate_reg_pressure_cost): Update the heuristics in presence
35 of call_p.
36
37Signed-off-by:Ajit Agarwal ajitkum@xilinx.com.
38---
39 gcc/cfgloopanal.c | 4 +++-
40 gcc/loop-invariant.c | 63 +++++++++++++++++++++++++++++++++++++++-------------
41 2 files changed, 50 insertions(+), 17 deletions(-)
42
43diff --git a/gcc/cfgloopanal.c b/gcc/cfgloopanal.c
44index 6dbe96f..ec5cba2 100644
45--- a/gcc/cfgloopanal.c
46+++ b/gcc/cfgloopanal.c
47@@ -411,7 +411,9 @@ estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed,
48 if (regs_needed + target_res_regs <= available_regs)
49 return 0;
50
51- if (regs_needed <= available_regs)
52+ if ((regs_needed <= available_regs)
53+ || (call_p && (regs_needed <=
54+ (available_regs + target_clobbered_regs))))
55 /* If we are close to running out of registers, try to preserve
56 them. */
57 cost = target_reg_cost [speed] * n_new;
58diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
59index fd7a019..ad54297 100644
60--- a/gcc/loop-invariant.c
61+++ b/gcc/loop-invariant.c
62@@ -1519,7 +1519,7 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
63 size_cost = 0;
64 }
65
66- return comp_cost - size_cost;
67+ return comp_cost - size_cost + 1;
68 }
69
70 /* Finds invariant with best gain for moving. Returns the gain, stores
71@@ -1613,22 +1613,53 @@ find_invariants_to_move (bool speed, bool call_p)
72 /* REGS_USED is actually never used when the flag is on. */
73 regs_used = 0;
74 else
75- /* We do not really do a good job in estimating number of
76- registers used; we put some initial bound here to stand for
77- induction variables etc. that we do not detect. */
78+ /* The logic used in estimating the number of regs_used is changed.
79+ Now it will be based on liveness of the loop. */
80 {
81- unsigned int n_regs = DF_REG_SIZE (df);
82-
83- regs_used = 2;
84-
85- for (i = 0; i < n_regs; i++)
86- {
87- if (!DF_REGNO_FIRST_DEF (i) && DF_REGNO_LAST_USE (i))
88- {
89- /* This is a value that is used but not changed inside loop. */
90- regs_used++;
91- }
92- }
93+ int i;
94+ edge e;
95+ vec<edge> edges;
96+ bitmap_head regs_live;
97+
98+ bitmap_initialize (&regs_live, &reg_obstack);
99+ edges = get_loop_exit_edges (curr_loop);
100+
101+ /* Loop liveness is based on the following properties.
102+ We only need to find the set of objects that are live at the
103+ birth or the header of the loop.
104+ We don't need to calculate the live through the loop considering
105+ live-in and live-out of all the basic blocks of the loop. This is
106+ based on the point that the set of objects that are live-in at the
107+ birth or header of the loop will be live-in at every block in the
108+ loop.
109+
110+ If a v live out at the header of the loop then the variable is
111+ live-in at every node in the Loop. To prove this, consider a loop
112+ L with header h such that the variable v defined at d is live-in
113+ at h. Since v is live at h, d is not part of L. This follows from
114+ the dominance property, i.e. h is strictly dominated by d. Furthermore,
115+ there exists a path from h to a use of v which does not go through d.
116+ For every node of the loop, p, since the loop is strongly connected
117+ component of the CFG, there exists a path, consisting only of nodes
118+ of L from p to h. Concatenating these two paths prove that v is
119+ live-in and live-out of p. */
120+
121+ bitmap_ior_into (&regs_live, DF_LR_IN (curr_loop->header));
122+ bitmap_ior_into (&regs_live, DF_LR_OUT (curr_loop->header));
123+
124+ /* Calculate the live-out and live-in for the exit edge of the loop.
125+ This considers liveness for not only the loop latch but also the
126+ liveness outside the loops. */
127+
128+ FOR_EACH_VEC_ELT (edges, i, e)
129+ {
130+ bitmap_ior_into (&regs_live, DF_LR_OUT (e->src));
131+ bitmap_ior_into (&regs_live, DF_LR_IN (e->dest));
132+ }
133+
134+ regs_used = bitmap_count_bits (&regs_live) + 2;
135+ bitmap_clear (&regs_live);
136+ edges.release ();
137 }
138
139 if (! flag_ira_loop_pressure)
140--
1412.7.4
142
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch
new file mode 100644
index 00000000..b5ee2c8c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch
@@ -0,0 +1,69 @@
1From 8f8c6cd35a2cf79449c0155fa865a665d730e541 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 18 Jan 2017 11:25:48 +0530
4Subject: [PATCH 28/63] [Patch, microblaze]: Correct the const high double
5 immediate value With this patch the loading of the DI mode immediate values
6 will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE
7 functions, as CONST_DOUBLE_HIGH was returning the sign extension value even
8 of the unsigned long long constants also
9
10Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
11 Ajit Agarwal <ajitkum@xilinx.com>
12
13ChangeLog:
142016-02-03 Nagaraju Mekala <nmekala@xilix.com>
15 Ajit Agarwal <ajitkum@xilinx.com>
16
17 *microblaze.c (print_operand): Use REAL_VALUE_FROM_CONST_DOUBLE &
18 REAL_VALUE_TO_TARGET_DOUBLE
19 *long.c (new): Added new testcase
20---
21 gcc/config/microblaze/microblaze.c | 8 ++++++--
22 gcc/testsuite/gcc.target/microblaze/long.c | 10 ++++++++++
23 2 files changed, 16 insertions(+), 2 deletions(-)
24 create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c
25
26diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
27index ae7d5dd..002d7a5 100644
28--- a/gcc/config/microblaze/microblaze.c
29+++ b/gcc/config/microblaze/microblaze.c
30@@ -2594,14 +2594,18 @@ print_operand (FILE * file, rtx op, int letter)
31 else if (letter == 'h' || letter == 'j')
32 {
33 long val[2];
34+ long l[2];
35 if (code == CONST_DOUBLE)
36 {
37 if (GET_MODE (op) == DFmode)
38 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
39 else
40 {
41- val[0] = CONST_DOUBLE_HIGH (op);
42- val[1] = CONST_DOUBLE_LOW (op);
43+ REAL_VALUE_TYPE rv;
44+ REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
45+ REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
46+ val[1] = l[WORDS_BIG_ENDIAN == 0];
47+ val[0] = l[WORDS_BIG_ENDIAN != 0];
48 }
49 }
50 else if (code == CONST_INT)
51diff --git a/gcc/testsuite/gcc.target/microblaze/long.c b/gcc/testsuite/gcc.target/microblaze/long.c
52new file mode 100644
53index 0000000..4d45186
54--- /dev/null
55+++ b/gcc/testsuite/gcc.target/microblaze/long.c
56@@ -0,0 +1,10 @@
57+/* { dg-options "-O0" } */
58+#define BASEADDR 0xF0000000ULL
59+int main ()
60+{
61+ unsigned long long start;
62+ start = (unsigned long long) BASEADDR;
63+ return 0;
64+}
65+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */
66+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */
67--
682.7.4
69
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
new file mode 100644
index 00000000..cbfc98de
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
@@ -0,0 +1,36 @@
1From 30402c3bcfeb8a93656957b22558997b65d69cb8 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 18 Jan 2017 11:49:58 +0530
4Subject: [PATCH 29/63] [Fix, microblaze]: Fix internal compiler error with
5 msmall-divides This patch will fix the internal error
6 microblaze_expand_divide function which comes because of rtx PLUS where the
7 mem_rtx is of type SI and the operand is of type QImode. This patch modifies
8 the mem_rtx as QImode and Plus as QImode to fix the error.
9
10Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
11 Ajit Agarwal <ajitkum@xilinx.com>
12ChangeLog:
13 2016-02-23 Nagaraju Mekala <nmekala@xilix.com>
14 Ajit Agarwal <ajitkum@xilinx.com>
15
16 *microblaze.c (microblaze_expand_divide): Update
17---
18 gcc/config/microblaze/microblaze.c | 2 +-
19 1 file changed, 1 insertion(+), 1 deletion(-)
20
21diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
22index 002d7a5..c662952 100644
23--- a/gcc/config/microblaze/microblaze.c
24+++ b/gcc/config/microblaze/microblaze.c
25@@ -3909,7 +3909,7 @@ microblaze_expand_divide (rtx operands[])
26 emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
27 emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
28 mem_rtx = gen_rtx_MEM (QImode,
29- gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
30+ gen_rtx_PLUS (QImode, regt1, div_table_rtx));
31
32 insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
33 jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
34--
352.7.4
36
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
new file mode 100644
index 00000000..fce06359
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
@@ -0,0 +1,45 @@
1From 5ac80cf926c4dc96cbfd189f02c9250865b52dd3 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 18 Jan 2017 12:03:39 +0530
4Subject: [PATCH 30/63] [patch,microblaze]: Fix the calculation of high word in
5 a long long 6. .4-bit
6
7This patch will change the calculation of high word in a long long 64-bit.
8Earlier to this patch the high word of long long word (0xF0000000ULL) is
9coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word
10should be 0x00000000 and the low word should be 0xF0000000. This patch
11removes the condition of checking high word = 0 & low word < 0.
12This check is not required for the correctness of calculating 32-bit high
13and low words in a 64-bit long long.
14
15Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
16 Ajit Agarwal <ajitkum@xilinx.com>
17
18ChangeLog:
192016-03-01 Nagaraju Mekala <nmekala@xilix.com>
20 Ajit Agarwal <ajitkum@xilinx.com>
21
22 *config/microblaze/microblaze.c (print_operand): Remove the condition of checking
23 high word = 0 & low word < 0.
24 *testsuite/gcc.target/microblaze/others/long.c: Add -O0 option.
25---
26 gcc/config/microblaze/microblaze.c | 3 ---
27 1 file changed, 3 deletions(-)
28
29diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
30index c662952..8013a2c 100644
31--- a/gcc/config/microblaze/microblaze.c
32+++ b/gcc/config/microblaze/microblaze.c
33@@ -2612,9 +2612,6 @@ print_operand (FILE * file, rtx op, int letter)
34 {
35 val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
36 val[1] = INTVAL (op) & 0x00000000ffffffffLL;
37- if (val[0] == 0 && val[1] < 0)
38- val[0] = -1;
39-
40 }
41 fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
42 }
43--
442.7.4
45
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0031-Patch-microblaze-Add-new-bit-field-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0031-Patch-microblaze-Add-new-bit-field-instructions.patch
new file mode 100644
index 00000000..cbf64d97
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0031-Patch-microblaze-Add-new-bit-field-instructions.patch
@@ -0,0 +1,120 @@
1From 45deb5bd3ae8c3db360ef181c9873e37d2288848 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 18 Jan 2017 12:14:51 +0530
4Subject: [PATCH 31/63] [Patch, microblaze]: Add new bit-field instructions
5 This patches adds new bsefi and bsifi instructions. BSEFI- The instruction
6 shall extract a bit field from a register and place it right-adjusted in the
7 destination register. The other bits in the destination register shall be set
8 to zero BSIFI- The instruction shall insert a right-adjusted bit field from a
9 register at another position in the destination register. The rest of the
10 bits in the destination register shall be unchanged
11
12Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
13
14ChangeLog:
15 2016-02-03 Nagaraju Mekala <nmekala@xilix.com>
16
17 *microblaze.md (Update): Added new patterns
18---
19 gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++++++++++
20 1 file changed, 73 insertions(+)
21
22diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
23index b7c16ac..67b298a 100644
24--- a/gcc/config/microblaze/microblaze.md
25+++ b/gcc/config/microblaze/microblaze.md
26@@ -982,6 +982,8 @@
27 (set_attr "mode" "DI")
28 (set_attr "length" "20,20,20")])
29
30+
31+
32 ;;----------------------------------------------------------------
33 ;; Data movement
34 ;;----------------------------------------------------------------
35@@ -1776,6 +1778,7 @@
36 (set_attr "length" "28")]
37 )
38
39+
40 ;;----------------------------------------------------------------
41 ;; Setting a register from an integer comparison.
42 ;;----------------------------------------------------------------
43@@ -2489,4 +2492,74 @@
44 DONE;
45 }")
46
47+(define_expand "extvsi"
48+ [(set (match_operand:SI 0 "register_operand" "r")
49+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
50+ (match_operand:SI 2 "immediate_operand" "I")
51+ (match_operand:SI 3 "immediate_operand" "I")))]
52+"TARGET_HAS_BITFIELD"
53+"
54+{
55+ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
56+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
57+
58+ if ((len == 0) || (pos + len > 32) )
59+ FAIL;
60+
61+ ;;if (!register_operand (operands[1], VOIDmode))
62+ ;; FAIL;
63+ if (operands[0] == operands[1])
64+ FAIL;
65+ if (GET_CODE (operands[1]) == ASHIFT)
66+ FAIL;
67+;; operands[2] = GEN_INT(INTVAL(operands[2])+1 );
68+ emit_insn (gen_extv_32 (operands[0], operands[1],
69+ operands[2], operands[3]));
70+ DONE;
71+}")
72+
73+(define_insn "extv_32"
74+ [(set (match_operand:SI 0 "register_operand" "=r")
75+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
76+ (match_operand:SI 2 "immediate_operand" "I")
77+ (match_operand:SI 3 "immediate_operand" "I")))]
78+ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0)
79+ && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
80+ "bsefi %0,%1,%2,%3"
81+ [(set_attr "type" "bshift")
82+ (set_attr "length" "4")])
83+
84+(define_expand "insvsi"
85+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
86+ (match_operand:SI 1 "immediate_operand" "I")
87+ (match_operand:SI 2 "immediate_operand" "I"))
88+ (match_operand:SI 3 "register_operand" "r"))]
89+ "TARGET_HAS_BITFIELD"
90+ "
91+{
92+ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
93+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
94+
95+ if (len <= 0 || pos + len > 32)
96+ FAIL;
97+
98+ ;;if (!register_operand (operands[0], VOIDmode))
99+ ;; FAIL;
100+
101+ emit_insn (gen_insv_32 (operands[0], operands[1],
102+ operands[2], operands[3]));
103+ DONE;
104+}")
105+
106+(define_insn "insv_32"
107+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
108+ (match_operand:SI 1 "immediate_operand" "I")
109+ (match_operand:SI 2 "immediate_operand" "I"))
110+ (match_operand:SI 3 "register_operand" "r"))]
111+ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0
112+ && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
113+ "bsifi %0, %3, %1, %2"
114+ [(set_attr "type" "bshift")
115+ (set_attr "length" "4")])
116+
117 (include "sync.md")
118--
1192.7.4
120
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
new file mode 100644
index 00000000..86df58b3
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
@@ -0,0 +1,247 @@
1From bc95cc12b2c4d96ea709eefc4b99181b8c40b19c Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 18 Jan 2017 12:42:10 +0530
4Subject: [PATCH 32/63] [Patch, microblaze]: Fix bug in MB version calculation
5 This patch fixes the bug in microblaze_version_to_int function. Earlier the
6 conversion of vXX.YY.Z to int has a bug which is fixed now.
7
8Signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com>
9 Nagaraju Mekala <nmekala@xilix.com>
10---
11 gcc/config/microblaze/microblaze.c | 147 ++++++++++++++++++-------------------
12 1 file changed, 70 insertions(+), 77 deletions(-)
13
14diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
15index 8013a2c..3f68ef0 100644
16--- a/gcc/config/microblaze/microblaze.c
17+++ b/gcc/config/microblaze/microblaze.c
18@@ -239,6 +239,63 @@ section *sdata2_section;
19 #define TARGET_HAVE_TLS true
20 #endif
21
22+/* Convert a version number of the form "vX.YY.Z" to an integer encoding
23+ for easier range comparison. */
24+static int
25+microblaze_version_to_int (const char *version)
26+{
27+ const char *p, *v;
28+ const char *tmpl = "vXX.YY.Z";
29+ int iver1 =0, iver2 =0, iver3 =0;
30+
31+ p = version;
32+ v = tmpl;
33+
34+ while (*p)
35+ {
36+ if (*v == 'X')
37+ { /* Looking for major */
38+ if (*p == '.')
39+ {
40+ *v++;
41+ }
42+ else
43+ {
44+ if (!(*p >= '0' && *p <= '9'))
45+ return -1;
46+ iver1 += (int) (*p - '0');
47+ iver1 *= 1000;
48+ }
49+ }
50+ else if (*v == 'Y')
51+ { /* Looking for minor */
52+ if (!(*p >= '0' && *p <= '9'))
53+ return -1;
54+ iver2 += (int) (*p - '0');
55+ iver2 *= 10;
56+ }
57+ else if (*v == 'Z')
58+ { /* Looking for compat */
59+ if (!(*p >= 'a' && *p <= 'z'))
60+ return -1;
61+ iver3 = ((int) (*p)) - 96;
62+ }
63+ else
64+ {
65+ if (*p != *v)
66+ return -1;
67+ }
68+
69+ v++;
70+ p++;
71+ }
72+
73+ if (*p)
74+ return -1;
75+
76+ return iver1 + iver2 + iver3;
77+}
78+
79 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
80 static bool
81 microblaze_const_double_ok (rtx op, machine_mode mode)
82@@ -1338,8 +1395,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
83 {
84 if (TARGET_BARREL_SHIFT)
85 {
86- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
87- >= 0)
88+ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
89 *total = COSTS_N_INSNS (1);
90 else
91 *total = COSTS_N_INSNS (2);
92@@ -1400,8 +1456,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
93 }
94 else if (!TARGET_SOFT_MUL)
95 {
96- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
97- >= 0)
98+ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
99 *total = COSTS_N_INSNS (1);
100 else
101 *total = COSTS_N_INSNS (3);
102@@ -1682,72 +1737,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
103 return 0;
104 }
105
106-/* Convert a version number of the form "vX.YY.Z" to an integer encoding
107- for easier range comparison. */
108-static int
109-microblaze_version_to_int (const char *version)
110-{
111- const char *p, *v;
112- const char *tmpl = "vXX.YY.Z";
113- int iver = 0;
114-
115- p = version;
116- v = tmpl;
117-
118- while (*p)
119- {
120- if (*v == 'X')
121- { /* Looking for major */
122- if (*p == '.')
123- {
124- v++;
125- }
126- else
127- {
128- if (!(*p >= '0' && *p <= '9'))
129- return -1;
130- iver += (int) (*p - '0');
131- iver *= 10;
132- }
133- }
134- else if (*v == 'Y')
135- { /* Looking for minor */
136- if (!(*p >= '0' && *p <= '9'))
137- return -1;
138- iver += (int) (*p - '0');
139- iver *= 10;
140- }
141- else if (*v == 'Z')
142- { /* Looking for compat */
143- if (!(*p >= 'a' && *p <= 'z'))
144- return -1;
145- iver *= 10;
146- iver += (int) (*p - 'a');
147- }
148- else
149- {
150- if (*p != *v)
151- return -1;
152- }
153-
154- v++;
155- p++;
156- }
157-
158- if (*p)
159- return -1;
160-
161- return iver;
162-}
163-
164-
165 static void
166 microblaze_option_override (void)
167 {
168 register int i, start;
169 register int regno;
170 register machine_mode mode;
171- int ver;
172+ int ver,ver_int;
173
174 microblaze_section_threshold = (global_options_set.x_g_switch_value
175 ? g_switch_value
176@@ -1768,13 +1764,13 @@ microblaze_option_override (void)
177 /* Check the MicroBlaze CPU version for any special action to be done. */
178 if (microblaze_select_cpu == NULL)
179 microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU;
180- ver = microblaze_version_to_int (microblaze_select_cpu);
181- if (ver == -1)
182+ ver_int = microblaze_version_to_int (microblaze_select_cpu);
183+ if (ver_int == -1)
184 {
185 error ("%qs is an invalid argument to %<-mcpu=%>", microblaze_select_cpu);
186 }
187
188- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a");
189+ ver = ver_int - microblaze_version_to_int("v3.00.a");
190 if (ver < 0)
191 {
192 /* No hardware exceptions in earlier versions. So no worries. */
193@@ -1785,8 +1781,7 @@ microblaze_option_override (void)
194 microblaze_pipe = MICROBLAZE_PIPE_3;
195 }
196 else if (ver == 0
197- || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b")
198- == 0))
199+ || (ver_int == microblaze_version_to_int("v4.00.b")))
200 {
201 #if 0
202 microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY);
203@@ -1803,11 +1798,9 @@ microblaze_option_override (void)
204 #endif
205 microblaze_no_unsafe_delay = 0;
206 microblaze_pipe = MICROBLAZE_PIPE_5;
207- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0
208- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
209- "v5.00.b") == 0
210- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
211- "v5.00.c") == 0)
212+ if ((ver_int == microblaze_version_to_int("v5.00.a"))
213+ || (ver_int == microblaze_version_to_int("v5.00.b"))
214+ || (ver_int == microblaze_version_to_int("v5.00.c")))
215 {
216 /* Pattern compares are to be turned on by default only when
217 compiling for MB v5.00.'z'. */
218@@ -1815,7 +1808,7 @@ microblaze_option_override (void)
219 }
220 }
221
222- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a");
223+ ver = ver_int - microblaze_version_to_int("v6.00.a");
224 if (ver < 0)
225 {
226 if (TARGET_MULTIPLY_HIGH)
227@@ -1824,7 +1817,7 @@ microblaze_option_override (void)
228 "%<-mcpu=v6.00.a%> or greater");
229 }
230
231- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a");
232+ ver = ver_int - microblaze_version_to_int("v8.10.a");
233 microblaze_has_clz = 1;
234 if (ver < 0)
235 {
236@@ -1833,7 +1826,7 @@ microblaze_option_override (void)
237 }
238
239 /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */
240- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a");
241+ ver = ver_int - microblaze_version_to_int("v8.30.a");
242 if (ver < 0)
243 {
244 if (TARGET_REORDER == 1)
245--
2462.7.4
247
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0033-Fixing-the-bug-in-the-bit-field-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0033-Fixing-the-bug-in-the-bit-field-instruction.patch
new file mode 100644
index 00000000..68f70ae8
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0033-Fixing-the-bug-in-the-bit-field-instruction.patch
@@ -0,0 +1,48 @@
1From 51da0572e0650378e422030b26d1258c8fc76df6 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 18 Jan 2017 13:57:48 +0530
4Subject: [PATCH 33/63] Fixing the bug in the bit-field instruction. Bit field
5 instruction should be generated only if mcpu >10.0
6
7---
8 gcc/config/microblaze/microblaze.c | 3 +++
9 gcc/config/microblaze/microblaze.h | 2 ++
10 2 files changed, 5 insertions(+)
11
12diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
13index 3f68ef0..a37f08eea 100644
14--- a/gcc/config/microblaze/microblaze.c
15+++ b/gcc/config/microblaze/microblaze.c
16@@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay;
17 /* Set to one if the targeted core has the CLZ insn. */
18 int microblaze_has_clz = 0;
19
20+/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
21+int microblaze_has_bitfield = 0;
22+
23 /* Which CPU pipeline do we use. We haven't really standardized on a CPU
24 version having only a particular type of pipeline. There can still be
25 options on the CPU to scale pipeline features up or down. :(
26diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
27index bf7f3b4..1d05e6e 100644
28--- a/gcc/config/microblaze/microblaze.h
29+++ b/gcc/config/microblaze/microblaze.h
30@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
31
32 extern int microblaze_no_unsafe_delay;
33 extern int microblaze_has_clz;
34+extern int microblaze_has_bitfield;
35 extern enum pipeline_type microblaze_pipe;
36
37 #define OBJECT_FORMAT_ELF
38@@ -62,6 +63,7 @@ extern enum pipeline_type microblaze_pipe;
39
40 /* Do we have CLZ? */
41 #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz)
42+#define TARGET_HAS_BITFIELD (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
43
44 /* The default is to support PIC. */
45 #define TARGET_SUPPORTS_PIC 1
46--
472.7.4
48
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch
new file mode 100644
index 00000000..04326205
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch
@@ -0,0 +1,32 @@
1From 132b913b721f66c5db17f62dd5559bbca11bb875 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 18 Jan 2017 20:57:10 +0530
4Subject: [PATCH 34/63] [Patch, microblaze]: Macros used in Xilinx internal
5 patches has been removed in gcc 6.2 version so modified the code accordingly.
6
7---
8 gcc/config/microblaze/microblaze.c | 8 +++-----
9 1 file changed, 3 insertions(+), 5 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
12index a37f08eea..71640e5 100644
13--- a/gcc/config/microblaze/microblaze.c
14+++ b/gcc/config/microblaze/microblaze.c
15@@ -2597,11 +2597,9 @@ print_operand (FILE * file, rtx op, int letter)
16 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
17 else
18 {
19- REAL_VALUE_TYPE rv;
20- REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
21- REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
22- val[1] = l[WORDS_BIG_ENDIAN == 0];
23- val[0] = l[WORDS_BIG_ENDIAN != 0];
24+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
25+ val[1] = l[WORDS_BIG_ENDIAN == 0];
26+ val[0] = l[WORDS_BIG_ENDIAN != 0];
27 }
28 }
29 else if (code == CONST_INT)
30--
312.7.4
32
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0035-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0035-Fixing-the-issue-with-the-builtin_alloc.patch
new file mode 100644
index 00000000..91ac0d02
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0035-Fixing-the-issue-with-the-builtin_alloc.patch
@@ -0,0 +1,44 @@
1From e672184af6a43b773131181270c7a8c5c5273bd8 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Thu, 23 Feb 2017 17:09:04 +0530
4Subject: [PATCH 35/63] Fixing the issue with the builtin_alloc. register r18
5 was not properly handling the stack pattern which was resolved by using free
6 available register
7
8signed-off-by:nagaraju mekala <nmekala@xilinx.com>
9---
10 gcc/config/microblaze/microblaze.md | 8 ++++----
11 1 file changed, 4 insertions(+), 4 deletions(-)
12
13diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
14index 67b298a..7bae957 100644
15--- a/gcc/config/microblaze/microblaze.md
16+++ b/gcc/config/microblaze/microblaze.md
17@@ -2078,10 +2078,10 @@
18 ""
19 {
20 rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
21- rtx rtmp = gen_rtx_REG (SImode, R_TMP);
22+ rtx reg = gen_reg_rtx (Pmode);
23 rtx neg_op0;
24
25- emit_move_insn (rtmp, retaddr);
26+ emit_move_insn (reg, retaddr);
27 if (GET_CODE (operands[1]) != CONST_INT)
28 {
29 neg_op0 = gen_reg_rtx (Pmode);
30@@ -2090,9 +2090,9 @@
31 neg_op0 = GEN_INT (- INTVAL (operands[1]));
32
33 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
34- emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp);
35+ emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg);
36 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
37- emit_insn (gen_rtx_CLOBBER (SImode, rtmp));
38+ emit_insn (gen_rtx_CLOBBER (SImode, reg));
39 DONE;
40 }
41 )
42--
432.7.4
44
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch
new file mode 100644
index 00000000..7079789f
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch
@@ -0,0 +1,49 @@
1From ac30efb4a5f5b6d289fdd27b268c2095d60dcb42 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 2 Mar 2017 19:02:31 +0530
4Subject: [PATCH 36/63] [Patch,Microblaze]:reverting the cost check before
5 propagating constants.
6
7---
8 gcc/cprop.c | 4 ++++
9 1 file changed, 4 insertions(+)
10
11diff --git a/gcc/cprop.c b/gcc/cprop.c
12index 65c0130..42bcc81 100644
13--- a/gcc/cprop.c
14+++ b/gcc/cprop.c
15@@ -733,6 +733,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
16 int success = 0;
17 rtx set = single_set (insn);
18
19+#if 0
20 bool check_rtx_costs = true;
21 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
22 int old_cost = set ? set_rtx_cost (set, speed) : 0;
23@@ -744,6 +745,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
24 && (GET_CODE (XEXP (note, 0)) == CONST
25 || CONSTANT_P (XEXP (note, 0)))))
26 check_rtx_costs = false;
27+#endif
28
29 /* Usually we substitute easy stuff, so we won't copy everything.
30 We however need to take care to not duplicate non-trivial CONST
31@@ -752,6 +754,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
32
33 validate_replace_src_group (from, to, insn);
34
35+#if 0
36 /* If TO is a constant, check the cost of the set after propagation
37 to the cost of the set before the propagation. If the cost is
38 higher, then do not replace FROM with TO. */
39@@ -764,6 +767,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
40 return false;
41 }
42
43+#endif
44
45 if (num_changes_pending () && apply_change_group ())
46 success = 1;
47--
482.7.4
49
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
new file mode 100644
index 00000000..ba0f8e80
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
@@ -0,0 +1,80 @@
1From f436198b817f33d56aaddb88ff629378498de489 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Mon, 19 Feb 2018 18:06:16 +0530
4Subject: [PATCH 37/63] [Patch,Microblaze]: update in constraints for bitfield
5 insert and extract instructions.
6
7---
8 gcc/config/microblaze/microblaze.md | 43 ++++++-------------------------------
9 1 file changed, 7 insertions(+), 36 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
12index 7bae957..6101387 100644
13--- a/gcc/config/microblaze/microblaze.md
14+++ b/gcc/config/microblaze/microblaze.md
15@@ -2492,33 +2492,17 @@
16 DONE;
17 }")
18
19-(define_expand "extvsi"
20+(define_expand "extzvsi"
21 [(set (match_operand:SI 0 "register_operand" "r")
22 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
23 (match_operand:SI 2 "immediate_operand" "I")
24 (match_operand:SI 3 "immediate_operand" "I")))]
25 "TARGET_HAS_BITFIELD"
26-"
27-{
28- unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
29- unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
30-
31- if ((len == 0) || (pos + len > 32) )
32- FAIL;
33-
34- ;;if (!register_operand (operands[1], VOIDmode))
35- ;; FAIL;
36- if (operands[0] == operands[1])
37- FAIL;
38- if (GET_CODE (operands[1]) == ASHIFT)
39- FAIL;
40-;; operands[2] = GEN_INT(INTVAL(operands[2])+1 );
41- emit_insn (gen_extv_32 (operands[0], operands[1],
42- operands[2], operands[3]));
43- DONE;
44-}")
45+""
46+)
47
48-(define_insn "extv_32"
49+
50+(define_insn "extzv_32"
51 [(set (match_operand:SI 0 "register_operand" "=r")
52 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
53 (match_operand:SI 2 "immediate_operand" "I")
54@@ -2535,21 +2519,8 @@
55 (match_operand:SI 2 "immediate_operand" "I"))
56 (match_operand:SI 3 "register_operand" "r"))]
57 "TARGET_HAS_BITFIELD"
58- "
59-{
60- unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
61- unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
62-
63- if (len <= 0 || pos + len > 32)
64- FAIL;
65-
66- ;;if (!register_operand (operands[0], VOIDmode))
67- ;; FAIL;
68-
69- emit_insn (gen_insv_32 (operands[0], operands[1],
70- operands[2], operands[3]));
71- DONE;
72-}")
73+""
74+)
75
76 (define_insn "insv_32"
77 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
78--
792.7.4
80
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
new file mode 100644
index 00000000..2b90880f
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
@@ -0,0 +1,38 @@
1From 89aa1907ab0abad38e394f46f7e5f577bdb26498 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Mon, 4 Jun 2018 10:10:18 +0530
4Subject: [PATCH 38/63] [Patch,Microblaze] : Removed fsqrt generation for
5 double values.
6
7---
8 gcc/config/microblaze/microblaze.md | 14 --------------
9 1 file changed, 14 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
12index 6101387..eb01221 100644
13--- a/gcc/config/microblaze/microblaze.md
14+++ b/gcc/config/microblaze/microblaze.md
15@@ -526,20 +526,6 @@
16 (set_attr "mode" "SF")
17 (set_attr "length" "4")])
18
19-(define_insn "sqrtdf2"
20- [(set (match_operand:DF 0 "register_operand" "=d")
21- (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
22- "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
23- {
24- if (REGNO (operands[0]) == REGNO (operands[1]))
25- return "fsqrt\t%0,%1";
26- else
27- return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
28- }
29- [(set_attr "type" "fsqrt")
30- (set_attr "mode" "SF")
31- (set_attr "length" "4")])
32-
33 (define_insn "fix_truncsfsi2"
34 [(set (match_operand:SI 0 "register_operand" "=d")
35 (fix:SI (match_operand:SF 1 "register_operand" "d")))]
36--
372.7.4
38
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0039-Intial-commit-of-64-bit-Microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0039-Intial-commit-of-64-bit-Microblaze.patch
new file mode 100644
index 00000000..f524cba2
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0039-Intial-commit-of-64-bit-Microblaze.patch
@@ -0,0 +1,804 @@
1From 68359cc8e82f63d01a77c39c68e782e6757cd71e Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Tue, 3 Apr 2018 16:48:39 +0530
4Subject: [PATCH 39/63] Intial commit of 64-bit Microblaze
5
6Conflicts:
7 gcc/config/microblaze/microblaze.opt
8---
9 gcc/config/microblaze/microblaze-protos.h | 1 +
10 gcc/config/microblaze/microblaze.c | 109 +++++++--
11 gcc/config/microblaze/microblaze.h | 4 +-
12 gcc/config/microblaze/microblaze.md | 370 +++++++++++++++++++++++++++++-
13 gcc/config/microblaze/microblaze.opt | 7 +-
14 gcc/config/microblaze/t-microblaze | 7 +-
15 6 files changed, 460 insertions(+), 38 deletions(-)
16
17diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
18index bdc9b69..7d6c189 100644
19--- a/gcc/config/microblaze/microblaze-protos.h
20+++ b/gcc/config/microblaze/microblaze-protos.h
21@@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *);
22 extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
23 extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
24 extern void microblaze_expand_conditional_branch_sf (rtx *);
25+extern void microblaze_expand_conditional_branch_df (rtx *);
26 extern int microblaze_can_use_return_insn (void);
27 extern void print_operand (FILE *, rtx, int);
28 extern void print_operand_address (FILE *, rtx);
29diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
30index 71640e5..f740f5c 100644
31--- a/gcc/config/microblaze/microblaze.c
32+++ b/gcc/config/microblaze/microblaze.c
33@@ -3570,11 +3570,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
34 op0 = operands[0];
35 op1 = operands[1];
36
37- if (!register_operand (op0, SImode)
38- && !register_operand (op1, SImode)
39+ if (!register_operand (op0, mode)
40+ && !register_operand (op1, mode)
41 && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0))
42 {
43- rtx temp = force_reg (SImode, op1);
44+ rtx temp = force_reg (mode, op1);
45 emit_move_insn (op0, temp);
46 return true;
47 }
48@@ -3639,12 +3639,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
49 && (flag_pic == 2 || microblaze_tls_symbol_p (p0)
50 || !SMALL_INT (p1)))))
51 {
52- rtx temp = force_reg (SImode, p0);
53+ rtx temp = force_reg (mode, p0);
54 rtx temp2 = p1;
55
56 if (flag_pic && reload_in_progress)
57 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
58- emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2));
59+ emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2));
60 return true;
61 }
62 }
63@@ -3775,7 +3775,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
64 rtx cmp_op0 = operands[1];
65 rtx cmp_op1 = operands[2];
66 rtx label1 = operands[3];
67- rtx comp_reg = gen_reg_rtx (SImode);
68+ rtx comp_reg = gen_reg_rtx (mode);
69 rtx condition;
70
71 gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
72@@ -3784,23 +3784,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
73 if (cmp_op1 == const0_rtx)
74 {
75 comp_reg = cmp_op0;
76- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
77- emit_jump_insn (gen_condjump (condition, label1));
78+ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
79+ if (mode == SImode)
80+ emit_jump_insn (gen_condjump (condition, label1));
81+ else
82+ emit_jump_insn (gen_long_condjump (condition, label1));
83+
84 }
85
86 else if (code == EQ || code == NE)
87 {
88 /* Use xor for equal/not-equal comparison. */
89- emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
90- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
91- emit_jump_insn (gen_condjump (condition, label1));
92+ if (mode == SImode)
93+ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
94+ else
95+ emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
96+ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
97+ if (mode == SImode)
98+ emit_jump_insn (gen_condjump (condition, label1));
99+ else
100+ emit_jump_insn (gen_long_condjump (condition, label1));
101 }
102 else
103 {
104 /* Generate compare and branch in single instruction. */
105 cmp_op1 = force_reg (mode, cmp_op1);
106 condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
107- emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
108+ if (mode == SImode)
109+ emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
110+ else
111+ emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1));
112 }
113 }
114
115@@ -3811,7 +3824,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
116 rtx cmp_op0 = operands[1];
117 rtx cmp_op1 = operands[2];
118 rtx label1 = operands[3];
119- rtx comp_reg = gen_reg_rtx (SImode);
120+ rtx comp_reg = gen_reg_rtx (mode);
121 rtx condition;
122
123 gcc_assert ((GET_CODE (cmp_op0) == REG)
124@@ -3822,30 +3835,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
125 {
126 comp_reg = cmp_op0;
127 condition = gen_rtx_fmt_ee (signed_condition (code),
128- SImode, comp_reg, const0_rtx);
129- emit_jump_insn (gen_condjump (condition, label1));
130+ mode, comp_reg, const0_rtx);
131+ if (mode == SImode)
132+ emit_jump_insn (gen_condjump (condition, label1));
133+ else
134+ emit_jump_insn (gen_long_condjump (condition, label1));
135 }
136 else if (code == EQ)
137 {
138- emit_insn (gen_seq_internal_pat (comp_reg,
139- cmp_op0, cmp_op1));
140- condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx);
141- emit_jump_insn (gen_condjump (condition, label1));
142+ if (mode == SImode)
143+ {
144+ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
145+ cmp_op1));
146+ }
147+ else
148+ {
149+ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
150+ cmp_op1));
151+ }
152+ condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
153+ if (mode == SImode)
154+ emit_jump_insn (gen_condjump (condition, label1));
155+ else
156+ emit_jump_insn (gen_long_condjump (condition, label1));
157+
158 }
159 else if (code == NE)
160 {
161- emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
162- cmp_op1));
163- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
164- emit_jump_insn (gen_condjump (condition, label1));
165+ if (mode == SImode)
166+ {
167+ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
168+ cmp_op1));
169+ }
170+ else
171+ {
172+ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
173+ cmp_op1));
174+ }
175+ condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
176+ if (mode == SImode)
177+ emit_jump_insn (gen_condjump (condition, label1));
178+ else
179+ emit_jump_insn (gen_long_condjump (condition, label1));
180 }
181 else
182 {
183 /* Generate compare and branch in single instruction. */
184 cmp_op1 = force_reg (mode, cmp_op1);
185 condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
186- emit_jump_insn (gen_branch_compare (condition, cmp_op0,
187- cmp_op1, label1));
188+ if (mode == SImode)
189+ emit_jump_insn (gen_branch_compare (condition, cmp_op0,
190+ cmp_op1, label1));
191+ else
192+ {
193+ emit_jump_insn (gen_long_branch_compare (condition, cmp_op0,
194+ cmp_op1, label1));
195+ }
196+
197 }
198 }
199
200@@ -3862,6 +3908,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
201 emit_jump_insn (gen_condjump (condition, operands[3]));
202 }
203
204+void
205+microblaze_expand_conditional_branch_df (rtx operands[])
206+{
207+ rtx condition;
208+ rtx cmp_op0 = XEXP (operands[0], 0);
209+ rtx cmp_op1 = XEXP (operands[0], 1);
210+ rtx comp_reg = gen_reg_rtx (DImode);
211+
212+ emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
213+ condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
214+ emit_jump_insn (gen_long_condjump (condition, operands[3]));
215+}
216+
217 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
218
219 static bool
220diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
221index 1d05e6e..2ca44f5 100644
222--- a/gcc/config/microblaze/microblaze.h
223+++ b/gcc/config/microblaze/microblaze.h
224@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe;
225 #define ASM_SPEC "\
226 %(target_asm_spec) \
227 %{mbig-endian:-EB} \
228+%{m64:-m64} \
229 %{mlittle-endian:-EL}"
230
231 /* Extra switches sometimes passed to the linker. */
232@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe;
233 #define LINK_SPEC "%{shared:-shared} -N -relax \
234 %{mbig-endian:-EB --oformat=elf32-microblaze} \
235 %{mlittle-endian:-EL --oformat=elf32-microblazeel} \
236+ %{m64:-EL --oformat=elf64-microblazeel} \
237 %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
238 %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
239 %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
240@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe;
241 #define MIN_UNITS_PER_WORD 4
242 #define INT_TYPE_SIZE 32
243 #define SHORT_TYPE_SIZE 16
244-#define LONG_TYPE_SIZE 32
245+#define LONG_TYPE_SIZE 64
246 #define LONG_LONG_TYPE_SIZE 64
247 #define FLOAT_TYPE_SIZE 32
248 #define DOUBLE_TYPE_SIZE 64
249diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
250index eb01221..dbb592e 100644
251--- a/gcc/config/microblaze/microblaze.md
252+++ b/gcc/config/microblaze/microblaze.md
253@@ -497,7 +497,6 @@
254 (set_attr "mode" "SF")
255 (set_attr "length" "4")])
256
257-
258 (define_insn "divsf3"
259 [(set (match_operand:SF 0 "register_operand" "=d")
260 (div:SF (match_operand:SF 1 "register_operand" "d")
261@@ -508,6 +507,7 @@
262 (set_attr "mode" "SF")
263 (set_attr "length" "4")])
264
265+
266 (define_insn "sqrtsf2"
267 [(set (match_operand:SF 0 "register_operand" "=d")
268 (sqrt:SF (match_operand:SF 1 "register_operand" "d")))]
269@@ -562,6 +562,18 @@
270
271 ;; Adding 2 DI operands in register or reg/imm
272
273+(define_insn "adddi3_long"
274+ [(set (match_operand:DI 0 "register_operand" "=d,d")
275+ (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
276+ (match_operand:DI 2 "arith_plus_operand" "d,K")))]
277+ "TARGET_MB_64"
278+ "@
279+ addlk\t%0,%z1,%2
280+ addlik\t%0,%z1,%2"
281+ [(set_attr "type" "arith,arith")
282+ (set_attr "mode" "DI,DI")
283+ (set_attr "length" "4,4")])
284+
285 (define_insn "adddi3"
286 [(set (match_operand:DI 0 "register_operand" "=d,d")
287 (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
288@@ -606,6 +618,18 @@
289 ;; Double Precision Subtraction
290 ;;----------------------------------------------------------------
291
292+(define_insn "subdi3_long"
293+ [(set (match_operand:DI 0 "register_operand" "=d,d")
294+ (minus:DI (match_operand:DI 1 "register_operand" "d,d")
295+ (match_operand:DI 2 "register_operand" "d,n")))]
296+ "TARGET_MB_64"
297+ "@
298+ rsubl\t%0,%2,%1
299+ addlik\t%0,%z1,-%2"
300+ [(set_attr "type" "darith")
301+ (set_attr "mode" "DI,DI")
302+ (set_attr "length" "4,4")])
303+
304 (define_insn "subdi3"
305 [(set (match_operand:DI 0 "register_operand" "=&d")
306 (minus:DI (match_operand:DI 1 "register_operand" "d")
307@@ -795,6 +819,15 @@
308 (set_attr "mode" "SI")
309 (set_attr "length" "4")])
310
311+(define_insn "negdi2_long"
312+ [(set (match_operand:DI 0 "register_operand" "=d")
313+ (neg:DI (match_operand:DI 1 "register_operand" "d")))]
314+ "TARGET_MB_64"
315+ "rsubl\t%0,%1,r0"
316+ [(set_attr "type" "darith")
317+ (set_attr "mode" "DI")
318+ (set_attr "length" "4")])
319+
320 (define_insn "negdi2"
321 [(set (match_operand:DI 0 "register_operand" "=d")
322 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
323@@ -814,6 +847,15 @@
324 (set_attr "mode" "SI")
325 (set_attr "length" "4")])
326
327+(define_insn "one_cmpldi2_long"
328+ [(set (match_operand:DI 0 "register_operand" "=d")
329+ (not:DI (match_operand:DI 1 "register_operand" "d")))]
330+ "TARGET_MB_64"
331+ "xorli\t%0,%1,-1"
332+ [(set_attr "type" "arith")
333+ (set_attr "mode" "DI")
334+ (set_attr "length" "4")])
335+
336 (define_insn "*one_cmpldi2"
337 [(set (match_operand:DI 0 "register_operand" "=d")
338 (not:DI (match_operand:DI 1 "register_operand" "d")))]
339@@ -840,6 +882,20 @@
340 ;; Logical
341 ;;----------------------------------------------------------------
342
343+(define_insn "anddi3"
344+ [(set (match_operand:DI 0 "register_operand" "=d,d")
345+ (and:DI (match_operand:DI 1 "arith_operand" "d,d")
346+ (match_operand:DI 2 "arith_operand" "d,K")))]
347+ "TARGET_MB_64"
348+ "@
349+ andl\t%0,%1,%2
350+ andli\t%0,%1,%2 #andl1"
351+ ;; andli\t%0,%1,%2 #andl3
352+ ;; andli\t%0,%1,%2 #andl2
353+ [(set_attr "type" "arith,arith")
354+ (set_attr "mode" "DI,DI")
355+ (set_attr "length" "4,4")])
356+
357 (define_insn "andsi3"
358 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
359 (and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
360@@ -855,6 +911,18 @@
361 (set_attr "length" "4,8,8,8")])
362
363
364+(define_insn "iordi3"
365+ [(set (match_operand:DI 0 "register_operand" "=d,d")
366+ (ior:DI (match_operand:DI 1 "arith_operand" "d,d")
367+ (match_operand:DI 2 "arith_operand" "d,K")))]
368+ "TARGET_MB_64"
369+ "@
370+ orl\t%0,%1,%2
371+ orli\t%0,%1,%2 #andl1"
372+ [(set_attr "type" "arith,arith")
373+ (set_attr "mode" "DI,DI")
374+ (set_attr "length" "4,4")])
375+
376 (define_insn "iorsi3"
377 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
378 (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
379@@ -869,6 +937,19 @@
380 (set_attr "mode" "SI,SI,SI,SI")
381 (set_attr "length" "4,8,8,8")])
382
383+(define_insn "xordi3"
384+ [(set (match_operand:DI 0 "register_operand" "=d,d")
385+ (xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
386+ (match_operand:DI 2 "arith_operand" "d,K")))]
387+ "TARGET_MB_64"
388+ "@
389+ xorl\t%0,%1,%2
390+ xorli\t%0,%1,%2 #andl1"
391+ [(set_attr "type" "arith,arith")
392+ (set_attr "mode" "DI,DI")
393+ (set_attr "length" "4,4")])
394+
395+
396 (define_insn "xorsi3"
397 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
398 (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d")
399@@ -937,6 +1018,26 @@
400 (set_attr "mode" "SI")
401 (set_attr "length" "4")])
402
403+;;(define_expand "extendqidi2"
404+;; [(set (match_operand:DI 0 "register_operand" "=d")
405+;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
406+;; "TARGET_MB_64"
407+;; {
408+;; if (GET_CODE (operands[1]) != REG)
409+;; FAIL;
410+;; }
411+;;)
412+
413+
414+;;(define_insn "extendqidi2"
415+;; [(set (match_operand:DI 0 "register_operand" "=d")
416+;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
417+;; "TARGET_MB_64"
418+;; "sextl8\t%0,%1"
419+;; [(set_attr "type" "arith")
420+;; (set_attr "mode" "DI")
421+;; (set_attr "length" "4")])
422+
423 (define_insn "extendhisi2"
424 [(set (match_operand:SI 0 "register_operand" "=d")
425 (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
426@@ -946,6 +1047,16 @@
427 (set_attr "mode" "SI")
428 (set_attr "length" "4")])
429
430+(define_insn "extendhidi2"
431+ [(set (match_operand:DI 0 "register_operand" "=d")
432+ (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
433+ "TARGET_MB_64"
434+ "sextl16\t%0,%1"
435+ [(set_attr "type" "arith")
436+ (set_attr "mode" "DI")
437+ (set_attr "length" "4")])
438+
439+
440 ;; Those for integer source operand are ordered
441 ;; widest source type first.
442
443@@ -1011,7 +1122,6 @@
444 )
445
446
447-
448 (define_insn "*movdi_internal"
449 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
450 (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))]
451@@ -1423,6 +1533,36 @@
452 (set_attr "length" "4,4")]
453 )
454
455+;; Barrel shift left
456+(define_expand "ashldi3"
457+ [(set (match_operand:DI 0 "register_operand" "=&d")
458+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
459+ (match_operand:DI 2 "arith_operand" "")))]
460+"TARGET_MB_64"
461+{
462+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
463+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
464+ {
465+ emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
466+ DONE;
467+ }
468+else
469+ FAIL;
470+}
471+)
472+
473+(define_insn "ashldi3_long"
474+ [(set (match_operand:DI 0 "register_operand" "=d,d")
475+ (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
476+ (match_operand:DI 2 "arith_operand" "I,d")))]
477+ "TARGET_MB_64"
478+ "@
479+ bsllli\t%0,%1,%2
480+ bslll\t%0,%1,%2"
481+ [(set_attr "type" "bshift,bshift")
482+ (set_attr "mode" "DI,DI")
483+ (set_attr "length" "4,4")]
484+)
485 ;; The following patterns apply when there is no barrel shifter present
486
487 (define_insn "*ashlsi3_with_mul_delay"
488@@ -1548,6 +1688,36 @@
489 ;;----------------------------------------------------------------
490 ;; 32-bit right shifts
491 ;;----------------------------------------------------------------
492+;; Barrel shift left
493+(define_expand "ashrdi3"
494+ [(set (match_operand:DI 0 "register_operand" "=&d")
495+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
496+ (match_operand:DI 2 "arith_operand" "")))]
497+"TARGET_MB_64"
498+{
499+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
500+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
501+ {
502+ emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
503+ DONE;
504+ }
505+else
506+ FAIL;
507+}
508+)
509+
510+(define_insn "ashrdi3_long"
511+ [(set (match_operand:DI 0 "register_operand" "=d,d")
512+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
513+ (match_operand:DI 2 "arith_operand" "I,d")))]
514+ "TARGET_MB_64"
515+ "@
516+ bslrai\t%0,%1,%2
517+ bslra\t%0,%1,%2"
518+ [(set_attr "type" "bshift,bshift")
519+ (set_attr "mode" "DI,DI")
520+ (set_attr "length" "4,4")]
521+ )
522 (define_expand "ashrsi3"
523 [(set (match_operand:SI 0 "register_operand" "=&d")
524 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
525@@ -1657,6 +1827,36 @@
526 ;;----------------------------------------------------------------
527 ;; 32-bit right shifts (logical)
528 ;;----------------------------------------------------------------
529+;; Barrel shift left
530+(define_expand "lshrdi3"
531+ [(set (match_operand:DI 0 "register_operand" "=&d")
532+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
533+ (match_operand:DI 2 "arith_operand" "")))]
534+"TARGET_MB_64"
535+{
536+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
537+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
538+ {
539+ emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
540+ DONE;
541+ }
542+else
543+ FAIL;
544+}
545+)
546+
547+(define_insn "lshrdi3_long"
548+ [(set (match_operand:DI 0 "register_operand" "=d,d")
549+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
550+ (match_operand:DI 2 "arith_operand" "I,d")))]
551+ "TARGET_MB_64"
552+ "@
553+ bslrli\t%0,%1,%2
554+ bslrl\t%0,%1,%2"
555+ [(set_attr "type" "bshift,bshift")
556+ (set_attr "mode" "DI,DI")
557+ (set_attr "length" "4,4")]
558+ )
559
560 (define_expand "lshrsi3"
561 [(set (match_operand:SI 0 "register_operand" "=&d")
562@@ -1803,6 +2003,8 @@
563 (set_attr "length" "4")]
564 )
565
566+
567+
568 ;;----------------------------------------------------------------
569 ;; Setting a register from an floating point comparison.
570 ;;----------------------------------------------------------------
571@@ -1818,6 +2020,18 @@
572 (set_attr "length" "4")]
573 )
574
575+(define_insn "cstoredf4"
576+ [(set (match_operand:DI 0 "register_operand" "=r")
577+ (match_operator:DI 1 "ordered_comparison_operator"
578+ [(match_operand:DF 2 "register_operand" "r")
579+ (match_operand:DF 3 "register_operand" "r")]))]
580+ "TARGET_MB_64"
581+ "dcmp.%C1\t%0,%3,%2"
582+ [(set_attr "type" "fcmp")
583+ (set_attr "mode" "DF")
584+ (set_attr "length" "4")]
585+)
586+
587 ;;----------------------------------------------------------------
588 ;; Conditional branches
589 ;;----------------------------------------------------------------
590@@ -1930,6 +2144,115 @@
591 (set_attr "length" "12")]
592 )
593
594+
595+(define_expand "cbranchdi4"
596+ [(set (pc)
597+ (if_then_else (match_operator 0 "ordered_comparison_operator"
598+ [(match_operand:DI 1 "register_operand")
599+ (match_operand:DI 2 "arith_operand" "I,i")])
600+ (label_ref (match_operand 3 ""))
601+ (pc)))]
602+ "TARGET_MB_64"
603+{
604+ microblaze_expand_conditional_branch (DImode, operands);
605+ DONE;
606+})
607+
608+(define_expand "cbranchdi4_reg"
609+ [(set (pc)
610+ (if_then_else (match_operator 0 "ordered_comparison_operator"
611+ [(match_operand:DI 1 "register_operand")
612+ (match_operand:DI 2 "register_operand")])
613+ (label_ref (match_operand 3 ""))
614+ (pc)))]
615+ "TARGET_MB_64"
616+{
617+ microblaze_expand_conditional_branch_reg (DImode, operands);
618+ DONE;
619+})
620+
621+(define_expand "cbranchdf4"
622+ [(set (pc)
623+ (if_then_else (match_operator 0 "ordered_comparison_operator"
624+ [(match_operand:DF 1 "register_operand")
625+ (match_operand:DF 2 "register_operand")])
626+ (label_ref (match_operand 3 ""))
627+ (pc)))]
628+ "TARGET_MB_64"
629+{
630+ microblaze_expand_conditional_branch_df (operands);
631+ DONE;
632+
633+})
634+
635+;; Used to implement comparison instructions
636+(define_expand "long_condjump"
637+ [(set (pc)
638+ (if_then_else (match_operand 0)
639+ (label_ref (match_operand 1))
640+ (pc)))])
641+
642+(define_insn "long_branch_zero"
643+ [(set (pc)
644+ (if_then_else (match_operator:DI 0 "ordered_comparison_operator"
645+ [(match_operand:DI 1 "register_operand" "d")
646+ (const_int 0)])
647+ (match_operand:DI 2 "pc_or_label_operand" "")
648+ (match_operand:DI 3 "pc_or_label_operand" "")))
649+ ]
650+ "TARGET_MB_64"
651+ {
652+ if (operands[3] == pc_rtx)
653+ return "beal%C0i%?\t%z1,%2";
654+ else
655+ return "beal%N0i%?\t%z1,%3";
656+ }
657+ [(set_attr "type" "branch")
658+ (set_attr "mode" "none")
659+ (set_attr "length" "4")]
660+)
661+
662+(define_insn "long_branch_compare"
663+ [(set (pc)
664+ (if_then_else (match_operator:DI 0 "cmp_op"
665+ [(match_operand:DI 1 "register_operand" "d")
666+ (match_operand:DI 2 "register_operand" "d")
667+ ])
668+ (label_ref (match_operand 3))
669+ (pc)))
670+ (clobber(reg:DI R_TMP))]
671+ "TARGET_MB_64"
672+ {
673+ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
674+ enum rtx_code code = GET_CODE (operands[0]);
675+
676+ if (code == GT || code == LE)
677+ {
678+ output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
679+ code = swap_condition (code);
680+ }
681+ else if (code == GTU || code == LEU)
682+ {
683+ output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
684+ code = swap_condition (code);
685+ }
686+ else if (code == GE || code == LT)
687+ {
688+ output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
689+ }
690+ else if (code == GEU || code == LTU)
691+ {
692+ output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
693+ }
694+
695+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
696+ return "beal%C0i%?\tr18,%3";
697+ }
698+ [(set_attr "type" "branch")
699+ (set_attr "mode" "none")
700+ (set_attr "length" "12")]
701+)
702+
703 ;;----------------------------------------------------------------
704 ;; Unconditional branches
705 ;;----------------------------------------------------------------
706@@ -2478,17 +2801,33 @@
707 DONE;
708 }")
709
710-(define_expand "extzvsi"
711+(define_expand "extvsi"
712 [(set (match_operand:SI 0 "register_operand" "r")
713 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
714 (match_operand:SI 2 "immediate_operand" "I")
715 (match_operand:SI 3 "immediate_operand" "I")))]
716 "TARGET_HAS_BITFIELD"
717-""
718-)
719-
720+"
721+{
722+ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
723+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
724+
725+ if ((len == 0) || (pos + len > 32) )
726+ FAIL;
727+
728+ ;;if (!register_operand (operands[1], VOIDmode))
729+ ;; FAIL;
730+ if (operands[0] == operands[1])
731+ FAIL;
732+ if (GET_CODE (operands[1]) == ASHIFT)
733+ FAIL;
734+;; operands[2] = GEN_INT(INTVAL(operands[2])+1 );
735+ emit_insn (gen_extv_32 (operands[0], operands[1],
736+ operands[2], operands[3]));
737+ DONE;
738+}")
739
740-(define_insn "extzv_32"
741+(define_insn "extv_32"
742 [(set (match_operand:SI 0 "register_operand" "=r")
743 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
744 (match_operand:SI 2 "immediate_operand" "I")
745@@ -2505,8 +2844,21 @@
746 (match_operand:SI 2 "immediate_operand" "I"))
747 (match_operand:SI 3 "register_operand" "r"))]
748 "TARGET_HAS_BITFIELD"
749-""
750-)
751+ "
752+{
753+ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
754+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
755+
756+ if (len <= 0 || pos + len > 32)
757+ FAIL;
758+
759+ ;;if (!register_operand (operands[0], VOIDmode))
760+ ;; FAIL;
761+
762+ emit_insn (gen_insv_32 (operands[0], operands[1],
763+ operands[2], operands[3]));
764+ DONE;
765+}")
766
767 (define_insn "insv_32"
768 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
769diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
770index d23f376..f316e27 100644
771--- a/gcc/config/microblaze/microblaze.opt
772+++ b/gcc/config/microblaze/microblaze.opt
773@@ -136,4 +136,9 @@ Target
774
775 mxl-frequency
776 Target Mask(AREA_OPTIMIZED_2)
777-Use 8 stage pipeline (frequency optimization)
778+Use 8 stage pipeline (frequency optimization).
779+
780+m64
781+Target Mask(MB_64)
782+MicroBlaze 64-bit mode.
783+
784diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
785index 41fa9a9..e9a1921 100644
786--- a/gcc/config/microblaze/t-microblaze
787+++ b/gcc/config/microblaze/t-microblaze
788@@ -1,8 +1,11 @@
789-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian
790-MULTILIB_DIRNAMES = bs m mh le
791+MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
792+MULTILIB_DIRNAMES = bs m mh le m64
793 MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
794 MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
795+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
796 MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
797+MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
798+MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
799
800 # Extra files
801 microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
802--
8032.7.4
804
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch
new file mode 100644
index 00000000..a973f4cd
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch
@@ -0,0 +1,83 @@
1From 95615e1bfae642dc4f5f1b03e1ffaea4f16aa99c Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Wed, 4 Apr 2018 16:41:41 +0530
4Subject: [PATCH 40/63] Added load store pattern movdi and also adding missing
5 files
6
7---
8 gcc/config/microblaze/constraints.md | 5 +++++
9 gcc/config/microblaze/microblaze.md | 26 ++++++++++++++++++++++++++
10 gcc/config/microblaze/t-microblaze | 4 ++--
11 3 files changed, 33 insertions(+), 2 deletions(-)
12
13diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
14index 5e1d79a..69bcb24 100644
15--- a/gcc/config/microblaze/constraints.md
16+++ b/gcc/config/microblaze/constraints.md
17@@ -52,6 +52,11 @@
18 (and (match_code "const_int")
19 (match_test "ival > 0 && ival < 0x10000")))
20
21+(define_constraint "K"
22+ "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)."
23+ (and (match_code "const_int")
24+ (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
25+
26 ;; Define floating point constraints
27
28 (define_constraint "G"
29diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
30index dbb592e..eb52957 100644
31--- a/gcc/config/microblaze/microblaze.md
32+++ b/gcc/config/microblaze/microblaze.md
33@@ -1122,6 +1122,32 @@
34 )
35
36
37+(define_insn "*movdi_internal_64"
38+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
39+ (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))]
40+ "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
41+ {
42+ switch (which_alternative)
43+ {
44+ case 0:
45+ return "addlk\t%0,%1";
46+ case 1:
47+ return "addlik\t%0,r0,%1";
48+ case 2:
49+ return "addlk\t%0,r0,r0";
50+ case 3:
51+ case 4:
52+ return "lli\t%0,%1";
53+ case 5:
54+ case 6:
55+ return "sli\t%1,%0";
56+ }
57+ return "unreachable";
58+ }
59+ [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
60+ (set_attr "mode" "DI")
61+ (set_attr "length" "8,8,8,8,12,8,12")])
62+
63 (define_insn "*movdi_internal"
64 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
65 (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))]
66diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
67index e9a1921..7671f63 100644
68--- a/gcc/config/microblaze/t-microblaze
69+++ b/gcc/config/microblaze/t-microblaze
70@@ -4,8 +4,8 @@ MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
71 MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
72 MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
73 MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
74-MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
75-MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
76+#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
77+#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
78
79 # Extra files
80 microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
81--
822.7.4
83
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0041-Intial-commit-for-64bit-MB-sources.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0041-Intial-commit-for-64bit-MB-sources.patch
new file mode 100644
index 00000000..b022eb77
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0041-Intial-commit-for-64bit-MB-sources.patch
@@ -0,0 +1,2463 @@
1From 7c68b1c9771f09f7cc53410248e8432c562d24bf Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Fri, 27 Jul 2018 15:23:41 +0530
4Subject: [PATCH 41/63] Intial commit for 64bit-MB sources. Need to cleanup the
5 code later.
6
7---
8 gcc/config/microblaze/constraints.md | 2 +-
9 gcc/config/microblaze/microblaze-c.c | 6 +
10 gcc/config/microblaze/microblaze.c | 218 ++++++++----
11 gcc/config/microblaze/microblaze.h | 63 ++--
12 gcc/config/microblaze/microblaze.md | 606 ++++++++++++++++++++++++--------
13 gcc/config/microblaze/t-microblaze | 7 +-
14 libgcc/config/microblaze/crti.S | 4 +-
15 libgcc/config/microblaze/crtn.S | 4 +-
16 libgcc/config/microblaze/divdi3.S | 98 ++++++
17 libgcc/config/microblaze/divdi3_table.c | 62 ++++
18 libgcc/config/microblaze/moddi3.S | 97 +++++
19 libgcc/config/microblaze/muldi3.S | 73 ++++
20 libgcc/config/microblaze/t-microblaze | 11 +-
21 libgcc/config/microblaze/udivdi3.S | 107 ++++++
22 libgcc/config/microblaze/umoddi3.S | 110 ++++++
23 15 files changed, 1232 insertions(+), 236 deletions(-)
24 create mode 100644 libgcc/config/microblaze/divdi3.S
25 create mode 100644 libgcc/config/microblaze/divdi3_table.c
26 create mode 100644 libgcc/config/microblaze/moddi3.S
27 create mode 100644 libgcc/config/microblaze/muldi3.S
28 create mode 100644 libgcc/config/microblaze/udivdi3.S
29 create mode 100644 libgcc/config/microblaze/umoddi3.S
30
31diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
32index 69bcb24..2fce91e 100644
33--- a/gcc/config/microblaze/constraints.md
34+++ b/gcc/config/microblaze/constraints.md
35@@ -55,7 +55,7 @@
36 (define_constraint "K"
37 "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)."
38 (and (match_code "const_int")
39- (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
40+ (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
41
42 ;; Define floating point constraints
43
44diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
45index cd21319..d2b0c76 100644
46--- a/gcc/config/microblaze/microblaze-c.c
47+++ b/gcc/config/microblaze/microblaze-c.c
48@@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile)
49 builtin_define ("HAVE_HW_FPU_SQRT");
50 builtin_define ("__HAVE_HW_FPU_SQRT__");
51 }
52+ if (TARGET_MB_64)
53+ {
54+ builtin_define ("__arch64__");
55+ builtin_define ("__microblaze64__");
56+ builtin_define ("__MICROBLAZE64__");
57+ }
58 }
59diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
60index f740f5c..d5ff7af 100644
61--- a/gcc/config/microblaze/microblaze.c
62+++ b/gcc/config/microblaze/microblaze.c
63@@ -383,10 +383,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
64 {
65 return 1;
66 }
67- else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
68+ /*else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
69 {
70 return 1;
71- }
72+ }*/
73 else
74 return 0;
75
76@@ -434,7 +434,7 @@ double_memory_operand (rtx op, machine_mode mode)
77 return 1;
78
79 return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
80- ? E_SImode : E_SFmode),
81+ ? Pmode : E_SFmode),
82 plus_constant (Pmode, addr, 4));
83 }
84
85@@ -681,7 +681,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg)
86 /* Load the addend. */
87 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)),
88 UNSPEC_TLS);
89- addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
90+ addend = force_reg (Pmode, gen_rtx_CONST (Pmode, addend));
91 dest = gen_rtx_PLUS (Pmode, dest, addend);
92 break;
93
94@@ -699,7 +699,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x)
95
96 if (XINT (x, 1) == UNSPEC_GOTOFF)
97 {
98- info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM);
99+ info->regA = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
100 info->type = ADDRESS_GOTOFF;
101 }
102 else if (XINT (x, 1) == UNSPEC_PLT)
103@@ -1302,8 +1302,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
104 emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES));
105
106 /* Emit the test & branch. */
107- emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src),
108+
109+ if (TARGET_MB_64) {
110+ emit_insn (gen_cbranchdi4 (gen_rtx_NE (Pmode, src_reg, final_src),
111+ src_reg, final_src, label));
112+ }
113+ else {
114+ emit_insn (gen_cbranchsi4 (gen_rtx_NE (Pmode, src_reg, final_src),
115 src_reg, final_src, label));
116+
117+ }
118
119 /* Mop up any left-over bytes. */
120 if (leftover)
121@@ -1634,14 +1642,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v,
122 break;
123
124 case E_DFmode:
125- cum->arg_words += 2;
126+ if (TARGET_MB_64)
127+ cum->arg_words++;
128+ else
129+ cum->arg_words += 2;
130 if (!cum->gp_reg_found && cum->arg_number <= 2)
131 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
132 break;
133
134 case E_DImode:
135 cum->gp_reg_found = 1;
136- cum->arg_words += 2;
137+ if (TARGET_MB_64)
138+ cum->arg_words++;
139+ else
140+ cum->arg_words += 2;
141 break;
142
143 case E_QImode:
144@@ -2295,7 +2309,7 @@ compute_frame_size (HOST_WIDE_INT size)
145
146 if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM)
147 /* Don't account for link register. It is accounted specially below. */
148- gp_reg_size += GET_MODE_SIZE (SImode);
149+ gp_reg_size += GET_MODE_SIZE (Pmode);
150
151 mask |= (1L << (regno - GP_REG_FIRST));
152 }
153@@ -2564,7 +2578,7 @@ print_operand (FILE * file, rtx op, int letter)
154
155 if ((letter == 'M' && !WORDS_BIG_ENDIAN)
156 || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D')
157- regnum++;
158+ regnum++;
159
160 fprintf (file, "%s", reg_names[regnum]);
161 }
162@@ -2590,6 +2604,7 @@ print_operand (FILE * file, rtx op, int letter)
163 else if (letter == 'h' || letter == 'j')
164 {
165 long val[2];
166+ int val1[2];
167 long l[2];
168 if (code == CONST_DOUBLE)
169 {
170@@ -2602,12 +2617,12 @@ print_operand (FILE * file, rtx op, int letter)
171 val[0] = l[WORDS_BIG_ENDIAN != 0];
172 }
173 }
174- else if (code == CONST_INT)
175+ else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
176 {
177- val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
178- val[1] = INTVAL (op) & 0x00000000ffffffffLL;
179+ val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
180+ val1[1] = INTVAL (op) & 0x00000000ffffffffLL;
181 }
182- fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
183+ fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]);
184 }
185 else if (code == CONST_DOUBLE)
186 {
187@@ -2801,7 +2816,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
188
189 switch_to_section (get_section (section, 0, NULL));
190 assemble_align (POINTER_SIZE);
191- fputs ("\t.word\t", asm_out_file);
192+ if (TARGET_MB_64)
193+ fputs ("\t.dword\t", asm_out_file);
194+ else
195+ fputs ("\t.word\t", asm_out_file);
196 output_addr_const (asm_out_file, symbol);
197 fputs ("\n", asm_out_file);
198 }
199@@ -2824,7 +2842,10 @@ microblaze_asm_destructor (rtx symbol, int priority)
200
201 switch_to_section (get_section (section, 0, NULL));
202 assemble_align (POINTER_SIZE);
203- fputs ("\t.word\t", asm_out_file);
204+ if (TARGET_MB_64)
205+ fputs ("\t.dword\t", asm_out_file);
206+ else
207+ fputs ("\t.word\t", asm_out_file);
208 output_addr_const (asm_out_file, symbol);
209 fputs ("\n", asm_out_file);
210 }
211@@ -2890,7 +2911,7 @@ save_restore_insns (int prologue)
212 /* For interrupt_handlers, need to save/restore the MSR. */
213 if (microblaze_is_interrupt_variant ())
214 {
215- isr_mem_rtx = gen_rtx_MEM (SImode,
216+ isr_mem_rtx = gen_rtx_MEM (Pmode,
217 gen_rtx_PLUS (Pmode, base_reg_rtx,
218 GEN_INT (current_frame_info.
219 gp_offset -
220@@ -2898,8 +2919,8 @@ save_restore_insns (int prologue)
221
222 /* Do not optimize in flow analysis. */
223 MEM_VOLATILE_P (isr_mem_rtx) = 1;
224- isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG);
225- isr_msr_rtx = gen_rtx_REG (SImode, ST_REG);
226+ isr_reg_rtx = gen_rtx_REG (Pmode, MB_ABI_MSR_SAVE_REG);
227+ isr_msr_rtx = gen_rtx_REG (Pmode, ST_REG);
228 }
229
230 if (microblaze_is_interrupt_variant () && !prologue)
231@@ -2907,8 +2928,8 @@ save_restore_insns (int prologue)
232 emit_move_insn (isr_reg_rtx, isr_mem_rtx);
233 emit_move_insn (isr_msr_rtx, isr_reg_rtx);
234 /* Do not optimize in flow analysis. */
235- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx));
236- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx));
237+ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx));
238+ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx));
239 }
240
241 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
242@@ -2919,9 +2940,9 @@ save_restore_insns (int prologue)
243 /* Don't handle here. Already handled as the first register. */
244 continue;
245
246- reg_rtx = gen_rtx_REG (SImode, regno);
247+ reg_rtx = gen_rtx_REG (Pmode, regno);
248 insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset));
249- mem_rtx = gen_rtx_MEM (SImode, insn);
250+ mem_rtx = gen_rtx_MEM (Pmode, insn);
251 if (microblaze_is_interrupt_variant () || save_volatiles)
252 /* Do not optimize in flow analysis. */
253 MEM_VOLATILE_P (mem_rtx) = 1;
254@@ -2936,7 +2957,7 @@ save_restore_insns (int prologue)
255 insn = emit_move_insn (reg_rtx, mem_rtx);
256 }
257
258- gp_offset += GET_MODE_SIZE (SImode);
259+ gp_offset += GET_MODE_SIZE (Pmode);
260 }
261 }
262
263@@ -2946,8 +2967,8 @@ save_restore_insns (int prologue)
264 emit_move_insn (isr_mem_rtx, isr_reg_rtx);
265
266 /* Do not optimize in flow analysis. */
267- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx));
268- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx));
269+ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx));
270+ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx));
271 }
272
273 /* Done saving and restoring */
274@@ -3037,7 +3058,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
275
276 switch_to_section (s);
277 assemble_align (POINTER_SIZE);
278- fputs ("\t.word\t", asm_out_file);
279+ if (TARGET_MB_64)
280+ fputs ("\t.dword\t", asm_out_file);
281+ else
282+ fputs ("\t.word\t", asm_out_file);
283 output_addr_const (asm_out_file, symbol);
284 fputs ("\n", asm_out_file);
285 }
286@@ -3182,10 +3206,10 @@ microblaze_expand_prologue (void)
287 {
288 if (offset != 0)
289 ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset));
290- emit_move_insn (gen_rtx_MEM (SImode, ptr),
291- gen_rtx_REG (SImode, regno));
292+ emit_move_insn (gen_rtx_MEM (Pmode, ptr),
293+ gen_rtx_REG (Pmode, regno));
294
295- offset += GET_MODE_SIZE (SImode);
296+ offset += GET_MODE_SIZE (Pmode);
297 }
298 }
299
300@@ -3194,15 +3218,23 @@ microblaze_expand_prologue (void)
301 rtx fsiz_rtx = GEN_INT (fsiz);
302
303 rtx_insn *insn = NULL;
304- insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
305+ if (TARGET_MB_64)
306+ {
307+
308+ insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
309 fsiz_rtx));
310+ }
311+ else {
312+ insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
313+ fsiz_rtx));
314+ }
315 if (insn)
316 RTX_FRAME_RELATED_P (insn) = 1;
317
318 /* Handle SUB_RETURN_ADDR_REGNUM specially at first. */
319 if (!crtl->is_leaf || interrupt_handler)
320 {
321- mem_rtx = gen_rtx_MEM (SImode,
322+ mem_rtx = gen_rtx_MEM (Pmode,
323 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
324 const0_rtx));
325
326@@ -3210,7 +3242,7 @@ microblaze_expand_prologue (void)
327 /* Do not optimize in flow analysis. */
328 MEM_VOLATILE_P (mem_rtx) = 1;
329
330- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
331+ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
332 insn = emit_move_insn (mem_rtx, reg_rtx);
333 RTX_FRAME_RELATED_P (insn) = 1;
334 }
335@@ -3320,12 +3352,12 @@ microblaze_expand_epilogue (void)
336 if (!crtl->is_leaf || interrupt_handler)
337 {
338 mem_rtx =
339- gen_rtx_MEM (SImode,
340+ gen_rtx_MEM (Pmode,
341 gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx));
342 if (interrupt_handler)
343 /* Do not optimize in flow analysis. */
344 MEM_VOLATILE_P (mem_rtx) = 1;
345- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
346+ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
347 emit_move_insn (reg_rtx, mem_rtx);
348 }
349
350@@ -3341,15 +3373,25 @@ microblaze_expand_epilogue (void)
351 /* _restore_ registers for epilogue. */
352 save_restore_insns (0);
353 emit_insn (gen_blockage ());
354- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
355+ if (TARGET_MB_64)
356+ emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
357+ else
358+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
359 }
360
361 if (crtl->calls_eh_return)
362- emit_insn (gen_addsi3 (stack_pointer_rtx,
363+ if (TARGET_MB_64) {
364+ emit_insn (gen_adddi3 (stack_pointer_rtx,
365 stack_pointer_rtx,
366- gen_raw_REG (SImode,
367+ gen_raw_REG (Pmode,
368 MB_EH_STACKADJ_REGNUM)));
369-
370+ }
371+ else {
372+ emit_insn (gen_addsi3 (stack_pointer_rtx,
373+ stack_pointer_rtx,
374+ gen_raw_REG (Pmode,
375+ MB_EH_STACKADJ_REGNUM)));
376+ }
377 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST +
378 MB_ABI_SUB_RETURN_ADDR_REGNUM)));
379 }
380@@ -3515,9 +3557,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
381 else
382 this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM);
383
384- /* Apply the constant offset, if required. */
385+ /* Apply the constant offset, if required. */
386 if (delta)
387- emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
388+ {
389+ if (TARGET_MB_64)
390+ emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (delta)));
391+ else
392+ emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
393+ }
394
395 /* Apply the offset from the vtable, if required. */
396 if (vcall_offset)
397@@ -3530,7 +3577,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
398 rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx);
399 emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc));
400
401- emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
402+ if (TARGET_MB_64)
403+ emit_insn (gen_adddi3 (this_rtx, this_rtx, temp1));
404+ else
405+ emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
406 }
407
408 /* Generate a tail call to the target function. */
409@@ -3704,7 +3754,7 @@ microblaze_eh_return (rtx op0)
410 /* Queue an .ident string in the queue of top-level asm statements.
411 If the string size is below the threshold, put it into .sdata2.
412 If the front-end is done, we must be being called from toplev.c.
413- In that case, do nothing. */
414+ In that case, do nothing. */
415 void
416 microblaze_asm_output_ident (const char *string)
417 {
418@@ -3759,9 +3809,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
419 emit_block_move (m_tramp, assemble_trampoline_template (),
420 GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL);
421
422- mem = adjust_address (m_tramp, SImode, 16);
423+ mem = adjust_address (m_tramp, Pmode, 16);
424 emit_move_insn (mem, chain_value);
425- mem = adjust_address (m_tramp, SImode, 20);
426+ mem = adjust_address (m_tramp, Pmode, 20);
427 emit_move_insn (mem, fnaddr);
428 }
429
430@@ -3785,7 +3835,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
431 {
432 comp_reg = cmp_op0;
433 condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
434- if (mode == SImode)
435+ if (mode == Pmode)
436 emit_jump_insn (gen_condjump (condition, label1));
437 else
438 emit_jump_insn (gen_long_condjump (condition, label1));
439@@ -3904,7 +3954,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
440 rtx comp_reg = gen_reg_rtx (SImode);
441
442 emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
443- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
444+ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
445 emit_jump_insn (gen_condjump (condition, operands[3]));
446 }
447
448@@ -3914,10 +3964,10 @@ microblaze_expand_conditional_branch_df (rtx operands[])
449 rtx condition;
450 rtx cmp_op0 = XEXP (operands[0], 0);
451 rtx cmp_op1 = XEXP (operands[0], 1);
452- rtx comp_reg = gen_reg_rtx (DImode);
453+ rtx comp_reg = gen_reg_rtx (Pmode);
454
455 emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
456- condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
457+ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
458 emit_jump_insn (gen_long_condjump (condition, operands[3]));
459 }
460
461@@ -3938,8 +3988,8 @@ microblaze_expand_divide (rtx operands[])
462 {
463 /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15). */
464
465- rtx regt1 = gen_reg_rtx (SImode);
466- rtx reg18 = gen_rtx_REG (SImode, R_TMP);
467+ rtx regt1 = gen_reg_rtx (Pmode);
468+ rtx reg18 = gen_rtx_REG (Pmode, R_TMP);
469 rtx regqi = gen_reg_rtx (QImode);
470 rtx_code_label *div_label = gen_label_rtx ();
471 rtx_code_label *div_end_label = gen_label_rtx ();
472@@ -3947,17 +3997,31 @@ microblaze_expand_divide (rtx operands[])
473 rtx mem_rtx;
474 rtx ret;
475 rtx_insn *jump, *cjump, *insn;
476-
477- insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2]));
478- cjump = emit_jump_insn_after (gen_cbranchsi4 (
479- gen_rtx_GTU (SImode, regt1, GEN_INT (15)),
480+
481+ if (TARGET_MB_64) {
482+ insn = emit_insn (gen_iordi3 (regt1, operands[1], operands[2]));
483+ cjump = emit_jump_insn_after (gen_cbranchdi4 (
484+ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)),
485+ regt1, GEN_INT (15), div_label), insn);
486+ }
487+ else {
488+ insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2]));
489+ cjump = emit_jump_insn_after (gen_cbranchsi4 (
490+ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)),
491 regt1, GEN_INT (15), div_label), insn);
492+ }
493 LABEL_NUSES (div_label) = 1;
494 JUMP_LABEL (cjump) = div_label;
495- emit_insn (gen_rtx_CLOBBER (SImode, reg18));
496+ emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
497
498- emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
499- emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
500+ if (TARGET_MB_64) {
501+ emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
502+ emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
503+ }
504+ else {
505+ emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
506+ emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
507+ }
508 mem_rtx = gen_rtx_MEM (QImode,
509 gen_rtx_PLUS (QImode, regt1, div_table_rtx));
510
511@@ -4104,7 +4168,7 @@ insert_wic_for_ilb_runout (rtx_insn *first)
512 {
513 insn =
514 emit_insn_before (gen_iprefetch
515- (gen_int_mode (addr_offset, SImode)),
516+ (gen_int_mode (addr_offset, Pmode)),
517 before_4);
518 recog_memoized (insn);
519 INSN_LOCATION (insn) = INSN_LOCATION (before_4);
520@@ -4114,7 +4178,27 @@ insert_wic_for_ilb_runout (rtx_insn *first)
521 }
522 }
523 }
524-
525+
526+/* Set the names for various arithmetic operations according to the
527+ * MICROBLAZE ABI. */
528+static void
529+microblaze_init_libfuncs (void)
530+{
531+ set_optab_libfunc (smod_optab, SImode, "__modsi3");
532+ set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
533+ set_optab_libfunc (smul_optab, SImode, "__mulsi3");
534+ set_optab_libfunc (umod_optab, SImode, "__umodsi3");
535+ set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
536+
537+ if (TARGET_MB_64)
538+ {
539+ set_optab_libfunc (smod_optab, DImode, "__moddi3");
540+ set_optab_libfunc (sdiv_optab, DImode, "__divdi3");
541+ set_optab_libfunc (smul_optab, DImode, "__muldi3");
542+ set_optab_libfunc (umod_optab, DImode, "__umoddi3");
543+ set_optab_libfunc (udiv_optab, DImode, "__udivdi3");
544+ }
545+}
546 /* Insert instruction prefetch instruction at the fall
547 through path of the function call. */
548
549@@ -4267,6 +4351,17 @@ microblaze_starting_frame_offset (void)
550 #undef TARGET_LRA_P
551 #define TARGET_LRA_P hook_bool_void_false
552
553+#ifdef TARGET_MB_64
554+#undef TARGET_ASM_ALIGNED_DI_OP
555+#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
556+
557+#undef TARGET_ASM_ALIGNED_HI_OP
558+#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
559+
560+#undef TARGET_ASM_ALIGNED_SI_OP
561+#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
562+#endif
563+
564 #undef TARGET_FRAME_POINTER_REQUIRED
565 #define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required
566
567@@ -4276,6 +4371,9 @@ microblaze_starting_frame_offset (void)
568 #undef TARGET_TRAMPOLINE_INIT
569 #define TARGET_TRAMPOLINE_INIT microblaze_trampoline_init
570
571+#undef TARGET_INIT_LIBFUNCS
572+#define TARGET_INIT_LIBFUNCS microblaze_init_libfuncs
573+
574 #undef TARGET_PROMOTE_FUNCTION_MODE
575 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
576
577diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
578index 2ca44f5..a23fd4e 100644
579--- a/gcc/config/microblaze/microblaze.h
580+++ b/gcc/config/microblaze/microblaze.h
581@@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe;
582
583 /* Generate DWARF exception handling info. */
584 #define DWARF2_UNWIND_INFO 1
585-
586 /* Don't generate .loc operations. */
587 #define DWARF2_ASM_LINE_DEBUG_INFO 0
588
589@@ -206,38 +205,51 @@ extern enum pipeline_type microblaze_pipe;
590 ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr)
591
592 /* Use DWARF 2 debugging information by default. */
593-#define DWARF2_DEBUGGING_INFO
594+#define DWARF2_DEBUGGING_INFO 1
595 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
596+#define DWARF2_ADDR_SIZE 4
597
598 /* Target machine storage layout */
599
600 #define BITS_BIG_ENDIAN 0
601 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
602 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
603-#define BITS_PER_WORD 32
604-#define UNITS_PER_WORD 4
605+//#define BITS_PER_WORD 64
606+//Revisit
607+#define MAX_BITS_PER_WORD 64
608+#define UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4)
609+//#define MIN_UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4)
610+//#define UNITS_PER_WORD 4
611 #define MIN_UNITS_PER_WORD 4
612 #define INT_TYPE_SIZE 32
613 #define SHORT_TYPE_SIZE 16
614-#define LONG_TYPE_SIZE 64
615+#define LONG_TYPE_SIZE (TARGET_MB_64 ? 64 : 32)
616 #define LONG_LONG_TYPE_SIZE 64
617 #define FLOAT_TYPE_SIZE 32
618 #define DOUBLE_TYPE_SIZE 64
619 #define LONG_DOUBLE_TYPE_SIZE 64
620-#define POINTER_SIZE 32
621-#define PARM_BOUNDARY 32
622-#define FUNCTION_BOUNDARY 32
623-#define EMPTY_FIELD_BOUNDARY 32
624+#define POINTER_SIZE (TARGET_MB_64 ? 64 : 32)
625+//#define WIDEST_HARDWARE_FP_SIZE 64
626+//#define POINTERS_EXTEND_UNSIGNED 1
627+#define PARM_BOUNDARY (TARGET_MB_64 ? 64 : 32)
628+#define FUNCTION_BOUNDARY (TARGET_MB_64 ? 64 : 32)
629+#define EMPTY_FIELD_BOUNDARY (TARGET_MB_64 ? 64 : 32)
630 #define STRUCTURE_SIZE_BOUNDARY 8
631-#define BIGGEST_ALIGNMENT 32
632+#define BIGGEST_ALIGNMENT (TARGET_MB_64 ? 64 : 32)
633 #define STRICT_ALIGNMENT 1
634 #define PCC_BITFIELD_TYPE_MATTERS 1
635
636+//#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_MB_64 ? TImode : DImode)
637 #undef SIZE_TYPE
638-#define SIZE_TYPE "unsigned int"
639+#define SIZE_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
640
641 #undef PTRDIFF_TYPE
642-#define PTRDIFF_TYPE "int"
643+#define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int")
644+
645+/*#undef INTPTR_TYPE
646+#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/
647+#undef UINTPTR_TYPE
648+#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
649
650 #define DATA_ALIGNMENT(TYPE, ALIGN) \
651 ((((ALIGN) < BITS_PER_WORD) \
652@@ -253,12 +265,12 @@ extern enum pipeline_type microblaze_pipe;
653 #define WORD_REGISTER_OPERATIONS 1
654
655 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
656-
657+/*
658 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
659 if (GET_MODE_CLASS (MODE) == MODE_INT \
660- && GET_MODE_SIZE (MODE) < 4) \
661- (MODE) = SImode;
662-
663+ && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
664+ (MODE) = TARGET_MB_64 ? DImode : SImode;
665+*/
666 /* Standard register usage. */
667
668 /* On the MicroBlaze, we have 32 integer registers */
669@@ -438,13 +450,16 @@ extern struct microblaze_frame_info current_frame_info;
670 #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD)
671
672 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
673+#define DWARF_CIE_DATA_ALIGNMENT -1
674
675 #define REG_PARM_STACK_SPACE(FNDECL) microblaze_reg_parm_stack_space(FNDECL)
676
677 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
678
679-#define STACK_BOUNDARY 32
680+#define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32)
681
682+#define PREFERRED_STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32)
683+
684 #define NUM_OF_ARGS 6
685
686 #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM)
687@@ -455,12 +470,15 @@ extern struct microblaze_frame_info current_frame_info;
688 #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
689
690 #define LIBCALL_VALUE(MODE) \
691+ gen_rtx_REG (MODE,GP_RETURN)
692+
693+/*#define LIBCALL_VALUE(MODE) \
694 gen_rtx_REG ( \
695 ((GET_MODE_CLASS (MODE) != MODE_INT \
696 || GET_MODE_SIZE (MODE) >= 4) \
697 ? (MODE) \
698 : SImode), GP_RETURN)
699-
700+*/
701 /* 1 if N is a possible register number for a function value.
702 On the MicroBlaze, R2 R3 are the only register thus used.
703 Currently, R2 are only implemented here (C has no complex type) */
704@@ -500,7 +518,7 @@ typedef struct microblaze_args
705 /* 4 insns + 2 words of data. */
706 #define TRAMPOLINE_SIZE (6 * 4)
707
708-#define TRAMPOLINE_ALIGNMENT 32
709+#define TRAMPOLINE_ALIGNMENT 64
710
711 #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
712
713@@ -529,13 +547,13 @@ typedef struct microblaze_args
714 addresses which require two reload registers. */
715 #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X)
716
717-#define CASE_VECTOR_MODE (SImode)
718+#define CASE_VECTOR_MODE (TARGET_MB_64? DImode:SImode)
719
720 #ifndef DEFAULT_SIGNED_CHAR
721 #define DEFAULT_SIGNED_CHAR 1
722 #endif
723
724-#define MOVE_MAX 4
725+#define MOVE_MAX (TARGET_MB_64 ? 8 : 4)
726 #define MAX_MOVE_MAX 8
727
728 #define SLOW_BYTE_ACCESS 1
729@@ -545,7 +563,7 @@ typedef struct microblaze_args
730
731 #define SHIFT_COUNT_TRUNCATED 1
732
733-#define Pmode SImode
734+#define Pmode (TARGET_MB_64? DImode:SImode)
735
736 #define FUNCTION_MODE SImode
737
738@@ -707,6 +725,7 @@ do { \
739
740 #undef TARGET_ASM_OUTPUT_IDENT
741 #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident
742+//#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive
743
744 /* Default to -G 8 */
745 #ifndef MICROBLAZE_DEFAULT_GVALUE
746diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
747index eb52957..77627a7 100644
748--- a/gcc/config/microblaze/microblaze.md
749+++ b/gcc/config/microblaze/microblaze.md
750@@ -26,6 +26,7 @@
751 ;; Constants
752 ;;----------------------------------------------------
753 (define_constants [
754+ (R_Z 0) ;; For reg r0
755 (R_SP 1) ;; Stack pointer reg
756 (R_SR 15) ;; Sub-routine return addr reg
757 (R_IR 14) ;; Interrupt return addr reg
758@@ -541,6 +542,7 @@
759
760 ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ]
761 ;; Leave carry as is
762+
763 (define_insn "addsi3"
764 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
765 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ")
766@@ -562,23 +564,38 @@
767
768 ;; Adding 2 DI operands in register or reg/imm
769
770-(define_insn "adddi3_long"
771+(define_expand "adddi3"
772+ [(set (match_operand:DI 0 "register_operand" "")
773+ (plus:DI (match_operand:DI 1 "register_operand" "")
774+ (match_operand:DI 2 "arith_plus_operand" "")))]
775+""
776+{
777+ if (TARGET_MB_64)
778+ {
779+ if (GET_CODE (operands[2]) == CONST_INT &&
780+ INTVAL(operands[2]) < (long)-549755813888 &&
781+ INTVAL(operands[2]) > (long)549755813887)
782+ FAIL;
783+ }
784+})
785+
786+(define_insn "*adddi3_long"
787 [(set (match_operand:DI 0 "register_operand" "=d,d")
788- (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
789+ (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
790 (match_operand:DI 2 "arith_plus_operand" "d,K")))]
791 "TARGET_MB_64"
792 "@
793- addlk\t%0,%z1,%2
794- addlik\t%0,%z1,%2"
795- [(set_attr "type" "arith,arith")
796- (set_attr "mode" "DI,DI")
797+ addlk\t%0,%1,%2
798+ addlik\t%0,%1,%2 #N10"
799+ [(set_attr "type" "darith,no_delay_arith")
800+ (set_attr "mode" "DI")
801 (set_attr "length" "4,4")])
802
803-(define_insn "adddi3"
804+(define_insn "*adddi3_all"
805 [(set (match_operand:DI 0 "register_operand" "=d,d")
806 (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
807 (match_operand:DI 2 "arith_operand" "d,i")))]
808- ""
809+ "!TARGET_MB_64"
810 "@
811 add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
812 addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
813@@ -605,7 +622,7 @@
814 (define_insn "iprefetch"
815 [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH)
816 (clobber (mem:BLK (scratch)))]
817- "TARGET_PREFETCH"
818+ "TARGET_PREFETCH && !TARGET_MB_64"
819 {
820 operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
821 return "mfs\t%2,rpc\n\twic\t%2,r0";
822@@ -618,23 +635,33 @@
823 ;; Double Precision Subtraction
824 ;;----------------------------------------------------------------
825
826-(define_insn "subdi3_long"
827- [(set (match_operand:DI 0 "register_operand" "=d,d")
828- (minus:DI (match_operand:DI 1 "register_operand" "d,d")
829- (match_operand:DI 2 "register_operand" "d,n")))]
830+(define_expand "subdi3"
831+ [(set (match_operand:DI 0 "register_operand" "")
832+ (minus:DI (match_operand:DI 1 "register_operand" "")
833+ (match_operand:DI 2 "arith_operand" "")))]
834+""
835+"
836+{
837+}")
838+
839+(define_insn "subsidi3"
840+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
841+ (minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
842+ (match_operand:DI 2 "arith_operand" "d,K,n")))]
843 "TARGET_MB_64"
844 "@
845 rsubl\t%0,%2,%1
846- addlik\t%0,%z1,-%2"
847- [(set_attr "type" "darith")
848- (set_attr "mode" "DI,DI")
849- (set_attr "length" "4,4")])
850+ addik\t%0,%z1,-%2
851+ addik\t%0,%z1,-%2"
852+ [(set_attr "type" "arith,no_delay_arith,no_delay_arith")
853+ (set_attr "mode" "DI")
854+ (set_attr "length" "4,4,4")])
855
856-(define_insn "subdi3"
857+(define_insn "subdi3_small"
858 [(set (match_operand:DI 0 "register_operand" "=&d")
859 (minus:DI (match_operand:DI 1 "register_operand" "d")
860 (match_operand:DI 2 "register_operand" "d")))]
861- ""
862+ "!TARGET_MB_64"
863 "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
864 [(set_attr "type" "darith")
865 (set_attr "mode" "DI")
866@@ -663,7 +690,7 @@
867 (mult:DI
868 (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
869 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
870- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
871+ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
872 "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2"
873 [(set_attr "type" "no_delay_arith")
874 (set_attr "mode" "DI")
875@@ -674,7 +701,7 @@
876 (mult:DI
877 (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
878 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
879- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
880+ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
881 "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2"
882 [(set_attr "type" "no_delay_arith")
883 (set_attr "mode" "DI")
884@@ -685,7 +712,7 @@
885 (mult:DI
886 (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
887 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
888- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
889+ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
890 "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1"
891 [(set_attr "type" "no_delay_arith")
892 (set_attr "mode" "DI")
893@@ -789,7 +816,7 @@
894 (match_operand:SI 4 "arith_operand")])
895 (label_ref (match_operand 5))
896 (pc)))]
897- "TARGET_HARD_FLOAT"
898+ "TARGET_HARD_FLOAT && !TARGET_MB_64"
899 [(set (match_dup 1) (match_dup 3))]
900
901 {
902@@ -819,6 +846,15 @@
903 (set_attr "mode" "SI")
904 (set_attr "length" "4")])
905
906+(define_insn "negsi_long"
907+ [(set (match_operand:SI 0 "register_operand" "=d")
908+ (neg:SI (match_operand:DI 1 "register_operand" "d")))]
909+ ""
910+ "rsubk\t%0,%1,r0"
911+ [(set_attr "type" "arith")
912+ (set_attr "mode" "SI")
913+ (set_attr "length" "4")])
914+
915 (define_insn "negdi2_long"
916 [(set (match_operand:DI 0 "register_operand" "=d")
917 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
918@@ -847,16 +883,24 @@
919 (set_attr "mode" "SI")
920 (set_attr "length" "4")])
921
922-(define_insn "one_cmpldi2_long"
923+(define_expand "one_cmpldi2"
924+ [(set (match_operand:DI 0 "register_operand" "")
925+ (not:DI (match_operand:DI 1 "register_operand" "")))]
926+ ""
927+ "
928+{
929+}")
930+
931+(define_insn ""
932 [(set (match_operand:DI 0 "register_operand" "=d")
933- (not:DI (match_operand:DI 1 "register_operand" "d")))]
934+ (not:DI (match_operand:DI 1 "arith_operand" "d")))]
935 "TARGET_MB_64"
936 "xorli\t%0,%1,-1"
937- [(set_attr "type" "arith")
938+ [(set_attr "type" "no_delay_arith")
939 (set_attr "mode" "DI")
940 (set_attr "length" "4")])
941
942-(define_insn "*one_cmpldi2"
943+(define_insn ""
944 [(set (match_operand:DI 0 "register_operand" "=d")
945 (not:DI (match_operand:DI 1 "register_operand" "d")))]
946 ""
947@@ -871,7 +915,8 @@
948 (not:DI (match_operand:DI 1 "register_operand" "")))]
949 "reload_completed
950 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
951- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
952+ && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
953+ && !TARGET_MB_64"
954
955 [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
956 (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
957@@ -883,18 +928,17 @@
958 ;;----------------------------------------------------------------
959
960 (define_insn "anddi3"
961- [(set (match_operand:DI 0 "register_operand" "=d,d")
962- (and:DI (match_operand:DI 1 "arith_operand" "d,d")
963- (match_operand:DI 2 "arith_operand" "d,K")))]
964+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
965+ (and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
966+ (match_operand:DI 2 "arith_operand" "d,K,I")))]
967 "TARGET_MB_64"
968 "@
969 andl\t%0,%1,%2
970- andli\t%0,%1,%2 #andl1"
971- ;; andli\t%0,%1,%2 #andl3
972- ;; andli\t%0,%1,%2 #andl2
973- [(set_attr "type" "arith,arith")
974- (set_attr "mode" "DI,DI")
975- (set_attr "length" "4,4")])
976+ andli\t%0,%1,%2 #andl2
977+ andli\t%0,%1,%2 #andl3"
978+ [(set_attr "type" "arith,no_delay_arith,no_delay_arith")
979+ (set_attr "mode" "DI,DI,DI")
980+ (set_attr "length" "4,4,4")])
981
982 (define_insn "andsi3"
983 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
984@@ -919,7 +963,7 @@
985 "@
986 orl\t%0,%1,%2
987 orli\t%0,%1,%2 #andl1"
988- [(set_attr "type" "arith,arith")
989+ [(set_attr "type" "arith,no_delay_arith")
990 (set_attr "mode" "DI,DI")
991 (set_attr "length" "4,4")])
992
993@@ -945,7 +989,7 @@
994 "@
995 xorl\t%0,%1,%2
996 xorli\t%0,%1,%2 #andl1"
997- [(set_attr "type" "arith,arith")
998+ [(set_attr "type" "arith,no_delay_arith")
999 (set_attr "mode" "DI,DI")
1000 (set_attr "length" "4,4")])
1001
1002@@ -1018,26 +1062,6 @@
1003 (set_attr "mode" "SI")
1004 (set_attr "length" "4")])
1005
1006-;;(define_expand "extendqidi2"
1007-;; [(set (match_operand:DI 0 "register_operand" "=d")
1008-;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
1009-;; "TARGET_MB_64"
1010-;; {
1011-;; if (GET_CODE (operands[1]) != REG)
1012-;; FAIL;
1013-;; }
1014-;;)
1015-
1016-
1017-;;(define_insn "extendqidi2"
1018-;; [(set (match_operand:DI 0 "register_operand" "=d")
1019-;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
1020-;; "TARGET_MB_64"
1021-;; "sextl8\t%0,%1"
1022-;; [(set_attr "type" "arith")
1023-;; (set_attr "mode" "DI")
1024-;; (set_attr "length" "4")])
1025-
1026 (define_insn "extendhisi2"
1027 [(set (match_operand:SI 0 "register_operand" "=d")
1028 (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
1029@@ -1060,6 +1084,27 @@
1030 ;; Those for integer source operand are ordered
1031 ;; widest source type first.
1032
1033+(define_insn "extendsidi2_long"
1034+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1035+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
1036+ "TARGET_MB_64"
1037+ {
1038+ switch (which_alternative)
1039+ {
1040+ case 0:
1041+ return "sextl32\t%0,%1";
1042+ case 1:
1043+ case 2:
1044+ {
1045+ output_asm_insn ("ll%i1\t%0,%1", operands);
1046+ return "sextl32\t%0,%0";
1047+ }
1048+ }
1049+ }
1050+ [(set_attr "type" "multi,multi,multi")
1051+ (set_attr "mode" "DI")
1052+ (set_attr "length" "4,8,8")])
1053+
1054 (define_insn "extendsidi2"
1055 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1056 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
1057@@ -1090,68 +1135,117 @@
1058 ;; Unlike most other insns, the move insns can't be split with
1059 ;; different predicates, because register spilling and other parts of
1060 ;; the compiler, have memoized the insn number already.
1061+;; //}
1062
1063 (define_expand "movdi"
1064 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1065 (match_operand:DI 1 "general_operand" ""))]
1066 ""
1067 {
1068- /* If operands[1] is a constant address illegal for pic, then we need to
1069- handle it just like microblaze_legitimize_address does. */
1070- if (flag_pic && pic_address_needs_scratch (operands[1]))
1071+ if (TARGET_MB_64)
1072+ {
1073+ if (microblaze_expand_move (DImode, operands)) DONE;
1074+ }
1075+ else
1076 {
1077+ /* If operands[1] is a constant address illegal for pic, then we need to
1078+ handle it just like microblaze_legitimize_address does. */
1079+ if (flag_pic && pic_address_needs_scratch (operands[1]))
1080+ {
1081 rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
1082 rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
1083 emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2));
1084 DONE;
1085- }
1086-
1087-
1088- if ((reload_in_progress | reload_completed) == 0
1089- && !register_operand (operands[0], DImode)
1090- && !register_operand (operands[1], DImode)
1091- && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
1092- && operands[1] != CONST0_RTX (DImode))))
1093- {
1094+ }
1095
1096- rtx temp = force_reg (DImode, operands[1]);
1097- emit_move_insn (operands[0], temp);
1098- DONE;
1099+ if ((reload_in_progress | reload_completed) == 0
1100+ && !register_operand (operands[0], DImode)
1101+ && !register_operand (operands[1], DImode)
1102+ && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
1103+ && operands[1] != CONST0_RTX (DImode))))
1104+ {
1105+ rtx temp = force_reg (DImode, operands[1]);
1106+ emit_move_insn (operands[0], temp);
1107+ DONE;
1108+ }
1109 }
1110 }
1111 )
1112
1113+;; Added for status registers
1114+(define_insn "movdi_status"
1115+ [(set (match_operand:DI 0 "register_operand" "=d,d,z")
1116+ (match_operand:DI 1 "register_operand" "z,d,d"))]
1117+ "microblaze_is_interrupt_variant () && TARGET_MB_64"
1118+ "@
1119+ mfs\t%0,%1 #mfs
1120+ addlk\t%0,%1,r0 #add movdi
1121+ mts\t%0,%1 #mts"
1122+ [(set_attr "type" "move")
1123+ (set_attr "mode" "DI")
1124+ (set_attr "length" "12")])
1125
1126-(define_insn "*movdi_internal_64"
1127- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
1128- (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))]
1129- "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
1130+;; This move will be not be moved to delay slot.
1131+(define_insn "*movdi_internal3"
1132+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
1133+ (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
1134+ "TARGET_MB_64 && (register_operand (operands[0], DImode) &&
1135+ (GET_CODE (operands[1]) == CONST_INT &&
1136+ (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))"
1137+ "@
1138+ addlk\t%0,r0,r0\t
1139+ addlik\t%0,r0,%1\t #N1 %X1
1140+ addlik\t%0,r0,%1\t #N2 %X1"
1141+ [(set_attr "type" "arith,no_delay_arith,no_delay_arith")
1142+ (set_attr "mode" "DI")
1143+ (set_attr "length" "4")])
1144+
1145+;; This move may be used for PLT label operand
1146+(define_insn "*movdi_internal5_pltop"
1147+ [(set (match_operand:DI 0 "register_operand" "=d,d")
1148+ (match_operand:DI 1 "call_insn_operand" ""))]
1149+ "TARGET_MB_64 && (register_operand (operands[0], Pmode) &&
1150+ PLT_ADDR_P (operands[1]))"
1151+ {
1152+ gcc_unreachable ();
1153+ }
1154+ [(set_attr "type" "load")
1155+ (set_attr "mode" "DI")
1156+ (set_attr "length" "4")])
1157+
1158+(define_insn "*movdi_internal2"
1159+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m")
1160+ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))]
1161+ "TARGET_MB_64"
1162 {
1163 switch (which_alternative)
1164 {
1165 case 0:
1166- return "addlk\t%0,%1";
1167- case 1:
1168- return "addlik\t%0,r0,%1";
1169- case 2:
1170- return "addlk\t%0,r0,r0";
1171- case 3:
1172- case 4:
1173- return "lli\t%0,%1";
1174- case 5:
1175- case 6:
1176- return "sli\t%1,%0";
1177- }
1178- return "unreachable";
1179- }
1180- [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
1181+ return "addlk\t%0,%1,r0";
1182+ case 1:
1183+ case 2:
1184+ if (GET_CODE (operands[1]) == CONST_INT &&
1185+ (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888))
1186+ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
1187+ else
1188+ return "addlik\t%0,r0,%1";
1189+ case 3:
1190+ case 4:
1191+ return "ll%i1\t%0,%1";
1192+ case 5:
1193+ case 6:
1194+ return "sl%i0\t%z1,%0";
1195+ }
1196+ }
1197+ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
1198 (set_attr "mode" "DI")
1199- (set_attr "length" "8,8,8,8,12,8,12")])
1200+ (set_attr "length" "4,4,12,4,8,4,8")])
1201+
1202
1203 (define_insn "*movdi_internal"
1204 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
1205 (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))]
1206- ""
1207+ "!TARGET_MB_64"
1208 {
1209 switch (which_alternative)
1210 {
1211@@ -1183,7 +1277,8 @@
1212 "reload_completed
1213 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1214 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1215- && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))"
1216+ && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))
1217+ && !(TARGET_MB_64)"
1218
1219 [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
1220 (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
1221@@ -1195,12 +1290,22 @@
1222 "reload_completed
1223 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1224 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1225- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
1226+ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))
1227+ && !(TARGET_MB_64)"
1228
1229 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
1230 (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
1231 "")
1232
1233+(define_insn "movdi_long_int"
1234+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1235+ (match_operand:DI 1 "general_operand" "i"))]
1236+ ""
1237+ "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
1238+ [(set_attr "type" "no_delay_arith")
1239+ (set_attr "mode" "DI")
1240+ (set_attr "length" "12")])
1241+
1242 ;; Unlike most other insns, the move insns can't be split with
1243 ;; different predicates, because register spilling and other parts of
1244 ;; the compiler, have memoized the insn number already.
1245@@ -1272,6 +1377,8 @@
1246 (set_attr "length" "4,4,8,4,8,4,8")])
1247
1248
1249+
1250+
1251 ;; 16-bit Integer moves
1252
1253 ;; Unlike most other insns, the move insns can't be split with
1254@@ -1304,8 +1411,8 @@
1255 "@
1256 addik\t%0,r0,%1\t# %X1
1257 addk\t%0,%1,r0
1258- lhui\t%0,%1
1259- lhui\t%0,%1
1260+ lhu%i1\t%0,%1
1261+ lhu%i1\t%0,%1
1262 sh%i0\t%z1,%0
1263 sh%i0\t%z1,%0"
1264 [(set_attr "type" "arith,move,load,no_delay_load,store,no_delay_store")
1265@@ -1348,7 +1455,7 @@
1266 lbu%i1\t%0,%1
1267 lbu%i1\t%0,%1
1268 sb%i0\t%z1,%0
1269- sbi\t%z1,%0"
1270+ sb%i0\t%z1,%0"
1271 [(set_attr "type" "arith,arith,move,load,no_delay_load,store,no_delay_store")
1272 (set_attr "mode" "QI")
1273 (set_attr "length" "4,4,8,4,8,4,8")])
1274@@ -1421,7 +1528,7 @@
1275 addik\t%0,r0,%F1
1276 lw%i1\t%0,%1
1277 sw%i0\t%z1,%0
1278- swi\t%z1,%0"
1279+ sw%i0\t%z1,%0"
1280 [(set_attr "type" "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store")
1281 (set_attr "mode" "SF")
1282 (set_attr "length" "4,4,4,4,4,4,4")])
1283@@ -1460,6 +1567,33 @@
1284 ;; movdf_internal
1285 ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
1286 ;;
1287+(define_insn "*movdf_internal_64"
1288+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
1289+ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
1290+ "TARGET_MB_64"
1291+ {
1292+ switch (which_alternative)
1293+ {
1294+ case 0:
1295+ return "addlk\t%0,%1,r0";
1296+ case 1:
1297+ return "addlk\t%0,r0,r0";
1298+ case 2:
1299+ case 4:
1300+ return "ll%i1\t%0,%1";
1301+ case 3:
1302+ {
1303+ return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo";
1304+ }
1305+ case 5:
1306+ return "sl%i0\t%1,%0";
1307+ }
1308+ gcc_unreachable ();
1309+ }
1310+ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
1311+ (set_attr "mode" "DF")
1312+ (set_attr "length" "4,4,4,16,4,4")])
1313+
1314 (define_insn "*movdf_internal"
1315 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o")
1316 (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))]
1317@@ -1494,7 +1628,8 @@
1318 "reload_completed
1319 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1320 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1321- && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))"
1322+ && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))
1323+ && !TARGET_MB_64"
1324 [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
1325 (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
1326 "")
1327@@ -1505,7 +1640,8 @@
1328 "reload_completed
1329 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1330 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1331- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
1332+ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))
1333+ && !TARGET_MB_64"
1334 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
1335 (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
1336 "")
1337@@ -2005,6 +2141,31 @@ else
1338 "
1339 )
1340
1341+
1342+(define_insn "seq_internal_pat_long"
1343+ [(set (match_operand:DI 0 "register_operand" "=d")
1344+ (eq:DI
1345+ (match_operand:DI 1 "register_operand" "d")
1346+ (match_operand:DI 2 "register_operand" "d")))]
1347+ "TARGET_MB_64"
1348+ "pcmpleq\t%0,%1,%2"
1349+ [(set_attr "type" "arith")
1350+ (set_attr "mode" "DI")
1351+ (set_attr "length" "4")]
1352+)
1353+
1354+(define_insn "sne_internal_pat_long"
1355+ [(set (match_operand:DI 0 "register_operand" "=d")
1356+ (ne:DI
1357+ (match_operand:DI 1 "register_operand" "d")
1358+ (match_operand:DI 2 "register_operand" "d")))]
1359+ "TARGET_MB_64"
1360+ "pcmplne\t%0,%1,%2"
1361+ [(set_attr "type" "arith")
1362+ (set_attr "mode" "DI")
1363+ (set_attr "length" "4")]
1364+)
1365+
1366 (define_insn "seq_internal_pat"
1367 [(set (match_operand:SI 0 "register_operand" "=d")
1368 (eq:SI
1369@@ -2065,8 +2226,8 @@ else
1370 (define_expand "cbranchsi4"
1371 [(set (pc)
1372 (if_then_else (match_operator 0 "ordered_comparison_operator"
1373- [(match_operand:SI 1 "register_operand")
1374- (match_operand:SI 2 "arith_operand" "I,i")])
1375+ [(match_operand 1 "register_operand")
1376+ (match_operand 2 "arith_operand" "I,i")])
1377 (label_ref (match_operand 3 ""))
1378 (pc)))]
1379 ""
1380@@ -2078,13 +2239,13 @@ else
1381 (define_expand "cbranchsi4_reg"
1382 [(set (pc)
1383 (if_then_else (match_operator 0 "ordered_comparison_operator"
1384- [(match_operand:SI 1 "register_operand")
1385- (match_operand:SI 2 "register_operand")])
1386+ [(match_operand 1 "register_operand")
1387+ (match_operand 2 "register_operand")])
1388 (label_ref (match_operand 3 ""))
1389 (pc)))]
1390 ""
1391 {
1392- microblaze_expand_conditional_branch_reg (SImode, operands);
1393+ microblaze_expand_conditional_branch_reg (Pmode, operands);
1394 DONE;
1395 })
1396
1397@@ -2109,6 +2270,26 @@ else
1398 (label_ref (match_operand 1))
1399 (pc)))])
1400
1401+(define_insn "branch_zero64"
1402+ [(set (pc)
1403+ (if_then_else (match_operator 0 "ordered_comparison_operator"
1404+ [(match_operand 1 "register_operand" "d")
1405+ (const_int 0)])
1406+ (match_operand 2 "pc_or_label_operand" "")
1407+ (match_operand 3 "pc_or_label_operand" "")))
1408+ ]
1409+ "TARGET_MB_64"
1410+ {
1411+ if (operands[3] == pc_rtx)
1412+ return "bea%C0i%?\t%z1,%2";
1413+ else
1414+ return "bea%N0i%?\t%z1,%3";
1415+ }
1416+ [(set_attr "type" "branch")
1417+ (set_attr "mode" "none")
1418+ (set_attr "length" "4")]
1419+)
1420+
1421 (define_insn "branch_zero"
1422 [(set (pc)
1423 (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
1424@@ -2129,6 +2310,47 @@ else
1425 (set_attr "length" "4")]
1426 )
1427
1428+(define_insn "branch_compare64"
1429+ [(set (pc)
1430+ (if_then_else (match_operator 0 "cmp_op"
1431+ [(match_operand 1 "register_operand" "d")
1432+ (match_operand 2 "register_operand" "d")
1433+ ])
1434+ (label_ref (match_operand 3))
1435+ (pc)))
1436+ (clobber(reg:SI R_TMP))]
1437+ "TARGET_MB_64"
1438+ {
1439+ operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
1440+ enum rtx_code code = GET_CODE (operands[0]);
1441+
1442+ if (code == GT || code == LE)
1443+ {
1444+ output_asm_insn ("cmp\tr18,%z1,%z2", operands);
1445+ code = swap_condition (code);
1446+ }
1447+ else if (code == GTU || code == LEU)
1448+ {
1449+ output_asm_insn ("cmpu\tr18,%z1,%z2", operands);
1450+ code = swap_condition (code);
1451+ }
1452+ else if (code == GE || code == LT)
1453+ {
1454+ output_asm_insn ("cmp\tr18,%z2,%z1", operands);
1455+ }
1456+ else if (code == GEU || code == LTU)
1457+ {
1458+ output_asm_insn ("cmpu\tr18,%z2,%z1", operands);
1459+ }
1460+
1461+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx);
1462+ return "bea%C0i%?\tr18,%3";
1463+ }
1464+ [(set_attr "type" "branch")
1465+ (set_attr "mode" "none")
1466+ (set_attr "length" "12")]
1467+)
1468+
1469 (define_insn "branch_compare"
1470 [(set (pc)
1471 (if_then_else (match_operator:SI 0 "cmp_op"
1472@@ -2312,7 +2534,7 @@ else
1473 ;; Indirect jumps. Jump to register values. Assuming absolute jumps
1474
1475 (define_insn "indirect_jump_internal1"
1476- [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
1477+ [(set (pc) (match_operand 0 "register_operand" "d"))]
1478 ""
1479 "bra%?\t%0"
1480 [(set_attr "type" "jump")
1481@@ -2325,7 +2547,7 @@ else
1482 (use (label_ref (match_operand 1 "" "")))]
1483 ""
1484 {
1485- gcc_assert (GET_MODE (operands[0]) == Pmode);
1486+ //gcc_assert (GET_MODE (operands[0]) == Pmode);
1487
1488 if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
1489 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
1490@@ -2337,7 +2559,7 @@ else
1491
1492 (define_insn "tablejump_internal1"
1493 [(set (pc)
1494- (match_operand:SI 0 "register_operand" "d"))
1495+ (match_operand 0 "register_operand" "d"))
1496 (use (label_ref (match_operand 1 "" "")))]
1497 ""
1498 "bra%?\t%0 "
1499@@ -2347,9 +2569,9 @@ else
1500
1501 (define_expand "tablejump_internal3"
1502 [(parallel [(set (pc)
1503- (plus:SI (match_operand:SI 0 "register_operand" "d")
1504- (label_ref:SI (match_operand:SI 1 "" ""))))
1505- (use (label_ref:SI (match_dup 1)))])]
1506+ (plus (match_operand 0 "register_operand" "d")
1507+ (label_ref (match_operand:SI 1 "" ""))))
1508+ (use (label_ref (match_dup 1)))])]
1509 ""
1510 ""
1511 )
1512@@ -2410,7 +2632,7 @@ else
1513 (minus (reg 1) (match_operand 1 "register_operand" "")))
1514 (set (reg 1)
1515 (minus (reg 1) (match_dup 1)))]
1516- ""
1517+ "!TARGET_MB_64"
1518 {
1519 rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
1520 rtx reg = gen_reg_rtx (Pmode);
1521@@ -2435,7 +2657,7 @@ else
1522 (define_expand "save_stack_block"
1523 [(match_operand 0 "register_operand" "")
1524 (match_operand 1 "register_operand" "")]
1525- ""
1526+ "!TARGET_MB_64"
1527 {
1528 emit_move_insn (operands[0], operands[1]);
1529 DONE;
1530@@ -2445,7 +2667,7 @@ else
1531 (define_expand "restore_stack_block"
1532 [(match_operand 0 "register_operand" "")
1533 (match_operand 1 "register_operand" "")]
1534- ""
1535+ "!TARGET_MB_64"
1536 {
1537 rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
1538 rtx rtmp = gen_rtx_REG (SImode, R_TMP);
1539@@ -2492,7 +2714,7 @@ else
1540
1541 (define_insn "<optab>_internal"
1542 [(any_return)
1543- (use (match_operand:SI 0 "register_operand" ""))]
1544+ (use (match_operand 0 "register_operand" ""))]
1545 ""
1546 {
1547 if (microblaze_is_break_handler ())
1548@@ -2525,7 +2747,7 @@ else
1549 (define_expand "call"
1550 [(parallel [(call (match_operand 0 "memory_operand" "m")
1551 (match_operand 1 "" "i"))
1552- (clobber (reg:SI R_SR))
1553+ (clobber (reg R_SR))
1554 (use (match_operand 2 "" ""))
1555 (use (match_operand 3 "" ""))])]
1556 ""
1557@@ -2546,12 +2768,12 @@ else
1558
1559 if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC)
1560 emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1],
1561- gen_rtx_REG (SImode,
1562+ gen_rtx_REG (Pmode,
1563 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM),
1564 pic_offset_table_rtx));
1565 else
1566 emit_call_insn (gen_call_internal0 (operands[0], operands[1],
1567- gen_rtx_REG (SImode,
1568+ gen_rtx_REG (Pmode,
1569 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
1570
1571 DONE;
1572@@ -2561,7 +2783,7 @@ else
1573 (define_expand "call_internal0"
1574 [(parallel [(call (match_operand 0 "" "")
1575 (match_operand 1 "" ""))
1576- (clobber (match_operand:SI 2 "" ""))])]
1577+ (clobber (match_operand 2 "" ""))])]
1578 ""
1579 {
1580 }
1581@@ -2570,18 +2792,34 @@ else
1582 (define_expand "call_internal_plt0"
1583 [(parallel [(call (match_operand 0 "" "")
1584 (match_operand 1 "" ""))
1585- (clobber (match_operand:SI 2 "" ""))
1586- (use (match_operand:SI 3 "" ""))])]
1587+ (clobber (match_operand 2 "" ""))
1588+ (use (match_operand 3 "" ""))])]
1589 ""
1590 {
1591 }
1592 )
1593
1594+(define_insn "call_internal_plt_64"
1595+ [(call (mem (match_operand 0 "call_insn_plt_operand" ""))
1596+ (match_operand 1 "" "i"))
1597+ (clobber (reg R_SR))
1598+ (use (reg R_GOT))]
1599+ "flag_pic && TARGET_MB_64"
1600+ {
1601+ register rtx target2 = gen_rtx_REG (Pmode,
1602+ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
1603+ gen_rtx_CLOBBER (VOIDmode, target2);
1604+ return "brealid\tr15,%0\;%#";
1605+ }
1606+ [(set_attr "type" "call")
1607+ (set_attr "mode" "none")
1608+ (set_attr "length" "4")])
1609+
1610 (define_insn "call_internal_plt"
1611- [(call (mem (match_operand:SI 0 "call_insn_plt_operand" ""))
1612- (match_operand:SI 1 "" "i"))
1613- (clobber (reg:SI R_SR))
1614- (use (reg:SI R_GOT))]
1615+ [(call (mem (match_operand 0 "call_insn_plt_operand" ""))
1616+ (match_operand 1 "" "i"))
1617+ (clobber (reg R_SR))
1618+ (use (reg R_GOT))]
1619 "flag_pic"
1620 {
1621 register rtx target2 = gen_rtx_REG (Pmode,
1622@@ -2593,10 +2831,41 @@ else
1623 (set_attr "mode" "none")
1624 (set_attr "length" "4")])
1625
1626+(define_insn "call_internal1_64"
1627+ [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
1628+ (match_operand 1 "" "i"))
1629+ (clobber (reg R_SR))]
1630+ "TARGET_MB_64"
1631+ {
1632+ register rtx target = operands[0];
1633+ register rtx target2 = gen_rtx_REG (Pmode,
1634+ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
1635+ if (GET_CODE (target) == SYMBOL_REF) {
1636+ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) {
1637+ gen_rtx_CLOBBER (VOIDmode, target2);
1638+ return "breaki\tr16,%0\;%#";
1639+ }
1640+ else {
1641+ gen_rtx_CLOBBER (VOIDmode, target2);
1642+ return "brealid\tr15,%0\;%#";
1643+ }
1644+ } else if (GET_CODE (target) == CONST_INT)
1645+ return "la\t%@,r0,%0\;brald\tr15,%@\;%#";
1646+ else if (GET_CODE (target) == REG)
1647+ return "brald\tr15,%0\;%#";
1648+ else {
1649+ fprintf (stderr,"Unsupported call insn\n");
1650+ return NULL;
1651+ }
1652+ }
1653+ [(set_attr "type" "call")
1654+ (set_attr "mode" "none")
1655+ (set_attr "length" "4")])
1656+
1657 (define_insn "call_internal1"
1658 [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
1659- (match_operand:SI 1 "" "i"))
1660- (clobber (reg:SI R_SR))]
1661+ (match_operand 1 "" "i"))
1662+ (clobber (reg R_SR))]
1663 ""
1664 {
1665 register rtx target = operands[0];
1666@@ -2630,7 +2899,7 @@ else
1667 [(parallel [(set (match_operand 0 "register_operand" "=d")
1668 (call (match_operand 1 "memory_operand" "m")
1669 (match_operand 2 "" "i")))
1670- (clobber (reg:SI R_SR))
1671+ (clobber (reg R_SR))
1672 (use (match_operand 3 "" ""))])] ;; next_arg_reg
1673 ""
1674 {
1675@@ -2651,13 +2920,13 @@ else
1676 if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC)
1677 emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1],
1678 operands[2],
1679- gen_rtx_REG (SImode,
1680+ gen_rtx_REG (Pmode,
1681 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM),
1682 pic_offset_table_rtx));
1683 else
1684 emit_call_insn (gen_call_value_internal (operands[0], operands[1],
1685 operands[2],
1686- gen_rtx_REG (SImode,
1687+ gen_rtx_REG (Pmode,
1688 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
1689
1690 DONE;
1691@@ -2669,7 +2938,7 @@ else
1692 [(parallel [(set (match_operand 0 "" "")
1693 (call (match_operand 1 "" "")
1694 (match_operand 2 "" "")))
1695- (clobber (match_operand:SI 3 "" ""))
1696+ (clobber (match_operand 3 "" ""))
1697 ])]
1698 ""
1699 {}
1700@@ -2679,18 +2948,35 @@ else
1701 [(parallel[(set (match_operand 0 "" "")
1702 (call (match_operand 1 "" "")
1703 (match_operand 2 "" "")))
1704- (clobber (match_operand:SI 3 "" ""))
1705- (use (match_operand:SI 4 "" ""))])]
1706+ (clobber (match_operand 3 "" ""))
1707+ (use (match_operand 4 "" ""))])]
1708 "flag_pic"
1709 {}
1710 )
1711
1712+(define_insn "call_value_intern_plt_64"
1713+ [(set (match_operand:VOID 0 "register_operand" "=d")
1714+ (call (mem (match_operand 1 "call_insn_plt_operand" ""))
1715+ (match_operand 2 "" "i")))
1716+ (clobber (match_operand 3 "register_operand" "=d"))
1717+ (use (match_operand 4 "register_operand"))]
1718+ "flag_pic && TARGET_MB_64"
1719+ {
1720+ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
1721+
1722+ gen_rtx_CLOBBER (VOIDmode,target2);
1723+ return "brealid\tr15,%1\;%#";
1724+ }
1725+ [(set_attr "type" "call")
1726+ (set_attr "mode" "none")
1727+ (set_attr "length" "4")])
1728+
1729 (define_insn "call_value_intern_plt"
1730 [(set (match_operand:VOID 0 "register_operand" "=d")
1731- (call (mem (match_operand:SI 1 "call_insn_plt_operand" ""))
1732- (match_operand:SI 2 "" "i")))
1733- (clobber (match_operand:SI 3 "register_operand" "=d"))
1734- (use (match_operand:SI 4 "register_operand"))]
1735+ (call (mem (match_operand 1 "call_insn_plt_operand" ""))
1736+ (match_operand 2 "" "i")))
1737+ (clobber (match_operand 3 "register_operand" "=d"))
1738+ (use (match_operand 4 "register_operand"))]
1739 "flag_pic"
1740 {
1741 register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
1742@@ -2702,11 +2988,46 @@ else
1743 (set_attr "mode" "none")
1744 (set_attr "length" "4")])
1745
1746+(define_insn "call_value_intern_64"
1747+ [(set (match_operand:VOID 0 "register_operand" "=d")
1748+ (call (mem (match_operand:VOID 1 "call_insn_operand" "ri"))
1749+ (match_operand 2 "" "i")))
1750+ (clobber (match_operand 3 "register_operand" "=d"))]
1751+ "TARGET_MB_64"
1752+ {
1753+ register rtx target = operands[1];
1754+ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
1755+
1756+ if (GET_CODE (target) == SYMBOL_REF)
1757+ {
1758+ gen_rtx_CLOBBER (VOIDmode,target2);
1759+ if (microblaze_break_function_p (SYMBOL_REF_DECL (target)))
1760+ return "breaki\tr16,%1\;%#";
1761+ else if (SYMBOL_REF_FLAGS (target) & SYMBOL_FLAG_FUNCTION)
1762+ {
1763+ return "brealid\tr15,%1\;%#";
1764+ }
1765+ else
1766+ {
1767+ return "bralid\tr15,%1\;%#";
1768+ }
1769+ }
1770+ else if (GET_CODE (target) == CONST_INT)
1771+ return "la\t%@,r0,%1\;brald\tr15,%@\;%#";
1772+ else if (GET_CODE (target) == REG)
1773+ return "brald\tr15,%1\;%#";
1774+ else
1775+ return "Unsupported call insn\n";
1776+ }
1777+ [(set_attr "type" "call")
1778+ (set_attr "mode" "none")
1779+ (set_attr "length" "4")])
1780+
1781 (define_insn "call_value_intern"
1782 [(set (match_operand:VOID 0 "register_operand" "=d")
1783 (call (mem (match_operand:VOID 1 "call_insn_operand" "ri"))
1784- (match_operand:SI 2 "" "i")))
1785- (clobber (match_operand:SI 3 "register_operand" "=d"))]
1786+ (match_operand 2 "" "i")))
1787+ (clobber (match_operand 3 "register_operand" "=d"))]
1788 ""
1789 {
1790 register rtx target = operands[1];
1791@@ -2880,7 +3201,6 @@ else
1792
1793 ;;if (!register_operand (operands[0], VOIDmode))
1794 ;; FAIL;
1795-
1796 emit_insn (gen_insv_32 (operands[0], operands[1],
1797 operands[2], operands[3]));
1798 DONE;
1799diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
1800index 7671f63..9fc80b1 100644
1801--- a/gcc/config/microblaze/t-microblaze
1802+++ b/gcc/config/microblaze/t-microblaze
1803@@ -2,10 +2,11 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en
1804 MULTILIB_DIRNAMES = bs m mh le m64
1805 MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
1806 MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
1807-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
1808+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
1809+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
1810 MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
1811-#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
1812-#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
1813+MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
1814+MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
1815
1816 # Extra files
1817 microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
1818diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
1819index ee380ee..1811327 100644
1820--- a/libgcc/config/microblaze/crti.S
1821+++ b/libgcc/config/microblaze/crti.S
1822@@ -40,7 +40,7 @@
1823
1824 .align 2
1825 __init:
1826- addik r1, r1, -8
1827+ addik r1, r1, -16
1828 sw r15, r0, r1
1829 la r11, r0, _stack
1830 mts rshr, r11
1831@@ -51,5 +51,5 @@ __init:
1832 .global __fini
1833 .align 2
1834 __fini:
1835- addik r1, r1, -8
1836+ addik r1, r1, -16
1837 sw r15, r0, r1
1838diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
1839index 00d398a..60a4648 100644
1840--- a/libgcc/config/microblaze/crtn.S
1841+++ b/libgcc/config/microblaze/crtn.S
1842@@ -33,9 +33,9 @@
1843 .section .init, "ax"
1844 lw r15, r0, r1
1845 rtsd r15, 8
1846- addik r1, r1, 8
1847+ addik r1, r1, 16
1848
1849 .section .fini, "ax"
1850 lw r15, r0, r1
1851 rtsd r15, 8
1852- addik r1, r1, 8
1853+ addik r1, r1, 16
1854diff --git a/libgcc/config/microblaze/divdi3.S b/libgcc/config/microblaze/divdi3.S
1855new file mode 100644
1856index 0000000..d37bf51
1857--- /dev/null
1858+++ b/libgcc/config/microblaze/divdi3.S
1859@@ -0,0 +1,98 @@
1860+###################################-
1861+#
1862+# Copyright (C) 2009-2017 Free Software Foundation, Inc.
1863+#
1864+# Contributed by Michael Eager <eager@eagercon.com>.
1865+#
1866+# This file is free software; you can redistribute it and/or modify it
1867+# under the terms of the GNU General Public License as published by the
1868+# Free Software Foundation; either version 3, or (at your option) any
1869+# later version.
1870+#
1871+# GCC is distributed in the hope that it will be useful, but WITHOUT
1872+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
1873+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
1874+# License for more details.
1875+#
1876+# Under Section 7 of GPL version 3, you are granted additional
1877+# permissions described in the GCC Runtime Library Exception, version
1878+# 3.1, as published by the Free Software Foundation.
1879+#
1880+# You should have received a copy of the GNU General Public License and
1881+# a copy of the GCC Runtime Library Exception along with this program;
1882+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
1883+# <http://www.gnu.org/licenses/>.
1884+#
1885+# divdi3.S
1886+#
1887+# Divide operation for 32 bit integers.
1888+# Input : Dividend in Reg r5
1889+# Divisor in Reg r6
1890+# Output: Result in Reg r3
1891+#
1892+#######################################
1893+
1894+#ifdef __arch64__
1895+ .globl __divdi3
1896+ .ent __divdi3
1897+ .type __divdi3,@function
1898+__divdi3:
1899+ .frame r1,0,r15
1900+
1901+ ADDLIK r1,r1,-32
1902+ SLI r28,r1,0
1903+ SLI r29,r1,8
1904+ SLI r30,r1,16
1905+ SLI r31,r1,24
1906+
1907+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
1908+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero
1909+ XORL r28,r5,r6 # Get the sign of the result
1910+ BEALGEI r5,$LaR5_Pos
1911+ RSUBLI r5,r5,0 # Make r5 positive
1912+$LaR5_Pos:
1913+ BEALGEI r6,$LaR6_Pos
1914+ RSUBLI r6,r6,0 # Make r6 positive
1915+$LaR6_Pos:
1916+ ADDLIK r30,r0,0 # Clear mod
1917+ ADDLIK r3,r0,0 # clear div
1918+ ADDLIK r29,r0,64 # Initialize the loop count
1919+
1920+ # First part try to find the first '1' in the r5
1921+$LaDIV0:
1922+ BEALLTI r5,$LaDIV2 # This traps r5 == 0x80000000
1923+$LaDIV1:
1924+ ADDL r5,r5,r5 # left shift logical r5
1925+ ADDLIK r29,r29,-1
1926+ BEALGTI r5,$LaDIV1
1927+$LaDIV2:
1928+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry
1929+ ADDLC r30,r30,r30 # Move that bit into the Mod register
1930+ RSUBL r31,r6,r30 # Try to subtract (r30 a r6)
1931+ BEALLTI r31,$LaMOD_TOO_SMALL
1932+ ORL r30,r0,r31 # Move the r31 to mod since the result was positive
1933+ ADDLIK r3,r3,1
1934+$LaMOD_TOO_SMALL:
1935+ ADDLIK r29,r29,-1
1936+ BEALEQi r29,$LaLOOP_END
1937+ ADDL r3,r3,r3 # Shift in the '1' into div
1938+ BREAI $LaDIV2 # Div2
1939+$LaLOOP_END:
1940+ BEALGEI r28,$LaRETURN_HERE
1941+ RSUBLI r3,r3,0 # Negate the result
1942+ BREAI $LaRETURN_HERE
1943+$LaDiv_By_Zero:
1944+$LaResult_Is_Zero:
1945+ ORL r3,r0,r0 # set result to 0
1946+$LaRETURN_HERE:
1947+# Restore values of CSRs and that of r3 and the divisor and the dividend
1948+ LLI r28,r1,0
1949+ LLI r29,r1,8
1950+ LLI r30,r1,16
1951+ LLI r31,r1,24
1952+ ADDLIK r1,r1,32
1953+ RTSD r15,8
1954+ nop
1955+.end __divdi3
1956+ .size __divdi3, . - __divdi3
1957+#endif
1958diff --git a/libgcc/config/microblaze/divdi3_table.c b/libgcc/config/microblaze/divdi3_table.c
1959new file mode 100644
1960index 0000000..8096259
1961--- /dev/null
1962+++ b/libgcc/config/microblaze/divdi3_table.c
1963@@ -0,0 +1,62 @@
1964+/* Table for software lookup divide for Xilinx MicroBlaze.
1965+
1966+ Copyright (C) 2009-2017 Free Software Foundation, Inc.
1967+
1968+ Contributed by Michael Eager <eager@eagercon.com>.
1969+
1970+ This file is free software; you can redistribute it and/or modify it
1971+ under the terms of the GNU General Public License as published by the
1972+ Free Software Foundation; either version 3, or (at your option) any
1973+ later version.
1974+
1975+ GCC is distributed in the hope that it will be useful, but WITHOUT
1976+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
1977+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
1978+ License for more details.
1979+
1980+ Under Section 7 of GPL version 3, you are granted additional
1981+ permissions described in the GCC Runtime Library Exception, version
1982+ 3.1, as published by the Free Software Foundation.
1983+
1984+ You should have received a copy of the GNU General Public License and
1985+ a copy of the GCC Runtime Library Exception along with this program;
1986+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
1987+ <http://www.gnu.org/licenses/>. */
1988+
1989+
1990+unsigned char _divdi3_table[] =
1991+{
1992+ 0, 0/1, 0/2, 0/3, 0/4, 0/5, 0/6, 0/7,
1993+ 0/8, 0/9, 0/10, 0/11, 0/12, 0/13, 0/14, 0/15,
1994+ 0, 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7,
1995+ 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14, 1/15,
1996+ 0, 2/1, 2/2, 2/3, 2/4, 2/5, 2/6, 2/7,
1997+ 2/8, 2/9, 2/10, 2/11, 2/12, 2/13, 2/14, 2/15,
1998+ 0, 3/1, 3/2, 3/3, 3/4, 3/5, 3/6, 3/7,
1999+ 3/8, 3/9, 3/10, 3/11, 3/12, 3/13, 3/14, 3/15,
2000+ 0, 4/1, 4/2, 4/3, 4/4, 4/5, 4/6, 4/7,
2001+ 4/8, 4/9, 4/10, 4/11, 4/12, 4/13, 4/14, 4/15,
2002+ 0, 5/1, 5/2, 5/3, 5/4, 5/5, 5/6, 5/7,
2003+ 5/8, 5/9, 5/10, 5/11, 5/12, 5/13, 5/14, 5/15,
2004+ 0, 6/1, 6/2, 6/3, 6/4, 6/5, 6/6, 6/7,
2005+ 6/8, 6/9, 6/10, 6/11, 6/12, 6/13, 6/14, 6/15,
2006+ 0, 7/1, 7/2, 7/3, 7/4, 7/5, 7/6, 7/7,
2007+ 7/8, 7/9, 7/10, 7/11, 7/12, 7/13, 7/14, 7/15,
2008+ 0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, 8/7,
2009+ 8/8, 8/9, 8/10, 8/11, 8/12, 8/13, 8/14, 8/15,
2010+ 0, 9/1, 9/2, 9/3, 9/4, 9/5, 9/6, 9/7,
2011+ 9/8, 9/9, 9/10, 9/11, 9/12, 9/13, 9/14, 9/15,
2012+ 0, 10/1, 10/2, 10/3, 10/4, 10/5, 10/6, 10/7,
2013+ 10/8, 10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15,
2014+ 0, 11/1, 11/2, 11/3, 11/4, 11/5, 11/6, 11/7,
2015+ 11/8, 11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15,
2016+ 0, 12/1, 12/2, 12/3, 12/4, 12/5, 12/6, 12/7,
2017+ 12/8, 12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15,
2018+ 0, 13/1, 13/2, 13/3, 13/4, 13/5, 13/6, 13/7,
2019+ 13/8, 13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15,
2020+ 0, 14/1, 14/2, 14/3, 14/4, 14/5, 14/6, 14/7,
2021+ 14/8, 14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15,
2022+ 0, 15/1, 15/2, 15/3, 15/4, 15/5, 15/6, 15/7,
2023+ 15/8, 15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15,
2024+};
2025+
2026diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
2027new file mode 100644
2028index 0000000..5d3f7c0
2029--- /dev/null
2030+++ b/libgcc/config/microblaze/moddi3.S
2031@@ -0,0 +1,97 @@
2032+###################################
2033+#
2034+# Copyright (C) 2009-2017 Free Software Foundation, Inc.
2035+#
2036+# Contributed by Michael Eager <eager@eagercon.com>.
2037+#
2038+# This file is free software; you can redistribute it and/or modify it
2039+# under the terms of the GNU General Public License as published by the
2040+# Free Software Foundation; either version 3, or (at your option) any
2041+# later version.
2042+#
2043+# GCC is distributed in the hope that it will be useful, but WITHOUT
2044+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
2045+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
2046+# License for more details.
2047+#
2048+# Under Section 7 of GPL version 3, you are granted additional
2049+# permissions described in the GCC Runtime Library Exception, version
2050+# 3.1, as published by the Free Software Foundation.
2051+#
2052+# You should have received a copy of the GNU General Public License and
2053+# a copy of the GCC Runtime Library Exception along with this program;
2054+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2055+# <http://www.gnu.org/licenses/>.
2056+#
2057+# moddi3.S
2058+#
2059+# modulo operation for 32 bit integers.
2060+# Input : op1 in Reg r5
2061+# op2 in Reg r6
2062+# Output: op1 mod op2 in Reg r3
2063+#
2064+#######################################
2065+
2066+#ifdef __arch64__
2067+ .globl __moddi3
2068+ .ent __moddi3
2069+ .type __moddi3,@function
2070+__moddi3:
2071+ .frame r1,0,r15
2072+
2073+ addlik r1,r1,-32
2074+ sli r28,r1,0
2075+ sli r29,r1,8
2076+ sli r30,r1,16
2077+ sli r31,r1,32
2078+
2079+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
2080+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero
2081+ ADDL r28,r5,r0 # Get the sign of the result [ Depends only on the first arg]
2082+ BEALGEI r5,$LaR5_Pos
2083+ RSUBLI r5,r5,0 # Make r5 positive
2084+$LaR5_Pos:
2085+ BEALGEI r6,$LaR6_Pos
2086+ RSUBLI r6,r6,0 # Make r6 positive
2087+$LaR6_Pos:
2088+ ADDLIK r3,r0,0 # Clear mod
2089+ ADDLIK r30,r0,0 # clear div
2090+ ADDLIK r29,r0,64 # Initialize the loop count
2091+ BEALLTI r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
2092+ # the first bit search.
2093+ # First part try to find the first '1' in the r5
2094+$LaDIV1:
2095+ ADDL r5,r5,r5 # left shift logical r5
2096+ ADDLIK r29,r29,-1
2097+ BEALGEI r5,$LaDIV1 #
2098+$LaDIV2:
2099+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry
2100+ ADDLC r3,r3,r3 # Move that bit into the Mod register
2101+ rSUBL r31,r6,r3 # Try to subtract (r30 a r6)
2102+ BEALLTi r31,$LaMOD_TOO_SMALL
2103+ ORL r3,r0,r31 # Move the r31 to mod since the result was positive
2104+ ADDLIK r30,r30,1
2105+$LaMOD_TOO_SMALL:
2106+ ADDLIK r29,r29,-1
2107+ BEALEQi r29,$LaLOOP_END
2108+ ADDL r30,r30,r30 # Shift in the '1' into div
2109+ BREAI $LaDIV2 # Div2
2110+$LaLOOP_END:
2111+ BEALGEI r28,$LaRETURN_HERE
2112+ rsubli r3,r3,0 # Negate the result
2113+ BREAI $LaRETURN_HERE
2114+$LaDiv_By_Zero:
2115+$LaResult_Is_Zero:
2116+ orl r3,r0,r0 # set result to 0 [Both mod as well as div are 0]
2117+$LaRETURN_HERE:
2118+# Restore values of CSRs and that of r3 and the divisor and the dividend
2119+ lli r28,r1,0
2120+ lli r29,r1,8
2121+ lli r30,r1,16
2122+ lli r31,r1,24
2123+ addlik r1,r1,32
2124+ rtsd r15,8
2125+ nop
2126+ .end __moddi3
2127+ .size __moddi3, . - __moddi3
2128+#endif
2129diff --git a/libgcc/config/microblaze/muldi3.S b/libgcc/config/microblaze/muldi3.S
2130new file mode 100644
2131index 0000000..5677841
2132--- /dev/null
2133+++ b/libgcc/config/microblaze/muldi3.S
2134@@ -0,0 +1,73 @@
2135+/*###################################-*-asm*-
2136+#
2137+# Copyright (C) 2009-2017 Free Software Foundation, Inc.
2138+#
2139+# Contributed by Michael Eager <eager@eagercon.com>.
2140+#
2141+# This file is free software; you can redistribute it and/or modify it
2142+# under the terms of the GNU General Public License as published by the
2143+# Free Software Foundation; either version 3, or (at your option) any
2144+# later version.
2145+#
2146+# GCC is distributed in the hope that it will be useful, but WITHOUT
2147+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
2148+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
2149+# License for more details.
2150+#
2151+# Under Section 7 of GPL version 3, you are granted additional
2152+# permissions described in the GCC Runtime Library Exception, version
2153+# 3.1, as published by the Free Software Foundation.
2154+#
2155+# You should have received a copy of the GNU General Public License and
2156+# a copy of the GCC Runtime Library Exception along with this program;
2157+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2158+# <http://www.gnu.org/licenses/>.
2159+#
2160+# muldi3.S
2161+#
2162+# Multiply operation for 32 bit integers.
2163+# Input : Operand1 in Reg r5
2164+# Operand2 in Reg r6
2165+# Output: Result [op1 * op2] in Reg r3
2166+#
2167+#######################################*/
2168+
2169+#ifdef __arch64__
2170+ .globl __muldi3
2171+ .ent __muldi3
2172+ .type __muldi3,@function
2173+__muldi3:
2174+ .frame r1,0,r15
2175+ addl r3,r0,r0
2176+ BEALEQI r5,$L_Result_Is_Zero # Multiply by Zero
2177+ BEALEQI r6,$L_Result_Is_Zero # Multiply by Zero
2178+ XORL r4,r5,r6 # Get the sign of the result
2179+ BEALGEI r5,$L_R5_Pos
2180+ RSUBLI r5,r5,0 # Make r5 positive
2181+$L_R5_Pos:
2182+ BEALGEI r6,$L_R6_Pos
2183+ RSUBLI r6,r6,0 # Make r6 positive
2184+$L_R6_Pos:
2185+ breai $L1
2186+$L2:
2187+ addl r5,r5,r5
2188+$L1:
2189+ srll r6,r6
2190+ addlc r7,r0,r0
2191+ bealeqi r7,$L2
2192+ addl r3,r3,r5
2193+ bealnei r6,$L2
2194+ beallti r4,$L_NegateResult
2195+ rtsd r15,8
2196+ nop
2197+$L_NegateResult:
2198+ rsubl r3,r3,r0
2199+ rtsd r15,8
2200+ nop
2201+$L_Result_Is_Zero:
2202+ addli r3,r0,0
2203+ rtsd r15,8
2204+ nop
2205+ .end __muldi3
2206+ .size __muldi3, . - __muldi3
2207+#endif
2208diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
2209index 8d954a4..35021b2 100644
2210--- a/libgcc/config/microblaze/t-microblaze
2211+++ b/libgcc/config/microblaze/t-microblaze
2212@@ -1,11 +1,16 @@
2213-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
2214+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \
2215+ _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3
2216
2217 LIB2ADD += \
2218 $(srcdir)/config/microblaze/divsi3.S \
2219+ $(srcdir)/config/microblaze/divdi3.S \
2220 $(srcdir)/config/microblaze/modsi3.S \
2221- $(srcdir)/config/microblaze/muldi3_hard.S \
2222+ $(srcdir)/config/microblaze/moddi3.S \
2223 $(srcdir)/config/microblaze/mulsi3.S \
2224+ $(srcdir)/config/microblaze/muldi3.S \
2225 $(srcdir)/config/microblaze/stack_overflow_exit.S \
2226 $(srcdir)/config/microblaze/udivsi3.S \
2227+ $(srcdir)/config/microblaze/udivdi3.S \
2228 $(srcdir)/config/microblaze/umodsi3.S \
2229- $(srcdir)/config/microblaze/divsi3_table.c
2230+ $(srcdir)/config/microblaze/umoddi3.S \
2231+ $(srcdir)/config/microblaze/divsi3_table.c \
2232diff --git a/libgcc/config/microblaze/udivdi3.S b/libgcc/config/microblaze/udivdi3.S
2233new file mode 100644
2234index 0000000..c210fbc
2235--- /dev/null
2236+++ b/libgcc/config/microblaze/udivdi3.S
2237@@ -0,0 +1,107 @@
2238+###################################-
2239+#
2240+# Copyright (C) 2009-2017 Free Software Foundation, Inc.
2241+#
2242+# Contributed by Michael Eager <eager@eagercon.com>.
2243+#
2244+# This file is free software; you can redistribute it and/or modify it
2245+# under the terms of the GNU General Public License as published by the
2246+# Free Software Foundation; either version 3, or (at your option) any
2247+# later version.
2248+#
2249+# GCC is distributed in the hope that it will be useful, but WITHOUT
2250+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
2251+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
2252+# License for more details.
2253+#
2254+# Under Section 7 of GPL version 3, you are granted additional
2255+# permissions described in the GCC Runtime Library Exception, version
2256+# 3.1, as published by the Free Software Foundation.
2257+#
2258+# You should have received a copy of the GNU General Public License and
2259+# a copy of the GCC Runtime Library Exception along with this program;
2260+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2261+# <http://www.gnu.org/licenses/>.
2262+#
2263+# udivdi3.S
2264+#
2265+# Unsigned divide operation.
2266+# Input : Divisor in Reg r5
2267+# Dividend in Reg r6
2268+# Output: Result in Reg r3
2269+#
2270+#######################################
2271+
2272+#ifdef __arch64__
2273+ .globl __udivdi3
2274+ .ent __udivdi3
2275+ .type __udivdi3,@function
2276+__udivdi3:
2277+ .frame r1,0,r15
2278+
2279+ ADDlIK r1,r1,-24
2280+ SLI r29,r1,0
2281+ SLI r30,r1,8
2282+ SLI r31,r1,16
2283+
2284+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
2285+ ADDLIK r30,r0,0 # Clear mod
2286+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero
2287+ ADDLIK r29,r0,64 # Initialize the loop count
2288+
2289+ # Check if r6 and r5 are equal # if yes, return 1
2290+ RSUBL r18,r5,r6
2291+ ADDLIK r3,r0,1
2292+ BEALEQI r18,$LaRETURN_HERE
2293+
2294+ # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
2295+ XORL r18,r5,r6
2296+ ADDL r3,r0,r0 # We would anyways clear r3
2297+ BEALGEI r18,$LRSUBL
2298+ BEALLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater
2299+ BREAI $LCheckr6
2300+$LRSUBL:
2301+ RSUBL r18,r6,r5 # MICROBLAZEcmp
2302+ BEALLTI r18,$LaRETURN_HERE
2303+
2304+ # If r6 [bit 31] is set, then return result as 1
2305+$LCheckr6:
2306+ BEALGTI r6,$LaDIV0
2307+ ADDLIK r3,r0,1
2308+ BREAI $LaRETURN_HERE
2309+
2310+ # First part try to find the first '1' in the r5
2311+$LaDIV0:
2312+ BEALLTI r5,$LaDIV2
2313+$LaDIV1:
2314+ ADDL r5,r5,r5 # left shift logical r5
2315+ ADDLIK r29,r29,-1
2316+ BEALGTI r5,$LaDIV1
2317+$LaDIV2:
2318+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry
2319+ ADDLC r30,r30,r30 # Move that bit into the Mod register
2320+ RSUBL r31,r6,r30 # Try to subtract (r30 a r6)
2321+ BEALLTI r31,$LaMOD_TOO_SMALL
2322+ ORL r30,r0,r31 # Move the r31 to mod since the result was positive
2323+ ADDLIK r3,r3,1
2324+$LaMOD_TOO_SMALL:
2325+ ADDLIK r29,r29,-1
2326+ BEALEQi r29,$LaLOOP_END
2327+ ADDL r3,r3,r3 # Shift in the '1' into div
2328+ BREAI $LaDIV2 # Div2
2329+$LaLOOP_END:
2330+ BREAI $LaRETURN_HERE
2331+$LaDiv_By_Zero:
2332+$LaResult_Is_Zero:
2333+ ORL r3,r0,r0 # set result to 0
2334+$LaRETURN_HERE:
2335+ # Restore values of CSRs and that of r3 and the divisor and the dividend
2336+ LLI r29,r1,0
2337+ LLI r30,r1,8
2338+ LLI r31,r1,16
2339+ ADDLIK r1,r1,24
2340+ RTSD r15,8
2341+ NOP
2342+ .end __udivdi3
2343+ .size __udivdi3, . - __udivdi3
2344+#endif
2345diff --git a/libgcc/config/microblaze/umoddi3.S b/libgcc/config/microblaze/umoddi3.S
2346new file mode 100644
2347index 0000000..7f5cd23
2348--- /dev/null
2349+++ b/libgcc/config/microblaze/umoddi3.S
2350@@ -0,0 +1,110 @@
2351+###################################
2352+#
2353+# Copyright (C) 2009-2017 Free Software Foundation, Inc.
2354+#
2355+# Contributed by Michael Eager <eager@eagercon.com>.
2356+#
2357+# This file is free software; you can redistribute it and/or modify it
2358+# under the terms of the GNU General Public License as published by the
2359+# Free Software Foundation; either version 3, or (at your option) any
2360+# later version.
2361+#
2362+# GCC is distributed in the hope that it will be useful, but WITHOUT
2363+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
2364+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
2365+# License for more details.
2366+#
2367+# Under Section 7 of GPL version 3, you are granted additional
2368+# permissions described in the GCC Runtime Library Exception, version
2369+# 3.1, as published by the Free Software Foundation.
2370+#
2371+# You should have received a copy of the GNU General Public License and
2372+# a copy of the GCC Runtime Library Exception along with this program;
2373+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2374+# <http://www.gnu.org/licenses/>.
2375+#
2376+# umoddi3.S
2377+#
2378+# Unsigned modulo operation for 32 bit integers.
2379+# Input : op1 in Reg r5
2380+# op2 in Reg r6
2381+# Output: op1 mod op2 in Reg r3
2382+#
2383+#######################################
2384+
2385+#ifdef __arch64__
2386+ .globl __umoddi3
2387+ .ent __umoddi3
2388+ .type __umoddi3,@function
2389+__umoddi3:
2390+ .frame r1,0,r15
2391+
2392+ addlik r1,r1,-24
2393+ sli r29,r1,0
2394+ sli r30,r1,8
2395+ sli r31,r1,16
2396+
2397+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
2398+ ADDLIK r3,r0,0 # Clear div
2399+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero
2400+ ADDLIK r30,r0,0 # clear mod
2401+ ADDLIK r29,r0,64 # Initialize the loop count
2402+
2403+# Check if r6 and r5 are equal # if yes, return 0
2404+ rsubl r18,r5,r6
2405+ bealeqi r18,$LaRETURN_HERE
2406+
2407+# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
2408+ xorl r18,r5,r6
2409+ addlik r3,r5,0
2410+ bealgei r18,$LRSUB
2411+ beallti r6,$LaRETURN_HERE
2412+ breai $LCheckr6
2413+$LRSUB:
2414+ rsubl r18,r5,r6 # MICROBLAZEcmp
2415+ bealgti r18,$LaRETURN_HERE
2416+
2417+# If r6 [bit 31] is set, then return result as r5-r6
2418+$LCheckr6:
2419+ addlik r3,r0,0
2420+ bealgti r6,$LaDIV0
2421+ addlik r18,r0,0x7fffffff
2422+ andl r5,r5,r18
2423+ andl r6,r6,r18
2424+ breaid $LaRETURN_HERE
2425+ rsubl r3,r6,r5
2426+# First part: try to find the first '1' in the r5
2427+$LaDIV0:
2428+ BEALLTI r5,$LaDIV2
2429+$LaDIV1:
2430+ ADDL r5,r5,r5 # left shift logical r5
2431+ ADDLIK r29,r29,-1
2432+ BEALGEI r5,$LaDIV1 #
2433+$LaDIV2:
2434+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry
2435+ ADDLC r3,r3,r3 # Move that bit into the Mod register
2436+ rSUBL r31,r6,r3 # Try to subtract (r3 a r6)
2437+ BEALLTi r31,$LaMOD_TOO_SMALL
2438+ ORL r3,r0,r31 # Move the r31 to mod since the result was positive
2439+ ADDLIK r30,r30,1
2440+$LaMOD_TOO_SMALL:
2441+ ADDLIK r29,r29,-1
2442+ BEALEQi r29,$LaLOOP_END
2443+ ADDL r30,r30,r30 # Shift in the '1' into div
2444+ BREAI $LaDIV2 # Div2
2445+$LaLOOP_END:
2446+ BREAI $LaRETURN_HERE
2447+$LaDiv_By_Zero:
2448+$LaResult_Is_Zero:
2449+ orl r3,r0,r0 # set result to 0
2450+$LaRETURN_HERE:
2451+# Restore values of CSRs and that of r3 and the divisor and the dividend
2452+ lli r29,r1,0
2453+ lli r30,r1,8
2454+ lli r31,r1,16
2455+ addlik r1,r1,24
2456+ rtsd r15,8
2457+ nop
2458+.end __umoddi3
2459+ .size __umoddi3, . - __umoddi3
2460+#endif
2461--
24622.7.4
2463
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0042-re-arrangement-of-the-compare-branches.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0042-re-arrangement-of-the-compare-branches.patch
new file mode 100644
index 00000000..3afb7629
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0042-re-arrangement-of-the-compare-branches.patch
@@ -0,0 +1,268 @@
1From 31062878a2c1773a1fc94242ad29e6d03e4828b1 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Fri, 3 Aug 2018 15:41:39 +0530
4Subject: [PATCH 42/63] re-arrangement of the compare branches
5
6---
7 gcc/config/microblaze/microblaze.c | 28 ++-----
8 gcc/config/microblaze/microblaze.md | 141 +++++++++++++++++-------------------
9 2 files changed, 73 insertions(+), 96 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
12index d5ff7af..dd46d93 100644
13--- a/gcc/config/microblaze/microblaze.c
14+++ b/gcc/config/microblaze/microblaze.c
15@@ -3835,11 +3835,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
16 {
17 comp_reg = cmp_op0;
18 condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
19- if (mode == Pmode)
20- emit_jump_insn (gen_condjump (condition, label1));
21- else
22- emit_jump_insn (gen_long_condjump (condition, label1));
23-
24+ emit_jump_insn (gen_condjump (condition, label1));
25 }
26
27 else if (code == EQ || code == NE)
28@@ -3850,10 +3846,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
29 else
30 emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
31 condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
32- if (mode == SImode)
33- emit_jump_insn (gen_condjump (condition, label1));
34- else
35- emit_jump_insn (gen_long_condjump (condition, label1));
36+ emit_jump_insn (gen_condjump (condition, label1));
37 }
38 else
39 {
40@@ -3886,10 +3879,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
41 comp_reg = cmp_op0;
42 condition = gen_rtx_fmt_ee (signed_condition (code),
43 mode, comp_reg, const0_rtx);
44- if (mode == SImode)
45- emit_jump_insn (gen_condjump (condition, label1));
46- else
47- emit_jump_insn (gen_long_condjump (condition, label1));
48+ emit_jump_insn (gen_condjump (condition, label1));
49 }
50 else if (code == EQ)
51 {
52@@ -3904,10 +3894,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
53 cmp_op1));
54 }
55 condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
56- if (mode == SImode)
57- emit_jump_insn (gen_condjump (condition, label1));
58- else
59- emit_jump_insn (gen_long_condjump (condition, label1));
60+ emit_jump_insn (gen_condjump (condition, label1));
61
62 }
63 else if (code == NE)
64@@ -3923,10 +3910,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
65 cmp_op1));
66 }
67 condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
68- if (mode == SImode)
69- emit_jump_insn (gen_condjump (condition, label1));
70- else
71- emit_jump_insn (gen_long_condjump (condition, label1));
72+ emit_jump_insn (gen_condjump (condition, label1));
73 }
74 else
75 {
76@@ -3968,7 +3952,7 @@ microblaze_expand_conditional_branch_df (rtx operands[])
77
78 emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
79 condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
80- emit_jump_insn (gen_long_condjump (condition, operands[3]));
81+ emit_jump_insn (gen_condjump (condition, operands[3]));
82 }
83
84 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
85diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
86index 77627a7..edb7aab 100644
87--- a/gcc/config/microblaze/microblaze.md
88+++ b/gcc/config/microblaze/microblaze.md
89@@ -2270,7 +2270,27 @@ else
90 (label_ref (match_operand 1))
91 (pc)))])
92
93-(define_insn "branch_zero64"
94+(define_insn "branch_zero_64"
95+ [(set (pc)
96+ (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
97+ [(match_operand:SI 1 "register_operand" "d")
98+ (const_int 0)])
99+ (match_operand:SI 2 "pc_or_label_operand" "")
100+ (match_operand:SI 3 "pc_or_label_operand" "")))
101+ ]
102+ "TARGET_MB_64"
103+ {
104+ if (operands[3] == pc_rtx)
105+ return "bea%C0i%?\t%z1,%2";
106+ else
107+ return "bea%N0i%?\t%z1,%3";
108+ }
109+ [(set_attr "type" "branch")
110+ (set_attr "mode" "none")
111+ (set_attr "length" "4")]
112+)
113+
114+(define_insn "long_branch_zero"
115 [(set (pc)
116 (if_then_else (match_operator 0 "ordered_comparison_operator"
117 [(match_operand 1 "register_operand" "d")
118@@ -2281,9 +2301,9 @@ else
119 "TARGET_MB_64"
120 {
121 if (operands[3] == pc_rtx)
122- return "bea%C0i%?\t%z1,%2";
123+ return "beal%C0i%?\t%z1,%2";
124 else
125- return "bea%N0i%?\t%z1,%3";
126+ return "beal%N0i%?\t%z1,%3";
127 }
128 [(set_attr "type" "branch")
129 (set_attr "mode" "none")
130@@ -2312,9 +2332,9 @@ else
131
132 (define_insn "branch_compare64"
133 [(set (pc)
134- (if_then_else (match_operator 0 "cmp_op"
135- [(match_operand 1 "register_operand" "d")
136- (match_operand 2 "register_operand" "d")
137+ (if_then_else (match_operator:SI 0 "cmp_op"
138+ [(match_operand:SI 1 "register_operand" "d")
139+ (match_operand:SI 2 "register_operand" "d")
140 ])
141 (label_ref (match_operand 3))
142 (pc)))
143@@ -2351,6 +2371,47 @@ else
144 (set_attr "length" "12")]
145 )
146
147+(define_insn "long_branch_compare"
148+ [(set (pc)
149+ (if_then_else (match_operator 0 "cmp_op"
150+ [(match_operand 1 "register_operand" "d")
151+ (match_operand 2 "register_operand" "d")
152+ ])
153+ (label_ref (match_operand 3))
154+ (pc)))
155+ (clobber(reg:DI R_TMP))]
156+ "TARGET_MB_64"
157+ {
158+ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
159+ enum rtx_code code = GET_CODE (operands[0]);
160+
161+ if (code == GT || code == LE)
162+ {
163+ output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
164+ code = swap_condition (code);
165+ }
166+ else if (code == GTU || code == LEU)
167+ {
168+ output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
169+ code = swap_condition (code);
170+ }
171+ else if (code == GE || code == LT)
172+ {
173+ output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
174+ }
175+ else if (code == GEU || code == LTU)
176+ {
177+ output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
178+ }
179+
180+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
181+ return "beal%C0i%?\tr18,%3";
182+ }
183+ [(set_attr "type" "branch")
184+ (set_attr "mode" "none")
185+ (set_attr "length" "12")]
186+)
187+
188 (define_insn "branch_compare"
189 [(set (pc)
190 (if_then_else (match_operator:SI 0 "cmp_op"
191@@ -2433,74 +2494,6 @@ else
192
193 })
194
195-;; Used to implement comparison instructions
196-(define_expand "long_condjump"
197- [(set (pc)
198- (if_then_else (match_operand 0)
199- (label_ref (match_operand 1))
200- (pc)))])
201-
202-(define_insn "long_branch_zero"
203- [(set (pc)
204- (if_then_else (match_operator:DI 0 "ordered_comparison_operator"
205- [(match_operand:DI 1 "register_operand" "d")
206- (const_int 0)])
207- (match_operand:DI 2 "pc_or_label_operand" "")
208- (match_operand:DI 3 "pc_or_label_operand" "")))
209- ]
210- "TARGET_MB_64"
211- {
212- if (operands[3] == pc_rtx)
213- return "beal%C0i%?\t%z1,%2";
214- else
215- return "beal%N0i%?\t%z1,%3";
216- }
217- [(set_attr "type" "branch")
218- (set_attr "mode" "none")
219- (set_attr "length" "4")]
220-)
221-
222-(define_insn "long_branch_compare"
223- [(set (pc)
224- (if_then_else (match_operator:DI 0 "cmp_op"
225- [(match_operand:DI 1 "register_operand" "d")
226- (match_operand:DI 2 "register_operand" "d")
227- ])
228- (label_ref (match_operand 3))
229- (pc)))
230- (clobber(reg:DI R_TMP))]
231- "TARGET_MB_64"
232- {
233- operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
234- enum rtx_code code = GET_CODE (operands[0]);
235-
236- if (code == GT || code == LE)
237- {
238- output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
239- code = swap_condition (code);
240- }
241- else if (code == GTU || code == LEU)
242- {
243- output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
244- code = swap_condition (code);
245- }
246- else if (code == GE || code == LT)
247- {
248- output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
249- }
250- else if (code == GEU || code == LTU)
251- {
252- output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
253- }
254-
255- operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
256- return "beal%C0i%?\tr18,%3";
257- }
258- [(set_attr "type" "branch")
259- (set_attr "mode" "none")
260- (set_attr "length" "12")]
261-)
262-
263 ;;----------------------------------------------------------------
264 ;; Unconditional branches
265 ;;----------------------------------------------------------------
266--
2672.7.4
268
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch
new file mode 100644
index 00000000..f4074899
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch
@@ -0,0 +1,28 @@
1From 7ab47599c2bec80d622883b3e220827dce89c598 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 8 Aug 2018 17:37:26 +0530
4Subject: [PATCH 43/63] [Patch,Microblaze] : previous commit broke the
5 handling of SI Branch compare for Microblaze 32-bit..
6
7---
8 gcc/config/microblaze/microblaze.md | 4 ++--
9 1 file changed, 2 insertions(+), 2 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
12index edb7aab..fb22edb 100644
13--- a/gcc/config/microblaze/microblaze.md
14+++ b/gcc/config/microblaze/microblaze.md
15@@ -2226,8 +2226,8 @@ else
16 (define_expand "cbranchsi4"
17 [(set (pc)
18 (if_then_else (match_operator 0 "ordered_comparison_operator"
19- [(match_operand 1 "register_operand")
20- (match_operand 2 "arith_operand" "I,i")])
21+ [(match_operand:SI 1 "register_operand")
22+ (match_operand:SI 2 "arith_operand" "I,i")])
23 (label_ref (match_operand 3 ""))
24 (pc)))]
25 ""
26--
272.7.4
28
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch
new file mode 100644
index 00000000..ad287e57
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch
@@ -0,0 +1,73 @@
1From 23622921a153258de469ff10db4926b83ff0c432 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 11 Sep 2018 13:43:48 +0530
4Subject: [PATCH 44/63] [Patch, Microblaze] : Support of multilibs with m64 ...
5
6---
7 gcc/config/microblaze/microblaze-c.c | 1 +
8 gcc/config/microblaze/t-microblaze | 15 ++++++---------
9 libgcc/config/microblaze/t-microblaze | 11 +++--------
10 3 files changed, 10 insertions(+), 17 deletions(-)
11
12diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
13index d2b0c76..6670091 100644
14--- a/gcc/config/microblaze/microblaze-c.c
15+++ b/gcc/config/microblaze/microblaze-c.c
16@@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile)
17 }
18 if (TARGET_MB_64)
19 {
20+ builtin_define ("__microblaze64");
21 builtin_define ("__arch64__");
22 builtin_define ("__microblaze64__");
23 builtin_define ("__MICROBLAZE64__");
24diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
25index 9fc80b1..35ab9654 100644
26--- a/gcc/config/microblaze/t-microblaze
27+++ b/gcc/config/microblaze/t-microblaze
28@@ -1,12 +1,9 @@
29-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
30-MULTILIB_DIRNAMES = bs m mh le m64
31-MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
32-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
33-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
34-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
35-MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
36-MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
37-MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
38+MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
39+MULTILIB_DIRNAMES = m64 bs le m mh
40+MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
41+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
42+MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
43+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
44
45 # Extra files
46 microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
47diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
48index 35021b2..8d954a4 100644
49--- a/libgcc/config/microblaze/t-microblaze
50+++ b/libgcc/config/microblaze/t-microblaze
51@@ -1,16 +1,11 @@
52-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \
53- _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3
54+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
55
56 LIB2ADD += \
57 $(srcdir)/config/microblaze/divsi3.S \
58- $(srcdir)/config/microblaze/divdi3.S \
59 $(srcdir)/config/microblaze/modsi3.S \
60- $(srcdir)/config/microblaze/moddi3.S \
61+ $(srcdir)/config/microblaze/muldi3_hard.S \
62 $(srcdir)/config/microblaze/mulsi3.S \
63- $(srcdir)/config/microblaze/muldi3.S \
64 $(srcdir)/config/microblaze/stack_overflow_exit.S \
65 $(srcdir)/config/microblaze/udivsi3.S \
66- $(srcdir)/config/microblaze/udivdi3.S \
67 $(srcdir)/config/microblaze/umodsi3.S \
68- $(srcdir)/config/microblaze/umoddi3.S \
69- $(srcdir)/config/microblaze/divsi3_table.c \
70+ $(srcdir)/config/microblaze/divsi3_table.c
71--
722.7.4
73
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0045-Fixed-issues-like.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0045-Fixed-issues-like.patch
new file mode 100644
index 00000000..3f5f7827
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0045-Fixed-issues-like.patch
@@ -0,0 +1,70 @@
1From 6e6fcbe5fafcbebaf63ff071ad947966af0c1559 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Tue, 11 Sep 2018 14:58:00 +0530
4Subject: [PATCH 45/63] Fixed issues like: 1 Interrupt alignment issue 2 Sign
5 extension issue
6
7---
8 gcc/config/microblaze/microblaze.c | 16 ++++++++++------
9 gcc/config/microblaze/microblaze.md | 2 +-
10 2 files changed, 11 insertions(+), 7 deletions(-)
11
12diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
13index dd46d93..bfa667b 100644
14--- a/gcc/config/microblaze/microblaze.c
15+++ b/gcc/config/microblaze/microblaze.c
16@@ -2317,9 +2317,14 @@ compute_frame_size (HOST_WIDE_INT size)
17
18 total_size += gp_reg_size;
19
20- /* Add 4 bytes for MSR. */
21+ /* Add 4/8 bytes for MSR. */
22 if (microblaze_is_interrupt_variant ())
23- total_size += 4;
24+ {
25+ if (TARGET_MB_64)
26+ total_size += 8;
27+ else
28+ total_size += 4;
29+ }
30
31 /* No space to be allocated for link register in leaf functions with no other
32 stack requirements. */
33@@ -2604,7 +2609,6 @@ print_operand (FILE * file, rtx op, int letter)
34 else if (letter == 'h' || letter == 'j')
35 {
36 long val[2];
37- int val1[2];
38 long l[2];
39 if (code == CONST_DOUBLE)
40 {
41@@ -2619,10 +2623,10 @@ print_operand (FILE * file, rtx op, int letter)
42 }
43 else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
44 {
45- val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
46- val1[1] = INTVAL (op) & 0x00000000ffffffffLL;
47+ val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
48+ val[1] = INTVAL (op) & 0x00000000ffffffffLL;
49 }
50- fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]);
51+ fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
52 }
53 else if (code == CONST_DOUBLE)
54 {
55diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
56index fb22edb..4a8fbab 100644
57--- a/gcc/config/microblaze/microblaze.md
58+++ b/gcc/config/microblaze/microblaze.md
59@@ -1096,7 +1096,7 @@
60 case 1:
61 case 2:
62 {
63- output_asm_insn ("ll%i1\t%0,%1", operands);
64+ output_asm_insn ("lw%i1\t%0,%1", operands);
65 return "sextl32\t%0,%0";
66 }
67 }
68--
692.7.4
70
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0046-Fixed-below-issues.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0046-Fixed-below-issues.patch
new file mode 100644
index 00000000..fc2fe3b5
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0046-Fixed-below-issues.patch
@@ -0,0 +1,307 @@
1From 7c911a5ae8cf4a7496c059374f170f1919c00f6d Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 26 Nov 2019 17:26:15 +0530
4Subject: [PATCH 46/63] Fixed below issues:
5
6- Floating point print issues in 64bit mode
7- Dejagnu Jump related issues
8- Added dbl instruction
9
10Conflicts:
11 gcc/config/microblaze/microblaze.md
12---
13 gcc/config/microblaze/microblaze.c | 12 +++++-
14 gcc/config/microblaze/microblaze.h | 7 +++
15 gcc/config/microblaze/microblaze.md | 86 +++++++++++++++++++++++++++++++------
16 libgcc/config/microblaze/crti.S | 24 ++++++++++-
17 libgcc/config/microblaze/crtn.S | 13 ++++++
18 5 files changed, 125 insertions(+), 17 deletions(-)
19
20diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
21index bfa667b..220e03d 100644
22--- a/gcc/config/microblaze/microblaze.c
23+++ b/gcc/config/microblaze/microblaze.c
24@@ -2613,7 +2613,12 @@ print_operand (FILE * file, rtx op, int letter)
25 if (code == CONST_DOUBLE)
26 {
27 if (GET_MODE (op) == DFmode)
28- REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
29+ {
30+ if (TARGET_MB_64)
31+ REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
32+ else
33+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
34+ }
35 else
36 {
37 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
38@@ -4014,7 +4019,10 @@ microblaze_expand_divide (rtx operands[])
39 gen_rtx_PLUS (QImode, regt1, div_table_rtx));
40
41 insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
42- jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
43+ if (TARGET_MB_64)
44+ jump = emit_jump_insn_after (gen_jump_64 (div_end_label), insn);
45+ else
46+ jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
47 JUMP_LABEL (jump) = div_end_label;
48 LABEL_NUSES (div_end_label) = 1;
49 emit_barrier ();
50diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
51index a23fd4e..7497cfb 100644
52--- a/gcc/config/microblaze/microblaze.h
53+++ b/gcc/config/microblaze/microblaze.h
54@@ -888,10 +888,17 @@ do { \
55 /* We do this to save a few 10s of code space that would be taken up
56 by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
57 definition in crtstuff.c. */
58+#ifdef __arch64__
59+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
60+ asm ( SECTION_OP "\n" \
61+ "\tbrealid r15, " #FUNC "\n\t nop\n" \
62+ TEXT_SECTION_ASM_OP);
63+#else
64 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
65 asm ( SECTION_OP "\n" \
66 "\tbrlid r15, " #FUNC "\n\t nop\n" \
67 TEXT_SECTION_ASM_OP);
68+#endif
69
70 /* We need to group -lm as well, since some Newlib math functions
71 reference __errno! */
72diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
73index 4a8fbab..65ec32c 100644
74--- a/gcc/config/microblaze/microblaze.md
75+++ b/gcc/config/microblaze/microblaze.md
76@@ -527,6 +527,15 @@
77 (set_attr "mode" "SF")
78 (set_attr "length" "4")])
79
80+(define_insn "floatdidf2"
81+ [(set (match_operand:DF 0 "register_operand" "=d")
82+ (float:DF (match_operand:DI 1 "register_operand" "d")))]
83+ "TARGET_MB_64"
84+ "dbl\t%0,%1"
85+ [(set_attr "type" "fcvt")
86+ (set_attr "mode" "DF")
87+ (set_attr "length" "4")])
88+
89 (define_insn "fix_truncsfsi2"
90 [(set (match_operand:SI 0 "register_operand" "=d")
91 (fix:SI (match_operand:SF 1 "register_operand" "d")))]
92@@ -1300,7 +1309,7 @@
93 (define_insn "movdi_long_int"
94 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
95 (match_operand:DI 1 "general_operand" "i"))]
96- ""
97+ "TARGET_MB_64"
98 "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
99 [(set_attr "type" "no_delay_arith")
100 (set_attr "mode" "DI")
101@@ -1583,7 +1592,7 @@
102 return "ll%i1\t%0,%1";
103 case 3:
104 {
105- return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo";
106+ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
107 }
108 case 5:
109 return "sl%i0\t%1,%0";
110@@ -2373,9 +2382,9 @@ else
111
112 (define_insn "long_branch_compare"
113 [(set (pc)
114- (if_then_else (match_operator 0 "cmp_op"
115- [(match_operand 1 "register_operand" "d")
116- (match_operand 2 "register_operand" "d")
117+ (if_then_else (match_operator:DI 0 "cmp_op"
118+ [(match_operand:DI 1 "register_operand" "d")
119+ (match_operand:DI 2 "register_operand" "d")
120 ])
121 (label_ref (match_operand 3))
122 (pc)))
123@@ -2497,6 +2506,20 @@ else
124 ;;----------------------------------------------------------------
125 ;; Unconditional branches
126 ;;----------------------------------------------------------------
127+(define_insn "jump_64"
128+ [(set (pc)
129+ (label_ref (match_operand 0 "" "")))]
130+ "TARGET_MB_64"
131+ {
132+ if (GET_CODE (operands[0]) == REG)
133+ return "brea%?\t%0";
134+ else
135+ return "breai%?\t%l0";
136+ }
137+ [(set_attr "type" "jump")
138+ (set_attr "mode" "none")
139+ (set_attr "length" "4")])
140+
141 (define_insn "jump"
142 [(set (pc)
143 (label_ref (match_operand 0 "" "")))]
144@@ -2542,17 +2565,25 @@ else
145 {
146 //gcc_assert (GET_MODE (operands[0]) == Pmode);
147
148- if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
149- emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
150- else
151- emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
152+ if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) {
153+ if (!TARGET_MB_64)
154+ emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
155+ else
156+ emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
157+ }
158+ else {
159+ if (!TARGET_MB_64)
160+ emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
161+ else
162+ emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
163+ }
164 DONE;
165 }
166 )
167
168 (define_insn "tablejump_internal1"
169 [(set (pc)
170- (match_operand 0 "register_operand" "d"))
171+ (match_operand:SI 0 "register_operand" "d"))
172 (use (label_ref (match_operand 1 "" "")))]
173 ""
174 "bra%?\t%0 "
175@@ -2560,11 +2591,21 @@ else
176 (set_attr "mode" "none")
177 (set_attr "length" "4")])
178
179+(define_insn "tablejump_internal2"
180+ [(set (pc)
181+ (match_operand:DI 0 "register_operand" "d"))
182+ (use (label_ref (match_operand 1 "" "")))]
183+ "TARGET_MB_64"
184+ "bra%?\t%0 "
185+ [(set_attr "type" "jump")
186+ (set_attr "mode" "none")
187+ (set_attr "length" "4")])
188+
189 (define_expand "tablejump_internal3"
190 [(parallel [(set (pc)
191- (plus (match_operand 0 "register_operand" "d")
192- (label_ref (match_operand:SI 1 "" ""))))
193- (use (label_ref (match_dup 1)))])]
194+ (plus:SI (match_operand:SI 0 "register_operand" "d")
195+ (label_ref:SI (match_operand:SI 1 "" ""))))
196+ (use (label_ref:SI (match_dup 1)))])]
197 ""
198 ""
199 )
200@@ -2595,6 +2636,23 @@ else
201 ""
202 )
203
204+(define_insn ""
205+ [(set (pc)
206+ (plus:DI (match_operand:DI 0 "register_operand" "d")
207+ (label_ref:DI (match_operand 1 "" ""))))
208+ (use (label_ref:DI (match_dup 1)))]
209+ "TARGET_MB_64 && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0
210+ && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC
211+ && flag_pic"
212+ {
213+ output_asm_insn ("addlk\t%0,%0,r20",operands);
214+ return "bra%?\t%0";
215+}
216+ [(set_attr "type" "jump")
217+ (set_attr "mode" "none")
218+ (set_attr "length" "4")])
219+
220+
221 ;;----------------------------------------------------------------
222 ;; Function prologue/epilogue and stack allocation
223 ;;----------------------------------------------------------------
224@@ -3101,7 +3159,7 @@ else
225 ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference
226 ;; between "mfs" and "addik" instructions.
227 (define_insn "set_got"
228- [(set (match_operand:SI 0 "register_operand" "=r")
229+ [(set (match_operand 0 "register_operand" "=r")
230 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))]
231 ""
232 "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8"
233diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
234index 1811327..a661319 100644
235--- a/libgcc/config/microblaze/crti.S
236+++ b/libgcc/config/microblaze/crti.S
237@@ -33,11 +33,32 @@
238 .section .init, "ax"
239 .global __init
240
241+#ifdef __arch64__
242 .weak _stack
243- .set _stack, 0xffffffff
244+ .set _stack, 0xffffffffffffffff
245 .weak _stack_end
246 .set _stack_end, 0
247
248+ .align 3
249+__init:
250+ addlik r1, r1, -32
251+ sl r15, r0, r1
252+ addlik r11, r0, _stack
253+ mts rshr, r11
254+ addlik r11, r0, _stack_end
255+ mts rslr, r11
256+
257+ .section .fini, "ax"
258+ .global __fini
259+ .align 3
260+__fini:
261+ addlik r1, r1, -32
262+ sl r15, r0, r1
263+#else
264+ .weak _stack
265+ .set _stack, 0xffffffff
266+ .weak _stack_end
267+ .set _stack_end, 0
268 .align 2
269 __init:
270 addik r1, r1, -16
271@@ -53,3 +74,4 @@ __init:
272 __fini:
273 addik r1, r1, -16
274 sw r15, r0, r1
275+#endif
276diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
277index 60a4648..d72507b 100644
278--- a/libgcc/config/microblaze/crtn.S
279+++ b/libgcc/config/microblaze/crtn.S
280@@ -29,7 +29,19 @@
281 .section .note.GNU-stack,"",%progbits
282 .previous
283 #endif
284+#ifdef __arch64__
285+ .section .init, "ax"
286+ ll r15, r0, r1
287+ addlik r1, r1, 32
288+ rtsd r15, 8
289+ nop
290
291+ .section .fini, "ax"
292+ ll r15, r0, r1
293+ addlik r1, r1, 32
294+ rtsd r15, 8
295+ nop
296+#else
297 .section .init, "ax"
298 lw r15, r0, r1
299 rtsd r15, 8
300@@ -39,3 +51,4 @@
301 lw r15, r0, r1
302 rtsd r15, 8
303 addik r1, r1, 16
304+#endif
305--
3062.7.4
307
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0047-Added-double-arith-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0047-Added-double-arith-instructions.patch
new file mode 100644
index 00000000..1b7ac28b
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0047-Added-double-arith-instructions.patch
@@ -0,0 +1,135 @@
1From 0f310964ff1c19cbc3404ec7ceba286d6de315c0 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Tue, 9 Oct 2018 10:07:08 +0530
4Subject: [PATCH 47/63] -Added double arith instructions -Fixed prologue stack
5 pointer decrement issue
6
7---
8 gcc/config/microblaze/microblaze.md | 78 ++++++++++++++++++++++++++++++++-----
9 gcc/config/microblaze/t-microblaze | 7 ++++
10 2 files changed, 76 insertions(+), 9 deletions(-)
11
12diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
13index 65ec32c..c199b27 100644
14--- a/gcc/config/microblaze/microblaze.md
15+++ b/gcc/config/microblaze/microblaze.md
16@@ -527,6 +527,66 @@
17 (set_attr "mode" "SF")
18 (set_attr "length" "4")])
19
20+(define_insn "fix_truncsfsi2"
21+ [(set (match_operand:SI 0 "register_operand" "=d")
22+ (fix:SI (match_operand:SF 1 "register_operand" "d")))]
23+ "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
24+ "fint\t%0,%1"
25+ [(set_attr "type" "fint")
26+ (set_attr "mode" "SF")
27+ (set_attr "length" "4")])
28+
29+
30+(define_insn "adddf3"
31+ [(set (match_operand:DF 0 "register_operand" "=d")
32+ (plus:DF (match_operand:DF 1 "register_operand" "d")
33+ (match_operand:DF 2 "register_operand" "d")))]
34+ "TARGET_MB_64"
35+ "dadd\t%0,%1,%2"
36+ [(set_attr "type" "fadd")
37+ (set_attr "mode" "DF")
38+ (set_attr "length" "4")])
39+
40+(define_insn "subdf3"
41+ [(set (match_operand:DF 0 "register_operand" "=d")
42+ (minus:DF (match_operand:DF 1 "register_operand" "d")
43+ (match_operand:DF 2 "register_operand" "d")))]
44+ "TARGET_MB_64"
45+ "drsub\t%0,%2,%1"
46+ [(set_attr "type" "frsub")
47+ (set_attr "mode" "DF")
48+ (set_attr "length" "4")])
49+
50+(define_insn "muldf3"
51+ [(set (match_operand:DF 0 "register_operand" "=d")
52+ (mult:DF (match_operand:DF 1 "register_operand" "d")
53+ (match_operand:DF 2 "register_operand" "d")))]
54+ "TARGET_MB_64"
55+ "dmul\t%0,%1,%2"
56+ [(set_attr "type" "fmul")
57+ (set_attr "mode" "DF")
58+ (set_attr "length" "4")])
59+
60+(define_insn "divdf3"
61+ [(set (match_operand:DF 0 "register_operand" "=d")
62+ (div:DF (match_operand:DF 1 "register_operand" "d")
63+ (match_operand:DF 2 "register_operand" "d")))]
64+ "TARGET_MB_64"
65+ "ddiv\t%0,%2,%1"
66+ [(set_attr "type" "fdiv")
67+ (set_attr "mode" "DF")
68+ (set_attr "length" "4")])
69+
70+
71+(define_insn "sqrtdf2"
72+ [(set (match_operand:DF 0 "register_operand" "=d")
73+ (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
74+ "TARGET_MB_64"
75+ "dsqrt\t%0,%1"
76+ [(set_attr "type" "fsqrt")
77+ (set_attr "mode" "DF")
78+ (set_attr "length" "4")])
79+
80 (define_insn "floatdidf2"
81 [(set (match_operand:DF 0 "register_operand" "=d")
82 (float:DF (match_operand:DI 1 "register_operand" "d")))]
83@@ -536,13 +596,13 @@
84 (set_attr "mode" "DF")
85 (set_attr "length" "4")])
86
87-(define_insn "fix_truncsfsi2"
88- [(set (match_operand:SI 0 "register_operand" "=d")
89- (fix:SI (match_operand:SF 1 "register_operand" "d")))]
90- "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
91- "fint\t%0,%1"
92- [(set_attr "type" "fint")
93- (set_attr "mode" "SF")
94+(define_insn "floatdfdi2"
95+ [(set (match_operand:DI 0 "register_operand" "=d")
96+ (float:DI (match_operand:DF 1 "register_operand" "d")))]
97+ "TARGET_MB_64"
98+ "dlong\t%0,%1"
99+ [(set_attr "type" "fcvt")
100+ (set_attr "mode" "DI")
101 (set_attr "length" "4")])
102
103 ;;----------------------------------------------------------------
104@@ -660,8 +720,8 @@
105 "TARGET_MB_64"
106 "@
107 rsubl\t%0,%2,%1
108- addik\t%0,%z1,-%2
109- addik\t%0,%z1,-%2"
110+ addlik\t%0,%z1,-%2
111+ addlik\t%0,%z1,-%2"
112 [(set_attr "type" "arith,no_delay_arith,no_delay_arith")
113 (set_attr "mode" "DI")
114 (set_attr "length" "4,4,4")])
115diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
116index 35ab9654..dfef45c 100644
117--- a/gcc/config/microblaze/t-microblaze
118+++ b/gcc/config/microblaze/t-microblaze
119@@ -1,6 +1,13 @@
120 MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
121 MULTILIB_DIRNAMES = m64 bs le m mh
122 MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
123+MULTILIB_EXCEPTIONS += *m64
124+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift
125+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
126+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul
127+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
128+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high
129+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high
130 MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
131 MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
132 MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
133--
1342.7.4
135
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
new file mode 100644
index 00000000..c00b0a2b
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
@@ -0,0 +1,37 @@
1From b63cd2a410b9350fa67ed3ca348dcca349da4e44 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Fri, 12 Oct 2018 16:07:36 +0530
4Subject: [PATCH 48/63] Fixed the issue in the delay slot with swap
5 instructions
6
7---
8 gcc/config/microblaze/microblaze.md | 6 ++++++
9 1 file changed, 6 insertions(+)
10
11diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
12index c199b27..d6370d8 100644
13--- a/gcc/config/microblaze/microblaze.md
14+++ b/gcc/config/microblaze/microblaze.md
15@@ -443,6 +443,9 @@
16 (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
17 "TARGET_REORDER"
18 "swapb %0, %1"
19+ [(set_attr "type" "no_delay_arith")
20+ (set_attr "mode" "SI")
21+ (set_attr "length" "4")]
22 )
23
24 (define_insn "bswaphi2"
25@@ -451,6 +454,9 @@
26 "TARGET_REORDER"
27 "swapb %0, %1
28 swaph %0, %0"
29+ [(set_attr "type" "no_delay_arith")
30+ (set_attr "mode" "SI")
31+ (set_attr "length" "8")]
32 )
33
34 ;;----------------------------------------------------------------
35--
362.7.4
37
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
new file mode 100644
index 00000000..7e92df2e
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
@@ -0,0 +1,256 @@
1From f39f36cb0f0466343ef4ead50261b58595af708c Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Sat, 13 Oct 2018 21:12:43 +0530
4Subject: [PATCH 49/63] Fixed the load store issue with the 32bit arith
5 libraries
6
7---
8 libgcc/config/microblaze/divsi3.S | 25 ++++++++++++++++++++++++-
9 libgcc/config/microblaze/modsi3.S | 26 +++++++++++++++++++++++++-
10 libgcc/config/microblaze/mulsi3.S | 3 +++
11 libgcc/config/microblaze/udivsi3.S | 24 +++++++++++++++++++++++-
12 libgcc/config/microblaze/umodsi3.S | 24 +++++++++++++++++++++++-
13 5 files changed, 98 insertions(+), 4 deletions(-)
14
15diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
16index 24b94b9..2765e42 100644
17--- a/libgcc/config/microblaze/divsi3.S
18+++ b/libgcc/config/microblaze/divsi3.S
19@@ -41,6 +41,17 @@
20 .globl __divsi3
21 .ent __divsi3
22 .type __divsi3,@function
23+#ifdef __arch64__
24+ .align 3
25+__divsi3:
26+ .frame r1,0,r15
27+
28+ ADDIK r1,r1,-32
29+ SLI r28,r1,0
30+ SLI r29,r1,8
31+ SLI r30,r1,16
32+ SLI r31,r1,24
33+#else
34 __divsi3:
35 .frame r1,0,r15
36
37@@ -49,7 +60,7 @@ __divsi3:
38 SWI r29,r1,4
39 SWI r30,r1,8
40 SWI r31,r1,12
41-
42+#endif
43 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
44 BEQI r5,$LaResult_Is_Zero # Result is Zero
45 BGEID r5,$LaR5_Pos
46@@ -89,6 +100,17 @@ $LaLOOP_END:
47 $LaDiv_By_Zero:
48 $LaResult_Is_Zero:
49 OR r3,r0,r0 # set result to 0
50+#ifdef __arch64__
51+$LaRETURN_HERE:
52+# Restore values of CSRs and that of r3 and the divisor and the dividend
53+ LLI r28,r1,0
54+ LLI r29,r1,8
55+ LLI r30,r1,16
56+ LLI r31,r1,24
57+ ADDLIK r1,r1,32
58+ RTSD r15,8
59+ NOP
60+#else
61 $LaRETURN_HERE:
62 # Restore values of CSRs and that of r3 and the divisor and the dividend
63 LWI r28,r1,0
64@@ -97,6 +119,7 @@ $LaRETURN_HERE:
65 LWI r31,r1,12
66 RTSD r15,8
67 ADDIK r1,r1,16
68+#endif
69 .end __divsi3
70 .size __divsi3, . - __divsi3
71
72diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
73index 87372f5..7e61453 100644
74--- a/libgcc/config/microblaze/modsi3.S
75+++ b/libgcc/config/microblaze/modsi3.S
76@@ -41,6 +41,17 @@
77 .globl __modsi3
78 .ent __modsi3
79 .type __modsi3,@function
80+#ifdef __arch64__
81+ .align 3
82+__modsi3:
83+ .frame r1,0,r15
84+
85+ addlik r1,r1,-32
86+ sli r28,r1,0
87+ sli r29,r1,8
88+ sli r30,r1,16
89+ sli r31,r1,24
90+#else
91 __modsi3:
92 .frame r1,0,r15
93
94@@ -49,6 +60,7 @@ __modsi3:
95 swi r29,r1,4
96 swi r30,r1,8
97 swi r31,r1,12
98+#endif
99
100 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
101 BEQI r5,$LaResult_Is_Zero # Result is Zero
102@@ -88,6 +100,18 @@ $LaLOOP_END:
103 $LaDiv_By_Zero:
104 $LaResult_Is_Zero:
105 or r3,r0,r0 # set result to 0 [Both mod as well as div are 0]
106+
107+#ifdef __arch64__
108+$LaRETURN_HERE:
109+# Restore values of CSRs and that of r3 and the divisor and the dividend
110+ lli r28,r1,0
111+ lli r29,r1,8
112+ lli r30,r1,16
113+ lli r31,r1,24
114+ addik r1,r1,32
115+ rtsd r15,8
116+ nop
117+#else
118 $LaRETURN_HERE:
119 # Restore values of CSRs and that of r3 and the divisor and the dividend
120 lwi r28,r1,0
121@@ -95,7 +119,7 @@ $LaRETURN_HERE:
122 lwi r30,r1,8
123 lwi r31,r1,12
124 rtsd r15,8
125- addik r1,r1,16
126+#endif
127 .end __modsi3
128 .size __modsi3, . - __modsi3
129
130diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
131index 8c3f788..e28c69a 100644
132--- a/libgcc/config/microblaze/mulsi3.S
133+++ b/libgcc/config/microblaze/mulsi3.S
134@@ -41,6 +41,9 @@
135 .globl __mulsi3
136 .ent __mulsi3
137 .type __mulsi3,@function
138+#ifdef __arch64__
139+ .align 3
140+#endif
141 __mulsi3:
142 .frame r1,0,r15
143 add r3,r0,r0
144diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
145index 5d726ad..b1e44b6 100644
146--- a/libgcc/config/microblaze/udivsi3.S
147+++ b/libgcc/config/microblaze/udivsi3.S
148@@ -41,6 +41,16 @@
149 .globl __udivsi3
150 .ent __udivsi3
151 .type __udivsi3,@function
152+#ifdef __arch64__
153+ .align 3
154+__udivsi3:
155+ .frame r1,0,r15
156+
157+ ADDLIK r1,r1,-24
158+ SLI r29,r1,0
159+ SLI r30,r1,8
160+ SLI r31,r1,16
161+#else
162 __udivsi3:
163 .frame r1,0,r15
164
165@@ -48,7 +58,7 @@ __udivsi3:
166 SWI r29,r1,0
167 SWI r30,r1,4
168 SWI r31,r1,8
169-
170+#endif
171 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
172 BEQID r5,$LaResult_Is_Zero # Result is Zero
173 ADDIK r30,r0,0 # Clear mod
174@@ -98,6 +108,17 @@ $LaLOOP_END:
175 $LaDiv_By_Zero:
176 $LaResult_Is_Zero:
177 OR r3,r0,r0 # set result to 0
178+
179+#ifdef __arch64__
180+$LaRETURN_HERE:
181+ # Restore values of CSRs and that of r3 and the divisor and the dividend
182+ LLI r29,r1,0
183+ LLI r30,r1,8
184+ LLI r31,r1,16
185+ ADDIK r1,r1,24
186+ RTSD r15,8
187+ NOP
188+#else
189 $LaRETURN_HERE:
190 # Restore values of CSRs and that of r3 and the divisor and the dividend
191 LWI r29,r1,0
192@@ -105,5 +126,6 @@ $LaRETURN_HERE:
193 LWI r31,r1,8
194 RTSD r15,8
195 ADDIK r1,r1,12
196+#endif
197 .end __udivsi3
198 .size __udivsi3, . - __udivsi3
199diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
200index b29d7e1..8804b99 100644
201--- a/libgcc/config/microblaze/umodsi3.S
202+++ b/libgcc/config/microblaze/umodsi3.S
203@@ -41,6 +41,16 @@
204 .globl __umodsi3
205 .ent __umodsi3
206 .type __umodsi3,@function
207+#ifdef __arch64__
208+ .align 3
209+__umodsi3:
210+ .frame r1,0,r15
211+
212+ addik r1,r1,-24
213+ swi r29,r1,0
214+ swi r30,r1,8
215+ swi r31,r1,16
216+#else
217 __umodsi3:
218 .frame r1,0,r15
219
220@@ -48,7 +58,7 @@ __umodsi3:
221 swi r29,r1,0
222 swi r30,r1,4
223 swi r31,r1,8
224-
225+#endif
226 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
227 BEQId r5,$LaResult_Is_Zero # Result is Zero
228 ADDIK r3,r0,0 # Clear div
229@@ -101,6 +111,17 @@ $LaLOOP_END:
230 $LaDiv_By_Zero:
231 $LaResult_Is_Zero:
232 or r3,r0,r0 # set result to 0
233+
234+#ifdef __arch64__
235+$LaRETURN_HERE:
236+# Restore values of CSRs and that of r3 and the divisor and the dividend
237+ lli r29,r1,0
238+ lli r30,r1,8
239+ lli r31,r1,16
240+ addlik r1,r1,24
241+ rtsd r15,8
242+ nop
243+#else
244 $LaRETURN_HERE:
245 # Restore values of CSRs and that of r3 and the divisor and the dividend
246 lwi r29,r1,0
247@@ -108,5 +129,6 @@ $LaRETURN_HERE:
248 lwi r31,r1,8
249 rtsd r15,8
250 addik r1,r1,12
251+#endif
252 .end __umodsi3
253 .size __umodsi3, . - __umodsi3
254--
2552.7.4
256
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch
new file mode 100644
index 00000000..ba717327
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch
@@ -0,0 +1,25 @@
1From 51886f40b6bccea22277f8dcc971706d7c24bdd0 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Mon, 15 Oct 2018 12:00:10 +0530
4Subject: [PATCH 50/63] extending the Dwarf support to 64bit Microblaze
5
6---
7 gcc/config/microblaze/microblaze.h | 2 +-
8 1 file changed, 1 insertion(+), 1 deletion(-)
9
10diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
11index 7497cfb..bd5e216 100644
12--- a/gcc/config/microblaze/microblaze.h
13+++ b/gcc/config/microblaze/microblaze.h
14@@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe;
15 /* Use DWARF 2 debugging information by default. */
16 #define DWARF2_DEBUGGING_INFO 1
17 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
18-#define DWARF2_ADDR_SIZE 4
19+#define DWARF2_ADDR_SIZE (TARGET_MB_64 ? 8 : 4)
20
21 /* Target machine storage layout */
22
23--
242.7.4
25
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0051-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0051-fixing-the-typo-errors-in-umodsi3-file.patch
new file mode 100644
index 00000000..a0758b31
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0051-fixing-the-typo-errors-in-umodsi3-file.patch
@@ -0,0 +1,29 @@
1From a8978d71c8b5adfa59430443611bd785a4d54ef9 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Tue, 16 Oct 2018 07:55:46 +0530
4Subject: [PATCH 51/63] fixing the typo errors in umodsi3 file
5
6---
7 libgcc/config/microblaze/umodsi3.S | 6 +++---
8 1 file changed, 3 insertions(+), 3 deletions(-)
9
10diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
11index 8804b99..1b3070e 100644
12--- a/libgcc/config/microblaze/umodsi3.S
13+++ b/libgcc/config/microblaze/umodsi3.S
14@@ -47,9 +47,9 @@ __umodsi3:
15 .frame r1,0,r15
16
17 addik r1,r1,-24
18- swi r29,r1,0
19- swi r30,r1,8
20- swi r31,r1,16
21+ sli r29,r1,0
22+ sli r30,r1,8
23+ sli r31,r1,16
24 #else
25 __umodsi3:
26 .frame r1,0,r15
27--
282.7.4
29
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
new file mode 100644
index 00000000..d0b534bc
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
@@ -0,0 +1,68 @@
1From 328bd339c292b63d2068a132a245bdc037815d6b Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Wed, 17 Oct 2018 16:56:14 +0530
4Subject: [PATCH 52/63] fixing the 32bit LTO related issue9(1014024)
5
6---
7 gcc/config/microblaze/microblaze.h | 24 ++++++++++++++----------
8 1 file changed, 14 insertions(+), 10 deletions(-)
9
10diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
11index bd5e216..ab541f7 100644
12--- a/gcc/config/microblaze/microblaze.h
13+++ b/gcc/config/microblaze/microblaze.h
14@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe;
15 #define WORD_REGISTER_OPERATIONS 1
16
17 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
18-/*
19-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
20- if (GET_MODE_CLASS (MODE) == MODE_INT \
21- && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
22- (MODE) = TARGET_MB_64 ? DImode : SImode;
23-*/
24+
25+#ifndef __arch64__
26+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
27+ if (GET_MODE_CLASS (MODE) == MODE_INT \
28+ && GET_MODE_SIZE (MODE) < 4) \
29+ (MODE) = SImode;
30+#endif
31+
32 /* Standard register usage. */
33
34 /* On the MicroBlaze, we have 32 integer registers */
35@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info;
36
37 #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
38
39+#ifdef __aarch64__
40 #define LIBCALL_VALUE(MODE) \
41 gen_rtx_REG (MODE,GP_RETURN)
42-
43-/*#define LIBCALL_VALUE(MODE) \
44+#else
45+#define LIBCALL_VALUE(MODE) \
46 gen_rtx_REG ( \
47 ((GET_MODE_CLASS (MODE) != MODE_INT \
48 || GET_MODE_SIZE (MODE) >= 4) \
49 ? (MODE) \
50 : SImode), GP_RETURN)
51-*/
52+#endif
53+
54 /* 1 if N is a possible register number for a function value.
55 On the MicroBlaze, R2 R3 are the only register thus used.
56 Currently, R2 are only implemented here (C has no complex type) */
57@@ -518,7 +522,7 @@ typedef struct microblaze_args
58 /* 4 insns + 2 words of data. */
59 #define TRAMPOLINE_SIZE (6 * 4)
60
61-#define TRAMPOLINE_ALIGNMENT 64
62+#define TRAMPOLINE_ALIGNMENT (TARGET_MB_64 ? 64 : 32)
63
64 #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
65
66--
672.7.4
68
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
new file mode 100644
index 00000000..f8ac364c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
@@ -0,0 +1,25 @@
1From 3f65f0432d42f4d469fbb10828f1683cd30a5d84 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Fri, 19 Oct 2018 14:26:25 +0530
4Subject: [PATCH 53/63] Fixed the missing stack adjustment in prologue of
5 modsi3 function
6
7---
8 libgcc/config/microblaze/modsi3.S | 1 +
9 1 file changed, 1 insertion(+)
10
11diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
12index 7e61453..b0e6cad 100644
13--- a/libgcc/config/microblaze/modsi3.S
14+++ b/libgcc/config/microblaze/modsi3.S
15@@ -119,6 +119,7 @@ $LaRETURN_HERE:
16 lwi r30,r1,8
17 lwi r31,r1,12
18 rtsd r15,8
19+ addik r1,r1,16
20 #endif
21 .end __modsi3
22 .size __modsi3, . - __modsi3
23--
242.7.4
25
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
new file mode 100644
index 00000000..0e704506
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
@@ -0,0 +1,29 @@
1From 0dbb2b7bfe466c18d54aec680208fd1459619bc1 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 24 Oct 2018 18:31:04 +0530
4Subject: [PATCH 54/63] [Patch,Microblaze] : corrected SPN for dlong
5 instruction mapping.
6
7---
8 gcc/config/microblaze/microblaze.md | 4 ++--
9 1 file changed, 2 insertions(+), 2 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
12index d6370d8..6b6b7c6 100644
13--- a/gcc/config/microblaze/microblaze.md
14+++ b/gcc/config/microblaze/microblaze.md
15@@ -602,9 +602,9 @@
16 (set_attr "mode" "DF")
17 (set_attr "length" "4")])
18
19-(define_insn "floatdfdi2"
20+(define_insn "fix_truncdfdi2"
21 [(set (match_operand:DI 0 "register_operand" "=d")
22- (float:DI (match_operand:DF 1 "register_operand" "d")))]
23+ (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
24 "TARGET_MB_64"
25 "dlong\t%0,%1"
26 [(set_attr "type" "fcvt")
27--
282.7.4
29
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch
new file mode 100644
index 00000000..28554722
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -0,0 +1,59 @@
1From a56b23ae244eee1da6d6595d3a6477085d77271e Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Thu, 29 Nov 2018 17:55:08 +0530
4Subject: [PATCH 55/63] fixing the long & long long mingw toolchain issue
5
6---
7 gcc/config/microblaze/constraints.md | 2 +-
8 gcc/config/microblaze/microblaze.md | 8 ++++----
9 2 files changed, 5 insertions(+), 5 deletions(-)
10
11diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
12index 2fce91e..9a5aa6b 100644
13--- a/gcc/config/microblaze/constraints.md
14+++ b/gcc/config/microblaze/constraints.md
15@@ -55,7 +55,7 @@
16 (define_constraint "K"
17 "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)."
18 (and (match_code "const_int")
19- (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
20+ (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
21
22 ;; Define floating point constraints
23
24diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
25index 6b6b7c6..a1dc41f 100644
26--- a/gcc/config/microblaze/microblaze.md
27+++ b/gcc/config/microblaze/microblaze.md
28@@ -648,8 +648,8 @@
29 if (TARGET_MB_64)
30 {
31 if (GET_CODE (operands[2]) == CONST_INT &&
32- INTVAL(operands[2]) < (long)-549755813888 &&
33- INTVAL(operands[2]) > (long)549755813887)
34+ INTVAL(operands[2]) < (long long)-549755813888 &&
35+ INTVAL(operands[2]) > (long long)549755813887)
36 FAIL;
37 }
38 })
39@@ -1266,7 +1266,7 @@
40 (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
41 "TARGET_MB_64 && (register_operand (operands[0], DImode) &&
42 (GET_CODE (operands[1]) == CONST_INT &&
43- (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))"
44+ (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))"
45 "@
46 addlk\t%0,r0,r0\t
47 addlik\t%0,r0,%1\t #N1 %X1
48@@ -1300,7 +1300,7 @@
49 case 1:
50 case 2:
51 if (GET_CODE (operands[1]) == CONST_INT &&
52- (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888))
53+ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
54 return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
55 else
56 return "addlik\t%0,r0,%1";
57--
582.7.4
59
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0055-microblaze_linker_script_xilinx_ld.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0055-microblaze_linker_script_xilinx_ld.patch
new file mode 100644
index 00000000..c009c92d
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0055-microblaze_linker_script_xilinx_ld.patch
@@ -0,0 +1,16 @@
1diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
2index 740b8d9..4bda9c2 100644
3--- a/gcc/config/microblaze/microblaze.h
4+++ b/gcc/config/microblaze/microblaze.h
5@@ -114,8 +114,9 @@ extern enum pipeline_type microblaze_pipe;
6 %{m64:-EL --oformat=elf64-microblazeel} \
7 %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
8 %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
9- %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
10- %{!T*: -dT xilinx.ld%s}"
11+ %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0}"
12+
13+// %{!T*: -dT xilinx.ld%s}"
14
15 /* Specs for the compiler proper */
16
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch
new file mode 100644
index 00000000..a419216c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch
@@ -0,0 +1,47 @@
1From e13b1b70972511a642512cbc7093ed21e5a9e141 Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Thu, 14 Mar 2019 18:11:04 +0530
4Subject: [PATCH 56/63] Fix the MB-64 bug of handling QI objects
5
6---
7 gcc/config/microblaze/microblaze.md | 14 +++++++-------
8 1 file changed, 7 insertions(+), 7 deletions(-)
9
10diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
11index a1dc41f..bb96e2d 100644
12--- a/gcc/config/microblaze/microblaze.md
13+++ b/gcc/config/microblaze/microblaze.md
14@@ -2347,11 +2347,11 @@ else
15
16 (define_insn "branch_zero_64"
17 [(set (pc)
18- (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
19+ (if_then_else (match_operator 0 "ordered_comparison_operator"
20 [(match_operand:SI 1 "register_operand" "d")
21 (const_int 0)])
22- (match_operand:SI 2 "pc_or_label_operand" "")
23- (match_operand:SI 3 "pc_or_label_operand" "")))
24+ (match_operand 2 "pc_or_label_operand" "")
25+ (match_operand 3 "pc_or_label_operand" "")))
26 ]
27 "TARGET_MB_64"
28 {
29@@ -2367,11 +2367,11 @@ else
30
31 (define_insn "long_branch_zero"
32 [(set (pc)
33- (if_then_else (match_operator 0 "ordered_comparison_operator"
34- [(match_operand 1 "register_operand" "d")
35+ (if_then_else (match_operator:DI 0 "ordered_comparison_operator"
36+ [(match_operand:DI 1 "register_operand" "d")
37 (const_int 0)])
38- (match_operand 2 "pc_or_label_operand" "")
39- (match_operand 3 "pc_or_label_operand" "")))
40+ (match_operand:DI 2 "pc_or_label_operand" "")
41+ (match_operand:DI 3 "pc_or_label_operand" "")))
42 ]
43 "TARGET_MB_64"
44 {
45--
462.7.4
47
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-fix-the-lto-wrapper-issue-on-windows.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-fix-the-lto-wrapper-issue-on-windows.patch
new file mode 100644
index 00000000..ff524770
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0056-fix-the-lto-wrapper-issue-on-windows.patch
@@ -0,0 +1,36 @@
1From f30b99b5b8d3f2a8d8e4973cd155a4b9f1849039 Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Thu, 14 Mar 2019 18:08:06 +0530
4Subject: [PATCH 56/57] fix the lto-wrapper issue on windows
5
6---
7 libiberty/simple-object.c | 6 +++++-
8 1 file changed, 5 insertions(+), 1 deletion(-)
9
10diff --git a/libiberty/simple-object.c b/libiberty/simple-object.c
11index 42aa6ac..d2465c6 100644
12--- a/libiberty/simple-object.c
13+++ b/libiberty/simple-object.c
14@@ -44,6 +44,10 @@ Boston, MA 02110-1301, USA. */
15 #define SEEK_SET 0
16 #endif
17
18+#ifndef O_BINARY
19+#define O_BINARY 0
20+#endif
21+
22 #include "simple-object-common.h"
23
24 /* The known object file formats. */
25@@ -326,7 +330,7 @@ simple_object_copy_lto_debug_sections (simple_object_read *sobj,
26 return errmsg;
27 }
28
29- outfd = creat (dest, 00777);
30+ outfd = open (dest, O_CREAT|O_WRONLY|O_TRUNC|O_BINARY, 00777);
31 if (outfd == -1)
32 {
33 *err = errno;
34--
352.7.4
36
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch
new file mode 100644
index 00000000..a5a2039d
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch
@@ -0,0 +1,47 @@
1From 6c58973f1cc1e37773aeab583aa3ac6331489106 Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Thu, 14 Mar 2019 18:11:04 +0530
4Subject: [PATCH 57/57] Fix the MB-64 bug of handling QI objects
5
6---
7 gcc/config/microblaze/microblaze.md | 14 +++++++-------
8 1 file changed, 7 insertions(+), 7 deletions(-)
9
10diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
11index e03b835..88aee9e 100644
12--- a/gcc/config/microblaze/microblaze.md
13+++ b/gcc/config/microblaze/microblaze.md
14@@ -2345,11 +2345,11 @@ else
15
16 (define_insn "branch_zero_64"
17 [(set (pc)
18- (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
19+ (if_then_else (match_operator 0 "ordered_comparison_operator"
20 [(match_operand:SI 1 "register_operand" "d")
21 (const_int 0)])
22- (match_operand:SI 2 "pc_or_label_operand" "")
23- (match_operand:SI 3 "pc_or_label_operand" "")))
24+ (match_operand 2 "pc_or_label_operand" "")
25+ (match_operand 3 "pc_or_label_operand" "")))
26 ]
27 "TARGET_MB_64"
28 {
29@@ -2365,11 +2365,11 @@ else
30
31 (define_insn "long_branch_zero"
32 [(set (pc)
33- (if_then_else (match_operator 0 "ordered_comparison_operator"
34- [(match_operand 1 "register_operand" "d")
35+ (if_then_else (match_operator:DI 0 "ordered_comparison_operator"
36+ [(match_operand:DI 1 "register_operand" "d")
37 (const_int 0)])
38- (match_operand 2 "pc_or_label_operand" "")
39- (match_operand 3 "pc_or_label_operand" "")))
40+ (match_operand:DI 2 "pc_or_label_operand" "")
41+ (match_operand:DI 3 "pc_or_label_operand" "")))
42 ]
43 "TARGET_MB_64"
44 {
45--
462.7.4
47
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
new file mode 100644
index 00000000..940009de
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
@@ -0,0 +1,87 @@
1From 1387d4fedb397f78b08ad33204a3fcf2bd63f183 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Fri, 29 Mar 2019 12:08:39 +0530
4Subject: [PATCH 57/63] [Patch,Microblaze] : We will check the possibility of
5 peephole2 optimization,if we can then we will fix the compiler issue.
6
7---
8 gcc/config/microblaze/microblaze.md | 63 ++++++++++++++++++++++---------------
9 1 file changed, 38 insertions(+), 25 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
12index bb96e2d..830ef77 100644
13--- a/gcc/config/microblaze/microblaze.md
14+++ b/gcc/config/microblaze/microblaze.md
15@@ -882,31 +882,44 @@
16 (set_attr "mode" "SI")
17 (set_attr "length" "4")])
18
19-(define_peephole2
20- [(set (match_operand:SI 0 "register_operand")
21- (fix:SI (match_operand:SF 1 "register_operand")))
22- (set (pc)
23- (if_then_else (match_operator 2 "ordered_comparison_operator"
24- [(match_operand:SI 3 "register_operand")
25- (match_operand:SI 4 "arith_operand")])
26- (label_ref (match_operand 5))
27- (pc)))]
28- "TARGET_HARD_FLOAT && !TARGET_MB_64"
29- [(set (match_dup 1) (match_dup 3))]
30-
31- {
32- rtx condition;
33- rtx cmp_op0 = operands[3];
34- rtx cmp_op1 = operands[4];
35- rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
36-
37- emit_insn (gen_cstoresf4 (comp_reg, operands[2],
38- gen_rtx_REG (SFmode, REGNO (cmp_op0)),
39- gen_rtx_REG (SFmode, REGNO (cmp_op1))));
40- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
41- emit_jump_insn (gen_condjump (condition, operands[5]));
42- }
43-)
44+;; peephole2 optimization will be done only if fint and if-then-else
45+;; are dependent.added condition for the same.
46+;; if they are dependent then gcc is giving "flow control insn inside a basic block"
47+;; testcase:
48+;; volatile float vec = 1.0;
49+;; volatile int ci = 2;
50+;; register int cj = (int)(vec);
51+;;// ci=cj;
52+;;// if (ci <0) {
53+;; if (cj < 0) {
54+;; ci = 0;
55+;; }
56+;; commenting for now.we will check the possibility of this optimization later
57+
58+;;(define_peephole2
59+;; [(set (match_operand:SI 0 "register_operand")
60+;; (fix:SI (match_operand:SF 1 "register_operand")))
61+;; (set (pc)
62+;; (if_then_else (match_operator 2 "ordered_comparison_operator"
63+;; [(match_operand:SI 3 "register_operand")
64+;; (match_operand:SI 4 "arith_operand")])
65+;; (label_ref (match_operand 5))
66+;; (pc)))]
67+;; "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))"
68+;; [(set (match_dup 1) (match_dup 3))]
69+;; {
70+;; rtx condition;
71+;; rtx cmp_op0 = operands[3];
72+;; rtx cmp_op1 = operands[4];
73+;; rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
74+;;
75+;; emit_insn (gen_cstoresf4 (comp_reg, operands[2],
76+;; gen_rtx_REG (SFmode, REGNO (cmp_op0)),
77+;; gen_rtx_REG (SFmode, REGNO (cmp_op1))));
78+;; condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
79+;; emit_jump_insn (gen_condjump (condition, operands[5]));
80+;; }
81+;;)
82
83 ;;----------------------------------------------------------------
84 ;; Negation and one's complement
85--
862.7.4
87
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
new file mode 100644
index 00000000..8bc47a43
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
@@ -0,0 +1,87 @@
1From bcbfd9f69d858306a080aa7213e96ca6eca66106 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Fri, 29 Mar 2019 12:08:39 +0530
4Subject: [PATCH 58/61] [Patch,Microblaze] : We will check the possibility of
5 peephole2 optimization,if we can then we will fix the compiler issue.
6
7---
8 gcc/config/microblaze/microblaze.md | 63 ++++++++++++++++++++++---------------
9 1 file changed, 38 insertions(+), 25 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
12index 88aee9e..8bd175f 100644
13--- a/gcc/config/microblaze/microblaze.md
14+++ b/gcc/config/microblaze/microblaze.md
15@@ -880,31 +880,44 @@
16 (set_attr "mode" "SI")
17 (set_attr "length" "4")])
18
19-(define_peephole2
20- [(set (match_operand:SI 0 "register_operand")
21- (fix:SI (match_operand:SF 1 "register_operand")))
22- (set (pc)
23- (if_then_else (match_operator 2 "ordered_comparison_operator"
24- [(match_operand:SI 3 "register_operand")
25- (match_operand:SI 4 "arith_operand")])
26- (label_ref (match_operand 5))
27- (pc)))]
28- "TARGET_HARD_FLOAT && !TARGET_MB_64"
29- [(set (match_dup 1) (match_dup 3))]
30-
31- {
32- rtx condition;
33- rtx cmp_op0 = operands[3];
34- rtx cmp_op1 = operands[4];
35- rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
36-
37- emit_insn (gen_cstoresf4 (comp_reg, operands[2],
38- gen_rtx_REG (SFmode, REGNO (cmp_op0)),
39- gen_rtx_REG (SFmode, REGNO (cmp_op1))));
40- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
41- emit_jump_insn (gen_condjump (condition, operands[5]));
42- }
43-)
44+;; peephole2 optimization will be done only if fint and if-then-else
45+;; are dependent.added condition for the same.
46+;; if they are dependent then gcc is giving "flow control insn inside a basic block"
47+;; testcase:
48+;; volatile float vec = 1.0;
49+;; volatile int ci = 2;
50+;; register int cj = (int)(vec);
51+;;// ci=cj;
52+;;// if (ci <0) {
53+;; if (cj < 0) {
54+;; ci = 0;
55+;; }
56+;; commenting for now.we will check the possibility of this optimization later
57+
58+;;(define_peephole2
59+;; [(set (match_operand:SI 0 "register_operand")
60+;; (fix:SI (match_operand:SF 1 "register_operand")))
61+;; (set (pc)
62+;; (if_then_else (match_operator 2 "ordered_comparison_operator"
63+;; [(match_operand:SI 3 "register_operand")
64+;; (match_operand:SI 4 "arith_operand")])
65+;; (label_ref (match_operand 5))
66+;; (pc)))]
67+;; "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))"
68+;; [(set (match_dup 1) (match_dup 3))]
69+;; {
70+;; rtx condition;
71+;; rtx cmp_op0 = operands[3];
72+;; rtx cmp_op1 = operands[4];
73+;; rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
74+;;
75+;; emit_insn (gen_cstoresf4 (comp_reg, operands[2],
76+;; gen_rtx_REG (SFmode, REGNO (cmp_op0)),
77+;; gen_rtx_REG (SFmode, REGNO (cmp_op1))));
78+;; condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
79+;; emit_jump_insn (gen_condjump (condition, operands[5]));
80+;; }
81+;;)
82
83 ;;----------------------------------------------------------------
84 ;; Negation and one's complement
85--
862.7.4
87
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
new file mode 100644
index 00000000..69b49898
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
@@ -0,0 +1,51 @@
1From 8e7d7f3d2e103c34bbb28afe1338107b9fd824f0 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 16 Apr 2019 17:20:24 +0530
4Subject: [PATCH 58/63] Reverting the patch as kernel boot is not working with
5 this patch CR-1026413 Revert "[Patch,Microblaze]:reverting the cost check
6 before propagating constants."
7
8This reverts commit 7156e379a67fa47a5fb9ede1448c0d528dbda65b.
9---
10 gcc/cprop.c | 4 ----
11 1 file changed, 4 deletions(-)
12
13diff --git a/gcc/cprop.c b/gcc/cprop.c
14index 42bcc81..65c0130 100644
15--- a/gcc/cprop.c
16+++ b/gcc/cprop.c
17@@ -733,7 +733,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
18 int success = 0;
19 rtx set = single_set (insn);
20
21-#if 0
22 bool check_rtx_costs = true;
23 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
24 int old_cost = set ? set_rtx_cost (set, speed) : 0;
25@@ -745,7 +744,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
26 && (GET_CODE (XEXP (note, 0)) == CONST
27 || CONSTANT_P (XEXP (note, 0)))))
28 check_rtx_costs = false;
29-#endif
30
31 /* Usually we substitute easy stuff, so we won't copy everything.
32 We however need to take care to not duplicate non-trivial CONST
33@@ -754,7 +752,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
34
35 validate_replace_src_group (from, to, insn);
36
37-#if 0
38 /* If TO is a constant, check the cost of the set after propagation
39 to the cost of the set before the propagation. If the cost is
40 higher, then do not replace FROM with TO. */
41@@ -767,7 +764,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
42 return false;
43 }
44
45-#endif
46
47 if (num_changes_pending () && apply_change_group ())
48 success = 1;
49--
502.7.4
51
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
new file mode 100644
index 00000000..2e570330
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
@@ -0,0 +1,466 @@
1From e1a10a708f209704a3921cf66dd3ff4d0814befc Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 17 Apr 2019 12:36:16 +0530
4Subject: [PATCH 59/63] [Patch,MicroBlaze]: fixed typos in mul,div and mod
5 assembly files.
6
7---
8 libgcc/config/microblaze/divsi3.S | 47 ++++++++++++++++++++++++++----
9 libgcc/config/microblaze/modsi3.S | 40 +++++++++++++++++++++++---
10 libgcc/config/microblaze/mulsi3.S | 33 +++++++++++++++++++++-
11 libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++++++++----
12 libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++++++++++---
13 5 files changed, 212 insertions(+), 20 deletions(-)
14
15diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
16index 2765e42..bd56522 100644
17--- a/libgcc/config/microblaze/divsi3.S
18+++ b/libgcc/config/microblaze/divsi3.S
19@@ -46,7 +46,7 @@
20 __divsi3:
21 .frame r1,0,r15
22
23- ADDIK r1,r1,-32
24+ ADDLIK r1,r1,-32
25 SLI r28,r1,0
26 SLI r29,r1,8
27 SLI r30,r1,16
28@@ -61,13 +61,23 @@ __divsi3:
29 SWI r30,r1,8
30 SWI r31,r1,12
31 #endif
32- BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
33- BEQI r5,$LaResult_Is_Zero # Result is Zero
34- BGEID r5,$LaR5_Pos
35+#ifdef __arch64__
36+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
37+ BEAEQI r5,$LaResult_Is_Zero # Result is Zero
38+ BEAGEID r5,$LaR5_Pos
39+#else
40+ BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
41+ BEQI r5,$LaResult_Is_Zero # Result is Zero
42+ BGEID r5,$LaR5_Pos
43+#endif
44 XOR r28,r5,r6 # Get the sign of the result
45 RSUBI r5,r5,0 # Make r5 positive
46 $LaR5_Pos:
47- BGEI r6,$LaR6_Pos
48+#ifdef __arch64__
49+ BEAGEI r6,$LaR6_Pos
50+#else
51+ BGEI r6,$LaR6_Pos
52+#endif
53 RSUBI r6,r6,0 # Make r6 positive
54 $LaR6_Pos:
55 ADDIK r30,r0,0 # Clear mod
56@@ -76,26 +86,51 @@ $LaR6_Pos:
57
58 # First part try to find the first '1' in the r5
59 $LaDIV0:
60- BLTI r5,$LaDIV2 # This traps r5 == 0x80000000
61+#ifdef __arch64__
62+ BEALTI r5,$LaDIV2 # This traps r5 == 0x80000000
63+#else
64+ BLTI r5,$LaDIV2 # This traps r5 == 0x80000000
65+#endif
66 $LaDIV1:
67 ADD r5,r5,r5 # left shift logical r5
68+#ifdef __arch64__
69+ BEAGTID r5,$LaDIV1
70+#else
71 BGTID r5,$LaDIV1
72+#endif
73 ADDIK r29,r29,-1
74 $LaDIV2:
75 ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
76 ADDC r30,r30,r30 # Move that bit into the Mod register
77 RSUB r31,r6,r30 # Try to subtract (r30 a r6)
78+#ifdef __arch64__
79+ BEALTI r31,$LaMOD_TOO_SMALL
80+#else
81 BLTI r31,$LaMOD_TOO_SMALL
82+#endif
83 OR r30,r0,r31 # Move the r31 to mod since the result was positive
84 ADDIK r3,r3,1
85 $LaMOD_TOO_SMALL:
86 ADDIK r29,r29,-1
87+#ifdef __arch64__
88+ BEAEQi r29,$LaLOOP_END
89+#else
90 BEQi r29,$LaLOOP_END
91+#endif
92 ADD r3,r3,r3 # Shift in the '1' into div
93+#ifdef __arch64__
94+ BREAI $LaDIV2 # Div2
95+#else
96 BRI $LaDIV2 # Div2
97+#endif
98 $LaLOOP_END:
99+#ifdef __arch64__
100+ BEAGEI r28,$LaRETURN_HERE
101+ BREAID $LaRETURN_HERE
102+#else
103 BGEI r28,$LaRETURN_HERE
104 BRID $LaRETURN_HERE
105+#endif
106 RSUBI r3,r3,0 # Negate the result
107 $LaDiv_By_Zero:
108 $LaResult_Is_Zero:
109diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
110index b0e6cad..3632fad 100644
111--- a/libgcc/config/microblaze/modsi3.S
112+++ b/libgcc/config/microblaze/modsi3.S
113@@ -62,40 +62,72 @@ __modsi3:
114 swi r31,r1,12
115 #endif
116
117+#ifdef __arch64__
118+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
119+ BEAEQI r5,$LaResult_Is_Zero # Result is Zero
120+ BEAGEId r5,$LaR5_Pos
121+#else
122 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
123 BEQI r5,$LaResult_Is_Zero # Result is Zero
124 BGEId r5,$LaR5_Pos
125+#endif
126 ADD r28,r5,r0 # Get the sign of the result [ Depends only on the first arg]
127 RSUBI r5,r5,0 # Make r5 positive
128 $LaR5_Pos:
129- BGEI r6,$LaR6_Pos
130+#ifdef __arch64__
131+ BEAGEI r6,$LaR6_Pos
132+#else
133+ BGEI r6,$LaR6_Pos
134+#endif
135 RSUBI r6,r6,0 # Make r6 positive
136 $LaR6_Pos:
137 ADDIK r3,r0,0 # Clear mod
138 ADDIK r30,r0,0 # clear div
139- BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
140+#ifdef __arch64__
141+ BEALTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
142 # the first bit search.
143+#else
144+ BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
145+ # the first bit search.
146+#endif
147 ADDIK r29,r0,32 # Initialize the loop count
148 # First part try to find the first '1' in the r5
149 $LaDIV1:
150 ADD r5,r5,r5 # left shift logical r5
151- BGEID r5,$LaDIV1 #
152+#ifdef __arch64__
153+ BEAGEID r5,$LaDIV1 #
154+#else
155+ BGEID r5,$LaDIV1 #
156+#endif
157 ADDIK r29,r29,-1
158 $LaDIV2:
159 ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
160 ADDC r3,r3,r3 # Move that bit into the Mod register
161 rSUB r31,r6,r3 # Try to subtract (r30 a r6)
162+#ifdef __arch64__
163+ BEALTi r31,$LaMOD_TOO_SMALL
164+#else
165 BLTi r31,$LaMOD_TOO_SMALL
166+#endif
167 OR r3,r0,r31 # Move the r31 to mod since the result was positive
168 ADDIK r30,r30,1
169 $LaMOD_TOO_SMALL:
170 ADDIK r29,r29,-1
171+#ifdef __arch64__
172+ BEAEQi r29,$LaLOOP_END
173+ ADD r30,r30,r30 # Shift in the '1' into div
174+ BREAI $LaDIV2 # Div2
175+$LaLOOP_END:
176+ BEAGEI r28,$LaRETURN_HERE
177+ BREAId $LaRETURN_HERE
178+#else
179 BEQi r29,$LaLOOP_END
180 ADD r30,r30,r30 # Shift in the '1' into div
181 BRI $LaDIV2 # Div2
182 $LaLOOP_END:
183 BGEI r28,$LaRETURN_HERE
184 BRId $LaRETURN_HERE
185+#endif
186 rsubi r3,r3,0 # Negate the result
187 $LaDiv_By_Zero:
188 $LaResult_Is_Zero:
189@@ -108,7 +140,7 @@ $LaRETURN_HERE:
190 lli r29,r1,8
191 lli r30,r1,16
192 lli r31,r1,24
193- addik r1,r1,32
194+ addlik r1,r1,32
195 rtsd r15,8
196 nop
197 #else
198diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
199index e28c69a..991dbcd 100644
200--- a/libgcc/config/microblaze/mulsi3.S
201+++ b/libgcc/config/microblaze/mulsi3.S
202@@ -43,7 +43,37 @@
203 .type __mulsi3,@function
204 #ifdef __arch64__
205 .align 3
206-#endif
207+__mulsi3:
208+ .frame r1,0,r15
209+ add r3,r0,r0
210+ BEAEQI r5,$L_Result_Is_Zero # Multiply by Zero
211+ BEAEQI r6,$L_Result_Is_Zero # Multiply by Zero
212+ BEAGEId r5,$L_R5_Pos
213+ XOR r4,r5,r6 # Get the sign of the result
214+ RSUBI r5,r5,0 # Make r5 positive
215+$L_R5_Pos:
216+ BEAGEI r6,$L_R6_Pos
217+ RSUBI r6,r6,0 # Make r6 positive
218+$L_R6_Pos:
219+ breai $L1
220+$L2:
221+ add r5,r5,r5
222+$L1:
223+ srl r6,r6
224+ addc r7,r0,r0
225+ beaeqi r7,$L2
226+ beaneid r6,$L2
227+ add r3,r3,r5
228+ bealti r4,$L_NegateResult
229+ rtsd r15,8
230+ nop
231+$L_NegateResult:
232+ rtsd r15,8
233+ rsub r3,r3,r0
234+$L_Result_Is_Zero:
235+ rtsd r15,8
236+ addi r3,r0,0
237+#else
238 __mulsi3:
239 .frame r1,0,r15
240 add r3,r0,r0
241@@ -74,5 +104,6 @@ $L_NegateResult:
242 $L_Result_Is_Zero:
243 rtsd r15,8
244 addi r3,r0,0
245+#endif
246 .end __mulsi3
247 .size __mulsi3, . - __mulsi3
248diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
249index b1e44b6..42b086e 100644
250--- a/libgcc/config/microblaze/udivsi3.S
251+++ b/libgcc/config/microblaze/udivsi3.S
252@@ -59,52 +59,96 @@ __udivsi3:
253 SWI r30,r1,4
254 SWI r31,r1,8
255 #endif
256+#ifdef __arch64__
257+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
258+ BEAEQID r5,$LaResult_Is_Zero # Result is Zero
259+#else
260 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
261 BEQID r5,$LaResult_Is_Zero # Result is Zero
262+#endif
263 ADDIK r30,r0,0 # Clear mod
264 ADDIK r29,r0,32 # Initialize the loop count
265
266 # Check if r6 and r5 are equal # if yes, return 1
267 RSUB r18,r5,r6
268+#ifdef __arch64__
269+ BEAEQID r18,$LaRETURN_HERE
270+#else
271 BEQID r18,$LaRETURN_HERE
272+#endif
273 ADDIK r3,r0,1
274
275 # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
276 XOR r18,r5,r6
277- BGEID r18,16
278+#ifdef __arch64__
279+ BEAGEID r18,16
280+#else
281+ BGEID r18,16
282+#endif
283 ADD r3,r0,r0 # We would anyways clear r3
284+#ifdef __arch64__
285+ BEALTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater
286+ BREAI $LCheckr6
287+ RSUB r18,r6,r5 # MICROBLAZEcmp
288+ BEALTI r18,$LaRETURN_HERE
289+#else
290 BLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater
291 BRI $LCheckr6
292 RSUB r18,r6,r5 # MICROBLAZEcmp
293 BLTI r18,$LaRETURN_HERE
294-
295+#endif
296 # If r6 [bit 31] is set, then return result as 1
297 $LCheckr6:
298- BGTI r6,$LaDIV0
299- BRID $LaRETURN_HERE
300+#ifdef __arch64__
301+ BEAGTI r6,$LaDIV0
302+ BREAID $LaRETURN_HERE
303+#else
304+ BGTI r6,$LaDIV0
305+ BRID $LaRETURN_HERE
306+#endif
307 ADDIK r3,r0,1
308
309 # First part try to find the first '1' in the r5
310 $LaDIV0:
311+#ifdef __arch64__
312+ BEALTI r5,$LaDIV2
313+#else
314 BLTI r5,$LaDIV2
315+#endif
316 $LaDIV1:
317 ADD r5,r5,r5 # left shift logical r5
318+#ifdef __arch64__
319+ BEAGTID r5,$LaDIV1
320+#else
321 BGTID r5,$LaDIV1
322+#endif
323 ADDIK r29,r29,-1
324 $LaDIV2:
325 ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
326 ADDC r30,r30,r30 # Move that bit into the Mod register
327 RSUB r31,r6,r30 # Try to subtract (r30 a r6)
328+#ifdef __arch64__
329+ BEALTI r31,$LaMOD_TOO_SMALL
330+#else
331 BLTI r31,$LaMOD_TOO_SMALL
332+#endif
333 OR r30,r0,r31 # Move the r31 to mod since the result was positive
334 ADDIK r3,r3,1
335 $LaMOD_TOO_SMALL:
336 ADDIK r29,r29,-1
337+#ifdef __arch64__
338+ BEAEQi r29,$LaLOOP_END
339+ ADD r3,r3,r3 # Shift in the '1' into div
340+ BREAI $LaDIV2 # Div2
341+$LaLOOP_END:
342+ BREAI $LaRETURN_HERE
343+#else
344 BEQi r29,$LaLOOP_END
345 ADD r3,r3,r3 # Shift in the '1' into div
346 BRI $LaDIV2 # Div2
347 $LaLOOP_END:
348 BRI $LaRETURN_HERE
349+#endif
350 $LaDiv_By_Zero:
351 $LaResult_Is_Zero:
352 OR r3,r0,r0 # set result to 0
353@@ -115,7 +159,7 @@ $LaRETURN_HERE:
354 LLI r29,r1,0
355 LLI r30,r1,8
356 LLI r31,r1,16
357- ADDIK r1,r1,24
358+ ADDLIK r1,r1,24
359 RTSD r15,8
360 NOP
361 #else
362diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
363index 1b3070e..91430a6 100644
364--- a/libgcc/config/microblaze/umodsi3.S
365+++ b/libgcc/config/microblaze/umodsi3.S
366@@ -46,7 +46,7 @@
367 __umodsi3:
368 .frame r1,0,r15
369
370- addik r1,r1,-24
371+ addlik r1,r1,-24
372 sli r29,r1,0
373 sli r30,r1,8
374 sli r31,r1,16
375@@ -59,27 +59,77 @@ __umodsi3:
376 swi r30,r1,4
377 swi r31,r1,8
378 #endif
379+#ifdef __arch64__
380+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
381+ BEAEQId r5,$LaResult_Is_Zero # Result is Zero
382+#else
383 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
384 BEQId r5,$LaResult_Is_Zero # Result is Zero
385+#endif
386 ADDIK r3,r0,0 # Clear div
387 ADDIK r30,r0,0 # clear mod
388 ADDIK r29,r0,32 # Initialize the loop count
389
390 # Check if r6 and r5 are equal # if yes, return 0
391 rsub r18,r5,r6
392- beqi r18,$LaRETURN_HERE
393
394+#ifdef __arch64__
395+ beaeqi r18,$LaRETURN_HERE
396+#else
397+ beqi r18,$LaRETURN_HERE
398+#endif
399 # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
400 xor r18,r5,r6
401+#ifdef __arch64__
402+ beageid r18,16
403+ addik r3,r5,0
404+ bealti r6,$LaRETURN_HERE
405+ breai $LCheckr6
406+ rsub r18,r5,r6 # MICROBLAZEcmp
407+ beagti r18,$LaRETURN_HERE
408+#else
409 bgeid r18,16
410 addik r3,r5,0
411 blti r6,$LaRETURN_HERE
412 bri $LCheckr6
413 rsub r18,r5,r6 # MICROBLAZEcmp
414 bgti r18,$LaRETURN_HERE
415-
416+#endif
417 # If r6 [bit 31] is set, then return result as r5-r6
418 $LCheckr6:
419+#ifdef __arch64__
420+ beagtid r6,$LaDIV0
421+ addik r3,r0,0
422+ addik r18,r0,0x7fffffff
423+ and r5,r5,r18
424+ and r6,r6,r18
425+ breaid $LaRETURN_HERE
426+ rsub r3,r6,r5
427+# First part: try to find the first '1' in the r5
428+$LaDIV0:
429+ BEALTI r5,$LaDIV2
430+$LaDIV1:
431+ ADD r5,r5,r5 # left shift logical r5
432+ BEAGEID r5,$LaDIV1 #
433+ ADDIK r29,r29,-1
434+$LaDIV2:
435+ ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
436+ ADDC r3,r3,r3 # Move that bit into the Mod register
437+ rSUB r31,r6,r3 # Try to subtract (r3 a r6)
438+ BEALTi r31,$LaMOD_TOO_SMALL
439+ OR r3,r0,r31 # Move the r31 to mod since the result was positive
440+ ADDIK r30,r30,1
441+$LaMOD_TOO_SMALL:
442+ ADDIK r29,r29,-1
443+ BEAEQi r29,$LaLOOP_END
444+ ADD r30,r30,r30 # Shift in the '1' into div
445+ BREAI $LaDIV2 # Div2
446+$LaLOOP_END:
447+ BREAI $LaRETURN_HERE
448+$LaDiv_By_Zero:
449+$LaResult_Is_Zero:
450+ or r3,r0,r0 # set result to 0
451+#else
452 bgtid r6,$LaDIV0
453 addik r3,r0,0
454 addik r18,r0,0x7fffffff
455@@ -111,7 +161,7 @@ $LaLOOP_END:
456 $LaDiv_By_Zero:
457 $LaResult_Is_Zero:
458 or r3,r0,r0 # set result to 0
459-
460+#endif
461 #ifdef __arch64__
462 $LaRETURN_HERE:
463 # Restore values of CSRs and that of r3 and the divisor and the dividend
464--
4652.7.4
466
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
new file mode 100644
index 00000000..be4dfad5
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
@@ -0,0 +1,51 @@
1From 2f22090a7e8216f7a9f7e958b77ac83006a7ce89 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 16 Apr 2019 17:20:24 +0530
4Subject: [PATCH 59/61] Reverting the patch as kernel boot is not working with
5 this patch CR-1026413 Revert "[Patch,Microblaze]:reverting the cost check
6 before propagating constants."
7
8This reverts commit 7156e379a67fa47a5fb9ede1448c0d528dbda65b.
9---
10 gcc/cprop.c | 4 ----
11 1 file changed, 4 deletions(-)
12
13diff --git a/gcc/cprop.c b/gcc/cprop.c
14index deb706b..e4df509 100644
15--- a/gcc/cprop.c
16+++ b/gcc/cprop.c
17@@ -733,7 +733,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
18 int success = 0;
19 rtx set = single_set (insn);
20
21-#if 0
22 bool check_rtx_costs = true;
23 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
24 int old_cost = set ? set_rtx_cost (set, speed) : 0;
25@@ -745,7 +744,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
26 && (GET_CODE (XEXP (note, 0)) == CONST
27 || CONSTANT_P (XEXP (note, 0)))))
28 check_rtx_costs = false;
29-#endif
30
31 /* Usually we substitute easy stuff, so we won't copy everything.
32 We however need to take care to not duplicate non-trivial CONST
33@@ -754,7 +752,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
34
35 validate_replace_src_group (from, to, insn);
36
37-#if 0
38 /* If TO is a constant, check the cost of the set after propagation
39 to the cost of the set before the propagation. If the cost is
40 higher, then do not replace FROM with TO. */
41@@ -767,7 +764,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
42 return false;
43 }
44
45-#endif
46
47 if (num_changes_pending () && apply_change_group ())
48 success = 1;
49--
502.7.4
51
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Author-Nagaraju-nmekala-xilinx.com.patch
new file mode 100644
index 00000000..9f878669
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Author-Nagaraju-nmekala-xilinx.com.patch
@@ -0,0 +1,479 @@
1From f0332f119c3cbe95886dae77c4b5a9b9907b4b17 Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Thu, 18 Apr 2019 16:00:37 +0530
4Subject: [PATCH 60/63] Author: Nagaraju <nmekala@xilinx.com> Date: Wed Apr
5 17 14:11:00 2019 +0530
6
7 [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default
8 By default MB-64 is generatting barrel-shift instructions. It has been
9 removed from default. Barrel-shift instructions will be generated only if
10 barrel-shifter is enabled. Similarly to double instructions as well.
11
12 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
13---
14 gcc/config/microblaze/microblaze.c | 2 +-
15 gcc/config/microblaze/microblaze.md | 269 +++++++++++++++++++++++++++++++++---
16 2 files changed, 252 insertions(+), 19 deletions(-)
17
18diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
19index 220e03d..5c09452 100644
20--- a/gcc/config/microblaze/microblaze.c
21+++ b/gcc/config/microblaze/microblaze.c
22@@ -4008,7 +4008,7 @@ microblaze_expand_divide (rtx operands[])
23 emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
24
25 if (TARGET_MB_64) {
26- emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
27+ emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4)));
28 emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
29 }
30 else {
31diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
32index 830ef77..3e7c647 100644
33--- a/gcc/config/microblaze/microblaze.md
34+++ b/gcc/config/microblaze/microblaze.md
35@@ -547,7 +547,7 @@
36 [(set (match_operand:DF 0 "register_operand" "=d")
37 (plus:DF (match_operand:DF 1 "register_operand" "d")
38 (match_operand:DF 2 "register_operand" "d")))]
39- "TARGET_MB_64"
40+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
41 "dadd\t%0,%1,%2"
42 [(set_attr "type" "fadd")
43 (set_attr "mode" "DF")
44@@ -557,7 +557,7 @@
45 [(set (match_operand:DF 0 "register_operand" "=d")
46 (minus:DF (match_operand:DF 1 "register_operand" "d")
47 (match_operand:DF 2 "register_operand" "d")))]
48- "TARGET_MB_64"
49+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
50 "drsub\t%0,%2,%1"
51 [(set_attr "type" "frsub")
52 (set_attr "mode" "DF")
53@@ -567,7 +567,7 @@
54 [(set (match_operand:DF 0 "register_operand" "=d")
55 (mult:DF (match_operand:DF 1 "register_operand" "d")
56 (match_operand:DF 2 "register_operand" "d")))]
57- "TARGET_MB_64"
58+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
59 "dmul\t%0,%1,%2"
60 [(set_attr "type" "fmul")
61 (set_attr "mode" "DF")
62@@ -577,7 +577,7 @@
63 [(set (match_operand:DF 0 "register_operand" "=d")
64 (div:DF (match_operand:DF 1 "register_operand" "d")
65 (match_operand:DF 2 "register_operand" "d")))]
66- "TARGET_MB_64"
67+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
68 "ddiv\t%0,%2,%1"
69 [(set_attr "type" "fdiv")
70 (set_attr "mode" "DF")
71@@ -587,7 +587,7 @@
72 (define_insn "sqrtdf2"
73 [(set (match_operand:DF 0 "register_operand" "=d")
74 (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
75- "TARGET_MB_64"
76+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
77 "dsqrt\t%0,%1"
78 [(set_attr "type" "fsqrt")
79 (set_attr "mode" "DF")
80@@ -596,7 +596,7 @@
81 (define_insn "floatdidf2"
82 [(set (match_operand:DF 0 "register_operand" "=d")
83 (float:DF (match_operand:DI 1 "register_operand" "d")))]
84- "TARGET_MB_64"
85+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
86 "dbl\t%0,%1"
87 [(set_attr "type" "fcvt")
88 (set_attr "mode" "DF")
89@@ -605,7 +605,7 @@
90 (define_insn "fix_truncdfdi2"
91 [(set (match_operand:DI 0 "register_operand" "=d")
92 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
93- "TARGET_MB_64"
94+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
95 "dlong\t%0,%1"
96 [(set_attr "type" "fcvt")
97 (set_attr "mode" "DI")
98@@ -1301,6 +1301,34 @@
99 (set_attr "mode" "DI")
100 (set_attr "length" "4")])
101
102+(define_insn "*movdi_internal2_bshift"
103+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m")
104+ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))]
105+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
106+ {
107+ switch (which_alternative)
108+ {
109+ case 0:
110+ return "addlk\t%0,%1,r0";
111+ case 1:
112+ case 2:
113+ if (GET_CODE (operands[1]) == CONST_INT &&
114+ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
115+ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
116+ else
117+ return "addlik\t%0,r0,%1";
118+ case 3:
119+ case 4:
120+ return "ll%i1\t%0,%1";
121+ case 5:
122+ case 6:
123+ return "sl%i0\t%z1,%0";
124+ }
125+ }
126+ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
127+ (set_attr "mode" "DI")
128+ (set_attr "length" "4,4,12,4,8,4,8")])
129+
130 (define_insn "*movdi_internal2"
131 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m")
132 (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))]
133@@ -1314,7 +1342,15 @@
134 case 2:
135 if (GET_CODE (operands[1]) == CONST_INT &&
136 (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
137- return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
138+ {
139+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
140+ output_asm_insn ("addlik\t%0,r0,%h1", operands);
141+ output_asm_insn ("addlik\t%2,r0,32", operands);
142+ output_asm_insn ("addlik\t%2,%2,-1", operands);
143+ output_asm_insn ("beaneid\t%2,.-8", operands);
144+ output_asm_insn ("addlk\t%0,%0,%0", operands);
145+ return "addlik\t%0,%0,%j1 #li => la";
146+ }
147 else
148 return "addlik\t%0,r0,%1";
149 case 3:
150@@ -1388,7 +1424,7 @@
151 (define_insn "movdi_long_int"
152 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
153 (match_operand:DI 1 "general_operand" "i"))]
154- "TARGET_MB_64"
155+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
156 "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
157 [(set_attr "type" "no_delay_arith")
158 (set_attr "mode" "DI")
159@@ -1655,6 +1691,33 @@
160 ;; movdf_internal
161 ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
162 ;;
163+(define_insn "*movdf_internal_64_bshift"
164+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
165+ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
166+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
167+ {
168+ switch (which_alternative)
169+ {
170+ case 0:
171+ return "addlk\t%0,%1,r0";
172+ case 1:
173+ return "addlk\t%0,r0,r0";
174+ case 2:
175+ case 4:
176+ return "ll%i1\t%0,%1";
177+ case 3:
178+ {
179+ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
180+ }
181+ case 5:
182+ return "sl%i0\t%1,%0";
183+ }
184+ gcc_unreachable ();
185+ }
186+ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
187+ (set_attr "mode" "DF")
188+ (set_attr "length" "4,4,4,16,4,4")])
189+
190 (define_insn "*movdf_internal_64"
191 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
192 (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
193@@ -1671,7 +1734,13 @@
194 return "ll%i1\t%0,%1";
195 case 3:
196 {
197- return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
198+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
199+ output_asm_insn ("addlik\t%0,r0,%h1", operands);
200+ output_asm_insn ("addlik\t%2,r0,32", operands);
201+ output_asm_insn ("addlik\t%2,%2,-1", operands);
202+ output_asm_insn ("beaneid\t%2,.-8", operands);
203+ output_asm_insn ("addlk\t%0,%0,%0", operands);
204+ return "addlik\t%0,%0,%j1 #li => la";
205 }
206 case 5:
207 return "sl%i0\t%1,%0";
208@@ -1791,11 +1860,21 @@
209 "TARGET_MB_64"
210 {
211 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
212-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
213+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
214 {
215 emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
216 DONE;
217 }
218+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
219+ {
220+ emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2]));
221+ DONE;
222+ }
223+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
224+ {
225+ emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2]));
226+ DONE;
227+ }
228 else
229 FAIL;
230 }
231@@ -1805,7 +1884,7 @@ else
232 [(set (match_operand:DI 0 "register_operand" "=d,d")
233 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
234 (match_operand:DI 2 "arith_operand" "I,d")))]
235- "TARGET_MB_64"
236+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
237 "@
238 bsllli\t%0,%1,%2
239 bslll\t%0,%1,%2"
240@@ -1813,6 +1892,51 @@ else
241 (set_attr "mode" "DI,DI")
242 (set_attr "length" "4,4")]
243 )
244+
245+(define_insn "ashldi3_const"
246+ [(set (match_operand:DI 0 "register_operand" "=&d")
247+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
248+ (match_operand:DI 2 "immediate_operand" "I")))]
249+ "TARGET_MB_64"
250+ {
251+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
252+
253+ output_asm_insn ("orli\t%3,r0,%2", operands);
254+ if (REGNO (operands[0]) != REGNO (operands[1]))
255+ output_asm_insn ("addlk\t%0,%1,r0", operands);
256+
257+ output_asm_insn ("addlik\t%3,%3,-1", operands);
258+ output_asm_insn ("beaneid\t%3,.-8", operands);
259+ return "addlk\t%0,%0,%0";
260+ }
261+ [(set_attr "type" "multi")
262+ (set_attr "mode" "DI")
263+ (set_attr "length" "20")]
264+)
265+
266+(define_insn "ashldi3_reg"
267+ [(set (match_operand:DI 0 "register_operand" "=&d")
268+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
269+ (match_operand:DI 2 "register_operand" "d")))]
270+ "TARGET_MB_64"
271+ {
272+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
273+ output_asm_insn ("andli\t%3,%2,31", operands);
274+ if (REGNO (operands[0]) != REGNO (operands[1]))
275+ output_asm_insn ("addlk\t%0,r0,%1", operands);
276+ /* Exit the loop if zero shift. */
277+ output_asm_insn ("beaeqid\t%3,.+24", operands);
278+ /* Emit the loop. */
279+ output_asm_insn ("addlk\t%0,%0,r0", operands);
280+ output_asm_insn ("addlik\t%3,%3,-1", operands);
281+ output_asm_insn ("beaneid\t%3,.-8", operands);
282+ return "addlk\t%0,%0,%0";
283+ }
284+ [(set_attr "type" "multi")
285+ (set_attr "mode" "DI")
286+ (set_attr "length" "28")]
287+)
288+
289 ;; The following patterns apply when there is no barrel shifter present
290
291 (define_insn "*ashlsi3_with_mul_delay"
292@@ -1946,11 +2070,21 @@ else
293 "TARGET_MB_64"
294 {
295 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
296-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
297+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
298 {
299 emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
300 DONE;
301 }
302+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
303+ {
304+ emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2]));
305+ DONE;
306+ }
307+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
308+ {
309+ emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2]));
310+ DONE;
311+ }
312 else
313 FAIL;
314 }
315@@ -1960,7 +2094,7 @@ else
316 [(set (match_operand:DI 0 "register_operand" "=d,d")
317 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
318 (match_operand:DI 2 "arith_operand" "I,d")))]
319- "TARGET_MB_64"
320+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
321 "@
322 bslrai\t%0,%1,%2
323 bslra\t%0,%1,%2"
324@@ -1968,6 +2102,51 @@ else
325 (set_attr "mode" "DI,DI")
326 (set_attr "length" "4,4")]
327 )
328+
329+(define_insn "ashrdi3_const"
330+ [(set (match_operand:DI 0 "register_operand" "=&d")
331+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
332+ (match_operand:DI 2 "immediate_operand" "I")))]
333+ "TARGET_MB_64"
334+ {
335+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
336+
337+ output_asm_insn ("orli\t%3,r0,%2", operands);
338+ if (REGNO (operands[0]) != REGNO (operands[1]))
339+ output_asm_insn ("addlk\t%0,%1,r0", operands);
340+
341+ output_asm_insn ("addlik\t%3,%3,-1", operands);
342+ output_asm_insn ("beaneid\t%3,.-8", operands);
343+ return "srla\t%0,%0";
344+ }
345+ [(set_attr "type" "arith")
346+ (set_attr "mode" "DI")
347+ (set_attr "length" "20")]
348+)
349+
350+(define_insn "ashrdi3_reg"
351+ [(set (match_operand:DI 0 "register_operand" "=&d")
352+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
353+ (match_operand:DI 2 "register_operand" "d")))]
354+ "TARGET_MB_64"
355+ {
356+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
357+ output_asm_insn ("andli\t%3,%2,31", operands);
358+ if (REGNO (operands[0]) != REGNO (operands[1]))
359+ output_asm_insn ("addlk\t%0,r0,%1", operands);
360+ /* Exit the loop if zero shift. */
361+ output_asm_insn ("beaeqid\t%3,.+24", operands);
362+ /* Emit the loop. */
363+ output_asm_insn ("addlk\t%0,%0,r0", operands);
364+ output_asm_insn ("addlik\t%3,%3,-1", operands);
365+ output_asm_insn ("beaneid\t%3,.-8", operands);
366+ return "srla\t%0,%0";
367+ }
368+ [(set_attr "type" "multi")
369+ (set_attr "mode" "DI")
370+ (set_attr "length" "28")]
371+)
372+
373 (define_expand "ashrsi3"
374 [(set (match_operand:SI 0 "register_operand" "=&d")
375 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
376@@ -2085,11 +2264,21 @@ else
377 "TARGET_MB_64"
378 {
379 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
380-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
381+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
382 {
383 emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
384 DONE;
385 }
386+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
387+ {
388+ emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2]));
389+ DONE;
390+ }
391+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
392+ {
393+ emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2]));
394+ DONE;
395+ }
396 else
397 FAIL;
398 }
399@@ -2099,7 +2288,7 @@ else
400 [(set (match_operand:DI 0 "register_operand" "=d,d")
401 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
402 (match_operand:DI 2 "arith_operand" "I,d")))]
403- "TARGET_MB_64"
404+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
405 "@
406 bslrli\t%0,%1,%2
407 bslrl\t%0,%1,%2"
408@@ -2108,6 +2297,50 @@ else
409 (set_attr "length" "4,4")]
410 )
411
412+(define_insn "lshrdi3_const"
413+ [(set (match_operand:DI 0 "register_operand" "=&d")
414+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
415+ (match_operand:DI 2 "immediate_operand" "I")))]
416+ "TARGET_MB_64"
417+ {
418+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
419+
420+ output_asm_insn ("orli\t%3,r0,%2", operands);
421+ if (REGNO (operands[0]) != REGNO (operands[1]))
422+ output_asm_insn ("addlk\t%0,%1,r0", operands);
423+
424+ output_asm_insn ("addlik\t%3,%3,-1", operands);
425+ output_asm_insn ("beaneid\t%3,.-8", operands);
426+ return "srll\t%0,%0";
427+ }
428+ [(set_attr "type" "multi")
429+ (set_attr "mode" "DI")
430+ (set_attr "length" "20")]
431+)
432+
433+(define_insn "lshrdi3_reg"
434+ [(set (match_operand:DI 0 "register_operand" "=&d")
435+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
436+ (match_operand:DI 2 "register_operand" "d")))]
437+ "TARGET_MB_64"
438+ {
439+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
440+ output_asm_insn ("andli\t%3,%2,31", operands);
441+ if (REGNO (operands[0]) != REGNO (operands[1]))
442+ output_asm_insn ("addlk\t%0,r0,%1", operands);
443+ /* Exit the loop if zero shift. */
444+ output_asm_insn ("beaeqid\t%3,.+24", operands);
445+ /* Emit the loop. */
446+ output_asm_insn ("addlk\t%0,%0,r0", operands);
447+ output_asm_insn ("addlik\t%3,%3,-1", operands);
448+ output_asm_insn ("beaneid\t%3,.-8", operands);
449+ return "srll\t%0,%0";
450+ }
451+ [(set_attr "type" "multi")
452+ (set_attr "mode" "SI")
453+ (set_attr "length" "28")]
454+)
455+
456 (define_expand "lshrsi3"
457 [(set (match_operand:SI 0 "register_operand" "=&d")
458 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
459@@ -2235,7 +2468,7 @@ else
460 (eq:DI
461 (match_operand:DI 1 "register_operand" "d")
462 (match_operand:DI 2 "register_operand" "d")))]
463- "TARGET_MB_64"
464+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
465 "pcmpleq\t%0,%1,%2"
466 [(set_attr "type" "arith")
467 (set_attr "mode" "DI")
468@@ -2247,7 +2480,7 @@ else
469 (ne:DI
470 (match_operand:DI 1 "register_operand" "d")
471 (match_operand:DI 2 "register_operand" "d")))]
472- "TARGET_MB_64"
473+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
474 "pcmplne\t%0,%1,%2"
475 [(set_attr "type" "arith")
476 (set_attr "mode" "DI")
477--
4782.7.4
479
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
new file mode 100644
index 00000000..1548faad
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
@@ -0,0 +1,466 @@
1From 80919b0f43b275e70521e4f85cd28bcd0ece3b80 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 17 Apr 2019 12:36:16 +0530
4Subject: [PATCH 60/61] [Patch,MicroBlaze]: fixed typos in mul,div and mod
5 assembly files.
6
7---
8 libgcc/config/microblaze/divsi3.S | 47 ++++++++++++++++++++++++++----
9 libgcc/config/microblaze/modsi3.S | 40 +++++++++++++++++++++++---
10 libgcc/config/microblaze/mulsi3.S | 33 +++++++++++++++++++++-
11 libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++++++++----
12 libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++++++++++---
13 5 files changed, 212 insertions(+), 20 deletions(-)
14
15diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
16index 7e7d875..cfb4c05 100644
17--- a/libgcc/config/microblaze/divsi3.S
18+++ b/libgcc/config/microblaze/divsi3.S
19@@ -46,7 +46,7 @@
20 __divsi3:
21 .frame r1,0,r15
22
23- ADDIK r1,r1,-32
24+ ADDLIK r1,r1,-32
25 SLI r28,r1,0
26 SLI r29,r1,8
27 SLI r30,r1,16
28@@ -61,13 +61,23 @@ __divsi3:
29 SWI r30,r1,8
30 SWI r31,r1,12
31 #endif
32- BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
33- BEQI r5,$LaResult_Is_Zero # Result is Zero
34- BGEID r5,$LaR5_Pos
35+#ifdef __arch64__
36+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
37+ BEAEQI r5,$LaResult_Is_Zero # Result is Zero
38+ BEAGEID r5,$LaR5_Pos
39+#else
40+ BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
41+ BEQI r5,$LaResult_Is_Zero # Result is Zero
42+ BGEID r5,$LaR5_Pos
43+#endif
44 XOR r28,r5,r6 # Get the sign of the result
45 RSUBI r5,r5,0 # Make r5 positive
46 $LaR5_Pos:
47- BGEI r6,$LaR6_Pos
48+#ifdef __arch64__
49+ BEAGEI r6,$LaR6_Pos
50+#else
51+ BGEI r6,$LaR6_Pos
52+#endif
53 RSUBI r6,r6,0 # Make r6 positive
54 $LaR6_Pos:
55 ADDIK r30,r0,0 # Clear mod
56@@ -76,26 +86,51 @@ $LaR6_Pos:
57
58 # First part try to find the first '1' in the r5
59 $LaDIV0:
60- BLTI r5,$LaDIV2 # This traps r5 == 0x80000000
61+#ifdef __arch64__
62+ BEALTI r5,$LaDIV2 # This traps r5 == 0x80000000
63+#else
64+ BLTI r5,$LaDIV2 # This traps r5 == 0x80000000
65+#endif
66 $LaDIV1:
67 ADD r5,r5,r5 # left shift logical r5
68+#ifdef __arch64__
69+ BEAGTID r5,$LaDIV1
70+#else
71 BGTID r5,$LaDIV1
72+#endif
73 ADDIK r29,r29,-1
74 $LaDIV2:
75 ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
76 ADDC r30,r30,r30 # Move that bit into the Mod register
77 RSUB r31,r6,r30 # Try to subtract (r30 a r6)
78+#ifdef __arch64__
79+ BEALTI r31,$LaMOD_TOO_SMALL
80+#else
81 BLTI r31,$LaMOD_TOO_SMALL
82+#endif
83 OR r30,r0,r31 # Move the r31 to mod since the result was positive
84 ADDIK r3,r3,1
85 $LaMOD_TOO_SMALL:
86 ADDIK r29,r29,-1
87+#ifdef __arch64__
88+ BEAEQi r29,$LaLOOP_END
89+#else
90 BEQi r29,$LaLOOP_END
91+#endif
92 ADD r3,r3,r3 # Shift in the '1' into div
93+#ifdef __arch64__
94+ BREAI $LaDIV2 # Div2
95+#else
96 BRI $LaDIV2 # Div2
97+#endif
98 $LaLOOP_END:
99+#ifdef __arch64__
100+ BEAGEI r28,$LaRETURN_HERE
101+ BREAID $LaRETURN_HERE
102+#else
103 BGEI r28,$LaRETURN_HERE
104 BRID $LaRETURN_HERE
105+#endif
106 RSUBI r3,r3,0 # Negate the result
107 $LaDiv_By_Zero:
108 $LaResult_Is_Zero:
109diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
110index 46ff34a..49618dd 100644
111--- a/libgcc/config/microblaze/modsi3.S
112+++ b/libgcc/config/microblaze/modsi3.S
113@@ -62,40 +62,72 @@ __modsi3:
114 swi r31,r1,12
115 #endif
116
117+#ifdef __arch64__
118+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
119+ BEAEQI r5,$LaResult_Is_Zero # Result is Zero
120+ BEAGEId r5,$LaR5_Pos
121+#else
122 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
123 BEQI r5,$LaResult_Is_Zero # Result is Zero
124 BGEId r5,$LaR5_Pos
125+#endif
126 ADD r28,r5,r0 # Get the sign of the result [ Depends only on the first arg]
127 RSUBI r5,r5,0 # Make r5 positive
128 $LaR5_Pos:
129- BGEI r6,$LaR6_Pos
130+#ifdef __arch64__
131+ BEAGEI r6,$LaR6_Pos
132+#else
133+ BGEI r6,$LaR6_Pos
134+#endif
135 RSUBI r6,r6,0 # Make r6 positive
136 $LaR6_Pos:
137 ADDIK r3,r0,0 # Clear mod
138 ADDIK r30,r0,0 # clear div
139- BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
140+#ifdef __arch64__
141+ BEALTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
142 # the first bit search.
143+#else
144+ BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
145+ # the first bit search.
146+#endif
147 ADDIK r29,r0,32 # Initialize the loop count
148 # First part try to find the first '1' in the r5
149 $LaDIV1:
150 ADD r5,r5,r5 # left shift logical r5
151- BGEID r5,$LaDIV1 #
152+#ifdef __arch64__
153+ BEAGEID r5,$LaDIV1 #
154+#else
155+ BGEID r5,$LaDIV1 #
156+#endif
157 ADDIK r29,r29,-1
158 $LaDIV2:
159 ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
160 ADDC r3,r3,r3 # Move that bit into the Mod register
161 rSUB r31,r6,r3 # Try to subtract (r30 a r6)
162+#ifdef __arch64__
163+ BEALTi r31,$LaMOD_TOO_SMALL
164+#else
165 BLTi r31,$LaMOD_TOO_SMALL
166+#endif
167 OR r3,r0,r31 # Move the r31 to mod since the result was positive
168 ADDIK r30,r30,1
169 $LaMOD_TOO_SMALL:
170 ADDIK r29,r29,-1
171+#ifdef __arch64__
172+ BEAEQi r29,$LaLOOP_END
173+ ADD r30,r30,r30 # Shift in the '1' into div
174+ BREAI $LaDIV2 # Div2
175+$LaLOOP_END:
176+ BEAGEI r28,$LaRETURN_HERE
177+ BREAId $LaRETURN_HERE
178+#else
179 BEQi r29,$LaLOOP_END
180 ADD r30,r30,r30 # Shift in the '1' into div
181 BRI $LaDIV2 # Div2
182 $LaLOOP_END:
183 BGEI r28,$LaRETURN_HERE
184 BRId $LaRETURN_HERE
185+#endif
186 rsubi r3,r3,0 # Negate the result
187 $LaDiv_By_Zero:
188 $LaResult_Is_Zero:
189@@ -108,7 +140,7 @@ $LaRETURN_HERE:
190 lli r29,r1,8
191 lli r30,r1,16
192 lli r31,r1,24
193- addik r1,r1,32
194+ addlik r1,r1,32
195 rtsd r15,8
196 nop
197 #else
198diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
199index 31a73c2..39951be 100644
200--- a/libgcc/config/microblaze/mulsi3.S
201+++ b/libgcc/config/microblaze/mulsi3.S
202@@ -43,7 +43,37 @@
203 .type __mulsi3,@function
204 #ifdef __arch64__
205 .align 3
206-#endif
207+__mulsi3:
208+ .frame r1,0,r15
209+ add r3,r0,r0
210+ BEAEQI r5,$L_Result_Is_Zero # Multiply by Zero
211+ BEAEQI r6,$L_Result_Is_Zero # Multiply by Zero
212+ BEAGEId r5,$L_R5_Pos
213+ XOR r4,r5,r6 # Get the sign of the result
214+ RSUBI r5,r5,0 # Make r5 positive
215+$L_R5_Pos:
216+ BEAGEI r6,$L_R6_Pos
217+ RSUBI r6,r6,0 # Make r6 positive
218+$L_R6_Pos:
219+ breai $L1
220+$L2:
221+ add r5,r5,r5
222+$L1:
223+ srl r6,r6
224+ addc r7,r0,r0
225+ beaeqi r7,$L2
226+ beaneid r6,$L2
227+ add r3,r3,r5
228+ bealti r4,$L_NegateResult
229+ rtsd r15,8
230+ nop
231+$L_NegateResult:
232+ rtsd r15,8
233+ rsub r3,r3,r0
234+$L_Result_Is_Zero:
235+ rtsd r15,8
236+ addi r3,r0,0
237+#else
238 __mulsi3:
239 .frame r1,0,r15
240 add r3,r0,r0
241@@ -74,5 +104,6 @@ $L_NegateResult:
242 $L_Result_Is_Zero:
243 rtsd r15,8
244 addi r3,r0,0
245+#endif
246 .end __mulsi3
247 .size __mulsi3, . - __mulsi3
248diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
249index 94adb6a..d4fe285 100644
250--- a/libgcc/config/microblaze/udivsi3.S
251+++ b/libgcc/config/microblaze/udivsi3.S
252@@ -59,52 +59,96 @@ __udivsi3:
253 SWI r30,r1,4
254 SWI r31,r1,8
255 #endif
256+#ifdef __arch64__
257+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
258+ BEAEQID r5,$LaResult_Is_Zero # Result is Zero
259+#else
260 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
261 BEQID r5,$LaResult_Is_Zero # Result is Zero
262+#endif
263 ADDIK r30,r0,0 # Clear mod
264 ADDIK r29,r0,32 # Initialize the loop count
265
266 # Check if r6 and r5 are equal # if yes, return 1
267 RSUB r18,r5,r6
268+#ifdef __arch64__
269+ BEAEQID r18,$LaRETURN_HERE
270+#else
271 BEQID r18,$LaRETURN_HERE
272+#endif
273 ADDIK r3,r0,1
274
275 # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
276 XOR r18,r5,r6
277- BGEID r18,16
278+#ifdef __arch64__
279+ BEAGEID r18,16
280+#else
281+ BGEID r18,16
282+#endif
283 ADD r3,r0,r0 # We would anyways clear r3
284+#ifdef __arch64__
285+ BEALTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater
286+ BREAI $LCheckr6
287+ RSUB r18,r6,r5 # MICROBLAZEcmp
288+ BEALTI r18,$LaRETURN_HERE
289+#else
290 BLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater
291 BRI $LCheckr6
292 RSUB r18,r6,r5 # MICROBLAZEcmp
293 BLTI r18,$LaRETURN_HERE
294-
295+#endif
296 # If r6 [bit 31] is set, then return result as 1
297 $LCheckr6:
298- BGTI r6,$LaDIV0
299- BRID $LaRETURN_HERE
300+#ifdef __arch64__
301+ BEAGTI r6,$LaDIV0
302+ BREAID $LaRETURN_HERE
303+#else
304+ BGTI r6,$LaDIV0
305+ BRID $LaRETURN_HERE
306+#endif
307 ADDIK r3,r0,1
308
309 # First part try to find the first '1' in the r5
310 $LaDIV0:
311+#ifdef __arch64__
312+ BEALTI r5,$LaDIV2
313+#else
314 BLTI r5,$LaDIV2
315+#endif
316 $LaDIV1:
317 ADD r5,r5,r5 # left shift logical r5
318+#ifdef __arch64__
319+ BEAGTID r5,$LaDIV1
320+#else
321 BGTID r5,$LaDIV1
322+#endif
323 ADDIK r29,r29,-1
324 $LaDIV2:
325 ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
326 ADDC r30,r30,r30 # Move that bit into the Mod register
327 RSUB r31,r6,r30 # Try to subtract (r30 a r6)
328+#ifdef __arch64__
329+ BEALTI r31,$LaMOD_TOO_SMALL
330+#else
331 BLTI r31,$LaMOD_TOO_SMALL
332+#endif
333 OR r30,r0,r31 # Move the r31 to mod since the result was positive
334 ADDIK r3,r3,1
335 $LaMOD_TOO_SMALL:
336 ADDIK r29,r29,-1
337+#ifdef __arch64__
338+ BEAEQi r29,$LaLOOP_END
339+ ADD r3,r3,r3 # Shift in the '1' into div
340+ BREAI $LaDIV2 # Div2
341+$LaLOOP_END:
342+ BREAI $LaRETURN_HERE
343+#else
344 BEQi r29,$LaLOOP_END
345 ADD r3,r3,r3 # Shift in the '1' into div
346 BRI $LaDIV2 # Div2
347 $LaLOOP_END:
348 BRI $LaRETURN_HERE
349+#endif
350 $LaDiv_By_Zero:
351 $LaResult_Is_Zero:
352 OR r3,r0,r0 # set result to 0
353@@ -115,7 +159,7 @@ $LaRETURN_HERE:
354 LLI r29,r1,0
355 LLI r30,r1,8
356 LLI r31,r1,16
357- ADDIK r1,r1,24
358+ ADDLIK r1,r1,24
359 RTSD r15,8
360 NOP
361 #else
362diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
363index 9bf65c3..3bd5d48 100644
364--- a/libgcc/config/microblaze/umodsi3.S
365+++ b/libgcc/config/microblaze/umodsi3.S
366@@ -46,7 +46,7 @@
367 __umodsi3:
368 .frame r1,0,r15
369
370- addik r1,r1,-24
371+ addlik r1,r1,-24
372 sli r29,r1,0
373 sli r30,r1,8
374 sli r31,r1,16
375@@ -59,27 +59,77 @@ __umodsi3:
376 swi r30,r1,4
377 swi r31,r1,8
378 #endif
379+#ifdef __arch64__
380+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
381+ BEAEQId r5,$LaResult_Is_Zero # Result is Zero
382+#else
383 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
384 BEQId r5,$LaResult_Is_Zero # Result is Zero
385+#endif
386 ADDIK r3,r0,0 # Clear div
387 ADDIK r30,r0,0 # clear mod
388 ADDIK r29,r0,32 # Initialize the loop count
389
390 # Check if r6 and r5 are equal # if yes, return 0
391 rsub r18,r5,r6
392- beqi r18,$LaRETURN_HERE
393
394+#ifdef __arch64__
395+ beaeqi r18,$LaRETURN_HERE
396+#else
397+ beqi r18,$LaRETURN_HERE
398+#endif
399 # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
400 xor r18,r5,r6
401+#ifdef __arch64__
402+ beageid r18,16
403+ addik r3,r5,0
404+ bealti r6,$LaRETURN_HERE
405+ breai $LCheckr6
406+ rsub r18,r5,r6 # MICROBLAZEcmp
407+ beagti r18,$LaRETURN_HERE
408+#else
409 bgeid r18,16
410 addik r3,r5,0
411 blti r6,$LaRETURN_HERE
412 bri $LCheckr6
413 rsub r18,r5,r6 # MICROBLAZEcmp
414 bgti r18,$LaRETURN_HERE
415-
416+#endif
417 # If r6 [bit 31] is set, then return result as r5-r6
418 $LCheckr6:
419+#ifdef __arch64__
420+ beagtid r6,$LaDIV0
421+ addik r3,r0,0
422+ addik r18,r0,0x7fffffff
423+ and r5,r5,r18
424+ and r6,r6,r18
425+ breaid $LaRETURN_HERE
426+ rsub r3,r6,r5
427+# First part: try to find the first '1' in the r5
428+$LaDIV0:
429+ BEALTI r5,$LaDIV2
430+$LaDIV1:
431+ ADD r5,r5,r5 # left shift logical r5
432+ BEAGEID r5,$LaDIV1 #
433+ ADDIK r29,r29,-1
434+$LaDIV2:
435+ ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
436+ ADDC r3,r3,r3 # Move that bit into the Mod register
437+ rSUB r31,r6,r3 # Try to subtract (r3 a r6)
438+ BEALTi r31,$LaMOD_TOO_SMALL
439+ OR r3,r0,r31 # Move the r31 to mod since the result was positive
440+ ADDIK r30,r30,1
441+$LaMOD_TOO_SMALL:
442+ ADDIK r29,r29,-1
443+ BEAEQi r29,$LaLOOP_END
444+ ADD r30,r30,r30 # Shift in the '1' into div
445+ BREAI $LaDIV2 # Div2
446+$LaLOOP_END:
447+ BREAI $LaRETURN_HERE
448+$LaDiv_By_Zero:
449+$LaResult_Is_Zero:
450+ or r3,r0,r0 # set result to 0
451+#else
452 bgtid r6,$LaDIV0
453 addik r3,r0,0
454 addik r18,r0,0x7fffffff
455@@ -111,7 +161,7 @@ $LaLOOP_END:
456 $LaDiv_By_Zero:
457 $LaResult_Is_Zero:
458 or r3,r0,r0 # set result to 0
459-
460+#endif
461 #ifdef __arch64__
462 $LaRETURN_HERE:
463 # Restore values of CSRs and that of r3 and the divisor and the dividend
464--
4652.7.4
466
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Author-Nagaraju-nmekala-xilinx.com.patch
new file mode 100644
index 00000000..690bc727
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Author-Nagaraju-nmekala-xilinx.com.patch
@@ -0,0 +1,479 @@
1From e1b8cfe6c0b4a0bd90ecbd3e85ae7114df21b6cc Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Thu, 18 Apr 2019 16:00:37 +0530
4Subject: [PATCH 61/62] Author: Nagaraju <nmekala@xilinx.com> Date: Wed Apr
5 17 14:11:00 2019 +0530
6
7 [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default
8 By default MB-64 is generatting barrel-shift instructions. It has been
9 removed from default. Barrel-shift instructions will be generated only if
10 barrel-shifter is enabled. Similarly to double instructions as well.
11
12 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
13---
14 gcc/config/microblaze/microblaze.c | 2 +-
15 gcc/config/microblaze/microblaze.md | 269 +++++++++++++++++++++++++++++++++---
16 2 files changed, 252 insertions(+), 19 deletions(-)
17
18diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
19index 33d183e..c321b03 100644
20--- a/gcc/config/microblaze/microblaze.c
21+++ b/gcc/config/microblaze/microblaze.c
22@@ -3868,7 +3868,7 @@ microblaze_expand_divide (rtx operands[])
23 emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
24
25 if (TARGET_MB_64) {
26- emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
27+ emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4)));
28 emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
29 }
30 else {
31diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
32index 8bd175f..b5b60fb 100644
33--- a/gcc/config/microblaze/microblaze.md
34+++ b/gcc/config/microblaze/microblaze.md
35@@ -545,7 +545,7 @@
36 [(set (match_operand:DF 0 "register_operand" "=d")
37 (plus:DF (match_operand:DF 1 "register_operand" "d")
38 (match_operand:DF 2 "register_operand" "d")))]
39- "TARGET_MB_64"
40+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
41 "dadd\t%0,%1,%2"
42 [(set_attr "type" "fadd")
43 (set_attr "mode" "DF")
44@@ -555,7 +555,7 @@
45 [(set (match_operand:DF 0 "register_operand" "=d")
46 (minus:DF (match_operand:DF 1 "register_operand" "d")
47 (match_operand:DF 2 "register_operand" "d")))]
48- "TARGET_MB_64"
49+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
50 "drsub\t%0,%2,%1"
51 [(set_attr "type" "frsub")
52 (set_attr "mode" "DF")
53@@ -565,7 +565,7 @@
54 [(set (match_operand:DF 0 "register_operand" "=d")
55 (mult:DF (match_operand:DF 1 "register_operand" "d")
56 (match_operand:DF 2 "register_operand" "d")))]
57- "TARGET_MB_64"
58+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
59 "dmul\t%0,%1,%2"
60 [(set_attr "type" "fmul")
61 (set_attr "mode" "DF")
62@@ -575,7 +575,7 @@
63 [(set (match_operand:DF 0 "register_operand" "=d")
64 (div:DF (match_operand:DF 1 "register_operand" "d")
65 (match_operand:DF 2 "register_operand" "d")))]
66- "TARGET_MB_64"
67+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
68 "ddiv\t%0,%2,%1"
69 [(set_attr "type" "fdiv")
70 (set_attr "mode" "DF")
71@@ -585,7 +585,7 @@
72 (define_insn "sqrtdf2"
73 [(set (match_operand:DF 0 "register_operand" "=d")
74 (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
75- "TARGET_MB_64"
76+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
77 "dsqrt\t%0,%1"
78 [(set_attr "type" "fsqrt")
79 (set_attr "mode" "DF")
80@@ -594,7 +594,7 @@
81 (define_insn "floatdidf2"
82 [(set (match_operand:DF 0 "register_operand" "=d")
83 (float:DF (match_operand:DI 1 "register_operand" "d")))]
84- "TARGET_MB_64"
85+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
86 "dbl\t%0,%1"
87 [(set_attr "type" "fcvt")
88 (set_attr "mode" "DF")
89@@ -603,7 +603,7 @@
90 (define_insn "fix_truncdfdi2"
91 [(set (match_operand:DI 0 "register_operand" "=d")
92 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
93- "TARGET_MB_64"
94+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
95 "dlong\t%0,%1"
96 [(set_attr "type" "fcvt")
97 (set_attr "mode" "DI")
98@@ -1299,6 +1299,34 @@
99 (set_attr "mode" "DI")
100 (set_attr "length" "4")])
101
102+(define_insn "*movdi_internal2_bshift"
103+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m")
104+ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))]
105+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
106+ {
107+ switch (which_alternative)
108+ {
109+ case 0:
110+ return "addlk\t%0,%1,r0";
111+ case 1:
112+ case 2:
113+ if (GET_CODE (operands[1]) == CONST_INT &&
114+ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
115+ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
116+ else
117+ return "addlik\t%0,r0,%1";
118+ case 3:
119+ case 4:
120+ return "ll%i1\t%0,%1";
121+ case 5:
122+ case 6:
123+ return "sl%i0\t%z1,%0";
124+ }
125+ }
126+ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
127+ (set_attr "mode" "DI")
128+ (set_attr "length" "4,4,12,4,8,4,8")])
129+
130 (define_insn "*movdi_internal2"
131 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m")
132 (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))]
133@@ -1312,7 +1340,15 @@
134 case 2:
135 if (GET_CODE (operands[1]) == CONST_INT &&
136 (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
137- return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
138+ {
139+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
140+ output_asm_insn ("addlik\t%0,r0,%h1", operands);
141+ output_asm_insn ("addlik\t%2,r0,32", operands);
142+ output_asm_insn ("addlik\t%2,%2,-1", operands);
143+ output_asm_insn ("beaneid\t%2,.-8", operands);
144+ output_asm_insn ("addlk\t%0,%0,%0", operands);
145+ return "addlik\t%0,%0,%j1 #li => la";
146+ }
147 else
148 return "addlik\t%0,r0,%1";
149 case 3:
150@@ -1386,7 +1422,7 @@
151 (define_insn "movdi_long_int"
152 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
153 (match_operand:DI 1 "general_operand" "i"))]
154- "TARGET_MB_64"
155+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
156 "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
157 [(set_attr "type" "no_delay_arith")
158 (set_attr "mode" "DI")
159@@ -1653,6 +1689,33 @@
160 ;; movdf_internal
161 ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
162 ;;
163+(define_insn "*movdf_internal_64_bshift"
164+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
165+ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
166+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
167+ {
168+ switch (which_alternative)
169+ {
170+ case 0:
171+ return "addlk\t%0,%1,r0";
172+ case 1:
173+ return "addlk\t%0,r0,r0";
174+ case 2:
175+ case 4:
176+ return "ll%i1\t%0,%1";
177+ case 3:
178+ {
179+ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
180+ }
181+ case 5:
182+ return "sl%i0\t%1,%0";
183+ }
184+ gcc_unreachable ();
185+ }
186+ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
187+ (set_attr "mode" "DF")
188+ (set_attr "length" "4,4,4,16,4,4")])
189+
190 (define_insn "*movdf_internal_64"
191 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
192 (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
193@@ -1669,7 +1732,13 @@
194 return "ll%i1\t%0,%1";
195 case 3:
196 {
197- return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
198+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
199+ output_asm_insn ("addlik\t%0,r0,%h1", operands);
200+ output_asm_insn ("addlik\t%2,r0,32", operands);
201+ output_asm_insn ("addlik\t%2,%2,-1", operands);
202+ output_asm_insn ("beaneid\t%2,.-8", operands);
203+ output_asm_insn ("addlk\t%0,%0,%0", operands);
204+ return "addlik\t%0,%0,%j1 #li => la";
205 }
206 case 5:
207 return "sl%i0\t%1,%0";
208@@ -1789,11 +1858,21 @@
209 "TARGET_MB_64"
210 {
211 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
212-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
213+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
214 {
215 emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
216 DONE;
217 }
218+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
219+ {
220+ emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2]));
221+ DONE;
222+ }
223+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
224+ {
225+ emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2]));
226+ DONE;
227+ }
228 else
229 FAIL;
230 }
231@@ -1803,7 +1882,7 @@ else
232 [(set (match_operand:DI 0 "register_operand" "=d,d")
233 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
234 (match_operand:DI 2 "arith_operand" "I,d")))]
235- "TARGET_MB_64"
236+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
237 "@
238 bsllli\t%0,%1,%2
239 bslll\t%0,%1,%2"
240@@ -1811,6 +1890,51 @@ else
241 (set_attr "mode" "DI,DI")
242 (set_attr "length" "4,4")]
243 )
244+
245+(define_insn "ashldi3_const"
246+ [(set (match_operand:DI 0 "register_operand" "=&d")
247+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
248+ (match_operand:DI 2 "immediate_operand" "I")))]
249+ "TARGET_MB_64"
250+ {
251+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
252+
253+ output_asm_insn ("orli\t%3,r0,%2", operands);
254+ if (REGNO (operands[0]) != REGNO (operands[1]))
255+ output_asm_insn ("addlk\t%0,%1,r0", operands);
256+
257+ output_asm_insn ("addlik\t%3,%3,-1", operands);
258+ output_asm_insn ("beaneid\t%3,.-8", operands);
259+ return "addlk\t%0,%0,%0";
260+ }
261+ [(set_attr "type" "multi")
262+ (set_attr "mode" "DI")
263+ (set_attr "length" "20")]
264+)
265+
266+(define_insn "ashldi3_reg"
267+ [(set (match_operand:DI 0 "register_operand" "=&d")
268+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
269+ (match_operand:DI 2 "register_operand" "d")))]
270+ "TARGET_MB_64"
271+ {
272+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
273+ output_asm_insn ("andli\t%3,%2,31", operands);
274+ if (REGNO (operands[0]) != REGNO (operands[1]))
275+ output_asm_insn ("addlk\t%0,r0,%1", operands);
276+ /* Exit the loop if zero shift. */
277+ output_asm_insn ("beaeqid\t%3,.+24", operands);
278+ /* Emit the loop. */
279+ output_asm_insn ("addlk\t%0,%0,r0", operands);
280+ output_asm_insn ("addlik\t%3,%3,-1", operands);
281+ output_asm_insn ("beaneid\t%3,.-8", operands);
282+ return "addlk\t%0,%0,%0";
283+ }
284+ [(set_attr "type" "multi")
285+ (set_attr "mode" "DI")
286+ (set_attr "length" "28")]
287+)
288+
289 ;; The following patterns apply when there is no barrel shifter present
290
291 (define_insn "*ashlsi3_with_mul_delay"
292@@ -1944,11 +2068,21 @@ else
293 "TARGET_MB_64"
294 {
295 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
296-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
297+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
298 {
299 emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
300 DONE;
301 }
302+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
303+ {
304+ emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2]));
305+ DONE;
306+ }
307+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
308+ {
309+ emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2]));
310+ DONE;
311+ }
312 else
313 FAIL;
314 }
315@@ -1958,7 +2092,7 @@ else
316 [(set (match_operand:DI 0 "register_operand" "=d,d")
317 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
318 (match_operand:DI 2 "arith_operand" "I,d")))]
319- "TARGET_MB_64"
320+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
321 "@
322 bslrai\t%0,%1,%2
323 bslra\t%0,%1,%2"
324@@ -1966,6 +2100,51 @@ else
325 (set_attr "mode" "DI,DI")
326 (set_attr "length" "4,4")]
327 )
328+
329+(define_insn "ashrdi3_const"
330+ [(set (match_operand:DI 0 "register_operand" "=&d")
331+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
332+ (match_operand:DI 2 "immediate_operand" "I")))]
333+ "TARGET_MB_64"
334+ {
335+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
336+
337+ output_asm_insn ("orli\t%3,r0,%2", operands);
338+ if (REGNO (operands[0]) != REGNO (operands[1]))
339+ output_asm_insn ("addlk\t%0,%1,r0", operands);
340+
341+ output_asm_insn ("addlik\t%3,%3,-1", operands);
342+ output_asm_insn ("beaneid\t%3,.-8", operands);
343+ return "srla\t%0,%0";
344+ }
345+ [(set_attr "type" "arith")
346+ (set_attr "mode" "DI")
347+ (set_attr "length" "20")]
348+)
349+
350+(define_insn "ashrdi3_reg"
351+ [(set (match_operand:DI 0 "register_operand" "=&d")
352+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
353+ (match_operand:DI 2 "register_operand" "d")))]
354+ "TARGET_MB_64"
355+ {
356+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
357+ output_asm_insn ("andli\t%3,%2,31", operands);
358+ if (REGNO (operands[0]) != REGNO (operands[1]))
359+ output_asm_insn ("addlk\t%0,r0,%1", operands);
360+ /* Exit the loop if zero shift. */
361+ output_asm_insn ("beaeqid\t%3,.+24", operands);
362+ /* Emit the loop. */
363+ output_asm_insn ("addlk\t%0,%0,r0", operands);
364+ output_asm_insn ("addlik\t%3,%3,-1", operands);
365+ output_asm_insn ("beaneid\t%3,.-8", operands);
366+ return "srla\t%0,%0";
367+ }
368+ [(set_attr "type" "multi")
369+ (set_attr "mode" "DI")
370+ (set_attr "length" "28")]
371+)
372+
373 (define_expand "ashrsi3"
374 [(set (match_operand:SI 0 "register_operand" "=&d")
375 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
376@@ -2083,11 +2262,21 @@ else
377 "TARGET_MB_64"
378 {
379 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
380-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
381+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
382 {
383 emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
384 DONE;
385 }
386+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
387+ {
388+ emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2]));
389+ DONE;
390+ }
391+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
392+ {
393+ emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2]));
394+ DONE;
395+ }
396 else
397 FAIL;
398 }
399@@ -2097,7 +2286,7 @@ else
400 [(set (match_operand:DI 0 "register_operand" "=d,d")
401 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
402 (match_operand:DI 2 "arith_operand" "I,d")))]
403- "TARGET_MB_64"
404+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
405 "@
406 bslrli\t%0,%1,%2
407 bslrl\t%0,%1,%2"
408@@ -2106,6 +2295,50 @@ else
409 (set_attr "length" "4,4")]
410 )
411
412+(define_insn "lshrdi3_const"
413+ [(set (match_operand:DI 0 "register_operand" "=&d")
414+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
415+ (match_operand:DI 2 "immediate_operand" "I")))]
416+ "TARGET_MB_64"
417+ {
418+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
419+
420+ output_asm_insn ("orli\t%3,r0,%2", operands);
421+ if (REGNO (operands[0]) != REGNO (operands[1]))
422+ output_asm_insn ("addlk\t%0,%1,r0", operands);
423+
424+ output_asm_insn ("addlik\t%3,%3,-1", operands);
425+ output_asm_insn ("beaneid\t%3,.-8", operands);
426+ return "srll\t%0,%0";
427+ }
428+ [(set_attr "type" "multi")
429+ (set_attr "mode" "DI")
430+ (set_attr "length" "20")]
431+)
432+
433+(define_insn "lshrdi3_reg"
434+ [(set (match_operand:DI 0 "register_operand" "=&d")
435+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
436+ (match_operand:DI 2 "register_operand" "d")))]
437+ "TARGET_MB_64"
438+ {
439+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
440+ output_asm_insn ("andli\t%3,%2,31", operands);
441+ if (REGNO (operands[0]) != REGNO (operands[1]))
442+ output_asm_insn ("addlk\t%0,r0,%1", operands);
443+ /* Exit the loop if zero shift. */
444+ output_asm_insn ("beaeqid\t%3,.+24", operands);
445+ /* Emit the loop. */
446+ output_asm_insn ("addlk\t%0,%0,r0", operands);
447+ output_asm_insn ("addlik\t%3,%3,-1", operands);
448+ output_asm_insn ("beaneid\t%3,.-8", operands);
449+ return "srll\t%0,%0";
450+ }
451+ [(set_attr "type" "multi")
452+ (set_attr "mode" "SI")
453+ (set_attr "length" "28")]
454+)
455+
456 (define_expand "lshrsi3"
457 [(set (match_operand:SI 0 "register_operand" "=&d")
458 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
459@@ -2233,7 +2466,7 @@ else
460 (eq:DI
461 (match_operand:DI 1 "register_operand" "d")
462 (match_operand:DI 2 "register_operand" "d")))]
463- "TARGET_MB_64"
464+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
465 "pcmpleq\t%0,%1,%2"
466 [(set_attr "type" "arith")
467 (set_attr "mode" "DI")
468@@ -2245,7 +2478,7 @@ else
469 (ne:DI
470 (match_operand:DI 1 "register_operand" "d")
471 (match_operand:DI 2 "register_operand" "d")))]
472- "TARGET_MB_64"
473+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
474 "pcmplne\t%0,%1,%2"
475 [(set_attr "type" "arith")
476 (set_attr "mode" "DI")
477--
4782.7.4
479
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
new file mode 100644
index 00000000..d3ed669c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
@@ -0,0 +1,41 @@
1From 11766e4f7aaad3f217944079335c71525b72201c Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Wed, 8 May 2019 14:12:03 +0530
4Subject: [PATCH 61/63] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and
5 disable fivopts by default
6
7Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default.
8
9 * gcc/common/config/microblaze/microblaze-common.c
10 (microblaze_option_optimization_table): Disable fivopts by default.
11
12Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
13---
14 gcc/common/config/microblaze/microblaze-common.c | 6 ++++--
15 1 file changed, 4 insertions(+), 2 deletions(-)
16
17diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
18index 9b6ef21..3cae2a6 100644
19--- a/gcc/common/config/microblaze/microblaze-common.c
20+++ b/gcc/common/config/microblaze/microblaze-common.c
21@@ -27,13 +27,15 @@
22 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
23 static const struct default_options microblaze_option_optimization_table[] =
24 {
25- /* Turn off ivopts by default. It messes up cse. */
26+ /* Turn off ivopts by default. It messes up cse.
27+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */
28 { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
29- { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
30 { OPT_LEVELS_NONE, 0, NULL, 0 }
31 };
32
33 #undef TARGET_DEFAULT_TARGET_FLAGS
34 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
35
36+#undef TARGET_OPTION_OPTIMIZATION_TABLE
37+#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table
38 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
39--
402.7.4
41
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch
new file mode 100644
index 00000000..ca1a2b9f
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch
@@ -0,0 +1,107 @@
1From bb65903ab6293a47d154764a585f6c53b5fcf853 Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Fri, 23 Aug 2019 16:16:53 +0530
4Subject: [PATCH 62/63] Added new MB-64 single register arithmetic instructions
5
6---
7 gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++++++++++
8 1 file changed, 56 insertions(+)
9
10diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
11index 3e7c647..4d40cc5 100644
12--- a/gcc/config/microblaze/microblaze.md
13+++ b/gcc/config/microblaze/microblaze.md
14@@ -654,6 +654,18 @@
15 }
16 })
17
18+(define_insn "adddi3_int"
19+ [(set (match_operand:DI 0 "register_operand" "=d")
20+ (plus:DI (match_operand:DI 1 "register_operand" "%0")
21+ (match_operand:DI 2 "immediate_operand" "I")))]
22+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
23+ "@
24+ addlik\t%0,%2"
25+ [(set_attr "type" "darith")
26+ (set_attr "mode" "DI")
27+ (set_attr "length" "4")]
28+)
29+
30 (define_insn "*adddi3_long"
31 [(set (match_operand:DI 0 "register_operand" "=d,d")
32 (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
33@@ -719,6 +731,18 @@
34 {
35 }")
36
37+(define_insn "subdi316imm"
38+ [(set (match_operand:DI 0 "register_operand" "=d")
39+ (minus:DI (match_operand:DI 1 "register_operand" "d")
40+ (match_operand:DI 2 "arith_operand" "K")))]
41+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767) && (REGNO (operands[0]) == REGNO (operands[1]))"
42+ "@
43+ addlik\t%0,-%2"
44+ [(set_attr "type" "darith")
45+ (set_attr "mode" "DI")
46+ (set_attr "length" "4")])
47+
48+
49 (define_insn "subsidi3"
50 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
51 (minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
52@@ -1015,6 +1039,17 @@
53 ;; Logical
54 ;;----------------------------------------------------------------
55
56+(define_insn "anddi3imm16"
57+ [(set (match_operand:DI 0 "register_operand" "=d")
58+ (and:DI (match_operand:DI 1 "arith_operand" "%0")
59+ (match_operand:DI 2 "arith_operand" "K")))]
60+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
61+ "@
62+ andli\t%0,%2"
63+ [(set_attr "type" "darith")
64+ (set_attr "mode" "DI")
65+ (set_attr "length" "4")])
66+
67 (define_insn "anddi3"
68 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
69 (and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
70@@ -1042,6 +1077,16 @@
71 (set_attr "mode" "SI,SI,SI,SI")
72 (set_attr "length" "4,8,8,8")])
73
74+(define_insn "iordi3imm16"
75+ [(set (match_operand:DI 0 "register_operand" "=d")
76+ (ior:DI (match_operand:DI 1 "arith_operand" "%0")
77+ (match_operand:DI 2 "arith_operand" "K")))]
78+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
79+ "@
80+ orli\t%0,%2"
81+ [(set_attr "type" "darith")
82+ (set_attr "mode" "DI")
83+ (set_attr "length" "4")])
84
85 (define_insn "iordi3"
86 [(set (match_operand:DI 0 "register_operand" "=d,d")
87@@ -1069,6 +1114,17 @@
88 (set_attr "mode" "SI,SI,SI,SI")
89 (set_attr "length" "4,8,8,8")])
90
91+(define_insn "xordi3imm16"
92+ [(set (match_operand:DI 0 "register_operand" "=d")
93+ (xor:DI (match_operand:DI 1 "arith_operand" "%0")
94+ (match_operand:DI 2 "arith_operand" "K")))]
95+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
96+ "@
97+ xorli\t%0,%2"
98+ [(set_attr "type" "darith")
99+ (set_attr "mode" "DI")
100+ (set_attr "length" "4")])
101+
102 (define_insn "xordi3"
103 [(set (match_operand:DI 0 "register_operand" "=d,d")
104 (xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
105--
1062.7.4
107
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
new file mode 100644
index 00000000..e7dfa89c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
@@ -0,0 +1,41 @@
1From 612e6579116e6714417ea21e6c13b0968bb6aac2 Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Wed, 8 May 2019 14:12:03 +0530
4Subject: [PATCH 62/62] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and
5 disable fivopts by default
6
7Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default.
8
9 * gcc/common/config/microblaze/microblaze-common.c
10 (microblaze_option_optimization_table): Disable fivopts by default.
11
12Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
13---
14 gcc/common/config/microblaze/microblaze-common.c | 6 ++++--
15 1 file changed, 4 insertions(+), 2 deletions(-)
16
17diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
18index fe45f2e..2873d4b 100644
19--- a/gcc/common/config/microblaze/microblaze-common.c
20+++ b/gcc/common/config/microblaze/microblaze-common.c
21@@ -27,13 +27,15 @@
22 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
23 static const struct default_options microblaze_option_optimization_table[] =
24 {
25- /* Turn off ivopts by default. It messes up cse. */
26+ /* Turn off ivopts by default. It messes up cse.
27+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */
28 { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
29- { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
30 { OPT_LEVELS_NONE, 0, NULL, 0 }
31 };
32
33 #undef TARGET_DEFAULT_TARGET_FLAGS
34 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
35
36+#undef TARGET_OPTION_OPTIMIZATION_TABLE
37+#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table
38 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
39--
402.7.4
41
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
new file mode 100644
index 00000000..edf6a0f3
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
@@ -0,0 +1,44 @@
1From d4b23a1dd0564bcf67b5b88a68d62eb49bdab15d Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Mon, 26 Aug 2019 15:55:22 +0530
4Subject: [PATCH 63/63] [Patch,MicroBlaze] : Added support for 64 bit Immediate
5 values.
6
7---
8 gcc/config/microblaze/constraints.md | 4 ++--
9 gcc/config/microblaze/microblaze.md | 3 +--
10 2 files changed, 3 insertions(+), 4 deletions(-)
11
12diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
13index 9a5aa6b..e87a90f 100644
14--- a/gcc/config/microblaze/constraints.md
15+++ b/gcc/config/microblaze/constraints.md
16@@ -53,9 +53,9 @@
17 (match_test "ival > 0 && ival < 0x10000")))
18
19 (define_constraint "K"
20- "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)."
21+ "A constant in the range -9223372036854775808 to 9223372036854775807 (inclusive)."
22 (and (match_code "const_int")
23- (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
24+ (match_test "ival > (long long)-9223372036854775808 && ival < (long long)9223372036854775807")))
25
26 ;; Define floating point constraints
27
28diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
29index 4d40cc5..6e74503 100644
30--- a/gcc/config/microblaze/microblaze.md
31+++ b/gcc/config/microblaze/microblaze.md
32@@ -1334,8 +1334,7 @@
33 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
34 (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
35 "TARGET_MB_64 && (register_operand (operands[0], DImode) &&
36- (GET_CODE (operands[1]) == CONST_INT &&
37- (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))"
38+ (GET_CODE (operands[1]) == CONST_INT))"
39 "@
40 addlk\t%0,r0,r0\t
41 addlik\t%0,r0,%1\t #N1 %X1
42--
432.7.4
44
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0064-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0064-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
new file mode 100644
index 00000000..41c90353
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0064-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
@@ -0,0 +1,77 @@
1From 5f54efe1e7d9604b45ddddd510ce439477d0e94f Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Thu, 9 Jan 2020 12:30:41 +0530
4Subject: [PATCH] [Patch, microblaze]: Fix Compiler crash with
5 -freg-struct-return This patch fixes a bug in MB GCC regarding the passing
6 struct values in registers. Currently we are only handling SImode With this
7 patch all other modes are handled properly
8
9Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
10
11---
12 gcc/config/microblaze/microblaze.c | 11 ++++++++++-
13 gcc/config/microblaze/microblaze.h | 19 -------------------
14 2 files changed, 10 insertions(+), 20 deletions(-)
15
16diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
17index 5c09452..beccd12 100644
18--- a/gcc/config/microblaze/microblaze.c
19+++ b/gcc/config/microblaze/microblaze.c
20@@ -4046,7 +4046,16 @@ microblaze_function_value (const_tree valtype,
21 const_tree func ATTRIBUTE_UNUSED,
22 bool outgoing ATTRIBUTE_UNUSED)
23 {
24- return LIBCALL_VALUE (TYPE_MODE (valtype));
25+ return gen_rtx_REG (TYPE_MODE (valtype), GP_RETURN);
26+}
27+
28+#undef TARGET_LIBCALL_VALUE
29+#define TARGET_LIBCALL_VALUE microblaze_libcall_value
30+
31+rtx
32+microblaze_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
33+{
34+ return gen_rtx_REG (mode, GP_RETURN);
35 }
36
37 /* Implement TARGET_SCHED_ADJUST_COST. */
38diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
39index ab541f7..100e7b2 100644
40--- a/gcc/config/microblaze/microblaze.h
41+++ b/gcc/config/microblaze/microblaze.h
42@@ -266,13 +266,6 @@ extern enum pipeline_type microblaze_pipe;
43
44 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
45
46-#ifndef __arch64__
47-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
48- if (GET_MODE_CLASS (MODE) == MODE_INT \
49- && GET_MODE_SIZE (MODE) < 4) \
50- (MODE) = SImode;
51-#endif
52-
53 /* Standard register usage. */
54
55 /* On the MicroBlaze, we have 32 integer registers */
56@@ -471,18 +464,6 @@ extern struct microblaze_frame_info current_frame_info;
57
58 #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
59
60-#ifdef __aarch64__
61-#define LIBCALL_VALUE(MODE) \
62- gen_rtx_REG (MODE,GP_RETURN)
63-#else
64-#define LIBCALL_VALUE(MODE) \
65- gen_rtx_REG ( \
66- ((GET_MODE_CLASS (MODE) != MODE_INT \
67- || GET_MODE_SIZE (MODE) >= 4) \
68- ? (MODE) \
69- : SImode), GP_RETURN)
70-#endif
71-
72 /* 1 if N is a possible register number for a function value.
73 On the MicroBlaze, R2 R3 are the only register thus used.
74 Currently, R2 are only implemented here (C has no complex type) */
75--
761.8.3.1
77
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-15 16:47:55 +0000