summaryrefslogtreecommitdiffstats
path: root/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb
diff options
context:
space:
mode:
authorRaju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com>2021-01-05 20:20:17 +0530
committerSai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>2021-07-14 14:32:21 -0700
commitab8a21322538c77b6f66770102a8e97262458f9a (patch)
tree2ae60fadc1d3e5857176829eb71d246cf69b5aa6 /meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb
parent0696df5ad0fd19faafe5e0f52715e6a0bff30d2b (diff)
downloadmeta-xilinx-ab8a21322538c77b6f66770102a8e97262458f9a.tar.gz
u-boot-zynq-scr: Add microblaze support for boot.scr
Adding microblaze support for boot.scr and moving the generic boot script from petalinux to yocto layers. The generic boot script will read the boot_target variable on uboot and based on the bootmode it will execute the boot commands. Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com> Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
Diffstat (limited to 'meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb')
-rw-r--r--meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb17
1 files changed, 7 insertions, 10 deletions
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb
index 0e91ae79..aecc36df 100644
--- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb
+++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb
@@ -33,7 +33,6 @@ SKIP_APPEND_BASEADDR ?= "0"
33 33
34DDR_BASEADDR ?= "0x0" 34DDR_BASEADDR ?= "0x0"
35DDR_BASEADDR_microblaze ?= "0x80000000" 35DDR_BASEADDR_microblaze ?= "0x80000000"
36PRE_BOOTENV ?= ""
37 36
38SRC_URI = " \ 37SRC_URI = " \
39 file://boot.cmd.sd.zynq \ 38 file://boot.cmd.sd.zynq \
@@ -102,16 +101,16 @@ NAND_RAMDISK_SIZE ?= "0x3200000"
102## For zynqMP 101## For zynqMP
103## Load boot.scr at 0x3E80000 -> 62MB of QSPI/NAND Memory 102## Load boot.scr at 0x3E80000 -> 62MB of QSPI/NAND Memory
104QSPI_KERNEL_OFFSET ?= "0xF00000" 103QSPI_KERNEL_OFFSET ?= "0xF00000"
105QSPI_KERNEL_OFFSET_zynqmp-dr ?= "0x3F00000" 104QSPI_KERNEL_OFFSET_zynqmpdr ?= "0x3F00000"
106QSPI_RAMDISK_OFFSET ?= "0x4000000" 105QSPI_RAMDISK_OFFSET ?= "0x4000000"
107QSPI_RAMDISK_OFFSET_zynqmp-dr ?= "0x5D00000" 106QSPI_RAMDISK_OFFSET_zynqmpdr ?= "0x5D00000"
108 107
109NAND_KERNEL_OFFSET_zynqmp ?= "0x4100000" 108NAND_KERNEL_OFFSET_zynqmp ?= "0x4100000"
110NAND_RAMDISK_OFFSET_zynqmp ?= "0x7800000" 109NAND_RAMDISK_OFFSET_zynqmp ?= "0x7800000"
111 110
112QSPI_KERNEL_SIZE_zynqmp ?= "0x1D00000" 111QSPI_KERNEL_SIZE_zynqmp ?= "0x1D00000"
113QSPI_RAMDISK_SIZE ?= "0x4000000" 112QSPI_RAMDISK_SIZE ?= "0x4000000"
114QSPI_RAMDISK_SIZE_zynqmp-dr ?= "0x1D00000" 113QSPI_RAMDISK_SIZE_zynqmpdr ?= "0x1D00000"
115 114
116## For versal 115## For versal
117## Load boot.scr at 0x7F80000 -> 127MB of QSPI/NAND Memory 116## Load boot.scr at 0x7F80000 -> 127MB of QSPI/NAND Memory
@@ -131,15 +130,13 @@ QSPI_KERNEL_IMAGE_versal ?= "image.ub"
131 130
132NAND_KERNEL_IMAGE ?= "image.ub" 131NAND_KERNEL_IMAGE ?= "image.ub"
133 132
134QSPI_FIT_IMAGE_LOAD_ADDRESS ?= "${@append_baseaddr(d,d.getVar('QSPI_FIT_IMAGE_OFFSET'))}" 133QSPI_FIT_IMAGE_LOAD_ADDRESS ?= "${@append_baseaddr(d,"0x10000000")}"
135QSPI_FIT_IMAGE_OFFSET ?= "0x10000000"
136QSPI_FIT_IMAGE_SIZE ?= "0x6400000" 134QSPI_FIT_IMAGE_SIZE ?= "0x6400000"
137QSPI_FIT_IMAGE_SIZE_zynqmp-dr ?= "0x3F00000" 135QSPI_FIT_IMAGE_SIZE_zynqmpdr ?= "0x3F00000"
138QSPI_FIT_IMAGE_SIZE_zynq ?= "0xF00000" 136QSPI_FIT_IMAGE_SIZE_zynq ?= "0xF00000"
139QSPI_FIT_IMAGE_SIZE_microblaze ?= "0xF00000" 137QSPI_FIT_IMAGE_SIZE_microblaze ?= "0xF00000"
140 138
141NAND_FIT_IMAGE_LOAD_ADDRESS ?= "${@append_baseaddr(d,d.getVar('NAND_FIT_IMAGE_OFFSET'))}" 139NAND_FIT_IMAGE_LOAD_ADDRESS ?= "${@append_baseaddr(d,"0x10000000")}"
142NAND_FIT_IMAGE_OFFSET ?= "0x10000000"
143NAND_FIT_IMAGE_SIZE ?= "0x6400000" 140NAND_FIT_IMAGE_SIZE ?= "0x6400000"
144 141
145SDBOOTDEV ?= "0" 142SDBOOTDEV ?= "0"
@@ -152,7 +149,7 @@ do_install[noexec] = "1"
152python () { 149python () {
153 baseaddr = d.getVar('DDR_BASEADDR') or "0x0" 150 baseaddr = d.getVar('DDR_BASEADDR') or "0x0"
154 if baseaddr == "0x0": 151 if baseaddr == "0x0":
155 d.appendVar('PRE_BOOTENV','') 152 d.setVar('PRE_BOOTENV','')
156 else: 153 else:
157 soc_family = d.getVar('SOC_FAMILY') or "" 154 soc_family = d.getVar('SOC_FAMILY') or ""
158 if soc_family == "zynqmp": 155 if soc_family == "zynqmp":