summaryrefslogtreecommitdiffstats
path: root/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch
diff options
context:
space:
mode:
authorMark Hatle <mark.hatle@kernel.crashing.org>2020-08-13 15:25:54 -0500
committerMark Hatle <mark.hatle@kernel.crashing.org>2020-08-14 11:56:34 -0500
commit276f2a014483170cfbcbf391c6350426e0a19fdc (patch)
treeb68a8b36c7d5df81fa6adff396e1f255715dc0b2 /meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch
parent559d46390c65d34c14b56a7f8690b1ac705430ac (diff)
downloadmeta-xilinx-276f2a014483170cfbcbf391c6350426e0a19fdc.tar.gz
meta-microblaze: toolchains
Resync the microblaze toolchain items to match the latest YP master version. binutils and gdb are based on the same patch set, but the release version are based on slightly different sources, thus the patches are a bit different. Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
Diffstat (limited to 'meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch')
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch844
1 files changed, 844 insertions, 0 deletions
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch
new file mode 100644
index 00000000..acf14b23
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch
@@ -0,0 +1,844 @@
1From 9600049313b095d6d7d8ea46a7ab783fabae71a2 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Tue, 3 Apr 2018 16:48:39 +0530
4Subject: [PATCH 34/58] Intial commit of 64-bit Microblaze
5
6Added load store pattern movdi and also adding missing files
7---
8 gcc/config/microblaze/constraints.md | 5 +
9 gcc/config/microblaze/microblaze-protos.h | 1 +
10 gcc/config/microblaze/microblaze.c | 109 ++++--
11 gcc/config/microblaze/microblaze.h | 4 +-
12 gcc/config/microblaze/microblaze.md | 394 +++++++++++++++++++++-
13 gcc/config/microblaze/microblaze.opt | 7 +-
14 gcc/config/microblaze/t-microblaze | 7 +-
15 7 files changed, 490 insertions(+), 37 deletions(-)
16
17diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
18index b9fc6e3fae2..f636b035280 100644
19--- a/gcc/config/microblaze/constraints.md
20+++ b/gcc/config/microblaze/constraints.md
21@@ -52,6 +52,11 @@
22 (and (match_code "const_int")
23 (match_test "ival > 0 && ival < 0x10000")))
24
25+(define_constraint "K"
26+ "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)."
27+ (and (match_code "const_int")
28+ (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
29+
30 ;; Define floating point constraints
31
32 (define_constraint "G"
33diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
34index 76ffc682df2..b8a3321dbdf 100644
35--- a/gcc/config/microblaze/microblaze-protos.h
36+++ b/gcc/config/microblaze/microblaze-protos.h
37@@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *);
38 extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
39 extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
40 extern void microblaze_expand_conditional_branch_sf (rtx *);
41+extern void microblaze_expand_conditional_branch_df (rtx *);
42 extern int microblaze_can_use_return_insn (void);
43 extern void print_operand (FILE *, rtx, int);
44 extern void print_operand_address (FILE *, rtx);
45diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
46index 4b5699671e8..8a3ccae558a 100644
47--- a/gcc/config/microblaze/microblaze.c
48+++ b/gcc/config/microblaze/microblaze.c
49@@ -3562,11 +3562,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
50 op0 = operands[0];
51 op1 = operands[1];
52
53- if (!register_operand (op0, SImode)
54- && !register_operand (op1, SImode)
55+ if (!register_operand (op0, mode)
56+ && !register_operand (op1, mode)
57 && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0))
58 {
59- rtx temp = force_reg (SImode, op1);
60+ rtx temp = force_reg (mode, op1);
61 emit_move_insn (op0, temp);
62 return true;
63 }
64@@ -3631,12 +3631,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
65 && (flag_pic == 2 || microblaze_tls_symbol_p (p0)
66 || !SMALL_INT (p1)))))
67 {
68- rtx temp = force_reg (SImode, p0);
69+ rtx temp = force_reg (mode, p0);
70 rtx temp2 = p1;
71
72 if (flag_pic && reload_in_progress)
73 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
74- emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2));
75+ emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2));
76 return true;
77 }
78 }
79@@ -3767,7 +3767,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
80 rtx cmp_op0 = operands[1];
81 rtx cmp_op1 = operands[2];
82 rtx label1 = operands[3];
83- rtx comp_reg = gen_reg_rtx (SImode);
84+ rtx comp_reg = gen_reg_rtx (mode);
85 rtx condition;
86
87 gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
88@@ -3776,23 +3776,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
89 if (cmp_op1 == const0_rtx)
90 {
91 comp_reg = cmp_op0;
92- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
93- emit_jump_insn (gen_condjump (condition, label1));
94+ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
95+ if (mode == SImode)
96+ emit_jump_insn (gen_condjump (condition, label1));
97+ else
98+ emit_jump_insn (gen_long_condjump (condition, label1));
99+
100 }
101
102 else if (code == EQ || code == NE)
103 {
104 /* Use xor for equal/not-equal comparison. */
105- emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
106- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
107- emit_jump_insn (gen_condjump (condition, label1));
108+ if (mode == SImode)
109+ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
110+ else
111+ emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
112+ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
113+ if (mode == SImode)
114+ emit_jump_insn (gen_condjump (condition, label1));
115+ else
116+ emit_jump_insn (gen_long_condjump (condition, label1));
117 }
118 else
119 {
120 /* Generate compare and branch in single instruction. */
121 cmp_op1 = force_reg (mode, cmp_op1);
122 condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
123- emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
124+ if (mode == SImode)
125+ emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
126+ else
127+ emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1));
128 }
129 }
130
131@@ -3803,7 +3816,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
132 rtx cmp_op0 = operands[1];
133 rtx cmp_op1 = operands[2];
134 rtx label1 = operands[3];
135- rtx comp_reg = gen_reg_rtx (SImode);
136+ rtx comp_reg = gen_reg_rtx (mode);
137 rtx condition;
138
139 gcc_assert ((GET_CODE (cmp_op0) == REG)
140@@ -3814,30 +3827,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
141 {
142 comp_reg = cmp_op0;
143 condition = gen_rtx_fmt_ee (signed_condition (code),
144- SImode, comp_reg, const0_rtx);
145- emit_jump_insn (gen_condjump (condition, label1));
146+ mode, comp_reg, const0_rtx);
147+ if (mode == SImode)
148+ emit_jump_insn (gen_condjump (condition, label1));
149+ else
150+ emit_jump_insn (gen_long_condjump (condition, label1));
151 }
152 else if (code == EQ)
153 {
154- emit_insn (gen_seq_internal_pat (comp_reg,
155- cmp_op0, cmp_op1));
156- condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx);
157- emit_jump_insn (gen_condjump (condition, label1));
158+ if (mode == SImode)
159+ {
160+ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
161+ cmp_op1));
162+ }
163+ else
164+ {
165+ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
166+ cmp_op1));
167+ }
168+ condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
169+ if (mode == SImode)
170+ emit_jump_insn (gen_condjump (condition, label1));
171+ else
172+ emit_jump_insn (gen_long_condjump (condition, label1));
173+
174 }
175 else if (code == NE)
176 {
177- emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
178- cmp_op1));
179- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
180- emit_jump_insn (gen_condjump (condition, label1));
181+ if (mode == SImode)
182+ {
183+ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
184+ cmp_op1));
185+ }
186+ else
187+ {
188+ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
189+ cmp_op1));
190+ }
191+ condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
192+ if (mode == SImode)
193+ emit_jump_insn (gen_condjump (condition, label1));
194+ else
195+ emit_jump_insn (gen_long_condjump (condition, label1));
196 }
197 else
198 {
199 /* Generate compare and branch in single instruction. */
200 cmp_op1 = force_reg (mode, cmp_op1);
201 condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
202- emit_jump_insn (gen_branch_compare (condition, cmp_op0,
203- cmp_op1, label1));
204+ if (mode == SImode)
205+ emit_jump_insn (gen_branch_compare (condition, cmp_op0,
206+ cmp_op1, label1));
207+ else
208+ {
209+ emit_jump_insn (gen_long_branch_compare (condition, cmp_op0,
210+ cmp_op1, label1));
211+ }
212+
213 }
214 }
215
216@@ -3854,6 +3900,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
217 emit_jump_insn (gen_condjump (condition, operands[3]));
218 }
219
220+void
221+microblaze_expand_conditional_branch_df (rtx operands[])
222+{
223+ rtx condition;
224+ rtx cmp_op0 = XEXP (operands[0], 0);
225+ rtx cmp_op1 = XEXP (operands[0], 1);
226+ rtx comp_reg = gen_reg_rtx (DImode);
227+
228+ emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
229+ condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
230+ emit_jump_insn (gen_long_condjump (condition, operands[3]));
231+}
232+
233 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
234
235 static bool
236diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
237index b5b7b22cec9..4931895e650 100644
238--- a/gcc/config/microblaze/microblaze.h
239+++ b/gcc/config/microblaze/microblaze.h
240@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe;
241 #define ASM_SPEC "\
242 %(target_asm_spec) \
243 %{mbig-endian:-EB} \
244+%{m64:-m64} \
245 %{mlittle-endian:-EL}"
246
247 /* Extra switches sometimes passed to the linker. */
248@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe;
249 #define LINK_SPEC "%{shared:-shared} -N -relax \
250 %{mbig-endian:-EB --oformat=elf32-microblaze} \
251 %{mlittle-endian:-EL --oformat=elf32-microblazeel} \
252+ %{m64:-EL --oformat=elf64-microblazeel} \
253 %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
254 %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
255 %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
256@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe;
257 #define MIN_UNITS_PER_WORD 4
258 #define INT_TYPE_SIZE 32
259 #define SHORT_TYPE_SIZE 16
260-#define LONG_TYPE_SIZE 32
261+#define LONG_TYPE_SIZE 64
262 #define LONG_LONG_TYPE_SIZE 64
263 #define FLOAT_TYPE_SIZE 32
264 #define DOUBLE_TYPE_SIZE 64
265diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
266index a527da70f8a..bcf2b9244f8 100644
267--- a/gcc/config/microblaze/microblaze.md
268+++ b/gcc/config/microblaze/microblaze.md
269@@ -497,7 +497,6 @@
270 (set_attr "mode" "SF")
271 (set_attr "length" "4")])
272
273-
274 (define_insn "divsf3"
275 [(set (match_operand:SF 0 "register_operand" "=d")
276 (div:SF (match_operand:SF 1 "register_operand" "d")
277@@ -508,6 +507,7 @@
278 (set_attr "mode" "SF")
279 (set_attr "length" "4")])
280
281+
282 (define_insn "sqrtsf2"
283 [(set (match_operand:SF 0 "register_operand" "=d")
284 (sqrt:SF (match_operand:SF 1 "register_operand" "d")))]
285@@ -562,6 +562,18 @@
286
287 ;; Adding 2 DI operands in register or reg/imm
288
289+(define_insn "adddi3_long"
290+ [(set (match_operand:DI 0 "register_operand" "=d,d")
291+ (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
292+ (match_operand:DI 2 "arith_plus_operand" "d,K")))]
293+ "TARGET_MB_64"
294+ "@
295+ addlk\t%0,%z1,%2
296+ addlik\t%0,%z1,%2"
297+ [(set_attr "type" "arith,arith")
298+ (set_attr "mode" "DI,DI")
299+ (set_attr "length" "4,4")])
300+
301 (define_insn "adddi3"
302 [(set (match_operand:DI 0 "register_operand" "=d,d")
303 (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
304@@ -606,6 +618,18 @@
305 ;; Double Precision Subtraction
306 ;;----------------------------------------------------------------
307
308+(define_insn "subdi3_long"
309+ [(set (match_operand:DI 0 "register_operand" "=d,d")
310+ (minus:DI (match_operand:DI 1 "register_operand" "d,d")
311+ (match_operand:DI 2 "register_operand" "d,n")))]
312+ "TARGET_MB_64"
313+ "@
314+ rsubl\t%0,%2,%1
315+ addlik\t%0,%z1,-%2"
316+ [(set_attr "type" "darith")
317+ (set_attr "mode" "DI,DI")
318+ (set_attr "length" "4,4")])
319+
320 (define_insn "subdi3"
321 [(set (match_operand:DI 0 "register_operand" "=&d")
322 (minus:DI (match_operand:DI 1 "register_operand" "d")
323@@ -795,6 +819,15 @@
324 (set_attr "mode" "SI")
325 (set_attr "length" "4")])
326
327+(define_insn "negdi2_long"
328+ [(set (match_operand:DI 0 "register_operand" "=d")
329+ (neg:DI (match_operand:DI 1 "register_operand" "d")))]
330+ "TARGET_MB_64"
331+ "rsubl\t%0,%1,r0"
332+ [(set_attr "type" "darith")
333+ (set_attr "mode" "DI")
334+ (set_attr "length" "4")])
335+
336 (define_insn "negdi2"
337 [(set (match_operand:DI 0 "register_operand" "=d")
338 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
339@@ -814,6 +847,15 @@
340 (set_attr "mode" "SI")
341 (set_attr "length" "4")])
342
343+(define_insn "one_cmpldi2_long"
344+ [(set (match_operand:DI 0 "register_operand" "=d")
345+ (not:DI (match_operand:DI 1 "register_operand" "d")))]
346+ "TARGET_MB_64"
347+ "xorli\t%0,%1,-1"
348+ [(set_attr "type" "arith")
349+ (set_attr "mode" "DI")
350+ (set_attr "length" "4")])
351+
352 (define_insn "*one_cmpldi2"
353 [(set (match_operand:DI 0 "register_operand" "=d")
354 (not:DI (match_operand:DI 1 "register_operand" "d")))]
355@@ -840,6 +882,20 @@
356 ;; Logical
357 ;;----------------------------------------------------------------
358
359+(define_insn "anddi3"
360+ [(set (match_operand:DI 0 "register_operand" "=d,d")
361+ (and:DI (match_operand:DI 1 "arith_operand" "d,d")
362+ (match_operand:DI 2 "arith_operand" "d,K")))]
363+ "TARGET_MB_64"
364+ "@
365+ andl\t%0,%1,%2
366+ andli\t%0,%1,%2 #andl1"
367+ ;; andli\t%0,%1,%2 #andl3
368+ ;; andli\t%0,%1,%2 #andl2
369+ [(set_attr "type" "arith,arith")
370+ (set_attr "mode" "DI,DI")
371+ (set_attr "length" "4,4")])
372+
373 (define_insn "andsi3"
374 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
375 (and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
376@@ -855,6 +911,18 @@
377 (set_attr "length" "4,8,8,8")])
378
379
380+(define_insn "iordi3"
381+ [(set (match_operand:DI 0 "register_operand" "=d,d")
382+ (ior:DI (match_operand:DI 1 "arith_operand" "d,d")
383+ (match_operand:DI 2 "arith_operand" "d,K")))]
384+ "TARGET_MB_64"
385+ "@
386+ orl\t%0,%1,%2
387+ orli\t%0,%1,%2 #andl1"
388+ [(set_attr "type" "arith,arith")
389+ (set_attr "mode" "DI,DI")
390+ (set_attr "length" "4,4")])
391+
392 (define_insn "iorsi3"
393 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
394 (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
395@@ -869,6 +937,19 @@
396 (set_attr "mode" "SI,SI,SI,SI")
397 (set_attr "length" "4,8,8,8")])
398
399+(define_insn "xordi3"
400+ [(set (match_operand:DI 0 "register_operand" "=d,d")
401+ (xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
402+ (match_operand:DI 2 "arith_operand" "d,K")))]
403+ "TARGET_MB_64"
404+ "@
405+ xorl\t%0,%1,%2
406+ xorli\t%0,%1,%2 #andl1"
407+ [(set_attr "type" "arith,arith")
408+ (set_attr "mode" "DI,DI")
409+ (set_attr "length" "4,4")])
410+
411+
412 (define_insn "xorsi3"
413 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
414 (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d")
415@@ -937,6 +1018,26 @@
416 (set_attr "mode" "SI")
417 (set_attr "length" "4")])
418
419+;;(define_expand "extendqidi2"
420+;; [(set (match_operand:DI 0 "register_operand" "=d")
421+;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
422+;; "TARGET_MB_64"
423+;; {
424+;; if (GET_CODE (operands[1]) != REG)
425+;; FAIL;
426+;; }
427+;;)
428+
429+
430+;;(define_insn "extendqidi2"
431+;; [(set (match_operand:DI 0 "register_operand" "=d")
432+;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
433+;; "TARGET_MB_64"
434+;; "sextl8\t%0,%1"
435+;; [(set_attr "type" "arith")
436+;; (set_attr "mode" "DI")
437+;; (set_attr "length" "4")])
438+
439 (define_insn "extendhisi2"
440 [(set (match_operand:SI 0 "register_operand" "=d")
441 (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
442@@ -946,6 +1047,16 @@
443 (set_attr "mode" "SI")
444 (set_attr "length" "4")])
445
446+(define_insn "extendhidi2"
447+ [(set (match_operand:DI 0 "register_operand" "=d")
448+ (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
449+ "TARGET_MB_64"
450+ "sextl16\t%0,%1"
451+ [(set_attr "type" "arith")
452+ (set_attr "mode" "DI")
453+ (set_attr "length" "4")])
454+
455+
456 ;; Those for integer source operand are ordered
457 ;; widest source type first.
458
459@@ -1011,6 +1122,31 @@
460 )
461
462
463+(define_insn "*movdi_internal_64"
464+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
465+ (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))]
466+ "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
467+ {
468+ switch (which_alternative)
469+ {
470+ case 0:
471+ return "addlk\t%0,%1";
472+ case 1:
473+ return "addlik\t%0,r0,%1";
474+ case 2:
475+ return "addlk\t%0,r0,r0";
476+ case 3:
477+ case 4:
478+ return "lli\t%0,%1";
479+ case 5:
480+ case 6:
481+ return "sli\t%1,%0";
482+ }
483+ return "unreachable";
484+ }
485+ [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
486+ (set_attr "mode" "DI")
487+ (set_attr "length" "8,8,8,8,12,8,12")])
488
489 (define_insn "*movdi_internal"
490 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
491@@ -1423,6 +1559,36 @@
492 (set_attr "length" "4,4")]
493 )
494
495+;; Barrel shift left
496+(define_expand "ashldi3"
497+ [(set (match_operand:DI 0 "register_operand" "=&d")
498+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
499+ (match_operand:DI 2 "arith_operand" "")))]
500+"TARGET_MB_64"
501+{
502+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
503+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
504+ {
505+ emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
506+ DONE;
507+ }
508+else
509+ FAIL;
510+}
511+)
512+
513+(define_insn "ashldi3_long"
514+ [(set (match_operand:DI 0 "register_operand" "=d,d")
515+ (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
516+ (match_operand:DI 2 "arith_operand" "I,d")))]
517+ "TARGET_MB_64"
518+ "@
519+ bsllli\t%0,%1,%2
520+ bslll\t%0,%1,%2"
521+ [(set_attr "type" "bshift,bshift")
522+ (set_attr "mode" "DI,DI")
523+ (set_attr "length" "4,4")]
524+)
525 ;; The following patterns apply when there is no barrel shifter present
526
527 (define_insn "*ashlsi3_with_mul_delay"
528@@ -1548,6 +1714,36 @@
529 ;;----------------------------------------------------------------
530 ;; 32-bit right shifts
531 ;;----------------------------------------------------------------
532+;; Barrel shift left
533+(define_expand "ashrdi3"
534+ [(set (match_operand:DI 0 "register_operand" "=&d")
535+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
536+ (match_operand:DI 2 "arith_operand" "")))]
537+"TARGET_MB_64"
538+{
539+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
540+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
541+ {
542+ emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
543+ DONE;
544+ }
545+else
546+ FAIL;
547+}
548+)
549+
550+(define_insn "ashrdi3_long"
551+ [(set (match_operand:DI 0 "register_operand" "=d,d")
552+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
553+ (match_operand:DI 2 "arith_operand" "I,d")))]
554+ "TARGET_MB_64"
555+ "@
556+ bslrai\t%0,%1,%2
557+ bslra\t%0,%1,%2"
558+ [(set_attr "type" "bshift,bshift")
559+ (set_attr "mode" "DI,DI")
560+ (set_attr "length" "4,4")]
561+ )
562 (define_expand "ashrsi3"
563 [(set (match_operand:SI 0 "register_operand" "=&d")
564 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
565@@ -1657,6 +1853,36 @@
566 ;;----------------------------------------------------------------
567 ;; 32-bit right shifts (logical)
568 ;;----------------------------------------------------------------
569+;; Barrel shift left
570+(define_expand "lshrdi3"
571+ [(set (match_operand:DI 0 "register_operand" "=&d")
572+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
573+ (match_operand:DI 2 "arith_operand" "")))]
574+"TARGET_MB_64"
575+{
576+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
577+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
578+ {
579+ emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
580+ DONE;
581+ }
582+else
583+ FAIL;
584+}
585+)
586+
587+(define_insn "lshrdi3_long"
588+ [(set (match_operand:DI 0 "register_operand" "=d,d")
589+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
590+ (match_operand:DI 2 "arith_operand" "I,d")))]
591+ "TARGET_MB_64"
592+ "@
593+ bslrli\t%0,%1,%2
594+ bslrl\t%0,%1,%2"
595+ [(set_attr "type" "bshift,bshift")
596+ (set_attr "mode" "DI,DI")
597+ (set_attr "length" "4,4")]
598+ )
599
600 (define_expand "lshrsi3"
601 [(set (match_operand:SI 0 "register_operand" "=&d")
602@@ -1803,6 +2029,8 @@
603 (set_attr "length" "4")]
604 )
605
606+
607+
608 ;;----------------------------------------------------------------
609 ;; Setting a register from an floating point comparison.
610 ;;----------------------------------------------------------------
611@@ -1818,6 +2046,18 @@
612 (set_attr "length" "4")]
613 )
614
615+(define_insn "cstoredf4"
616+ [(set (match_operand:DI 0 "register_operand" "=r")
617+ (match_operator:DI 1 "ordered_comparison_operator"
618+ [(match_operand:DF 2 "register_operand" "r")
619+ (match_operand:DF 3 "register_operand" "r")]))]
620+ "TARGET_MB_64"
621+ "dcmp.%C1\t%0,%3,%2"
622+ [(set_attr "type" "fcmp")
623+ (set_attr "mode" "DF")
624+ (set_attr "length" "4")]
625+)
626+
627 ;;----------------------------------------------------------------
628 ;; Conditional branches
629 ;;----------------------------------------------------------------
630@@ -1930,6 +2170,115 @@
631 (set_attr "length" "12")]
632 )
633
634+
635+(define_expand "cbranchdi4"
636+ [(set (pc)
637+ (if_then_else (match_operator 0 "ordered_comparison_operator"
638+ [(match_operand:DI 1 "register_operand")
639+ (match_operand:DI 2 "arith_operand" "I,i")])
640+ (label_ref (match_operand 3 ""))
641+ (pc)))]
642+ "TARGET_MB_64"
643+{
644+ microblaze_expand_conditional_branch (DImode, operands);
645+ DONE;
646+})
647+
648+(define_expand "cbranchdi4_reg"
649+ [(set (pc)
650+ (if_then_else (match_operator 0 "ordered_comparison_operator"
651+ [(match_operand:DI 1 "register_operand")
652+ (match_operand:DI 2 "register_operand")])
653+ (label_ref (match_operand 3 ""))
654+ (pc)))]
655+ "TARGET_MB_64"
656+{
657+ microblaze_expand_conditional_branch_reg (DImode, operands);
658+ DONE;
659+})
660+
661+(define_expand "cbranchdf4"
662+ [(set (pc)
663+ (if_then_else (match_operator 0 "ordered_comparison_operator"
664+ [(match_operand:DF 1 "register_operand")
665+ (match_operand:DF 2 "register_operand")])
666+ (label_ref (match_operand 3 ""))
667+ (pc)))]
668+ "TARGET_MB_64"
669+{
670+ microblaze_expand_conditional_branch_df (operands);
671+ DONE;
672+
673+})
674+
675+;; Used to implement comparison instructions
676+(define_expand "long_condjump"
677+ [(set (pc)
678+ (if_then_else (match_operand 0)
679+ (label_ref (match_operand 1))
680+ (pc)))])
681+
682+(define_insn "long_branch_zero"
683+ [(set (pc)
684+ (if_then_else (match_operator:DI 0 "ordered_comparison_operator"
685+ [(match_operand:DI 1 "register_operand" "d")
686+ (const_int 0)])
687+ (match_operand:DI 2 "pc_or_label_operand" "")
688+ (match_operand:DI 3 "pc_or_label_operand" "")))
689+ ]
690+ "TARGET_MB_64"
691+ {
692+ if (operands[3] == pc_rtx)
693+ return "beal%C0i%?\t%z1,%2";
694+ else
695+ return "beal%N0i%?\t%z1,%3";
696+ }
697+ [(set_attr "type" "branch")
698+ (set_attr "mode" "none")
699+ (set_attr "length" "4")]
700+)
701+
702+(define_insn "long_branch_compare"
703+ [(set (pc)
704+ (if_then_else (match_operator:DI 0 "cmp_op"
705+ [(match_operand:DI 1 "register_operand" "d")
706+ (match_operand:DI 2 "register_operand" "d")
707+ ])
708+ (label_ref (match_operand 3))
709+ (pc)))
710+ (clobber(reg:DI R_TMP))]
711+ "TARGET_MB_64"
712+ {
713+ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
714+ enum rtx_code code = GET_CODE (operands[0]);
715+
716+ if (code == GT || code == LE)
717+ {
718+ output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
719+ code = swap_condition (code);
720+ }
721+ else if (code == GTU || code == LEU)
722+ {
723+ output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
724+ code = swap_condition (code);
725+ }
726+ else if (code == GE || code == LT)
727+ {
728+ output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
729+ }
730+ else if (code == GEU || code == LTU)
731+ {
732+ output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
733+ }
734+
735+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
736+ return "beal%C0i%?\tr18,%3";
737+ }
738+ [(set_attr "type" "branch")
739+ (set_attr "mode" "none")
740+ (set_attr "length" "12")]
741+)
742+
743 ;;----------------------------------------------------------------
744 ;; Unconditional branches
745 ;;----------------------------------------------------------------
746@@ -2478,17 +2827,33 @@
747 DONE;
748 }")
749
750-(define_expand "extzvsi"
751+(define_expand "extvsi"
752 [(set (match_operand:SI 0 "register_operand" "r")
753 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
754 (match_operand:SI 2 "immediate_operand" "I")
755 (match_operand:SI 3 "immediate_operand" "I")))]
756 "TARGET_HAS_BITFIELD"
757-""
758-)
759-
760+"
761+{
762+ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
763+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
764+
765+ if ((len == 0) || (pos + len > 32) )
766+ FAIL;
767+
768+ ;;if (!register_operand (operands[1], VOIDmode))
769+ ;; FAIL;
770+ if (operands[0] == operands[1])
771+ FAIL;
772+ if (GET_CODE (operands[1]) == ASHIFT)
773+ FAIL;
774+;; operands[2] = GEN_INT(INTVAL(operands[2])+1 );
775+ emit_insn (gen_extv_32 (operands[0], operands[1],
776+ operands[2], operands[3]));
777+ DONE;
778+}")
779
780-(define_insn "extzv_32"
781+(define_insn "extv_32"
782 [(set (match_operand:SI 0 "register_operand" "=r")
783 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
784 (match_operand:SI 2 "immediate_operand" "I")
785@@ -2505,8 +2870,21 @@
786 (match_operand:SI 2 "immediate_operand" "I"))
787 (match_operand:SI 3 "register_operand" "r"))]
788 "TARGET_HAS_BITFIELD"
789-""
790-)
791+ "
792+{
793+ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
794+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
795+
796+ if (len <= 0 || pos + len > 32)
797+ FAIL;
798+
799+ ;;if (!register_operand (operands[0], VOIDmode))
800+ ;; FAIL;
801+
802+ emit_insn (gen_insv_32 (operands[0], operands[1],
803+ operands[2], operands[3]));
804+ DONE;
805+}")
806
807 (define_insn "insv_32"
808 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
809diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
810index a29c6f8df90..bbe48b06da6 100644
811--- a/gcc/config/microblaze/microblaze.opt
812+++ b/gcc/config/microblaze/microblaze.opt
813@@ -136,4 +136,9 @@ Target
814
815 mxl-frequency
816 Target Mask(AREA_OPTIMIZED_2)
817-Use 8 stage pipeline (frequency optimization)
818+Use 8 stage pipeline (frequency optimization).
819+
820+m64
821+Target Mask(MB_64)
822+MicroBlaze 64-bit mode.
823+
824diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
825index 41fa9a92081..7671f63c5b5 100644
826--- a/gcc/config/microblaze/t-microblaze
827+++ b/gcc/config/microblaze/t-microblaze
828@@ -1,8 +1,11 @@
829-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian
830-MULTILIB_DIRNAMES = bs m mh le
831+MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
832+MULTILIB_DIRNAMES = bs m mh le m64
833 MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
834 MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
835+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
836 MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
837+#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
838+#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
839
840 # Extra files
841 microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
842--
8432.17.1
844
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-07-05 07:12:05 +0000