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Add device tree overlay for extending support for mcu_uart0 as well as
wkup_uart0 for boards with J7200 SoC. This overlay will mainly be used
for the purpose of testing uart instances.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Signed-off-by: Ryan Eatmon <reatmon@ti.com>
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Add the MCSPI loopback overlay file for J7200 EVM which helps
users to enable MCU-MAIN MCSPI loopback applications.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Ryan Eatmon <reatmon@ti.com>
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Only the first two K3 devices do not support multi-cert boot so
lets make multi-cert the default and only add back sysfw.itb
for these two devices.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: lines be preserved?
Signed-off-by: Ryan Eatmon <reatmon@ti.com>
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Remove jailhouse overlay as it is not currently available in
ti-linux-5.10.y branch.
Removing for now, and shall be added back once they are
available in 5.10 kernel.
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
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Switch to using all of multi-certificate boot images. This allows us
to create bootable images - in this case, we are missing tiboot3.bin
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Denys Dmytriyenko <denys@konsulko.com>
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wic and tar dependency on trusted firmware is wrong. It is u-boot build
that depends on trusted firmware deployment and is correctly handled by
u-boot recipe. No point in duplicating that dependency, so just clean it
all up.
Reported-by: Denys Dmytriyenko <denys@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Denys Dmytriyenko <denys@konsulko.com>
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j7200-evm supports virtualization with Jailhouse hypervisor.
To use Jailhouse, kernel needs to boot with an additional
DTB overlay. Include this in the list of DTBs for the machine.
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
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The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded
products.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, two clusters of lockstep
capable dual Cortex-R5F MCUs and a Centralized Device Management and
Security Controller (DMSC).
* Configurable L3 Cache and IO-coherent architecture with high data
throughput capable distributed DMA architecture under NAVSS.
* Integrated Ethernet switch supporting up to a total of 4 external ports
in addition to legacy Ethernet switch of up to 2 ports.
* Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and
I2C, eCAP/eQEP, eHRPWM among other peripherals.
* One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
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