1 files changed, 40 insertions, 0 deletions

diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/3.2.10/0067-ARM-7355-1-perf-clear-overflow-flag-when-disabling-c.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/3.2.10/0067-ARM-7355-1-perf-clear-overflow-flag-when-disabling-c.patch
new file mode 100644
index 00000000..5d401cb9
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/3.2.10/0067-ARM-7355-1-perf-clear-overflow-flag-when-disabling-c.patch
@@ -0,0 +1,40 @@
+From 54426f627a1b329bda270f1e85f9ee0e01e18573 Mon Sep 17 00:00:00 2001
+From: Will Deacon <will.deacon@arm.com>
+Date: Tue, 6 Mar 2012 17:34:22 +0100
+Subject: [PATCH 67/95] ARM: 7355/1: perf: clear overflow flag when disabling
+ counter on ARMv7 PMU
+
+commit 99c1745b9c76910e195889044f914b4898b7c9a5 upstream.
+
+When disabling a counter on an ARMv7 PMU, we should also clear the
+overflow flag in case an overflow occurred whilst stopping the counter.
+This prevents a spurious overflow being picked up later and leading to
+either false accounting or a NULL dereference.
+
+Reported-by: Ming Lei <tom.leiming@gmail.com>
+Signed-off-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm/kernel/perf_event_v7.c |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
+index c63a13e..5e1e4f7 100644
+--- a/arch/arm/kernel/perf_event_v7.c
++++ b/arch/arm/kernel/perf_event_v7.c
+@@ -781,6 +781,11 @@ static inline int armv7_pmnc_disable_intens(int idx)
+ 
+        counter = ARMV7_IDX_TO_COUNTER(idx);
+        asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter)));
++       isb();
++       /* Clear the overflow flag in case an interrupt is pending. */
++       asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter)));
++       isb();
++
+        return idx;
+ }
+ 
+-- 
+1.7.9.4
+