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Diffstat (limited to 'recipes-kernel/linux/linux-am335x-3.2.0-psp04.06.00.08/0001-am335x-Add-pm_runtime-API-to-crypto-driver.patch')
-rw-r--r--recipes-kernel/linux/linux-am335x-3.2.0-psp04.06.00.08/0001-am335x-Add-pm_runtime-API-to-crypto-driver.patch405
1 files changed, 405 insertions, 0 deletions
diff --git a/recipes-kernel/linux/linux-am335x-3.2.0-psp04.06.00.08/0001-am335x-Add-pm_runtime-API-to-crypto-driver.patch b/recipes-kernel/linux/linux-am335x-3.2.0-psp04.06.00.08/0001-am335x-Add-pm_runtime-API-to-crypto-driver.patch
new file mode 100644
index 00000000..cef94b70
--- /dev/null
+++ b/recipes-kernel/linux/linux-am335x-3.2.0-psp04.06.00.08/0001-am335x-Add-pm_runtime-API-to-crypto-driver.patch
@@ -0,0 +1,405 @@
1From 7cb6dbae57e2bb5d237bb88f6eb40971cf8fc3b5 Mon Sep 17 00:00:00 2001
2From: Greg Turner <gregturner@ti.com>
3Date: Wed, 18 Jul 2012 09:15:18 -0500
4Subject: [PATCH] [am335x]: Add pm_runtime API to crypto driver
5
6* Add pm_runtime API to crypto driver AES and SHA
7* Mod devices.c file to add pm_runtime for crypto
8* Mod omap_hwmod_33xx_data.c to add resources structures
9* Crypto module clocks are enabled in probe function
10 and disabled only on remove or other error.
11---
12 arch/arm/mach-omap2/devices.c | 66 ++++++++++++++++++++++++++++
13 arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 15 ++++++-
14 drivers/crypto/omap4-aes.c | 52 +++++++++++----------
15 drivers/crypto/omap4-sham.c | 45 ++++++++++---------
16 4 files changed, 131 insertions(+), 47 deletions(-)
17 mode change 100644 => 100755 arch/arm/mach-omap2/devices.c
18 mode change 100644 => 100755 arch/arm/mach-omap2/omap_hwmod_33xx_data.c
19 mode change 100644 => 100755 drivers/crypto/omap4-aes.c
20 mode change 100644 => 100755 drivers/crypto/omap4-sham.c
21
22diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
23old mode 100644
24new mode 100755
25index ebf0d9e..156e363
26--- a/arch/arm/mach-omap2/devices.c
27+++ b/arch/arm/mach-omap2/devices.c
28@@ -751,6 +751,7 @@ static struct platform_device sham_device = {
29 .id = -1,
30 };
31
32+#if 0
33 static void omap_init_sham(void)
34 {
35 sham_device.resource = omap4_sham_resources;
36@@ -758,6 +759,38 @@ static void omap_init_sham(void)
37
38 platform_device_register(&sham_device);
39 }
40+#endif
41+
42+int __init omap_init_sham(void)
43+{
44+ int id = -1;
45+ struct platform_device *pdev;
46+ struct omap_hwmod *oh;
47+ char *oh_name = "sha0";
48+ char *name = "omap4-sham";
49+
50+ oh = omap_hwmod_lookup(oh_name);
51+ if (!oh) {
52+ pr_err("Could not look up %s\n", oh_name);
53+ return -ENODEV;
54+ }
55+
56+ pdev = omap_device_build(name, id, oh, NULL, 0, NULL, 0, 0);
57+ //pdev.resource = omap4_sham_resources;
58+ //pdev.num_resources = omap4_sham_resources_sz;
59+
60+ if (IS_ERR(pdev)) {
61+ WARN(1, "Can't build omap_device for %s:%s.\n",
62+ name, oh->name);
63+ return PTR_ERR(pdev);
64+ }
65+
66+ return 0;
67+}
68+
69+
70+
71+
72
73 #else
74 static inline void omap_init_sham(void) { }
75@@ -853,12 +886,45 @@ static struct platform_device aes_device = {
76 .id = -1,
77 };
78
79+#if 0
80 static void omap_init_aes(void)
81 {
82 aes_device.resource = omap4_aes_resources;
83 aes_device.num_resources = omap4_aes_resources_sz;
84 platform_device_register(&aes_device);
85 }
86+#endif
87+
88+int __init omap_init_aes(void)
89+{
90+ int id = -1;
91+ struct platform_device *pdev;
92+ struct omap_hwmod *oh;
93+ char *oh_name = "aes0";
94+ char *name = "omap4-aes";
95+
96+ oh = omap_hwmod_lookup(oh_name);
97+ if (!oh) {
98+ pr_err("Could not look up %s\n", oh_name);
99+ return -ENODEV;
100+ }
101+
102+ pdev = omap_device_build(name, id, oh, NULL, 0, NULL, 0, 0);
103+ //pdev.resource = omap4_sham_resources;
104+ //pdev.num_resources = omap4_sham_resources_sz;
105+
106+ if (IS_ERR(pdev)) {
107+ WARN(1, "Can't build omap_device for %s:%s.\n",
108+ name, oh->name);
109+ return PTR_ERR(pdev);
110+ }
111+
112+ return 0;
113+}
114+
115+
116+
117+
118
119 #else
120 static inline void omap_init_aes(void) { }
121diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
122old mode 100644
123new mode 100755
124index 995b73f..2f9982c
125--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
126+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
127@@ -434,11 +434,18 @@ static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
128 { .irq = -1 }
129 };
130
131+static struct omap_hwmod_dma_info am33xx_aes0_dma[] = {
132+ { .dma_req = AM33XX_DMA_AESEIP36T0_DOUT },
133+ { .dma_req = AM33XX_DMA_AESEIP36T0_DIN },
134+ { .dma_req = -1 }
135+};
136+
137 static struct omap_hwmod am33xx_aes0_hwmod = {
138 .name = "aes0",
139 .class = &am33xx_aes_hwmod_class,
140 .clkdm_name = "l3_clkdm",
141 .mpu_irqs = am33xx_aes0_irqs,
142+ .sdma_reqs = am33xx_aes0_dma,
143 .main_clk = "aes0_fck",
144 .prcm = {
145 .omap4 = {
146@@ -2165,15 +2172,21 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
147 };
148
149 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
150- { .irq = 108 },
151+ { .irq = AM33XX_IRQ_SHAEIP57t0_P },
152 { .irq = -1 }
153 };
154
155+static struct omap_hwmod_dma_info am33xx_sha0_dma[] = {
156+ { .dma_req = AM33XX_DMA_SHAEIP57T0_DIN },
157+ { .dma_req = -1 }
158+};
159+
160 static struct omap_hwmod am33xx_sha0_hwmod = {
161 .name = "sha0",
162 .class = &am33xx_sha0_hwmod_class,
163 .clkdm_name = "l3_clkdm",
164 .mpu_irqs = am33xx_sha0_irqs,
165+ .sdma_reqs = am33xx_sha0_dma,
166 .main_clk = "sha0_fck",
167 .prcm = {
168 .omap4 = {
169diff --git a/drivers/crypto/omap4-aes.c b/drivers/crypto/omap4-aes.c
170old mode 100644
171new mode 100755
172index f0b3fe2..76f988a
173--- a/drivers/crypto/omap4-aes.c
174+++ b/drivers/crypto/omap4-aes.c
175@@ -32,13 +32,14 @@
176 #include <linux/init.h>
177 #include <linux/errno.h>
178 #include <linux/kernel.h>
179-#include <linux/clk.h>
180 #include <linux/platform_device.h>
181 #include <linux/scatterlist.h>
182 #include <linux/dma-mapping.h>
183 #include <linux/io.h>
184 #include <linux/crypto.h>
185+#include <linux/pm_runtime.h>
186 #include <linux/interrupt.h>
187+#include <linux/delay.h>
188 #include <crypto/scatterwalk.h>
189 #include <crypto/aes.h>
190
191@@ -145,12 +146,6 @@ static void omap4_aes_write_n(struct omap4_aes_dev *dd, u32 offset,
192
193 static int omap4_aes_hw_init(struct omap4_aes_dev *dd)
194 {
195- /*
196- * clocks are enabled when request starts and disabled when finished.
197- * It may be long delays between requests.
198- * Device might go to off mode to save power.
199- */
200- clk_enable(dd->iclk);
201 omap4_aes_write(dd, AES_REG_SYSCFG, 0);
202
203 if (!(dd->flags & FLAGS_INIT)) {
204@@ -494,7 +489,6 @@ static void omap4_aes_finish_req(struct omap4_aes_dev *dd, int err)
205
206 pr_debug("err: %d\n", err);
207
208- clk_disable(dd->iclk);
209 dd->flags &= ~FLAGS_BUSY;
210
211 req->base.complete(&req->base, err);
212@@ -801,13 +795,15 @@ static int omap4_aes_probe(struct platform_device *pdev)
213 crypto_init_queue(&dd->queue, AM33X_AES_QUEUE_LENGTH);
214
215 /* Get the base address */
216- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
217- if (!res) {
218- dev_err(dev, "invalid resource type\n");
219- err = -ENODEV;
220- goto err_res;
221- }
222- dd->phys_base = res->start;
223+ //res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
224+ //if (!res) {
225+ // dev_err(dev, "invalid resource type\n");
226+ // err = -ENODEV;
227+ // goto err_res;
228+ //}
229+
230+ //dd->phys_base = res->start;
231+ dd->phys_base = AM33XX_AES0_P_BASE;
232
233 /* Get the DMA */
234 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
235@@ -823,13 +819,10 @@ static int omap4_aes_probe(struct platform_device *pdev)
236 else
237 dd->dma_in = res->start;
238
239- /* Initializing the clock */
240- dd->iclk = clk_get(dev, "aes0_fck");
241- if (IS_ERR(dd->iclk)) {
242- dev_err(dev, "clock initialization failed.\n");
243- err = PTR_ERR(dd->iclk);
244- goto err_res;
245- }
246+ pm_runtime_enable(dev);
247+ udelay(1);
248+ pm_runtime_get_sync(dev);
249+ udelay(1);
250
251 dd->io_base = ioremap(dd->phys_base, SZ_4K);
252 if (!dd->io_base) {
253@@ -840,7 +833,7 @@ static int omap4_aes_probe(struct platform_device *pdev)
254
255 omap4_aes_hw_init(dd);
256 reg = omap4_aes_read(dd, AES_REG_REV);
257- clk_disable(dd->iclk);
258+
259 dev_info(dev, "AM33X AES hw accel rev: %u.%02u\n",
260 ((reg & AES_REG_REV_X_MAJOR_MASK) >> 8),
261 (reg & AES_REG_REV_Y_MINOR_MASK));
262@@ -879,7 +872,12 @@ err_dma:
263 iounmap(dd->io_base);
264
265 err_io:
266- clk_put(dd->iclk);
267+ pm_runtime_put_sync(dev);
268+ udelay(1);
269+ pm_runtime_disable(dev);
270+ udelay(1);
271+
272+
273 err_res:
274 kfree(dd);
275 dd = NULL;
276@@ -907,7 +905,11 @@ static int omap4_aes_remove(struct platform_device *pdev)
277 tasklet_kill(&dd->queue_task);
278 omap4_aes_dma_cleanup(dd);
279 iounmap(dd->io_base);
280- clk_put(dd->iclk);
281+ pm_runtime_put_sync(&pdev->dev);
282+ udelay(1);
283+ pm_runtime_disable(&pdev->dev);
284+ udelay(1);
285+
286 kfree(dd);
287 dd = NULL;
288
289diff --git a/drivers/crypto/omap4-sham.c b/drivers/crypto/omap4-sham.c
290old mode 100644
291new mode 100755
292index 79f6be9..21f1b48
293--- a/drivers/crypto/omap4-sham.c
294+++ b/drivers/crypto/omap4-sham.c
295@@ -31,7 +31,6 @@
296 #include <linux/errno.h>
297 #include <linux/interrupt.h>
298 #include <linux/kernel.h>
299-#include <linux/clk.h>
300 #include <linux/irq.h>
301 #include <linux/io.h>
302 #include <linux/platform_device.h>
303@@ -40,6 +39,7 @@
304 #include <linux/delay.h>
305 #include <linux/crypto.h>
306 #include <linux/cryptohash.h>
307+#include <linux/pm_runtime.h>
308 #include <crypto/scatterwalk.h>
309 #include <crypto/algapi.h>
310 #include <crypto/sha.h>
311@@ -700,7 +700,6 @@ static void omap4_sham_finish_req(struct ahash_request *req, int err)
312 /* atomic operation is not needed here */
313 dd->dflags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
314 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
315- clk_disable(dd->iclk);
316
317 if (req->base.complete)
318 req->base.complete(&req->base, err);
319@@ -743,7 +742,6 @@ static int omap4_sham_handle_queue(struct omap4_sham_dev *dd,
320 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
321 ctx->op, req->nbytes);
322
323- clk_enable(dd->iclk);
324 if (!test_bit(FLAGS_INIT, &dd->dflags)) {
325 set_bit(FLAGS_INIT, &dd->dflags);
326 dd->err = 0;
327@@ -1272,13 +1270,15 @@ static int __devinit omap4_sham_probe(struct platform_device *pdev)
328 dd->irq = -1;
329
330 /* Get the base address */
331- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
332- if (!res) {
333- dev_err(dev, "no MEM resource info\n");
334- err = -ENODEV;
335- goto res_err;
336- }
337- dd->phys_base = res->start;
338+ //res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
339+ //if (!res) {
340+ // dev_err(dev, "no MEM resource info\n");
341+ // err = -ENODEV;
342+ // goto res_err;
343+ //}
344+
345+ //dd->phys_base = res->start;
346+ dd->phys_base = AM33XX_SHA1MD5_P_BASE;
347
348 /* Get the DMA */
349 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
350@@ -1308,13 +1308,10 @@ static int __devinit omap4_sham_probe(struct platform_device *pdev)
351 if (err)
352 goto dma_err;
353
354- /* Initializing the clock */
355- dd->iclk = clk_get(dev, "sha0_fck");
356- if (IS_ERR(dd->iclk)) {
357- dev_err(dev, "clock initialization failed.\n");
358- err = PTR_ERR(dd->iclk);
359- goto clk_err;
360- }
361+ pm_runtime_enable(dev);
362+ udelay(1);
363+ pm_runtime_get_sync(dev);
364+ udelay(1);
365
366 dd->io_base = ioremap(dd->phys_base, SZ_4K);
367 if (!dd->io_base) {
368@@ -1323,9 +1320,7 @@ static int __devinit omap4_sham_probe(struct platform_device *pdev)
369 goto io_err;
370 }
371
372- clk_enable(dd->iclk);
373 reg = omap4_sham_read(dd, SHA_REG_REV);
374- clk_disable(dd->iclk);
375
376 dev_info(dev, "AM33X SHA/MD5 hw accel rev: %u.%02u\n",
377 (reg & SHA_REG_REV_X_MAJOR_MASK) >> 8, reg & SHA_REG_REV_Y_MINOR_MASK);
378@@ -1349,7 +1344,11 @@ err_algs:
379 crypto_unregister_ahash(&algs[j]);
380 iounmap(dd->io_base);
381 io_err:
382- clk_put(dd->iclk);
383+ pm_runtime_put_sync(dev);
384+ udelay(1);
385+ pm_runtime_disable(dev);
386+ udelay(1);
387+
388 clk_err:
389 omap4_sham_dma_cleanup(dd);
390 dma_err:
391@@ -1379,7 +1378,11 @@ static int __devexit omap4_sham_remove(struct platform_device *pdev)
392 crypto_unregister_ahash(&algs[i]);
393 tasklet_kill(&dd->done_task);
394 iounmap(dd->io_base);
395- clk_put(dd->iclk);
396+ pm_runtime_put_sync(&pdev->dev);
397+ udelay(1);
398+ pm_runtime_disable(&pdev->dev);
399+ udelay(1);
400+
401 omap4_sham_dma_cleanup(dd);
402 if (dd->irq >= 0)
403 free_irq(dd->irq, dd);
404--
4051.7.0.4