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-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0001-beagleboard-probe-DDC-bus-for-expansionboard-EEPROMS.patch165
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0001-omap3-mem-Comment-enable_gpmc_cs_config-more.patch56
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0002-OMAP3-Update-SDRC-dram_init-to-always-call-make_cs1_.patch66
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0003-OMAP3-Add-a-helper-function-to-set-timings-in-SDRC.patch172
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0004-OMAP3-Change-mem_ok-to-clear-again-after-reading-bac.patch30
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0005-OMAP3-Remove-get_mem_type-prototype.patch28
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0006-omap3-mem-Add-MCFG-helper-macro.patch97
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0007-OMAP3-Add-optimal-SDRC-autorefresh-control-values.patch59
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0008-OMAP3-Suffix-all-Micron-memory-timing-parts-with-the.patch55
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0009-OMAP3-SPL-Rework-memory-initalization-and-devkit8000.patch174
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0010-OMAP3-SPL-Add-identify_nand_chip-function.patch142
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0011-OMAP3-Add-SPL-support-to-Beagleboard.patch315
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0012-OMAP3-Add-SPL-support-to-omap3_evm.patch319
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0013-AM3517-Add-SPL-support.patch150
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0014-AM3517-CraneBoard-Add-SPL-support.patch150
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0015-HACK-beagleboard-config-disable-cache-for-USB.patch (renamed from recipes-bsp/u-boot/u-boot/2011.09/0001-HACK-beagleboard-config-disable-cache-for-USB.patch)12
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0016-beagleboard-config-enable-gpio-command.patch (renamed from recipes-bsp/u-boot/u-boot/2011.09/0002-beagleboard-config-enable-gpio-command.patch)10
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0017-Increased-some-timeout-durations-for-MMC-and-EHCI.patch (renamed from recipes-bsp/u-boot/u-boot/2011.09/0003-Increased-some-timeout-durations-for-MMC-and-EHCI.patch)14
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0018-beagleboard-mount-rootfs-RO-instead-of-RW-at-boot.patch (renamed from recipes-bsp/u-boot/u-boot/2011.09/0003-beagleboard-mount-rootfs-RO-instead-of-RW-at-boot.patch)16
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0019-BeagleBoard-config-Really-switch-to-ttyO2.patch (renamed from recipes-bsp/u-boot/u-boot/2011.09/0002-beagleboard-switch-to-ttyO2.patch)18
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0020-beagleboard-add-support-for-TCT-Beacon-board.patch (renamed from recipes-bsp/u-boot/u-boot/2011.09/0001-beagleboard-add-support-for-TCT-Beacon-board.patch)20
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09/0021-beagleboard-add-support-for-scanning-loop-through-ex.patch (renamed from recipes-bsp/u-boot/u-boot/2011.09/0001-beagleboard-add-support-for-scanning-loop-through-ex.patch)26
-rw-r--r--recipes-bsp/u-boot/u-boot_2011.09.bb37
23 files changed, 1901 insertions, 230 deletions
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0001-beagleboard-probe-DDC-bus-for-expansionboard-EEPROMS.patch b/recipes-bsp/u-boot/u-boot/2011.09/0001-beagleboard-probe-DDC-bus-for-expansionboard-EEPROMS.patch
deleted file mode 100644
index 4155d29a..00000000
--- a/recipes-bsp/u-boot/u-boot/2011.09/0001-beagleboard-probe-DDC-bus-for-expansionboard-EEPROMS.patch
+++ /dev/null
@@ -1,165 +0,0 @@
1From 559eb0f547267df0706d283974916b88d6b9fb7d Mon Sep 17 00:00:00 2001
2From: Koen Kooi <koen@dominion.thruhere.net>
3Date: Sun, 9 Oct 2011 15:55:05 +0200
4Subject: [PATCH] beagleboard: probe DDC bus for expansionboard EEPROMS as well
5
6Add beacon support as well, needs to get split into a seperate patch
7
8Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
9---
10 board/ti/beagle/beagle.c | 59 ++++++++++++++++++++++++++++++++++++++++
11 board/ti/beagle/beagle.h | 7 +++++
12 include/configs/omap3_beagle.h | 7 +++++
13 3 files changed, 73 insertions(+), 0 deletions(-)
14
15diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
16index 8cdceaf..f4e986c 100644
17--- a/board/ti/beagle/beagle.c
18+++ b/board/ti/beagle/beagle.c
19@@ -57,11 +57,14 @@ extern volatile struct ehci_hcor *hcor;
20 #define TWL4030_I2C_BUS 0
21 #define EXPANSION_EEPROM_I2C_BUS 1
22 #define EXPANSION_EEPROM_I2C_ADDRESS 0x50
23+#define DVI_EDID_I2C_BUS 2
24+#define DVI_EDID_I2C_ADDRESS 0x50
25
26 #define TINCANTOOLS_ZIPPY 0x01000100
27 #define TINCANTOOLS_ZIPPY2 0x02000100
28 #define TINCANTOOLS_TRAINER 0x04000100
29 #define TINCANTOOLS_SHOWDOG 0x03000100
30+#define TINCANTOOLS_BEACON 0x05000100
31 #define KBADC_BEAGLEFPGA 0x01000600
32 #define LW_BEAGLETOUCH 0x01000700
33 #define BRAINMUX_LCDOG 0x01000800
34@@ -69,6 +72,7 @@ extern volatile struct ehci_hcor *hcor;
35 #define BBTOYS_WIFI 0x01000B00
36 #define BBTOYS_VGA 0x02000B00
37 #define BBTOYS_LCD 0x03000B00
38+#define BBTOYS_ULCD 0x04000B00
39 #define BEAGLE_NO_EEPROM 0xffffffff
40
41 DECLARE_GLOBAL_DATA_PTR;
42@@ -82,6 +86,16 @@ static struct {
43 char env_setting[64];
44 } expansion_config;
45
46+static struct {
47+ unsigned int device_vendor;
48+ unsigned char revision;
49+ unsigned char content;
50+ char fab_revision[8];
51+ char env_var[16];
52+ char env_setting[64];
53+} edid_config;
54+
55+
56 /*
57 * Routine: board_init
58 * Description: Early hardware init.
59@@ -165,6 +179,33 @@ unsigned int get_expansion_id(void)
60 }
61
62 /*
63+ * Routine: get_edid
64+ * Description: This function checks for expansion board by checking I2C
65+ * bus 2 for the availability of an EEPROM
66+ * returns the device_vendor field from the EEPROM
67+ * The content can be either real EDID data or expansionboard data.
68+ * Only expansionboar data is currently supported
69+ */
70+unsigned int get_edid(void)
71+{
72+ i2c_set_bus_num(DVI_EDID_I2C_BUS);
73+
74+ /* return BEAGLE_NO_EEPROM if eeprom doesn't respond */
75+ if (i2c_probe(DVI_EDID_I2C_ADDRESS) == 1) {
76+ i2c_set_bus_num(TWL4030_I2C_BUS);
77+ return BEAGLE_NO_EEPROM;
78+ }
79+
80+ /* read EEPROM data */
81+ i2c_read(DVI_EDID_I2C_ADDRESS, 0, 1, (u8 *)&edid_config,
82+ sizeof(edid_config));
83+
84+ i2c_set_bus_num(TWL4030_I2C_BUS);
85+
86+ return edid_config.device_vendor;
87+}
88+
89+/*
90 * Configure DSS to display background color on DVID
91 * Configure VENC to display color bar on S-Video
92 */
93@@ -290,6 +331,13 @@ int misc_init_r(void)
94 setenv("defaultdisplay", "showdoglcd");
95 setenv("buddy", "showdog");
96 break;
97+ case TINCANTOOLS_BEACON:
98+ printf("Recognized Tincantools Beacon board (rev %d %s)\n",
99+ expansion_config.revision,
100+ expansion_config.fab_revision);
101+ MUX_TINCANTOOLS_BEACON();
102+ setenv("buddy", "beacon");
103+ break;
104 case KBADC_BEAGLEFPGA:
105 printf("Recognized KBADC Beagle FPGA board\n");
106 MUX_KBADC_BEAGLEFPGA();
107@@ -331,6 +379,17 @@ int misc_init_r(void)
108 if (expansion_config.content == 1)
109 setenv(expansion_config.env_var, expansion_config.env_setting);
110
111+ switch(get_edid()) {
112+ case BBTOYS_ULCD:
113+ printf("Recognized BeagleBoardToys universal LCD board on DDC bus\n");
114+ setenv("edid", "uLCD");
115+ break;
116+ default:
117+ printf("Unrecognized EEPROM content on DDC bus: %x\n",
118+ edid_config.device_vendor);
119+ setenv("edid", "unknown");
120+ }
121+
122 twl4030_power_init();
123 switch (get_board_revision()) {
124 case REVISION_XM_A:
125diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
126index 18bfaa8..6a9ad73 100644
127--- a/board/ti/beagle/beagle.h
128+++ b/board/ti/beagle/beagle.h
129@@ -456,6 +456,13 @@ const omap3_sysinfo sysinfo = {
130 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) /*GPIO_141*/\
131 MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) /*GPIO_162*/
132
133+#define MUX_TINCANTOOLS_BEACON() \
134+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
135+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
136+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
137+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
138+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
139+
140 #define MUX_KBADC_BEAGLEFPGA() \
141 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | DIS | M1)) /*MCSPI4_CLK*/\
142 MUX_VAL(CP(MCBSP1_DX), (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
143diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
144index 1369c89..73df658 100644
145--- a/include/configs/omap3_beagle.h
146+++ b/include/configs/omap3_beagle.h
147@@ -219,6 +224,7 @@
148 "console=ttyS2,115200n8\0" \
149 "mpurate=auto\0" \
150 "buddy=none "\
151+ "edid=none "\
152 "optargs=\0" \
153 "camera=none\0" \
154 "vram=12M\0" \
155@@ -235,6 +241,7 @@
156 "${optargs} " \
157 "mpurate=${mpurate} " \
158 "buddy=${buddy} "\
159+ "edid=${edid} "\
160 "camera=${camera} "\
161 "vram=${vram} " \
162 "omapfb.mode=dvi:${dvimode} " \
163--
1641.6.6.1
165
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0001-omap3-mem-Comment-enable_gpmc_cs_config-more.patch b/recipes-bsp/u-boot/u-boot/2011.09/0001-omap3-mem-Comment-enable_gpmc_cs_config-more.patch
new file mode 100644
index 00000000..38da967d
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0001-omap3-mem-Comment-enable_gpmc_cs_config-more.patch
@@ -0,0 +1,56 @@
1From 81630b54970a9274140b1c14caa31da6331a62fa Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:47:58 +0000
4Subject: [PATCH 01/21] omap3: mem: Comment enable_gpmc_cs_config more
5
6Expand the "enable the config" comment to explain what the bit shifts
7are and define out two of the magic numbers.
8
9Signed-off-by: Tom Rini <trini@ti.com>
10Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
11---
12 arch/arm/cpu/armv7/omap3/mem.c | 12 +++++++++---
13 arch/arm/include/asm/arch-omap3/mem.h | 4 ++++
14 2 files changed, 13 insertions(+), 3 deletions(-)
15
16diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
17index a01c303..2f1efea 100644
18--- a/arch/arm/cpu/armv7/omap3/mem.c
19+++ b/arch/arm/cpu/armv7/omap3/mem.c
20@@ -105,9 +105,15 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
21 writel(gpmc_config[3], &cs->config4);
22 writel(gpmc_config[4], &cs->config5);
23 writel(gpmc_config[5], &cs->config6);
24- /* Enable the config */
25- writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
26- (1 << 6)), &cs->config7);
27+
28+ /*
29+ * Enable the config. size is the CS size and goes in
30+ * bits 11:8. We set bit 6 to enable this CS and the base
31+ * address goes into bits 5:0.
32+ */
33+ writel((size << 8) | (GPMC_CS_ENABLE << 6) |
34+ ((base >> 24) & GPMC_BASEADDR_MASK),
35+ &cs->config7);
36 sdelay(2000);
37 }
38
39diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
40index db6a696..abf4e82 100644
41--- a/arch/arm/include/asm/arch-omap3/mem.h
42+++ b/arch/arm/include/asm/arch-omap3/mem.h
43@@ -259,6 +259,10 @@ enum {
44 #define GPMC_SIZE_32M 0xE
45 #define GPMC_SIZE_16M 0xF
46
47+#define GPMC_BASEADDR_MASK 0x3F
48+
49+#define GPMC_CS_ENABLE 0x1
50+
51 #define SMNAND_GPMC_CONFIG1 0x00000800
52 #define SMNAND_GPMC_CONFIG2 0x00141400
53 #define SMNAND_GPMC_CONFIG3 0x00141400
54--
551.7.2.5
56
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0002-OMAP3-Update-SDRC-dram_init-to-always-call-make_cs1_.patch b/recipes-bsp/u-boot/u-boot/2011.09/0002-OMAP3-Update-SDRC-dram_init-to-always-call-make_cs1_.patch
new file mode 100644
index 00000000..cb128738
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0002-OMAP3-Update-SDRC-dram_init-to-always-call-make_cs1_.patch
@@ -0,0 +1,66 @@
1From 42db3ebdd76628017e7ab83752e9b288ec4f26a0 Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:47:59 +0000
4Subject: [PATCH 02/21] OMAP3: Update SDRC dram_init to always call make_cs1_contiguous()
5
6We update the comment in make_cs1_contiguous() to be a little bit
7more clear (it's been copy/pasted from other silicons) and then
8explain in dram_init() why we need to always try this.
9
10Note that in the previous behavior we were always calling this on
11boards that never had cs1 populated anyhow so making sure we do
12this always is fine and will correct things like omap3evm detecting
13an invalid amount of memory (384MB).
14
15Signed-off-by: Tom Rini <trini@ti.com>
16Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
17---
18 arch/arm/cpu/armv7/omap3/sdrc.c | 23 +++++++++++------------
19 1 files changed, 11 insertions(+), 12 deletions(-)
20
21diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
22index 0dd1955..66ce33f 100644
23--- a/arch/arm/cpu/armv7/omap3/sdrc.c
24+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
25@@ -58,10 +58,9 @@ u32 is_mem_sdr(void)
26
27 /*
28 * make_cs1_contiguous -
29- * - For es2 and above remap cs1 behind cs0 to allow command line
30- * mem=xyz use all memory with out discontinuous support compiled in.
31- * Could do it at the ATAG, but there really is two banks...
32- * - Called as part of 2nd phase DDR init.
33+ * - When we have CS1 populated we want to have it mapped after cs0 to allow
34+ * command line mem=xyz use all memory with out discontinuous support
35+ * compiled in. We could do it in the ATAG, but there really is two banks...
36 */
37 void make_cs1_contiguous(void)
38 {
39@@ -207,16 +206,16 @@ int dram_init(void)
40
41 size0 = get_sdr_cs_size(CS0);
42 /*
43- * If a second bank of DDR is attached to CS1 this is
44- * where it can be started. Early init code will init
45- * memory on CS0.
46+ * We always need to have cs_cfg point at where the second
47+ * bank would be, if present. Failure to do so can lead to
48+ * strange situations where memory isn't detected and
49+ * configured correctly. CS0 will already have been setup
50+ * at this point.
51 */
52- if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
53- do_sdrc_init(CS1, NOT_EARLY);
54- make_cs1_contiguous();
55+ make_cs1_contiguous();
56+ do_sdrc_init(CS1, NOT_EARLY);
57+ size1 = get_sdr_cs_size(CS1);
58
59- size1 = get_sdr_cs_size(CS1);
60- }
61 gd->ram_size = size0 + size1;
62
63 return 0;
64--
651.7.2.5
66
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0003-OMAP3-Add-a-helper-function-to-set-timings-in-SDRC.patch b/recipes-bsp/u-boot/u-boot/2011.09/0003-OMAP3-Add-a-helper-function-to-set-timings-in-SDRC.patch
new file mode 100644
index 00000000..71e49afd
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0003-OMAP3-Add-a-helper-function-to-set-timings-in-SDRC.patch
@@ -0,0 +1,172 @@
1From a186210c5003db4df2a4f97bd6d4cb2dc616a591 Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:48:00 +0000
4Subject: [PATCH 03/21] OMAP3: Add a helper function to set timings in SDRC
5
6Since we go through the sequence to setup the SDRC timings more than
7once, break this logic out into its own function and have that function
8call mem_ok() to make sure the memory is usable.
9
10Signed-off-by: Tom Rini <trini@ti.com>
11Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
12---
13 arch/arm/cpu/armv7/omap3/sdrc.c | 116 ++++++++++++++++++++------------------
14 1 files changed, 61 insertions(+), 55 deletions(-)
15
16diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
17index 66ce33f..2756024 100644
18--- a/arch/arm/cpu/armv7/omap3/sdrc.c
19+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
20@@ -108,14 +108,45 @@ u32 get_sdr_cs_offset(u32 cs)
21 }
22
23 /*
24+ * write_sdrc_timings -
25+ * - Takes CS and associated timings and initalize SDRAM
26+ * - Test CS to make sure it's OK for use
27+ */
28+static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
29+ u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr)
30+{
31+ /* Setup timings we got from the board. */
32+ writel(mcfg, &sdrc_base->cs[cs].mcfg);
33+ writel(ctrla, &sdrc_actim_base->ctrla);
34+ writel(ctrlb, &sdrc_actim_base->ctrlb);
35+ writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
36+ writel(CMD_NOP, &sdrc_base->cs[cs].manual);
37+ writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
38+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
39+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
40+ writel(mr, &sdrc_base->cs[cs].mr);
41+
42+ /*
43+ * Test ram in this bank
44+ * Disable if bad or not present
45+ */
46+ if (!mem_ok(cs))
47+ writel(0, &sdrc_base->cs[cs].mcfg);
48+}
49+
50+/*
51 * do_sdrc_init -
52- * - Initialize the SDRAM for use.
53- * - code called once in C-Stack only context for CS0 and a possible 2nd
54- * time depending on memory configuration from stack+global context
55+ * - Code called once in C-Stack only context for CS0 and with early being
56+ * true and a possible 2nd time depending on memory configuration from
57+ * stack+global context.
58 */
59 void do_sdrc_init(u32 cs, u32 early)
60 {
61 struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
62+ u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr;
63+
64+ sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
65+ sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
66
67 if (early) {
68 /* reset sdrc controller */
69@@ -127,73 +158,48 @@ void do_sdrc_init(u32 cs, u32 early)
70 /* setup sdrc to ball mux */
71 writel(SDRC_SHARING, &sdrc_base->sharing);
72
73- /* Disable Power Down of CKE cuz of 1 CKE on combo part */
74+ /* Disable Power Down of CKE because of 1 CKE on combo part */
75 writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
76 &sdrc_base->power);
77
78 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
79 sdelay(0x20000);
80- }
81-
82 /* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
83 * to prevent this to be build in non-SPL build */
84 #ifdef CONFIG_SPL_BUILD
85- /* If we use a SPL there is no x-loader nor config header so we have
86- * to do the job ourselfs
87- */
88- if (cs == CS0) {
89- sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
90-
91- /* General SDRC config */
92- writel(V_MCFG, &sdrc_base->cs[cs].mcfg);
93- writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl);
94-
95- /* AC timings */
96- writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla);
97- writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
98-
99- /* Initialize */
100- writel(CMD_NOP, &sdrc_base->cs[cs].manual);
101- writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
102- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
103- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
104+ /*
105+ * If we use a SPL there is no x-loader nor config header so
106+ * we have to do the job ourselfs
107+ */
108+
109+ mcfg = V_MCFG;
110+ ctrla = V_ACTIMA_165;
111+ ctrlb = V_ACTIMB_165;
112+ rfr_ctrl = V_RFR_CTRL;
113+ mr = V_MR;
114+
115+ write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
116+ rfr_ctrl, mr);
117+#endif
118
119- writel(V_MR, &sdrc_base->cs[cs].mr);
120 }
121-#endif
122
123 /*
124- * SDRC timings are set up by x-load or config header
125- * We don't need to redo them here.
126- * Older x-loads configure only CS0
127- * configure CS1 to handle this ommission
128+ * If we aren't using SPL we have been loaded by some
129+ * other means which may not have correctly initialized
130+ * both CS0 and CS1 (such as some older versions of x-loader)
131+ * so we may be asked now to setup CS1.
132 */
133 if (cs == CS1) {
134- sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
135- sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
136- writel(readl(&sdrc_base->cs[CS0].mcfg),
137- &sdrc_base->cs[CS1].mcfg);
138- writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
139- &sdrc_base->cs[CS1].rfr_ctrl);
140- writel(readl(&sdrc_actim_base0->ctrla),
141- &sdrc_actim_base1->ctrla);
142- writel(readl(&sdrc_actim_base0->ctrlb),
143- &sdrc_actim_base1->ctrlb);
144-
145- writel(CMD_NOP, &sdrc_base->cs[cs].manual);
146- writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
147- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
148- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
149- writel(readl(&sdrc_base->cs[CS0].mr),
150- &sdrc_base->cs[CS1].mr);
151- }
152+ mcfg = readl(&sdrc_base->cs[CS0].mcfg),
153+ rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
154+ ctrla = readl(&sdrc_actim_base0->ctrla),
155+ ctrlb = readl(&sdrc_actim_base0->ctrlb);
156+ mr = readl(&sdrc_base->cs[CS0].mr);
157+ write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb,
158+ rfr_ctrl, mr);
159
160- /*
161- * Test ram in this bank
162- * Disable if bad or not present
163- */
164- if (!mem_ok(cs))
165- writel(0, &sdrc_base->cs[cs].mcfg);
166+ }
167 }
168
169 /*
170--
1711.7.2.5
172
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0004-OMAP3-Change-mem_ok-to-clear-again-after-reading-bac.patch b/recipes-bsp/u-boot/u-boot/2011.09/0004-OMAP3-Change-mem_ok-to-clear-again-after-reading-bac.patch
new file mode 100644
index 00000000..30d912c5
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0004-OMAP3-Change-mem_ok-to-clear-again-after-reading-bac.patch
@@ -0,0 +1,30 @@
1From 0cf0d611823f6e1f3b63f9233c145a3940a89694 Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:48:01 +0000
4Subject: [PATCH 04/21] OMAP3: Change mem_ok to clear again after reading back
5
6It's possible to need to call this function on the same banks multiple
7times so we want to be sure that 'pos A' is cleared out again at the
8end.
9
10Signed-off-by: Tom Rini <trini@ti.com>
11Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
12---
13 arch/arm/cpu/armv7/omap3/mem.c | 1 +
14 1 files changed, 1 insertions(+), 0 deletions(-)
15
16diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
17index 2f1efea..2fe5ac7 100644
18--- a/arch/arm/cpu/armv7/omap3/mem.c
19+++ b/arch/arm/cpu/armv7/omap3/mem.c
20@@ -86,6 +86,7 @@ u32 mem_ok(u32 cs)
21 writel(0x0, addr + 4); /* remove pattern off the bus */
22 val1 = readl(addr + 0x400); /* get pos A value */
23 val2 = readl(addr); /* get val2 */
24+ writel(0x0, addr + 0x400); /* clear pos A */
25
26 if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
27 return 0;
28--
291.7.2.5
30
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0005-OMAP3-Remove-get_mem_type-prototype.patch b/recipes-bsp/u-boot/u-boot/2011.09/0005-OMAP3-Remove-get_mem_type-prototype.patch
new file mode 100644
index 00000000..ec1b5f76
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0005-OMAP3-Remove-get_mem_type-prototype.patch
@@ -0,0 +1,28 @@
1From 45ccdf2ba3aa6e5f258c463691c85ac4529246e6 Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:48:02 +0000
4Subject: [PATCH 05/21] OMAP3: Remove get_mem_type prototype
5
6This function doesn't exist for omap3
7
8Signed-off-by: Tom Rini <trini@ti.com>
9Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
10---
11 arch/arm/include/asm/arch-omap3/sys_proto.h | 1 -
12 1 files changed, 0 insertions(+), 1 deletions(-)
13
14diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
15index 995e7cb..9e64410 100644
16--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
17+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
18@@ -49,7 +49,6 @@ void set_muxconf_regs(void);
19 u32 get_cpu_family(void);
20 u32 get_cpu_rev(void);
21 u32 get_sku_id(void);
22-u32 get_mem_type(void);
23 u32 get_sysboot_value(void);
24 u32 is_gpmc_muxed(void);
25 u32 get_gpmc0_type(void);
26--
271.7.2.5
28
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0006-omap3-mem-Add-MCFG-helper-macro.patch b/recipes-bsp/u-boot/u-boot/2011.09/0006-omap3-mem-Add-MCFG-helper-macro.patch
new file mode 100644
index 00000000..475febff
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0006-omap3-mem-Add-MCFG-helper-macro.patch
@@ -0,0 +1,97 @@
1From bd50b147ff61a5203815296eac726b0a244c3cb2 Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:48:03 +0000
4Subject: [PATCH 06/21] omap3: mem: Add MCFG helper macro
5
6This adds an MCFG macro to calculate the correct value, similar to
7the ACTIMA/ACTIMB macros and adds a comment that all of the potential
8values here are documented in the TRM. Then we convert the Micron
9value to use this macro.
10
11Signed-off-by: Tom Rini <trini@ti.com>
12Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
13---
14 arch/arm/include/asm/arch-omap3/mem.h | 46 +++++++++++++++++++++-----------
15 1 files changed, 30 insertions(+), 16 deletions(-)
16
17diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
18index abf4e82..12ff3b0 100644
19--- a/arch/arm/include/asm/arch-omap3/mem.h
20+++ b/arch/arm/include/asm/arch-omap3/mem.h
21@@ -39,6 +39,12 @@ enum {
22
23 #define EARLY_INIT 1
24
25+/*
26+ * For a full explanation of these registers and values please see
27+ * the Technical Reference Manual (TRM) for any of the processors in
28+ * this family.
29+ */
30+
31 /* Slower full frequency range default timings for x32 operation*/
32 #define SDRC_SHARING 0x00000100
33 #define SDRC_MR_0_SDR 0x00000031
34@@ -86,6 +92,27 @@ enum {
35 ACTIM_CTRLB_TXP(b) | \
36 ACTIM_CTRLB_TXSR(d)
37
38+/*
39+ * Values used in the MCFG register. Only values we use today
40+ * are defined and the rest can be found in the TRM. Unless otherwise
41+ * noted all fields are one bit.
42+ */
43+#define V_MCFG_RAMTYPE_DDR (0x1)
44+#define V_MCFG_DEEPPD_EN (0x1 << 3)
45+#define V_MCFG_B32NOT16_32 (0x1 << 4)
46+#define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
47+#define V_MCFG_RAMSIZE(a) ((((a)/(1024*1024))/2) << 8) /* 8:17 */
48+#define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19)
49+#define V_MCFG_CASWIDTH_10B (0x5 << 20) /* 20:22 */
50+#define V_MCFG_RASWIDTH(a) ((a) << 24) /* 24:26 */
51+
52+/* Macro to construct MCFG */
53+#define MCFG(a, b) \
54+ V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B | \
55+ V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) | \
56+ V_MCFG_BANKALLOCATION_RBC | \
57+ V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
58+
59 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
60 #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
61 /* 15/6 + 18/6 = 5.5 -> 6 */
62@@ -138,21 +165,8 @@ enum {
63 ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
64 MICRON_TXP_165, MICRON_XSR_165)
65
66-#define MICRON_RAMTYPE 0x1
67-#define MICRON_DDRTYPE 0x0
68-#define MICRON_DEEPPD 0x1
69-#define MICRON_B32NOT16 0x1
70-#define MICRON_BANKALLOCATION 0x2
71-#define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2)
72-#define MICRON_ADDRMUXLEGACY 0x1
73-#define MICRON_CASWIDTH 0x5
74-#define MICRON_RASWIDTH 0x2
75-#define MICRON_LOCKSTATUS 0x0
76-#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \
77- (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \
78- (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \
79- (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \
80- (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
81+#define MICRON_RASWIDTH 0x2
82+#define MICRON_V_MCFG(size) MCFG((size), MICRON_RASWIDTH)
83
84 #define MICRON_ARCV 2030
85 #define MICRON_ARE 0x1
86@@ -199,7 +213,7 @@ enum {
87 #ifdef CONFIG_OMAP3_MICRON_DDR
88 #define V_ACTIMA_165 MICRON_V_ACTIMA_165
89 #define V_ACTIMB_165 MICRON_V_ACTIMB_165
90-#define V_MCFG MICRON_V_MCFG
91+#define V_MCFG MICRON_V_MCFG(PHYS_SDRAM_1_SIZE)
92 #define V_RFR_CTRL MICRON_V_RFR_CTRL
93 #define V_MR MICRON_V_MR
94 #endif
95--
961.7.2.5
97
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0007-OMAP3-Add-optimal-SDRC-autorefresh-control-values.patch b/recipes-bsp/u-boot/u-boot/2011.09/0007-OMAP3-Add-optimal-SDRC-autorefresh-control-values.patch
new file mode 100644
index 00000000..2024094c
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0007-OMAP3-Add-optimal-SDRC-autorefresh-control-values.patch
@@ -0,0 +1,59 @@
1From 67ea79f7a99d7168915a5db8a577814ec501774e Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:48:04 +0000
4Subject: [PATCH 07/21] OMAP3: Add optimal SDRC autorefresh control values
5
6This adds the optimal SDRC autorefresh control register values for
7100Mhz, 133MHz, 165MHz and 200MHz clocks. We switch to using this
8to provide the default 165MHz value.
9
10Signed-off-by: Tom Rini <trini@ti.com>
11Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
12---
13 arch/arm/include/asm/arch-omap3/mem.h | 16 +++++++++++-----
14 1 files changed, 11 insertions(+), 5 deletions(-)
15
16diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
17index 12ff3b0..912c737 100644
18--- a/arch/arm/include/asm/arch-omap3/mem.h
19+++ b/arch/arm/include/asm/arch-omap3/mem.h
20@@ -49,6 +49,16 @@ enum {
21 #define SDRC_SHARING 0x00000100
22 #define SDRC_MR_0_SDR 0x00000031
23
24+/*
25+ * SDRC autorefresh control values. This register consists of autorefresh
26+ * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The
27+ * counter is a result of ( tREFI / tCK ) - 50.
28+ */
29+#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
30+#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
31+#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
32+#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
33+
34 #define DLL_OFFSET 0
35 #define DLL_WRITEDDRCLKX2DIS 1
36 #define DLL_ENADLL 1
37@@ -168,10 +178,6 @@ enum {
38 #define MICRON_RASWIDTH 0x2
39 #define MICRON_V_MCFG(size) MCFG((size), MICRON_RASWIDTH)
40
41-#define MICRON_ARCV 2030
42-#define MICRON_ARE 0x1
43-#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE))
44-
45 #define MICRON_BL 0x2
46 #define MICRON_SIL 0x0
47 #define MICRON_CASL 0x3
48@@ -214,7 +220,7 @@ enum {
49 #define V_ACTIMA_165 MICRON_V_ACTIMA_165
50 #define V_ACTIMB_165 MICRON_V_ACTIMB_165
51 #define V_MCFG MICRON_V_MCFG(PHYS_SDRAM_1_SIZE)
52-#define V_RFR_CTRL MICRON_V_RFR_CTRL
53+#define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
54 #define V_MR MICRON_V_MR
55 #endif
56
57--
581.7.2.5
59
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0008-OMAP3-Suffix-all-Micron-memory-timing-parts-with-the.patch b/recipes-bsp/u-boot/u-boot/2011.09/0008-OMAP3-Suffix-all-Micron-memory-timing-parts-with-the.patch
new file mode 100644
index 00000000..79f4efb6
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0008-OMAP3-Suffix-all-Micron-memory-timing-parts-with-the.patch
@@ -0,0 +1,55 @@
1From 0e9f4ab3cafdc1de638ab7a603a750acd4688967 Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:48:05 +0000
4Subject: [PATCH 08/21] OMAP3: Suffix all Micron memory timing parts with their speed
5
6Signed-off-by: Tom Rini <trini@ti.com>
7Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
8---
9 arch/arm/include/asm/arch-omap3/mem.h | 21 +++++++++++----------
10 1 files changed, 11 insertions(+), 10 deletions(-)
11
12diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
13index 912c737..4f996d9 100644
14--- a/arch/arm/include/asm/arch-omap3/mem.h
15+++ b/arch/arm/include/asm/arch-omap3/mem.h
16@@ -175,15 +175,16 @@ enum {
17 ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
18 MICRON_TXP_165, MICRON_XSR_165)
19
20-#define MICRON_RASWIDTH 0x2
21-#define MICRON_V_MCFG(size) MCFG((size), MICRON_RASWIDTH)
22+#define MICRON_RASWIDTH_165 0x2
23+#define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165)
24
25-#define MICRON_BL 0x2
26-#define MICRON_SIL 0x0
27-#define MICRON_CASL 0x3
28-#define MICRON_WBST 0x0
29-#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \
30- (MICRON_SIL << 3) | (MICRON_BL))
31+#define MICRON_BL_165 0x2
32+#define MICRON_SIL_165 0x0
33+#define MICRON_CASL_165 0x3
34+#define MICRON_WBST_165 0x0
35+#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \
36+ (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
37+ (MICRON_BL_165))
38
39 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
40 #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
41@@ -219,9 +220,9 @@ enum {
42 #ifdef CONFIG_OMAP3_MICRON_DDR
43 #define V_ACTIMA_165 MICRON_V_ACTIMA_165
44 #define V_ACTIMB_165 MICRON_V_ACTIMB_165
45-#define V_MCFG MICRON_V_MCFG(PHYS_SDRAM_1_SIZE)
46+#define V_MCFG MICRON_V_MCFG_165(PHYS_SDRAM_1_SIZE)
47 #define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
48-#define V_MR MICRON_V_MR
49+#define V_MR MICRON_V_MR_165
50 #endif
51
52 #ifdef CONFIG_OMAP3_NUMONYX_DDR
53--
541.7.2.5
55
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0009-OMAP3-SPL-Rework-memory-initalization-and-devkit8000.patch b/recipes-bsp/u-boot/u-boot/2011.09/0009-OMAP3-SPL-Rework-memory-initalization-and-devkit8000.patch
new file mode 100644
index 00000000..7c12e7a5
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0009-OMAP3-SPL-Rework-memory-initalization-and-devkit8000.patch
@@ -0,0 +1,174 @@
1From bf66bbd9347874b6ad13f7747288327e968022d2 Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:48:06 +0000
4Subject: [PATCH 09/21] OMAP3 SPL: Rework memory initalization and devkit8000 support
5
6This changes to making the board be responsible for providing the
7memory initialization timings in SPL and converts the devkit8000
8to this framework. In SPL we try and initialize both CS0 and CS1.
9
10Cc: Frederik Kriewitz <frederik@kriewitz.eu>
11Signed-off-by: Tom Rini <trini@ti.com>
12Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
13---
14 arch/arm/cpu/armv7/omap3/sdrc.c | 28 ++++++++++++++------------
15 arch/arm/include/asm/arch-omap3/mem.h | 26 -------------------------
16 arch/arm/include/asm/arch-omap3/sys_proto.h | 2 +
17 board/timll/devkit8000/devkit8000.c | 21 ++++++++++++++++++++
18 include/configs/devkit8000.h | 5 ----
19 5 files changed, 38 insertions(+), 44 deletions(-)
20
21diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
22index 2756024..a27b4b1 100644
23--- a/arch/arm/cpu/armv7/omap3/sdrc.c
24+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
25@@ -148,6 +148,18 @@ void do_sdrc_init(u32 cs, u32 early)
26 sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
27 sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
28
29+ /*
30+ * When called in the early context this may be SPL and we will
31+ * need to set all of the timings. This ends up being board
32+ * specific so we call a helper function to take care of this
33+ * for us. Otherwise, to be safe, we need to copy the settings
34+ * from the first bank to the second. We will setup CS0,
35+ * then set cs_cfg to the appropriate value then try and
36+ * setup CS1.
37+ */
38+#ifdef CONFIG_SPL_BUILD
39+ get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr);
40+#endif
41 if (early) {
42 /* reset sdrc controller */
43 writel(SOFTRESET, &sdrc_base->sysconfig);
44@@ -164,22 +176,12 @@ void do_sdrc_init(u32 cs, u32 early)
45
46 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
47 sdelay(0x20000);
48-/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
49- * to prevent this to be build in non-SPL build */
50 #ifdef CONFIG_SPL_BUILD
51- /*
52- * If we use a SPL there is no x-loader nor config header so
53- * we have to do the job ourselfs
54- */
55-
56- mcfg = V_MCFG;
57- ctrla = V_ACTIMA_165;
58- ctrlb = V_ACTIMB_165;
59- rfr_ctrl = V_RFR_CTRL;
60- mr = V_MR;
61-
62 write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
63 rfr_ctrl, mr);
64+ make_cs1_contiguous();
65+ write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb,
66+ rfr_ctrl, mr);
67 #endif
68
69 }
70diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
71index 4f996d9..09f5872 100644
72--- a/arch/arm/include/asm/arch-omap3/mem.h
73+++ b/arch/arm/include/asm/arch-omap3/mem.h
74@@ -212,32 +212,6 @@ enum {
75 ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
76 NUMONYX_TXP_165, NUMONYX_XSR_165)
77
78-#ifdef CONFIG_OMAP3_INFINEON_DDR
79-#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
80-#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
81-#endif
82-
83-#ifdef CONFIG_OMAP3_MICRON_DDR
84-#define V_ACTIMA_165 MICRON_V_ACTIMA_165
85-#define V_ACTIMB_165 MICRON_V_ACTIMB_165
86-#define V_MCFG MICRON_V_MCFG_165(PHYS_SDRAM_1_SIZE)
87-#define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz
88-#define V_MR MICRON_V_MR_165
89-#endif
90-
91-#ifdef CONFIG_OMAP3_NUMONYX_DDR
92-#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
93-#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
94-#endif
95-
96-#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
97-#error "Please choose the right DDR type in config header"
98-#endif
99-
100-#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL))
101-#error "Please choose the right DDR type in config header"
102-#endif
103-
104 /*
105 * GPMC settings -
106 * Definitions is as per the following format
107diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
108index 9e64410..80e167b 100644
109--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
110+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
111@@ -38,6 +38,8 @@ void per_clocks_enable(void);
112 void memif_init(void);
113 void sdrc_init(void);
114 void do_sdrc_init(u32, u32);
115+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
116+ u32 *mr);
117 void emif4_init(void);
118 void gpmc_init(void);
119 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
120diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
121index fee0dff..b06aab6 100644
122--- a/board/timll/devkit8000/devkit8000.c
123+++ b/board/timll/devkit8000/devkit8000.c
124@@ -138,3 +138,24 @@ int board_eth_init(bd_t *bis)
125 return dm9000_initialize(bis);
126 }
127 #endif
128+
129+/*
130+ * Routine: get_board_mem_timings
131+ * Description: If we use SPL then there is no x-loader nor config header
132+ * so we have to setup the DDR timings ourself on the first bank. This
133+ * provides the timing values back to the function that configures
134+ * the memory. We have either one or two banks of 128MB DDR.
135+ */
136+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
137+ u32 *mr)
138+{
139+ /* General SDRC config */
140+ *mcfg = MICRON_V_MCFG_165(128 << 20);
141+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
142+
143+ /* AC timings */
144+ *ctrla = MICRON_V_ACTIMA_165;
145+ *ctrlb = MICRON_V_ACTIMB_165;
146+
147+ *mr = MICRON_V_MR_165;
148+}
149diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
150index e1743dc..b3e60cd 100644
151--- a/include/configs/devkit8000.h
152+++ b/include/configs/devkit8000.h
153@@ -68,10 +68,6 @@
154 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
155
156 /* Hardware drivers */
157-
158-/* DDR - I use Micron DDR */
159-#define CONFIG_OMAP3_MICRON_DDR 1
160-
161 /* DM9000 */
162 #define CONFIG_NET_RETRY_COUNT 20
163 #define CONFIG_DRIVER_DM9000 1
164@@ -284,7 +280,6 @@
165 /* Physical Memory Map */
166 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
167 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
168-#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */
169 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
170
171 /* SDRAM Bank Allocation method */
172--
1731.7.2.5
174
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0010-OMAP3-SPL-Add-identify_nand_chip-function.patch b/recipes-bsp/u-boot/u-boot/2011.09/0010-OMAP3-SPL-Add-identify_nand_chip-function.patch
new file mode 100644
index 00000000..94ef0de3
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0010-OMAP3-SPL-Add-identify_nand_chip-function.patch
@@ -0,0 +1,142 @@
1From 290ebce5d39112ce80c6180206952aa5cc0ea871 Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:48:07 +0000
4Subject: [PATCH 10/21] OMAP3 SPL: Add identify_nand_chip function
5
6A number of boards are populated with a PoP chip for both DDR and NAND
7memory. Other boards may simply use this as an easy way to identify
8board revs. So we provide a function that can be called early to reset
9the NAND chip and return the result of NAND_CMD_READID. All of this
10code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
11
12Signed-off-by: Tom Rini <trini@ti.com>
13Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
14---
15 arch/arm/cpu/armv7/omap3/Makefile | 3 +
16 arch/arm/cpu/armv7/omap3/spl_id_nand.c | 87 +++++++++++++++++++++++++++
17 arch/arm/include/asm/arch-omap3/sys_proto.h | 1 +
18 3 files changed, 91 insertions(+), 0 deletions(-)
19 create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c
20
21diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile
22index 8e85891..4b38e45 100644
23--- a/arch/arm/cpu/armv7/omap3/Makefile
24+++ b/arch/arm/cpu/armv7/omap3/Makefile
25@@ -31,6 +31,9 @@ COBJS += board.o
26 COBJS += clock.o
27 COBJS += mem.o
28 COBJS += sys_info.o
29+ifdef CONFIG_SPL_BUILD
30+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o
31+endif
32
33 COBJS-$(CONFIG_EMIF4) += emif4.o
34 COBJS-$(CONFIG_SDRC) += sdrc.o
35diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
36new file mode 100644
37index 0000000..0871fc9
38--- /dev/null
39+++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
40@@ -0,0 +1,87 @@
41+/*
42+ * (C) Copyright 2011
43+ * Texas Instruments, <www.ti.com>
44+ *
45+ * Author :
46+ * Tom Rini <trini@ti.com>
47+ *
48+ * Initial Code from:
49+ * Richard Woodruff <r-woodruff2@ti.com>
50+ * Jian Zhang <jzhang@ti.com>
51+ *
52+ * This program is free software; you can redistribute it and/or
53+ * modify it under the terms of the GNU General Public License as
54+ * published by the Free Software Foundation; either version 2 of
55+ * the License, or (at your option) any later version.
56+ *
57+ * This program is distributed in the hope that it will be useful,
58+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
59+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
60+ * GNU General Public License for more details.
61+ *
62+ * You should have received a copy of the GNU General Public License
63+ * along with this program; if not, write to the Free Software
64+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
65+ * MA 02111-1307 USA
66+ */
67+
68+#include <common.h>
69+#include <linux/mtd/nand.h>
70+#include <asm/io.h>
71+#include <asm/arch/sys_proto.h>
72+#include <asm/arch/mem.h>
73+
74+static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
75+
76+/* nand_command: Send a flash command to the flash chip */
77+static void nand_command(u8 command)
78+{
79+ writeb(command, &gpmc_config->cs[0].nand_cmd);
80+
81+ if (command == NAND_CMD_RESET) {
82+ unsigned char ret_val;
83+ writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
84+ do {
85+ /* Wait until ready */
86+ ret_val = readl(&gpmc_config->cs[0].nand_dat);
87+ } while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY);
88+ }
89+}
90+
91+/*
92+ * Many boards will want to know the results of the NAND_CMD_READID command
93+ * in order to decide what to do about DDR initialization. This function
94+ * allows us to do that very early and to pass those results back to the
95+ * board so it can make whatever decisions need to be made.
96+ */
97+void identify_nand_chip(int *mfr, int *id)
98+{
99+ /* Make sure that we have setup GPMC for NAND correctly. */
100+ writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
101+ writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
102+ writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
103+ writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
104+ writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
105+ writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
106+
107+ /*
108+ * Enable the config. The CS size goes in bits 11:8. We set
109+ * bit 6 to enable the CS and the base address goes into bits 5:0.
110+ */
111+ writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) |
112+ ((NAND_BASE >> 24) & GPMC_BASEADDR_MASK),
113+ &gpmc_config->cs[0].config7);
114+
115+ sdelay(2000);
116+
117+ /* Issue a RESET and then READID */
118+ nand_command(NAND_CMD_RESET);
119+ nand_command(NAND_CMD_READID);
120+
121+ /* Set the address to read to 0x0 */
122+ writeb(0x0, &gpmc_config->cs[0].nand_adr);
123+
124+ /* Read off the manufacturer and device id. */
125+ *mfr = readb(&gpmc_config->cs[0].nand_dat);
126+ *id = readb(&gpmc_config->cs[0].nand_dat);
127+}
128diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
129index 80e167b..e5031d5 100644
130--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
131+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
132@@ -40,6 +40,7 @@ void sdrc_init(void);
133 void do_sdrc_init(u32, u32);
134 void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
135 u32 *mr);
136+void identify_nand_chip(int *mfr, int *id);
137 void emif4_init(void);
138 void gpmc_init(void);
139 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
140--
1411.7.2.5
142
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0011-OMAP3-Add-SPL-support-to-Beagleboard.patch b/recipes-bsp/u-boot/u-boot/2011.09/0011-OMAP3-Add-SPL-support-to-Beagleboard.patch
new file mode 100644
index 00000000..a32c21d1
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0011-OMAP3-Add-SPL-support-to-Beagleboard.patch
@@ -0,0 +1,315 @@
1From 4ce72b52b5eeb172c1118fbd6e23d49eeec30ad2 Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:48:08 +0000
4Subject: [PATCH 11/21] OMAP3: Add SPL support to Beagleboard
5
6This introduces 200MHz Micron parts timing information based on x-loader
7to <asm/arch-omap3/mem.h> and Numonyx MCFG calculation. The memory init
8logic is also based on what x-loader does in these cases. Note that
9while previously u-boot would be flashed in with SW ECC in this case it
10now must be flashed with HW ECC. We also change CONFIG_SYS_TEXT_BASE to
110x80100000.
12
13Cc: Dirk Behme <dirk.behme@gmail.com>
14Beagleboard rev C5, xM rev A:
15Tested-by: Tom Rini <trini@ti.com>
16Beagleboard xM rev C:
17Tested-by: Matt Ranostay <mranostay@gmail.com>
18Beagleboard rev B7, C2, xM rev B:
19Tested-by: Matt Porter <mporter@ti.com>
20Signed-off-by: Tom Rini <trini@ti.com>
21Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
22---
23 arch/arm/include/asm/arch-omap3/mem.h | 29 +++++++++++++
24 board/ti/beagle/beagle.c | 71 ++++++++++++++++++++++++++++++++-
25 board/ti/beagle/config.mk | 33 ---------------
26 include/configs/omap3_beagle.h | 59 +++++++++++++++++++++++++--
27 4 files changed, 153 insertions(+), 39 deletions(-)
28 delete mode 100644 board/ti/beagle/config.mk
29
30diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
31index 09f5872..4ea5f74 100644
32--- a/arch/arm/include/asm/arch-omap3/mem.h
33+++ b/arch/arm/include/asm/arch-omap3/mem.h
34@@ -186,6 +186,32 @@ enum {
35 (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
36 (MICRON_BL_165))
37
38+/* Micron part (200MHz optimized) 5 ns */
39+#define MICRON_TDAL_200 6
40+#define MICRON_TDPL_200 3
41+#define MICRON_TRRD_200 2
42+#define MICRON_TRCD_200 3
43+#define MICRON_TRP_200 3
44+#define MICRON_TRAS_200 8
45+#define MICRON_TRC_200 11
46+#define MICRON_TRFC_200 15
47+#define MICRON_V_ACTIMA_200 \
48+ ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \
49+ MICRON_TRAS_200, MICRON_TRP_200, \
50+ MICRON_TRCD_200, MICRON_TRRD_200, \
51+ MICRON_TDPL_200, MICRON_TDAL_200)
52+
53+#define MICRON_TWTR_200 2
54+#define MICRON_TCKE_200 4
55+#define MICRON_TXP_200 2
56+#define MICRON_XSR_200 23
57+#define MICRON_V_ACTIMB_200 \
58+ ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \
59+ MICRON_TXP_200, MICRON_XSR_200)
60+
61+#define MICRON_RASWIDTH_200 0x3
62+#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
63+
64 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
65 #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
66 /* 15/6 + 18/6 = 5.5 -> 6 */
67@@ -212,6 +238,9 @@ enum {
68 ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
69 NUMONYX_TXP_165, NUMONYX_XSR_165)
70
71+#define NUMONYX_RASWIDTH_165 0x4
72+#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165)
73+
74 /*
75 * GPMC settings -
76 * Definitions is as per the following format
77diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
78index 9482c5e..6a457cb 100644
79--- a/board/ti/beagle/beagle.c
80+++ b/board/ti/beagle/beagle.c
81@@ -1,5 +1,5 @@
82 /*
83- * (C) Copyright 2004-2008
84+ * (C) Copyright 2004-2011
85 * Texas Instruments, <www.ti.com>
86 *
87 * Author :
88@@ -34,9 +34,11 @@
89 #include <status_led.h>
90 #endif
91 #include <twl4030.h>
92+#include <linux/mtd/nand.h>
93 #include <asm/io.h>
94 #include <asm/arch/mmc_host_def.h>
95 #include <asm/arch/mux.h>
96+#include <asm/arch/mem.h>
97 #include <asm/arch/sys_proto.h>
98 #include <asm/gpio.h>
99 #include <asm/mach-types.h>
100@@ -135,6 +137,69 @@ int get_board_revision(void)
101 return revision;
102 }
103
104+#ifdef CONFIG_SPL_BUILD
105+/*
106+ * Routine: get_board_mem_timings
107+ * Description: If we use SPL then there is no x-loader nor config header
108+ * so we have to setup the DDR timings ourself on both banks.
109+ */
110+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
111+ u32 *mr)
112+{
113+ int pop_mfr, pop_id;
114+
115+ /*
116+ * We need to identify what PoP memory is on the board so that
117+ * we know what timings to use. If we can't identify it then
118+ * we know it's an xM. To map the ID values please see nand_ids.c
119+ */
120+ identify_nand_chip(&pop_mfr, &pop_id);
121+
122+ *mr = MICRON_V_MR_165;
123+ switch (get_board_revision()) {
124+ case REVISION_C4:
125+ if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
126+ /* 512MB DDR */
127+ *mcfg = NUMONYX_V_MCFG_165(512 << 20);
128+ *ctrla = NUMONYX_V_ACTIMA_165;
129+ *ctrlb = NUMONYX_V_ACTIMB_165;
130+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
131+ break;
132+ } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
133+ /* Beagleboard Rev C5, 256MB DDR */
134+ *mcfg = MICRON_V_MCFG_200(256 << 20);
135+ *ctrla = MICRON_V_ACTIMA_200;
136+ *ctrlb = MICRON_V_ACTIMB_200;
137+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
138+ break;
139+ }
140+ case REVISION_XM_A:
141+ case REVISION_XM_B:
142+ case REVISION_XM_C:
143+ if (pop_mfr == 0) {
144+ /* 256MB DDR */
145+ *mcfg = MICRON_V_MCFG_200(256 << 20);
146+ *ctrla = MICRON_V_ACTIMA_200;
147+ *ctrlb = MICRON_V_ACTIMB_200;
148+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
149+ } else {
150+ /* 512MB DDR */
151+ *mcfg = NUMONYX_V_MCFG_165(512 << 20);
152+ *ctrla = NUMONYX_V_ACTIMA_165;
153+ *ctrlb = NUMONYX_V_ACTIMB_165;
154+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
155+ }
156+ break;
157+ default:
158+ /* Assume 128MB and Micron/165MHz timings to be safe */
159+ *mcfg = MICRON_V_MCFG_165(128 << 20);
160+ *ctrla = MICRON_V_ACTIMA_165;
161+ *ctrlb = MICRON_V_ACTIMB_165;
162+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
163+ }
164+}
165+#endif
166+
167 /*
168 * Routine: get_expansion_id
169 * Description: This function checks for expansion board by checking I2C
170@@ -367,7 +432,7 @@ void set_muxconf_regs(void)
171 MUX_BEAGLE();
172 }
173
174-#ifdef CONFIG_GENERIC_MMC
175+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
176 int board_mmc_init(bd_t *bis)
177 {
178 omap_mmc_init(0);
179@@ -476,6 +541,7 @@ int ehci_hcd_init(void)
180
181 #endif /* CONFIG_USB_EHCI */
182
183+#ifndef CONFIG_SPL_BUILD
184 /*
185 * This command returns the status of the user button on beagle xM
186 * Input - none
187@@ -528,3 +594,4 @@ U_BOOT_CMD(
188 "Return the status of the BeagleBoard USER button",
189 ""
190 );
191+#endif
192diff --git a/board/ti/beagle/config.mk b/board/ti/beagle/config.mk
193deleted file mode 100644
194index cf055db..0000000
195--- a/board/ti/beagle/config.mk
196+++ /dev/null
197@@ -1,33 +0,0 @@
198-#
199-# (C) Copyright 2006
200-# Texas Instruments, <www.ti.com>
201-#
202-# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
203-# see http://www.ti.com/ for more information on Texas Instruments
204-#
205-# See file CREDITS for list of people who contributed to this
206-# project.
207-#
208-# This program is free software; you can redistribute it and/or
209-# modify it under the terms of the GNU General Public License as
210-# published by the Free Software Foundation; either version 2 of
211-# the License, or (at your option) any later version.
212-#
213-# This program is distributed in the hope that it will be useful,
214-# but WITHOUT ANY WARRANTY; without even the implied warranty of
215-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
216-# GNU General Public License for more details.
217-#
218-# You should have received a copy of the GNU General Public License
219-# along with this program; if not, write to the Free Software
220-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
221-# MA 02111-1307 USA
222-#
223-# Physical Address:
224-# 8000'0000 (bank0)
225-# A000/0000 (bank1)
226-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
227-# (mem base + reserved)
228-
229-# For use with external or internal boots.
230-CONFIG_SYS_TEXT_BASE = 0x80008000
231diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
232index 15e40c5..941ec38 100644
233--- a/include/configs/omap3_beagle.h
234+++ b/include/configs/omap3_beagle.h
235@@ -111,9 +111,6 @@
236 #define STATUS_LED_BOOT STATUS_LED_BIT
237 #define STATUS_LED_GREEN STATUS_LED_BIT1
238
239-/* DDR - I use Micron DDR */
240-#define CONFIG_OMAP3_MICRON_DDR 1
241-
242 /* Enable Multi Bus support for I2C */
243 #define CONFIG_I2C_MULTI_BUS 1
244
245@@ -347,7 +344,6 @@
246 */
247 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
248 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
249-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
250 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
251
252 /* SDRAM Bank Allocation method */
253@@ -390,4 +386,59 @@
254
255 #define CONFIG_OMAP3_SPI
256
257+/* Defines for SPL */
258+#define CONFIG_SPL
259+#define CONFIG_SPL_NAND_SIMPLE
260+#define CONFIG_SPL_TEXT_BASE 0x40200800
261+#define CONFIG_SPL_MAX_SIZE (45 * 1024)
262+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
263+
264+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
265+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
266+
267+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
268+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
269+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
270+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
271+
272+#define CONFIG_SPL_LIBCOMMON_SUPPORT
273+#define CONFIG_SPL_LIBDISK_SUPPORT
274+#define CONFIG_SPL_I2C_SUPPORT
275+#define CONFIG_SPL_LIBGENERIC_SUPPORT
276+#define CONFIG_SPL_MMC_SUPPORT
277+#define CONFIG_SPL_FAT_SUPPORT
278+#define CONFIG_SPL_SERIAL_SUPPORT
279+#define CONFIG_SPL_NAND_SUPPORT
280+#define CONFIG_SPL_POWER_SUPPORT
281+#define CONFIG_SPL_OMAP3_ID_NAND
282+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
283+
284+/* NAND boot config */
285+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
286+#define CONFIG_SYS_NAND_PAGE_COUNT 64
287+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
288+#define CONFIG_SYS_NAND_OOBSIZE 64
289+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
290+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
291+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
292+ 10, 11, 12, 13}
293+#define CONFIG_SYS_NAND_ECCSIZE 512
294+#define CONFIG_SYS_NAND_ECCBYTES 3
295+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
296+ CONFIG_SYS_NAND_ECCSIZE)
297+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
298+ CONFIG_SYS_NAND_ECCSTEPS)
299+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
300+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
301+
302+/*
303+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
304+ * 64 bytes before this address should be set aside for u-boot.img's
305+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
306+ * other needs.
307+ */
308+#define CONFIG_SYS_TEXT_BASE 0x80100000
309+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
310+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
311+
312 #endif /* __CONFIG_H */
313--
3141.7.2.5
315
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0012-OMAP3-Add-SPL-support-to-omap3_evm.patch b/recipes-bsp/u-boot/u-boot/2011.09/0012-OMAP3-Add-SPL-support-to-omap3_evm.patch
new file mode 100644
index 00000000..7121ff7e
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0012-OMAP3-Add-SPL-support-to-omap3_evm.patch
@@ -0,0 +1,319 @@
1From a2985d6ef29ee6eb09ad1b40cf09f955549e66e2 Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:48:09 +0000
4Subject: [PATCH 12/21] OMAP3: Add SPL support to omap3_evm
5
6Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>.
7This also changes CONFIG_SYS_TEXT_BASE to 0x80100000.
8
9Signed-off-by: Tom Rini <trini@ti.com>
10Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
11---
12 arch/arm/include/asm/arch-omap3/mem.h | 26 ++++++++++++++++++++
13 board/ti/evm/config.mk | 33 -------------------------
14 board/ti/evm/evm.c | 41 ++++++++++++++++++++++++++++++-
15 include/configs/omap3_evm.h | 27 +++++++++++++++++++++
16 include/configs/omap3_evm_common.h | 30 +++++++++++++++++++++-
17 include/configs/omap3_evm_quick_mmc.h | 10 +++++++
18 include/configs/omap3_evm_quick_nand.h | 22 +++++++++++++++++
19 7 files changed, 152 insertions(+), 37 deletions(-)
20 delete mode 100644 board/ti/evm/config.mk
21
22diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
23index 4ea5f74..5fd02d4 100644
24--- a/arch/arm/include/asm/arch-omap3/mem.h
25+++ b/arch/arm/include/asm/arch-omap3/mem.h
26@@ -123,6 +123,32 @@ enum {
27 V_MCFG_BANKALLOCATION_RBC | \
28 V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
29
30+/* Hynix part of AM/DM37xEVM (200MHz optimized) */
31+#define HYNIX_TDAL_200 6
32+#define HYNIX_TDPL_200 3
33+#define HYNIX_TRRD_200 2
34+#define HYNIX_TRCD_200 4
35+#define HYNIX_TRP_200 3
36+#define HYNIX_TRAS_200 8
37+#define HYNIX_TRC_200 11
38+#define HYNIX_TRFC_200 18
39+#define HYNIX_V_ACTIMA_200 \
40+ ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \
41+ HYNIX_TRAS_200, HYNIX_TRP_200, \
42+ HYNIX_TRCD_200, HYNIX_TRRD_200, \
43+ HYNIX_TDPL_200, HYNIX_TDAL_200)
44+
45+#define HYNIX_TWTR_200 2
46+#define HYNIX_TCKE_200 1
47+#define HYNIX_TXP_200 1
48+#define HYNIX_XSR_200 28
49+#define HYNIX_V_ACTIMB_200 \
50+ ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \
51+ HYNIX_TXP_200, HYNIX_XSR_200)
52+
53+#define HYNIX_RASWIDTH_200 0x3
54+#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200)
55+
56 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
57 #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
58 /* 15/6 + 18/6 = 5.5 -> 6 */
59diff --git a/board/ti/evm/config.mk b/board/ti/evm/config.mk
60deleted file mode 100644
61index d173eef..0000000
62--- a/board/ti/evm/config.mk
63+++ /dev/null
64@@ -1,33 +0,0 @@
65-#
66-# (C) Copyright 2006 - 2008
67-# Texas Instruments, <www.ti.com>
68-#
69-# EVM uses OMAP3 (ARM-CortexA8) cpu
70-# see http://www.ti.com/ for more information on Texas Instruments
71-#
72-# See file CREDITS for list of people who contributed to this
73-# project.
74-#
75-# This program is free software; you can redistribute it and/or
76-# modify it under the terms of the GNU General Public License as
77-# published by the Free Software Foundation; either version 2 of
78-# the License, or (at your option) any later version.
79-#
80-# This program is distributed in the hope that it will be useful,
81-# but WITHOUT ANY WARRANTY; without even the implied warranty of
82-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
83-# GNU General Public License for more details.
84-#
85-# You should have received a copy of the GNU General Public License
86-# along with this program; if not, write to the Free Software
87-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
88-# MA 02111-1307 USA
89-#
90-# Physical Address:
91-# 8000'0000 (bank0)
92-# A000/0000 (bank1)
93-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
94-# (mem base + reserved)
95-
96-# For use with external or internal boots.
97-CONFIG_SYS_TEXT_BASE = 0x80008000
98diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
99index 8c43463..8497aee 100644
100--- a/board/ti/evm/evm.c
101+++ b/board/ti/evm/evm.c
102@@ -1,5 +1,5 @@
103 /*
104- * (C) Copyright 2004-2008
105+ * (C) Copyright 2004-2011
106 * Texas Instruments, <www.ti.com>
107 *
108 * Author :
109@@ -37,6 +37,7 @@
110 #include <asm/gpio.h>
111 #include <i2c.h>
112 #include <asm/mach-types.h>
113+#include <linux/mtd/nand.h>
114 #include "evm.h"
115
116 #define OMAP3EVM_GPIO_ETH_RST_GEN1 64
117@@ -119,6 +120,42 @@ int board_init(void)
118 return 0;
119 }
120
121+#ifdef CONFIG_SPL_BUILD
122+/*
123+ * Routine: get_board_mem_timings
124+ * Description: If we use SPL then there is no x-loader nor config header
125+ * so we have to setup the DDR timings ourself on the first bank. This
126+ * provides the timing values back to the function that configures
127+ * the memory.
128+ */
129+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
130+ u32 *mr)
131+{
132+ int pop_mfr, pop_id;
133+
134+ /*
135+ * We need to identify what PoP memory is on the board so that
136+ * we know what timings to use. To map the ID values please see
137+ * nand_ids.c
138+ */
139+ identify_nand_chip(&pop_mfr, &pop_id);
140+
141+ if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
142+ /* 256MB DDR */
143+ *mcfg = HYNIX_V_MCFG_200(256 << 20);
144+ *ctrla = HYNIX_V_ACTIMA_200;
145+ *ctrlb = HYNIX_V_ACTIMB_200;
146+ } else {
147+ /* 128MB DDR */
148+ *mcfg = MICRON_V_MCFG_165(128 << 20);
149+ *ctrla = MICRON_V_ACTIMA_165;
150+ *ctrlb = MICRON_V_ACTIMB_165;
151+ }
152+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
153+ *mr = MICRON_V_MR_165;
154+}
155+#endif
156+
157 /*
158 * Routine: misc_init_r
159 * Description: Init ethernet (done here so udelay works)
160@@ -238,7 +275,7 @@ int board_eth_init(bd_t *bis)
161 }
162 #endif /* CONFIG_CMD_NET */
163
164-#ifdef CONFIG_GENERIC_MMC
165+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
166 int board_mmc_init(bd_t *bis)
167 {
168 omap_mmc_init(0);
169diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
170index 47ec39f..dc611ca 100644
171--- a/include/configs/omap3_evm.h
172+++ b/include/configs/omap3_evm.h
173@@ -84,6 +84,13 @@
174 #define CONFIG_GENERIC_MMC
175 #define CONFIG_OMAP_HSMMC
176 #define CONFIG_DOS_PARTITION
177+/* SPL */
178+#define CONFIG_SPL_MMC_SUPPORT
179+#define CONFIG_SPL_FAT_SUPPORT
180+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
181+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
182+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
183+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
184
185 /* USB
186 *
187@@ -94,6 +101,26 @@
188 #define CONFIG_MUSB_HCD
189 /* #define CONFIG_MUSB_UDC */
190
191+/* NAND SPL */
192+#define CONFIG_SPL_NAND_SIMPLE
193+#define CONFIG_SPL_NAND_SUPPORT
194+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
195+#define CONFIG_SYS_NAND_PAGE_COUNT 64
196+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
197+#define CONFIG_SYS_NAND_OOBSIZE 64
198+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
199+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
200+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
201+ 10, 11, 12, 13}
202+#define CONFIG_SYS_NAND_ECCSIZE 512
203+#define CONFIG_SYS_NAND_ECCBYTES 3
204+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
205+ CONFIG_SYS_NAND_ECCSIZE)
206+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
207+ CONFIG_SYS_NAND_ECCSTEPS)
208+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
209+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
210+
211 /* -----------------------------------------------------------------------------
212 * Include common board configuration
213 * -----------------------------------------------------------------------------
214diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
215index 54aa7a7..a2aeb76 100644
216--- a/include/configs/omap3_evm_common.h
217+++ b/include/configs/omap3_evm_common.h
218@@ -27,7 +27,6 @@
219 #define CONFIG_SDRC /* The chip has SDRC controller */
220
221 #define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
222-#define CONFIG_OMAP3_MICRON_DDR /* with MICRON DDR part */
223 #define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
224
225 #undef CONFIG_USE_IRQ /* no support for IRQs */
226@@ -71,7 +70,6 @@
227 */
228 #define CONFIG_NR_DRAM_BANKS 2
229 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
230-#define PHYS_SDRAM_1_SIZE (32 << 20)
231 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
232
233 /* SDRAM Bank Allocation method */
234@@ -289,4 +287,32 @@
235 /* Uncomment to define the board revision statically */
236 /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
237
238+/* Defines for SPL */
239+#define CONFIG_SPL
240+#define CONFIG_SPL_TEXT_BASE 0x40200800
241+#define CONFIG_SPL_MAX_SIZE (45 * 1024) /* 45 KB */
242+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
243+
244+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
245+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
246+
247+#define CONFIG_SPL_LIBCOMMON_SUPPORT
248+#define CONFIG_SPL_LIBDISK_SUPPORT
249+#define CONFIG_SPL_I2C_SUPPORT
250+#define CONFIG_SPL_LIBGENERIC_SUPPORT
251+#define CONFIG_SPL_SERIAL_SUPPORT
252+#define CONFIG_SPL_POWER_SUPPORT
253+#define CONFIG_SPL_OMAP3_ID_NAND
254+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
255+
256+/*
257+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
258+ * 64 bytes before this address should be set aside for u-boot.img's
259+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
260+ * other needs.
261+ */
262+#define CONFIG_SYS_TEXT_BASE 0x80100000
263+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
264+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
265+
266 #endif /* __OMAP3_EVM_COMMON_H */
267diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h
268index 691e4c2..912da7d 100644
269--- a/include/configs/omap3_evm_quick_mmc.h
270+++ b/include/configs/omap3_evm_quick_mmc.h
271@@ -88,4 +88,14 @@
272 "root=/dev/mmcblk0p2 rw " \
273 "rootfstype=ext3 rootwait"
274
275+/*
276+ * SPL
277+ */
278+#define CONFIG_SPL_MMC_SUPPORT
279+#define CONFIG_SPL_FAT_SUPPORT
280+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
281+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
282+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
283+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
284+
285 #endif /* __OMAP3_EVM_QUICK_MMC_H */
286diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h
287index 2d18314..2f879c0 100644
288--- a/include/configs/omap3_evm_quick_nand.h
289+++ b/include/configs/omap3_evm_quick_nand.h
290@@ -76,4 +76,26 @@
291 "root=/dev/mtdblock4 rw " \
292 "rootfstype=jffs2 "
293
294+/*
295+ * SPL
296+ */
297+#define CONFIG_SPL_NAND_SIMPLE
298+#define CONFIG_SPL_NAND_SUPPORT
299+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
300+#define CONFIG_SYS_NAND_PAGE_COUNT 64
301+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
302+#define CONFIG_SYS_NAND_OOBSIZE 64
303+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
304+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
305+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
306+ 10, 11, 12, 13}
307+#define CONFIG_SYS_NAND_ECCSIZE 512
308+#define CONFIG_SYS_NAND_ECCBYTES 3
309+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
310+ CONFIG_SYS_NAND_ECCSIZE)
311+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
312+ CONFIG_SYS_NAND_ECCSTEPS)
313+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
314+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
315+
316 #endif /* __OMAP3_EVM_QUICK_NAND_H */
317--
3181.7.2.5
319
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0013-AM3517-Add-SPL-support.patch b/recipes-bsp/u-boot/u-boot/2011.09/0013-AM3517-Add-SPL-support.patch
new file mode 100644
index 00000000..cb9c1b28
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0013-AM3517-Add-SPL-support.patch
@@ -0,0 +1,150 @@
1From aff5a412e0353407420ed63246ea630988ebf469 Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:48:10 +0000
4Subject: [PATCH 13/21] AM3517: Add SPL support
5
6The only change of note is that we move from 0x80008000 to 0x80100000
7for CONFIG_SYS_TEXT_BASE
8
9Cc: Vaibhav Hiremath <hvaibhav@ti.com>
10Signed-off-by: Tom Rini <trini@ti.com>
11Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
12---
13 board/logicpd/am3517evm/am3517evm.c | 2 +-
14 board/logicpd/am3517evm/config.mk | 30 ------------------
15 include/configs/am3517_evm.h | 57 +++++++++++++++++++++++++++++++++-
16 3 files changed, 56 insertions(+), 33 deletions(-)
17 delete mode 100644 board/logicpd/am3517evm/config.mk
18
19diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
20index c0a006a..0a105bf 100644
21--- a/board/logicpd/am3517evm/am3517evm.c
22+++ b/board/logicpd/am3517evm/am3517evm.c
23@@ -76,7 +76,7 @@ void set_muxconf_regs(void)
24 MUX_AM3517EVM();
25 }
26
27-#ifdef CONFIG_GENERIC_MMC
28+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
29 int board_mmc_init(bd_t *bis)
30 {
31 omap_mmc_init(0);
32diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk
33deleted file mode 100644
34index 71ec5d0..0000000
35--- a/board/logicpd/am3517evm/config.mk
36+++ /dev/null
37@@ -1,30 +0,0 @@
38-#
39-# Author: Vaibhav Hiremath <hvaibhav@ti.com>
40-#
41-# Based on ti/evm/config.mk
42-#
43-# Copyright (C) 2010
44-# Texas Instruments Incorporated - http://www.ti.com/
45-#
46-# This program is free software; you can redistribute it and/or modify
47-# it under the terms of the GNU General Public License as published by
48-# the Free Software Foundation; either version 2 of the License, or
49-# (at your option) any later version.
50-#
51-# This program is distributed in the hope that it will be useful,
52-# but WITHOUT ANY WARRANTY; without even the implied warranty of
53-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
54-# GNU General Public License for more details.
55-#
56-# You should have received a copy of the GNU General Public License
57-# along with this program; if not, write to the Free Software
58-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
59-#
60-# Physical Address:
61-# 8000'0000 (bank0)
62-# A000/0000 (bank1)
63-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
64-# (mem base + reserved)
65-
66-# For use with external or internal boots.
67-CONFIG_SYS_TEXT_BASE = 0x80008000
68diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
69index 1c70b9d..4a1c72c 100644
70--- a/include/configs/am3517_evm.h
71+++ b/include/configs/am3517_evm.h
72@@ -63,7 +63,6 @@
73 /*
74 * DDR related
75 */
76-#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */
77 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
78
79 /*
80@@ -273,7 +272,6 @@
81 */
82 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
83 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
84-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
85 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
86
87 /* SDRAM Bank Allocation method */
88@@ -331,4 +329,59 @@
89 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
90 CONFIG_SYS_INIT_RAM_SIZE - \
91 GENERATED_GBL_DATA_SIZE)
92+
93+/* Defines for SPL */
94+#define CONFIG_SPL
95+#define CONFIG_SPL_NAND_SIMPLE
96+#define CONFIG_SPL_TEXT_BASE 0x40200800
97+#define CONFIG_SPL_MAX_SIZE (45 * 1024)
98+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
99+
100+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
101+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
102+
103+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
104+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
105+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
106+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
107+
108+#define CONFIG_SPL_LIBCOMMON_SUPPORT
109+#define CONFIG_SPL_LIBDISK_SUPPORT
110+#define CONFIG_SPL_I2C_SUPPORT
111+#define CONFIG_SPL_LIBGENERIC_SUPPORT
112+#define CONFIG_SPL_MMC_SUPPORT
113+#define CONFIG_SPL_FAT_SUPPORT
114+#define CONFIG_SPL_SERIAL_SUPPORT
115+#define CONFIG_SPL_NAND_SUPPORT
116+#define CONFIG_SPL_POWER_SUPPORT
117+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
118+
119+/* NAND boot config */
120+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
121+#define CONFIG_SYS_NAND_PAGE_COUNT 64
122+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
123+#define CONFIG_SYS_NAND_OOBSIZE 64
124+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
125+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
126+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
127+ 10, 11, 12, 13}
128+#define CONFIG_SYS_NAND_ECCSIZE 512
129+#define CONFIG_SYS_NAND_ECCBYTES 3
130+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
131+ CONFIG_SYS_NAND_ECCSIZE)
132+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
133+ CONFIG_SYS_NAND_ECCSTEPS)
134+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
135+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
136+
137+/*
138+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
139+ * 64 bytes before this address should be set aside for u-boot.img's
140+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
141+ * other needs.
142+ */
143+#define CONFIG_SYS_TEXT_BASE 0x80100000
144+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
145+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
146+
147 #endif /* __CONFIG_H */
148--
1491.7.2.5
150
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0014-AM3517-CraneBoard-Add-SPL-support.patch b/recipes-bsp/u-boot/u-boot/2011.09/0014-AM3517-CraneBoard-Add-SPL-support.patch
new file mode 100644
index 00000000..22a3e71d
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0014-AM3517-CraneBoard-Add-SPL-support.patch
@@ -0,0 +1,150 @@
1From 04567bb3a9e3b8aefe2a58c339c592c4b62b79d3 Mon Sep 17 00:00:00 2001
2From: Tom Rini <trini@ti.com>
3Date: Fri, 18 Nov 2011 12:48:11 +0000
4Subject: [PATCH 14/21] AM3517 CraneBoard: Add SPL support
5
6The only change of note is that we move from 0x80008000 to 0x80100000
7for CONFIG_SYS_TEXT_BASE
8
9Cc: Nagendra T S <nagendra@mistralsolutions.com>
10Tested-by: Koen Kooi <k-kooi@ti.com>
11Signed-off-by: Tom Rini <trini@ti.com>
12Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
13---
14 board/ti/am3517crane/am3517crane.c | 2 +-
15 board/ti/am3517crane/config.mk | 29 ------------------
16 include/configs/am3517_crane.h | 57 ++++++++++++++++++++++++++++++++++-
17 3 files changed, 56 insertions(+), 32 deletions(-)
18 delete mode 100644 board/ti/am3517crane/config.mk
19
20diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c
21index cd5683d..436645a 100644
22--- a/board/ti/am3517crane/am3517crane.c
23+++ b/board/ti/am3517crane/am3517crane.c
24@@ -75,7 +75,7 @@ void set_muxconf_regs(void)
25 MUX_AM3517CRANE();
26 }
27
28-#ifdef CONFIG_GENERIC_MMC
29+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
30 int board_mmc_init(bd_t *bis)
31 {
32 omap_mmc_init(0);
33diff --git a/board/ti/am3517crane/config.mk b/board/ti/am3517crane/config.mk
34deleted file mode 100644
35index c6a18b5..0000000
36--- a/board/ti/am3517crane/config.mk
37+++ /dev/null
38@@ -1,29 +0,0 @@
39-#
40-# Author: Srinath R <srinath@mistralsolutions.com>
41-#
42-# Based on logicpd/am3517evm/config.mk
43-#
44-# Copyright (C) 2011 Mistral Solutions Pvt Ltd
45-#
46-# This program is free software; you can redistribute it and/or modify
47-# it under the terms of the GNU General Public License as published by
48-# the Free Software Foundation; either version 2 of the License, or
49-# (at your option) any later version.
50-#
51-# This program is distributed in the hope that it will be useful,
52-# but WITHOUT ANY WARRANTY; without even the implied warranty of
53-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
54-# GNU General Public License for more details.
55-#
56-# You should have received a copy of the GNU General Public License
57-# along with this program; if not, write to the Free Software
58-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
59-#
60-# Physical Address:
61-# 8000'0000 (bank0)
62-# A000/0000 (bank1)
63-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
64-# (mem base + reserved)
65-
66-# For use with external or internal boots.
67-CONFIG_SYS_TEXT_BASE = 0x80008000
68diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
69index 8842a18..68cbf37 100644
70--- a/include/configs/am3517_crane.h
71+++ b/include/configs/am3517_crane.h
72@@ -64,7 +64,6 @@
73 /*
74 * DDR related
75 */
76-#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */
77 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
78
79 /*
80@@ -274,7 +273,6 @@
81 */
82 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
83 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
84-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
85 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
86
87 /* SDRAM Bank Allocation method */
88@@ -330,4 +328,59 @@
89 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
90 CONFIG_SYS_INIT_RAM_SIZE - \
91 GENERATED_GBL_DATA_SIZE)
92+
93+/* Defines for SPL */
94+#define CONFIG_SPL
95+#define CONFIG_SPL_NAND_SIMPLE
96+#define CONFIG_SPL_TEXT_BASE 0x40200800
97+#define CONFIG_SPL_MAX_SIZE (45 * 1024)
98+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
99+
100+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
101+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
102+
103+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
104+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
105+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
106+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
107+
108+#define CONFIG_SPL_LIBCOMMON_SUPPORT
109+#define CONFIG_SPL_LIBDISK_SUPPORT
110+#define CONFIG_SPL_I2C_SUPPORT
111+#define CONFIG_SPL_LIBGENERIC_SUPPORT
112+#define CONFIG_SPL_MMC_SUPPORT
113+#define CONFIG_SPL_FAT_SUPPORT
114+#define CONFIG_SPL_SERIAL_SUPPORT
115+#define CONFIG_SPL_NAND_SUPPORT
116+#define CONFIG_SPL_POWER_SUPPORT
117+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
118+
119+/* NAND boot config */
120+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
121+#define CONFIG_SYS_NAND_PAGE_COUNT 64
122+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
123+#define CONFIG_SYS_NAND_OOBSIZE 64
124+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
125+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
126+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
127+ 10, 11, 12, 13}
128+#define CONFIG_SYS_NAND_ECCSIZE 512
129+#define CONFIG_SYS_NAND_ECCBYTES 3
130+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
131+ CONFIG_SYS_NAND_ECCSIZE)
132+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
133+ CONFIG_SYS_NAND_ECCSTEPS)
134+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
135+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
136+
137+/*
138+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
139+ * 64 bytes before this address should be set aside for u-boot.img's
140+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
141+ * other needs.
142+ */
143+#define CONFIG_SYS_TEXT_BASE 0x80100000
144+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
145+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
146+
147 #endif /* __CONFIG_H */
148--
1491.7.2.5
150
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0001-HACK-beagleboard-config-disable-cache-for-USB.patch b/recipes-bsp/u-boot/u-boot/2011.09/0015-HACK-beagleboard-config-disable-cache-for-USB.patch
index a2776e9a..ec1ec26e 100644
--- a/recipes-bsp/u-boot/u-boot/2011.09/0001-HACK-beagleboard-config-disable-cache-for-USB.patch
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0015-HACK-beagleboard-config-disable-cache-for-USB.patch
@@ -1,7 +1,7 @@
1From 03b9bca863257cb24d8f11bb773ad2b8dff820c6 Mon Sep 17 00:00:00 2001 1From 3fe471d34ef6575bc49c9f85ed74368e3ac25ad6 Mon Sep 17 00:00:00 2001
2From: Jason Kridner <jdk@ti.com> 2From: Jason Kridner <jdk@ti.com>
3Date: Sun, 18 Sep 2011 12:16:31 -0400 3Date: Sun, 18 Sep 2011 12:16:31 -0400
4Subject: [PATCH 1/3] HACK: beagleboard: config: disable cache for USB 4Subject: [PATCH 15/21] HACK: beagleboard: config: disable cache for USB
5 5
6There is currently a bug in the USB code for the BeagleBoard that is 6There is currently a bug in the USB code for the BeagleBoard that is
7worked-around by disabling the cache. 7worked-around by disabling the cache.
@@ -10,11 +10,11 @@ See http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/108224
10 10
11Signed-off-by: Jason Kridner <jdk@ti.com> 11Signed-off-by: Jason Kridner <jdk@ti.com>
12--- 12---
13 include/configs/omap3_beagle.h | 5 +++++ 13 include/configs/omap3_beagle.h | 4 ++++
14 1 files changed, 5 insertions(+), 0 deletions(-) 14 1 files changed, 4 insertions(+), 0 deletions(-)
15 15
16diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h 16diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
17index 1369c89..8a84d7a 100644 17index 941ec38..569d747 100644
18--- a/include/configs/omap3_beagle.h 18--- a/include/configs/omap3_beagle.h
19+++ b/include/configs/omap3_beagle.h 19+++ b/include/configs/omap3_beagle.h
20@@ -36,6 +36,10 @@ 20@@ -36,6 +36,10 @@
@@ -29,5 +29,5 @@ index 1369c89..8a84d7a 100644
29 29
30 #include <asm/arch/cpu.h> /* get chip and board defs */ 30 #include <asm/arch/cpu.h> /* get chip and board defs */
31-- 31--
321.7.4.1 321.7.2.5
33 33
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0002-beagleboard-config-enable-gpio-command.patch b/recipes-bsp/u-boot/u-boot/2011.09/0016-beagleboard-config-enable-gpio-command.patch
index 096a1ce3..268932b7 100644
--- a/recipes-bsp/u-boot/u-boot/2011.09/0002-beagleboard-config-enable-gpio-command.patch
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0016-beagleboard-config-enable-gpio-command.patch
@@ -1,7 +1,7 @@
1From 79e8280783d445f7630b8a9830f8db73f2e04828 Mon Sep 17 00:00:00 2001 1From e5bf80f2fb4af9a2627541cb8bc8686e8a9e8404 Mon Sep 17 00:00:00 2001
2From: Jason Kridner <jdk@ti.com> 2From: Jason Kridner <jdk@ti.com>
3Date: Tue, 6 Sep 2011 18:56:11 -0400 3Date: Tue, 6 Sep 2011 18:56:11 -0400
4Subject: [PATCH 2/3] beagleboard: config: enable gpio command 4Subject: [PATCH 16/21] beagleboard: config: enable gpio command
5 5
6Now that we are using the generic GPIO framework, enable the command. 6Now that we are using the generic GPIO framework, enable the command.
7--- 7---
@@ -9,10 +9,10 @@ Now that we are using the generic GPIO framework, enable the command.
9 1 files changed, 1 insertions(+), 0 deletions(-) 9 1 files changed, 1 insertions(+), 0 deletions(-)
10 10
11diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h 11diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
12index 8a84d7a..43dc94a 100644 12index 569d747..337ca29 100644
13--- a/include/configs/omap3_beagle.h 13--- a/include/configs/omap3_beagle.h
14+++ b/include/configs/omap3_beagle.h 14+++ b/include/configs/omap3_beagle.h
15@@ -169,6 +169,7 @@ 15@@ -164,6 +164,7 @@
16 #define CONFIG_CMD_PING 16 #define CONFIG_CMD_PING
17 #define CONFIG_CMD_DHCP 17 #define CONFIG_CMD_DHCP
18 #define CONFIG_CMD_SETEXPR /* Evaluate expressions */ 18 #define CONFIG_CMD_SETEXPR /* Evaluate expressions */
@@ -21,5 +21,5 @@ index 8a84d7a..43dc94a 100644
21 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 21 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
22 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 22 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
23-- 23--
241.7.4.1 241.7.2.5
25 25
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0003-Increased-some-timeout-durations-for-MMC-and-EHCI.patch b/recipes-bsp/u-boot/u-boot/2011.09/0017-Increased-some-timeout-durations-for-MMC-and-EHCI.patch
index c3ebf1bd..9aeb5485 100644
--- a/recipes-bsp/u-boot/u-boot/2011.09/0003-Increased-some-timeout-durations-for-MMC-and-EHCI.patch
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0017-Increased-some-timeout-durations-for-MMC-and-EHCI.patch
@@ -1,7 +1,7 @@
1From 316e3a4573bdbbbc395baeca4f7b2208707e30fa Mon Sep 17 00:00:00 2001 1From 7ba57c9e6372c067609797cbac53f8a14691fc2d Mon Sep 17 00:00:00 2001
2From: Jason Kridner <jdk@ti.com> 2From: Jason Kridner <jdk@ti.com>
3Date: Wed, 7 Sep 2011 08:56:48 -0400 3Date: Wed, 7 Sep 2011 08:56:48 -0400
4Subject: [PATCH 3/3] Increased some timeout durations for MMC and EHCI 4Subject: [PATCH 17/21] Increased some timeout durations for MMC and EHCI
5 5
6--- 6---
7 drivers/mmc/omap_hsmmc.c | 2 +- 7 drivers/mmc/omap_hsmmc.c | 2 +-
@@ -9,18 +9,18 @@ Subject: [PATCH 3/3] Increased some timeout durations for MMC and EHCI
9 2 files changed, 2 insertions(+), 2 deletions(-) 9 2 files changed, 2 insertions(+), 2 deletions(-)
10 10
11diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c 11diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
12index ef12ecd..7e35372 100644 12index c38b9e6..5054a21 100644
13--- a/drivers/mmc/omap_hsmmc.c 13--- a/drivers/mmc/omap_hsmmc.c
14+++ b/drivers/mmc/omap_hsmmc.c 14+++ b/drivers/mmc/omap_hsmmc.c
15@@ -33,7 +33,7 @@ 15@@ -34,7 +34,7 @@
16 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/sys_proto.h>
17 17
18 /* If we fail after 1 second wait, something is really bad */ 18 /* If we fail after 1 second wait, something is really bad */
19-#define MAX_RETRY_MS 1000 19-#define MAX_RETRY_MS 1000
20+#define MAX_RETRY_MS 5000 20+#define MAX_RETRY_MS 5000
21 21
22 static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size); 22 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
23 static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int siz); 23 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
24diff --git a/include/usb.h b/include/usb.h 24diff --git a/include/usb.h b/include/usb.h
25index 06170cd..0d99b92 100644 25index 06170cd..0d99b92 100644
26--- a/include/usb.h 26--- a/include/usb.h
@@ -35,5 +35,5 @@ index 06170cd..0d99b92 100644
35 /* device request (setup) */ 35 /* device request (setup) */
36 struct devrequest { 36 struct devrequest {
37-- 37--
381.7.4.1 381.7.2.5
39 39
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0003-beagleboard-mount-rootfs-RO-instead-of-RW-at-boot.patch b/recipes-bsp/u-boot/u-boot/2011.09/0018-beagleboard-mount-rootfs-RO-instead-of-RW-at-boot.patch
index 3c6743e9..b571a4e4 100644
--- a/recipes-bsp/u-boot/u-boot/2011.09/0003-beagleboard-mount-rootfs-RO-instead-of-RW-at-boot.patch
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0018-beagleboard-mount-rootfs-RO-instead-of-RW-at-boot.patch
@@ -1,7 +1,7 @@
1From 78080b20d8daa8e80f962beeab898d171bcc8eac Mon Sep 17 00:00:00 2001 1From daa9fa5f66a1b370072f1e91fd51c6a5e3d81fd8 Mon Sep 17 00:00:00 2001
2From: Koen Kooi <koen@dominion.thruhere.net> 2From: Koen Kooi <koen@dominion.thruhere.net>
3Date: Sun, 16 Oct 2011 09:37:38 +0200 3Date: Sun, 27 Nov 2011 14:43:58 +0100
4Subject: [PATCH 3/3] beagleboard: mount rootfs RO instead of RW at boot 4Subject: [PATCH 18/21] beagleboard: mount rootfs RO instead of RW at boot
5 5
6Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> 6Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
7--- 7---
@@ -9,18 +9,18 @@ Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
9 1 files changed, 1 insertions(+), 1 deletions(-) 9 1 files changed, 1 insertions(+), 1 deletions(-)
10 10
11diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h 11diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
12index a67e5a0..95a134b 100644 12index 337ca29..186586f 100644
13--- a/include/configs/omap3_beagle.h 13--- a/include/configs/omap3_beagle.h
14+++ b/include/configs/omap3_beagle.h 14+++ b/include/configs/omap3_beagle.h
15@@ -231,7 +231,7 @@ 15@@ -226,7 +226,7 @@
16 "dvimode=640x480MR-16@60\0" \ 16 "dvimode=640x480MR-16@60\0" \
17 "defaultdisplay=dvi\0" \ 17 "defaultdisplay=dvi\0" \
18 "mmcdev=0\0" \ 18 "mmcdev=0\0" \
19- "mmcroot=/dev/mmcblk0p2 rw\0" \ 19- "mmcroot=/dev/mmcblk0p2 rw\0" \
20+ "mmcroot=/dev/mmcblk0p2 ro\0" \ 20+ "mmcroot=/dev/mmcblk0p2 ro\0" \
21 "mmcrootfstype=ext3 rootwait\0" \ 21 "mmcrootfstype=ext3 rootwait\0" \
22 "nandroot=/dev/mtdblock4 rw\0" \ 22 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
23 "nandrootfstype=jffs2\0" \ 23 "nandrootfstype=ubifs\0" \
24-- 24--
251.6.6.1 251.7.2.5
26 26
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0002-beagleboard-switch-to-ttyO2.patch b/recipes-bsp/u-boot/u-boot/2011.09/0019-BeagleBoard-config-Really-switch-to-ttyO2.patch
index bc7cf06c..1d21612c 100644
--- a/recipes-bsp/u-boot/u-boot/2011.09/0002-beagleboard-switch-to-ttyO2.patch
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0019-BeagleBoard-config-Really-switch-to-ttyO2.patch
@@ -1,7 +1,9 @@
1From d901c32c1bd9343a932f8bdd96f3ec539407b42b Mon Sep 17 00:00:00 2001 1From ceb3c55ff226f068edb369342e3bd2db70ca8827 Mon Sep 17 00:00:00 2001
2From: Koen Kooi <koen@dominion.thruhere.net> 2From: Koen Kooi <koen@dominion.thruhere.net>
3Date: Tue, 11 Oct 2011 13:53:21 +0200 3Date: Sun, 27 Nov 2011 14:46:04 +0100
4Subject: [PATCH 2/2] beagleboard: switch to ttyO2 4Subject: [PATCH 19/21] BeagleBoard: config: Really switch to ttyO2
5
6The previous commit changed it to "zero two" instead of the proper "Oh two". This was completely broken!
5 7
6Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> 8Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
7--- 9---
@@ -9,18 +11,18 @@ Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
9 1 files changed, 1 insertions(+), 1 deletions(-) 11 1 files changed, 1 insertions(+), 1 deletions(-)
10 12
11diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h 13diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
12index 23f19f6..04c2188 100644 14index 186586f..833f86a 100644
13--- a/include/configs/omap3_beagle.h 15--- a/include/configs/omap3_beagle.h
14+++ b/include/configs/omap3_beagle.h 16+++ b/include/configs/omap3_beagle.h
15@@ -220,7 +220,7 @@ 17@@ -217,7 +217,7 @@
16 "rdaddr=0x81000000\0" \ 18 "rdaddr=0x81000000\0" \
17 "usbtty=cdc_acm\0" \ 19 "usbtty=cdc_acm\0" \
18 "bootfile=uImage.beagle\0" \ 20 "bootfile=uImage.beagle\0" \
19- "console=ttyS2,115200n8\0" \ 21- "console=tty02,115200n8\0" \
20+ "console=ttyO2,115200n8\0" \ 22+ "console=ttyO2,115200n8\0" \
21 "mpurate=auto\0" \ 23 "mpurate=auto\0" \
22 "buddy=none "\ 24 "buddy=none "\
23 "buddy2=none "\ 25 "optargs=\0" \
24-- 26--
251.6.6.1 271.7.2.5
26 28
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0001-beagleboard-add-support-for-TCT-Beacon-board.patch b/recipes-bsp/u-boot/u-boot/2011.09/0020-beagleboard-add-support-for-TCT-Beacon-board.patch
index 819c6233..39c2a36c 100644
--- a/recipes-bsp/u-boot/u-boot/2011.09/0001-beagleboard-add-support-for-TCT-Beacon-board.patch
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0020-beagleboard-add-support-for-TCT-Beacon-board.patch
@@ -1,20 +1,19 @@
1From f6ce74793e6341895153e43643460b7fc812dc9d Mon Sep 17 00:00:00 2001 1From e368b3cc2b281146c7848a2044e8a7d457ea1e38 Mon Sep 17 00:00:00 2001
2From: Koen Kooi <koen@dominion.thruhere.net> 2From: Koen Kooi <koen@dominion.thruhere.net>
3Date: Sat, 8 Oct 2011 21:56:35 +0200 3Date: Sat, 8 Oct 2011 21:56:35 +0200
4Subject: [PATCH] beagleboard: add support for TCT Beacon board 4Subject: [PATCH 20/21] beagleboard: add support for TCT Beacon board
5 5
6Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> 6Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
7--- 7---
8 board/ti/beagle/beagle.c | 59 ++++++++++++++++++++++++++++++++++++++++ 8 board/ti/beagle/beagle.c | 10 ++++++++++
9 board/ti/beagle/beagle.h | 7 +++++ 9 board/ti/beagle/beagle.h | 7 +++++++
10 include/configs/omap3_beagle.h | 7 +++++ 10 2 files changed, 17 insertions(+), 0 deletions(-)
11 3 files changed, 73 insertions(+), 0 deletions(-)
12 11
13diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c 12diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
14index 8cdceaf..f4e986c 100644 13index 6a457cb..9c2e6d0 100644
15--- a/board/ti/beagle/beagle.c 14--- a/board/ti/beagle/beagle.c
16+++ b/board/ti/beagle/beagle.c 15+++ b/board/ti/beagle/beagle.c
17@@ -57,11 +57,14 @@ extern volatile struct ehci_hcor *hcor; 16@@ -59,11 +59,14 @@ extern volatile struct ehci_hcor *hcor;
18 #define TWL4030_I2C_BUS 0 17 #define TWL4030_I2C_BUS 0
19 #define EXPANSION_EEPROM_I2C_BUS 1 18 #define EXPANSION_EEPROM_I2C_BUS 1
20 #define EXPANSION_EEPROM_I2C_ADDRESS 0x50 19 #define EXPANSION_EEPROM_I2C_ADDRESS 0x50
@@ -29,7 +28,7 @@ index 8cdceaf..f4e986c 100644
29 #define KBADC_BEAGLEFPGA 0x01000600 28 #define KBADC_BEAGLEFPGA 0x01000600
30 #define LW_BEAGLETOUCH 0x01000700 29 #define LW_BEAGLETOUCH 0x01000700
31 #define BRAINMUX_LCDOG 0x01000800 30 #define BRAINMUX_LCDOG 0x01000800
32@@ -290,6 +331,13 @@ int misc_init_r(void) 31@@ -351,6 +354,13 @@ int misc_init_r(void)
33 setenv("defaultdisplay", "showdoglcd"); 32 setenv("defaultdisplay", "showdoglcd");
34 setenv("buddy", "showdog"); 33 setenv("buddy", "showdog");
35 break; 34 break;
@@ -61,3 +60,6 @@ index 18bfaa8..6a9ad73 100644
61 #define MUX_KBADC_BEAGLEFPGA() \ 60 #define MUX_KBADC_BEAGLEFPGA() \
62 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | DIS | M1)) /*MCSPI4_CLK*/\ 61 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | DIS | M1)) /*MCSPI4_CLK*/\
63 MUX_VAL(CP(MCBSP1_DX), (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\ 62 MUX_VAL(CP(MCBSP1_DX), (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
63--
641.7.2.5
65
diff --git a/recipes-bsp/u-boot/u-boot/2011.09/0001-beagleboard-add-support-for-scanning-loop-through-ex.patch b/recipes-bsp/u-boot/u-boot/2011.09/0021-beagleboard-add-support-for-scanning-loop-through-ex.patch
index fdd62004..a2df7ca4 100644
--- a/recipes-bsp/u-boot/u-boot/2011.09/0001-beagleboard-add-support-for-scanning-loop-through-ex.patch
+++ b/recipes-bsp/u-boot/u-boot/2011.09/0021-beagleboard-add-support-for-scanning-loop-through-ex.patch
@@ -1,7 +1,7 @@
1From d6dd7efc7a74e6bdcbcbda204f66d4ad23fd0f53 Mon Sep 17 00:00:00 2001 1From 78fd05bd746f623de3150469a9f6f4e9531a17c4 Mon Sep 17 00:00:00 2001
2From: Koen Kooi <koen@dominion.thruhere.net> 2From: Koen Kooi <koen@dominion.thruhere.net>
3Date: Tue, 11 Oct 2011 13:05:32 +0200 3Date: Sun, 27 Nov 2011 14:53:56 +0100
4Subject: [PATCH 1/2] beagleboard: add support for scanning loop-through expansionboards like the uLCD-lite 4Subject: [PATCH 21/21] beagleboard: add support for scanning loop-through expansionboards like the uLCD-lite
5 5
6Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> 6Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
7--- 7---
@@ -10,10 +10,10 @@ Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
10 2 files changed, 28 insertions(+), 4 deletions(-) 10 2 files changed, 28 insertions(+), 4 deletions(-)
11 11
12diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c 12diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
13index 96fac51..51a90a0 100644 13index 9c2e6d0..5ea50d1 100644
14--- a/board/ti/beagle/beagle.c 14--- a/board/ti/beagle/beagle.c
15+++ b/board/ti/beagle/beagle.c 15+++ b/board/ti/beagle/beagle.c
16@@ -72,6 +72,7 @@ extern volatile struct ehci_hcor *hcor; 16@@ -74,6 +74,7 @@ extern volatile struct ehci_hcor *hcor;
17 #define BBTOYS_WIFI 0x01000B00 17 #define BBTOYS_WIFI 0x01000B00
18 #define BBTOYS_VGA 0x02000B00 18 #define BBTOYS_VGA 0x02000B00
19 #define BBTOYS_LCD 0x03000B00 19 #define BBTOYS_LCD 0x03000B00
@@ -21,7 +21,7 @@ index 96fac51..51a90a0 100644
21 #define BEAGLE_NO_EEPROM 0xffffffff 21 #define BEAGLE_NO_EEPROM 0xffffffff
22 22
23 DECLARE_GLOBAL_DATA_PTR; 23 DECLARE_GLOBAL_DATA_PTR;
24@@ -148,18 +149,18 @@ int get_board_revision(void) 24@@ -209,18 +210,18 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
25 * bus 1 for the availability of an AT24C01B serial EEPROM. 25 * bus 1 for the availability of an AT24C01B serial EEPROM.
26 * returns the device_vendor field from the EEPROM 26 * returns the device_vendor field from the EEPROM
27 */ 27 */
@@ -43,7 +43,7 @@ index 96fac51..51a90a0 100644
43 sizeof(expansion_config)); 43 sizeof(expansion_config));
44 44
45 i2c_set_bus_num(TWL4030_I2C_BUS); 45 i2c_set_bus_num(TWL4030_I2C_BUS);
46@@ -262,7 +263,7 @@ int misc_init_r(void) 46@@ -323,7 +324,7 @@ int misc_init_r(void)
47 TWL4030_PM_RECEIVER_DEV_GRP_P1); 47 TWL4030_PM_RECEIVER_DEV_GRP_P1);
48 } 48 }
49 49
@@ -52,7 +52,7 @@ index 96fac51..51a90a0 100644
52 case TINCANTOOLS_ZIPPY: 52 case TINCANTOOLS_ZIPPY:
53 printf("Recognized Tincantools Zippy board (rev %d %s)\n", 53 printf("Recognized Tincantools Zippy board (rev %d %s)\n",
54 expansion_config.revision, 54 expansion_config.revision,
55@@ -341,6 +342,27 @@ int misc_init_r(void) 55@@ -402,6 +403,27 @@ int misc_init_r(void)
56 if (expansion_config.content == 1) 56 if (expansion_config.content == 1)
57 setenv(expansion_config.env_var, expansion_config.env_setting); 57 setenv(expansion_config.env_var, expansion_config.env_setting);
58 58
@@ -81,18 +81,18 @@ index 96fac51..51a90a0 100644
81 switch (get_board_revision()) { 81 switch (get_board_revision()) {
82 case REVISION_XM_A: 82 case REVISION_XM_A:
83diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h 83diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
84index dbe682a..23f19f6 100644 84index 833f86a..1cc46dc 100644
85--- a/include/configs/omap3_beagle.h 85--- a/include/configs/omap3_beagle.h
86+++ b/include/configs/omap3_beagle.h 86+++ b/include/configs/omap3_beagle.h
87@@ -223,6 +223,7 @@ 87@@ -220,6 +220,7 @@
88 "console=ttyS2,115200n8\0" \ 88 "console=ttyO2,115200n8\0" \
89 "mpurate=auto\0" \ 89 "mpurate=auto\0" \
90 "buddy=none "\ 90 "buddy=none "\
91+ "buddy2=none "\ 91+ "buddy2=none "\
92 "optargs=\0" \ 92 "optargs=\0" \
93 "camera=none\0" \ 93 "camera=none\0" \
94 "vram=12M\0" \ 94 "vram=12M\0" \
95@@ -239,6 +240,7 @@ 95@@ -236,6 +237,7 @@
96 "${optargs} " \ 96 "${optargs} " \
97 "mpurate=${mpurate} " \ 97 "mpurate=${mpurate} " \
98 "buddy=${buddy} "\ 98 "buddy=${buddy} "\
@@ -101,5 +101,5 @@ index dbe682a..23f19f6 100644
101 "vram=${vram} " \ 101 "vram=${vram} " \
102 "omapfb.mode=dvi:${dvimode} " \ 102 "omapfb.mode=dvi:${dvimode} " \
103-- 103--
1041.6.6.1 1041.7.2.5
105 105
diff --git a/recipes-bsp/u-boot/u-boot_2011.09.bb b/recipes-bsp/u-boot/u-boot_2011.09.bb
index 8eef7c71..74c8518f 100644
--- a/recipes-bsp/u-boot/u-boot_2011.09.bb
+++ b/recipes-bsp/u-boot/u-boot_2011.09.bb
@@ -1,22 +1,41 @@
1require u-boot.inc 1require u-boot.inc
2 2
3PR = "r4" 3PR = "r5"
4
5# SPL build
6UBOOT_BINARY = "u-boot.img"
7UBOOT_IMAGE = "u-boot-${MACHINE}-${PV}-${PR}.img"
8UBOOT_SYMLINK = "u-boot-${MACHINE}.img"
4 9
5# No patches for other machines yet 10# No patches for other machines yet
6COMPATIBLE_MACHINE = "(beagleboard)" 11COMPATIBLE_MACHINE = "(beagleboard)"
7 12
8SRC_URI = "git://www.denx.de/git/u-boot.git;protocol=git \ 13SRC_URI = "git://www.denx.de/git/u-boot.git;protocol=git \
9 file://2011.09/0001-HACK-beagleboard-config-disable-cache-for-USB.patch \ 14 file://2011.09/0001-omap3-mem-Comment-enable_gpmc_cs_config-more.patch \
10 file://2011.09/0002-beagleboard-config-enable-gpio-command.patch \ 15 file://2011.09/0002-OMAP3-Update-SDRC-dram_init-to-always-call-make_cs1_.patch \
11 file://2011.09/0003-Increased-some-timeout-durations-for-MMC-and-EHCI.patch \ 16 file://2011.09/0003-OMAP3-Add-a-helper-function-to-set-timings-in-SDRC.patch \
12 file://2011.09/0001-beagleboard-add-support-for-TCT-Beacon-board.patch \ 17 file://2011.09/0004-OMAP3-Change-mem_ok-to-clear-again-after-reading-bac.patch \
13 file://2011.09/0001-beagleboard-add-support-for-scanning-loop-through-ex.patch \ 18 file://2011.09/0005-OMAP3-Remove-get_mem_type-prototype.patch \
14 file://2011.09/0002-beagleboard-switch-to-ttyO2.patch \ 19 file://2011.09/0006-omap3-mem-Add-MCFG-helper-macro.patch \
15 file://2011.09/0003-beagleboard-mount-rootfs-RO-instead-of-RW-at-boot.patch \ 20 file://2011.09/0007-OMAP3-Add-optimal-SDRC-autorefresh-control-values.patch \
21 file://2011.09/0008-OMAP3-Suffix-all-Micron-memory-timing-parts-with-the.patch \
22 file://2011.09/0009-OMAP3-SPL-Rework-memory-initalization-and-devkit8000.patch \
23 file://2011.09/0010-OMAP3-SPL-Add-identify_nand_chip-function.patch \
24 file://2011.09/0011-OMAP3-Add-SPL-support-to-Beagleboard.patch \
25 file://2011.09/0012-OMAP3-Add-SPL-support-to-omap3_evm.patch \
26 file://2011.09/0013-AM3517-Add-SPL-support.patch \
27 file://2011.09/0014-AM3517-CraneBoard-Add-SPL-support.patch \
28 file://2011.09/0015-HACK-beagleboard-config-disable-cache-for-USB.patch \
29 file://2011.09/0016-beagleboard-config-enable-gpio-command.patch \
30 file://2011.09/0017-Increased-some-timeout-durations-for-MMC-and-EHCI.patch \
31 file://2011.09/0018-beagleboard-mount-rootfs-RO-instead-of-RW-at-boot.patch \
32 file://2011.09/0019-BeagleBoard-config-Really-switch-to-ttyO2.patch \
33 file://2011.09/0020-beagleboard-add-support-for-TCT-Beacon-board.patch \
34 file://2011.09/0021-beagleboard-add-support-for-scanning-loop-through-ex.patch \
16 file://fw_env.config \ 35 file://fw_env.config \
17 " 36 "
18 37
19SRCREV = "1d5e7fb403257d62f0f2419cb83fdf6b0f02f215" 38SRCREV = "fdbe8b9a2d1858ba35dd6214315563ad44d4a0e3"
20 39
21LIC_FILES_CHKSUM = "file://COPYING;md5=1707d6db1d42237583f50183a5651ecb" 40LIC_FILES_CHKSUM = "file://COPYING;md5=1707d6db1d42237583f50183a5651ecb"
22 41
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-16 16:53:00 +0000