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authorKoen Kooi <koen@dominion.thruhere.net>2011-01-02 16:50:43 +0100
committerKoen Kooi <koen@dominion.thruhere.net>2011-01-03 09:01:08 +0100
commit13a25a08f2d3b6b00d0cf33855978b215390e710 (patch)
treee335843faca564f5b4e4a43e3696a16d13c5a902 /recipes-bsp
parent60f1c4f27eb8d791dc7cc1e21ead3a7749d2d15c (diff)
downloadmeta-ti-13a25a08f2d3b6b00d0cf33855978b215390e710.tar.gz
TI BSP: add support the OMAP35x EVM board
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Diffstat (limited to 'recipes-bsp')
-rw-r--r--recipes-bsp/u-boot/u-boot/0001-omap3evm-Change-default-console-serial-port-from.patch30
-rw-r--r--recipes-bsp/u-boot/u-boot_git.bb15
-rw-r--r--recipes-bsp/x-load/x-load-git/bb8547fcbc54ecc7a75f9ad45a31042a04d8a2ce.patch35
-rw-r--r--recipes-bsp/x-load/x-load-git/name.patch13
-rw-r--r--recipes-bsp/x-load/x-load-git/xm-mem.patch237
-rw-r--r--recipes-bsp/x-load/x-load/0001-OMAP4-clocks-Enable-only-required-clks.patch265
-rw-r--r--recipes-bsp/x-load/x-load/0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch32
-rw-r--r--recipes-bsp/x-load/x-load/0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch33
-rw-r--r--recipes-bsp/x-load/x-load/0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch34
-rw-r--r--recipes-bsp/x-load/x-load/0005-omap4-Make-1GHz-as-default-MPU-clock.patch49
-rw-r--r--recipes-bsp/x-load/x-load_git.bb24
11 files changed, 466 insertions, 301 deletions
diff --git a/recipes-bsp/u-boot/u-boot/0001-omap3evm-Change-default-console-serial-port-from.patch b/recipes-bsp/u-boot/u-boot/0001-omap3evm-Change-default-console-serial-port-from.patch
new file mode 100644
index 00000000..d171b78a
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/0001-omap3evm-Change-default-console-serial-port-from.patch
@@ -0,0 +1,30 @@
1From 6b23ecf49d1c2ee5227ff57101919af46ecd7396 Mon Sep 17 00:00:00 2001
2From: Roger Monk <r-monk@ti.com>
3Date: Fri, 9 Jul 2010 08:37:04 +0100
4Subject: [PATCH] omap3evm: Change default 'console' serial port from ttyS2 to ttyS0
5
6 * Update default kernel console env variable ($(console))
7 to use ttyS0 (instead of ttyS2) to match the serial port
8 used by x-loader and u-boot
9
10Signed-off-by: Roger Monk <r-monk@ti.com>
11---
12 include/configs/omap3_evm.h | 2 +-
13 1 files changed, 1 insertions(+), 1 deletions(-)
14
15diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
16index 73a5c98..d01d733 100644
17--- a/include/configs/omap3_evm.h
18+++ b/include/configs/omap3_evm.h
19@@ -203,7 +203,7 @@
20 #define CONFIG_EXTRA_ENV_SETTINGS \
21 "loadaddr=0x82000000\0" \
22 "usbtty=cdc_acm\0" \
23- "console=ttyS2,115200n8\0" \
24+ "console=ttyS0,115200n8\0" \
25 "mmcargs=setenv bootargs console=${console} " \
26 "root=/dev/mmcblk0p2 rw " \
27 "rootfstype=ext3 rootwait\0" \
28--
291.6.0.4
30
diff --git a/recipes-bsp/u-boot/u-boot_git.bb b/recipes-bsp/u-boot/u-boot_git.bb
index 37508630..3aa69b77 100644
--- a/recipes-bsp/u-boot/u-boot_git.bb
+++ b/recipes-bsp/u-boot/u-boot_git.bb
@@ -3,7 +3,7 @@ PR ="r65"
3 3
4FILESPATHPKG =. "u-boot-git:" 4FILESPATHPKG =. "u-boot-git:"
5 5
6SRC_URI = "git://www.denx.de/git/u-boot.git;protocol=git \ 6SRC_URI_beagleboard = "git://www.denx.de/git/u-boot.git;protocol=git \
7 file://0001-OMAP3-enable-i2c-bus-switching-for-Beagle-and-Overo.patch \ 7 file://0001-OMAP3-enable-i2c-bus-switching-for-Beagle-and-Overo.patch \
8 file://0002-OMAP3-add-board-revision-detection-for-Overo.patch \ 8 file://0002-OMAP3-add-board-revision-detection-for-Overo.patch \
9 file://0003-OMAP3-update-Beagle-revision-detection-to-recognize-.patch \ 9 file://0003-OMAP3-update-Beagle-revision-detection-to-recognize-.patch \
@@ -53,10 +53,17 @@ SRC_URI = "git://www.denx.de/git/u-boot.git;protocol=git \
53 file://0044-Beagleboard-Adjust-boot.patch \ 53 file://0044-Beagleboard-Adjust-boot.patch \
54 file://0045-BeagleBoard-Enable-pullups-on-i2c2.patch \ 54 file://0045-BeagleBoard-Enable-pullups-on-i2c2.patch \
55 file://0046-BeagleBoard-Add-camera-to-default-bootargs.patch \ 55 file://0046-BeagleBoard-Add-camera-to-default-bootargs.patch \
56 file://0001-BeagleBoard-move-ramdisk-parameters.patch \ 56 file://0001-BeagleBoard-move-ramdisk-parameters.patch \
57 file://fw_env.config \ 57 file://fw_env.config \
58" 58"
59SRCREV = "ca6e1c136ddb720c3bb2cc043b99f7f06bc46c55" 59SRCREV_beagleboard = "ca6e1c136ddb720c3bb2cc043b99f7f06bc46c55"
60PV = "2010.03+${PR}+gitr${SRCREV}" 60PV_beagleboard = "2010.03+${PR}+gitr${SRCREV}"
61
62# ~ TI PSP v2009.11_OMAPPSP_03.00.01.06 (+ couple of commits)
63SRC_URI_omap3evm = "git://arago-project.org/git/projects/u-boot-omap3.git;protocol=git \
64 file://0001-omap3evm-Change-default-console-serial-port-from.patch \
65"
66SRCREV_omap3evm = "c0a8fb217fdca7888d89f9a3dee74a4cec865620"
67PV_omap3evm = "2009.11+${PR}+gitr${SRCREV}"
61 68
62S = "${WORKDIR}/git" 69S = "${WORKDIR}/git"
diff --git a/recipes-bsp/x-load/x-load-git/bb8547fcbc54ecc7a75f9ad45a31042a04d8a2ce.patch b/recipes-bsp/x-load/x-load-git/bb8547fcbc54ecc7a75f9ad45a31042a04d8a2ce.patch
deleted file mode 100644
index d447fd0b..00000000
--- a/recipes-bsp/x-load/x-load-git/bb8547fcbc54ecc7a75f9ad45a31042a04d8a2ce.patch
+++ /dev/null
@@ -1,35 +0,0 @@
1From bb8547fcbc54ecc7a75f9ad45a31042a04d8a2ce Mon Sep 17 00:00:00 2001
2From: Laine Walker-Avina <lwalkera@ieee.org>
3Date: Tue, 13 Apr 2010 13:27:31 -0700
4Subject: [PATCH] FAT: Find the start of the first partition in a non-hardcoded way
5
6---
7 fs/fat/fat.c | 12 +++++-------
8 1 files changed, 5 insertions(+), 7 deletions(-)
9
10diff --git a/fs/fat/fat.c b/fs/fat/fat.c
11index eb754c0..c6bdb13 100644
12--- a/fs/fat/fat.c
13+++ b/fs/fat/fat.c
14@@ -145,13 +145,11 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no)
15 return -1;
16 }
17 #else
18- /* FIXME we need to determine the start block of the
19- * partition where the DOS FS resides. This can be done
20- * by using the get_partition_info routine. For this
21- * purpose the libpart must be included.
22- */
23- part_offset=63;
24- //part_offset=0;
25+ part_offset = buffer[DOS_PART_TBL_OFFSET+8] |
26+ buffer[DOS_PART_TBL_OFFSET+9] <<8 |
27+ buffer[DOS_PART_TBL_OFFSET+10]<<16 |
28+ buffer[DOS_PART_TBL_OFFSET+11]<<24;
29+
30 cur_part = 1;
31 #endif
32 }
33--
341.6.1
35
diff --git a/recipes-bsp/x-load/x-load-git/name.patch b/recipes-bsp/x-load/x-load-git/name.patch
deleted file mode 100644
index 1a7aa567..00000000
--- a/recipes-bsp/x-load/x-load-git/name.patch
+++ /dev/null
@@ -1,13 +0,0 @@
1--- git/Makefile-orig 2010-03-08 06:56:36.000000000 -0800
2+++ git/Makefile 2010-03-08 06:56:52.000000000 -0800
3@@ -153,8 +153,8 @@ omap3evm_config : unconfig
4 overo_config : unconfig
5 @./mkconfig $(@:_config=) arm omap3 overo
6
7-omap3530beagle_config : unconfig
8- @./mkconfig $(@:_config=) arm omap3 omap3530beagle
9+beagleboard_config : unconfig
10+ @./mkconfig omap3530beagle arm omap3 omap3530beagle
11
12 #########################################################################
13
diff --git a/recipes-bsp/x-load/x-load-git/xm-mem.patch b/recipes-bsp/x-load/x-load-git/xm-mem.patch
deleted file mode 100644
index d038faf2..00000000
--- a/recipes-bsp/x-load/x-load-git/xm-mem.patch
+++ /dev/null
@@ -1,237 +0,0 @@
1From a25b926ff963a1866e26b11a4dac742564618375 Mon Sep 17 00:00:00 2001
2From: Steve Kipisz <s-kipisz2@ti.com>
3Date: Thu, 8 Jul 2010 10:30:58 -0500
4Subject: [PATCH] Support Micron or Numonyx memory
5
6* Updated Numonyx memory size.
7---
8 board/omap3530beagle/omap3530beagle.c | 56 +++++++++++++++++++++++++++-----
9 drivers/k9f1g08r0a.c | 43 +++++++++++++++++++------
10 include/asm/arch-omap3/mem.h | 43 ++++++++++++++++++++++++-
11 3 files changed, 121 insertions(+), 21 deletions(-)
12
13diff --git a/board/omap3530beagle/omap3530beagle.c b/board/omap3530beagle/omap3530beagle.c
14index eb8008e..1b3d8c7 100644
15--- a/board/omap3530beagle/omap3530beagle.c
16+++ b/board/omap3530beagle/omap3530beagle.c
17@@ -265,6 +265,32 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
18 }
19
20 #ifdef CFG_3430SDRAM_DDR
21+
22+#define MICRON_DDR 0
23+#define NUMONYX_MCP 1
24+int identify_xm_ddr()
25+{
26+ int mfr, id;
27+
28+ __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
29+ __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
30+ __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
31+ __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
32+ __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
33+ __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
34+
35+ /* Enable the GPMC Mapping */
36+ __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
37+ ((NAND_BASE_ADR>>24) & 0x3F) |
38+ (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
39+ delay(2000);
40+
41+ nand_readid(&mfr, &id);
42+ if (mfr == 0)
43+ return MICRON_DDR;
44+ if ((mfr == 0x20) && (id == 0xba))
45+ return NUMONYX_MCP;
46+}
47 /*********************************************************************
48 * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
49 *********************************************************************/
50@@ -279,15 +305,27 @@ void config_3430sdram_ddr(void)
51 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
52
53 if (beagle_revision() == REVISION_XM) {
54- __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
55- __raw_writel(SDP_SDRC_MDCFG_0_DDR_XM, SDRC_MCFG_0);
56- __raw_writel(SDP_SDRC_MDCFG_0_DDR_XM, SDRC_MCFG_1);
57- __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
58- __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
59- __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
60- __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
61- __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
62- __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
63+ if (identify_xm_ddr() == MICRON_DDR) {
64+ __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
65+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
66+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
67+ __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
68+ __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
69+ __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
70+ __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
71+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
72+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
73+ } else {
74+ __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */
75+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0);
76+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1);
77+ __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
78+ __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
79+ __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
80+ __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
81+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
82+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
83+ }
84 } else {
85 __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
86 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
87diff --git a/drivers/k9f1g08r0a.c b/drivers/k9f1g08r0a.c
88index 8968a1b..d2da804 100644
89--- a/drivers/k9f1g08r0a.c
90+++ b/drivers/k9f1g08r0a.c
91@@ -154,6 +154,29 @@ static int NanD_Address(unsigned int numbytes, unsigned long ofs)
92 return 0;
93 }
94
95+int nand_readid(int *mfr, int *id)
96+{
97+ NAND_ENABLE_CE();
98+
99+ if (NanD_Command(NAND_CMD_RESET)) {
100+ NAND_DISABLE_CE();
101+ return 1;
102+ }
103+
104+ if (NanD_Command(NAND_CMD_READID)) {
105+ NAND_DISABLE_CE();
106+ return 1;
107+ }
108+
109+ NanD_Address(ADDR_COLUMN, 0);
110+
111+ *mfr = READ_NAND(NAND_ADDR);
112+ *id = READ_NAND(NAND_ADDR);
113+
114+ NAND_DISABLE_CE();
115+ return 0;
116+}
117+
118 /* read chip mfr and id
119 * return 0 if they match board config
120 * return 1 if not
121@@ -162,23 +185,23 @@ int nand_chip()
122 {
123 int mfr, id;
124
125- NAND_ENABLE_CE();
126+ NAND_ENABLE_CE();
127
128- if (NanD_Command(NAND_CMD_RESET)) {
129- printf("Err: RESET\n");
130- NAND_DISABLE_CE();
131+ if (NanD_Command(NAND_CMD_RESET)) {
132+ printf("Err: RESET\n");
133+ NAND_DISABLE_CE();
134 return 1;
135 }
136
137- if (NanD_Command(NAND_CMD_READID)) {
138- printf("Err: READID\n");
139- NAND_DISABLE_CE();
140+ if (NanD_Command(NAND_CMD_READID)) {
141+ printf("Err: READID\n");
142+ NAND_DISABLE_CE();
143 return 1;
144- }
145+ }
146
147- NanD_Address(ADDR_COLUMN, 0);
148+ NanD_Address(ADDR_COLUMN, 0);
149
150- mfr = READ_NAND(NAND_ADDR);
151+ mfr = READ_NAND(NAND_ADDR);
152 id = READ_NAND(NAND_ADDR);
153
154 NAND_DISABLE_CE();
155diff --git a/include/asm/arch-omap3/mem.h b/include/asm/arch-omap3/mem.h
156index cba4c6f..63cdba1 100644
157--- a/include/asm/arch-omap3/mem.h
158+++ b/include/asm/arch-omap3/mem.h
159@@ -46,6 +46,7 @@ typedef enum {
160 #define MMC_NAND 4
161 #define MMC_ONENAND 5
162 #define GPMC_NONE 6
163+#define GPMC_ONENAND_TRY 7
164
165 #endif
166
167@@ -71,7 +72,8 @@ typedef enum {
168 #define SDP_SDRC_MDCFG_0_DDR (0x02582019|B_ALL) /* Infin ddr module */
169 #else
170 #define SDP_SDRC_MDCFG_0_DDR (0x02584019|B_ALL)
171-#define SDP_SDRC_MDCFG_0_DDR_XM (0x03588019|B_ALL)
172+#define SDP_SDRC_MDCFG_0_DDR_MICRON_XM (0x03588019|B_ALL)
173+#define SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM (0x04590019|B_ALL)
174 #endif
175
176 #define SDP_SDRC_MR_0_DDR 0x00000032
177@@ -252,12 +254,47 @@ typedef enum {
178 (MICRON_TDPL_200 << 6) | (MICRON_TDAL_200))
179
180 #define MICRON_TWTR_200 2
181-#define MICRON_TCKE_200 1
182+#define MICRON_TCKE_200 4
183 #define MICRON_TXP_200 2
184 #define MICRON_XSR_200 23
185 #define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | (MICRON_XSR_200 << 0)) | \
186 (MICRON_TXP_200 << 8) | (MICRON_TWTR_200 << 16)
187
188+/* NUMONYX part of IGEP0020 (165MHz optimized) 6.06ns
189+ * ACTIMA
190+ * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
191+ * TDPL (Twr) = 15/6 = 2.5 -> 3
192+ * TRRD = 12/6 = 2
193+ * TRCD = 22.5/6 = 3.75 -> 4
194+ * TRP = 18/6 = 3
195+ * TRAS = 42/6 = 7
196+ * TRC = 60/6 = 10
197+ * TRFC = 140/6 = 23.3 -> 24
198+ * ACTIMB
199+ * TWTR = 2
200+ * TCKE = 2
201+ * TXSR = 200/6 = 33.3 -> 34
202+ * TXP = 1.0 + 1.1 = 2.1 -> 3 ¿?
203+ */
204+#define NUMONYX_TDAL_165 6
205+#define NUMONYX_TDPL_165 3
206+#define NUMONYX_TRRD_165 2
207+#define NUMONYX_TRCD_165 4
208+#define NUMONYX_TRP_165 3
209+#define NUMONYX_TRAS_165 7
210+#define NUMONYX_TRC_165 10
211+#define NUMONYX_TRFC_165 24
212+#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) \
213+ | (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) |(NUMONYX_TRRD_165 << 9) | \
214+ (NUMONYX_TDPL_165 << 6) | (NUMONYX_TDAL_165))
215+
216+#define NUMONYX_TWTR_165 2
217+#define NUMONYX_TCKE_165 2
218+#define NUMONYX_TXP_165 3
219+#define NUMONYX_XSR_165 34
220+#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | (NUMONYX_XSR_165 << 0)) | \
221+ (NUMONYX_TXP_165 << 8) | (NUMONYX_TWTR_165 << 16)
222+
223 /* New and compatability speed defines */
224 #if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
225 # define L3_100MHZ /* Use with <= 100MHz SDRAM */
226@@ -276,6 +313,8 @@ typedef enum {
227 #elif defined(L3_165MHZ)
228 # define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_165
229 # define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_165
230+# define NUMONYX_SDRC_ACTIM_CTRLA_0 NUMONYX_V_ACTIMA_165
231+# define NUMONYX_SDRC_ACTIM_CTRLB_0 NUMONYX_V_ACTIMB_165
232 #endif
233
234
235--
2361.6.1
237
diff --git a/recipes-bsp/x-load/x-load/0001-OMAP4-clocks-Enable-only-required-clks.patch b/recipes-bsp/x-load/x-load/0001-OMAP4-clocks-Enable-only-required-clks.patch
new file mode 100644
index 00000000..774f1e78
--- /dev/null
+++ b/recipes-bsp/x-load/x-load/0001-OMAP4-clocks-Enable-only-required-clks.patch
@@ -0,0 +1,265 @@
1From 94fee465a6d63b6f0551037fe14cec4410bb9af2 Mon Sep 17 00:00:00 2001
2From: Rajendra Nayak <rnayak@ti.com>
3Date: Tue, 21 Dec 2010 11:55:01 -0200
4Subject: [PATCH 1/5] OMAP4: clocks: Enable only required clks
5
6X-loader untill now, was enabling all clks at bootup
7to help all modules to be functional at the kernel, even
8with drivers which do not handle clks well.
9Now that we are moving towards all drivers being adapted
10to request/release clks as expected, most of this code is
11useless and hence removed.
12
13Signed-off-by: Rajendra Nayak <rnayak@ti.com>
14Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
15---
16 board/omap4430panda/clock.c | 225 ++++++++++++++++++++++---------------------
17 1 files changed, 117 insertions(+), 108 deletions(-)
18
19diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
20index 792e5d6..149fc85 100644
21--- a/board/omap4430panda/clock.c
22+++ b/board/omap4430panda/clock.c
23@@ -552,71 +552,73 @@ static void enable_all_clocks(void)
24 {
25 volatile int regvalue = 0;
26
27- /* Enable Ducati clocks */
28- sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
29- sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
30-
31- wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
32- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
33-
34- /* Enable ivahd and sl2 clocks */
35- sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
36- sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
37- sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
38-
39- wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
40-
41- /* wait for ivahd to become accessible */
42- //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
43- /* wait for sl2 to become accessible */
44- //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
45-
46- /* Enable Tesla clocks */
47- sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
48- sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
49-
50- wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
51-
52- /* wait for tesla to become accessible */
53- //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
54-
55- /* TODO: Some hack needed by MM: Clean this */
56- #if 0 /* Doesn't work on some Zebu */
57- *(volatile int*)0x4a306910 = 0x00000003;
58- *(volatile int*)0x550809a0 = 0x00000001;
59- *(volatile int*)0x55080a20 = 0x00000007;
60- #endif
61-
62- /* ABE clocks */
63- sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
64- sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
65- //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
66- sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
67- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
68- sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
69- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
70- sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
71- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
72- sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
73- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
74- sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
75- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
76- sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
77- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
78- sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
79- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
80- sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
81- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
82- sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
83- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
84- sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
85- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
86- sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
87- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
88- sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
89- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
90- /* Disable sleep transitions */
91- sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
92+ if (omap_revision() == OMAP4430_ES1_0) {
93+ /* Enable Ducati clocks */
94+ sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
95+ sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
96+
97+ wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
98+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
99+
100+ /* Enable ivahd and sl2 clocks */
101+ sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
102+ sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
103+ sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
104+
105+ wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
106+
107+ /* wait for ivahd to become accessible */
108+ //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
109+ /* wait for sl2 to become accessible */
110+ //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
111+
112+ /* Enable Tesla clocks */
113+ sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
114+ sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
115+
116+ wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
117+
118+ /* wait for tesla to become accessible */
119+ //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
120+
121+ /* TODO: Some hack needed by MM: Clean this */
122+ #if 0 /* Doesn't work on some Zebu */
123+ *(volatile int*)0x4a306910 = 0x00000003;
124+ *(volatile int*)0x550809a0 = 0x00000001;
125+ *(volatile int*)0x55080a20 = 0x00000007;
126+ #endif
127+
128+ /* ABE clocks */
129+ sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
130+ sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
131+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
132+ sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
133+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
134+ sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
135+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
136+ sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
137+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
138+ sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
139+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
140+ sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
141+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
142+ sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
143+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
144+ sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
145+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
146+ sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
147+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
148+ sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
149+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
150+ sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
151+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
152+ sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
153+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
154+ sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
155+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
156+ /* Disable sleep transitions */
157+ sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
158+ }
159
160 /* L4PER clocks */
161 sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2);
162@@ -723,50 +725,57 @@ static void enable_all_clocks(void)
163 sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2);
164 wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY);
165
166- /* Enable Camera clocks */
167- sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
168- sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
169- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
170- sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
171- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
172- sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
173-
174- /* Enable DSS clocks */
175- /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
176- *(volatile int*)0x4A307100 = 0x7; //DSS_PRM
177- sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
178- sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
179- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
180- sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
181- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
182- /* Check for DSS Clocks */
183- while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
184- /* Set HW_AUTO transition mode */
185- sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
186-
187- /* Enable SGX clocks */
188- sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
189- sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
190- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
191- /* Check for SGX FCLK and ICLK */
192- while ( (*(volatile int*)0x4A009200) != 0x302 );
193- //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
194- /* Enable hsi/unipro/usb clocks */
195- sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
196- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
197- sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
198- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
199- sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
200- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
201- sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
202- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
203- sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
204- //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
205- sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
206- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
207- /* enable the 32K, 48M optional clocks and enable the module */
208+ if (omap_revision() == OMAP4430_ES1_0) {
209+ /* Enable Camera clocks */
210+ sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
211+ sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
212+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
213+ sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
214+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
215+ sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
216+
217+ /* Enable DSS clocks */
218+ /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
219+ *(volatile int*)0x4A307100 = 0x7; //DSS_PRM
220+ sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
221+ sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
222+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
223+ sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
224+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
225+ /* Check for DSS Clocks */
226+ while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
227+ /* Set HW_AUTO transition mode */
228+ sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
229+
230+ /* Enable SGX clocks */
231+ sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
232+ sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
233+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
234+ /* Check for SGX FCLK and ICLK */
235+ while ( (*(volatile int*)0x4A009200) != 0x302 );
236+ //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
237+ /* Enable hsi/unipro/usb clocks */
238+ sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
239+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
240+ sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
241+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
242+ sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
243+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
244+ sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
245+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
246+ sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
247+ //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
248+ sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
249+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
250+ /* enable the 32K, 48M optional clocks and enable the module */
251+ sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
252+ //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
253+ }
254+
255+ /* Enable clocks for USB fast boot to work */
256 sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
257- //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
258+ sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
259+
260 return;
261 }
262
263--
2641.6.6.1
265
diff --git a/recipes-bsp/x-load/x-load/0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch b/recipes-bsp/x-load/x-load/0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch
new file mode 100644
index 00000000..ffcf8591
--- /dev/null
+++ b/recipes-bsp/x-load/x-load/0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch
@@ -0,0 +1,32 @@
1From fff093ab92c5dadd646130c38097dc167d2d0e1e Mon Sep 17 00:00:00 2001
2From: Rajeev Kulkarni <rajeevk@ti.com>
3Date: Tue, 26 Oct 2010 07:34:43 -0500
4Subject: [PATCH 2/5] OMAP4: Select DPLL PER Clock as source for SGX FCLK
5
6The correct frequncy for SGX is 307.2 Mhz.. If DPLL_PER
7is set 1536 Mhz, There is no need to change dividers, just
8parent clock need to change. And DPLL PER is set at 1536.
9
10Signed-off-by: Rajeev Kulkarni <rajeevk@ti.com>
11Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
12---
13 board/omap4430panda/clock.c | 3 +++
14 1 files changed, 3 insertions(+), 0 deletions(-)
15
16diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
17index 149fc85..0961f51 100644
18--- a/board/omap4430panda/clock.c
19+++ b/board/omap4430panda/clock.c
20@@ -772,6 +772,9 @@ static void enable_all_clocks(void)
21 //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
22 }
23
24+ /* Select DPLL PER CLOCK as source for SGX FCLK */
25+ sr32(CM_SGX_SGX_CLKCTRL, 24, 1, 0x1);
26+
27 /* Enable clocks for USB fast boot to work */
28 sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
29 sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
30--
311.6.6.1
32
diff --git a/recipes-bsp/x-load/x-load/0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch b/recipes-bsp/x-load/x-load/0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch
new file mode 100644
index 00000000..1475308f
--- /dev/null
+++ b/recipes-bsp/x-load/x-load/0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch
@@ -0,0 +1,33 @@
1From daaaf036f3336e01a83a13dd93b8030b00a0af50 Mon Sep 17 00:00:00 2001
2From: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
3Date: Tue, 21 Dec 2010 12:03:50 -0200
4Subject: [PATCH 3/5] MUX: Configure SYS_NIRQ2 pin in safe mode
5
6SYS_NIRQ2 pin if not in safe mode, with audio driver
7enabled gates CORE RET. Hence configured in safe mode.
8Audio driver is expected to re-init the pin in the
9kernel.
10
11Patch from sdp, by Rajendra Nayak <rnayak@ti.com>
12
13Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
14---
15 board/omap4430panda/omap4430panda.c | 2 +-
16 1 files changed, 1 insertions(+), 1 deletions(-)
17
18diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c
19index 5695733..814b2cb 100644
20--- a/board/omap4430panda/omap4430panda.c
21+++ b/board/omap4430panda/omap4430panda.c
22@@ -910,7 +910,7 @@ int dram_init(void)
23 MV(CP(FREF_CLK1_OUT) , ( M0)) /* fref_clk1_out */ \
24 MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3)) /* gpio_182 */ \
25 MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0)) /* sys_nirq1 */ \
26- MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0)) /* sys_nirq2 */ \
27+ MV(CP(SYS_NIRQ2) , (M7_SAFE)) /* sys_nirq2 */ \
28 MV(CP(SYS_BOOT0) , ( PTU | IEN | M3)) /* gpio_184 */ \
29 MV(CP(SYS_BOOT1) , ( M3)) /* gpio_185 */ \
30 MV(CP(SYS_BOOT2) , ( PTD | IEN | M3)) /* gpio_186 */ \
31--
321.6.6.1
33
diff --git a/recipes-bsp/x-load/x-load/0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch b/recipes-bsp/x-load/x-load/0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch
new file mode 100644
index 00000000..9b6e2f9d
--- /dev/null
+++ b/recipes-bsp/x-load/x-load/0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch
@@ -0,0 +1,34 @@
1From 4af562525c7779cd41ae9a68d56771407df558d7 Mon Sep 17 00:00:00 2001
2From: Rajendra Nayak <rnayak@ti.com>
3Date: Mon, 4 Oct 2010 18:49:18 +0530
4Subject: [PATCH 4/5] OMAP4: clocks: Disable slimbus and pad_clks
5
6The slimbus and pad_clks if left enabled in x-loader
7would gate abe power domain from transitioning to RET.
8
9These should be enabled by the audio driver (if present)
10in the kernel.
11
12Signed-off-by: Rajendra Nayak <rnayak@ti.com>
13Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
14---
15 board/omap4430panda/clock.c | 3 ---
16 1 files changed, 0 insertions(+), 3 deletions(-)
17
18diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
19index 0961f51..c591a9f 100644
20--- a/board/omap4430panda/clock.c
21+++ b/board/omap4430panda/clock.c
22@@ -333,9 +333,6 @@ static void configure_abe_dpll(u32 clk_index)
23 /* Select sys_clk as ref clk for ABE dpll */
24 sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0);
25
26- /* Enable slimbus and pad clocks */
27- sr32(CM_CLKSEL_ABE, 0, 32, 0x500);
28-
29 /* Unlock the ABE dpll */
30 sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS);
31 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY);
32--
331.6.6.1
34
diff --git a/recipes-bsp/x-load/x-load/0005-omap4-Make-1GHz-as-default-MPU-clock.patch b/recipes-bsp/x-load/x-load/0005-omap4-Make-1GHz-as-default-MPU-clock.patch
new file mode 100644
index 00000000..7c23f604
--- /dev/null
+++ b/recipes-bsp/x-load/x-load/0005-omap4-Make-1GHz-as-default-MPU-clock.patch
@@ -0,0 +1,49 @@
1From ce1ae065d5eb875990f55ede0405e061e4d4b8d3 Mon Sep 17 00:00:00 2001
2From: Sebastien Jan <s-jan@ti.com>
3Date: Wed, 22 Dec 2010 13:53:18 +0100
4Subject: [PATCH 5/5] omap4: Make 1GHz as default MPU clock
5
6Signed-off-by: Aneesh V <aneesh@ti.com>
7Signed-off-by: Rajendra Nayak <rnayak@ti.com>
8Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
9Signed-off-by: Sebastien Jan <s-jan@ti.com>
10Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
11---
12 Makefile | 8 ++++++++
13 include/configs/omap4430panda.h | 1 -
14 2 files changed, 8 insertions(+), 1 deletions(-)
15
16diff --git a/Makefile b/Makefile
17index d134fdc..1c4fdd5 100644
18--- a/Makefile
19+++ b/Makefile
20@@ -170,6 +170,14 @@ omap3530beagle_config : unconfig
21 #########################################################################
22 omap4430panda_config : unconfig
23 @./mkconfig $(@:_config=) arm omap4 omap4430panda
24+ @[ -n "$(findstring _MPU_600MHz,$@)" ] || \
25+ { echo "#define CONFIG_MPU_1000 1" >> $(obj)include/config.h; \
26+ echo "MPU at 1GHz revision.."; \
27+ }
28+ @[ -z "$(findstring _MPU_600MHz,$@)" ] || \
29+ { echo "#define CONFIG_MPU_600 1" >> $(obj)include/config.h; \
30+ echo "MPU at 600MHz revision.."; \
31+ }
32
33 #########################################################################
34
35diff --git a/include/configs/omap4430panda.h b/include/configs/omap4430panda.h
36index 74e2f42..eae02ef 100644
37--- a/include/configs/omap4430panda.h
38+++ b/include/configs/omap4430panda.h
39@@ -44,7 +44,6 @@
40 * On Phoenix board vlotage needs to be bumped up
41 * before scaling the MPU up
42 */
43-#define CONFIG_MPU_600 1
44 #define CORE_190MHZ 1
45 /* Enable the below macro if MMC boot support is required */
46 #define CONFIG_MMC 1
47--
481.6.6.1
49
diff --git a/recipes-bsp/x-load/x-load_git.bb b/recipes-bsp/x-load/x-load_git.bb
index f45bac95..ddb20907 100644
--- a/recipes-bsp/x-load/x-load_git.bb
+++ b/recipes-bsp/x-load/x-load_git.bb
@@ -1,22 +1,22 @@
1require x-load.inc 1require x-load.inc
2 2
3DEFAULT_PREFERENCE_omap3-pandora = "-1" 3#FILESPATHPKG_prepend = "x-load-git:x-load-git/${MACHINE}"
4
5FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/x-load-git"
6
7SRCREV_pn-${PN} = "1c9276af4d6a5b7014a7630a1abeddf3b3177563"
8 4
9PV = "1.44+${PR}+gitr${SRCREV}" 5PV = "1.44+${PR}+gitr${SRCREV}"
10PR ="r16" 6PR ="r17"
11PE = "1" 7PE = "1"
12 8
13SRC_URI = "git://gitorious.org/x-load-omap3/mainline.git;branch=master;protocol=git" 9SRCREV_pn-${PN} = "6f3a26101303051e0f91b6213735b68ce804e94e"
10SRC_URI = "git://gitorious.org/x-loader/x-loader.git;branch=master;protocol=git \
11 file://0001-OMAP4-clocks-Enable-only-required-clks.patch \
12 file://0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch \
13 file://0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch \
14 file://0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch \
15 file://0005-omap4-Make-1GHz-as-default-MPU-clock.patch \
16 "
14 17
15SRC_URI_append_beagleboard = " \
16 file://name.patch \
17 file://bb8547fcbc54ecc7a75f9ad45a31042a04d8a2ce.patch \
18 file://xm-mem.patch \
19 "
20S = "${WORKDIR}/git" 18S = "${WORKDIR}/git"
21 19
20XLOAD_MACHINE_beagleboard = "omap3530beagle_config"
21
22PACKAGE_ARCH = "${MACHINE_ARCH}" 22PACKAGE_ARCH = "${MACHINE_ARCH}"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-16 07:28:20 +0000