diff options
author | Koen Kooi <koen@dominion.thruhere.net> | 2011-03-25 09:48:24 +0100 |
---|---|---|
committer | Koen Kooi <koen@dominion.thruhere.net> | 2011-03-25 09:48:24 +0100 |
commit | aefbc8ddedd8253623dbe9539852a1e8c096faf7 (patch) | |
tree | 9a96de82012c491817735038275868e79bc3a5b7 /recipes-bsp/x-load | |
parent | 11c815f2268d7b9ab8939fe20ee2c3df9b7a37c9 (diff) | |
download | meta-ti-aefbc8ddedd8253623dbe9539852a1e8c096faf7.tar.gz |
x-load git: update to 1.5.0
Tested on beagle-xm/angstrom and pandaboard/angstrom
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Diffstat (limited to 'recipes-bsp/x-load')
7 files changed, 3 insertions, 475 deletions
diff --git a/recipes-bsp/x-load/x-load/0001-OMAP4-clocks-Enable-only-required-clks.patch b/recipes-bsp/x-load/x-load/0001-OMAP4-clocks-Enable-only-required-clks.patch deleted file mode 100644 index 6cec4ef8..00000000 --- a/recipes-bsp/x-load/x-load/0001-OMAP4-clocks-Enable-only-required-clks.patch +++ /dev/null | |||
@@ -1,265 +0,0 @@ | |||
1 | From 7c5a2dd1e20702d220bd75910f7cfb6141230e5b Mon Sep 17 00:00:00 2001 | ||
2 | From: Rajendra Nayak <rnayak@ti.com> | ||
3 | Date: Tue, 21 Dec 2010 11:55:01 -0200 | ||
4 | Subject: [PATCH 1/5] OMAP4: clocks: Enable only required clks | ||
5 | |||
6 | X-loader untill now, was enabling all clks at bootup | ||
7 | to help all modules to be functional at the kernel, even | ||
8 | with drivers which do not handle clks well. | ||
9 | Now that we are moving towards all drivers being adapted | ||
10 | to request/release clks as expected, most of this code is | ||
11 | useless and hence removed. | ||
12 | |||
13 | Signed-off-by: Rajendra Nayak <rnayak@ti.com> | ||
14 | Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> | ||
15 | --- | ||
16 | board/omap4430panda/clock.c | 225 ++++++++++++++++++++++--------------------- | ||
17 | 1 files changed, 117 insertions(+), 108 deletions(-) | ||
18 | |||
19 | diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c | ||
20 | index a83f1c6..b323885 100644 | ||
21 | --- a/board/omap4430panda/clock.c | ||
22 | +++ b/board/omap4430panda/clock.c | ||
23 | @@ -552,71 +552,73 @@ static void enable_all_clocks(void) | ||
24 | { | ||
25 | volatile int regvalue = 0; | ||
26 | |||
27 | - /* Enable Ducati clocks */ | ||
28 | - sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1); | ||
29 | - sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2); | ||
30 | - | ||
31 | - wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY); | ||
32 | - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY); | ||
33 | - | ||
34 | - /* Enable ivahd and sl2 clocks */ | ||
35 | - sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1); | ||
36 | - sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1); | ||
37 | - sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2); | ||
38 | - | ||
39 | - wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY); | ||
40 | - | ||
41 | - /* wait for ivahd to become accessible */ | ||
42 | - //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY); | ||
43 | - /* wait for sl2 to become accessible */ | ||
44 | - //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY); | ||
45 | - | ||
46 | - /* Enable Tesla clocks */ | ||
47 | - sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1); | ||
48 | - sr32(DSP_CLKSTCTRL, 0, 32, 0x2); | ||
49 | - | ||
50 | - wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY); | ||
51 | - | ||
52 | - /* wait for tesla to become accessible */ | ||
53 | - //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY); | ||
54 | - | ||
55 | - /* TODO: Some hack needed by MM: Clean this */ | ||
56 | - #if 0 /* Doesn't work on some Zebu */ | ||
57 | - *(volatile int*)0x4a306910 = 0x00000003; | ||
58 | - *(volatile int*)0x550809a0 = 0x00000001; | ||
59 | - *(volatile int*)0x55080a20 = 0x00000007; | ||
60 | - #endif | ||
61 | - | ||
62 | - /* ABE clocks */ | ||
63 | - sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3); | ||
64 | - sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2); | ||
65 | - //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY); | ||
66 | - sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2); | ||
67 | - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY); | ||
68 | - sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2); | ||
69 | - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY); | ||
70 | - sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2); | ||
71 | - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY); | ||
72 | - sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002); | ||
73 | - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY); | ||
74 | - sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002); | ||
75 | - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY); | ||
76 | - sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002); | ||
77 | - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY); | ||
78 | - sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02); | ||
79 | - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY); | ||
80 | - sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2); | ||
81 | - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY); | ||
82 | - sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2); | ||
83 | - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY); | ||
84 | - sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2); | ||
85 | - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY); | ||
86 | - sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2); | ||
87 | - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY); | ||
88 | - sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2); | ||
89 | - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY); | ||
90 | - /* Disable sleep transitions */ | ||
91 | - sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0); | ||
92 | + if (omap_revision() == OMAP4430_ES1_0) { | ||
93 | + /* Enable Ducati clocks */ | ||
94 | + sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1); | ||
95 | + sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2); | ||
96 | + | ||
97 | + wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY); | ||
98 | + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY); | ||
99 | + | ||
100 | + /* Enable ivahd and sl2 clocks */ | ||
101 | + sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1); | ||
102 | + sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1); | ||
103 | + sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2); | ||
104 | + | ||
105 | + wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY); | ||
106 | + | ||
107 | + /* wait for ivahd to become accessible */ | ||
108 | + //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY); | ||
109 | + /* wait for sl2 to become accessible */ | ||
110 | + //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY); | ||
111 | + | ||
112 | + /* Enable Tesla clocks */ | ||
113 | + sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1); | ||
114 | + sr32(DSP_CLKSTCTRL, 0, 32, 0x2); | ||
115 | + | ||
116 | + wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY); | ||
117 | + | ||
118 | + /* wait for tesla to become accessible */ | ||
119 | + //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY); | ||
120 | + | ||
121 | + /* TODO: Some hack needed by MM: Clean this */ | ||
122 | + #if 0 /* Doesn't work on some Zebu */ | ||
123 | + *(volatile int*)0x4a306910 = 0x00000003; | ||
124 | + *(volatile int*)0x550809a0 = 0x00000001; | ||
125 | + *(volatile int*)0x55080a20 = 0x00000007; | ||
126 | + #endif | ||
127 | + | ||
128 | + /* ABE clocks */ | ||
129 | + sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3); | ||
130 | + sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2); | ||
131 | + //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY); | ||
132 | + sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2); | ||
133 | + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY); | ||
134 | + sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2); | ||
135 | + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY); | ||
136 | + sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2); | ||
137 | + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY); | ||
138 | + sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002); | ||
139 | + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY); | ||
140 | + sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002); | ||
141 | + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY); | ||
142 | + sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002); | ||
143 | + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY); | ||
144 | + sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02); | ||
145 | + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY); | ||
146 | + sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2); | ||
147 | + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY); | ||
148 | + sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2); | ||
149 | + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY); | ||
150 | + sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2); | ||
151 | + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY); | ||
152 | + sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2); | ||
153 | + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY); | ||
154 | + sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2); | ||
155 | + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY); | ||
156 | + /* Disable sleep transitions */ | ||
157 | + sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0); | ||
158 | + } | ||
159 | |||
160 | /* L4PER clocks */ | ||
161 | sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2); | ||
162 | @@ -723,50 +725,57 @@ static void enable_all_clocks(void) | ||
163 | sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2); | ||
164 | wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY); | ||
165 | |||
166 | - /* Enable Camera clocks */ | ||
167 | - sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3); | ||
168 | - sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102); | ||
169 | - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY); | ||
170 | - sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2); | ||
171 | - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY); | ||
172 | - sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0); | ||
173 | - | ||
174 | - /* Enable DSS clocks */ | ||
175 | - /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */ | ||
176 | - *(volatile int*)0x4A307100 = 0x7; //DSS_PRM | ||
177 | - sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2); | ||
178 | - sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02); | ||
179 | - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY); | ||
180 | - sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2); | ||
181 | - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY); | ||
182 | - /* Check for DSS Clocks */ | ||
183 | - while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00) | ||
184 | - /* Set HW_AUTO transition mode */ | ||
185 | - sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3); | ||
186 | - | ||
187 | - /* Enable SGX clocks */ | ||
188 | - sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2); | ||
189 | - sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2); | ||
190 | - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY); | ||
191 | - /* Check for SGX FCLK and ICLK */ | ||
192 | - while ( (*(volatile int*)0x4A009200) != 0x302 ); | ||
193 | - //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0); | ||
194 | - /* Enable hsi/unipro/usb clocks */ | ||
195 | - sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1); | ||
196 | - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY); | ||
197 | - sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2); | ||
198 | - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY); | ||
199 | - sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2); | ||
200 | - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY); | ||
201 | - sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1); | ||
202 | - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY); | ||
203 | - sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1); | ||
204 | - //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY); | ||
205 | - sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2); | ||
206 | - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY); | ||
207 | - /* enable the 32K, 48M optional clocks and enable the module */ | ||
208 | + if (omap_revision() == OMAP4430_ES1_0) { | ||
209 | + /* Enable Camera clocks */ | ||
210 | + sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3); | ||
211 | + sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102); | ||
212 | + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY); | ||
213 | + sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2); | ||
214 | + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY); | ||
215 | + sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0); | ||
216 | + | ||
217 | + /* Enable DSS clocks */ | ||
218 | + /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */ | ||
219 | + *(volatile int*)0x4A307100 = 0x7; //DSS_PRM | ||
220 | + sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2); | ||
221 | + sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02); | ||
222 | + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY); | ||
223 | + sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2); | ||
224 | + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY); | ||
225 | + /* Check for DSS Clocks */ | ||
226 | + while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00) | ||
227 | + /* Set HW_AUTO transition mode */ | ||
228 | + sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3); | ||
229 | + | ||
230 | + /* Enable SGX clocks */ | ||
231 | + sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2); | ||
232 | + sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2); | ||
233 | + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY); | ||
234 | + /* Check for SGX FCLK and ICLK */ | ||
235 | + while ( (*(volatile int*)0x4A009200) != 0x302 ); | ||
236 | + //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0); | ||
237 | + /* Enable hsi/unipro/usb clocks */ | ||
238 | + sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1); | ||
239 | + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY); | ||
240 | + sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2); | ||
241 | + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY); | ||
242 | + sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2); | ||
243 | + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY); | ||
244 | + sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1); | ||
245 | + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY); | ||
246 | + sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1); | ||
247 | + //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY); | ||
248 | + sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2); | ||
249 | + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY); | ||
250 | + /* enable the 32K, 48M optional clocks and enable the module */ | ||
251 | + sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301); | ||
252 | + //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY); | ||
253 | + } | ||
254 | + | ||
255 | + /* Enable clocks for USB fast boot to work */ | ||
256 | sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301); | ||
257 | - //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY); | ||
258 | + sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1); | ||
259 | + | ||
260 | return; | ||
261 | } | ||
262 | |||
263 | -- | ||
264 | 1.6.6.1 | ||
265 | |||
diff --git a/recipes-bsp/x-load/x-load/0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch b/recipes-bsp/x-load/x-load/0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch deleted file mode 100644 index 8e62d2fd..00000000 --- a/recipes-bsp/x-load/x-load/0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | From 17028354b438883e98668803bf433d8a0bae12a1 Mon Sep 17 00:00:00 2001 | ||
2 | From: Rajeev Kulkarni <rajeevk@ti.com> | ||
3 | Date: Tue, 26 Oct 2010 07:34:43 -0500 | ||
4 | Subject: [PATCH 2/5] OMAP4: Select DPLL PER Clock as source for SGX FCLK | ||
5 | |||
6 | The correct frequncy for SGX is 307.2 Mhz.. If DPLL_PER | ||
7 | is set 1536 Mhz, There is no need to change dividers, just | ||
8 | parent clock need to change. And DPLL PER is set at 1536. | ||
9 | |||
10 | Signed-off-by: Rajeev Kulkarni <rajeevk@ti.com> | ||
11 | Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> | ||
12 | --- | ||
13 | board/omap4430panda/clock.c | 3 +++ | ||
14 | 1 files changed, 3 insertions(+), 0 deletions(-) | ||
15 | |||
16 | diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c | ||
17 | index b323885..4404cc5 100644 | ||
18 | --- a/board/omap4430panda/clock.c | ||
19 | +++ b/board/omap4430panda/clock.c | ||
20 | @@ -772,6 +772,9 @@ static void enable_all_clocks(void) | ||
21 | //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY); | ||
22 | } | ||
23 | |||
24 | + /* Select DPLL PER CLOCK as source for SGX FCLK */ | ||
25 | + sr32(CM_SGX_SGX_CLKCTRL, 24, 1, 0x1); | ||
26 | + | ||
27 | /* Enable clocks for USB fast boot to work */ | ||
28 | sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301); | ||
29 | sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1); | ||
30 | -- | ||
31 | 1.6.6.1 | ||
32 | |||
diff --git a/recipes-bsp/x-load/x-load/0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch b/recipes-bsp/x-load/x-load/0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch deleted file mode 100644 index 7f9b7672..00000000 --- a/recipes-bsp/x-load/x-load/0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | From 3421142b95238893a90032c3056123544c353752 Mon Sep 17 00:00:00 2001 | ||
2 | From: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> | ||
3 | Date: Tue, 21 Dec 2010 12:03:50 -0200 | ||
4 | Subject: [PATCH 3/5] MUX: Configure SYS_NIRQ2 pin in safe mode | ||
5 | |||
6 | SYS_NIRQ2 pin if not in safe mode, with audio driver | ||
7 | enabled gates CORE RET. Hence configured in safe mode. | ||
8 | Audio driver is expected to re-init the pin in the | ||
9 | kernel. | ||
10 | |||
11 | Patch from sdp, by Rajendra Nayak <rnayak@ti.com> | ||
12 | |||
13 | Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> | ||
14 | --- | ||
15 | board/omap4430panda/omap4430panda.c | 2 +- | ||
16 | 1 files changed, 1 insertions(+), 1 deletions(-) | ||
17 | |||
18 | diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c | ||
19 | index a91e2aa..f6f515b 100644 | ||
20 | --- a/board/omap4430panda/omap4430panda.c | ||
21 | +++ b/board/omap4430panda/omap4430panda.c | ||
22 | @@ -910,7 +910,7 @@ int dram_init(void) | ||
23 | MV(CP(FREF_CLK1_OUT) , ( M0)) /* fref_clk1_out */ \ | ||
24 | MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3)) /* gpio_182 */ \ | ||
25 | MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0)) /* sys_nirq1 */ \ | ||
26 | - MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0)) /* sys_nirq2 */ \ | ||
27 | + MV(CP(SYS_NIRQ2) , (M7_SAFE)) /* sys_nirq2 */ \ | ||
28 | MV(CP(SYS_BOOT0) , ( PTU | IEN | M3)) /* gpio_184 */ \ | ||
29 | MV(CP(SYS_BOOT1) , ( M3)) /* gpio_185 */ \ | ||
30 | MV(CP(SYS_BOOT2) , ( PTD | IEN | M3)) /* gpio_186 */ \ | ||
31 | -- | ||
32 | 1.6.6.1 | ||
33 | |||
diff --git a/recipes-bsp/x-load/x-load/0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch b/recipes-bsp/x-load/x-load/0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch deleted file mode 100644 index e3107121..00000000 --- a/recipes-bsp/x-load/x-load/0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | From 14a48e4b24aee2387f8e4cd3b480236451fe1294 Mon Sep 17 00:00:00 2001 | ||
2 | From: Rajendra Nayak <rnayak@ti.com> | ||
3 | Date: Mon, 4 Oct 2010 18:49:18 +0530 | ||
4 | Subject: [PATCH 4/5] OMAP4: clocks: Disable slimbus and pad_clks | ||
5 | |||
6 | The slimbus and pad_clks if left enabled in x-loader | ||
7 | would gate abe power domain from transitioning to RET. | ||
8 | |||
9 | These should be enabled by the audio driver (if present) | ||
10 | in the kernel. | ||
11 | |||
12 | Signed-off-by: Rajendra Nayak <rnayak@ti.com> | ||
13 | Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> | ||
14 | --- | ||
15 | board/omap4430panda/clock.c | 3 --- | ||
16 | 1 files changed, 0 insertions(+), 3 deletions(-) | ||
17 | |||
18 | diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c | ||
19 | index 4404cc5..e41f327 100644 | ||
20 | --- a/board/omap4430panda/clock.c | ||
21 | +++ b/board/omap4430panda/clock.c | ||
22 | @@ -333,9 +333,6 @@ static void configure_abe_dpll(u32 clk_index) | ||
23 | /* Select sys_clk as ref clk for ABE dpll */ | ||
24 | sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0); | ||
25 | |||
26 | - /* Enable slimbus and pad clocks */ | ||
27 | - sr32(CM_CLKSEL_ABE, 0, 32, 0x500); | ||
28 | - | ||
29 | /* Unlock the ABE dpll */ | ||
30 | sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS); | ||
31 | wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY); | ||
32 | -- | ||
33 | 1.6.6.1 | ||
34 | |||
diff --git a/recipes-bsp/x-load/x-load/0005-omap4-Make-1GHz-as-default-MPU-clock.patch b/recipes-bsp/x-load/x-load/0005-omap4-Make-1GHz-as-default-MPU-clock.patch deleted file mode 100644 index 3008e6da..00000000 --- a/recipes-bsp/x-load/x-load/0005-omap4-Make-1GHz-as-default-MPU-clock.patch +++ /dev/null | |||
@@ -1,50 +0,0 @@ | |||
1 | From 76ebc9fdbfff91f226bc559706e3e7ece43ec30d Mon Sep 17 00:00:00 2001 | ||
2 | From: Sebastien Jan <s-jan@ti.com> | ||
3 | Date: Wed, 22 Dec 2010 13:53:18 +0100 | ||
4 | Subject: [PATCH 5/5] omap4: Make 1GHz as default MPU clock | ||
5 | |||
6 | Signed-off-by: Aneesh V <aneesh@ti.com> | ||
7 | Signed-off-by: Rajendra Nayak <rnayak@ti.com> | ||
8 | Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> | ||
9 | Signed-off-by: Sebastien Jan <s-jan@ti.com> | ||
10 | Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> | ||
11 | --- | ||
12 | Makefile | 9 +++++++++ | ||
13 | include/configs/omap4430panda.h | 1 - | ||
14 | 2 files changed, 9 insertions(+), 1 deletions(-) | ||
15 | |||
16 | diff --git a/Makefile b/Makefile | ||
17 | index fd85142..6258324 100644 | ||
18 | --- a/Makefile | ||
19 | +++ b/Makefile | ||
20 | @@ -235,6 +235,15 @@ igep0020_config : unconfig | ||
21 | ######################################################################### | ||
22 | omap4430panda_config : unconfig | ||
23 | @./mkconfig $(@:_config=) arm omap4 omap4430panda 1 | ||
24 | + @./mkconfig $(@:_config=) arm omap4 omap4430panda 1 | ||
25 | + @[ -n "$(findstring _MPU_600MHz,$@)" ] || \ | ||
26 | + { echo "#define CONFIG_MPU_1000 1" >> $(obj)include/config.h; \ | ||
27 | + echo "MPU at 1GHz revision.."; \ | ||
28 | + } | ||
29 | + @[ -z "$(findstring _MPU_600MHz,$@)" ] || \ | ||
30 | + { echo "#define CONFIG_MPU_600 1" >> $(obj)include/config.h; \ | ||
31 | + echo "MPU at 600MHz revision.."; \ | ||
32 | + } | ||
33 | |||
34 | ######################################################################### | ||
35 | |||
36 | diff --git a/include/configs/omap4430panda.h b/include/configs/omap4430panda.h | ||
37 | index 74e2f42..eae02ef 100644 | ||
38 | --- a/include/configs/omap4430panda.h | ||
39 | +++ b/include/configs/omap4430panda.h | ||
40 | @@ -44,7 +44,6 @@ | ||
41 | * On Phoenix board vlotage needs to be bumped up | ||
42 | * before scaling the MPU up | ||
43 | */ | ||
44 | -#define CONFIG_MPU_600 1 | ||
45 | #define CORE_190MHZ 1 | ||
46 | /* Enable the below macro if MMC boot support is required */ | ||
47 | #define CONFIG_MMC 1 | ||
48 | -- | ||
49 | 1.6.6.1 | ||
50 | |||
diff --git a/recipes-bsp/x-load/x-load/xmc.patch b/recipes-bsp/x-load/x-load/xmc.patch deleted file mode 100644 index bddcb8fc..00000000 --- a/recipes-bsp/x-load/x-load/xmc.patch +++ /dev/null | |||
@@ -1,52 +0,0 @@ | |||
1 | From b35937bf29c828e311f1d9bb1385bd32d34ec060 Mon Sep 17 00:00:00 2001 | ||
2 | From: Jason Kridner <jkridner@beagleboard.org> | ||
3 | Date: Mon, 7 Mar 2011 19:31:15 -0600 | ||
4 | Subject: [PATCH] Forced newer revisions to default to xM. | ||
5 | |||
6 | --- | ||
7 | board/omap3530beagle/omap3530beagle.c | 15 ++++++++++++++- | ||
8 | 1 files changed, 14 insertions(+), 1 deletions(-) | ||
9 | |||
10 | diff --git a/board/omap3530beagle/omap3530beagle.c b/board/omap3530beagle/omap3530beagle.c | ||
11 | index 1b3d8c7..d55d32e 100644 | ||
12 | --- a/board/omap3530beagle/omap3530beagle.c | ||
13 | +++ b/board/omap3530beagle/omap3530beagle.c | ||
14 | @@ -212,6 +212,7 @@ u32 cpu_is_3410(void) | ||
15 | * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3 | ||
16 | * GPIO173, GPIO172, GPIO171: 1 0 1 => C4 | ||
17 | * GPIO173, GPIO172, GPIO171: 0 0 0 => XM | ||
18 | + * default => XM | ||
19 | ******************************************/ | ||
20 | int beagle_revision(void) | ||
21 | { | ||
22 | @@ -227,6 +228,18 @@ int beagle_revision(void) | ||
23 | rev = omap_get_gpio_datain(173) << 2 | | ||
24 | omap_get_gpio_datain(172) << 1 | | ||
25 | omap_get_gpio_datain(171); | ||
26 | + | ||
27 | + /* Default newer board revisions to XM */ | ||
28 | + switch(rev) { | ||
29 | + case REVISION_AXBX: | ||
30 | + case REVISION_CX: | ||
31 | + case REVISION_C4: | ||
32 | + break; | ||
33 | + case REVISION_XM: | ||
34 | + default: | ||
35 | + rev = REVISION_XM; | ||
36 | + } | ||
37 | + | ||
38 | omap_free_gpio(171); | ||
39 | omap_free_gpio(172); | ||
40 | omap_free_gpio(173); | ||
41 | @@ -662,7 +675,7 @@ int misc_init_r(void) | ||
42 | printf("Beagle Rev C4\n"); | ||
43 | break; | ||
44 | case REVISION_XM: | ||
45 | - printf("Beagle xM Rev A\n"); | ||
46 | + printf("Beagle xM\n"); | ||
47 | break; | ||
48 | default: | ||
49 | printf("Beagle unknown 0x%02x\n", rev); | ||
50 | -- | ||
51 | 1.6.1 | ||
52 | |||
diff --git a/recipes-bsp/x-load/x-load_git.bb b/recipes-bsp/x-load/x-load_git.bb index eb8f3eaf..ad46efc0 100644 --- a/recipes-bsp/x-load/x-load_git.bb +++ b/recipes-bsp/x-load/x-load_git.bb | |||
@@ -2,18 +2,12 @@ require x-load.inc | |||
2 | 2 | ||
3 | #FILESPATHPKG_prepend = "x-load-git:x-load-git/${MACHINE}" | 3 | #FILESPATHPKG_prepend = "x-load-git:x-load-git/${MACHINE}" |
4 | 4 | ||
5 | PV = "1.44+${PR}+gitr${SRCREV}" | 5 | PV = "1.5.0+${PR}+gitr${SRCREV}" |
6 | PR ="r21" | 6 | PR ="r22" |
7 | PE = "1" | 7 | PE = "1" |
8 | 8 | ||
9 | SRCREV_pn-${PN} = "24b8b7f41a83540433024854736518876257672c" | 9 | SRCREV_pn-${PN} = "b6bbfe7848de547b64edf1c363c86cec4921b517" |
10 | SRC_URI = "git://gitorious.org/x-loader/x-loader.git;branch=master;protocol=git \ | 10 | SRC_URI = "git://gitorious.org/x-loader/x-loader.git;branch=master;protocol=git \ |
11 | file://0001-OMAP4-clocks-Enable-only-required-clks.patch \ | ||
12 | file://0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch \ | ||
13 | file://0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch \ | ||
14 | file://0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch \ | ||
15 | file://0005-omap4-Make-1GHz-as-default-MPU-clock.patch \ | ||
16 | file://xmc.patch \ | ||
17 | " | 11 | " |
18 | 12 | ||
19 | S = "${WORKDIR}/git" | 13 | S = "${WORKDIR}/git" |