summaryrefslogtreecommitdiffstats
path: root/recipes-bsp/u-boot/u-boot
diff options
context:
space:
mode:
authorKoen Kooi <koen@dominion.thruhere.net>2012-02-13 14:46:34 +0100
committerDenys Dmytriyenko <denys@ti.com>2012-02-27 09:04:55 -0500
commitc5f5ead49160ebf82546ea913035ec6d8fc96654 (patch)
tree2387116ebbc1a51d2bceabc74200a55d930960d5 /recipes-bsp/u-boot/u-boot
parentb43e9fc0e1d3b52636f818c2303d43202e723114 (diff)
downloadmeta-ti-c5f5ead49160ebf82546ea913035ec6d8fc96654.tar.gz
u-boot 2011.09: add patch to support 'cold' AM335x silicon
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Diffstat (limited to 'recipes-bsp/u-boot/u-boot')
-rw-r--r--recipes-bsp/u-boot/u-boot/2011.09git/0001-ddr_defs-change-DDR-timings-for-15x15-EVM.patch30
1 files changed, 30 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot/u-boot/2011.09git/0001-ddr_defs-change-DDR-timings-for-15x15-EVM.patch b/recipes-bsp/u-boot/u-boot/2011.09git/0001-ddr_defs-change-DDR-timings-for-15x15-EVM.patch
new file mode 100644
index 00000000..4563a2ce
--- /dev/null
+++ b/recipes-bsp/u-boot/u-boot/2011.09git/0001-ddr_defs-change-DDR-timings-for-15x15-EVM.patch
@@ -0,0 +1,30 @@
1From 7a3b3b04b1aed6a649d99396f914ec042968f924 Mon Sep 17 00:00:00 2001
2From: Chase Maupin <Chase.Maupin@ti.com>
3Date: Thu, 9 Feb 2012 13:09:27 -0600
4Subject: [PATCH] ddr_defs: change DDR timings for 15x15 EVM
5
6* For cold silicon the DDR timings need to be relaxed in order for
7 the device to boot with DDR at 266MHz
8* Fix proposed by James Doublesin
9
10Signed-off-by: Chase Maupin <Chase.Maupin@ti.com>
11---
12 arch/arm/include/asm/arch-ti81xx/ddr_defs.h | 2 +-
13 1 files changed, 1 insertions(+), 1 deletions(-)
14
15diff --git a/arch/arm/include/asm/arch-ti81xx/ddr_defs.h b/arch/arm/include/asm/arch-ti81xx/ddr_defs.h
16index 6c4b422..0b7ffe7 100644
17--- a/arch/arm/include/asm/arch-ti81xx/ddr_defs.h
18+++ b/arch/arm/include/asm/arch-ti81xx/ddr_defs.h
19@@ -338,7 +338,7 @@
20 #define DDR2_RD_DQS 0x40
21 #define DDR2_PHY_FIFO_WE 0x56
22 #else
23-#define EMIF_READ_LATENCY 0x04
24+#define EMIF_READ_LATENCY 0x05
25 #define EMIF_TIM1 0x0666B3D6
26 #define EMIF_TIM2 0x143731DA
27 #define EMIF_TIM3 0x00000347
28--
291.7.0.4
30