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authorKoen Kooi <koen@dominion.thruhere.net>2012-06-07 17:40:42 +0200
committerDenys Dmytriyenko <denys@ti.com>2012-06-11 16:59:07 -0400
commit536748db584b77158c166c068ffe8960b0847ea5 (patch)
tree3e32da9191f7bdc20cf3c79249a2aa9b70fedd86
parente4fc1993e17cc120a2667eac8b747107a2750e71 (diff)
downloadmeta-ti-536748db584b77158c166c068ffe8960b0847ea5.tar.gz
linux-ti33x-psp 3.2: backport PM and USB fixes from PSP
The complete patchset will get rebased to the tip of the PSP tree soon, but the conflicts take a lot of time to resolve. Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Diffstat
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0001-ARM-OMAP-AM33XX-Add-missing-EMIF-register-offsets.patch61
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0002-ARM-OMAP-AM33XX-PM-Get-rid-of-hardcoded-resume-addre.patch99
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0003-ARM-OMAP-AM33XX-PM-Skip-DDR-PHY-reconfiguration-in-r.patch397
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0004-ARM-OMAP-AM33XX-PM-Save-and-restore-EMIF-registers.patch241
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0005-ARM-OMAP-AM33XX-PM-Wait-correctly-for-the-PLLs-to-re.patch37
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0006-ARM-OMAP-AM33XX-PM-Restore-the-PLLs-to-pre-suspend-s.patch139
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0007-ARM-OMAP-PM-AM33XX-Update-the-sleep-code-to-handle-D.patch150
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0008-usb-musb-update-babble-workaround-fix.patch168
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0009-usb-musb-ti81xx-print-the-usbss-revision-id-during-i.patch29
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0010-usb-musb-cppi41-enable-txfifo-empty-interrupt-logic.patch425
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0011-usb-musb-host-Flush-txfifo-only-if-TxPktRdy-bit-set.patch57
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0012-usb-musb-cppi41-use-dsb-to-make-sure-PDs-are-updated.patch43
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0013-usb-musb-cppi41-fix-zero-byte-OUT-issue.patch46
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0014-usb-musb-host-fix-for-urb-error-handling.patch66
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0015-usb-musb-cppi41-txdma-flushfifo-fixes-during-channel.patch50
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0016-usb-musb-cppi41-tx-dma-completion-fixes.patch41
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0017-usb-musb-host-Flush-RxFIFO-only-when-RxPktRdy-is-set.patch30
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0018-usb-musb-ti81xx-fix-role-switching-issue.patch65
-rw-r--r--recipes-kernel/linux/linux-ti33x-psp_3.2.bb20
19 files changed, 2163 insertions, 1 deletions
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0001-ARM-OMAP-AM33XX-Add-missing-EMIF-register-offsets.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0001-ARM-OMAP-AM33XX-Add-missing-EMIF-register-offsets.patch
new file mode 100644
index 00000000..3300bc9f
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0001-ARM-OMAP-AM33XX-Add-missing-EMIF-register-offsets.patch
@@ -0,0 +1,61 @@
1From 824f30e3a045347806deedb75f16e96b057f430b Mon Sep 17 00:00:00 2001
2From: Vaibhav Bedia <vaibhav.bedia@ti.com>
3Date: Tue, 22 May 2012 16:25:53 +0530
4Subject: [PATCH 01/18] ARM: OMAP: AM33XX: Add missing EMIF register offsets
5
6Add a couple of missing register offsets in the EMIF
7header file. While here also fix the indentation issue.
8
9Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
10---
11 arch/arm/plat-omap/include/plat/emif.h | 34 ++++++++++++++++----------------
12 1 files changed, 17 insertions(+), 17 deletions(-)
13
14diff --git a/arch/arm/plat-omap/include/plat/emif.h b/arch/arm/plat-omap/include/plat/emif.h
15index 314c126..445cbb1 100644
16--- a/arch/arm/plat-omap/include/plat/emif.h
17+++ b/arch/arm/plat-omap/include/plat/emif.h
18@@ -17,23 +17,23 @@
19 #define __EMIF_H
20
21 #define EMIF_MOD_ID_REV (0x0)
22-#define EMIF4_0_SDRAM_STATUS (0x04)
23-#define EMIF4_0_SDRAM_CONFIG (0x08)
24-#define EMIF4_0_SDRAM_CONFIG2 (0x0C)
25-#define EMIF4_0_SDRAM_REF_CTRL (0x10)
26-#define EMIF4_0_SDRAM_REF_CTRL_SHADOW (0x14)
27-#define EMIF4_0_SDRAM_TIM_1 (0x18)
28-#define EMIF4_0_SDRAM_TIM_1_SHADOW (0x1C)
29-#define EMIF4_0_SDRAM_TIM_2 (0x20)
30-#define EMIF4_0_SDRAM_TIM_2_SHADOW (0x24)
31-#define EMIF4_0_SDRAM_TIM_3 (0x28)
32-#define EMIF4_0_SDRAM_TIM_3_SHADOW (0x2C)
33-#define EMIF4_0_SDRAM_MGMT_CTRL (0x38)
34-#define EMIF4_0_SDRAM_MGMT_CTRL_SHD (0x3C)
35-#define EMIF4_0_DDR_PHY_CTRL_1 (0xE4)
36-#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW (0xE8)
37-#define EMIF4_0_DDR_PHY_CTRL_2 (0xEC)
38-#define EMIF4_0_IODFT_TLGC (0x60)
39+#define EMIF4_0_SDRAM_STATUS (0x04)
40+#define EMIF4_0_SDRAM_CONFIG (0x08)
41+#define EMIF4_0_SDRAM_CONFIG2 (0x0C)
42+#define EMIF4_0_SDRAM_REF_CTRL (0x10)
43+#define EMIF4_0_SDRAM_REF_CTRL_SHADOW (0x14)
44+#define EMIF4_0_SDRAM_TIM_1 (0x18)
45+#define EMIF4_0_SDRAM_TIM_1_SHADOW (0x1C)
46+#define EMIF4_0_SDRAM_TIM_2 (0x20)
47+#define EMIF4_0_SDRAM_TIM_2_SHADOW (0x24)
48+#define EMIF4_0_SDRAM_TIM_3 (0x28)
49+#define EMIF4_0_SDRAM_TIM_3_SHADOW (0x2C)
50+#define EMIF4_0_SDRAM_MGMT_CTRL (0x38)
51+#define EMIF4_0_SDRAM_MGMT_CTRL_SHADOW (0x3C)
52+#define EMIF4_0_IODFT_TLGC (0x60)
53+#define EMIF4_0_ZQ_CONFIG (0xC8)
54+#define EMIF4_0_DDR_PHY_CTRL_1 (0xE4)
55+#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW (0xE8)
56
57 #define SELF_REFRESH_ENABLE(m) (0x2 << 8 | (m << 4))
58 #define SELF_REFRESH_DISABLE (0x0 << 8)
59--
601.7.7.6
61
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0002-ARM-OMAP-AM33XX-PM-Get-rid-of-hardcoded-resume-addre.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0002-ARM-OMAP-AM33XX-PM-Get-rid-of-hardcoded-resume-addre.patch
new file mode 100644
index 00000000..04f71207
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0002-ARM-OMAP-AM33XX-PM-Get-rid-of-hardcoded-resume-addre.patch
@@ -0,0 +1,99 @@
1From 29ed395e3c56764a994ed4528e10c8835359a34b Mon Sep 17 00:00:00 2001
2From: Vaibhav Bedia <vaibhav.bedia@ti.com>
3Date: Tue, 22 May 2012 12:02:02 +0530
4Subject: [PATCH 02/18] ARM: OMAP: AM33XX: PM: Get rid of hardcoded resume
5 address
6
7Instead of using a harcoded resume address in the IPC registers
8add a dynamically computed offset to the start of OCMC address.
9
10Note: This approach currently assumes that the suspend-resume code
11is the first block of code that is copied to internal RAM. Due to
12the initcall level used by the SRAM mapping code this holds true.
13Ideally the sram mapping code should provide an API for doing this.
14This will be done at a later point of time when the generic SRAM
15allocator gets merged in mainline kernel.
16
17Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
18---
19 arch/arm/mach-omap2/pm.h | 1 +
20 arch/arm/mach-omap2/pm33xx.c | 8 +++++++-
21 arch/arm/mach-omap2/pm33xx.h | 2 +-
22 arch/arm/mach-omap2/sleep33xx.S | 16 +++-------------
23 4 files changed, 12 insertions(+), 15 deletions(-)
24
25diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
26index 68aeafc..f7a7500 100644
27--- a/arch/arm/mach-omap2/pm.h
28+++ b/arch/arm/mach-omap2/pm.h
29@@ -100,6 +100,7 @@ extern void omap3_save_scratchpad_contents(void);
30 /* am33xx_do_wfi function pointer and size, for copy to SRAM */
31 extern void am33xx_do_wfi(void);
32 extern unsigned int am33xx_do_wfi_sz;
33+extern unsigned int am33xx_resume_offset;
34 /* ... and its pointer from SRAM after copy */
35 extern void (*am33xx_do_wfi_sram)(void);
36 /* The resume location */
37diff --git a/arch/arm/mach-omap2/pm33xx.c b/arch/arm/mach-omap2/pm33xx.c
38index 70bcb42..c4c5187 100644
39--- a/arch/arm/mach-omap2/pm33xx.c
40+++ b/arch/arm/mach-omap2/pm33xx.c
41@@ -217,7 +217,13 @@ static int am33xx_pm_begin(suspend_state_t state)
42
43 disable_hlt();
44
45- am33xx_lp_ipc.resume_addr = DS_RESUME_ADDR;
46+ /*
47+ * Populate the resume address as part of IPC data
48+ * The offset to be added comes from sleep33xx.S
49+ * Add 4 bytes to ensure that resume happens from
50+ * the word *after* the word which holds the resume offset
51+ */
52+ am33xx_lp_ipc.resume_addr = (DS_RESUME_BASE + am33xx_resume_offset + 4);
53 am33xx_lp_ipc.sleep_mode = DS_MODE;
54 am33xx_lp_ipc.ipc_data1 = DS_IPC_DEFAULT;
55 am33xx_lp_ipc.ipc_data2 = DS_IPC_DEFAULT;
56diff --git a/arch/arm/mach-omap2/pm33xx.h b/arch/arm/mach-omap2/pm33xx.h
57index f72c28e..7b3504b 100644
58--- a/arch/arm/mach-omap2/pm33xx.h
59+++ b/arch/arm/mach-omap2/pm33xx.h
60@@ -47,7 +47,7 @@ struct am33xx_padconf {
61
62 #define M3_TXEV_EOI (AM33XX_CTRL_BASE + 0x1324)
63 #define A8_M3_IPC_REGS (AM33XX_CTRL_BASE + 0x1328)
64-#define DS_RESUME_ADDR 0x40300340
65+#define DS_RESUME_BASE 0x40300000
66 #define DS_IPC_DEFAULT 0xffffffff
67 #define M3_UMEM 0x44D00000
68
69diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
70index 69b49ea..9c57335 100644
71--- a/arch/arm/mach-omap2/sleep33xx.S
72+++ b/arch/arm/mach-omap2/sleep33xx.S
73@@ -234,20 +234,10 @@ wait_emif_enable:
74 mov r0, #7
75 ldmfd sp!, {r4 - r11, pc} @ restore regs and return
76
77- nop
78- nop
79- nop
80- nop
81- nop
82- nop
83- nop
84- nop
85- nop
86- nop
87- nop
88- nop
89- nop
90+ENTRY(am33xx_resume_offset)
91+ .word . - am33xx_do_wfi
92
93+ENTRY(am33xx_resume_from_deep_sleep)
94 /* Take the PLLs out of LP_BYPASS */
95 pll_lock mpu, phys_mpu_clk_mode, phys_mpu_idlest
96 pll_lock per, phys_per_clk_mode, phys_per_idlest
97--
981.7.7.6
99
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0003-ARM-OMAP-AM33XX-PM-Skip-DDR-PHY-reconfiguration-in-r.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0003-ARM-OMAP-AM33XX-PM-Skip-DDR-PHY-reconfiguration-in-r.patch
new file mode 100644
index 00000000..ad402a08
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0003-ARM-OMAP-AM33XX-PM-Skip-DDR-PHY-reconfiguration-in-r.patch
@@ -0,0 +1,397 @@
1From 49b0e8259aec1ffb11e0d2be13fc89fc84162fac Mon Sep 17 00:00:00 2001
2From: Vaibhav Bedia <vaibhav.bedia@ti.com>
3Date: Tue, 22 May 2012 12:19:21 +0530
4Subject: [PATCH 03/18] ARM: OMAP: AM33XX: PM: Skip DDR PHY reconfiguration in
5 resume
6
7DDR PHY registers were earlier being reconfigured in the resume
8path. This is not necessary since these registers lie in the
9WKUP domain and retain their content across various low power
10state. Skipping the reconfiguration will also enabling in getting
11a single kernel image to work for boards with different memory
12types.
13
14Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
15---
16 arch/arm/mach-omap2/pm33xx.h | 75 +------------
17 arch/arm/mach-omap2/sleep33xx.S | 245 +--------------------------------------
18 2 files changed, 7 insertions(+), 313 deletions(-)
19
20diff --git a/arch/arm/mach-omap2/pm33xx.h b/arch/arm/mach-omap2/pm33xx.h
21index 7b3504b..f52e54c 100644
22--- a/arch/arm/mach-omap2/pm33xx.h
23+++ b/arch/arm/mach-omap2/pm33xx.h
24@@ -60,59 +60,6 @@ struct am33xx_padconf {
25 #define M3_STATE_MSG_FOR_LP 2
26 #define M3_STATE_MSG_FOR_RESET 3
27
28-/* DDR offsets */
29-#define DDR_CMD0_IOCTRL (AM33XX_CTRL_BASE + 0x1404)
30-#define DDR_CMD1_IOCTRL (AM33XX_CTRL_BASE + 0x1408)
31-#define DDR_CMD2_IOCTRL (AM33XX_CTRL_BASE + 0x140C)
32-#define DDR_DATA0_IOCTRL (AM33XX_CTRL_BASE + 0x1440)
33-#define DDR_DATA1_IOCTRL (AM33XX_CTRL_BASE + 0x1444)
34-
35-#define DDR_IO_CTRL (AM33XX_CTRL_BASE + 0x0E04)
36-#define VTP0_CTRL_REG (AM33XX_CTRL_BASE + 0x0E0C)
37-#define DDR_CKE_CTRL (AM33XX_CTRL_BASE + 0x131C)
38-#define DDR_PHY_BASE_ADDR (AM33XX_CTRL_BASE + 0x2000)
39-
40-#define CMD0_CTRL_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x01C)
41-#define CMD0_CTRL_SLAVE_FORCE_0 (DDR_PHY_BASE_ADDR + 0x020)
42-#define CMD0_CTRL_SLAVE_DELAY_0 (DDR_PHY_BASE_ADDR + 0x024)
43-#define CMD0_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x028)
44-#define CMD0_INVERT_CLKOUT_0 (DDR_PHY_BASE_ADDR + 0x02C)
45-
46-#define CMD1_CTRL_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x050)
47-#define CMD1_CTRL_SLAVE_FORCE_0 (DDR_PHY_BASE_ADDR + 0x054)
48-#define CMD1_CTRL_SLAVE_DELAY_0 (DDR_PHY_BASE_ADDR + 0x058)
49-#define CMD1_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x05C)
50-#define CMD1_INVERT_CLKOUT_0 (DDR_PHY_BASE_ADDR + 0x060)
51-
52-#define CMD2_CTRL_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x084)
53-#define CMD2_CTRL_SLAVE_FORCE_0 (DDR_PHY_BASE_ADDR + 0x088)
54-#define CMD2_CTRL_SLAVE_DELAY_0 (DDR_PHY_BASE_ADDR + 0x08C)
55-#define CMD2_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x090)
56-#define CMD2_INVERT_CLKOUT_0 (DDR_PHY_BASE_ADDR + 0x094)
57-
58-#define DATA0_RD_DQS_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0C8)
59-#define DATA0_RD_DQS_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x0CC)
60-
61-#define DATA0_WR_DQS_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0DC)
62-#define DATA0_WR_DQS_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x0E0)
63-
64-#define DATA0_WRLVL_INIT_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0F0)
65-#define DATA0_WRLVL_INIT_RATIO_1 (DDR_PHY_BASE_ADDR + 0x0F4)
66-
67-#define DATA0_GATELVL_INIT_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0FC)
68-#define DATA0_GATELVL_INIT_RATIO_1 (DDR_PHY_BASE_ADDR + 0x100)
69-
70-#define DATA0_FIFO_WE_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x108)
71-#define DATA0_FIFO_WE_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x10C)
72-
73-#define DATA0_WR_DATA_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x120)
74-#define DATA0_WR_DATA_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x124)
75-
76-#define DATA0_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x138)
77-
78-#define DATA0_RANK0_DELAYS_0 (DDR_PHY_BASE_ADDR + 0x134)
79-#define DATA1_RANK0_DELAYS_0 (DDR_PHY_BASE_ADDR + 0x1D8)
80-
81 /* Temp placeholder for the values we want in the registers */
82 #define EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
83 #define EMIF_TIM1 0x0666B3C9
84@@ -124,28 +71,12 @@ struct am33xx_padconf {
85 #define EMIF_SDRAM 0x00004650
86 #define EMIF_PHYCFG 0x2
87
88-#define DDR2_DLL_LOCK_DIFF 0x0
89-#define DDR2_RD_DQS 0x12
90-#define DDR2_PHY_FIFO_WE 0x80
91-
92-#define DDR_PHY_RESET (0x1 << 10)
93-#define DDR_PHY_READY (0x1 << 2)
94-#define DDR2_RATIO 0x80
95-#define CMD_FORCE 0x00
96-#define CMD_DELAY 0x00
97-
98-#define DDR2_INVERT_CLKOUT 0x00
99-#define DDR2_WR_DQS 0x00
100-#define DDR2_PHY_WRLVL 0x00
101-#define DDR2_PHY_GATELVL 0x00
102-#define DDR2_PHY_WR_DATA 0x40
103-#define PHY_RANK0_DELAY 0x01
104-#define PHY_DLL_LOCK_DIFF 0x0
105-#define DDR_IOCTRL_VALUE 0x18B
106-
107 #define VTP_CTRL_READY (0x1 << 5)
108 #define VTP_CTRL_ENABLE (0x1 << 6)
109 #define VTP_CTRL_LOCK_EN (0x1 << 4)
110 #define VTP_CTRL_START_EN (0x1)
111
112+#define DDR_IO_CTRL (AM33XX_CTRL_BASE + 0x0E04)
113+#define VTP0_CTRL_REG (AM33XX_CTRL_BASE + 0x0E0C)
114+
115 #endif
116diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
117index 9c57335..4c601b11 100644
118--- a/arch/arm/mach-omap2/sleep33xx.S
119+++ b/arch/arm/mach-omap2/sleep33xx.S
120@@ -273,21 +273,9 @@ ENTRY(am33xx_resume_from_deep_sleep)
121 bic r1, r1, #28
122 str r1, [r0]
123
124-/*
125- * Instead of harcoding the EMIF and DDR PHY related settings
126- * in this file, the sane thing to do would have been to backup
127- * the register contents during suspend and restore it back in
128- * the resume path. However, due to the Si errata related to
129- * DDR PHY registers, these registers are read-only. So, we'll
130- * need to hardcode atleast the DDR PHY configuration over here.
131- * We _could_ back up the EMIF registers but in order to be
132- * consistent with the DDR setup procedure we skip this for now.
133- * The person updating the DDR PHY config values is expected
134- * to update the EMIF config values also.
135- */
136
137 config_vtp:
138- ldr r0, vtp0_addr
139+ ldr r0, phys_ddr_vtp_ctrl
140 ldr r1, [r0]
141 mov r2, #0x0 @ clear the register
142 str r2, [r0]
143@@ -312,179 +300,6 @@ poll_vtp_ready:
144 tst r1, #(1 << 5)
145 beq poll_vtp_ready
146
147-cmd_macro_config:
148- ldr r0, ddr_phy_base
149- ldr r1, [r0]
150- ldr r2, ddr2_ratio_val
151- mov r3, r2
152- @ TODO: Need to use proper variable here
153- mov r4, #0
154- str r3, [r0, #28] @cmd0
155- str r4, [r0, #32]
156- str r4, [r0, #36]
157- str r4, [r0, #40]
158- str r4, [r0, #44]
159- str r3, [r0, #80] @cmd1
160- str r4, [r0, #84]
161- str r4, [r0, #88]
162- str r4, [r0, #92]
163- str r4, [r0, #96]
164- str r3, [r0, #132] @cmd2
165- str r4, [r0, #136]
166- str r4, [r0, #140]
167- str r4, [r0, #144]
168- str r4, [r0, #148]
169-
170- mov r3, #0x0
171- bl data_macro_config
172- mov r3, #0xa4
173- bl data_macro_config
174- b setup_rank_delays
175-
176-data_macro_config:
177- ldr r0, ddr_phy_base
178- add r0, r0, r3
179-rd_dqs:
180- ldr r1, data0_rd_dqs_slave_ratio0_val
181- mov r2, r1
182- /* shift by 30, 20, 10 and orr */
183- mov r5, r2, lsl #10
184- mov r6, r2, lsl #20
185- mov r7, r2, lsl #30
186- orr r2, r2, r5
187- orr r2, r2, r6
188- orr r2, r2, r7
189- /* Done with crazy bit ops. store it now */
190- str r2, [r0, #200]
191- ldr r1, data0_rd_dqs_slave_ratio1_val
192- mov r2, r1
193- mov r5, r2, lsr #2
194- mov r2, r5
195- str r2, [r0, #204]
196-wr_dqs:
197- ldr r1, data0_wr_dqs_slave_ratio0_val
198- mov r2, r1
199- /* shift by 30, 20, 10 and orr */
200- mov r5, r2, lsl #10
201- mov r6, r2, lsl #20
202- mov r7, r2, lsl #30
203- orr r2, r2, r5
204- orr r2, r2, r6
205- orr r2, r2, r7
206- /* Done with crazy bit ops. store it now */
207- str r2, [r0, #220]
208- ldr r1, data0_wr_dqs_slave_ratio1_val
209- mov r2, r1
210- mov r5, r2, lsr #2
211- mov r2, r5
212- str r2, [r0, #224]
213-wr_lvl:
214- ldr r1, data0_wr_lvl_init_ratio0_val
215- mov r2, r1
216- /* shift by 30, 20, 10 and orr */
217- mov r5, r2, lsl #10
218- mov r6, r2, lsl #20
219- mov r7, r2, lsl #30
220- orr r2, r2, r5
221- orr r2, r2, r6
222- orr r2, r2, r7
223- /* Done with crazy bit ops. store it now */
224- str r2, [r0, #240]
225- ldr r1, data0_wr_lvl_init_ratio1_val
226- mov r2, r1
227- mov r5, r2, lsr #2
228- mov r2, r5
229- str r2, [r0, #244]
230-gate_lvl:
231- ldr r1, data0_gate_lvl_init_ratio0_val
232- mov r2, r1
233- /* shift by 30, 20, 10 and orr */
234- mov r5, r2, lsl #10
235- mov r6, r2, lsl #20
236- mov r7, r2, lsl #30
237- orr r2, r2, r5
238- orr r2, r2, r6
239- orr r2, r2, r7
240- /* Done with crazy bit ops. store it now */
241- str r2, [r0, #248]
242- ldr r1, data0_gate_lvl_init_ratio1_val
243- mov r2, r1
244- mov r5, r2, lsr #2
245- mov r2, r5
246- str r2, [r0, #256]
247-we_slv:
248- ldr r1, data0_wr_lvl_slave_ratio0_val
249- mov r2, r1
250- /* shift by 30, 20, 10 and orr */
251- mov r5, r2, lsl #10
252- mov r6, r2, lsl #20
253- mov r7, r2, lsl #30
254- orr r2, r2, r5
255- orr r2, r2, r6
256- orr r2, r2, r7
257- /* Done with crazy bit ops. store it now */
258- str r2, [r0, #264]
259- ldr r1, data0_wr_lvl_slave_ratio1_val
260- mov r2, r1
261- mov r5, r2, lsr #2
262- mov r2, r5
263- str r2, [r0, #268]
264-wr_data:
265- ldr r1, data0_wr_data_slave_ratio0_val
266- mov r2, r1
267- /* shift by 30, 20, 10 and orr */
268- mov r5, r2, lsl #10
269- mov r6, r2, lsl #20
270- mov r7, r2, lsl #30
271- orr r2, r2, r5
272- orr r2, r2, r6
273- orr r2, r2, r7
274- /* Done with crazy bit ops. store it now */
275- str r2, [r0, #288]
276- ldr r1, data0_wr_data_slave_ratio1_val
277- mov r2, r1
278- mov r5, r2, lsr #2
279- mov r2, r5
280- str r2, [r0, #292]
281-dll_lock:
282- ldr r1, data0_dll_lock_diff_val
283- mov r2, r1
284- str r2, [r0, #312]
285-
286-setup_rank_delays:
287- ldr r1, data0_rank0_delay0_val
288- mov r2, r1
289- str r2, [r0, #308]
290- ldr r1, data1_rank0_delay1_val
291- mov r2, r1
292- str r2, [r0, #472]
293-
294-setup_io_ctrl:
295- ldr r0, control_base
296- ldr r1, ddr_ioctrl_val
297- mov r2, r1
298- ldr r4, ddr_cmd_offset
299- mov r3, r4
300- str r2, [r0, r3] @cmd0 0x1404
301- add r3, r3, #4
302- str r2, [r0, r3] @cmd1 0x1408
303- add r3, r3, #4
304- str r2, [r0, r3] @cmd2 0x140c
305- ldr r4, ddr_data_offset
306- mov r3, r4
307- str r2, [r0, r3] @data0 0x1440
308- add r3, r3, #4
309- str r2, [r0, r3] @data1 0x1444
310-
311-misc_config:
312- ldr r1, ddr_io_ctrl_addr
313- ldr r2, [r1]
314- and r2, #0xefffffff
315- str r2, [r1]
316- ldr r1, ddr_cke_addr
317- ldr r2, [r1]
318- orr r2, #0x00000001
319- str r2, [r1]
320
321 config_emif_timings:
322 mov r3, #1275068416 @ 0x4c000000
323@@ -628,61 +443,6 @@ module_disabled_val:
324 .word 0x30000
325
326 /* DDR related stuff */
327-vtp0_addr:
328- .word VTP0_CTRL_REG
329-vtp_enable:
330- .word VTP_CTRL_ENABLE
331-vtp_start_en:
332- .word VTP_CTRL_START_EN
333-vtp_ready:
334- .word VTP_CTRL_READY
335-
336-ddr_phy_base:
337- .word DDR_PHY_BASE_ADDR
338-ddr2_ratio_val:
339- .word DDR2_RATIO
340-data0_rd_dqs_slave_ratio0_val:
341- .word DDR2_RD_DQS
342-data0_rd_dqs_slave_ratio1_val:
343- .word DDR2_RD_DQS
344-data0_wr_dqs_slave_ratio0_val:
345- .word DDR2_WR_DQS
346-data0_wr_dqs_slave_ratio1_val:
347- .word DDR2_WR_DQS
348-data0_wr_lvl_init_ratio0_val:
349- .word DDR2_PHY_WRLVL
350-data0_wr_lvl_init_ratio1_val:
351- .word DDR2_PHY_WRLVL
352-data0_gate_lvl_init_ratio0_val:
353- .word DDR2_PHY_GATELVL
354-data0_gate_lvl_init_ratio1_val:
355- .word DDR2_PHY_GATELVL
356-data0_wr_lvl_slave_ratio0_val:
357- .word DDR2_PHY_FIFO_WE
358-data0_wr_lvl_slave_ratio1_val:
359- .word DDR2_PHY_FIFO_WE
360-data0_wr_data_slave_ratio0_val:
361- .word DDR2_PHY_WR_DATA
362-data0_wr_data_slave_ratio1_val:
363- .word DDR2_PHY_WR_DATA
364-data0_dll_lock_diff_val:
365- .word PHY_DLL_LOCK_DIFF
366-
367-data0_rank0_delay0_val:
368- .word PHY_RANK0_DELAY
369-data1_rank0_delay1_val:
370- .word PHY_RANK0_DELAY
371-
372-control_base:
373- .word AM33XX_CTRL_BASE
374-ddr_io_ctrl_addr:
375- .word DDR_IO_CTRL
376-ddr_ioctrl_val:
377- .word 0x18B
378-ddr_cmd_offset:
379- .word 0x1404
380-ddr_data_offset:
381- .word 0x1440
382 virt_ddr_io_ctrl:
383 .word AM33XX_CTRL_REGADDR(0x0E04)
384 phys_ddr_io_ctrl:
385@@ -691,6 +451,9 @@ virt_ddr_vtp_ctrl:
386 .word AM33XX_CTRL_REGADDR(0x0E0C)
387 phys_ddr_vtp_ctrl:
388 .word VTP0_CTRL_REG
389+vtp_enable:
390+ .word VTP_CTRL_ENABLE
391+
392 virt_ddr_io_pull1:
393 .word AM33XX_CTRL_REGADDR(0x1440)
394 phys_ddr_io_pull1:
395--
3961.7.7.6
397
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0004-ARM-OMAP-AM33XX-PM-Save-and-restore-EMIF-registers.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0004-ARM-OMAP-AM33XX-PM-Save-and-restore-EMIF-registers.patch
new file mode 100644
index 00000000..a1c66ad7
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0004-ARM-OMAP-AM33XX-PM-Save-and-restore-EMIF-registers.patch
@@ -0,0 +1,241 @@
1From 334c051e4d0b3214136dbee1b0a52e2d29747c0a Mon Sep 17 00:00:00 2001
2From: Vaibhav Bedia <vaibhav.bedia@ti.com>
3Date: Tue, 22 May 2012 12:24:55 +0530
4Subject: [PATCH 04/18] ARM: OMAP: AM33XX: PM: Save and restore EMIF registers
5
6The EMIF configuration parameters were earlier harcoded
7under the assumption that the person updating the DDR PHY
8configuration values will update the EMIF parameters also.
9
10Now that the DDR PHY reconfiguration has been dropped, this
11restriction can also go away by adopting a save and restore
12mechanism of these registers.
13
14At the same time switch to macros for EMIF register offsets
15to improve readability.
16
17Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
18---
19 arch/arm/mach-omap2/pm33xx.h | 11 ---
20 arch/arm/mach-omap2/sleep33xx.S | 141 +++++++++++++++++++++------------------
21 2 files changed, 75 insertions(+), 77 deletions(-)
22
23diff --git a/arch/arm/mach-omap2/pm33xx.h b/arch/arm/mach-omap2/pm33xx.h
24index f52e54c..a40f4d4 100644
25--- a/arch/arm/mach-omap2/pm33xx.h
26+++ b/arch/arm/mach-omap2/pm33xx.h
27@@ -60,17 +60,6 @@ struct am33xx_padconf {
28 #define M3_STATE_MSG_FOR_LP 2
29 #define M3_STATE_MSG_FOR_RESET 3
30
31-/* Temp placeholder for the values we want in the registers */
32-#define EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
33-#define EMIF_TIM1 0x0666B3C9
34-#define EMIF_TIM2 0x243631CA
35-#define EMIF_TIM3 0x0000033F
36-#define EMIF_SDCFG 0x41805332
37-#define EMIF_SDREF 0x0000081a
38-#define EMIF_SDMGT 0x80000000
39-#define EMIF_SDRAM 0x00004650
40-#define EMIF_PHYCFG 0x2
41-
42 #define VTP_CTRL_READY (0x1 << 5)
43 #define VTP_CTRL_ENABLE (0x1 << 6)
44 #define VTP_CTRL_LOCK_EN (0x1 << 4)
45diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
46index 4c601b11..b7a1612 100644
47--- a/arch/arm/mach-omap2/sleep33xx.S
48+++ b/arch/arm/mach-omap2/sleep33xx.S
49@@ -71,6 +71,26 @@ wait_pll_lock_\name:
50
51 str r0, emif_addr_virt
52
53+ /* Save EMIF configuration */
54+ ldr r1, [r0, #EMIF4_0_SDRAM_CONFIG]
55+ str r1, emif_sdcfg_val
56+ ldr r1, [r0, #EMIF4_0_SDRAM_REF_CTRL]
57+ str r1, emif_ref_ctrl_val
58+ ldr r1, [r0, #EMIF4_0_SDRAM_TIM_1]
59+ str r1, emif_timing1_val
60+ ldr r1, [r0, #EMIF4_0_SDRAM_TIM_2]
61+ str r1, emif_timing2_val
62+ ldr r1, [r0, #EMIF4_0_SDRAM_TIM_3]
63+ str r1, emif_timing3_val
64+ ldr r1, [r0, #EMIF4_0_SDRAM_MGMT_CTRL]
65+ str r1, emif_pmcr_val
66+ ldr r1, [r0, #EMIF4_0_SDRAM_MGMT_CTRL_SHADOW]
67+ str r1, emif_pmcr_shdw_val
68+ ldr r1, [r0, #EMIF4_0_ZQ_CONFIG]
69+ str r1, emif_zqcfg_val
70+ ldr r1, [r0, #EMIF4_0_DDR_PHY_CTRL_1]
71+ str r1, emif_rd_lat_val
72+
73 /* Ensure that all the writes to DDR leave the A8 */
74 dsb
75 dmb
76@@ -302,58 +322,52 @@ poll_vtp_ready:
77
78
79 config_emif_timings:
80- mov r3, #1275068416 @ 0x4c000000
81-disable_sr:
82- mov r4, #0
83- str r4, [r3, #56] @ 0x38
84+ ldr r3, emif_phys_addr
85 ldr r4, emif_rd_lat_val
86- mov r2, r4
87 rd_lat:
88- str r2, [r3, #228] @ 0xe4
89- str r2, [r3, #232] @ 0xe8
90- str r2, [r3, #236] @ 0xec
91+ str r4, [r3, #EMIF4_0_DDR_PHY_CTRL_1]
92+ str r4, [r3, #EMIF4_0_DDR_PHY_CTRL_1_SHADOW]
93 timing1:
94 ldr r4, emif_timing1_val
95- mov r2, r4
96- str r2, [r3, #24]
97- str r2, [r3, #28]
98+ str r4, [r3, #EMIF4_0_SDRAM_TIM_1]
99+ str r4, [r3, #EMIF4_0_SDRAM_TIM_1_SHADOW]
100 timing2:
101 ldr r4, emif_timing2_val
102- mov r2, r4
103- str r2, [r3, #32]
104- str r2, [r3, #36] @ 0x24
105+ str r4, [r3, #EMIF4_0_SDRAM_TIM_2]
106+ str r4, [r3, #EMIF4_0_SDRAM_TIM_2_SHADOW]
107 timing3:
108 ldr r4, emif_timing3_val
109- mov r2, r4
110- str r2, [r3, #40] @ 0x28
111- str r2, [r3, #44] @ 0x2c
112-sdcfg1:
113- ldr r4, emif_sdcfg_val
114- mov r2, r4
115- str r2, [r3, #8]
116- str r2, [r3, #12]
117-ref_ctrl_const:
118- ldr r4, emif_ref_ctrl_const_val
119- mov r2, r4
120- str r2, [r3, #16]
121- str r2, [r3, #20]
122-
123- /* GEL had a loop with init value of 5000 */
124- mov r0, #0x1000
125-wait_loop1:
126- subs r0, r0, #1
127- bne wait_loop1
128-
129-ref_ctrl_actual:
130+ str r4, [r3, #EMIF4_0_SDRAM_TIM_3]
131+ str r4, [r3, #EMIF4_0_SDRAM_TIM_3_SHADOW]
132+sdram_ref_ctrl:
133 ldr r4, emif_ref_ctrl_val
134- mov r2, r4
135- str r2, [r3, #16]
136- str r2, [r3, #20]
137-sdcfg2:
138+ str r4, [r3, #EMIF4_0_SDRAM_REF_CTRL]
139+ str r4, [r3, #EMIF4_0_SDRAM_REF_CTRL_SHADOW]
140+pmcr:
141+ ldr r4, emif_pmcr_val
142+ str r4, [r3, #EMIF4_0_SDRAM_MGMT_CTRL]
143+pmcr_shdw:
144+ ldr r4, emif_pmcr_shdw_val
145+ str r4, [r3, #EMIF4_0_SDRAM_MGMT_CTRL_SHADOW]
146+
147+ /*
148+ * Output impedence calib needed only for DDR3
149+ * but since the initial state of this will be
150+ * disabled for DDR2 no harm in restoring the
151+ * old configuration
152+ */
153+zqcfg:
154+ ldr r4, emif_zqcfg_val
155+ str r4, [r3, #EMIF4_0_ZQ_CONFIG]
156+
157+ /*
158+ * A write to SDRAM CONFIG register triggers
159+ * an init sequence and hence it must be done
160+ * at the end
161+ */
162+sdcfg:
163 ldr r4, emif_sdcfg_val
164- mov r2, r4
165- str r2, [r3, #8]
166- str r2, [r3, #12]
167+ str r4, [r3, #EMIF4_0_SDRAM_CONFIG]
168
169 /* Back from la-la-land. Kill some time for sanity to settle in */
170 mov r0, #0x1000
171@@ -377,10 +391,8 @@ emif_addr_func:
172 emif_phys_addr:
173 .word AM33XX_EMIF0_BASE
174
175-emif_pm_ctrl:
176- .word EMIF4_0_SDRAM_MGMT_CTRL
177 ddr_start:
178- .word PAGE_OFFSET
179+ .word PAGE_OFFSET
180
181 virt_mpu_idlest:
182 .word AM33XX_CM_IDLEST_DPLL_MPU
183@@ -467,37 +479,34 @@ virt_ddr_io_pull3:
184 phys_ddr_io_pull3:
185 .word AM33XX_CTRL_BASE + (0x1448)
186
187-ddr_cke_addr:
188- .word DDR_CKE_CTRL
189-emif_rd_lat_val:
190- .word EMIF_READ_LATENCY
191-emif_timing1_val:
192- .word EMIF_TIM1
193-emif_timing2_val:
194- .word EMIF_TIM2
195-emif_timing3_val:
196- .word EMIF_TIM3
197-emif_sdcfg_val:
198- .word EMIF_SDCFG
199-emif_ref_ctrl_const_val:
200- .word 0x4650
201-emif_ref_ctrl_val:
202- .word EMIF_SDREF
203-
204 susp_io_pull:
205 .word 0x3FF00003
206 resume_io_pull1:
207 .word 0x18B
208 resume_io_pull2:
209 .word 0x18B
210-dyn_pd_val:
211- .word 0x100000
212-susp_sdram_config:
213- .word 0x40805332
214 susp_vtp_ctrl_val:
215 .word 0x10117
216 emif_addr_virt:
217 .word 0xDEADBEEF
218+emif_rd_lat_val:
219+ .word 0xDEADBEEF
220+emif_timing1_val:
221+ .word 0xDEADBEEF
222+emif_timing2_val:
223+ .word 0xDEADBEEF
224+emif_timing3_val:
225+ .word 0xDEADBEEF
226+emif_sdcfg_val:
227+ .word 0xDEADBEEF
228+emif_ref_ctrl_val:
229+ .word 0xDEADBEEF
230+emif_zqcfg_val:
231+ .word 0xDEADBEEF
232+emif_pmcr_val:
233+ .word 0xDEADBEEF
234+emif_pmcr_shdw_val:
235+ .word 0xDEADBEEF
236
237
238 ENTRY(am33xx_do_wfi_sz)
239--
2401.7.7.6
241
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0005-ARM-OMAP-AM33XX-PM-Wait-correctly-for-the-PLLs-to-re.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0005-ARM-OMAP-AM33XX-PM-Wait-correctly-for-the-PLLs-to-re.patch
new file mode 100644
index 00000000..a8db01e3
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0005-ARM-OMAP-AM33XX-PM-Wait-correctly-for-the-PLLs-to-re.patch
@@ -0,0 +1,37 @@
1From a7cfe5e7b86ebba4aa184b2612c4ecb70a01aa02 Mon Sep 17 00:00:00 2001
2From: "Satyanarayana, Sandhya" <sandhya.satyanarayana@ti.com>
3Date: Tue, 22 May 2012 12:33:20 +0530
4Subject: [PATCH 05/18] ARM: OMAP: AM33XX: PM: Wait correctly for the PLLs to
5 relock in the sleep code
6
7The PLL relock code was incorrectly exiting the loop
8before the PLLs relock. Since the PLLs relock within
9a couple of A8 assembly instruction execution this went
10unnoticed till now. The issue was noticed when validating
11the abort path of the suspend process wherein the
12incorrect check for PLL relock resulted in a lockup.
13
14Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
15Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
16---
17 arch/arm/mach-omap2/sleep33xx.S | 4 ++--
18 1 files changed, 2 insertions(+), 2 deletions(-)
19
20diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
21index b7a1612..79a9e39 100644
22--- a/arch/arm/mach-omap2/sleep33xx.S
23+++ b/arch/arm/mach-omap2/sleep33xx.S
24@@ -61,8 +61,8 @@ pll_lock_\name:
25 ldr r0, \idlest_addr
26 wait_pll_lock_\name:
27 ldr r1, [r0]
28- tst r1, #0x1
29- bne wait_pll_lock_\name
30+ ands r1, #0x1
31+ beq wait_pll_lock_\name
32 .endm
33
34 /* EMIF config for low power mode */
35--
361.7.7.6
37
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0006-ARM-OMAP-AM33XX-PM-Restore-the-PLLs-to-pre-suspend-s.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0006-ARM-OMAP-AM33XX-PM-Restore-the-PLLs-to-pre-suspend-s.patch
new file mode 100644
index 00000000..c0d0ef14
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0006-ARM-OMAP-AM33XX-PM-Restore-the-PLLs-to-pre-suspend-s.patch
@@ -0,0 +1,139 @@
1From d3ec36ec2c36ecb234c5a575b713205473e6cab8 Mon Sep 17 00:00:00 2001
2From: Vaibhav Bedia <vaibhav.bedia@ti.com>
3Date: Tue, 22 May 2012 12:43:01 +0530
4Subject: [PATCH 06/18] ARM: OMAP: AM33XX: PM: Restore the PLLs to pre-suspend
5 state
6
7In some scenarios all the PLLs (especially Display) might not be
8in a locked state when the suspend process starts. Trying to relock
9a PLL in MN-bypass mode without a proper set of M and N values results
10into the PLLs never locking and the resume process hanging. Fix this
11by restoring the PLLs to the mode that they were in before the suspend
12process started.
13
14Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
15---
16 arch/arm/mach-omap2/sleep33xx.S | 57 +++++++++++++++++++++++++-------------
17 1 files changed, 37 insertions(+), 20 deletions(-)
18
19diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
20index 79a9e39..4db3a94 100644
21--- a/arch/arm/mach-omap2/sleep33xx.S
22+++ b/arch/arm/mach-omap2/sleep33xx.S
23@@ -37,10 +37,11 @@
24 ENTRY(am33xx_do_wfi)
25 stmfd sp!, {r4 - r11, lr} @ save registers on stack
26
27- .macro pll_bypass, name, clk_mode_addr, idlest_addr
28+ .macro pll_bypass, name, clk_mode_addr, idlest_addr, pll_mode
29 pll_bypass_\name:
30 ldr r0, \clk_mode_addr
31 ldr r1, [r0]
32+ str r1, clk_mode_\pll_mode
33 bic r1, r1, #(7 << 0)
34 orr r1, r1, #0x5
35 str r1, [r0]
36@@ -51,18 +52,21 @@ wait_pll_bypass_\name:
37 bne wait_pll_bypass_\name
38 .endm
39
40- .macro pll_lock, name, clk_mode_addr, idlest_addr
41+ .macro pll_lock, name, clk_mode_addr, idlest_addr, pll_mode
42 pll_lock_\name:
43 ldr r0, \clk_mode_addr
44- ldr r1, [r0]
45- bic r1, r1, #(7 << 0)
46- orr r1, r1, #0x7
47+ ldr r1, clk_mode_\pll_mode
48 str r1, [r0]
49+ and r1, r1, #0x7
50+ cmp r1, #0x7
51+ bne pll_mode_restored_\name
52 ldr r0, \idlest_addr
53 wait_pll_lock_\name:
54 ldr r1, [r0]
55 ands r1, #0x1
56 beq wait_pll_lock_\name
57+pll_mode_restored_\name:
58+ nop
59 .endm
60
61 /* EMIF config for low power mode */
62@@ -154,11 +158,11 @@ wait_emif_disable:
63 str r1, [r0]
64
65 /* Put the PLLs in bypass mode */
66- pll_bypass core, virt_core_clk_mode, virt_core_idlest
67- pll_bypass ddr, virt_ddr_clk_mode, virt_ddr_idlest
68- pll_bypass disp, virt_disp_clk_mode, virt_disp_idlest
69- pll_bypass per, virt_per_clk_mode, virt_per_idlest
70- pll_bypass mpu, virt_mpu_clk_mode, virt_mpu_idlest
71+ pll_bypass core, virt_core_clk_mode, virt_core_idlest, core_val
72+ pll_bypass ddr, virt_ddr_clk_mode, virt_ddr_idlest, ddr_val
73+ pll_bypass disp, virt_disp_clk_mode, virt_disp_idlest, disp_val
74+ pll_bypass per, virt_per_clk_mode, virt_per_idlest, per_val
75+ pll_bypass mpu, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
76
77 dsb
78 dmb
79@@ -176,15 +180,17 @@ wait_emif_disable:
80 nop
81 nop
82 nop
83+ nop
84+ nop
85
86 /* We come here in case of an abort */
87
88 /* Relock the PLLs */
89- pll_lock mpu_abt, virt_mpu_clk_mode, virt_mpu_idlest
90- pll_lock per_abt, virt_per_clk_mode, virt_per_idlest
91- pll_lock disp_abt, virt_disp_clk_mode, virt_disp_idlest
92- pll_lock ddr_abt, virt_ddr_clk_mode, virt_ddr_idlest
93- pll_lock core_abt, virt_core_clk_mode, virt_core_idlest
94+ pll_lock mpu_abt, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
95+ pll_lock per_abt, virt_per_clk_mode, virt_per_idlest, per_val
96+ pll_lock disp_abt, virt_disp_clk_mode, virt_disp_idlest, disp_val
97+ pll_lock ddr_abt, virt_ddr_clk_mode, virt_ddr_idlest, ddr_val
98+ pll_lock core_abt, virt_core_clk_mode, virt_core_idlest, core_val
99
100 /* Disable SRAM LDO ret mode */
101 ldr r0, virt_sram_ldo_addr
102@@ -259,11 +265,11 @@ ENTRY(am33xx_resume_offset)
103
104 ENTRY(am33xx_resume_from_deep_sleep)
105 /* Take the PLLs out of LP_BYPASS */
106- pll_lock mpu, phys_mpu_clk_mode, phys_mpu_idlest
107- pll_lock per, phys_per_clk_mode, phys_per_idlest
108- pll_lock disp, phys_disp_clk_mode, phys_disp_idlest
109- pll_lock ddr, phys_ddr_clk_mode, phys_ddr_idlest
110- pll_lock core, phys_core_clk_mode, phys_core_idlest
111+ pll_lock mpu, phys_mpu_clk_mode, phys_mpu_idlest, mpu_val
112+ pll_lock per, phys_per_clk_mode, phys_per_idlest, per_val
113+ pll_lock disp, phys_disp_clk_mode, phys_disp_idlest, disp_val
114+ pll_lock ddr, phys_ddr_clk_mode, phys_ddr_idlest, ddr_val
115+ pll_lock core, phys_core_clk_mode, phys_core_idlest, core_val
116
117 /* Disable SRAM LDO ret mode */
118 ldr r0, phys_sram_ldo_addr
119@@ -508,6 +514,17 @@ emif_pmcr_val:
120 emif_pmcr_shdw_val:
121 .word 0xDEADBEEF
122
123+/* PLL CLKMODE before suspend */
124+clk_mode_mpu_val:
125+ .word 0xDEADBEEF
126+clk_mode_per_val:
127+ .word 0xDEADBEEF
128+clk_mode_disp_val:
129+ .word 0xDEADBEEF
130+clk_mode_ddr_val:
131+ .word 0xDEADBEEF
132+clk_mode_core_val:
133+ .word 0xDEADBEEF
134
135 ENTRY(am33xx_do_wfi_sz)
136 .word . - am33xx_do_wfi
137--
1381.7.7.6
139
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0007-ARM-OMAP-PM-AM33XX-Update-the-sleep-code-to-handle-D.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0007-ARM-OMAP-PM-AM33XX-Update-the-sleep-code-to-handle-D.patch
new file mode 100644
index 00000000..37f1874b
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0007-ARM-OMAP-PM-AM33XX-Update-the-sleep-code-to-handle-D.patch
@@ -0,0 +1,150 @@
1From db18037175f6b61dfe2be5e657f1b90fe29fd946 Mon Sep 17 00:00:00 2001
2From: "Satyanarayana, Sandhya" <sandhya.satyanarayana@ti.com>
3Date: Tue, 22 May 2012 13:40:34 +0530
4Subject: [PATCH 07/18] ARM: OMAP: PM: AM33XX: Update the sleep code to handle
5 DDR3
6
7DDR3 devices have a reset signal which is active low. When the
8system enters low power state this signal needs to be kept high
9to avoid a reset and hence a loss of memory content. DDR_IO_CTRL
10register in the control module gives s/w control over the reset
11line. Since the reset line is left open for DDR2 devices
12(some implementation might connect this but finally it becomes
13a NOP), there is no harm in setting the reset pin to high even
14for DDR2. This also enables us to have the same sequence for
15DDR2 and DDR3 devices.
16
17Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
18Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
19---
20 arch/arm/mach-omap2/sleep33xx.S | 59 +++++++++++++++-----------------------
21 1 files changed, 23 insertions(+), 36 deletions(-)
22
23diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
24index 4db3a94..6e802da 100644
25--- a/arch/arm/mach-omap2/sleep33xx.S
26+++ b/arch/arm/mach-omap2/sleep33xx.S
27@@ -104,13 +104,13 @@ pll_mode_restored_\name:
28 ldr r2, [r1]
29 orr r2, r2, #0xa0 @ a reasonable delay for entering SR
30 str r2, [r1, #0]
31+ str r2, [r1, #4] @ write to shadow register also
32
33 ldr r2, ddr_start @ do a dummy access to DDR
34 ldr r3, [r2, #0]
35 ldr r3, [r1, #0]
36 orr r3, r3, #0x200 @ now set the LP MODE to Self-Refresh
37 str r3, [r1, #0]
38- str r2, [r1, #4] @ write to shadow register also
39
40 mov r1, #0x1000 @ Give some time for the system to enter SR
41 wait_sr:
42@@ -130,6 +130,11 @@ wait_emif_disable:
43 cmp r2, r3
44 bne wait_emif_disable
45
46+ /* DDR3 reset override and mDDR mode selection */
47+ ldr r0, virt_ddr_io_ctrl
48+ mov r1, #(0x9 << 28)
49+ str r1, [r0]
50+
51 /* Weak pull down for DQ, DM */
52 ldr r1, virt_ddr_io_pull1
53 ldr r2, susp_io_pull
54@@ -144,13 +149,6 @@ wait_emif_disable:
55 ldr r2, susp_vtp_ctrl_val
56 str r2, [r1]
57
58- /* IO to work in mDDR mode */
59- ldr r0, virt_ddr_io_ctrl
60- ldr r1, [r0]
61- mov r2, #1
62- mov r3, r2, lsl #28
63- str r3, [r0]
64-
65 /* Enable SRAM LDO ret mode */
66 ldr r0, virt_sram_ldo_addr
67 ldr r1, [r0]
68@@ -198,13 +196,6 @@ wait_emif_disable:
69 bic r1, #1
70 str r1, [r0]
71
72- /* IO to work in DDR mode */
73- ldr r0, virt_ddr_io_ctrl
74- ldr r1, [r0]
75- mov r2, #0x0
76- mov r3, r2, lsl #28
77- str r3, [r0]
78-
79 /* Restore the pull for DQ, DM */
80 ldr r1, virt_ddr_io_pull1
81 ldr r2, resume_io_pull1
82@@ -214,6 +205,15 @@ wait_emif_disable:
83 ldr r2, resume_io_pull2
84 str r2, [r1]
85
86+ /* Enable EMIF */
87+ ldr r1, virt_emif_clkctrl
88+ mov r2, #0x2
89+ str r2, [r1]
90+wait_emif_enable:
91+ ldr r3, [r1]
92+ cmp r2, r3
93+ bne wait_emif_enable
94+
95 /* Enable VTP */
96 config_vtp_abt:
97 ldr r0, virt_ddr_vtp_ctrl
98@@ -241,14 +241,10 @@ poll_vtp_ready_abt:
99 tst r1, #(1 << 5)
100 beq poll_vtp_ready_abt
101
102- /* Enable EMIF */
103- ldr r1, virt_emif_clkctrl
104- mov r2, #0x2
105- str r2, [r1]
106-wait_emif_enable:
107- ldr r3, [r1]
108- cmp r2, r3
109- bne wait_emif_enable
110+ /* DDR3 reset override and mDDR mode clear */
111+ ldr r0, virt_ddr_io_ctrl
112+ mov r1, #0
113+ str r1, [r0]
114
115 /* Disable EMIF self-refresh */
116 ldr r0, emif_addr_virt
117@@ -286,19 +282,6 @@ ENTRY(am33xx_resume_from_deep_sleep)
118 ldr r2, resume_io_pull2
119 str r2, [r1]
120
121- /* Disable EMIF self-refresh */
122- ldr r0, emif_phys_addr
123- add r0, r0, #EMIF4_0_SDRAM_MGMT_CTRL
124- ldr r1, [r0]
125- bic r1, r1, #(0x7 << 7)
126- str r1, [r0]
127-
128- /* Take out IO of mDDR mode */
129- ldr r0, phys_ddr_io_ctrl
130- ldr r1, [r0]
131- bic r1, r1, #28
132- str r1, [r0]
133-
134
135 config_vtp:
136 ldr r0, phys_ddr_vtp_ctrl
137@@ -326,6 +309,10 @@ poll_vtp_ready:
138 tst r1, #(1 << 5)
139 beq poll_vtp_ready
140
141+ /* DDR3 reset override and mDDR mode clear */
142+ ldr r0, phys_ddr_io_ctrl
143+ mov r1, #0
144+ str r1, [r0]
145
146 config_emif_timings:
147 ldr r3, emif_phys_addr
148--
1491.7.7.6
150
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0008-usb-musb-update-babble-workaround-fix.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0008-usb-musb-update-babble-workaround-fix.patch
new file mode 100644
index 00000000..9b1ee973
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0008-usb-musb-update-babble-workaround-fix.patch
@@ -0,0 +1,168 @@
1From 6573dac17629de93ca32dca7fb656c550a4af00d Mon Sep 17 00:00:00 2001
2From: Ajay Kumar Gupta <ajay.gupta@ti.com>
3Date: Thu, 24 May 2012 10:37:27 +0530
4Subject: [PATCH 08/18] usb: musb: update babble workaround fix
5
6Resetting of usb controller also resets the tx and rx fifo addresses of
7each endpoints and hence tx and rx fifo addresses need to be reconfigured.
8
9Signed-off-by: Ravi B <ravibabu@ti.com>
10---
11 drivers/usb/musb/musb_core.c | 19 ++++++++++---------
12 drivers/usb/musb/musb_core.h | 1 +
13 drivers/usb/musb/musb_procfs.c | 1 +
14 drivers/usb/musb/ti81xx.c | 11 +++++------
15 4 files changed, 17 insertions(+), 15 deletions(-)
16
17diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
18index db5afeb..5850889 100644
19--- a/drivers/usb/musb/musb_core.c
20+++ b/drivers/usb/musb/musb_core.c
21@@ -1067,7 +1067,7 @@ static void musb_shutdown(struct platform_device *pdev)
22 */
23
24 /* mode 0 - fits in 2KB */
25-static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
26+static struct musb_fifo_cfg mode_0_cfg[] = {
27 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
28 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
29 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
30@@ -1076,7 +1076,7 @@ static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
31 };
32
33 /* mode 1 - fits in 4KB */
34-static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
35+static struct musb_fifo_cfg mode_1_cfg[] = {
36 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
37 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
38 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
39@@ -1085,7 +1085,7 @@ static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
40 };
41
42 /* mode 2 - fits in 4KB */
43-static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
44+static struct musb_fifo_cfg mode_2_cfg[] = {
45 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
46 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
47 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
48@@ -1095,7 +1095,7 @@ static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
49 };
50
51 /* mode 3 - fits in 4KB */
52-static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
53+static struct musb_fifo_cfg mode_3_cfg[] = {
54 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
55 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
56 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
57@@ -1105,7 +1105,7 @@ static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
58 };
59
60 /* mode 4 - fits in 16KB */
61-static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
62+static struct musb_fifo_cfg mode_4_cfg[] = {
63 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512,},
64 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512,},
65 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512,},
66@@ -1137,7 +1137,7 @@ static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
67
68
69 /* mode 5 - fits in 8KB */
70-static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
71+static struct musb_fifo_cfg mode_5_cfg[] = {
72 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
73 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
74 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
75@@ -1168,7 +1168,7 @@ static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
76 };
77
78 /* mode 6 - fits in 32KB */
79-static struct musb_fifo_cfg __devinitdata mode_6_cfg[] = {
80+static struct musb_fifo_cfg mode_6_cfg[] = {
81 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE,},
82 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE,},
83 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE,},
84@@ -1275,11 +1275,11 @@ fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
85 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
86 }
87
88-static struct musb_fifo_cfg __devinitdata ep0_cfg = {
89+static struct musb_fifo_cfg ep0_cfg = {
90 .style = FIFO_RXTX, .maxpacket = 64,
91 };
92
93-static int __devinit ep_config_from_table(struct musb *musb)
94+int ep_config_from_table(struct musb *musb)
95 {
96 const struct musb_fifo_cfg *cfg;
97 unsigned i, n;
98@@ -1370,6 +1370,7 @@ done:
99
100 return 0;
101 }
102+EXPORT_SYMBOL(ep_config_from_table);
103
104 /*
105 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
106diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
107index 87b6ff0..184c043 100644
108--- a/drivers/usb/musb/musb_core.h
109+++ b/drivers/usb/musb/musb_core.h
110@@ -652,6 +652,7 @@ static inline const char *get_dma_name(struct musb *musb)
111 return "?dma?";
112 #endif
113 }
114+extern int ep_config_from_table(struct musb *musb);
115
116 extern void musb_gb_work(struct work_struct *data);
117 /*-------------------------- ProcFS definitions ---------------------*/
118diff --git a/drivers/usb/musb/musb_procfs.c b/drivers/usb/musb/musb_procfs.c
119index e3aa42f..2db7eac 100644
120--- a/drivers/usb/musb/musb_procfs.c
121+++ b/drivers/usb/musb/musb_procfs.c
122@@ -719,6 +719,7 @@ static int musb_proc_write(struct file *file, const char __user *buffer,
123 INFO("T: start sending TEST_PACKET\n");
124 INFO("D: set/read dbug level\n");
125 INFO("K/k: enable/disable babble workaround\n");
126+ INFO("b: generate software babble interrupt\n");
127 break;
128
129 default:
130diff --git a/drivers/usb/musb/ti81xx.c b/drivers/usb/musb/ti81xx.c
131index d76a693..e3cf38b 100644
132--- a/drivers/usb/musb/ti81xx.c
133+++ b/drivers/usb/musb/ti81xx.c
134@@ -813,8 +813,7 @@ int musb_simulate_babble(struct musb *musb)
135 mdelay(100);
136
137 /* generate s/w babble interrupt */
138- musb_writel(reg_base, USB_IRQ_STATUS_RAW_1,
139- MUSB_INTR_BABBLE);
140+ musb_writel(reg_base, USB_IRQ_STATUS_RAW_1, MUSB_INTR_BABBLE);
141 return 0;
142 }
143 EXPORT_SYMBOL(musb_simulate_babble);
144@@ -828,7 +827,8 @@ void musb_babble_workaround(struct musb *musb)
145
146 /* Reset the controller */
147 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
148- udelay(100);
149+ while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
150+ cpu_relax();
151
152 /* Shutdown the on-chip PHY and its PLL. */
153 if (data->set_phy_power)
154@@ -843,9 +843,8 @@ void musb_babble_workaround(struct musb *musb)
155 data->set_phy_power(musb->id, 1);
156 mdelay(100);
157
158- /* save the usbotgss register contents */
159- musb_platform_enable(musb);
160-
161+ /* re-setup the endpoint fifo addresses */
162+ ep_config_from_table(musb);
163 musb_start(musb);
164 }
165
166--
1671.7.7.6
168
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0009-usb-musb-ti81xx-print-the-usbss-revision-id-during-i.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0009-usb-musb-ti81xx-print-the-usbss-revision-id-during-i.patch
new file mode 100644
index 00000000..fce35bc7
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0009-usb-musb-ti81xx-print-the-usbss-revision-id-during-i.patch
@@ -0,0 +1,29 @@
1From 9a362c5b759686f056070b6cddfc7405782464a9 Mon Sep 17 00:00:00 2001
2From: Ajay Kumar Gupta <ajay.gupta@ti.com>
3Date: Wed, 23 May 2012 15:32:37 +0530
4Subject: [PATCH 09/18] usb: musb: ti81xx: print the usbss revision id during
5 init
6
7This is to identify the id which can help in debugging.
8
9Signed-off-by: Ravi B <ravibabu@ti.com>
10---
11 drivers/usb/musb/ti81xx.c | 2 ++
12 1 files changed, 2 insertions(+), 0 deletions(-)
13
14diff --git a/drivers/usb/musb/ti81xx.c b/drivers/usb/musb/ti81xx.c
15index e3cf38b..f7b2f62 100644
16--- a/drivers/usb/musb/ti81xx.c
17+++ b/drivers/usb/musb/ti81xx.c
18@@ -1069,6 +1069,8 @@ int ti81xx_musb_init(struct musb *musb)
19 if (!rev)
20 return -ENODEV;
21
22+ pr_info("MUSB%d controller's USBSS revision = %08x\n", musb->id, rev);
23+
24 if (is_host_enabled(musb))
25 setup_timer(&musb->otg_workaround, otg_timer,
26 (unsigned long) musb);
27--
281.7.7.6
29
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0010-usb-musb-cppi41-enable-txfifo-empty-interrupt-logic.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0010-usb-musb-cppi41-enable-txfifo-empty-interrupt-logic.patch
new file mode 100644
index 00000000..761f4d60
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0010-usb-musb-cppi41-enable-txfifo-empty-interrupt-logic.patch
@@ -0,0 +1,425 @@
1From a4d99c3c1e01b91b69c6939ba3ee708611869402 Mon Sep 17 00:00:00 2001
2From: Ajay Kumar Gupta <ajay.gupta@ti.com>
3Date: Wed, 23 May 2012 15:25:32 +0530
4Subject: [PATCH 10/18] usb: musb: cppi41: enable txfifo empty interrupt logic
5
6Fixes the txdma early completion issue as the TxFIFO empty interrupt
7logic generates an interrupt when last byte from TxFIFO is
8transmitted out.
9
10The application issues fixed are -
111) The isochronous gap issue seen due to txdma early completion and
12 thus a delay caused in scheduling of txdma workthread which polls
13 for txfifo empty status.
14
152) The workthread is rescheduled once again when txfifo is empty to
16 make sure any miss of transfer of the data in internal cppififo.
17
183) For non-isochronous tx request uses workthread to poll for txfifo
19 empty status if there is possiblity of data in internal cppififo
20 other wise the request is completed directly in the tx-dma isr
21 function.
22
23Signed-off-by: Ravi B <ravibabu@ti.com>
24---
25 drivers/usb/musb/cppi41_dma.c | 101 ++++++++++++++++++++++++++++++++++++++--
26 drivers/usb/musb/cppi41_dma.h | 7 +++
27 drivers/usb/musb/musb_core.h | 16 ++++++
28 drivers/usb/musb/musb_gadget.c | 1 +
29 drivers/usb/musb/musb_host.c | 1 +
30 drivers/usb/musb/ti81xx.c | 51 ++++++++++++++++++++-
31 drivers/usb/musb/ti81xx.h | 3 +
32 7 files changed, 174 insertions(+), 6 deletions(-)
33
34diff --git a/drivers/usb/musb/cppi41_dma.c b/drivers/usb/musb/cppi41_dma.c
35index 4761acd..3665d0f 100644
36--- a/drivers/usb/musb/cppi41_dma.c
37+++ b/drivers/usb/musb/cppi41_dma.c
38@@ -101,6 +101,9 @@ struct cppi41_channel {
39 u8 inf_mode;
40 u8 tx_complete;
41 u8 hb_mult;
42+ u8 txf_complete;
43+ u8 txfifo_intr_enable;
44+ u8 count;
45 };
46
47 /**
48@@ -132,6 +135,7 @@ struct cppi41 {
49 u32 teardown_reg_offs; /* USB_TEARDOWN_REG offset */
50 u32 bd_size;
51 u8 inf_mode;
52+ u8 txfifo_intr_enable; /* txfifo empty interrupt logic */
53 };
54
55 struct usb_cppi41_info usb_cppi41_info[2];
56@@ -573,6 +577,9 @@ static unsigned cppi41_next_tx_segment(struct cppi41_channel *tx_ch)
57 u16 q_mgr = cppi_info->q_mgr;
58 u16 tx_comp_q = cppi_info->tx_comp_q[tx_ch->ch_num];
59 u8 en_bd_intr = cppi->en_bd_intr;
60+ u8 is_isoc = 0;
61+ struct musb_hw_ep *hw_ep = cppi->musb->endpoints + tx_ch->end_pt->epnum;
62+ int xfer_type = hw_ep->xfer_type;
63
64 /*
65 * Tx can use the generic RNDIS mode where we can probably fit this
66@@ -599,6 +606,12 @@ static unsigned cppi41_next_tx_segment(struct cppi41_channel *tx_ch)
67 tx_ch->ch_num, tx_ch->dma_mode ? "accelerated" : "transparent",
68 pkt_size, num_pds, tx_ch->start_addr + tx_ch->curr_offset, length);
69
70+ if (xfer_type == USB_ENDPOINT_XFER_ISOC)
71+ is_isoc = 1;
72+
73+ if (is_isoc && cppi->txfifo_intr_enable && (length <= tx_ch->pkt_size))
74+ tx_ch->txfifo_intr_enable = 1;
75+
76 for (n = 0; n < num_pds; n++) {
77 struct cppi41_host_pkt_desc *hw_desc;
78
79@@ -640,6 +653,14 @@ static unsigned cppi41_next_tx_segment(struct cppi41_channel *tx_ch)
80 dev_dbg(musb->controller, "TX PD %p: buf %08x, len %08x, pkt info %08x\n", curr_pd,
81 hw_desc->buf_ptr, hw_desc->buf_len, hw_desc->pkt_info);
82
83+ /* enable tx fifo empty interrupt */
84+ if (tx_ch->txfifo_intr_enable) {
85+ dev_dbg(musb->controller, "txs(%p %d) enable txFintr\n",
86+ curr_pd, hw_desc->orig_buf_len &
87+ ~CPPI41_PKT_INTR_FLAG);
88+ txfifoempty_int_enable(cppi->musb, curr_pd->ep_num);
89+ }
90+
91 cppi41_queue_push(&tx_ch->queue_obj, curr_pd->dma_addr,
92 USB_CPPI41_DESC_ALIGN, pkt_size);
93 }
94@@ -1211,6 +1232,8 @@ static int cppi41_channel_abort(struct dma_channel *channel)
95 csr &= ~MUSB_TXCSR_DMAENAB;
96 musb_writew(epio, MUSB_TXCSR, csr);
97
98+ cppi_ch->tx_complete = 0;
99+ cppi_ch->txf_complete = 0;
100 /* Tear down Tx DMA channel */
101 usb_tx_ch_teardown(cppi_ch);
102
103@@ -1224,7 +1247,6 @@ static int cppi41_channel_abort(struct dma_channel *channel)
104 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_H_WZC_BITS;
105 musb_writew(epio, MUSB_TXCSR, csr);
106 musb_writew(epio, MUSB_TXCSR, csr);
107- cppi_ch->tx_complete = 0;
108 } else { /* Rx */
109 dprintk("Rx channel teardown, cppi_ch = %p\n", cppi_ch);
110
111@@ -1331,16 +1353,23 @@ void txdma_completion_work(struct work_struct *data)
112 */
113 if (!tx_ch->end_pt) {
114 tx_ch->tx_complete = 0;
115+ tx_ch->count = 0;
116 continue;
117 }
118
119 epio = tx_ch->end_pt->regs;
120 csr = musb_readw(epio, MUSB_TXCSR);
121
122- if (csr & (MUSB_TXCSR_TXPKTRDY |
123- MUSB_TXCSR_FIFONOTEMPTY)) {
124+ if (!tx_ch->txfifo_intr_enable &&
125+ (csr & (MUSB_TXCSR_TXPKTRDY |
126+ MUSB_TXCSR_FIFONOTEMPTY))) {
127 resched = 1;
128 } else {
129+ if (tx_ch->count > 0) {
130+ tx_ch->count--;
131+ resched = 1;
132+ continue;
133+ }
134 tx_ch->channel.status =
135 MUSB_DMA_STATUS_FREE;
136 tx_ch->tx_complete = 0;
137@@ -1363,6 +1392,38 @@ void txdma_completion_work(struct work_struct *data)
138
139 }
140
141+void cppi41_handle_txfifo_intr(struct musb *musb, u16 usbintr)
142+{
143+ struct cppi41 *cppi;
144+ struct cppi41_channel *tx_ch;
145+ int index;
146+
147+ cppi = container_of(musb->dma_controller, struct cppi41, controller);
148+ for (index = 0; (index < USB_CPPI41_NUM_CH) && usbintr; index++) {
149+ if (usbintr & 1) {
150+ tx_ch = &cppi->tx_cppi_ch[index];
151+ if (tx_ch->txf_complete) {
152+ /* disable txfifo empty interupt */
153+ txfifoempty_int_disable(musb, index+1);
154+ tx_ch->txf_complete = 0;
155+ if (!tx_ch->txfifo_intr_enable)
156+ dev_dbg(musb->controller,
157+ "Bug, wrong TxFintr ep%d\n", index+1);
158+ tx_ch->txfifo_intr_enable = 0;
159+
160+ tx_ch->channel.status =
161+ MUSB_DMA_STATUS_FREE;
162+
163+ dev_dbg(musb->controller,
164+ "txc: givback ep%d\n", index+1);
165+ musb_dma_completion(musb, index+1, 1);
166+ }
167+ }
168+ usbintr = usbintr >> 1;
169+ }
170+}
171+EXPORT_SYMBOL(cppi41_handle_txfifo_intr);
172+
173 /**
174 * cppi41_dma_controller_create -
175 * instantiate an object representing DMA controller.
176@@ -1386,6 +1447,7 @@ cppi41_dma_controller_create(struct musb *musb, void __iomem *mregs)
177 cppi->controller.channel_abort = cppi41_channel_abort;
178 cppi->cppi_info = (struct usb_cppi41_info *)&usb_cppi41_info[musb->id];;
179 cppi->en_bd_intr = cppi->cppi_info->bd_intr_ctrl;
180+ cppi->txfifo_intr_enable = musb->txfifo_intr_enable;
181 INIT_WORK(&cppi->txdma_work, txdma_completion_work);
182
183 /*
184@@ -1472,6 +1534,9 @@ static void usb_process_tx_queue(struct cppi41 *cppi, unsigned index)
185 (tx_ch->transfer_mode && !tx_ch->zlp_queued))
186 cppi41_next_tx_segment(tx_ch);
187 else if (tx_ch->channel.actual_len >= tx_ch->length) {
188+ void __iomem *epio;
189+ u16 csr;
190+
191 /*
192 * We get Tx DMA completion interrupt even when
193 * data is still in FIFO and not moved out to
194@@ -1480,8 +1545,34 @@ static void usb_process_tx_queue(struct cppi41 *cppi, unsigned index)
195 * USB functionality. So far, we have obsered
196 * failure with iperf.
197 */
198- tx_ch->tx_complete = 1;
199- schedule_work(&cppi->txdma_work);
200+ /* wait for tx fifo empty completion interrupt
201+ * if enabled other wise use the workthread
202+ * to poll fifo empty status
203+ */
204+ epio = tx_ch->end_pt->regs;
205+ csr = musb_readw(epio, MUSB_TXCSR);
206+
207+ if (tx_ch->txfifo_intr_enable) {
208+ tx_ch->txf_complete = 1;
209+ dev_dbg(musb->controller,
210+ "wait for TxF-EmptyIntr ep%d\n", ep_num);
211+ } else {
212+ int residue;
213+
214+ residue = tx_ch->channel.actual_len %
215+ tx_ch->pkt_size;
216+
217+ if (tx_ch->pkt_size > 128 && !residue) {
218+ tx_ch->channel.status =
219+ MUSB_DMA_STATUS_FREE;
220+ musb_dma_completion(cppi->musb,
221+ ep_num, 1);
222+ } else {
223+ tx_ch->tx_complete = 1;
224+ tx_ch->count = 1;
225+ schedule_work(&cppi->txdma_work);
226+ }
227+ }
228 }
229 }
230 }
231diff --git a/drivers/usb/musb/cppi41_dma.h b/drivers/usb/musb/cppi41_dma.h
232index bedf3bb..053a135 100644
233--- a/drivers/usb/musb/cppi41_dma.h
234+++ b/drivers/usb/musb/cppi41_dma.h
235@@ -58,4 +58,11 @@ extern struct usb_cppi41_info usb_cppi41_info[];
236 */
237 void cppi41_completion(struct musb *musb, u32 rx, u32 tx);
238
239+/**
240+ * cppi41_handle_txfifo_intr - Handles tx fifo empty interupts
241+ * @musb: the controller
242+ */
243+void cppi41_handle_txfifo_intr(struct musb *musb, u16 usbintr);
244+void txfifoempty_int_enable(struct musb *musb, u8 ep_num);
245+void txfifoempty_int_disable(struct musb *musb, u8 ep_num);
246 #endif /* _CPPI41_DMA_H_ */
247diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
248index 184c043..40f02ae 100644
249--- a/drivers/usb/musb/musb_core.h
250+++ b/drivers/usb/musb/musb_core.h
251@@ -228,6 +228,8 @@ struct musb_platform_ops {
252 void __iomem *);
253 void (*dma_controller_destroy)(struct dma_controller *);
254 int (*simulate_babble_intr)(struct musb *musb);
255+ void (*txfifoempty_intr_enable)(struct musb *musb, u8 ep_num);
256+ void (*txfifoempty_intr_disable)(struct musb *musb, u8 ep_num);
257 };
258
259 /*
260@@ -278,6 +280,7 @@ struct musb_hw_ep {
261 struct musb_ep ep_out; /* RX */
262
263 u8 prev_toggle; /* Rx */
264+ u8 xfer_type;
265 };
266
267 static inline struct musb_request *next_in_request(struct musb_hw_ep *hw_ep)
268@@ -472,6 +475,7 @@ struct musb {
269 u64 *orig_dma_mask;
270 #endif
271 short fifo_mode;
272+ u8 txfifo_intr_enable;
273 };
274
275 static inline struct musb *gadget_to_musb(struct usb_gadget *g)
276@@ -562,6 +566,18 @@ extern irqreturn_t musb_interrupt(struct musb *);
277
278 extern void musb_hnp_stop(struct musb *musb);
279
280+static inline void txfifoempty_int_enable(struct musb *musb, u8 ep_num)
281+{
282+ if (musb->ops->txfifoempty_intr_enable)
283+ musb->ops->txfifoempty_intr_enable(musb, ep_num);
284+}
285+
286+static inline void txfifoempty_int_disable(struct musb *musb, u8 ep_num)
287+{
288+ if (musb->ops->txfifoempty_intr_disable)
289+ musb->ops->txfifoempty_intr_disable(musb, ep_num);
290+}
291+
292 static inline void musb_platform_set_vbus(struct musb *musb, int is_on)
293 {
294 if (musb->ops->set_vbus)
295diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
296index 305d843..47349ca 100644
297--- a/drivers/usb/musb/musb_gadget.c
298+++ b/drivers/usb/musb/musb_gadget.c
299@@ -1020,6 +1020,7 @@ static int musb_gadget_enable(struct usb_ep *ep,
300 goto fail;
301 }
302 musb_ep->type = usb_endpoint_type(desc);
303+ hw_ep->xfer_type = musb_ep->type;
304
305 /* check direction and (later) maxpacket size against endpoint */
306 if (usb_endpoint_num(desc) != epnum)
307diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
308index 80d83bd..c3629bd 100644
309--- a/drivers/usb/musb/musb_host.c
310+++ b/drivers/usb/musb/musb_host.c
311@@ -246,6 +246,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
312 /* initialize software qh state */
313 qh->offset = 0;
314 qh->segsize = 0;
315+ hw_ep->xfer_type = qh->type;
316
317 /* gather right source of data */
318 switch (qh->type) {
319diff --git a/drivers/usb/musb/ti81xx.c b/drivers/usb/musb/ti81xx.c
320index f7b2f62..7e21c25 100644
321--- a/drivers/usb/musb/ti81xx.c
322+++ b/drivers/usb/musb/ti81xx.c
323@@ -568,7 +568,6 @@ int cppi41_enable_sched_rx(void)
324 cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
325 return 0;
326 }
327-#endif /* CONFIG_USB_TI_CPPI41_DMA */
328
329 /*
330 * Because we don't set CTRL.UINT, it's "important" to:
331@@ -577,6 +576,33 @@ int cppi41_enable_sched_rx(void)
332 * - use INTSET/INTCLR instead.
333 */
334
335+void txfifoempty_intr_enable(struct musb *musb, u8 ep_num)
336+{
337+ void __iomem *reg_base = musb->ctrl_base;
338+ u32 coremask;
339+
340+ if (musb->txfifo_intr_enable) {
341+ coremask = musb_readl(reg_base, USB_CORE_INTR_SET_REG);
342+ coremask |= (1 << (ep_num + 16));
343+ musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
344+ dev_dbg(musb->controller, "enable txF intr ep%d coremask %x\n",
345+ ep_num, coremask);
346+ }
347+}
348+
349+void txfifoempty_intr_disable(struct musb *musb, u8 ep_num)
350+{
351+ void __iomem *reg_base = musb->ctrl_base;
352+ u32 coremask;
353+
354+ if (musb->txfifo_intr_enable) {
355+ coremask = (1 << (ep_num + 16));
356+ musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, coremask);
357+ }
358+}
359+
360+#endif /* CONFIG_USB_TI_CPPI41_DMA */
361+
362 /**
363 * ti81xx_musb_enable - enable interrupts
364 */
365@@ -889,6 +915,18 @@ static irqreturn_t ti81xx_interrupt(int irq, void *hci)
366 musb->int_usb = (usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
367
368 dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);
369+
370+ if (musb->txfifo_intr_enable && (usbintr & USB_INTR_TXFIFO_MASK)) {
371+#ifdef CONFIG_USB_TI_CPPI41_DMA
372+ dev_dbg(musb->controller,
373+ "TxFIFOIntr %x\n", usbintr >> USB_INTR_TXFIFO_EMPTY);
374+ cppi41_handle_txfifo_intr(musb,
375+ usbintr >> USB_INTR_TXFIFO_EMPTY);
376+ ret = IRQ_HANDLED;
377+#endif
378+ }
379+ usbintr &= ~USB_INTR_TXFIFO_MASK;
380+
381 /*
382 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
383 * AM3517's missing ID change IRQ. We need an ID change IRQ to
384@@ -1108,6 +1146,13 @@ int ti81xx_musb_init(struct musb *musb)
385 /* set musb controller to host mode */
386 musb_platform_set_mode(musb, mode);
387
388+#ifdef CONFIG_USB_TI_CPPI41_DMA
389+ musb->txfifo_intr_enable = 1;
390+ if (musb->txfifo_intr_enable)
391+ printk(KERN_DEBUG "TxFifo Empty intr enabled\n");
392+ else
393+ printk(KERN_DEBUG "TxFifo Empty intr disabled\n");
394+#endif
395 /* enable babble workaround */
396 INIT_WORK(&musb->work, evm_deferred_musb_restart);
397 musb->enable_babble_work = 0;
398@@ -1184,6 +1229,10 @@ static struct musb_platform_ops ti81xx_ops = {
399 .dma_controller_create = cppi41_dma_controller_create,
400 .dma_controller_destroy = cppi41_dma_controller_destroy,
401 .simulate_babble_intr = musb_simulate_babble,
402+#ifdef CONFIG_USB_TI_CPPI41_DMA
403+ .txfifoempty_intr_enable = txfifoempty_intr_enable,
404+ .txfifoempty_intr_disable = txfifoempty_intr_disable,
405+#endif
406 };
407
408 static void __devexit ti81xx_delete_musb_pdev(struct ti81xx_glue *glue, u8 id)
409diff --git a/drivers/usb/musb/ti81xx.h b/drivers/usb/musb/ti81xx.h
410index e0dbd3e..d173b55 100644
411--- a/drivers/usb/musb/ti81xx.h
412+++ b/drivers/usb/musb/ti81xx.h
413@@ -125,6 +125,9 @@
414 /* USB interrupt register bits */
415 #define USB_INTR_USB_SHIFT 0
416 #define USB_INTR_USB_MASK (0x1ff << USB_INTR_USB_SHIFT) /* 8 Mentor */
417+#define USB_INTR_TXFIFO_MASK (0xffff << 16)
418+#define USB_INTR_TXFIFO_EMPTY 17
419+
420 /* interrupts and DRVVBUS interrupt */
421 #define USB_INTR_DRVVBUS 0x100
422 #define USB_INTR_RX_SHIFT 16
423--
4241.7.7.6
425
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0011-usb-musb-host-Flush-txfifo-only-if-TxPktRdy-bit-set.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0011-usb-musb-host-Flush-txfifo-only-if-TxPktRdy-bit-set.patch
new file mode 100644
index 00000000..cd7a96bc
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0011-usb-musb-host-Flush-txfifo-only-if-TxPktRdy-bit-set.patch
@@ -0,0 +1,57 @@
1From e5fad55642b91e45ed640c546dd10bd454b6e4df Mon Sep 17 00:00:00 2001
2From: Ajay Kumar Gupta <ajay.gupta@ti.com>
3Date: Thu, 24 May 2012 15:42:53 +0530
4Subject: [PATCH 11/18] usb: musb: host: Flush txfifo only if TxPktRdy bit set
5
6This is needed as per mentor core documents.
7
8Signed-off-by: Ravi B <ravibabu@ti.com>
9---
10 drivers/usb/musb/musb_host.c | 23 ++++++++++++-----------
11 1 files changed, 12 insertions(+), 11 deletions(-)
12
13diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
14index c3629bd..7545a65 100644
15--- a/drivers/usb/musb/musb_host.c
16+++ b/drivers/usb/musb/musb_host.c
17@@ -133,25 +133,26 @@ static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
18 struct musb *musb = ep->musb;
19 void __iomem *epio = ep->regs;
20 u16 csr;
21- u16 lastcsr = 0;
22 int retries = 1000;
23
24 csr = musb_readw(epio, MUSB_TXCSR);
25- while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
26- if (csr != lastcsr)
27- dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
28- lastcsr = csr;
29- csr = MUSB_TXCSR_FLUSHFIFO;
30+ while (csr & MUSB_TXCSR_TXPKTRDY) {
31+ if (!(csr & MUSB_TXCSR_FIFONOTEMPTY))
32+ return;
33+ else
34+ dev_dbg(musb->controller,
35+ "Host TX FIFONOTEMPTY csr: %02x\n", csr);
36+
37+ csr |= MUSB_TXCSR_FLUSHFIFO;
38 musb_writew(epio, MUSB_TXCSR, csr);
39 csr = musb_readw(epio, MUSB_TXCSR);
40- if (!(csr & MUSB_TXCSR_FIFONOTEMPTY))
41- break;
42+
43 if (retries-- < 1) {
44- dev_dbg(musb->controller, "Could not flush host TX%d fifo: csr: %04x\n",
45- ep->epnum, csr);
46+ dev_dbg(musb->controller,
47+ "Could not flush host TX%d fifo: csr: %04x\n",
48+ ep->epnum, csr);
49 return;
50 }
51- mdelay(1);
52 }
53 }
54
55--
561.7.7.6
57
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0012-usb-musb-cppi41-use-dsb-to-make-sure-PDs-are-updated.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0012-usb-musb-cppi41-use-dsb-to-make-sure-PDs-are-updated.patch
new file mode 100644
index 00000000..0edb2557
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0012-usb-musb-cppi41-use-dsb-to-make-sure-PDs-are-updated.patch
@@ -0,0 +1,43 @@
1From 946a82d6042097a0b3c5e072df75da9ffcbbc44c Mon Sep 17 00:00:00 2001
2From: Ajay Kumar Gupta <ajay.gupta@ti.com>
3Date: Thu, 24 May 2012 15:45:45 +0530
4Subject: [PATCH 12/18] usb: musb: cppi41: use dsb() to make sure PDs are
5 updated to memory
6
7Before pushing the tx/rx cppi packet descriptors to respective input queues
8of TX/RX DMA channels, use memory barrier dsb() to make sure the descriptors
9contents are written to memory
10
11Signed-off-by: Ravi B <ravibabu@ti.com>
12---
13 drivers/usb/musb/cppi41_dma.c | 7 +++++++
14 1 files changed, 7 insertions(+), 0 deletions(-)
15
16diff --git a/drivers/usb/musb/cppi41_dma.c b/drivers/usb/musb/cppi41_dma.c
17index 3665d0f..bf74cf3 100644
18--- a/drivers/usb/musb/cppi41_dma.c
19+++ b/drivers/usb/musb/cppi41_dma.c
20@@ -653,6 +653,9 @@ static unsigned cppi41_next_tx_segment(struct cppi41_channel *tx_ch)
21 dev_dbg(musb->controller, "TX PD %p: buf %08x, len %08x, pkt info %08x\n", curr_pd,
22 hw_desc->buf_ptr, hw_desc->buf_len, hw_desc->pkt_info);
23
24+ /* make sure descriptor details are updated to memory*/
25+ dsb();
26+
27 /* enable tx fifo empty interrupt */
28 if (tx_ch->txfifo_intr_enable) {
29 dev_dbg(musb->controller, "txs(%p %d) enable txFintr\n",
30@@ -869,6 +872,10 @@ static unsigned cppi41_next_rx_segment(struct cppi41_channel *rx_ch)
31
32 if (en_bd_intr)
33 hw_desc->orig_buf_len |= CPPI41_PKT_INTR_FLAG;
34+
35+ /* make sure descriptor details are updated to memory*/
36+ dsb();
37+
38 /*
39 * Push the free Rx packet descriptor
40 * to the free descriptor/buffer queue.
41--
421.7.7.6
43
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0013-usb-musb-cppi41-fix-zero-byte-OUT-issue.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0013-usb-musb-cppi41-fix-zero-byte-OUT-issue.patch
new file mode 100644
index 00000000..11f05c10
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0013-usb-musb-cppi41-fix-zero-byte-OUT-issue.patch
@@ -0,0 +1,46 @@
1From 4fbf77cebc6d141b9a74a92fd2b3f756908ef657 Mon Sep 17 00:00:00 2001
2From: Ajay Kumar Gupta <ajay.gupta@ti.com>
3Date: Wed, 18 Apr 2012 00:16:03 +0530
4Subject: [PATCH 13/18] usb: musb: cppi41: fix zero byte OUT issue
5
6Fixes ZERO byte transfer in tx direction which was not being done in DMA mode.
7Used PIO mode for all zero byte tx transfer.
8---
9 drivers/usb/musb/musb_host.c | 12 +++++++++++-
10 1 files changed, 11 insertions(+), 1 deletions(-)
11
12diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
13index 7545a65..8981586 100644
14--- a/drivers/usb/musb/musb_host.c
15+++ b/drivers/usb/musb/musb_host.c
16@@ -761,6 +761,8 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
17 void __iomem *epio = hw_ep->regs;
18 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
19 u16 packet_sz = qh->maxpacket;
20+ u8 use_dma = 1;
21+ u16 csr;
22
23 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
24 "h_addr%02x h_port%02x bytes %d\n",
25@@ -772,9 +774,17 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
26
27 musb_ep_select(musb, mbase, epnum);
28
29+ if (is_out && !len) {
30+ use_dma = 0;
31+ csr = musb_readw(epio, MUSB_TXCSR);
32+ csr &= ~MUSB_TXCSR_DMAENAB;
33+ musb_writew(epio, MUSB_TXCSR, csr);
34+ hw_ep->tx_channel = NULL;
35+ }
36+
37 /* candidate for DMA? */
38 dma_controller = musb->dma_controller;
39- if (is_dma_capable() && epnum && dma_controller) {
40+ if (use_dma && is_dma_capable() && epnum && dma_controller) {
41 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
42 if (!dma_channel) {
43 dma_channel = dma_controller->channel_alloc(
44--
451.7.7.6
46
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0014-usb-musb-host-fix-for-urb-error-handling.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0014-usb-musb-host-fix-for-urb-error-handling.patch
new file mode 100644
index 00000000..8831c2ca
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0014-usb-musb-host-fix-for-urb-error-handling.patch
@@ -0,0 +1,66 @@
1From 984969ee49797eadbfd4ca72f1d55c6ac52b4db6 Mon Sep 17 00:00:00 2001
2From: Ajay Kumar Gupta <ajay.gupta@ti.com>
3Date: Thu, 24 May 2012 15:56:37 +0530
4Subject: [PATCH 14/18] usb: musb: host: fix for urb error handling
5
6Fixes below two issues related urb error handling
7
81) Handling incomplete transfer when short packet not expected
9
102) Do not start next urb when current urb has failed, this is
11 because stack will unlink/dequeue remaining urbs. Programming
12 the next urb will endup in urb completion because of expected
13 error (cause of current urb failure) interrupts and interfere
14 with urb dequeue initiated by stack and cause a crash.
15
16Signed-off-by: Ravi B <ravibabu@ti.com>
17Signed-off-by: Visuvanadan Pasupathy <vichu@ti.com>
18---
19 drivers/usb/musb/musb_host.c | 24 +++++++++++++++++++++---
20 1 files changed, 21 insertions(+), 3 deletions(-)
21
22diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
23index 8981586..13520ee 100644
24--- a/drivers/usb/musb/musb_host.c
25+++ b/drivers/usb/musb/musb_host.c
26@@ -481,7 +481,14 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb,
27 }
28 }
29
30- if (qh != NULL && qh->is_ready) {
31+ /* we should not start next urb when current urb
32+ * has failed, this is because stack will unlink/dequeue
33+ * remaining urbs. Programming the next urb will endup in
34+ * urb completion because of expected error (cause of current
35+ * urb failure) interrupts and interfere with urb dequeue
36+ * initiated by stack and cause a crash.
37+ */
38+ if (status == 0 && qh != NULL && qh->is_ready) {
39 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
40 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
41 musb_start_urb(musb, is_in, qh);
42@@ -1891,8 +1898,19 @@ finish:
43 urb->actual_length += xfer_len;
44 qh->offset += xfer_len;
45 if (done) {
46- if (urb->status == -EINPROGRESS)
47- urb->status = status;
48+ if (urb->status == -EINPROGRESS) {
49+ /* If short packet is not expected any transfer length
50+ * less than actual length is an error, hence
51+ * set urb status to -EREMOTEIO
52+ */
53+ if ((urb->status == -EINPROGRESS)
54+ && (urb->transfer_flags & URB_SHORT_NOT_OK)
55+ && (urb->actual_length
56+ < urb->transfer_buffer_length))
57+ urb->status = -EREMOTEIO;
58+ else
59+ urb->status = status;
60+ }
61 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
62 }
63 }
64--
651.7.7.6
66
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0015-usb-musb-cppi41-txdma-flushfifo-fixes-during-channel.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0015-usb-musb-cppi41-txdma-flushfifo-fixes-during-channel.patch
new file mode 100644
index 00000000..4bf31443
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0015-usb-musb-cppi41-txdma-flushfifo-fixes-during-channel.patch
@@ -0,0 +1,50 @@
1From a67c22912417f2b4c22f063767405992e702efbe Mon Sep 17 00:00:00 2001
2From: Ravi B <ravibabu@ti.com>
3Date: Thu, 10 May 2012 17:05:41 +0530
4Subject: [PATCH 15/18] usb: musb: cppi41: txdma flushfifo fixes during
5 channel abort
6
7This patch fixes the flushfifo sequence during tx dma channel
8abort, the txfifo should be flushed only when the TXPKTRDY bit
9is set in TXCSR register.
10
11Signed-off-by: Ravi B <ravibabu@ti.com>
12---
13 drivers/usb/musb/cppi41_dma.c | 14 +++++++++-----
14 1 files changed, 9 insertions(+), 5 deletions(-)
15
16diff --git a/drivers/usb/musb/cppi41_dma.c b/drivers/usb/musb/cppi41_dma.c
17index bf74cf3..4367e4f 100644
18--- a/drivers/usb/musb/cppi41_dma.c
19+++ b/drivers/usb/musb/cppi41_dma.c
20@@ -1198,7 +1198,7 @@ static int cppi41_channel_abort(struct dma_channel *channel)
21 void __iomem *reg_base, *epio;
22 unsigned long pd_addr;
23 u32 csr, td_reg;
24- u8 ch_num, ep_num;
25+ u8 ch_num, ep_num, i;
26
27 cppi_ch = container_of(channel, struct cppi41_channel, channel);
28 ch_num = cppi_ch->ch_num;
29@@ -1250,10 +1250,14 @@ static int cppi41_channel_abort(struct dma_channel *channel)
30 musb_writel(reg_base, cppi->teardown_reg_offs, td_reg);
31
32 /* Flush FIFO of the endpoint */
33- csr = musb_readw(epio, MUSB_TXCSR);
34- csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_H_WZC_BITS;
35- musb_writew(epio, MUSB_TXCSR, csr);
36- musb_writew(epio, MUSB_TXCSR, csr);
37+ for (i = 0; i < 2; ++i) {
38+ csr = musb_readw(epio, MUSB_TXCSR);
39+ if (csr & MUSB_TXCSR_TXPKTRDY) {
40+ csr |= MUSB_TXCSR_FLUSHFIFO |
41+ MUSB_TXCSR_H_WZC_BITS;
42+ musb_writew(epio, MUSB_TXCSR, csr);
43+ }
44+ }
45 } else { /* Rx */
46 dprintk("Rx channel teardown, cppi_ch = %p\n", cppi_ch);
47
48--
491.7.7.6
50
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0016-usb-musb-cppi41-tx-dma-completion-fixes.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0016-usb-musb-cppi41-tx-dma-completion-fixes.patch
new file mode 100644
index 00000000..97983972
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0016-usb-musb-cppi41-tx-dma-completion-fixes.patch
@@ -0,0 +1,41 @@
1From 2e3ec89c3e6cf54d83479d7437696343463c90e5 Mon Sep 17 00:00:00 2001
2From: Ajay Kumar Gupta <ajay.gupta@ti.com>
3Date: Thu, 24 May 2012 16:03:02 +0530
4Subject: [PATCH 16/18] usb: musb: cppi41: tx dma completion fixes
5
6Use spinlock_irqsave/restore only during txdma completion giveback.
7
8Signed-off-by: Ravi B <ravibabu@ti.com>
9---
10 drivers/usb/musb/cppi41_dma.c | 5 +++--
11 1 files changed, 3 insertions(+), 2 deletions(-)
12
13diff --git a/drivers/usb/musb/cppi41_dma.c b/drivers/usb/musb/cppi41_dma.c
14index 4367e4f..ea83f9a 100644
15--- a/drivers/usb/musb/cppi41_dma.c
16+++ b/drivers/usb/musb/cppi41_dma.c
17@@ -1354,7 +1354,6 @@ void txdma_completion_work(struct work_struct *data)
18 u16 csr;
19
20 tx_ch = &cppi->tx_cppi_ch[index];
21- spin_lock_irqsave(&musb->lock, flags);
22 if (tx_ch->tx_complete) {
23 /* Sometimes a EP can unregister from a DMA
24 * channel while the data is still in the FIFO.
25@@ -1384,10 +1383,12 @@ void txdma_completion_work(struct work_struct *data)
26 tx_ch->channel.status =
27 MUSB_DMA_STATUS_FREE;
28 tx_ch->tx_complete = 0;
29+ spin_lock_irqsave(&musb->lock, flags);
30 musb_dma_completion(musb, index+1, 1);
31+ spin_unlock_irqrestore(&musb->lock,
32+ flags);
33 }
34 }
35- spin_unlock_irqrestore(&musb->lock, flags);
36
37 if (!resched)
38 cond_resched();
39--
401.7.7.6
41
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0017-usb-musb-host-Flush-RxFIFO-only-when-RxPktRdy-is-set.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0017-usb-musb-host-Flush-RxFIFO-only-when-RxPktRdy-is-set.patch
new file mode 100644
index 00000000..c2912070
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0017-usb-musb-host-Flush-RxFIFO-only-when-RxPktRdy-is-set.patch
@@ -0,0 +1,30 @@
1From c336629a155593e443ba21a0734b3c519a61e560 Mon Sep 17 00:00:00 2001
2From: Ajay Kumar Gupta <ajay.gupta@ti.com>
3Date: Thu, 24 May 2012 16:31:27 +0530
4Subject: [PATCH 17/18] usb: musb: host: Flush RxFIFO only when RxPktRdy is
5 set
6
7This need to be done as per mentor core documentations.
8
9Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
10---
11 drivers/usb/musb/musb_host.c | 3 ++-
12 1 files changed, 2 insertions(+), 1 deletions(-)
13
14diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
15index 13520ee..f56fde2 100644
16--- a/drivers/usb/musb/musb_host.c
17+++ b/drivers/usb/musb/musb_host.c
18@@ -507,7 +507,8 @@ static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
19 * ignore dma (various models),
20 * leave toggle alone (may not have been saved yet)
21 */
22- csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
23+ if (csr & MUSB_RXCSR_RXPKTRDY)
24+ csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
25 csr &= ~(MUSB_RXCSR_H_REQPKT
26 | MUSB_RXCSR_H_AUTOREQ
27 | MUSB_RXCSR_AUTOCLEAR);
28--
291.7.7.6
30
diff --git a/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0018-usb-musb-ti81xx-fix-role-switching-issue.patch b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0018-usb-musb-ti81xx-fix-role-switching-issue.patch
new file mode 100644
index 00000000..d923f08a
--- /dev/null
+++ b/recipes-kernel/linux/linux-ti33x-psp-3.2/psp/0018-usb-musb-ti81xx-fix-role-switching-issue.patch
@@ -0,0 +1,65 @@
1From f2ddff7377332c9e18878aaa84456d01fcf1d39e Mon Sep 17 00:00:00 2001
2From: Ajay Kumar Gupta <ajay.gupta@ti.com>
3Date: Fri, 25 May 2012 11:59:20 +0530
4Subject: [PATCH 18/18] usb: musb: ti81xx: fix role switching issue
5
6Fixing the role switching issue seen when followed steps below:
7
8a) Configure port in OTG mode
9b) Connect MSC device through micro-A-plug to std-A-receptacle
10c) MSC enumerated and works fine.
11d) Disconnect MSC device and let cable be connected to port
12e) Now disconnect cable also
13f) Connect port to host PC using micro-B plug to std-A plug.
14e) PC doesn't recognise the gadget driver.
15---
16 drivers/usb/musb/ti81xx.c | 26 +++++++++++++++++++++-----
17 1 files changed, 21 insertions(+), 5 deletions(-)
18
19diff --git a/drivers/usb/musb/ti81xx.c b/drivers/usb/musb/ti81xx.c
20index 7e21c25..6b0eb9e 100644
21--- a/drivers/usb/musb/ti81xx.c
22+++ b/drivers/usb/musb/ti81xx.c
23@@ -708,6 +708,12 @@ static void otg_timer(unsigned long _musb)
24 devctl = musb_readb(mregs, MUSB_DEVCTL);
25 if (devctl & MUSB_DEVCTL_HM) {
26 musb->xceiv->state = OTG_STATE_A_IDLE;
27+ } else if ((devctl & MUSB_DEVCTL_SESSION) &&
28+ !(devctl & MUSB_DEVCTL_BDEVICE)) {
29+ mod_timer(&musb->otg_workaround,
30+ jiffies + POLL_SECONDS * HZ);
31+ musb_writeb(musb->mregs, MUSB_DEVCTL, devctl &
32+ ~MUSB_DEVCTL_SESSION);
33 } else {
34 mod_timer(&musb->otg_workaround,
35 jiffies + POLL_SECONDS * HZ);
36@@ -976,11 +982,21 @@ static irqreturn_t ti81xx_interrupt(int irq, void *hci)
37 jiffies + POLL_SECONDS * HZ);
38 WARNING("VBUS error workaround (delay coming)\n");
39 } else if (is_host_enabled(musb) && drvvbus) {
40- musb->is_active = 1;
41- MUSB_HST_MODE(musb);
42- musb->xceiv->default_a = 1;
43- musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
44- del_timer(&musb->otg_workaround);
45+ if ((devctl & MUSB_DEVCTL_SESSION) &&
46+ !(devctl & MUSB_DEVCTL_BDEVICE) &&
47+ !(devctl & MUSB_DEVCTL_HM)) {
48+ dev_dbg(musb->controller,
49+ "Only micro-A plug is connected\n");
50+ } else {
51+ if (musb->is_active)
52+ del_timer(&musb->otg_workaround);
53+ else
54+ musb->is_active = 1;
55+
56+ MUSB_HST_MODE(musb);
57+ musb->xceiv->default_a = 1;
58+ musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
59+ }
60 } else {
61 musb->is_active = 0;
62 MUSB_DEV_MODE(musb);
63--
641.7.7.6
65
diff --git a/recipes-kernel/linux/linux-ti33x-psp_3.2.bb b/recipes-kernel/linux/linux-ti33x-psp_3.2.bb
index f279b24a..e51de2af 100644
--- a/recipes-kernel/linux/linux-ti33x-psp_3.2.bb
+++ b/recipes-kernel/linux/linux-ti33x-psp_3.2.bb
@@ -15,7 +15,7 @@ PV = "${@base_contains('DISTRO_FEATURES', 'tipspkernel', "3.2", "3.2.18", d)}"
15 15
16BRANCH = "v3.2-staging" 16BRANCH = "v3.2-staging"
17SRCREV = "720e07b4c1f687b61b147b31c698cb6816d72f01" 17SRCREV = "720e07b4c1f687b61b147b31c698cb6816d72f01"
18MACHINE_KERNEL_PR_append = "g+gitr${SRCREV}" 18MACHINE_KERNEL_PR_append = "h+gitr${SRCREV}"
19 19
20COMPATIBLE_MACHINE = "(ti33x)" 20COMPATIBLE_MACHINE = "(ti33x)"
21 21
@@ -38,6 +38,24 @@ PATCHES_OVER_PSP = " \
38 file://usb/0004-usb-gadget-udc-core-fix-asymmetric-calls-in-remove_d.patch \ 38 file://usb/0004-usb-gadget-udc-core-fix-asymmetric-calls-in-remove_d.patch \
39 file://usb/0005-usb-gadget-udc-core-fix-wrong-call-order.patch \ 39 file://usb/0005-usb-gadget-udc-core-fix-wrong-call-order.patch \
40 file://usb/0006-usb-gadget-udc-core-fix-incompatibility-with-dummy-h.patch \ 40 file://usb/0006-usb-gadget-udc-core-fix-incompatibility-with-dummy-h.patch \
41 file://psp/0001-ARM-OMAP-AM33XX-Add-missing-EMIF-register-offsets.patch \
42 file://psp/0002-ARM-OMAP-AM33XX-PM-Get-rid-of-hardcoded-resume-addre.patch \
43 file://psp/0003-ARM-OMAP-AM33XX-PM-Skip-DDR-PHY-reconfiguration-in-r.patch \
44 file://psp/0004-ARM-OMAP-AM33XX-PM-Save-and-restore-EMIF-registers.patch \
45 file://psp/0005-ARM-OMAP-AM33XX-PM-Wait-correctly-for-the-PLLs-to-re.patch \
46 file://psp/0006-ARM-OMAP-AM33XX-PM-Restore-the-PLLs-to-pre-suspend-s.patch \
47 file://psp/0007-ARM-OMAP-PM-AM33XX-Update-the-sleep-code-to-handle-D.patch \
48 file://psp/0008-usb-musb-update-babble-workaround-fix.patch \
49 file://psp/0009-usb-musb-ti81xx-print-the-usbss-revision-id-during-i.patch \
50 file://psp/0010-usb-musb-cppi41-enable-txfifo-empty-interrupt-logic.patch \
51 file://psp/0011-usb-musb-host-Flush-txfifo-only-if-TxPktRdy-bit-set.patch \
52 file://psp/0012-usb-musb-cppi41-use-dsb-to-make-sure-PDs-are-updated.patch \
53 file://psp/0013-usb-musb-cppi41-fix-zero-byte-OUT-issue.patch \
54 file://psp/0014-usb-musb-host-fix-for-urb-error-handling.patch \
55 file://psp/0015-usb-musb-cppi41-txdma-flushfifo-fixes-during-channel.patch \
56 file://psp/0016-usb-musb-cppi41-tx-dma-completion-fixes.patch \
57 file://psp/0017-usb-musb-host-Flush-RxFIFO-only-when-RxPktRdy-is-set.patch \
58 file://psp/0018-usb-musb-ti81xx-fix-role-switching-issue.patch \
41 file://3.2.1/0001-MAINTAINERS-stable-Update-address.patch \ 59 file://3.2.1/0001-MAINTAINERS-stable-Update-address.patch \
42 file://3.2.1/0002-Documentation-Update-stable-address.patch \ 60 file://3.2.1/0002-Documentation-Update-stable-address.patch \
43 file://3.2.1/0003-firmware-Fix-an-oops-on-reading-fw_priv-fw-in-sysfs-.patch \ 61 file://3.2.1/0003-firmware-Fix-an-oops-on-reading-fw_priv-fw-in-sysfs-.patch \
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-28 15:37:13 +0000