diff options
Diffstat (limited to 'toolchain-layer/recipes-devtools/gcc')
242 files changed, 0 insertions, 122182 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5.inc b/toolchain-layer/recipes-devtools/gcc/gcc-4.5.inc deleted file mode 100644 index 8fabf3044..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5.inc +++ /dev/null | |||
| @@ -1,274 +0,0 @@ | |||
| 1 | require recipes-devtools/gcc/gcc-common.inc | ||
| 2 | ARM_INSTRUCTION_SET = "arm" | ||
| 3 | |||
| 4 | DEPENDS =+ "mpfr gmp libmpc elfutils" | ||
| 5 | NATIVEDEPS = "mpfr-native gmp-native gettext-native libmpc-native elfutils-native" | ||
| 6 | |||
| 7 | LICENSE="GPL-3.0-with-GCC-exception & GPLv2 & GPLv3 & LGPLv2.1 & LGPLv3" | ||
| 8 | |||
| 9 | LIC_FILES_CHKSUM = "file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \ | ||
| 10 | file://COPYING3;md5=d32239bcb673463ab874e80d47fae504 \ | ||
| 11 | file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6 \ | ||
| 12 | file://COPYING.LIB;md5=2d5025d4aa3495befef8f17206a5b0a1 \ | ||
| 13 | file://COPYING.RUNTIME;md5=fe60d87048567d4fe8c8a0ed2448bcc8" | ||
| 14 | |||
| 15 | |||
| 16 | PV = "4.5" | ||
| 17 | PR = "r49" | ||
| 18 | |||
| 19 | # BINV should be incremented after updating to a revision | ||
| 20 | # after a minor gcc release (e.g. 4.5.1 or 4.5.2) has been made | ||
| 21 | # the value will be minor-release+1 e.g. if minor release was | ||
| 22 | # 4.5.1 then the value below will be 2 which will mean 4.5.2 | ||
| 23 | # which will be next minor release and so on. | ||
| 24 | |||
| 25 | BINV = "${PV}.4" | ||
| 26 | SRCREV = "184907" | ||
| 27 | BRANCH = "gcc-4_5-branch" | ||
| 28 | PR_append = "+svnr${SRCPV}" | ||
| 29 | |||
| 30 | SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \ | ||
| 31 | file://gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch \ | ||
| 32 | file://100-uclibc-conf.patch \ | ||
| 33 | file://gcc-uclibc-locale-ctype_touplow_t.patch \ | ||
| 34 | file://cache-amnesia.patch \ | ||
| 35 | file://gcc-flags-for-build.patch \ | ||
| 36 | file://libstdc++-emit-__cxa_end_cleanup-in-text.patch \ | ||
| 37 | file://Makefile.in.patch \ | ||
| 38 | file://gcc-armv4-pass-fix-v4bx-to-ld.patch \ | ||
| 39 | file://sh4-multilib.patch \ | ||
| 40 | file://arm-lib1funcs.as-fix-mismatch-between-conditions-of-an-IT-block.patch \ | ||
| 41 | file://cpp-honour-sysroot.patch \ | ||
| 42 | \ | ||
| 43 | file://linaro/gcc-4.5-linaro-r99297.patch \ | ||
| 44 | file://linaro/gcc-4.5-linaro-r99298.patch \ | ||
| 45 | file://linaro/gcc-4.5-linaro-r99299.patch \ | ||
| 46 | file://linaro/gcc-4.5-linaro-r99300.patch \ | ||
| 47 | file://linaro/gcc-4.5-linaro-r99301.patch \ | ||
| 48 | file://linaro/gcc-4.5-linaro-r99302.patch \ | ||
| 49 | file://linaro/gcc-4.5-linaro-r99303.patch \ | ||
| 50 | file://linaro/gcc-4.5-linaro-r99304.patch \ | ||
| 51 | file://linaro/gcc-4.5-linaro-r99305.patch \ | ||
| 52 | file://linaro/gcc-4.5-linaro-r99306.patch \ | ||
| 53 | file://linaro/gcc-4.5-linaro-r99307.patch \ | ||
| 54 | file://linaro/gcc-4.5-linaro-r99308.patch \ | ||
| 55 | file://linaro/gcc-4.5-linaro-r99310.patch \ | ||
| 56 | file://linaro/gcc-4.5-linaro-r99312.patch \ | ||
| 57 | file://linaro/gcc-4.5-linaro-r99313.patch \ | ||
| 58 | file://linaro/gcc-4.5-linaro-r99314.patch \ | ||
| 59 | file://linaro/gcc-4.5-linaro-r99315.patch \ | ||
| 60 | file://linaro/gcc-4.5-linaro-r99316.patch \ | ||
| 61 | file://linaro/gcc-4.5-linaro-r99318.patch \ | ||
| 62 | file://linaro/gcc-4.5-linaro-r99319.patch \ | ||
| 63 | file://linaro/gcc-4.5-linaro-r99320.patch \ | ||
| 64 | file://linaro/gcc-4.5-linaro-r99321.patch \ | ||
| 65 | file://linaro/gcc-4.5-linaro-r99322.patch \ | ||
| 66 | file://linaro/gcc-4.5-linaro-r99323.patch \ | ||
| 67 | file://linaro/gcc-4.5-linaro-r99324.patch \ | ||
| 68 | file://linaro/gcc-4.5-linaro-r99325.patch \ | ||
| 69 | file://linaro/gcc-4.5-linaro-r99326.patch \ | ||
| 70 | file://linaro/gcc-4.5-linaro-r99327.patch \ | ||
| 71 | file://linaro/gcc-4.5-linaro-r99332.patch \ | ||
| 72 | file://linaro/gcc-4.5-linaro-r99335.patch \ | ||
| 73 | file://linaro/gcc-4.5-linaro-r99336.patch \ | ||
| 74 | file://linaro/gcc-4.5-linaro-r99337.patch \ | ||
| 75 | file://linaro/gcc-4.5-linaro-r99338.patch \ | ||
| 76 | file://linaro/gcc-4.5-linaro-r99339.patch \ | ||
| 77 | file://linaro/gcc-4.5-linaro-r99340.patch \ | ||
| 78 | file://linaro/gcc-4.5-linaro-r99341.patch \ | ||
| 79 | file://linaro/gcc-4.5-linaro-r99342.patch \ | ||
| 80 | file://linaro/gcc-4.5-linaro-r99343.patch \ | ||
| 81 | file://linaro/gcc-4.5-linaro-r99344.patch \ | ||
| 82 | file://linaro/gcc-4.5-linaro-r99345.patch \ | ||
| 83 | file://linaro/gcc-4.5-linaro-r99346.patch \ | ||
| 84 | file://linaro/gcc-4.5-linaro-r99348.patch \ | ||
| 85 | file://linaro/gcc-4.5-linaro-r99349.patch \ | ||
| 86 | file://linaro/gcc-4.5-linaro-r99351.patch \ | ||
| 87 | file://linaro/gcc-4.5-linaro-r99352.patch \ | ||
| 88 | file://linaro/gcc-4.5-linaro-r99353.patch \ | ||
| 89 | file://linaro/gcc-4.5-linaro-r99354.patch \ | ||
| 90 | file://linaro/gcc-4.5-linaro-r99355.patch \ | ||
| 91 | file://linaro/gcc-4.5-linaro-r99356.patch \ | ||
| 92 | file://linaro/gcc-4.5-linaro-r99357.patch \ | ||
| 93 | file://linaro/gcc-4.5-linaro-r99358.patch \ | ||
| 94 | file://linaro/gcc-4.5-linaro-r99359.patch \ | ||
| 95 | file://linaro/gcc-4.5-linaro-r99360.patch \ | ||
| 96 | file://linaro/gcc-4.5-linaro-r99361.patch \ | ||
| 97 | file://linaro/gcc-4.5-linaro-r99363.patch \ | ||
| 98 | file://linaro/gcc-4.5-linaro-r99364.patch \ | ||
| 99 | file://linaro/gcc-4.5-linaro-r99365.patch \ | ||
| 100 | file://linaro/gcc-4.5-linaro-r99366.patch \ | ||
| 101 | file://linaro/gcc-4.5-linaro-r99367.patch \ | ||
| 102 | file://linaro/gcc-4.5-linaro-r99368.patch \ | ||
| 103 | file://linaro/gcc-4.5-linaro-r99369.patch \ | ||
| 104 | file://linaro/gcc-4.5-linaro-r99371.patch \ | ||
| 105 | file://linaro/gcc-4.5-linaro-r99372.patch \ | ||
| 106 | file://linaro/gcc-4.5-linaro-r99373.patch \ | ||
| 107 | file://linaro/gcc-4.5-linaro-r99374.patch \ | ||
| 108 | file://linaro/gcc-4.5-linaro-r99375.patch \ | ||
| 109 | file://linaro/gcc-4.5-linaro-r99376.patch \ | ||
| 110 | file://linaro/gcc-4.5-linaro-r99377.patch \ | ||
| 111 | file://linaro/gcc-4.5-linaro-r99378.patch \ | ||
| 112 | file://linaro/gcc-4.5-linaro-r99379.patch \ | ||
| 113 | file://linaro/gcc-4.5-linaro-r99380.patch \ | ||
| 114 | file://linaro/gcc-4.5-linaro-r99381.patch \ | ||
| 115 | file://linaro/gcc-4.5-linaro-r99383.patch \ | ||
| 116 | file://linaro/gcc-4.5-linaro-r99384.patch \ | ||
| 117 | file://linaro/gcc-4.5-linaro-r99385.patch \ | ||
| 118 | file://linaro/gcc-4.5-linaro-r99388.patch \ | ||
| 119 | file://linaro/gcc-4.5-linaro-r99391.patch \ | ||
| 120 | file://linaro/gcc-4.5-linaro-r99392.patch \ | ||
| 121 | file://linaro/gcc-4.5-linaro-r99393.patch \ | ||
| 122 | file://linaro/gcc-4.5-linaro-r99395.patch \ | ||
| 123 | file://linaro/gcc-4.5-linaro-r99396.patch \ | ||
| 124 | file://linaro/gcc-4.5-linaro-r99397.patch \ | ||
| 125 | file://linaro/gcc-4.5-linaro-r99398.patch \ | ||
| 126 | file://linaro/gcc-4.5-linaro-r99402.patch \ | ||
| 127 | file://linaro/gcc-4.5-linaro-r99403.patch \ | ||
| 128 | file://linaro/gcc-4.5-linaro-r99404.patch \ | ||
| 129 | file://linaro/gcc-4.5-linaro-r99405.patch \ | ||
| 130 | file://linaro/gcc-4.5-linaro-r99406.patch \ | ||
| 131 | file://linaro/gcc-4.5-linaro-r99407.patch \ | ||
| 132 | file://linaro/gcc-4.5-linaro-r99408.patch \ | ||
| 133 | file://linaro/gcc-4.5-linaro-r99409.patch \ | ||
| 134 | file://linaro/gcc-4.5-linaro-r99410.patch \ | ||
| 135 | file://linaro/gcc-4.5-linaro-r99411.patch \ | ||
| 136 | file://linaro/gcc-4.5-linaro-r99412.patch \ | ||
| 137 | file://linaro/gcc-4.5-linaro-r99413.patch \ | ||
| 138 | file://linaro/gcc-4.5-linaro-r99415.patch \ | ||
| 139 | file://linaro/gcc-4.5-linaro-r99416.patch \ | ||
| 140 | file://linaro/gcc-4.5-linaro-r99417.patch \ | ||
| 141 | file://linaro/gcc-4.5-linaro-r99418.patch \ | ||
| 142 | file://linaro/gcc-4.5-linaro-r99419.patch \ | ||
| 143 | file://linaro/gcc-4.5-linaro-r99420.patch \ | ||
| 144 | file://linaro/gcc-4.5-linaro-r99421.patch \ | ||
| 145 | file://linaro/gcc-4.5-linaro-r99423.patch \ | ||
| 146 | file://linaro/gcc-4.5-linaro-r99424.patch \ | ||
| 147 | file://linaro/gcc-4.5-linaro-r99425.patch \ | ||
| 148 | file://linaro/gcc-4.5-linaro-r99426.patch \ | ||
| 149 | file://linaro/gcc-4.5-linaro-r99429.patch \ | ||
| 150 | file://linaro/gcc-4.5-linaro-r99432.patch \ | ||
| 151 | file://linaro/gcc-4.5-linaro-r99433.patch \ | ||
| 152 | file://linaro/gcc-4.5-linaro-r99434.patch \ | ||
| 153 | file://linaro/gcc-4.5-linaro-r99435.patch \ | ||
| 154 | file://linaro/gcc-4.5-linaro-r99436.patch \ | ||
| 155 | file://linaro/gcc-4.5-linaro-r99437.patch \ | ||
| 156 | file://linaro/gcc-4.5-linaro-r99439.patch \ | ||
| 157 | file://linaro/gcc-4.5-linaro-r99440.patch \ | ||
| 158 | file://linaro/gcc-4.5-linaro-r99441.patch \ | ||
| 159 | file://linaro/gcc-4.5-linaro-r99442.patch \ | ||
| 160 | file://linaro/gcc-4.5-linaro-r99443.patch \ | ||
| 161 | file://linaro/gcc-4.5-linaro-r99444.patch \ | ||
| 162 | file://linaro/gcc-4.5-linaro-r99449.patch \ | ||
| 163 | file://linaro/gcc-4.5-linaro-r99450.patch \ | ||
| 164 | file://linaro/gcc-4.5-linaro-r99451.patch \ | ||
| 165 | file://linaro/gcc-4.5-linaro-r99452.patch \ | ||
| 166 | file://linaro/gcc-4.5-linaro-r99453.patch \ | ||
| 167 | file://linaro/gcc-4.5-linaro-r99454.patch \ | ||
| 168 | file://linaro/gcc-4.5-linaro-r99455.patch \ | ||
| 169 | file://linaro/gcc-4.5-linaro-r99464.patch \ | ||
| 170 | file://linaro/gcc-4.5-linaro-r99465.patch \ | ||
| 171 | file://linaro/gcc-4.5-linaro-r99466.patch \ | ||
| 172 | file://linaro/gcc-4.5-linaro-r99468.patch \ | ||
| 173 | file://linaro/gcc-4.5-linaro-r99473.patch \ | ||
| 174 | file://linaro/gcc-4.5-linaro-r99475.patch \ | ||
| 175 | file://linaro/gcc-4.5-linaro-r99478.patch \ | ||
| 176 | file://linaro/gcc-4.5-linaro-r99479.patch \ | ||
| 177 | file://linaro/gcc-4.5-linaro-r99480.patch \ | ||
| 178 | file://linaro/gcc-4.5-linaro-r99483.patch \ | ||
| 179 | file://linaro/gcc-4.5-linaro-r99488.patch \ | ||
| 180 | file://linaro/gcc-4.5-linaro-r99489.patch \ | ||
| 181 | file://linaro/gcc-4.5-linaro-r99494.patch \ | ||
| 182 | file://linaro/gcc-4.5-linaro-r99495.patch \ | ||
| 183 | file://linaro/gcc-4.5-linaro-r99498.patch \ | ||
| 184 | file://linaro/gcc-4.5-linaro-r99502.patch \ | ||
| 185 | file://linaro/gcc-4.5-linaro-r99503.patch \ | ||
| 186 | file://linaro/gcc-4.5-linaro-r99504.patch \ | ||
| 187 | file://linaro/gcc-4.5-linaro-r99506.patch \ | ||
| 188 | file://linaro/gcc-4.5-linaro-r99507.patch \ | ||
| 189 | file://linaro/gcc-4.5-linaro-r99510.patch \ | ||
| 190 | file://linaro/gcc-4.5-linaro-r99511.patch \ | ||
| 191 | file://linaro/gcc-4.5-linaro-r99514.patch \ | ||
| 192 | file://linaro/gcc-4.5-linaro-r99516.patch \ | ||
| 193 | file://linaro/gcc-4.5-linaro-r99519.patch \ | ||
| 194 | file://linaro/gcc-4.5-linaro-r99521.patch \ | ||
| 195 | file://linaro/gcc-4.5-linaro-r99522.patch \ | ||
| 196 | file://linaro/gcc-4.5-linaro-r99523.patch \ | ||
| 197 | file://linaro/gcc-4.5-linaro-r99524.patch \ | ||
| 198 | file://linaro/gcc-4.5-linaro-r99525.patch \ | ||
| 199 | file://linaro/gcc-4.5-linaro-r99528.patch \ | ||
| 200 | file://linaro/gcc-4.5-linaro-r99529.patch \ | ||
| 201 | file://linaro/gcc-4.5-linaro-r99530.patch \ | ||
| 202 | file://linaro/gcc-4.5-linaro-r99531.patch \ | ||
| 203 | file://linaro/gcc-4.5-linaro-r99532.patch \ | ||
| 204 | file://linaro/gcc-4.5-linaro-r99533.patch \ | ||
| 205 | file://linaro/gcc-4.5-linaro-r99534.patch \ | ||
| 206 | file://linaro/gcc-4.5-linaro-r99536.patch \ | ||
| 207 | file://linaro/gcc-4.5-linaro-r99537.patch \ | ||
| 208 | file://linaro/gcc-4.5-linaro-r99540.patch \ | ||
| 209 | file://linaro/gcc-4.5-linaro-r99548.patch \ | ||
| 210 | file://linaro/gcc-4.5-linaro-r99549.patch \ | ||
| 211 | \ | ||
| 212 | file://more-epilogues.patch \ | ||
| 213 | file://gcc-scalar-widening-pr45847.patch \ | ||
| 214 | file://gcc-arm-volatile-bitfield-fix.patch \ | ||
| 215 | \ | ||
| 216 | file://fedora/gcc43-c++-builtin-redecl.patch;striplevel=0 \ | ||
| 217 | file://fedora/gcc43-ia64-libunwind.patch;striplevel=0 \ | ||
| 218 | file://fedora/gcc43-java-nomulti.patch;striplevel=0 \ | ||
| 219 | file://fedora/gcc43-ppc32-retaddr.patch;striplevel=0 \ | ||
| 220 | file://fedora/gcc43-pr32139.patch;striplevel=0 \ | ||
| 221 | file://fedora/gcc43-pr33763.patch;striplevel=0 \ | ||
| 222 | file://fedora/gcc43-rh330771.patch;striplevel=0 \ | ||
| 223 | file://fedora/gcc43-rh341221.patch;striplevel=0 \ | ||
| 224 | file://fedora/gcc43-java-debug-iface-type.patch;striplevel=0 \ | ||
| 225 | file://fedora/gcc43-i386-libgomp.patch;striplevel=0 \ | ||
| 226 | file://fedora/gcc45-no-add-needed.patch;striplevel=0 \ | ||
| 227 | file://optional_libstdc.patch \ | ||
| 228 | file://64bithack.patch \ | ||
| 229 | file://COLLECT_GCC_OPTIONS.patch \ | ||
| 230 | file://gcc-poison-dir-extend.patch \ | ||
| 231 | file://gcc-poison-parameters.patch \ | ||
| 232 | file://gcc-ppc-config-fix.patch \ | ||
| 233 | file://use-defaults.h-and-t-oe-in-B.patch \ | ||
| 234 | file://gcc-with-linker-hash-style.patch \ | ||
| 235 | file://GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch \ | ||
| 236 | \ | ||
| 237 | file://fortran-cross-compile-hack.patch \ | ||
| 238 | " | ||
| 239 | |||
| 240 | # Language Overrides | ||
| 241 | FORTRAN = "" | ||
| 242 | JAVA = "" | ||
| 243 | |||
| 244 | S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/${BRANCH}" | ||
| 245 | B = "${WORKDIR}/${BRANCH}/build.${HOST_SYS}.${TARGET_SYS}" | ||
| 246 | |||
| 247 | #EXTRA_OECONF_BASE = " --enable-cheaders=c_std \ | ||
| 248 | # --enable-libssp \ | ||
| 249 | # --disable-bootstrap \ | ||
| 250 | # --disable-libgomp \ | ||
| 251 | # --disable-libmudflap" | ||
| 252 | EXTRA_OECONF_BASE = "--enable-lto \ | ||
| 253 | --enable-libssp \ | ||
| 254 | --disable-bootstrap \ | ||
| 255 | --disable-libgomp \ | ||
| 256 | --disable-libmudflap \ | ||
| 257 | --with-linker-hash-style=${LINKER_HASH_STYLE} \ | ||
| 258 | --with-ppl=no \ | ||
| 259 | --with-cloog=no \ | ||
| 260 | --enable-cheaders=c_global " | ||
| 261 | |||
| 262 | EXTRA_OECONF_INITIAL = "--disable-libmudflap \ | ||
| 263 | --disable-libgomp \ | ||
| 264 | --disable-libssp \ | ||
| 265 | --enable-decimal-float=no" | ||
| 266 | |||
| 267 | EXTRA_OECONF_INTERMEDIATE = "--disable-libmudflap \ | ||
| 268 | --disable-libgomp \ | ||
| 269 | --disable-libssp" | ||
| 270 | |||
| 271 | EXTRA_OECONF_append_libc-uclibc = " --disable-decimal-float " | ||
| 272 | EXTRA_OECONF_append_mips64 = " --with-arch-64=mips64 --with-tune-64=mips64" | ||
| 273 | EXTRA_OECONF_append_mips64el = " --with-arch-64=mips64 --with-tune-64=mips64" | ||
| 274 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/100-uclibc-conf.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/100-uclibc-conf.patch deleted file mode 100644 index 0b799607e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/100-uclibc-conf.patch +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | Index: gcc-4.3.1/contrib/regression/objs-gcc.sh | ||
| 2 | =================================================================== | ||
| 3 | --- gcc-4.3.1.orig/contrib/regression/objs-gcc.sh 2007-12-24 15:18:57.000000000 -0800 | ||
| 4 | +++ gcc-4.3.1/contrib/regression/objs-gcc.sh 2008-08-16 01:15:12.000000000 -0700 | ||
| 5 | @@ -105,6 +105,10 @@ | ||
| 6 | then | ||
| 7 | make all-gdb all-dejagnu all-ld || exit 1 | ||
| 8 | make install-gdb install-dejagnu install-ld || exit 1 | ||
| 9 | +elif [ $H_REAL_TARGET = $H_REAL_HOST -a $H_REAL_TARGET = i686-pc-linux-uclibc ] | ||
| 10 | + then | ||
| 11 | + make all-gdb all-dejagnu all-ld || exit 1 | ||
| 12 | + make install-gdb install-dejagnu install-ld || exit 1 | ||
| 13 | elif [ $H_REAL_TARGET = $H_REAL_HOST ] ; then | ||
| 14 | make bootstrap || exit 1 | ||
| 15 | make install || exit 1 | ||
| 16 | Index: gcc-4.3.1/libjava/classpath/ltconfig | ||
| 17 | =================================================================== | ||
| 18 | --- gcc-4.3.1.orig/libjava/classpath/ltconfig 2007-06-03 16:18:43.000000000 -0700 | ||
| 19 | +++ gcc-4.3.1/libjava/classpath/ltconfig 2008-08-16 01:15:12.000000000 -0700 | ||
| 20 | @@ -603,7 +603,7 @@ | ||
| 21 | |||
| 22 | # Transform linux* to *-*-linux-gnu*, to support old configure scripts. | ||
| 23 | case $host_os in | ||
| 24 | -linux-gnu*) ;; | ||
| 25 | +linux-gnu*|linux-uclibc*) ;; | ||
| 26 | linux*) host=`echo $host | sed 's/^\(.*-.*-linux\)\(.*\)$/\1-gnu\2/'` | ||
| 27 | esac | ||
| 28 | |||
| 29 | @@ -1251,7 +1251,7 @@ | ||
| 30 | ;; | ||
| 31 | |||
| 32 | # This must be Linux ELF. | ||
| 33 | -linux-gnu*) | ||
| 34 | +linux*) | ||
| 35 | version_type=linux | ||
| 36 | need_lib_prefix=no | ||
| 37 | need_version=no | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/602-sdk-libstdc++-includes.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/602-sdk-libstdc++-includes.patch deleted file mode 100644 index 23fce7544..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/602-sdk-libstdc++-includes.patch +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | --- gcc-4.1.0/libstdc++-v3/fragment.am 2005-03-21 11:40:14.000000000 -0600 | ||
| 2 | +++ gcc-4.1.0-patched/libstdc++-v3/fragment.am 2005-04-25 20:14:39.856251785 -0500 | ||
| 3 | @@ -21,5 +21,5 @@ | ||
| 4 | $(WARN_FLAGS) $(WERROR) -fdiagnostics-show-location=once | ||
| 5 | |||
| 6 | # -I/-D flags to pass when compiling. | ||
| 7 | -AM_CPPFLAGS = $(GLIBCXX_INCLUDES) | ||
| 8 | +AM_CPPFLAGS = $(GLIBCXX_INCLUDES) -I$(toplevel_srcdir)/include | ||
| 9 | |||
| 10 | --- gcc-4.1.0/libstdc++-v3/libmath/Makefile.am 2005-03-21 11:40:18.000000000 -0600 | ||
| 11 | +++ gcc-4.1.0-patched/libstdc++-v3/libmath/Makefile.am 2005-04-25 20:14:39.682280735 -0500 | ||
| 12 | @@ -35,7 +35,7 @@ | ||
| 13 | |||
| 14 | libmath_la_SOURCES = stubs.c | ||
| 15 | |||
| 16 | -AM_CPPFLAGS = $(CANADIAN_INCLUDES) | ||
| 17 | +AM_CPPFLAGS = $(CANADIAN_INCLUDES) -I$(toplevel_srcdir)/include | ||
| 18 | |||
| 19 | # Only compiling "C" sources in this directory. | ||
| 20 | LIBTOOL = @LIBTOOL@ --tag CC | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/64bithack.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/64bithack.patch deleted file mode 100644 index 70330145e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/64bithack.patch +++ /dev/null | |||
| @@ -1,68 +0,0 @@ | |||
| 1 | Upstream-Status: Inappropriate [embedded specific] | ||
| 2 | |||
| 3 | GCC has internal multilib handling code but it assumes a very specific rigid directory | ||
| 4 | layout. The build system implementation of multilib layout is very generic and allows | ||
| 5 | complete customisation of the library directories. | ||
| 6 | |||
| 7 | This patch is a partial solution to allow any custom directories to be passed into gcc | ||
| 8 | and handled correctly. It forces gcc to use the base_libdir (which is the current | ||
| 9 | directory, "."). We need to do this for each multilib that is configured as we don't | ||
| 10 | know which compiler options may be being passed into the compiler. Since we have a compiler | ||
| 11 | per mulitlib at this point that isn't an issue. | ||
| 12 | |||
| 13 | The one problem is the target compiler is only going to work for the default multlilib at | ||
| 14 | this point. Ideally we'd figure out which multilibs were being enabled with which paths | ||
| 15 | and be able to patch these entries with a complete set of correct paths but this we | ||
| 16 | don't have such code at this point. This is something the target gcc recipe should do | ||
| 17 | and override these platform defaults in its build config. | ||
| 18 | |||
| 19 | RP 15/8/11 | ||
| 20 | |||
| 21 | Index: gcc-4_5-branch/gcc/config/i386/t-linux64 | ||
| 22 | =================================================================== | ||
| 23 | --- gcc-4_5-branch.orig/gcc/config/i386/t-linux64 2011-09-22 11:37:51.188913390 -0700 | ||
| 24 | +++ gcc-4_5-branch/gcc/config/i386/t-linux64 2011-09-22 11:37:56.818913303 -0700 | ||
| 25 | @@ -24,8 +24,8 @@ | ||
| 26 | # MULTILIB_OSDIRNAMES according to what is found on the target. | ||
| 27 | |||
| 28 | MULTILIB_OPTIONS = m64/m32 | ||
| 29 | -MULTILIB_DIRNAMES = 64 32 | ||
| 30 | -MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) | ||
| 31 | +MULTILIB_DIRNAMES = . . | ||
| 32 | +MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) | ||
| 33 | |||
| 34 | LIBGCC = stmp-multilib | ||
| 35 | INSTALL_LIBGCC = install-multilib | ||
| 36 | Index: gcc-4_5-branch/gcc/config/mips/t-linux64 | ||
| 37 | =================================================================== | ||
| 38 | --- gcc-4_5-branch.orig/gcc/config/mips/t-linux64 2011-06-16 17:59:02.000000000 -0700 | ||
| 39 | +++ gcc-4_5-branch/gcc/config/mips/t-linux64 2011-09-22 11:37:56.838913302 -0700 | ||
| 40 | @@ -17,8 +17,8 @@ | ||
| 41 | # <http://www.gnu.org/licenses/>. | ||
| 42 | |||
| 43 | MULTILIB_OPTIONS = mabi=n32/mabi=32/mabi=64 | ||
| 44 | -MULTILIB_DIRNAMES = n32 32 64 | ||
| 45 | -MULTILIB_OSDIRNAMES = ../lib32 ../lib ../lib64 | ||
| 46 | +MULTILIB_DIRNAMES = . . . | ||
| 47 | +MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) | ||
| 48 | |||
| 49 | EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o | ||
| 50 | |||
| 51 | Index: gcc-4_5-branch/gcc/config/rs6000/t-linux64 | ||
| 52 | =================================================================== | ||
| 53 | --- gcc-4_5-branch.orig/gcc/config/rs6000/t-linux64 2011-06-16 17:58:58.000000000 -0700 | ||
| 54 | +++ gcc-4_5-branch/gcc/config/rs6000/t-linux64 2011-09-22 11:37:56.838913302 -0700 | ||
| 55 | @@ -32,11 +32,11 @@ TARGET_LIBGCC2_CFLAGS += -mno-minimal-to | ||
| 56 | # MULTILIB_OSDIRNAMES according to what is found on the target. | ||
| 57 | |||
| 58 | MULTILIB_OPTIONS = m64/m32 msoft-float | ||
| 59 | -MULTILIB_DIRNAMES = 64 32 nof | ||
| 60 | +MULTILIB_DIRNAMES = . . . | ||
| 61 | MULTILIB_EXTRA_OPTS = fPIC mstrict-align | ||
| 62 | MULTILIB_EXCEPTIONS = m64/msoft-float | ||
| 63 | MULTILIB_EXCLUSIONS = m64/!m32/msoft-float | ||
| 64 | -MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) nof | ||
| 65 | +MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) | ||
| 66 | MULTILIB_MATCHES = $(MULTILIB_MATCHES_FLOAT) | ||
| 67 | |||
| 68 | softfp_wrap_start := '\#ifndef __powerpc64__' | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/740-sh-pr24836.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/740-sh-pr24836.patch deleted file mode 100644 index d84889259..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/740-sh-pr24836.patch +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | http://sourceforge.net/mailarchive/forum.php?thread_id=8959304&forum_id=5348 | ||
| 2 | http://gcc.gnu.org/bugzilla/show_bug.cgi?id=24836 | ||
| 3 | |||
| 4 | Index: gcc-4.5.0/gcc/configure.ac | ||
| 5 | =================================================================== | ||
| 6 | --- gcc-4.5.0.orig/gcc/configure.ac 2010-03-25 22:40:32.000000000 -0700 | ||
| 7 | +++ gcc-4.5.0/gcc/configure.ac 2010-06-25 11:02:48.489057877 -0700 | ||
| 8 | @@ -2784,7 +2784,7 @@ | ||
| 9 | tls_first_minor=14 | ||
| 10 | tls_as_opt="-m64 -Aesame --fatal-warnings" | ||
| 11 | ;; | ||
| 12 | - sh-*-* | sh[34]-*-*) | ||
| 13 | + sh-*-* | sh[34]*-*-*) | ||
| 14 | conftest_s=' | ||
| 15 | .section ".tdata","awT",@progbits | ||
| 16 | foo: .long 25 | ||
| 17 | Index: gcc-4.5.0/gcc/configure | ||
| 18 | =================================================================== | ||
| 19 | --- gcc-4.5.0.orig/gcc/configure 2010-03-25 22:40:32.000000000 -0700 | ||
| 20 | +++ gcc-4.5.0/gcc/configure 2010-06-25 11:02:48.508381845 -0700 | ||
| 21 | @@ -22156,7 +22156,7 @@ | ||
| 22 | tls_first_minor=14 | ||
| 23 | tls_as_opt="-m64 -Aesame --fatal-warnings" | ||
| 24 | ;; | ||
| 25 | - sh-*-* | sh[34]-*-*) | ||
| 26 | + sh-*-* | sh[34]*-*-*) | ||
| 27 | conftest_s=' | ||
| 28 | .section ".tdata","awT",@progbits | ||
| 29 | foo: .long 25 | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/800-arm-bigendian.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/800-arm-bigendian.patch deleted file mode 100644 index 77d02c3ab..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/800-arm-bigendian.patch +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | By Lennert Buytenhek <buytenh@wantstofly.org> | ||
| 2 | Adds support for arm*b-linux* big-endian ARM targets | ||
| 3 | |||
| 4 | See http://gcc.gnu.org/PR16350 | ||
| 5 | |||
| 6 | Index: gcc-4.5.0/gcc/config/arm/linux-elf.h | ||
| 7 | =================================================================== | ||
| 8 | --- gcc-4.5.0.orig/gcc/config/arm/linux-elf.h 2009-11-05 06:47:45.000000000 -0800 | ||
| 9 | +++ gcc-4.5.0/gcc/config/arm/linux-elf.h 2010-06-25 11:03:06.997132728 -0700 | ||
| 10 | @@ -51,7 +51,7 @@ | ||
| 11 | |||
| 12 | #undef MULTILIB_DEFAULTS | ||
| 13 | #define MULTILIB_DEFAULTS \ | ||
| 14 | - { "marm", "mlittle-endian", "mhard-float", "mno-thumb-interwork" } | ||
| 15 | + { "marm", TARGET_ENDIAN_OPTION, "mhard-float", "mno-thumb-interwork" } | ||
| 16 | |||
| 17 | /* Now we define the strings used to build the spec file. */ | ||
| 18 | #undef LIB_SPEC | ||
| 19 | Index: gcc-4.5.0/gcc/config.gcc | ||
| 20 | =================================================================== | ||
| 21 | --- gcc-4.5.0.orig/gcc/config.gcc 2010-06-25 10:40:33.321880880 -0700 | ||
| 22 | +++ gcc-4.5.0/gcc/config.gcc 2010-06-25 11:03:07.013133525 -0700 | ||
| 23 | @@ -734,6 +734,11 @@ | ||
| 24 | esac | ||
| 25 | tmake_file="${tmake_file} t-linux arm/t-arm" | ||
| 26 | case ${target} in | ||
| 27 | + arm*b-*) | ||
| 28 | + tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1" | ||
| 29 | + ;; | ||
| 30 | + esac | ||
| 31 | + case ${target} in | ||
| 32 | arm*-*-linux-*eabi) | ||
| 33 | tm_file="$tm_file arm/bpabi.h arm/linux-eabi.h" | ||
| 34 | tmake_file="$tmake_file arm/t-arm-elf arm/t-bpabi arm/t-linux-eabi t-slibgcc-libgcc" | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/904-flatten-switch-stmt-00.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/904-flatten-switch-stmt-00.patch deleted file mode 100644 index c4641dc63..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/904-flatten-switch-stmt-00.patch +++ /dev/null | |||
| @@ -1,74 +0,0 @@ | |||
| 1 | Hi, | ||
| 2 | |||
| 3 | The attached patch makes sure that we create smaller object code for | ||
| 4 | simple switch statements. We just make sure to flatten the switch | ||
| 5 | statement into an if-else chain, basically. | ||
| 6 | |||
| 7 | This fixes a size-regression as compared to gcc-3.4, as can be seen | ||
| 8 | below. | ||
| 9 | |||
| 10 | 2007-04-15 Bernhard Fischer <..> | ||
| 11 | |||
| 12 | * stmt.c (expand_case): Do not create a complex binary tree when | ||
| 13 | optimizing for size but rather use the simple ordered list. | ||
| 14 | (emit_case_nodes): do not emit jumps to the default_label when | ||
| 15 | optimizing for size. | ||
| 16 | |||
| 17 | Not regtested so far. | ||
| 18 | Comments? | ||
| 19 | |||
| 20 | Attached is the test switch.c mentioned below. | ||
| 21 | |||
| 22 | $ for i in 2.95 3.3 3.4 4.0 4.1 4.2.orig-HEAD 4.3.orig-HEAD 4.3-HEAD;do | ||
| 23 | gcc-$i -DCHAIN -Os -o switch-CHAIN-$i.o -c switch.c ;done | ||
| 24 | $ for i in 2.95 3.3 3.4 4.0 4.1 4.2.orig-HEAD 4.3.orig-HEAD 4.3-HEAD;do | ||
| 25 | gcc-$i -UCHAIN -Os -o switch-$i.o -c switch.c ;done | ||
| 26 | |||
| 27 | $ size switch-*.o | ||
| 28 | text data bss dec hex filename | ||
| 29 | 169 0 0 169 a9 switch-2.95.o | ||
| 30 | 115 0 0 115 73 switch-3.3.o | ||
| 31 | 103 0 0 103 67 switch-3.4.o | ||
| 32 | 124 0 0 124 7c switch-4.0.o | ||
| 33 | 124 0 0 124 7c switch-4.1.o | ||
| 34 | 124 0 0 124 7c switch-4.2.orig-HEAD.o | ||
| 35 | 95 0 0 95 5f switch-4.3-HEAD.o | ||
| 36 | 124 0 0 124 7c switch-4.3.orig-HEAD.o | ||
| 37 | 166 0 0 166 a6 switch-CHAIN-2.95.o | ||
| 38 | 111 0 0 111 6f switch-CHAIN-3.3.o | ||
| 39 | 95 0 0 95 5f switch-CHAIN-3.4.o | ||
| 40 | 95 0 0 95 5f switch-CHAIN-4.0.o | ||
| 41 | 95 0 0 95 5f switch-CHAIN-4.1.o | ||
| 42 | 95 0 0 95 5f switch-CHAIN-4.2.orig-HEAD.o | ||
| 43 | 95 0 0 95 5f switch-CHAIN-4.3-HEAD.o | ||
| 44 | 95 0 0 95 5f switch-CHAIN-4.3.orig-HEAD.o | ||
| 45 | |||
| 46 | |||
| 47 | Content-Type: text/x-diff; charset=us-ascii | ||
| 48 | Content-Disposition: attachment; filename="gcc-4.3.gcc-flatten-switch-stmt.00.diff" | ||
| 49 | |||
| 50 | Index: gcc-4.5.0/gcc/stmt.c | ||
| 51 | =================================================================== | ||
| 52 | --- gcc-4.5.0.orig/gcc/stmt.c 2010-02-19 01:53:51.000000000 -0800 | ||
| 53 | +++ gcc-4.5.0/gcc/stmt.c 2010-06-25 11:05:31.816881094 -0700 | ||
| 54 | @@ -2440,7 +2440,11 @@ | ||
| 55 | default code is emitted. */ | ||
| 56 | |||
| 57 | use_cost_table = estimate_case_costs (case_list); | ||
| 58 | - balance_case_nodes (&case_list, NULL); | ||
| 59 | + /* When optimizing for size, we want a straight list to avoid | ||
| 60 | + jumps as much as possible. This basically creates an if-else | ||
| 61 | + chain. */ | ||
| 62 | + if (!optimize_size) | ||
| 63 | + balance_case_nodes (&case_list, NULL); | ||
| 64 | emit_case_nodes (index, case_list, default_label, index_type); | ||
| 65 | if (default_label) | ||
| 66 | emit_jump (default_label); | ||
| 67 | @@ -3008,6 +3012,7 @@ | ||
| 68 | { | ||
| 69 | if (!node_has_low_bound (node, index_type)) | ||
| 70 | { | ||
| 71 | + if (!optimize_size) /* don't jl to the .default_label. */ | ||
| 72 | emit_cmp_and_jump_insns (index, | ||
| 73 | convert_modes | ||
| 74 | (mode, imode, | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/COLLECT_GCC_OPTIONS.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/COLLECT_GCC_OPTIONS.patch deleted file mode 100644 index 076e9a614..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/COLLECT_GCC_OPTIONS.patch +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | #This patck added --sysroot into COLLECT_GCC_OPTIONS which is used to | ||
| 2 | #invoke collect2. | ||
| 3 | |||
| 4 | Index: gcc-4_5-branch/gcc/gcc.c | ||
| 5 | =================================================================== | ||
| 6 | --- gcc-4_5-branch.orig/gcc/gcc.c | ||
| 7 | +++ gcc-4_5-branch/gcc/gcc.c | ||
| 8 | @@ -4667,6 +4667,15 @@ set_collect_gcc_options (void) | ||
| 9 | sizeof ("COLLECT_GCC_OPTIONS=") - 1); | ||
| 10 | |||
| 11 | first_time = TRUE; | ||
| 12 | +#ifdef HAVE_LD_SYSROOT | ||
| 13 | + if (target_system_root_changed && target_system_root) | ||
| 14 | + { | ||
| 15 | + obstack_grow (&collect_obstack, "'--sysroot=", sizeof("'--sysroot=")-1); | ||
| 16 | + obstack_grow (&collect_obstack, target_system_root,strlen(target_system_root)); | ||
| 17 | + obstack_grow (&collect_obstack, "'", 1); | ||
| 18 | + first_time = FALSE; | ||
| 19 | + } | ||
| 20 | +#endif | ||
| 21 | for (i = 0; (int) i < n_switches; i++) | ||
| 22 | { | ||
| 23 | const char *const *args; | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch deleted file mode 100644 index 5c7b346ca..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch +++ /dev/null | |||
| @@ -1,178 +0,0 @@ | |||
| 1 | source: http://patchwork.ozlabs.org/patch/129800/ | ||
| 2 | Upstream-Status: Submitted | ||
| 3 | |||
| 4 | ChangeLog | ||
| 5 | * Makefile.in (gcc_gxx_include_dir_add_sysroot): New. | ||
| 6 | (PREPROCESSOR_DEFINES): Define GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT. | ||
| 7 | |||
| 8 | * cppdefault.c (cpp_include_defaults): replace hard coded "1" with | ||
| 9 | GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT for "add_sysroot" field. | ||
| 10 | |||
| 11 | * configure.ac (AC_SUBST): Add gcc_gxx_include_dir_add_sysroot to | ||
| 12 | control whether sysroot should be prepended to gxx include dir. | ||
| 13 | |||
| 14 | * configure: Regenerate. | ||
| 15 | |||
| 16 | Hi, this is a follow up for issue "http://codereview.appspot.com/4641076". | ||
| 17 | |||
| 18 | The rationale for the patch copied from previous thread: | ||
| 19 | ======================================= | ||
| 20 | The setup: | ||
| 21 | |||
| 22 | Configuring a toolchain targeting x86-64 GNU Linux (Ubuntu Lucid), as a | ||
| 23 | cross-compiler. Using a sysroot to provide the Lucid headers+libraries, | ||
| 24 | with the sysroot path being within the GCC install tree. Want to use the | ||
| 25 | Lucid system libstdc++ and headers, which means that I'm not | ||
| 26 | building/installing libstdc++-v3. | ||
| 27 | |||
| 28 | So, configuring with: | ||
| 29 | --with-sysroot="$SYSROOT" | ||
| 30 | --disable-libstdc++-v3 \ | ||
| 31 | --with-gxx-include-dir="$SYSROOT/usr/include/c++/4.4" \ | ||
| 32 | (among other options). | ||
| 33 | |||
| 34 | Hoping to support two usage models with this configuration, w.r.t. use of | ||
| 35 | the sysroot: | ||
| 36 | |||
| 37 | (1) somebody installs the sysroot in the normal location relative to the | ||
| 38 | GCC install, and relocates the whole bundle (sysroot+GCC). This works | ||
| 39 | great AFAICT, GCC finds its includes (including the C++ includes) thanks | ||
| 40 | to the add_standard_paths iprefix handling. | ||
| 41 | |||
| 42 | (2) somebody installs the sysroot in a non-standard location, and uses | ||
| 43 | --sysroot to try to access it. This works fine for the C headers, but | ||
| 44 | doesn't work. | ||
| 45 | |||
| 46 | For the C headers, add_standard_paths prepends the sysroot location to | ||
| 47 | the /usr/include path (since that's what's specified in cppdefault.c for | ||
| 48 | that path). It doesn't do the same for the C++ include path, though | ||
| 49 | (again, as specified in cppdefault.c). | ||
| 50 | |||
| 51 | add_standard_paths doesn't attempt to relocate built-in include paths that | ||
| 52 | start with the compiled-in sysroot location (e.g., the g++ include dir, in | ||
| 53 | this case). This isn't surprising really: normally you either prepend the | ||
| 54 | sysroot location or you don't (as specified by cppdefault.c); none of the | ||
| 55 | built-in paths normally *start* with the sysroot location and need to be | ||
| 56 | relocated. However, in this odd-ball case of trying to use the C++ headers | ||
| 57 | from the sysroot, one of the paths *does* need to be relocated in this way. | ||
| 58 | =========================== | ||
| 59 | --- a/gcc/Makefile.in | ||
| 60 | +++ b/gcc/Makefile.in | ||
| 61 | @@ -585,6 +585,7 @@ slibdir = @slibdir@ | ||
| 62 | build_tooldir = $(exec_prefix)/$(target_noncanonical) | ||
| 63 | # Directory in which the compiler finds target-independent g++ includes. | ||
| 64 | gcc_gxx_include_dir = @gcc_gxx_include_dir@ | ||
| 65 | +gcc_gxx_include_dir_add_sysroot = @gcc_gxx_include_dir_add_sysroot@ | ||
| 66 | # Directory to search for site-specific includes. | ||
| 67 | local_includedir = $(local_prefix)/include | ||
| 68 | includedir = $(prefix)/include | ||
| 69 | @@ -3788,6 +3789,7 @@ PREPROCESSOR_DEFINES = \ | ||
| 70 | -DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \ | ||
| 71 | -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \ | ||
| 72 | -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \ | ||
| 73 | + -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \ | ||
| 74 | -DGPLUSPLUS_TOOL_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/$(target_noncanonical)\" \ | ||
| 75 | -DGPLUSPLUS_BACKWARD_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/backward\" \ | ||
| 76 | -DLOCAL_INCLUDE_DIR=\"$(local_includedir)\" \ | ||
| 77 | --- a/gcc/configure.ac | ||
| 78 | +++ b/gcc/configure.ac | ||
| 79 | @@ -144,6 +144,15 @@ if test x${gcc_gxx_include_dir} = x; the | ||
| 80 | fi | ||
| 81 | fi | ||
| 82 | |||
| 83 | +gcc_gxx_include_dir_add_sysroot=0 | ||
| 84 | +if test "${with_sysroot+set}" = set; then : | ||
| 85 | + gcc_gxx_without_sysroot=`expr "${gcc_gxx_include_dir}" : "${with_sysroot}"'\(.*\)'` | ||
| 86 | + if test "${gcc_gxx_without_sysroot}"; then : | ||
| 87 | + gcc_gxx_include_dir="${gcc_gxx_without_sysroot}" | ||
| 88 | + gcc_gxx_include_dir_add_sysroot=1 | ||
| 89 | + fi | ||
| 90 | +fi | ||
| 91 | + | ||
| 92 | AC_ARG_WITH(cpp_install_dir, | ||
| 93 | [ --with-cpp-install-dir=DIR | ||
| 94 | install the user visible C preprocessor in DIR | ||
| 95 | @@ -4492,6 +4501,7 @@ AC_SUBST(extra_programs) | ||
| 96 | AC_SUBST(float_h_file) | ||
| 97 | AC_SUBST(gcc_config_arguments) | ||
| 98 | AC_SUBST(gcc_gxx_include_dir) | ||
| 99 | +AC_SUBST(gcc_gxx_include_dir_add_sysroot) | ||
| 100 | AC_SUBST(host_exeext) | ||
| 101 | AC_SUBST(host_xm_file_list) | ||
| 102 | AC_SUBST(host_xm_include_list) | ||
| 103 | --- a/gcc/cppdefault.c | ||
| 104 | +++ b/gcc/cppdefault.c | ||
| 105 | @@ -48,15 +48,18 @@ const struct default_include cpp_include | ||
| 106 | = { | ||
| 107 | #ifdef GPLUSPLUS_INCLUDE_DIR | ||
| 108 | /* Pick up GNU C++ generic include files. */ | ||
| 109 | - { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, 0, 0 }, | ||
| 110 | + { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, | ||
| 111 | + GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, | ||
| 112 | #endif | ||
| 113 | #ifdef GPLUSPLUS_TOOL_INCLUDE_DIR | ||
| 114 | /* Pick up GNU C++ target-dependent include files. */ | ||
| 115 | - { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, 0, 1 }, | ||
| 116 | + { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, | ||
| 117 | + GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, | ||
| 118 | #endif | ||
| 119 | #ifdef GPLUSPLUS_BACKWARD_INCLUDE_DIR | ||
| 120 | /* Pick up GNU C++ backward and deprecated include files. */ | ||
| 121 | - { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, 0, 0 }, | ||
| 122 | + { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, | ||
| 123 | + GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, | ||
| 124 | #endif | ||
| 125 | #ifdef LOCAL_INCLUDE_DIR | ||
| 126 | /* /usr/local/include comes before the fixincluded header files. */ | ||
| 127 | --- a/gcc/configure | ||
| 128 | +++ b/gcc/configure | ||
| 129 | @@ -639,6 +639,7 @@ host_xm_defines | ||
| 130 | host_xm_include_list | ||
| 131 | host_xm_file_list | ||
| 132 | host_exeext | ||
| 133 | +gcc_gxx_include_dir_add_sysroot | ||
| 134 | gcc_gxx_include_dir | ||
| 135 | gcc_config_arguments | ||
| 136 | float_h_file | ||
| 137 | @@ -3282,6 +3283,15 @@ if test x${gcc_gxx_include_dir} = x; the | ||
| 138 | fi | ||
| 139 | fi | ||
| 140 | |||
| 141 | +gcc_gxx_include_dir_add_sysroot=0 | ||
| 142 | +if test "${with_sysroot+set}" = set; then : | ||
| 143 | + gcc_gxx_without_sysroot=`expr "${gcc_gxx_include_dir}" : "${with_sysroot}"'\(.*\)'` | ||
| 144 | + if test "${gcc_gxx_without_sysroot}"; then : | ||
| 145 | + gcc_gxx_include_dir="${gcc_gxx_without_sysroot}" | ||
| 146 | + gcc_gxx_include_dir_add_sysroot=1 | ||
| 147 | + fi | ||
| 148 | +fi | ||
| 149 | + | ||
| 150 | |||
| 151 | # Check whether --with-cpp_install_dir was given. | ||
| 152 | if test "${with_cpp_install_dir+set}" = set; then : | ||
| 153 | @@ -17118,7 +17128,7 @@ else | ||
| 154 | lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 | ||
| 155 | lt_status=$lt_dlunknown | ||
| 156 | cat > conftest.$ac_ext <<_LT_EOF | ||
| 157 | -#line 17121 "configure" | ||
| 158 | +#line 17131 "configure" | ||
| 159 | #include "confdefs.h" | ||
| 160 | |||
| 161 | #if HAVE_DLFCN_H | ||
| 162 | @@ -17224,7 +17234,7 @@ else | ||
| 163 | lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 | ||
| 164 | lt_status=$lt_dlunknown | ||
| 165 | cat > conftest.$ac_ext <<_LT_EOF | ||
| 166 | -#line 17227 "configure" | ||
| 167 | +#line 17237 "configure" | ||
| 168 | #include "confdefs.h" | ||
| 169 | |||
| 170 | #if HAVE_DLFCN_H | ||
| 171 | @@ -25381,6 +25391,7 @@ fi | ||
| 172 | |||
| 173 | |||
| 174 | |||
| 175 | + | ||
| 176 | |||
| 177 | |||
| 178 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/Makefile.in.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/Makefile.in.patch deleted file mode 100644 index 45df47c5b..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/Makefile.in.patch +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | Index: gcc-4.5/gcc/Makefile.in | ||
| 2 | =================================================================== | ||
| 3 | --- gcc-4.5.orig/gcc/Makefile.in | ||
| 4 | +++ gcc-4.5/gcc/Makefile.in | ||
| 5 | @@ -656,7 +656,7 @@ LIBGCC2_INCLUDES = | ||
| 6 | TARGET_LIBGCC2_CFLAGS = | ||
| 7 | |||
| 8 | # Options to use when compiling crtbegin/end. | ||
| 9 | -CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \ | ||
| 10 | +CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(TARGET_INCLUDES) $(MULTILIB_CFLAGS) -g0 \ | ||
| 11 | -finhibit-size-directive -fno-inline -fno-exceptions \ | ||
| 12 | -fno-zero-initialized-in-bss -fno-toplevel-reorder -fno-tree-vectorize \ | ||
| 13 | $(INHIBIT_LIBC_CFLAGS) | ||
| 14 | @@ -1038,10 +1038,14 @@ BUILD_ERRORS = build/errors.o | ||
| 15 | # -I$(@D) and -I$(srcdir)/$(@D) cause the subdirectory of the file | ||
| 16 | # currently being compiled, in both source trees, to be examined as well. | ||
| 17 | # libintl.h will be found in ../intl if we are using the included libintl. | ||
| 18 | -INCLUDES = -I. -I$(@D) -I$(srcdir) -I$(srcdir)/$(@D) \ | ||
| 19 | +# | ||
| 20 | +# TARGET_INCLUDES is added to avoid that GMPINC (which points to the host | ||
| 21 | +# include dir) is used for compiling libgcc.a | ||
| 22 | +TARGET_INCLUDES = -I. -I$(@D) -I$(srcdir) -I$(srcdir)/$(@D) \ | ||
| 23 | -I$(srcdir)/../include @INCINTL@ \ | ||
| 24 | - $(CPPINC) $(GMPINC) $(DECNUMINC) \ | ||
| 25 | + $(CPPINC) $(DECNUMINC) \ | ||
| 26 | $(PPLINC) $(CLOOGINC) $(LIBELFINC) | ||
| 27 | +INCLUDES = $(TARGET_INCLUDES) $(GMPINC) | ||
| 28 | |||
| 29 | .c.o: | ||
| 30 | $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $< $(OUTPUT_OPTION) | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-lib1funcs.as-fix-mismatch-between-conditions-of-an-IT-block.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-lib1funcs.as-fix-mismatch-between-conditions-of-an-IT-block.patch deleted file mode 100644 index 39c90e7e7..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-lib1funcs.as-fix-mismatch-between-conditions-of-an-IT-block.patch +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | Fix for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43999 | ||
| 2 | |||
| 3 | http://patchwork.ozlabs.org/patch/72260/ is the patch that made into | ||
| 4 | upstream gcc | ||
| 5 | |||
| 6 | diff --git a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm | ||
| 7 | index 085e690..2e76c01 100644 | ||
| 8 | --- a/gcc/config/arm/lib1funcs.asm | ||
| 9 | +++ b/gcc/config/arm/lib1funcs.asm | ||
| 10 | @@ -641,7 +641,7 @@ pc .req r15 | ||
| 11 | subhs \dividend, \dividend, \divisor, lsr #3 | ||
| 12 | orrhs \result, \result, \curbit, lsr #3 | ||
| 13 | cmp \dividend, #0 @ Early termination? | ||
| 14 | - do_it hs, t | ||
| 15 | + do_it ne, t | ||
| 16 | movnes \curbit, \curbit, lsr #4 @ No, any more bits to do? | ||
| 17 | movne \divisor, \divisor, lsr #4 | ||
| 18 | bne 1b | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-unbreak-eabi-armv4t.dpatch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-unbreak-eabi-armv4t.dpatch deleted file mode 100644 index 7bb888706..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-unbreak-eabi-armv4t.dpatch +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | #! /bin/sh -e | ||
| 2 | |||
| 3 | # DP: Fix armv4t build on ARM | ||
| 4 | |||
| 5 | dir= | ||
| 6 | if [ $# -eq 3 -a "$2" = '-d' ]; then | ||
| 7 | pdir="-d $3" | ||
| 8 | dir="$3/" | ||
| 9 | elif [ $# -ne 1 ]; then | ||
| 10 | echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" | ||
| 11 | exit 1 | ||
| 12 | fi | ||
| 13 | case "$1" in | ||
| 14 | -patch) | ||
| 15 | patch $pdir -f --no-backup-if-mismatch -p1 < $0 | ||
| 16 | ;; | ||
| 17 | -unpatch) | ||
| 18 | patch $pdir -f --no-backup-if-mismatch -R -p1 < $0 | ||
| 19 | ;; | ||
| 20 | *) | ||
| 21 | echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" | ||
| 22 | exit 1 | ||
| 23 | esac | ||
| 24 | exit 0 | ||
| 25 | |||
| 26 | --- src/gcc/config/arm/linux-eabi.h.orig 2007-11-24 12:37:38.000000000 +0000 | ||
| 27 | +++ src/gcc/config/arm/linux-eabi.h 2007-11-24 12:39:41.000000000 +0000 | ||
| 28 | @@ -44,7 +44,7 @@ | ||
| 29 | The ARM10TDMI core is the default for armv5t, so set | ||
| 30 | SUBTARGET_CPU_DEFAULT to achieve this. */ | ||
| 31 | #undef SUBTARGET_CPU_DEFAULT | ||
| 32 | -#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm10tdmi | ||
| 33 | +#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm9tdmi | ||
| 34 | |||
| 35 | /* TARGET_BIG_ENDIAN_DEFAULT is set in | ||
| 36 | config.gcc for big endian configurations. */ | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/cache-amnesia.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/cache-amnesia.patch deleted file mode 100644 index b889f9b6c..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/cache-amnesia.patch +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | --- | ||
| 2 | gcc/configure | 2 +- | ||
| 3 | gcc/configure.ac | 2 +- | ||
| 4 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
| 5 | |||
| 6 | Index: gcc-4.5+svnr155514/gcc/configure | ||
| 7 | =================================================================== | ||
| 8 | --- gcc-4.5+svnr155514.orig/gcc/configure 2009-12-29 22:00:40.000000000 -0800 | ||
| 9 | +++ gcc-4.5+svnr155514/gcc/configure 2009-12-29 23:52:43.381592113 -0800 | ||
| 10 | @@ -10467,7 +10467,7 @@ else | ||
| 11 | saved_CFLAGS="${CFLAGS}" | ||
| 12 | CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \ | ||
| 13 | LDFLAGS="${LDFLAGS_FOR_BUILD}" \ | ||
| 14 | - ${realsrcdir}/configure \ | ||
| 15 | + CONFIG_SITE= ${realsrcdir}/configure --cache-file=./other.cache \ | ||
| 16 | --enable-languages=${enable_languages-all} \ | ||
| 17 | --target=$target_alias --host=$build_alias --build=$build_alias | ||
| 18 | CFLAGS="${saved_CFLAGS}" | ||
| 19 | Index: gcc-4.5+svnr155514/gcc/configure.ac | ||
| 20 | =================================================================== | ||
| 21 | --- gcc-4.5+svnr155514.orig/gcc/configure.ac 2009-12-29 22:00:40.000000000 -0800 | ||
| 22 | +++ gcc-4.5+svnr155514/gcc/configure.ac 2009-12-29 23:51:54.589091778 -0800 | ||
| 23 | @@ -1458,7 +1458,7 @@ else | ||
| 24 | saved_CFLAGS="${CFLAGS}" | ||
| 25 | CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \ | ||
| 26 | LDFLAGS="${LDFLAGS_FOR_BUILD}" \ | ||
| 27 | - ${realsrcdir}/configure \ | ||
| 28 | + CONFIG_SITE= ${realsrcdir}/configure --cache-file=./other.cache \ | ||
| 29 | --enable-languages=${enable_languages-all} \ | ||
| 30 | --target=$target_alias --host=$build_alias --build=$build_alias | ||
| 31 | CFLAGS="${saved_CFLAGS}" | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/cpp-honour-sysroot.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/cpp-honour-sysroot.patch deleted file mode 100644 index cf4c77c26..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/cpp-honour-sysroot.patch +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | Currently, if the gcc toolchain is relocated and installed from sstate, then you try and compile | ||
| 2 | preprocessed source (.i or .ii files), the compiler will try and access the builtin sysroot location | ||
| 3 | rather than the --sysroot option specified on the commandline. If access to that directory is | ||
| 4 | permission denied (unreadable), gcc will error. | ||
| 5 | |||
| 6 | This happens when ccache is in use due to the fact it uses preprocessed source files. | ||
| 7 | |||
| 8 | The fix below adds %I to the cpp-output spec macro so the default substitutions for -iprefix, | ||
| 9 | -isystem, -isysroot happen and the correct sysroot is used. | ||
| 10 | |||
| 11 | [YOCTO #2074] | ||
| 12 | |||
| 13 | Upstream-Status: Pending | ||
| 14 | |||
| 15 | RP 2012/04/13 | ||
| 16 | |||
| 17 | --- a/gcc/gcc.c | ||
| 18 | +++ b/gcc/gcc.c | ||
| 19 | @@ -1106,7 +1106,7 @@ static const struct compiler default_com | ||
| 20 | %W{o*:--output-pch=%*}%V}}}}}}", 0, 0, 0}, | ||
| 21 | {".i", "@cpp-output", 0, 1, 0}, | ||
| 22 | {"@cpp-output", | ||
| 23 | - "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %(cc1_options) %{!fsyntax-only:%(invoke_as)}}}}", 0, 1, 0}, | ||
| 24 | + "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %I %(cc1_options) %{!fsyntax-only:%(invoke_as)}}}}", 0, 1, 0}, | ||
| 25 | {".s", "@assembler", 0, 1, 0}, | ||
| 26 | {"@assembler", | ||
| 27 | "%{!M:%{!MM:%{!E:%{!S:as %(asm_debug) %(asm_options) %i %A }}}}", 0, 1, 0}, | ||
| 28 | --- a/gcc/cp/lang-specs.h | ||
| 29 | +++ b/gcc/cp/lang-specs.h | ||
| 30 | @@ -63,5 +63,5 @@ along with GCC; see the file COPYING3. | ||
| 31 | {".ii", "@c++-cpp-output", 0, 0, 0}, | ||
| 32 | {"@c++-cpp-output", | ||
| 33 | "%{!M:%{!MM:%{!E:\ | ||
| 34 | - cc1plus -fpreprocessed %i %(cc1_options) %2 %{+e*}\ | ||
| 35 | + cc1plus -fpreprocessed %i %I %(cc1_options) %2 %{+e*}\ | ||
| 36 | %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/disable_relax_pic_calls_flag.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/disable_relax_pic_calls_flag.patch deleted file mode 100644 index b1d5a1a3c..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/disable_relax_pic_calls_flag.patch +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | GCC: disable MASK_RELAX_PIC_CALLS bit | ||
| 2 | |||
| 3 | The new feature added after 4.3.3 | ||
| 4 | "http://www.pubbs.net/200909/gcc/94048-patch-add-support-for-rmipsjalr.html" | ||
| 5 | will cause cc1plus eat up all the system memory when build webkit-gtk. | ||
| 6 | The function mips_get_pic_call_symbol keeps on recursively calling itself. | ||
| 7 | Disable this feature to walk aside the bug. | ||
| 8 | |||
| 9 | Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com> | ||
| 10 | |||
| 11 | diff -ruN gcc-4.5.0-orig/gcc/configure gcc-4.5.0/gcc/configure | ||
| 12 | --- gcc-4.5.0-orig/gcc/configure 2010-09-17 23:30:21.000000000 +0800 | ||
| 13 | +++ gcc-4.5.0/gcc/configure 2010-09-19 18:21:28.000000000 +0800 | ||
| 14 | @@ -23945,13 +23945,6 @@ | ||
| 15 | rm -f conftest.* | ||
| 16 | fi | ||
| 17 | fi | ||
| 18 | - if test $gcc_cv_as_ld_jalr_reloc = yes; then | ||
| 19 | - if test x$target_cpu_default = x; then | ||
| 20 | - target_cpu_default=MASK_RELAX_PIC_CALLS | ||
| 21 | - else | ||
| 22 | - target_cpu_default="($target_cpu_default)|MASK_RELAX_PIC_CALLS" | ||
| 23 | - fi | ||
| 24 | - fi | ||
| 25 | { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_ld_jalr_reloc" >&5 | ||
| 26 | $as_echo "$gcc_cv_as_ld_jalr_reloc" >&6; } | ||
| 27 | |||
| 28 | diff -ruN gcc-4.5.0-orig/gcc/configure.ac gcc-4.5.0/gcc/configure.ac | ||
| 29 | --- gcc-4.5.0-orig/gcc/configure.ac 2010-09-17 23:30:21.000000000 +0800 | ||
| 30 | +++ gcc-4.5.0/gcc/configure.ac 2010-09-19 18:21:11.000000000 +0800 | ||
| 31 | @@ -3467,13 +3467,6 @@ | ||
| 32 | rm -f conftest.* | ||
| 33 | fi | ||
| 34 | fi | ||
| 35 | - if test $gcc_cv_as_ld_jalr_reloc = yes; then | ||
| 36 | - if test x$target_cpu_default = x; then | ||
| 37 | - target_cpu_default=MASK_RELAX_PIC_CALLS | ||
| 38 | - else | ||
| 39 | - target_cpu_default="($target_cpu_default)|MASK_RELAX_PIC_CALLS" | ||
| 40 | - fi | ||
| 41 | - fi | ||
| 42 | AC_MSG_RESULT($gcc_cv_as_ld_jalr_reloc) | ||
| 43 | |||
| 44 | AC_CACHE_CHECK([linker for .eh_frame personality relaxation], | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-c++-builtin-redecl.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-c++-builtin-redecl.patch deleted file mode 100644 index a149eae98..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-c++-builtin-redecl.patch +++ /dev/null | |||
| @@ -1,114 +0,0 @@ | |||
| 1 | 2007-10-02 Jakub Jelinek <jakub@redhat.com> | ||
| 2 | |||
| 3 | * decl.c (duplicate_decls): When redeclaring a builtin function, | ||
| 4 | keep the merged decl builtin whenever types match, even if new | ||
| 5 | decl defines a function. | ||
| 6 | |||
| 7 | * gcc.dg/builtins-65.c: New test. | ||
| 8 | * g++.dg/ext/builtin10.C: New test. | ||
| 9 | |||
| 10 | Index: gcc/cp/decl.c | ||
| 11 | =================================================================== | ||
| 12 | --- gcc/cp/decl.c.orig 2010-04-01 11:48:46.000000000 -0700 | ||
| 13 | +++ gcc/cp/decl.c 2010-06-25 10:10:54.749131719 -0700 | ||
| 14 | @@ -2021,23 +2021,21 @@ | ||
| 15 | DECL_ARGUMENTS (olddecl) = DECL_ARGUMENTS (newdecl); | ||
| 16 | DECL_RESULT (olddecl) = DECL_RESULT (newdecl); | ||
| 17 | } | ||
| 18 | + /* If redeclaring a builtin function, it stays built in. */ | ||
| 19 | + if (types_match && DECL_BUILT_IN (olddecl)) | ||
| 20 | + { | ||
| 21 | + DECL_BUILT_IN_CLASS (newdecl) = DECL_BUILT_IN_CLASS (olddecl); | ||
| 22 | + DECL_FUNCTION_CODE (newdecl) = DECL_FUNCTION_CODE (olddecl); | ||
| 23 | + /* If we're keeping the built-in definition, keep the rtl, | ||
| 24 | + regardless of declaration matches. */ | ||
| 25 | + COPY_DECL_RTL (olddecl, newdecl); | ||
| 26 | + } | ||
| 27 | if (new_defines_function) | ||
| 28 | /* If defining a function declared with other language | ||
| 29 | linkage, use the previously declared language linkage. */ | ||
| 30 | SET_DECL_LANGUAGE (newdecl, DECL_LANGUAGE (olddecl)); | ||
| 31 | else if (types_match) | ||
| 32 | { | ||
| 33 | - /* If redeclaring a builtin function, and not a definition, | ||
| 34 | - it stays built in. */ | ||
| 35 | - if (DECL_BUILT_IN (olddecl)) | ||
| 36 | - { | ||
| 37 | - DECL_BUILT_IN_CLASS (newdecl) = DECL_BUILT_IN_CLASS (olddecl); | ||
| 38 | - DECL_FUNCTION_CODE (newdecl) = DECL_FUNCTION_CODE (olddecl); | ||
| 39 | - /* If we're keeping the built-in definition, keep the rtl, | ||
| 40 | - regardless of declaration matches. */ | ||
| 41 | - COPY_DECL_RTL (olddecl, newdecl); | ||
| 42 | - } | ||
| 43 | - | ||
| 44 | DECL_RESULT (newdecl) = DECL_RESULT (olddecl); | ||
| 45 | /* Don't clear out the arguments if we're just redeclaring a | ||
| 46 | function. */ | ||
| 47 | Index: gcc/testsuite/gcc.dg/builtins-65.c | ||
| 48 | =================================================================== | ||
| 49 | --- gcc/testsuite/gcc.dg/builtins-65.c.orig 2009-06-26 02:02:04.000000000 -0700 | ||
| 50 | +++ gcc/testsuite/gcc.dg/builtins-65.c 2010-06-25 10:10:54.784464429 -0700 | ||
| 51 | @@ -1,3 +1,28 @@ | ||
| 52 | +/* { dg-do compile } */ | ||
| 53 | +/* { dg-options "-O2" } */ | ||
| 54 | + | ||
| 55 | +typedef __SIZE_TYPE__ size_t; | ||
| 56 | +extern void __chk_fail (void); | ||
| 57 | +extern int snprintf (char *, size_t, const char *, ...); | ||
| 58 | +extern inline __attribute__((gnu_inline, always_inline)) int snprintf (char *a, size_t b, const char *fmt, ...) | ||
| 59 | +{ | ||
| 60 | + if (__builtin_object_size (a, 0) != -1UL && __builtin_object_size (a, 0) < b) | ||
| 61 | + __chk_fail (); | ||
| 62 | + return __builtin_snprintf (a, b, fmt, __builtin_va_arg_pack ()); | ||
| 63 | +} | ||
| 64 | +extern int snprintf (char *, size_t, const char *, ...) __asm ("mysnprintf"); | ||
| 65 | + | ||
| 66 | +char buf[10]; | ||
| 67 | + | ||
| 68 | +int | ||
| 69 | +main (void) | ||
| 70 | +{ | ||
| 71 | + snprintf (buf, 10, "%d%d\n", 10, 10); | ||
| 72 | + return 0; | ||
| 73 | +} | ||
| 74 | + | ||
| 75 | +/* { dg-final { scan-assembler "mysnprintf" } } */ | ||
| 76 | +/* { dg-final { scan-assembler-not "__chk_fail" } } */ | ||
| 77 | /* { dg-do link } */ | ||
| 78 | /* { dg-options "-O2 -ffast-math" } */ | ||
| 79 | /* { dg-require-effective-target c99_runtime } */ | ||
| 80 | Index: gcc/testsuite/g++.dg/ext/builtin10.C | ||
| 81 | =================================================================== | ||
| 82 | --- gcc/testsuite/g++.dg/ext/builtin10.C.orig 2009-02-02 03:27:50.000000000 -0800 | ||
| 83 | +++ gcc/testsuite/g++.dg/ext/builtin10.C 2010-06-25 10:10:54.816467202 -0700 | ||
| 84 | @@ -1,3 +1,30 @@ | ||
| 85 | +// { dg-do compile } | ||
| 86 | +// { dg-options "-O2" } | ||
| 87 | + | ||
| 88 | +typedef __SIZE_TYPE__ size_t; | ||
| 89 | +extern "C" { | ||
| 90 | +extern void __chk_fail (void); | ||
| 91 | +extern int snprintf (char *, size_t, const char *, ...); | ||
| 92 | +extern inline __attribute__((gnu_inline, always_inline)) int snprintf (char *a, size_t b, const char *fmt, ...) | ||
| 93 | +{ | ||
| 94 | + if (__builtin_object_size (a, 0) != -1UL && __builtin_object_size (a, 0) < b) | ||
| 95 | + __chk_fail (); | ||
| 96 | + return __builtin_snprintf (a, b, fmt, __builtin_va_arg_pack ()); | ||
| 97 | +} | ||
| 98 | +extern int snprintf (char *, size_t, const char *, ...) __asm ("mysnprintf"); | ||
| 99 | +} | ||
| 100 | + | ||
| 101 | +char buf[10]; | ||
| 102 | + | ||
| 103 | +int | ||
| 104 | +main (void) | ||
| 105 | +{ | ||
| 106 | + snprintf (buf, 10, "%d%d\n", 10, 10); | ||
| 107 | + return 0; | ||
| 108 | +} | ||
| 109 | + | ||
| 110 | +// { dg-final { scan-assembler "mysnprintf" } } | ||
| 111 | +// { dg-final { scan-assembler-not "__chk_fail" } } | ||
| 112 | // { dg-do compile { target correct_iso_cpp_string_wchar_protos } } | ||
| 113 | // { dg-options "-O2 -fdump-tree-optimized" } | ||
| 114 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-cpp-pragma.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-cpp-pragma.patch deleted file mode 100644 index 00d37bd7c..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-cpp-pragma.patch +++ /dev/null | |||
| @@ -1,284 +0,0 @@ | |||
| 1 | 2008-02-26 Jakub Jelinek <jakub@redhat.com> | ||
| 2 | |||
| 3 | * c-ppoutput.c (scan_translation_unit): Handle CPP_PRAGMA | ||
| 4 | and CPP_PRAGMA_EOL. | ||
| 5 | * c-pragma.c (pragma_ns_name): New typedef. | ||
| 6 | (registered_pp_pragmas): New variable. | ||
| 7 | (c_pp_lookup_pragma): New function. | ||
| 8 | (c_register_pragma_1): If flag_preprocess_only, do nothing | ||
| 9 | for non-expanded pragmas, for expanded ones push pragma's | ||
| 10 | namespace and name into registered_pp_pragmas vector. | ||
| 11 | (c_invoke_pragma_handler): Register OpenMP pragmas even when | ||
| 12 | flag_preprocess_only, don't register GCC pch_preprocess | ||
| 13 | pragma if flag_preprocess_only. | ||
| 14 | * c-opts.c (c_common_init): Call init_pragma even if | ||
| 15 | flag_preprocess_only. | ||
| 16 | * c-pragma.c (c_pp_lookup_pragma): New prototype. | ||
| 17 | * config/darwin.h (DARWIN_REGISTER_TARGET_PRAGMAS): Don't call | ||
| 18 | cpp_register_pragma if flag_preprocess_only. | ||
| 19 | |||
| 20 | * gcc.dg/gomp/preprocess-1.c: New test. | ||
| 21 | |||
| 22 | --- gcc/c-ppoutput.c.jj 2008-01-26 18:01:16.000000000 +0100 | ||
| 23 | +++ gcc/c-ppoutput.c 2008-02-26 22:54:57.000000000 +0100 | ||
| 24 | @@ -1,6 +1,6 @@ | ||
| 25 | /* Preprocess only, using cpplib. | ||
| 26 | - Copyright (C) 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007 | ||
| 27 | - Free Software Foundation, Inc. | ||
| 28 | + Copyright (C) 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007, | ||
| 29 | + 2008 Free Software Foundation, Inc. | ||
| 30 | Written by Per Bothner, 1994-95. | ||
| 31 | |||
| 32 | This program is free software; you can redistribute it and/or modify it | ||
| 33 | @@ -177,7 +177,24 @@ scan_translation_unit (cpp_reader *pfile | ||
| 34 | avoid_paste = false; | ||
| 35 | print.source = NULL; | ||
| 36 | print.prev = token; | ||
| 37 | - cpp_output_token (token, print.outf); | ||
| 38 | + if (token->type == CPP_PRAGMA) | ||
| 39 | + { | ||
| 40 | + const char *space; | ||
| 41 | + const char *name; | ||
| 42 | + | ||
| 43 | + maybe_print_line (token->src_loc); | ||
| 44 | + fputs ("#pragma ", print.outf); | ||
| 45 | + c_pp_lookup_pragma (token->val.pragma, &space, &name); | ||
| 46 | + if (space) | ||
| 47 | + fprintf (print.outf, "%s %s", space, name); | ||
| 48 | + else | ||
| 49 | + fprintf (print.outf, "%s", name); | ||
| 50 | + print.printed = 1; | ||
| 51 | + } | ||
| 52 | + else if (token->type == CPP_PRAGMA_EOL) | ||
| 53 | + maybe_print_line (token->src_loc); | ||
| 54 | + else | ||
| 55 | + cpp_output_token (token, print.outf); | ||
| 56 | |||
| 57 | if (token->type == CPP_COMMENT) | ||
| 58 | account_for_newlines (token->val.str.text, token->val.str.len); | ||
| 59 | --- gcc/c-pragma.c.jj 2008-02-15 18:43:03.000000000 +0100 | ||
| 60 | +++ gcc/c-pragma.c 2008-02-26 22:59:44.000000000 +0100 | ||
| 61 | @@ -1,6 +1,6 @@ | ||
| 62 | /* Handle #pragma, system V.4 style. Supports #pragma weak and #pragma pack. | ||
| 63 | Copyright (C) 1992, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, | ||
| 64 | - 2006, 2007 Free Software Foundation, Inc. | ||
| 65 | + 2006, 2007, 2008 Free Software Foundation, Inc. | ||
| 66 | |||
| 67 | This file is part of GCC. | ||
| 68 | |||
| 69 | @@ -872,6 +872,61 @@ DEF_VEC_ALLOC_O (pragma_handler, heap); | ||
| 70 | |||
| 71 | static VEC(pragma_handler, heap) *registered_pragmas; | ||
| 72 | |||
| 73 | +typedef struct | ||
| 74 | +{ | ||
| 75 | + const char *space; | ||
| 76 | + const char *name; | ||
| 77 | +} pragma_ns_name; | ||
| 78 | + | ||
| 79 | +DEF_VEC_O (pragma_ns_name); | ||
| 80 | +DEF_VEC_ALLOC_O (pragma_ns_name, heap); | ||
| 81 | + | ||
| 82 | +static VEC(pragma_ns_name, heap) *registered_pp_pragmas; | ||
| 83 | + | ||
| 84 | +struct omp_pragma_def { const char *name; unsigned int id; }; | ||
| 85 | +static const struct omp_pragma_def omp_pragmas[] = { | ||
| 86 | + { "atomic", PRAGMA_OMP_ATOMIC }, | ||
| 87 | + { "barrier", PRAGMA_OMP_BARRIER }, | ||
| 88 | + { "critical", PRAGMA_OMP_CRITICAL }, | ||
| 89 | + { "flush", PRAGMA_OMP_FLUSH }, | ||
| 90 | + { "for", PRAGMA_OMP_FOR }, | ||
| 91 | + { "master", PRAGMA_OMP_MASTER }, | ||
| 92 | + { "ordered", PRAGMA_OMP_ORDERED }, | ||
| 93 | + { "parallel", PRAGMA_OMP_PARALLEL }, | ||
| 94 | + { "section", PRAGMA_OMP_SECTION }, | ||
| 95 | + { "sections", PRAGMA_OMP_SECTIONS }, | ||
| 96 | + { "single", PRAGMA_OMP_SINGLE }, | ||
| 97 | + { "threadprivate", PRAGMA_OMP_THREADPRIVATE } | ||
| 98 | +}; | ||
| 99 | + | ||
| 100 | +void | ||
| 101 | +c_pp_lookup_pragma (unsigned int id, const char **space, const char **name) | ||
| 102 | +{ | ||
| 103 | + const int n_omp_pragmas = sizeof (omp_pragmas) / sizeof (*omp_pragmas); | ||
| 104 | + int i; | ||
| 105 | + | ||
| 106 | + for (i = 0; i < n_omp_pragmas; ++i) | ||
| 107 | + if (omp_pragmas[i].id == id) | ||
| 108 | + { | ||
| 109 | + *space = "omp"; | ||
| 110 | + *name = omp_pragmas[i].name; | ||
| 111 | + return; | ||
| 112 | + } | ||
| 113 | + | ||
| 114 | + if (id >= PRAGMA_FIRST_EXTERNAL | ||
| 115 | + && (id < PRAGMA_FIRST_EXTERNAL | ||
| 116 | + + VEC_length (pragma_ns_name, registered_pp_pragmas))) | ||
| 117 | + { | ||
| 118 | + *space = VEC_index (pragma_ns_name, registered_pp_pragmas, | ||
| 119 | + id - PRAGMA_FIRST_EXTERNAL)->space; | ||
| 120 | + *name = VEC_index (pragma_ns_name, registered_pp_pragmas, | ||
| 121 | + id - PRAGMA_FIRST_EXTERNAL)->name; | ||
| 122 | + return; | ||
| 123 | + } | ||
| 124 | + | ||
| 125 | + gcc_unreachable (); | ||
| 126 | +} | ||
| 127 | + | ||
| 128 | /* Front-end wrappers for pragma registration to avoid dragging | ||
| 129 | cpplib.h in almost everywhere. */ | ||
| 130 | |||
| 131 | @@ -881,13 +936,29 @@ c_register_pragma_1 (const char *space, | ||
| 132 | { | ||
| 133 | unsigned id; | ||
| 134 | |||
| 135 | - VEC_safe_push (pragma_handler, heap, registered_pragmas, &handler); | ||
| 136 | - id = VEC_length (pragma_handler, registered_pragmas); | ||
| 137 | - id += PRAGMA_FIRST_EXTERNAL - 1; | ||
| 138 | - | ||
| 139 | - /* The C++ front end allocates 6 bits in cp_token; the C front end | ||
| 140 | - allocates 7 bits in c_token. At present this is sufficient. */ | ||
| 141 | - gcc_assert (id < 64); | ||
| 142 | + if (flag_preprocess_only) | ||
| 143 | + { | ||
| 144 | + pragma_ns_name ns_name; | ||
| 145 | + | ||
| 146 | + if (!allow_expansion) | ||
| 147 | + return; | ||
| 148 | + | ||
| 149 | + ns_name.space = space; | ||
| 150 | + ns_name.name = name; | ||
| 151 | + VEC_safe_push (pragma_ns_name, heap, registered_pp_pragmas, &ns_name); | ||
| 152 | + id = VEC_length (pragma_ns_name, registered_pp_pragmas); | ||
| 153 | + id += PRAGMA_FIRST_EXTERNAL - 1; | ||
| 154 | + } | ||
| 155 | + else | ||
| 156 | + { | ||
| 157 | + VEC_safe_push (pragma_handler, heap, registered_pragmas, &handler); | ||
| 158 | + id = VEC_length (pragma_handler, registered_pragmas); | ||
| 159 | + id += PRAGMA_FIRST_EXTERNAL - 1; | ||
| 160 | + | ||
| 161 | + /* The C++ front end allocates 6 bits in cp_token; the C front end | ||
| 162 | + allocates 7 bits in c_token. At present this is sufficient. */ | ||
| 163 | + gcc_assert (id < 64); | ||
| 164 | + } | ||
| 165 | |||
| 166 | cpp_register_deferred_pragma (parse_in, space, name, id, | ||
| 167 | allow_expansion, false); | ||
| 168 | @@ -921,24 +992,8 @@ c_invoke_pragma_handler (unsigned int id | ||
| 169 | void | ||
| 170 | init_pragma (void) | ||
| 171 | { | ||
| 172 | - if (flag_openmp && !flag_preprocess_only) | ||
| 173 | + if (flag_openmp) | ||
| 174 | { | ||
| 175 | - struct omp_pragma_def { const char *name; unsigned int id; }; | ||
| 176 | - static const struct omp_pragma_def omp_pragmas[] = { | ||
| 177 | - { "atomic", PRAGMA_OMP_ATOMIC }, | ||
| 178 | - { "barrier", PRAGMA_OMP_BARRIER }, | ||
| 179 | - { "critical", PRAGMA_OMP_CRITICAL }, | ||
| 180 | - { "flush", PRAGMA_OMP_FLUSH }, | ||
| 181 | - { "for", PRAGMA_OMP_FOR }, | ||
| 182 | - { "master", PRAGMA_OMP_MASTER }, | ||
| 183 | - { "ordered", PRAGMA_OMP_ORDERED }, | ||
| 184 | - { "parallel", PRAGMA_OMP_PARALLEL }, | ||
| 185 | - { "section", PRAGMA_OMP_SECTION }, | ||
| 186 | - { "sections", PRAGMA_OMP_SECTIONS }, | ||
| 187 | - { "single", PRAGMA_OMP_SINGLE }, | ||
| 188 | - { "threadprivate", PRAGMA_OMP_THREADPRIVATE } | ||
| 189 | - }; | ||
| 190 | - | ||
| 191 | const int n_omp_pragmas = sizeof (omp_pragmas) / sizeof (*omp_pragmas); | ||
| 192 | int i; | ||
| 193 | |||
| 194 | @@ -947,8 +1002,9 @@ init_pragma (void) | ||
| 195 | omp_pragmas[i].id, true, true); | ||
| 196 | } | ||
| 197 | |||
| 198 | - cpp_register_deferred_pragma (parse_in, "GCC", "pch_preprocess", | ||
| 199 | - PRAGMA_GCC_PCH_PREPROCESS, false, false); | ||
| 200 | + if (!flag_preprocess_only) | ||
| 201 | + cpp_register_deferred_pragma (parse_in, "GCC", "pch_preprocess", | ||
| 202 | + PRAGMA_GCC_PCH_PREPROCESS, false, false); | ||
| 203 | |||
| 204 | #ifdef HANDLE_PRAGMA_PACK | ||
| 205 | #ifdef HANDLE_PRAGMA_PACK_WITH_EXPANSION | ||
| 206 | --- gcc/c-opts.c.jj 2008-02-26 22:53:23.000000000 +0100 | ||
| 207 | +++ gcc/c-opts.c 2008-02-26 22:54:57.000000000 +0100 | ||
| 208 | @@ -1,5 +1,5 @@ | ||
| 209 | /* C/ObjC/C++ command line option handling. | ||
| 210 | - Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007 | ||
| 211 | + Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008 | ||
| 212 | Free Software Foundation, Inc. | ||
| 213 | Contributed by Neil Booth. | ||
| 214 | |||
| 215 | @@ -1239,6 +1239,9 @@ c_common_init (void) | ||
| 216 | if (version_flag) | ||
| 217 | c_common_print_pch_checksum (stderr); | ||
| 218 | |||
| 219 | + /* Has to wait until now so that cpplib has its hash table. */ | ||
| 220 | + init_pragma (); | ||
| 221 | + | ||
| 222 | if (flag_preprocess_only) | ||
| 223 | { | ||
| 224 | finish_options (); | ||
| 225 | @@ -1246,9 +1249,6 @@ c_common_init (void) | ||
| 226 | return false; | ||
| 227 | } | ||
| 228 | |||
| 229 | - /* Has to wait until now so that cpplib has its hash table. */ | ||
| 230 | - init_pragma (); | ||
| 231 | - | ||
| 232 | return true; | ||
| 233 | } | ||
| 234 | |||
| 235 | --- gcc/c-pragma.h.jj 2008-01-26 18:01:16.000000000 +0100 | ||
| 236 | +++ gcc/c-pragma.h 2008-02-26 22:54:57.000000000 +0100 | ||
| 237 | @@ -1,6 +1,6 @@ | ||
| 238 | /* Pragma related interfaces. | ||
| 239 | Copyright (C) 1995, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, | ||
| 240 | - 2007 Free Software Foundation, Inc. | ||
| 241 | + 2007, 2008 Free Software Foundation, Inc. | ||
| 242 | |||
| 243 | This file is part of GCC. | ||
| 244 | |||
| 245 | @@ -124,4 +124,6 @@ extern enum cpp_ttype pragma_lex (tree * | ||
| 246 | extern enum cpp_ttype c_lex_with_flags (tree *, location_t *, unsigned char *, | ||
| 247 | int); | ||
| 248 | |||
| 249 | +extern void c_pp_lookup_pragma (unsigned int, const char **, const char **); | ||
| 250 | + | ||
| 251 | #endif /* GCC_C_PRAGMA_H */ | ||
| 252 | --- gcc/config/darwin.h.jj 2008-02-11 14:48:12.000000000 +0100 | ||
| 253 | +++ gcc/config/darwin.h 2008-02-26 22:54:57.000000000 +0100 | ||
| 254 | @@ -892,8 +892,9 @@ enum machopic_addr_class { | ||
| 255 | |||
| 256 | #define DARWIN_REGISTER_TARGET_PRAGMAS() \ | ||
| 257 | do { \ | ||
| 258 | - cpp_register_pragma (parse_in, NULL, "mark", \ | ||
| 259 | - darwin_pragma_ignore, false); \ | ||
| 260 | + if (!flag_preprocess_only) \ | ||
| 261 | + cpp_register_pragma (parse_in, NULL, "mark", \ | ||
| 262 | + darwin_pragma_ignore, false); \ | ||
| 263 | c_register_pragma (0, "options", darwin_pragma_options); \ | ||
| 264 | c_register_pragma (0, "segment", darwin_pragma_ignore); \ | ||
| 265 | c_register_pragma (0, "unused", darwin_pragma_unused); \ | ||
| 266 | --- gcc/testsuite/gcc.dg/gomp/preprocess-1.c.jj 2008-02-26 22:54:57.000000000 +0100 | ||
| 267 | +++ gcc/testsuite/gcc.dg/gomp/preprocess-1.c 2008-02-26 22:54:57.000000000 +0100 | ||
| 268 | @@ -0,0 +1,16 @@ | ||
| 269 | +/* { dg-do preprocess } */ | ||
| 270 | + | ||
| 271 | +void foo (void) | ||
| 272 | +{ | ||
| 273 | + int i1, j1, k1; | ||
| 274 | +#define p parallel | ||
| 275 | +#define P(x) private (x##1) | ||
| 276 | +#define S(x) shared (x##1) | ||
| 277 | +#define F(x) firstprivate (x##1) | ||
| 278 | +#pragma omp p P(i) \ | ||
| 279 | + S(j) \ | ||
| 280 | + F(k) | ||
| 281 | + ; | ||
| 282 | +} | ||
| 283 | + | ||
| 284 | +/* { dg-final { scan-file preprocess-1.i "(^|\n)#pragma omp parallel private \\(i1\\) shared \\(j1\\) firstprivate \\(k1\\)($|\n)" } } */ | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-i386-libgomp.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-i386-libgomp.patch deleted file mode 100644 index a588db28e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-i386-libgomp.patch +++ /dev/null | |||
| @@ -1,65 +0,0 @@ | |||
| 1 | Build i386.rpm libgomp and libsupc++.a(guard.o) as i486+, pre-i486 | ||
| 2 | hardware isn't supported because NPTL doesn't support it anyway. | ||
| 3 | |||
| 4 | Index: libgomp/configure.tgt | ||
| 5 | =================================================================== | ||
| 6 | --- libgomp/configure.tgt.orig 2010-01-28 13:47:59.000000000 -0800 | ||
| 7 | +++ libgomp/configure.tgt 2010-06-25 10:32:26.706135558 -0700 | ||
| 8 | @@ -48,14 +48,14 @@ | ||
| 9 | ;; | ||
| 10 | |||
| 11 | # Note that bare i386 is not included here. We need cmpxchg. | ||
| 12 | - i[456]86-*-linux*) | ||
| 13 | + i[3456]86-*-linux*) | ||
| 14 | config_path="linux/x86 linux posix" | ||
| 15 | case " ${CC} ${CFLAGS} " in | ||
| 16 | *" -m64 "*) | ||
| 17 | ;; | ||
| 18 | *) | ||
| 19 | if test -z "$with_arch"; then | ||
| 20 | - XCFLAGS="${XCFLAGS} -march=i486 -mtune=${target_cpu}" | ||
| 21 | + XCFLAGS="${XCFLAGS} -march=i486 -mtune=generic" | ||
| 22 | fi | ||
| 23 | esac | ||
| 24 | ;; | ||
| 25 | @@ -67,7 +67,7 @@ | ||
| 26 | config_path="linux/x86 linux posix" | ||
| 27 | case " ${CC} ${CFLAGS} " in | ||
| 28 | *" -m32 "*) | ||
| 29 | - XCFLAGS="${XCFLAGS} -march=i486 -mtune=i686" | ||
| 30 | + XCFLAGS="${XCFLAGS} -march=i486 -mtune=generic" | ||
| 31 | ;; | ||
| 32 | esac | ||
| 33 | ;; | ||
| 34 | Index: libstdc++-v3/libsupc++/guard.cc | ||
| 35 | =================================================================== | ||
| 36 | --- libstdc++-v3/libsupc++/guard.cc.orig 2009-11-09 14:09:30.000000000 -0800 | ||
| 37 | +++ libstdc++-v3/libsupc++/guard.cc 2010-06-25 10:32:26.710135964 -0700 | ||
| 38 | @@ -30,6 +30,27 @@ | ||
| 39 | #include <new> | ||
| 40 | #include <ext/atomicity.h> | ||
| 41 | #include <ext/concurrence.h> | ||
| 42 | +#if defined __i386__ && !defined _GLIBCXX_ATOMIC_BUILTINS | ||
| 43 | +# define _GLIBCXX_ATOMIC_BUILTINS 1 | ||
| 44 | +# define __sync_val_compare_and_swap(a, b, c) \ | ||
| 45 | + ({ \ | ||
| 46 | + typedef char sltast[sizeof (*a) == sizeof (int) ? 1 : -1]; \ | ||
| 47 | + int sltas; \ | ||
| 48 | + __asm __volatile ("lock; cmpxchgl %3, (%1)" \ | ||
| 49 | + : "=a" (sltas) \ | ||
| 50 | + : "r" (a), "0" (b), "r" (c) : "memory"); \ | ||
| 51 | + sltas; \ | ||
| 52 | + }) | ||
| 53 | +# define __sync_lock_test_and_set(a, b) \ | ||
| 54 | + ({ \ | ||
| 55 | + typedef char sltast[sizeof (*a) == sizeof (int) ? 1 : -1]; \ | ||
| 56 | + int sltas; \ | ||
| 57 | + __asm __volatile ("xchgl (%1), %0" \ | ||
| 58 | + : "=r" (sltas) \ | ||
| 59 | + : "r" (a), "0" (b) : "memory"); \ | ||
| 60 | + sltas; \ | ||
| 61 | + }) | ||
| 62 | +#endif | ||
| 63 | #if defined(__GTHREADS) && defined(__GTHREAD_HAS_COND) \ | ||
| 64 | && defined(_GLIBCXX_ATOMIC_BUILTINS_4) && defined(_GLIBCXX_HAVE_LINUX_FUTEX) | ||
| 65 | # include <climits> | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ia64-libunwind.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ia64-libunwind.patch deleted file mode 100644 index cad13d122..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ia64-libunwind.patch +++ /dev/null | |||
| @@ -1,550 +0,0 @@ | |||
| 1 | 2004-11-27 Jakub Jelinek <jakub@redhat.com> | ||
| 2 | |||
| 3 | * config.gcc (ia64*-*-linux*): If native and libelf is installed, | ||
| 4 | use ia64/t-glibc-no-libunwind instead of the other t-*unwind* | ||
| 5 | fragments. | ||
| 6 | * config/ia64/t-glibc-no-libunwind: New file. | ||
| 7 | * config/ia64/change-symver.c: New file. | ||
| 8 | * config/ia64/unwind-ia64.c: If USE_SYMVER_GLOBAL and SHARED, | ||
| 9 | define _Unwind_* to __symverglobal_Unwind_*. | ||
| 10 | (alias): Undefine. | ||
| 11 | (symverglobal): Define. Use it on _Unwind_*. | ||
| 12 | * config/ia64/mkmap-symver-multi.awk: New file. | ||
| 13 | * config/ia64/libgcc-ia64-no-libunwind.ver: New file. | ||
| 14 | |||
| 15 | Index: gcc/config.gcc | ||
| 16 | =================================================================== | ||
| 17 | --- gcc/config.gcc.orig 2010-04-07 03:34:00.000000000 -0700 | ||
| 18 | +++ gcc/config.gcc 2010-06-25 10:15:25.133131055 -0700 | ||
| 19 | @@ -1457,9 +1457,16 @@ | ||
| 20 | ;; | ||
| 21 | ia64*-*-linux*) | ||
| 22 | tm_file="${tm_file} dbxelf.h elfos.h svr4.h linux.h glibc-stdint.h ia64/sysv4.h ia64/linux.h" | ||
| 23 | - tmake_file="${tmake_file} ia64/t-ia64 t-libunwind ia64/t-glibc" | ||
| 24 | - if test x$with_system_libunwind != xyes ; then | ||
| 25 | - tmake_file="${tmake_file} t-libunwind-elf ia64/t-glibc-libunwind" | ||
| 26 | + tmake_file="${tmake_file} ia64/t-ia64" | ||
| 27 | + if test x${target} = x${host} && test x${target} = x${build} \ | ||
| 28 | + && grep gelf_getverdef /usr/include/gelf.h > /dev/null 2>&1 \ | ||
| 29 | + && test -f /usr/lib/libelf.so; then | ||
| 30 | + tmake_file="${tmake_file} ia64/t-glibc-no-libunwind" | ||
| 31 | + else | ||
| 32 | + tmake_file="${tmake_file} t-libunwind ia64/t-glibc" | ||
| 33 | + if test x$with_system_libunwind != xyes ; then | ||
| 34 | + tmake_file="${tmake_file} t-libunwind-elf ia64/t-glibc-libunwind" | ||
| 35 | + fi | ||
| 36 | fi | ||
| 37 | target_cpu_default="MASK_GNU_AS|MASK_GNU_LD" | ||
| 38 | extra_parts="crtbegin.o crtend.o crtbeginS.o crtendS.o crtfastmath.o" | ||
| 39 | Index: gcc/config/ia64/t-glibc-no-libunwind | ||
| 40 | =================================================================== | ||
| 41 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 42 | +++ gcc/config/ia64/t-glibc-no-libunwind 2010-06-25 10:14:32.521880765 -0700 | ||
| 43 | @@ -0,0 +1,30 @@ | ||
| 44 | +# Don't use system libunwind library on IA-64 GLIBC based system, | ||
| 45 | +# but make _Unwind_* symbols unversioned, so that created programs | ||
| 46 | +# are usable even when libgcc_s uses libunwind. | ||
| 47 | +LIB2ADDEH += $(srcdir)/config/ia64/fde-glibc.c | ||
| 48 | +SHLIB_MAPFILES += $(srcdir)/config/ia64/libgcc-ia64-no-libunwind.ver | ||
| 49 | +SHLIB_MKMAP = $(srcdir)/config/ia64/mkmap-symver-multi.awk | ||
| 50 | + | ||
| 51 | +SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \ | ||
| 52 | + -Wl,--soname=$(SHLIB_SONAME) \ | ||
| 53 | + -Wl,--version-script=$(SHLIB_MAP) \ | ||
| 54 | + -o $(SHLIB_DIR)/$(SHLIB_SONAME).tmp @multilib_flags@ $(SHLIB_OBJS) -lc && \ | ||
| 55 | + rm -f $(SHLIB_DIR)/$(SHLIB_SOLINK) && \ | ||
| 56 | + if [ -f $(SHLIB_DIR)/$(SHLIB_SONAME) ]; then \ | ||
| 57 | + mv -f $(SHLIB_DIR)/$(SHLIB_SONAME) \ | ||
| 58 | + $(SHLIB_DIR)/$(SHLIB_SONAME).backup; \ | ||
| 59 | + else true; fi && \ | ||
| 60 | + gcc -O2 -o $(SHLIB_DIR)/$(SHLIB_SONAME).tweak \ | ||
| 61 | + $$(gcc_srcdir)/config/ia64/change-symver.c -lelf && \ | ||
| 62 | + $(SHLIB_DIR)/$(SHLIB_SONAME).tweak $(SHLIB_DIR)/$(SHLIB_SONAME).tmp \ | ||
| 63 | + GCC_3.4.2 _GLOBAL_ \ | ||
| 64 | + _Unwind_GetGR _Unwind_RaiseException _Unwind_GetRegionStart _Unwind_SetIP \ | ||
| 65 | + _Unwind_GetIP _Unwind_GetLanguageSpecificData _Unwind_Resume \ | ||
| 66 | + _Unwind_DeleteException _Unwind_SetGR _Unwind_ForcedUnwind \ | ||
| 67 | + _Unwind_Backtrace _Unwind_FindEnclosingFunction _Unwind_GetCFA \ | ||
| 68 | + _Unwind_Resume_or_Rethrow _Unwind_GetBSP && \ | ||
| 69 | + rm -f $(SHLIB_DIR)/$(SHLIB_SONAME).tweak && \ | ||
| 70 | + mv $(SHLIB_DIR)/$(SHLIB_SONAME).tmp $(SHLIB_DIR)/$(SHLIB_SONAME) && \ | ||
| 71 | + $(LN_S) $(SHLIB_SONAME) $(SHLIB_DIR)/$(SHLIB_SOLINK) | ||
| 72 | + | ||
| 73 | +TARGET_LIBGCC2_CFLAGS += -DUSE_SYMVER_GLOBAL | ||
| 74 | Index: gcc/config/ia64/change-symver.c | ||
| 75 | =================================================================== | ||
| 76 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 77 | +++ gcc/config/ia64/change-symver.c 2010-06-25 10:14:32.521880765 -0700 | ||
| 78 | @@ -0,0 +1,211 @@ | ||
| 79 | +#define _GNU_SOURCE 1 | ||
| 80 | +#define _FILE_OFFSET_BITS 64 | ||
| 81 | +#include <endian.h> | ||
| 82 | +#include <errno.h> | ||
| 83 | +#include <error.h> | ||
| 84 | +#include <fcntl.h> | ||
| 85 | +#include <fnmatch.h> | ||
| 86 | +#include <gelf.h> | ||
| 87 | +#include <stdlib.h> | ||
| 88 | +#include <string.h> | ||
| 89 | +#include <unistd.h> | ||
| 90 | + | ||
| 91 | +int | ||
| 92 | +compute_veridx (const char *name, Elf *elf, Elf_Data *verd, GElf_Shdr *verd_shdr) | ||
| 93 | +{ | ||
| 94 | + if (strcmp (name, "_GLOBAL_") == 0) | ||
| 95 | + return 1; | ||
| 96 | + | ||
| 97 | + int cnt; | ||
| 98 | + size_t offset = 0; | ||
| 99 | + for (cnt = verd_shdr->sh_info; --cnt >= 0; ) | ||
| 100 | + { | ||
| 101 | + GElf_Verdef defmem; | ||
| 102 | + GElf_Verdef *def; | ||
| 103 | + GElf_Verdaux auxmem; | ||
| 104 | + GElf_Verdaux *aux; | ||
| 105 | + unsigned int auxoffset; | ||
| 106 | + | ||
| 107 | + /* Get the data at the next offset. */ | ||
| 108 | + def = gelf_getverdef (verd, offset, &defmem); | ||
| 109 | + if (def == NULL) | ||
| 110 | + break; | ||
| 111 | + | ||
| 112 | + auxoffset = offset + def->vd_aux; | ||
| 113 | + aux = gelf_getverdaux (verd, auxoffset, &auxmem); | ||
| 114 | + if (aux == NULL) | ||
| 115 | + break; | ||
| 116 | + | ||
| 117 | + if (strcmp (name, elf_strptr (elf, verd_shdr->sh_link, | ||
| 118 | + aux->vda_name)) == 0) | ||
| 119 | + return def->vd_ndx; | ||
| 120 | + | ||
| 121 | + /* Find the next offset. */ | ||
| 122 | + offset += def->vd_next; | ||
| 123 | + } | ||
| 124 | + | ||
| 125 | + return -1; | ||
| 126 | +} | ||
| 127 | + | ||
| 128 | +int | ||
| 129 | +main (int argc, char **argv) | ||
| 130 | +{ | ||
| 131 | + if (argc < 4) | ||
| 132 | + error (1, 0, "Usage: change_symver library from_symver to_symver symbol...\nExample: change_symver libfoo.so FOO_1.0 *global* bar baz"); | ||
| 133 | + | ||
| 134 | + const char *fname = argv[1]; | ||
| 135 | + | ||
| 136 | + /* Open the file. */ | ||
| 137 | + int fd; | ||
| 138 | + fd = open (fname, O_RDWR); | ||
| 139 | + if (fd == -1) | ||
| 140 | + error (1, errno, fname); | ||
| 141 | + | ||
| 142 | + elf_version (EV_CURRENT); | ||
| 143 | + | ||
| 144 | + /* Now get the ELF descriptor. */ | ||
| 145 | + Elf *elf = elf_begin (fd, ELF_C_READ_MMAP, NULL); | ||
| 146 | + if (elf == NULL || elf_kind (elf) != ELF_K_ELF) | ||
| 147 | + error (1, 0, "Couldn't open %s: %s", fname, elf_errmsg (-1)); | ||
| 148 | + | ||
| 149 | + size_t shstrndx; | ||
| 150 | + /* Get the section header string table index. */ | ||
| 151 | + if (elf_getshstrndx (elf, &shstrndx) < 0) | ||
| 152 | + error (1, 0, "cannot get shstrndx from %s", fname); | ||
| 153 | + | ||
| 154 | + GElf_Ehdr ehdr_mem; | ||
| 155 | + GElf_Ehdr *ehdr; | ||
| 156 | + | ||
| 157 | + /* We need the ELF header in a few places. */ | ||
| 158 | + ehdr = gelf_getehdr (elf, &ehdr_mem); | ||
| 159 | + if (ehdr == NULL) | ||
| 160 | + error (1, 0, "couldn't get ELF headers %s: %s", fname, elf_errmsg (-1)); | ||
| 161 | + | ||
| 162 | + Elf_Scn *scn = NULL; | ||
| 163 | + GElf_Shdr shdr_mem, verd_shdr, ver_shdr, dynsym_shdr; | ||
| 164 | + Elf_Data *ver = NULL, *verd = NULL, *dynsym = NULL; | ||
| 165 | + | ||
| 166 | + while ((scn = elf_nextscn (elf, scn)) != NULL) | ||
| 167 | + { | ||
| 168 | + GElf_Shdr *shdr = gelf_getshdr (scn, &shdr_mem); | ||
| 169 | + | ||
| 170 | + if (shdr == NULL) | ||
| 171 | + error (1, 0, "couldn't get shdr from %s", fname); | ||
| 172 | + | ||
| 173 | + if ((shdr->sh_flags & SHF_ALLOC) != 0) | ||
| 174 | + { | ||
| 175 | + const char *name = elf_strptr (elf, shstrndx, shdr->sh_name); | ||
| 176 | + Elf_Data **p; | ||
| 177 | + | ||
| 178 | + if (strcmp (name, ".gnu.version") == 0) | ||
| 179 | + { | ||
| 180 | + p = &ver; | ||
| 181 | + ver_shdr = *shdr; | ||
| 182 | + } | ||
| 183 | + else if (strcmp (name, ".gnu.version_d") == 0) | ||
| 184 | + { | ||
| 185 | + p = &verd; | ||
| 186 | + verd_shdr = *shdr; | ||
| 187 | + } | ||
| 188 | + else if (strcmp (name, ".dynsym") == 0) | ||
| 189 | + { | ||
| 190 | + p = &dynsym; | ||
| 191 | + dynsym_shdr = *shdr; | ||
| 192 | + } | ||
| 193 | + else | ||
| 194 | + continue; | ||
| 195 | + | ||
| 196 | + if (*p != NULL) | ||
| 197 | + error (1, 0, "Two %s sections in %s", name, fname); | ||
| 198 | + *p = elf_getdata (scn, NULL); | ||
| 199 | + if (*p == NULL || elf_getdata (scn, *p) != NULL) | ||
| 200 | + error (1, 0, "No data or non-contiguous data in %s section in %s", | ||
| 201 | + name, fname); | ||
| 202 | + } | ||
| 203 | + } | ||
| 204 | + | ||
| 205 | + if (ver == NULL || verd == NULL || dynsym == NULL) | ||
| 206 | + error (1, 0, "Couldn't find one of the needed sections in %s", fname); | ||
| 207 | + | ||
| 208 | + int from_idx = compute_veridx (argv[2], elf, verd, &verd_shdr); | ||
| 209 | + if (from_idx == -1) | ||
| 210 | + error (1, 0, "Could not find symbol version %s in %s", argv[2], fname); | ||
| 211 | + | ||
| 212 | + int to_idx = compute_veridx (argv[3], elf, verd, &verd_shdr); | ||
| 213 | + if (to_idx == -1) | ||
| 214 | + error (1, 0, "Could not find symbol version %s in %s", argv[3], fname); | ||
| 215 | + | ||
| 216 | + if (dynsym_shdr.sh_entsize != gelf_fsize (elf, ELF_T_SYM, 1, ehdr->e_version) | ||
| 217 | + || dynsym_shdr.sh_size % dynsym_shdr.sh_entsize | ||
| 218 | + || ver_shdr.sh_entsize != 2 | ||
| 219 | + || (ver_shdr.sh_size & 1) | ||
| 220 | + || dynsym_shdr.sh_size / dynsym_shdr.sh_entsize != ver_shdr.sh_size / 2) | ||
| 221 | + error (1, 0, "Unexpected sh_size or sh_entsize in %s", fname); | ||
| 222 | + | ||
| 223 | + size_t nentries = ver_shdr.sh_size / 2; | ||
| 224 | + size_t cnt; | ||
| 225 | + GElf_Versym array[nentries]; | ||
| 226 | + for (cnt = 0; cnt < nentries; ++cnt) | ||
| 227 | + { | ||
| 228 | + GElf_Versym vsymmem; | ||
| 229 | + GElf_Versym *vsym; | ||
| 230 | + | ||
| 231 | + vsym = gelf_getversym (ver, cnt, &vsymmem); | ||
| 232 | + if (vsym == NULL) | ||
| 233 | + error (1, 0, "gelt_getversym failed in %s: %s", fname, elf_errmsg (-1)); | ||
| 234 | + | ||
| 235 | + array[cnt] = *vsym; | ||
| 236 | + if (*vsym != from_idx) | ||
| 237 | + continue; | ||
| 238 | + | ||
| 239 | + GElf_Sym sym_mem; | ||
| 240 | + GElf_Sym *sym; | ||
| 241 | + sym = gelf_getsym (dynsym, cnt, &sym_mem); | ||
| 242 | + if (sym == NULL) | ||
| 243 | + error (1, 0, "gelt_getsym failed in %s: %s", fname, elf_errmsg (-1)); | ||
| 244 | + | ||
| 245 | + const char *name = elf_strptr (elf, dynsym_shdr.sh_link, sym->st_name); | ||
| 246 | + | ||
| 247 | + int argn; | ||
| 248 | + for (argn = 4; argn < argc; ++argn) | ||
| 249 | + if (fnmatch (argv[argn], name, 0) == 0) | ||
| 250 | + { | ||
| 251 | + array[cnt] = to_idx; | ||
| 252 | + break; | ||
| 253 | + } | ||
| 254 | + } | ||
| 255 | + | ||
| 256 | + if (sizeof (array[0]) != 2) | ||
| 257 | + abort (); | ||
| 258 | + | ||
| 259 | +#if __BYTE_ORDER == __LITTLE_ENDIAN | ||
| 260 | + if (ehdr->e_ident[EI_DATA] == ELFDATA2LSB) | ||
| 261 | + ; | ||
| 262 | + else if (ehdr->e_ident[EI_DATA] == ELFDATA2MSB) | ||
| 263 | +#elif __BYTE_ORDER == __BIG_ENDIAN | ||
| 264 | + if (ehdr->e_ident[EI_DATA] == ELFDATA2MSB) | ||
| 265 | + ; | ||
| 266 | + else if (ehdr->e_ident[EI_DATA] == ELFDATA2LSB) | ||
| 267 | +#else | ||
| 268 | +# error Unsupported endianity | ||
| 269 | +#endif | ||
| 270 | + { | ||
| 271 | + for (cnt = 0; cnt < nentries; ++cnt) | ||
| 272 | + array[cnt] = ((array[cnt] & 0xff) << 8) | ((array[cnt] & 0xff00) >> 8); | ||
| 273 | + } | ||
| 274 | + else | ||
| 275 | + error (1, 0, "Unknown EI_DATA %d in %s", ehdr->e_ident[EI_DATA], fname); | ||
| 276 | + | ||
| 277 | + if (elf_end (elf) != 0) | ||
| 278 | + error (1, 0, "couldn't close %s: %s", fname, elf_errmsg (-1)); | ||
| 279 | + | ||
| 280 | + if (lseek (fd, ver_shdr.sh_offset, SEEK_SET) != (off_t) ver_shdr.sh_offset) | ||
| 281 | + error (1, 0, "failed to seek to %zd in %s", (size_t) ver_shdr.sh_offset, | ||
| 282 | + fname); | ||
| 283 | + | ||
| 284 | + if (write (fd, array, 2 * nentries) != (ssize_t) (2 * nentries)) | ||
| 285 | + error (1, 0, "failed to write .gnu.version section into %s", fname); | ||
| 286 | + | ||
| 287 | + close (fd); | ||
| 288 | + return 0; | ||
| 289 | +} | ||
| 290 | Index: gcc/config/ia64/unwind-ia64.c | ||
| 291 | =================================================================== | ||
| 292 | --- gcc/config/ia64/unwind-ia64.c.orig 2009-09-07 08:41:52.000000000 -0700 | ||
| 293 | +++ gcc/config/ia64/unwind-ia64.c 2010-06-25 10:14:32.521880765 -0700 | ||
| 294 | @@ -48,6 +48,51 @@ | ||
| 295 | #define MD_UNW_COMPATIBLE_PERSONALITY_P(HEADER) 1 | ||
| 296 | #endif | ||
| 297 | |||
| 298 | +#if defined (USE_SYMVER_GLOBAL) && defined (SHARED) | ||
| 299 | +extern _Unwind_Reason_Code __symverglobal_Unwind_Backtrace | ||
| 300 | + (_Unwind_Trace_Fn, void *); | ||
| 301 | +extern void __symverglobal_Unwind_DeleteException | ||
| 302 | + (struct _Unwind_Exception *); | ||
| 303 | +extern void * __symverglobal_Unwind_FindEnclosingFunction (void *); | ||
| 304 | +extern _Unwind_Reason_Code __symverglobal_Unwind_ForcedUnwind | ||
| 305 | + (struct _Unwind_Exception *, _Unwind_Stop_Fn, void *); | ||
| 306 | +extern _Unwind_Word __symverglobal_Unwind_GetCFA | ||
| 307 | + (struct _Unwind_Context *); | ||
| 308 | +extern _Unwind_Word __symverglobal_Unwind_GetBSP | ||
| 309 | + (struct _Unwind_Context *); | ||
| 310 | +extern _Unwind_Word __symverglobal_Unwind_GetGR | ||
| 311 | + (struct _Unwind_Context *, int ); | ||
| 312 | +extern _Unwind_Ptr __symverglobal_Unwind_GetIP (struct _Unwind_Context *); | ||
| 313 | +extern void *__symverglobal_Unwind_GetLanguageSpecificData | ||
| 314 | + (struct _Unwind_Context *); | ||
| 315 | +extern _Unwind_Ptr __symverglobal_Unwind_GetRegionStart | ||
| 316 | + (struct _Unwind_Context *); | ||
| 317 | +extern _Unwind_Reason_Code __symverglobal_Unwind_RaiseException | ||
| 318 | + (struct _Unwind_Exception *); | ||
| 319 | +extern void __symverglobal_Unwind_Resume (struct _Unwind_Exception *); | ||
| 320 | +extern _Unwind_Reason_Code __symverglobal_Unwind_Resume_or_Rethrow | ||
| 321 | + (struct _Unwind_Exception *); | ||
| 322 | +extern void __symverglobal_Unwind_SetGR | ||
| 323 | + (struct _Unwind_Context *, int, _Unwind_Word); | ||
| 324 | +extern void __symverglobal_Unwind_SetIP | ||
| 325 | + (struct _Unwind_Context *, _Unwind_Ptr); | ||
| 326 | +#define _Unwind_Backtrace __symverglobal_Unwind_Backtrace | ||
| 327 | +#define _Unwind_DeleteException __symverglobal_Unwind_DeleteException | ||
| 328 | +#define _Unwind_FindEnclosingFunction __symverglobal_Unwind_FindEnclosingFunction | ||
| 329 | +#define _Unwind_ForcedUnwind __symverglobal_Unwind_ForcedUnwind | ||
| 330 | +#define _Unwind_GetBSP __symverglobal_Unwind_GetBSP | ||
| 331 | +#define _Unwind_GetCFA __symverglobal_Unwind_GetCFA | ||
| 332 | +#define _Unwind_GetGR __symverglobal_Unwind_GetGR | ||
| 333 | +#define _Unwind_GetIP __symverglobal_Unwind_GetIP | ||
| 334 | +#define _Unwind_GetLanguageSpecificData __symverglobal_Unwind_GetLanguageSpecificData | ||
| 335 | +#define _Unwind_GetRegionStart __symverglobal_Unwind_GetRegionStart | ||
| 336 | +#define _Unwind_RaiseException __symverglobal_Unwind_RaiseException | ||
| 337 | +#define _Unwind_Resume __symverglobal_Unwind_Resume | ||
| 338 | +#define _Unwind_Resume_or_Rethrow __symverglobal_Unwind_Resume_or_Rethrow | ||
| 339 | +#define _Unwind_SetGR __symverglobal_Unwind_SetGR | ||
| 340 | +#define _Unwind_SetIP __symverglobal_Unwind_SetIP | ||
| 341 | +#endif | ||
| 342 | + | ||
| 343 | enum unw_application_register | ||
| 344 | { | ||
| 345 | UNW_AR_BSP, | ||
| 346 | @@ -2457,4 +2502,44 @@ | ||
| 347 | alias (_Unwind_SetIP); | ||
| 348 | #endif | ||
| 349 | |||
| 350 | +#if defined (USE_SYMVER_GLOBAL) && defined (SHARED) | ||
| 351 | +#undef alias | ||
| 352 | +#define symverglobal(name, version) \ | ||
| 353 | +__typeof (__symverglobal##name) __symverlocal##name \ | ||
| 354 | + __attribute__ ((alias ("__symverglobal" #name))); \ | ||
| 355 | +__asm__ (".symver __symverglobal" #name"," #name "@@GCC_3.4.2");\ | ||
| 356 | +__asm__ (".symver __symverlocal" #name"," #name "@" #version) | ||
| 357 | + | ||
| 358 | +#undef _Unwind_Backtrace | ||
| 359 | +#undef _Unwind_DeleteException | ||
| 360 | +#undef _Unwind_FindEnclosingFunction | ||
| 361 | +#undef _Unwind_ForcedUnwind | ||
| 362 | +#undef _Unwind_GetBSP | ||
| 363 | +#undef _Unwind_GetCFA | ||
| 364 | +#undef _Unwind_GetGR | ||
| 365 | +#undef _Unwind_GetIP | ||
| 366 | +#undef _Unwind_GetLanguageSpecificData | ||
| 367 | +#undef _Unwind_GetRegionStart | ||
| 368 | +#undef _Unwind_RaiseException | ||
| 369 | +#undef _Unwind_Resume | ||
| 370 | +#undef _Unwind_Resume_or_Rethrow | ||
| 371 | +#undef _Unwind_SetGR | ||
| 372 | +#undef _Unwind_SetIP | ||
| 373 | +symverglobal (_Unwind_Backtrace, GCC_3.3); | ||
| 374 | +symverglobal (_Unwind_DeleteException, GCC_3.0); | ||
| 375 | +symverglobal (_Unwind_FindEnclosingFunction, GCC_3.3); | ||
| 376 | +symverglobal (_Unwind_ForcedUnwind, GCC_3.0); | ||
| 377 | +symverglobal (_Unwind_GetBSP, GCC_3.3.2); | ||
| 378 | +symverglobal (_Unwind_GetCFA, GCC_3.3); | ||
| 379 | +symverglobal (_Unwind_GetGR, GCC_3.0); | ||
| 380 | +symverglobal (_Unwind_GetIP, GCC_3.0); | ||
| 381 | +symverglobal (_Unwind_GetLanguageSpecificData, GCC_3.0); | ||
| 382 | +symverglobal (_Unwind_GetRegionStart, GCC_3.0); | ||
| 383 | +symverglobal (_Unwind_RaiseException, GCC_3.0); | ||
| 384 | +symverglobal (_Unwind_Resume, GCC_3.0); | ||
| 385 | +symverglobal (_Unwind_Resume_or_Rethrow, GCC_3.3); | ||
| 386 | +symverglobal (_Unwind_SetGR, GCC_3.0); | ||
| 387 | +symverglobal (_Unwind_SetIP, GCC_3.0); | ||
| 388 | +#endif | ||
| 389 | + | ||
| 390 | #endif | ||
| 391 | Index: gcc/config/ia64/mkmap-symver-multi.awk | ||
| 392 | =================================================================== | ||
| 393 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 394 | +++ gcc/config/ia64/mkmap-symver-multi.awk 2010-06-25 10:14:32.521880765 -0700 | ||
| 395 | @@ -0,0 +1,133 @@ | ||
| 396 | +# Generate an ELF symbol version map a-la Solaris and GNU ld. | ||
| 397 | +# Contributed by Richard Henderson <rth@cygnus.com> | ||
| 398 | +# | ||
| 399 | +# This file is part of GCC. | ||
| 400 | +# | ||
| 401 | +# GCC is free software; you can redistribute it and/or modify it under | ||
| 402 | +# the terms of the GNU General Public License as published by the Free | ||
| 403 | +# Software Foundation; either version 2, or (at your option) any later | ||
| 404 | +# version. | ||
| 405 | +# | ||
| 406 | +# GCC is distributed in the hope that it will be useful, but WITHOUT | ||
| 407 | +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
| 408 | +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | ||
| 409 | +# License for more details. | ||
| 410 | +# | ||
| 411 | +# You should have received a copy of the GNU General Public License | ||
| 412 | +# along with GCC; see the file COPYING. If not, write to the Free | ||
| 413 | +# Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA | ||
| 414 | +# 02110-1301, USA. | ||
| 415 | + | ||
| 416 | +BEGIN { | ||
| 417 | + state = "nm"; | ||
| 418 | + sawsymbol = 0; | ||
| 419 | +} | ||
| 420 | + | ||
| 421 | +# Remove comment and blank lines. | ||
| 422 | +/^ *#/ || /^ *$/ { | ||
| 423 | + next; | ||
| 424 | +} | ||
| 425 | + | ||
| 426 | +# We begin with nm input. Collect the set of symbols that are present | ||
| 427 | +# so that we can not emit them into the final version script -- Solaris | ||
| 428 | +# complains at us if we do. | ||
| 429 | + | ||
| 430 | +state == "nm" && /^%%/ { | ||
| 431 | + state = "ver"; | ||
| 432 | + next; | ||
| 433 | +} | ||
| 434 | + | ||
| 435 | +state == "nm" && ($1 == "U" || $2 == "U") { | ||
| 436 | + next; | ||
| 437 | +} | ||
| 438 | + | ||
| 439 | +state == "nm" && NF == 3 { | ||
| 440 | + if ($3 ~ /^[^@]*@GCC_[0-9.]*$/) { | ||
| 441 | + def[$3] = 1 | ||
| 442 | + tl=$3 | ||
| 443 | + sub(/^.*@/,"",tl) | ||
| 444 | + ver[$3] = tl | ||
| 445 | + } else { | ||
| 446 | + sub(/@@?GCC_[0-9.]*$/,"",$3) | ||
| 447 | + def[$3] = 1; | ||
| 448 | + } | ||
| 449 | + sawsymbol = 1; | ||
| 450 | + next; | ||
| 451 | +} | ||
| 452 | + | ||
| 453 | +state == "nm" { | ||
| 454 | + next; | ||
| 455 | +} | ||
| 456 | + | ||
| 457 | +# Now we process a simplified variant of the Solaris symbol version | ||
| 458 | +# script. We have one symbol per line, no semicolons, simple markers | ||
| 459 | +# for beginning and ending each section, and %inherit markers for | ||
| 460 | +# describing version inheritence. A symbol may appear in more than | ||
| 461 | +# one symbol version, and the last seen takes effect. | ||
| 462 | + | ||
| 463 | +NF == 3 && $1 == "%inherit" { | ||
| 464 | + inherit[$2] = $3; | ||
| 465 | + next; | ||
| 466 | +} | ||
| 467 | + | ||
| 468 | +NF == 2 && $2 == "{" { | ||
| 469 | + libs[$1] = 1; | ||
| 470 | + thislib = $1; | ||
| 471 | + next; | ||
| 472 | +} | ||
| 473 | + | ||
| 474 | +$1 == "}" { | ||
| 475 | + thislib = ""; | ||
| 476 | + next; | ||
| 477 | +} | ||
| 478 | + | ||
| 479 | +{ | ||
| 480 | + ver[$1] = thislib; | ||
| 481 | + next; | ||
| 482 | +} | ||
| 483 | + | ||
| 484 | +END { | ||
| 485 | + if (!sawsymbol) | ||
| 486 | + { | ||
| 487 | + print "No symbols seen -- broken or mis-installed nm?" | "cat 1>&2"; | ||
| 488 | + exit 1; | ||
| 489 | + } | ||
| 490 | + for (l in libs) | ||
| 491 | + output(l); | ||
| 492 | +} | ||
| 493 | + | ||
| 494 | +function output(lib) { | ||
| 495 | + if (done[lib]) | ||
| 496 | + return; | ||
| 497 | + done[lib] = 1; | ||
| 498 | + if (inherit[lib]) | ||
| 499 | + output(inherit[lib]); | ||
| 500 | + | ||
| 501 | + empty=1 | ||
| 502 | + for (sym in ver) | ||
| 503 | + if ((ver[sym] == lib) && (sym in def)) | ||
| 504 | + { | ||
| 505 | + if (empty) | ||
| 506 | + { | ||
| 507 | + printf("%s {\n", lib); | ||
| 508 | + printf(" global:\n"); | ||
| 509 | + empty = 0; | ||
| 510 | + } | ||
| 511 | + symp = sym; | ||
| 512 | + sub(/@GCC_[0-9.]*$/,"",symp); | ||
| 513 | + printf("\t%s;\n", symp); | ||
| 514 | + if (dotsyms) | ||
| 515 | + printf("\t.%s;\n", symp); | ||
| 516 | + } | ||
| 517 | + | ||
| 518 | + if (empty) | ||
| 519 | + { | ||
| 520 | + for (l in libs) | ||
| 521 | + if (inherit[l] == lib) | ||
| 522 | + inherit[l] = inherit[lib]; | ||
| 523 | + } | ||
| 524 | + else if (inherit[lib]) | ||
| 525 | + printf("} %s;\n", inherit[lib]); | ||
| 526 | + else | ||
| 527 | + printf ("\n local:\n\t*;\n};\n"); | ||
| 528 | +} | ||
| 529 | Index: gcc/config/ia64/libgcc-ia64-no-libunwind.ver | ||
| 530 | =================================================================== | ||
| 531 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 532 | +++ gcc/config/ia64/libgcc-ia64-no-libunwind.ver 2010-06-25 10:14:32.525880902 -0700 | ||
| 533 | @@ -0,0 +1,17 @@ | ||
| 534 | +GCC_3.4.2 { | ||
| 535 | + _Unwind_GetGR | ||
| 536 | + _Unwind_RaiseException | ||
| 537 | + _Unwind_GetRegionStart | ||
| 538 | + _Unwind_SetIP | ||
| 539 | + _Unwind_GetIP | ||
| 540 | + _Unwind_GetLanguageSpecificData | ||
| 541 | + _Unwind_Resume | ||
| 542 | + _Unwind_DeleteException | ||
| 543 | + _Unwind_SetGR | ||
| 544 | + _Unwind_ForcedUnwind | ||
| 545 | + _Unwind_Backtrace | ||
| 546 | + _Unwind_FindEnclosingFunction | ||
| 547 | + _Unwind_GetCFA | ||
| 548 | + _Unwind_Resume_or_Rethrow | ||
| 549 | + _Unwind_GetBSP | ||
| 550 | +} | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-debug-iface-type.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-debug-iface-type.patch deleted file mode 100644 index de14a5001..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-debug-iface-type.patch +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | 2008-01-25 Jakub Jelinek <jakub@redhat.com> | ||
| 2 | |||
| 3 | * lang.c (java_classify_record): Revert 2007-12-20 change. | ||
| 4 | |||
| 5 | Index: gcc/java/lang.c | ||
| 6 | =================================================================== | ||
| 7 | --- gcc/java/lang.c.orig 2010-01-20 00:17:00.000000000 -0800 | ||
| 8 | +++ gcc/java/lang.c 2010-06-25 10:28:46.569383189 -0700 | ||
| 9 | @@ -881,9 +881,7 @@ | ||
| 10 | if (! CLASS_P (type)) | ||
| 11 | return RECORD_IS_STRUCT; | ||
| 12 | |||
| 13 | - /* ??? GDB does not support DW_TAG_interface_type as of December, | ||
| 14 | - 2007. Re-enable this at a later time. */ | ||
| 15 | - if (0 && CLASS_INTERFACE (TYPE_NAME (type))) | ||
| 16 | + if (CLASS_INTERFACE (TYPE_NAME (type))) | ||
| 17 | return RECORD_IS_INTERFACE; | ||
| 18 | |||
| 19 | return RECORD_IS_CLASS; | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-nomulti.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-nomulti.patch deleted file mode 100644 index 3cb10f3c2..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-nomulti.patch +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | Index: libjava/configure.ac | ||
| 2 | =================================================================== | ||
| 3 | --- libjava/configure.ac.orig 2010-03-21 12:41:37.000000000 -0700 | ||
| 4 | +++ libjava/configure.ac 2010-06-25 10:17:47.489886278 -0700 | ||
| 5 | @@ -139,6 +139,13 @@ | ||
| 6 | [allow rebuilding of .class and .h files])) | ||
| 7 | AM_CONDITIONAL(JAVA_MAINTAINER_MODE, test "$enable_java_maintainer_mode" = yes) | ||
| 8 | |||
| 9 | +AC_ARG_ENABLE(libjava-multilib, | ||
| 10 | + AS_HELP_STRING([--enable-libjava-multilib], [build libjava as multilib])) | ||
| 11 | +if test "$enable_libjava_multilib" = no; then | ||
| 12 | + multilib=no | ||
| 13 | + ac_configure_args="$ac_configure_args --disable-multilib" | ||
| 14 | +fi | ||
| 15 | + | ||
| 16 | # It may not be safe to run linking tests in AC_PROG_CC/AC_PROG_CXX. | ||
| 17 | GCC_NO_EXECUTABLES | ||
| 18 | |||
| 19 | Index: libjava/configure | ||
| 20 | =================================================================== | ||
| 21 | --- libjava/configure.orig 2010-04-02 11:18:06.000000000 -0700 | ||
| 22 | +++ libjava/configure 2010-06-25 10:17:47.516381209 -0700 | ||
| 23 | @@ -1609,6 +1609,8 @@ | ||
| 24 | default=yes | ||
| 25 | --enable-java-maintainer-mode | ||
| 26 | allow rebuilding of .class and .h files | ||
| 27 | + --enable-libjava-multilib | ||
| 28 | + build libjava as multilib | ||
| 29 | --disable-dependency-tracking speeds up one-time build | ||
| 30 | --enable-dependency-tracking do not reject slow dependency extractors | ||
| 31 | --enable-maintainer-mode enable make rules and dependencies not useful | ||
| 32 | @@ -3346,6 +3348,16 @@ | ||
| 33 | fi | ||
| 34 | |||
| 35 | |||
| 36 | +# Check whether --enable-libjava-multilib was given. | ||
| 37 | +if test "${enable_libjava_multilib+set}" = set; then | ||
| 38 | + enableval=$enable_libjava_multilib; | ||
| 39 | +fi | ||
| 40 | + | ||
| 41 | +if test "$enable_libjava_multilib" = no; then | ||
| 42 | + multilib=no | ||
| 43 | + ac_configure_args="$ac_configure_args --disable-multilib" | ||
| 44 | +fi | ||
| 45 | + | ||
| 46 | # It may not be safe to run linking tests in AC_PROG_CC/AC_PROG_CXX. | ||
| 47 | |||
| 48 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-libgomp-speedup.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-libgomp-speedup.patch deleted file mode 100644 index da85e556e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-libgomp-speedup.patch +++ /dev/null | |||
| @@ -1,2797 +0,0 @@ | |||
| 1 | 2008-03-28 Jakub Jelinek <jakub@redhat.com> | ||
| 2 | |||
| 3 | * config/linux/sparc/futex.h (atomic_write_barrier): Fix membar | ||
| 4 | argument. | ||
| 5 | |||
| 6 | 2008-03-27 Jakub Jelinek <jakub@redhat.com> | ||
| 7 | |||
| 8 | * libgomp.h (struct gomp_team_state): Remove single_count field | ||
| 9 | ifndef HAVE_SYNC_BUILTINS. | ||
| 10 | (struct gomp_team): Likewise. Add work_share_list_free_lock | ||
| 11 | ifndef HAVE_SYNC_BUILTINS. | ||
| 12 | * team.c (gomp_new_team): If HAVE_SYNC_BUILTINS is not defined, | ||
| 13 | don't initialize single_count, but instead initialize | ||
| 14 | work_share_list_free_lock. | ||
| 15 | (free_team): Destroy work_share_list_free_lock ifndef | ||
| 16 | HAVE_SYNC_BUILTINS. | ||
| 17 | (gomp_team_start): Don't initialize ts.single_count ifndef | ||
| 18 | HAVE_SYNC_BUILTINS. | ||
| 19 | * work.c (alloc_work_share, free_work_share): Use | ||
| 20 | work_share_list_free_lock instead of atomic chaining ifndef | ||
| 21 | HAVE_SYNC_BUILTINS. | ||
| 22 | |||
| 23 | 2008-03-26 Jakub Jelinek <jakub@redhat.com> | ||
| 24 | |||
| 25 | * loop.c (gomp_loop_init): Fix GFS_DYNAMIC ws->mode setting. | ||
| 26 | * testsuite/libgomp.c/loop-4.c: New test. | ||
| 27 | |||
| 28 | * libgomp.h (struct gomp_team_state): Add single_count field. | ||
| 29 | (struct gomp_team): Likewise. | ||
| 30 | * team.c (gomp_new_team): Clear single_count. | ||
| 31 | (gomp_team_start): Likewise. | ||
| 32 | * single.c (GOMP_single_start): Rewritten if HAVE_SYNC_BUILTINS. | ||
| 33 | |||
| 34 | 2008-03-25 Jakub Jelinek <jakub@redhat.com> | ||
| 35 | |||
| 36 | * team.c (gomp_thread_start): Don't clear ts.static_trip here. | ||
| 37 | * loop.c (gomp_loop_static_start, gomp_loop_dynamic_start): Clear | ||
| 38 | ts.static_trip here. | ||
| 39 | * work.c (gomp_work_share_start): Don't clear ts.static_trip here. | ||
| 40 | |||
| 41 | 2008-03-21 Jakub Jelinek <jakub@redhat.com> | ||
| 42 | |||
| 43 | * libgomp.h: Include ptrlock.h. | ||
| 44 | (struct gomp_work_share): Reshuffle fields. Add next_alloc, | ||
| 45 | next_ws, next_free and inline_ordered_team_ids fields, change | ||
| 46 | ordered_team_ids into pointer from flexible array member. | ||
| 47 | (struct gomp_team_state): Add last_work_share field, remove | ||
| 48 | work_share_generation. | ||
| 49 | (struct gomp_team): Remove work_share_lock, generation_mask, | ||
| 50 | oldest_live_gen, num_live_gen and init_work_shares fields, add | ||
| 51 | work work_share_list_alloc, work_share_list_free and work_share_chunk | ||
| 52 | fields. Change work_shares from pointer to pointers into an array. | ||
| 53 | (gomp_new_team): New prototype. | ||
| 54 | (gomp_team_start): Change type of last argument. | ||
| 55 | (gomp_new_work_share): Removed. | ||
| 56 | (gomp_init_work_share, gomp_fini_work_share): New prototypes. | ||
| 57 | (gomp_work_share_init_done): New static inline. | ||
| 58 | * team.c (gomp_thread_start): Clear ts.last_work_share, don't clear | ||
| 59 | ts.work_share_generation. | ||
| 60 | (new_team): Removed. | ||
| 61 | (gomp_new_team): New function. | ||
| 62 | (free_team): Free gomp_work_share blocks chained through next_alloc, | ||
| 63 | instead of freeing work_shares and destroying work_share_lock. | ||
| 64 | (gomp_team_start): Change last argument from ws to team, don't create | ||
| 65 | new team, set ts.work_share to &team->work_shares[0] and clear | ||
| 66 | ts.last_work_share. Don't clear ts.work_share_generation. | ||
| 67 | (gomp_team_end): Call gomp_fini_work_share. | ||
| 68 | * work.c (gomp_new_work_share): Removed. | ||
| 69 | (alloc_work_share, gomp_init_work_share, gomp_fini_work_share): New | ||
| 70 | functions. | ||
| 71 | (free_work_share): Add team argument. Call gomp_fini_work_share | ||
| 72 | and then either free ws if orphaned, or put it into | ||
| 73 | work_share_list_free list of the current team. | ||
| 74 | (gomp_work_share_start, gomp_work_share_end, | ||
| 75 | gomp_work_share_end_nowait): Rewritten. | ||
| 76 | * sections.c (GOMP_sections_start): Call gomp_work_share_init_done | ||
| 77 | after gomp_sections_init. If HAVE_SYNC_BUILTINS, call | ||
| 78 | gomp_iter_dynamic_next instead of the _locked variant and don't take | ||
| 79 | lock around it, otherwise acquire it before calling | ||
| 80 | gomp_iter_dynamic_next_locked. | ||
| 81 | (GOMP_sections_next): If HAVE_SYNC_BUILTINS, call | ||
| 82 | gomp_iter_dynamic_next instead of the _locked variant and don't take | ||
| 83 | lock around it. | ||
| 84 | (GOMP_parallel_sections_start): Call gomp_new_team instead of | ||
| 85 | gomp_new_work_share. Call gomp_sections_init on &team->work_shares[0]. | ||
| 86 | Adjust gomp_team_start caller. | ||
| 87 | * loop.c (gomp_loop_static_start, gomp_loop_ordered_static_start): Call | ||
| 88 | gomp_work_share_init_done after gomp_loop_init. Don't unlock ws->lock. | ||
| 89 | (gomp_loop_dynamic_start, gomp_loop_guided_start): Call | ||
| 90 | gomp_work_share_init_done after gomp_loop_init. If HAVE_SYNC_BUILTINS, | ||
| 91 | don't unlock ws->lock, otherwise lock it. | ||
| 92 | (gomp_loop_ordered_dynamic_start, gomp_loop_ordered_guided_start): Call | ||
| 93 | gomp_work_share_init_done after gomp_loop_init. Lock ws->lock. | ||
| 94 | (gomp_parallel_loop_start): Call gomp_new_team instead of | ||
| 95 | gomp_new_work_share. Call gomp_loop_init on &team->work_shares[0]. | ||
| 96 | Adjust gomp_team_start caller. | ||
| 97 | * single.c (GOMP_single_start, GOMP_single_copy_start): Call | ||
| 98 | gomp_work_share_init_done if gomp_work_share_start returned true. | ||
| 99 | Don't unlock ws->lock. | ||
| 100 | * parallel.c (GOMP_parallel_start): Call gomp_new_team and pass that | ||
| 101 | as last argument to gomp_team_start. | ||
| 102 | * config/linux/ptrlock.c: New file. | ||
| 103 | * config/linux/ptrlock.h: New file. | ||
| 104 | * config/posix/ptrlock.c: New file. | ||
| 105 | * config/posix/ptrlock.h: New file. | ||
| 106 | * Makefile.am (libgomp_la_SOURCES): Add ptrlock.c. | ||
| 107 | * Makefile.in: Regenerated. | ||
| 108 | * testsuite/Makefile.in: Regenerated. | ||
| 109 | |||
| 110 | 2008-03-19 Jakub Jelinek <jakub@redhat.com> | ||
| 111 | |||
| 112 | * libgomp.h (gomp_active_wait_policy): Remove decl. | ||
| 113 | (gomp_throttled_spin_count_var, gomp_available_cpus, | ||
| 114 | gomp_managed_threads): New extern decls. | ||
| 115 | * team.c (gomp_team_start, gomp_team_end): If number of threads | ||
| 116 | changed, adjust atomically gomp_managed_threads. | ||
| 117 | * env.c (gomp_active_wait_policy, gomp_block_time_var): Remove. | ||
| 118 | (gomp_throttled_spin_count_var, gomp_available_cpus, | ||
| 119 | gomp_managed_threads): New variables. | ||
| 120 | (parse_millis): Removed. | ||
| 121 | (parse_spincount): New function. | ||
| 122 | (parse_wait_policy): Return -1/0/1 instead of setting | ||
| 123 | gomp_active_wait_policy. | ||
| 124 | (initialize_env): Call gomp_init_num_threads unconditionally. | ||
| 125 | Initialize gomp_available_cpus. Call parse_spincount instead | ||
| 126 | of parse_millis, initialize gomp_{,throttled_}spin_count_var | ||
| 127 | depending on presence and value of OMP_WAIT_POLICY and | ||
| 128 | GOMP_SPINCOUNT env vars. | ||
| 129 | * config/linux/wait.h (do_wait): Use gomp_throttled_spin_count_var | ||
| 130 | instead of gomp_spin_count_var if gomp_managed_threads > | ||
| 131 | gomp_available_cpus. | ||
| 132 | |||
| 133 | * config/linux/wait.h: Include errno.h. | ||
| 134 | (FUTEX_WAIT, FUTEX_WAKE, FUTEX_PRIVATE_FLAG): Define. | ||
| 135 | (gomp_futex_wake, gomp_futex_wait): New extern decls. | ||
| 136 | * config/linux/mutex.c (gomp_futex_wake, gomp_futex_wait): New | ||
| 137 | variables. | ||
| 138 | * config/linux/powerpc/futex.h (FUTEX_WAIT, FUTEX_WAKE): Remove. | ||
| 139 | (sys_futex0): Return error code. | ||
| 140 | (futex_wake, futex_wait): If ENOSYS was returned, clear | ||
| 141 | FUTEX_PRIVATE_FLAG in gomp_futex_wa{ke,it} and retry. | ||
| 142 | * config/linux/alpha/futex.h (FUTEX_WAIT, FUTEX_WAKE): Remove. | ||
| 143 | (futex_wake, futex_wait): If ENOSYS was returned, clear | ||
| 144 | FUTEX_PRIVATE_FLAG in gomp_futex_wa{ke,it} and retry. | ||
| 145 | * config/linux/x86/futex.h (FUTEX_WAIT, FUTEX_WAKE): Remove. | ||
| 146 | (sys_futex0): Return error code. | ||
| 147 | (futex_wake, futex_wait): If ENOSYS was returned, clear | ||
| 148 | FUTEX_PRIVATE_FLAG in gomp_futex_wa{ke,it} and retry. | ||
| 149 | * config/linux/s390/futex.h (FUTEX_WAIT, FUTEX_WAKE): Remove. | ||
| 150 | (sys_futex0): Return error code. | ||
| 151 | (futex_wake, futex_wait): If ENOSYS was returned, clear | ||
| 152 | FUTEX_PRIVATE_FLAG in gomp_futex_wa{ke,it} and retry. | ||
| 153 | * config/linux/ia64/futex.h (FUTEX_WAIT, FUTEX_WAKE): Remove. | ||
| 154 | (sys_futex0): Return error code. | ||
| 155 | (futex_wake, futex_wait): If ENOSYS was returned, clear | ||
| 156 | FUTEX_PRIVATE_FLAG in gomp_futex_wa{ke,it} and retry. | ||
| 157 | * config/linux/sparc/futex.h (FUTEX_WAIT, FUTEX_WAKE): Remove. | ||
| 158 | (sys_futex0): Return error code. | ||
| 159 | (futex_wake, futex_wait): If ENOSYS was returned, clear | ||
| 160 | FUTEX_PRIVATE_FLAG in gomp_futex_wa{ke,it} and retry. | ||
| 161 | |||
| 162 | 2008-03-18 Jakub Jelinek <jakub@redhat.com> | ||
| 163 | |||
| 164 | * libgomp.h (struct gomp_work_share): Add mode field. Put lock and | ||
| 165 | next into a different cache line from most of the write-once fields. | ||
| 166 | * loop.c: Include limits.h. | ||
| 167 | (gomp_loop_init): For GFS_DYNAMIC, multiply ws->chunk_size by incr. | ||
| 168 | If adding ws->chunk_size nthreads + 1 times after end won't | ||
| 169 | overflow, set ws->mode to 1. | ||
| 170 | * iter.c (gomp_iter_dynamic_next_locked): Don't multiply | ||
| 171 | ws->chunk_size by incr. | ||
| 172 | (gomp_iter_dynamic_next): Likewise. If ws->mode, use more efficient | ||
| 173 | code. | ||
| 174 | * work.c: Include stddef.h. | ||
| 175 | (gomp_new_work_share): Use offsetof rather than sizeof. | ||
| 176 | |||
| 177 | 2008-03-17 Jakub Jelinek <jakub@redhat.com> | ||
| 178 | |||
| 179 | * libgomp.h (struct gomp_team): Change ordered_release field | ||
| 180 | into gomp_sem_t ** from flexible array member. Add implicit_task | ||
| 181 | and initial_work_shares fields. | ||
| 182 | (gomp_new_task): Removed. | ||
| 183 | (gomp_init_task): New prototype. | ||
| 184 | * team.c (new_team): Allocate implicit_task for each thread | ||
| 185 | and initial work_shares together with gomp_team allocation. | ||
| 186 | (free_team): Only free work_shares if it is not init_work_shares. | ||
| 187 | (gomp_team_start): Use gomp_init_task instead of gomp_new_task, | ||
| 188 | set thr->task to the corresponding implicit_task array entry. | ||
| 189 | * task.c (gomp_new_task): Removed. | ||
| 190 | (gomp_init_task): New function. | ||
| 191 | (gomp_end_task): Don't free the task. | ||
| 192 | (GOMP_task): Allocate struct gomp_task on the stack, call | ||
| 193 | gomp_init_task rather than gomp_new_task. | ||
| 194 | * work.c (gomp_work_share_start): If work_shares == | ||
| 195 | init_work_shares, gomp_malloc + memcpy rather than gomp_realloc. | ||
| 196 | |||
| 197 | 2008-03-15 Jakub Jelinek <jakub@redhat.com> | ||
| 198 | Ulrich Drepper <drepper@redhat.com> | ||
| 199 | |||
| 200 | * config/linux/bar.h (gomp_barrier_state_t): Rewritten. | ||
| 201 | (gomp_barrier_state_t): Change to unsigned int. | ||
| 202 | (gomp_barrier_init, gomp_barrier_reinit, gomp_barrier_destroy, | ||
| 203 | gomp_barrier_wait_start, gomp_barrier_last_thread): Rewritten. | ||
| 204 | (gomp_barrier_wait_last): Prototype rather than inline. | ||
| 205 | * config/linux/bar.c (gomp_barrier_wait_end): Rewritten. | ||
| 206 | (gomp_barrier_wait_last): New function. | ||
| 207 | |||
| 208 | 2008-03-15 Jakub Jelinek <jakub@redhat.com> | ||
| 209 | |||
| 210 | * team.c (gomp_thread_start): Use gomp_barrier_wait_last instead | ||
| 211 | of gomp_barrier_wait. | ||
| 212 | * env.c (gomp_block_time_var, gomp_spin_count_var): New variables. | ||
| 213 | (parse_millis): New function. | ||
| 214 | (initialize_env): Handle GOMP_BLOCKTIME env var. | ||
| 215 | * libgomp.h (struct gomp_team): Move close to the end of the struct. | ||
| 216 | (gomp_spin_count_var): New extern var decl. | ||
| 217 | * work.c (gomp_work_share_end): Use gomp_barrier_state_t bstate | ||
| 218 | var instead of bool last, call gomp_barrier_last_thread to check | ||
| 219 | for last thread, pass bstate to gomp_barrier_wait_end. | ||
| 220 | * config/linux/wait.h: New file. | ||
| 221 | * config/linux/mutex.c: Include wait.h instead of libgomp.h and | ||
| 222 | futex.h. | ||
| 223 | (gomp_mutex_lock_slow): Call do_wait instead of futex_wait. | ||
| 224 | * config/linux/bar.c: Include wait.h instead of libgomp.h and | ||
| 225 | futex.h. | ||
| 226 | (gomp_barrier_wait_end): Change second argument to | ||
| 227 | gomp_barrier_state_t. Call do_wait instead of futex_wait. | ||
| 228 | * config/linux/sem.c: Include wait.h instead of libgomp.h and | ||
| 229 | futex.h. | ||
| 230 | (gomp_sem_wait_slow): Call do_wait instead of futex_wait. | ||
| 231 | * config/linux/lock.c: Include wait.h instead of libgomp.h and | ||
| 232 | futex.h. | ||
| 233 | (gomp_set_nest_lock_25): Call do_wait instead of futex_wait. | ||
| 234 | * config/linux/affinity.c: Assume HAVE_SYNC_BUILTINS. | ||
| 235 | * config/linux/bar.h (gomp_barrier_state_t): New typedef. | ||
| 236 | (gomp_barrier_wait_end): Change second argument to | ||
| 237 | gomp_barrier_state_t. | ||
| 238 | (gomp_barrier_wait_start): Return gomp_barrier_state_t. | ||
| 239 | (gomp_barrier_last_thread, gomp_barrier_wait_last): New static | ||
| 240 | inlines. | ||
| 241 | * config/linux/powerpc/futex.h (cpu_relax, atomic_write_barrier): New | ||
| 242 | static inlines. | ||
| 243 | * config/linux/alpha/futex.h (cpu_relax, atomic_write_barrier): | ||
| 244 | Likewise. | ||
| 245 | * config/linux/x86/futex.h (cpu_relax, atomic_write_barrier): | ||
| 246 | Likewise. | ||
| 247 | * config/linux/s390/futex.h (cpu_relax, atomic_write_barrier): | ||
| 248 | Likewise. | ||
| 249 | * config/linux/ia64/futex.h (cpu_relax, atomic_write_barrier): | ||
| 250 | Likewise. | ||
| 251 | * config/linux/sparc/futex.h (cpu_relax, atomic_write_barrier): | ||
| 252 | Likewise. | ||
| 253 | * config/posix/bar.c (gomp_barrier_wait_end): Change second argument | ||
| 254 | to gomp_barrier_state_t. | ||
| 255 | * config/posix/bar.h (gomp_barrier_state_t): New typedef. | ||
| 256 | (gomp_barrier_wait_end): Change second argument to | ||
| 257 | gomp_barrier_state_t. | ||
| 258 | (gomp_barrier_wait_start): Return gomp_barrier_state_t. | ||
| 259 | (gomp_barrier_last_thread, gomp_barrier_wait_last): New static | ||
| 260 | inlines. | ||
| 261 | |||
| 262 | --- libgomp/parallel.c.jj 2007-12-07 14:41:01.000000000 +0100 | ||
| 263 | +++ libgomp/parallel.c 2008-03-26 15:32:06.000000000 +0100 | ||
| 264 | @@ -68,7 +68,7 @@ void | ||
| 265 | GOMP_parallel_start (void (*fn) (void *), void *data, unsigned num_threads) | ||
| 266 | { | ||
| 267 | num_threads = gomp_resolve_num_threads (num_threads); | ||
| 268 | - gomp_team_start (fn, data, num_threads, NULL); | ||
| 269 | + gomp_team_start (fn, data, num_threads, gomp_new_team (num_threads)); | ||
| 270 | } | ||
| 271 | |||
| 272 | void | ||
| 273 | --- libgomp/sections.c.jj 2007-12-07 14:41:01.000000000 +0100 | ||
| 274 | +++ libgomp/sections.c 2008-03-26 15:33:06.000000000 +0100 | ||
| 275 | @@ -59,14 +59,24 @@ GOMP_sections_start (unsigned count) | ||
| 276 | long s, e, ret; | ||
| 277 | |||
| 278 | if (gomp_work_share_start (false)) | ||
| 279 | - gomp_sections_init (thr->ts.work_share, count); | ||
| 280 | + { | ||
| 281 | + gomp_sections_init (thr->ts.work_share, count); | ||
| 282 | + gomp_work_share_init_done (); | ||
| 283 | + } | ||
| 284 | |||
| 285 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 286 | + if (gomp_iter_dynamic_next (&s, &e)) | ||
| 287 | + ret = s; | ||
| 288 | + else | ||
| 289 | + ret = 0; | ||
| 290 | +#else | ||
| 291 | + gomp_mutex_lock (&thr->ts.work_share->lock); | ||
| 292 | if (gomp_iter_dynamic_next_locked (&s, &e)) | ||
| 293 | ret = s; | ||
| 294 | else | ||
| 295 | ret = 0; | ||
| 296 | - | ||
| 297 | gomp_mutex_unlock (&thr->ts.work_share->lock); | ||
| 298 | +#endif | ||
| 299 | |||
| 300 | return ret; | ||
| 301 | } | ||
| 302 | @@ -83,15 +93,23 @@ GOMP_sections_start (unsigned count) | ||
| 303 | unsigned | ||
| 304 | GOMP_sections_next (void) | ||
| 305 | { | ||
| 306 | - struct gomp_thread *thr = gomp_thread (); | ||
| 307 | long s, e, ret; | ||
| 308 | |||
| 309 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 310 | + if (gomp_iter_dynamic_next (&s, &e)) | ||
| 311 | + ret = s; | ||
| 312 | + else | ||
| 313 | + ret = 0; | ||
| 314 | +#else | ||
| 315 | + struct gomp_thread *thr = gomp_thread (); | ||
| 316 | + | ||
| 317 | gomp_mutex_lock (&thr->ts.work_share->lock); | ||
| 318 | if (gomp_iter_dynamic_next_locked (&s, &e)) | ||
| 319 | ret = s; | ||
| 320 | else | ||
| 321 | ret = 0; | ||
| 322 | gomp_mutex_unlock (&thr->ts.work_share->lock); | ||
| 323 | +#endif | ||
| 324 | |||
| 325 | return ret; | ||
| 326 | } | ||
| 327 | @@ -103,15 +121,15 @@ void | ||
| 328 | GOMP_parallel_sections_start (void (*fn) (void *), void *data, | ||
| 329 | unsigned num_threads, unsigned count) | ||
| 330 | { | ||
| 331 | - struct gomp_work_share *ws; | ||
| 332 | + struct gomp_team *team; | ||
| 333 | |||
| 334 | num_threads = gomp_resolve_num_threads (num_threads); | ||
| 335 | if (gomp_dyn_var && num_threads > count) | ||
| 336 | num_threads = count; | ||
| 337 | |||
| 338 | - ws = gomp_new_work_share (false, num_threads); | ||
| 339 | - gomp_sections_init (ws, count); | ||
| 340 | - gomp_team_start (fn, data, num_threads, ws); | ||
| 341 | + team = gomp_new_team (num_threads); | ||
| 342 | + gomp_sections_init (&team->work_shares[0], count); | ||
| 343 | + gomp_team_start (fn, data, num_threads, team); | ||
| 344 | } | ||
| 345 | |||
| 346 | /* The GOMP_section_end* routines are called after the thread is told | ||
| 347 | --- libgomp/env.c.jj 2007-12-07 14:41:01.000000000 +0100 | ||
| 348 | +++ libgomp/env.c 2008-03-26 16:40:26.000000000 +0100 | ||
| 349 | @@ -44,6 +44,11 @@ enum gomp_schedule_type gomp_run_sched_v | ||
| 350 | unsigned long gomp_run_sched_chunk = 1; | ||
| 351 | unsigned short *gomp_cpu_affinity; | ||
| 352 | size_t gomp_cpu_affinity_len; | ||
| 353 | +#ifndef HAVE_SYNC_BUILTINS | ||
| 354 | +gomp_mutex_t gomp_remaining_threads_lock; | ||
| 355 | +#endif | ||
| 356 | +unsigned long gomp_available_cpus = 1, gomp_managed_threads = 1; | ||
| 357 | +unsigned long long gomp_spin_count_var, gomp_throttled_spin_count_var; | ||
| 358 | |||
| 359 | /* Parse the OMP_SCHEDULE environment variable. */ | ||
| 360 | |||
| 361 | @@ -147,6 +152,79 @@ parse_unsigned_long (const char *name, u | ||
| 362 | return false; | ||
| 363 | } | ||
| 364 | |||
| 365 | +/* Parse the GOMP_SPINCOUNT environment varible. Return true if one was | ||
| 366 | + present and it was successfully parsed. */ | ||
| 367 | + | ||
| 368 | +static bool | ||
| 369 | +parse_spincount (const char *name, unsigned long long *pvalue) | ||
| 370 | +{ | ||
| 371 | + char *env, *end; | ||
| 372 | + unsigned long long value, mult = 1; | ||
| 373 | + | ||
| 374 | + env = getenv (name); | ||
| 375 | + if (env == NULL) | ||
| 376 | + return false; | ||
| 377 | + | ||
| 378 | + while (isspace ((unsigned char) *env)) | ||
| 379 | + ++env; | ||
| 380 | + if (*env == '\0') | ||
| 381 | + goto invalid; | ||
| 382 | + | ||
| 383 | + if (strncasecmp (env, "infinite", 8) == 0 | ||
| 384 | + || strncasecmp (env, "infinity", 8) == 0) | ||
| 385 | + { | ||
| 386 | + value = ~0ULL; | ||
| 387 | + end = env + 8; | ||
| 388 | + goto check_tail; | ||
| 389 | + } | ||
| 390 | + | ||
| 391 | + errno = 0; | ||
| 392 | + value = strtoull (env, &end, 10); | ||
| 393 | + if (errno) | ||
| 394 | + goto invalid; | ||
| 395 | + | ||
| 396 | + while (isspace ((unsigned char) *end)) | ||
| 397 | + ++end; | ||
| 398 | + if (*end != '\0') | ||
| 399 | + { | ||
| 400 | + switch (tolower (*end)) | ||
| 401 | + { | ||
| 402 | + case 'k': | ||
| 403 | + mult = 1000LL; | ||
| 404 | + break; | ||
| 405 | + case 'm': | ||
| 406 | + mult = 1000LL * 1000LL; | ||
| 407 | + break; | ||
| 408 | + case 'g': | ||
| 409 | + mult = 1000LL * 1000LL * 1000LL; | ||
| 410 | + break; | ||
| 411 | + case 't': | ||
| 412 | + mult = 1000LL * 1000LL * 1000LL * 1000LL; | ||
| 413 | + break; | ||
| 414 | + default: | ||
| 415 | + goto invalid; | ||
| 416 | + } | ||
| 417 | + ++end; | ||
| 418 | + check_tail: | ||
| 419 | + while (isspace ((unsigned char) *end)) | ||
| 420 | + ++end; | ||
| 421 | + if (*end != '\0') | ||
| 422 | + goto invalid; | ||
| 423 | + } | ||
| 424 | + | ||
| 425 | + if (value > ~0ULL / mult) | ||
| 426 | + value = ~0ULL; | ||
| 427 | + else | ||
| 428 | + value *= mult; | ||
| 429 | + | ||
| 430 | + *pvalue = value; | ||
| 431 | + return true; | ||
| 432 | + | ||
| 433 | + invalid: | ||
| 434 | + gomp_error ("Invalid value for environment variable %s", name); | ||
| 435 | + return false; | ||
| 436 | +} | ||
| 437 | + | ||
| 438 | /* Parse a boolean value for environment variable NAME and store the | ||
| 439 | result in VALUE. */ | ||
| 440 | |||
| 441 | @@ -281,10 +359,25 @@ initialize_env (void) | ||
| 442 | parse_schedule (); | ||
| 443 | parse_boolean ("OMP_DYNAMIC", &gomp_dyn_var); | ||
| 444 | parse_boolean ("OMP_NESTED", &gomp_nest_var); | ||
| 445 | + gomp_init_num_threads (); | ||
| 446 | + gomp_available_cpus = gomp_nthreads_var; | ||
| 447 | if (!parse_unsigned_long ("OMP_NUM_THREADS", &gomp_nthreads_var)) | ||
| 448 | - gomp_init_num_threads (); | ||
| 449 | + gomp_nthreads_var = gomp_available_cpus; | ||
| 450 | if (parse_affinity ()) | ||
| 451 | gomp_init_affinity (); | ||
| 452 | + if (!parse_spincount ("GOMP_SPINCOUNT", &gomp_spin_count_var)) | ||
| 453 | + { | ||
| 454 | + /* Using a rough estimation of 100000 spins per msec, | ||
| 455 | + use 200 msec blocking. | ||
| 456 | + Depending on the CPU speed, this can be e.g. 5 times longer | ||
| 457 | + or 5 times shorter. */ | ||
| 458 | + gomp_spin_count_var = 20000000LL; | ||
| 459 | + } | ||
| 460 | + /* gomp_throttled_spin_count_var is used when there are more libgomp | ||
| 461 | + managed threads than available CPUs. Use very short spinning. */ | ||
| 462 | + gomp_throttled_spin_count_var = 100LL; | ||
| 463 | + if (gomp_throttled_spin_count_var > gomp_spin_count_var) | ||
| 464 | + gomp_throttled_spin_count_var = gomp_spin_count_var; | ||
| 465 | |||
| 466 | /* Not strictly environment related, but ordering constructors is tricky. */ | ||
| 467 | pthread_attr_init (&gomp_thread_attr); | ||
| 468 | --- libgomp/libgomp.h.jj 2007-12-07 14:41:01.000000000 +0100 | ||
| 469 | +++ libgomp/libgomp.h 2008-03-27 12:21:51.000000000 +0100 | ||
| 470 | @@ -50,6 +50,7 @@ | ||
| 471 | #include "sem.h" | ||
| 472 | #include "mutex.h" | ||
| 473 | #include "bar.h" | ||
| 474 | +#include "ptrlock.h" | ||
| 475 | |||
| 476 | |||
| 477 | /* This structure contains the data to control one work-sharing construct, | ||
| 478 | @@ -70,6 +71,8 @@ struct gomp_work_share | ||
| 479 | If this is a SECTIONS construct, this value will always be DYNAMIC. */ | ||
| 480 | enum gomp_schedule_type sched; | ||
| 481 | |||
| 482 | + int mode; | ||
| 483 | + | ||
| 484 | /* This is the chunk_size argument to the SCHEDULE clause. */ | ||
| 485 | long chunk_size; | ||
| 486 | |||
| 487 | @@ -81,17 +84,38 @@ struct gomp_work_share | ||
| 488 | is always 1. */ | ||
| 489 | long incr; | ||
| 490 | |||
| 491 | - /* This lock protects the update of the following members. */ | ||
| 492 | - gomp_mutex_t lock; | ||
| 493 | + /* This is a circular queue that details which threads will be allowed | ||
| 494 | + into the ordered region and in which order. When a thread allocates | ||
| 495 | + iterations on which it is going to work, it also registers itself at | ||
| 496 | + the end of the array. When a thread reaches the ordered region, it | ||
| 497 | + checks to see if it is the one at the head of the queue. If not, it | ||
| 498 | + blocks on its RELEASE semaphore. */ | ||
| 499 | + unsigned *ordered_team_ids; | ||
| 500 | |||
| 501 | - union { | ||
| 502 | - /* This is the next iteration value to be allocated. In the case of | ||
| 503 | - GFS_STATIC loops, this the iteration start point and never changes. */ | ||
| 504 | - long next; | ||
| 505 | + /* This is the number of threads that have registered themselves in | ||
| 506 | + the circular queue ordered_team_ids. */ | ||
| 507 | + unsigned ordered_num_used; | ||
| 508 | |||
| 509 | - /* This is the returned data structure for SINGLE COPYPRIVATE. */ | ||
| 510 | - void *copyprivate; | ||
| 511 | - }; | ||
| 512 | + /* This is the team_id of the currently acknowledged owner of the ordered | ||
| 513 | + section, or -1u if the ordered section has not been acknowledged by | ||
| 514 | + any thread. This is distinguished from the thread that is *allowed* | ||
| 515 | + to take the section next. */ | ||
| 516 | + unsigned ordered_owner; | ||
| 517 | + | ||
| 518 | + /* This is the index into the circular queue ordered_team_ids of the | ||
| 519 | + current thread that's allowed into the ordered reason. */ | ||
| 520 | + unsigned ordered_cur; | ||
| 521 | + | ||
| 522 | + /* This is a chain of allocated gomp_work_share blocks, valid only | ||
| 523 | + in the first gomp_work_share struct in the block. */ | ||
| 524 | + struct gomp_work_share *next_alloc; | ||
| 525 | + | ||
| 526 | + /* The above fields are written once during workshare initialization, | ||
| 527 | + or related to ordered worksharing. Make sure the following fields | ||
| 528 | + are in a different cache line. */ | ||
| 529 | + | ||
| 530 | + /* This lock protects the update of the following members. */ | ||
| 531 | + gomp_mutex_t lock __attribute__((aligned (64))); | ||
| 532 | |||
| 533 | /* This is the count of the number of threads that have exited the work | ||
| 534 | share construct. If the construct was marked nowait, they have moved on | ||
| 535 | @@ -99,27 +123,28 @@ struct gomp_work_share | ||
| 536 | of the team to exit the work share construct must deallocate it. */ | ||
| 537 | unsigned threads_completed; | ||
| 538 | |||
| 539 | - /* This is the index into the circular queue ordered_team_ids of the | ||
| 540 | - current thread that's allowed into the ordered reason. */ | ||
| 541 | - unsigned ordered_cur; | ||
| 542 | + union { | ||
| 543 | + /* This is the next iteration value to be allocated. In the case of | ||
| 544 | + GFS_STATIC loops, this the iteration start point and never changes. */ | ||
| 545 | + long next; | ||
| 546 | |||
| 547 | - /* This is the number of threads that have registered themselves in | ||
| 548 | - the circular queue ordered_team_ids. */ | ||
| 549 | - unsigned ordered_num_used; | ||
| 550 | + /* This is the returned data structure for SINGLE COPYPRIVATE. */ | ||
| 551 | + void *copyprivate; | ||
| 552 | + }; | ||
| 553 | |||
| 554 | - /* This is the team_id of the currently acknoledged owner of the ordered | ||
| 555 | - section, or -1u if the ordered section has not been acknowledged by | ||
| 556 | - any thread. This is distinguished from the thread that is *allowed* | ||
| 557 | - to take the section next. */ | ||
| 558 | - unsigned ordered_owner; | ||
| 559 | + union { | ||
| 560 | + /* Link to gomp_work_share struct for next work sharing construct | ||
| 561 | + encountered after this one. */ | ||
| 562 | + gomp_ptrlock_t next_ws; | ||
| 563 | + | ||
| 564 | + /* gomp_work_share structs are chained in the free work share cache | ||
| 565 | + through this. */ | ||
| 566 | + struct gomp_work_share *next_free; | ||
| 567 | + }; | ||
| 568 | |||
| 569 | - /* This is a circular queue that details which threads will be allowed | ||
| 570 | - into the ordered region and in which order. When a thread allocates | ||
| 571 | - iterations on which it is going to work, it also registers itself at | ||
| 572 | - the end of the array. When a thread reaches the ordered region, it | ||
| 573 | - checks to see if it is the one at the head of the queue. If not, it | ||
| 574 | - blocks on its RELEASE semaphore. */ | ||
| 575 | - unsigned ordered_team_ids[]; | ||
| 576 | + /* If only few threads are in the team, ordered_team_ids can point | ||
| 577 | + to this array which fills the padding at the end of this struct. */ | ||
| 578 | + unsigned inline_ordered_team_ids[0]; | ||
| 579 | }; | ||
| 580 | |||
| 581 | /* This structure contains all of the thread-local data associated with | ||
| 582 | @@ -133,21 +158,24 @@ struct gomp_team_state | ||
| 583 | |||
| 584 | /* This is the work share construct which this thread is currently | ||
| 585 | processing. Recall that with NOWAIT, not all threads may be | ||
| 586 | - processing the same construct. This value is NULL when there | ||
| 587 | - is no construct being processed. */ | ||
| 588 | + processing the same construct. */ | ||
| 589 | struct gomp_work_share *work_share; | ||
| 590 | |||
| 591 | + /* This is the previous work share construct or NULL if there wasn't any. | ||
| 592 | + When all threads are done with the current work sharing construct, | ||
| 593 | + the previous one can be freed. The current one can't, as its | ||
| 594 | + next_ws field is used. */ | ||
| 595 | + struct gomp_work_share *last_work_share; | ||
| 596 | + | ||
| 597 | /* This is the ID of this thread within the team. This value is | ||
| 598 | guaranteed to be between 0 and N-1, where N is the number of | ||
| 599 | threads in the team. */ | ||
| 600 | unsigned team_id; | ||
| 601 | |||
| 602 | - /* The work share "generation" is a number that increases by one for | ||
| 603 | - each work share construct encountered in the dynamic flow of the | ||
| 604 | - program. It is used to find the control data for the work share | ||
| 605 | - when encountering it for the first time. This particular number | ||
| 606 | - reflects the generation of the work_share member of this struct. */ | ||
| 607 | - unsigned work_share_generation; | ||
| 608 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 609 | + /* Number of single stmts encountered. */ | ||
| 610 | + unsigned long single_count; | ||
| 611 | +#endif | ||
| 612 | |||
| 613 | /* For GFS_RUNTIME loops that resolved to GFS_STATIC, this is the | ||
| 614 | trip number through the loop. So first time a particular loop | ||
| 615 | @@ -163,41 +191,53 @@ struct gomp_team_state | ||
| 616 | |||
| 617 | struct gomp_team | ||
| 618 | { | ||
| 619 | - /* This lock protects access to the following work shares data structures. */ | ||
| 620 | - gomp_mutex_t work_share_lock; | ||
| 621 | - | ||
| 622 | - /* This is a dynamically sized array containing pointers to the control | ||
| 623 | - structs for all "live" work share constructs. Here "live" means that | ||
| 624 | - the construct has been encountered by at least one thread, and not | ||
| 625 | - completed by all threads. */ | ||
| 626 | - struct gomp_work_share **work_shares; | ||
| 627 | - | ||
| 628 | - /* The work_shares array is indexed by "generation & generation_mask". | ||
| 629 | - The mask will be 2**N - 1, where 2**N is the size of the array. */ | ||
| 630 | - unsigned generation_mask; | ||
| 631 | - | ||
| 632 | - /* These two values define the bounds of the elements of the work_shares | ||
| 633 | - array that are currently in use. */ | ||
| 634 | - unsigned oldest_live_gen; | ||
| 635 | - unsigned num_live_gen; | ||
| 636 | - | ||
| 637 | /* This is the number of threads in the current team. */ | ||
| 638 | unsigned nthreads; | ||
| 639 | |||
| 640 | + /* This is number of gomp_work_share structs that have been allocated | ||
| 641 | + as a block last time. */ | ||
| 642 | + unsigned work_share_chunk; | ||
| 643 | + | ||
| 644 | /* This is the saved team state that applied to a master thread before | ||
| 645 | the current thread was created. */ | ||
| 646 | struct gomp_team_state prev_ts; | ||
| 647 | |||
| 648 | - /* This barrier is used for most synchronization of the team. */ | ||
| 649 | - gomp_barrier_t barrier; | ||
| 650 | - | ||
| 651 | /* This semaphore should be used by the master thread instead of its | ||
| 652 | "native" semaphore in the thread structure. Required for nested | ||
| 653 | parallels, as the master is a member of two teams. */ | ||
| 654 | gomp_sem_t master_release; | ||
| 655 | |||
| 656 | - /* This array contains pointers to the release semaphore of the threads | ||
| 657 | - in the team. */ | ||
| 658 | + /* List of gomp_work_share structs chained through next_free fields. | ||
| 659 | + This is populated and taken off only by the first thread in the | ||
| 660 | + team encountering a new work sharing construct, in a critical | ||
| 661 | + section. */ | ||
| 662 | + struct gomp_work_share *work_share_list_alloc; | ||
| 663 | + | ||
| 664 | + /* List of gomp_work_share structs freed by free_work_share. New | ||
| 665 | + entries are atomically added to the start of the list, and | ||
| 666 | + alloc_work_share can safely only move all but the first entry | ||
| 667 | + to work_share_list alloc, as free_work_share can happen concurrently | ||
| 668 | + with alloc_work_share. */ | ||
| 669 | + struct gomp_work_share *work_share_list_free; | ||
| 670 | + | ||
| 671 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 672 | + /* Number of simple single regions encountered by threads in this | ||
| 673 | + team. */ | ||
| 674 | + unsigned long single_count; | ||
| 675 | +#else | ||
| 676 | + /* Mutex protecting addition of workshares to work_share_list_free. */ | ||
| 677 | + gomp_mutex_t work_share_list_free_lock; | ||
| 678 | +#endif | ||
| 679 | + | ||
| 680 | + /* This barrier is used for most synchronization of the team. */ | ||
| 681 | + gomp_barrier_t barrier; | ||
| 682 | + | ||
| 683 | + /* Initial work shares, to avoid allocating any gomp_work_share | ||
| 684 | + structs in the common case. */ | ||
| 685 | + struct gomp_work_share work_shares[8]; | ||
| 686 | + | ||
| 687 | + /* This is an array with pointers to the release semaphore | ||
| 688 | + of the threads in the team. */ | ||
| 689 | gomp_sem_t *ordered_release[]; | ||
| 690 | }; | ||
| 691 | |||
| 692 | @@ -242,6 +282,11 @@ extern bool gomp_dyn_var; | ||
| 693 | extern bool gomp_nest_var; | ||
| 694 | extern enum gomp_schedule_type gomp_run_sched_var; | ||
| 695 | extern unsigned long gomp_run_sched_chunk; | ||
| 696 | +#ifndef HAVE_SYNC_BUILTINS | ||
| 697 | +extern gomp_mutex_t gomp_remaining_threads_lock; | ||
| 698 | +#endif | ||
| 699 | +extern unsigned long long gomp_spin_count_var, gomp_throttled_spin_count_var; | ||
| 700 | +extern unsigned long gomp_available_cpus, gomp_managed_threads; | ||
| 701 | |||
| 702 | /* The attributes to be used during thread creation. */ | ||
| 703 | extern pthread_attr_t gomp_thread_attr; | ||
| 704 | @@ -306,17 +351,27 @@ extern unsigned gomp_dynamic_max_threads | ||
| 705 | |||
| 706 | /* team.c */ | ||
| 707 | |||
| 708 | +extern struct gomp_team *gomp_new_team (unsigned); | ||
| 709 | extern void gomp_team_start (void (*) (void *), void *, unsigned, | ||
| 710 | - struct gomp_work_share *); | ||
| 711 | + struct gomp_team *); | ||
| 712 | extern void gomp_team_end (void); | ||
| 713 | |||
| 714 | /* work.c */ | ||
| 715 | |||
| 716 | -extern struct gomp_work_share * gomp_new_work_share (bool, unsigned); | ||
| 717 | +extern void gomp_init_work_share (struct gomp_work_share *, bool, unsigned); | ||
| 718 | +extern void gomp_fini_work_share (struct gomp_work_share *); | ||
| 719 | extern bool gomp_work_share_start (bool); | ||
| 720 | extern void gomp_work_share_end (void); | ||
| 721 | extern void gomp_work_share_end_nowait (void); | ||
| 722 | |||
| 723 | +static inline void | ||
| 724 | +gomp_work_share_init_done (void) | ||
| 725 | +{ | ||
| 726 | + struct gomp_thread *thr = gomp_thread (); | ||
| 727 | + if (__builtin_expect (thr->ts.last_work_share != NULL, 1)) | ||
| 728 | + gomp_ptrlock_set (&thr->ts.last_work_share->next_ws, thr->ts.work_share); | ||
| 729 | +} | ||
| 730 | + | ||
| 731 | #ifdef HAVE_ATTRIBUTE_VISIBILITY | ||
| 732 | # pragma GCC visibility pop | ||
| 733 | #endif | ||
| 734 | --- libgomp/iter.c.jj 2008-03-26 14:48:34.000000000 +0100 | ||
| 735 | +++ libgomp/iter.c 2008-03-26 15:11:23.000000000 +0100 | ||
| 736 | @@ -1,4 +1,4 @@ | ||
| 737 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 738 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 739 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 740 | |||
| 741 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 742 | @@ -154,7 +154,7 @@ gomp_iter_dynamic_next_locked (long *pst | ||
| 743 | if (start == ws->end) | ||
| 744 | return false; | ||
| 745 | |||
| 746 | - chunk = ws->chunk_size * ws->incr; | ||
| 747 | + chunk = ws->chunk_size; | ||
| 748 | left = ws->end - start; | ||
| 749 | if (ws->incr < 0) | ||
| 750 | { | ||
| 751 | @@ -186,11 +186,38 @@ gomp_iter_dynamic_next (long *pstart, lo | ||
| 752 | struct gomp_work_share *ws = thr->ts.work_share; | ||
| 753 | long start, end, nend, chunk, incr; | ||
| 754 | |||
| 755 | - start = ws->next; | ||
| 756 | end = ws->end; | ||
| 757 | incr = ws->incr; | ||
| 758 | - chunk = ws->chunk_size * incr; | ||
| 759 | + chunk = ws->chunk_size; | ||
| 760 | + | ||
| 761 | + if (__builtin_expect (ws->mode, 1)) | ||
| 762 | + { | ||
| 763 | + long tmp = __sync_fetch_and_add (&ws->next, chunk); | ||
| 764 | + if (incr > 0) | ||
| 765 | + { | ||
| 766 | + if (tmp >= end) | ||
| 767 | + return false; | ||
| 768 | + nend = tmp + chunk; | ||
| 769 | + if (nend > end) | ||
| 770 | + nend = end; | ||
| 771 | + *pstart = tmp; | ||
| 772 | + *pend = nend; | ||
| 773 | + return true; | ||
| 774 | + } | ||
| 775 | + else | ||
| 776 | + { | ||
| 777 | + if (tmp <= end) | ||
| 778 | + return false; | ||
| 779 | + nend = tmp + chunk; | ||
| 780 | + if (nend < end) | ||
| 781 | + nend = end; | ||
| 782 | + *pstart = tmp; | ||
| 783 | + *pend = nend; | ||
| 784 | + return true; | ||
| 785 | + } | ||
| 786 | + } | ||
| 787 | |||
| 788 | + start = ws->next; | ||
| 789 | while (1) | ||
| 790 | { | ||
| 791 | long left = end - start; | ||
| 792 | --- libgomp/work.c.jj 2007-12-07 14:41:01.000000000 +0100 | ||
| 793 | +++ libgomp/work.c 2008-03-27 12:21:51.000000000 +0100 | ||
| 794 | @@ -1,4 +1,4 @@ | ||
| 795 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 796 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 797 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 798 | |||
| 799 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 800 | @@ -29,39 +29,138 @@ | ||
| 801 | of threads. */ | ||
| 802 | |||
| 803 | #include "libgomp.h" | ||
| 804 | +#include <stddef.h> | ||
| 805 | #include <stdlib.h> | ||
| 806 | #include <string.h> | ||
| 807 | |||
| 808 | |||
| 809 | -/* Create a new work share structure. */ | ||
| 810 | +/* Allocate a new work share structure, preferably from current team's | ||
| 811 | + free gomp_work_share cache. */ | ||
| 812 | |||
| 813 | -struct gomp_work_share * | ||
| 814 | -gomp_new_work_share (bool ordered, unsigned nthreads) | ||
| 815 | +static struct gomp_work_share * | ||
| 816 | +alloc_work_share (struct gomp_team *team) | ||
| 817 | { | ||
| 818 | struct gomp_work_share *ws; | ||
| 819 | - size_t size; | ||
| 820 | + unsigned int i; | ||
| 821 | |||
| 822 | - size = sizeof (*ws); | ||
| 823 | - if (ordered) | ||
| 824 | - size += nthreads * sizeof (ws->ordered_team_ids[0]); | ||
| 825 | + /* This is called in a critical section. */ | ||
| 826 | + if (team->work_share_list_alloc != NULL) | ||
| 827 | + { | ||
| 828 | + ws = team->work_share_list_alloc; | ||
| 829 | + team->work_share_list_alloc = ws->next_free; | ||
| 830 | + return ws; | ||
| 831 | + } | ||
| 832 | |||
| 833 | - ws = gomp_malloc_cleared (size); | ||
| 834 | - gomp_mutex_init (&ws->lock); | ||
| 835 | - ws->ordered_owner = -1; | ||
| 836 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 837 | + ws = team->work_share_list_free; | ||
| 838 | + /* We need atomic read from work_share_list_free, | ||
| 839 | + as free_work_share can be called concurrently. */ | ||
| 840 | + __asm ("" : "+r" (ws)); | ||
| 841 | + | ||
| 842 | + if (ws && ws->next_free) | ||
| 843 | + { | ||
| 844 | + struct gomp_work_share *next = ws->next_free; | ||
| 845 | + ws->next_free = NULL; | ||
| 846 | + team->work_share_list_alloc = next->next_free; | ||
| 847 | + return next; | ||
| 848 | + } | ||
| 849 | +#else | ||
| 850 | + gomp_mutex_lock (&team->work_share_list_free_lock); | ||
| 851 | + ws = team->work_share_list_free; | ||
| 852 | + if (ws) | ||
| 853 | + { | ||
| 854 | + team->work_share_list_alloc = ws->next_free; | ||
| 855 | + team->work_share_list_free = NULL; | ||
| 856 | + gomp_mutex_unlock (&team->work_share_list_free_lock); | ||
| 857 | + return ws; | ||
| 858 | + } | ||
| 859 | + gomp_mutex_unlock (&team->work_share_list_free_lock); | ||
| 860 | +#endif | ||
| 861 | |||
| 862 | + team->work_share_chunk *= 2; | ||
| 863 | + ws = gomp_malloc (team->work_share_chunk * sizeof (struct gomp_work_share)); | ||
| 864 | + ws->next_alloc = team->work_shares[0].next_alloc; | ||
| 865 | + team->work_shares[0].next_alloc = ws; | ||
| 866 | + team->work_share_list_alloc = &ws[1]; | ||
| 867 | + for (i = 1; i < team->work_share_chunk - 1; i++) | ||
| 868 | + ws[i].next_free = &ws[i + 1]; | ||
| 869 | + ws[i].next_free = NULL; | ||
| 870 | return ws; | ||
| 871 | } | ||
| 872 | |||
| 873 | +/* Initialize an already allocated struct gomp_work_share. | ||
| 874 | + This shouldn't touch the next_alloc field. */ | ||
| 875 | + | ||
| 876 | +void | ||
| 877 | +gomp_init_work_share (struct gomp_work_share *ws, bool ordered, | ||
| 878 | + unsigned nthreads) | ||
| 879 | +{ | ||
| 880 | + gomp_mutex_init (&ws->lock); | ||
| 881 | + if (__builtin_expect (ordered, 0)) | ||
| 882 | + { | ||
| 883 | +#define INLINE_ORDERED_TEAM_IDS_CNT \ | ||
| 884 | + ((sizeof (struct gomp_work_share) \ | ||
| 885 | + - offsetof (struct gomp_work_share, inline_ordered_team_ids)) \ | ||
| 886 | + / sizeof (((struct gomp_work_share *) 0)->inline_ordered_team_ids[0])) | ||
| 887 | + | ||
| 888 | + if (nthreads > INLINE_ORDERED_TEAM_IDS_CNT) | ||
| 889 | + ws->ordered_team_ids | ||
| 890 | + = gomp_malloc (nthreads * sizeof (*ws->ordered_team_ids)); | ||
| 891 | + else | ||
| 892 | + ws->ordered_team_ids = ws->inline_ordered_team_ids; | ||
| 893 | + memset (ws->ordered_team_ids, '\0', | ||
| 894 | + nthreads * sizeof (*ws->ordered_team_ids)); | ||
| 895 | + ws->ordered_num_used = 0; | ||
| 896 | + ws->ordered_owner = -1; | ||
| 897 | + ws->ordered_cur = 0; | ||
| 898 | + } | ||
| 899 | + else | ||
| 900 | + ws->ordered_team_ids = NULL; | ||
| 901 | + gomp_ptrlock_init (&ws->next_ws, NULL); | ||
| 902 | + ws->threads_completed = 0; | ||
| 903 | +} | ||
| 904 | |||
| 905 | -/* Free a work share structure. */ | ||
| 906 | +/* Do any needed destruction of gomp_work_share fields before it | ||
| 907 | + is put back into free gomp_work_share cache or freed. */ | ||
| 908 | |||
| 909 | -static void | ||
| 910 | -free_work_share (struct gomp_work_share *ws) | ||
| 911 | +void | ||
| 912 | +gomp_fini_work_share (struct gomp_work_share *ws) | ||
| 913 | { | ||
| 914 | gomp_mutex_destroy (&ws->lock); | ||
| 915 | - free (ws); | ||
| 916 | + if (ws->ordered_team_ids != ws->inline_ordered_team_ids) | ||
| 917 | + free (ws->ordered_team_ids); | ||
| 918 | + gomp_ptrlock_destroy (&ws->next_ws); | ||
| 919 | } | ||
| 920 | |||
| 921 | +/* Free a work share struct, if not orphaned, put it into current | ||
| 922 | + team's free gomp_work_share cache. */ | ||
| 923 | + | ||
| 924 | +static inline void | ||
| 925 | +free_work_share (struct gomp_team *team, struct gomp_work_share *ws) | ||
| 926 | +{ | ||
| 927 | + gomp_fini_work_share (ws); | ||
| 928 | + if (__builtin_expect (team == NULL, 0)) | ||
| 929 | + free (ws); | ||
| 930 | + else | ||
| 931 | + { | ||
| 932 | + struct gomp_work_share *next_ws; | ||
| 933 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 934 | + do | ||
| 935 | + { | ||
| 936 | + next_ws = team->work_share_list_free; | ||
| 937 | + ws->next_free = next_ws; | ||
| 938 | + } | ||
| 939 | + while (!__sync_bool_compare_and_swap (&team->work_share_list_free, | ||
| 940 | + next_ws, ws)); | ||
| 941 | +#else | ||
| 942 | + gomp_mutex_lock (&team->work_share_list_free_lock); | ||
| 943 | + next_ws = team->work_share_list_free; | ||
| 944 | + ws->next_free = next_ws; | ||
| 945 | + team->work_share_list_free = ws; | ||
| 946 | + gomp_mutex_unlock (&team->work_share_list_free_lock); | ||
| 947 | +#endif | ||
| 948 | + } | ||
| 949 | +} | ||
| 950 | |||
| 951 | /* The current thread is ready to begin the next work sharing construct. | ||
| 952 | In all cases, thr->ts.work_share is updated to point to the new | ||
| 953 | @@ -74,71 +173,34 @@ gomp_work_share_start (bool ordered) | ||
| 954 | struct gomp_thread *thr = gomp_thread (); | ||
| 955 | struct gomp_team *team = thr->ts.team; | ||
| 956 | struct gomp_work_share *ws; | ||
| 957 | - unsigned ws_index, ws_gen; | ||
| 958 | |||
| 959 | /* Work sharing constructs can be orphaned. */ | ||
| 960 | if (team == NULL) | ||
| 961 | { | ||
| 962 | - ws = gomp_new_work_share (ordered, 1); | ||
| 963 | + ws = gomp_malloc (sizeof (*ws)); | ||
| 964 | + gomp_init_work_share (ws, ordered, 1); | ||
| 965 | thr->ts.work_share = ws; | ||
| 966 | - thr->ts.static_trip = 0; | ||
| 967 | - gomp_mutex_lock (&ws->lock); | ||
| 968 | - return true; | ||
| 969 | + return ws; | ||
| 970 | } | ||
| 971 | |||
| 972 | - gomp_mutex_lock (&team->work_share_lock); | ||
| 973 | - | ||
| 974 | - /* This thread is beginning its next generation. */ | ||
| 975 | - ws_gen = ++thr->ts.work_share_generation; | ||
| 976 | - | ||
| 977 | - /* If this next generation is not newer than any other generation in | ||
| 978 | - the team, then simply reference the existing construct. */ | ||
| 979 | - if (ws_gen - team->oldest_live_gen < team->num_live_gen) | ||
| 980 | + ws = thr->ts.work_share; | ||
| 981 | + thr->ts.last_work_share = ws; | ||
| 982 | + ws = gomp_ptrlock_get (&ws->next_ws); | ||
| 983 | + if (ws == NULL) | ||
| 984 | { | ||
| 985 | - ws_index = ws_gen & team->generation_mask; | ||
| 986 | - ws = team->work_shares[ws_index]; | ||
| 987 | + /* This thread encountered a new ws first. */ | ||
| 988 | + struct gomp_work_share *ws = alloc_work_share (team); | ||
| 989 | + gomp_init_work_share (ws, ordered, team->nthreads); | ||
| 990 | thr->ts.work_share = ws; | ||
| 991 | - thr->ts.static_trip = 0; | ||
| 992 | - | ||
| 993 | - gomp_mutex_lock (&ws->lock); | ||
| 994 | - gomp_mutex_unlock (&team->work_share_lock); | ||
| 995 | - | ||
| 996 | - return false; | ||
| 997 | + return true; | ||
| 998 | } | ||
| 999 | - | ||
| 1000 | - /* Resize the work shares queue if we've run out of space. */ | ||
| 1001 | - if (team->num_live_gen++ == team->generation_mask) | ||
| 1002 | + else | ||
| 1003 | { | ||
| 1004 | - team->work_shares = gomp_realloc (team->work_shares, | ||
| 1005 | - 2 * team->num_live_gen | ||
| 1006 | - * sizeof (*team->work_shares)); | ||
| 1007 | - | ||
| 1008 | - /* Unless oldest_live_gen is zero, the sequence of live elements | ||
| 1009 | - wraps around the end of the array. If we do nothing, we break | ||
| 1010 | - lookup of the existing elements. Fix that by unwrapping the | ||
| 1011 | - data from the front to the end. */ | ||
| 1012 | - if (team->oldest_live_gen > 0) | ||
| 1013 | - memcpy (team->work_shares + team->num_live_gen, | ||
| 1014 | - team->work_shares, | ||
| 1015 | - (team->oldest_live_gen & team->generation_mask) | ||
| 1016 | - * sizeof (*team->work_shares)); | ||
| 1017 | - | ||
| 1018 | - team->generation_mask = team->generation_mask * 2 + 1; | ||
| 1019 | - } | ||
| 1020 | - | ||
| 1021 | - ws_index = ws_gen & team->generation_mask; | ||
| 1022 | - ws = gomp_new_work_share (ordered, team->nthreads); | ||
| 1023 | - thr->ts.work_share = ws; | ||
| 1024 | - thr->ts.static_trip = 0; | ||
| 1025 | - team->work_shares[ws_index] = ws; | ||
| 1026 | - | ||
| 1027 | - gomp_mutex_lock (&ws->lock); | ||
| 1028 | - gomp_mutex_unlock (&team->work_share_lock); | ||
| 1029 | - | ||
| 1030 | - return true; | ||
| 1031 | + thr->ts.work_share = ws; | ||
| 1032 | + return false; | ||
| 1033 | + } | ||
| 1034 | } | ||
| 1035 | |||
| 1036 | - | ||
| 1037 | /* The current thread is done with its current work sharing construct. | ||
| 1038 | This version does imply a barrier at the end of the work-share. */ | ||
| 1039 | |||
| 1040 | @@ -147,36 +209,28 @@ gomp_work_share_end (void) | ||
| 1041 | { | ||
| 1042 | struct gomp_thread *thr = gomp_thread (); | ||
| 1043 | struct gomp_team *team = thr->ts.team; | ||
| 1044 | - struct gomp_work_share *ws = thr->ts.work_share; | ||
| 1045 | - bool last; | ||
| 1046 | - | ||
| 1047 | - thr->ts.work_share = NULL; | ||
| 1048 | + gomp_barrier_state_t bstate; | ||
| 1049 | |||
| 1050 | /* Work sharing constructs can be orphaned. */ | ||
| 1051 | if (team == NULL) | ||
| 1052 | { | ||
| 1053 | - free_work_share (ws); | ||
| 1054 | + free_work_share (NULL, thr->ts.work_share); | ||
| 1055 | + thr->ts.work_share = NULL; | ||
| 1056 | return; | ||
| 1057 | } | ||
| 1058 | |||
| 1059 | - last = gomp_barrier_wait_start (&team->barrier); | ||
| 1060 | + bstate = gomp_barrier_wait_start (&team->barrier); | ||
| 1061 | |||
| 1062 | - if (last) | ||
| 1063 | + if (gomp_barrier_last_thread (bstate)) | ||
| 1064 | { | ||
| 1065 | - unsigned ws_index; | ||
| 1066 | - | ||
| 1067 | - ws_index = thr->ts.work_share_generation & team->generation_mask; | ||
| 1068 | - team->work_shares[ws_index] = NULL; | ||
| 1069 | - team->oldest_live_gen++; | ||
| 1070 | - team->num_live_gen = 0; | ||
| 1071 | - | ||
| 1072 | - free_work_share (ws); | ||
| 1073 | + if (__builtin_expect (thr->ts.last_work_share != NULL, 1)) | ||
| 1074 | + free_work_share (team, thr->ts.last_work_share); | ||
| 1075 | } | ||
| 1076 | |||
| 1077 | - gomp_barrier_wait_end (&team->barrier, last); | ||
| 1078 | + gomp_barrier_wait_end (&team->barrier, bstate); | ||
| 1079 | + thr->ts.last_work_share = NULL; | ||
| 1080 | } | ||
| 1081 | |||
| 1082 | - | ||
| 1083 | /* The current thread is done with its current work sharing construct. | ||
| 1084 | This version does NOT imply a barrier at the end of the work-share. */ | ||
| 1085 | |||
| 1086 | @@ -188,15 +242,17 @@ gomp_work_share_end_nowait (void) | ||
| 1087 | struct gomp_work_share *ws = thr->ts.work_share; | ||
| 1088 | unsigned completed; | ||
| 1089 | |||
| 1090 | - thr->ts.work_share = NULL; | ||
| 1091 | - | ||
| 1092 | /* Work sharing constructs can be orphaned. */ | ||
| 1093 | if (team == NULL) | ||
| 1094 | { | ||
| 1095 | - free_work_share (ws); | ||
| 1096 | + free_work_share (NULL, ws); | ||
| 1097 | + thr->ts.work_share = NULL; | ||
| 1098 | return; | ||
| 1099 | } | ||
| 1100 | |||
| 1101 | + if (__builtin_expect (thr->ts.last_work_share == NULL, 0)) | ||
| 1102 | + return; | ||
| 1103 | + | ||
| 1104 | #ifdef HAVE_SYNC_BUILTINS | ||
| 1105 | completed = __sync_add_and_fetch (&ws->threads_completed, 1); | ||
| 1106 | #else | ||
| 1107 | @@ -206,18 +262,6 @@ gomp_work_share_end_nowait (void) | ||
| 1108 | #endif | ||
| 1109 | |||
| 1110 | if (completed == team->nthreads) | ||
| 1111 | - { | ||
| 1112 | - unsigned ws_index; | ||
| 1113 | - | ||
| 1114 | - gomp_mutex_lock (&team->work_share_lock); | ||
| 1115 | - | ||
| 1116 | - ws_index = thr->ts.work_share_generation & team->generation_mask; | ||
| 1117 | - team->work_shares[ws_index] = NULL; | ||
| 1118 | - team->oldest_live_gen++; | ||
| 1119 | - team->num_live_gen--; | ||
| 1120 | - | ||
| 1121 | - gomp_mutex_unlock (&team->work_share_lock); | ||
| 1122 | - | ||
| 1123 | - free_work_share (ws); | ||
| 1124 | - } | ||
| 1125 | + free_work_share (team, thr->ts.last_work_share); | ||
| 1126 | + thr->ts.last_work_share = NULL; | ||
| 1127 | } | ||
| 1128 | --- libgomp/single.c.jj 2007-12-07 14:41:01.000000000 +0100 | ||
| 1129 | +++ libgomp/single.c 2008-03-26 15:11:32.000000000 +0100 | ||
| 1130 | @@ -1,4 +1,4 @@ | ||
| 1131 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 1132 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 1133 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 1134 | |||
| 1135 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 1136 | @@ -37,10 +37,24 @@ | ||
| 1137 | bool | ||
| 1138 | GOMP_single_start (void) | ||
| 1139 | { | ||
| 1140 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 1141 | + struct gomp_thread *thr = gomp_thread (); | ||
| 1142 | + struct gomp_team *team = thr->ts.team; | ||
| 1143 | + unsigned long single_count; | ||
| 1144 | + | ||
| 1145 | + if (__builtin_expect (team == NULL, 0)) | ||
| 1146 | + return true; | ||
| 1147 | + | ||
| 1148 | + single_count = thr->ts.single_count++; | ||
| 1149 | + return __sync_bool_compare_and_swap (&team->single_count, single_count, | ||
| 1150 | + single_count + 1L); | ||
| 1151 | +#else | ||
| 1152 | bool ret = gomp_work_share_start (false); | ||
| 1153 | - gomp_mutex_unlock (&gomp_thread ()->ts.work_share->lock); | ||
| 1154 | + if (ret) | ||
| 1155 | + gomp_work_share_init_done (); | ||
| 1156 | gomp_work_share_end_nowait (); | ||
| 1157 | return ret; | ||
| 1158 | +#endif | ||
| 1159 | } | ||
| 1160 | |||
| 1161 | /* This routine is called when first encountering a SINGLE construct that | ||
| 1162 | @@ -57,10 +71,12 @@ GOMP_single_copy_start (void) | ||
| 1163 | void *ret; | ||
| 1164 | |||
| 1165 | first = gomp_work_share_start (false); | ||
| 1166 | - gomp_mutex_unlock (&thr->ts.work_share->lock); | ||
| 1167 | |||
| 1168 | if (first) | ||
| 1169 | - ret = NULL; | ||
| 1170 | + { | ||
| 1171 | + gomp_work_share_init_done (); | ||
| 1172 | + ret = NULL; | ||
| 1173 | + } | ||
| 1174 | else | ||
| 1175 | { | ||
| 1176 | gomp_barrier_wait (&thr->ts.team->barrier); | ||
| 1177 | --- libgomp/loop.c.jj 2007-12-07 14:41:01.000000000 +0100 | ||
| 1178 | +++ libgomp/loop.c 2008-03-26 18:47:04.000000000 +0100 | ||
| 1179 | @@ -27,8 +27,9 @@ | ||
| 1180 | |||
| 1181 | /* This file handles the LOOP (FOR/DO) construct. */ | ||
| 1182 | |||
| 1183 | -#include "libgomp.h" | ||
| 1184 | +#include <limits.h> | ||
| 1185 | #include <stdlib.h> | ||
| 1186 | +#include "libgomp.h" | ||
| 1187 | |||
| 1188 | |||
| 1189 | /* Initialize the given work share construct from the given arguments. */ | ||
| 1190 | @@ -44,6 +45,39 @@ gomp_loop_init (struct gomp_work_share * | ||
| 1191 | ? start : end; | ||
| 1192 | ws->incr = incr; | ||
| 1193 | ws->next = start; | ||
| 1194 | + if (sched == GFS_DYNAMIC) | ||
| 1195 | + { | ||
| 1196 | + ws->chunk_size *= incr; | ||
| 1197 | + | ||
| 1198 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 1199 | + { | ||
| 1200 | + /* For dynamic scheduling prepare things to make each iteration | ||
| 1201 | + faster. */ | ||
| 1202 | + struct gomp_thread *thr = gomp_thread (); | ||
| 1203 | + struct gomp_team *team = thr->ts.team; | ||
| 1204 | + long nthreads = team ? team->nthreads : 1; | ||
| 1205 | + | ||
| 1206 | + if (__builtin_expect (incr > 0, 1)) | ||
| 1207 | + { | ||
| 1208 | + /* Cheap overflow protection. */ | ||
| 1209 | + if (__builtin_expect ((nthreads | ws->chunk_size) | ||
| 1210 | + >= 1UL << (sizeof (long) | ||
| 1211 | + * __CHAR_BIT__ / 2 - 1), 0)) | ||
| 1212 | + ws->mode = 0; | ||
| 1213 | + else | ||
| 1214 | + ws->mode = ws->end < (LONG_MAX | ||
| 1215 | + - (nthreads + 1) * ws->chunk_size); | ||
| 1216 | + } | ||
| 1217 | + /* Cheap overflow protection. */ | ||
| 1218 | + else if (__builtin_expect ((nthreads | -ws->chunk_size) | ||
| 1219 | + >= 1UL << (sizeof (long) | ||
| 1220 | + * __CHAR_BIT__ / 2 - 1), 0)) | ||
| 1221 | + ws->mode = 0; | ||
| 1222 | + else | ||
| 1223 | + ws->mode = ws->end > (nthreads + 1) * -ws->chunk_size - LONG_MAX; | ||
| 1224 | + } | ||
| 1225 | +#endif | ||
| 1226 | + } | ||
| 1227 | } | ||
| 1228 | |||
| 1229 | /* The *_start routines are called when first encountering a loop construct | ||
| 1230 | @@ -68,10 +102,13 @@ gomp_loop_static_start (long start, long | ||
| 1231 | { | ||
| 1232 | struct gomp_thread *thr = gomp_thread (); | ||
| 1233 | |||
| 1234 | + thr->ts.static_trip = 0; | ||
| 1235 | if (gomp_work_share_start (false)) | ||
| 1236 | - gomp_loop_init (thr->ts.work_share, start, end, incr, | ||
| 1237 | - GFS_STATIC, chunk_size); | ||
| 1238 | - gomp_mutex_unlock (&thr->ts.work_share->lock); | ||
| 1239 | + { | ||
| 1240 | + gomp_loop_init (thr->ts.work_share, start, end, incr, | ||
| 1241 | + GFS_STATIC, chunk_size); | ||
| 1242 | + gomp_work_share_init_done (); | ||
| 1243 | + } | ||
| 1244 | |||
| 1245 | return !gomp_iter_static_next (istart, iend); | ||
| 1246 | } | ||
| 1247 | @@ -84,13 +121,16 @@ gomp_loop_dynamic_start (long start, lon | ||
| 1248 | bool ret; | ||
| 1249 | |||
| 1250 | if (gomp_work_share_start (false)) | ||
| 1251 | - gomp_loop_init (thr->ts.work_share, start, end, incr, | ||
| 1252 | - GFS_DYNAMIC, chunk_size); | ||
| 1253 | + { | ||
| 1254 | + gomp_loop_init (thr->ts.work_share, start, end, incr, | ||
| 1255 | + GFS_DYNAMIC, chunk_size); | ||
| 1256 | + gomp_work_share_init_done (); | ||
| 1257 | + } | ||
| 1258 | |||
| 1259 | #ifdef HAVE_SYNC_BUILTINS | ||
| 1260 | - gomp_mutex_unlock (&thr->ts.work_share->lock); | ||
| 1261 | ret = gomp_iter_dynamic_next (istart, iend); | ||
| 1262 | #else | ||
| 1263 | + gomp_mutex_lock (&thr->ts.work_share->lock); | ||
| 1264 | ret = gomp_iter_dynamic_next_locked (istart, iend); | ||
| 1265 | gomp_mutex_unlock (&thr->ts.work_share->lock); | ||
| 1266 | #endif | ||
| 1267 | @@ -106,13 +146,16 @@ gomp_loop_guided_start (long start, long | ||
| 1268 | bool ret; | ||
| 1269 | |||
| 1270 | if (gomp_work_share_start (false)) | ||
| 1271 | - gomp_loop_init (thr->ts.work_share, start, end, incr, | ||
| 1272 | - GFS_GUIDED, chunk_size); | ||
| 1273 | + { | ||
| 1274 | + gomp_loop_init (thr->ts.work_share, start, end, incr, | ||
| 1275 | + GFS_GUIDED, chunk_size); | ||
| 1276 | + gomp_work_share_init_done (); | ||
| 1277 | + } | ||
| 1278 | |||
| 1279 | #ifdef HAVE_SYNC_BUILTINS | ||
| 1280 | - gomp_mutex_unlock (&thr->ts.work_share->lock); | ||
| 1281 | ret = gomp_iter_guided_next (istart, iend); | ||
| 1282 | #else | ||
| 1283 | + gomp_mutex_lock (&thr->ts.work_share->lock); | ||
| 1284 | ret = gomp_iter_guided_next_locked (istart, iend); | ||
| 1285 | gomp_mutex_unlock (&thr->ts.work_share->lock); | ||
| 1286 | #endif | ||
| 1287 | @@ -149,13 +192,14 @@ gomp_loop_ordered_static_start (long sta | ||
| 1288 | { | ||
| 1289 | struct gomp_thread *thr = gomp_thread (); | ||
| 1290 | |||
| 1291 | + thr->ts.static_trip = 0; | ||
| 1292 | if (gomp_work_share_start (true)) | ||
| 1293 | { | ||
| 1294 | gomp_loop_init (thr->ts.work_share, start, end, incr, | ||
| 1295 | GFS_STATIC, chunk_size); | ||
| 1296 | gomp_ordered_static_init (); | ||
| 1297 | + gomp_work_share_init_done (); | ||
| 1298 | } | ||
| 1299 | - gomp_mutex_unlock (&thr->ts.work_share->lock); | ||
| 1300 | |||
| 1301 | return !gomp_iter_static_next (istart, iend); | ||
| 1302 | } | ||
| 1303 | @@ -168,8 +212,14 @@ gomp_loop_ordered_dynamic_start (long st | ||
| 1304 | bool ret; | ||
| 1305 | |||
| 1306 | if (gomp_work_share_start (true)) | ||
| 1307 | - gomp_loop_init (thr->ts.work_share, start, end, incr, | ||
| 1308 | - GFS_DYNAMIC, chunk_size); | ||
| 1309 | + { | ||
| 1310 | + gomp_loop_init (thr->ts.work_share, start, end, incr, | ||
| 1311 | + GFS_DYNAMIC, chunk_size); | ||
| 1312 | + gomp_mutex_lock (&thr->ts.work_share->lock); | ||
| 1313 | + gomp_work_share_init_done (); | ||
| 1314 | + } | ||
| 1315 | + else | ||
| 1316 | + gomp_mutex_lock (&thr->ts.work_share->lock); | ||
| 1317 | |||
| 1318 | ret = gomp_iter_dynamic_next_locked (istart, iend); | ||
| 1319 | if (ret) | ||
| 1320 | @@ -187,8 +237,14 @@ gomp_loop_ordered_guided_start (long sta | ||
| 1321 | bool ret; | ||
| 1322 | |||
| 1323 | if (gomp_work_share_start (true)) | ||
| 1324 | - gomp_loop_init (thr->ts.work_share, start, end, incr, | ||
| 1325 | - GFS_GUIDED, chunk_size); | ||
| 1326 | + { | ||
| 1327 | + gomp_loop_init (thr->ts.work_share, start, end, incr, | ||
| 1328 | + GFS_GUIDED, chunk_size); | ||
| 1329 | + gomp_mutex_lock (&thr->ts.work_share->lock); | ||
| 1330 | + gomp_work_share_init_done (); | ||
| 1331 | + } | ||
| 1332 | + else | ||
| 1333 | + gomp_mutex_lock (&thr->ts.work_share->lock); | ||
| 1334 | |||
| 1335 | ret = gomp_iter_guided_next_locked (istart, iend); | ||
| 1336 | if (ret) | ||
| 1337 | @@ -375,12 +431,12 @@ gomp_parallel_loop_start (void (*fn) (vo | ||
| 1338 | long incr, enum gomp_schedule_type sched, | ||
| 1339 | long chunk_size) | ||
| 1340 | { | ||
| 1341 | - struct gomp_work_share *ws; | ||
| 1342 | + struct gomp_team *team; | ||
| 1343 | |||
| 1344 | num_threads = gomp_resolve_num_threads (num_threads); | ||
| 1345 | - ws = gomp_new_work_share (false, num_threads); | ||
| 1346 | - gomp_loop_init (ws, start, end, incr, sched, chunk_size); | ||
| 1347 | - gomp_team_start (fn, data, num_threads, ws); | ||
| 1348 | + team = gomp_new_team (num_threads); | ||
| 1349 | + gomp_loop_init (&team->work_shares[0], start, end, incr, sched, chunk_size); | ||
| 1350 | + gomp_team_start (fn, data, num_threads, team); | ||
| 1351 | } | ||
| 1352 | |||
| 1353 | void | ||
| 1354 | --- libgomp/Makefile.in.jj 2008-01-10 20:53:47.000000000 +0100 | ||
| 1355 | +++ libgomp/Makefile.in 2008-03-26 18:51:01.000000000 +0100 | ||
| 1356 | @@ -83,7 +83,7 @@ libgomp_la_LIBADD = | ||
| 1357 | am_libgomp_la_OBJECTS = alloc.lo barrier.lo critical.lo env.lo \ | ||
| 1358 | error.lo iter.lo loop.lo ordered.lo parallel.lo sections.lo \ | ||
| 1359 | single.lo team.lo work.lo lock.lo mutex.lo proc.lo sem.lo \ | ||
| 1360 | - bar.lo time.lo fortran.lo affinity.lo | ||
| 1361 | + bar.lo ptrlock.lo time.lo fortran.lo affinity.lo | ||
| 1362 | libgomp_la_OBJECTS = $(am_libgomp_la_OBJECTS) | ||
| 1363 | DEFAULT_INCLUDES = -I. -I$(srcdir) -I. | ||
| 1364 | depcomp = $(SHELL) $(top_srcdir)/../depcomp | ||
| 1365 | @@ -292,7 +292,7 @@ libgomp_version_info = -version-info $(l | ||
| 1366 | libgomp_la_LDFLAGS = $(libgomp_version_info) $(libgomp_version_script) | ||
| 1367 | libgomp_la_SOURCES = alloc.c barrier.c critical.c env.c error.c iter.c \ | ||
| 1368 | loop.c ordered.c parallel.c sections.c single.c team.c work.c \ | ||
| 1369 | - lock.c mutex.c proc.c sem.c bar.c time.c fortran.c affinity.c | ||
| 1370 | + lock.c mutex.c proc.c sem.c bar.c ptrlock.c time.c fortran.c affinity.c | ||
| 1371 | |||
| 1372 | nodist_noinst_HEADERS = libgomp_f.h | ||
| 1373 | nodist_libsubinclude_HEADERS = omp.h | ||
| 1374 | @@ -434,6 +434,7 @@ distclean-compile: | ||
| 1375 | @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ordered.Plo@am__quote@ | ||
| 1376 | @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/parallel.Plo@am__quote@ | ||
| 1377 | @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/proc.Plo@am__quote@ | ||
| 1378 | +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ptrlock.Plo@am__quote@ | ||
| 1379 | @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sections.Plo@am__quote@ | ||
| 1380 | @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sem.Plo@am__quote@ | ||
| 1381 | @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/single.Plo@am__quote@ | ||
| 1382 | --- libgomp/testsuite/libgomp.c/loop-4.c.jj 2008-03-26 18:47:04.000000000 +0100 | ||
| 1383 | +++ libgomp/testsuite/libgomp.c/loop-4.c 2008-03-26 18:47:04.000000000 +0100 | ||
| 1384 | @@ -0,0 +1,28 @@ | ||
| 1385 | +/* { dg-do run } */ | ||
| 1386 | + | ||
| 1387 | +extern void abort (void); | ||
| 1388 | + | ||
| 1389 | +int | ||
| 1390 | +main (void) | ||
| 1391 | +{ | ||
| 1392 | + int e = 0; | ||
| 1393 | +#pragma omp parallel num_threads (4) reduction(+:e) | ||
| 1394 | + { | ||
| 1395 | + long i; | ||
| 1396 | + #pragma omp for schedule(dynamic,1) | ||
| 1397 | + for (i = __LONG_MAX__ - 30001; i <= __LONG_MAX__ - 10001; i += 10000) | ||
| 1398 | + if (i != __LONG_MAX__ - 30001 | ||
| 1399 | + && i != __LONG_MAX__ - 20001 | ||
| 1400 | + && i != __LONG_MAX__ - 10001) | ||
| 1401 | + e = 1; | ||
| 1402 | + #pragma omp for schedule(dynamic,1) | ||
| 1403 | + for (i = -__LONG_MAX__ + 30000; i >= -__LONG_MAX__ + 10000; i -= 10000) | ||
| 1404 | + if (i != -__LONG_MAX__ + 30000 | ||
| 1405 | + && i != -__LONG_MAX__ + 20000 | ||
| 1406 | + && i != -__LONG_MAX__ + 10000) | ||
| 1407 | + e = 1; | ||
| 1408 | + } | ||
| 1409 | + if (e) | ||
| 1410 | + abort (); | ||
| 1411 | + return 0; | ||
| 1412 | +} | ||
| 1413 | --- libgomp/Makefile.am.jj 2007-12-07 14:41:01.000000000 +0100 | ||
| 1414 | +++ libgomp/Makefile.am 2008-03-26 15:15:19.000000000 +0100 | ||
| 1415 | @@ -31,7 +31,7 @@ libgomp_la_LDFLAGS = $(libgomp_version_i | ||
| 1416 | |||
| 1417 | libgomp_la_SOURCES = alloc.c barrier.c critical.c env.c error.c iter.c \ | ||
| 1418 | loop.c ordered.c parallel.c sections.c single.c team.c work.c \ | ||
| 1419 | - lock.c mutex.c proc.c sem.c bar.c time.c fortran.c affinity.c | ||
| 1420 | + lock.c mutex.c proc.c sem.c bar.c ptrlock.c time.c fortran.c affinity.c | ||
| 1421 | |||
| 1422 | nodist_noinst_HEADERS = libgomp_f.h | ||
| 1423 | nodist_libsubinclude_HEADERS = omp.h | ||
| 1424 | --- libgomp/team.c.jj 2007-12-07 14:41:01.000000000 +0100 | ||
| 1425 | +++ libgomp/team.c 2008-03-27 12:22:26.000000000 +0100 | ||
| 1426 | @@ -94,7 +94,7 @@ gomp_thread_start (void *xdata) | ||
| 1427 | { | ||
| 1428 | gomp_barrier_wait (&thr->ts.team->barrier); | ||
| 1429 | local_fn (local_data); | ||
| 1430 | - gomp_barrier_wait (&thr->ts.team->barrier); | ||
| 1431 | + gomp_barrier_wait_last (&thr->ts.team->barrier); | ||
| 1432 | } | ||
| 1433 | else | ||
| 1434 | { | ||
| 1435 | @@ -114,11 +114,10 @@ gomp_thread_start (void *xdata) | ||
| 1436 | thr->data = NULL; | ||
| 1437 | thr->ts.team = NULL; | ||
| 1438 | thr->ts.work_share = NULL; | ||
| 1439 | + thr->ts.last_work_share = NULL; | ||
| 1440 | thr->ts.team_id = 0; | ||
| 1441 | - thr->ts.work_share_generation = 0; | ||
| 1442 | - thr->ts.static_trip = 0; | ||
| 1443 | |||
| 1444 | - gomp_barrier_wait (&team->barrier); | ||
| 1445 | + gomp_barrier_wait_last (&team->barrier); | ||
| 1446 | gomp_barrier_wait (&gomp_threads_dock); | ||
| 1447 | |||
| 1448 | local_fn = thr->fn; | ||
| 1449 | @@ -133,21 +132,29 @@ gomp_thread_start (void *xdata) | ||
| 1450 | |||
| 1451 | /* Create a new team data structure. */ | ||
| 1452 | |||
| 1453 | -static struct gomp_team * | ||
| 1454 | -new_team (unsigned nthreads, struct gomp_work_share *work_share) | ||
| 1455 | +struct gomp_team * | ||
| 1456 | +gomp_new_team (unsigned nthreads) | ||
| 1457 | { | ||
| 1458 | struct gomp_team *team; | ||
| 1459 | size_t size; | ||
| 1460 | + int i; | ||
| 1461 | |||
| 1462 | size = sizeof (*team) + nthreads * sizeof (team->ordered_release[0]); | ||
| 1463 | team = gomp_malloc (size); | ||
| 1464 | - gomp_mutex_init (&team->work_share_lock); | ||
| 1465 | |||
| 1466 | - team->work_shares = gomp_malloc (4 * sizeof (struct gomp_work_share *)); | ||
| 1467 | - team->generation_mask = 3; | ||
| 1468 | - team->oldest_live_gen = work_share == NULL; | ||
| 1469 | - team->num_live_gen = work_share != NULL; | ||
| 1470 | - team->work_shares[0] = work_share; | ||
| 1471 | + team->work_share_chunk = 8; | ||
| 1472 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 1473 | + team->single_count = 0; | ||
| 1474 | +#else | ||
| 1475 | + gomp_mutex_init (&team->work_share_list_free_lock); | ||
| 1476 | +#endif | ||
| 1477 | + gomp_init_work_share (&team->work_shares[0], false, nthreads); | ||
| 1478 | + team->work_shares[0].next_alloc = NULL; | ||
| 1479 | + team->work_share_list_free = NULL; | ||
| 1480 | + team->work_share_list_alloc = &team->work_shares[1]; | ||
| 1481 | + for (i = 1; i < 7; i++) | ||
| 1482 | + team->work_shares[i].next_free = &team->work_shares[i + 1]; | ||
| 1483 | + team->work_shares[i].next_free = NULL; | ||
| 1484 | |||
| 1485 | team->nthreads = nthreads; | ||
| 1486 | gomp_barrier_init (&team->barrier, nthreads); | ||
| 1487 | @@ -164,10 +171,22 @@ new_team (unsigned nthreads, struct gomp | ||
| 1488 | static void | ||
| 1489 | free_team (struct gomp_team *team) | ||
| 1490 | { | ||
| 1491 | - free (team->work_shares); | ||
| 1492 | - gomp_mutex_destroy (&team->work_share_lock); | ||
| 1493 | + if (__builtin_expect (team->work_shares[0].next_alloc != NULL, 0)) | ||
| 1494 | + { | ||
| 1495 | + struct gomp_work_share *ws = team->work_shares[0].next_alloc; | ||
| 1496 | + do | ||
| 1497 | + { | ||
| 1498 | + struct gomp_work_share *next_ws = ws->next_alloc; | ||
| 1499 | + free (ws); | ||
| 1500 | + ws = next_ws; | ||
| 1501 | + } | ||
| 1502 | + while (ws != NULL); | ||
| 1503 | + } | ||
| 1504 | gomp_barrier_destroy (&team->barrier); | ||
| 1505 | gomp_sem_destroy (&team->master_release); | ||
| 1506 | +#ifndef HAVE_SYNC_BUILTINS | ||
| 1507 | + gomp_mutex_destroy (&team->work_share_list_free_lock); | ||
| 1508 | +#endif | ||
| 1509 | free (team); | ||
| 1510 | } | ||
| 1511 | |||
| 1512 | @@ -176,11 +195,10 @@ free_team (struct gomp_team *team) | ||
| 1513 | |||
| 1514 | void | ||
| 1515 | gomp_team_start (void (*fn) (void *), void *data, unsigned nthreads, | ||
| 1516 | - struct gomp_work_share *work_share) | ||
| 1517 | + struct gomp_team *team) | ||
| 1518 | { | ||
| 1519 | struct gomp_thread_start_data *start_data; | ||
| 1520 | struct gomp_thread *thr, *nthr; | ||
| 1521 | - struct gomp_team *team; | ||
| 1522 | bool nested; | ||
| 1523 | unsigned i, n, old_threads_used = 0; | ||
| 1524 | pthread_attr_t thread_attr, *attr; | ||
| 1525 | @@ -188,17 +206,18 @@ gomp_team_start (void (*fn) (void *), vo | ||
| 1526 | thr = gomp_thread (); | ||
| 1527 | nested = thr->ts.team != NULL; | ||
| 1528 | |||
| 1529 | - team = new_team (nthreads, work_share); | ||
| 1530 | - | ||
| 1531 | /* Always save the previous state, even if this isn't a nested team. | ||
| 1532 | In particular, we should save any work share state from an outer | ||
| 1533 | orphaned work share construct. */ | ||
| 1534 | team->prev_ts = thr->ts; | ||
| 1535 | |||
| 1536 | thr->ts.team = team; | ||
| 1537 | - thr->ts.work_share = work_share; | ||
| 1538 | thr->ts.team_id = 0; | ||
| 1539 | - thr->ts.work_share_generation = 0; | ||
| 1540 | + thr->ts.work_share = &team->work_shares[0]; | ||
| 1541 | + thr->ts.last_work_share = NULL; | ||
| 1542 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 1543 | + thr->ts.single_count = 0; | ||
| 1544 | +#endif | ||
| 1545 | thr->ts.static_trip = 0; | ||
| 1546 | |||
| 1547 | if (nthreads == 1) | ||
| 1548 | @@ -241,9 +260,12 @@ gomp_team_start (void (*fn) (void *), vo | ||
| 1549 | { | ||
| 1550 | nthr = gomp_threads[i]; | ||
| 1551 | nthr->ts.team = team; | ||
| 1552 | - nthr->ts.work_share = work_share; | ||
| 1553 | + nthr->ts.work_share = &team->work_shares[0]; | ||
| 1554 | + nthr->ts.last_work_share = NULL; | ||
| 1555 | nthr->ts.team_id = i; | ||
| 1556 | - nthr->ts.work_share_generation = 0; | ||
| 1557 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 1558 | + nthr->ts.single_count = 0; | ||
| 1559 | +#endif | ||
| 1560 | nthr->ts.static_trip = 0; | ||
| 1561 | nthr->fn = fn; | ||
| 1562 | nthr->data = data; | ||
| 1563 | @@ -266,8 +288,24 @@ gomp_team_start (void (*fn) (void *), vo | ||
| 1564 | } | ||
| 1565 | } | ||
| 1566 | |||
| 1567 | + if (__builtin_expect (nthreads > old_threads_used, 0)) | ||
| 1568 | + { | ||
| 1569 | + long diff = (long) nthreads - (long) old_threads_used; | ||
| 1570 | + | ||
| 1571 | + if (old_threads_used == 0) | ||
| 1572 | + --diff; | ||
| 1573 | + | ||
| 1574 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 1575 | + __sync_fetch_and_add (&gomp_managed_threads, diff); | ||
| 1576 | +#else | ||
| 1577 | + gomp_mutex_lock (&gomp_remaining_threads_lock); | ||
| 1578 | + gomp_managed_threads += diff; | ||
| 1579 | + gomp_mutex_unlock (&gomp_remaining_threads_lock); | ||
| 1580 | +#endif | ||
| 1581 | + } | ||
| 1582 | + | ||
| 1583 | attr = &gomp_thread_attr; | ||
| 1584 | - if (gomp_cpu_affinity != NULL) | ||
| 1585 | + if (__builtin_expect (gomp_cpu_affinity != NULL, 0)) | ||
| 1586 | { | ||
| 1587 | size_t stacksize; | ||
| 1588 | pthread_attr_init (&thread_attr); | ||
| 1589 | @@ -287,9 +325,12 @@ gomp_team_start (void (*fn) (void *), vo | ||
| 1590 | int err; | ||
| 1591 | |||
| 1592 | start_data->ts.team = team; | ||
| 1593 | - start_data->ts.work_share = work_share; | ||
| 1594 | + start_data->ts.work_share = &team->work_shares[0]; | ||
| 1595 | + start_data->ts.last_work_share = NULL; | ||
| 1596 | start_data->ts.team_id = i; | ||
| 1597 | - start_data->ts.work_share_generation = 0; | ||
| 1598 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 1599 | + start_data->ts.single_count = 0; | ||
| 1600 | +#endif | ||
| 1601 | start_data->ts.static_trip = 0; | ||
| 1602 | start_data->fn = fn; | ||
| 1603 | start_data->fn_data = data; | ||
| 1604 | @@ -303,7 +344,7 @@ gomp_team_start (void (*fn) (void *), vo | ||
| 1605 | gomp_fatal ("Thread creation failed: %s", strerror (err)); | ||
| 1606 | } | ||
| 1607 | |||
| 1608 | - if (gomp_cpu_affinity != NULL) | ||
| 1609 | + if (__builtin_expect (gomp_cpu_affinity != NULL, 0)) | ||
| 1610 | pthread_attr_destroy (&thread_attr); | ||
| 1611 | |||
| 1612 | do_release: | ||
| 1613 | @@ -313,8 +354,20 @@ gomp_team_start (void (*fn) (void *), vo | ||
| 1614 | that should arrive back at the end of this team. The extra | ||
| 1615 | threads should be exiting. Note that we arrange for this test | ||
| 1616 | to never be true for nested teams. */ | ||
| 1617 | - if (nthreads < old_threads_used) | ||
| 1618 | - gomp_barrier_reinit (&gomp_threads_dock, nthreads); | ||
| 1619 | + if (__builtin_expect (nthreads < old_threads_used, 0)) | ||
| 1620 | + { | ||
| 1621 | + long diff = (long) nthreads - (long) old_threads_used; | ||
| 1622 | + | ||
| 1623 | + gomp_barrier_reinit (&gomp_threads_dock, nthreads); | ||
| 1624 | + | ||
| 1625 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 1626 | + __sync_fetch_and_add (&gomp_managed_threads, diff); | ||
| 1627 | +#else | ||
| 1628 | + gomp_mutex_lock (&gomp_remaining_threads_lock); | ||
| 1629 | + gomp_managed_threads += diff; | ||
| 1630 | + gomp_mutex_unlock (&gomp_remaining_threads_lock); | ||
| 1631 | +#endif | ||
| 1632 | + } | ||
| 1633 | } | ||
| 1634 | |||
| 1635 | |||
| 1636 | @@ -329,8 +382,21 @@ gomp_team_end (void) | ||
| 1637 | |||
| 1638 | gomp_barrier_wait (&team->barrier); | ||
| 1639 | |||
| 1640 | + gomp_fini_work_share (thr->ts.work_share); | ||
| 1641 | + | ||
| 1642 | thr->ts = team->prev_ts; | ||
| 1643 | |||
| 1644 | + if (__builtin_expect (thr->ts.team != NULL, 0)) | ||
| 1645 | + { | ||
| 1646 | +#ifdef HAVE_SYNC_BUILTINS | ||
| 1647 | + __sync_fetch_and_add (&gomp_managed_threads, 1L - team->nthreads); | ||
| 1648 | +#else | ||
| 1649 | + gomp_mutex_lock (&gomp_remaining_threads_lock); | ||
| 1650 | + gomp_managed_threads -= team->nthreads - 1L; | ||
| 1651 | + gomp_mutex_unlock (&gomp_remaining_threads_lock); | ||
| 1652 | +#endif | ||
| 1653 | + } | ||
| 1654 | + | ||
| 1655 | free_team (team); | ||
| 1656 | } | ||
| 1657 | |||
| 1658 | --- libgomp/config/posix/bar.h.jj 2007-12-07 14:41:01.000000000 +0100 | ||
| 1659 | +++ libgomp/config/posix/bar.h 2008-03-26 15:11:32.000000000 +0100 | ||
| 1660 | @@ -1,4 +1,4 @@ | ||
| 1661 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 1662 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 1663 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 1664 | |||
| 1665 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 1666 | @@ -46,18 +46,32 @@ typedef struct | ||
| 1667 | unsigned total; | ||
| 1668 | unsigned arrived; | ||
| 1669 | } gomp_barrier_t; | ||
| 1670 | +typedef bool gomp_barrier_state_t; | ||
| 1671 | |||
| 1672 | extern void gomp_barrier_init (gomp_barrier_t *, unsigned); | ||
| 1673 | extern void gomp_barrier_reinit (gomp_barrier_t *, unsigned); | ||
| 1674 | extern void gomp_barrier_destroy (gomp_barrier_t *); | ||
| 1675 | |||
| 1676 | extern void gomp_barrier_wait (gomp_barrier_t *); | ||
| 1677 | -extern void gomp_barrier_wait_end (gomp_barrier_t *, bool); | ||
| 1678 | +extern void gomp_barrier_wait_end (gomp_barrier_t *, gomp_barrier_state_t); | ||
| 1679 | |||
| 1680 | -static inline bool gomp_barrier_wait_start (gomp_barrier_t *bar) | ||
| 1681 | +static inline gomp_barrier_state_t | ||
| 1682 | +gomp_barrier_wait_start (gomp_barrier_t *bar) | ||
| 1683 | { | ||
| 1684 | gomp_mutex_lock (&bar->mutex1); | ||
| 1685 | return ++bar->arrived == bar->total; | ||
| 1686 | } | ||
| 1687 | |||
| 1688 | +static inline bool | ||
| 1689 | +gomp_barrier_last_thread (gomp_barrier_state_t state) | ||
| 1690 | +{ | ||
| 1691 | + return state; | ||
| 1692 | +} | ||
| 1693 | + | ||
| 1694 | +static inline void | ||
| 1695 | +gomp_barrier_wait_last (gomp_barrier_t *bar) | ||
| 1696 | +{ | ||
| 1697 | + gomp_barrier_wait (bar); | ||
| 1698 | +} | ||
| 1699 | + | ||
| 1700 | #endif /* GOMP_BARRIER_H */ | ||
| 1701 | --- libgomp/config/posix/ptrlock.h.jj 2008-03-26 15:11:32.000000000 +0100 | ||
| 1702 | +++ libgomp/config/posix/ptrlock.h 2008-03-26 15:11:32.000000000 +0100 | ||
| 1703 | @@ -0,0 +1,69 @@ | ||
| 1704 | +/* Copyright (C) 2008 Free Software Foundation, Inc. | ||
| 1705 | + Contributed by Jakub Jelinek <jakub@redhat.com>. | ||
| 1706 | + | ||
| 1707 | + This file is part of the GNU OpenMP Library (libgomp). | ||
| 1708 | + | ||
| 1709 | + Libgomp is free software; you can redistribute it and/or modify it | ||
| 1710 | + under the terms of the GNU Lesser General Public License as published by | ||
| 1711 | + the Free Software Foundation; either version 2.1 of the License, or | ||
| 1712 | + (at your option) any later version. | ||
| 1713 | + | ||
| 1714 | + Libgomp is distributed in the hope that it will be useful, but WITHOUT ANY | ||
| 1715 | + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS | ||
| 1716 | + FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for | ||
| 1717 | + more details. | ||
| 1718 | + | ||
| 1719 | + You should have received a copy of the GNU Lesser General Public License | ||
| 1720 | + along with libgomp; see the file COPYING.LIB. If not, write to the | ||
| 1721 | + Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 1722 | + MA 02110-1301, USA. */ | ||
| 1723 | + | ||
| 1724 | +/* As a special exception, if you link this library with other files, some | ||
| 1725 | + of which are compiled with GCC, to produce an executable, this library | ||
| 1726 | + does not by itself cause the resulting executable to be covered by the | ||
| 1727 | + GNU General Public License. This exception does not however invalidate | ||
| 1728 | + any other reasons why the executable file might be covered by the GNU | ||
| 1729 | + General Public License. */ | ||
| 1730 | + | ||
| 1731 | +/* This is a Linux specific implementation of a mutex synchronization | ||
| 1732 | + mechanism for libgomp. This type is private to the library. This | ||
| 1733 | + implementation uses atomic instructions and the futex syscall. */ | ||
| 1734 | + | ||
| 1735 | +#ifndef GOMP_PTRLOCK_H | ||
| 1736 | +#define GOMP_PTRLOCK_H 1 | ||
| 1737 | + | ||
| 1738 | +typedef struct { void *ptr; gomp_mutex_t lock; } gomp_ptrlock_t; | ||
| 1739 | + | ||
| 1740 | +static inline void gomp_ptrlock_init (gomp_ptrlock_t *ptrlock, void *ptr) | ||
| 1741 | +{ | ||
| 1742 | + ptrlock->ptr = ptr; | ||
| 1743 | + gomp_mutex_init (&ptrlock->lock); | ||
| 1744 | +} | ||
| 1745 | + | ||
| 1746 | +static inline void *gomp_ptrlock_get (gomp_ptrlock_t *ptrlock) | ||
| 1747 | +{ | ||
| 1748 | + if (ptrlock->ptr != NULL) | ||
| 1749 | + return ptrlock->ptr; | ||
| 1750 | + | ||
| 1751 | + gomp_mutex_lock (&ptrlock->lock); | ||
| 1752 | + if (ptrlock->ptr != NULL) | ||
| 1753 | + { | ||
| 1754 | + gomp_mutex_unlock (&ptrlock->lock); | ||
| 1755 | + return ptrlock->ptr; | ||
| 1756 | + } | ||
| 1757 | + | ||
| 1758 | + return NULL; | ||
| 1759 | +} | ||
| 1760 | + | ||
| 1761 | +static inline void gomp_ptrlock_set (gomp_ptrlock_t *ptrlock, void *ptr) | ||
| 1762 | +{ | ||
| 1763 | + ptrlock->ptr = ptr; | ||
| 1764 | + gomp_mutex_unlock (&ptrlock->lock); | ||
| 1765 | +} | ||
| 1766 | + | ||
| 1767 | +static inline void gomp_ptrlock_destroy (gomp_ptrlock_t *ptrlock) | ||
| 1768 | +{ | ||
| 1769 | + gomp_mutex_destroy (&ptrlock->lock); | ||
| 1770 | +} | ||
| 1771 | + | ||
| 1772 | +#endif /* GOMP_PTRLOCK_H */ | ||
| 1773 | --- libgomp/config/posix/ptrlock.c.jj 2008-03-26 15:11:32.000000000 +0100 | ||
| 1774 | +++ libgomp/config/posix/ptrlock.c 2008-03-26 15:11:32.000000000 +0100 | ||
| 1775 | @@ -0,0 +1 @@ | ||
| 1776 | +/* Everything is in the header. */ | ||
| 1777 | --- libgomp/config/posix/bar.c.jj 2007-12-07 14:41:01.000000000 +0100 | ||
| 1778 | +++ libgomp/config/posix/bar.c 2008-03-26 15:11:32.000000000 +0100 | ||
| 1779 | @@ -1,4 +1,4 @@ | ||
| 1780 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 1781 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 1782 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 1783 | |||
| 1784 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 1785 | @@ -70,7 +70,7 @@ gomp_barrier_reinit (gomp_barrier_t *bar | ||
| 1786 | } | ||
| 1787 | |||
| 1788 | void | ||
| 1789 | -gomp_barrier_wait_end (gomp_barrier_t *bar, bool last) | ||
| 1790 | +gomp_barrier_wait_end (gomp_barrier_t *bar, gomp_barrier_state_t last) | ||
| 1791 | { | ||
| 1792 | unsigned int n; | ||
| 1793 | |||
| 1794 | --- libgomp/config/linux/alpha/futex.h.jj 2007-12-07 14:41:00.000000000 +0100 | ||
| 1795 | +++ libgomp/config/linux/alpha/futex.h 2008-03-26 15:11:32.000000000 +0100 | ||
| 1796 | @@ -1,4 +1,4 @@ | ||
| 1797 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 1798 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 1799 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 1800 | |||
| 1801 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 1802 | @@ -30,8 +30,6 @@ | ||
| 1803 | #ifndef SYS_futex | ||
| 1804 | #define SYS_futex 394 | ||
| 1805 | #endif | ||
| 1806 | -#define FUTEX_WAIT 0 | ||
| 1807 | -#define FUTEX_WAKE 1 | ||
| 1808 | |||
| 1809 | |||
| 1810 | static inline void | ||
| 1811 | @@ -45,7 +43,7 @@ futex_wait (int *addr, int val) | ||
| 1812 | |||
| 1813 | sc_0 = SYS_futex; | ||
| 1814 | sc_16 = (long) addr; | ||
| 1815 | - sc_17 = FUTEX_WAIT; | ||
| 1816 | + sc_17 = gomp_futex_wait; | ||
| 1817 | sc_18 = val; | ||
| 1818 | sc_19 = 0; | ||
| 1819 | __asm volatile ("callsys" | ||
| 1820 | @@ -53,6 +51,20 @@ futex_wait (int *addr, int val) | ||
| 1821 | : "0"(sc_0), "r" (sc_16), "r"(sc_17), "r"(sc_18), "1"(sc_19) | ||
| 1822 | : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", | ||
| 1823 | "$22", "$23", "$24", "$25", "$27", "$28", "memory"); | ||
| 1824 | + if (__builtin_expect (sc_19, 0) && sc_0 == ENOSYS) | ||
| 1825 | + { | ||
| 1826 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 1827 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 1828 | + sc_0 = SYS_futex; | ||
| 1829 | + sc_17 &= ~FUTEX_PRIVATE_FLAG; | ||
| 1830 | + sc_19 = 0; | ||
| 1831 | + __asm volatile ("callsys" | ||
| 1832 | + : "=r" (sc_0), "=r"(sc_19) | ||
| 1833 | + : "0"(sc_0), "r" (sc_16), "r"(sc_17), "r"(sc_18), | ||
| 1834 | + "1"(sc_19) | ||
| 1835 | + : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", | ||
| 1836 | + "$22", "$23", "$24", "$25", "$27", "$28", "memory"); | ||
| 1837 | + } | ||
| 1838 | } | ||
| 1839 | |||
| 1840 | static inline void | ||
| 1841 | @@ -66,11 +78,35 @@ futex_wake (int *addr, int count) | ||
| 1842 | |||
| 1843 | sc_0 = SYS_futex; | ||
| 1844 | sc_16 = (long) addr; | ||
| 1845 | - sc_17 = FUTEX_WAKE; | ||
| 1846 | + sc_17 = gomp_futex_wake; | ||
| 1847 | sc_18 = count; | ||
| 1848 | __asm volatile ("callsys" | ||
| 1849 | : "=r" (sc_0), "=r"(sc_19) | ||
| 1850 | : "0"(sc_0), "r" (sc_16), "r"(sc_17), "r"(sc_18) | ||
| 1851 | : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", | ||
| 1852 | "$22", "$23", "$24", "$25", "$27", "$28", "memory"); | ||
| 1853 | + if (__builtin_expect (sc_19, 0) && sc_0 == ENOSYS) | ||
| 1854 | + { | ||
| 1855 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 1856 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 1857 | + sc_0 = SYS_futex; | ||
| 1858 | + sc_17 &= ~FUTEX_PRIVATE_FLAG; | ||
| 1859 | + __asm volatile ("callsys" | ||
| 1860 | + : "=r" (sc_0), "=r"(sc_19) | ||
| 1861 | + : "0"(sc_0), "r" (sc_16), "r"(sc_17), "r"(sc_18) | ||
| 1862 | + : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", | ||
| 1863 | + "$22", "$23", "$24", "$25", "$27", "$28", "memory"); | ||
| 1864 | + } | ||
| 1865 | +} | ||
| 1866 | + | ||
| 1867 | +static inline void | ||
| 1868 | +cpu_relax (void) | ||
| 1869 | +{ | ||
| 1870 | + __asm volatile ("" : : : "memory"); | ||
| 1871 | +} | ||
| 1872 | + | ||
| 1873 | +static inline void | ||
| 1874 | +atomic_write_barrier (void) | ||
| 1875 | +{ | ||
| 1876 | + __asm volatile ("wmb" : : : "memory"); | ||
| 1877 | } | ||
| 1878 | --- libgomp/config/linux/affinity.c.jj 2007-12-07 14:41:00.000000000 +0100 | ||
| 1879 | +++ libgomp/config/linux/affinity.c 2008-03-26 15:11:32.000000000 +0100 | ||
| 1880 | @@ -1,4 +1,4 @@ | ||
| 1881 | -/* Copyright (C) 2006, 2007 Free Software Foundation, Inc. | ||
| 1882 | +/* Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc. | ||
| 1883 | Contributed by Jakub Jelinek <jakub@redhat.com>. | ||
| 1884 | |||
| 1885 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 1886 | @@ -38,9 +38,6 @@ | ||
| 1887 | #ifdef HAVE_PTHREAD_AFFINITY_NP | ||
| 1888 | |||
| 1889 | static unsigned int affinity_counter; | ||
| 1890 | -#ifndef HAVE_SYNC_BUILTINS | ||
| 1891 | -static gomp_mutex_t affinity_lock; | ||
| 1892 | -#endif | ||
| 1893 | |||
| 1894 | void | ||
| 1895 | gomp_init_affinity (void) | ||
| 1896 | @@ -76,9 +73,6 @@ gomp_init_affinity (void) | ||
| 1897 | CPU_SET (gomp_cpu_affinity[0], &cpuset); | ||
| 1898 | pthread_setaffinity_np (pthread_self (), sizeof (cpuset), &cpuset); | ||
| 1899 | affinity_counter = 1; | ||
| 1900 | -#ifndef HAVE_SYNC_BUILTINS | ||
| 1901 | - gomp_mutex_init (&affinity_lock); | ||
| 1902 | -#endif | ||
| 1903 | } | ||
| 1904 | |||
| 1905 | void | ||
| 1906 | @@ -87,13 +81,7 @@ gomp_init_thread_affinity (pthread_attr_ | ||
| 1907 | unsigned int cpu; | ||
| 1908 | cpu_set_t cpuset; | ||
| 1909 | |||
| 1910 | -#ifdef HAVE_SYNC_BUILTINS | ||
| 1911 | cpu = __sync_fetch_and_add (&affinity_counter, 1); | ||
| 1912 | -#else | ||
| 1913 | - gomp_mutex_lock (&affinity_lock); | ||
| 1914 | - cpu = affinity_counter++; | ||
| 1915 | - gomp_mutex_unlock (&affinity_lock); | ||
| 1916 | -#endif | ||
| 1917 | cpu %= gomp_cpu_affinity_len; | ||
| 1918 | CPU_ZERO (&cpuset); | ||
| 1919 | CPU_SET (gomp_cpu_affinity[cpu], &cpuset); | ||
| 1920 | --- libgomp/config/linux/bar.h.jj 2007-12-07 14:41:00.000000000 +0100 | ||
| 1921 | +++ libgomp/config/linux/bar.h 2008-03-26 15:11:32.000000000 +0100 | ||
| 1922 | @@ -1,4 +1,4 @@ | ||
| 1923 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 1924 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 1925 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 1926 | |||
| 1927 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 1928 | @@ -36,40 +36,49 @@ | ||
| 1929 | |||
| 1930 | typedef struct | ||
| 1931 | { | ||
| 1932 | - gomp_mutex_t mutex; | ||
| 1933 | - unsigned total; | ||
| 1934 | - unsigned arrived; | ||
| 1935 | - int generation; | ||
| 1936 | + /* Make sure total/generation is in a mostly read cacheline, while | ||
| 1937 | + awaited in a separate cacheline. */ | ||
| 1938 | + unsigned total __attribute__((aligned (64))); | ||
| 1939 | + unsigned generation; | ||
| 1940 | + unsigned awaited __attribute__((aligned (64))); | ||
| 1941 | } gomp_barrier_t; | ||
| 1942 | +typedef unsigned int gomp_barrier_state_t; | ||
| 1943 | |||
| 1944 | static inline void gomp_barrier_init (gomp_barrier_t *bar, unsigned count) | ||
| 1945 | { | ||
| 1946 | - gomp_mutex_init (&bar->mutex); | ||
| 1947 | bar->total = count; | ||
| 1948 | - bar->arrived = 0; | ||
| 1949 | + bar->awaited = count; | ||
| 1950 | bar->generation = 0; | ||
| 1951 | } | ||
| 1952 | |||
| 1953 | static inline void gomp_barrier_reinit (gomp_barrier_t *bar, unsigned count) | ||
| 1954 | { | ||
| 1955 | - gomp_mutex_lock (&bar->mutex); | ||
| 1956 | + __sync_fetch_and_add (&bar->awaited, count - bar->total); | ||
| 1957 | bar->total = count; | ||
| 1958 | - gomp_mutex_unlock (&bar->mutex); | ||
| 1959 | } | ||
| 1960 | |||
| 1961 | static inline void gomp_barrier_destroy (gomp_barrier_t *bar) | ||
| 1962 | { | ||
| 1963 | - /* Before destroying, make sure all threads have left the barrier. */ | ||
| 1964 | - gomp_mutex_lock (&bar->mutex); | ||
| 1965 | } | ||
| 1966 | |||
| 1967 | extern void gomp_barrier_wait (gomp_barrier_t *); | ||
| 1968 | -extern void gomp_barrier_wait_end (gomp_barrier_t *, bool); | ||
| 1969 | +extern void gomp_barrier_wait_last (gomp_barrier_t *); | ||
| 1970 | +extern void gomp_barrier_wait_end (gomp_barrier_t *, gomp_barrier_state_t); | ||
| 1971 | |||
| 1972 | -static inline bool gomp_barrier_wait_start (gomp_barrier_t *bar) | ||
| 1973 | +static inline gomp_barrier_state_t | ||
| 1974 | +gomp_barrier_wait_start (gomp_barrier_t *bar) | ||
| 1975 | { | ||
| 1976 | - gomp_mutex_lock (&bar->mutex); | ||
| 1977 | - return ++bar->arrived == bar->total; | ||
| 1978 | + unsigned int ret = bar->generation; | ||
| 1979 | + /* Do we need any barrier here or is __sync_add_and_fetch acting | ||
| 1980 | + as the needed LoadLoad barrier already? */ | ||
| 1981 | + ret += __sync_add_and_fetch (&bar->awaited, -1) == 0; | ||
| 1982 | + return ret; | ||
| 1983 | +} | ||
| 1984 | + | ||
| 1985 | +static inline bool | ||
| 1986 | +gomp_barrier_last_thread (gomp_barrier_state_t state) | ||
| 1987 | +{ | ||
| 1988 | + return state & 1; | ||
| 1989 | } | ||
| 1990 | |||
| 1991 | #endif /* GOMP_BARRIER_H */ | ||
| 1992 | --- libgomp/config/linux/ptrlock.h.jj 2008-03-26 15:11:32.000000000 +0100 | ||
| 1993 | +++ libgomp/config/linux/ptrlock.h 2008-03-26 15:11:32.000000000 +0100 | ||
| 1994 | @@ -0,0 +1,65 @@ | ||
| 1995 | +/* Copyright (C) 2008 Free Software Foundation, Inc. | ||
| 1996 | + Contributed by Jakub Jelinek <jakub@redhat.com>. | ||
| 1997 | + | ||
| 1998 | + This file is part of the GNU OpenMP Library (libgomp). | ||
| 1999 | + | ||
| 2000 | + Libgomp is free software; you can redistribute it and/or modify it | ||
| 2001 | + under the terms of the GNU Lesser General Public License as published by | ||
| 2002 | + the Free Software Foundation; either version 2.1 of the License, or | ||
| 2003 | + (at your option) any later version. | ||
| 2004 | + | ||
| 2005 | + Libgomp is distributed in the hope that it will be useful, but WITHOUT ANY | ||
| 2006 | + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS | ||
| 2007 | + FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for | ||
| 2008 | + more details. | ||
| 2009 | + | ||
| 2010 | + You should have received a copy of the GNU Lesser General Public License | ||
| 2011 | + along with libgomp; see the file COPYING.LIB. If not, write to the | ||
| 2012 | + Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 2013 | + MA 02110-1301, USA. */ | ||
| 2014 | + | ||
| 2015 | +/* As a special exception, if you link this library with other files, some | ||
| 2016 | + of which are compiled with GCC, to produce an executable, this library | ||
| 2017 | + does not by itself cause the resulting executable to be covered by the | ||
| 2018 | + GNU General Public License. This exception does not however invalidate | ||
| 2019 | + any other reasons why the executable file might be covered by the GNU | ||
| 2020 | + General Public License. */ | ||
| 2021 | + | ||
| 2022 | +/* This is a Linux specific implementation of a mutex synchronization | ||
| 2023 | + mechanism for libgomp. This type is private to the library. This | ||
| 2024 | + implementation uses atomic instructions and the futex syscall. */ | ||
| 2025 | + | ||
| 2026 | +#ifndef GOMP_PTRLOCK_H | ||
| 2027 | +#define GOMP_PTRLOCK_H 1 | ||
| 2028 | + | ||
| 2029 | +typedef void *gomp_ptrlock_t; | ||
| 2030 | + | ||
| 2031 | +static inline void gomp_ptrlock_init (gomp_ptrlock_t *ptrlock, void *ptr) | ||
| 2032 | +{ | ||
| 2033 | + *ptrlock = ptr; | ||
| 2034 | +} | ||
| 2035 | + | ||
| 2036 | +extern void *gomp_ptrlock_get_slow (gomp_ptrlock_t *ptrlock); | ||
| 2037 | +static inline void *gomp_ptrlock_get (gomp_ptrlock_t *ptrlock) | ||
| 2038 | +{ | ||
| 2039 | + if ((uintptr_t) *ptrlock > 2) | ||
| 2040 | + return *ptrlock; | ||
| 2041 | + | ||
| 2042 | + if (__sync_bool_compare_and_swap (ptrlock, NULL, (uintptr_t) 1)) | ||
| 2043 | + return NULL; | ||
| 2044 | + | ||
| 2045 | + return gomp_ptrlock_get_slow (ptrlock); | ||
| 2046 | +} | ||
| 2047 | + | ||
| 2048 | +extern void gomp_ptrlock_set_slow (gomp_ptrlock_t *ptrlock, void *ptr); | ||
| 2049 | +static inline void gomp_ptrlock_set (gomp_ptrlock_t *ptrlock, void *ptr) | ||
| 2050 | +{ | ||
| 2051 | + if (!__sync_bool_compare_and_swap (ptrlock, (uintptr_t) 1, ptr)) | ||
| 2052 | + gomp_ptrlock_set_slow (ptrlock, ptr); | ||
| 2053 | +} | ||
| 2054 | + | ||
| 2055 | +static inline void gomp_ptrlock_destroy (gomp_ptrlock_t *ptrlock) | ||
| 2056 | +{ | ||
| 2057 | +} | ||
| 2058 | + | ||
| 2059 | +#endif /* GOMP_PTRLOCK_H */ | ||
| 2060 | --- libgomp/config/linux/lock.c.jj 2007-12-07 14:41:00.000000000 +0100 | ||
| 2061 | +++ libgomp/config/linux/lock.c 2008-03-26 15:11:32.000000000 +0100 | ||
| 2062 | @@ -29,11 +29,10 @@ | ||
| 2063 | primitives. This implementation uses atomic instructions and the futex | ||
| 2064 | syscall. */ | ||
| 2065 | |||
| 2066 | -#include "libgomp.h" | ||
| 2067 | #include <string.h> | ||
| 2068 | #include <unistd.h> | ||
| 2069 | #include <sys/syscall.h> | ||
| 2070 | -#include "futex.h" | ||
| 2071 | +#include "wait.h" | ||
| 2072 | |||
| 2073 | |||
| 2074 | /* The internal gomp_mutex_t and the external non-recursive omp_lock_t | ||
| 2075 | @@ -137,7 +136,7 @@ omp_set_nest_lock (omp_nest_lock_t *lock | ||
| 2076 | return; | ||
| 2077 | } | ||
| 2078 | |||
| 2079 | - futex_wait (&lock->owner, otid); | ||
| 2080 | + do_wait (&lock->owner, otid); | ||
| 2081 | } | ||
| 2082 | } | ||
| 2083 | |||
| 2084 | --- libgomp/config/linux/ptrlock.c.jj 2008-03-26 15:11:32.000000000 +0100 | ||
| 2085 | +++ libgomp/config/linux/ptrlock.c 2008-03-26 15:11:32.000000000 +0100 | ||
| 2086 | @@ -0,0 +1,70 @@ | ||
| 2087 | +/* Copyright (C) 2008 Free Software Foundation, Inc. | ||
| 2088 | + Contributed by Jakub Jelinek <jakub@redhat.com>. | ||
| 2089 | + | ||
| 2090 | + This file is part of the GNU OpenMP Library (libgomp). | ||
| 2091 | + | ||
| 2092 | + Libgomp is free software; you can redistribute it and/or modify it | ||
| 2093 | + under the terms of the GNU Lesser General Public License as published by | ||
| 2094 | + the Free Software Foundation; either version 2.1 of the License, or | ||
| 2095 | + (at your option) any later version. | ||
| 2096 | + | ||
| 2097 | + Libgomp is distributed in the hope that it will be useful, but WITHOUT ANY | ||
| 2098 | + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS | ||
| 2099 | + FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for | ||
| 2100 | + more details. | ||
| 2101 | + | ||
| 2102 | + You should have received a copy of the GNU Lesser General Public License | ||
| 2103 | + along with libgomp; see the file COPYING.LIB. If not, write to the | ||
| 2104 | + Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 2105 | + MA 02110-1301, USA. */ | ||
| 2106 | + | ||
| 2107 | +/* As a special exception, if you link this library with other files, some | ||
| 2108 | + of which are compiled with GCC, to produce an executable, this library | ||
| 2109 | + does not by itself cause the resulting executable to be covered by the | ||
| 2110 | + GNU General Public License. This exception does not however invalidate | ||
| 2111 | + any other reasons why the executable file might be covered by the GNU | ||
| 2112 | + General Public License. */ | ||
| 2113 | + | ||
| 2114 | +/* This is a Linux specific implementation of a mutex synchronization | ||
| 2115 | + mechanism for libgomp. This type is private to the library. This | ||
| 2116 | + implementation uses atomic instructions and the futex syscall. */ | ||
| 2117 | + | ||
| 2118 | +#include <endian.h> | ||
| 2119 | +#include <limits.h> | ||
| 2120 | +#include "wait.h" | ||
| 2121 | + | ||
| 2122 | +void * | ||
| 2123 | +gomp_ptrlock_get_slow (gomp_ptrlock_t *ptrlock) | ||
| 2124 | +{ | ||
| 2125 | + int *intptr; | ||
| 2126 | + __sync_bool_compare_and_swap (ptrlock, 1, 2); | ||
| 2127 | + | ||
| 2128 | + /* futex works on ints, not pointers. | ||
| 2129 | + But a valid work share pointer will be at least | ||
| 2130 | + 8 byte aligned, so it is safe to assume the low | ||
| 2131 | + 32-bits of the pointer won't contain values 1 or 2. */ | ||
| 2132 | + __asm volatile ("" : "=r" (intptr) : "0" (ptrlock)); | ||
| 2133 | +#if __BYTE_ORDER == __BIG_ENDIAN | ||
| 2134 | + if (sizeof (*ptrlock) > sizeof (int)) | ||
| 2135 | + intptr += (sizeof (*ptrlock) / sizeof (int)) - 1; | ||
| 2136 | +#endif | ||
| 2137 | + do | ||
| 2138 | + do_wait (intptr, 2); | ||
| 2139 | + while (*intptr == 2); | ||
| 2140 | + __asm volatile ("" : : : "memory"); | ||
| 2141 | + return *ptrlock; | ||
| 2142 | +} | ||
| 2143 | + | ||
| 2144 | +void | ||
| 2145 | +gomp_ptrlock_set_slow (gomp_ptrlock_t *ptrlock, void *ptr) | ||
| 2146 | +{ | ||
| 2147 | + int *intptr; | ||
| 2148 | + | ||
| 2149 | + *ptrlock = ptr; | ||
| 2150 | + __asm volatile ("" : "=r" (intptr) : "0" (ptrlock)); | ||
| 2151 | +#if __BYTE_ORDER == __BIG_ENDIAN | ||
| 2152 | + if (sizeof (*ptrlock) > sizeof (int)) | ||
| 2153 | + intptr += (sizeof (*ptrlock) / sizeof (int)) - 1; | ||
| 2154 | +#endif | ||
| 2155 | + futex_wake (intptr, INT_MAX); | ||
| 2156 | +} | ||
| 2157 | --- libgomp/config/linux/x86/futex.h.jj 2007-12-07 14:41:00.000000000 +0100 | ||
| 2158 | +++ libgomp/config/linux/x86/futex.h 2008-03-26 15:11:32.000000000 +0100 | ||
| 2159 | @@ -1,4 +1,4 @@ | ||
| 2160 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 2161 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 2162 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 2163 | |||
| 2164 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 2165 | @@ -27,9 +27,6 @@ | ||
| 2166 | |||
| 2167 | /* Provide target-specific access to the futex system call. */ | ||
| 2168 | |||
| 2169 | -#define FUTEX_WAIT 0 | ||
| 2170 | -#define FUTEX_WAKE 1 | ||
| 2171 | - | ||
| 2172 | #ifdef __LP64__ | ||
| 2173 | # ifndef SYS_futex | ||
| 2174 | # define SYS_futex 202 | ||
| 2175 | @@ -38,14 +35,26 @@ | ||
| 2176 | static inline void | ||
| 2177 | futex_wait (int *addr, int val) | ||
| 2178 | { | ||
| 2179 | - register long r10 __asm__("%r10") = 0; | ||
| 2180 | + register long r10 __asm__("%r10"); | ||
| 2181 | long res; | ||
| 2182 | |||
| 2183 | + r10 = 0; | ||
| 2184 | __asm volatile ("syscall" | ||
| 2185 | : "=a" (res) | ||
| 2186 | - : "0"(SYS_futex), "D" (addr), "S"(FUTEX_WAIT), | ||
| 2187 | - "d"(val), "r"(r10) | ||
| 2188 | + : "0" (SYS_futex), "D" (addr), "S" (gomp_futex_wait), | ||
| 2189 | + "d" (val), "r" (r10) | ||
| 2190 | : "r11", "rcx", "memory"); | ||
| 2191 | + if (__builtin_expect (res == -ENOSYS, 0)) | ||
| 2192 | + { | ||
| 2193 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 2194 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 2195 | + r10 = 0; | ||
| 2196 | + __asm volatile ("syscall" | ||
| 2197 | + : "=a" (res) | ||
| 2198 | + : "0" (SYS_futex), "D" (addr), "S" (gomp_futex_wait), | ||
| 2199 | + "d" (val), "r" (r10) | ||
| 2200 | + : "r11", "rcx", "memory"); | ||
| 2201 | + } | ||
| 2202 | } | ||
| 2203 | |||
| 2204 | static inline void | ||
| 2205 | @@ -55,8 +64,19 @@ futex_wake (int *addr, int count) | ||
| 2206 | |||
| 2207 | __asm volatile ("syscall" | ||
| 2208 | : "=a" (res) | ||
| 2209 | - : "0"(SYS_futex), "D" (addr), "S"(FUTEX_WAKE), "d"(count) | ||
| 2210 | + : "0" (SYS_futex), "D" (addr), "S" (gomp_futex_wake), | ||
| 2211 | + "d" (count) | ||
| 2212 | : "r11", "rcx", "memory"); | ||
| 2213 | + if (__builtin_expect (res == -ENOSYS, 0)) | ||
| 2214 | + { | ||
| 2215 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 2216 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 2217 | + __asm volatile ("syscall" | ||
| 2218 | + : "=a" (res) | ||
| 2219 | + : "0" (SYS_futex), "D" (addr), "S" (gomp_futex_wake), | ||
| 2220 | + "d" (count) | ||
| 2221 | + : "r11", "rcx", "memory"); | ||
| 2222 | + } | ||
| 2223 | } | ||
| 2224 | #else | ||
| 2225 | # ifndef SYS_futex | ||
| 2226 | @@ -65,7 +85,7 @@ futex_wake (int *addr, int count) | ||
| 2227 | |||
| 2228 | # ifdef __PIC__ | ||
| 2229 | |||
| 2230 | -static inline void | ||
| 2231 | +static inline long | ||
| 2232 | sys_futex0 (int *addr, int op, int val) | ||
| 2233 | { | ||
| 2234 | long res; | ||
| 2235 | @@ -77,11 +97,12 @@ sys_futex0 (int *addr, int op, int val) | ||
| 2236 | : "0"(SYS_futex), "r" (addr), "c"(op), | ||
| 2237 | "d"(val), "S"(0) | ||
| 2238 | : "memory"); | ||
| 2239 | + return res; | ||
| 2240 | } | ||
| 2241 | |||
| 2242 | # else | ||
| 2243 | |||
| 2244 | -static inline void | ||
| 2245 | +static inline long | ||
| 2246 | sys_futex0 (int *addr, int op, int val) | ||
| 2247 | { | ||
| 2248 | long res; | ||
| 2249 | @@ -91,6 +112,7 @@ sys_futex0 (int *addr, int op, int val) | ||
| 2250 | : "0"(SYS_futex), "b" (addr), "c"(op), | ||
| 2251 | "d"(val), "S"(0) | ||
| 2252 | : "memory"); | ||
| 2253 | + return res; | ||
| 2254 | } | ||
| 2255 | |||
| 2256 | # endif /* __PIC__ */ | ||
| 2257 | @@ -98,13 +120,37 @@ sys_futex0 (int *addr, int op, int val) | ||
| 2258 | static inline void | ||
| 2259 | futex_wait (int *addr, int val) | ||
| 2260 | { | ||
| 2261 | - sys_futex0 (addr, FUTEX_WAIT, val); | ||
| 2262 | + long res = sys_futex0 (addr, gomp_futex_wait, val); | ||
| 2263 | + if (__builtin_expect (res == -ENOSYS, 0)) | ||
| 2264 | + { | ||
| 2265 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 2266 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 2267 | + sys_futex0 (addr, gomp_futex_wait, val); | ||
| 2268 | + } | ||
| 2269 | } | ||
| 2270 | |||
| 2271 | static inline void | ||
| 2272 | futex_wake (int *addr, int count) | ||
| 2273 | { | ||
| 2274 | - sys_futex0 (addr, FUTEX_WAKE, count); | ||
| 2275 | + long res = sys_futex0 (addr, gomp_futex_wake, count); | ||
| 2276 | + if (__builtin_expect (res == -ENOSYS, 0)) | ||
| 2277 | + { | ||
| 2278 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 2279 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 2280 | + sys_futex0 (addr, gomp_futex_wake, count); | ||
| 2281 | + } | ||
| 2282 | } | ||
| 2283 | |||
| 2284 | #endif /* __LP64__ */ | ||
| 2285 | + | ||
| 2286 | +static inline void | ||
| 2287 | +cpu_relax (void) | ||
| 2288 | +{ | ||
| 2289 | + __asm volatile ("rep; nop" : : : "memory"); | ||
| 2290 | +} | ||
| 2291 | + | ||
| 2292 | +static inline void | ||
| 2293 | +atomic_write_barrier (void) | ||
| 2294 | +{ | ||
| 2295 | + __sync_synchronize (); | ||
| 2296 | +} | ||
| 2297 | --- libgomp/config/linux/wait.h.jj 2008-03-26 15:11:32.000000000 +0100 | ||
| 2298 | +++ libgomp/config/linux/wait.h 2008-03-26 15:11:32.000000000 +0100 | ||
| 2299 | @@ -0,0 +1,68 @@ | ||
| 2300 | +/* Copyright (C) 2008 Free Software Foundation, Inc. | ||
| 2301 | + Contributed by Jakub Jelinek <jakub@redhat.com>. | ||
| 2302 | + | ||
| 2303 | + This file is part of the GNU OpenMP Library (libgomp). | ||
| 2304 | + | ||
| 2305 | + Libgomp is free software; you can redistribute it and/or modify it | ||
| 2306 | + under the terms of the GNU Lesser General Public License as published by | ||
| 2307 | + the Free Software Foundation; either version 2.1 of the License, or | ||
| 2308 | + (at your option) any later version. | ||
| 2309 | + | ||
| 2310 | + Libgomp is distributed in the hope that it will be useful, but WITHOUT ANY | ||
| 2311 | + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS | ||
| 2312 | + FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for | ||
| 2313 | + more details. | ||
| 2314 | + | ||
| 2315 | + You should have received a copy of the GNU Lesser General Public License | ||
| 2316 | + along with libgomp; see the file COPYING.LIB. If not, write to the | ||
| 2317 | + Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 2318 | + MA 02110-1301, USA. */ | ||
| 2319 | + | ||
| 2320 | +/* As a special exception, if you link this library with other files, some | ||
| 2321 | + of which are compiled with GCC, to produce an executable, this library | ||
| 2322 | + does not by itself cause the resulting executable to be covered by the | ||
| 2323 | + GNU General Public License. This exception does not however invalidate | ||
| 2324 | + any other reasons why the executable file might be covered by the GNU | ||
| 2325 | + General Public License. */ | ||
| 2326 | + | ||
| 2327 | +/* This is a Linux specific implementation of a mutex synchronization | ||
| 2328 | + mechanism for libgomp. This type is private to the library. This | ||
| 2329 | + implementation uses atomic instructions and the futex syscall. */ | ||
| 2330 | + | ||
| 2331 | +#ifndef GOMP_WAIT_H | ||
| 2332 | +#define GOMP_WAIT_H 1 | ||
| 2333 | + | ||
| 2334 | +#include "libgomp.h" | ||
| 2335 | +#include <errno.h> | ||
| 2336 | + | ||
| 2337 | +#define FUTEX_WAIT 0 | ||
| 2338 | +#define FUTEX_WAKE 1 | ||
| 2339 | +#define FUTEX_PRIVATE_FLAG 128L | ||
| 2340 | + | ||
| 2341 | +#ifdef HAVE_ATTRIBUTE_VISIBILITY | ||
| 2342 | +# pragma GCC visibility push(hidden) | ||
| 2343 | +#endif | ||
| 2344 | + | ||
| 2345 | +extern long int gomp_futex_wait, gomp_futex_wake; | ||
| 2346 | + | ||
| 2347 | +#include "futex.h" | ||
| 2348 | + | ||
| 2349 | +static inline void do_wait (int *addr, int val) | ||
| 2350 | +{ | ||
| 2351 | + unsigned long long i, count = gomp_spin_count_var; | ||
| 2352 | + | ||
| 2353 | + if (__builtin_expect (gomp_managed_threads > gomp_available_cpus, 0)) | ||
| 2354 | + count = gomp_throttled_spin_count_var; | ||
| 2355 | + for (i = 0; i < count; i++) | ||
| 2356 | + if (__builtin_expect (*addr != val, 0)) | ||
| 2357 | + return; | ||
| 2358 | + else | ||
| 2359 | + cpu_relax (); | ||
| 2360 | + futex_wait (addr, val); | ||
| 2361 | +} | ||
| 2362 | + | ||
| 2363 | +#ifdef HAVE_ATTRIBUTE_VISIBILITY | ||
| 2364 | +# pragma GCC visibility pop | ||
| 2365 | +#endif | ||
| 2366 | + | ||
| 2367 | +#endif /* GOMP_WAIT_H */ | ||
| 2368 | --- libgomp/config/linux/sparc/futex.h.jj 2007-12-07 14:41:00.000000000 +0100 | ||
| 2369 | +++ libgomp/config/linux/sparc/futex.h 2008-03-26 15:11:32.000000000 +0100 | ||
| 2370 | @@ -1,4 +1,4 @@ | ||
| 2371 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 2372 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 2373 | Contributed by Jakub Jelinek <jakub@redhat.com>. | ||
| 2374 | |||
| 2375 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 2376 | @@ -28,10 +28,8 @@ | ||
| 2377 | /* Provide target-specific access to the futex system call. */ | ||
| 2378 | |||
| 2379 | #include <sys/syscall.h> | ||
| 2380 | -#define FUTEX_WAIT 0 | ||
| 2381 | -#define FUTEX_WAKE 1 | ||
| 2382 | |||
| 2383 | -static inline void | ||
| 2384 | +static inline long | ||
| 2385 | sys_futex0 (int *addr, int op, int val) | ||
| 2386 | { | ||
| 2387 | register long int g1 __asm__ ("g1"); | ||
| 2388 | @@ -47,9 +45,9 @@ sys_futex0 (int *addr, int op, int val) | ||
| 2389 | o3 = 0; | ||
| 2390 | |||
| 2391 | #ifdef __arch64__ | ||
| 2392 | -# define SYSCALL_STRING "ta\t0x6d" | ||
| 2393 | +# define SYSCALL_STRING "ta\t0x6d; bcs,a,pt %%xcc, 1f; sub %%g0, %%o0, %%o0; 1:" | ||
| 2394 | #else | ||
| 2395 | -# define SYSCALL_STRING "ta\t0x10" | ||
| 2396 | +# define SYSCALL_STRING "ta\t0x10; bcs,a 1f; sub %%g0, %%o0, %%o0; 1:" | ||
| 2397 | #endif | ||
| 2398 | |||
| 2399 | __asm volatile (SYSCALL_STRING | ||
| 2400 | @@ -65,16 +63,49 @@ sys_futex0 (int *addr, int op, int val) | ||
| 2401 | "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", | ||
| 2402 | #endif | ||
| 2403 | "cc", "memory"); | ||
| 2404 | + return o0; | ||
| 2405 | } | ||
| 2406 | |||
| 2407 | static inline void | ||
| 2408 | futex_wait (int *addr, int val) | ||
| 2409 | { | ||
| 2410 | - sys_futex0 (addr, FUTEX_WAIT, val); | ||
| 2411 | + long err = sys_futex0 (addr, gomp_futex_wait, val); | ||
| 2412 | + if (__builtin_expect (err == ENOSYS, 0)) | ||
| 2413 | + { | ||
| 2414 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 2415 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 2416 | + sys_futex0 (addr, gomp_futex_wait, val); | ||
| 2417 | + } | ||
| 2418 | } | ||
| 2419 | |||
| 2420 | static inline void | ||
| 2421 | futex_wake (int *addr, int count) | ||
| 2422 | { | ||
| 2423 | - sys_futex0 (addr, FUTEX_WAKE, count); | ||
| 2424 | + long err = sys_futex0 (addr, gomp_futex_wake, count); | ||
| 2425 | + if (__builtin_expect (err == ENOSYS, 0)) | ||
| 2426 | + { | ||
| 2427 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 2428 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 2429 | + sys_futex0 (addr, gomp_futex_wake, count); | ||
| 2430 | + } | ||
| 2431 | +} | ||
| 2432 | + | ||
| 2433 | +static inline void | ||
| 2434 | +cpu_relax (void) | ||
| 2435 | +{ | ||
| 2436 | +#if defined __arch64__ || defined __sparc_v9__ | ||
| 2437 | + __asm volatile ("membar #LoadLoad" : : : "memory"); | ||
| 2438 | +#else | ||
| 2439 | + __asm volatile ("" : : : "memory"); | ||
| 2440 | +#endif | ||
| 2441 | +} | ||
| 2442 | + | ||
| 2443 | +static inline void | ||
| 2444 | +atomic_write_barrier (void) | ||
| 2445 | +{ | ||
| 2446 | +#if defined __arch64__ || defined __sparc_v9__ | ||
| 2447 | + __asm volatile ("membar #StoreStore" : : : "memory"); | ||
| 2448 | +#else | ||
| 2449 | + __sync_synchronize (); | ||
| 2450 | +#endif | ||
| 2451 | } | ||
| 2452 | --- libgomp/config/linux/ia64/futex.h.jj 2007-12-07 14:41:00.000000000 +0100 | ||
| 2453 | +++ libgomp/config/linux/ia64/futex.h 2008-03-26 15:11:32.000000000 +0100 | ||
| 2454 | @@ -1,4 +1,4 @@ | ||
| 2455 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 2456 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 2457 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 2458 | |||
| 2459 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 2460 | @@ -29,23 +29,24 @@ | ||
| 2461 | |||
| 2462 | #include <sys/syscall.h> | ||
| 2463 | |||
| 2464 | -#define FUTEX_WAIT 0 | ||
| 2465 | -#define FUTEX_WAKE 1 | ||
| 2466 | |||
| 2467 | |||
| 2468 | -static inline void | ||
| 2469 | -sys_futex0(int *addr, int op, int val) | ||
| 2470 | +static inline long | ||
| 2471 | +sys_futex0(int *addr, long op, int val) | ||
| 2472 | { | ||
| 2473 | register long out0 asm ("out0") = (long) addr; | ||
| 2474 | register long out1 asm ("out1") = op; | ||
| 2475 | register long out2 asm ("out2") = val; | ||
| 2476 | register long out3 asm ("out3") = 0; | ||
| 2477 | + register long r8 asm ("r8"); | ||
| 2478 | + register long r10 asm ("r10"); | ||
| 2479 | register long r15 asm ("r15") = SYS_futex; | ||
| 2480 | |||
| 2481 | __asm __volatile ("break 0x100000" | ||
| 2482 | - : "=r"(r15), "=r"(out0), "=r"(out1), "=r"(out2), "=r"(out3) | ||
| 2483 | + : "=r"(r15), "=r"(out0), "=r"(out1), "=r"(out2), "=r"(out3), | ||
| 2484 | + "=r"(r8), "=r"(r10) | ||
| 2485 | : "r"(r15), "r"(out0), "r"(out1), "r"(out2), "r"(out3) | ||
| 2486 | - : "memory", "r8", "r10", "out4", "out5", "out6", "out7", | ||
| 2487 | + : "memory", "out4", "out5", "out6", "out7", | ||
| 2488 | /* Non-stacked integer registers, minus r8, r10, r15. */ | ||
| 2489 | "r2", "r3", "r9", "r11", "r12", "r13", "r14", "r16", "r17", "r18", | ||
| 2490 | "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", | ||
| 2491 | @@ -56,16 +57,41 @@ sys_futex0(int *addr, int op, int val) | ||
| 2492 | "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | ||
| 2493 | /* Branch registers. */ | ||
| 2494 | "b6"); | ||
| 2495 | + return r8 & r10; | ||
| 2496 | } | ||
| 2497 | |||
| 2498 | static inline void | ||
| 2499 | futex_wait (int *addr, int val) | ||
| 2500 | { | ||
| 2501 | - sys_futex0 (addr, FUTEX_WAIT, val); | ||
| 2502 | + long err = sys_futex0 (addr, gomp_futex_wait, val); | ||
| 2503 | + if (__builtin_expect (err == ENOSYS, 0)) | ||
| 2504 | + { | ||
| 2505 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 2506 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 2507 | + sys_futex0 (addr, gomp_futex_wait, val); | ||
| 2508 | + } | ||
| 2509 | } | ||
| 2510 | |||
| 2511 | static inline void | ||
| 2512 | futex_wake (int *addr, int count) | ||
| 2513 | { | ||
| 2514 | - sys_futex0 (addr, FUTEX_WAKE, count); | ||
| 2515 | + long err = sys_futex0 (addr, gomp_futex_wake, count); | ||
| 2516 | + if (__builtin_expect (err == ENOSYS, 0)) | ||
| 2517 | + { | ||
| 2518 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 2519 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 2520 | + sys_futex0 (addr, gomp_futex_wake, count); | ||
| 2521 | + } | ||
| 2522 | +} | ||
| 2523 | + | ||
| 2524 | +static inline void | ||
| 2525 | +cpu_relax (void) | ||
| 2526 | +{ | ||
| 2527 | + __asm volatile ("hint @pause" : : : "memory"); | ||
| 2528 | +} | ||
| 2529 | + | ||
| 2530 | +static inline void | ||
| 2531 | +atomic_write_barrier (void) | ||
| 2532 | +{ | ||
| 2533 | + __sync_synchronize (); | ||
| 2534 | } | ||
| 2535 | --- libgomp/config/linux/s390/futex.h.jj 2007-12-07 14:41:00.000000000 +0100 | ||
| 2536 | +++ libgomp/config/linux/s390/futex.h 2008-03-26 15:11:32.000000000 +0100 | ||
| 2537 | @@ -1,4 +1,4 @@ | ||
| 2538 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 2539 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 2540 | Contributed by Jakub Jelinek <jakub@redhat.com>. | ||
| 2541 | |||
| 2542 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 2543 | @@ -28,10 +28,8 @@ | ||
| 2544 | /* Provide target-specific access to the futex system call. */ | ||
| 2545 | |||
| 2546 | #include <sys/syscall.h> | ||
| 2547 | -#define FUTEX_WAIT 0 | ||
| 2548 | -#define FUTEX_WAKE 1 | ||
| 2549 | |||
| 2550 | -static inline void | ||
| 2551 | +static inline long | ||
| 2552 | sys_futex0 (int *addr, int op, int val) | ||
| 2553 | { | ||
| 2554 | register long int gpr2 __asm__ ("2"); | ||
| 2555 | @@ -49,16 +47,41 @@ sys_futex0 (int *addr, int op, int val) | ||
| 2556 | : "i" (SYS_futex), | ||
| 2557 | "0" (gpr2), "d" (gpr3), "d" (gpr4), "d" (gpr5) | ||
| 2558 | : "memory"); | ||
| 2559 | + return gpr2; | ||
| 2560 | } | ||
| 2561 | |||
| 2562 | static inline void | ||
| 2563 | futex_wait (int *addr, int val) | ||
| 2564 | { | ||
| 2565 | - sys_futex0 (addr, FUTEX_WAIT, val); | ||
| 2566 | + long err = sys_futex0 (addr, gomp_futex_wait, val); | ||
| 2567 | + if (__builtin_expect (err == -ENOSYS, 0)) | ||
| 2568 | + { | ||
| 2569 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 2570 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 2571 | + sys_futex0 (addr, gomp_futex_wait, val); | ||
| 2572 | + } | ||
| 2573 | } | ||
| 2574 | |||
| 2575 | static inline void | ||
| 2576 | futex_wake (int *addr, int count) | ||
| 2577 | { | ||
| 2578 | - sys_futex0 (addr, FUTEX_WAKE, count); | ||
| 2579 | + long err = sys_futex0 (addr, gomp_futex_wake, count); | ||
| 2580 | + if (__builtin_expect (err == -ENOSYS, 0)) | ||
| 2581 | + { | ||
| 2582 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 2583 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 2584 | + sys_futex0 (addr, gomp_futex_wake, count); | ||
| 2585 | + } | ||
| 2586 | +} | ||
| 2587 | + | ||
| 2588 | +static inline void | ||
| 2589 | +cpu_relax (void) | ||
| 2590 | +{ | ||
| 2591 | + __asm volatile ("" : : : "memory"); | ||
| 2592 | +} | ||
| 2593 | + | ||
| 2594 | +static inline void | ||
| 2595 | +atomic_write_barrier (void) | ||
| 2596 | +{ | ||
| 2597 | + __sync_synchronize (); | ||
| 2598 | } | ||
| 2599 | --- libgomp/config/linux/mutex.c.jj 2007-12-07 14:41:00.000000000 +0100 | ||
| 2600 | +++ libgomp/config/linux/mutex.c 2008-03-26 15:11:32.000000000 +0100 | ||
| 2601 | @@ -1,4 +1,4 @@ | ||
| 2602 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 2603 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 2604 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 2605 | |||
| 2606 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 2607 | @@ -29,9 +29,10 @@ | ||
| 2608 | mechanism for libgomp. This type is private to the library. This | ||
| 2609 | implementation uses atomic instructions and the futex syscall. */ | ||
| 2610 | |||
| 2611 | -#include "libgomp.h" | ||
| 2612 | -#include "futex.h" | ||
| 2613 | +#include "wait.h" | ||
| 2614 | |||
| 2615 | +long int gomp_futex_wake = FUTEX_WAKE | FUTEX_PRIVATE_FLAG; | ||
| 2616 | +long int gomp_futex_wait = FUTEX_WAIT | FUTEX_PRIVATE_FLAG; | ||
| 2617 | |||
| 2618 | void | ||
| 2619 | gomp_mutex_lock_slow (gomp_mutex_t *mutex) | ||
| 2620 | @@ -40,7 +41,7 @@ gomp_mutex_lock_slow (gomp_mutex_t *mute | ||
| 2621 | { | ||
| 2622 | int oldval = __sync_val_compare_and_swap (mutex, 1, 2); | ||
| 2623 | if (oldval != 0) | ||
| 2624 | - futex_wait (mutex, 2); | ||
| 2625 | + do_wait (mutex, 2); | ||
| 2626 | } | ||
| 2627 | while (!__sync_bool_compare_and_swap (mutex, 0, 2)); | ||
| 2628 | } | ||
| 2629 | --- libgomp/config/linux/sem.c.jj 2007-12-07 14:41:00.000000000 +0100 | ||
| 2630 | +++ libgomp/config/linux/sem.c 2008-03-26 15:11:32.000000000 +0100 | ||
| 2631 | @@ -1,4 +1,4 @@ | ||
| 2632 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 2633 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 2634 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 2635 | |||
| 2636 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 2637 | @@ -29,8 +29,7 @@ | ||
| 2638 | mechanism for libgomp. This type is private to the library. This | ||
| 2639 | implementation uses atomic instructions and the futex syscall. */ | ||
| 2640 | |||
| 2641 | -#include "libgomp.h" | ||
| 2642 | -#include "futex.h" | ||
| 2643 | +#include "wait.h" | ||
| 2644 | |||
| 2645 | |||
| 2646 | void | ||
| 2647 | @@ -44,7 +43,7 @@ gomp_sem_wait_slow (gomp_sem_t *sem) | ||
| 2648 | if (__sync_bool_compare_and_swap (sem, val, val - 1)) | ||
| 2649 | return; | ||
| 2650 | } | ||
| 2651 | - futex_wait (sem, -1); | ||
| 2652 | + do_wait (sem, -1); | ||
| 2653 | } | ||
| 2654 | } | ||
| 2655 | |||
| 2656 | --- libgomp/config/linux/powerpc/futex.h.jj 2007-12-07 14:41:00.000000000 +0100 | ||
| 2657 | +++ libgomp/config/linux/powerpc/futex.h 2008-03-26 15:11:32.000000000 +0100 | ||
| 2658 | @@ -1,4 +1,4 @@ | ||
| 2659 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 2660 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 2661 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 2662 | |||
| 2663 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 2664 | @@ -28,10 +28,8 @@ | ||
| 2665 | /* Provide target-specific access to the futex system call. */ | ||
| 2666 | |||
| 2667 | #include <sys/syscall.h> | ||
| 2668 | -#define FUTEX_WAIT 0 | ||
| 2669 | -#define FUTEX_WAKE 1 | ||
| 2670 | |||
| 2671 | -static inline void | ||
| 2672 | +static inline long | ||
| 2673 | sys_futex0 (int *addr, int op, int val) | ||
| 2674 | { | ||
| 2675 | register long int r0 __asm__ ("r0"); | ||
| 2676 | @@ -50,21 +48,48 @@ sys_futex0 (int *addr, int op, int val) | ||
| 2677 | doesn't. It doesn't much matter for us. In the interest of unity, | ||
| 2678 | go ahead and clobber it always. */ | ||
| 2679 | |||
| 2680 | - __asm volatile ("sc" | ||
| 2681 | + __asm volatile ("sc; mfcr %0" | ||
| 2682 | : "=r"(r0), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6) | ||
| 2683 | : "r"(r0), "r"(r3), "r"(r4), "r"(r5), "r"(r6) | ||
| 2684 | : "r7", "r8", "r9", "r10", "r11", "r12", | ||
| 2685 | "cr0", "ctr", "memory"); | ||
| 2686 | + if (__builtin_expect (r0 & (1 << 28), 0)) | ||
| 2687 | + return r3; | ||
| 2688 | + return 0; | ||
| 2689 | } | ||
| 2690 | |||
| 2691 | static inline void | ||
| 2692 | futex_wait (int *addr, int val) | ||
| 2693 | { | ||
| 2694 | - sys_futex0 (addr, FUTEX_WAIT, val); | ||
| 2695 | + long err = sys_futex0 (addr, gomp_futex_wait, val); | ||
| 2696 | + if (__builtin_expect (err == ENOSYS, 0)) | ||
| 2697 | + { | ||
| 2698 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 2699 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 2700 | + sys_futex0 (addr, gomp_futex_wait, val); | ||
| 2701 | + } | ||
| 2702 | } | ||
| 2703 | |||
| 2704 | static inline void | ||
| 2705 | futex_wake (int *addr, int count) | ||
| 2706 | { | ||
| 2707 | - sys_futex0 (addr, FUTEX_WAKE, count); | ||
| 2708 | + long err = sys_futex0 (addr, gomp_futex_wake, count); | ||
| 2709 | + if (__builtin_expect (err == ENOSYS, 0)) | ||
| 2710 | + { | ||
| 2711 | + gomp_futex_wait &= ~FUTEX_PRIVATE_FLAG; | ||
| 2712 | + gomp_futex_wake &= ~FUTEX_PRIVATE_FLAG; | ||
| 2713 | + sys_futex0 (addr, gomp_futex_wake, count); | ||
| 2714 | + } | ||
| 2715 | +} | ||
| 2716 | + | ||
| 2717 | +static inline void | ||
| 2718 | +cpu_relax (void) | ||
| 2719 | +{ | ||
| 2720 | + __asm volatile ("" : : : "memory"); | ||
| 2721 | +} | ||
| 2722 | + | ||
| 2723 | +static inline void | ||
| 2724 | +atomic_write_barrier (void) | ||
| 2725 | +{ | ||
| 2726 | + __asm volatile ("eieio" : : : "memory"); | ||
| 2727 | } | ||
| 2728 | --- libgomp/config/linux/bar.c.jj 2007-12-07 14:41:00.000000000 +0100 | ||
| 2729 | +++ libgomp/config/linux/bar.c 2008-03-26 15:11:32.000000000 +0100 | ||
| 2730 | @@ -1,4 +1,4 @@ | ||
| 2731 | -/* Copyright (C) 2005 Free Software Foundation, Inc. | ||
| 2732 | +/* Copyright (C) 2005, 2008 Free Software Foundation, Inc. | ||
| 2733 | Contributed by Richard Henderson <rth@redhat.com>. | ||
| 2734 | |||
| 2735 | This file is part of the GNU OpenMP Library (libgomp). | ||
| 2736 | @@ -29,32 +29,29 @@ | ||
| 2737 | mechanism for libgomp. This type is private to the library. This | ||
| 2738 | implementation uses atomic instructions and the futex syscall. */ | ||
| 2739 | |||
| 2740 | -#include "libgomp.h" | ||
| 2741 | -#include "futex.h" | ||
| 2742 | #include <limits.h> | ||
| 2743 | +#include "wait.h" | ||
| 2744 | |||
| 2745 | |||
| 2746 | void | ||
| 2747 | -gomp_barrier_wait_end (gomp_barrier_t *bar, bool last) | ||
| 2748 | +gomp_barrier_wait_end (gomp_barrier_t *bar, gomp_barrier_state_t state) | ||
| 2749 | { | ||
| 2750 | - if (last) | ||
| 2751 | + if (__builtin_expect ((state & 1) != 0, 0)) | ||
| 2752 | { | ||
| 2753 | - bar->generation++; | ||
| 2754 | - futex_wake (&bar->generation, INT_MAX); | ||
| 2755 | + /* Next time we'll be awaiting TOTAL threads again. */ | ||
| 2756 | + bar->awaited = bar->total; | ||
| 2757 | + atomic_write_barrier (); | ||
| 2758 | + bar->generation += 2; | ||
| 2759 | + futex_wake ((int *) &bar->generation, INT_MAX); | ||
| 2760 | } | ||
| 2761 | else | ||
| 2762 | { | ||
| 2763 | - unsigned int generation = bar->generation; | ||
| 2764 | - | ||
| 2765 | - gomp_mutex_unlock (&bar->mutex); | ||
| 2766 | + unsigned int generation = state; | ||
| 2767 | |||
| 2768 | do | ||
| 2769 | - futex_wait (&bar->generation, generation); | ||
| 2770 | + do_wait ((int *) &bar->generation, generation); | ||
| 2771 | while (bar->generation == generation); | ||
| 2772 | } | ||
| 2773 | - | ||
| 2774 | - if (__sync_add_and_fetch (&bar->arrived, -1) == 0) | ||
| 2775 | - gomp_mutex_unlock (&bar->mutex); | ||
| 2776 | } | ||
| 2777 | |||
| 2778 | void | ||
| 2779 | @@ -62,3 +59,18 @@ gomp_barrier_wait (gomp_barrier_t *barri | ||
| 2780 | { | ||
| 2781 | gomp_barrier_wait_end (barrier, gomp_barrier_wait_start (barrier)); | ||
| 2782 | } | ||
| 2783 | + | ||
| 2784 | +/* Like gomp_barrier_wait, except that if the encountering thread | ||
| 2785 | + is not the last one to hit the barrier, it returns immediately. | ||
| 2786 | + The intended usage is that a thread which intends to gomp_barrier_destroy | ||
| 2787 | + this barrier calls gomp_barrier_wait, while all other threads | ||
| 2788 | + call gomp_barrier_wait_last. When gomp_barrier_wait returns, | ||
| 2789 | + the barrier can be safely destroyed. */ | ||
| 2790 | + | ||
| 2791 | +void | ||
| 2792 | +gomp_barrier_wait_last (gomp_barrier_t *barrier) | ||
| 2793 | +{ | ||
| 2794 | + gomp_barrier_state_t state = gomp_barrier_wait_start (barrier); | ||
| 2795 | + if (state & 1) | ||
| 2796 | + gomp_barrier_wait_end (barrier, state); | ||
| 2797 | +} | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ppc32-retaddr.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ppc32-retaddr.patch deleted file mode 100644 index 3de4158eb..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ppc32-retaddr.patch +++ /dev/null | |||
| @@ -1,90 +0,0 @@ | |||
| 1 | 2005-11-28 Jakub Jelinek <jakub@redhat.com> | ||
| 2 | |||
| 3 | * config/rs6000/rs6000.c (rs6000_return_addr): If COUNT == 0, | ||
| 4 | read word RETURN_ADDRESS_OFFSET bytes above arg_pointer_rtx | ||
| 5 | instead of doing an extran indirection from frame_pointer_rtx. | ||
| 6 | |||
| 7 | * gcc.dg/20051128-1.c: New test. | ||
| 8 | |||
| 9 | Index: gcc/config/rs6000/rs6000.c | ||
| 10 | =================================================================== | ||
| 11 | --- gcc/config/rs6000/rs6000.c.orig 2010-03-27 03:27:39.000000000 -0700 | ||
| 12 | +++ gcc/config/rs6000/rs6000.c 2010-06-25 10:18:04.053381930 -0700 | ||
| 13 | @@ -17646,17 +17646,22 @@ | ||
| 14 | don't try to be too clever here. */ | ||
| 15 | if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) | ||
| 16 | { | ||
| 17 | + rtx x; | ||
| 18 | cfun->machine->ra_needs_full_frame = 1; | ||
| 19 | |||
| 20 | - return | ||
| 21 | - gen_rtx_MEM | ||
| 22 | - (Pmode, | ||
| 23 | - memory_address | ||
| 24 | - (Pmode, | ||
| 25 | - plus_constant (copy_to_reg | ||
| 26 | - (gen_rtx_MEM (Pmode, | ||
| 27 | - memory_address (Pmode, frame))), | ||
| 28 | - RETURN_ADDRESS_OFFSET))); | ||
| 29 | + if (count == 0) | ||
| 30 | + { | ||
| 31 | + gcc_assert (frame == frame_pointer_rtx); | ||
| 32 | + x = arg_pointer_rtx; | ||
| 33 | + } | ||
| 34 | + else | ||
| 35 | + { | ||
| 36 | + x = memory_address (Pmode, frame); | ||
| 37 | + x = copy_to_reg (gen_rtx_MEM (Pmode, x)); | ||
| 38 | + } | ||
| 39 | + | ||
| 40 | + x = plus_constant (x, RETURN_ADDRESS_OFFSET); | ||
| 41 | + return gen_rtx_MEM (Pmode, memory_address (Pmode, x)); | ||
| 42 | } | ||
| 43 | |||
| 44 | cfun->machine->ra_need_lr = 1; | ||
| 45 | Index: gcc/testsuite/gcc.dg/20051128-1.c | ||
| 46 | =================================================================== | ||
| 47 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 48 | +++ gcc/testsuite/gcc.dg/20051128-1.c 2010-06-25 10:18:04.061382856 -0700 | ||
| 49 | @@ -0,0 +1,41 @@ | ||
| 50 | +/* { dg-do run } */ | ||
| 51 | +/* { dg-options "-O2 -fpic" } */ | ||
| 52 | + | ||
| 53 | +extern void exit (int); | ||
| 54 | +extern void abort (void); | ||
| 55 | + | ||
| 56 | +int b; | ||
| 57 | + | ||
| 58 | +struct A | ||
| 59 | +{ | ||
| 60 | + void *pad[147]; | ||
| 61 | + void *ra, *h; | ||
| 62 | + long o; | ||
| 63 | +}; | ||
| 64 | + | ||
| 65 | +void | ||
| 66 | +__attribute__((noinline)) | ||
| 67 | +foo (struct A *a, void *x) | ||
| 68 | +{ | ||
| 69 | + __builtin_memset (a, 0, sizeof (a)); | ||
| 70 | + if (!b) | ||
| 71 | + exit (0); | ||
| 72 | +} | ||
| 73 | + | ||
| 74 | +void | ||
| 75 | +__attribute__((noinline)) | ||
| 76 | +bar (void) | ||
| 77 | +{ | ||
| 78 | + struct A a; | ||
| 79 | + | ||
| 80 | + __builtin_unwind_init (); | ||
| 81 | + foo (&a, __builtin_return_address (0)); | ||
| 82 | +} | ||
| 83 | + | ||
| 84 | +int | ||
| 85 | +main (void) | ||
| 86 | +{ | ||
| 87 | + bar (); | ||
| 88 | + abort (); | ||
| 89 | + return 0; | ||
| 90 | +} | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr27898.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr27898.patch deleted file mode 100644 index 172bb8117..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr27898.patch +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | 2006-08-18 Jakub Jelinek <jakub@redhat.com> | ||
| 2 | |||
| 3 | PR c/27898 | ||
| 4 | * gcc.dg/pr27898.c: New test. | ||
| 5 | |||
| 6 | --- gcc/testsuite/gcc.dg/pr27898.c.jj 2006-08-18 09:19:33.000000000 +0200 | ||
| 7 | +++ gcc/testsuite/gcc.dg/pr27898.c 2006-08-18 09:19:27.000000000 +0200 | ||
| 8 | @@ -0,0 +1,8 @@ | ||
| 9 | +/* PR c/27898 */ | ||
| 10 | +/* { dg-do compile } */ | ||
| 11 | +/* { dg-options "--combine" } */ | ||
| 12 | +/* { dg-additional-sources "pr27898.c" } */ | ||
| 13 | + | ||
| 14 | +union u { struct { int i; }; }; | ||
| 15 | + | ||
| 16 | +extern int foo (union u *); | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr32139.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr32139.patch deleted file mode 100644 index f35696703..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr32139.patch +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | 2007-06-01 Jakub Jelinek <jakub@redhat.com> | ||
| 2 | |||
| 3 | PR tree-optimization/32139 | ||
| 4 | * gcc.c-torture/compile/20070531-1.c: New test. | ||
| 5 | |||
| 6 | --- gcc/testsuite/gcc.c-torture/compile/20070531-1.c.jj 2007-05-31 13:47:22.000000000 +0200 | ||
| 7 | +++ gcc/testsuite/gcc.c-torture/compile/20070531-1.c 2007-06-01 10:57:15.000000000 +0200 | ||
| 8 | @@ -0,0 +1,11 @@ | ||
| 9 | +/* PR tree-optimization/32139 */ | ||
| 10 | +int foo (void); | ||
| 11 | +int bar (void) __attribute__ ((const)); | ||
| 12 | + | ||
| 13 | +int | ||
| 14 | +test (int x) | ||
| 15 | +{ | ||
| 16 | + int a = (x == 10000 ? foo : bar) (); | ||
| 17 | + int b = (x == 10000 ? foo : bar) (); | ||
| 18 | + return a + b; | ||
| 19 | +} | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr33763.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr33763.patch deleted file mode 100644 index 68c30650f..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr33763.patch +++ /dev/null | |||
| @@ -1,159 +0,0 @@ | |||
| 1 | 2007-11-06 Jakub Jelinek <jakub@redhat.com> | ||
| 2 | |||
| 3 | PR tree-optimization/33763 | ||
| 4 | * gcc.dg/pr33763.c: New test. | ||
| 5 | * g++.dg/opt/inline13.C: New test. | ||
| 6 | |||
| 7 | 2007-11-06 Jan Hubicka <jh@suse.cz> | ||
| 8 | |||
| 9 | PR tree-optimization/33763 | ||
| 10 | * tree-inline.c (expand_call_inline): Silently ignore always_inline | ||
| 11 | attribute for redefined extern inline functions. | ||
| 12 | |||
| 13 | Index: gcc/tree-inline.c | ||
| 14 | =================================================================== | ||
| 15 | --- gcc/tree-inline.c.orig 2010-03-18 13:07:13.000000000 -0700 | ||
| 16 | +++ gcc/tree-inline.c 2010-06-25 10:18:51.230139825 -0700 | ||
| 17 | @@ -3545,6 +3545,12 @@ | ||
| 18 | goto egress; | ||
| 19 | |||
| 20 | if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (fn)) | ||
| 21 | + /* For extern inline functions that get redefined we always | ||
| 22 | + silently ignored alway_inline flag. Better behaviour would | ||
| 23 | + be to be able to keep both bodies and use extern inline body | ||
| 24 | + for inlining, but we can't do that because frontends overwrite | ||
| 25 | + the body. */ | ||
| 26 | + && !cg_edge->callee->local.redefined_extern_inline | ||
| 27 | /* Avoid warnings during early inline pass. */ | ||
| 28 | && cgraph_global_info_ready) | ||
| 29 | { | ||
| 30 | Index: gcc/testsuite/gcc.dg/pr33763.c | ||
| 31 | =================================================================== | ||
| 32 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 33 | +++ gcc/testsuite/gcc.dg/pr33763.c 2010-06-25 10:18:51.234141302 -0700 | ||
| 34 | @@ -0,0 +1,60 @@ | ||
| 35 | +/* PR tree-optimization/33763 */ | ||
| 36 | +/* { dg-do compile } */ | ||
| 37 | +/* { dg-options "-O2" } */ | ||
| 38 | + | ||
| 39 | +typedef struct | ||
| 40 | +{ | ||
| 41 | + void *a; | ||
| 42 | + void *b; | ||
| 43 | +} T; | ||
| 44 | +extern void *foo (const char *, const char *); | ||
| 45 | +extern void *bar (void *, const char *, T); | ||
| 46 | +extern int baz (const char *, int); | ||
| 47 | + | ||
| 48 | +extern inline __attribute__ ((always_inline, gnu_inline)) int | ||
| 49 | +baz (const char *x, int y) | ||
| 50 | +{ | ||
| 51 | + return 2; | ||
| 52 | +} | ||
| 53 | + | ||
| 54 | +int | ||
| 55 | +baz (const char *x, int y) | ||
| 56 | +{ | ||
| 57 | + return 1; | ||
| 58 | +} | ||
| 59 | + | ||
| 60 | +int xa, xb; | ||
| 61 | + | ||
| 62 | +static void * | ||
| 63 | +inl (const char *x, const char *y) | ||
| 64 | +{ | ||
| 65 | + T t = { &xa, &xb }; | ||
| 66 | + int *f = (int *) __builtin_malloc (sizeof (int)); | ||
| 67 | + const char *z; | ||
| 68 | + int o = 0; | ||
| 69 | + void *r = 0; | ||
| 70 | + | ||
| 71 | + for (z = y; *z; z++) | ||
| 72 | + { | ||
| 73 | + if (*z == 'r') | ||
| 74 | + o |= 1; | ||
| 75 | + if (*z == 'w') | ||
| 76 | + o |= 2; | ||
| 77 | + } | ||
| 78 | + if (o == 1) | ||
| 79 | + *f = baz (x, 0); | ||
| 80 | + if (o == 2) | ||
| 81 | + *f = baz (x, 1); | ||
| 82 | + if (o == 3) | ||
| 83 | + *f = baz (x, 2); | ||
| 84 | + | ||
| 85 | + if (o && *f > 0) | ||
| 86 | + r = bar (f, "w", t); | ||
| 87 | + return r; | ||
| 88 | +} | ||
| 89 | + | ||
| 90 | +void * | ||
| 91 | +foo (const char *x, const char *y) | ||
| 92 | +{ | ||
| 93 | + return inl (x, y); | ||
| 94 | +} | ||
| 95 | Index: gcc/testsuite/g++.dg/opt/inline13.C | ||
| 96 | =================================================================== | ||
| 97 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 98 | +++ gcc/testsuite/g++.dg/opt/inline13.C 2010-06-25 10:18:51.261052137 -0700 | ||
| 99 | @@ -0,0 +1,60 @@ | ||
| 100 | +// PR tree-optimization/33763 | ||
| 101 | +// { dg-do compile } | ||
| 102 | +// { dg-options "-O2" } | ||
| 103 | + | ||
| 104 | +typedef struct | ||
| 105 | +{ | ||
| 106 | + void *a; | ||
| 107 | + void *b; | ||
| 108 | +} T; | ||
| 109 | +extern void *foo (const char *, const char *); | ||
| 110 | +extern void *bar (void *, const char *, T); | ||
| 111 | +extern int baz (const char *, int); | ||
| 112 | + | ||
| 113 | +extern inline __attribute__ ((always_inline, gnu_inline)) int | ||
| 114 | +baz (const char *x, int y) | ||
| 115 | +{ | ||
| 116 | + return 2; | ||
| 117 | +} | ||
| 118 | + | ||
| 119 | +int | ||
| 120 | +baz (const char *x, int y) | ||
| 121 | +{ | ||
| 122 | + return 1; | ||
| 123 | +} | ||
| 124 | + | ||
| 125 | +int xa, xb; | ||
| 126 | + | ||
| 127 | +static void * | ||
| 128 | +inl (const char *x, const char *y) | ||
| 129 | +{ | ||
| 130 | + T t = { &xa, &xb }; | ||
| 131 | + int *f = (int *) __builtin_malloc (sizeof (int)); | ||
| 132 | + const char *z; | ||
| 133 | + int o = 0; | ||
| 134 | + void *r = 0; | ||
| 135 | + | ||
| 136 | + for (z = y; *z; z++) | ||
| 137 | + { | ||
| 138 | + if (*z == 'r') | ||
| 139 | + o |= 1; | ||
| 140 | + if (*z == 'w') | ||
| 141 | + o |= 2; | ||
| 142 | + } | ||
| 143 | + if (o == 1) | ||
| 144 | + *f = baz (x, 0); | ||
| 145 | + if (o == 2) | ||
| 146 | + *f = baz (x, 1); | ||
| 147 | + if (o == 3) | ||
| 148 | + *f = baz (x, 2); | ||
| 149 | + | ||
| 150 | + if (o && *f > 0) | ||
| 151 | + r = bar (f, "w", t); | ||
| 152 | + return r; | ||
| 153 | +} | ||
| 154 | + | ||
| 155 | +void * | ||
| 156 | +foo (const char *x, const char *y) | ||
| 157 | +{ | ||
| 158 | + return inl (x, y); | ||
| 159 | +} | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh251682.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh251682.patch deleted file mode 100644 index e96ae6f13..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh251682.patch +++ /dev/null | |||
| @@ -1,89 +0,0 @@ | |||
| 1 | 2008-04-01 Jakub Jelinek <jakub@redhat.com> | ||
| 2 | |||
| 3 | PR pch/13675 | ||
| 4 | * files.c (struct _cpp_file): Remove pch field. | ||
| 5 | (pch_open_file): Don't set file->pch, just file->pchname. | ||
| 6 | (should_stack_file): After pfile->cb.read_pch call | ||
| 7 | free pchname and clear pchname, don't close file->fd. | ||
| 8 | Test file->pchname instead of file->pch. Don't close fd after cb. | ||
| 9 | (_cpp_stack_include): Test file->pchname instead of file->pch. | ||
| 10 | |||
| 11 | * c-pch.c (c_common_read_pch): On error close (fd) resp. fclose (f). | ||
| 12 | |||
| 13 | --- libcpp/files.c.jj 2008-02-18 23:50:17.000000000 +0100 | ||
| 14 | +++ libcpp/files.c 2008-03-31 15:59:01.000000000 +0200 | ||
| 15 | @@ -106,9 +106,6 @@ struct _cpp_file | ||
| 16 | |||
| 17 | /* If BUFFER above contains the true contents of the file. */ | ||
| 18 | bool buffer_valid; | ||
| 19 | - | ||
| 20 | - /* File is a PCH (on return from find_include_file). */ | ||
| 21 | - bool pch; | ||
| 22 | }; | ||
| 23 | |||
| 24 | /* A singly-linked list for all searches for a given file name, with | ||
| 25 | @@ -322,9 +319,7 @@ pch_open_file (cpp_reader *pfile, _cpp_f | ||
| 26 | } | ||
| 27 | closedir (pchdir); | ||
| 28 | } | ||
| 29 | - if (valid) | ||
| 30 | - file->pch = true; | ||
| 31 | - else | ||
| 32 | + if (!valid) | ||
| 33 | *invalid_pch = true; | ||
| 34 | } | ||
| 35 | |||
| 36 | @@ -703,11 +698,12 @@ should_stack_file (cpp_reader *pfile, _c | ||
| 37 | return false; | ||
| 38 | |||
| 39 | /* Handle PCH files immediately; don't stack them. */ | ||
| 40 | - if (file->pch) | ||
| 41 | + if (file->pchname) | ||
| 42 | { | ||
| 43 | pfile->cb.read_pch (pfile, file->pchname, file->fd, file->path); | ||
| 44 | - close (file->fd); | ||
| 45 | file->fd = -1; | ||
| 46 | + free ((void *) file->pchname); | ||
| 47 | + file->pchname = NULL; | ||
| 48 | return false; | ||
| 49 | } | ||
| 50 | |||
| 51 | @@ -916,7 +912,7 @@ _cpp_stack_include (cpp_reader *pfile, c | ||
| 52 | complicates LAST_SOURCE_LINE_LOCATION. This does not apply if we | ||
| 53 | found a PCH file (in which case linemap_add is not called) or we | ||
| 54 | were included from the command-line. */ | ||
| 55 | - if (! file->pch && file->err_no == 0 && type != IT_CMDLINE) | ||
| 56 | + if (file->pchname == NULL && file->err_no == 0 && type != IT_CMDLINE) | ||
| 57 | pfile->line_table->highest_location--; | ||
| 58 | |||
| 59 | return _cpp_stack_file (pfile, file, type == IT_IMPORT); | ||
| 60 | --- gcc/c-pch.c.jj 2008-02-18 23:46:08.000000000 +0100 | ||
| 61 | +++ gcc/c-pch.c 2008-03-31 15:56:00.000000000 +0200 | ||
| 62 | @@ -372,6 +372,7 @@ c_common_read_pch (cpp_reader *pfile, co | ||
| 63 | if (f == NULL) | ||
| 64 | { | ||
| 65 | cpp_errno (pfile, CPP_DL_ERROR, "calling fdopen"); | ||
| 66 | + close (fd); | ||
| 67 | return; | ||
| 68 | } | ||
| 69 | |||
| 70 | @@ -380,6 +381,7 @@ c_common_read_pch (cpp_reader *pfile, co | ||
| 71 | if (fread (&h, sizeof (h), 1, f) != 1) | ||
| 72 | { | ||
| 73 | cpp_errno (pfile, CPP_DL_ERROR, "reading"); | ||
| 74 | + fclose (f); | ||
| 75 | return; | ||
| 76 | } | ||
| 77 | |||
| 78 | @@ -425,7 +427,10 @@ c_common_read_pch (cpp_reader *pfile, co | ||
| 79 | gt_pch_restore (f); | ||
| 80 | |||
| 81 | if (cpp_read_state (pfile, name, f, smd) != 0) | ||
| 82 | - return; | ||
| 83 | + { | ||
| 84 | + fclose (f); | ||
| 85 | + return; | ||
| 86 | + } | ||
| 87 | |||
| 88 | fclose (f); | ||
| 89 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh330771.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh330771.patch deleted file mode 100644 index 4888ac47d..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh330771.patch +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | 2007-10-16 Jakub Jelinek <jakub@redhat.com> | ||
| 2 | |||
| 3 | * Makefile.am (libgcj_tools_la_LIBADD): Add. | ||
| 4 | * Makefile.in: Regenerated. | ||
| 5 | |||
| 6 | Index: libjava/Makefile.am | ||
| 7 | =================================================================== | ||
| 8 | --- libjava/Makefile.am.orig 2010-03-21 12:41:37.000000000 -0700 | ||
| 9 | +++ libjava/Makefile.am 2010-06-25 10:22:11.394130458 -0700 | ||
| 10 | @@ -507,6 +507,8 @@ | ||
| 11 | libgcj_tools_la_GCJFLAGS = $(AM_GCJFLAGS) -findirect-dispatch \ | ||
| 12 | -fno-bootstrap-classes -fno-indirect-classes \ | ||
| 13 | -fsource-filename=$(here)/classpath/tools/all-classes.lst | ||
| 14 | +## See jv_convert_LDADD. | ||
| 15 | +libgcj_tools_la_LIBADD = -L$(here)/.libs libgcj.la | ||
| 16 | libgcj_tools_la_LDFLAGS = -rpath $(toolexeclibdir) \ | ||
| 17 | -version-info `grep -v '^\#' $(srcdir)/libtool-version` \ | ||
| 18 | $(LIBGCJ_LD_SYMBOLIC_FUNCTIONS) $(LIBJAVA_LDFLAGS_NOUNDEF) | ||
| 19 | Index: libjava/Makefile.in | ||
| 20 | =================================================================== | ||
| 21 | --- libjava/Makefile.in.orig 2010-04-02 11:18:06.000000000 -0700 | ||
| 22 | +++ libjava/Makefile.in 2010-06-25 10:27:41.841708512 -0700 | ||
| 23 | @@ -1190,7 +1190,7 @@ | ||
| 24 | -version-info `grep -v '^\#' $(srcdir)/libtool-version` \ | ||
| 25 | $(LIBGCJ_LD_SYMBOLIC_FUNCTIONS) $(LIBJAVA_LDFLAGS_NOUNDEF) | ||
| 26 | |||
| 27 | -libgcj_tools_la_LIBADD = libgcj.la -lm | ||
| 28 | +libgcj_tools_la_LIBADD = -L$(here)/.libs libgcj.la -lm | ||
| 29 | libgcj_tools_la_DEPENDENCIES = libgcj.la libgcj.spec $(am__append_22) | ||
| 30 | libgcj_tools_la_LINK = $(LIBLINK) $(libgcj_tools_la_LDFLAGS) | ||
| 31 | libjvm_la_SOURCES = jni-libjvm.cc | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh341221.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh341221.patch deleted file mode 100644 index 7e2801b99..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh341221.patch +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | 2007-10-21 Jakub Jelinek <jakub@redhat.com> | ||
| 2 | |||
| 3 | * doc/Makefile.am (POD2MAN): Set date from cp-tools.texinfo | ||
| 4 | timestamp rather than from current date. | ||
| 5 | * doc/Makefile.in: Regenerated. | ||
| 6 | |||
| 7 | Index: libjava/classpath/doc/Makefile.am | ||
| 8 | =================================================================== | ||
| 9 | --- libjava/classpath/doc/Makefile.am.orig 2008-10-21 10:55:01.000000000 -0700 | ||
| 10 | +++ libjava/classpath/doc/Makefile.am 2010-06-25 10:28:30.237631599 -0700 | ||
| 11 | @@ -31,7 +31,7 @@ | ||
| 12 | gtnameserv.1 \ | ||
| 13 | gjdoc.1 | ||
| 14 | |||
| 15 | -POD2MAN = pod2man --center="GNU" --release="$(VERSION)" | ||
| 16 | +POD2MAN = pod2man --center="GNU" --release="$(VERSION)" --date="$(shell ls --time-style=+%F -l $(srcdir)/cp-tools.texinfo | awk '{print $$6}')" | ||
| 17 | TEXI2POD = perl $(srcdir)/texi2pod.pl | ||
| 18 | STAMP = echo timestamp > | ||
| 19 | |||
| 20 | Index: libjava/classpath/doc/Makefile.in | ||
| 21 | =================================================================== | ||
| 22 | --- libjava/classpath/doc/Makefile.in.orig 2010-04-02 11:18:06.000000000 -0700 | ||
| 23 | +++ libjava/classpath/doc/Makefile.in 2010-06-25 10:28:30.245635728 -0700 | ||
| 24 | @@ -376,7 +376,7 @@ | ||
| 25 | gtnameserv.1 \ | ||
| 26 | gjdoc.1 | ||
| 27 | |||
| 28 | -POD2MAN = pod2man --center="GNU" --release="$(VERSION)" | ||
| 29 | +POD2MAN = pod2man --center="GNU" --release="$(VERSION)" --date="$(shell ls --time-style=+%F -l $(srcdir)/cp-tools.texinfo | awk '{print $$6}')" | ||
| 30 | TEXI2POD = perl $(srcdir)/texi2pod.pl | ||
| 31 | STAMP = echo timestamp > | ||
| 32 | @GENINSRC_FALSE@STAMP_GENINSRC = | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc45-no-add-needed.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc45-no-add-needed.patch deleted file mode 100644 index bf03c2785..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc45-no-add-needed.patch +++ /dev/null | |||
| @@ -1,60 +0,0 @@ | |||
| 1 | 2010-02-08 Roland McGrath <roland@redhat.com> | ||
| 2 | |||
| 3 | * config/rs6000/sysv4.h (LINK_EH_SPEC): Pass --no-add-needed to the | ||
| 4 | linker. | ||
| 5 | * config/linux.h (LINK_EH_SPEC): Likewise. | ||
| 6 | * config/alpha/elf.h (LINK_EH_SPEC): Likewise. | ||
| 7 | * config/ia64/linux.h (LINK_EH_SPEC): Likewise. | ||
| 8 | |||
| 9 | Index: gcc/config/alpha/elf.h | ||
| 10 | =================================================================== | ||
| 11 | --- gcc/config/alpha/elf.h.orig 2011-06-16 17:58:47.000000000 -0700 | ||
| 12 | +++ gcc/config/alpha/elf.h 2011-09-17 11:04:57.033298875 -0700 | ||
| 13 | @@ -441,7 +441,7 @@ extern int alpha_this_gpdisp_sequence_nu | ||
| 14 | I imagine that other systems will catch up. In the meantime, it | ||
| 15 | doesn't harm to make sure that the data exists to be used later. */ | ||
| 16 | #if defined(HAVE_LD_EH_FRAME_HDR) | ||
| 17 | -#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} " | ||
| 18 | +#define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} " | ||
| 19 | #endif | ||
| 20 | |||
| 21 | /* A C statement (sans semicolon) to output to the stdio stream STREAM | ||
| 22 | Index: gcc/config/ia64/linux.h | ||
| 23 | =================================================================== | ||
| 24 | --- gcc/config/ia64/linux.h.orig 2011-09-17 11:03:19.000000000 -0700 | ||
| 25 | +++ gcc/config/ia64/linux.h 2011-09-17 11:04:57.033298875 -0700 | ||
| 26 | @@ -80,7 +80,7 @@ do { \ | ||
| 27 | Signalize that because we have fde-glibc, we don't need all C shared libs | ||
| 28 | linked against -lgcc_s. */ | ||
| 29 | #undef LINK_EH_SPEC | ||
| 30 | -#define LINK_EH_SPEC "" | ||
| 31 | +#define LINK_EH_SPEC "--no-add-needed " | ||
| 32 | |||
| 33 | #define MD_UNWIND_SUPPORT "config/ia64/linux-unwind.h" | ||
| 34 | |||
| 35 | Index: gcc/config/linux.h | ||
| 36 | =================================================================== | ||
| 37 | --- gcc/config/linux.h.orig 2011-09-17 11:03:38.000000000 -0700 | ||
| 38 | +++ gcc/config/linux.h 2011-09-17 11:04:57.033298875 -0700 | ||
| 39 | @@ -101,7 +101,7 @@ see the files COPYING3 and COPYING.RUNTI | ||
| 40 | } while (0) | ||
| 41 | |||
| 42 | #if defined(HAVE_LD_EH_FRAME_HDR) | ||
| 43 | -#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} " | ||
| 44 | +#define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} " | ||
| 45 | #endif | ||
| 46 | |||
| 47 | /* Define this so we can compile MS code for use with WINE. */ | ||
| 48 | Index: gcc/config/rs6000/sysv4.h | ||
| 49 | =================================================================== | ||
| 50 | --- gcc/config/rs6000/sysv4.h.orig 2011-09-17 11:03:41.000000000 -0700 | ||
| 51 | +++ gcc/config/rs6000/sysv4.h 2011-09-17 11:05:58.653298861 -0700 | ||
| 52 | @@ -908,7 +908,7 @@ SVR4_ASM_SPEC \ | ||
| 53 | |||
| 54 | #if defined(HAVE_LD_EH_FRAME_HDR) | ||
| 55 | # undef LINK_EH_SPEC | ||
| 56 | -# define LINK_EH_SPEC "%{!static:--eh-frame-hdr} " | ||
| 57 | +# define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} " | ||
| 58 | #endif | ||
| 59 | |||
| 60 | #define CPP_OS_LINUX_SPEC "-D__unix__ -D__gnu_linux__ -D__linux__ \ | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fortran-cross-compile-hack.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fortran-cross-compile-hack.patch deleted file mode 100644 index 348c77006..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/fortran-cross-compile-hack.patch +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | * Fortran would have searched for arm-angstrom-gnueabi-gfortran but would have used | ||
| 2 | used gfortan. For gcc_4.2.2.bb we want to use the gfortran compiler from our cross | ||
| 3 | directory. | ||
| 4 | |||
| 5 | Index: gcc-4.5+svnr155514/libgfortran/configure | ||
| 6 | =================================================================== | ||
| 7 | --- gcc-4.5+svnr155514.orig/libgfortran/configure 2009-12-29 22:02:01.000000000 -0800 | ||
| 8 | +++ gcc-4.5+svnr155514/libgfortran/configure 2009-12-30 08:12:40.889091657 -0800 | ||
| 9 | @@ -11655,7 +11655,7 @@ CC="$lt_save_CC" | ||
| 10 | |||
| 11 | # We need gfortran to compile parts of the library | ||
| 12 | #AC_PROG_FC(gfortran) | ||
| 13 | -FC="$GFORTRAN" | ||
| 14 | +#FC="$GFORTRAN" | ||
| 15 | ac_ext=${ac_fc_srcext-f} | ||
| 16 | ac_compile='$FC -c $FCFLAGS $ac_fcflags_srcext conftest.$ac_ext >&5' | ||
| 17 | ac_link='$FC -o conftest$ac_exeext $FCFLAGS $LDFLAGS $ac_fcflags_srcext conftest.$ac_ext $LIBS >&5' | ||
| 18 | Index: gcc-4.5+svnr155514/libgfortran/configure.ac | ||
| 19 | =================================================================== | ||
| 20 | --- gcc-4.5+svnr155514.orig/libgfortran/configure.ac 2009-12-29 22:02:01.000000000 -0800 | ||
| 21 | +++ gcc-4.5+svnr155514/libgfortran/configure.ac 2009-12-30 08:12:13.453094218 -0800 | ||
| 22 | @@ -187,7 +187,7 @@ AC_SUBST(enable_static) | ||
| 23 | |||
| 24 | # We need gfortran to compile parts of the library | ||
| 25 | #AC_PROG_FC(gfortran) | ||
| 26 | -FC="$GFORTRAN" | ||
| 27 | +#FC="$GFORTRAN" | ||
| 28 | AC_PROG_FC(gfortran) | ||
| 29 | |||
| 30 | # extra LD Flags which are required for targets | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.0.2-e300c2c3.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.0.2-e300c2c3.patch deleted file mode 100644 index d1df8b271..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.0.2-e300c2c3.patch +++ /dev/null | |||
| @@ -1,319 +0,0 @@ | |||
| 1 | Adds support for Freescale Power architecture e300c2 and e300c3 cores. | ||
| 2 | http://www.bitshrine.org/gpp/tc-fsl-x86lnx-e300c3-nptl-4.0.2-2.src.rpm | ||
| 3 | |||
| 4 | Leon Woestenberg <leonw@mailcan.com> | ||
| 5 | |||
| 6 | --- | ||
| 7 | gcc/config.gcc | 2 | ||
| 8 | gcc/config/rs6000/e300c2c3.md | 189 ++++++++++++++++++++++++++++++++++++++++++ | ||
| 9 | gcc/config/rs6000/rs6000.c | 24 +++++ | ||
| 10 | gcc/config/rs6000/rs6000.h | 4 | ||
| 11 | gcc/config/rs6000/rs6000.md | 3 | ||
| 12 | 5 files changed, 220 insertions(+), 2 deletions(-) | ||
| 13 | |||
| 14 | Index: gcc-4.3.1/gcc/config/rs6000/e300c2c3.md | ||
| 15 | =================================================================== | ||
| 16 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 17 | +++ gcc-4.3.1/gcc/config/rs6000/e300c2c3.md 2008-08-23 16:51:33.000000000 -0700 | ||
| 18 | @@ -0,0 +1,189 @@ | ||
| 19 | +;; Pipeline description for Motorola PowerPC e300c3 core. | ||
| 20 | +;; Copyright (C) 2003 Free Software Foundation, Inc. | ||
| 21 | +;; | ||
| 22 | +;; This file is part of GCC. | ||
| 23 | + | ||
| 24 | +;; GCC is free software; you can redistribute it and/or modify it | ||
| 25 | +;; under the terms of the GNU General Public License as published | ||
| 26 | +;; by the Free Software Foundation; either version 2, or (at your | ||
| 27 | +;; option) any later version. | ||
| 28 | + | ||
| 29 | +;; GCC is distributed in the hope that it will be useful, but WITHOUT | ||
| 30 | +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
| 31 | +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | ||
| 32 | +;; License for more details. | ||
| 33 | + | ||
| 34 | +;; You should have received a copy of the GNU General Public License | ||
| 35 | +;; along with GCC; see the file COPYING. If not, write to the | ||
| 36 | +;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, | ||
| 37 | +;; MA 02111-1307, USA. | ||
| 38 | + | ||
| 39 | +(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire") | ||
| 40 | +(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most") | ||
| 41 | + | ||
| 42 | +;; We don't simulate general issue queue (GIC). If we have SU insn | ||
| 43 | +;; and then SU1 insn, they can not be issued on the same cycle | ||
| 44 | +;; (although SU1 insn and then SU insn can be issued) because the SU | ||
| 45 | +;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle | ||
| 46 | +;; multipass insn scheduling will find the situation and issue the SU1 | ||
| 47 | +;; insn and then the SU insn. | ||
| 48 | +(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most") | ||
| 49 | + | ||
| 50 | +;; We could describe completion buffers slots in combination with the | ||
| 51 | +;; retirement units and the order of completion but the result | ||
| 52 | +;; automaton would behave in the same way because we can not describe | ||
| 53 | +;; real latency time with taking in order completion into account. | ||
| 54 | +;; Actually we could define the real latency time by querying reserved | ||
| 55 | +;; automaton units but the current scheduler uses latency time before | ||
| 56 | +;; issuing insns and making any reservations. | ||
| 57 | +;; | ||
| 58 | +;; So our description is aimed to achieve a insn schedule in which the | ||
| 59 | +;; insns would not wait in the completion buffer. | ||
| 60 | +(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire") | ||
| 61 | + | ||
| 62 | +;; Branch unit: | ||
| 63 | +(define_cpu_unit "ppce300c3_bu" "ppce300c3_most") | ||
| 64 | + | ||
| 65 | +;; IU: | ||
| 66 | +(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most") | ||
| 67 | + | ||
| 68 | +;; IU: This used to describe non-pipelined division. | ||
| 69 | +(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long") | ||
| 70 | + | ||
| 71 | +;; SRU: | ||
| 72 | +(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most") | ||
| 73 | + | ||
| 74 | +;; Here we simplified LSU unit description not describing the stages. | ||
| 75 | +(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most") | ||
| 76 | + | ||
| 77 | +;; FPU: | ||
| 78 | +(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most") | ||
| 79 | + | ||
| 80 | +;; The following units are used to make automata deterministic | ||
| 81 | +(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most") | ||
| 82 | +(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most") | ||
| 83 | +(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire") | ||
| 84 | +(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most") | ||
| 85 | + | ||
| 86 | +;; The following sets to make automata deterministic when option ndfa is used. | ||
| 87 | +(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0") | ||
| 88 | +(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0") | ||
| 89 | +(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0") | ||
| 90 | +(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0") | ||
| 91 | + | ||
| 92 | +;; Some useful abbreviations. | ||
| 93 | +(define_reservation "ppce300c3_decode" | ||
| 94 | + "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0") | ||
| 95 | +(define_reservation "ppce300c3_issue" | ||
| 96 | + "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0") | ||
| 97 | +(define_reservation "ppce300c3_retire" | ||
| 98 | + "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0") | ||
| 99 | +(define_reservation "ppce300c3_iu_stage0" | ||
| 100 | + "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0") | ||
| 101 | + | ||
| 102 | +;; Compares can be executed either one of the IU or SRU | ||
| 103 | +(define_insn_reservation "ppce300c3_cmp" 1 | ||
| 104 | + (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare") | ||
| 105 | + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | ||
| 106 | + "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \ | ||
| 107 | + +ppce300c3_retire") | ||
| 108 | + | ||
| 109 | +;; Other one cycle IU insns | ||
| 110 | +(define_insn_reservation "ppce300c3_iu" 1 | ||
| 111 | + (and (eq_attr "type" "integer,insert_word") | ||
| 112 | + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | ||
| 113 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire") | ||
| 114 | + | ||
| 115 | +;; Branch. Actually this latency time is not used by the scheduler. | ||
| 116 | +(define_insn_reservation "ppce300c3_branch" 1 | ||
| 117 | + (and (eq_attr "type" "jmpreg,branch") | ||
| 118 | + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | ||
| 119 | + "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire") | ||
| 120 | + | ||
| 121 | +;; Multiply is non-pipelined but can be executed in any IU | ||
| 122 | +(define_insn_reservation "ppce300c3_multiply" 2 | ||
| 123 | + (and (eq_attr "type" "imul,imul2,imul3,imul_compare") | ||
| 124 | + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | ||
| 125 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \ | ||
| 126 | + ppce300c3_iu_stage0+ppce300c3_retire") | ||
| 127 | + | ||
| 128 | +;; Divide. We use the average latency time here. We omit reserving a | ||
| 129 | +;; retire unit because of the result automata will be huge. | ||
| 130 | +(define_insn_reservation "ppce300c3_divide" 20 | ||
| 131 | + (and (eq_attr "type" "idiv") | ||
| 132 | + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | ||
| 133 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\ | ||
| 134 | + ppce300c3_mu_div*19") | ||
| 135 | + | ||
| 136 | +;; CR logical | ||
| 137 | +(define_insn_reservation "ppce300c3_cr_logical" 1 | ||
| 138 | + (and (eq_attr "type" "cr_logical,delayed_cr") | ||
| 139 | + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | ||
| 140 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") | ||
| 141 | + | ||
| 142 | +;; Mfcr | ||
| 143 | +(define_insn_reservation "ppce300c3_mfcr" 1 | ||
| 144 | + (and (eq_attr "type" "mfcr") | ||
| 145 | + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | ||
| 146 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") | ||
| 147 | + | ||
| 148 | +;; Mtcrf | ||
| 149 | +(define_insn_reservation "ppce300c3_mtcrf" 1 | ||
| 150 | + (and (eq_attr "type" "mtcr") | ||
| 151 | + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | ||
| 152 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") | ||
| 153 | + | ||
| 154 | +;; Mtjmpr | ||
| 155 | +(define_insn_reservation "ppce300c3_mtjmpr" 1 | ||
| 156 | + (and (eq_attr "type" "mtjmpr,mfjmpr") | ||
| 157 | + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | ||
| 158 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") | ||
| 159 | + | ||
| 160 | +;; Float point instructions | ||
| 161 | +(define_insn_reservation "ppce300c3_fpcompare" 3 | ||
| 162 | + (and (eq_attr "type" "fpcompare") | ||
| 163 | + (eq_attr "cpu" "ppce300c3")) | ||
| 164 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") | ||
| 165 | + | ||
| 166 | +(define_insn_reservation "ppce300c3_fp" 3 | ||
| 167 | + (and (eq_attr "type" "fp") | ||
| 168 | + (eq_attr "cpu" "ppce300c3")) | ||
| 169 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") | ||
| 170 | + | ||
| 171 | +(define_insn_reservation "ppce300c3_dmul" 4 | ||
| 172 | + (and (eq_attr "type" "dmul") | ||
| 173 | + (eq_attr "cpu" "ppce300c3")) | ||
| 174 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire") | ||
| 175 | + | ||
| 176 | +; Divides are not pipelined | ||
| 177 | +(define_insn_reservation "ppce300c3_sdiv" 18 | ||
| 178 | + (and (eq_attr "type" "sdiv") | ||
| 179 | + (eq_attr "cpu" "ppce300c3")) | ||
| 180 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17") | ||
| 181 | + | ||
| 182 | +(define_insn_reservation "ppce300c3_ddiv" 33 | ||
| 183 | + (and (eq_attr "type" "ddiv") | ||
| 184 | + (eq_attr "cpu" "ppce300c3")) | ||
| 185 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32") | ||
| 186 | + | ||
| 187 | +;; Loads | ||
| 188 | +(define_insn_reservation "ppce300c3_load" 2 | ||
| 189 | + (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") | ||
| 190 | + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | ||
| 191 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") | ||
| 192 | + | ||
| 193 | +(define_insn_reservation "ppce300c3_fpload" 2 | ||
| 194 | + (and (eq_attr "type" "fpload,fpload_ux,fpload_u") | ||
| 195 | + (eq_attr "cpu" "ppce300c3")) | ||
| 196 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") | ||
| 197 | + | ||
| 198 | +;; Stores. | ||
| 199 | +(define_insn_reservation "ppce300c3_store" 2 | ||
| 200 | + (and (eq_attr "type" "store,store_ux,store_u") | ||
| 201 | + (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) | ||
| 202 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") | ||
| 203 | + | ||
| 204 | +(define_insn_reservation "ppce300c3_fpstore" 2 | ||
| 205 | + (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") | ||
| 206 | + (eq_attr "cpu" "ppce300c3")) | ||
| 207 | + "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") | ||
| 208 | Index: gcc-4.3.1/gcc/config/rs6000/rs6000.c | ||
| 209 | =================================================================== | ||
| 210 | --- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.c 2008-08-23 16:49:39.000000000 -0700 | ||
| 211 | +++ gcc-4.3.1/gcc/config/rs6000/rs6000.c 2008-08-23 16:54:25.000000000 -0700 | ||
| 212 | @@ -669,6 +669,21 @@ struct processor_costs ppc8540_cost = { | ||
| 213 | 1, /* prefetch streams /*/ | ||
| 214 | }; | ||
| 215 | |||
| 216 | +/* Instruction costs on E300C2 and E300C3 cores. */ | ||
| 217 | +static const | ||
| 218 | +struct processor_costs ppce300c2c3_cost = { | ||
| 219 | + COSTS_N_INSNS (4), /* mulsi */ | ||
| 220 | + COSTS_N_INSNS (4), /* mulsi_const */ | ||
| 221 | + COSTS_N_INSNS (4), /* mulsi_const9 */ | ||
| 222 | + COSTS_N_INSNS (4), /* muldi */ | ||
| 223 | + COSTS_N_INSNS (19), /* divsi */ | ||
| 224 | + COSTS_N_INSNS (19), /* divdi */ | ||
| 225 | + COSTS_N_INSNS (3), /* fp */ | ||
| 226 | + COSTS_N_INSNS (4), /* dmul */ | ||
| 227 | + COSTS_N_INSNS (18), /* sdiv */ | ||
| 228 | + COSTS_N_INSNS (33), /* ddiv */ | ||
| 229 | +}; | ||
| 230 | + | ||
| 231 | /* Instruction costs on POWER4 and POWER5 processors. */ | ||
| 232 | static const | ||
| 233 | struct processor_costs power4_cost = { | ||
| 234 | @@ -1420,6 +1435,8 @@ rs6000_override_options (const char *def | ||
| 235 | {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN}, | ||
| 236 | /* 8548 has a dummy entry for now. */ | ||
| 237 | {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN}, | ||
| 238 | + {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | ||
| 239 | + {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK}, | ||
| 240 | {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, | ||
| 241 | {"970", PROCESSOR_POWER4, | ||
| 242 | POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, | ||
| 243 | @@ -1845,6 +1862,11 @@ rs6000_override_options (const char *def | ||
| 244 | rs6000_cost = &ppc8540_cost; | ||
| 245 | break; | ||
| 246 | |||
| 247 | + case PROCESSOR_PPCE300C2: | ||
| 248 | + case PROCESSOR_PPCE300C3: | ||
| 249 | + rs6000_cost = &ppce300c2c3_cost; | ||
| 250 | + break; | ||
| 251 | + | ||
| 252 | case PROCESSOR_POWER4: | ||
| 253 | case PROCESSOR_POWER5: | ||
| 254 | rs6000_cost = &power4_cost; | ||
| 255 | @@ -18606,6 +18628,8 @@ rs6000_issue_rate (void) | ||
| 256 | case CPU_PPC7400: | ||
| 257 | case CPU_PPC8540: | ||
| 258 | case CPU_CELL: | ||
| 259 | + case CPU_PPCE300C2: | ||
| 260 | + case CPU_PPCE300C3: | ||
| 261 | return 2; | ||
| 262 | case CPU_RIOS2: | ||
| 263 | case CPU_PPC604: | ||
| 264 | Index: gcc-4.3.1/gcc/config/rs6000/rs6000.h | ||
| 265 | =================================================================== | ||
| 266 | --- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.h 2008-01-26 09:18:35.000000000 -0800 | ||
| 267 | +++ gcc-4.3.1/gcc/config/rs6000/rs6000.h 2008-08-23 16:55:30.000000000 -0700 | ||
| 268 | @@ -117,6 +117,8 @@ | ||
| 269 | %{mcpu=G5: -mpower4 -maltivec} \ | ||
| 270 | %{mcpu=8540: -me500} \ | ||
| 271 | %{mcpu=8548: -me500} \ | ||
| 272 | +%{mcpu=e300c2: -mppc} \ | ||
| 273 | +%{mcpu=e300c3: -mppc -mpmr} \ | ||
| 274 | %{maltivec: -maltivec} \ | ||
| 275 | -many" | ||
| 276 | |||
| 277 | @@ -262,6 +264,8 @@ enum processor_type | ||
| 278 | PROCESSOR_PPC7400, | ||
| 279 | PROCESSOR_PPC7450, | ||
| 280 | PROCESSOR_PPC8540, | ||
| 281 | + PROCESSOR_PPCE300C2, | ||
| 282 | + PROCESSOR_PPCE300C3, | ||
| 283 | PROCESSOR_POWER4, | ||
| 284 | PROCESSOR_POWER5, | ||
| 285 | PROCESSOR_POWER6, | ||
| 286 | Index: gcc-4.3.1/gcc/config/rs6000/rs6000.md | ||
| 287 | =================================================================== | ||
| 288 | --- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.md 2008-02-13 16:14:45.000000000 -0800 | ||
| 289 | +++ gcc-4.3.1/gcc/config/rs6000/rs6000.md 2008-08-23 16:57:29.000000000 -0700 | ||
| 290 | @@ -133,7 +133,7 @@ | ||
| 291 | ;; Processor type -- this attribute must exactly match the processor_type | ||
| 292 | ;; enumeration in rs6000.h. | ||
| 293 | |||
| 294 | -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell" | ||
| 295 | +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell,ppce300c2,ppce300c3" | ||
| 296 | (const (symbol_ref "rs6000_cpu_attr"))) | ||
| 297 | |||
| 298 | |||
| 299 | @@ -166,6 +166,7 @@ | ||
| 300 | (include "7xx.md") | ||
| 301 | (include "7450.md") | ||
| 302 | (include "8540.md") | ||
| 303 | +(include "e300c2c3.md") | ||
| 304 | (include "power4.md") | ||
| 305 | (include "power5.md") | ||
| 306 | (include "power6.md") | ||
| 307 | Index: gcc-4.3.1/gcc/config.gcc | ||
| 308 | =================================================================== | ||
| 309 | --- gcc-4.3.1.orig/gcc/config.gcc 2008-08-23 16:49:43.000000000 -0700 | ||
| 310 | +++ gcc-4.3.1/gcc/config.gcc 2008-08-23 17:03:55.000000000 -0700 | ||
| 311 | @@ -3144,7 +3144,7 @@ case "${target}" in | ||
| 312 | | rios | rios1 | rios2 | rsc | rsc1 | rs64a \ | ||
| 313 | | 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \ | ||
| 314 | | 601 | 602 | 603 | 603e | ec603e | 604 \ | ||
| 315 | - | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \ | ||
| 316 | + | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \ | ||
| 317 | | 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell) | ||
| 318 | # OK | ||
| 319 | ;; | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch deleted file mode 100644 index f33e6c1ea..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | --- | ||
| 2 | configure | 2 +- | ||
| 3 | configure.ac | 2 +- | ||
| 4 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
| 5 | |||
| 6 | Index: gcc-4.3.1/configure.ac | ||
| 7 | =================================================================== | ||
| 8 | --- gcc-4.3.1.orig/configure.ac 2008-07-21 12:29:18.000000000 -0700 | ||
| 9 | +++ gcc-4.3.1/configure.ac 2008-07-21 12:29:35.000000000 -0700 | ||
| 10 | @@ -2352,7 +2352,7 @@ fi | ||
| 11 | # for target_alias and gcc doesn't manage it consistently. | ||
| 12 | target_configargs="--cache-file=./config.cache ${target_configargs}" | ||
| 13 | |||
| 14 | -FLAGS_FOR_TARGET= | ||
| 15 | +FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET" | ||
| 16 | case " $target_configdirs " in | ||
| 17 | *" newlib "*) | ||
| 18 | case " $target_configargs " in | ||
| 19 | Index: gcc-4.3.1/configure | ||
| 20 | =================================================================== | ||
| 21 | --- gcc-4.3.1.orig/configure 2008-07-21 12:29:48.000000000 -0700 | ||
| 22 | +++ gcc-4.3.1/configure 2008-07-21 12:29:59.000000000 -0700 | ||
| 23 | @@ -5841,7 +5841,7 @@ fi | ||
| 24 | # for target_alias and gcc doesn't manage it consistently. | ||
| 25 | target_configargs="--cache-file=./config.cache ${target_configargs}" | ||
| 26 | |||
| 27 | -FLAGS_FOR_TARGET= | ||
| 28 | +FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET" | ||
| 29 | case " $target_configdirs " in | ||
| 30 | *" newlib "*) | ||
| 31 | case " $target_configargs " in | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.5.0_to_svn_162697.patch.bz2 b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.5.0_to_svn_162697.patch.bz2 deleted file mode 100644 index d37a2c032..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.5.0_to_svn_162697.patch.bz2 +++ /dev/null | |||
| Binary files differ | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-arm-volatile-bitfield-fix.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-arm-volatile-bitfield-fix.patch deleted file mode 100644 index d5a31d19d..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-arm-volatile-bitfield-fix.patch +++ /dev/null | |||
| @@ -1,103 +0,0 @@ | |||
| 1 | Date: Mon, 22 Nov 2010 13:28:54 +0000 | ||
| 2 | From: Julian Brown <julian at codesourcery dot com> | ||
| 3 | To: gcc-patches at gcc dot gnu dot org | ||
| 4 | Cc: DJ Delorie <dj at redhat dot com> | ||
| 5 | Subject: [PATCH] Volatile bitfields vs. inline asm memory constraints | ||
| 6 | Message-ID: <20101122132854.0aca431a@rex.config> | ||
| 7 | Mime-Version: 1.0 | ||
| 8 | Content-Type: multipart/mixed; boundary="MP_/ONpW806RnQ1ziaYj7_Y5E27" | ||
| 9 | X-IsSubscribed: yes | ||
| 10 | Mailing-List: contact gcc-patches-help at gcc dot gnu dot org; run by ezmlm | ||
| 11 | Precedence: bulk | ||
| 12 | List-Id: <gcc-patches.gcc.gnu.org> | ||
| 13 | List-Archive: <http://gcc.gnu.org/ml/gcc-patches/> | ||
| 14 | List-Post: <mailto:gcc-patches at gcc dot gnu dot org> | ||
| 15 | List-Help: <mailto:gcc-patches-help at gcc dot gnu dot org> | ||
| 16 | Sender: gcc-patches-owner at gcc dot gnu dot org | ||
| 17 | Delivered-To: mailing list gcc-patches at gcc dot gnu dot org | ||
| 18 | |||
| 19 | |||
| 20 | |||
| 21 | Hi, | ||
| 22 | |||
| 23 | This patch fixes the issue in the (Launchpad, not GCC) bug tracker: | ||
| 24 | |||
| 25 | https://bugs.launchpad.net/gcc-linaro/+bug/675347 | ||
| 26 | |||
| 27 | The problem was introduced by the patch from DJ to honour volatile | ||
| 28 | bitfield types: | ||
| 29 | |||
| 30 | http://gcc.gnu.org/ml/gcc-patches/2010-06/msg01167.html | ||
| 31 | |||
| 32 | but not exposed (on ARM) until the option was made the default (on the | ||
| 33 | Linaro branch) -- it's not yet the default on mainline. | ||
| 34 | |||
| 35 | The issue is as follows: after DJ's patch and with | ||
| 36 | -fstrict-volatile-bitfields, in expr.c:expand_expr_real_1, the if | ||
| 37 | condition with the comment "In cases where an aligned union has an | ||
| 38 | unaligned object as a field, we might be extracting a BLKmode value | ||
| 39 | from an integer-mode (e.g., SImode) object [...]" triggers for a normal | ||
| 40 | (non-bitfield) volatile field of a struct/class. | ||
| 41 | |||
| 42 | But, this appears to be over-eager: in the particular case mentioned | ||
| 43 | above, when expanding a "volatile int" struct field used as a memory | ||
| 44 | constraint for an inline asm, we end up with something which is no | ||
| 45 | longer addressable (I think because of the actions of | ||
| 46 | extract_bit_field). So, compilation aborts. | ||
| 47 | |||
| 48 | My proposed fix is to restrict the conditional by only making it execute | ||
| 49 | for -fstrict-volatile-bitfields only for non-naturally-aligned accesses: | ||
| 50 | this appears to work (fixes test in question, and no regressions for | ||
| 51 | cross to ARM Linux, gcc/g++/libstdc++, with -fstrict-volatile-bitfields | ||
| 52 | turned on), but I don't know if there will be unintended consequences. | ||
| 53 | DJ, does it look sane to you? | ||
| 54 | |||
| 55 | Incidentally the constraints in the inline asm in the Launchpad | ||
| 56 | testcase might be slightly dubious (attempting to force (mem (reg)) by | ||
| 57 | using both "+m" (var) and "r" (&var) constraints), but replacing | ||
| 58 | them with e.g.: | ||
| 59 | |||
| 60 | asm volatile("0:\n" | ||
| 61 | "ldrex %[newValue], %[_q_value]\n" | ||
| 62 | "sub %[newValue], %[newValue], #1\n" | ||
| 63 | "strex %[result], %[newValue], %[_q_value]\n" | ||
| 64 | "teq %[result], #0\n" | ||
| 65 | "bne 0b\n" | ||
| 66 | : [newValue] "=&r" (newValue), | ||
| 67 | [result] "=&r" (result) | ||
| 68 | : [_q_value] "Q" (_q_value) | ||
| 69 | : "cc", "memory"); | ||
| 70 | |||
| 71 | still leads to a warning (not an error) with trunk and | ||
| 72 | -fstrict-volatile-bitfields: | ||
| 73 | |||
| 74 | atomic-changed.cc:24:35: warning: use of memory input without lvalue in | ||
| 75 | asm operand 2 is deprecated [enabled by default] | ||
| 76 | |||
| 77 | The warning goes away with the attached patch. So, I don't think the | ||
| 78 | problem is purely that the original inline asm is invalid. | ||
| 79 | |||
| 80 | OK to apply, or any comments? | ||
| 81 | |||
| 82 | Julian | ||
| 83 | |||
| 84 | ChangeLog | ||
| 85 | |||
| 86 | gcc/ | ||
| 87 | * expr.c (expand_expr_real_1): Only use BLKmode for volatile | ||
| 88 | accesses which are not naturally aligned. | ||
| 89 | |||
| 90 | Index: gcc-4_5-branch/gcc/expr.c | ||
| 91 | =================================================================== | ||
| 92 | --- gcc-4_5-branch.orig/gcc/expr.c 2010-12-23 00:42:11.690101002 -0800 | ||
| 93 | +++ gcc-4_5-branch/gcc/expr.c 2010-12-24 15:07:39.400101000 -0800 | ||
| 94 | @@ -9029,7 +9029,8 @@ | ||
| 95 | && modifier != EXPAND_INITIALIZER) | ||
| 96 | /* If the field is volatile, we always want an aligned | ||
| 97 | access. */ | ||
| 98 | - || (volatilep && flag_strict_volatile_bitfields > 0) | ||
| 99 | + || (volatilep && flag_strict_volatile_bitfields > 0 | ||
| 100 | + && (bitpos % GET_MODE_ALIGNMENT (mode) != 0)) | ||
| 101 | /* If the field isn't aligned enough to fetch as a memref, | ||
| 102 | fetch it as a bit field. */ | ||
| 103 | || (mode1 != BLKmode | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-armv4-pass-fix-v4bx-to-ld.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-armv4-pass-fix-v4bx-to-ld.patch deleted file mode 100644 index 5d1a033a9..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-armv4-pass-fix-v4bx-to-ld.patch +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | The LINK_SPEC for linux gets overwritten by linux-eabi.h which | ||
| 2 | means the value of TARGET_FIX_V4BX_SPEC gets lost and as a result | ||
| 3 | the option is not passed to linker when chosing march=armv4 | ||
| 4 | This patch redefines this in linux-eabi.h and reinserts it | ||
| 5 | for eabi defaulting toolchains. | ||
| 6 | |||
| 7 | We might want to send it upstream | ||
| 8 | |||
| 9 | -Khem | ||
| 10 | Index: gcc-4.5/gcc/config/arm/linux-eabi.h | ||
| 11 | =================================================================== | ||
| 12 | --- gcc-4.5.orig/gcc/config/arm/linux-eabi.h | ||
| 13 | +++ gcc-4.5/gcc/config/arm/linux-eabi.h | ||
| 14 | @@ -63,10 +63,14 @@ | ||
| 15 | #undef GLIBC_DYNAMIC_LINKER | ||
| 16 | #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.3" | ||
| 17 | |||
| 18 | +/* For armv4 we pass --fix-v4bx to linker to support EABI */ | ||
| 19 | +#undef TARGET_FIX_V4BX_SPEC | ||
| 20 | +#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4:--fix-v4bx}" | ||
| 21 | + | ||
| 22 | /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to | ||
| 23 | use the GNU/Linux version, not the generic BPABI version. */ | ||
| 24 | #undef LINK_SPEC | ||
| 25 | -#define LINK_SPEC LINUX_TARGET_LINK_SPEC BE8_LINK_SPEC | ||
| 26 | +#define LINK_SPEC LINUX_TARGET_LINK_SPEC BE8_LINK_SPEC TARGET_FIX_V4BX_SPEC | ||
| 27 | |||
| 28 | /* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we | ||
| 29 | do not use -lfloat. */ | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-flags-for-build.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-flags-for-build.patch deleted file mode 100644 index 51892855a..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-flags-for-build.patch +++ /dev/null | |||
| @@ -1,178 +0,0 @@ | |||
| 1 | Index: gcc-4.5/Makefile.def | ||
| 2 | =================================================================== | ||
| 3 | --- gcc-4.5.orig/Makefile.def | ||
| 4 | +++ gcc-4.5/Makefile.def | ||
| 5 | @@ -240,6 +240,7 @@ flags_to_pass = { flag= AWK ; }; | ||
| 6 | flags_to_pass = { flag= BISON ; }; | ||
| 7 | flags_to_pass = { flag= CC_FOR_BUILD ; }; | ||
| 8 | flags_to_pass = { flag= CFLAGS_FOR_BUILD ; }; | ||
| 9 | +flags_to_pass = { flag= CPPFLAGS_FOR_BUILD ; }; | ||
| 10 | flags_to_pass = { flag= CXX_FOR_BUILD ; }; | ||
| 11 | flags_to_pass = { flag= EXPECT ; }; | ||
| 12 | flags_to_pass = { flag= FLEX ; }; | ||
| 13 | Index: gcc-4.5/gcc/Makefile.in | ||
| 14 | =================================================================== | ||
| 15 | --- gcc-4.5.orig/gcc/Makefile.in | ||
| 16 | +++ gcc-4.5/gcc/Makefile.in | ||
| 17 | @@ -766,7 +766,7 @@ BUILD_LINKERFLAGS = $(BUILD_CFLAGS) | ||
| 18 | |||
| 19 | # Native linker and preprocessor flags. For x-fragment overrides. | ||
| 20 | BUILD_LDFLAGS=@BUILD_LDFLAGS@ | ||
| 21 | -BUILD_CPPFLAGS=$(ALL_CPPFLAGS) | ||
| 22 | +BUILD_CPPFLAGS=$(INCLUDES) @BUILD_CPPFLAGS@ $(X_CPPFLAGS) | ||
| 23 | |||
| 24 | # Actual name to use when installing a native compiler. | ||
| 25 | GCC_INSTALL_NAME := $(shell echo gcc|sed '$(program_transform_name)') | ||
| 26 | Index: gcc-4.5/gcc/configure.ac | ||
| 27 | =================================================================== | ||
| 28 | --- gcc-4.5.orig/gcc/configure.ac | ||
| 29 | +++ gcc-4.5/gcc/configure.ac | ||
| 30 | @@ -1798,16 +1798,18 @@ AC_SUBST(inhibit_libc) | ||
| 31 | # Also, we cannot run fixincludes. | ||
| 32 | |||
| 33 | # These are the normal (build=host) settings: | ||
| 34 | -CC_FOR_BUILD='$(CC)' AC_SUBST(CC_FOR_BUILD) | ||
| 35 | -BUILD_CFLAGS='$(ALL_CFLAGS)' AC_SUBST(BUILD_CFLAGS) | ||
| 36 | -BUILD_LDFLAGS='$(LDFLAGS)' AC_SUBST(BUILD_LDFLAGS) | ||
| 37 | -STMP_FIXINC=stmp-fixinc AC_SUBST(STMP_FIXINC) | ||
| 38 | +CC_FOR_BUILD='$(CC)' AC_SUBST(CC_FOR_BUILD) | ||
| 39 | +BUILD_CFLAGS='$(ALL_CFLAGS)' AC_SUBST(BUILD_CFLAGS) | ||
| 40 | +BUILD_LDFLAGS='$(LDFLAGS)' AC_SUBST(BUILD_LDFLAGS) | ||
| 41 | +BUILD_CPPFLAGS='$(ALL_CPPFLAGS)' AC_SUBST(BUILD_CPPFLAGS) | ||
| 42 | +STMP_FIXINC=stmp-fixinc AC_SUBST(STMP_FIXINC) | ||
| 43 | |||
| 44 | # And these apply if build != host, or we are generating coverage data | ||
| 45 | if test x$build != x$host || test "x$coverage_flags" != x | ||
| 46 | then | ||
| 47 | BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)' | ||
| 48 | BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)' | ||
| 49 | + BUILD_CPPFLAGS='$(CPPFLAGS_FOR_BUILD)' | ||
| 50 | fi | ||
| 51 | |||
| 52 | # Expand extra_headers to include complete path. | ||
| 53 | Index: gcc-4.5/Makefile.in | ||
| 54 | =================================================================== | ||
| 55 | --- gcc-4.5.orig/Makefile.in | ||
| 56 | +++ gcc-4.5/Makefile.in | ||
| 57 | @@ -333,6 +333,7 @@ AR_FOR_BUILD = @AR_FOR_BUILD@ | ||
| 58 | AS_FOR_BUILD = @AS_FOR_BUILD@ | ||
| 59 | CC_FOR_BUILD = @CC_FOR_BUILD@ | ||
| 60 | CFLAGS_FOR_BUILD = @CFLAGS_FOR_BUILD@ | ||
| 61 | +CPPFLAGS_FOR_BUILD = @CPPFLAGS_FOR_BUILD@ | ||
| 62 | CXXFLAGS_FOR_BUILD = @CXXFLAGS_FOR_BUILD@ | ||
| 63 | CXX_FOR_BUILD = @CXX_FOR_BUILD@ | ||
| 64 | DLLTOOL_FOR_BUILD = @DLLTOOL_FOR_BUILD@ | ||
| 65 | @@ -662,6 +663,7 @@ BASE_FLAGS_TO_PASS = \ | ||
| 66 | "BISON=$(BISON)" \ | ||
| 67 | "CC_FOR_BUILD=$(CC_FOR_BUILD)" \ | ||
| 68 | "CFLAGS_FOR_BUILD=$(CFLAGS_FOR_BUILD)" \ | ||
| 69 | + "CPPFLAGS_FOR_BUILD=$(CPPFLAGS_FOR_BUILD)" \ | ||
| 70 | "CXX_FOR_BUILD=$(CXX_FOR_BUILD)" \ | ||
| 71 | "EXPECT=$(EXPECT)" \ | ||
| 72 | "FLEX=$(FLEX)" \ | ||
| 73 | Index: gcc-4.5/gcc/configure | ||
| 74 | =================================================================== | ||
| 75 | --- gcc-4.5.orig/gcc/configure | ||
| 76 | +++ gcc-4.5/gcc/configure | ||
| 77 | @@ -707,6 +707,7 @@ SED | ||
| 78 | LIBTOOL | ||
| 79 | collect2 | ||
| 80 | STMP_FIXINC | ||
| 81 | +BUILD_CPPFLAGS | ||
| 82 | BUILD_LDFLAGS | ||
| 83 | BUILD_CFLAGS | ||
| 84 | CC_FOR_BUILD | ||
| 85 | @@ -10982,6 +10983,7 @@ fi | ||
| 86 | CC_FOR_BUILD='$(CC)' | ||
| 87 | BUILD_CFLAGS='$(ALL_CFLAGS)' | ||
| 88 | BUILD_LDFLAGS='$(LDFLAGS)' | ||
| 89 | +BUILD_CPPFLAGS='$(ALL_CPPFLAGS)' | ||
| 90 | STMP_FIXINC=stmp-fixinc | ||
| 91 | |||
| 92 | # And these apply if build != host, or we are generating coverage data | ||
| 93 | @@ -10989,6 +10991,7 @@ if test x$build != x$host || test "x$cov | ||
| 94 | then | ||
| 95 | BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)' | ||
| 96 | BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)' | ||
| 97 | + BUILD_CPPFLAGS='$(CPPFLAGS_FOR_BUILD)' | ||
| 98 | fi | ||
| 99 | |||
| 100 | # Expand extra_headers to include complete path. | ||
| 101 | @@ -17108,7 +17111,7 @@ else | ||
| 102 | lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 | ||
| 103 | lt_status=$lt_dlunknown | ||
| 104 | cat > conftest.$ac_ext <<_LT_EOF | ||
| 105 | -#line 17111 "configure" | ||
| 106 | +#line 17114 "configure" | ||
| 107 | #include "confdefs.h" | ||
| 108 | |||
| 109 | #if HAVE_DLFCN_H | ||
| 110 | @@ -17214,7 +17217,7 @@ else | ||
| 111 | lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 | ||
| 112 | lt_status=$lt_dlunknown | ||
| 113 | cat > conftest.$ac_ext <<_LT_EOF | ||
| 114 | -#line 17217 "configure" | ||
| 115 | +#line 17220 "configure" | ||
| 116 | #include "confdefs.h" | ||
| 117 | |||
| 118 | #if HAVE_DLFCN_H | ||
| 119 | Index: gcc-4.5/Makefile.tpl | ||
| 120 | =================================================================== | ||
| 121 | --- gcc-4.5.orig/Makefile.tpl | ||
| 122 | +++ gcc-4.5/Makefile.tpl | ||
| 123 | @@ -336,6 +336,7 @@ AR_FOR_BUILD = @AR_FOR_BUILD@ | ||
| 124 | AS_FOR_BUILD = @AS_FOR_BUILD@ | ||
| 125 | CC_FOR_BUILD = @CC_FOR_BUILD@ | ||
| 126 | CFLAGS_FOR_BUILD = @CFLAGS_FOR_BUILD@ | ||
| 127 | +CPPFLAGS_FOR_BUILD = @CPPFLAGS_FOR_BUILD@ | ||
| 128 | CXXFLAGS_FOR_BUILD = @CXXFLAGS_FOR_BUILD@ | ||
| 129 | CXX_FOR_BUILD = @CXX_FOR_BUILD@ | ||
| 130 | DLLTOOL_FOR_BUILD = @DLLTOOL_FOR_BUILD@ | ||
| 131 | Index: gcc-4.5/configure | ||
| 132 | =================================================================== | ||
| 133 | --- gcc-4.5.orig/configure | ||
| 134 | +++ gcc-4.5/configure | ||
| 135 | @@ -651,6 +651,7 @@ GCJ_FOR_BUILD | ||
| 136 | DLLTOOL_FOR_BUILD | ||
| 137 | CXX_FOR_BUILD | ||
| 138 | CXXFLAGS_FOR_BUILD | ||
| 139 | +CPPFLAGS_FOR_BUILD | ||
| 140 | CFLAGS_FOR_BUILD | ||
| 141 | CC_FOR_BUILD | ||
| 142 | AS_FOR_BUILD | ||
| 143 | @@ -8036,6 +8037,7 @@ esac | ||
| 144 | # our build compiler if desired. | ||
| 145 | if test x"${build}" = x"${host}" ; then | ||
| 146 | CFLAGS_FOR_BUILD=${CFLAGS_FOR_BUILD-${CFLAGS}} | ||
| 147 | + CPPFLAGS_FOR_BUILD=${CPPFLAGS_FOR_BUILD-${CPPFLAGS}} | ||
| 148 | CXXFLAGS_FOR_BUILD=${CXXFLAGS_FOR_BUILD-${CXXFLAGS}} | ||
| 149 | LDFLAGS_FOR_BUILD=${LDFLAGS_FOR_BUILD-${LDFLAGS}} | ||
| 150 | fi | ||
| 151 | @@ -8101,6 +8103,7 @@ done | ||
| 152 | |||
| 153 | |||
| 154 | |||
| 155 | + | ||
| 156 | |||
| 157 | |||
| 158 | |||
| 159 | Index: gcc-4.5/configure.ac | ||
| 160 | =================================================================== | ||
| 161 | --- gcc-4.5.orig/configure.ac | ||
| 162 | +++ gcc-4.5/configure.ac | ||
| 163 | @@ -3089,6 +3089,7 @@ esac | ||
| 164 | # our build compiler if desired. | ||
| 165 | if test x"${build}" = x"${host}" ; then | ||
| 166 | CFLAGS_FOR_BUILD=${CFLAGS_FOR_BUILD-${CFLAGS}} | ||
| 167 | + CPPFLAGS_FOR_BUILD=${CPPFLAGS_FOR_BUILD-${CPPFLAGS}} | ||
| 168 | CXXFLAGS_FOR_BUILD=${CXXFLAGS_FOR_BUILD-${CXXFLAGS}} | ||
| 169 | LDFLAGS_FOR_BUILD=${LDFLAGS_FOR_BUILD-${LDFLAGS}} | ||
| 170 | fi | ||
| 171 | @@ -3155,6 +3156,7 @@ AC_SUBST(AR_FOR_BUILD) | ||
| 172 | AC_SUBST(AS_FOR_BUILD) | ||
| 173 | AC_SUBST(CC_FOR_BUILD) | ||
| 174 | AC_SUBST(CFLAGS_FOR_BUILD) | ||
| 175 | +AC_SUBST(CPPFLAGS_FOR_BUILD) | ||
| 176 | AC_SUBST(CXXFLAGS_FOR_BUILD) | ||
| 177 | AC_SUBST(CXX_FOR_BUILD) | ||
| 178 | AC_SUBST(DLLTOOL_FOR_BUILD) | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ice-hack.dpatch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ice-hack.dpatch deleted file mode 100644 index 84c5ef2eb..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ice-hack.dpatch +++ /dev/null | |||
| @@ -1,331 +0,0 @@ | |||
| 1 | #! /bin/sh -e | ||
| 2 | |||
| 3 | # DP: Retry the build on an ice, save the calling options and preprocessed | ||
| 4 | # DP: source when the ice is reproducible. | ||
| 5 | |||
| 6 | dir= | ||
| 7 | if [ $# -eq 3 -a "$2" = '-d' ]; then | ||
| 8 | pdir="-d $3" | ||
| 9 | dir="$3/" | ||
| 10 | elif [ $# -ne 1 ]; then | ||
| 11 | echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" | ||
| 12 | exit 1 | ||
| 13 | fi | ||
| 14 | case "$1" in | ||
| 15 | -patch) | ||
| 16 | patch $pdir -f --no-backup-if-mismatch -p0 < $0 | ||
| 17 | ;; | ||
| 18 | -unpatch) | ||
| 19 | patch $pdir -f --no-backup-if-mismatch -R -p0 < $0 | ||
| 20 | ;; | ||
| 21 | *) | ||
| 22 | echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" | ||
| 23 | exit 1 | ||
| 24 | esac | ||
| 25 | exit 0 | ||
| 26 | |||
| 27 | 2004-01-23 Jakub Jelinek <jakub@redhat.com> | ||
| 28 | |||
| 29 | * system.h (ICE_EXIT_CODE): Define. | ||
| 30 | * gcc.c (execute): Don't free first string early, but at the end | ||
| 31 | of the function. Call retry_ice if compiler exited with | ||
| 32 | ICE_EXIT_CODE. | ||
| 33 | (retry_ice): New function. | ||
| 34 | * diagnostic.c (diagnostic_count_diagnostic, | ||
| 35 | diagnostic_action_after_output, error_recursion): Exit with | ||
| 36 | ICE_EXIT_CODE instead of FATAL_EXIT_CODE. | ||
| 37 | |||
| 38 | --- gcc/diagnostic.c.orig 2007-09-30 10:48:13.000000000 +0000 | ||
| 39 | +++ gcc/diagnostic.c 2007-09-30 10:49:57.000000000 +0000 | ||
| 40 | @@ -244,7 +244,7 @@ | ||
| 41 | fnotice (stderr, "Please submit a full bug report,\n" | ||
| 42 | "with preprocessed source if appropriate.\n" | ||
| 43 | "See %s for instructions.\n", bug_report_url); | ||
| 44 | - exit (ICE_EXIT_CODE); | ||
| 45 | + exit (FATAL_EXIT_CODE); | ||
| 46 | |||
| 47 | case DK_FATAL: | ||
| 48 | if (context->abort_on_error) | ||
| 49 | --- gcc/gcc.c.orig 2007-09-30 10:48:13.000000000 +0000 | ||
| 50 | +++ gcc/gcc.c 2007-09-30 10:48:39.000000000 +0000 | ||
| 51 | @@ -357,6 +357,9 @@ | ||
| 52 | #if defined(HAVE_TARGET_OBJECT_SUFFIX) || defined(HAVE_TARGET_EXECUTABLE_SUFFIX) | ||
| 53 | static const char *convert_filename (const char *, int, int); | ||
| 54 | #endif | ||
| 55 | +#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS)) | ||
| 56 | +static void retry_ice (const char *prog, const char **argv); | ||
| 57 | +#endif | ||
| 58 | |||
| 59 | static const char *getenv_spec_function (int, const char **); | ||
| 60 | static const char *if_exists_spec_function (int, const char **); | ||
| 61 | @@ -2999,7 +3002,7 @@ | ||
| 62 | } | ||
| 63 | } | ||
| 64 | |||
| 65 | - if (string != commands[i].prog) | ||
| 66 | + if (i && string != commands[i].prog) | ||
| 67 | free (CONST_CAST (char *, string)); | ||
| 68 | } | ||
| 69 | |||
| 70 | @@ -3056,6 +3059,16 @@ | ||
| 71 | else if (WIFEXITED (status) | ||
| 72 | && WEXITSTATUS (status) >= MIN_FATAL_STATUS) | ||
| 73 | { | ||
| 74 | +#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS)) | ||
| 75 | + /* For ICEs in cc1, cc1obj, cc1plus see if it is | ||
| 76 | + reproducible or not. */ | ||
| 77 | + char *p; | ||
| 78 | + if (WEXITSTATUS (status) == ICE_EXIT_CODE | ||
| 79 | + && i == 0 | ||
| 80 | + && (p = strrchr (commands[0].argv[0], DIR_SEPARATOR)) | ||
| 81 | + && ! strncmp (p + 1, "cc1", 3)) | ||
| 82 | + retry_ice (commands[0].prog, commands[0].argv); | ||
| 83 | +#endif | ||
| 84 | if (WEXITSTATUS (status) > greatest_status) | ||
| 85 | greatest_status = WEXITSTATUS (status); | ||
| 86 | ret_code = -1; | ||
| 87 | @@ -3076,6 +3089,9 @@ | ||
| 88 | } | ||
| 89 | } | ||
| 90 | |||
| 91 | + if (commands[0].argv[0] != commands[0].prog) | ||
| 92 | + free ((PTR) commands[0].argv[0]); | ||
| 93 | + | ||
| 94 | return ret_code; | ||
| 95 | } | ||
| 96 | } | ||
| 97 | @@ -6016,6 +6032,224 @@ | ||
| 98 | switches[switchnum].validated = 1; | ||
| 99 | } | ||
| 100 | |||
| 101 | +#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS)) | ||
| 102 | +#define RETRY_ICE_ATTEMPTS 2 | ||
| 103 | + | ||
| 104 | +static void | ||
| 105 | +retry_ice (const char *prog, const char **argv) | ||
| 106 | +{ | ||
| 107 | + int nargs, out_arg = -1, quiet = 0, attempt; | ||
| 108 | + int pid, retries, sleep_interval; | ||
| 109 | + const char **new_argv; | ||
| 110 | + char *temp_filenames[RETRY_ICE_ATTEMPTS * 2 + 2]; | ||
| 111 | + | ||
| 112 | + if (input_filename == NULL || ! strcmp (input_filename, "-")) | ||
| 113 | + return; | ||
| 114 | + | ||
| 115 | + for (nargs = 0; argv[nargs] != NULL; ++nargs) | ||
| 116 | + /* Only retry compiler ICEs, not preprocessor ones. */ | ||
| 117 | + if (! strcmp (argv[nargs], "-E")) | ||
| 118 | + return; | ||
| 119 | + else if (argv[nargs][0] == '-' && argv[nargs][1] == 'o') | ||
| 120 | + { | ||
| 121 | + if (out_arg == -1) | ||
| 122 | + out_arg = nargs; | ||
| 123 | + else | ||
| 124 | + return; | ||
| 125 | + } | ||
| 126 | + /* If the compiler is going to output any time information, | ||
| 127 | + it might vary between invocations. */ | ||
| 128 | + else if (! strcmp (argv[nargs], "-quiet")) | ||
| 129 | + quiet = 1; | ||
| 130 | + else if (! strcmp (argv[nargs], "-ftime-report")) | ||
| 131 | + return; | ||
| 132 | + | ||
| 133 | + if (out_arg == -1 || !quiet) | ||
| 134 | + return; | ||
| 135 | + | ||
| 136 | + memset (temp_filenames, '\0', sizeof (temp_filenames)); | ||
| 137 | + new_argv = alloca ((nargs + 3) * sizeof (const char *)); | ||
| 138 | + memcpy (new_argv, argv, (nargs + 1) * sizeof (const char *)); | ||
| 139 | + new_argv[nargs++] = "-frandom-seed=0"; | ||
| 140 | + new_argv[nargs] = NULL; | ||
| 141 | + if (new_argv[out_arg][2] == '\0') | ||
| 142 | + new_argv[out_arg + 1] = "-"; | ||
| 143 | + else | ||
| 144 | + new_argv[out_arg] = "-o-"; | ||
| 145 | + | ||
| 146 | + for (attempt = 0; attempt < RETRY_ICE_ATTEMPTS + 1; ++attempt) | ||
| 147 | + { | ||
| 148 | + int fd = -1; | ||
| 149 | + int status; | ||
| 150 | + | ||
| 151 | + temp_filenames[attempt * 2] = make_temp_file (".out"); | ||
| 152 | + temp_filenames[attempt * 2 + 1] = make_temp_file (".err"); | ||
| 153 | + | ||
| 154 | + if (attempt == RETRY_ICE_ATTEMPTS) | ||
| 155 | + { | ||
| 156 | + int i; | ||
| 157 | + int fd1, fd2; | ||
| 158 | + struct stat st1, st2; | ||
| 159 | + size_t n, len; | ||
| 160 | + char *buf; | ||
| 161 | + | ||
| 162 | + buf = xmalloc (8192); | ||
| 163 | + | ||
| 164 | + for (i = 0; i < 2; ++i) | ||
| 165 | + { | ||
| 166 | + fd1 = open (temp_filenames[i], O_RDONLY); | ||
| 167 | + fd2 = open (temp_filenames[2 + i], O_RDONLY); | ||
| 168 | + | ||
| 169 | + if (fd1 < 0 || fd2 < 0) | ||
| 170 | + { | ||
| 171 | + i = -1; | ||
| 172 | + close (fd1); | ||
| 173 | + close (fd2); | ||
| 174 | + break; | ||
| 175 | + } | ||
| 176 | + | ||
| 177 | + if (fstat (fd1, &st1) < 0 || fstat (fd2, &st2) < 0) | ||
| 178 | + { | ||
| 179 | + i = -1; | ||
| 180 | + close (fd1); | ||
| 181 | + close (fd2); | ||
| 182 | + break; | ||
| 183 | + } | ||
| 184 | + | ||
| 185 | + if (st1.st_size != st2.st_size) | ||
| 186 | + { | ||
| 187 | + close (fd1); | ||
| 188 | + close (fd2); | ||
| 189 | + break; | ||
| 190 | + } | ||
| 191 | + | ||
| 192 | + len = 0; | ||
| 193 | + for (n = st1.st_size; n; n -= len) | ||
| 194 | + { | ||
| 195 | + len = n; | ||
| 196 | + if (len > 4096) | ||
| 197 | + len = 4096; | ||
| 198 | + | ||
| 199 | + if (read (fd1, buf, len) != (int) len | ||
| 200 | + || read (fd2, buf + 4096, len) != (int) len) | ||
| 201 | + { | ||
| 202 | + i = -1; | ||
| 203 | + break; | ||
| 204 | + } | ||
| 205 | + | ||
| 206 | + if (memcmp (buf, buf + 4096, len) != 0) | ||
| 207 | + break; | ||
| 208 | + } | ||
| 209 | + | ||
| 210 | + close (fd1); | ||
| 211 | + close (fd2); | ||
| 212 | + | ||
| 213 | + if (n) | ||
| 214 | + break; | ||
| 215 | + } | ||
| 216 | + | ||
| 217 | + free (buf); | ||
| 218 | + if (i == -1) | ||
| 219 | + break; | ||
| 220 | + | ||
| 221 | + if (i != 2) | ||
| 222 | + { | ||
| 223 | + notice ("The bug is not reproducible, so it is likely a hardware or OS problem.\n"); | ||
| 224 | + break; | ||
| 225 | + } | ||
| 226 | + | ||
| 227 | + fd = open (temp_filenames[attempt * 2], O_RDWR); | ||
| 228 | + if (fd < 0) | ||
| 229 | + break; | ||
| 230 | + write (fd, "//", 2); | ||
| 231 | + for (i = 0; i < nargs; i++) | ||
| 232 | + { | ||
| 233 | + write (fd, " ", 1); | ||
| 234 | + write (fd, new_argv[i], strlen (new_argv[i])); | ||
| 235 | + } | ||
| 236 | + write (fd, "\n", 1); | ||
| 237 | + new_argv[nargs] = "-E"; | ||
| 238 | + new_argv[nargs + 1] = NULL; | ||
| 239 | + } | ||
| 240 | + | ||
| 241 | + /* Fork a subprocess; wait and retry if it fails. */ | ||
| 242 | + sleep_interval = 1; | ||
| 243 | + pid = -1; | ||
| 244 | + for (retries = 0; retries < 4; retries++) | ||
| 245 | + { | ||
| 246 | + pid = fork (); | ||
| 247 | + if (pid >= 0) | ||
| 248 | + break; | ||
| 249 | + sleep (sleep_interval); | ||
| 250 | + sleep_interval *= 2; | ||
| 251 | + } | ||
| 252 | + | ||
| 253 | + if (pid < 0) | ||
| 254 | + break; | ||
| 255 | + else if (pid == 0) | ||
| 256 | + { | ||
| 257 | + if (attempt != RETRY_ICE_ATTEMPTS) | ||
| 258 | + fd = open (temp_filenames[attempt * 2], O_RDWR); | ||
| 259 | + if (fd < 0) | ||
| 260 | + exit (-1); | ||
| 261 | + if (fd != 1) | ||
| 262 | + { | ||
| 263 | + close (1); | ||
| 264 | + dup (fd); | ||
| 265 | + close (fd); | ||
| 266 | + } | ||
| 267 | + | ||
| 268 | + fd = open (temp_filenames[attempt * 2 + 1], O_RDWR); | ||
| 269 | + if (fd < 0) | ||
| 270 | + exit (-1); | ||
| 271 | + if (fd != 2) | ||
| 272 | + { | ||
| 273 | + close (2); | ||
| 274 | + dup (fd); | ||
| 275 | + close (fd); | ||
| 276 | + } | ||
| 277 | + | ||
| 278 | + if (prog == new_argv[0]) | ||
| 279 | + execvp (prog, (char *const *) new_argv); | ||
| 280 | + else | ||
| 281 | + execv (new_argv[0], (char *const *) new_argv); | ||
| 282 | + exit (-1); | ||
| 283 | + } | ||
| 284 | + | ||
| 285 | + if (waitpid (pid, &status, 0) < 0) | ||
| 286 | + break; | ||
| 287 | + | ||
| 288 | + if (attempt < RETRY_ICE_ATTEMPTS | ||
| 289 | + && (! WIFEXITED (status) || WEXITSTATUS (status) != ICE_EXIT_CODE)) | ||
| 290 | + { | ||
| 291 | + notice ("The bug is not reproducible, so it is likely a hardware or OS problem.\n"); | ||
| 292 | + break; | ||
| 293 | + } | ||
| 294 | + else if (attempt == RETRY_ICE_ATTEMPTS) | ||
| 295 | + { | ||
| 296 | + close (fd); | ||
| 297 | + if (WIFEXITED (status) | ||
| 298 | + && WEXITSTATUS (status) == SUCCESS_EXIT_CODE) | ||
| 299 | + { | ||
| 300 | + notice ("Preprocessed source stored into %s file, please attach this to your bugreport.\n", | ||
| 301 | + temp_filenames[attempt * 2]); | ||
| 302 | + /* Make sure it is not deleted. */ | ||
| 303 | + free (temp_filenames[attempt * 2]); | ||
| 304 | + temp_filenames[attempt * 2] = NULL; | ||
| 305 | + break; | ||
| 306 | + } | ||
| 307 | + } | ||
| 308 | + } | ||
| 309 | + | ||
| 310 | + for (attempt = 0; attempt < RETRY_ICE_ATTEMPTS * 2 + 2; attempt++) | ||
| 311 | + if (temp_filenames[attempt]) | ||
| 312 | + { | ||
| 313 | + unlink (temp_filenames[attempt]); | ||
| 314 | + free (temp_filenames[attempt]); | ||
| 315 | + } | ||
| 316 | +} | ||
| 317 | +#endif | ||
| 318 | + | ||
| 319 | /* Search for a file named NAME trying various prefixes including the | ||
| 320 | user's -B prefix and some standard ones. | ||
| 321 | Return the absolute file name found. If nothing is found, return NAME. */ | ||
| 322 | --- gcc/Makefile.in.orig 2007-09-30 10:48:13.000000000 +0000 | ||
| 323 | +++ gcc/Makefile.in 2007-09-30 10:48:39.000000000 +0000 | ||
| 324 | @@ -192,6 +192,7 @@ | ||
| 325 | build/gengtype-lex.o-warn = -Wno-error | ||
| 326 | # SYSCALLS.c misses prototypes | ||
| 327 | SYSCALLS.c.X-warn = -Wno-strict-prototypes -Wno-error | ||
| 328 | +build/gcc.o-warn = -Wno-error | ||
| 329 | |||
| 330 | # All warnings have to be shut off in stage1 if the compiler used then | ||
| 331 | # isn't gcc; configure determines that. WARN_CFLAGS will be either | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-dir-extend.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-dir-extend.patch deleted file mode 100644 index 862b10213..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-dir-extend.patch +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | Add /sw/include and /opt/include based on the original | ||
| 2 | zecke-no-host-includes.patch patch. The original patch checked for | ||
| 3 | /usr/include, /sw/include and /opt/include and then triggered a failure and | ||
| 4 | aborted. | ||
| 5 | |||
| 6 | Instead, we add the two missing items to the current scan. If the user | ||
| 7 | wants this to be a failure, they can add "-Werror=poison-system-directories". | ||
| 8 | |||
| 9 | Signed-off-by: Mark Hatle <mark.hatle@windriver.com> | ||
| 10 | |||
| 11 | Index: gcc-4_5-branch/gcc/incpath.c | ||
| 12 | =================================================================== | ||
| 13 | --- gcc-4_5-branch.orig/gcc/incpath.c | ||
| 14 | +++ gcc-4_5-branch/gcc/incpath.c | ||
| 15 | @@ -365,7 +365,9 @@ merge_include_chains (const char *sysroo | ||
| 16 | { | ||
| 17 | if ((!strncmp (p->name, "/usr/include", 12)) | ||
| 18 | || (!strncmp (p->name, "/usr/local/include", 18)) | ||
| 19 | - || (!strncmp (p->name, "/usr/X11R6/include", 18))) | ||
| 20 | + || (!strncmp (p->name, "/usr/X11R6/include", 18)) | ||
| 21 | + || (!strncmp (p->name, "/sw/include", 11)) | ||
| 22 | + || (!strncmp (p->name, "/opt/include", 12))) | ||
| 23 | warning (OPT_Wpoison_system_directories, | ||
| 24 | "include location \"%s\" is unsafe for " | ||
| 25 | "cross-compilation", | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-parameters.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-parameters.patch deleted file mode 100644 index ba20e8b15..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-parameters.patch +++ /dev/null | |||
| @@ -1,83 +0,0 @@ | |||
| 1 | gcc: add poison parameters detection | ||
| 2 | |||
| 3 | Add the logic that, if not configured with "--enable-target-optspace", | ||
| 4 | gcc will meet error when build target app with "-Os" option. | ||
| 5 | This could avoid potential binary crash. | ||
| 6 | |||
| 7 | Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com> | ||
| 8 | |||
| 9 | Index: gcc-4_5-branch/gcc/config.in | ||
| 10 | =================================================================== | ||
| 11 | --- gcc-4_5-branch.orig/gcc/config.in | ||
| 12 | +++ gcc-4_5-branch/gcc/config.in | ||
| 13 | @@ -138,6 +138,12 @@ | ||
| 14 | #endif | ||
| 15 | |||
| 16 | |||
| 17 | +/* Define to enable target optspace support. */ | ||
| 18 | +#ifndef USED_FOR_TARGET | ||
| 19 | +#undef ENABLE_TARGET_OPTSPACE | ||
| 20 | +#endif | ||
| 21 | + | ||
| 22 | + | ||
| 23 | /* Define if you want all operations on RTL (the basic data structure of the | ||
| 24 | optimizer and back end) to be checked for dynamic type safety at runtime. | ||
| 25 | This is quite expensive. */ | ||
| 26 | Index: gcc-4_5-branch/gcc/configure | ||
| 27 | =================================================================== | ||
| 28 | --- gcc-4_5-branch.orig/gcc/configure | ||
| 29 | +++ gcc-4_5-branch/gcc/configure | ||
| 30 | @@ -915,6 +915,7 @@ enable_version_specific_runtime_libs | ||
| 31 | with_slibdir | ||
| 32 | enable_poison_system_directories | ||
| 33 | enable_plugin | ||
| 34 | +enable_target_optspace | ||
| 35 | ' | ||
| 36 | ac_precious_vars='build_alias | ||
| 37 | host_alias | ||
| 38 | @@ -25658,6 +25659,13 @@ $as_echo "#define ENABLE_PLUGIN 1" >>con | ||
| 39 | |||
| 40 | fi | ||
| 41 | |||
| 42 | +if test x"$enable_target_optspace" != x; then : | ||
| 43 | + | ||
| 44 | +$as_echo "#define ENABLE_TARGET_OPTSPACE 1" >>confdefs.h | ||
| 45 | + | ||
| 46 | +fi | ||
| 47 | + | ||
| 48 | + | ||
| 49 | # Configure the subdirectories | ||
| 50 | # AC_CONFIG_SUBDIRS($subdirs) | ||
| 51 | |||
| 52 | Index: gcc-4_5-branch/gcc/configure.ac | ||
| 53 | =================================================================== | ||
| 54 | --- gcc-4_5-branch.orig/gcc/configure.ac | ||
| 55 | +++ gcc-4_5-branch/gcc/configure.ac | ||
| 56 | @@ -4659,6 +4659,11 @@ if test x"$enable_plugin" = x"yes"; then | ||
| 57 | AC_DEFINE(ENABLE_PLUGIN, 1, [Define to enable plugin support.]) | ||
| 58 | fi | ||
| 59 | |||
| 60 | +AC_SUBST(enable_target_optspace) | ||
| 61 | +if test x"$enable_target_optspace" != x; then | ||
| 62 | + AC_DEFINE(ENABLE_TARGET_OPTSPACE, 1, [Define to enable target optspace support.]) | ||
| 63 | +fi | ||
| 64 | + | ||
| 65 | # Configure the subdirectories | ||
| 66 | # AC_CONFIG_SUBDIRS($subdirs) | ||
| 67 | |||
| 68 | Index: gcc-4_5-branch/gcc/opts.c | ||
| 69 | =================================================================== | ||
| 70 | --- gcc-4_5-branch.orig/gcc/opts.c | ||
| 71 | +++ gcc-4_5-branch/gcc/opts.c | ||
| 72 | @@ -953,6 +953,11 @@ decode_options (unsigned int argc, const | ||
| 73 | else | ||
| 74 | set_param_value ("min-crossjump-insns", initial_min_crossjump_insns); | ||
| 75 | |||
| 76 | +#ifndef ENABLE_TARGET_OPTSPACE | ||
| 77 | + if (optimize_size == 1) | ||
| 78 | + error ("Do not use -Os option if --enable-target-optspace is not set."); | ||
| 79 | +#endif | ||
| 80 | + | ||
| 81 | if (first_time_p) | ||
| 82 | { | ||
| 83 | /* Initialize whether `char' is signed. */ | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-system-directories.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-system-directories.patch deleted file mode 100644 index 04043ff0b..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-system-directories.patch +++ /dev/null | |||
| @@ -1,201 +0,0 @@ | |||
| 1 | gcc/ | ||
| 2 | 2008-07-02 Joseph Myers <joseph@codesourcery.com> | ||
| 3 | * c-incpath.c: Include toplev.h. | ||
| 4 | (merge_include_chains): Use warning instead of cpp_error for | ||
| 5 | system directory poisoning diagnostic. | ||
| 6 | * Makefile.in (c-incpath.o): Depend on toplev.h. | ||
| 7 | * gcc.c (LINK_COMMAND_SPEC): Pass | ||
| 8 | --error-poison-system-directories if | ||
| 9 | -Werror=poison-system-directories. | ||
| 10 | |||
| 11 | 2007-06-13 Joseph Myers <joseph@codesourcery.com> | ||
| 12 | * common.opt (--Wno-poison-system-directories): New. | ||
| 13 | * doc/invoke.texi (-Wno-poison-system-directories): Document. | ||
| 14 | * c-incpath.c: Include flags.h. | ||
| 15 | (merge_include_chains): Check flag_poison_system_directories. | ||
| 16 | * gcc.c (LINK_COMMAND_SPEC): Pass --no-poison-system-directories | ||
| 17 | to linker if -Wno-poison-system-directories. | ||
| 18 | * Makefile.in (c-incpath.o): Depend on $(FLAGS_H). | ||
| 19 | |||
| 20 | 2007-03-20 Daniel Jacobowitz <dan@codesourcery.com> | ||
| 21 | Joseph Myers <joseph@codesourcery.com> | ||
| 22 | * configure.ac (--enable-poison-system-directories): New option. | ||
| 23 | * configure, config.in: Regenerate. | ||
| 24 | * c-incpath.c (merge_include_chains): If | ||
| 25 | ENABLE_POISON_SYSTEM_DIRECTORIES defined, warn for use of | ||
| 26 | /usr/include, /usr/local/include or /usr/X11R6/include. | ||
| 27 | |||
| 28 | Index: gcc-4.5.0/gcc/common.opt | ||
| 29 | =================================================================== | ||
| 30 | --- gcc-4.5.0.orig/gcc/common.opt 2010-03-17 20:01:09.000000000 -0700 | ||
| 31 | +++ gcc-4.5.0/gcc/common.opt 2010-06-25 11:35:39.965383734 -0700 | ||
| 32 | @@ -152,6 +152,10 @@ | ||
| 33 | Common Var(warn_padded) Warning | ||
| 34 | Warn when padding is required to align structure members | ||
| 35 | |||
| 36 | +Wpoison-system-directories | ||
| 37 | +Common Var(flag_poison_system_directories) Init(1) Warning | ||
| 38 | +Warn for -I and -L options using system directories if cross compiling | ||
| 39 | + | ||
| 40 | Wshadow | ||
| 41 | Common Var(warn_shadow) Warning | ||
| 42 | Warn when one local variable shadows another | ||
| 43 | Index: gcc-4.5.0/gcc/config.in | ||
| 44 | =================================================================== | ||
| 45 | --- gcc-4.5.0.orig/gcc/config.in 2010-04-14 02:30:07.000000000 -0700 | ||
| 46 | +++ gcc-4.5.0/gcc/config.in 2010-06-25 11:35:39.969383588 -0700 | ||
| 47 | @@ -132,6 +132,12 @@ | ||
| 48 | #endif | ||
| 49 | |||
| 50 | |||
| 51 | +/* Define to warn for use of native system header directories */ | ||
| 52 | +#ifndef USED_FOR_TARGET | ||
| 53 | +#undef ENABLE_POISON_SYSTEM_DIRECTORIES | ||
| 54 | +#endif | ||
| 55 | + | ||
| 56 | + | ||
| 57 | /* Define if you want all operations on RTL (the basic data structure of the | ||
| 58 | optimizer and back end) to be checked for dynamic type safety at runtime. | ||
| 59 | This is quite expensive. */ | ||
| 60 | Index: gcc-4.5.0/gcc/configure.ac | ||
| 61 | =================================================================== | ||
| 62 | --- gcc-4.5.0.orig/gcc/configure.ac 2010-06-25 11:34:01.433382161 -0700 | ||
| 63 | +++ gcc-4.5.0/gcc/configure.ac 2010-06-25 11:35:39.969383588 -0700 | ||
| 64 | @@ -4276,6 +4276,16 @@ | ||
| 65 | fi) | ||
| 66 | AC_SUBST(slibdir) | ||
| 67 | |||
| 68 | +AC_ARG_ENABLE([poison-system-directories], | ||
| 69 | + AS_HELP_STRING([--enable-poison-system-directories], | ||
| 70 | + [warn for use of native system header directories]),, | ||
| 71 | + [enable_poison_system_directories=no]) | ||
| 72 | +if test "x${enable_poison_system_directories}" = "xyes"; then | ||
| 73 | + AC_DEFINE([ENABLE_POISON_SYSTEM_DIRECTORIES], | ||
| 74 | + [1], | ||
| 75 | + [Define to warn for use of native system header directories]) | ||
| 76 | +fi | ||
| 77 | + | ||
| 78 | # Substitute configuration variables | ||
| 79 | AC_SUBST(subdirs) | ||
| 80 | AC_SUBST(srcdir) | ||
| 81 | Index: gcc-4.5.0/gcc/doc/invoke.texi | ||
| 82 | =================================================================== | ||
| 83 | --- gcc-4.5.0.orig/gcc/doc/invoke.texi 2010-04-06 07:02:22.000000000 -0700 | ||
| 84 | +++ gcc-4.5.0/gcc/doc/invoke.texi 2010-06-25 11:35:39.992666345 -0700 | ||
| 85 | @@ -252,6 +252,7 @@ | ||
| 86 | -Woverlength-strings -Wpacked -Wpacked-bitfield-compat -Wpadded @gol | ||
| 87 | -Wparentheses -Wpedantic-ms-format -Wno-pedantic-ms-format @gol | ||
| 88 | -Wpointer-arith -Wno-pointer-to-int-cast @gol | ||
| 89 | +-Wno-poison-system-directories @gol | ||
| 90 | -Wredundant-decls @gol | ||
| 91 | -Wreturn-type -Wsequence-point -Wshadow @gol | ||
| 92 | -Wsign-compare -Wsign-conversion -Wstack-protector @gol | ||
| 93 | @@ -3603,6 +3604,14 @@ | ||
| 94 | option will @emph{not} warn about unknown pragmas in system | ||
| 95 | headers---for that, @option{-Wunknown-pragmas} must also be used. | ||
| 96 | |||
| 97 | +@item -Wno-poison-system-directories | ||
| 98 | +@opindex Wno-poison-system-directories | ||
| 99 | +Do not warn for @option{-I} or @option{-L} options using system | ||
| 100 | +directories such as @file{/usr/include} when cross compiling. This | ||
| 101 | +option is intended for use in chroot environments when such | ||
| 102 | +directories contain the correct headers and libraries for the target | ||
| 103 | +system rather than the host. | ||
| 104 | + | ||
| 105 | @item -Wfloat-equal | ||
| 106 | @opindex Wfloat-equal | ||
| 107 | @opindex Wno-float-equal | ||
| 108 | Index: gcc-4.5.0/gcc/gcc.c | ||
| 109 | =================================================================== | ||
| 110 | --- gcc-4.5.0.orig/gcc/gcc.c 2010-02-11 04:23:08.000000000 -0800 | ||
| 111 | +++ gcc-4.5.0/gcc/gcc.c 2010-06-25 11:35:40.009381858 -0700 | ||
| 112 | @@ -792,6 +792,8 @@ | ||
| 113 | %{flto} %{fwhopr} %l " LINK_PIE_SPEC \ | ||
| 114 | "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\ | ||
| 115 | %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\ | ||
| 116 | + %{Wno-poison-system-directories:--no-poison-system-directories}\ | ||
| 117 | + %{Werror=poison-system-directories:--error-poison-system-directories}\ | ||
| 118 | %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\ | ||
| 119 | %{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)} %(mflib)\ | ||
| 120 | %{fprofile-arcs|fprofile-generate*|coverage:-lgcov}\ | ||
| 121 | Index: gcc-4.5.0/gcc/incpath.c | ||
| 122 | =================================================================== | ||
| 123 | --- gcc-4.5.0.orig/gcc/incpath.c 2009-11-25 02:55:54.000000000 -0800 | ||
| 124 | +++ gcc-4.5.0/gcc/incpath.c 2010-06-25 11:35:40.017209818 -0700 | ||
| 125 | @@ -353,6 +353,24 @@ | ||
| 126 | } | ||
| 127 | fprintf (stderr, _("End of search list.\n")); | ||
| 128 | } | ||
| 129 | + | ||
| 130 | +#ifdef ENABLE_POISON_SYSTEM_DIRECTORIES | ||
| 131 | + if (flag_poison_system_directories) | ||
| 132 | + { | ||
| 133 | + struct cpp_dir *p; | ||
| 134 | + | ||
| 135 | + for (p = heads[QUOTE]; p; p = p->next) | ||
| 136 | + { | ||
| 137 | + if ((!strncmp (p->name, "/usr/include", 12)) | ||
| 138 | + || (!strncmp (p->name, "/usr/local/include", 18)) | ||
| 139 | + || (!strncmp (p->name, "/usr/X11R6/include", 18))) | ||
| 140 | + warning (OPT_Wpoison_system_directories, | ||
| 141 | + "include location \"%s\" is unsafe for " | ||
| 142 | + "cross-compilation", | ||
| 143 | + p->name); | ||
| 144 | + } | ||
| 145 | + } | ||
| 146 | +#endif | ||
| 147 | } | ||
| 148 | |||
| 149 | /* Use given -I paths for #include "..." but not #include <...>, and | ||
| 150 | diff -ur gcc-4.5.0.orig/gcc/Makefile.in gcc-4.5.0/gcc/Makefile.in | ||
| 151 | --- gcc-4.5.0.orig/gcc/Makefile.in 2010-09-29 17:13:49.164088845 -0500 | ||
| 152 | +++ gcc-4.5.0/gcc/Makefile.in 2010-09-29 18:48:19.300178501 -0500 | ||
| 153 | @@ -1965,7 +1965,7 @@ | ||
| 154 | |||
| 155 | incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \ | ||
| 156 | intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \ | ||
| 157 | - $(MACHMODE_H) | ||
| 158 | + $(MACHMODE_H) $(FLAGS_H) toplev.h | ||
| 159 | |||
| 160 | c-decl.o : c-decl.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) \ | ||
| 161 | $(RTL_H) $(C_TREE_H) $(GGC_H) $(TARGET_H) $(FLAGS_H) $(FUNCTION_H) output.h \ | ||
| 162 | diff -ur gcc-4.5.0.orig/gcc/configure gcc-4.5.0/gcc/configure | ||
| 163 | --- gcc-4.5.0.orig/gcc/configure 2010-09-29 14:58:31.702054881 -0500 | ||
| 164 | +++ gcc-4.5.0/gcc/configure 2010-09-29 18:46:31.486068500 -0500 | ||
| 165 | @@ -913,6 +913,7 @@ | ||
| 166 | enable_maintainer_mode | ||
| 167 | enable_version_specific_runtime_libs | ||
| 168 | with_slibdir | ||
| 169 | +enable_poison_system_directories | ||
| 170 | enable_plugin | ||
| 171 | enable_target_optspace | ||
| 172 | ' | ||
| 173 | @@ -1621,6 +1622,8 @@ | ||
| 174 | --enable-version-specific-runtime-libs | ||
| 175 | specify that runtime libraries should be | ||
| 176 | installed in a compiler-specific directory | ||
| 177 | + --enable-poison-system-directories | ||
| 178 | + warn for use of native system header directories | ||
| 179 | --enable-plugin enable plugin support | ||
| 180 | |||
| 181 | Optional Packages: | ||
| 182 | @@ -25339,6 +25377,19 @@ | ||
| 183 | |||
| 184 | |||
| 185 | |||
| 186 | +# Check whether --enable-poison-system-directories was given. | ||
| 187 | +if test "${enable_poison_system_directories+set}" = set; then : | ||
| 188 | + enableval=$enable_poison_system_directories; | ||
| 189 | +else | ||
| 190 | + enable_poison_system_directories=no | ||
| 191 | +fi | ||
| 192 | + | ||
| 193 | +if test "x${enable_poison_system_directories}" = "xyes"; then | ||
| 194 | + | ||
| 195 | +$as_echo "#define ENABLE_POISON_SYSTEM_DIRECTORIES 1" >>confdefs.h | ||
| 196 | + | ||
| 197 | +fi | ||
| 198 | + | ||
| 199 | # Substitute configuration variables | ||
| 200 | |||
| 201 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ppc-config-fix.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ppc-config-fix.patch deleted file mode 100644 index 6ae75a012..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ppc-config-fix.patch +++ /dev/null | |||
| @@ -1,221 +0,0 @@ | |||
| 1 | commit de784bee66a1ec1d0dad00d9eedbe9b1667dd883 | ||
| 2 | Author: jsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4> | ||
| 3 | Date: Mon Dec 20 15:29:31 2010 +0000 | ||
| 4 | |||
| 5 | * config/rs6000/freebsd.h (SVR4_ASM_SPEC): Don't define. | ||
| 6 | (DBX_REGISTER_NUMBER): Define. | ||
| 7 | * config/rs6000/lynx.h (DBX_REGISTER_NUMBER): Define. | ||
| 8 | * config/rs6000/netbsd.h (DBX_REGISTER_NUMBER): Define. | ||
| 9 | * config/rs6000/sysv4.h (SIZE_TYPE): Define. | ||
| 10 | (ASM_SPEC): Define without using SVR4_ASM_SPEC. | ||
| 11 | (DBX_REGISTER_NUMBER): Undefine. | ||
| 12 | * config.gcc (powerpc-*-eabispe*, powerpc-*-eabisimaltivec*, | ||
| 13 | powerpc-*-eabisim*, powerpc-*-elf*, powerpc-*-eabialtivec*, | ||
| 14 | powerpc-xilinx-eabi*, powerpc-*-eabi*, powerpc-*-rtems*, | ||
| 15 | powerpc-*-linux* | powerpc64-*-linux*, powerpc64-*-gnu*, | ||
| 16 | powerpc-*-gnu-gnualtivec*, powerpc-*-gnu*, | ||
| 17 | powerpc-wrs-vxworks|powerpc-wrs-vxworksae, powerpcle-*-elf*, | ||
| 18 | powerpcle-*-eabisim*, powerpcle-*-eabi*): Don't use svr4.h. | ||
| 19 | |||
| 20 | |||
| 21 | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@168085 138bc75d-0d04-0410-961f-82ee72b054a4 | ||
| 22 | |||
| 23 | Index: gcc-4_5-branch/gcc/config.gcc | ||
| 24 | =================================================================== | ||
| 25 | --- gcc-4_5-branch.orig/gcc/config.gcc 2011-09-17 11:11:28.000000000 -0700 | ||
| 26 | +++ gcc-4_5-branch/gcc/config.gcc 2011-09-17 11:16:32.543298716 -0700 | ||
| 27 | @@ -1989,48 +1989,48 @@ powerpc-*-netbsd*) | ||
| 28 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 29 | ;; | ||
| 30 | powerpc-*-eabispe*) | ||
| 31 | - tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabispe.h" | ||
| 32 | + tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabispe.h" | ||
| 33 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 34 | tmake_file="rs6000/t-spe rs6000/t-ppccomm" | ||
| 35 | use_gcc_stdint=wrap | ||
| 36 | ;; | ||
| 37 | powerpc-*-eabisimaltivec*) | ||
| 38 | - tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h rs6000/eabialtivec.h" | ||
| 39 | + tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h rs6000/eabialtivec.h" | ||
| 40 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 41 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcendian rs6000/t-ppccomm" | ||
| 42 | use_gcc_stdint=wrap | ||
| 43 | ;; | ||
| 44 | powerpc-*-eabisim*) | ||
| 45 | - tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h" | ||
| 46 | + tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h" | ||
| 47 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 48 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm" | ||
| 49 | use_gcc_stdint=wrap | ||
| 50 | ;; | ||
| 51 | powerpc-*-elf*) | ||
| 52 | - tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h" | ||
| 53 | + tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h" | ||
| 54 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 55 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm" | ||
| 56 | ;; | ||
| 57 | powerpc-*-eabialtivec*) | ||
| 58 | - tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabialtivec.h" | ||
| 59 | + tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabialtivec.h" | ||
| 60 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 61 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcendian rs6000/t-ppccomm" | ||
| 62 | use_gcc_stdint=wrap | ||
| 63 | ;; | ||
| 64 | powerpc-xilinx-eabi*) | ||
| 65 | - tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/singlefp.h rs6000/xfpu.h rs6000/xilinx.h" | ||
| 66 | + tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/singlefp.h rs6000/xfpu.h rs6000/xilinx.h" | ||
| 67 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 68 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm rs6000/t-xilinx" | ||
| 69 | use_gcc_stdint=wrap | ||
| 70 | ;; | ||
| 71 | powerpc-*-eabi*) | ||
| 72 | - tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h" | ||
| 73 | + tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h" | ||
| 74 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 75 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm" | ||
| 76 | use_gcc_stdint=wrap | ||
| 77 | ;; | ||
| 78 | powerpc-*-rtems*) | ||
| 79 | - tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/rtems.h rtems.h" | ||
| 80 | + tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/rtems.h rtems.h" | ||
| 81 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 82 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-rtems t-rtems rs6000/t-ppccomm" | ||
| 83 | ;; | ||
| 84 | @@ -2079,12 +2079,12 @@ powerpc-*-linux* | powerpc64-*-linux*) | ||
| 85 | fi | ||
| 86 | ;; | ||
| 87 | powerpc64-*-gnu*) | ||
| 88 | - tm_file="${tm_file} elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/default64.h rs6000/linux64.h rs6000/gnu.h glibc-stdint.h" | ||
| 89 | + tm_file="${tm_file} elfos.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/default64.h rs6000/linux64.h rs6000/gnu.h glibc-stdint.h" | ||
| 90 | extra_options="${extra_options} rs6000/sysv4.opt rs6000/linux64.opt" | ||
| 91 | tmake_file="t-slibgcc-elf-ver t-slibgcc-libgcc t-gnu" | ||
| 92 | ;; | ||
| 93 | powerpc-*-gnu-gnualtivec*) | ||
| 94 | - tm_file="${cpu_type}/${cpu_type}.h elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/linuxaltivec.h rs6000/gnu.h glibc-stdint.h" | ||
| 95 | + tm_file="${cpu_type}/${cpu_type}.h elfos.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/linuxaltivec.h rs6000/gnu.h glibc-stdint.h" | ||
| 96 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 97 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcos t-slibgcc-elf-ver t-slibgcc-libgcc t-gnu rs6000/t-ppccomm" | ||
| 98 | if test x$enable_threads = xyes; then | ||
| 99 | @@ -2092,7 +2092,7 @@ powerpc-*-gnu-gnualtivec*) | ||
| 100 | fi | ||
| 101 | ;; | ||
| 102 | powerpc-*-gnu*) | ||
| 103 | - tm_file="${cpu_type}/${cpu_type}.h elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/gnu.h glibc-stdint.h" | ||
| 104 | + tm_file="${cpu_type}/${cpu_type}.h elfos.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/gnu.h glibc-stdint.h" | ||
| 105 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcos t-slibgcc-elf-ver t-slibgcc-libgcc t-gnu rs6000/t-ppccomm" | ||
| 106 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 107 | if test x$enable_threads = xyes; then | ||
| 108 | @@ -2100,7 +2100,7 @@ powerpc-*-gnu*) | ||
| 109 | fi | ||
| 110 | ;; | ||
| 111 | powerpc-wrs-vxworks|powerpc-wrs-vxworksae) | ||
| 112 | - tm_file="${tm_file} elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h" | ||
| 113 | + tm_file="${tm_file} elfos.h freebsd-spec.h rs6000/sysv4.h" | ||
| 114 | tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppccomm rs6000/t-vxworks" | ||
| 115 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 116 | extra_headers=ppc-asm.h | ||
| 117 | @@ -2126,18 +2126,18 @@ powerpc-*-lynxos*) | ||
| 118 | gas=yes | ||
| 119 | ;; | ||
| 120 | powerpcle-*-elf*) | ||
| 121 | - tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h" | ||
| 122 | + tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h" | ||
| 123 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm" | ||
| 124 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 125 | ;; | ||
| 126 | powerpcle-*-eabisim*) | ||
| 127 | - tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h" | ||
| 128 | + tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h" | ||
| 129 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm" | ||
| 130 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 131 | use_gcc_stdint=wrap | ||
| 132 | ;; | ||
| 133 | powerpcle-*-eabi*) | ||
| 134 | - tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h" | ||
| 135 | + tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h" | ||
| 136 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm" | ||
| 137 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 138 | use_gcc_stdint=wrap | ||
| 139 | Index: gcc-4_5-branch/gcc/config/rs6000/freebsd.h | ||
| 140 | =================================================================== | ||
| 141 | --- gcc-4_5-branch.orig/gcc/config/rs6000/freebsd.h 2011-06-16 17:58:58.000000000 -0700 | ||
| 142 | +++ gcc-4_5-branch/gcc/config/rs6000/freebsd.h 2011-09-17 11:13:13.623298761 -0700 | ||
| 143 | @@ -69,6 +69,4 @@ | ||
| 144 | /* Override rs6000.h definition. */ | ||
| 145 | #undef ASM_APP_OFF | ||
| 146 | #define ASM_APP_OFF "#NO_APP\n" | ||
| 147 | -/* Define SVR4_ASM_SPEC, we use GAS by default. See svr4.h for details. */ | ||
| 148 | -#define SVR4_ASM_SPEC \ | ||
| 149 | - "%{v:-V} %{Wa,*:%*}" | ||
| 150 | +#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) | ||
| 151 | Index: gcc-4_5-branch/gcc/config/rs6000/lynx.h | ||
| 152 | =================================================================== | ||
| 153 | --- gcc-4_5-branch.orig/gcc/config/rs6000/lynx.h 2011-06-16 17:58:58.000000000 -0700 | ||
| 154 | +++ gcc-4_5-branch/gcc/config/rs6000/lynx.h 2011-09-17 11:13:13.623298761 -0700 | ||
| 155 | @@ -1,5 +1,5 @@ | ||
| 156 | /* Definitions for Rs6000 running LynxOS. | ||
| 157 | - Copyright (C) 1995, 1996, 2000, 2002, 2003, 2004, 2005, 2007 | ||
| 158 | + Copyright (C) 1995, 1996, 2000, 2002, 2003, 2004, 2005, 2007, 2010 | ||
| 159 | Free Software Foundation, Inc. | ||
| 160 | Contributed by David Henkel-Wallace, Cygnus Support (gumby@cygnus.com) | ||
| 161 | Rewritten by Adam Nemet, LynuxWorks Inc. | ||
| 162 | @@ -105,6 +105,8 @@ | ||
| 163 | #undef HAVE_AS_TLS | ||
| 164 | #define HAVE_AS_TLS 0 | ||
| 165 | |||
| 166 | +#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) | ||
| 167 | + | ||
| 168 | #ifdef CRT_BEGIN | ||
| 169 | /* This function is part of crtbegin*.o which is at the beginning of | ||
| 170 | the link and is called from .fini which is usually toward the end | ||
| 171 | Index: gcc-4_5-branch/gcc/config/rs6000/netbsd.h | ||
| 172 | =================================================================== | ||
| 173 | --- gcc-4_5-branch.orig/gcc/config/rs6000/netbsd.h 2011-06-16 17:58:58.000000000 -0700 | ||
| 174 | +++ gcc-4_5-branch/gcc/config/rs6000/netbsd.h 2011-09-17 11:13:13.623298761 -0700 | ||
| 175 | @@ -1,6 +1,6 @@ | ||
| 176 | /* Definitions of target machine for GNU compiler, | ||
| 177 | for PowerPC NetBSD systems. | ||
| 178 | - Copyright 2002, 2003, 2007, 2008 Free Software Foundation, Inc. | ||
| 179 | + Copyright 2002, 2003, 2007, 2008, 2010 Free Software Foundation, Inc. | ||
| 180 | Contributed by Wasabi Systems, Inc. | ||
| 181 | |||
| 182 | This file is part of GCC. | ||
| 183 | @@ -89,3 +89,5 @@ | ||
| 184 | |||
| 185 | #undef TARGET_VERSION | ||
| 186 | #define TARGET_VERSION fprintf (stderr, " (NetBSD/powerpc ELF)"); | ||
| 187 | + | ||
| 188 | +#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) | ||
| 189 | Index: gcc-4_5-branch/gcc/config/rs6000/sysv4.h | ||
| 190 | =================================================================== | ||
| 191 | --- gcc-4_5-branch.orig/gcc/config/rs6000/sysv4.h 2011-09-17 11:11:29.000000000 -0700 | ||
| 192 | +++ gcc-4_5-branch/gcc/config/rs6000/sysv4.h 2011-09-17 11:13:13.623298761 -0700 | ||
| 193 | @@ -293,6 +293,10 @@ do { \ | ||
| 194 | #define RESTORE_FP_PREFIX "_restfpr_" | ||
| 195 | #define RESTORE_FP_SUFFIX "" | ||
| 196 | |||
| 197 | +/* Type used for size_t, as a string used in a declaration. */ | ||
| 198 | +#undef SIZE_TYPE | ||
| 199 | +#define SIZE_TYPE "unsigned int" | ||
| 200 | + | ||
| 201 | /* Type used for ptrdiff_t, as a string used in a declaration. */ | ||
| 202 | #define PTRDIFF_TYPE "int" | ||
| 203 | |||
| 204 | @@ -588,9 +592,8 @@ extern int fixuplabelno; | ||
| 205 | /* Override svr4.h definition. */ | ||
| 206 | #undef ASM_SPEC | ||
| 207 | #define ASM_SPEC "%(asm_cpu) \ | ||
| 208 | -%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}}" \ | ||
| 209 | -SVR4_ASM_SPEC \ | ||
| 210 | -"%{mrelocatable} %{mrelocatable-lib} %{fpic|fpie|fPIC|fPIE:-K PIC} \ | ||
| 211 | +%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}} \ | ||
| 212 | +%{mrelocatable} %{mrelocatable-lib} %{fpic|fpie|fPIC|fPIE:-K PIC} \ | ||
| 213 | %{memb|msdata=eabi: -memb} \ | ||
| 214 | %{mlittle|mlittle-endian:-mlittle; \ | ||
| 215 | mbig|mbig-endian :-mbig; \ | ||
| 216 | @@ -1120,3 +1123,5 @@ ncrtn.o%s" | ||
| 217 | |||
| 218 | /* This target uses the sysv4.opt file. */ | ||
| 219 | #define TARGET_USES_SYSV4_OPT 1 | ||
| 220 | + | ||
| 221 | +#undef DBX_REGISTER_NUMBER | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-pr43698-arm-rev-instr.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-pr43698-arm-rev-instr.patch deleted file mode 100644 index 61c883e1f..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-pr43698-arm-rev-instr.patch +++ /dev/null | |||
| @@ -1,117 +0,0 @@ | |||
| 1 | backport http://gcc.gnu.org/viewcvs?view=revision&revision=162404 | ||
| 2 | from trunk | ||
| 3 | |||
| 4 | Which fixes http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43698 | ||
| 5 | |||
| 6 | 2010-07-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | ||
| 7 | |||
| 8 | PR target/43698 | ||
| 9 | * config/arm/arm.md: Split arm_rev into *arm_rev | ||
| 10 | and *thumb1_rev. Set *arm_rev to be predicable. | ||
| 11 | |||
| 12 | 2010-07-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | ||
| 13 | |||
| 14 | PR target/43698 | ||
| 15 | * gcc.target/arm/pr43698.c: New test. | ||
| 16 | |||
| 17 | |||
| 18 | /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date | ||
| 19 | Usage: date [OPTION]... [+FORMAT] | ||
| 20 | Display the current time in the given FORMAT. | ||
| 21 | |||
| 22 | -d, --date=STRING display time described by STRING, not `now' | ||
| 23 | -f, --file=DATEFILE like --date once for each line of DATEFILE | ||
| 24 | -R, --rfc-822 output RFC-822 compliant date string | ||
| 25 | -u, --utc, --universal print or set Coordinated Universal Time | ||
| 26 | --help display this help and exit | ||
| 27 | date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date | ||
| 28 | date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date | ||
| 29 | date is /bin/date | ||
| 30 | date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date | ||
| 31 | date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date | ||
| 32 | date is /bin/date | ||
| 33 | date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date | ||
| 34 | date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date | ||
| 35 | date is /bin/date | ||
| 36 | date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date | ||
| 37 | date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date | ||
| 38 | date is /bin/date | ||
| 39 | date | ||
| 40 | Khem | ||
| 41 | Index: gcc-4.5/gcc/config/arm/arm.md | ||
| 42 | =================================================================== | ||
| 43 | --- gcc-4.5.orig/gcc/config/arm/arm.md 2010-07-20 20:31:25.000000000 -0700 | ||
| 44 | +++ gcc-4.5/gcc/config/arm/arm.md 2010-07-22 14:55:54.303169081 -0700 | ||
| 45 | @@ -11197,15 +11197,21 @@ | ||
| 46 | (set_attr "length" "4")] | ||
| 47 | ) | ||
| 48 | |||
| 49 | -(define_insn "arm_rev" | ||
| 50 | +(define_insn "*arm_rev" | ||
| 51 | [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 52 | (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))] | ||
| 53 | - "TARGET_EITHER && arm_arch6" | ||
| 54 | - "rev\t%0, %1" | ||
| 55 | - [(set (attr "length") | ||
| 56 | - (if_then_else (eq_attr "is_thumb" "yes") | ||
| 57 | - (const_int 2) | ||
| 58 | - (const_int 4)))] | ||
| 59 | + "TARGET_32BIT && arm_arch6" | ||
| 60 | + "rev%?\t%0, %1" | ||
| 61 | + [(set_attr "predicable" "yes") | ||
| 62 | + (set_attr "length" "4")] | ||
| 63 | +) | ||
| 64 | + | ||
| 65 | +(define_insn "*thumb1_rev" | ||
| 66 | + [(set (match_operand:SI 0 "s_register_operand" "=l") | ||
| 67 | + (bswap:SI (match_operand:SI 1 "s_register_operand" "l")))] | ||
| 68 | + "TARGET_THUMB1 && arm_arch6" | ||
| 69 | + "rev\t%0, %1" | ||
| 70 | + [(set_attr "length" "2")] | ||
| 71 | ) | ||
| 72 | |||
| 73 | (define_expand "arm_legacy_rev" | ||
| 74 | Index: gcc-4.5/gcc/testsuite/gcc.target/arm/pr43698.c | ||
| 75 | =================================================================== | ||
| 76 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 77 | +++ gcc-4.5/gcc/testsuite/gcc.target/arm/pr43698.c 2010-07-22 14:56:35.406670213 -0700 | ||
| 78 | @@ -0,0 +1,39 @@ | ||
| 79 | +/* { dg-do run } */ | ||
| 80 | +/* { dg-options "-Os -march=armv7-a" } */ | ||
| 81 | +#include <stdint.h> | ||
| 82 | +#include <stdlib.h> | ||
| 83 | + | ||
| 84 | + | ||
| 85 | +char do_reverse_endian = 0; | ||
| 86 | + | ||
| 87 | +# define bswap_32(x) \ | ||
| 88 | + ((((x) & 0xff000000) >> 24) | \ | ||
| 89 | + (((x) & 0x00ff0000) >> 8) | \ | ||
| 90 | + (((x) & 0x0000ff00) << 8) | \ | ||
| 91 | + (((x) & 0x000000ff) << 24)) | ||
| 92 | + | ||
| 93 | +#define EGET(X) \ | ||
| 94 | + (__extension__ ({ \ | ||
| 95 | + uint64_t __res; \ | ||
| 96 | + if (!do_reverse_endian) { __res = (X); \ | ||
| 97 | + } else if (sizeof(X) == 4) { __res = bswap_32((X)); \ | ||
| 98 | + } \ | ||
| 99 | + __res; \ | ||
| 100 | + })) | ||
| 101 | + | ||
| 102 | +void __attribute__((noinline)) X(char **phdr, char **data, int *phoff) | ||
| 103 | +{ | ||
| 104 | + *phdr = *data + EGET(*phoff); | ||
| 105 | +} | ||
| 106 | + | ||
| 107 | +int main() | ||
| 108 | +{ | ||
| 109 | + char *phdr; | ||
| 110 | + char *data = (char *)0x40164000; | ||
| 111 | + int phoff = 0x34; | ||
| 112 | + X(&phdr, &data, &phoff); | ||
| 113 | + if (phdr != (char *)0x40164034) | ||
| 114 | + abort (); | ||
| 115 | + exit (0); | ||
| 116 | +} | ||
| 117 | + | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-scalar-widening-pr45847.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-scalar-widening-pr45847.patch deleted file mode 100644 index cbe12303e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-scalar-widening-pr45847.patch +++ /dev/null | |||
| @@ -1,63 +0,0 @@ | |||
| 1 | Hi, | ||
| 2 | |||
| 3 | The attached patch fixes Bugzilla 45847 | ||
| 4 | (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45847). When compiling | ||
| 5 | without -mvectorize-with-neon-quad and vectorizing scalar widening | ||
| 6 | operations that widen words to double words, there are no corresponding | ||
| 7 | vector types for DI scalar types. For this scenario, a call to | ||
| 8 | get_vect_type_for_scalar_type() returns NULL and an absent NULL-check | ||
| 9 | caused this segfault. The attached patch adds this NULL-check. Also, | ||
| 10 | this is consistent with all the other places where a NULL-check follows | ||
| 11 | a call to get_vect_type_for_scalar_type() in tree-vect-patterns.c. | ||
| 12 | |||
| 13 | Regression tested with arm-linux-gnueabi. OK? | ||
| 14 | |||
| 15 | -- | ||
| 16 | Tejas Belagod | ||
| 17 | ARM. | ||
| 18 | |||
| 19 | gcc/ | ||
| 20 | |||
| 21 | 2010-10-05 Tejas Belagod <tejas.belagod@arm.com> | ||
| 22 | |||
| 23 | * tree-vect-patterns.c (vect_recog_widen_mult_pattern): Add NULL | ||
| 24 | check for vectype_out returned by get_vectype_for_scalar_type(). | ||
| 25 | |||
| 26 | testsuite/ | ||
| 27 | |||
| 28 | 2010-10-05 Tejas Belagod <tejas.belagod@arm.com> | ||
| 29 | |||
| 30 | * gcc.dg/vect/pr45847.c: New test. | ||
| 31 | |||
| 32 | Index: gcc-4.5/gcc/testsuite/gcc.dg/vect/pr45847.c | ||
| 33 | =================================================================== | ||
| 34 | --- /dev/null | ||
| 35 | +++ gcc-4.5/gcc/testsuite/gcc.dg/vect/pr45847.c | ||
| 36 | @@ -0,0 +1,15 @@ | ||
| 37 | +/* { dg-do compile } */ | ||
| 38 | + | ||
| 39 | + | ||
| 40 | +long long foo (long long *__restrict a, int *__restrict b, int *__restrict c ) | ||
| 41 | +{ | ||
| 42 | + int i; | ||
| 43 | + long long sum=0; | ||
| 44 | + for (i=0;i<256;i++) | ||
| 45 | + sum += (long long)b[i] * c[i]; | ||
| 46 | + | ||
| 47 | + return sum; | ||
| 48 | +} | ||
| 49 | + | ||
| 50 | +/* { dg-final { cleanup-tree-dump "vect" } } */ | ||
| 51 | + | ||
| 52 | Index: gcc-4.5/gcc/tree-vect-patterns.c | ||
| 53 | =================================================================== | ||
| 54 | --- gcc-4.5.orig/gcc/tree-vect-patterns.c | ||
| 55 | +++ gcc-4.5/gcc/tree-vect-patterns.c | ||
| 56 | @@ -411,6 +411,7 @@ vect_recog_widen_mult_pattern (gimple la | ||
| 57 | /* Check target support */ | ||
| 58 | vectype = get_vectype_for_scalar_type (half_type0); | ||
| 59 | if (!vectype | ||
| 60 | + || !get_vectype_for_scalar_type (type) | ||
| 61 | || !supportable_widening_operation (WIDEN_MULT_EXPR, last_stmt, vectype, | ||
| 62 | &dummy, &dummy, &dummy_code, | ||
| 63 | &dummy_code, &dummy_int, &dummy_vec)) | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-uclibc-locale-ctype_touplow_t.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-uclibc-locale-ctype_touplow_t.patch deleted file mode 100644 index 4f94fc9d6..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-uclibc-locale-ctype_touplow_t.patch +++ /dev/null | |||
| @@ -1,67 +0,0 @@ | |||
| 1 | Index: gcc-4.5/libstdc++-v3/config/locale/generic/c_locale.h | ||
| 2 | =================================================================== | ||
| 3 | --- gcc-4.5.orig/libstdc++-v3/config/locale/generic/c_locale.h 2010-06-30 22:30:53.993316002 -0700 | ||
| 4 | +++ gcc-4.5/libstdc++-v3/config/locale/generic/c_locale.h 2010-06-30 22:31:26.043316001 -0700 | ||
| 5 | @@ -41,12 +41,17 @@ | ||
| 6 | |||
| 7 | #include <clocale> | ||
| 8 | #include <cstddef> | ||
| 9 | +#include <features.h> | ||
| 10 | +#include <ctype.h> | ||
| 11 | |||
| 12 | #define _GLIBCXX_NUM_CATEGORIES 0 | ||
| 13 | |||
| 14 | _GLIBCXX_BEGIN_NAMESPACE(std) | ||
| 15 | - | ||
| 16 | - typedef int* __c_locale; | ||
| 17 | +#ifdef __UCLIBC__ | ||
| 18 | + typedef __ctype_touplow_t* __c_locale; | ||
| 19 | +#else | ||
| 20 | + typedef int* __c_locale; | ||
| 21 | +#endif | ||
| 22 | |||
| 23 | // Convert numeric value of type double and long double to string and | ||
| 24 | // return length of string. If vsnprintf is available use it, otherwise | ||
| 25 | Index: gcc-4.5/libstdc++-v3/config/os/gnu-linux/ctype_base.h | ||
| 26 | =================================================================== | ||
| 27 | --- gcc-4.5.orig/libstdc++-v3/config/os/gnu-linux/ctype_base.h 2010-06-30 22:30:54.013316002 -0700 | ||
| 28 | +++ gcc-4.5/libstdc++-v3/config/os/gnu-linux/ctype_base.h 2010-06-30 22:31:26.053316001 -0700 | ||
| 29 | @@ -33,14 +33,21 @@ | ||
| 30 | */ | ||
| 31 | |||
| 32 | // Information as gleaned from /usr/include/ctype.h | ||
| 33 | - | ||
| 34 | + | ||
| 35 | +#include <features.h> | ||
| 36 | +#include <ctype.h> | ||
| 37 | + | ||
| 38 | _GLIBCXX_BEGIN_NAMESPACE(std) | ||
| 39 | |||
| 40 | /// @brief Base class for ctype. | ||
| 41 | struct ctype_base | ||
| 42 | { | ||
| 43 | // Non-standard typedefs. | ||
| 44 | - typedef const int* __to_type; | ||
| 45 | +#ifdef __UCLIBC__ | ||
| 46 | + typedef const __ctype_touplow_t* __to_type; | ||
| 47 | +#else | ||
| 48 | + typedef const int* __to_type; | ||
| 49 | +#endif | ||
| 50 | |||
| 51 | // NB: Offsets into ctype<char>::_M_table force a particular size | ||
| 52 | // on the mask type. Because of this, we don't use an enum. | ||
| 53 | Index: gcc-4.5/libstdc++-v3/config/locale/generic/c_locale.cc | ||
| 54 | =================================================================== | ||
| 55 | --- gcc-4.5.orig/libstdc++-v3/config/locale/generic/c_locale.cc 2010-06-28 12:12:42.000000000 -0700 | ||
| 56 | +++ gcc-4.5/libstdc++-v3/config/locale/generic/c_locale.cc 2010-06-30 22:31:26.063316001 -0700 | ||
| 57 | @@ -256,5 +256,10 @@ _GLIBCXX_END_NAMESPACE | ||
| 58 | #ifdef _GLIBCXX_LONG_DOUBLE_COMPAT | ||
| 59 | #define _GLIBCXX_LDBL_COMPAT(dbl, ldbl) \ | ||
| 60 | extern "C" void ldbl (void) __attribute__ ((alias (#dbl))) | ||
| 61 | +#ifdef __UCLIBC__ | ||
| 62 | +// This is because __c_locale is of type __ctype_touplow_t* which is short on uclibc. for glibc its int* | ||
| 63 | +_GLIBCXX_LDBL_COMPAT(_ZSt14__convert_to_vIdEvPKcRT_RSt12_Ios_IostateRKPs, _ZSt14__convert_to_vIeEvPKcRT_RSt12_Ios_IostateRKPs); | ||
| 64 | +#else | ||
| 65 | _GLIBCXX_LDBL_COMPAT(_ZSt14__convert_to_vIdEvPKcRT_RSt12_Ios_IostateRKPi, _ZSt14__convert_to_vIeEvPKcRT_RSt12_Ios_IostateRKPi); | ||
| 66 | +#endif | ||
| 67 | #endif // _GLIBCXX_LONG_DOUBLE_COMPAT | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-with-linker-hash-style.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-with-linker-hash-style.patch deleted file mode 100644 index ac4281ac2..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-with-linker-hash-style.patch +++ /dev/null | |||
| @@ -1,212 +0,0 @@ | |||
| 1 | Upstream-Status: Backport | ||
| 2 | Signed-off-by: Khem Raj <raj.khem@gmail.com> | ||
| 3 | |||
| 4 | commit 3cb9bbfa927aa187048534f9069202c017a78e38 | ||
| 5 | Author: ppluzhnikov <ppluzhnikov@138bc75d-0d04-0410-961f-82ee72b054a4> | ||
| 6 | Date: Wed May 11 18:28:14 2011 +0000 | ||
| 7 | |||
| 8 | 2011-05-11 Satoru Takabayashi <satorux@google.com> | ||
| 9 | Paul Pluzhnikov <ppluzhnikov@google.com> | ||
| 10 | |||
| 11 | * gcc/doc/install.texi (Configuration): Document | ||
| 12 | --with-linker-hash-style. | ||
| 13 | * gcc/gcc.c (init_spec): Handle LINKER_HASH_STYLE. | ||
| 14 | * gcc/config.in: Add LINKER_HASH_STYLE. | ||
| 15 | * gcc/configure.ac: Add --with-linker-hash-style. | ||
| 16 | * gcc/configure: Regenerate. | ||
| 17 | |||
| 18 | |||
| 19 | |||
| 20 | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@173668 138bc75d-0d04-0410-961f-82ee72b054a4 | ||
| 21 | |||
| 22 | Index: gcc-4_5-branch/gcc/config.in | ||
| 23 | =================================================================== | ||
| 24 | --- gcc-4_5-branch.orig/gcc/config.in 2011-12-03 13:41:00.000000000 -0800 | ||
| 25 | +++ gcc-4_5-branch/gcc/config.in 2011-12-03 13:44:46.287530329 -0800 | ||
| 26 | @@ -113,6 +113,12 @@ | ||
| 27 | #endif | ||
| 28 | |||
| 29 | |||
| 30 | +/* The linker hash style */ | ||
| 31 | +#ifndef USED_FOR_TARGET | ||
| 32 | +#undef LINKER_HASH_STYLE | ||
| 33 | +#endif | ||
| 34 | + | ||
| 35 | + | ||
| 36 | /* Define to enable LTO support. */ | ||
| 37 | #ifndef USED_FOR_TARGET | ||
| 38 | #undef ENABLE_LTO | ||
| 39 | Index: gcc-4_5-branch/gcc/configure | ||
| 40 | =================================================================== | ||
| 41 | --- gcc-4_5-branch.orig/gcc/configure 2011-12-03 13:41:00.000000000 -0800 | ||
| 42 | +++ gcc-4_5-branch/gcc/configure 2011-12-03 13:46:12.747530321 -0800 | ||
| 43 | @@ -600,6 +600,7 @@ | ||
| 44 | |||
| 45 | ac_subst_vars='LTLIBOBJS | ||
| 46 | LIBOBJS | ||
| 47 | +enable_target_optspace | ||
| 48 | enable_plugin | ||
| 49 | pluginlibs | ||
| 50 | LIBELFINC | ||
| 51 | @@ -915,7 +916,7 @@ | ||
| 52 | with_slibdir | ||
| 53 | enable_poison_system_directories | ||
| 54 | enable_plugin | ||
| 55 | -enable_target_optspace | ||
| 56 | +with_linker_hash_style | ||
| 57 | ' | ||
| 58 | ac_precious_vars='build_alias | ||
| 59 | host_alias | ||
| 60 | @@ -1663,6 +1664,8 @@ | ||
| 61 | with the compiler | ||
| 62 | --with-system-zlib use installed libz | ||
| 63 | --with-slibdir=DIR shared libraries in DIR [LIBDIR] | ||
| 64 | + --with-linker-hash-style={sysv,gnu,both} | ||
| 65 | + specify the linker hash style | ||
| 66 | |||
| 67 | Some influential environment variables: | ||
| 68 | CC C compiler command | ||
| 69 | @@ -17115,7 +17118,7 @@ | ||
| 70 | lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 | ||
| 71 | lt_status=$lt_dlunknown | ||
| 72 | cat > conftest.$ac_ext <<_LT_EOF | ||
| 73 | -#line 17114 "configure" | ||
| 74 | +#line 17121 "configure" | ||
| 75 | #include "confdefs.h" | ||
| 76 | |||
| 77 | #if HAVE_DLFCN_H | ||
| 78 | @@ -17221,7 +17224,7 @@ | ||
| 79 | lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 | ||
| 80 | lt_status=$lt_dlunknown | ||
| 81 | cat > conftest.$ac_ext <<_LT_EOF | ||
| 82 | -#line 17220 "configure" | ||
| 83 | +#line 17227 "configure" | ||
| 84 | #include "confdefs.h" | ||
| 85 | |||
| 86 | #if HAVE_DLFCN_H | ||
| 87 | @@ -25659,12 +25662,42 @@ | ||
| 88 | |||
| 89 | fi | ||
| 90 | |||
| 91 | -if test x"$enable_target_optspace" != x; then : | ||
| 92 | + | ||
| 93 | +if test x"$enable_target_optspace" != x; then | ||
| 94 | |||
| 95 | $as_echo "#define ENABLE_TARGET_OPTSPACE 1" >>confdefs.h | ||
| 96 | |||
| 97 | fi | ||
| 98 | |||
| 99 | +# Specify what hash style to use by default. | ||
| 100 | + | ||
| 101 | +# Check whether --with-linker-hash-style was given. | ||
| 102 | +if test "${with_linker_hash_style+set}" = set; then : | ||
| 103 | + withval=$with_linker_hash_style; case x"$withval" in | ||
| 104 | + xsysv) | ||
| 105 | + LINKER_HASH_STYLE=sysv | ||
| 106 | + ;; | ||
| 107 | + xgnu) | ||
| 108 | + LINKER_HASH_STYLE=gnu | ||
| 109 | + ;; | ||
| 110 | + xboth) | ||
| 111 | + LINKER_HASH_STYLE=both | ||
| 112 | + ;; | ||
| 113 | + *) | ||
| 114 | + as_fn_error "$withval is an invalid option to --with-linker-hash-style" "$LINENO" 5 | ||
| 115 | + ;; | ||
| 116 | + esac | ||
| 117 | +else | ||
| 118 | + LINKER_HASH_STYLE='' | ||
| 119 | +fi | ||
| 120 | + | ||
| 121 | +if test x"${LINKER_HASH_STYLE}" != x; then | ||
| 122 | + | ||
| 123 | +cat >>confdefs.h <<_ACEOF | ||
| 124 | +#define LINKER_HASH_STYLE "$LINKER_HASH_STYLE" | ||
| 125 | +_ACEOF | ||
| 126 | + | ||
| 127 | +fi | ||
| 128 | |||
| 129 | # Configure the subdirectories | ||
| 130 | # AC_CONFIG_SUBDIRS($subdirs) | ||
| 131 | Index: gcc-4_5-branch/gcc/configure.ac | ||
| 132 | =================================================================== | ||
| 133 | --- gcc-4_5-branch.orig/gcc/configure.ac 2011-12-03 13:41:00.000000000 -0800 | ||
| 134 | +++ gcc-4_5-branch/gcc/configure.ac 2011-12-03 13:41:04.499530358 -0800 | ||
| 135 | @@ -4664,6 +4664,30 @@ | ||
| 136 | AC_DEFINE(ENABLE_TARGET_OPTSPACE, 1, [Define to enable target optspace support.]) | ||
| 137 | fi | ||
| 138 | |||
| 139 | +# Specify what hash style to use by default. | ||
| 140 | +AC_ARG_WITH([linker-hash-style], | ||
| 141 | +[AC_HELP_STRING([--with-linker-hash-style={sysv,gnu,both}], | ||
| 142 | + [specify the linker hash style])], | ||
| 143 | +[case x"$withval" in | ||
| 144 | + xsysv) | ||
| 145 | + LINKER_HASH_STYLE=sysv | ||
| 146 | + ;; | ||
| 147 | + xgnu) | ||
| 148 | + LINKER_HASH_STYLE=gnu | ||
| 149 | + ;; | ||
| 150 | + xboth) | ||
| 151 | + LINKER_HASH_STYLE=both | ||
| 152 | + ;; | ||
| 153 | + *) | ||
| 154 | + AC_MSG_ERROR([$withval is an invalid option to --with-linker-hash-style]) | ||
| 155 | + ;; | ||
| 156 | + esac], | ||
| 157 | +[LINKER_HASH_STYLE='']) | ||
| 158 | +if test x"${LINKER_HASH_STYLE}" != x; then | ||
| 159 | + AC_DEFINE_UNQUOTED(LINKER_HASH_STYLE, "$LINKER_HASH_STYLE", | ||
| 160 | + [The linker hash style]) | ||
| 161 | +fi | ||
| 162 | + | ||
| 163 | # Configure the subdirectories | ||
| 164 | # AC_CONFIG_SUBDIRS($subdirs) | ||
| 165 | |||
| 166 | Index: gcc-4_5-branch/gcc/doc/install.texi | ||
| 167 | =================================================================== | ||
| 168 | --- gcc-4_5-branch.orig/gcc/doc/install.texi 2011-12-03 13:15:09.000000000 -0800 | ||
| 169 | +++ gcc-4_5-branch/gcc/doc/install.texi 2011-12-03 13:41:04.499530358 -0800 | ||
| 170 | @@ -1630,6 +1630,11 @@ | ||
| 171 | support @option{--build-id} option, a warning is issued and the | ||
| 172 | @option{--enable-linker-build-id} option is ignored. The default is off. | ||
| 173 | |||
| 174 | +@item --with-linker-hash-style=@var{choice} | ||
| 175 | +Tells GCC to pass @option{--hash-style=@var{choice}} option to the | ||
| 176 | +linker for all final links. @var{choice} can be one of | ||
| 177 | +@samp{sysv}, @samp{gnu}, and @samp{both} where @samp{sysv} is the default. | ||
| 178 | + | ||
| 179 | @item --enable-gnu-unique-object | ||
| 180 | @itemx --disable-gnu-unique-object | ||
| 181 | Tells GCC to use the gnu_unique_object relocation for C++ template | ||
| 182 | Index: gcc-4_5-branch/gcc/gcc.c | ||
| 183 | =================================================================== | ||
| 184 | --- gcc-4_5-branch.orig/gcc/gcc.c 2011-12-03 13:41:00.000000000 -0800 | ||
| 185 | +++ gcc-4_5-branch/gcc/gcc.c 2011-12-03 13:41:04.499530358 -0800 | ||
| 186 | @@ -1917,7 +1917,8 @@ | ||
| 187 | } | ||
| 188 | #endif | ||
| 189 | |||
| 190 | -#if defined LINK_EH_SPEC || defined LINK_BUILDID_SPEC | ||
| 191 | +#if defined LINK_EH_SPEC || defined LINK_BUILDID_SPEC || \ | ||
| 192 | + defined LINKER_HASH_STYLE | ||
| 193 | # ifdef LINK_BUILDID_SPEC | ||
| 194 | /* Prepend LINK_BUILDID_SPEC to whatever link_spec we had before. */ | ||
| 195 | obstack_grow (&obstack, LINK_BUILDID_SPEC, sizeof(LINK_BUILDID_SPEC) - 1); | ||
| 196 | @@ -1926,6 +1927,16 @@ | ||
| 197 | /* Prepend LINK_EH_SPEC to whatever link_spec we had before. */ | ||
| 198 | obstack_grow (&obstack, LINK_EH_SPEC, sizeof(LINK_EH_SPEC) - 1); | ||
| 199 | # endif | ||
| 200 | +# ifdef LINKER_HASH_STYLE | ||
| 201 | + /* Prepend --hash-style=LINKER_HASH_STYLE to whatever link_spec we had | ||
| 202 | + before. */ | ||
| 203 | + { | ||
| 204 | + static const char hash_style[] = "--hash-style="; | ||
| 205 | + obstack_grow (&obstack, hash_style, sizeof(hash_style) - 1); | ||
| 206 | + obstack_grow (&obstack, LINKER_HASH_STYLE, sizeof(LINKER_HASH_STYLE) - 1); | ||
| 207 | + obstack_1grow (&obstack, ' '); | ||
| 208 | + } | ||
| 209 | +# endif | ||
| 210 | obstack_grow0 (&obstack, link_spec, strlen (link_spec)); | ||
| 211 | link_spec = XOBFINISH (&obstack, const char *); | ||
| 212 | #endif | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc_revert_base_version_to_4.5.0.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc_revert_base_version_to_4.5.0.patch deleted file mode 100644 index 5f134ef33..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc_revert_base_version_to_4.5.0.patch +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | the svn patch changed the BASE-VER to 4.5.1, bring it back to 4.5.0 | ||
| 2 | - Nitin A Kamble nitin.a.kamble@intel.com | ||
| 3 | - 2010/07/20 | ||
| 4 | |||
| 5 | --- gcc-4.5.0/gcc/BASE-VER 2010-07-20 00:57:37.000000000 -0700 | ||
| 6 | +++ gcc-4.5.0.new/gcc/BASE-VER 2010-07-20 01:06:17.000000000 -0700 | ||
| 7 | @@ -1 +1 @@ | ||
| 8 | -4.5.1 | ||
| 9 | +4.5.0 | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-emit-__cxa_end_cleanup-in-text.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-emit-__cxa_end_cleanup-in-text.patch deleted file mode 100644 index ada36a591..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-emit-__cxa_end_cleanup-in-text.patch +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | 2010-06-07 Khem Raj <raj.khem@gmail.com> | ||
| 2 | |||
| 3 | * libsupc++/eh_arm.cc (__cxa_end_cleanup): Use .pushsection/.popsection | ||
| 4 | to emit inline assembly into .text section. | ||
| 5 | |||
| 6 | Index: gcc-4.5/libstdc++-v3/libsupc++/eh_arm.cc | ||
| 7 | =================================================================== | ||
| 8 | --- gcc-4.5.orig/libstdc++-v3/libsupc++/eh_arm.cc 2010-06-04 23:20:18.000000000 -0700 | ||
| 9 | +++ gcc-4.5/libstdc++-v3/libsupc++/eh_arm.cc 2010-06-08 11:27:34.247541722 -0700 | ||
| 10 | @@ -157,22 +157,26 @@ __gnu_end_cleanup(void) | ||
| 11 | // Assembly wrapper to call __gnu_end_cleanup without clobbering r1-r3. | ||
| 12 | // Also push r4 to preserve stack alignment. | ||
| 13 | #ifdef __thumb__ | ||
| 14 | -asm (".global __cxa_end_cleanup\n" | ||
| 15 | +asm (" .pushsection .text.__cxa_end_cleanup\n" | ||
| 16 | +" .global __cxa_end_cleanup\n" | ||
| 17 | " .type __cxa_end_cleanup, \"function\"\n" | ||
| 18 | " .thumb_func\n" | ||
| 19 | "__cxa_end_cleanup:\n" | ||
| 20 | " push\t{r1, r2, r3, r4}\n" | ||
| 21 | " bl\t__gnu_end_cleanup\n" | ||
| 22 | " pop\t{r1, r2, r3, r4}\n" | ||
| 23 | -" bl\t_Unwind_Resume @ Never returns\n"); | ||
| 24 | +" bl\t_Unwind_Resume @ Never returns\n" | ||
| 25 | +" .popsection\n"); | ||
| 26 | #else | ||
| 27 | -asm (".global __cxa_end_cleanup\n" | ||
| 28 | +asm (" .pushsection .text.__cxa_end_cleanup\n" | ||
| 29 | +" .global __cxa_end_cleanup\n" | ||
| 30 | " .type __cxa_end_cleanup, \"function\"\n" | ||
| 31 | "__cxa_end_cleanup:\n" | ||
| 32 | " stmfd\tsp!, {r1, r2, r3, r4}\n" | ||
| 33 | " bl\t__gnu_end_cleanup\n" | ||
| 34 | " ldmfd\tsp!, {r1, r2, r3, r4}\n" | ||
| 35 | -" bl\t_Unwind_Resume @ Never returns\n"); | ||
| 36 | +" bl\t_Unwind_Resume @ Never returns\n" | ||
| 37 | +" .popsection\n"); | ||
| 38 | #endif | ||
| 39 | |||
| 40 | #endif | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-pic.dpatch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-pic.dpatch deleted file mode 100644 index 70c9e8154..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-pic.dpatch +++ /dev/null | |||
| @@ -1,71 +0,0 @@ | |||
| 1 | #! /bin/sh -e | ||
| 2 | |||
| 3 | # DP: Build and install libstdc++_pic.a library. | ||
| 4 | |||
| 5 | dir= | ||
| 6 | if [ $# -eq 3 -a "$2" = '-d' ]; then | ||
| 7 | pdir="-d $3" | ||
| 8 | dir="$3/" | ||
| 9 | elif [ $# -ne 1 ]; then | ||
| 10 | echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" | ||
| 11 | exit 1 | ||
| 12 | fi | ||
| 13 | case "$1" in | ||
| 14 | -patch) | ||
| 15 | patch $pdir -f --no-backup-if-mismatch -p0 < $0 | ||
| 16 | ;; | ||
| 17 | -unpatch) | ||
| 18 | patch $pdir -f --no-backup-if-mismatch -R -p0 < $0 | ||
| 19 | ;; | ||
| 20 | *) | ||
| 21 | echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" | ||
| 22 | exit 1 | ||
| 23 | esac | ||
| 24 | exit 0 | ||
| 25 | |||
| 26 | diff -ur libstdc++-v3/src/Makefile.am libstdc++-v3/src/Makefile.am | ||
| 27 | --- libstdc++-v3/src/Makefile.am~ 2004-04-16 21:04:05.000000000 +0200 | ||
| 28 | +++ libstdc++-v3/src/Makefile.am 2004-07-03 20:22:43.000000000 +0200 | ||
| 29 | @@ -210,6 +210,10 @@ | ||
| 30 | $(OPT_LDFLAGS) $(SECTION_LDFLAGS) $(AM_CXXFLAGS) $(LDFLAGS) -o $@ | ||
| 31 | |||
| 32 | |||
| 33 | +install-exec-local: | ||
| 34 | + $(AR) cru libstdc++_pic.a .libs/*.o $(top_builddir)/libsupc++/*.o || touch libstdc++_pic.a | ||
| 35 | + $(INSTALL_DATA) libstdc++_pic.a $(DESTDIR)$(toolexeclibdir) | ||
| 36 | + | ||
| 37 | # Added bits to build debug library. | ||
| 38 | if GLIBCXX_BUILD_DEBUG | ||
| 39 | all-local: build_debug | ||
| 40 | diff -ur libstdc++-v3/src/Makefile.in libstdc++-v3/src/Makefile.in | ||
| 41 | --- libstdc++-v3/src/Makefile.in 2004-07-03 06:41:13.000000000 +0200 | ||
| 42 | +++ libstdc++-v3/src/Makefile.in 2004-07-03 20:25:05.000000000 +0200 | ||
| 43 | @@ -611,7 +611,7 @@ | ||
| 44 | |||
| 45 | install-data-am: install-data-local | ||
| 46 | |||
| 47 | -install-exec-am: install-toolexeclibLTLIBRARIES | ||
| 48 | +install-exec-am: install-toolexeclibLTLIBRARIES install-exec-local | ||
| 49 | |||
| 50 | install-info: install-info-am | ||
| 51 | |||
| 52 | @@ -644,6 +644,7 @@ | ||
| 53 | distclean-libtool distclean-tags distdir dvi dvi-am html \ | ||
| 54 | html-am info info-am install install-am install-data \ | ||
| 55 | install-data-am install-data-local install-exec \ | ||
| 56 | + install-exec-local \ | ||
| 57 | install-exec-am install-info install-info-am install-man \ | ||
| 58 | install-strip install-toolexeclibLTLIBRARIES installcheck \ | ||
| 59 | installcheck-am installdirs maintainer-clean \ | ||
| 60 | @@ -729,6 +730,11 @@ | ||
| 61 | install_debug: | ||
| 62 | (cd ${debugdir} && $(MAKE) \ | ||
| 63 | toolexeclibdir=$(glibcxx_toolexeclibdir)/debug install) | ||
| 64 | + | ||
| 65 | +install-exec-local: | ||
| 66 | + $(AR) cru libstdc++_pic.a .libs/*.o $(top_builddir)/libsupc++/*.o || touch libstdc++_pic.a | ||
| 67 | + $(INSTALL_DATA) libstdc++_pic.a $(DESTDIR)$(toolexeclibdir) | ||
| 68 | + | ||
| 69 | # Tell versions [3.59,3.63) of GNU make to not export all variables. | ||
| 70 | # Otherwise a system limit (for SysV at least) may be exceeded. | ||
| 71 | .NOEXPORT: | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99297.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99297.patch deleted file mode 100644 index bff745dae..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99297.patch +++ /dev/null | |||
| @@ -1,207 +0,0 @@ | |||
| 1 | 2010-06-28 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ 4.4: | ||
| 4 | |||
| 5 | Daniel Jacobowitz <dan@codesourcery.com> | ||
| 6 | Joseph Myers <joseph@codesourcery.com> | ||
| 7 | |||
| 8 | gcc/ | ||
| 9 | * doc/invoke.texi (-Wno-poison-system-directories): Document. | ||
| 10 | * gcc.c (LINK_COMMAND_SPEC): Pass --no-poison-system-directories | ||
| 11 | if -Wno-poison-system-directories and --error-poison-system-directories | ||
| 12 | if -Werror=poison-system-directories to linker. | ||
| 13 | * incpath.c: Include flags.h. Include toplev.h. | ||
| 14 | (merge_include_chains): If ENABLE_POISON_SYSTEM_DIRECTORIES defined | ||
| 15 | and flag_poison_system_directories is true, warn for use of | ||
| 16 | /usr/include, /usr/local/include or /usr/X11R6/include. | ||
| 17 | * Makefile.in (incpath.o): Depend on $(FLAGS_H) and toplev.h. | ||
| 18 | * common.opt (--Wno-poison-system-directories): New. | ||
| 19 | * configure.ac (--enable-poison-system-directories): New option. | ||
| 20 | * configure: Regenerate. | ||
| 21 | * config.in: Regenerate. | ||
| 22 | |||
| 23 | Index: gcc-4.5/gcc/Makefile.in | ||
| 24 | =================================================================== | ||
| 25 | --- gcc-4.5.orig/gcc/Makefile.in 2010-09-23 16:44:12.000000000 -0700 | ||
| 26 | +++ gcc-4.5/gcc/Makefile.in 2010-09-23 16:46:33.552416860 -0700 | ||
| 27 | @@ -1969,7 +1969,7 @@ gcc.srcextra: gengtype-lex.c | ||
| 28 | |||
| 29 | incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \ | ||
| 30 | intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \ | ||
| 31 | - $(MACHMODE_H) | ||
| 32 | + $(MACHMODE_H) $(FLAGS_H) toplev.h | ||
| 33 | |||
| 34 | c-decl.o : c-decl.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) \ | ||
| 35 | $(RTL_H) $(C_TREE_H) $(GGC_H) $(TARGET_H) $(FLAGS_H) $(FUNCTION_H) output.h \ | ||
| 36 | Index: gcc-4.5/gcc/common.opt | ||
| 37 | =================================================================== | ||
| 38 | --- gcc-4.5.orig/gcc/common.opt 2010-07-11 16:14:47.000000000 -0700 | ||
| 39 | +++ gcc-4.5/gcc/common.opt 2010-09-23 16:46:33.556418045 -0700 | ||
| 40 | @@ -152,6 +152,10 @@ Wpadded | ||
| 41 | Common Var(warn_padded) Warning | ||
| 42 | Warn when padding is required to align structure members | ||
| 43 | |||
| 44 | +Wpoison-system-directories | ||
| 45 | +Common Var(flag_poison_system_directories) Init(1) | ||
| 46 | +Warn for -I and -L options using system directories if cross compiling | ||
| 47 | + | ||
| 48 | Wshadow | ||
| 49 | Common Var(warn_shadow) Warning | ||
| 50 | Warn when one local variable shadows another | ||
| 51 | Index: gcc-4.5/gcc/config.in | ||
| 52 | =================================================================== | ||
| 53 | --- gcc-4.5.orig/gcc/config.in 2010-07-11 16:14:46.000000000 -0700 | ||
| 54 | +++ gcc-4.5/gcc/config.in 2010-09-23 16:46:33.556418045 -0700 | ||
| 55 | @@ -132,6 +132,12 @@ | ||
| 56 | #endif | ||
| 57 | |||
| 58 | |||
| 59 | +/* Define to warn for use of native system header directories */ | ||
| 60 | +#ifndef USED_FOR_TARGET | ||
| 61 | +#undef ENABLE_POISON_SYSTEM_DIRECTORIES | ||
| 62 | +#endif | ||
| 63 | + | ||
| 64 | + | ||
| 65 | /* Define if you want all operations on RTL (the basic data structure of the | ||
| 66 | optimizer and back end) to be checked for dynamic type safety at runtime. | ||
| 67 | This is quite expensive. */ | ||
| 68 | Index: gcc-4.5/gcc/configure | ||
| 69 | =================================================================== | ||
| 70 | --- gcc-4.5.orig/gcc/configure 2010-09-23 16:44:11.000000000 -0700 | ||
| 71 | +++ gcc-4.5/gcc/configure 2010-09-23 16:46:33.572415719 -0700 | ||
| 72 | @@ -913,6 +913,7 @@ with_system_zlib | ||
| 73 | enable_maintainer_mode | ||
| 74 | enable_version_specific_runtime_libs | ||
| 75 | with_slibdir | ||
| 76 | +enable_poison_system_directories | ||
| 77 | enable_plugin | ||
| 78 | ' | ||
| 79 | ac_precious_vars='build_alias | ||
| 80 | @@ -1620,6 +1621,8 @@ Optional Features: | ||
| 81 | --enable-version-specific-runtime-libs | ||
| 82 | specify that runtime libraries should be | ||
| 83 | installed in a compiler-specific directory | ||
| 84 | + --enable-poison-system-directories | ||
| 85 | + warn for use of native system header directories | ||
| 86 | --enable-plugin enable plugin support | ||
| 87 | |||
| 88 | Optional Packages: | ||
| 89 | @@ -25345,6 +25348,19 @@ fi | ||
| 90 | |||
| 91 | |||
| 92 | |||
| 93 | +# Check whether --enable-poison-system-directories was given. | ||
| 94 | +if test "${enable_poison_system_directories+set}" = set; then : | ||
| 95 | + enableval=$enable_poison_system_directories; | ||
| 96 | +else | ||
| 97 | + enable_poison_system_directories=no | ||
| 98 | +fi | ||
| 99 | + | ||
| 100 | +if test "x${enable_poison_system_directories}" = "xyes"; then | ||
| 101 | + | ||
| 102 | +$as_echo "#define ENABLE_POISON_SYSTEM_DIRECTORIES 1" >>confdefs.h | ||
| 103 | + | ||
| 104 | +fi | ||
| 105 | + | ||
| 106 | # Substitute configuration variables | ||
| 107 | |||
| 108 | |||
| 109 | Index: gcc-4.5/gcc/configure.ac | ||
| 110 | =================================================================== | ||
| 111 | --- gcc-4.5.orig/gcc/configure.ac 2010-09-23 16:44:11.000000000 -0700 | ||
| 112 | +++ gcc-4.5/gcc/configure.ac 2010-09-23 16:46:33.576417624 -0700 | ||
| 113 | @@ -4439,6 +4439,16 @@ else | ||
| 114 | fi) | ||
| 115 | AC_SUBST(slibdir) | ||
| 116 | |||
| 117 | +AC_ARG_ENABLE([poison-system-directories], | ||
| 118 | + AS_HELP_STRING([--enable-poison-system-directories], | ||
| 119 | + [warn for use of native system header directories]),, | ||
| 120 | + [enable_poison_system_directories=no]) | ||
| 121 | +if test "x${enable_poison_system_directories}" = "xyes"; then | ||
| 122 | + AC_DEFINE([ENABLE_POISON_SYSTEM_DIRECTORIES], | ||
| 123 | + [1], | ||
| 124 | + [Define to warn for use of native system header directories]) | ||
| 125 | +fi | ||
| 126 | + | ||
| 127 | # Substitute configuration variables | ||
| 128 | AC_SUBST(subdirs) | ||
| 129 | AC_SUBST(srcdir) | ||
| 130 | Index: gcc-4.5/gcc/doc/invoke.texi | ||
| 131 | =================================================================== | ||
| 132 | --- gcc-4.5.orig/gcc/doc/invoke.texi 2010-09-23 15:33:28.000000000 -0700 | ||
| 133 | +++ gcc-4.5/gcc/doc/invoke.texi 2010-09-23 16:46:33.584416934 -0700 | ||
| 134 | @@ -252,6 +252,7 @@ Objective-C and Objective-C++ Dialects}. | ||
| 135 | -Woverlength-strings -Wpacked -Wpacked-bitfield-compat -Wpadded @gol | ||
| 136 | -Wparentheses -Wpedantic-ms-format -Wno-pedantic-ms-format @gol | ||
| 137 | -Wpointer-arith -Wno-pointer-to-int-cast @gol | ||
| 138 | +-Wno-poison-system-directories @gol | ||
| 139 | -Wredundant-decls @gol | ||
| 140 | -Wreturn-type -Wsequence-point -Wshadow @gol | ||
| 141 | -Wsign-compare -Wsign-conversion -Wstack-protector @gol | ||
| 142 | @@ -3603,6 +3604,14 @@ code. However, note that using @option{ | ||
| 143 | option will @emph{not} warn about unknown pragmas in system | ||
| 144 | headers---for that, @option{-Wunknown-pragmas} must also be used. | ||
| 145 | |||
| 146 | +@item -Wno-poison-system-directories | ||
| 147 | +@opindex Wno-poison-system-directories | ||
| 148 | +Do not warn for @option{-I} or @option{-L} options using system | ||
| 149 | +directories such as @file{/usr/include} when cross compiling. This | ||
| 150 | +option is intended for use in chroot environments when such | ||
| 151 | +directories contain the correct headers and libraries for the target | ||
| 152 | +system rather than the host. | ||
| 153 | + | ||
| 154 | @item -Wfloat-equal | ||
| 155 | @opindex Wfloat-equal | ||
| 156 | @opindex Wno-float-equal | ||
| 157 | Index: gcc-4.5/gcc/gcc.c | ||
| 158 | =================================================================== | ||
| 159 | --- gcc-4.5.orig/gcc/gcc.c 2010-07-11 16:14:46.000000000 -0700 | ||
| 160 | +++ gcc-4.5/gcc/gcc.c 2010-09-23 16:46:33.588417920 -0700 | ||
| 161 | @@ -792,6 +792,8 @@ proper position among the other output f | ||
| 162 | %{flto} %{fwhopr} %l " LINK_PIE_SPEC \ | ||
| 163 | "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\ | ||
| 164 | %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\ | ||
| 165 | + %{Wno-poison-system-directories:--no-poison-system-directories}\ | ||
| 166 | + %{Werror=poison-system-directories:--error-poison-system-directories}\ | ||
| 167 | %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\ | ||
| 168 | %{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)} %(mflib)\ | ||
| 169 | %{fprofile-arcs|fprofile-generate*|coverage:-lgcov}\ | ||
| 170 | Index: gcc-4.5/gcc/incpath.c | ||
| 171 | =================================================================== | ||
| 172 | --- gcc-4.5.orig/gcc/incpath.c 2010-07-11 16:14:44.000000000 -0700 | ||
| 173 | +++ gcc-4.5/gcc/incpath.c 2010-09-23 16:46:33.588417920 -0700 | ||
| 174 | @@ -30,6 +30,8 @@ | ||
| 175 | #include "intl.h" | ||
| 176 | #include "incpath.h" | ||
| 177 | #include "cppdefault.h" | ||
| 178 | +#include "flags.h" | ||
| 179 | +#include "toplev.h" | ||
| 180 | |||
| 181 | /* Microsoft Windows does not natively support inodes. | ||
| 182 | VMS has non-numeric inodes. */ | ||
| 183 | @@ -353,6 +355,24 @@ merge_include_chains (const char *sysroo | ||
| 184 | } | ||
| 185 | fprintf (stderr, _("End of search list.\n")); | ||
| 186 | } | ||
| 187 | + | ||
| 188 | +#ifdef ENABLE_POISON_SYSTEM_DIRECTORIES | ||
| 189 | + if (flag_poison_system_directories) | ||
| 190 | + { | ||
| 191 | + struct cpp_dir *p; | ||
| 192 | + | ||
| 193 | + for (p = heads[QUOTE]; p; p = p->next) | ||
| 194 | + { | ||
| 195 | + if ((!strncmp (p->name, "/usr/include", 12)) | ||
| 196 | + || (!strncmp (p->name, "/usr/local/include", 18)) | ||
| 197 | + || (!strncmp (p->name, "/usr/X11R6/include", 18))) | ||
| 198 | + warning (OPT_Wpoison_system_directories, | ||
| 199 | + "include location \"%s\" is unsafe for " | ||
| 200 | + "cross-compilation", | ||
| 201 | + p->name); | ||
| 202 | + } | ||
| 203 | + } | ||
| 204 | +#endif | ||
| 205 | } | ||
| 206 | |||
| 207 | /* Use given -I paths for #include "..." but not #include <...>, and | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99298.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99298.patch deleted file mode 100644 index 541134a6b..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99298.patch +++ /dev/null | |||
| @@ -1,26654 +0,0 @@ | |||
| 1 | 2010-07-07 Sandra Loosemore <sandra@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline (originally from Sourcery G++ 4.4): | ||
| 4 | |||
| 5 | 2010-05-24 Daniel Jacobowitz <dan@codesourcery.com> | ||
| 6 | Sandra Loosemore <sandra@codesourcery.com> | ||
| 7 | |||
| 8 | gcc/ | ||
| 9 | * config/arm/neon-testgen.ml: Use dg-add-options arm_neon. | ||
| 10 | * doc/sourcebuild.texi (Effective-Target Keywords): Update arm_neon_ok | ||
| 11 | description. Add arm_neon_fp16_ok. | ||
| 12 | (Add Options): Add arm_neon and arm_neon_fp16. | ||
| 13 | |||
| 14 | gcc/testsuite/ | ||
| 15 | * gcc.target/arm/neon/: Regenerated test cases. | ||
| 16 | |||
| 17 | * gcc.target/arm/neon/polytypes.c, | ||
| 18 | gcc.target/arm/neon-vmla-1.c, gcc.target/arm/neon-vmls-1.c, | ||
| 19 | gcc.target/arm/neon-cond-1.c, gcc.target/arm/neon/vfp-shift-a2t2.c, | ||
| 20 | gcc.target/arm/neon-thumb2-move.c, gcc.dg/torture/arm-fp16-ops-8.c, | ||
| 21 | gcc.dg/torture/arm-fp16-ops-7.c, g++.dg/ext/arm-fp16/arm-fp16-ops-7.C, | ||
| 22 | g++.dg/ext/arm-fp16/arm-fp16-ops-8.C, g++.dg/abi/mangle-neon.C: Use | ||
| 23 | dg-add-options arm_neon. | ||
| 24 | |||
| 25 | * gcc.target/arm/fp16-compile-vcvt.c, gcc.dg/torture/arm-fp16-ops-5.c, | ||
| 26 | gcc.dg/torture/arm-fp16-ops-6.c, g++.dg/ext/arm-fp16/arm-fp16-ops-5.C, | ||
| 27 | g++.dg/ext/arm-fp16/arm-fp16-ops-6.C: Use dg-add-options arm_neon_fp16 | ||
| 28 | and arm_neon_fp16_ok. | ||
| 29 | |||
| 30 | * gcc.dg/vect/vect.exp, g++.dg/vect/vect.exp, | ||
| 31 | gfortran.dg/vect/vect.exp: Use add_options_for_arm_neon. | ||
| 32 | |||
| 33 | * lib/target-supports.exp (add_options_for_arm_neon): New. | ||
| 34 | (check_effective_target_arm_neon_ok_nocache): New, from | ||
| 35 | check_effective_target_arm_neon_ok. Check multiple possibilities. | ||
| 36 | (check_effective_target_arm_neon_ok): Use | ||
| 37 | check_effective_target_arm_neon_ok_nocache. | ||
| 38 | (add_options_for_arm_neon_fp16) | ||
| 39 | (check_effective_target_arm_neon_fp16_ok) | ||
| 40 | check_effective_target_arm_neon_fp16_ok_nocache): New. | ||
| 41 | (check_effective_target_arm_neon_hw): Use add_options_for_arm_neon. | ||
| 42 | |||
| 43 | |||
| 44 | === modified file 'gcc/config/arm/neon-testgen.ml' | ||
| 45 | Index: gcc-4_5-branch/gcc/config/arm/neon-testgen.ml | ||
| 46 | =================================================================== | ||
| 47 | --- gcc-4_5-branch.orig/gcc/config/arm/neon-testgen.ml | ||
| 48 | +++ gcc-4_5-branch/gcc/config/arm/neon-testgen.ml | ||
| 49 | @@ -51,8 +51,8 @@ let emit_prologue chan test_name = | ||
| 50 | Printf.fprintf chan "/* This file was autogenerated by neon-testgen. */\n\n"; | ||
| 51 | Printf.fprintf chan "/* { dg-do assemble } */\n"; | ||
| 52 | Printf.fprintf chan "/* { dg-require-effective-target arm_neon_ok } */\n"; | ||
| 53 | - Printf.fprintf chan | ||
| 54 | - "/* { dg-options \"-save-temps -O0 -mfpu=neon -mfloat-abi=softfp\" } */\n"; | ||
| 55 | + Printf.fprintf chan "/* { dg-options \"-save-temps -O0\" } */\n"; | ||
| 56 | + Printf.fprintf chan "/* { dg-add-options arm_neon } */\n"; | ||
| 57 | Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n"; | ||
| 58 | Printf.fprintf chan "void test_%s (void)\n{\n" test_name | ||
| 59 | |||
| 60 | Index: gcc-4_5-branch/gcc/doc/sourcebuild.texi | ||
| 61 | =================================================================== | ||
| 62 | --- gcc-4_5-branch.orig/gcc/doc/sourcebuild.texi | ||
| 63 | +++ gcc-4_5-branch/gcc/doc/sourcebuild.texi | ||
| 64 | @@ -362,7 +362,7 @@ A copy of @file{texinfo.tex} known to wo | ||
| 65 | @end table | ||
| 66 | |||
| 67 | DVI-formatted manuals are generated by @samp{make dvi}, which uses | ||
| 68 | -@command{texi2dvi} (via the Makefile macro @code{$(TEXI2DVI)}). | ||
| 69 | +@command{texi2dvi} (via the Makefile macro @code{$(TEXI2DVI)}). | ||
| 70 | PDF-formatted manuals are generated by @samp{make pdf}, which uses | ||
| 71 | @command{texi2pdf} (via the Makefile macro @code{$(TEXI2PDF)}). HTML | ||
| 72 | formatted manuals are generated by @samp{make html}. Info | ||
| 73 | @@ -1500,8 +1500,14 @@ ARM target supports generating NEON inst | ||
| 74 | Test system supports executing NEON instructions. | ||
| 75 | |||
| 76 | @item arm_neon_ok | ||
| 77 | -ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp}. | ||
| 78 | -Some multilibs may be incompatible with these options. | ||
| 79 | +@anchor{arm_neon_ok} | ||
| 80 | +ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp} or compatible | ||
| 81 | +options. Some multilibs may be incompatible with these options. | ||
| 82 | + | ||
| 83 | +@item arm_neon_fp16_ok | ||
| 84 | +@anchor{arm_neon_fp16_ok} | ||
| 85 | +ARM Target supports @code{-mfpu=neon-fp16 -mfloat-abi=softfp} or compatible | ||
| 86 | +options. Some multilibs may be incompatible with these options. | ||
| 87 | |||
| 88 | @item arm_thumb1_ok | ||
| 89 | ARM target generates Thumb-1 code for @code{-mthumb}. | ||
| 90 | @@ -1895,6 +1901,16 @@ Only MIPS targets support this feature, | ||
| 91 | |||
| 92 | @item tls | ||
| 93 | Add the target-specific flags needed to use thread-local storage. | ||
| 94 | + | ||
| 95 | +@item arm_neon | ||
| 96 | +NEON support. Only ARM targets support this feature, and only then | ||
| 97 | +in certain modes; see the @ref{arm_neon_ok,,arm_neon_ok effective target | ||
| 98 | +keyword}. | ||
| 99 | + | ||
| 100 | +@item arm_neon_fp16 | ||
| 101 | +NEON and half-precision floating point support. Only ARM targets | ||
| 102 | +support this feature, and only then in certain modes; see | ||
| 103 | +the @ref{arm_neon_ok,,arm_neon_fp16_ok effective target keyword}. | ||
| 104 | @end table | ||
| 105 | |||
| 106 | @node Require Support | ||
| 107 | Index: gcc-4_5-branch/gcc/testsuite/g++.dg/abi/mangle-neon.C | ||
| 108 | =================================================================== | ||
| 109 | --- gcc-4_5-branch.orig/gcc/testsuite/g++.dg/abi/mangle-neon.C | ||
| 110 | +++ gcc-4_5-branch/gcc/testsuite/g++.dg/abi/mangle-neon.C | ||
| 111 | @@ -2,7 +2,7 @@ | ||
| 112 | |||
| 113 | // { dg-do compile } | ||
| 114 | // { dg-require-effective-target arm_neon_ok } | ||
| 115 | -// { dg-options "-mfpu=neon -mfloat-abi=softfp" } | ||
| 116 | +// { dg-add-options arm_neon } | ||
| 117 | |||
| 118 | #include <arm_neon.h> | ||
| 119 | |||
| 120 | Index: gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C | ||
| 121 | =================================================================== | ||
| 122 | --- gcc-4_5-branch.orig/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C | ||
| 123 | +++ gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C | ||
| 124 | @@ -1,7 +1,8 @@ | ||
| 125 | /* Test various operators on __fp16 and mixed __fp16/float operands. */ | ||
| 126 | /* { dg-do compile { target arm*-*-* } } */ | ||
| 127 | -/* { dg-require-effective-target arm_neon_ok } */ | ||
| 128 | -/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */ | ||
| 129 | +/* { dg-require-effective-target arm_neon_fp16_ok } */ | ||
| 130 | +/* { dg-options "-mfp16-format=ieee" } */ | ||
| 131 | +/* { dg-add-options arm_neon_fp16 } */ | ||
| 132 | |||
| 133 | #include "arm-fp16-ops.h" | ||
| 134 | |||
| 135 | Index: gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C | ||
| 136 | =================================================================== | ||
| 137 | --- gcc-4_5-branch.orig/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C | ||
| 138 | +++ gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C | ||
| 139 | @@ -1,7 +1,8 @@ | ||
| 140 | /* Test various operators on __fp16 and mixed __fp16/float operands. */ | ||
| 141 | /* { dg-do compile { target arm*-*-* } } */ | ||
| 142 | -/* { dg-require-effective-target arm_neon_ok } */ | ||
| 143 | -/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon-fp16 -mfloat-abi=softfp" } */ | ||
| 144 | +/* { dg-require-effective-target arm_neon_fp16_ok } */ | ||
| 145 | +/* { dg-options "-mfp16-format=ieee -ffast-math" } */ | ||
| 146 | +/* { dg-add-options arm_neon_fp16 } */ | ||
| 147 | |||
| 148 | #include "arm-fp16-ops.h" | ||
| 149 | |||
| 150 | Index: gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C | ||
| 151 | =================================================================== | ||
| 152 | --- gcc-4_5-branch.orig/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C | ||
| 153 | +++ gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C | ||
| 154 | @@ -1,7 +1,8 @@ | ||
| 155 | /* Test various operators on __fp16 and mixed __fp16/float operands. */ | ||
| 156 | /* { dg-do compile { target arm*-*-* } } */ | ||
| 157 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 158 | -/* { dg-options "-mfp16-format=ieee -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 159 | +/* { dg-options "-mfp16-format=ieee" } */ | ||
| 160 | +/* { dg-add-options arm_neon } */ | ||
| 161 | |||
| 162 | #include "arm-fp16-ops.h" | ||
| 163 | |||
| 164 | Index: gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C | ||
| 165 | =================================================================== | ||
| 166 | --- gcc-4_5-branch.orig/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C | ||
| 167 | +++ gcc-4_5-branch/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C | ||
| 168 | @@ -1,7 +1,8 @@ | ||
| 169 | /* Test various operators on __fp16 and mixed __fp16/float operands. */ | ||
| 170 | /* { dg-do compile { target arm*-*-* } } */ | ||
| 171 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 172 | -/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 173 | +/* { dg-options "-mfp16-format=ieee -ffast-math" } */ | ||
| 174 | +/* { dg-add-options arm_neon } */ | ||
| 175 | |||
| 176 | #include "arm-fp16-ops.h" | ||
| 177 | |||
| 178 | Index: gcc-4_5-branch/gcc/testsuite/g++.dg/vect/vect.exp | ||
| 179 | =================================================================== | ||
| 180 | --- gcc-4_5-branch.orig/gcc/testsuite/g++.dg/vect/vect.exp | ||
| 181 | +++ gcc-4_5-branch/gcc/testsuite/g++.dg/vect/vect.exp | ||
| 182 | @@ -112,7 +112,7 @@ if [istarget "powerpc-*paired*"] { | ||
| 183 | } elseif [istarget "ia64-*-*"] { | ||
| 184 | set dg-do-what-default run | ||
| 185 | } elseif [is-effective-target arm_neon_ok] { | ||
| 186 | - lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp" | ||
| 187 | + eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""] | ||
| 188 | if [is-effective-target arm_neon_hw] { | ||
| 189 | set dg-do-what-default run | ||
| 190 | } else { | ||
| 191 | Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c | ||
| 192 | =================================================================== | ||
| 193 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c | ||
| 194 | +++ gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c | ||
| 195 | @@ -1,7 +1,8 @@ | ||
| 196 | /* Test various operators on __fp16 and mixed __fp16/float operands. */ | ||
| 197 | /* { dg-do compile { target arm*-*-* } } */ | ||
| 198 | -/* { dg-require-effective-target arm_neon_ok } */ | ||
| 199 | -/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */ | ||
| 200 | +/* { dg-require-effective-target arm_neon_fp16_ok } */ | ||
| 201 | +/* { dg-options "-mfp16-format=ieee" } */ | ||
| 202 | +/* { dg-add-options arm_neon_fp16 } */ | ||
| 203 | |||
| 204 | #include "arm-fp16-ops.h" | ||
| 205 | |||
| 206 | Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c | ||
| 207 | =================================================================== | ||
| 208 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c | ||
| 209 | +++ gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c | ||
| 210 | @@ -1,7 +1,8 @@ | ||
| 211 | /* Test various operators on __fp16 and mixed __fp16/float operands. */ | ||
| 212 | /* { dg-do compile { target arm*-*-* } } */ | ||
| 213 | -/* { dg-require-effective-target arm_neon_ok } */ | ||
| 214 | -/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon-fp16 -mfloat-abi=softfp" } */ | ||
| 215 | +/* { dg-require-effective-target arm_neon_fp16_ok } */ | ||
| 216 | +/* { dg-options "-mfp16-format=ieee -ffast-math" } */ | ||
| 217 | +/* { dg-add-options arm_neon_fp16 } */ | ||
| 218 | |||
| 219 | #include "arm-fp16-ops.h" | ||
| 220 | |||
| 221 | Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c | ||
| 222 | =================================================================== | ||
| 223 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c | ||
| 224 | +++ gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c | ||
| 225 | @@ -1,7 +1,8 @@ | ||
| 226 | /* Test various operators on __fp16 and mixed __fp16/float operands. */ | ||
| 227 | /* { dg-do compile { target arm*-*-* } } */ | ||
| 228 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 229 | -/* { dg-options "-mfp16-format=ieee -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 230 | +/* { dg-options "-mfp16-format=ieee" } */ | ||
| 231 | +/* { dg-add-options arm_neon } */ | ||
| 232 | |||
| 233 | #include "arm-fp16-ops.h" | ||
| 234 | |||
| 235 | Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c | ||
| 236 | =================================================================== | ||
| 237 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c | ||
| 238 | +++ gcc-4_5-branch/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c | ||
| 239 | @@ -1,7 +1,8 @@ | ||
| 240 | /* Test various operators on __fp16 and mixed __fp16/float operands. */ | ||
| 241 | /* { dg-do compile { target arm*-*-* } } */ | ||
| 242 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 243 | -/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 244 | +/* { dg-options "-mfp16-format=ieee -ffast-math" } */ | ||
| 245 | +/* { dg-add-options arm_neon } */ | ||
| 246 | |||
| 247 | #include "arm-fp16-ops.h" | ||
| 248 | |||
| 249 | Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/vect/vect.exp | ||
| 250 | =================================================================== | ||
| 251 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.dg/vect/vect.exp | ||
| 252 | +++ gcc-4_5-branch/gcc/testsuite/gcc.dg/vect/vect.exp | ||
| 253 | @@ -104,7 +104,7 @@ if [istarget "powerpc-*paired*"] { | ||
| 254 | } elseif [istarget "ia64-*-*"] { | ||
| 255 | set dg-do-what-default run | ||
| 256 | } elseif [is-effective-target arm_neon_ok] { | ||
| 257 | - lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp" | ||
| 258 | + eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""] | ||
| 259 | if [is-effective-target arm_neon_hw] { | ||
| 260 | set dg-do-what-default run | ||
| 261 | } else { | ||
| 262 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c | ||
| 263 | =================================================================== | ||
| 264 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c | ||
| 265 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c | ||
| 266 | @@ -1,6 +1,7 @@ | ||
| 267 | /* { dg-do compile } */ | ||
| 268 | -/* { dg-require-effective-target arm_neon_ok } */ | ||
| 269 | -/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */ | ||
| 270 | +/* { dg-require-effective-target arm_neon_fp16_ok } */ | ||
| 271 | +/* { dg-options "-mfp16-format=ieee" } */ | ||
| 272 | +/* { dg-add-options arm_neon_fp16 } */ | ||
| 273 | |||
| 274 | /* Test generation of VFP __fp16 instructions. */ | ||
| 275 | |||
| 276 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-cond-1.c | ||
| 277 | =================================================================== | ||
| 278 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon-cond-1.c | ||
| 279 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-cond-1.c | ||
| 280 | @@ -1,6 +1,7 @@ | ||
| 281 | /* { dg-do run } */ | ||
| 282 | /* { dg-require-effective-target arm_neon_hw } */ | ||
| 283 | -/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 284 | +/* { dg-options "-O2" } */ | ||
| 285 | +/* { dg-add-options arm_neon } */ | ||
| 286 | /* Check that the arm_final_prescan_insn ccfsm code does not try to | ||
| 287 | * conditionally execute NEON instructions. */ | ||
| 288 | #include <arm_neon.h> | ||
| 289 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c | ||
| 290 | =================================================================== | ||
| 291 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c | ||
| 292 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c | ||
| 293 | @@ -1,6 +1,7 @@ | ||
| 294 | /* { dg-do compile } */ | ||
| 295 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 296 | -/* { dg-options "-O2 -mthumb -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */ | ||
| 297 | +/* { dg-options "-O2 -mthumb -march=armv7-a" } */ | ||
| 298 | +/* { dg-add-options arm_neon } */ | ||
| 299 | |||
| 300 | #include <arm_neon.h> | ||
| 301 | #include <stddef.h> | ||
| 302 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-vmla-1.c | ||
| 303 | =================================================================== | ||
| 304 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon-vmla-1.c | ||
| 305 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-vmla-1.c | ||
| 306 | @@ -1,5 +1,6 @@ | ||
| 307 | /* { dg-require-effective-target arm_neon_hw } */ | ||
| 308 | -/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ | ||
| 309 | +/* { dg-options "-O2 -ftree-vectorize" } */ | ||
| 310 | +/* { dg-add-options arm_neon } */ | ||
| 311 | /* { dg-final { scan-assembler "vmla\\.f32" } } */ | ||
| 312 | |||
| 313 | /* Verify that VMLA is used. */ | ||
| 314 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-vmls-1.c | ||
| 315 | =================================================================== | ||
| 316 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon-vmls-1.c | ||
| 317 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon-vmls-1.c | ||
| 318 | @@ -1,5 +1,6 @@ | ||
| 319 | /* { dg-require-effective-target arm_neon_hw } */ | ||
| 320 | -/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */ | ||
| 321 | +/* { dg-options "-O2 -ftree-vectorize" } */ | ||
| 322 | +/* { dg-add-options arm_neon } */ | ||
| 323 | /* { dg-final { scan-assembler "vmls\\.f32" } } */ | ||
| 324 | |||
| 325 | /* Verify that VMLS is used. */ | ||
| 326 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/polytypes.c | ||
| 327 | =================================================================== | ||
| 328 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/polytypes.c | ||
| 329 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/polytypes.c | ||
| 330 | @@ -3,7 +3,7 @@ | ||
| 331 | |||
| 332 | /* { dg-do compile } */ | ||
| 333 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 334 | -/* { dg-options "-mfpu=neon -mfloat-abi=softfp" } */ | ||
| 335 | +/* { dg-add-options arm_neon } */ | ||
| 336 | |||
| 337 | #include <arm_neon.h> | ||
| 338 | |||
| 339 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c | ||
| 340 | =================================================================== | ||
| 341 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c | ||
| 342 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c | ||
| 343 | @@ -3,7 +3,8 @@ | ||
| 344 | |||
| 345 | /* { dg-do assemble } */ | ||
| 346 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 347 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 348 | +/* { dg-options "-save-temps -O0" } */ | ||
| 349 | +/* { dg-add-options arm_neon } */ | ||
| 350 | |||
| 351 | #include "arm_neon.h" | ||
| 352 | |||
| 353 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c | ||
| 354 | =================================================================== | ||
| 355 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c | ||
| 356 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c | ||
| 357 | @@ -3,7 +3,8 @@ | ||
| 358 | |||
| 359 | /* { dg-do assemble } */ | ||
| 360 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 361 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 362 | +/* { dg-options "-save-temps -O0" } */ | ||
| 363 | +/* { dg-add-options arm_neon } */ | ||
| 364 | |||
| 365 | #include "arm_neon.h" | ||
| 366 | |||
| 367 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c | ||
| 368 | =================================================================== | ||
| 369 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c | ||
| 370 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c | ||
| 371 | @@ -3,7 +3,8 @@ | ||
| 372 | |||
| 373 | /* { dg-do assemble } */ | ||
| 374 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 375 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 376 | +/* { dg-options "-save-temps -O0" } */ | ||
| 377 | +/* { dg-add-options arm_neon } */ | ||
| 378 | |||
| 379 | #include "arm_neon.h" | ||
| 380 | |||
| 381 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c | ||
| 382 | =================================================================== | ||
| 383 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c | ||
| 384 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c | ||
| 385 | @@ -3,7 +3,8 @@ | ||
| 386 | |||
| 387 | /* { dg-do assemble } */ | ||
| 388 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 389 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 390 | +/* { dg-options "-save-temps -O0" } */ | ||
| 391 | +/* { dg-add-options arm_neon } */ | ||
| 392 | |||
| 393 | #include "arm_neon.h" | ||
| 394 | |||
| 395 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c | ||
| 396 | =================================================================== | ||
| 397 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c | ||
| 398 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c | ||
| 399 | @@ -3,7 +3,8 @@ | ||
| 400 | |||
| 401 | /* { dg-do assemble } */ | ||
| 402 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 403 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 404 | +/* { dg-options "-save-temps -O0" } */ | ||
| 405 | +/* { dg-add-options arm_neon } */ | ||
| 406 | |||
| 407 | #include "arm_neon.h" | ||
| 408 | |||
| 409 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c | ||
| 410 | =================================================================== | ||
| 411 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c | ||
| 412 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c | ||
| 413 | @@ -3,7 +3,8 @@ | ||
| 414 | |||
| 415 | /* { dg-do assemble } */ | ||
| 416 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 417 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 418 | +/* { dg-options "-save-temps -O0" } */ | ||
| 419 | +/* { dg-add-options arm_neon } */ | ||
| 420 | |||
| 421 | #include "arm_neon.h" | ||
| 422 | |||
| 423 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c | ||
| 424 | =================================================================== | ||
| 425 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c | ||
| 426 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c | ||
| 427 | @@ -3,7 +3,8 @@ | ||
| 428 | |||
| 429 | /* { dg-do assemble } */ | ||
| 430 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 431 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 432 | +/* { dg-options "-save-temps -O0" } */ | ||
| 433 | +/* { dg-add-options arm_neon } */ | ||
| 434 | |||
| 435 | #include "arm_neon.h" | ||
| 436 | |||
| 437 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c | ||
| 438 | =================================================================== | ||
| 439 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c | ||
| 440 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c | ||
| 441 | @@ -3,7 +3,8 @@ | ||
| 442 | |||
| 443 | /* { dg-do assemble } */ | ||
| 444 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 445 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 446 | +/* { dg-options "-save-temps -O0" } */ | ||
| 447 | +/* { dg-add-options arm_neon } */ | ||
| 448 | |||
| 449 | #include "arm_neon.h" | ||
| 450 | |||
| 451 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c | ||
| 452 | =================================================================== | ||
| 453 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c | ||
| 454 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c | ||
| 455 | @@ -3,7 +3,8 @@ | ||
| 456 | |||
| 457 | /* { dg-do assemble } */ | ||
| 458 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 459 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 460 | +/* { dg-options "-save-temps -O0" } */ | ||
| 461 | +/* { dg-add-options arm_neon } */ | ||
| 462 | |||
| 463 | #include "arm_neon.h" | ||
| 464 | |||
| 465 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c | ||
| 466 | =================================================================== | ||
| 467 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c | ||
| 468 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c | ||
| 469 | @@ -3,7 +3,8 @@ | ||
| 470 | |||
| 471 | /* { dg-do assemble } */ | ||
| 472 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 473 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 474 | +/* { dg-options "-save-temps -O0" } */ | ||
| 475 | +/* { dg-add-options arm_neon } */ | ||
| 476 | |||
| 477 | #include "arm_neon.h" | ||
| 478 | |||
| 479 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c | ||
| 480 | =================================================================== | ||
| 481 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c | ||
| 482 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c | ||
| 483 | @@ -3,7 +3,8 @@ | ||
| 484 | |||
| 485 | /* { dg-do assemble } */ | ||
| 486 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 487 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 488 | +/* { dg-options "-save-temps -O0" } */ | ||
| 489 | +/* { dg-add-options arm_neon } */ | ||
| 490 | |||
| 491 | #include "arm_neon.h" | ||
| 492 | |||
| 493 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c | ||
| 494 | =================================================================== | ||
| 495 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c | ||
| 496 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c | ||
| 497 | @@ -3,7 +3,8 @@ | ||
| 498 | |||
| 499 | /* { dg-do assemble } */ | ||
| 500 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 501 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 502 | +/* { dg-options "-save-temps -O0" } */ | ||
| 503 | +/* { dg-add-options arm_neon } */ | ||
| 504 | |||
| 505 | #include "arm_neon.h" | ||
| 506 | |||
| 507 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c | ||
| 508 | =================================================================== | ||
| 509 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c | ||
| 510 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c | ||
| 511 | @@ -3,7 +3,8 @@ | ||
| 512 | |||
| 513 | /* { dg-do assemble } */ | ||
| 514 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 515 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 516 | +/* { dg-options "-save-temps -O0" } */ | ||
| 517 | +/* { dg-add-options arm_neon } */ | ||
| 518 | |||
| 519 | #include "arm_neon.h" | ||
| 520 | |||
| 521 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c | ||
| 522 | =================================================================== | ||
| 523 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c | ||
| 524 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c | ||
| 525 | @@ -3,7 +3,8 @@ | ||
| 526 | |||
| 527 | /* { dg-do assemble } */ | ||
| 528 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 529 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 530 | +/* { dg-options "-save-temps -O0" } */ | ||
| 531 | +/* { dg-add-options arm_neon } */ | ||
| 532 | |||
| 533 | #include "arm_neon.h" | ||
| 534 | |||
| 535 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c | ||
| 536 | =================================================================== | ||
| 537 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c | ||
| 538 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c | ||
| 539 | @@ -3,7 +3,8 @@ | ||
| 540 | |||
| 541 | /* { dg-do assemble } */ | ||
| 542 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 543 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 544 | +/* { dg-options "-save-temps -O0" } */ | ||
| 545 | +/* { dg-add-options arm_neon } */ | ||
| 546 | |||
| 547 | #include "arm_neon.h" | ||
| 548 | |||
| 549 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c | ||
| 550 | =================================================================== | ||
| 551 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c | ||
| 552 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c | ||
| 553 | @@ -3,7 +3,8 @@ | ||
| 554 | |||
| 555 | /* { dg-do assemble } */ | ||
| 556 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 557 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 558 | +/* { dg-options "-save-temps -O0" } */ | ||
| 559 | +/* { dg-add-options arm_neon } */ | ||
| 560 | |||
| 561 | #include "arm_neon.h" | ||
| 562 | |||
| 563 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c | ||
| 564 | =================================================================== | ||
| 565 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c | ||
| 566 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c | ||
| 567 | @@ -3,7 +3,8 @@ | ||
| 568 | |||
| 569 | /* { dg-do assemble } */ | ||
| 570 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 571 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 572 | +/* { dg-options "-save-temps -O0" } */ | ||
| 573 | +/* { dg-add-options arm_neon } */ | ||
| 574 | |||
| 575 | #include "arm_neon.h" | ||
| 576 | |||
| 577 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c | ||
| 578 | =================================================================== | ||
| 579 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c | ||
| 580 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c | ||
| 581 | @@ -3,7 +3,8 @@ | ||
| 582 | |||
| 583 | /* { dg-do assemble } */ | ||
| 584 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 585 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 586 | +/* { dg-options "-save-temps -O0" } */ | ||
| 587 | +/* { dg-add-options arm_neon } */ | ||
| 588 | |||
| 589 | #include "arm_neon.h" | ||
| 590 | |||
| 591 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c | ||
| 592 | =================================================================== | ||
| 593 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c | ||
| 594 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c | ||
| 595 | @@ -3,7 +3,8 @@ | ||
| 596 | |||
| 597 | /* { dg-do assemble } */ | ||
| 598 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 599 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 600 | +/* { dg-options "-save-temps -O0" } */ | ||
| 601 | +/* { dg-add-options arm_neon } */ | ||
| 602 | |||
| 603 | #include "arm_neon.h" | ||
| 604 | |||
| 605 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c | ||
| 606 | =================================================================== | ||
| 607 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c | ||
| 608 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c | ||
| 609 | @@ -3,7 +3,8 @@ | ||
| 610 | |||
| 611 | /* { dg-do assemble } */ | ||
| 612 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 613 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 614 | +/* { dg-options "-save-temps -O0" } */ | ||
| 615 | +/* { dg-add-options arm_neon } */ | ||
| 616 | |||
| 617 | #include "arm_neon.h" | ||
| 618 | |||
| 619 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c | ||
| 620 | =================================================================== | ||
| 621 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c | ||
| 622 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c | ||
| 623 | @@ -3,7 +3,8 @@ | ||
| 624 | |||
| 625 | /* { dg-do assemble } */ | ||
| 626 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 627 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 628 | +/* { dg-options "-save-temps -O0" } */ | ||
| 629 | +/* { dg-add-options arm_neon } */ | ||
| 630 | |||
| 631 | #include "arm_neon.h" | ||
| 632 | |||
| 633 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c | ||
| 634 | =================================================================== | ||
| 635 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c | ||
| 636 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c | ||
| 637 | @@ -3,7 +3,8 @@ | ||
| 638 | |||
| 639 | /* { dg-do assemble } */ | ||
| 640 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 641 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 642 | +/* { dg-options "-save-temps -O0" } */ | ||
| 643 | +/* { dg-add-options arm_neon } */ | ||
| 644 | |||
| 645 | #include "arm_neon.h" | ||
| 646 | |||
| 647 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c | ||
| 648 | =================================================================== | ||
| 649 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c | ||
| 650 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c | ||
| 651 | @@ -3,7 +3,8 @@ | ||
| 652 | |||
| 653 | /* { dg-do assemble } */ | ||
| 654 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 655 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 656 | +/* { dg-options "-save-temps -O0" } */ | ||
| 657 | +/* { dg-add-options arm_neon } */ | ||
| 658 | |||
| 659 | #include "arm_neon.h" | ||
| 660 | |||
| 661 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c | ||
| 662 | =================================================================== | ||
| 663 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c | ||
| 664 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c | ||
| 665 | @@ -3,7 +3,8 @@ | ||
| 666 | |||
| 667 | /* { dg-do assemble } */ | ||
| 668 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 669 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 670 | +/* { dg-options "-save-temps -O0" } */ | ||
| 671 | +/* { dg-add-options arm_neon } */ | ||
| 672 | |||
| 673 | #include "arm_neon.h" | ||
| 674 | |||
| 675 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c | ||
| 676 | =================================================================== | ||
| 677 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c | ||
| 678 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c | ||
| 679 | @@ -3,7 +3,8 @@ | ||
| 680 | |||
| 681 | /* { dg-do assemble } */ | ||
| 682 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 683 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 684 | +/* { dg-options "-save-temps -O0" } */ | ||
| 685 | +/* { dg-add-options arm_neon } */ | ||
| 686 | |||
| 687 | #include "arm_neon.h" | ||
| 688 | |||
| 689 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c | ||
| 690 | =================================================================== | ||
| 691 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c | ||
| 692 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c | ||
| 693 | @@ -3,7 +3,8 @@ | ||
| 694 | |||
| 695 | /* { dg-do assemble } */ | ||
| 696 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 697 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 698 | +/* { dg-options "-save-temps -O0" } */ | ||
| 699 | +/* { dg-add-options arm_neon } */ | ||
| 700 | |||
| 701 | #include "arm_neon.h" | ||
| 702 | |||
| 703 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls16.c | ||
| 704 | =================================================================== | ||
| 705 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshls16.c | ||
| 706 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls16.c | ||
| 707 | @@ -3,7 +3,8 @@ | ||
| 708 | |||
| 709 | /* { dg-do assemble } */ | ||
| 710 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 711 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 712 | +/* { dg-options "-save-temps -O0" } */ | ||
| 713 | +/* { dg-add-options arm_neon } */ | ||
| 714 | |||
| 715 | #include "arm_neon.h" | ||
| 716 | |||
| 717 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls32.c | ||
| 718 | =================================================================== | ||
| 719 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshls32.c | ||
| 720 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls32.c | ||
| 721 | @@ -3,7 +3,8 @@ | ||
| 722 | |||
| 723 | /* { dg-do assemble } */ | ||
| 724 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 725 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 726 | +/* { dg-options "-save-temps -O0" } */ | ||
| 727 | +/* { dg-add-options arm_neon } */ | ||
| 728 | |||
| 729 | #include "arm_neon.h" | ||
| 730 | |||
| 731 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls64.c | ||
| 732 | =================================================================== | ||
| 733 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshls64.c | ||
| 734 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls64.c | ||
| 735 | @@ -3,7 +3,8 @@ | ||
| 736 | |||
| 737 | /* { dg-do assemble } */ | ||
| 738 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 739 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 740 | +/* { dg-options "-save-temps -O0" } */ | ||
| 741 | +/* { dg-add-options arm_neon } */ | ||
| 742 | |||
| 743 | #include "arm_neon.h" | ||
| 744 | |||
| 745 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls8.c | ||
| 746 | =================================================================== | ||
| 747 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshls8.c | ||
| 748 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshls8.c | ||
| 749 | @@ -3,7 +3,8 @@ | ||
| 750 | |||
| 751 | /* { dg-do assemble } */ | ||
| 752 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 753 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 754 | +/* { dg-options "-save-temps -O0" } */ | ||
| 755 | +/* { dg-add-options arm_neon } */ | ||
| 756 | |||
| 757 | #include "arm_neon.h" | ||
| 758 | |||
| 759 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c | ||
| 760 | =================================================================== | ||
| 761 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c | ||
| 762 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c | ||
| 763 | @@ -3,7 +3,8 @@ | ||
| 764 | |||
| 765 | /* { dg-do assemble } */ | ||
| 766 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 767 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 768 | +/* { dg-options "-save-temps -O0" } */ | ||
| 769 | +/* { dg-add-options arm_neon } */ | ||
| 770 | |||
| 771 | #include "arm_neon.h" | ||
| 772 | |||
| 773 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c | ||
| 774 | =================================================================== | ||
| 775 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c | ||
| 776 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c | ||
| 777 | @@ -3,7 +3,8 @@ | ||
| 778 | |||
| 779 | /* { dg-do assemble } */ | ||
| 780 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 781 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 782 | +/* { dg-options "-save-temps -O0" } */ | ||
| 783 | +/* { dg-add-options arm_neon } */ | ||
| 784 | |||
| 785 | #include "arm_neon.h" | ||
| 786 | |||
| 787 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c | ||
| 788 | =================================================================== | ||
| 789 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c | ||
| 790 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c | ||
| 791 | @@ -3,7 +3,8 @@ | ||
| 792 | |||
| 793 | /* { dg-do assemble } */ | ||
| 794 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 795 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 796 | +/* { dg-options "-save-temps -O0" } */ | ||
| 797 | +/* { dg-add-options arm_neon } */ | ||
| 798 | |||
| 799 | #include "arm_neon.h" | ||
| 800 | |||
| 801 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c | ||
| 802 | =================================================================== | ||
| 803 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c | ||
| 804 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c | ||
| 805 | @@ -3,7 +3,8 @@ | ||
| 806 | |||
| 807 | /* { dg-do assemble } */ | ||
| 808 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 809 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 810 | +/* { dg-options "-save-temps -O0" } */ | ||
| 811 | +/* { dg-add-options arm_neon } */ | ||
| 812 | |||
| 813 | #include "arm_neon.h" | ||
| 814 | |||
| 815 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c | ||
| 816 | =================================================================== | ||
| 817 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c | ||
| 818 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c | ||
| 819 | @@ -3,7 +3,8 @@ | ||
| 820 | |||
| 821 | /* { dg-do assemble } */ | ||
| 822 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 823 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 824 | +/* { dg-options "-save-temps -O0" } */ | ||
| 825 | +/* { dg-add-options arm_neon } */ | ||
| 826 | |||
| 827 | #include "arm_neon.h" | ||
| 828 | |||
| 829 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c | ||
| 830 | =================================================================== | ||
| 831 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c | ||
| 832 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c | ||
| 833 | @@ -3,7 +3,8 @@ | ||
| 834 | |||
| 835 | /* { dg-do assemble } */ | ||
| 836 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 837 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 838 | +/* { dg-options "-save-temps -O0" } */ | ||
| 839 | +/* { dg-add-options arm_neon } */ | ||
| 840 | |||
| 841 | #include "arm_neon.h" | ||
| 842 | |||
| 843 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c | ||
| 844 | =================================================================== | ||
| 845 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c | ||
| 846 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c | ||
| 847 | @@ -3,7 +3,8 @@ | ||
| 848 | |||
| 849 | /* { dg-do assemble } */ | ||
| 850 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 851 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 852 | +/* { dg-options "-save-temps -O0" } */ | ||
| 853 | +/* { dg-add-options arm_neon } */ | ||
| 854 | |||
| 855 | #include "arm_neon.h" | ||
| 856 | |||
| 857 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c | ||
| 858 | =================================================================== | ||
| 859 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c | ||
| 860 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c | ||
| 861 | @@ -3,7 +3,8 @@ | ||
| 862 | |||
| 863 | /* { dg-do assemble } */ | ||
| 864 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 865 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 866 | +/* { dg-options "-save-temps -O0" } */ | ||
| 867 | +/* { dg-add-options arm_neon } */ | ||
| 868 | |||
| 869 | #include "arm_neon.h" | ||
| 870 | |||
| 871 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c | ||
| 872 | =================================================================== | ||
| 873 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c | ||
| 874 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c | ||
| 875 | @@ -3,7 +3,8 @@ | ||
| 876 | |||
| 877 | /* { dg-do assemble } */ | ||
| 878 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 879 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 880 | +/* { dg-options "-save-temps -O0" } */ | ||
| 881 | +/* { dg-add-options arm_neon } */ | ||
| 882 | |||
| 883 | #include "arm_neon.h" | ||
| 884 | |||
| 885 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c | ||
| 886 | =================================================================== | ||
| 887 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c | ||
| 888 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c | ||
| 889 | @@ -3,7 +3,8 @@ | ||
| 890 | |||
| 891 | /* { dg-do assemble } */ | ||
| 892 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 893 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 894 | +/* { dg-options "-save-temps -O0" } */ | ||
| 895 | +/* { dg-add-options arm_neon } */ | ||
| 896 | |||
| 897 | #include "arm_neon.h" | ||
| 898 | |||
| 899 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c | ||
| 900 | =================================================================== | ||
| 901 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c | ||
| 902 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c | ||
| 903 | @@ -3,7 +3,8 @@ | ||
| 904 | |||
| 905 | /* { dg-do assemble } */ | ||
| 906 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 907 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 908 | +/* { dg-options "-save-temps -O0" } */ | ||
| 909 | +/* { dg-add-options arm_neon } */ | ||
| 910 | |||
| 911 | #include "arm_neon.h" | ||
| 912 | |||
| 913 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c | ||
| 914 | =================================================================== | ||
| 915 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c | ||
| 916 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c | ||
| 917 | @@ -3,7 +3,8 @@ | ||
| 918 | |||
| 919 | /* { dg-do assemble } */ | ||
| 920 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 921 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 922 | +/* { dg-options "-save-temps -O0" } */ | ||
| 923 | +/* { dg-add-options arm_neon } */ | ||
| 924 | |||
| 925 | #include "arm_neon.h" | ||
| 926 | |||
| 927 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c | ||
| 928 | =================================================================== | ||
| 929 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c | ||
| 930 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c | ||
| 931 | @@ -3,7 +3,8 @@ | ||
| 932 | |||
| 933 | /* { dg-do assemble } */ | ||
| 934 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 935 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 936 | +/* { dg-options "-save-temps -O0" } */ | ||
| 937 | +/* { dg-add-options arm_neon } */ | ||
| 938 | |||
| 939 | #include "arm_neon.h" | ||
| 940 | |||
| 941 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c | ||
| 942 | =================================================================== | ||
| 943 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c | ||
| 944 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c | ||
| 945 | @@ -3,7 +3,8 @@ | ||
| 946 | |||
| 947 | /* { dg-do assemble } */ | ||
| 948 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 949 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 950 | +/* { dg-options "-save-temps -O0" } */ | ||
| 951 | +/* { dg-add-options arm_neon } */ | ||
| 952 | |||
| 953 | #include "arm_neon.h" | ||
| 954 | |||
| 955 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c | ||
| 956 | =================================================================== | ||
| 957 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c | ||
| 958 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c | ||
| 959 | @@ -3,7 +3,8 @@ | ||
| 960 | |||
| 961 | /* { dg-do assemble } */ | ||
| 962 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 963 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 964 | +/* { dg-options "-save-temps -O0" } */ | ||
| 965 | +/* { dg-add-options arm_neon } */ | ||
| 966 | |||
| 967 | #include "arm_neon.h" | ||
| 968 | |||
| 969 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c | ||
| 970 | =================================================================== | ||
| 971 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c | ||
| 972 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c | ||
| 973 | @@ -3,7 +3,8 @@ | ||
| 974 | |||
| 975 | /* { dg-do assemble } */ | ||
| 976 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 977 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 978 | +/* { dg-options "-save-temps -O0" } */ | ||
| 979 | +/* { dg-add-options arm_neon } */ | ||
| 980 | |||
| 981 | #include "arm_neon.h" | ||
| 982 | |||
| 983 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c | ||
| 984 | =================================================================== | ||
| 985 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c | ||
| 986 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c | ||
| 987 | @@ -3,7 +3,8 @@ | ||
| 988 | |||
| 989 | /* { dg-do assemble } */ | ||
| 990 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 991 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 992 | +/* { dg-options "-save-temps -O0" } */ | ||
| 993 | +/* { dg-add-options arm_neon } */ | ||
| 994 | |||
| 995 | #include "arm_neon.h" | ||
| 996 | |||
| 997 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c | ||
| 998 | =================================================================== | ||
| 999 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c | ||
| 1000 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c | ||
| 1001 | @@ -3,7 +3,8 @@ | ||
| 1002 | |||
| 1003 | /* { dg-do assemble } */ | ||
| 1004 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1005 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1006 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1007 | +/* { dg-add-options arm_neon } */ | ||
| 1008 | |||
| 1009 | #include "arm_neon.h" | ||
| 1010 | |||
| 1011 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c | ||
| 1012 | =================================================================== | ||
| 1013 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c | ||
| 1014 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c | ||
| 1015 | @@ -3,7 +3,8 @@ | ||
| 1016 | |||
| 1017 | /* { dg-do assemble } */ | ||
| 1018 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1019 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1020 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1021 | +/* { dg-add-options arm_neon } */ | ||
| 1022 | |||
| 1023 | #include "arm_neon.h" | ||
| 1024 | |||
| 1025 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c | ||
| 1026 | =================================================================== | ||
| 1027 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c | ||
| 1028 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c | ||
| 1029 | @@ -3,7 +3,8 @@ | ||
| 1030 | |||
| 1031 | /* { dg-do assemble } */ | ||
| 1032 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1033 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1034 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1035 | +/* { dg-add-options arm_neon } */ | ||
| 1036 | |||
| 1037 | #include "arm_neon.h" | ||
| 1038 | |||
| 1039 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c | ||
| 1040 | =================================================================== | ||
| 1041 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c | ||
| 1042 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c | ||
| 1043 | @@ -3,7 +3,8 @@ | ||
| 1044 | |||
| 1045 | /* { dg-do assemble } */ | ||
| 1046 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1047 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1048 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1049 | +/* { dg-add-options arm_neon } */ | ||
| 1050 | |||
| 1051 | #include "arm_neon.h" | ||
| 1052 | |||
| 1053 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c | ||
| 1054 | =================================================================== | ||
| 1055 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c | ||
| 1056 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c | ||
| 1057 | @@ -3,7 +3,8 @@ | ||
| 1058 | |||
| 1059 | /* { dg-do assemble } */ | ||
| 1060 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1061 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1062 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1063 | +/* { dg-add-options arm_neon } */ | ||
| 1064 | |||
| 1065 | #include "arm_neon.h" | ||
| 1066 | |||
| 1067 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c | ||
| 1068 | =================================================================== | ||
| 1069 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c | ||
| 1070 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c | ||
| 1071 | @@ -3,7 +3,8 @@ | ||
| 1072 | |||
| 1073 | /* { dg-do assemble } */ | ||
| 1074 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1075 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1076 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1077 | +/* { dg-add-options arm_neon } */ | ||
| 1078 | |||
| 1079 | #include "arm_neon.h" | ||
| 1080 | |||
| 1081 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c | ||
| 1082 | =================================================================== | ||
| 1083 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c | ||
| 1084 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c | ||
| 1085 | @@ -3,7 +3,8 @@ | ||
| 1086 | |||
| 1087 | /* { dg-do assemble } */ | ||
| 1088 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1089 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1090 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1091 | +/* { dg-add-options arm_neon } */ | ||
| 1092 | |||
| 1093 | #include "arm_neon.h" | ||
| 1094 | |||
| 1095 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c | ||
| 1096 | =================================================================== | ||
| 1097 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c | ||
| 1098 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c | ||
| 1099 | @@ -3,7 +3,8 @@ | ||
| 1100 | |||
| 1101 | /* { dg-do assemble } */ | ||
| 1102 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1103 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1104 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1105 | +/* { dg-add-options arm_neon } */ | ||
| 1106 | |||
| 1107 | #include "arm_neon.h" | ||
| 1108 | |||
| 1109 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c | ||
| 1110 | =================================================================== | ||
| 1111 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c | ||
| 1112 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c | ||
| 1113 | @@ -3,7 +3,8 @@ | ||
| 1114 | |||
| 1115 | /* { dg-do assemble } */ | ||
| 1116 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1117 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1118 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1119 | +/* { dg-add-options arm_neon } */ | ||
| 1120 | |||
| 1121 | #include "arm_neon.h" | ||
| 1122 | |||
| 1123 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c | ||
| 1124 | =================================================================== | ||
| 1125 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c | ||
| 1126 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c | ||
| 1127 | @@ -3,7 +3,8 @@ | ||
| 1128 | |||
| 1129 | /* { dg-do assemble } */ | ||
| 1130 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1131 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1132 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1133 | +/* { dg-add-options arm_neon } */ | ||
| 1134 | |||
| 1135 | #include "arm_neon.h" | ||
| 1136 | |||
| 1137 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c | ||
| 1138 | =================================================================== | ||
| 1139 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c | ||
| 1140 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c | ||
| 1141 | @@ -3,7 +3,8 @@ | ||
| 1142 | |||
| 1143 | /* { dg-do assemble } */ | ||
| 1144 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1145 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1146 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1147 | +/* { dg-add-options arm_neon } */ | ||
| 1148 | |||
| 1149 | #include "arm_neon.h" | ||
| 1150 | |||
| 1151 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c | ||
| 1152 | =================================================================== | ||
| 1153 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c | ||
| 1154 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c | ||
| 1155 | @@ -3,7 +3,8 @@ | ||
| 1156 | |||
| 1157 | /* { dg-do assemble } */ | ||
| 1158 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1159 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1160 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1161 | +/* { dg-add-options arm_neon } */ | ||
| 1162 | |||
| 1163 | #include "arm_neon.h" | ||
| 1164 | |||
| 1165 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c | ||
| 1166 | =================================================================== | ||
| 1167 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c | ||
| 1168 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c | ||
| 1169 | @@ -3,7 +3,8 @@ | ||
| 1170 | |||
| 1171 | /* { dg-do assemble } */ | ||
| 1172 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1173 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1174 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1175 | +/* { dg-add-options arm_neon } */ | ||
| 1176 | |||
| 1177 | #include "arm_neon.h" | ||
| 1178 | |||
| 1179 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c | ||
| 1180 | =================================================================== | ||
| 1181 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c | ||
| 1182 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c | ||
| 1183 | @@ -3,7 +3,8 @@ | ||
| 1184 | |||
| 1185 | /* { dg-do assemble } */ | ||
| 1186 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1187 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1188 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1189 | +/* { dg-add-options arm_neon } */ | ||
| 1190 | |||
| 1191 | #include "arm_neon.h" | ||
| 1192 | |||
| 1193 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c | ||
| 1194 | =================================================================== | ||
| 1195 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c | ||
| 1196 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c | ||
| 1197 | @@ -3,7 +3,8 @@ | ||
| 1198 | |||
| 1199 | /* { dg-do assemble } */ | ||
| 1200 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1201 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1202 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1203 | +/* { dg-add-options arm_neon } */ | ||
| 1204 | |||
| 1205 | #include "arm_neon.h" | ||
| 1206 | |||
| 1207 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c | ||
| 1208 | =================================================================== | ||
| 1209 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c | ||
| 1210 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c | ||
| 1211 | @@ -3,7 +3,8 @@ | ||
| 1212 | |||
| 1213 | /* { dg-do assemble } */ | ||
| 1214 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1215 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1216 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1217 | +/* { dg-add-options arm_neon } */ | ||
| 1218 | |||
| 1219 | #include "arm_neon.h" | ||
| 1220 | |||
| 1221 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c | ||
| 1222 | =================================================================== | ||
| 1223 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c | ||
| 1224 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c | ||
| 1225 | @@ -3,7 +3,8 @@ | ||
| 1226 | |||
| 1227 | /* { dg-do assemble } */ | ||
| 1228 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1229 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1230 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1231 | +/* { dg-add-options arm_neon } */ | ||
| 1232 | |||
| 1233 | #include "arm_neon.h" | ||
| 1234 | |||
| 1235 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c | ||
| 1236 | =================================================================== | ||
| 1237 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c | ||
| 1238 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c | ||
| 1239 | @@ -3,7 +3,8 @@ | ||
| 1240 | |||
| 1241 | /* { dg-do assemble } */ | ||
| 1242 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1243 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1244 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1245 | +/* { dg-add-options arm_neon } */ | ||
| 1246 | |||
| 1247 | #include "arm_neon.h" | ||
| 1248 | |||
| 1249 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c | ||
| 1250 | =================================================================== | ||
| 1251 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c | ||
| 1252 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c | ||
| 1253 | @@ -3,7 +3,8 @@ | ||
| 1254 | |||
| 1255 | /* { dg-do assemble } */ | ||
| 1256 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1257 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1258 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1259 | +/* { dg-add-options arm_neon } */ | ||
| 1260 | |||
| 1261 | #include "arm_neon.h" | ||
| 1262 | |||
| 1263 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c | ||
| 1264 | =================================================================== | ||
| 1265 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c | ||
| 1266 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c | ||
| 1267 | @@ -3,7 +3,8 @@ | ||
| 1268 | |||
| 1269 | /* { dg-do assemble } */ | ||
| 1270 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1271 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1272 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1273 | +/* { dg-add-options arm_neon } */ | ||
| 1274 | |||
| 1275 | #include "arm_neon.h" | ||
| 1276 | |||
| 1277 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c | ||
| 1278 | =================================================================== | ||
| 1279 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c | ||
| 1280 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c | ||
| 1281 | @@ -3,7 +3,8 @@ | ||
| 1282 | |||
| 1283 | /* { dg-do assemble } */ | ||
| 1284 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1285 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1286 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1287 | +/* { dg-add-options arm_neon } */ | ||
| 1288 | |||
| 1289 | #include "arm_neon.h" | ||
| 1290 | |||
| 1291 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c | ||
| 1292 | =================================================================== | ||
| 1293 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c | ||
| 1294 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c | ||
| 1295 | @@ -3,7 +3,8 @@ | ||
| 1296 | |||
| 1297 | /* { dg-do assemble } */ | ||
| 1298 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1299 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1300 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1301 | +/* { dg-add-options arm_neon } */ | ||
| 1302 | |||
| 1303 | #include "arm_neon.h" | ||
| 1304 | |||
| 1305 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c | ||
| 1306 | =================================================================== | ||
| 1307 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c | ||
| 1308 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c | ||
| 1309 | @@ -3,7 +3,8 @@ | ||
| 1310 | |||
| 1311 | /* { dg-do assemble } */ | ||
| 1312 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1313 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1314 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1315 | +/* { dg-add-options arm_neon } */ | ||
| 1316 | |||
| 1317 | #include "arm_neon.h" | ||
| 1318 | |||
| 1319 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c | ||
| 1320 | =================================================================== | ||
| 1321 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c | ||
| 1322 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c | ||
| 1323 | @@ -3,7 +3,8 @@ | ||
| 1324 | |||
| 1325 | /* { dg-do assemble } */ | ||
| 1326 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1327 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1328 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1329 | +/* { dg-add-options arm_neon } */ | ||
| 1330 | |||
| 1331 | #include "arm_neon.h" | ||
| 1332 | |||
| 1333 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c | ||
| 1334 | =================================================================== | ||
| 1335 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c | ||
| 1336 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c | ||
| 1337 | @@ -3,7 +3,8 @@ | ||
| 1338 | |||
| 1339 | /* { dg-do assemble } */ | ||
| 1340 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1341 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1342 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1343 | +/* { dg-add-options arm_neon } */ | ||
| 1344 | |||
| 1345 | #include "arm_neon.h" | ||
| 1346 | |||
| 1347 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c | ||
| 1348 | =================================================================== | ||
| 1349 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c | ||
| 1350 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c | ||
| 1351 | @@ -3,7 +3,8 @@ | ||
| 1352 | |||
| 1353 | /* { dg-do assemble } */ | ||
| 1354 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1355 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1356 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1357 | +/* { dg-add-options arm_neon } */ | ||
| 1358 | |||
| 1359 | #include "arm_neon.h" | ||
| 1360 | |||
| 1361 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c | ||
| 1362 | =================================================================== | ||
| 1363 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c | ||
| 1364 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c | ||
| 1365 | @@ -3,7 +3,8 @@ | ||
| 1366 | |||
| 1367 | /* { dg-do assemble } */ | ||
| 1368 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1369 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1370 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1371 | +/* { dg-add-options arm_neon } */ | ||
| 1372 | |||
| 1373 | #include "arm_neon.h" | ||
| 1374 | |||
| 1375 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c | ||
| 1376 | =================================================================== | ||
| 1377 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c | ||
| 1378 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c | ||
| 1379 | @@ -3,7 +3,8 @@ | ||
| 1380 | |||
| 1381 | /* { dg-do assemble } */ | ||
| 1382 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1383 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1384 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1385 | +/* { dg-add-options arm_neon } */ | ||
| 1386 | |||
| 1387 | #include "arm_neon.h" | ||
| 1388 | |||
| 1389 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c | ||
| 1390 | =================================================================== | ||
| 1391 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c | ||
| 1392 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c | ||
| 1393 | @@ -3,7 +3,8 @@ | ||
| 1394 | |||
| 1395 | /* { dg-do assemble } */ | ||
| 1396 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1397 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1398 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1399 | +/* { dg-add-options arm_neon } */ | ||
| 1400 | |||
| 1401 | #include "arm_neon.h" | ||
| 1402 | |||
| 1403 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c | ||
| 1404 | =================================================================== | ||
| 1405 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c | ||
| 1406 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c | ||
| 1407 | @@ -3,7 +3,8 @@ | ||
| 1408 | |||
| 1409 | /* { dg-do assemble } */ | ||
| 1410 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1411 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1412 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1413 | +/* { dg-add-options arm_neon } */ | ||
| 1414 | |||
| 1415 | #include "arm_neon.h" | ||
| 1416 | |||
| 1417 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c | ||
| 1418 | =================================================================== | ||
| 1419 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c | ||
| 1420 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c | ||
| 1421 | @@ -3,7 +3,8 @@ | ||
| 1422 | |||
| 1423 | /* { dg-do assemble } */ | ||
| 1424 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1425 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1426 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1427 | +/* { dg-add-options arm_neon } */ | ||
| 1428 | |||
| 1429 | #include "arm_neon.h" | ||
| 1430 | |||
| 1431 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c | ||
| 1432 | =================================================================== | ||
| 1433 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c | ||
| 1434 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c | ||
| 1435 | @@ -3,7 +3,8 @@ | ||
| 1436 | |||
| 1437 | /* { dg-do assemble } */ | ||
| 1438 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1439 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1440 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1441 | +/* { dg-add-options arm_neon } */ | ||
| 1442 | |||
| 1443 | #include "arm_neon.h" | ||
| 1444 | |||
| 1445 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c | ||
| 1446 | =================================================================== | ||
| 1447 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c | ||
| 1448 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c | ||
| 1449 | @@ -3,7 +3,8 @@ | ||
| 1450 | |||
| 1451 | /* { dg-do assemble } */ | ||
| 1452 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1453 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1454 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1455 | +/* { dg-add-options arm_neon } */ | ||
| 1456 | |||
| 1457 | #include "arm_neon.h" | ||
| 1458 | |||
| 1459 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c | ||
| 1460 | =================================================================== | ||
| 1461 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c | ||
| 1462 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c | ||
| 1463 | @@ -3,7 +3,8 @@ | ||
| 1464 | |||
| 1465 | /* { dg-do assemble } */ | ||
| 1466 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1467 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1468 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1469 | +/* { dg-add-options arm_neon } */ | ||
| 1470 | |||
| 1471 | #include "arm_neon.h" | ||
| 1472 | |||
| 1473 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c | ||
| 1474 | =================================================================== | ||
| 1475 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c | ||
| 1476 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c | ||
| 1477 | @@ -3,7 +3,8 @@ | ||
| 1478 | |||
| 1479 | /* { dg-do assemble } */ | ||
| 1480 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1481 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1482 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1483 | +/* { dg-add-options arm_neon } */ | ||
| 1484 | |||
| 1485 | #include "arm_neon.h" | ||
| 1486 | |||
| 1487 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c | ||
| 1488 | =================================================================== | ||
| 1489 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c | ||
| 1490 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c | ||
| 1491 | @@ -3,7 +3,8 @@ | ||
| 1492 | |||
| 1493 | /* { dg-do assemble } */ | ||
| 1494 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1495 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1496 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1497 | +/* { dg-add-options arm_neon } */ | ||
| 1498 | |||
| 1499 | #include "arm_neon.h" | ||
| 1500 | |||
| 1501 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c | ||
| 1502 | =================================================================== | ||
| 1503 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c | ||
| 1504 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c | ||
| 1505 | @@ -3,7 +3,8 @@ | ||
| 1506 | |||
| 1507 | /* { dg-do assemble } */ | ||
| 1508 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1509 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1510 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1511 | +/* { dg-add-options arm_neon } */ | ||
| 1512 | |||
| 1513 | #include "arm_neon.h" | ||
| 1514 | |||
| 1515 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabals16.c | ||
| 1516 | =================================================================== | ||
| 1517 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabals16.c | ||
| 1518 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabals16.c | ||
| 1519 | @@ -3,7 +3,8 @@ | ||
| 1520 | |||
| 1521 | /* { dg-do assemble } */ | ||
| 1522 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1523 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1524 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1525 | +/* { dg-add-options arm_neon } */ | ||
| 1526 | |||
| 1527 | #include "arm_neon.h" | ||
| 1528 | |||
| 1529 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabals32.c | ||
| 1530 | =================================================================== | ||
| 1531 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabals32.c | ||
| 1532 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabals32.c | ||
| 1533 | @@ -3,7 +3,8 @@ | ||
| 1534 | |||
| 1535 | /* { dg-do assemble } */ | ||
| 1536 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1537 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1538 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1539 | +/* { dg-add-options arm_neon } */ | ||
| 1540 | |||
| 1541 | #include "arm_neon.h" | ||
| 1542 | |||
| 1543 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabals8.c | ||
| 1544 | =================================================================== | ||
| 1545 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabals8.c | ||
| 1546 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabals8.c | ||
| 1547 | @@ -3,7 +3,8 @@ | ||
| 1548 | |||
| 1549 | /* { dg-do assemble } */ | ||
| 1550 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1551 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1552 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1553 | +/* { dg-add-options arm_neon } */ | ||
| 1554 | |||
| 1555 | #include "arm_neon.h" | ||
| 1556 | |||
| 1557 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabalu16.c | ||
| 1558 | =================================================================== | ||
| 1559 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabalu16.c | ||
| 1560 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabalu16.c | ||
| 1561 | @@ -3,7 +3,8 @@ | ||
| 1562 | |||
| 1563 | /* { dg-do assemble } */ | ||
| 1564 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1565 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1566 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1567 | +/* { dg-add-options arm_neon } */ | ||
| 1568 | |||
| 1569 | #include "arm_neon.h" | ||
| 1570 | |||
| 1571 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabalu32.c | ||
| 1572 | =================================================================== | ||
| 1573 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabalu32.c | ||
| 1574 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabalu32.c | ||
| 1575 | @@ -3,7 +3,8 @@ | ||
| 1576 | |||
| 1577 | /* { dg-do assemble } */ | ||
| 1578 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1579 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1580 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1581 | +/* { dg-add-options arm_neon } */ | ||
| 1582 | |||
| 1583 | #include "arm_neon.h" | ||
| 1584 | |||
| 1585 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabalu8.c | ||
| 1586 | =================================================================== | ||
| 1587 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabalu8.c | ||
| 1588 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabalu8.c | ||
| 1589 | @@ -3,7 +3,8 @@ | ||
| 1590 | |||
| 1591 | /* { dg-do assemble } */ | ||
| 1592 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1593 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1594 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1595 | +/* { dg-add-options arm_neon } */ | ||
| 1596 | |||
| 1597 | #include "arm_neon.h" | ||
| 1598 | |||
| 1599 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabas16.c | ||
| 1600 | =================================================================== | ||
| 1601 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabas16.c | ||
| 1602 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabas16.c | ||
| 1603 | @@ -3,7 +3,8 @@ | ||
| 1604 | |||
| 1605 | /* { dg-do assemble } */ | ||
| 1606 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1607 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1608 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1609 | +/* { dg-add-options arm_neon } */ | ||
| 1610 | |||
| 1611 | #include "arm_neon.h" | ||
| 1612 | |||
| 1613 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabas32.c | ||
| 1614 | =================================================================== | ||
| 1615 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabas32.c | ||
| 1616 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabas32.c | ||
| 1617 | @@ -3,7 +3,8 @@ | ||
| 1618 | |||
| 1619 | /* { dg-do assemble } */ | ||
| 1620 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1621 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1622 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1623 | +/* { dg-add-options arm_neon } */ | ||
| 1624 | |||
| 1625 | #include "arm_neon.h" | ||
| 1626 | |||
| 1627 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabas8.c | ||
| 1628 | =================================================================== | ||
| 1629 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabas8.c | ||
| 1630 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabas8.c | ||
| 1631 | @@ -3,7 +3,8 @@ | ||
| 1632 | |||
| 1633 | /* { dg-do assemble } */ | ||
| 1634 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1635 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1636 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1637 | +/* { dg-add-options arm_neon } */ | ||
| 1638 | |||
| 1639 | #include "arm_neon.h" | ||
| 1640 | |||
| 1641 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabau16.c | ||
| 1642 | =================================================================== | ||
| 1643 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabau16.c | ||
| 1644 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabau16.c | ||
| 1645 | @@ -3,7 +3,8 @@ | ||
| 1646 | |||
| 1647 | /* { dg-do assemble } */ | ||
| 1648 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1649 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1650 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1651 | +/* { dg-add-options arm_neon } */ | ||
| 1652 | |||
| 1653 | #include "arm_neon.h" | ||
| 1654 | |||
| 1655 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabau32.c | ||
| 1656 | =================================================================== | ||
| 1657 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabau32.c | ||
| 1658 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabau32.c | ||
| 1659 | @@ -3,7 +3,8 @@ | ||
| 1660 | |||
| 1661 | /* { dg-do assemble } */ | ||
| 1662 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1663 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1664 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1665 | +/* { dg-add-options arm_neon } */ | ||
| 1666 | |||
| 1667 | #include "arm_neon.h" | ||
| 1668 | |||
| 1669 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabau8.c | ||
| 1670 | =================================================================== | ||
| 1671 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabau8.c | ||
| 1672 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabau8.c | ||
| 1673 | @@ -3,7 +3,8 @@ | ||
| 1674 | |||
| 1675 | /* { dg-do assemble } */ | ||
| 1676 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1677 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1678 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1679 | +/* { dg-add-options arm_neon } */ | ||
| 1680 | |||
| 1681 | #include "arm_neon.h" | ||
| 1682 | |||
| 1683 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c | ||
| 1684 | =================================================================== | ||
| 1685 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c | ||
| 1686 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c | ||
| 1687 | @@ -3,7 +3,8 @@ | ||
| 1688 | |||
| 1689 | /* { dg-do assemble } */ | ||
| 1690 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1691 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1692 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1693 | +/* { dg-add-options arm_neon } */ | ||
| 1694 | |||
| 1695 | #include "arm_neon.h" | ||
| 1696 | |||
| 1697 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c | ||
| 1698 | =================================================================== | ||
| 1699 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c | ||
| 1700 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c | ||
| 1701 | @@ -3,7 +3,8 @@ | ||
| 1702 | |||
| 1703 | /* { dg-do assemble } */ | ||
| 1704 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1705 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1706 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1707 | +/* { dg-add-options arm_neon } */ | ||
| 1708 | |||
| 1709 | #include "arm_neon.h" | ||
| 1710 | |||
| 1711 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c | ||
| 1712 | =================================================================== | ||
| 1713 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c | ||
| 1714 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c | ||
| 1715 | @@ -3,7 +3,8 @@ | ||
| 1716 | |||
| 1717 | /* { dg-do assemble } */ | ||
| 1718 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1719 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1720 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1721 | +/* { dg-add-options arm_neon } */ | ||
| 1722 | |||
| 1723 | #include "arm_neon.h" | ||
| 1724 | |||
| 1725 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c | ||
| 1726 | =================================================================== | ||
| 1727 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c | ||
| 1728 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c | ||
| 1729 | @@ -3,7 +3,8 @@ | ||
| 1730 | |||
| 1731 | /* { dg-do assemble } */ | ||
| 1732 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1733 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1734 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1735 | +/* { dg-add-options arm_neon } */ | ||
| 1736 | |||
| 1737 | #include "arm_neon.h" | ||
| 1738 | |||
| 1739 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c | ||
| 1740 | =================================================================== | ||
| 1741 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c | ||
| 1742 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c | ||
| 1743 | @@ -3,7 +3,8 @@ | ||
| 1744 | |||
| 1745 | /* { dg-do assemble } */ | ||
| 1746 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1747 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1748 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1749 | +/* { dg-add-options arm_neon } */ | ||
| 1750 | |||
| 1751 | #include "arm_neon.h" | ||
| 1752 | |||
| 1753 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c | ||
| 1754 | =================================================================== | ||
| 1755 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c | ||
| 1756 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c | ||
| 1757 | @@ -3,7 +3,8 @@ | ||
| 1758 | |||
| 1759 | /* { dg-do assemble } */ | ||
| 1760 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1761 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1762 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1763 | +/* { dg-add-options arm_neon } */ | ||
| 1764 | |||
| 1765 | #include "arm_neon.h" | ||
| 1766 | |||
| 1767 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c | ||
| 1768 | =================================================================== | ||
| 1769 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c | ||
| 1770 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c | ||
| 1771 | @@ -3,7 +3,8 @@ | ||
| 1772 | |||
| 1773 | /* { dg-do assemble } */ | ||
| 1774 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1775 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1776 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1777 | +/* { dg-add-options arm_neon } */ | ||
| 1778 | |||
| 1779 | #include "arm_neon.h" | ||
| 1780 | |||
| 1781 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdf32.c | ||
| 1782 | =================================================================== | ||
| 1783 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdf32.c | ||
| 1784 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdf32.c | ||
| 1785 | @@ -3,7 +3,8 @@ | ||
| 1786 | |||
| 1787 | /* { dg-do assemble } */ | ||
| 1788 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1789 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1790 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1791 | +/* { dg-add-options arm_neon } */ | ||
| 1792 | |||
| 1793 | #include "arm_neon.h" | ||
| 1794 | |||
| 1795 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdls16.c | ||
| 1796 | =================================================================== | ||
| 1797 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdls16.c | ||
| 1798 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdls16.c | ||
| 1799 | @@ -3,7 +3,8 @@ | ||
| 1800 | |||
| 1801 | /* { dg-do assemble } */ | ||
| 1802 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1803 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1804 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1805 | +/* { dg-add-options arm_neon } */ | ||
| 1806 | |||
| 1807 | #include "arm_neon.h" | ||
| 1808 | |||
| 1809 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdls32.c | ||
| 1810 | =================================================================== | ||
| 1811 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdls32.c | ||
| 1812 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdls32.c | ||
| 1813 | @@ -3,7 +3,8 @@ | ||
| 1814 | |||
| 1815 | /* { dg-do assemble } */ | ||
| 1816 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1817 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1818 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1819 | +/* { dg-add-options arm_neon } */ | ||
| 1820 | |||
| 1821 | #include "arm_neon.h" | ||
| 1822 | |||
| 1823 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdls8.c | ||
| 1824 | =================================================================== | ||
| 1825 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdls8.c | ||
| 1826 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdls8.c | ||
| 1827 | @@ -3,7 +3,8 @@ | ||
| 1828 | |||
| 1829 | /* { dg-do assemble } */ | ||
| 1830 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1831 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1832 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1833 | +/* { dg-add-options arm_neon } */ | ||
| 1834 | |||
| 1835 | #include "arm_neon.h" | ||
| 1836 | |||
| 1837 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c | ||
| 1838 | =================================================================== | ||
| 1839 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c | ||
| 1840 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c | ||
| 1841 | @@ -3,7 +3,8 @@ | ||
| 1842 | |||
| 1843 | /* { dg-do assemble } */ | ||
| 1844 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1845 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1846 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1847 | +/* { dg-add-options arm_neon } */ | ||
| 1848 | |||
| 1849 | #include "arm_neon.h" | ||
| 1850 | |||
| 1851 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c | ||
| 1852 | =================================================================== | ||
| 1853 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c | ||
| 1854 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c | ||
| 1855 | @@ -3,7 +3,8 @@ | ||
| 1856 | |||
| 1857 | /* { dg-do assemble } */ | ||
| 1858 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1859 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1860 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1861 | +/* { dg-add-options arm_neon } */ | ||
| 1862 | |||
| 1863 | #include "arm_neon.h" | ||
| 1864 | |||
| 1865 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c | ||
| 1866 | =================================================================== | ||
| 1867 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c | ||
| 1868 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c | ||
| 1869 | @@ -3,7 +3,8 @@ | ||
| 1870 | |||
| 1871 | /* { dg-do assemble } */ | ||
| 1872 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1873 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1874 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1875 | +/* { dg-add-options arm_neon } */ | ||
| 1876 | |||
| 1877 | #include "arm_neon.h" | ||
| 1878 | |||
| 1879 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabds16.c | ||
| 1880 | =================================================================== | ||
| 1881 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabds16.c | ||
| 1882 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabds16.c | ||
| 1883 | @@ -3,7 +3,8 @@ | ||
| 1884 | |||
| 1885 | /* { dg-do assemble } */ | ||
| 1886 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1887 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1888 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1889 | +/* { dg-add-options arm_neon } */ | ||
| 1890 | |||
| 1891 | #include "arm_neon.h" | ||
| 1892 | |||
| 1893 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabds32.c | ||
| 1894 | =================================================================== | ||
| 1895 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabds32.c | ||
| 1896 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabds32.c | ||
| 1897 | @@ -3,7 +3,8 @@ | ||
| 1898 | |||
| 1899 | /* { dg-do assemble } */ | ||
| 1900 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1901 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1902 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1903 | +/* { dg-add-options arm_neon } */ | ||
| 1904 | |||
| 1905 | #include "arm_neon.h" | ||
| 1906 | |||
| 1907 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabds8.c | ||
| 1908 | =================================================================== | ||
| 1909 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabds8.c | ||
| 1910 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabds8.c | ||
| 1911 | @@ -3,7 +3,8 @@ | ||
| 1912 | |||
| 1913 | /* { dg-do assemble } */ | ||
| 1914 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1915 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1916 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1917 | +/* { dg-add-options arm_neon } */ | ||
| 1918 | |||
| 1919 | #include "arm_neon.h" | ||
| 1920 | |||
| 1921 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdu16.c | ||
| 1922 | =================================================================== | ||
| 1923 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdu16.c | ||
| 1924 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdu16.c | ||
| 1925 | @@ -3,7 +3,8 @@ | ||
| 1926 | |||
| 1927 | /* { dg-do assemble } */ | ||
| 1928 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1929 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1930 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1931 | +/* { dg-add-options arm_neon } */ | ||
| 1932 | |||
| 1933 | #include "arm_neon.h" | ||
| 1934 | |||
| 1935 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdu32.c | ||
| 1936 | =================================================================== | ||
| 1937 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdu32.c | ||
| 1938 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdu32.c | ||
| 1939 | @@ -3,7 +3,8 @@ | ||
| 1940 | |||
| 1941 | /* { dg-do assemble } */ | ||
| 1942 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1943 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1944 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1945 | +/* { dg-add-options arm_neon } */ | ||
| 1946 | |||
| 1947 | #include "arm_neon.h" | ||
| 1948 | |||
| 1949 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdu8.c | ||
| 1950 | =================================================================== | ||
| 1951 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabdu8.c | ||
| 1952 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabdu8.c | ||
| 1953 | @@ -3,7 +3,8 @@ | ||
| 1954 | |||
| 1955 | /* { dg-do assemble } */ | ||
| 1956 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1957 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1958 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1959 | +/* { dg-add-options arm_neon } */ | ||
| 1960 | |||
| 1961 | #include "arm_neon.h" | ||
| 1962 | |||
| 1963 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c | ||
| 1964 | =================================================================== | ||
| 1965 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c | ||
| 1966 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c | ||
| 1967 | @@ -3,7 +3,8 @@ | ||
| 1968 | |||
| 1969 | /* { dg-do assemble } */ | ||
| 1970 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1971 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1972 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1973 | +/* { dg-add-options arm_neon } */ | ||
| 1974 | |||
| 1975 | #include "arm_neon.h" | ||
| 1976 | |||
| 1977 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c | ||
| 1978 | =================================================================== | ||
| 1979 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c | ||
| 1980 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c | ||
| 1981 | @@ -3,7 +3,8 @@ | ||
| 1982 | |||
| 1983 | /* { dg-do assemble } */ | ||
| 1984 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1985 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 1986 | +/* { dg-options "-save-temps -O0" } */ | ||
| 1987 | +/* { dg-add-options arm_neon } */ | ||
| 1988 | |||
| 1989 | #include "arm_neon.h" | ||
| 1990 | |||
| 1991 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c | ||
| 1992 | =================================================================== | ||
| 1993 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c | ||
| 1994 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c | ||
| 1995 | @@ -3,7 +3,8 @@ | ||
| 1996 | |||
| 1997 | /* { dg-do assemble } */ | ||
| 1998 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 1999 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2000 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2001 | +/* { dg-add-options arm_neon } */ | ||
| 2002 | |||
| 2003 | #include "arm_neon.h" | ||
| 2004 | |||
| 2005 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c | ||
| 2006 | =================================================================== | ||
| 2007 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c | ||
| 2008 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c | ||
| 2009 | @@ -3,7 +3,8 @@ | ||
| 2010 | |||
| 2011 | /* { dg-do assemble } */ | ||
| 2012 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2013 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2014 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2015 | +/* { dg-add-options arm_neon } */ | ||
| 2016 | |||
| 2017 | #include "arm_neon.h" | ||
| 2018 | |||
| 2019 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsf32.c | ||
| 2020 | =================================================================== | ||
| 2021 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabsf32.c | ||
| 2022 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabsf32.c | ||
| 2023 | @@ -3,7 +3,8 @@ | ||
| 2024 | |||
| 2025 | /* { dg-do assemble } */ | ||
| 2026 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2027 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2028 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2029 | +/* { dg-add-options arm_neon } */ | ||
| 2030 | |||
| 2031 | #include "arm_neon.h" | ||
| 2032 | |||
| 2033 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabss16.c | ||
| 2034 | =================================================================== | ||
| 2035 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabss16.c | ||
| 2036 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabss16.c | ||
| 2037 | @@ -3,7 +3,8 @@ | ||
| 2038 | |||
| 2039 | /* { dg-do assemble } */ | ||
| 2040 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2041 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2042 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2043 | +/* { dg-add-options arm_neon } */ | ||
| 2044 | |||
| 2045 | #include "arm_neon.h" | ||
| 2046 | |||
| 2047 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabss32.c | ||
| 2048 | =================================================================== | ||
| 2049 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabss32.c | ||
| 2050 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabss32.c | ||
| 2051 | @@ -3,7 +3,8 @@ | ||
| 2052 | |||
| 2053 | /* { dg-do assemble } */ | ||
| 2054 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2055 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2056 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2057 | +/* { dg-add-options arm_neon } */ | ||
| 2058 | |||
| 2059 | #include "arm_neon.h" | ||
| 2060 | |||
| 2061 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabss8.c | ||
| 2062 | =================================================================== | ||
| 2063 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vabss8.c | ||
| 2064 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vabss8.c | ||
| 2065 | @@ -3,7 +3,8 @@ | ||
| 2066 | |||
| 2067 | /* { dg-do assemble } */ | ||
| 2068 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2069 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2070 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2071 | +/* { dg-add-options arm_neon } */ | ||
| 2072 | |||
| 2073 | #include "arm_neon.h" | ||
| 2074 | |||
| 2075 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c | ||
| 2076 | =================================================================== | ||
| 2077 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c | ||
| 2078 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c | ||
| 2079 | @@ -3,7 +3,8 @@ | ||
| 2080 | |||
| 2081 | /* { dg-do assemble } */ | ||
| 2082 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2083 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2084 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2085 | +/* { dg-add-options arm_neon } */ | ||
| 2086 | |||
| 2087 | #include "arm_neon.h" | ||
| 2088 | |||
| 2089 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c | ||
| 2090 | =================================================================== | ||
| 2091 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c | ||
| 2092 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c | ||
| 2093 | @@ -3,7 +3,8 @@ | ||
| 2094 | |||
| 2095 | /* { dg-do assemble } */ | ||
| 2096 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2097 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2098 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2099 | +/* { dg-add-options arm_neon } */ | ||
| 2100 | |||
| 2101 | #include "arm_neon.h" | ||
| 2102 | |||
| 2103 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c | ||
| 2104 | =================================================================== | ||
| 2105 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c | ||
| 2106 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c | ||
| 2107 | @@ -3,7 +3,8 @@ | ||
| 2108 | |||
| 2109 | /* { dg-do assemble } */ | ||
| 2110 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2111 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2112 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2113 | +/* { dg-add-options arm_neon } */ | ||
| 2114 | |||
| 2115 | #include "arm_neon.h" | ||
| 2116 | |||
| 2117 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c | ||
| 2118 | =================================================================== | ||
| 2119 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c | ||
| 2120 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c | ||
| 2121 | @@ -3,7 +3,8 @@ | ||
| 2122 | |||
| 2123 | /* { dg-do assemble } */ | ||
| 2124 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2125 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2126 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2127 | +/* { dg-add-options arm_neon } */ | ||
| 2128 | |||
| 2129 | #include "arm_neon.h" | ||
| 2130 | |||
| 2131 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c | ||
| 2132 | =================================================================== | ||
| 2133 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c | ||
| 2134 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c | ||
| 2135 | @@ -3,7 +3,8 @@ | ||
| 2136 | |||
| 2137 | /* { dg-do assemble } */ | ||
| 2138 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2139 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2140 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2141 | +/* { dg-add-options arm_neon } */ | ||
| 2142 | |||
| 2143 | #include "arm_neon.h" | ||
| 2144 | |||
| 2145 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c | ||
| 2146 | =================================================================== | ||
| 2147 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c | ||
| 2148 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c | ||
| 2149 | @@ -3,7 +3,8 @@ | ||
| 2150 | |||
| 2151 | /* { dg-do assemble } */ | ||
| 2152 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2153 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2154 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2155 | +/* { dg-add-options arm_neon } */ | ||
| 2156 | |||
| 2157 | #include "arm_neon.h" | ||
| 2158 | |||
| 2159 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c | ||
| 2160 | =================================================================== | ||
| 2161 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c | ||
| 2162 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c | ||
| 2163 | @@ -3,7 +3,8 @@ | ||
| 2164 | |||
| 2165 | /* { dg-do assemble } */ | ||
| 2166 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2167 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2168 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2169 | +/* { dg-add-options arm_neon } */ | ||
| 2170 | |||
| 2171 | #include "arm_neon.h" | ||
| 2172 | |||
| 2173 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c | ||
| 2174 | =================================================================== | ||
| 2175 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c | ||
| 2176 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c | ||
| 2177 | @@ -3,7 +3,8 @@ | ||
| 2178 | |||
| 2179 | /* { dg-do assemble } */ | ||
| 2180 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2181 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2182 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2183 | +/* { dg-add-options arm_neon } */ | ||
| 2184 | |||
| 2185 | #include "arm_neon.h" | ||
| 2186 | |||
| 2187 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c | ||
| 2188 | =================================================================== | ||
| 2189 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c | ||
| 2190 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c | ||
| 2191 | @@ -3,7 +3,8 @@ | ||
| 2192 | |||
| 2193 | /* { dg-do assemble } */ | ||
| 2194 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2195 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2196 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2197 | +/* { dg-add-options arm_neon } */ | ||
| 2198 | |||
| 2199 | #include "arm_neon.h" | ||
| 2200 | |||
| 2201 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddf32.c | ||
| 2202 | =================================================================== | ||
| 2203 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddf32.c | ||
| 2204 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddf32.c | ||
| 2205 | @@ -3,7 +3,8 @@ | ||
| 2206 | |||
| 2207 | /* { dg-do assemble } */ | ||
| 2208 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2209 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2210 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2211 | +/* { dg-add-options arm_neon } */ | ||
| 2212 | |||
| 2213 | #include "arm_neon.h" | ||
| 2214 | |||
| 2215 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c | ||
| 2216 | =================================================================== | ||
| 2217 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c | ||
| 2218 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c | ||
| 2219 | @@ -3,7 +3,8 @@ | ||
| 2220 | |||
| 2221 | /* { dg-do assemble } */ | ||
| 2222 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2223 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2224 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2225 | +/* { dg-add-options arm_neon } */ | ||
| 2226 | |||
| 2227 | #include "arm_neon.h" | ||
| 2228 | |||
| 2229 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c | ||
| 2230 | =================================================================== | ||
| 2231 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c | ||
| 2232 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c | ||
| 2233 | @@ -3,7 +3,8 @@ | ||
| 2234 | |||
| 2235 | /* { dg-do assemble } */ | ||
| 2236 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2237 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2238 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2239 | +/* { dg-add-options arm_neon } */ | ||
| 2240 | |||
| 2241 | #include "arm_neon.h" | ||
| 2242 | |||
| 2243 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c | ||
| 2244 | =================================================================== | ||
| 2245 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c | ||
| 2246 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c | ||
| 2247 | @@ -3,7 +3,8 @@ | ||
| 2248 | |||
| 2249 | /* { dg-do assemble } */ | ||
| 2250 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2251 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2252 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2253 | +/* { dg-add-options arm_neon } */ | ||
| 2254 | |||
| 2255 | #include "arm_neon.h" | ||
| 2256 | |||
| 2257 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c | ||
| 2258 | =================================================================== | ||
| 2259 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c | ||
| 2260 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c | ||
| 2261 | @@ -3,7 +3,8 @@ | ||
| 2262 | |||
| 2263 | /* { dg-do assemble } */ | ||
| 2264 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2265 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2266 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2267 | +/* { dg-add-options arm_neon } */ | ||
| 2268 | |||
| 2269 | #include "arm_neon.h" | ||
| 2270 | |||
| 2271 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c | ||
| 2272 | =================================================================== | ||
| 2273 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c | ||
| 2274 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c | ||
| 2275 | @@ -3,7 +3,8 @@ | ||
| 2276 | |||
| 2277 | /* { dg-do assemble } */ | ||
| 2278 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2279 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2280 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2281 | +/* { dg-add-options arm_neon } */ | ||
| 2282 | |||
| 2283 | #include "arm_neon.h" | ||
| 2284 | |||
| 2285 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c | ||
| 2286 | =================================================================== | ||
| 2287 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c | ||
| 2288 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c | ||
| 2289 | @@ -3,7 +3,8 @@ | ||
| 2290 | |||
| 2291 | /* { dg-do assemble } */ | ||
| 2292 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2293 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2294 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2295 | +/* { dg-add-options arm_neon } */ | ||
| 2296 | |||
| 2297 | #include "arm_neon.h" | ||
| 2298 | |||
| 2299 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddls16.c | ||
| 2300 | =================================================================== | ||
| 2301 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddls16.c | ||
| 2302 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddls16.c | ||
| 2303 | @@ -3,7 +3,8 @@ | ||
| 2304 | |||
| 2305 | /* { dg-do assemble } */ | ||
| 2306 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2307 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2308 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2309 | +/* { dg-add-options arm_neon } */ | ||
| 2310 | |||
| 2311 | #include "arm_neon.h" | ||
| 2312 | |||
| 2313 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddls32.c | ||
| 2314 | =================================================================== | ||
| 2315 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddls32.c | ||
| 2316 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddls32.c | ||
| 2317 | @@ -3,7 +3,8 @@ | ||
| 2318 | |||
| 2319 | /* { dg-do assemble } */ | ||
| 2320 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2321 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2322 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2323 | +/* { dg-add-options arm_neon } */ | ||
| 2324 | |||
| 2325 | #include "arm_neon.h" | ||
| 2326 | |||
| 2327 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddls8.c | ||
| 2328 | =================================================================== | ||
| 2329 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddls8.c | ||
| 2330 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddls8.c | ||
| 2331 | @@ -3,7 +3,8 @@ | ||
| 2332 | |||
| 2333 | /* { dg-do assemble } */ | ||
| 2334 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2335 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2336 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2337 | +/* { dg-add-options arm_neon } */ | ||
| 2338 | |||
| 2339 | #include "arm_neon.h" | ||
| 2340 | |||
| 2341 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c | ||
| 2342 | =================================================================== | ||
| 2343 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c | ||
| 2344 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c | ||
| 2345 | @@ -3,7 +3,8 @@ | ||
| 2346 | |||
| 2347 | /* { dg-do assemble } */ | ||
| 2348 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2349 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2350 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2351 | +/* { dg-add-options arm_neon } */ | ||
| 2352 | |||
| 2353 | #include "arm_neon.h" | ||
| 2354 | |||
| 2355 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c | ||
| 2356 | =================================================================== | ||
| 2357 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c | ||
| 2358 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c | ||
| 2359 | @@ -3,7 +3,8 @@ | ||
| 2360 | |||
| 2361 | /* { dg-do assemble } */ | ||
| 2362 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2363 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2364 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2365 | +/* { dg-add-options arm_neon } */ | ||
| 2366 | |||
| 2367 | #include "arm_neon.h" | ||
| 2368 | |||
| 2369 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c | ||
| 2370 | =================================================================== | ||
| 2371 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c | ||
| 2372 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c | ||
| 2373 | @@ -3,7 +3,8 @@ | ||
| 2374 | |||
| 2375 | /* { dg-do assemble } */ | ||
| 2376 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2377 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2378 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2379 | +/* { dg-add-options arm_neon } */ | ||
| 2380 | |||
| 2381 | #include "arm_neon.h" | ||
| 2382 | |||
| 2383 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds16.c | ||
| 2384 | =================================================================== | ||
| 2385 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vadds16.c | ||
| 2386 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds16.c | ||
| 2387 | @@ -3,7 +3,8 @@ | ||
| 2388 | |||
| 2389 | /* { dg-do assemble } */ | ||
| 2390 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2391 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2392 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2393 | +/* { dg-add-options arm_neon } */ | ||
| 2394 | |||
| 2395 | #include "arm_neon.h" | ||
| 2396 | |||
| 2397 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds32.c | ||
| 2398 | =================================================================== | ||
| 2399 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vadds32.c | ||
| 2400 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds32.c | ||
| 2401 | @@ -3,7 +3,8 @@ | ||
| 2402 | |||
| 2403 | /* { dg-do assemble } */ | ||
| 2404 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2405 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2406 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2407 | +/* { dg-add-options arm_neon } */ | ||
| 2408 | |||
| 2409 | #include "arm_neon.h" | ||
| 2410 | |||
| 2411 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds64.c | ||
| 2412 | =================================================================== | ||
| 2413 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vadds64.c | ||
| 2414 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds64.c | ||
| 2415 | @@ -3,7 +3,8 @@ | ||
| 2416 | |||
| 2417 | /* { dg-do assemble } */ | ||
| 2418 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2419 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2420 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2421 | +/* { dg-add-options arm_neon } */ | ||
| 2422 | |||
| 2423 | #include "arm_neon.h" | ||
| 2424 | |||
| 2425 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds8.c | ||
| 2426 | =================================================================== | ||
| 2427 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vadds8.c | ||
| 2428 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vadds8.c | ||
| 2429 | @@ -3,7 +3,8 @@ | ||
| 2430 | |||
| 2431 | /* { dg-do assemble } */ | ||
| 2432 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2433 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2434 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2435 | +/* { dg-add-options arm_neon } */ | ||
| 2436 | |||
| 2437 | #include "arm_neon.h" | ||
| 2438 | |||
| 2439 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu16.c | ||
| 2440 | =================================================================== | ||
| 2441 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddu16.c | ||
| 2442 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu16.c | ||
| 2443 | @@ -3,7 +3,8 @@ | ||
| 2444 | |||
| 2445 | /* { dg-do assemble } */ | ||
| 2446 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2447 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2448 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2449 | +/* { dg-add-options arm_neon } */ | ||
| 2450 | |||
| 2451 | #include "arm_neon.h" | ||
| 2452 | |||
| 2453 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu32.c | ||
| 2454 | =================================================================== | ||
| 2455 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddu32.c | ||
| 2456 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu32.c | ||
| 2457 | @@ -3,7 +3,8 @@ | ||
| 2458 | |||
| 2459 | /* { dg-do assemble } */ | ||
| 2460 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2461 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2462 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2463 | +/* { dg-add-options arm_neon } */ | ||
| 2464 | |||
| 2465 | #include "arm_neon.h" | ||
| 2466 | |||
| 2467 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu64.c | ||
| 2468 | =================================================================== | ||
| 2469 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddu64.c | ||
| 2470 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu64.c | ||
| 2471 | @@ -3,7 +3,8 @@ | ||
| 2472 | |||
| 2473 | /* { dg-do assemble } */ | ||
| 2474 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2475 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2476 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2477 | +/* { dg-add-options arm_neon } */ | ||
| 2478 | |||
| 2479 | #include "arm_neon.h" | ||
| 2480 | |||
| 2481 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu8.c | ||
| 2482 | =================================================================== | ||
| 2483 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddu8.c | ||
| 2484 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddu8.c | ||
| 2485 | @@ -3,7 +3,8 @@ | ||
| 2486 | |||
| 2487 | /* { dg-do assemble } */ | ||
| 2488 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2489 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2490 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2491 | +/* { dg-add-options arm_neon } */ | ||
| 2492 | |||
| 2493 | #include "arm_neon.h" | ||
| 2494 | |||
| 2495 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddws16.c | ||
| 2496 | =================================================================== | ||
| 2497 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddws16.c | ||
| 2498 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddws16.c | ||
| 2499 | @@ -3,7 +3,8 @@ | ||
| 2500 | |||
| 2501 | /* { dg-do assemble } */ | ||
| 2502 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2503 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2504 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2505 | +/* { dg-add-options arm_neon } */ | ||
| 2506 | |||
| 2507 | #include "arm_neon.h" | ||
| 2508 | |||
| 2509 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddws32.c | ||
| 2510 | =================================================================== | ||
| 2511 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddws32.c | ||
| 2512 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddws32.c | ||
| 2513 | @@ -3,7 +3,8 @@ | ||
| 2514 | |||
| 2515 | /* { dg-do assemble } */ | ||
| 2516 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2517 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2518 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2519 | +/* { dg-add-options arm_neon } */ | ||
| 2520 | |||
| 2521 | #include "arm_neon.h" | ||
| 2522 | |||
| 2523 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddws8.c | ||
| 2524 | =================================================================== | ||
| 2525 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddws8.c | ||
| 2526 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddws8.c | ||
| 2527 | @@ -3,7 +3,8 @@ | ||
| 2528 | |||
| 2529 | /* { dg-do assemble } */ | ||
| 2530 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2531 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2532 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2533 | +/* { dg-add-options arm_neon } */ | ||
| 2534 | |||
| 2535 | #include "arm_neon.h" | ||
| 2536 | |||
| 2537 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c | ||
| 2538 | =================================================================== | ||
| 2539 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c | ||
| 2540 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c | ||
| 2541 | @@ -3,7 +3,8 @@ | ||
| 2542 | |||
| 2543 | /* { dg-do assemble } */ | ||
| 2544 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2545 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2546 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2547 | +/* { dg-add-options arm_neon } */ | ||
| 2548 | |||
| 2549 | #include "arm_neon.h" | ||
| 2550 | |||
| 2551 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c | ||
| 2552 | =================================================================== | ||
| 2553 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c | ||
| 2554 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c | ||
| 2555 | @@ -3,7 +3,8 @@ | ||
| 2556 | |||
| 2557 | /* { dg-do assemble } */ | ||
| 2558 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2559 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2560 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2561 | +/* { dg-add-options arm_neon } */ | ||
| 2562 | |||
| 2563 | #include "arm_neon.h" | ||
| 2564 | |||
| 2565 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c | ||
| 2566 | =================================================================== | ||
| 2567 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c | ||
| 2568 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c | ||
| 2569 | @@ -3,7 +3,8 @@ | ||
| 2570 | |||
| 2571 | /* { dg-do assemble } */ | ||
| 2572 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2573 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2574 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2575 | +/* { dg-add-options arm_neon } */ | ||
| 2576 | |||
| 2577 | #include "arm_neon.h" | ||
| 2578 | |||
| 2579 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs16.c | ||
| 2580 | =================================================================== | ||
| 2581 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQs16.c | ||
| 2582 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs16.c | ||
| 2583 | @@ -3,7 +3,8 @@ | ||
| 2584 | |||
| 2585 | /* { dg-do assemble } */ | ||
| 2586 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2587 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2588 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2589 | +/* { dg-add-options arm_neon } */ | ||
| 2590 | |||
| 2591 | #include "arm_neon.h" | ||
| 2592 | |||
| 2593 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs32.c | ||
| 2594 | =================================================================== | ||
| 2595 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQs32.c | ||
| 2596 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs32.c | ||
| 2597 | @@ -3,7 +3,8 @@ | ||
| 2598 | |||
| 2599 | /* { dg-do assemble } */ | ||
| 2600 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2601 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2602 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2603 | +/* { dg-add-options arm_neon } */ | ||
| 2604 | |||
| 2605 | #include "arm_neon.h" | ||
| 2606 | |||
| 2607 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs64.c | ||
| 2608 | =================================================================== | ||
| 2609 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQs64.c | ||
| 2610 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs64.c | ||
| 2611 | @@ -3,7 +3,8 @@ | ||
| 2612 | |||
| 2613 | /* { dg-do assemble } */ | ||
| 2614 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2615 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2616 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2617 | +/* { dg-add-options arm_neon } */ | ||
| 2618 | |||
| 2619 | #include "arm_neon.h" | ||
| 2620 | |||
| 2621 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs8.c | ||
| 2622 | =================================================================== | ||
| 2623 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQs8.c | ||
| 2624 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQs8.c | ||
| 2625 | @@ -3,7 +3,8 @@ | ||
| 2626 | |||
| 2627 | /* { dg-do assemble } */ | ||
| 2628 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2629 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2630 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2631 | +/* { dg-add-options arm_neon } */ | ||
| 2632 | |||
| 2633 | #include "arm_neon.h" | ||
| 2634 | |||
| 2635 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu16.c | ||
| 2636 | =================================================================== | ||
| 2637 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQu16.c | ||
| 2638 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu16.c | ||
| 2639 | @@ -3,7 +3,8 @@ | ||
| 2640 | |||
| 2641 | /* { dg-do assemble } */ | ||
| 2642 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2643 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2644 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2645 | +/* { dg-add-options arm_neon } */ | ||
| 2646 | |||
| 2647 | #include "arm_neon.h" | ||
| 2648 | |||
| 2649 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu32.c | ||
| 2650 | =================================================================== | ||
| 2651 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQu32.c | ||
| 2652 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu32.c | ||
| 2653 | @@ -3,7 +3,8 @@ | ||
| 2654 | |||
| 2655 | /* { dg-do assemble } */ | ||
| 2656 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2657 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2658 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2659 | +/* { dg-add-options arm_neon } */ | ||
| 2660 | |||
| 2661 | #include "arm_neon.h" | ||
| 2662 | |||
| 2663 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu64.c | ||
| 2664 | =================================================================== | ||
| 2665 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQu64.c | ||
| 2666 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu64.c | ||
| 2667 | @@ -3,7 +3,8 @@ | ||
| 2668 | |||
| 2669 | /* { dg-do assemble } */ | ||
| 2670 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2671 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2672 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2673 | +/* { dg-add-options arm_neon } */ | ||
| 2674 | |||
| 2675 | #include "arm_neon.h" | ||
| 2676 | |||
| 2677 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu8.c | ||
| 2678 | =================================================================== | ||
| 2679 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandQu8.c | ||
| 2680 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandQu8.c | ||
| 2681 | @@ -3,7 +3,8 @@ | ||
| 2682 | |||
| 2683 | /* { dg-do assemble } */ | ||
| 2684 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2685 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2686 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2687 | +/* { dg-add-options arm_neon } */ | ||
| 2688 | |||
| 2689 | #include "arm_neon.h" | ||
| 2690 | |||
| 2691 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands16.c | ||
| 2692 | =================================================================== | ||
| 2693 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vands16.c | ||
| 2694 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands16.c | ||
| 2695 | @@ -3,7 +3,8 @@ | ||
| 2696 | |||
| 2697 | /* { dg-do assemble } */ | ||
| 2698 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2699 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2700 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2701 | +/* { dg-add-options arm_neon } */ | ||
| 2702 | |||
| 2703 | #include "arm_neon.h" | ||
| 2704 | |||
| 2705 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands32.c | ||
| 2706 | =================================================================== | ||
| 2707 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vands32.c | ||
| 2708 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands32.c | ||
| 2709 | @@ -3,7 +3,8 @@ | ||
| 2710 | |||
| 2711 | /* { dg-do assemble } */ | ||
| 2712 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2713 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2714 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2715 | +/* { dg-add-options arm_neon } */ | ||
| 2716 | |||
| 2717 | #include "arm_neon.h" | ||
| 2718 | |||
| 2719 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands64.c | ||
| 2720 | =================================================================== | ||
| 2721 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vands64.c | ||
| 2722 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands64.c | ||
| 2723 | @@ -3,7 +3,8 @@ | ||
| 2724 | |||
| 2725 | /* { dg-do assemble } */ | ||
| 2726 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2727 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2728 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2729 | +/* { dg-add-options arm_neon } */ | ||
| 2730 | |||
| 2731 | #include "arm_neon.h" | ||
| 2732 | |||
| 2733 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands8.c | ||
| 2734 | =================================================================== | ||
| 2735 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vands8.c | ||
| 2736 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vands8.c | ||
| 2737 | @@ -3,7 +3,8 @@ | ||
| 2738 | |||
| 2739 | /* { dg-do assemble } */ | ||
| 2740 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2741 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2742 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2743 | +/* { dg-add-options arm_neon } */ | ||
| 2744 | |||
| 2745 | #include "arm_neon.h" | ||
| 2746 | |||
| 2747 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu16.c | ||
| 2748 | =================================================================== | ||
| 2749 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandu16.c | ||
| 2750 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu16.c | ||
| 2751 | @@ -3,7 +3,8 @@ | ||
| 2752 | |||
| 2753 | /* { dg-do assemble } */ | ||
| 2754 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2755 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2756 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2757 | +/* { dg-add-options arm_neon } */ | ||
| 2758 | |||
| 2759 | #include "arm_neon.h" | ||
| 2760 | |||
| 2761 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu32.c | ||
| 2762 | =================================================================== | ||
| 2763 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandu32.c | ||
| 2764 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu32.c | ||
| 2765 | @@ -3,7 +3,8 @@ | ||
| 2766 | |||
| 2767 | /* { dg-do assemble } */ | ||
| 2768 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2769 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2770 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2771 | +/* { dg-add-options arm_neon } */ | ||
| 2772 | |||
| 2773 | #include "arm_neon.h" | ||
| 2774 | |||
| 2775 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu64.c | ||
| 2776 | =================================================================== | ||
| 2777 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandu64.c | ||
| 2778 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu64.c | ||
| 2779 | @@ -3,7 +3,8 @@ | ||
| 2780 | |||
| 2781 | /* { dg-do assemble } */ | ||
| 2782 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2783 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2784 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2785 | +/* { dg-add-options arm_neon } */ | ||
| 2786 | |||
| 2787 | #include "arm_neon.h" | ||
| 2788 | |||
| 2789 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu8.c | ||
| 2790 | =================================================================== | ||
| 2791 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vandu8.c | ||
| 2792 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vandu8.c | ||
| 2793 | @@ -3,7 +3,8 @@ | ||
| 2794 | |||
| 2795 | /* { dg-do assemble } */ | ||
| 2796 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2797 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2798 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2799 | +/* { dg-add-options arm_neon } */ | ||
| 2800 | |||
| 2801 | #include "arm_neon.h" | ||
| 2802 | |||
| 2803 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c | ||
| 2804 | =================================================================== | ||
| 2805 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c | ||
| 2806 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c | ||
| 2807 | @@ -3,7 +3,8 @@ | ||
| 2808 | |||
| 2809 | /* { dg-do assemble } */ | ||
| 2810 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2811 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2812 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2813 | +/* { dg-add-options arm_neon } */ | ||
| 2814 | |||
| 2815 | #include "arm_neon.h" | ||
| 2816 | |||
| 2817 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c | ||
| 2818 | =================================================================== | ||
| 2819 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c | ||
| 2820 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c | ||
| 2821 | @@ -3,7 +3,8 @@ | ||
| 2822 | |||
| 2823 | /* { dg-do assemble } */ | ||
| 2824 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2825 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2826 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2827 | +/* { dg-add-options arm_neon } */ | ||
| 2828 | |||
| 2829 | #include "arm_neon.h" | ||
| 2830 | |||
| 2831 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c | ||
| 2832 | =================================================================== | ||
| 2833 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c | ||
| 2834 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c | ||
| 2835 | @@ -3,7 +3,8 @@ | ||
| 2836 | |||
| 2837 | /* { dg-do assemble } */ | ||
| 2838 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2839 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2840 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2841 | +/* { dg-add-options arm_neon } */ | ||
| 2842 | |||
| 2843 | #include "arm_neon.h" | ||
| 2844 | |||
| 2845 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c | ||
| 2846 | =================================================================== | ||
| 2847 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c | ||
| 2848 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c | ||
| 2849 | @@ -3,7 +3,8 @@ | ||
| 2850 | |||
| 2851 | /* { dg-do assemble } */ | ||
| 2852 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2853 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2854 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2855 | +/* { dg-add-options arm_neon } */ | ||
| 2856 | |||
| 2857 | #include "arm_neon.h" | ||
| 2858 | |||
| 2859 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c | ||
| 2860 | =================================================================== | ||
| 2861 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c | ||
| 2862 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c | ||
| 2863 | @@ -3,7 +3,8 @@ | ||
| 2864 | |||
| 2865 | /* { dg-do assemble } */ | ||
| 2866 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2867 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2868 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2869 | +/* { dg-add-options arm_neon } */ | ||
| 2870 | |||
| 2871 | #include "arm_neon.h" | ||
| 2872 | |||
| 2873 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c | ||
| 2874 | =================================================================== | ||
| 2875 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c | ||
| 2876 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c | ||
| 2877 | @@ -3,7 +3,8 @@ | ||
| 2878 | |||
| 2879 | /* { dg-do assemble } */ | ||
| 2880 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2881 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2882 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2883 | +/* { dg-add-options arm_neon } */ | ||
| 2884 | |||
| 2885 | #include "arm_neon.h" | ||
| 2886 | |||
| 2887 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c | ||
| 2888 | =================================================================== | ||
| 2889 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c | ||
| 2890 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c | ||
| 2891 | @@ -3,7 +3,8 @@ | ||
| 2892 | |||
| 2893 | /* { dg-do assemble } */ | ||
| 2894 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2895 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2896 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2897 | +/* { dg-add-options arm_neon } */ | ||
| 2898 | |||
| 2899 | #include "arm_neon.h" | ||
| 2900 | |||
| 2901 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c | ||
| 2902 | =================================================================== | ||
| 2903 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c | ||
| 2904 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c | ||
| 2905 | @@ -3,7 +3,8 @@ | ||
| 2906 | |||
| 2907 | /* { dg-do assemble } */ | ||
| 2908 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2909 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2910 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2911 | +/* { dg-add-options arm_neon } */ | ||
| 2912 | |||
| 2913 | #include "arm_neon.h" | ||
| 2914 | |||
| 2915 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics16.c | ||
| 2916 | =================================================================== | ||
| 2917 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbics16.c | ||
| 2918 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics16.c | ||
| 2919 | @@ -3,7 +3,8 @@ | ||
| 2920 | |||
| 2921 | /* { dg-do assemble } */ | ||
| 2922 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2923 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2924 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2925 | +/* { dg-add-options arm_neon } */ | ||
| 2926 | |||
| 2927 | #include "arm_neon.h" | ||
| 2928 | |||
| 2929 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics32.c | ||
| 2930 | =================================================================== | ||
| 2931 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbics32.c | ||
| 2932 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics32.c | ||
| 2933 | @@ -3,7 +3,8 @@ | ||
| 2934 | |||
| 2935 | /* { dg-do assemble } */ | ||
| 2936 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2937 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2938 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2939 | +/* { dg-add-options arm_neon } */ | ||
| 2940 | |||
| 2941 | #include "arm_neon.h" | ||
| 2942 | |||
| 2943 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics64.c | ||
| 2944 | =================================================================== | ||
| 2945 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbics64.c | ||
| 2946 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics64.c | ||
| 2947 | @@ -3,7 +3,8 @@ | ||
| 2948 | |||
| 2949 | /* { dg-do assemble } */ | ||
| 2950 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2951 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2952 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2953 | +/* { dg-add-options arm_neon } */ | ||
| 2954 | |||
| 2955 | #include "arm_neon.h" | ||
| 2956 | |||
| 2957 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics8.c | ||
| 2958 | =================================================================== | ||
| 2959 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbics8.c | ||
| 2960 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbics8.c | ||
| 2961 | @@ -3,7 +3,8 @@ | ||
| 2962 | |||
| 2963 | /* { dg-do assemble } */ | ||
| 2964 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2965 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2966 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2967 | +/* { dg-add-options arm_neon } */ | ||
| 2968 | |||
| 2969 | #include "arm_neon.h" | ||
| 2970 | |||
| 2971 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu16.c | ||
| 2972 | =================================================================== | ||
| 2973 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicu16.c | ||
| 2974 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu16.c | ||
| 2975 | @@ -3,7 +3,8 @@ | ||
| 2976 | |||
| 2977 | /* { dg-do assemble } */ | ||
| 2978 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2979 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2980 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2981 | +/* { dg-add-options arm_neon } */ | ||
| 2982 | |||
| 2983 | #include "arm_neon.h" | ||
| 2984 | |||
| 2985 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu32.c | ||
| 2986 | =================================================================== | ||
| 2987 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicu32.c | ||
| 2988 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu32.c | ||
| 2989 | @@ -3,7 +3,8 @@ | ||
| 2990 | |||
| 2991 | /* { dg-do assemble } */ | ||
| 2992 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 2993 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 2994 | +/* { dg-options "-save-temps -O0" } */ | ||
| 2995 | +/* { dg-add-options arm_neon } */ | ||
| 2996 | |||
| 2997 | #include "arm_neon.h" | ||
| 2998 | |||
| 2999 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu64.c | ||
| 3000 | =================================================================== | ||
| 3001 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicu64.c | ||
| 3002 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu64.c | ||
| 3003 | @@ -3,7 +3,8 @@ | ||
| 3004 | |||
| 3005 | /* { dg-do assemble } */ | ||
| 3006 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3007 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3008 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3009 | +/* { dg-add-options arm_neon } */ | ||
| 3010 | |||
| 3011 | #include "arm_neon.h" | ||
| 3012 | |||
| 3013 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu8.c | ||
| 3014 | =================================================================== | ||
| 3015 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbicu8.c | ||
| 3016 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbicu8.c | ||
| 3017 | @@ -3,7 +3,8 @@ | ||
| 3018 | |||
| 3019 | /* { dg-do assemble } */ | ||
| 3020 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3021 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3022 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3023 | +/* { dg-add-options arm_neon } */ | ||
| 3024 | |||
| 3025 | #include "arm_neon.h" | ||
| 3026 | |||
| 3027 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c | ||
| 3028 | =================================================================== | ||
| 3029 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c | ||
| 3030 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c | ||
| 3031 | @@ -3,7 +3,8 @@ | ||
| 3032 | |||
| 3033 | /* { dg-do assemble } */ | ||
| 3034 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3035 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3036 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3037 | +/* { dg-add-options arm_neon } */ | ||
| 3038 | |||
| 3039 | #include "arm_neon.h" | ||
| 3040 | |||
| 3041 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c | ||
| 3042 | =================================================================== | ||
| 3043 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c | ||
| 3044 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c | ||
| 3045 | @@ -3,7 +3,8 @@ | ||
| 3046 | |||
| 3047 | /* { dg-do assemble } */ | ||
| 3048 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3049 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3050 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3051 | +/* { dg-add-options arm_neon } */ | ||
| 3052 | |||
| 3053 | #include "arm_neon.h" | ||
| 3054 | |||
| 3055 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c | ||
| 3056 | =================================================================== | ||
| 3057 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c | ||
| 3058 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c | ||
| 3059 | @@ -3,7 +3,8 @@ | ||
| 3060 | |||
| 3061 | /* { dg-do assemble } */ | ||
| 3062 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3063 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3064 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3065 | +/* { dg-add-options arm_neon } */ | ||
| 3066 | |||
| 3067 | #include "arm_neon.h" | ||
| 3068 | |||
| 3069 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c | ||
| 3070 | =================================================================== | ||
| 3071 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c | ||
| 3072 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c | ||
| 3073 | @@ -3,7 +3,8 @@ | ||
| 3074 | |||
| 3075 | /* { dg-do assemble } */ | ||
| 3076 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3077 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3078 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3079 | +/* { dg-add-options arm_neon } */ | ||
| 3080 | |||
| 3081 | #include "arm_neon.h" | ||
| 3082 | |||
| 3083 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c | ||
| 3084 | =================================================================== | ||
| 3085 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c | ||
| 3086 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c | ||
| 3087 | @@ -3,7 +3,8 @@ | ||
| 3088 | |||
| 3089 | /* { dg-do assemble } */ | ||
| 3090 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3091 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3092 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3093 | +/* { dg-add-options arm_neon } */ | ||
| 3094 | |||
| 3095 | #include "arm_neon.h" | ||
| 3096 | |||
| 3097 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c | ||
| 3098 | =================================================================== | ||
| 3099 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c | ||
| 3100 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c | ||
| 3101 | @@ -3,7 +3,8 @@ | ||
| 3102 | |||
| 3103 | /* { dg-do assemble } */ | ||
| 3104 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3105 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3106 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3107 | +/* { dg-add-options arm_neon } */ | ||
| 3108 | |||
| 3109 | #include "arm_neon.h" | ||
| 3110 | |||
| 3111 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c | ||
| 3112 | =================================================================== | ||
| 3113 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c | ||
| 3114 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c | ||
| 3115 | @@ -3,7 +3,8 @@ | ||
| 3116 | |||
| 3117 | /* { dg-do assemble } */ | ||
| 3118 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3119 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3120 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3121 | +/* { dg-add-options arm_neon } */ | ||
| 3122 | |||
| 3123 | #include "arm_neon.h" | ||
| 3124 | |||
| 3125 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c | ||
| 3126 | =================================================================== | ||
| 3127 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c | ||
| 3128 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c | ||
| 3129 | @@ -3,7 +3,8 @@ | ||
| 3130 | |||
| 3131 | /* { dg-do assemble } */ | ||
| 3132 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3133 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3134 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3135 | +/* { dg-add-options arm_neon } */ | ||
| 3136 | |||
| 3137 | #include "arm_neon.h" | ||
| 3138 | |||
| 3139 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c | ||
| 3140 | =================================================================== | ||
| 3141 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c | ||
| 3142 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c | ||
| 3143 | @@ -3,7 +3,8 @@ | ||
| 3144 | |||
| 3145 | /* { dg-do assemble } */ | ||
| 3146 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3147 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3148 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3149 | +/* { dg-add-options arm_neon } */ | ||
| 3150 | |||
| 3151 | #include "arm_neon.h" | ||
| 3152 | |||
| 3153 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c | ||
| 3154 | =================================================================== | ||
| 3155 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c | ||
| 3156 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c | ||
| 3157 | @@ -3,7 +3,8 @@ | ||
| 3158 | |||
| 3159 | /* { dg-do assemble } */ | ||
| 3160 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3161 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3162 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3163 | +/* { dg-add-options arm_neon } */ | ||
| 3164 | |||
| 3165 | #include "arm_neon.h" | ||
| 3166 | |||
| 3167 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c | ||
| 3168 | =================================================================== | ||
| 3169 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c | ||
| 3170 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c | ||
| 3171 | @@ -3,7 +3,8 @@ | ||
| 3172 | |||
| 3173 | /* { dg-do assemble } */ | ||
| 3174 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3175 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3176 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3177 | +/* { dg-add-options arm_neon } */ | ||
| 3178 | |||
| 3179 | #include "arm_neon.h" | ||
| 3180 | |||
| 3181 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslf32.c | ||
| 3182 | =================================================================== | ||
| 3183 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslf32.c | ||
| 3184 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslf32.c | ||
| 3185 | @@ -3,7 +3,8 @@ | ||
| 3186 | |||
| 3187 | /* { dg-do assemble } */ | ||
| 3188 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3189 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3190 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3191 | +/* { dg-add-options arm_neon } */ | ||
| 3192 | |||
| 3193 | #include "arm_neon.h" | ||
| 3194 | |||
| 3195 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslp16.c | ||
| 3196 | =================================================================== | ||
| 3197 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslp16.c | ||
| 3198 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslp16.c | ||
| 3199 | @@ -3,7 +3,8 @@ | ||
| 3200 | |||
| 3201 | /* { dg-do assemble } */ | ||
| 3202 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3203 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3204 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3205 | +/* { dg-add-options arm_neon } */ | ||
| 3206 | |||
| 3207 | #include "arm_neon.h" | ||
| 3208 | |||
| 3209 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslp8.c | ||
| 3210 | =================================================================== | ||
| 3211 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslp8.c | ||
| 3212 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslp8.c | ||
| 3213 | @@ -3,7 +3,8 @@ | ||
| 3214 | |||
| 3215 | /* { dg-do assemble } */ | ||
| 3216 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3217 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3218 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3219 | +/* { dg-add-options arm_neon } */ | ||
| 3220 | |||
| 3221 | #include "arm_neon.h" | ||
| 3222 | |||
| 3223 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls16.c | ||
| 3224 | =================================================================== | ||
| 3225 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbsls16.c | ||
| 3226 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls16.c | ||
| 3227 | @@ -3,7 +3,8 @@ | ||
| 3228 | |||
| 3229 | /* { dg-do assemble } */ | ||
| 3230 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3231 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3232 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3233 | +/* { dg-add-options arm_neon } */ | ||
| 3234 | |||
| 3235 | #include "arm_neon.h" | ||
| 3236 | |||
| 3237 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls32.c | ||
| 3238 | =================================================================== | ||
| 3239 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbsls32.c | ||
| 3240 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls32.c | ||
| 3241 | @@ -3,7 +3,8 @@ | ||
| 3242 | |||
| 3243 | /* { dg-do assemble } */ | ||
| 3244 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3245 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3246 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3247 | +/* { dg-add-options arm_neon } */ | ||
| 3248 | |||
| 3249 | #include "arm_neon.h" | ||
| 3250 | |||
| 3251 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls64.c | ||
| 3252 | =================================================================== | ||
| 3253 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbsls64.c | ||
| 3254 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls64.c | ||
| 3255 | @@ -3,7 +3,8 @@ | ||
| 3256 | |||
| 3257 | /* { dg-do assemble } */ | ||
| 3258 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3259 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3260 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3261 | +/* { dg-add-options arm_neon } */ | ||
| 3262 | |||
| 3263 | #include "arm_neon.h" | ||
| 3264 | |||
| 3265 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls8.c | ||
| 3266 | =================================================================== | ||
| 3267 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbsls8.c | ||
| 3268 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbsls8.c | ||
| 3269 | @@ -3,7 +3,8 @@ | ||
| 3270 | |||
| 3271 | /* { dg-do assemble } */ | ||
| 3272 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3273 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3274 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3275 | +/* { dg-add-options arm_neon } */ | ||
| 3276 | |||
| 3277 | #include "arm_neon.h" | ||
| 3278 | |||
| 3279 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu16.c | ||
| 3280 | =================================================================== | ||
| 3281 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslu16.c | ||
| 3282 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu16.c | ||
| 3283 | @@ -3,7 +3,8 @@ | ||
| 3284 | |||
| 3285 | /* { dg-do assemble } */ | ||
| 3286 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3287 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3288 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3289 | +/* { dg-add-options arm_neon } */ | ||
| 3290 | |||
| 3291 | #include "arm_neon.h" | ||
| 3292 | |||
| 3293 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu32.c | ||
| 3294 | =================================================================== | ||
| 3295 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslu32.c | ||
| 3296 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu32.c | ||
| 3297 | @@ -3,7 +3,8 @@ | ||
| 3298 | |||
| 3299 | /* { dg-do assemble } */ | ||
| 3300 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3301 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3302 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3303 | +/* { dg-add-options arm_neon } */ | ||
| 3304 | |||
| 3305 | #include "arm_neon.h" | ||
| 3306 | |||
| 3307 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu64.c | ||
| 3308 | =================================================================== | ||
| 3309 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslu64.c | ||
| 3310 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu64.c | ||
| 3311 | @@ -3,7 +3,8 @@ | ||
| 3312 | |||
| 3313 | /* { dg-do assemble } */ | ||
| 3314 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3315 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3316 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3317 | +/* { dg-add-options arm_neon } */ | ||
| 3318 | |||
| 3319 | #include "arm_neon.h" | ||
| 3320 | |||
| 3321 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu8.c | ||
| 3322 | =================================================================== | ||
| 3323 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vbslu8.c | ||
| 3324 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vbslu8.c | ||
| 3325 | @@ -3,7 +3,8 @@ | ||
| 3326 | |||
| 3327 | /* { dg-do assemble } */ | ||
| 3328 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3329 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3330 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3331 | +/* { dg-add-options arm_neon } */ | ||
| 3332 | |||
| 3333 | #include "arm_neon.h" | ||
| 3334 | |||
| 3335 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c | ||
| 3336 | =================================================================== | ||
| 3337 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c | ||
| 3338 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c | ||
| 3339 | @@ -3,7 +3,8 @@ | ||
| 3340 | |||
| 3341 | /* { dg-do assemble } */ | ||
| 3342 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3343 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3344 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3345 | +/* { dg-add-options arm_neon } */ | ||
| 3346 | |||
| 3347 | #include "arm_neon.h" | ||
| 3348 | |||
| 3349 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcagef32.c | ||
| 3350 | =================================================================== | ||
| 3351 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcagef32.c | ||
| 3352 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcagef32.c | ||
| 3353 | @@ -3,7 +3,8 @@ | ||
| 3354 | |||
| 3355 | /* { dg-do assemble } */ | ||
| 3356 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3357 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3358 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3359 | +/* { dg-add-options arm_neon } */ | ||
| 3360 | |||
| 3361 | #include "arm_neon.h" | ||
| 3362 | |||
| 3363 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c | ||
| 3364 | =================================================================== | ||
| 3365 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c | ||
| 3366 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c | ||
| 3367 | @@ -3,7 +3,8 @@ | ||
| 3368 | |||
| 3369 | /* { dg-do assemble } */ | ||
| 3370 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3371 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3372 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3373 | +/* { dg-add-options arm_neon } */ | ||
| 3374 | |||
| 3375 | #include "arm_neon.h" | ||
| 3376 | |||
| 3377 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c | ||
| 3378 | =================================================================== | ||
| 3379 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c | ||
| 3380 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c | ||
| 3381 | @@ -3,7 +3,8 @@ | ||
| 3382 | |||
| 3383 | /* { dg-do assemble } */ | ||
| 3384 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3385 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3386 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3387 | +/* { dg-add-options arm_neon } */ | ||
| 3388 | |||
| 3389 | #include "arm_neon.h" | ||
| 3390 | |||
| 3391 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c | ||
| 3392 | =================================================================== | ||
| 3393 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c | ||
| 3394 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c | ||
| 3395 | @@ -3,7 +3,8 @@ | ||
| 3396 | |||
| 3397 | /* { dg-do assemble } */ | ||
| 3398 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3399 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3400 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3401 | +/* { dg-add-options arm_neon } */ | ||
| 3402 | |||
| 3403 | #include "arm_neon.h" | ||
| 3404 | |||
| 3405 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcalef32.c | ||
| 3406 | =================================================================== | ||
| 3407 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcalef32.c | ||
| 3408 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcalef32.c | ||
| 3409 | @@ -3,7 +3,8 @@ | ||
| 3410 | |||
| 3411 | /* { dg-do assemble } */ | ||
| 3412 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3413 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3414 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3415 | +/* { dg-add-options arm_neon } */ | ||
| 3416 | |||
| 3417 | #include "arm_neon.h" | ||
| 3418 | |||
| 3419 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c | ||
| 3420 | =================================================================== | ||
| 3421 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c | ||
| 3422 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c | ||
| 3423 | @@ -3,7 +3,8 @@ | ||
| 3424 | |||
| 3425 | /* { dg-do assemble } */ | ||
| 3426 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3427 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3428 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3429 | +/* { dg-add-options arm_neon } */ | ||
| 3430 | |||
| 3431 | #include "arm_neon.h" | ||
| 3432 | |||
| 3433 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c | ||
| 3434 | =================================================================== | ||
| 3435 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c | ||
| 3436 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c | ||
| 3437 | @@ -3,7 +3,8 @@ | ||
| 3438 | |||
| 3439 | /* { dg-do assemble } */ | ||
| 3440 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3441 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3442 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3443 | +/* { dg-add-options arm_neon } */ | ||
| 3444 | |||
| 3445 | #include "arm_neon.h" | ||
| 3446 | |||
| 3447 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c | ||
| 3448 | =================================================================== | ||
| 3449 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c | ||
| 3450 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c | ||
| 3451 | @@ -3,7 +3,8 @@ | ||
| 3452 | |||
| 3453 | /* { dg-do assemble } */ | ||
| 3454 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3455 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3456 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3457 | +/* { dg-add-options arm_neon } */ | ||
| 3458 | |||
| 3459 | #include "arm_neon.h" | ||
| 3460 | |||
| 3461 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c | ||
| 3462 | =================================================================== | ||
| 3463 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c | ||
| 3464 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c | ||
| 3465 | @@ -3,7 +3,8 @@ | ||
| 3466 | |||
| 3467 | /* { dg-do assemble } */ | ||
| 3468 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3469 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3470 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3471 | +/* { dg-add-options arm_neon } */ | ||
| 3472 | |||
| 3473 | #include "arm_neon.h" | ||
| 3474 | |||
| 3475 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c | ||
| 3476 | =================================================================== | ||
| 3477 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c | ||
| 3478 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c | ||
| 3479 | @@ -3,7 +3,8 @@ | ||
| 3480 | |||
| 3481 | /* { dg-do assemble } */ | ||
| 3482 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3483 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3484 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3485 | +/* { dg-add-options arm_neon } */ | ||
| 3486 | |||
| 3487 | #include "arm_neon.h" | ||
| 3488 | |||
| 3489 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c | ||
| 3490 | =================================================================== | ||
| 3491 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c | ||
| 3492 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c | ||
| 3493 | @@ -3,7 +3,8 @@ | ||
| 3494 | |||
| 3495 | /* { dg-do assemble } */ | ||
| 3496 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3497 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3498 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3499 | +/* { dg-add-options arm_neon } */ | ||
| 3500 | |||
| 3501 | #include "arm_neon.h" | ||
| 3502 | |||
| 3503 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c | ||
| 3504 | =================================================================== | ||
| 3505 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c | ||
| 3506 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c | ||
| 3507 | @@ -3,7 +3,8 @@ | ||
| 3508 | |||
| 3509 | /* { dg-do assemble } */ | ||
| 3510 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3511 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3512 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3513 | +/* { dg-add-options arm_neon } */ | ||
| 3514 | |||
| 3515 | #include "arm_neon.h" | ||
| 3516 | |||
| 3517 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c | ||
| 3518 | =================================================================== | ||
| 3519 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c | ||
| 3520 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c | ||
| 3521 | @@ -3,7 +3,8 @@ | ||
| 3522 | |||
| 3523 | /* { dg-do assemble } */ | ||
| 3524 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3525 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3526 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3527 | +/* { dg-add-options arm_neon } */ | ||
| 3528 | |||
| 3529 | #include "arm_neon.h" | ||
| 3530 | |||
| 3531 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c | ||
| 3532 | =================================================================== | ||
| 3533 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c | ||
| 3534 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c | ||
| 3535 | @@ -3,7 +3,8 @@ | ||
| 3536 | |||
| 3537 | /* { dg-do assemble } */ | ||
| 3538 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3539 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3540 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3541 | +/* { dg-add-options arm_neon } */ | ||
| 3542 | |||
| 3543 | #include "arm_neon.h" | ||
| 3544 | |||
| 3545 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c | ||
| 3546 | =================================================================== | ||
| 3547 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c | ||
| 3548 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c | ||
| 3549 | @@ -3,7 +3,8 @@ | ||
| 3550 | |||
| 3551 | /* { dg-do assemble } */ | ||
| 3552 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3553 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3554 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3555 | +/* { dg-add-options arm_neon } */ | ||
| 3556 | |||
| 3557 | #include "arm_neon.h" | ||
| 3558 | |||
| 3559 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqf32.c | ||
| 3560 | =================================================================== | ||
| 3561 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqf32.c | ||
| 3562 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqf32.c | ||
| 3563 | @@ -3,7 +3,8 @@ | ||
| 3564 | |||
| 3565 | /* { dg-do assemble } */ | ||
| 3566 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3567 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3568 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3569 | +/* { dg-add-options arm_neon } */ | ||
| 3570 | |||
| 3571 | #include "arm_neon.h" | ||
| 3572 | |||
| 3573 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqp8.c | ||
| 3574 | =================================================================== | ||
| 3575 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqp8.c | ||
| 3576 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqp8.c | ||
| 3577 | @@ -3,7 +3,8 @@ | ||
| 3578 | |||
| 3579 | /* { dg-do assemble } */ | ||
| 3580 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3581 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3582 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3583 | +/* { dg-add-options arm_neon } */ | ||
| 3584 | |||
| 3585 | #include "arm_neon.h" | ||
| 3586 | |||
| 3587 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqs16.c | ||
| 3588 | =================================================================== | ||
| 3589 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqs16.c | ||
| 3590 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqs16.c | ||
| 3591 | @@ -3,7 +3,8 @@ | ||
| 3592 | |||
| 3593 | /* { dg-do assemble } */ | ||
| 3594 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3595 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3596 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3597 | +/* { dg-add-options arm_neon } */ | ||
| 3598 | |||
| 3599 | #include "arm_neon.h" | ||
| 3600 | |||
| 3601 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqs32.c | ||
| 3602 | =================================================================== | ||
| 3603 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqs32.c | ||
| 3604 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqs32.c | ||
| 3605 | @@ -3,7 +3,8 @@ | ||
| 3606 | |||
| 3607 | /* { dg-do assemble } */ | ||
| 3608 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3609 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3610 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3611 | +/* { dg-add-options arm_neon } */ | ||
| 3612 | |||
| 3613 | #include "arm_neon.h" | ||
| 3614 | |||
| 3615 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqs8.c | ||
| 3616 | =================================================================== | ||
| 3617 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vceqs8.c | ||
| 3618 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vceqs8.c | ||
| 3619 | @@ -3,7 +3,8 @@ | ||
| 3620 | |||
| 3621 | /* { dg-do assemble } */ | ||
| 3622 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3623 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3624 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3625 | +/* { dg-add-options arm_neon } */ | ||
| 3626 | |||
| 3627 | #include "arm_neon.h" | ||
| 3628 | |||
| 3629 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcequ16.c | ||
| 3630 | =================================================================== | ||
| 3631 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcequ16.c | ||
| 3632 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcequ16.c | ||
| 3633 | @@ -3,7 +3,8 @@ | ||
| 3634 | |||
| 3635 | /* { dg-do assemble } */ | ||
| 3636 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3637 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3638 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3639 | +/* { dg-add-options arm_neon } */ | ||
| 3640 | |||
| 3641 | #include "arm_neon.h" | ||
| 3642 | |||
| 3643 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcequ32.c | ||
| 3644 | =================================================================== | ||
| 3645 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcequ32.c | ||
| 3646 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcequ32.c | ||
| 3647 | @@ -3,7 +3,8 @@ | ||
| 3648 | |||
| 3649 | /* { dg-do assemble } */ | ||
| 3650 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3651 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3652 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3653 | +/* { dg-add-options arm_neon } */ | ||
| 3654 | |||
| 3655 | #include "arm_neon.h" | ||
| 3656 | |||
| 3657 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcequ8.c | ||
| 3658 | =================================================================== | ||
| 3659 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcequ8.c | ||
| 3660 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcequ8.c | ||
| 3661 | @@ -3,7 +3,8 @@ | ||
| 3662 | |||
| 3663 | /* { dg-do assemble } */ | ||
| 3664 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3665 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3666 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3667 | +/* { dg-add-options arm_neon } */ | ||
| 3668 | |||
| 3669 | #include "arm_neon.h" | ||
| 3670 | |||
| 3671 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c | ||
| 3672 | =================================================================== | ||
| 3673 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c | ||
| 3674 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c | ||
| 3675 | @@ -3,7 +3,8 @@ | ||
| 3676 | |||
| 3677 | /* { dg-do assemble } */ | ||
| 3678 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3679 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3680 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3681 | +/* { dg-add-options arm_neon } */ | ||
| 3682 | |||
| 3683 | #include "arm_neon.h" | ||
| 3684 | |||
| 3685 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c | ||
| 3686 | =================================================================== | ||
| 3687 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c | ||
| 3688 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c | ||
| 3689 | @@ -3,7 +3,8 @@ | ||
| 3690 | |||
| 3691 | /* { dg-do assemble } */ | ||
| 3692 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3693 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3694 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3695 | +/* { dg-add-options arm_neon } */ | ||
| 3696 | |||
| 3697 | #include "arm_neon.h" | ||
| 3698 | |||
| 3699 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c | ||
| 3700 | =================================================================== | ||
| 3701 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c | ||
| 3702 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c | ||
| 3703 | @@ -3,7 +3,8 @@ | ||
| 3704 | |||
| 3705 | /* { dg-do assemble } */ | ||
| 3706 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3707 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3708 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3709 | +/* { dg-add-options arm_neon } */ | ||
| 3710 | |||
| 3711 | #include "arm_neon.h" | ||
| 3712 | |||
| 3713 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c | ||
| 3714 | =================================================================== | ||
| 3715 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c | ||
| 3716 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c | ||
| 3717 | @@ -3,7 +3,8 @@ | ||
| 3718 | |||
| 3719 | /* { dg-do assemble } */ | ||
| 3720 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3721 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3722 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3723 | +/* { dg-add-options arm_neon } */ | ||
| 3724 | |||
| 3725 | #include "arm_neon.h" | ||
| 3726 | |||
| 3727 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c | ||
| 3728 | =================================================================== | ||
| 3729 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c | ||
| 3730 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c | ||
| 3731 | @@ -3,7 +3,8 @@ | ||
| 3732 | |||
| 3733 | /* { dg-do assemble } */ | ||
| 3734 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3735 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3736 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3737 | +/* { dg-add-options arm_neon } */ | ||
| 3738 | |||
| 3739 | #include "arm_neon.h" | ||
| 3740 | |||
| 3741 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c | ||
| 3742 | =================================================================== | ||
| 3743 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c | ||
| 3744 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c | ||
| 3745 | @@ -3,7 +3,8 @@ | ||
| 3746 | |||
| 3747 | /* { dg-do assemble } */ | ||
| 3748 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3749 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3750 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3751 | +/* { dg-add-options arm_neon } */ | ||
| 3752 | |||
| 3753 | #include "arm_neon.h" | ||
| 3754 | |||
| 3755 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c | ||
| 3756 | =================================================================== | ||
| 3757 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c | ||
| 3758 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c | ||
| 3759 | @@ -3,7 +3,8 @@ | ||
| 3760 | |||
| 3761 | /* { dg-do assemble } */ | ||
| 3762 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3763 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3764 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3765 | +/* { dg-add-options arm_neon } */ | ||
| 3766 | |||
| 3767 | #include "arm_neon.h" | ||
| 3768 | |||
| 3769 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgef32.c | ||
| 3770 | =================================================================== | ||
| 3771 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgef32.c | ||
| 3772 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgef32.c | ||
| 3773 | @@ -3,7 +3,8 @@ | ||
| 3774 | |||
| 3775 | /* { dg-do assemble } */ | ||
| 3776 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3777 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3778 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3779 | +/* { dg-add-options arm_neon } */ | ||
| 3780 | |||
| 3781 | #include "arm_neon.h" | ||
| 3782 | |||
| 3783 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcges16.c | ||
| 3784 | =================================================================== | ||
| 3785 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcges16.c | ||
| 3786 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcges16.c | ||
| 3787 | @@ -3,7 +3,8 @@ | ||
| 3788 | |||
| 3789 | /* { dg-do assemble } */ | ||
| 3790 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3791 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3792 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3793 | +/* { dg-add-options arm_neon } */ | ||
| 3794 | |||
| 3795 | #include "arm_neon.h" | ||
| 3796 | |||
| 3797 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcges32.c | ||
| 3798 | =================================================================== | ||
| 3799 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcges32.c | ||
| 3800 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcges32.c | ||
| 3801 | @@ -3,7 +3,8 @@ | ||
| 3802 | |||
| 3803 | /* { dg-do assemble } */ | ||
| 3804 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3805 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3806 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3807 | +/* { dg-add-options arm_neon } */ | ||
| 3808 | |||
| 3809 | #include "arm_neon.h" | ||
| 3810 | |||
| 3811 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcges8.c | ||
| 3812 | =================================================================== | ||
| 3813 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcges8.c | ||
| 3814 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcges8.c | ||
| 3815 | @@ -3,7 +3,8 @@ | ||
| 3816 | |||
| 3817 | /* { dg-do assemble } */ | ||
| 3818 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3819 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3820 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3821 | +/* { dg-add-options arm_neon } */ | ||
| 3822 | |||
| 3823 | #include "arm_neon.h" | ||
| 3824 | |||
| 3825 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c | ||
| 3826 | =================================================================== | ||
| 3827 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c | ||
| 3828 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c | ||
| 3829 | @@ -3,7 +3,8 @@ | ||
| 3830 | |||
| 3831 | /* { dg-do assemble } */ | ||
| 3832 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3833 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3834 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3835 | +/* { dg-add-options arm_neon } */ | ||
| 3836 | |||
| 3837 | #include "arm_neon.h" | ||
| 3838 | |||
| 3839 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c | ||
| 3840 | =================================================================== | ||
| 3841 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c | ||
| 3842 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c | ||
| 3843 | @@ -3,7 +3,8 @@ | ||
| 3844 | |||
| 3845 | /* { dg-do assemble } */ | ||
| 3846 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3847 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3848 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3849 | +/* { dg-add-options arm_neon } */ | ||
| 3850 | |||
| 3851 | #include "arm_neon.h" | ||
| 3852 | |||
| 3853 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c | ||
| 3854 | =================================================================== | ||
| 3855 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c | ||
| 3856 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c | ||
| 3857 | @@ -3,7 +3,8 @@ | ||
| 3858 | |||
| 3859 | /* { dg-do assemble } */ | ||
| 3860 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3861 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3862 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3863 | +/* { dg-add-options arm_neon } */ | ||
| 3864 | |||
| 3865 | #include "arm_neon.h" | ||
| 3866 | |||
| 3867 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c | ||
| 3868 | =================================================================== | ||
| 3869 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c | ||
| 3870 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c | ||
| 3871 | @@ -3,7 +3,8 @@ | ||
| 3872 | |||
| 3873 | /* { dg-do assemble } */ | ||
| 3874 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3875 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3876 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3877 | +/* { dg-add-options arm_neon } */ | ||
| 3878 | |||
| 3879 | #include "arm_neon.h" | ||
| 3880 | |||
| 3881 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c | ||
| 3882 | =================================================================== | ||
| 3883 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c | ||
| 3884 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c | ||
| 3885 | @@ -3,7 +3,8 @@ | ||
| 3886 | |||
| 3887 | /* { dg-do assemble } */ | ||
| 3888 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3889 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3890 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3891 | +/* { dg-add-options arm_neon } */ | ||
| 3892 | |||
| 3893 | #include "arm_neon.h" | ||
| 3894 | |||
| 3895 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c | ||
| 3896 | =================================================================== | ||
| 3897 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c | ||
| 3898 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c | ||
| 3899 | @@ -3,7 +3,8 @@ | ||
| 3900 | |||
| 3901 | /* { dg-do assemble } */ | ||
| 3902 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3903 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3904 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3905 | +/* { dg-add-options arm_neon } */ | ||
| 3906 | |||
| 3907 | #include "arm_neon.h" | ||
| 3908 | |||
| 3909 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c | ||
| 3910 | =================================================================== | ||
| 3911 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c | ||
| 3912 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c | ||
| 3913 | @@ -3,7 +3,8 @@ | ||
| 3914 | |||
| 3915 | /* { dg-do assemble } */ | ||
| 3916 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3917 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3918 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3919 | +/* { dg-add-options arm_neon } */ | ||
| 3920 | |||
| 3921 | #include "arm_neon.h" | ||
| 3922 | |||
| 3923 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c | ||
| 3924 | =================================================================== | ||
| 3925 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c | ||
| 3926 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c | ||
| 3927 | @@ -3,7 +3,8 @@ | ||
| 3928 | |||
| 3929 | /* { dg-do assemble } */ | ||
| 3930 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3931 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3932 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3933 | +/* { dg-add-options arm_neon } */ | ||
| 3934 | |||
| 3935 | #include "arm_neon.h" | ||
| 3936 | |||
| 3937 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c | ||
| 3938 | =================================================================== | ||
| 3939 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c | ||
| 3940 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c | ||
| 3941 | @@ -3,7 +3,8 @@ | ||
| 3942 | |||
| 3943 | /* { dg-do assemble } */ | ||
| 3944 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3945 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3946 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3947 | +/* { dg-add-options arm_neon } */ | ||
| 3948 | |||
| 3949 | #include "arm_neon.h" | ||
| 3950 | |||
| 3951 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c | ||
| 3952 | =================================================================== | ||
| 3953 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c | ||
| 3954 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c | ||
| 3955 | @@ -3,7 +3,8 @@ | ||
| 3956 | |||
| 3957 | /* { dg-do assemble } */ | ||
| 3958 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3959 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3960 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3961 | +/* { dg-add-options arm_neon } */ | ||
| 3962 | |||
| 3963 | #include "arm_neon.h" | ||
| 3964 | |||
| 3965 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c | ||
| 3966 | =================================================================== | ||
| 3967 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c | ||
| 3968 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c | ||
| 3969 | @@ -3,7 +3,8 @@ | ||
| 3970 | |||
| 3971 | /* { dg-do assemble } */ | ||
| 3972 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3973 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3974 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3975 | +/* { dg-add-options arm_neon } */ | ||
| 3976 | |||
| 3977 | #include "arm_neon.h" | ||
| 3978 | |||
| 3979 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgts16.c | ||
| 3980 | =================================================================== | ||
| 3981 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgts16.c | ||
| 3982 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgts16.c | ||
| 3983 | @@ -3,7 +3,8 @@ | ||
| 3984 | |||
| 3985 | /* { dg-do assemble } */ | ||
| 3986 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 3987 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 3988 | +/* { dg-options "-save-temps -O0" } */ | ||
| 3989 | +/* { dg-add-options arm_neon } */ | ||
| 3990 | |||
| 3991 | #include "arm_neon.h" | ||
| 3992 | |||
| 3993 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgts32.c | ||
| 3994 | =================================================================== | ||
| 3995 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgts32.c | ||
| 3996 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgts32.c | ||
| 3997 | @@ -3,7 +3,8 @@ | ||
| 3998 | |||
| 3999 | /* { dg-do assemble } */ | ||
| 4000 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4001 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4002 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4003 | +/* { dg-add-options arm_neon } */ | ||
| 4004 | |||
| 4005 | #include "arm_neon.h" | ||
| 4006 | |||
| 4007 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgts8.c | ||
| 4008 | =================================================================== | ||
| 4009 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgts8.c | ||
| 4010 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgts8.c | ||
| 4011 | @@ -3,7 +3,8 @@ | ||
| 4012 | |||
| 4013 | /* { dg-do assemble } */ | ||
| 4014 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4015 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4016 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4017 | +/* { dg-add-options arm_neon } */ | ||
| 4018 | |||
| 4019 | #include "arm_neon.h" | ||
| 4020 | |||
| 4021 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c | ||
| 4022 | =================================================================== | ||
| 4023 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c | ||
| 4024 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c | ||
| 4025 | @@ -3,7 +3,8 @@ | ||
| 4026 | |||
| 4027 | /* { dg-do assemble } */ | ||
| 4028 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4029 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4030 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4031 | +/* { dg-add-options arm_neon } */ | ||
| 4032 | |||
| 4033 | #include "arm_neon.h" | ||
| 4034 | |||
| 4035 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c | ||
| 4036 | =================================================================== | ||
| 4037 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c | ||
| 4038 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c | ||
| 4039 | @@ -3,7 +3,8 @@ | ||
| 4040 | |||
| 4041 | /* { dg-do assemble } */ | ||
| 4042 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4043 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4044 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4045 | +/* { dg-add-options arm_neon } */ | ||
| 4046 | |||
| 4047 | #include "arm_neon.h" | ||
| 4048 | |||
| 4049 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c | ||
| 4050 | =================================================================== | ||
| 4051 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c | ||
| 4052 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c | ||
| 4053 | @@ -3,7 +3,8 @@ | ||
| 4054 | |||
| 4055 | /* { dg-do assemble } */ | ||
| 4056 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4057 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4058 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4059 | +/* { dg-add-options arm_neon } */ | ||
| 4060 | |||
| 4061 | #include "arm_neon.h" | ||
| 4062 | |||
| 4063 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c | ||
| 4064 | =================================================================== | ||
| 4065 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c | ||
| 4066 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c | ||
| 4067 | @@ -3,7 +3,8 @@ | ||
| 4068 | |||
| 4069 | /* { dg-do assemble } */ | ||
| 4070 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4071 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4072 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4073 | +/* { dg-add-options arm_neon } */ | ||
| 4074 | |||
| 4075 | #include "arm_neon.h" | ||
| 4076 | |||
| 4077 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c | ||
| 4078 | =================================================================== | ||
| 4079 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c | ||
| 4080 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c | ||
| 4081 | @@ -3,7 +3,8 @@ | ||
| 4082 | |||
| 4083 | /* { dg-do assemble } */ | ||
| 4084 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4085 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4086 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4087 | +/* { dg-add-options arm_neon } */ | ||
| 4088 | |||
| 4089 | #include "arm_neon.h" | ||
| 4090 | |||
| 4091 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c | ||
| 4092 | =================================================================== | ||
| 4093 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c | ||
| 4094 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c | ||
| 4095 | @@ -3,7 +3,8 @@ | ||
| 4096 | |||
| 4097 | /* { dg-do assemble } */ | ||
| 4098 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4099 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4100 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4101 | +/* { dg-add-options arm_neon } */ | ||
| 4102 | |||
| 4103 | #include "arm_neon.h" | ||
| 4104 | |||
| 4105 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c | ||
| 4106 | =================================================================== | ||
| 4107 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c | ||
| 4108 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c | ||
| 4109 | @@ -3,7 +3,8 @@ | ||
| 4110 | |||
| 4111 | /* { dg-do assemble } */ | ||
| 4112 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4113 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4114 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4115 | +/* { dg-add-options arm_neon } */ | ||
| 4116 | |||
| 4117 | #include "arm_neon.h" | ||
| 4118 | |||
| 4119 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c | ||
| 4120 | =================================================================== | ||
| 4121 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c | ||
| 4122 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c | ||
| 4123 | @@ -3,7 +3,8 @@ | ||
| 4124 | |||
| 4125 | /* { dg-do assemble } */ | ||
| 4126 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4127 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4128 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4129 | +/* { dg-add-options arm_neon } */ | ||
| 4130 | |||
| 4131 | #include "arm_neon.h" | ||
| 4132 | |||
| 4133 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c | ||
| 4134 | =================================================================== | ||
| 4135 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c | ||
| 4136 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c | ||
| 4137 | @@ -3,7 +3,8 @@ | ||
| 4138 | |||
| 4139 | /* { dg-do assemble } */ | ||
| 4140 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4141 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4142 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4143 | +/* { dg-add-options arm_neon } */ | ||
| 4144 | |||
| 4145 | #include "arm_neon.h" | ||
| 4146 | |||
| 4147 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c | ||
| 4148 | =================================================================== | ||
| 4149 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c | ||
| 4150 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c | ||
| 4151 | @@ -3,7 +3,8 @@ | ||
| 4152 | |||
| 4153 | /* { dg-do assemble } */ | ||
| 4154 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4155 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4156 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4157 | +/* { dg-add-options arm_neon } */ | ||
| 4158 | |||
| 4159 | #include "arm_neon.h" | ||
| 4160 | |||
| 4161 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclef32.c | ||
| 4162 | =================================================================== | ||
| 4163 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclef32.c | ||
| 4164 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclef32.c | ||
| 4165 | @@ -3,7 +3,8 @@ | ||
| 4166 | |||
| 4167 | /* { dg-do assemble } */ | ||
| 4168 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4169 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4170 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4171 | +/* { dg-add-options arm_neon } */ | ||
| 4172 | |||
| 4173 | #include "arm_neon.h" | ||
| 4174 | |||
| 4175 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcles16.c | ||
| 4176 | =================================================================== | ||
| 4177 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcles16.c | ||
| 4178 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcles16.c | ||
| 4179 | @@ -3,7 +3,8 @@ | ||
| 4180 | |||
| 4181 | /* { dg-do assemble } */ | ||
| 4182 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4183 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4184 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4185 | +/* { dg-add-options arm_neon } */ | ||
| 4186 | |||
| 4187 | #include "arm_neon.h" | ||
| 4188 | |||
| 4189 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcles32.c | ||
| 4190 | =================================================================== | ||
| 4191 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcles32.c | ||
| 4192 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcles32.c | ||
| 4193 | @@ -3,7 +3,8 @@ | ||
| 4194 | |||
| 4195 | /* { dg-do assemble } */ | ||
| 4196 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4197 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4198 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4199 | +/* { dg-add-options arm_neon } */ | ||
| 4200 | |||
| 4201 | #include "arm_neon.h" | ||
| 4202 | |||
| 4203 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcles8.c | ||
| 4204 | =================================================================== | ||
| 4205 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcles8.c | ||
| 4206 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcles8.c | ||
| 4207 | @@ -3,7 +3,8 @@ | ||
| 4208 | |||
| 4209 | /* { dg-do assemble } */ | ||
| 4210 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4211 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4212 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4213 | +/* { dg-add-options arm_neon } */ | ||
| 4214 | |||
| 4215 | #include "arm_neon.h" | ||
| 4216 | |||
| 4217 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleu16.c | ||
| 4218 | =================================================================== | ||
| 4219 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleu16.c | ||
| 4220 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleu16.c | ||
| 4221 | @@ -3,7 +3,8 @@ | ||
| 4222 | |||
| 4223 | /* { dg-do assemble } */ | ||
| 4224 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4225 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4226 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4227 | +/* { dg-add-options arm_neon } */ | ||
| 4228 | |||
| 4229 | #include "arm_neon.h" | ||
| 4230 | |||
| 4231 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleu32.c | ||
| 4232 | =================================================================== | ||
| 4233 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleu32.c | ||
| 4234 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleu32.c | ||
| 4235 | @@ -3,7 +3,8 @@ | ||
| 4236 | |||
| 4237 | /* { dg-do assemble } */ | ||
| 4238 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4239 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4240 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4241 | +/* { dg-add-options arm_neon } */ | ||
| 4242 | |||
| 4243 | #include "arm_neon.h" | ||
| 4244 | |||
| 4245 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleu8.c | ||
| 4246 | =================================================================== | ||
| 4247 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcleu8.c | ||
| 4248 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcleu8.c | ||
| 4249 | @@ -3,7 +3,8 @@ | ||
| 4250 | |||
| 4251 | /* { dg-do assemble } */ | ||
| 4252 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4253 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4254 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4255 | +/* { dg-add-options arm_neon } */ | ||
| 4256 | |||
| 4257 | #include "arm_neon.h" | ||
| 4258 | |||
| 4259 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c | ||
| 4260 | =================================================================== | ||
| 4261 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c | ||
| 4262 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c | ||
| 4263 | @@ -3,7 +3,8 @@ | ||
| 4264 | |||
| 4265 | /* { dg-do assemble } */ | ||
| 4266 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4267 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4268 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4269 | +/* { dg-add-options arm_neon } */ | ||
| 4270 | |||
| 4271 | #include "arm_neon.h" | ||
| 4272 | |||
| 4273 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c | ||
| 4274 | =================================================================== | ||
| 4275 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c | ||
| 4276 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c | ||
| 4277 | @@ -3,7 +3,8 @@ | ||
| 4278 | |||
| 4279 | /* { dg-do assemble } */ | ||
| 4280 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4281 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4282 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4283 | +/* { dg-add-options arm_neon } */ | ||
| 4284 | |||
| 4285 | #include "arm_neon.h" | ||
| 4286 | |||
| 4287 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c | ||
| 4288 | =================================================================== | ||
| 4289 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c | ||
| 4290 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c | ||
| 4291 | @@ -3,7 +3,8 @@ | ||
| 4292 | |||
| 4293 | /* { dg-do assemble } */ | ||
| 4294 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4295 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4296 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4297 | +/* { dg-add-options arm_neon } */ | ||
| 4298 | |||
| 4299 | #include "arm_neon.h" | ||
| 4300 | |||
| 4301 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclss16.c | ||
| 4302 | =================================================================== | ||
| 4303 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclss16.c | ||
| 4304 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclss16.c | ||
| 4305 | @@ -3,7 +3,8 @@ | ||
| 4306 | |||
| 4307 | /* { dg-do assemble } */ | ||
| 4308 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4309 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4310 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4311 | +/* { dg-add-options arm_neon } */ | ||
| 4312 | |||
| 4313 | #include "arm_neon.h" | ||
| 4314 | |||
| 4315 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclss32.c | ||
| 4316 | =================================================================== | ||
| 4317 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclss32.c | ||
| 4318 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclss32.c | ||
| 4319 | @@ -3,7 +3,8 @@ | ||
| 4320 | |||
| 4321 | /* { dg-do assemble } */ | ||
| 4322 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4323 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4324 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4325 | +/* { dg-add-options arm_neon } */ | ||
| 4326 | |||
| 4327 | #include "arm_neon.h" | ||
| 4328 | |||
| 4329 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclss8.c | ||
| 4330 | =================================================================== | ||
| 4331 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclss8.c | ||
| 4332 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclss8.c | ||
| 4333 | @@ -3,7 +3,8 @@ | ||
| 4334 | |||
| 4335 | /* { dg-do assemble } */ | ||
| 4336 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4337 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4338 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4339 | +/* { dg-add-options arm_neon } */ | ||
| 4340 | |||
| 4341 | #include "arm_neon.h" | ||
| 4342 | |||
| 4343 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c | ||
| 4344 | =================================================================== | ||
| 4345 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c | ||
| 4346 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c | ||
| 4347 | @@ -3,7 +3,8 @@ | ||
| 4348 | |||
| 4349 | /* { dg-do assemble } */ | ||
| 4350 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4351 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4352 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4353 | +/* { dg-add-options arm_neon } */ | ||
| 4354 | |||
| 4355 | #include "arm_neon.h" | ||
| 4356 | |||
| 4357 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c | ||
| 4358 | =================================================================== | ||
| 4359 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c | ||
| 4360 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c | ||
| 4361 | @@ -3,7 +3,8 @@ | ||
| 4362 | |||
| 4363 | /* { dg-do assemble } */ | ||
| 4364 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4365 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4366 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4367 | +/* { dg-add-options arm_neon } */ | ||
| 4368 | |||
| 4369 | #include "arm_neon.h" | ||
| 4370 | |||
| 4371 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c | ||
| 4372 | =================================================================== | ||
| 4373 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c | ||
| 4374 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c | ||
| 4375 | @@ -3,7 +3,8 @@ | ||
| 4376 | |||
| 4377 | /* { dg-do assemble } */ | ||
| 4378 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4379 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4380 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4381 | +/* { dg-add-options arm_neon } */ | ||
| 4382 | |||
| 4383 | #include "arm_neon.h" | ||
| 4384 | |||
| 4385 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c | ||
| 4386 | =================================================================== | ||
| 4387 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c | ||
| 4388 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c | ||
| 4389 | @@ -3,7 +3,8 @@ | ||
| 4390 | |||
| 4391 | /* { dg-do assemble } */ | ||
| 4392 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4393 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4394 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4395 | +/* { dg-add-options arm_neon } */ | ||
| 4396 | |||
| 4397 | #include "arm_neon.h" | ||
| 4398 | |||
| 4399 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c | ||
| 4400 | =================================================================== | ||
| 4401 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c | ||
| 4402 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c | ||
| 4403 | @@ -3,7 +3,8 @@ | ||
| 4404 | |||
| 4405 | /* { dg-do assemble } */ | ||
| 4406 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4407 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4408 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4409 | +/* { dg-add-options arm_neon } */ | ||
| 4410 | |||
| 4411 | #include "arm_neon.h" | ||
| 4412 | |||
| 4413 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c | ||
| 4414 | =================================================================== | ||
| 4415 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c | ||
| 4416 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c | ||
| 4417 | @@ -3,7 +3,8 @@ | ||
| 4418 | |||
| 4419 | /* { dg-do assemble } */ | ||
| 4420 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4421 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4422 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4423 | +/* { dg-add-options arm_neon } */ | ||
| 4424 | |||
| 4425 | #include "arm_neon.h" | ||
| 4426 | |||
| 4427 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c | ||
| 4428 | =================================================================== | ||
| 4429 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c | ||
| 4430 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c | ||
| 4431 | @@ -3,7 +3,8 @@ | ||
| 4432 | |||
| 4433 | /* { dg-do assemble } */ | ||
| 4434 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4435 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4436 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4437 | +/* { dg-add-options arm_neon } */ | ||
| 4438 | |||
| 4439 | #include "arm_neon.h" | ||
| 4440 | |||
| 4441 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltf32.c | ||
| 4442 | =================================================================== | ||
| 4443 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltf32.c | ||
| 4444 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltf32.c | ||
| 4445 | @@ -3,7 +3,8 @@ | ||
| 4446 | |||
| 4447 | /* { dg-do assemble } */ | ||
| 4448 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4449 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4450 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4451 | +/* { dg-add-options arm_neon } */ | ||
| 4452 | |||
| 4453 | #include "arm_neon.h" | ||
| 4454 | |||
| 4455 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclts16.c | ||
| 4456 | =================================================================== | ||
| 4457 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclts16.c | ||
| 4458 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclts16.c | ||
| 4459 | @@ -3,7 +3,8 @@ | ||
| 4460 | |||
| 4461 | /* { dg-do assemble } */ | ||
| 4462 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4463 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4464 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4465 | +/* { dg-add-options arm_neon } */ | ||
| 4466 | |||
| 4467 | #include "arm_neon.h" | ||
| 4468 | |||
| 4469 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclts32.c | ||
| 4470 | =================================================================== | ||
| 4471 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclts32.c | ||
| 4472 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclts32.c | ||
| 4473 | @@ -3,7 +3,8 @@ | ||
| 4474 | |||
| 4475 | /* { dg-do assemble } */ | ||
| 4476 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4477 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4478 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4479 | +/* { dg-add-options arm_neon } */ | ||
| 4480 | |||
| 4481 | #include "arm_neon.h" | ||
| 4482 | |||
| 4483 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclts8.c | ||
| 4484 | =================================================================== | ||
| 4485 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclts8.c | ||
| 4486 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclts8.c | ||
| 4487 | @@ -3,7 +3,8 @@ | ||
| 4488 | |||
| 4489 | /* { dg-do assemble } */ | ||
| 4490 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4491 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4492 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4493 | +/* { dg-add-options arm_neon } */ | ||
| 4494 | |||
| 4495 | #include "arm_neon.h" | ||
| 4496 | |||
| 4497 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltu16.c | ||
| 4498 | =================================================================== | ||
| 4499 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltu16.c | ||
| 4500 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltu16.c | ||
| 4501 | @@ -3,7 +3,8 @@ | ||
| 4502 | |||
| 4503 | /* { dg-do assemble } */ | ||
| 4504 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4505 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4506 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4507 | +/* { dg-add-options arm_neon } */ | ||
| 4508 | |||
| 4509 | #include "arm_neon.h" | ||
| 4510 | |||
| 4511 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltu32.c | ||
| 4512 | =================================================================== | ||
| 4513 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltu32.c | ||
| 4514 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltu32.c | ||
| 4515 | @@ -3,7 +3,8 @@ | ||
| 4516 | |||
| 4517 | /* { dg-do assemble } */ | ||
| 4518 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4519 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4520 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4521 | +/* { dg-add-options arm_neon } */ | ||
| 4522 | |||
| 4523 | #include "arm_neon.h" | ||
| 4524 | |||
| 4525 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltu8.c | ||
| 4526 | =================================================================== | ||
| 4527 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcltu8.c | ||
| 4528 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcltu8.c | ||
| 4529 | @@ -3,7 +3,8 @@ | ||
| 4530 | |||
| 4531 | /* { dg-do assemble } */ | ||
| 4532 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4533 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4534 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4535 | +/* { dg-add-options arm_neon } */ | ||
| 4536 | |||
| 4537 | #include "arm_neon.h" | ||
| 4538 | |||
| 4539 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c | ||
| 4540 | =================================================================== | ||
| 4541 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c | ||
| 4542 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c | ||
| 4543 | @@ -3,7 +3,8 @@ | ||
| 4544 | |||
| 4545 | /* { dg-do assemble } */ | ||
| 4546 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4547 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4548 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4549 | +/* { dg-add-options arm_neon } */ | ||
| 4550 | |||
| 4551 | #include "arm_neon.h" | ||
| 4552 | |||
| 4553 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c | ||
| 4554 | =================================================================== | ||
| 4555 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c | ||
| 4556 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c | ||
| 4557 | @@ -3,7 +3,8 @@ | ||
| 4558 | |||
| 4559 | /* { dg-do assemble } */ | ||
| 4560 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4561 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4562 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4563 | +/* { dg-add-options arm_neon } */ | ||
| 4564 | |||
| 4565 | #include "arm_neon.h" | ||
| 4566 | |||
| 4567 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c | ||
| 4568 | =================================================================== | ||
| 4569 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c | ||
| 4570 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c | ||
| 4571 | @@ -3,7 +3,8 @@ | ||
| 4572 | |||
| 4573 | /* { dg-do assemble } */ | ||
| 4574 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4575 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4576 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4577 | +/* { dg-add-options arm_neon } */ | ||
| 4578 | |||
| 4579 | #include "arm_neon.h" | ||
| 4580 | |||
| 4581 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c | ||
| 4582 | =================================================================== | ||
| 4583 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c | ||
| 4584 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c | ||
| 4585 | @@ -3,7 +3,8 @@ | ||
| 4586 | |||
| 4587 | /* { dg-do assemble } */ | ||
| 4588 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4589 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4590 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4591 | +/* { dg-add-options arm_neon } */ | ||
| 4592 | |||
| 4593 | #include "arm_neon.h" | ||
| 4594 | |||
| 4595 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c | ||
| 4596 | =================================================================== | ||
| 4597 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c | ||
| 4598 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c | ||
| 4599 | @@ -3,7 +3,8 @@ | ||
| 4600 | |||
| 4601 | /* { dg-do assemble } */ | ||
| 4602 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4603 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4604 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4605 | +/* { dg-add-options arm_neon } */ | ||
| 4606 | |||
| 4607 | #include "arm_neon.h" | ||
| 4608 | |||
| 4609 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c | ||
| 4610 | =================================================================== | ||
| 4611 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c | ||
| 4612 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c | ||
| 4613 | @@ -3,7 +3,8 @@ | ||
| 4614 | |||
| 4615 | /* { dg-do assemble } */ | ||
| 4616 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4617 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4618 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4619 | +/* { dg-add-options arm_neon } */ | ||
| 4620 | |||
| 4621 | #include "arm_neon.h" | ||
| 4622 | |||
| 4623 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzs16.c | ||
| 4624 | =================================================================== | ||
| 4625 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzs16.c | ||
| 4626 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzs16.c | ||
| 4627 | @@ -3,7 +3,8 @@ | ||
| 4628 | |||
| 4629 | /* { dg-do assemble } */ | ||
| 4630 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4631 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4632 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4633 | +/* { dg-add-options arm_neon } */ | ||
| 4634 | |||
| 4635 | #include "arm_neon.h" | ||
| 4636 | |||
| 4637 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzs32.c | ||
| 4638 | =================================================================== | ||
| 4639 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzs32.c | ||
| 4640 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzs32.c | ||
| 4641 | @@ -3,7 +3,8 @@ | ||
| 4642 | |||
| 4643 | /* { dg-do assemble } */ | ||
| 4644 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4645 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4646 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4647 | +/* { dg-add-options arm_neon } */ | ||
| 4648 | |||
| 4649 | #include "arm_neon.h" | ||
| 4650 | |||
| 4651 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzs8.c | ||
| 4652 | =================================================================== | ||
| 4653 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzs8.c | ||
| 4654 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzs8.c | ||
| 4655 | @@ -3,7 +3,8 @@ | ||
| 4656 | |||
| 4657 | /* { dg-do assemble } */ | ||
| 4658 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4659 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4660 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4661 | +/* { dg-add-options arm_neon } */ | ||
| 4662 | |||
| 4663 | #include "arm_neon.h" | ||
| 4664 | |||
| 4665 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzu16.c | ||
| 4666 | =================================================================== | ||
| 4667 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzu16.c | ||
| 4668 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzu16.c | ||
| 4669 | @@ -3,7 +3,8 @@ | ||
| 4670 | |||
| 4671 | /* { dg-do assemble } */ | ||
| 4672 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4673 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4674 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4675 | +/* { dg-add-options arm_neon } */ | ||
| 4676 | |||
| 4677 | #include "arm_neon.h" | ||
| 4678 | |||
| 4679 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzu32.c | ||
| 4680 | =================================================================== | ||
| 4681 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzu32.c | ||
| 4682 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzu32.c | ||
| 4683 | @@ -3,7 +3,8 @@ | ||
| 4684 | |||
| 4685 | /* { dg-do assemble } */ | ||
| 4686 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4687 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4688 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4689 | +/* { dg-add-options arm_neon } */ | ||
| 4690 | |||
| 4691 | #include "arm_neon.h" | ||
| 4692 | |||
| 4693 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzu8.c | ||
| 4694 | =================================================================== | ||
| 4695 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vclzu8.c | ||
| 4696 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vclzu8.c | ||
| 4697 | @@ -3,7 +3,8 @@ | ||
| 4698 | |||
| 4699 | /* { dg-do assemble } */ | ||
| 4700 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4701 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4702 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4703 | +/* { dg-add-options arm_neon } */ | ||
| 4704 | |||
| 4705 | #include "arm_neon.h" | ||
| 4706 | |||
| 4707 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c | ||
| 4708 | =================================================================== | ||
| 4709 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c | ||
| 4710 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c | ||
| 4711 | @@ -3,7 +3,8 @@ | ||
| 4712 | |||
| 4713 | /* { dg-do assemble } */ | ||
| 4714 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4715 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4716 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4717 | +/* { dg-add-options arm_neon } */ | ||
| 4718 | |||
| 4719 | #include "arm_neon.h" | ||
| 4720 | |||
| 4721 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c | ||
| 4722 | =================================================================== | ||
| 4723 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c | ||
| 4724 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c | ||
| 4725 | @@ -3,7 +3,8 @@ | ||
| 4726 | |||
| 4727 | /* { dg-do assemble } */ | ||
| 4728 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4729 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4730 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4731 | +/* { dg-add-options arm_neon } */ | ||
| 4732 | |||
| 4733 | #include "arm_neon.h" | ||
| 4734 | |||
| 4735 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c | ||
| 4736 | =================================================================== | ||
| 4737 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c | ||
| 4738 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c | ||
| 4739 | @@ -3,7 +3,8 @@ | ||
| 4740 | |||
| 4741 | /* { dg-do assemble } */ | ||
| 4742 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4743 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4744 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4745 | +/* { dg-add-options arm_neon } */ | ||
| 4746 | |||
| 4747 | #include "arm_neon.h" | ||
| 4748 | |||
| 4749 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntp8.c | ||
| 4750 | =================================================================== | ||
| 4751 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcntp8.c | ||
| 4752 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntp8.c | ||
| 4753 | @@ -3,7 +3,8 @@ | ||
| 4754 | |||
| 4755 | /* { dg-do assemble } */ | ||
| 4756 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4757 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4758 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4759 | +/* { dg-add-options arm_neon } */ | ||
| 4760 | |||
| 4761 | #include "arm_neon.h" | ||
| 4762 | |||
| 4763 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcnts8.c | ||
| 4764 | =================================================================== | ||
| 4765 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcnts8.c | ||
| 4766 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcnts8.c | ||
| 4767 | @@ -3,7 +3,8 @@ | ||
| 4768 | |||
| 4769 | /* { dg-do assemble } */ | ||
| 4770 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4771 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4772 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4773 | +/* { dg-add-options arm_neon } */ | ||
| 4774 | |||
| 4775 | #include "arm_neon.h" | ||
| 4776 | |||
| 4777 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntu8.c | ||
| 4778 | =================================================================== | ||
| 4779 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcntu8.c | ||
| 4780 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcntu8.c | ||
| 4781 | @@ -3,7 +3,8 @@ | ||
| 4782 | |||
| 4783 | /* { dg-do assemble } */ | ||
| 4784 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4785 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4786 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4787 | +/* { dg-add-options arm_neon } */ | ||
| 4788 | |||
| 4789 | #include "arm_neon.h" | ||
| 4790 | |||
| 4791 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c | ||
| 4792 | =================================================================== | ||
| 4793 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c | ||
| 4794 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c | ||
| 4795 | @@ -3,7 +3,8 @@ | ||
| 4796 | |||
| 4797 | /* { dg-do assemble } */ | ||
| 4798 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4799 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4800 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4801 | +/* { dg-add-options arm_neon } */ | ||
| 4802 | |||
| 4803 | #include "arm_neon.h" | ||
| 4804 | |||
| 4805 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c | ||
| 4806 | =================================================================== | ||
| 4807 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c | ||
| 4808 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c | ||
| 4809 | @@ -3,7 +3,8 @@ | ||
| 4810 | |||
| 4811 | /* { dg-do assemble } */ | ||
| 4812 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4813 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4814 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4815 | +/* { dg-add-options arm_neon } */ | ||
| 4816 | |||
| 4817 | #include "arm_neon.h" | ||
| 4818 | |||
| 4819 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c | ||
| 4820 | =================================================================== | ||
| 4821 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c | ||
| 4822 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c | ||
| 4823 | @@ -3,7 +3,8 @@ | ||
| 4824 | |||
| 4825 | /* { dg-do assemble } */ | ||
| 4826 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4827 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4828 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4829 | +/* { dg-add-options arm_neon } */ | ||
| 4830 | |||
| 4831 | #include "arm_neon.h" | ||
| 4832 | |||
| 4833 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines16.c | ||
| 4834 | =================================================================== | ||
| 4835 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombines16.c | ||
| 4836 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines16.c | ||
| 4837 | @@ -3,7 +3,8 @@ | ||
| 4838 | |||
| 4839 | /* { dg-do assemble } */ | ||
| 4840 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4841 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4842 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4843 | +/* { dg-add-options arm_neon } */ | ||
| 4844 | |||
| 4845 | #include "arm_neon.h" | ||
| 4846 | |||
| 4847 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines32.c | ||
| 4848 | =================================================================== | ||
| 4849 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombines32.c | ||
| 4850 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines32.c | ||
| 4851 | @@ -3,7 +3,8 @@ | ||
| 4852 | |||
| 4853 | /* { dg-do assemble } */ | ||
| 4854 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4855 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4856 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4857 | +/* { dg-add-options arm_neon } */ | ||
| 4858 | |||
| 4859 | #include "arm_neon.h" | ||
| 4860 | |||
| 4861 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines64.c | ||
| 4862 | =================================================================== | ||
| 4863 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombines64.c | ||
| 4864 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines64.c | ||
| 4865 | @@ -3,7 +3,8 @@ | ||
| 4866 | |||
| 4867 | /* { dg-do assemble } */ | ||
| 4868 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4869 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4870 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4871 | +/* { dg-add-options arm_neon } */ | ||
| 4872 | |||
| 4873 | #include "arm_neon.h" | ||
| 4874 | |||
| 4875 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines8.c | ||
| 4876 | =================================================================== | ||
| 4877 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombines8.c | ||
| 4878 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombines8.c | ||
| 4879 | @@ -3,7 +3,8 @@ | ||
| 4880 | |||
| 4881 | /* { dg-do assemble } */ | ||
| 4882 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4883 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4884 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4885 | +/* { dg-add-options arm_neon } */ | ||
| 4886 | |||
| 4887 | #include "arm_neon.h" | ||
| 4888 | |||
| 4889 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c | ||
| 4890 | =================================================================== | ||
| 4891 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c | ||
| 4892 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c | ||
| 4893 | @@ -3,7 +3,8 @@ | ||
| 4894 | |||
| 4895 | /* { dg-do assemble } */ | ||
| 4896 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4897 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4898 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4899 | +/* { dg-add-options arm_neon } */ | ||
| 4900 | |||
| 4901 | #include "arm_neon.h" | ||
| 4902 | |||
| 4903 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c | ||
| 4904 | =================================================================== | ||
| 4905 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c | ||
| 4906 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c | ||
| 4907 | @@ -3,7 +3,8 @@ | ||
| 4908 | |||
| 4909 | /* { dg-do assemble } */ | ||
| 4910 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4911 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4912 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4913 | +/* { dg-add-options arm_neon } */ | ||
| 4914 | |||
| 4915 | #include "arm_neon.h" | ||
| 4916 | |||
| 4917 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c | ||
| 4918 | =================================================================== | ||
| 4919 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c | ||
| 4920 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c | ||
| 4921 | @@ -3,7 +3,8 @@ | ||
| 4922 | |||
| 4923 | /* { dg-do assemble } */ | ||
| 4924 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4925 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4926 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4927 | +/* { dg-add-options arm_neon } */ | ||
| 4928 | |||
| 4929 | #include "arm_neon.h" | ||
| 4930 | |||
| 4931 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c | ||
| 4932 | =================================================================== | ||
| 4933 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c | ||
| 4934 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c | ||
| 4935 | @@ -3,7 +3,8 @@ | ||
| 4936 | |||
| 4937 | /* { dg-do assemble } */ | ||
| 4938 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4939 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4940 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4941 | +/* { dg-add-options arm_neon } */ | ||
| 4942 | |||
| 4943 | #include "arm_neon.h" | ||
| 4944 | |||
| 4945 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c | ||
| 4946 | =================================================================== | ||
| 4947 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c | ||
| 4948 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c | ||
| 4949 | @@ -3,7 +3,8 @@ | ||
| 4950 | |||
| 4951 | /* { dg-do assemble } */ | ||
| 4952 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4953 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4954 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4955 | +/* { dg-add-options arm_neon } */ | ||
| 4956 | |||
| 4957 | #include "arm_neon.h" | ||
| 4958 | |||
| 4959 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c | ||
| 4960 | =================================================================== | ||
| 4961 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c | ||
| 4962 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c | ||
| 4963 | @@ -3,7 +3,8 @@ | ||
| 4964 | |||
| 4965 | /* { dg-do assemble } */ | ||
| 4966 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4967 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4968 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4969 | +/* { dg-add-options arm_neon } */ | ||
| 4970 | |||
| 4971 | #include "arm_neon.h" | ||
| 4972 | |||
| 4973 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c | ||
| 4974 | =================================================================== | ||
| 4975 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c | ||
| 4976 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c | ||
| 4977 | @@ -3,7 +3,8 @@ | ||
| 4978 | |||
| 4979 | /* { dg-do assemble } */ | ||
| 4980 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4981 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4982 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4983 | +/* { dg-add-options arm_neon } */ | ||
| 4984 | |||
| 4985 | #include "arm_neon.h" | ||
| 4986 | |||
| 4987 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates16.c | ||
| 4988 | =================================================================== | ||
| 4989 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreates16.c | ||
| 4990 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates16.c | ||
| 4991 | @@ -3,7 +3,8 @@ | ||
| 4992 | |||
| 4993 | /* { dg-do assemble } */ | ||
| 4994 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 4995 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 4996 | +/* { dg-options "-save-temps -O0" } */ | ||
| 4997 | +/* { dg-add-options arm_neon } */ | ||
| 4998 | |||
| 4999 | #include "arm_neon.h" | ||
| 5000 | |||
| 5001 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates32.c | ||
| 5002 | =================================================================== | ||
| 5003 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreates32.c | ||
| 5004 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates32.c | ||
| 5005 | @@ -3,7 +3,8 @@ | ||
| 5006 | |||
| 5007 | /* { dg-do assemble } */ | ||
| 5008 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5009 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5010 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5011 | +/* { dg-add-options arm_neon } */ | ||
| 5012 | |||
| 5013 | #include "arm_neon.h" | ||
| 5014 | |||
| 5015 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates64.c | ||
| 5016 | =================================================================== | ||
| 5017 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreates64.c | ||
| 5018 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates64.c | ||
| 5019 | @@ -3,7 +3,8 @@ | ||
| 5020 | |||
| 5021 | /* { dg-do assemble } */ | ||
| 5022 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5023 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5024 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5025 | +/* { dg-add-options arm_neon } */ | ||
| 5026 | |||
| 5027 | #include "arm_neon.h" | ||
| 5028 | |||
| 5029 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates8.c | ||
| 5030 | =================================================================== | ||
| 5031 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreates8.c | ||
| 5032 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreates8.c | ||
| 5033 | @@ -3,7 +3,8 @@ | ||
| 5034 | |||
| 5035 | /* { dg-do assemble } */ | ||
| 5036 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5037 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5038 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5039 | +/* { dg-add-options arm_neon } */ | ||
| 5040 | |||
| 5041 | #include "arm_neon.h" | ||
| 5042 | |||
| 5043 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c | ||
| 5044 | =================================================================== | ||
| 5045 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c | ||
| 5046 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c | ||
| 5047 | @@ -3,7 +3,8 @@ | ||
| 5048 | |||
| 5049 | /* { dg-do assemble } */ | ||
| 5050 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5051 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5052 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5053 | +/* { dg-add-options arm_neon } */ | ||
| 5054 | |||
| 5055 | #include "arm_neon.h" | ||
| 5056 | |||
| 5057 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c | ||
| 5058 | =================================================================== | ||
| 5059 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c | ||
| 5060 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c | ||
| 5061 | @@ -3,7 +3,8 @@ | ||
| 5062 | |||
| 5063 | /* { dg-do assemble } */ | ||
| 5064 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5065 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5066 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5067 | +/* { dg-add-options arm_neon } */ | ||
| 5068 | |||
| 5069 | #include "arm_neon.h" | ||
| 5070 | |||
| 5071 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c | ||
| 5072 | =================================================================== | ||
| 5073 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c | ||
| 5074 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c | ||
| 5075 | @@ -3,7 +3,8 @@ | ||
| 5076 | |||
| 5077 | /* { dg-do assemble } */ | ||
| 5078 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5079 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5080 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5081 | +/* { dg-add-options arm_neon } */ | ||
| 5082 | |||
| 5083 | #include "arm_neon.h" | ||
| 5084 | |||
| 5085 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c | ||
| 5086 | =================================================================== | ||
| 5087 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c | ||
| 5088 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c | ||
| 5089 | @@ -3,7 +3,8 @@ | ||
| 5090 | |||
| 5091 | /* { dg-do assemble } */ | ||
| 5092 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5093 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5094 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5095 | +/* { dg-add-options arm_neon } */ | ||
| 5096 | |||
| 5097 | #include "arm_neon.h" | ||
| 5098 | |||
| 5099 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c | ||
| 5100 | =================================================================== | ||
| 5101 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c | ||
| 5102 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c | ||
| 5103 | @@ -3,7 +3,8 @@ | ||
| 5104 | |||
| 5105 | /* { dg-do assemble } */ | ||
| 5106 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5107 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5108 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5109 | +/* { dg-add-options arm_neon } */ | ||
| 5110 | |||
| 5111 | #include "arm_neon.h" | ||
| 5112 | |||
| 5113 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c | ||
| 5114 | =================================================================== | ||
| 5115 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c | ||
| 5116 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c | ||
| 5117 | @@ -3,7 +3,8 @@ | ||
| 5118 | |||
| 5119 | /* { dg-do assemble } */ | ||
| 5120 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5121 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5122 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5123 | +/* { dg-add-options arm_neon } */ | ||
| 5124 | |||
| 5125 | #include "arm_neon.h" | ||
| 5126 | |||
| 5127 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c | ||
| 5128 | =================================================================== | ||
| 5129 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c | ||
| 5130 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c | ||
| 5131 | @@ -3,7 +3,8 @@ | ||
| 5132 | |||
| 5133 | /* { dg-do assemble } */ | ||
| 5134 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5135 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5136 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5137 | +/* { dg-add-options arm_neon } */ | ||
| 5138 | |||
| 5139 | #include "arm_neon.h" | ||
| 5140 | |||
| 5141 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c | ||
| 5142 | =================================================================== | ||
| 5143 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c | ||
| 5144 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c | ||
| 5145 | @@ -3,7 +3,8 @@ | ||
| 5146 | |||
| 5147 | /* { dg-do assemble } */ | ||
| 5148 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5149 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5150 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5151 | +/* { dg-add-options arm_neon } */ | ||
| 5152 | |||
| 5153 | #include "arm_neon.h" | ||
| 5154 | |||
| 5155 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c | ||
| 5156 | =================================================================== | ||
| 5157 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c | ||
| 5158 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c | ||
| 5159 | @@ -3,7 +3,8 @@ | ||
| 5160 | |||
| 5161 | /* { dg-do assemble } */ | ||
| 5162 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5163 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5164 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5165 | +/* { dg-add-options arm_neon } */ | ||
| 5166 | |||
| 5167 | #include "arm_neon.h" | ||
| 5168 | |||
| 5169 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c | ||
| 5170 | =================================================================== | ||
| 5171 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c | ||
| 5172 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c | ||
| 5173 | @@ -3,7 +3,8 @@ | ||
| 5174 | |||
| 5175 | /* { dg-do assemble } */ | ||
| 5176 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5177 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5178 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5179 | +/* { dg-add-options arm_neon } */ | ||
| 5180 | |||
| 5181 | #include "arm_neon.h" | ||
| 5182 | |||
| 5183 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c | ||
| 5184 | =================================================================== | ||
| 5185 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c | ||
| 5186 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c | ||
| 5187 | @@ -3,7 +3,8 @@ | ||
| 5188 | |||
| 5189 | /* { dg-do assemble } */ | ||
| 5190 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5191 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5192 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5193 | +/* { dg-add-options arm_neon } */ | ||
| 5194 | |||
| 5195 | #include "arm_neon.h" | ||
| 5196 | |||
| 5197 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c | ||
| 5198 | =================================================================== | ||
| 5199 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c | ||
| 5200 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c | ||
| 5201 | @@ -3,7 +3,8 @@ | ||
| 5202 | |||
| 5203 | /* { dg-do assemble } */ | ||
| 5204 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5205 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5206 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5207 | +/* { dg-add-options arm_neon } */ | ||
| 5208 | |||
| 5209 | #include "arm_neon.h" | ||
| 5210 | |||
| 5211 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c | ||
| 5212 | =================================================================== | ||
| 5213 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c | ||
| 5214 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c | ||
| 5215 | @@ -3,7 +3,8 @@ | ||
| 5216 | |||
| 5217 | /* { dg-do assemble } */ | ||
| 5218 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5219 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5220 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5221 | +/* { dg-add-options arm_neon } */ | ||
| 5222 | |||
| 5223 | #include "arm_neon.h" | ||
| 5224 | |||
| 5225 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c | ||
| 5226 | =================================================================== | ||
| 5227 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c | ||
| 5228 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c | ||
| 5229 | @@ -3,7 +3,8 @@ | ||
| 5230 | |||
| 5231 | /* { dg-do assemble } */ | ||
| 5232 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5233 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5234 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5235 | +/* { dg-add-options arm_neon } */ | ||
| 5236 | |||
| 5237 | #include "arm_neon.h" | ||
| 5238 | |||
| 5239 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c | ||
| 5240 | =================================================================== | ||
| 5241 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c | ||
| 5242 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c | ||
| 5243 | @@ -3,7 +3,8 @@ | ||
| 5244 | |||
| 5245 | /* { dg-do assemble } */ | ||
| 5246 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5247 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5248 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5249 | +/* { dg-add-options arm_neon } */ | ||
| 5250 | |||
| 5251 | #include "arm_neon.h" | ||
| 5252 | |||
| 5253 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c | ||
| 5254 | =================================================================== | ||
| 5255 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c | ||
| 5256 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c | ||
| 5257 | @@ -3,7 +3,8 @@ | ||
| 5258 | |||
| 5259 | /* { dg-do assemble } */ | ||
| 5260 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5261 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5262 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5263 | +/* { dg-add-options arm_neon } */ | ||
| 5264 | |||
| 5265 | #include "arm_neon.h" | ||
| 5266 | |||
| 5267 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c | ||
| 5268 | =================================================================== | ||
| 5269 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c | ||
| 5270 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c | ||
| 5271 | @@ -3,7 +3,8 @@ | ||
| 5272 | |||
| 5273 | /* { dg-do assemble } */ | ||
| 5274 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5275 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5276 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5277 | +/* { dg-add-options arm_neon } */ | ||
| 5278 | |||
| 5279 | #include "arm_neon.h" | ||
| 5280 | |||
| 5281 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c | ||
| 5282 | =================================================================== | ||
| 5283 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c | ||
| 5284 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c | ||
| 5285 | @@ -3,7 +3,8 @@ | ||
| 5286 | |||
| 5287 | /* { dg-do assemble } */ | ||
| 5288 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5289 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5290 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5291 | +/* { dg-add-options arm_neon } */ | ||
| 5292 | |||
| 5293 | #include "arm_neon.h" | ||
| 5294 | |||
| 5295 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c | ||
| 5296 | =================================================================== | ||
| 5297 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c | ||
| 5298 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c | ||
| 5299 | @@ -3,7 +3,8 @@ | ||
| 5300 | |||
| 5301 | /* { dg-do assemble } */ | ||
| 5302 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5303 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5304 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5305 | +/* { dg-add-options arm_neon } */ | ||
| 5306 | |||
| 5307 | #include "arm_neon.h" | ||
| 5308 | |||
| 5309 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c | ||
| 5310 | =================================================================== | ||
| 5311 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c | ||
| 5312 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c | ||
| 5313 | @@ -3,7 +3,8 @@ | ||
| 5314 | |||
| 5315 | /* { dg-do assemble } */ | ||
| 5316 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5317 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5318 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5319 | +/* { dg-add-options arm_neon } */ | ||
| 5320 | |||
| 5321 | #include "arm_neon.h" | ||
| 5322 | |||
| 5323 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c | ||
| 5324 | =================================================================== | ||
| 5325 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c | ||
| 5326 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c | ||
| 5327 | @@ -3,7 +3,8 @@ | ||
| 5328 | |||
| 5329 | /* { dg-do assemble } */ | ||
| 5330 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5331 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5332 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5333 | +/* { dg-add-options arm_neon } */ | ||
| 5334 | |||
| 5335 | #include "arm_neon.h" | ||
| 5336 | |||
| 5337 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c | ||
| 5338 | =================================================================== | ||
| 5339 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c | ||
| 5340 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c | ||
| 5341 | @@ -3,7 +3,8 @@ | ||
| 5342 | |||
| 5343 | /* { dg-do assemble } */ | ||
| 5344 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5345 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5346 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5347 | +/* { dg-add-options arm_neon } */ | ||
| 5348 | |||
| 5349 | #include "arm_neon.h" | ||
| 5350 | |||
| 5351 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c | ||
| 5352 | =================================================================== | ||
| 5353 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c | ||
| 5354 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c | ||
| 5355 | @@ -3,7 +3,8 @@ | ||
| 5356 | |||
| 5357 | /* { dg-do assemble } */ | ||
| 5358 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5359 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5360 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5361 | +/* { dg-add-options arm_neon } */ | ||
| 5362 | |||
| 5363 | #include "arm_neon.h" | ||
| 5364 | |||
| 5365 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c | ||
| 5366 | =================================================================== | ||
| 5367 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c | ||
| 5368 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c | ||
| 5369 | @@ -3,7 +3,8 @@ | ||
| 5370 | |||
| 5371 | /* { dg-do assemble } */ | ||
| 5372 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5373 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5374 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5375 | +/* { dg-add-options arm_neon } */ | ||
| 5376 | |||
| 5377 | #include "arm_neon.h" | ||
| 5378 | |||
| 5379 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c | ||
| 5380 | =================================================================== | ||
| 5381 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c | ||
| 5382 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c | ||
| 5383 | @@ -3,7 +3,8 @@ | ||
| 5384 | |||
| 5385 | /* { dg-do assemble } */ | ||
| 5386 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5387 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5388 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5389 | +/* { dg-add-options arm_neon } */ | ||
| 5390 | |||
| 5391 | #include "arm_neon.h" | ||
| 5392 | |||
| 5393 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c | ||
| 5394 | =================================================================== | ||
| 5395 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c | ||
| 5396 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c | ||
| 5397 | @@ -3,7 +3,8 @@ | ||
| 5398 | |||
| 5399 | /* { dg-do assemble } */ | ||
| 5400 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5401 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5402 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5403 | +/* { dg-add-options arm_neon } */ | ||
| 5404 | |||
| 5405 | #include "arm_neon.h" | ||
| 5406 | |||
| 5407 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c | ||
| 5408 | =================================================================== | ||
| 5409 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c | ||
| 5410 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c | ||
| 5411 | @@ -3,7 +3,8 @@ | ||
| 5412 | |||
| 5413 | /* { dg-do assemble } */ | ||
| 5414 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5415 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5416 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5417 | +/* { dg-add-options arm_neon } */ | ||
| 5418 | |||
| 5419 | #include "arm_neon.h" | ||
| 5420 | |||
| 5421 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c | ||
| 5422 | =================================================================== | ||
| 5423 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c | ||
| 5424 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c | ||
| 5425 | @@ -3,7 +3,8 @@ | ||
| 5426 | |||
| 5427 | /* { dg-do assemble } */ | ||
| 5428 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5429 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5430 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5431 | +/* { dg-add-options arm_neon } */ | ||
| 5432 | |||
| 5433 | #include "arm_neon.h" | ||
| 5434 | |||
| 5435 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c | ||
| 5436 | =================================================================== | ||
| 5437 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c | ||
| 5438 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c | ||
| 5439 | @@ -3,7 +3,8 @@ | ||
| 5440 | |||
| 5441 | /* { dg-do assemble } */ | ||
| 5442 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5443 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5444 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5445 | +/* { dg-add-options arm_neon } */ | ||
| 5446 | |||
| 5447 | #include "arm_neon.h" | ||
| 5448 | |||
| 5449 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c | ||
| 5450 | =================================================================== | ||
| 5451 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c | ||
| 5452 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c | ||
| 5453 | @@ -3,7 +3,8 @@ | ||
| 5454 | |||
| 5455 | /* { dg-do assemble } */ | ||
| 5456 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5457 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5458 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5459 | +/* { dg-add-options arm_neon } */ | ||
| 5460 | |||
| 5461 | #include "arm_neon.h" | ||
| 5462 | |||
| 5463 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c | ||
| 5464 | =================================================================== | ||
| 5465 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c | ||
| 5466 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c | ||
| 5467 | @@ -3,7 +3,8 @@ | ||
| 5468 | |||
| 5469 | /* { dg-do assemble } */ | ||
| 5470 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5471 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5472 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5473 | +/* { dg-add-options arm_neon } */ | ||
| 5474 | |||
| 5475 | #include "arm_neon.h" | ||
| 5476 | |||
| 5477 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c | ||
| 5478 | =================================================================== | ||
| 5479 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c | ||
| 5480 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c | ||
| 5481 | @@ -3,7 +3,8 @@ | ||
| 5482 | |||
| 5483 | /* { dg-do assemble } */ | ||
| 5484 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5485 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5486 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5487 | +/* { dg-add-options arm_neon } */ | ||
| 5488 | |||
| 5489 | #include "arm_neon.h" | ||
| 5490 | |||
| 5491 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c | ||
| 5492 | =================================================================== | ||
| 5493 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c | ||
| 5494 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c | ||
| 5495 | @@ -3,7 +3,8 @@ | ||
| 5496 | |||
| 5497 | /* { dg-do assemble } */ | ||
| 5498 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5499 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5500 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5501 | +/* { dg-add-options arm_neon } */ | ||
| 5502 | |||
| 5503 | #include "arm_neon.h" | ||
| 5504 | |||
| 5505 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c | ||
| 5506 | =================================================================== | ||
| 5507 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c | ||
| 5508 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c | ||
| 5509 | @@ -3,7 +3,8 @@ | ||
| 5510 | |||
| 5511 | /* { dg-do assemble } */ | ||
| 5512 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5513 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5514 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5515 | +/* { dg-add-options arm_neon } */ | ||
| 5516 | |||
| 5517 | #include "arm_neon.h" | ||
| 5518 | |||
| 5519 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c | ||
| 5520 | =================================================================== | ||
| 5521 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c | ||
| 5522 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c | ||
| 5523 | @@ -3,7 +3,8 @@ | ||
| 5524 | |||
| 5525 | /* { dg-do assemble } */ | ||
| 5526 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5527 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5528 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5529 | +/* { dg-add-options arm_neon } */ | ||
| 5530 | |||
| 5531 | #include "arm_neon.h" | ||
| 5532 | |||
| 5533 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c | ||
| 5534 | =================================================================== | ||
| 5535 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c | ||
| 5536 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c | ||
| 5537 | @@ -3,7 +3,8 @@ | ||
| 5538 | |||
| 5539 | /* { dg-do assemble } */ | ||
| 5540 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5541 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5542 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5543 | +/* { dg-add-options arm_neon } */ | ||
| 5544 | |||
| 5545 | #include "arm_neon.h" | ||
| 5546 | |||
| 5547 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c | ||
| 5548 | =================================================================== | ||
| 5549 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c | ||
| 5550 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c | ||
| 5551 | @@ -3,7 +3,8 @@ | ||
| 5552 | |||
| 5553 | /* { dg-do assemble } */ | ||
| 5554 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5555 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5556 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5557 | +/* { dg-add-options arm_neon } */ | ||
| 5558 | |||
| 5559 | #include "arm_neon.h" | ||
| 5560 | |||
| 5561 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c | ||
| 5562 | =================================================================== | ||
| 5563 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c | ||
| 5564 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c | ||
| 5565 | @@ -3,7 +3,8 @@ | ||
| 5566 | |||
| 5567 | /* { dg-do assemble } */ | ||
| 5568 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5569 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5570 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5571 | +/* { dg-add-options arm_neon } */ | ||
| 5572 | |||
| 5573 | #include "arm_neon.h" | ||
| 5574 | |||
| 5575 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c | ||
| 5576 | =================================================================== | ||
| 5577 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c | ||
| 5578 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c | ||
| 5579 | @@ -3,7 +3,8 @@ | ||
| 5580 | |||
| 5581 | /* { dg-do assemble } */ | ||
| 5582 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5583 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5584 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5585 | +/* { dg-add-options arm_neon } */ | ||
| 5586 | |||
| 5587 | #include "arm_neon.h" | ||
| 5588 | |||
| 5589 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c | ||
| 5590 | =================================================================== | ||
| 5591 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c | ||
| 5592 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c | ||
| 5593 | @@ -3,7 +3,8 @@ | ||
| 5594 | |||
| 5595 | /* { dg-do assemble } */ | ||
| 5596 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5597 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5598 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5599 | +/* { dg-add-options arm_neon } */ | ||
| 5600 | |||
| 5601 | #include "arm_neon.h" | ||
| 5602 | |||
| 5603 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c | ||
| 5604 | =================================================================== | ||
| 5605 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c | ||
| 5606 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c | ||
| 5607 | @@ -3,7 +3,8 @@ | ||
| 5608 | |||
| 5609 | /* { dg-do assemble } */ | ||
| 5610 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5611 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5612 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5613 | +/* { dg-add-options arm_neon } */ | ||
| 5614 | |||
| 5615 | #include "arm_neon.h" | ||
| 5616 | |||
| 5617 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c | ||
| 5618 | =================================================================== | ||
| 5619 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c | ||
| 5620 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c | ||
| 5621 | @@ -3,7 +3,8 @@ | ||
| 5622 | |||
| 5623 | /* { dg-do assemble } */ | ||
| 5624 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5625 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5626 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5627 | +/* { dg-add-options arm_neon } */ | ||
| 5628 | |||
| 5629 | #include "arm_neon.h" | ||
| 5630 | |||
| 5631 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c | ||
| 5632 | =================================================================== | ||
| 5633 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c | ||
| 5634 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c | ||
| 5635 | @@ -3,7 +3,8 @@ | ||
| 5636 | |||
| 5637 | /* { dg-do assemble } */ | ||
| 5638 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5639 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5640 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5641 | +/* { dg-add-options arm_neon } */ | ||
| 5642 | |||
| 5643 | #include "arm_neon.h" | ||
| 5644 | |||
| 5645 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c | ||
| 5646 | =================================================================== | ||
| 5647 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c | ||
| 5648 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c | ||
| 5649 | @@ -3,7 +3,8 @@ | ||
| 5650 | |||
| 5651 | /* { dg-do assemble } */ | ||
| 5652 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5653 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5654 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5655 | +/* { dg-add-options arm_neon } */ | ||
| 5656 | |||
| 5657 | #include "arm_neon.h" | ||
| 5658 | |||
| 5659 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c | ||
| 5660 | =================================================================== | ||
| 5661 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c | ||
| 5662 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c | ||
| 5663 | @@ -3,7 +3,8 @@ | ||
| 5664 | |||
| 5665 | /* { dg-do assemble } */ | ||
| 5666 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5667 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5668 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5669 | +/* { dg-add-options arm_neon } */ | ||
| 5670 | |||
| 5671 | #include "arm_neon.h" | ||
| 5672 | |||
| 5673 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c | ||
| 5674 | =================================================================== | ||
| 5675 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c | ||
| 5676 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c | ||
| 5677 | @@ -3,7 +3,8 @@ | ||
| 5678 | |||
| 5679 | /* { dg-do assemble } */ | ||
| 5680 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5681 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5682 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5683 | +/* { dg-add-options arm_neon } */ | ||
| 5684 | |||
| 5685 | #include "arm_neon.h" | ||
| 5686 | |||
| 5687 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c | ||
| 5688 | =================================================================== | ||
| 5689 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c | ||
| 5690 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c | ||
| 5691 | @@ -3,7 +3,8 @@ | ||
| 5692 | |||
| 5693 | /* { dg-do assemble } */ | ||
| 5694 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5695 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5696 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5697 | +/* { dg-add-options arm_neon } */ | ||
| 5698 | |||
| 5699 | #include "arm_neon.h" | ||
| 5700 | |||
| 5701 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c | ||
| 5702 | =================================================================== | ||
| 5703 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c | ||
| 5704 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c | ||
| 5705 | @@ -3,7 +3,8 @@ | ||
| 5706 | |||
| 5707 | /* { dg-do assemble } */ | ||
| 5708 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5709 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5710 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5711 | +/* { dg-add-options arm_neon } */ | ||
| 5712 | |||
| 5713 | #include "arm_neon.h" | ||
| 5714 | |||
| 5715 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c | ||
| 5716 | =================================================================== | ||
| 5717 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c | ||
| 5718 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c | ||
| 5719 | @@ -3,7 +3,8 @@ | ||
| 5720 | |||
| 5721 | /* { dg-do assemble } */ | ||
| 5722 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5723 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5724 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5725 | +/* { dg-add-options arm_neon } */ | ||
| 5726 | |||
| 5727 | #include "arm_neon.h" | ||
| 5728 | |||
| 5729 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c | ||
| 5730 | =================================================================== | ||
| 5731 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c | ||
| 5732 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c | ||
| 5733 | @@ -3,7 +3,8 @@ | ||
| 5734 | |||
| 5735 | /* { dg-do assemble } */ | ||
| 5736 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5737 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5738 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5739 | +/* { dg-add-options arm_neon } */ | ||
| 5740 | |||
| 5741 | #include "arm_neon.h" | ||
| 5742 | |||
| 5743 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c | ||
| 5744 | =================================================================== | ||
| 5745 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c | ||
| 5746 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c | ||
| 5747 | @@ -3,7 +3,8 @@ | ||
| 5748 | |||
| 5749 | /* { dg-do assemble } */ | ||
| 5750 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5751 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5752 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5753 | +/* { dg-add-options arm_neon } */ | ||
| 5754 | |||
| 5755 | #include "arm_neon.h" | ||
| 5756 | |||
| 5757 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c | ||
| 5758 | =================================================================== | ||
| 5759 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c | ||
| 5760 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c | ||
| 5761 | @@ -3,7 +3,8 @@ | ||
| 5762 | |||
| 5763 | /* { dg-do assemble } */ | ||
| 5764 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5765 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5766 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5767 | +/* { dg-add-options arm_neon } */ | ||
| 5768 | |||
| 5769 | #include "arm_neon.h" | ||
| 5770 | |||
| 5771 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c | ||
| 5772 | =================================================================== | ||
| 5773 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c | ||
| 5774 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c | ||
| 5775 | @@ -3,7 +3,8 @@ | ||
| 5776 | |||
| 5777 | /* { dg-do assemble } */ | ||
| 5778 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5779 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5780 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5781 | +/* { dg-add-options arm_neon } */ | ||
| 5782 | |||
| 5783 | #include "arm_neon.h" | ||
| 5784 | |||
| 5785 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c | ||
| 5786 | =================================================================== | ||
| 5787 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c | ||
| 5788 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c | ||
| 5789 | @@ -3,7 +3,8 @@ | ||
| 5790 | |||
| 5791 | /* { dg-do assemble } */ | ||
| 5792 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5793 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5794 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5795 | +/* { dg-add-options arm_neon } */ | ||
| 5796 | |||
| 5797 | #include "arm_neon.h" | ||
| 5798 | |||
| 5799 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c | ||
| 5800 | =================================================================== | ||
| 5801 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c | ||
| 5802 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c | ||
| 5803 | @@ -3,7 +3,8 @@ | ||
| 5804 | |||
| 5805 | /* { dg-do assemble } */ | ||
| 5806 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5807 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5808 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5809 | +/* { dg-add-options arm_neon } */ | ||
| 5810 | |||
| 5811 | #include "arm_neon.h" | ||
| 5812 | |||
| 5813 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c | ||
| 5814 | =================================================================== | ||
| 5815 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c | ||
| 5816 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c | ||
| 5817 | @@ -3,7 +3,8 @@ | ||
| 5818 | |||
| 5819 | /* { dg-do assemble } */ | ||
| 5820 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5821 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5822 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5823 | +/* { dg-add-options arm_neon } */ | ||
| 5824 | |||
| 5825 | #include "arm_neon.h" | ||
| 5826 | |||
| 5827 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c | ||
| 5828 | =================================================================== | ||
| 5829 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c | ||
| 5830 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c | ||
| 5831 | @@ -3,7 +3,8 @@ | ||
| 5832 | |||
| 5833 | /* { dg-do assemble } */ | ||
| 5834 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5835 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5836 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5837 | +/* { dg-add-options arm_neon } */ | ||
| 5838 | |||
| 5839 | #include "arm_neon.h" | ||
| 5840 | |||
| 5841 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c | ||
| 5842 | =================================================================== | ||
| 5843 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c | ||
| 5844 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c | ||
| 5845 | @@ -3,7 +3,8 @@ | ||
| 5846 | |||
| 5847 | /* { dg-do assemble } */ | ||
| 5848 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5849 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5850 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5851 | +/* { dg-add-options arm_neon } */ | ||
| 5852 | |||
| 5853 | #include "arm_neon.h" | ||
| 5854 | |||
| 5855 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c | ||
| 5856 | =================================================================== | ||
| 5857 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c | ||
| 5858 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c | ||
| 5859 | @@ -3,7 +3,8 @@ | ||
| 5860 | |||
| 5861 | /* { dg-do assemble } */ | ||
| 5862 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5863 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5864 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5865 | +/* { dg-add-options arm_neon } */ | ||
| 5866 | |||
| 5867 | #include "arm_neon.h" | ||
| 5868 | |||
| 5869 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c | ||
| 5870 | =================================================================== | ||
| 5871 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c | ||
| 5872 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c | ||
| 5873 | @@ -3,7 +3,8 @@ | ||
| 5874 | |||
| 5875 | /* { dg-do assemble } */ | ||
| 5876 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5877 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5878 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5879 | +/* { dg-add-options arm_neon } */ | ||
| 5880 | |||
| 5881 | #include "arm_neon.h" | ||
| 5882 | |||
| 5883 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c | ||
| 5884 | =================================================================== | ||
| 5885 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c | ||
| 5886 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c | ||
| 5887 | @@ -3,7 +3,8 @@ | ||
| 5888 | |||
| 5889 | /* { dg-do assemble } */ | ||
| 5890 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5891 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5892 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5893 | +/* { dg-add-options arm_neon } */ | ||
| 5894 | |||
| 5895 | #include "arm_neon.h" | ||
| 5896 | |||
| 5897 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c | ||
| 5898 | =================================================================== | ||
| 5899 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c | ||
| 5900 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c | ||
| 5901 | @@ -3,7 +3,8 @@ | ||
| 5902 | |||
| 5903 | /* { dg-do assemble } */ | ||
| 5904 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5905 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5906 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5907 | +/* { dg-add-options arm_neon } */ | ||
| 5908 | |||
| 5909 | #include "arm_neon.h" | ||
| 5910 | |||
| 5911 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c | ||
| 5912 | =================================================================== | ||
| 5913 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c | ||
| 5914 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c | ||
| 5915 | @@ -3,7 +3,8 @@ | ||
| 5916 | |||
| 5917 | /* { dg-do assemble } */ | ||
| 5918 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5919 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5920 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5921 | +/* { dg-add-options arm_neon } */ | ||
| 5922 | |||
| 5923 | #include "arm_neon.h" | ||
| 5924 | |||
| 5925 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c | ||
| 5926 | =================================================================== | ||
| 5927 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c | ||
| 5928 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c | ||
| 5929 | @@ -3,7 +3,8 @@ | ||
| 5930 | |||
| 5931 | /* { dg-do assemble } */ | ||
| 5932 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5933 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5934 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5935 | +/* { dg-add-options arm_neon } */ | ||
| 5936 | |||
| 5937 | #include "arm_neon.h" | ||
| 5938 | |||
| 5939 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs16.c | ||
| 5940 | =================================================================== | ||
| 5941 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQs16.c | ||
| 5942 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs16.c | ||
| 5943 | @@ -3,7 +3,8 @@ | ||
| 5944 | |||
| 5945 | /* { dg-do assemble } */ | ||
| 5946 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5947 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5948 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5949 | +/* { dg-add-options arm_neon } */ | ||
| 5950 | |||
| 5951 | #include "arm_neon.h" | ||
| 5952 | |||
| 5953 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs32.c | ||
| 5954 | =================================================================== | ||
| 5955 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQs32.c | ||
| 5956 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs32.c | ||
| 5957 | @@ -3,7 +3,8 @@ | ||
| 5958 | |||
| 5959 | /* { dg-do assemble } */ | ||
| 5960 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5961 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5962 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5963 | +/* { dg-add-options arm_neon } */ | ||
| 5964 | |||
| 5965 | #include "arm_neon.h" | ||
| 5966 | |||
| 5967 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs64.c | ||
| 5968 | =================================================================== | ||
| 5969 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQs64.c | ||
| 5970 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs64.c | ||
| 5971 | @@ -3,7 +3,8 @@ | ||
| 5972 | |||
| 5973 | /* { dg-do assemble } */ | ||
| 5974 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5975 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5976 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5977 | +/* { dg-add-options arm_neon } */ | ||
| 5978 | |||
| 5979 | #include "arm_neon.h" | ||
| 5980 | |||
| 5981 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs8.c | ||
| 5982 | =================================================================== | ||
| 5983 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQs8.c | ||
| 5984 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQs8.c | ||
| 5985 | @@ -3,7 +3,8 @@ | ||
| 5986 | |||
| 5987 | /* { dg-do assemble } */ | ||
| 5988 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 5989 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 5990 | +/* { dg-options "-save-temps -O0" } */ | ||
| 5991 | +/* { dg-add-options arm_neon } */ | ||
| 5992 | |||
| 5993 | #include "arm_neon.h" | ||
| 5994 | |||
| 5995 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu16.c | ||
| 5996 | =================================================================== | ||
| 5997 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQu16.c | ||
| 5998 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu16.c | ||
| 5999 | @@ -3,7 +3,8 @@ | ||
| 6000 | |||
| 6001 | /* { dg-do assemble } */ | ||
| 6002 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6003 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6004 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6005 | +/* { dg-add-options arm_neon } */ | ||
| 6006 | |||
| 6007 | #include "arm_neon.h" | ||
| 6008 | |||
| 6009 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu32.c | ||
| 6010 | =================================================================== | ||
| 6011 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQu32.c | ||
| 6012 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu32.c | ||
| 6013 | @@ -3,7 +3,8 @@ | ||
| 6014 | |||
| 6015 | /* { dg-do assemble } */ | ||
| 6016 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6017 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6018 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6019 | +/* { dg-add-options arm_neon } */ | ||
| 6020 | |||
| 6021 | #include "arm_neon.h" | ||
| 6022 | |||
| 6023 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu64.c | ||
| 6024 | =================================================================== | ||
| 6025 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQu64.c | ||
| 6026 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu64.c | ||
| 6027 | @@ -3,7 +3,8 @@ | ||
| 6028 | |||
| 6029 | /* { dg-do assemble } */ | ||
| 6030 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6031 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6032 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6033 | +/* { dg-add-options arm_neon } */ | ||
| 6034 | |||
| 6035 | #include "arm_neon.h" | ||
| 6036 | |||
| 6037 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu8.c | ||
| 6038 | =================================================================== | ||
| 6039 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veorQu8.c | ||
| 6040 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veorQu8.c | ||
| 6041 | @@ -3,7 +3,8 @@ | ||
| 6042 | |||
| 6043 | /* { dg-do assemble } */ | ||
| 6044 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6045 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6046 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6047 | +/* { dg-add-options arm_neon } */ | ||
| 6048 | |||
| 6049 | #include "arm_neon.h" | ||
| 6050 | |||
| 6051 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors16.c | ||
| 6052 | =================================================================== | ||
| 6053 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veors16.c | ||
| 6054 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors16.c | ||
| 6055 | @@ -3,7 +3,8 @@ | ||
| 6056 | |||
| 6057 | /* { dg-do assemble } */ | ||
| 6058 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6059 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6060 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6061 | +/* { dg-add-options arm_neon } */ | ||
| 6062 | |||
| 6063 | #include "arm_neon.h" | ||
| 6064 | |||
| 6065 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors32.c | ||
| 6066 | =================================================================== | ||
| 6067 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veors32.c | ||
| 6068 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors32.c | ||
| 6069 | @@ -3,7 +3,8 @@ | ||
| 6070 | |||
| 6071 | /* { dg-do assemble } */ | ||
| 6072 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6073 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6074 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6075 | +/* { dg-add-options arm_neon } */ | ||
| 6076 | |||
| 6077 | #include "arm_neon.h" | ||
| 6078 | |||
| 6079 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors64.c | ||
| 6080 | =================================================================== | ||
| 6081 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veors64.c | ||
| 6082 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors64.c | ||
| 6083 | @@ -3,7 +3,8 @@ | ||
| 6084 | |||
| 6085 | /* { dg-do assemble } */ | ||
| 6086 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6087 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6088 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6089 | +/* { dg-add-options arm_neon } */ | ||
| 6090 | |||
| 6091 | #include "arm_neon.h" | ||
| 6092 | |||
| 6093 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors8.c | ||
| 6094 | =================================================================== | ||
| 6095 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veors8.c | ||
| 6096 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veors8.c | ||
| 6097 | @@ -3,7 +3,8 @@ | ||
| 6098 | |||
| 6099 | /* { dg-do assemble } */ | ||
| 6100 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6101 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6102 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6103 | +/* { dg-add-options arm_neon } */ | ||
| 6104 | |||
| 6105 | #include "arm_neon.h" | ||
| 6106 | |||
| 6107 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru16.c | ||
| 6108 | =================================================================== | ||
| 6109 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veoru16.c | ||
| 6110 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru16.c | ||
| 6111 | @@ -3,7 +3,8 @@ | ||
| 6112 | |||
| 6113 | /* { dg-do assemble } */ | ||
| 6114 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6115 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6116 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6117 | +/* { dg-add-options arm_neon } */ | ||
| 6118 | |||
| 6119 | #include "arm_neon.h" | ||
| 6120 | |||
| 6121 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru32.c | ||
| 6122 | =================================================================== | ||
| 6123 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veoru32.c | ||
| 6124 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru32.c | ||
| 6125 | @@ -3,7 +3,8 @@ | ||
| 6126 | |||
| 6127 | /* { dg-do assemble } */ | ||
| 6128 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6129 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6130 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6131 | +/* { dg-add-options arm_neon } */ | ||
| 6132 | |||
| 6133 | #include "arm_neon.h" | ||
| 6134 | |||
| 6135 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru64.c | ||
| 6136 | =================================================================== | ||
| 6137 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veoru64.c | ||
| 6138 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru64.c | ||
| 6139 | @@ -3,7 +3,8 @@ | ||
| 6140 | |||
| 6141 | /* { dg-do assemble } */ | ||
| 6142 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6143 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6144 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6145 | +/* { dg-add-options arm_neon } */ | ||
| 6146 | |||
| 6147 | #include "arm_neon.h" | ||
| 6148 | |||
| 6149 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru8.c | ||
| 6150 | =================================================================== | ||
| 6151 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/veoru8.c | ||
| 6152 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/veoru8.c | ||
| 6153 | @@ -3,7 +3,8 @@ | ||
| 6154 | |||
| 6155 | /* { dg-do assemble } */ | ||
| 6156 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6157 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6158 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6159 | +/* { dg-add-options arm_neon } */ | ||
| 6160 | |||
| 6161 | #include "arm_neon.h" | ||
| 6162 | |||
| 6163 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQf32.c | ||
| 6164 | =================================================================== | ||
| 6165 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQf32.c | ||
| 6166 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQf32.c | ||
| 6167 | @@ -3,7 +3,8 @@ | ||
| 6168 | |||
| 6169 | /* { dg-do assemble } */ | ||
| 6170 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6171 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6172 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6173 | +/* { dg-add-options arm_neon } */ | ||
| 6174 | |||
| 6175 | #include "arm_neon.h" | ||
| 6176 | |||
| 6177 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQp16.c | ||
| 6178 | =================================================================== | ||
| 6179 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQp16.c | ||
| 6180 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQp16.c | ||
| 6181 | @@ -3,7 +3,8 @@ | ||
| 6182 | |||
| 6183 | /* { dg-do assemble } */ | ||
| 6184 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6185 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6186 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6187 | +/* { dg-add-options arm_neon } */ | ||
| 6188 | |||
| 6189 | #include "arm_neon.h" | ||
| 6190 | |||
| 6191 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQp8.c | ||
| 6192 | =================================================================== | ||
| 6193 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQp8.c | ||
| 6194 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQp8.c | ||
| 6195 | @@ -3,7 +3,8 @@ | ||
| 6196 | |||
| 6197 | /* { dg-do assemble } */ | ||
| 6198 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6199 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6200 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6201 | +/* { dg-add-options arm_neon } */ | ||
| 6202 | |||
| 6203 | #include "arm_neon.h" | ||
| 6204 | |||
| 6205 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs16.c | ||
| 6206 | =================================================================== | ||
| 6207 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQs16.c | ||
| 6208 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs16.c | ||
| 6209 | @@ -3,7 +3,8 @@ | ||
| 6210 | |||
| 6211 | /* { dg-do assemble } */ | ||
| 6212 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6213 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6214 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6215 | +/* { dg-add-options arm_neon } */ | ||
| 6216 | |||
| 6217 | #include "arm_neon.h" | ||
| 6218 | |||
| 6219 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs32.c | ||
| 6220 | =================================================================== | ||
| 6221 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQs32.c | ||
| 6222 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs32.c | ||
| 6223 | @@ -3,7 +3,8 @@ | ||
| 6224 | |||
| 6225 | /* { dg-do assemble } */ | ||
| 6226 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6227 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6228 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6229 | +/* { dg-add-options arm_neon } */ | ||
| 6230 | |||
| 6231 | #include "arm_neon.h" | ||
| 6232 | |||
| 6233 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs64.c | ||
| 6234 | =================================================================== | ||
| 6235 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQs64.c | ||
| 6236 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs64.c | ||
| 6237 | @@ -3,7 +3,8 @@ | ||
| 6238 | |||
| 6239 | /* { dg-do assemble } */ | ||
| 6240 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6241 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6242 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6243 | +/* { dg-add-options arm_neon } */ | ||
| 6244 | |||
| 6245 | #include "arm_neon.h" | ||
| 6246 | |||
| 6247 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs8.c | ||
| 6248 | =================================================================== | ||
| 6249 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQs8.c | ||
| 6250 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQs8.c | ||
| 6251 | @@ -3,7 +3,8 @@ | ||
| 6252 | |||
| 6253 | /* { dg-do assemble } */ | ||
| 6254 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6255 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6256 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6257 | +/* { dg-add-options arm_neon } */ | ||
| 6258 | |||
| 6259 | #include "arm_neon.h" | ||
| 6260 | |||
| 6261 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu16.c | ||
| 6262 | =================================================================== | ||
| 6263 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQu16.c | ||
| 6264 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu16.c | ||
| 6265 | @@ -3,7 +3,8 @@ | ||
| 6266 | |||
| 6267 | /* { dg-do assemble } */ | ||
| 6268 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6269 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6270 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6271 | +/* { dg-add-options arm_neon } */ | ||
| 6272 | |||
| 6273 | #include "arm_neon.h" | ||
| 6274 | |||
| 6275 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu32.c | ||
| 6276 | =================================================================== | ||
| 6277 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQu32.c | ||
| 6278 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu32.c | ||
| 6279 | @@ -3,7 +3,8 @@ | ||
| 6280 | |||
| 6281 | /* { dg-do assemble } */ | ||
| 6282 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6283 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6284 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6285 | +/* { dg-add-options arm_neon } */ | ||
| 6286 | |||
| 6287 | #include "arm_neon.h" | ||
| 6288 | |||
| 6289 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu64.c | ||
| 6290 | =================================================================== | ||
| 6291 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQu64.c | ||
| 6292 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu64.c | ||
| 6293 | @@ -3,7 +3,8 @@ | ||
| 6294 | |||
| 6295 | /* { dg-do assemble } */ | ||
| 6296 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6297 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6298 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6299 | +/* { dg-add-options arm_neon } */ | ||
| 6300 | |||
| 6301 | #include "arm_neon.h" | ||
| 6302 | |||
| 6303 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu8.c | ||
| 6304 | =================================================================== | ||
| 6305 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextQu8.c | ||
| 6306 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextQu8.c | ||
| 6307 | @@ -3,7 +3,8 @@ | ||
| 6308 | |||
| 6309 | /* { dg-do assemble } */ | ||
| 6310 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6311 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6312 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6313 | +/* { dg-add-options arm_neon } */ | ||
| 6314 | |||
| 6315 | #include "arm_neon.h" | ||
| 6316 | |||
| 6317 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextf32.c | ||
| 6318 | =================================================================== | ||
| 6319 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextf32.c | ||
| 6320 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextf32.c | ||
| 6321 | @@ -3,7 +3,8 @@ | ||
| 6322 | |||
| 6323 | /* { dg-do assemble } */ | ||
| 6324 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6325 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6326 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6327 | +/* { dg-add-options arm_neon } */ | ||
| 6328 | |||
| 6329 | #include "arm_neon.h" | ||
| 6330 | |||
| 6331 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextp16.c | ||
| 6332 | =================================================================== | ||
| 6333 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextp16.c | ||
| 6334 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextp16.c | ||
| 6335 | @@ -3,7 +3,8 @@ | ||
| 6336 | |||
| 6337 | /* { dg-do assemble } */ | ||
| 6338 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6339 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6340 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6341 | +/* { dg-add-options arm_neon } */ | ||
| 6342 | |||
| 6343 | #include "arm_neon.h" | ||
| 6344 | |||
| 6345 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextp8.c | ||
| 6346 | =================================================================== | ||
| 6347 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextp8.c | ||
| 6348 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextp8.c | ||
| 6349 | @@ -3,7 +3,8 @@ | ||
| 6350 | |||
| 6351 | /* { dg-do assemble } */ | ||
| 6352 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6353 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6354 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6355 | +/* { dg-add-options arm_neon } */ | ||
| 6356 | |||
| 6357 | #include "arm_neon.h" | ||
| 6358 | |||
| 6359 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts16.c | ||
| 6360 | =================================================================== | ||
| 6361 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vexts16.c | ||
| 6362 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts16.c | ||
| 6363 | @@ -3,7 +3,8 @@ | ||
| 6364 | |||
| 6365 | /* { dg-do assemble } */ | ||
| 6366 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6367 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6368 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6369 | +/* { dg-add-options arm_neon } */ | ||
| 6370 | |||
| 6371 | #include "arm_neon.h" | ||
| 6372 | |||
| 6373 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts32.c | ||
| 6374 | =================================================================== | ||
| 6375 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vexts32.c | ||
| 6376 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts32.c | ||
| 6377 | @@ -3,7 +3,8 @@ | ||
| 6378 | |||
| 6379 | /* { dg-do assemble } */ | ||
| 6380 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6381 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6382 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6383 | +/* { dg-add-options arm_neon } */ | ||
| 6384 | |||
| 6385 | #include "arm_neon.h" | ||
| 6386 | |||
| 6387 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts64.c | ||
| 6388 | =================================================================== | ||
| 6389 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vexts64.c | ||
| 6390 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts64.c | ||
| 6391 | @@ -3,7 +3,8 @@ | ||
| 6392 | |||
| 6393 | /* { dg-do assemble } */ | ||
| 6394 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6395 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6396 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6397 | +/* { dg-add-options arm_neon } */ | ||
| 6398 | |||
| 6399 | #include "arm_neon.h" | ||
| 6400 | |||
| 6401 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts8.c | ||
| 6402 | =================================================================== | ||
| 6403 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vexts8.c | ||
| 6404 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vexts8.c | ||
| 6405 | @@ -3,7 +3,8 @@ | ||
| 6406 | |||
| 6407 | /* { dg-do assemble } */ | ||
| 6408 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6409 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6410 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6411 | +/* { dg-add-options arm_neon } */ | ||
| 6412 | |||
| 6413 | #include "arm_neon.h" | ||
| 6414 | |||
| 6415 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu16.c | ||
| 6416 | =================================================================== | ||
| 6417 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextu16.c | ||
| 6418 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu16.c | ||
| 6419 | @@ -3,7 +3,8 @@ | ||
| 6420 | |||
| 6421 | /* { dg-do assemble } */ | ||
| 6422 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6423 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6424 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6425 | +/* { dg-add-options arm_neon } */ | ||
| 6426 | |||
| 6427 | #include "arm_neon.h" | ||
| 6428 | |||
| 6429 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu32.c | ||
| 6430 | =================================================================== | ||
| 6431 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextu32.c | ||
| 6432 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu32.c | ||
| 6433 | @@ -3,7 +3,8 @@ | ||
| 6434 | |||
| 6435 | /* { dg-do assemble } */ | ||
| 6436 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6437 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6438 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6439 | +/* { dg-add-options arm_neon } */ | ||
| 6440 | |||
| 6441 | #include "arm_neon.h" | ||
| 6442 | |||
| 6443 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu64.c | ||
| 6444 | =================================================================== | ||
| 6445 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextu64.c | ||
| 6446 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu64.c | ||
| 6447 | @@ -3,7 +3,8 @@ | ||
| 6448 | |||
| 6449 | /* { dg-do assemble } */ | ||
| 6450 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6451 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6452 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6453 | +/* { dg-add-options arm_neon } */ | ||
| 6454 | |||
| 6455 | #include "arm_neon.h" | ||
| 6456 | |||
| 6457 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu8.c | ||
| 6458 | =================================================================== | ||
| 6459 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vextu8.c | ||
| 6460 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vextu8.c | ||
| 6461 | @@ -3,7 +3,8 @@ | ||
| 6462 | |||
| 6463 | /* { dg-do assemble } */ | ||
| 6464 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6465 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6466 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6467 | +/* { dg-add-options arm_neon } */ | ||
| 6468 | |||
| 6469 | #include "arm_neon.h" | ||
| 6470 | |||
| 6471 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c | ||
| 6472 | =================================================================== | ||
| 6473 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c | ||
| 6474 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c | ||
| 6475 | @@ -2,7 +2,8 @@ | ||
| 6476 | |||
| 6477 | /* { dg-do compile } */ | ||
| 6478 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6479 | -/* { dg-options "-save-temps -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6480 | +/* { dg-options "-save-temps" } */ | ||
| 6481 | +/* { dg-add-options arm_neon } */ | ||
| 6482 | |||
| 6483 | #include <arm_neon.h> | ||
| 6484 | |||
| 6485 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c | ||
| 6486 | =================================================================== | ||
| 6487 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c | ||
| 6488 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c | ||
| 6489 | @@ -3,7 +3,8 @@ | ||
| 6490 | |||
| 6491 | /* { dg-do assemble } */ | ||
| 6492 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6493 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6494 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6495 | +/* { dg-add-options arm_neon } */ | ||
| 6496 | |||
| 6497 | #include "arm_neon.h" | ||
| 6498 | |||
| 6499 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c | ||
| 6500 | =================================================================== | ||
| 6501 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c | ||
| 6502 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c | ||
| 6503 | @@ -3,7 +3,8 @@ | ||
| 6504 | |||
| 6505 | /* { dg-do assemble } */ | ||
| 6506 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6507 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6508 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6509 | +/* { dg-add-options arm_neon } */ | ||
| 6510 | |||
| 6511 | #include "arm_neon.h" | ||
| 6512 | |||
| 6513 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c | ||
| 6514 | =================================================================== | ||
| 6515 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c | ||
| 6516 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c | ||
| 6517 | @@ -3,7 +3,8 @@ | ||
| 6518 | |||
| 6519 | /* { dg-do assemble } */ | ||
| 6520 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6521 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6522 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6523 | +/* { dg-add-options arm_neon } */ | ||
| 6524 | |||
| 6525 | #include "arm_neon.h" | ||
| 6526 | |||
| 6527 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c | ||
| 6528 | =================================================================== | ||
| 6529 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c | ||
| 6530 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c | ||
| 6531 | @@ -3,7 +3,8 @@ | ||
| 6532 | |||
| 6533 | /* { dg-do assemble } */ | ||
| 6534 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6535 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6536 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6537 | +/* { dg-add-options arm_neon } */ | ||
| 6538 | |||
| 6539 | #include "arm_neon.h" | ||
| 6540 | |||
| 6541 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c | ||
| 6542 | =================================================================== | ||
| 6543 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c | ||
| 6544 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c | ||
| 6545 | @@ -3,7 +3,8 @@ | ||
| 6546 | |||
| 6547 | /* { dg-do assemble } */ | ||
| 6548 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6549 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6550 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6551 | +/* { dg-add-options arm_neon } */ | ||
| 6552 | |||
| 6553 | #include "arm_neon.h" | ||
| 6554 | |||
| 6555 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c | ||
| 6556 | =================================================================== | ||
| 6557 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c | ||
| 6558 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c | ||
| 6559 | @@ -3,7 +3,8 @@ | ||
| 6560 | |||
| 6561 | /* { dg-do assemble } */ | ||
| 6562 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6563 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6564 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6565 | +/* { dg-add-options arm_neon } */ | ||
| 6566 | |||
| 6567 | #include "arm_neon.h" | ||
| 6568 | |||
| 6569 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c | ||
| 6570 | =================================================================== | ||
| 6571 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c | ||
| 6572 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c | ||
| 6573 | @@ -3,7 +3,8 @@ | ||
| 6574 | |||
| 6575 | /* { dg-do assemble } */ | ||
| 6576 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6577 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6578 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6579 | +/* { dg-add-options arm_neon } */ | ||
| 6580 | |||
| 6581 | #include "arm_neon.h" | ||
| 6582 | |||
| 6583 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c | ||
| 6584 | =================================================================== | ||
| 6585 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c | ||
| 6586 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c | ||
| 6587 | @@ -3,7 +3,8 @@ | ||
| 6588 | |||
| 6589 | /* { dg-do assemble } */ | ||
| 6590 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6591 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6592 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6593 | +/* { dg-add-options arm_neon } */ | ||
| 6594 | |||
| 6595 | #include "arm_neon.h" | ||
| 6596 | |||
| 6597 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c | ||
| 6598 | =================================================================== | ||
| 6599 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c | ||
| 6600 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c | ||
| 6601 | @@ -3,7 +3,8 @@ | ||
| 6602 | |||
| 6603 | /* { dg-do assemble } */ | ||
| 6604 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6605 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6606 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6607 | +/* { dg-add-options arm_neon } */ | ||
| 6608 | |||
| 6609 | #include "arm_neon.h" | ||
| 6610 | |||
| 6611 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c | ||
| 6612 | =================================================================== | ||
| 6613 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c | ||
| 6614 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c | ||
| 6615 | @@ -3,7 +3,8 @@ | ||
| 6616 | |||
| 6617 | /* { dg-do assemble } */ | ||
| 6618 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6619 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6620 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6621 | +/* { dg-add-options arm_neon } */ | ||
| 6622 | |||
| 6623 | #include "arm_neon.h" | ||
| 6624 | |||
| 6625 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c | ||
| 6626 | =================================================================== | ||
| 6627 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c | ||
| 6628 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c | ||
| 6629 | @@ -3,7 +3,8 @@ | ||
| 6630 | |||
| 6631 | /* { dg-do assemble } */ | ||
| 6632 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6633 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6634 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6635 | +/* { dg-add-options arm_neon } */ | ||
| 6636 | |||
| 6637 | #include "arm_neon.h" | ||
| 6638 | |||
| 6639 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c | ||
| 6640 | =================================================================== | ||
| 6641 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c | ||
| 6642 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c | ||
| 6643 | @@ -3,7 +3,8 @@ | ||
| 6644 | |||
| 6645 | /* { dg-do assemble } */ | ||
| 6646 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6647 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6648 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6649 | +/* { dg-add-options arm_neon } */ | ||
| 6650 | |||
| 6651 | #include "arm_neon.h" | ||
| 6652 | |||
| 6653 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c | ||
| 6654 | =================================================================== | ||
| 6655 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c | ||
| 6656 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c | ||
| 6657 | @@ -3,7 +3,8 @@ | ||
| 6658 | |||
| 6659 | /* { dg-do assemble } */ | ||
| 6660 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6661 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6662 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6663 | +/* { dg-add-options arm_neon } */ | ||
| 6664 | |||
| 6665 | #include "arm_neon.h" | ||
| 6666 | |||
| 6667 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c | ||
| 6668 | =================================================================== | ||
| 6669 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c | ||
| 6670 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c | ||
| 6671 | @@ -3,7 +3,8 @@ | ||
| 6672 | |||
| 6673 | /* { dg-do assemble } */ | ||
| 6674 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6675 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6676 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6677 | +/* { dg-add-options arm_neon } */ | ||
| 6678 | |||
| 6679 | #include "arm_neon.h" | ||
| 6680 | |||
| 6681 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c | ||
| 6682 | =================================================================== | ||
| 6683 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c | ||
| 6684 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c | ||
| 6685 | @@ -3,7 +3,8 @@ | ||
| 6686 | |||
| 6687 | /* { dg-do assemble } */ | ||
| 6688 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6689 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6690 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6691 | +/* { dg-add-options arm_neon } */ | ||
| 6692 | |||
| 6693 | #include "arm_neon.h" | ||
| 6694 | |||
| 6695 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c | ||
| 6696 | =================================================================== | ||
| 6697 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c | ||
| 6698 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c | ||
| 6699 | @@ -3,7 +3,8 @@ | ||
| 6700 | |||
| 6701 | /* { dg-do assemble } */ | ||
| 6702 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6703 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6704 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6705 | +/* { dg-add-options arm_neon } */ | ||
| 6706 | |||
| 6707 | #include "arm_neon.h" | ||
| 6708 | |||
| 6709 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c | ||
| 6710 | =================================================================== | ||
| 6711 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c | ||
| 6712 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c | ||
| 6713 | @@ -3,7 +3,8 @@ | ||
| 6714 | |||
| 6715 | /* { dg-do assemble } */ | ||
| 6716 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6717 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6718 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6719 | +/* { dg-add-options arm_neon } */ | ||
| 6720 | |||
| 6721 | #include "arm_neon.h" | ||
| 6722 | |||
| 6723 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c | ||
| 6724 | =================================================================== | ||
| 6725 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c | ||
| 6726 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c | ||
| 6727 | @@ -3,7 +3,8 @@ | ||
| 6728 | |||
| 6729 | /* { dg-do assemble } */ | ||
| 6730 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6731 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6732 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6733 | +/* { dg-add-options arm_neon } */ | ||
| 6734 | |||
| 6735 | #include "arm_neon.h" | ||
| 6736 | |||
| 6737 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c | ||
| 6738 | =================================================================== | ||
| 6739 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c | ||
| 6740 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c | ||
| 6741 | @@ -3,7 +3,8 @@ | ||
| 6742 | |||
| 6743 | /* { dg-do assemble } */ | ||
| 6744 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6745 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6746 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6747 | +/* { dg-add-options arm_neon } */ | ||
| 6748 | |||
| 6749 | #include "arm_neon.h" | ||
| 6750 | |||
| 6751 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c | ||
| 6752 | =================================================================== | ||
| 6753 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c | ||
| 6754 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c | ||
| 6755 | @@ -3,7 +3,8 @@ | ||
| 6756 | |||
| 6757 | /* { dg-do assemble } */ | ||
| 6758 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6759 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6760 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6761 | +/* { dg-add-options arm_neon } */ | ||
| 6762 | |||
| 6763 | #include "arm_neon.h" | ||
| 6764 | |||
| 6765 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c | ||
| 6766 | =================================================================== | ||
| 6767 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c | ||
| 6768 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c | ||
| 6769 | @@ -3,7 +3,8 @@ | ||
| 6770 | |||
| 6771 | /* { dg-do assemble } */ | ||
| 6772 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6773 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6774 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6775 | +/* { dg-add-options arm_neon } */ | ||
| 6776 | |||
| 6777 | #include "arm_neon.h" | ||
| 6778 | |||
| 6779 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c | ||
| 6780 | =================================================================== | ||
| 6781 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c | ||
| 6782 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c | ||
| 6783 | @@ -3,7 +3,8 @@ | ||
| 6784 | |||
| 6785 | /* { dg-do assemble } */ | ||
| 6786 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6787 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6788 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6789 | +/* { dg-add-options arm_neon } */ | ||
| 6790 | |||
| 6791 | #include "arm_neon.h" | ||
| 6792 | |||
| 6793 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c | ||
| 6794 | =================================================================== | ||
| 6795 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c | ||
| 6796 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c | ||
| 6797 | @@ -3,7 +3,8 @@ | ||
| 6798 | |||
| 6799 | /* { dg-do assemble } */ | ||
| 6800 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6801 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6802 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6803 | +/* { dg-add-options arm_neon } */ | ||
| 6804 | |||
| 6805 | #include "arm_neon.h" | ||
| 6806 | |||
| 6807 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c | ||
| 6808 | =================================================================== | ||
| 6809 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c | ||
| 6810 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c | ||
| 6811 | @@ -3,7 +3,8 @@ | ||
| 6812 | |||
| 6813 | /* { dg-do assemble } */ | ||
| 6814 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6815 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6816 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6817 | +/* { dg-add-options arm_neon } */ | ||
| 6818 | |||
| 6819 | #include "arm_neon.h" | ||
| 6820 | |||
| 6821 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c | ||
| 6822 | =================================================================== | ||
| 6823 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c | ||
| 6824 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c | ||
| 6825 | @@ -3,7 +3,8 @@ | ||
| 6826 | |||
| 6827 | /* { dg-do assemble } */ | ||
| 6828 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6829 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6830 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6831 | +/* { dg-add-options arm_neon } */ | ||
| 6832 | |||
| 6833 | #include "arm_neon.h" | ||
| 6834 | |||
| 6835 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c | ||
| 6836 | =================================================================== | ||
| 6837 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c | ||
| 6838 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c | ||
| 6839 | @@ -3,7 +3,8 @@ | ||
| 6840 | |||
| 6841 | /* { dg-do assemble } */ | ||
| 6842 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6843 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6844 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6845 | +/* { dg-add-options arm_neon } */ | ||
| 6846 | |||
| 6847 | #include "arm_neon.h" | ||
| 6848 | |||
| 6849 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c | ||
| 6850 | =================================================================== | ||
| 6851 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c | ||
| 6852 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c | ||
| 6853 | @@ -3,7 +3,8 @@ | ||
| 6854 | |||
| 6855 | /* { dg-do assemble } */ | ||
| 6856 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6857 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6858 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6859 | +/* { dg-add-options arm_neon } */ | ||
| 6860 | |||
| 6861 | #include "arm_neon.h" | ||
| 6862 | |||
| 6863 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c | ||
| 6864 | =================================================================== | ||
| 6865 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c | ||
| 6866 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c | ||
| 6867 | @@ -3,7 +3,8 @@ | ||
| 6868 | |||
| 6869 | /* { dg-do assemble } */ | ||
| 6870 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6871 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6872 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6873 | +/* { dg-add-options arm_neon } */ | ||
| 6874 | |||
| 6875 | #include "arm_neon.h" | ||
| 6876 | |||
| 6877 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c | ||
| 6878 | =================================================================== | ||
| 6879 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c | ||
| 6880 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c | ||
| 6881 | @@ -3,7 +3,8 @@ | ||
| 6882 | |||
| 6883 | /* { dg-do assemble } */ | ||
| 6884 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6885 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6886 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6887 | +/* { dg-add-options arm_neon } */ | ||
| 6888 | |||
| 6889 | #include "arm_neon.h" | ||
| 6890 | |||
| 6891 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c | ||
| 6892 | =================================================================== | ||
| 6893 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c | ||
| 6894 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c | ||
| 6895 | @@ -3,7 +3,8 @@ | ||
| 6896 | |||
| 6897 | /* { dg-do assemble } */ | ||
| 6898 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6899 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6900 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6901 | +/* { dg-add-options arm_neon } */ | ||
| 6902 | |||
| 6903 | #include "arm_neon.h" | ||
| 6904 | |||
| 6905 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c | ||
| 6906 | =================================================================== | ||
| 6907 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c | ||
| 6908 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c | ||
| 6909 | @@ -3,7 +3,8 @@ | ||
| 6910 | |||
| 6911 | /* { dg-do assemble } */ | ||
| 6912 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6913 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6914 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6915 | +/* { dg-add-options arm_neon } */ | ||
| 6916 | |||
| 6917 | #include "arm_neon.h" | ||
| 6918 | |||
| 6919 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c | ||
| 6920 | =================================================================== | ||
| 6921 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c | ||
| 6922 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c | ||
| 6923 | @@ -3,7 +3,8 @@ | ||
| 6924 | |||
| 6925 | /* { dg-do assemble } */ | ||
| 6926 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6927 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6928 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6929 | +/* { dg-add-options arm_neon } */ | ||
| 6930 | |||
| 6931 | #include "arm_neon.h" | ||
| 6932 | |||
| 6933 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c | ||
| 6934 | =================================================================== | ||
| 6935 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c | ||
| 6936 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c | ||
| 6937 | @@ -3,7 +3,8 @@ | ||
| 6938 | |||
| 6939 | /* { dg-do assemble } */ | ||
| 6940 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6941 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6942 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6943 | +/* { dg-add-options arm_neon } */ | ||
| 6944 | |||
| 6945 | #include "arm_neon.h" | ||
| 6946 | |||
| 6947 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c | ||
| 6948 | =================================================================== | ||
| 6949 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c | ||
| 6950 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c | ||
| 6951 | @@ -3,7 +3,8 @@ | ||
| 6952 | |||
| 6953 | /* { dg-do assemble } */ | ||
| 6954 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6955 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6956 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6957 | +/* { dg-add-options arm_neon } */ | ||
| 6958 | |||
| 6959 | #include "arm_neon.h" | ||
| 6960 | |||
| 6961 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c | ||
| 6962 | =================================================================== | ||
| 6963 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c | ||
| 6964 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c | ||
| 6965 | @@ -3,7 +3,8 @@ | ||
| 6966 | |||
| 6967 | /* { dg-do assemble } */ | ||
| 6968 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6969 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6970 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6971 | +/* { dg-add-options arm_neon } */ | ||
| 6972 | |||
| 6973 | #include "arm_neon.h" | ||
| 6974 | |||
| 6975 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c | ||
| 6976 | =================================================================== | ||
| 6977 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c | ||
| 6978 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c | ||
| 6979 | @@ -3,7 +3,8 @@ | ||
| 6980 | |||
| 6981 | /* { dg-do assemble } */ | ||
| 6982 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6983 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6984 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6985 | +/* { dg-add-options arm_neon } */ | ||
| 6986 | |||
| 6987 | #include "arm_neon.h" | ||
| 6988 | |||
| 6989 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c | ||
| 6990 | =================================================================== | ||
| 6991 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c | ||
| 6992 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c | ||
| 6993 | @@ -3,7 +3,8 @@ | ||
| 6994 | |||
| 6995 | /* { dg-do assemble } */ | ||
| 6996 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 6997 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 6998 | +/* { dg-options "-save-temps -O0" } */ | ||
| 6999 | +/* { dg-add-options arm_neon } */ | ||
| 7000 | |||
| 7001 | #include "arm_neon.h" | ||
| 7002 | |||
| 7003 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c | ||
| 7004 | =================================================================== | ||
| 7005 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c | ||
| 7006 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c | ||
| 7007 | @@ -3,7 +3,8 @@ | ||
| 7008 | |||
| 7009 | /* { dg-do assemble } */ | ||
| 7010 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7011 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7012 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7013 | +/* { dg-add-options arm_neon } */ | ||
| 7014 | |||
| 7015 | #include "arm_neon.h" | ||
| 7016 | |||
| 7017 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c | ||
| 7018 | =================================================================== | ||
| 7019 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c | ||
| 7020 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c | ||
| 7021 | @@ -3,7 +3,8 @@ | ||
| 7022 | |||
| 7023 | /* { dg-do assemble } */ | ||
| 7024 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7025 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7026 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7027 | +/* { dg-add-options arm_neon } */ | ||
| 7028 | |||
| 7029 | #include "arm_neon.h" | ||
| 7030 | |||
| 7031 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c | ||
| 7032 | =================================================================== | ||
| 7033 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c | ||
| 7034 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c | ||
| 7035 | @@ -3,7 +3,8 @@ | ||
| 7036 | |||
| 7037 | /* { dg-do assemble } */ | ||
| 7038 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7039 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7040 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7041 | +/* { dg-add-options arm_neon } */ | ||
| 7042 | |||
| 7043 | #include "arm_neon.h" | ||
| 7044 | |||
| 7045 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c | ||
| 7046 | =================================================================== | ||
| 7047 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c | ||
| 7048 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c | ||
| 7049 | @@ -3,7 +3,8 @@ | ||
| 7050 | |||
| 7051 | /* { dg-do assemble } */ | ||
| 7052 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7053 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7054 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7055 | +/* { dg-add-options arm_neon } */ | ||
| 7056 | |||
| 7057 | #include "arm_neon.h" | ||
| 7058 | |||
| 7059 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c | ||
| 7060 | =================================================================== | ||
| 7061 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c | ||
| 7062 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c | ||
| 7063 | @@ -3,7 +3,8 @@ | ||
| 7064 | |||
| 7065 | /* { dg-do assemble } */ | ||
| 7066 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7067 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7068 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7069 | +/* { dg-add-options arm_neon } */ | ||
| 7070 | |||
| 7071 | #include "arm_neon.h" | ||
| 7072 | |||
| 7073 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c | ||
| 7074 | =================================================================== | ||
| 7075 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c | ||
| 7076 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c | ||
| 7077 | @@ -3,7 +3,8 @@ | ||
| 7078 | |||
| 7079 | /* { dg-do assemble } */ | ||
| 7080 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7081 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7082 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7083 | +/* { dg-add-options arm_neon } */ | ||
| 7084 | |||
| 7085 | #include "arm_neon.h" | ||
| 7086 | |||
| 7087 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c | ||
| 7088 | =================================================================== | ||
| 7089 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c | ||
| 7090 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c | ||
| 7091 | @@ -3,7 +3,8 @@ | ||
| 7092 | |||
| 7093 | /* { dg-do assemble } */ | ||
| 7094 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7095 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7096 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7097 | +/* { dg-add-options arm_neon } */ | ||
| 7098 | |||
| 7099 | #include "arm_neon.h" | ||
| 7100 | |||
| 7101 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c | ||
| 7102 | =================================================================== | ||
| 7103 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c | ||
| 7104 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c | ||
| 7105 | @@ -3,7 +3,8 @@ | ||
| 7106 | |||
| 7107 | /* { dg-do assemble } */ | ||
| 7108 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7109 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7110 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7111 | +/* { dg-add-options arm_neon } */ | ||
| 7112 | |||
| 7113 | #include "arm_neon.h" | ||
| 7114 | |||
| 7115 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c | ||
| 7116 | =================================================================== | ||
| 7117 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c | ||
| 7118 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c | ||
| 7119 | @@ -3,7 +3,8 @@ | ||
| 7120 | |||
| 7121 | /* { dg-do assemble } */ | ||
| 7122 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7123 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7124 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7125 | +/* { dg-add-options arm_neon } */ | ||
| 7126 | |||
| 7127 | #include "arm_neon.h" | ||
| 7128 | |||
| 7129 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c | ||
| 7130 | =================================================================== | ||
| 7131 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c | ||
| 7132 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c | ||
| 7133 | @@ -3,7 +3,8 @@ | ||
| 7134 | |||
| 7135 | /* { dg-do assemble } */ | ||
| 7136 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7137 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7138 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7139 | +/* { dg-add-options arm_neon } */ | ||
| 7140 | |||
| 7141 | #include "arm_neon.h" | ||
| 7142 | |||
| 7143 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c | ||
| 7144 | =================================================================== | ||
| 7145 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c | ||
| 7146 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c | ||
| 7147 | @@ -3,7 +3,8 @@ | ||
| 7148 | |||
| 7149 | /* { dg-do assemble } */ | ||
| 7150 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7151 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7152 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7153 | +/* { dg-add-options arm_neon } */ | ||
| 7154 | |||
| 7155 | #include "arm_neon.h" | ||
| 7156 | |||
| 7157 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c | ||
| 7158 | =================================================================== | ||
| 7159 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c | ||
| 7160 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c | ||
| 7161 | @@ -3,7 +3,8 @@ | ||
| 7162 | |||
| 7163 | /* { dg-do assemble } */ | ||
| 7164 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7165 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7166 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7167 | +/* { dg-add-options arm_neon } */ | ||
| 7168 | |||
| 7169 | #include "arm_neon.h" | ||
| 7170 | |||
| 7171 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c | ||
| 7172 | =================================================================== | ||
| 7173 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c | ||
| 7174 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c | ||
| 7175 | @@ -3,7 +3,8 @@ | ||
| 7176 | |||
| 7177 | /* { dg-do assemble } */ | ||
| 7178 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7179 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7180 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7181 | +/* { dg-add-options arm_neon } */ | ||
| 7182 | |||
| 7183 | #include "arm_neon.h" | ||
| 7184 | |||
| 7185 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhadds16.c | ||
| 7186 | =================================================================== | ||
| 7187 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhadds16.c | ||
| 7188 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhadds16.c | ||
| 7189 | @@ -3,7 +3,8 @@ | ||
| 7190 | |||
| 7191 | /* { dg-do assemble } */ | ||
| 7192 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7193 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7194 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7195 | +/* { dg-add-options arm_neon } */ | ||
| 7196 | |||
| 7197 | #include "arm_neon.h" | ||
| 7198 | |||
| 7199 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhadds32.c | ||
| 7200 | =================================================================== | ||
| 7201 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhadds32.c | ||
| 7202 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhadds32.c | ||
| 7203 | @@ -3,7 +3,8 @@ | ||
| 7204 | |||
| 7205 | /* { dg-do assemble } */ | ||
| 7206 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7207 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7208 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7209 | +/* { dg-add-options arm_neon } */ | ||
| 7210 | |||
| 7211 | #include "arm_neon.h" | ||
| 7212 | |||
| 7213 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhadds8.c | ||
| 7214 | =================================================================== | ||
| 7215 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhadds8.c | ||
| 7216 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhadds8.c | ||
| 7217 | @@ -3,7 +3,8 @@ | ||
| 7218 | |||
| 7219 | /* { dg-do assemble } */ | ||
| 7220 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7221 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7222 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7223 | +/* { dg-add-options arm_neon } */ | ||
| 7224 | |||
| 7225 | #include "arm_neon.h" | ||
| 7226 | |||
| 7227 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c | ||
| 7228 | =================================================================== | ||
| 7229 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c | ||
| 7230 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c | ||
| 7231 | @@ -3,7 +3,8 @@ | ||
| 7232 | |||
| 7233 | /* { dg-do assemble } */ | ||
| 7234 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7235 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7236 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7237 | +/* { dg-add-options arm_neon } */ | ||
| 7238 | |||
| 7239 | #include "arm_neon.h" | ||
| 7240 | |||
| 7241 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c | ||
| 7242 | =================================================================== | ||
| 7243 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c | ||
| 7244 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c | ||
| 7245 | @@ -3,7 +3,8 @@ | ||
| 7246 | |||
| 7247 | /* { dg-do assemble } */ | ||
| 7248 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7249 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7250 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7251 | +/* { dg-add-options arm_neon } */ | ||
| 7252 | |||
| 7253 | #include "arm_neon.h" | ||
| 7254 | |||
| 7255 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c | ||
| 7256 | =================================================================== | ||
| 7257 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c | ||
| 7258 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c | ||
| 7259 | @@ -3,7 +3,8 @@ | ||
| 7260 | |||
| 7261 | /* { dg-do assemble } */ | ||
| 7262 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7263 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7264 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7265 | +/* { dg-add-options arm_neon } */ | ||
| 7266 | |||
| 7267 | #include "arm_neon.h" | ||
| 7268 | |||
| 7269 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c | ||
| 7270 | =================================================================== | ||
| 7271 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c | ||
| 7272 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c | ||
| 7273 | @@ -3,7 +3,8 @@ | ||
| 7274 | |||
| 7275 | /* { dg-do assemble } */ | ||
| 7276 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7277 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7278 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7279 | +/* { dg-add-options arm_neon } */ | ||
| 7280 | |||
| 7281 | #include "arm_neon.h" | ||
| 7282 | |||
| 7283 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c | ||
| 7284 | =================================================================== | ||
| 7285 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c | ||
| 7286 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c | ||
| 7287 | @@ -3,7 +3,8 @@ | ||
| 7288 | |||
| 7289 | /* { dg-do assemble } */ | ||
| 7290 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7291 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7292 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7293 | +/* { dg-add-options arm_neon } */ | ||
| 7294 | |||
| 7295 | #include "arm_neon.h" | ||
| 7296 | |||
| 7297 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c | ||
| 7298 | =================================================================== | ||
| 7299 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c | ||
| 7300 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c | ||
| 7301 | @@ -3,7 +3,8 @@ | ||
| 7302 | |||
| 7303 | /* { dg-do assemble } */ | ||
| 7304 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7305 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7306 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7307 | +/* { dg-add-options arm_neon } */ | ||
| 7308 | |||
| 7309 | #include "arm_neon.h" | ||
| 7310 | |||
| 7311 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c | ||
| 7312 | =================================================================== | ||
| 7313 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c | ||
| 7314 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c | ||
| 7315 | @@ -3,7 +3,8 @@ | ||
| 7316 | |||
| 7317 | /* { dg-do assemble } */ | ||
| 7318 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7319 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7320 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7321 | +/* { dg-add-options arm_neon } */ | ||
| 7322 | |||
| 7323 | #include "arm_neon.h" | ||
| 7324 | |||
| 7325 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c | ||
| 7326 | =================================================================== | ||
| 7327 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c | ||
| 7328 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c | ||
| 7329 | @@ -3,7 +3,8 @@ | ||
| 7330 | |||
| 7331 | /* { dg-do assemble } */ | ||
| 7332 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7333 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7334 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7335 | +/* { dg-add-options arm_neon } */ | ||
| 7336 | |||
| 7337 | #include "arm_neon.h" | ||
| 7338 | |||
| 7339 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c | ||
| 7340 | =================================================================== | ||
| 7341 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c | ||
| 7342 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c | ||
| 7343 | @@ -3,7 +3,8 @@ | ||
| 7344 | |||
| 7345 | /* { dg-do assemble } */ | ||
| 7346 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7347 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7348 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7349 | +/* { dg-add-options arm_neon } */ | ||
| 7350 | |||
| 7351 | #include "arm_neon.h" | ||
| 7352 | |||
| 7353 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c | ||
| 7354 | =================================================================== | ||
| 7355 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c | ||
| 7356 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c | ||
| 7357 | @@ -3,7 +3,8 @@ | ||
| 7358 | |||
| 7359 | /* { dg-do assemble } */ | ||
| 7360 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7361 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7362 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7363 | +/* { dg-add-options arm_neon } */ | ||
| 7364 | |||
| 7365 | #include "arm_neon.h" | ||
| 7366 | |||
| 7367 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c | ||
| 7368 | =================================================================== | ||
| 7369 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c | ||
| 7370 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c | ||
| 7371 | @@ -3,7 +3,8 @@ | ||
| 7372 | |||
| 7373 | /* { dg-do assemble } */ | ||
| 7374 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7375 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7376 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7377 | +/* { dg-add-options arm_neon } */ | ||
| 7378 | |||
| 7379 | #include "arm_neon.h" | ||
| 7380 | |||
| 7381 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c | ||
| 7382 | =================================================================== | ||
| 7383 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c | ||
| 7384 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c | ||
| 7385 | @@ -3,7 +3,8 @@ | ||
| 7386 | |||
| 7387 | /* { dg-do assemble } */ | ||
| 7388 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7389 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7390 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7391 | +/* { dg-add-options arm_neon } */ | ||
| 7392 | |||
| 7393 | #include "arm_neon.h" | ||
| 7394 | |||
| 7395 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c | ||
| 7396 | =================================================================== | ||
| 7397 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c | ||
| 7398 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c | ||
| 7399 | @@ -3,7 +3,8 @@ | ||
| 7400 | |||
| 7401 | /* { dg-do assemble } */ | ||
| 7402 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7403 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7404 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7405 | +/* { dg-add-options arm_neon } */ | ||
| 7406 | |||
| 7407 | #include "arm_neon.h" | ||
| 7408 | |||
| 7409 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c | ||
| 7410 | =================================================================== | ||
| 7411 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c | ||
| 7412 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c | ||
| 7413 | @@ -3,7 +3,8 @@ | ||
| 7414 | |||
| 7415 | /* { dg-do assemble } */ | ||
| 7416 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7417 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7418 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7419 | +/* { dg-add-options arm_neon } */ | ||
| 7420 | |||
| 7421 | #include "arm_neon.h" | ||
| 7422 | |||
| 7423 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c | ||
| 7424 | =================================================================== | ||
| 7425 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c | ||
| 7426 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c | ||
| 7427 | @@ -3,7 +3,8 @@ | ||
| 7428 | |||
| 7429 | /* { dg-do assemble } */ | ||
| 7430 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7431 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7432 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7433 | +/* { dg-add-options arm_neon } */ | ||
| 7434 | |||
| 7435 | #include "arm_neon.h" | ||
| 7436 | |||
| 7437 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c | ||
| 7438 | =================================================================== | ||
| 7439 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c | ||
| 7440 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c | ||
| 7441 | @@ -3,7 +3,8 @@ | ||
| 7442 | |||
| 7443 | /* { dg-do assemble } */ | ||
| 7444 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7445 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7446 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7447 | +/* { dg-add-options arm_neon } */ | ||
| 7448 | |||
| 7449 | #include "arm_neon.h" | ||
| 7450 | |||
| 7451 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c | ||
| 7452 | =================================================================== | ||
| 7453 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c | ||
| 7454 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c | ||
| 7455 | @@ -3,7 +3,8 @@ | ||
| 7456 | |||
| 7457 | /* { dg-do assemble } */ | ||
| 7458 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7459 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7460 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7461 | +/* { dg-add-options arm_neon } */ | ||
| 7462 | |||
| 7463 | #include "arm_neon.h" | ||
| 7464 | |||
| 7465 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c | ||
| 7466 | =================================================================== | ||
| 7467 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c | ||
| 7468 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c | ||
| 7469 | @@ -3,7 +3,8 @@ | ||
| 7470 | |||
| 7471 | /* { dg-do assemble } */ | ||
| 7472 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7473 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7474 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7475 | +/* { dg-add-options arm_neon } */ | ||
| 7476 | |||
| 7477 | #include "arm_neon.h" | ||
| 7478 | |||
| 7479 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c | ||
| 7480 | =================================================================== | ||
| 7481 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c | ||
| 7482 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c | ||
| 7483 | @@ -3,7 +3,8 @@ | ||
| 7484 | |||
| 7485 | /* { dg-do assemble } */ | ||
| 7486 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7487 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7488 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7489 | +/* { dg-add-options arm_neon } */ | ||
| 7490 | |||
| 7491 | #include "arm_neon.h" | ||
| 7492 | |||
| 7493 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c | ||
| 7494 | =================================================================== | ||
| 7495 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c | ||
| 7496 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c | ||
| 7497 | @@ -3,7 +3,8 @@ | ||
| 7498 | |||
| 7499 | /* { dg-do assemble } */ | ||
| 7500 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7501 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7502 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7503 | +/* { dg-add-options arm_neon } */ | ||
| 7504 | |||
| 7505 | #include "arm_neon.h" | ||
| 7506 | |||
| 7507 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c | ||
| 7508 | =================================================================== | ||
| 7509 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c | ||
| 7510 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c | ||
| 7511 | @@ -3,7 +3,8 @@ | ||
| 7512 | |||
| 7513 | /* { dg-do assemble } */ | ||
| 7514 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7515 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7516 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7517 | +/* { dg-add-options arm_neon } */ | ||
| 7518 | |||
| 7519 | #include "arm_neon.h" | ||
| 7520 | |||
| 7521 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c | ||
| 7522 | =================================================================== | ||
| 7523 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c | ||
| 7524 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c | ||
| 7525 | @@ -3,7 +3,8 @@ | ||
| 7526 | |||
| 7527 | /* { dg-do assemble } */ | ||
| 7528 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7529 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7530 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7531 | +/* { dg-add-options arm_neon } */ | ||
| 7532 | |||
| 7533 | #include "arm_neon.h" | ||
| 7534 | |||
| 7535 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c | ||
| 7536 | =================================================================== | ||
| 7537 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c | ||
| 7538 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c | ||
| 7539 | @@ -3,7 +3,8 @@ | ||
| 7540 | |||
| 7541 | /* { dg-do assemble } */ | ||
| 7542 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7543 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7544 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7545 | +/* { dg-add-options arm_neon } */ | ||
| 7546 | |||
| 7547 | #include "arm_neon.h" | ||
| 7548 | |||
| 7549 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c | ||
| 7550 | =================================================================== | ||
| 7551 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c | ||
| 7552 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c | ||
| 7553 | @@ -3,7 +3,8 @@ | ||
| 7554 | |||
| 7555 | /* { dg-do assemble } */ | ||
| 7556 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7557 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7558 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7559 | +/* { dg-add-options arm_neon } */ | ||
| 7560 | |||
| 7561 | #include "arm_neon.h" | ||
| 7562 | |||
| 7563 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c | ||
| 7564 | =================================================================== | ||
| 7565 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c | ||
| 7566 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c | ||
| 7567 | @@ -3,7 +3,8 @@ | ||
| 7568 | |||
| 7569 | /* { dg-do assemble } */ | ||
| 7570 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7571 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7572 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7573 | +/* { dg-add-options arm_neon } */ | ||
| 7574 | |||
| 7575 | #include "arm_neon.h" | ||
| 7576 | |||
| 7577 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c | ||
| 7578 | =================================================================== | ||
| 7579 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c | ||
| 7580 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c | ||
| 7581 | @@ -3,7 +3,8 @@ | ||
| 7582 | |||
| 7583 | /* { dg-do assemble } */ | ||
| 7584 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7585 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7586 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7587 | +/* { dg-add-options arm_neon } */ | ||
| 7588 | |||
| 7589 | #include "arm_neon.h" | ||
| 7590 | |||
| 7591 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c | ||
| 7592 | =================================================================== | ||
| 7593 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c | ||
| 7594 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c | ||
| 7595 | @@ -3,7 +3,8 @@ | ||
| 7596 | |||
| 7597 | /* { dg-do assemble } */ | ||
| 7598 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7599 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7600 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7601 | +/* { dg-add-options arm_neon } */ | ||
| 7602 | |||
| 7603 | #include "arm_neon.h" | ||
| 7604 | |||
| 7605 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c | ||
| 7606 | =================================================================== | ||
| 7607 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c | ||
| 7608 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c | ||
| 7609 | @@ -3,7 +3,8 @@ | ||
| 7610 | |||
| 7611 | /* { dg-do assemble } */ | ||
| 7612 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7613 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7614 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7615 | +/* { dg-add-options arm_neon } */ | ||
| 7616 | |||
| 7617 | #include "arm_neon.h" | ||
| 7618 | |||
| 7619 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c | ||
| 7620 | =================================================================== | ||
| 7621 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c | ||
| 7622 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c | ||
| 7623 | @@ -3,7 +3,8 @@ | ||
| 7624 | |||
| 7625 | /* { dg-do assemble } */ | ||
| 7626 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7627 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7628 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7629 | +/* { dg-add-options arm_neon } */ | ||
| 7630 | |||
| 7631 | #include "arm_neon.h" | ||
| 7632 | |||
| 7633 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c | ||
| 7634 | =================================================================== | ||
| 7635 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c | ||
| 7636 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c | ||
| 7637 | @@ -3,7 +3,8 @@ | ||
| 7638 | |||
| 7639 | /* { dg-do assemble } */ | ||
| 7640 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7641 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7642 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7643 | +/* { dg-add-options arm_neon } */ | ||
| 7644 | |||
| 7645 | #include "arm_neon.h" | ||
| 7646 | |||
| 7647 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c | ||
| 7648 | =================================================================== | ||
| 7649 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c | ||
| 7650 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c | ||
| 7651 | @@ -3,7 +3,8 @@ | ||
| 7652 | |||
| 7653 | /* { dg-do assemble } */ | ||
| 7654 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7655 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7656 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7657 | +/* { dg-add-options arm_neon } */ | ||
| 7658 | |||
| 7659 | #include "arm_neon.h" | ||
| 7660 | |||
| 7661 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c | ||
| 7662 | =================================================================== | ||
| 7663 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c | ||
| 7664 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c | ||
| 7665 | @@ -3,7 +3,8 @@ | ||
| 7666 | |||
| 7667 | /* { dg-do assemble } */ | ||
| 7668 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7669 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7670 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7671 | +/* { dg-add-options arm_neon } */ | ||
| 7672 | |||
| 7673 | #include "arm_neon.h" | ||
| 7674 | |||
| 7675 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c | ||
| 7676 | =================================================================== | ||
| 7677 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c | ||
| 7678 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c | ||
| 7679 | @@ -3,7 +3,8 @@ | ||
| 7680 | |||
| 7681 | /* { dg-do assemble } */ | ||
| 7682 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7683 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7684 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7685 | +/* { dg-add-options arm_neon } */ | ||
| 7686 | |||
| 7687 | #include "arm_neon.h" | ||
| 7688 | |||
| 7689 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c | ||
| 7690 | =================================================================== | ||
| 7691 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c | ||
| 7692 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c | ||
| 7693 | @@ -3,7 +3,8 @@ | ||
| 7694 | |||
| 7695 | /* { dg-do assemble } */ | ||
| 7696 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7697 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7698 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7699 | +/* { dg-add-options arm_neon } */ | ||
| 7700 | |||
| 7701 | #include "arm_neon.h" | ||
| 7702 | |||
| 7703 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c | ||
| 7704 | =================================================================== | ||
| 7705 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c | ||
| 7706 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c | ||
| 7707 | @@ -3,7 +3,8 @@ | ||
| 7708 | |||
| 7709 | /* { dg-do assemble } */ | ||
| 7710 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7711 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7712 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7713 | +/* { dg-add-options arm_neon } */ | ||
| 7714 | |||
| 7715 | #include "arm_neon.h" | ||
| 7716 | |||
| 7717 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c | ||
| 7718 | =================================================================== | ||
| 7719 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c | ||
| 7720 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c | ||
| 7721 | @@ -3,7 +3,8 @@ | ||
| 7722 | |||
| 7723 | /* { dg-do assemble } */ | ||
| 7724 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7725 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7726 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7727 | +/* { dg-add-options arm_neon } */ | ||
| 7728 | |||
| 7729 | #include "arm_neon.h" | ||
| 7730 | |||
| 7731 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c | ||
| 7732 | =================================================================== | ||
| 7733 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c | ||
| 7734 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c | ||
| 7735 | @@ -3,7 +3,8 @@ | ||
| 7736 | |||
| 7737 | /* { dg-do assemble } */ | ||
| 7738 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7739 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7740 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7741 | +/* { dg-add-options arm_neon } */ | ||
| 7742 | |||
| 7743 | #include "arm_neon.h" | ||
| 7744 | |||
| 7745 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c | ||
| 7746 | =================================================================== | ||
| 7747 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c | ||
| 7748 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c | ||
| 7749 | @@ -3,7 +3,8 @@ | ||
| 7750 | |||
| 7751 | /* { dg-do assemble } */ | ||
| 7752 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7753 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7754 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7755 | +/* { dg-add-options arm_neon } */ | ||
| 7756 | |||
| 7757 | #include "arm_neon.h" | ||
| 7758 | |||
| 7759 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c | ||
| 7760 | =================================================================== | ||
| 7761 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c | ||
| 7762 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c | ||
| 7763 | @@ -3,7 +3,8 @@ | ||
| 7764 | |||
| 7765 | /* { dg-do assemble } */ | ||
| 7766 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7767 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7768 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7769 | +/* { dg-add-options arm_neon } */ | ||
| 7770 | |||
| 7771 | #include "arm_neon.h" | ||
| 7772 | |||
| 7773 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c | ||
| 7774 | =================================================================== | ||
| 7775 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c | ||
| 7776 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c | ||
| 7777 | @@ -3,7 +3,8 @@ | ||
| 7778 | |||
| 7779 | /* { dg-do assemble } */ | ||
| 7780 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7781 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7782 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7783 | +/* { dg-add-options arm_neon } */ | ||
| 7784 | |||
| 7785 | #include "arm_neon.h" | ||
| 7786 | |||
| 7787 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c | ||
| 7788 | =================================================================== | ||
| 7789 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c | ||
| 7790 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c | ||
| 7791 | @@ -3,7 +3,8 @@ | ||
| 7792 | |||
| 7793 | /* { dg-do assemble } */ | ||
| 7794 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7795 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7796 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7797 | +/* { dg-add-options arm_neon } */ | ||
| 7798 | |||
| 7799 | #include "arm_neon.h" | ||
| 7800 | |||
| 7801 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c | ||
| 7802 | =================================================================== | ||
| 7803 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c | ||
| 7804 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c | ||
| 7805 | @@ -3,7 +3,8 @@ | ||
| 7806 | |||
| 7807 | /* { dg-do assemble } */ | ||
| 7808 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7809 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7810 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7811 | +/* { dg-add-options arm_neon } */ | ||
| 7812 | |||
| 7813 | #include "arm_neon.h" | ||
| 7814 | |||
| 7815 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c | ||
| 7816 | =================================================================== | ||
| 7817 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c | ||
| 7818 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c | ||
| 7819 | @@ -3,7 +3,8 @@ | ||
| 7820 | |||
| 7821 | /* { dg-do assemble } */ | ||
| 7822 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7823 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7824 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7825 | +/* { dg-add-options arm_neon } */ | ||
| 7826 | |||
| 7827 | #include "arm_neon.h" | ||
| 7828 | |||
| 7829 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c | ||
| 7830 | =================================================================== | ||
| 7831 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c | ||
| 7832 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c | ||
| 7833 | @@ -3,7 +3,8 @@ | ||
| 7834 | |||
| 7835 | /* { dg-do assemble } */ | ||
| 7836 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7837 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7838 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7839 | +/* { dg-add-options arm_neon } */ | ||
| 7840 | |||
| 7841 | #include "arm_neon.h" | ||
| 7842 | |||
| 7843 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c | ||
| 7844 | =================================================================== | ||
| 7845 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c | ||
| 7846 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c | ||
| 7847 | @@ -3,7 +3,8 @@ | ||
| 7848 | |||
| 7849 | /* { dg-do assemble } */ | ||
| 7850 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7851 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7852 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7853 | +/* { dg-add-options arm_neon } */ | ||
| 7854 | |||
| 7855 | #include "arm_neon.h" | ||
| 7856 | |||
| 7857 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c | ||
| 7858 | =================================================================== | ||
| 7859 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c | ||
| 7860 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c | ||
| 7861 | @@ -3,7 +3,8 @@ | ||
| 7862 | |||
| 7863 | /* { dg-do assemble } */ | ||
| 7864 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7865 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7866 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7867 | +/* { dg-add-options arm_neon } */ | ||
| 7868 | |||
| 7869 | #include "arm_neon.h" | ||
| 7870 | |||
| 7871 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c | ||
| 7872 | =================================================================== | ||
| 7873 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c | ||
| 7874 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c | ||
| 7875 | @@ -3,7 +3,8 @@ | ||
| 7876 | |||
| 7877 | /* { dg-do assemble } */ | ||
| 7878 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7879 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7880 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7881 | +/* { dg-add-options arm_neon } */ | ||
| 7882 | |||
| 7883 | #include "arm_neon.h" | ||
| 7884 | |||
| 7885 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c | ||
| 7886 | =================================================================== | ||
| 7887 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c | ||
| 7888 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c | ||
| 7889 | @@ -3,7 +3,8 @@ | ||
| 7890 | |||
| 7891 | /* { dg-do assemble } */ | ||
| 7892 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7893 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7894 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7895 | +/* { dg-add-options arm_neon } */ | ||
| 7896 | |||
| 7897 | #include "arm_neon.h" | ||
| 7898 | |||
| 7899 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c | ||
| 7900 | =================================================================== | ||
| 7901 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c | ||
| 7902 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c | ||
| 7903 | @@ -3,7 +3,8 @@ | ||
| 7904 | |||
| 7905 | /* { dg-do assemble } */ | ||
| 7906 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7907 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7908 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7909 | +/* { dg-add-options arm_neon } */ | ||
| 7910 | |||
| 7911 | #include "arm_neon.h" | ||
| 7912 | |||
| 7913 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c | ||
| 7914 | =================================================================== | ||
| 7915 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c | ||
| 7916 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c | ||
| 7917 | @@ -3,7 +3,8 @@ | ||
| 7918 | |||
| 7919 | /* { dg-do assemble } */ | ||
| 7920 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7921 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7922 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7923 | +/* { dg-add-options arm_neon } */ | ||
| 7924 | |||
| 7925 | #include "arm_neon.h" | ||
| 7926 | |||
| 7927 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c | ||
| 7928 | =================================================================== | ||
| 7929 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c | ||
| 7930 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c | ||
| 7931 | @@ -3,7 +3,8 @@ | ||
| 7932 | |||
| 7933 | /* { dg-do assemble } */ | ||
| 7934 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7935 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7936 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7937 | +/* { dg-add-options arm_neon } */ | ||
| 7938 | |||
| 7939 | #include "arm_neon.h" | ||
| 7940 | |||
| 7941 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c | ||
| 7942 | =================================================================== | ||
| 7943 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c | ||
| 7944 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c | ||
| 7945 | @@ -3,7 +3,8 @@ | ||
| 7946 | |||
| 7947 | /* { dg-do assemble } */ | ||
| 7948 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7949 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7950 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7951 | +/* { dg-add-options arm_neon } */ | ||
| 7952 | |||
| 7953 | #include "arm_neon.h" | ||
| 7954 | |||
| 7955 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c | ||
| 7956 | =================================================================== | ||
| 7957 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c | ||
| 7958 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c | ||
| 7959 | @@ -3,7 +3,8 @@ | ||
| 7960 | |||
| 7961 | /* { dg-do assemble } */ | ||
| 7962 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7963 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7964 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7965 | +/* { dg-add-options arm_neon } */ | ||
| 7966 | |||
| 7967 | #include "arm_neon.h" | ||
| 7968 | |||
| 7969 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c | ||
| 7970 | =================================================================== | ||
| 7971 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c | ||
| 7972 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c | ||
| 7973 | @@ -3,7 +3,8 @@ | ||
| 7974 | |||
| 7975 | /* { dg-do assemble } */ | ||
| 7976 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7977 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7978 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7979 | +/* { dg-add-options arm_neon } */ | ||
| 7980 | |||
| 7981 | #include "arm_neon.h" | ||
| 7982 | |||
| 7983 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c | ||
| 7984 | =================================================================== | ||
| 7985 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c | ||
| 7986 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c | ||
| 7987 | @@ -3,7 +3,8 @@ | ||
| 7988 | |||
| 7989 | /* { dg-do assemble } */ | ||
| 7990 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 7991 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 7992 | +/* { dg-options "-save-temps -O0" } */ | ||
| 7993 | +/* { dg-add-options arm_neon } */ | ||
| 7994 | |||
| 7995 | #include "arm_neon.h" | ||
| 7996 | |||
| 7997 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c | ||
| 7998 | =================================================================== | ||
| 7999 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c | ||
| 8000 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c | ||
| 8001 | @@ -3,7 +3,8 @@ | ||
| 8002 | |||
| 8003 | /* { dg-do assemble } */ | ||
| 8004 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8005 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8006 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8007 | +/* { dg-add-options arm_neon } */ | ||
| 8008 | |||
| 8009 | #include "arm_neon.h" | ||
| 8010 | |||
| 8011 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c | ||
| 8012 | =================================================================== | ||
| 8013 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c | ||
| 8014 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c | ||
| 8015 | @@ -3,7 +3,8 @@ | ||
| 8016 | |||
| 8017 | /* { dg-do assemble } */ | ||
| 8018 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8019 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8020 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8021 | +/* { dg-add-options arm_neon } */ | ||
| 8022 | |||
| 8023 | #include "arm_neon.h" | ||
| 8024 | |||
| 8025 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c | ||
| 8026 | =================================================================== | ||
| 8027 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c | ||
| 8028 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c | ||
| 8029 | @@ -3,7 +3,8 @@ | ||
| 8030 | |||
| 8031 | /* { dg-do assemble } */ | ||
| 8032 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8033 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8034 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8035 | +/* { dg-add-options arm_neon } */ | ||
| 8036 | |||
| 8037 | #include "arm_neon.h" | ||
| 8038 | |||
| 8039 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c | ||
| 8040 | =================================================================== | ||
| 8041 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c | ||
| 8042 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c | ||
| 8043 | @@ -3,7 +3,8 @@ | ||
| 8044 | |||
| 8045 | /* { dg-do assemble } */ | ||
| 8046 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8047 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8048 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8049 | +/* { dg-add-options arm_neon } */ | ||
| 8050 | |||
| 8051 | #include "arm_neon.h" | ||
| 8052 | |||
| 8053 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c | ||
| 8054 | =================================================================== | ||
| 8055 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c | ||
| 8056 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c | ||
| 8057 | @@ -3,7 +3,8 @@ | ||
| 8058 | |||
| 8059 | /* { dg-do assemble } */ | ||
| 8060 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8061 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8062 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8063 | +/* { dg-add-options arm_neon } */ | ||
| 8064 | |||
| 8065 | #include "arm_neon.h" | ||
| 8066 | |||
| 8067 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c | ||
| 8068 | =================================================================== | ||
| 8069 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c | ||
| 8070 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c | ||
| 8071 | @@ -3,7 +3,8 @@ | ||
| 8072 | |||
| 8073 | /* { dg-do assemble } */ | ||
| 8074 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8075 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8076 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8077 | +/* { dg-add-options arm_neon } */ | ||
| 8078 | |||
| 8079 | #include "arm_neon.h" | ||
| 8080 | |||
| 8081 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c | ||
| 8082 | =================================================================== | ||
| 8083 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c | ||
| 8084 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c | ||
| 8085 | @@ -3,7 +3,8 @@ | ||
| 8086 | |||
| 8087 | /* { dg-do assemble } */ | ||
| 8088 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8089 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8090 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8091 | +/* { dg-add-options arm_neon } */ | ||
| 8092 | |||
| 8093 | #include "arm_neon.h" | ||
| 8094 | |||
| 8095 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c | ||
| 8096 | =================================================================== | ||
| 8097 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c | ||
| 8098 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c | ||
| 8099 | @@ -3,7 +3,8 @@ | ||
| 8100 | |||
| 8101 | /* { dg-do assemble } */ | ||
| 8102 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8103 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8104 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8105 | +/* { dg-add-options arm_neon } */ | ||
| 8106 | |||
| 8107 | #include "arm_neon.h" | ||
| 8108 | |||
| 8109 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c | ||
| 8110 | =================================================================== | ||
| 8111 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c | ||
| 8112 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c | ||
| 8113 | @@ -3,7 +3,8 @@ | ||
| 8114 | |||
| 8115 | /* { dg-do assemble } */ | ||
| 8116 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8117 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8118 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8119 | +/* { dg-add-options arm_neon } */ | ||
| 8120 | |||
| 8121 | #include "arm_neon.h" | ||
| 8122 | |||
| 8123 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c | ||
| 8124 | =================================================================== | ||
| 8125 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c | ||
| 8126 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c | ||
| 8127 | @@ -3,7 +3,8 @@ | ||
| 8128 | |||
| 8129 | /* { dg-do assemble } */ | ||
| 8130 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8131 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8132 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8133 | +/* { dg-add-options arm_neon } */ | ||
| 8134 | |||
| 8135 | #include "arm_neon.h" | ||
| 8136 | |||
| 8137 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c | ||
| 8138 | =================================================================== | ||
| 8139 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c | ||
| 8140 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c | ||
| 8141 | @@ -3,7 +3,8 @@ | ||
| 8142 | |||
| 8143 | /* { dg-do assemble } */ | ||
| 8144 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8145 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8146 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8147 | +/* { dg-add-options arm_neon } */ | ||
| 8148 | |||
| 8149 | #include "arm_neon.h" | ||
| 8150 | |||
| 8151 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c | ||
| 8152 | =================================================================== | ||
| 8153 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c | ||
| 8154 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c | ||
| 8155 | @@ -3,7 +3,8 @@ | ||
| 8156 | |||
| 8157 | /* { dg-do assemble } */ | ||
| 8158 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8159 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8160 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8161 | +/* { dg-add-options arm_neon } */ | ||
| 8162 | |||
| 8163 | #include "arm_neon.h" | ||
| 8164 | |||
| 8165 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c | ||
| 8166 | =================================================================== | ||
| 8167 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c | ||
| 8168 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c | ||
| 8169 | @@ -3,7 +3,8 @@ | ||
| 8170 | |||
| 8171 | /* { dg-do assemble } */ | ||
| 8172 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8173 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8174 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8175 | +/* { dg-add-options arm_neon } */ | ||
| 8176 | |||
| 8177 | #include "arm_neon.h" | ||
| 8178 | |||
| 8179 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c | ||
| 8180 | =================================================================== | ||
| 8181 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c | ||
| 8182 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c | ||
| 8183 | @@ -3,7 +3,8 @@ | ||
| 8184 | |||
| 8185 | /* { dg-do assemble } */ | ||
| 8186 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8187 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8188 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8189 | +/* { dg-add-options arm_neon } */ | ||
| 8190 | |||
| 8191 | #include "arm_neon.h" | ||
| 8192 | |||
| 8193 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c | ||
| 8194 | =================================================================== | ||
| 8195 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c | ||
| 8196 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c | ||
| 8197 | @@ -3,7 +3,8 @@ | ||
| 8198 | |||
| 8199 | /* { dg-do assemble } */ | ||
| 8200 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8201 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8202 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8203 | +/* { dg-add-options arm_neon } */ | ||
| 8204 | |||
| 8205 | #include "arm_neon.h" | ||
| 8206 | |||
| 8207 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1f32.c | ||
| 8208 | =================================================================== | ||
| 8209 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1f32.c | ||
| 8210 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1f32.c | ||
| 8211 | @@ -3,7 +3,8 @@ | ||
| 8212 | |||
| 8213 | /* { dg-do assemble } */ | ||
| 8214 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8215 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8216 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8217 | +/* { dg-add-options arm_neon } */ | ||
| 8218 | |||
| 8219 | #include "arm_neon.h" | ||
| 8220 | |||
| 8221 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1p16.c | ||
| 8222 | =================================================================== | ||
| 8223 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1p16.c | ||
| 8224 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1p16.c | ||
| 8225 | @@ -3,7 +3,8 @@ | ||
| 8226 | |||
| 8227 | /* { dg-do assemble } */ | ||
| 8228 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8229 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8230 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8231 | +/* { dg-add-options arm_neon } */ | ||
| 8232 | |||
| 8233 | #include "arm_neon.h" | ||
| 8234 | |||
| 8235 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1p8.c | ||
| 8236 | =================================================================== | ||
| 8237 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1p8.c | ||
| 8238 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1p8.c | ||
| 8239 | @@ -3,7 +3,8 @@ | ||
| 8240 | |||
| 8241 | /* { dg-do assemble } */ | ||
| 8242 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8243 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8244 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8245 | +/* { dg-add-options arm_neon } */ | ||
| 8246 | |||
| 8247 | #include "arm_neon.h" | ||
| 8248 | |||
| 8249 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s16.c | ||
| 8250 | =================================================================== | ||
| 8251 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s16.c | ||
| 8252 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s16.c | ||
| 8253 | @@ -3,7 +3,8 @@ | ||
| 8254 | |||
| 8255 | /* { dg-do assemble } */ | ||
| 8256 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8257 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8258 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8259 | +/* { dg-add-options arm_neon } */ | ||
| 8260 | |||
| 8261 | #include "arm_neon.h" | ||
| 8262 | |||
| 8263 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s32.c | ||
| 8264 | =================================================================== | ||
| 8265 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s32.c | ||
| 8266 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s32.c | ||
| 8267 | @@ -3,7 +3,8 @@ | ||
| 8268 | |||
| 8269 | /* { dg-do assemble } */ | ||
| 8270 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8271 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8272 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8273 | +/* { dg-add-options arm_neon } */ | ||
| 8274 | |||
| 8275 | #include "arm_neon.h" | ||
| 8276 | |||
| 8277 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s64.c | ||
| 8278 | =================================================================== | ||
| 8279 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s64.c | ||
| 8280 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s64.c | ||
| 8281 | @@ -3,7 +3,8 @@ | ||
| 8282 | |||
| 8283 | /* { dg-do assemble } */ | ||
| 8284 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8285 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8286 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8287 | +/* { dg-add-options arm_neon } */ | ||
| 8288 | |||
| 8289 | #include "arm_neon.h" | ||
| 8290 | |||
| 8291 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s8.c | ||
| 8292 | =================================================================== | ||
| 8293 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s8.c | ||
| 8294 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1s8.c | ||
| 8295 | @@ -3,7 +3,8 @@ | ||
| 8296 | |||
| 8297 | /* { dg-do assemble } */ | ||
| 8298 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8299 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8300 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8301 | +/* { dg-add-options arm_neon } */ | ||
| 8302 | |||
| 8303 | #include "arm_neon.h" | ||
| 8304 | |||
| 8305 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u16.c | ||
| 8306 | =================================================================== | ||
| 8307 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u16.c | ||
| 8308 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u16.c | ||
| 8309 | @@ -3,7 +3,8 @@ | ||
| 8310 | |||
| 8311 | /* { dg-do assemble } */ | ||
| 8312 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8313 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8314 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8315 | +/* { dg-add-options arm_neon } */ | ||
| 8316 | |||
| 8317 | #include "arm_neon.h" | ||
| 8318 | |||
| 8319 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u32.c | ||
| 8320 | =================================================================== | ||
| 8321 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u32.c | ||
| 8322 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u32.c | ||
| 8323 | @@ -3,7 +3,8 @@ | ||
| 8324 | |||
| 8325 | /* { dg-do assemble } */ | ||
| 8326 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8327 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8328 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8329 | +/* { dg-add-options arm_neon } */ | ||
| 8330 | |||
| 8331 | #include "arm_neon.h" | ||
| 8332 | |||
| 8333 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u64.c | ||
| 8334 | =================================================================== | ||
| 8335 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u64.c | ||
| 8336 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u64.c | ||
| 8337 | @@ -3,7 +3,8 @@ | ||
| 8338 | |||
| 8339 | /* { dg-do assemble } */ | ||
| 8340 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8341 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8342 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8343 | +/* { dg-add-options arm_neon } */ | ||
| 8344 | |||
| 8345 | #include "arm_neon.h" | ||
| 8346 | |||
| 8347 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u8.c | ||
| 8348 | =================================================================== | ||
| 8349 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u8.c | ||
| 8350 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld1u8.c | ||
| 8351 | @@ -3,7 +3,8 @@ | ||
| 8352 | |||
| 8353 | /* { dg-do assemble } */ | ||
| 8354 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8355 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8356 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8357 | +/* { dg-add-options arm_neon } */ | ||
| 8358 | |||
| 8359 | #include "arm_neon.h" | ||
| 8360 | |||
| 8361 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c | ||
| 8362 | =================================================================== | ||
| 8363 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c | ||
| 8364 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c | ||
| 8365 | @@ -3,7 +3,8 @@ | ||
| 8366 | |||
| 8367 | /* { dg-do assemble } */ | ||
| 8368 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8369 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8370 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8371 | +/* { dg-add-options arm_neon } */ | ||
| 8372 | |||
| 8373 | #include "arm_neon.h" | ||
| 8374 | |||
| 8375 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c | ||
| 8376 | =================================================================== | ||
| 8377 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c | ||
| 8378 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c | ||
| 8379 | @@ -3,7 +3,8 @@ | ||
| 8380 | |||
| 8381 | /* { dg-do assemble } */ | ||
| 8382 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8383 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8384 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8385 | +/* { dg-add-options arm_neon } */ | ||
| 8386 | |||
| 8387 | #include "arm_neon.h" | ||
| 8388 | |||
| 8389 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c | ||
| 8390 | =================================================================== | ||
| 8391 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c | ||
| 8392 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c | ||
| 8393 | @@ -3,7 +3,8 @@ | ||
| 8394 | |||
| 8395 | /* { dg-do assemble } */ | ||
| 8396 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8397 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8398 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8399 | +/* { dg-add-options arm_neon } */ | ||
| 8400 | |||
| 8401 | #include "arm_neon.h" | ||
| 8402 | |||
| 8403 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c | ||
| 8404 | =================================================================== | ||
| 8405 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c | ||
| 8406 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c | ||
| 8407 | @@ -3,7 +3,8 @@ | ||
| 8408 | |||
| 8409 | /* { dg-do assemble } */ | ||
| 8410 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8411 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8412 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8413 | +/* { dg-add-options arm_neon } */ | ||
| 8414 | |||
| 8415 | #include "arm_neon.h" | ||
| 8416 | |||
| 8417 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c | ||
| 8418 | =================================================================== | ||
| 8419 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c | ||
| 8420 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c | ||
| 8421 | @@ -3,7 +3,8 @@ | ||
| 8422 | |||
| 8423 | /* { dg-do assemble } */ | ||
| 8424 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8425 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8426 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8427 | +/* { dg-add-options arm_neon } */ | ||
| 8428 | |||
| 8429 | #include "arm_neon.h" | ||
| 8430 | |||
| 8431 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c | ||
| 8432 | =================================================================== | ||
| 8433 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c | ||
| 8434 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c | ||
| 8435 | @@ -3,7 +3,8 @@ | ||
| 8436 | |||
| 8437 | /* { dg-do assemble } */ | ||
| 8438 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8439 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8440 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8441 | +/* { dg-add-options arm_neon } */ | ||
| 8442 | |||
| 8443 | #include "arm_neon.h" | ||
| 8444 | |||
| 8445 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c | ||
| 8446 | =================================================================== | ||
| 8447 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c | ||
| 8448 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c | ||
| 8449 | @@ -3,7 +3,8 @@ | ||
| 8450 | |||
| 8451 | /* { dg-do assemble } */ | ||
| 8452 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8453 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8454 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8455 | +/* { dg-add-options arm_neon } */ | ||
| 8456 | |||
| 8457 | #include "arm_neon.h" | ||
| 8458 | |||
| 8459 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c | ||
| 8460 | =================================================================== | ||
| 8461 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c | ||
| 8462 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c | ||
| 8463 | @@ -3,7 +3,8 @@ | ||
| 8464 | |||
| 8465 | /* { dg-do assemble } */ | ||
| 8466 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8467 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8468 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8469 | +/* { dg-add-options arm_neon } */ | ||
| 8470 | |||
| 8471 | #include "arm_neon.h" | ||
| 8472 | |||
| 8473 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c | ||
| 8474 | =================================================================== | ||
| 8475 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c | ||
| 8476 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c | ||
| 8477 | @@ -3,7 +3,8 @@ | ||
| 8478 | |||
| 8479 | /* { dg-do assemble } */ | ||
| 8480 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8481 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8482 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8483 | +/* { dg-add-options arm_neon } */ | ||
| 8484 | |||
| 8485 | #include "arm_neon.h" | ||
| 8486 | |||
| 8487 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c | ||
| 8488 | =================================================================== | ||
| 8489 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c | ||
| 8490 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c | ||
| 8491 | @@ -3,7 +3,8 @@ | ||
| 8492 | |||
| 8493 | /* { dg-do assemble } */ | ||
| 8494 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8495 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8496 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8497 | +/* { dg-add-options arm_neon } */ | ||
| 8498 | |||
| 8499 | #include "arm_neon.h" | ||
| 8500 | |||
| 8501 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c | ||
| 8502 | =================================================================== | ||
| 8503 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c | ||
| 8504 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c | ||
| 8505 | @@ -3,7 +3,8 @@ | ||
| 8506 | |||
| 8507 | /* { dg-do assemble } */ | ||
| 8508 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8509 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8510 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8511 | +/* { dg-add-options arm_neon } */ | ||
| 8512 | |||
| 8513 | #include "arm_neon.h" | ||
| 8514 | |||
| 8515 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c | ||
| 8516 | =================================================================== | ||
| 8517 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c | ||
| 8518 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c | ||
| 8519 | @@ -3,7 +3,8 @@ | ||
| 8520 | |||
| 8521 | /* { dg-do assemble } */ | ||
| 8522 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8523 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8524 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8525 | +/* { dg-add-options arm_neon } */ | ||
| 8526 | |||
| 8527 | #include "arm_neon.h" | ||
| 8528 | |||
| 8529 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c | ||
| 8530 | =================================================================== | ||
| 8531 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c | ||
| 8532 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c | ||
| 8533 | @@ -3,7 +3,8 @@ | ||
| 8534 | |||
| 8535 | /* { dg-do assemble } */ | ||
| 8536 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8537 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8538 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8539 | +/* { dg-add-options arm_neon } */ | ||
| 8540 | |||
| 8541 | #include "arm_neon.h" | ||
| 8542 | |||
| 8543 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c | ||
| 8544 | =================================================================== | ||
| 8545 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c | ||
| 8546 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c | ||
| 8547 | @@ -3,7 +3,8 @@ | ||
| 8548 | |||
| 8549 | /* { dg-do assemble } */ | ||
| 8550 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8551 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8552 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8553 | +/* { dg-add-options arm_neon } */ | ||
| 8554 | |||
| 8555 | #include "arm_neon.h" | ||
| 8556 | |||
| 8557 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c | ||
| 8558 | =================================================================== | ||
| 8559 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c | ||
| 8560 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c | ||
| 8561 | @@ -3,7 +3,8 @@ | ||
| 8562 | |||
| 8563 | /* { dg-do assemble } */ | ||
| 8564 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8565 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8566 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8567 | +/* { dg-add-options arm_neon } */ | ||
| 8568 | |||
| 8569 | #include "arm_neon.h" | ||
| 8570 | |||
| 8571 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c | ||
| 8572 | =================================================================== | ||
| 8573 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c | ||
| 8574 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c | ||
| 8575 | @@ -3,7 +3,8 @@ | ||
| 8576 | |||
| 8577 | /* { dg-do assemble } */ | ||
| 8578 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8579 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8580 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8581 | +/* { dg-add-options arm_neon } */ | ||
| 8582 | |||
| 8583 | #include "arm_neon.h" | ||
| 8584 | |||
| 8585 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c | ||
| 8586 | =================================================================== | ||
| 8587 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c | ||
| 8588 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c | ||
| 8589 | @@ -3,7 +3,8 @@ | ||
| 8590 | |||
| 8591 | /* { dg-do assemble } */ | ||
| 8592 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8593 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8594 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8595 | +/* { dg-add-options arm_neon } */ | ||
| 8596 | |||
| 8597 | #include "arm_neon.h" | ||
| 8598 | |||
| 8599 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c | ||
| 8600 | =================================================================== | ||
| 8601 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c | ||
| 8602 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c | ||
| 8603 | @@ -3,7 +3,8 @@ | ||
| 8604 | |||
| 8605 | /* { dg-do assemble } */ | ||
| 8606 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8607 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8608 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8609 | +/* { dg-add-options arm_neon } */ | ||
| 8610 | |||
| 8611 | #include "arm_neon.h" | ||
| 8612 | |||
| 8613 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c | ||
| 8614 | =================================================================== | ||
| 8615 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c | ||
| 8616 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c | ||
| 8617 | @@ -3,7 +3,8 @@ | ||
| 8618 | |||
| 8619 | /* { dg-do assemble } */ | ||
| 8620 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8621 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8622 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8623 | +/* { dg-add-options arm_neon } */ | ||
| 8624 | |||
| 8625 | #include "arm_neon.h" | ||
| 8626 | |||
| 8627 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c | ||
| 8628 | =================================================================== | ||
| 8629 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c | ||
| 8630 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c | ||
| 8631 | @@ -3,7 +3,8 @@ | ||
| 8632 | |||
| 8633 | /* { dg-do assemble } */ | ||
| 8634 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8635 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8636 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8637 | +/* { dg-add-options arm_neon } */ | ||
| 8638 | |||
| 8639 | #include "arm_neon.h" | ||
| 8640 | |||
| 8641 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c | ||
| 8642 | =================================================================== | ||
| 8643 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c | ||
| 8644 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c | ||
| 8645 | @@ -3,7 +3,8 @@ | ||
| 8646 | |||
| 8647 | /* { dg-do assemble } */ | ||
| 8648 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8649 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8650 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8651 | +/* { dg-add-options arm_neon } */ | ||
| 8652 | |||
| 8653 | #include "arm_neon.h" | ||
| 8654 | |||
| 8655 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c | ||
| 8656 | =================================================================== | ||
| 8657 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c | ||
| 8658 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c | ||
| 8659 | @@ -3,7 +3,8 @@ | ||
| 8660 | |||
| 8661 | /* { dg-do assemble } */ | ||
| 8662 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8663 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8664 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8665 | +/* { dg-add-options arm_neon } */ | ||
| 8666 | |||
| 8667 | #include "arm_neon.h" | ||
| 8668 | |||
| 8669 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c | ||
| 8670 | =================================================================== | ||
| 8671 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c | ||
| 8672 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c | ||
| 8673 | @@ -3,7 +3,8 @@ | ||
| 8674 | |||
| 8675 | /* { dg-do assemble } */ | ||
| 8676 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8677 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8678 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8679 | +/* { dg-add-options arm_neon } */ | ||
| 8680 | |||
| 8681 | #include "arm_neon.h" | ||
| 8682 | |||
| 8683 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c | ||
| 8684 | =================================================================== | ||
| 8685 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c | ||
| 8686 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c | ||
| 8687 | @@ -3,7 +3,8 @@ | ||
| 8688 | |||
| 8689 | /* { dg-do assemble } */ | ||
| 8690 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8691 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8692 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8693 | +/* { dg-add-options arm_neon } */ | ||
| 8694 | |||
| 8695 | #include "arm_neon.h" | ||
| 8696 | |||
| 8697 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c | ||
| 8698 | =================================================================== | ||
| 8699 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c | ||
| 8700 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c | ||
| 8701 | @@ -3,7 +3,8 @@ | ||
| 8702 | |||
| 8703 | /* { dg-do assemble } */ | ||
| 8704 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8705 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8706 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8707 | +/* { dg-add-options arm_neon } */ | ||
| 8708 | |||
| 8709 | #include "arm_neon.h" | ||
| 8710 | |||
| 8711 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c | ||
| 8712 | =================================================================== | ||
| 8713 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c | ||
| 8714 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c | ||
| 8715 | @@ -3,7 +3,8 @@ | ||
| 8716 | |||
| 8717 | /* { dg-do assemble } */ | ||
| 8718 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8719 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8720 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8721 | +/* { dg-add-options arm_neon } */ | ||
| 8722 | |||
| 8723 | #include "arm_neon.h" | ||
| 8724 | |||
| 8725 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c | ||
| 8726 | =================================================================== | ||
| 8727 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c | ||
| 8728 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c | ||
| 8729 | @@ -3,7 +3,8 @@ | ||
| 8730 | |||
| 8731 | /* { dg-do assemble } */ | ||
| 8732 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8733 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8734 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8735 | +/* { dg-add-options arm_neon } */ | ||
| 8736 | |||
| 8737 | #include "arm_neon.h" | ||
| 8738 | |||
| 8739 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c | ||
| 8740 | =================================================================== | ||
| 8741 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c | ||
| 8742 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c | ||
| 8743 | @@ -3,7 +3,8 @@ | ||
| 8744 | |||
| 8745 | /* { dg-do assemble } */ | ||
| 8746 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8747 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8748 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8749 | +/* { dg-add-options arm_neon } */ | ||
| 8750 | |||
| 8751 | #include "arm_neon.h" | ||
| 8752 | |||
| 8753 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c | ||
| 8754 | =================================================================== | ||
| 8755 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c | ||
| 8756 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c | ||
| 8757 | @@ -3,7 +3,8 @@ | ||
| 8758 | |||
| 8759 | /* { dg-do assemble } */ | ||
| 8760 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8761 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8762 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8763 | +/* { dg-add-options arm_neon } */ | ||
| 8764 | |||
| 8765 | #include "arm_neon.h" | ||
| 8766 | |||
| 8767 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c | ||
| 8768 | =================================================================== | ||
| 8769 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c | ||
| 8770 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c | ||
| 8771 | @@ -3,7 +3,8 @@ | ||
| 8772 | |||
| 8773 | /* { dg-do assemble } */ | ||
| 8774 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8775 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8776 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8777 | +/* { dg-add-options arm_neon } */ | ||
| 8778 | |||
| 8779 | #include "arm_neon.h" | ||
| 8780 | |||
| 8781 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c | ||
| 8782 | =================================================================== | ||
| 8783 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c | ||
| 8784 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c | ||
| 8785 | @@ -3,7 +3,8 @@ | ||
| 8786 | |||
| 8787 | /* { dg-do assemble } */ | ||
| 8788 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8789 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8790 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8791 | +/* { dg-add-options arm_neon } */ | ||
| 8792 | |||
| 8793 | #include "arm_neon.h" | ||
| 8794 | |||
| 8795 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c | ||
| 8796 | =================================================================== | ||
| 8797 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c | ||
| 8798 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c | ||
| 8799 | @@ -3,7 +3,8 @@ | ||
| 8800 | |||
| 8801 | /* { dg-do assemble } */ | ||
| 8802 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8803 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8804 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8805 | +/* { dg-add-options arm_neon } */ | ||
| 8806 | |||
| 8807 | #include "arm_neon.h" | ||
| 8808 | |||
| 8809 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c | ||
| 8810 | =================================================================== | ||
| 8811 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c | ||
| 8812 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c | ||
| 8813 | @@ -3,7 +3,8 @@ | ||
| 8814 | |||
| 8815 | /* { dg-do assemble } */ | ||
| 8816 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8817 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8818 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8819 | +/* { dg-add-options arm_neon } */ | ||
| 8820 | |||
| 8821 | #include "arm_neon.h" | ||
| 8822 | |||
| 8823 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c | ||
| 8824 | =================================================================== | ||
| 8825 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c | ||
| 8826 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c | ||
| 8827 | @@ -3,7 +3,8 @@ | ||
| 8828 | |||
| 8829 | /* { dg-do assemble } */ | ||
| 8830 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8831 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8832 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8833 | +/* { dg-add-options arm_neon } */ | ||
| 8834 | |||
| 8835 | #include "arm_neon.h" | ||
| 8836 | |||
| 8837 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c | ||
| 8838 | =================================================================== | ||
| 8839 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c | ||
| 8840 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c | ||
| 8841 | @@ -3,7 +3,8 @@ | ||
| 8842 | |||
| 8843 | /* { dg-do assemble } */ | ||
| 8844 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8845 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8846 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8847 | +/* { dg-add-options arm_neon } */ | ||
| 8848 | |||
| 8849 | #include "arm_neon.h" | ||
| 8850 | |||
| 8851 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2f32.c | ||
| 8852 | =================================================================== | ||
| 8853 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2f32.c | ||
| 8854 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2f32.c | ||
| 8855 | @@ -3,7 +3,8 @@ | ||
| 8856 | |||
| 8857 | /* { dg-do assemble } */ | ||
| 8858 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8859 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8860 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8861 | +/* { dg-add-options arm_neon } */ | ||
| 8862 | |||
| 8863 | #include "arm_neon.h" | ||
| 8864 | |||
| 8865 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2p16.c | ||
| 8866 | =================================================================== | ||
| 8867 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2p16.c | ||
| 8868 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2p16.c | ||
| 8869 | @@ -3,7 +3,8 @@ | ||
| 8870 | |||
| 8871 | /* { dg-do assemble } */ | ||
| 8872 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8873 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8874 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8875 | +/* { dg-add-options arm_neon } */ | ||
| 8876 | |||
| 8877 | #include "arm_neon.h" | ||
| 8878 | |||
| 8879 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2p8.c | ||
| 8880 | =================================================================== | ||
| 8881 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2p8.c | ||
| 8882 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2p8.c | ||
| 8883 | @@ -3,7 +3,8 @@ | ||
| 8884 | |||
| 8885 | /* { dg-do assemble } */ | ||
| 8886 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8887 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8888 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8889 | +/* { dg-add-options arm_neon } */ | ||
| 8890 | |||
| 8891 | #include "arm_neon.h" | ||
| 8892 | |||
| 8893 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s16.c | ||
| 8894 | =================================================================== | ||
| 8895 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s16.c | ||
| 8896 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s16.c | ||
| 8897 | @@ -3,7 +3,8 @@ | ||
| 8898 | |||
| 8899 | /* { dg-do assemble } */ | ||
| 8900 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8901 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8902 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8903 | +/* { dg-add-options arm_neon } */ | ||
| 8904 | |||
| 8905 | #include "arm_neon.h" | ||
| 8906 | |||
| 8907 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s32.c | ||
| 8908 | =================================================================== | ||
| 8909 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s32.c | ||
| 8910 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s32.c | ||
| 8911 | @@ -3,7 +3,8 @@ | ||
| 8912 | |||
| 8913 | /* { dg-do assemble } */ | ||
| 8914 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8915 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8916 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8917 | +/* { dg-add-options arm_neon } */ | ||
| 8918 | |||
| 8919 | #include "arm_neon.h" | ||
| 8920 | |||
| 8921 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s64.c | ||
| 8922 | =================================================================== | ||
| 8923 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s64.c | ||
| 8924 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s64.c | ||
| 8925 | @@ -3,7 +3,8 @@ | ||
| 8926 | |||
| 8927 | /* { dg-do assemble } */ | ||
| 8928 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8929 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8930 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8931 | +/* { dg-add-options arm_neon } */ | ||
| 8932 | |||
| 8933 | #include "arm_neon.h" | ||
| 8934 | |||
| 8935 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s8.c | ||
| 8936 | =================================================================== | ||
| 8937 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s8.c | ||
| 8938 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2s8.c | ||
| 8939 | @@ -3,7 +3,8 @@ | ||
| 8940 | |||
| 8941 | /* { dg-do assemble } */ | ||
| 8942 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8943 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8944 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8945 | +/* { dg-add-options arm_neon } */ | ||
| 8946 | |||
| 8947 | #include "arm_neon.h" | ||
| 8948 | |||
| 8949 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u16.c | ||
| 8950 | =================================================================== | ||
| 8951 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u16.c | ||
| 8952 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u16.c | ||
| 8953 | @@ -3,7 +3,8 @@ | ||
| 8954 | |||
| 8955 | /* { dg-do assemble } */ | ||
| 8956 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8957 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8958 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8959 | +/* { dg-add-options arm_neon } */ | ||
| 8960 | |||
| 8961 | #include "arm_neon.h" | ||
| 8962 | |||
| 8963 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u32.c | ||
| 8964 | =================================================================== | ||
| 8965 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u32.c | ||
| 8966 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u32.c | ||
| 8967 | @@ -3,7 +3,8 @@ | ||
| 8968 | |||
| 8969 | /* { dg-do assemble } */ | ||
| 8970 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8971 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8972 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8973 | +/* { dg-add-options arm_neon } */ | ||
| 8974 | |||
| 8975 | #include "arm_neon.h" | ||
| 8976 | |||
| 8977 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u64.c | ||
| 8978 | =================================================================== | ||
| 8979 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u64.c | ||
| 8980 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u64.c | ||
| 8981 | @@ -3,7 +3,8 @@ | ||
| 8982 | |||
| 8983 | /* { dg-do assemble } */ | ||
| 8984 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8985 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 8986 | +/* { dg-options "-save-temps -O0" } */ | ||
| 8987 | +/* { dg-add-options arm_neon } */ | ||
| 8988 | |||
| 8989 | #include "arm_neon.h" | ||
| 8990 | |||
| 8991 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u8.c | ||
| 8992 | =================================================================== | ||
| 8993 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u8.c | ||
| 8994 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld2u8.c | ||
| 8995 | @@ -3,7 +3,8 @@ | ||
| 8996 | |||
| 8997 | /* { dg-do assemble } */ | ||
| 8998 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 8999 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9000 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9001 | +/* { dg-add-options arm_neon } */ | ||
| 9002 | |||
| 9003 | #include "arm_neon.h" | ||
| 9004 | |||
| 9005 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c | ||
| 9006 | =================================================================== | ||
| 9007 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c | ||
| 9008 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c | ||
| 9009 | @@ -3,7 +3,8 @@ | ||
| 9010 | |||
| 9011 | /* { dg-do assemble } */ | ||
| 9012 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9013 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9014 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9015 | +/* { dg-add-options arm_neon } */ | ||
| 9016 | |||
| 9017 | #include "arm_neon.h" | ||
| 9018 | |||
| 9019 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c | ||
| 9020 | =================================================================== | ||
| 9021 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c | ||
| 9022 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c | ||
| 9023 | @@ -3,7 +3,8 @@ | ||
| 9024 | |||
| 9025 | /* { dg-do assemble } */ | ||
| 9026 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9027 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9028 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9029 | +/* { dg-add-options arm_neon } */ | ||
| 9030 | |||
| 9031 | #include "arm_neon.h" | ||
| 9032 | |||
| 9033 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c | ||
| 9034 | =================================================================== | ||
| 9035 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c | ||
| 9036 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c | ||
| 9037 | @@ -3,7 +3,8 @@ | ||
| 9038 | |||
| 9039 | /* { dg-do assemble } */ | ||
| 9040 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9041 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9042 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9043 | +/* { dg-add-options arm_neon } */ | ||
| 9044 | |||
| 9045 | #include "arm_neon.h" | ||
| 9046 | |||
| 9047 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c | ||
| 9048 | =================================================================== | ||
| 9049 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c | ||
| 9050 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c | ||
| 9051 | @@ -3,7 +3,8 @@ | ||
| 9052 | |||
| 9053 | /* { dg-do assemble } */ | ||
| 9054 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9055 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9056 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9057 | +/* { dg-add-options arm_neon } */ | ||
| 9058 | |||
| 9059 | #include "arm_neon.h" | ||
| 9060 | |||
| 9061 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c | ||
| 9062 | =================================================================== | ||
| 9063 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c | ||
| 9064 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c | ||
| 9065 | @@ -3,7 +3,8 @@ | ||
| 9066 | |||
| 9067 | /* { dg-do assemble } */ | ||
| 9068 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9069 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9070 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9071 | +/* { dg-add-options arm_neon } */ | ||
| 9072 | |||
| 9073 | #include "arm_neon.h" | ||
| 9074 | |||
| 9075 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c | ||
| 9076 | =================================================================== | ||
| 9077 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c | ||
| 9078 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c | ||
| 9079 | @@ -3,7 +3,8 @@ | ||
| 9080 | |||
| 9081 | /* { dg-do assemble } */ | ||
| 9082 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9083 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9084 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9085 | +/* { dg-add-options arm_neon } */ | ||
| 9086 | |||
| 9087 | #include "arm_neon.h" | ||
| 9088 | |||
| 9089 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c | ||
| 9090 | =================================================================== | ||
| 9091 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c | ||
| 9092 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c | ||
| 9093 | @@ -3,7 +3,8 @@ | ||
| 9094 | |||
| 9095 | /* { dg-do assemble } */ | ||
| 9096 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9097 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9098 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9099 | +/* { dg-add-options arm_neon } */ | ||
| 9100 | |||
| 9101 | #include "arm_neon.h" | ||
| 9102 | |||
| 9103 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c | ||
| 9104 | =================================================================== | ||
| 9105 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c | ||
| 9106 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c | ||
| 9107 | @@ -3,7 +3,8 @@ | ||
| 9108 | |||
| 9109 | /* { dg-do assemble } */ | ||
| 9110 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9111 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9112 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9113 | +/* { dg-add-options arm_neon } */ | ||
| 9114 | |||
| 9115 | #include "arm_neon.h" | ||
| 9116 | |||
| 9117 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c | ||
| 9118 | =================================================================== | ||
| 9119 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c | ||
| 9120 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c | ||
| 9121 | @@ -3,7 +3,8 @@ | ||
| 9122 | |||
| 9123 | /* { dg-do assemble } */ | ||
| 9124 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9125 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9126 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9127 | +/* { dg-add-options arm_neon } */ | ||
| 9128 | |||
| 9129 | #include "arm_neon.h" | ||
| 9130 | |||
| 9131 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c | ||
| 9132 | =================================================================== | ||
| 9133 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c | ||
| 9134 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c | ||
| 9135 | @@ -3,7 +3,8 @@ | ||
| 9136 | |||
| 9137 | /* { dg-do assemble } */ | ||
| 9138 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9139 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9140 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9141 | +/* { dg-add-options arm_neon } */ | ||
| 9142 | |||
| 9143 | #include "arm_neon.h" | ||
| 9144 | |||
| 9145 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c | ||
| 9146 | =================================================================== | ||
| 9147 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c | ||
| 9148 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c | ||
| 9149 | @@ -3,7 +3,8 @@ | ||
| 9150 | |||
| 9151 | /* { dg-do assemble } */ | ||
| 9152 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9153 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9154 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9155 | +/* { dg-add-options arm_neon } */ | ||
| 9156 | |||
| 9157 | #include "arm_neon.h" | ||
| 9158 | |||
| 9159 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c | ||
| 9160 | =================================================================== | ||
| 9161 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c | ||
| 9162 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c | ||
| 9163 | @@ -3,7 +3,8 @@ | ||
| 9164 | |||
| 9165 | /* { dg-do assemble } */ | ||
| 9166 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9167 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9168 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9169 | +/* { dg-add-options arm_neon } */ | ||
| 9170 | |||
| 9171 | #include "arm_neon.h" | ||
| 9172 | |||
| 9173 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c | ||
| 9174 | =================================================================== | ||
| 9175 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c | ||
| 9176 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c | ||
| 9177 | @@ -3,7 +3,8 @@ | ||
| 9178 | |||
| 9179 | /* { dg-do assemble } */ | ||
| 9180 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9181 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9182 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9183 | +/* { dg-add-options arm_neon } */ | ||
| 9184 | |||
| 9185 | #include "arm_neon.h" | ||
| 9186 | |||
| 9187 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c | ||
| 9188 | =================================================================== | ||
| 9189 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c | ||
| 9190 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c | ||
| 9191 | @@ -3,7 +3,8 @@ | ||
| 9192 | |||
| 9193 | /* { dg-do assemble } */ | ||
| 9194 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9195 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9196 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9197 | +/* { dg-add-options arm_neon } */ | ||
| 9198 | |||
| 9199 | #include "arm_neon.h" | ||
| 9200 | |||
| 9201 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c | ||
| 9202 | =================================================================== | ||
| 9203 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c | ||
| 9204 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c | ||
| 9205 | @@ -3,7 +3,8 @@ | ||
| 9206 | |||
| 9207 | /* { dg-do assemble } */ | ||
| 9208 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9209 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9210 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9211 | +/* { dg-add-options arm_neon } */ | ||
| 9212 | |||
| 9213 | #include "arm_neon.h" | ||
| 9214 | |||
| 9215 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c | ||
| 9216 | =================================================================== | ||
| 9217 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c | ||
| 9218 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c | ||
| 9219 | @@ -3,7 +3,8 @@ | ||
| 9220 | |||
| 9221 | /* { dg-do assemble } */ | ||
| 9222 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9223 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9224 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9225 | +/* { dg-add-options arm_neon } */ | ||
| 9226 | |||
| 9227 | #include "arm_neon.h" | ||
| 9228 | |||
| 9229 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c | ||
| 9230 | =================================================================== | ||
| 9231 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c | ||
| 9232 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c | ||
| 9233 | @@ -3,7 +3,8 @@ | ||
| 9234 | |||
| 9235 | /* { dg-do assemble } */ | ||
| 9236 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9237 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9238 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9239 | +/* { dg-add-options arm_neon } */ | ||
| 9240 | |||
| 9241 | #include "arm_neon.h" | ||
| 9242 | |||
| 9243 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c | ||
| 9244 | =================================================================== | ||
| 9245 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c | ||
| 9246 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c | ||
| 9247 | @@ -3,7 +3,8 @@ | ||
| 9248 | |||
| 9249 | /* { dg-do assemble } */ | ||
| 9250 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9251 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9252 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9253 | +/* { dg-add-options arm_neon } */ | ||
| 9254 | |||
| 9255 | #include "arm_neon.h" | ||
| 9256 | |||
| 9257 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c | ||
| 9258 | =================================================================== | ||
| 9259 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c | ||
| 9260 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c | ||
| 9261 | @@ -3,7 +3,8 @@ | ||
| 9262 | |||
| 9263 | /* { dg-do assemble } */ | ||
| 9264 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9265 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9266 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9267 | +/* { dg-add-options arm_neon } */ | ||
| 9268 | |||
| 9269 | #include "arm_neon.h" | ||
| 9270 | |||
| 9271 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c | ||
| 9272 | =================================================================== | ||
| 9273 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c | ||
| 9274 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c | ||
| 9275 | @@ -3,7 +3,8 @@ | ||
| 9276 | |||
| 9277 | /* { dg-do assemble } */ | ||
| 9278 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9279 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9280 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9281 | +/* { dg-add-options arm_neon } */ | ||
| 9282 | |||
| 9283 | #include "arm_neon.h" | ||
| 9284 | |||
| 9285 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c | ||
| 9286 | =================================================================== | ||
| 9287 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c | ||
| 9288 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c | ||
| 9289 | @@ -3,7 +3,8 @@ | ||
| 9290 | |||
| 9291 | /* { dg-do assemble } */ | ||
| 9292 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9293 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9294 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9295 | +/* { dg-add-options arm_neon } */ | ||
| 9296 | |||
| 9297 | #include "arm_neon.h" | ||
| 9298 | |||
| 9299 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c | ||
| 9300 | =================================================================== | ||
| 9301 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c | ||
| 9302 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c | ||
| 9303 | @@ -3,7 +3,8 @@ | ||
| 9304 | |||
| 9305 | /* { dg-do assemble } */ | ||
| 9306 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9307 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9308 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9309 | +/* { dg-add-options arm_neon } */ | ||
| 9310 | |||
| 9311 | #include "arm_neon.h" | ||
| 9312 | |||
| 9313 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c | ||
| 9314 | =================================================================== | ||
| 9315 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c | ||
| 9316 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c | ||
| 9317 | @@ -3,7 +3,8 @@ | ||
| 9318 | |||
| 9319 | /* { dg-do assemble } */ | ||
| 9320 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9321 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9322 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9323 | +/* { dg-add-options arm_neon } */ | ||
| 9324 | |||
| 9325 | #include "arm_neon.h" | ||
| 9326 | |||
| 9327 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c | ||
| 9328 | =================================================================== | ||
| 9329 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c | ||
| 9330 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c | ||
| 9331 | @@ -3,7 +3,8 @@ | ||
| 9332 | |||
| 9333 | /* { dg-do assemble } */ | ||
| 9334 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9335 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9336 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9337 | +/* { dg-add-options arm_neon } */ | ||
| 9338 | |||
| 9339 | #include "arm_neon.h" | ||
| 9340 | |||
| 9341 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c | ||
| 9342 | =================================================================== | ||
| 9343 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c | ||
| 9344 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c | ||
| 9345 | @@ -3,7 +3,8 @@ | ||
| 9346 | |||
| 9347 | /* { dg-do assemble } */ | ||
| 9348 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9349 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9350 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9351 | +/* { dg-add-options arm_neon } */ | ||
| 9352 | |||
| 9353 | #include "arm_neon.h" | ||
| 9354 | |||
| 9355 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c | ||
| 9356 | =================================================================== | ||
| 9357 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c | ||
| 9358 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c | ||
| 9359 | @@ -3,7 +3,8 @@ | ||
| 9360 | |||
| 9361 | /* { dg-do assemble } */ | ||
| 9362 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9363 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9364 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9365 | +/* { dg-add-options arm_neon } */ | ||
| 9366 | |||
| 9367 | #include "arm_neon.h" | ||
| 9368 | |||
| 9369 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c | ||
| 9370 | =================================================================== | ||
| 9371 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c | ||
| 9372 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c | ||
| 9373 | @@ -3,7 +3,8 @@ | ||
| 9374 | |||
| 9375 | /* { dg-do assemble } */ | ||
| 9376 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9377 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9378 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9379 | +/* { dg-add-options arm_neon } */ | ||
| 9380 | |||
| 9381 | #include "arm_neon.h" | ||
| 9382 | |||
| 9383 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c | ||
| 9384 | =================================================================== | ||
| 9385 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c | ||
| 9386 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c | ||
| 9387 | @@ -3,7 +3,8 @@ | ||
| 9388 | |||
| 9389 | /* { dg-do assemble } */ | ||
| 9390 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9391 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9392 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9393 | +/* { dg-add-options arm_neon } */ | ||
| 9394 | |||
| 9395 | #include "arm_neon.h" | ||
| 9396 | |||
| 9397 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c | ||
| 9398 | =================================================================== | ||
| 9399 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c | ||
| 9400 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c | ||
| 9401 | @@ -3,7 +3,8 @@ | ||
| 9402 | |||
| 9403 | /* { dg-do assemble } */ | ||
| 9404 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9405 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9406 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9407 | +/* { dg-add-options arm_neon } */ | ||
| 9408 | |||
| 9409 | #include "arm_neon.h" | ||
| 9410 | |||
| 9411 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c | ||
| 9412 | =================================================================== | ||
| 9413 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c | ||
| 9414 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c | ||
| 9415 | @@ -3,7 +3,8 @@ | ||
| 9416 | |||
| 9417 | /* { dg-do assemble } */ | ||
| 9418 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9419 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9420 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9421 | +/* { dg-add-options arm_neon } */ | ||
| 9422 | |||
| 9423 | #include "arm_neon.h" | ||
| 9424 | |||
| 9425 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c | ||
| 9426 | =================================================================== | ||
| 9427 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c | ||
| 9428 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c | ||
| 9429 | @@ -3,7 +3,8 @@ | ||
| 9430 | |||
| 9431 | /* { dg-do assemble } */ | ||
| 9432 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9433 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9434 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9435 | +/* { dg-add-options arm_neon } */ | ||
| 9436 | |||
| 9437 | #include "arm_neon.h" | ||
| 9438 | |||
| 9439 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c | ||
| 9440 | =================================================================== | ||
| 9441 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c | ||
| 9442 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c | ||
| 9443 | @@ -3,7 +3,8 @@ | ||
| 9444 | |||
| 9445 | /* { dg-do assemble } */ | ||
| 9446 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9447 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9448 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9449 | +/* { dg-add-options arm_neon } */ | ||
| 9450 | |||
| 9451 | #include "arm_neon.h" | ||
| 9452 | |||
| 9453 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c | ||
| 9454 | =================================================================== | ||
| 9455 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c | ||
| 9456 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c | ||
| 9457 | @@ -3,7 +3,8 @@ | ||
| 9458 | |||
| 9459 | /* { dg-do assemble } */ | ||
| 9460 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9461 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9462 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9463 | +/* { dg-add-options arm_neon } */ | ||
| 9464 | |||
| 9465 | #include "arm_neon.h" | ||
| 9466 | |||
| 9467 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c | ||
| 9468 | =================================================================== | ||
| 9469 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c | ||
| 9470 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c | ||
| 9471 | @@ -3,7 +3,8 @@ | ||
| 9472 | |||
| 9473 | /* { dg-do assemble } */ | ||
| 9474 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9475 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9476 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9477 | +/* { dg-add-options arm_neon } */ | ||
| 9478 | |||
| 9479 | #include "arm_neon.h" | ||
| 9480 | |||
| 9481 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c | ||
| 9482 | =================================================================== | ||
| 9483 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c | ||
| 9484 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c | ||
| 9485 | @@ -3,7 +3,8 @@ | ||
| 9486 | |||
| 9487 | /* { dg-do assemble } */ | ||
| 9488 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9489 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9490 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9491 | +/* { dg-add-options arm_neon } */ | ||
| 9492 | |||
| 9493 | #include "arm_neon.h" | ||
| 9494 | |||
| 9495 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3f32.c | ||
| 9496 | =================================================================== | ||
| 9497 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3f32.c | ||
| 9498 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3f32.c | ||
| 9499 | @@ -3,7 +3,8 @@ | ||
| 9500 | |||
| 9501 | /* { dg-do assemble } */ | ||
| 9502 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9503 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9504 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9505 | +/* { dg-add-options arm_neon } */ | ||
| 9506 | |||
| 9507 | #include "arm_neon.h" | ||
| 9508 | |||
| 9509 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3p16.c | ||
| 9510 | =================================================================== | ||
| 9511 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3p16.c | ||
| 9512 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3p16.c | ||
| 9513 | @@ -3,7 +3,8 @@ | ||
| 9514 | |||
| 9515 | /* { dg-do assemble } */ | ||
| 9516 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9517 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9518 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9519 | +/* { dg-add-options arm_neon } */ | ||
| 9520 | |||
| 9521 | #include "arm_neon.h" | ||
| 9522 | |||
| 9523 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3p8.c | ||
| 9524 | =================================================================== | ||
| 9525 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3p8.c | ||
| 9526 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3p8.c | ||
| 9527 | @@ -3,7 +3,8 @@ | ||
| 9528 | |||
| 9529 | /* { dg-do assemble } */ | ||
| 9530 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9531 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9532 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9533 | +/* { dg-add-options arm_neon } */ | ||
| 9534 | |||
| 9535 | #include "arm_neon.h" | ||
| 9536 | |||
| 9537 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s16.c | ||
| 9538 | =================================================================== | ||
| 9539 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s16.c | ||
| 9540 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s16.c | ||
| 9541 | @@ -3,7 +3,8 @@ | ||
| 9542 | |||
| 9543 | /* { dg-do assemble } */ | ||
| 9544 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9545 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9546 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9547 | +/* { dg-add-options arm_neon } */ | ||
| 9548 | |||
| 9549 | #include "arm_neon.h" | ||
| 9550 | |||
| 9551 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s32.c | ||
| 9552 | =================================================================== | ||
| 9553 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s32.c | ||
| 9554 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s32.c | ||
| 9555 | @@ -3,7 +3,8 @@ | ||
| 9556 | |||
| 9557 | /* { dg-do assemble } */ | ||
| 9558 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9559 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9560 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9561 | +/* { dg-add-options arm_neon } */ | ||
| 9562 | |||
| 9563 | #include "arm_neon.h" | ||
| 9564 | |||
| 9565 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s64.c | ||
| 9566 | =================================================================== | ||
| 9567 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s64.c | ||
| 9568 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s64.c | ||
| 9569 | @@ -3,7 +3,8 @@ | ||
| 9570 | |||
| 9571 | /* { dg-do assemble } */ | ||
| 9572 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9573 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9574 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9575 | +/* { dg-add-options arm_neon } */ | ||
| 9576 | |||
| 9577 | #include "arm_neon.h" | ||
| 9578 | |||
| 9579 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s8.c | ||
| 9580 | =================================================================== | ||
| 9581 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s8.c | ||
| 9582 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3s8.c | ||
| 9583 | @@ -3,7 +3,8 @@ | ||
| 9584 | |||
| 9585 | /* { dg-do assemble } */ | ||
| 9586 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9587 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9588 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9589 | +/* { dg-add-options arm_neon } */ | ||
| 9590 | |||
| 9591 | #include "arm_neon.h" | ||
| 9592 | |||
| 9593 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u16.c | ||
| 9594 | =================================================================== | ||
| 9595 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u16.c | ||
| 9596 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u16.c | ||
| 9597 | @@ -3,7 +3,8 @@ | ||
| 9598 | |||
| 9599 | /* { dg-do assemble } */ | ||
| 9600 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9601 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9602 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9603 | +/* { dg-add-options arm_neon } */ | ||
| 9604 | |||
| 9605 | #include "arm_neon.h" | ||
| 9606 | |||
| 9607 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u32.c | ||
| 9608 | =================================================================== | ||
| 9609 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u32.c | ||
| 9610 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u32.c | ||
| 9611 | @@ -3,7 +3,8 @@ | ||
| 9612 | |||
| 9613 | /* { dg-do assemble } */ | ||
| 9614 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9615 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9616 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9617 | +/* { dg-add-options arm_neon } */ | ||
| 9618 | |||
| 9619 | #include "arm_neon.h" | ||
| 9620 | |||
| 9621 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u64.c | ||
| 9622 | =================================================================== | ||
| 9623 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u64.c | ||
| 9624 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u64.c | ||
| 9625 | @@ -3,7 +3,8 @@ | ||
| 9626 | |||
| 9627 | /* { dg-do assemble } */ | ||
| 9628 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9629 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9630 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9631 | +/* { dg-add-options arm_neon } */ | ||
| 9632 | |||
| 9633 | #include "arm_neon.h" | ||
| 9634 | |||
| 9635 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u8.c | ||
| 9636 | =================================================================== | ||
| 9637 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u8.c | ||
| 9638 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld3u8.c | ||
| 9639 | @@ -3,7 +3,8 @@ | ||
| 9640 | |||
| 9641 | /* { dg-do assemble } */ | ||
| 9642 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9643 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9644 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9645 | +/* { dg-add-options arm_neon } */ | ||
| 9646 | |||
| 9647 | #include "arm_neon.h" | ||
| 9648 | |||
| 9649 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c | ||
| 9650 | =================================================================== | ||
| 9651 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c | ||
| 9652 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c | ||
| 9653 | @@ -3,7 +3,8 @@ | ||
| 9654 | |||
| 9655 | /* { dg-do assemble } */ | ||
| 9656 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9657 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9658 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9659 | +/* { dg-add-options arm_neon } */ | ||
| 9660 | |||
| 9661 | #include "arm_neon.h" | ||
| 9662 | |||
| 9663 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c | ||
| 9664 | =================================================================== | ||
| 9665 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c | ||
| 9666 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c | ||
| 9667 | @@ -3,7 +3,8 @@ | ||
| 9668 | |||
| 9669 | /* { dg-do assemble } */ | ||
| 9670 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9671 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9672 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9673 | +/* { dg-add-options arm_neon } */ | ||
| 9674 | |||
| 9675 | #include "arm_neon.h" | ||
| 9676 | |||
| 9677 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c | ||
| 9678 | =================================================================== | ||
| 9679 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c | ||
| 9680 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c | ||
| 9681 | @@ -3,7 +3,8 @@ | ||
| 9682 | |||
| 9683 | /* { dg-do assemble } */ | ||
| 9684 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9685 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9686 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9687 | +/* { dg-add-options arm_neon } */ | ||
| 9688 | |||
| 9689 | #include "arm_neon.h" | ||
| 9690 | |||
| 9691 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c | ||
| 9692 | =================================================================== | ||
| 9693 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c | ||
| 9694 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c | ||
| 9695 | @@ -3,7 +3,8 @@ | ||
| 9696 | |||
| 9697 | /* { dg-do assemble } */ | ||
| 9698 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9699 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9700 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9701 | +/* { dg-add-options arm_neon } */ | ||
| 9702 | |||
| 9703 | #include "arm_neon.h" | ||
| 9704 | |||
| 9705 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c | ||
| 9706 | =================================================================== | ||
| 9707 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c | ||
| 9708 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c | ||
| 9709 | @@ -3,7 +3,8 @@ | ||
| 9710 | |||
| 9711 | /* { dg-do assemble } */ | ||
| 9712 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9713 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9714 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9715 | +/* { dg-add-options arm_neon } */ | ||
| 9716 | |||
| 9717 | #include "arm_neon.h" | ||
| 9718 | |||
| 9719 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c | ||
| 9720 | =================================================================== | ||
| 9721 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c | ||
| 9722 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c | ||
| 9723 | @@ -3,7 +3,8 @@ | ||
| 9724 | |||
| 9725 | /* { dg-do assemble } */ | ||
| 9726 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9727 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9728 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9729 | +/* { dg-add-options arm_neon } */ | ||
| 9730 | |||
| 9731 | #include "arm_neon.h" | ||
| 9732 | |||
| 9733 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c | ||
| 9734 | =================================================================== | ||
| 9735 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c | ||
| 9736 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c | ||
| 9737 | @@ -3,7 +3,8 @@ | ||
| 9738 | |||
| 9739 | /* { dg-do assemble } */ | ||
| 9740 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9741 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9742 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9743 | +/* { dg-add-options arm_neon } */ | ||
| 9744 | |||
| 9745 | #include "arm_neon.h" | ||
| 9746 | |||
| 9747 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c | ||
| 9748 | =================================================================== | ||
| 9749 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c | ||
| 9750 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c | ||
| 9751 | @@ -3,7 +3,8 @@ | ||
| 9752 | |||
| 9753 | /* { dg-do assemble } */ | ||
| 9754 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9755 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9756 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9757 | +/* { dg-add-options arm_neon } */ | ||
| 9758 | |||
| 9759 | #include "arm_neon.h" | ||
| 9760 | |||
| 9761 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c | ||
| 9762 | =================================================================== | ||
| 9763 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c | ||
| 9764 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c | ||
| 9765 | @@ -3,7 +3,8 @@ | ||
| 9766 | |||
| 9767 | /* { dg-do assemble } */ | ||
| 9768 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9769 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9770 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9771 | +/* { dg-add-options arm_neon } */ | ||
| 9772 | |||
| 9773 | #include "arm_neon.h" | ||
| 9774 | |||
| 9775 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c | ||
| 9776 | =================================================================== | ||
| 9777 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c | ||
| 9778 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c | ||
| 9779 | @@ -3,7 +3,8 @@ | ||
| 9780 | |||
| 9781 | /* { dg-do assemble } */ | ||
| 9782 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9783 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9784 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9785 | +/* { dg-add-options arm_neon } */ | ||
| 9786 | |||
| 9787 | #include "arm_neon.h" | ||
| 9788 | |||
| 9789 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c | ||
| 9790 | =================================================================== | ||
| 9791 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c | ||
| 9792 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c | ||
| 9793 | @@ -3,7 +3,8 @@ | ||
| 9794 | |||
| 9795 | /* { dg-do assemble } */ | ||
| 9796 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9797 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9798 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9799 | +/* { dg-add-options arm_neon } */ | ||
| 9800 | |||
| 9801 | #include "arm_neon.h" | ||
| 9802 | |||
| 9803 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c | ||
| 9804 | =================================================================== | ||
| 9805 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c | ||
| 9806 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c | ||
| 9807 | @@ -3,7 +3,8 @@ | ||
| 9808 | |||
| 9809 | /* { dg-do assemble } */ | ||
| 9810 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9811 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9812 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9813 | +/* { dg-add-options arm_neon } */ | ||
| 9814 | |||
| 9815 | #include "arm_neon.h" | ||
| 9816 | |||
| 9817 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c | ||
| 9818 | =================================================================== | ||
| 9819 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c | ||
| 9820 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c | ||
| 9821 | @@ -3,7 +3,8 @@ | ||
| 9822 | |||
| 9823 | /* { dg-do assemble } */ | ||
| 9824 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9825 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9826 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9827 | +/* { dg-add-options arm_neon } */ | ||
| 9828 | |||
| 9829 | #include "arm_neon.h" | ||
| 9830 | |||
| 9831 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c | ||
| 9832 | =================================================================== | ||
| 9833 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c | ||
| 9834 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c | ||
| 9835 | @@ -3,7 +3,8 @@ | ||
| 9836 | |||
| 9837 | /* { dg-do assemble } */ | ||
| 9838 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9839 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9840 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9841 | +/* { dg-add-options arm_neon } */ | ||
| 9842 | |||
| 9843 | #include "arm_neon.h" | ||
| 9844 | |||
| 9845 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c | ||
| 9846 | =================================================================== | ||
| 9847 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c | ||
| 9848 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c | ||
| 9849 | @@ -3,7 +3,8 @@ | ||
| 9850 | |||
| 9851 | /* { dg-do assemble } */ | ||
| 9852 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9853 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9854 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9855 | +/* { dg-add-options arm_neon } */ | ||
| 9856 | |||
| 9857 | #include "arm_neon.h" | ||
| 9858 | |||
| 9859 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c | ||
| 9860 | =================================================================== | ||
| 9861 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c | ||
| 9862 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c | ||
| 9863 | @@ -3,7 +3,8 @@ | ||
| 9864 | |||
| 9865 | /* { dg-do assemble } */ | ||
| 9866 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9867 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9868 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9869 | +/* { dg-add-options arm_neon } */ | ||
| 9870 | |||
| 9871 | #include "arm_neon.h" | ||
| 9872 | |||
| 9873 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c | ||
| 9874 | =================================================================== | ||
| 9875 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c | ||
| 9876 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c | ||
| 9877 | @@ -3,7 +3,8 @@ | ||
| 9878 | |||
| 9879 | /* { dg-do assemble } */ | ||
| 9880 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9881 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9882 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9883 | +/* { dg-add-options arm_neon } */ | ||
| 9884 | |||
| 9885 | #include "arm_neon.h" | ||
| 9886 | |||
| 9887 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c | ||
| 9888 | =================================================================== | ||
| 9889 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c | ||
| 9890 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c | ||
| 9891 | @@ -3,7 +3,8 @@ | ||
| 9892 | |||
| 9893 | /* { dg-do assemble } */ | ||
| 9894 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9895 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9896 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9897 | +/* { dg-add-options arm_neon } */ | ||
| 9898 | |||
| 9899 | #include "arm_neon.h" | ||
| 9900 | |||
| 9901 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c | ||
| 9902 | =================================================================== | ||
| 9903 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c | ||
| 9904 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c | ||
| 9905 | @@ -3,7 +3,8 @@ | ||
| 9906 | |||
| 9907 | /* { dg-do assemble } */ | ||
| 9908 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9909 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9910 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9911 | +/* { dg-add-options arm_neon } */ | ||
| 9912 | |||
| 9913 | #include "arm_neon.h" | ||
| 9914 | |||
| 9915 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c | ||
| 9916 | =================================================================== | ||
| 9917 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c | ||
| 9918 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c | ||
| 9919 | @@ -3,7 +3,8 @@ | ||
| 9920 | |||
| 9921 | /* { dg-do assemble } */ | ||
| 9922 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9923 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9924 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9925 | +/* { dg-add-options arm_neon } */ | ||
| 9926 | |||
| 9927 | #include "arm_neon.h" | ||
| 9928 | |||
| 9929 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c | ||
| 9930 | =================================================================== | ||
| 9931 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c | ||
| 9932 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c | ||
| 9933 | @@ -3,7 +3,8 @@ | ||
| 9934 | |||
| 9935 | /* { dg-do assemble } */ | ||
| 9936 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9937 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9938 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9939 | +/* { dg-add-options arm_neon } */ | ||
| 9940 | |||
| 9941 | #include "arm_neon.h" | ||
| 9942 | |||
| 9943 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c | ||
| 9944 | =================================================================== | ||
| 9945 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c | ||
| 9946 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c | ||
| 9947 | @@ -3,7 +3,8 @@ | ||
| 9948 | |||
| 9949 | /* { dg-do assemble } */ | ||
| 9950 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9951 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9952 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9953 | +/* { dg-add-options arm_neon } */ | ||
| 9954 | |||
| 9955 | #include "arm_neon.h" | ||
| 9956 | |||
| 9957 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c | ||
| 9958 | =================================================================== | ||
| 9959 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c | ||
| 9960 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c | ||
| 9961 | @@ -3,7 +3,8 @@ | ||
| 9962 | |||
| 9963 | /* { dg-do assemble } */ | ||
| 9964 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9965 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9966 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9967 | +/* { dg-add-options arm_neon } */ | ||
| 9968 | |||
| 9969 | #include "arm_neon.h" | ||
| 9970 | |||
| 9971 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c | ||
| 9972 | =================================================================== | ||
| 9973 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c | ||
| 9974 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c | ||
| 9975 | @@ -3,7 +3,8 @@ | ||
| 9976 | |||
| 9977 | /* { dg-do assemble } */ | ||
| 9978 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9979 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9980 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9981 | +/* { dg-add-options arm_neon } */ | ||
| 9982 | |||
| 9983 | #include "arm_neon.h" | ||
| 9984 | |||
| 9985 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c | ||
| 9986 | =================================================================== | ||
| 9987 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c | ||
| 9988 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c | ||
| 9989 | @@ -3,7 +3,8 @@ | ||
| 9990 | |||
| 9991 | /* { dg-do assemble } */ | ||
| 9992 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 9993 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 9994 | +/* { dg-options "-save-temps -O0" } */ | ||
| 9995 | +/* { dg-add-options arm_neon } */ | ||
| 9996 | |||
| 9997 | #include "arm_neon.h" | ||
| 9998 | |||
| 9999 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c | ||
| 10000 | =================================================================== | ||
| 10001 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c | ||
| 10002 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c | ||
| 10003 | @@ -3,7 +3,8 @@ | ||
| 10004 | |||
| 10005 | /* { dg-do assemble } */ | ||
| 10006 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10007 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10008 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10009 | +/* { dg-add-options arm_neon } */ | ||
| 10010 | |||
| 10011 | #include "arm_neon.h" | ||
| 10012 | |||
| 10013 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c | ||
| 10014 | =================================================================== | ||
| 10015 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c | ||
| 10016 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c | ||
| 10017 | @@ -3,7 +3,8 @@ | ||
| 10018 | |||
| 10019 | /* { dg-do assemble } */ | ||
| 10020 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10021 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10022 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10023 | +/* { dg-add-options arm_neon } */ | ||
| 10024 | |||
| 10025 | #include "arm_neon.h" | ||
| 10026 | |||
| 10027 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c | ||
| 10028 | =================================================================== | ||
| 10029 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c | ||
| 10030 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c | ||
| 10031 | @@ -3,7 +3,8 @@ | ||
| 10032 | |||
| 10033 | /* { dg-do assemble } */ | ||
| 10034 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10035 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10036 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10037 | +/* { dg-add-options arm_neon } */ | ||
| 10038 | |||
| 10039 | #include "arm_neon.h" | ||
| 10040 | |||
| 10041 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c | ||
| 10042 | =================================================================== | ||
| 10043 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c | ||
| 10044 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c | ||
| 10045 | @@ -3,7 +3,8 @@ | ||
| 10046 | |||
| 10047 | /* { dg-do assemble } */ | ||
| 10048 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10049 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10050 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10051 | +/* { dg-add-options arm_neon } */ | ||
| 10052 | |||
| 10053 | #include "arm_neon.h" | ||
| 10054 | |||
| 10055 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c | ||
| 10056 | =================================================================== | ||
| 10057 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c | ||
| 10058 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c | ||
| 10059 | @@ -3,7 +3,8 @@ | ||
| 10060 | |||
| 10061 | /* { dg-do assemble } */ | ||
| 10062 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10063 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10064 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10065 | +/* { dg-add-options arm_neon } */ | ||
| 10066 | |||
| 10067 | #include "arm_neon.h" | ||
| 10068 | |||
| 10069 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c | ||
| 10070 | =================================================================== | ||
| 10071 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c | ||
| 10072 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c | ||
| 10073 | @@ -3,7 +3,8 @@ | ||
| 10074 | |||
| 10075 | /* { dg-do assemble } */ | ||
| 10076 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10077 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10078 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10079 | +/* { dg-add-options arm_neon } */ | ||
| 10080 | |||
| 10081 | #include "arm_neon.h" | ||
| 10082 | |||
| 10083 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c | ||
| 10084 | =================================================================== | ||
| 10085 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c | ||
| 10086 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c | ||
| 10087 | @@ -3,7 +3,8 @@ | ||
| 10088 | |||
| 10089 | /* { dg-do assemble } */ | ||
| 10090 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10091 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10092 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10093 | +/* { dg-add-options arm_neon } */ | ||
| 10094 | |||
| 10095 | #include "arm_neon.h" | ||
| 10096 | |||
| 10097 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c | ||
| 10098 | =================================================================== | ||
| 10099 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c | ||
| 10100 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c | ||
| 10101 | @@ -3,7 +3,8 @@ | ||
| 10102 | |||
| 10103 | /* { dg-do assemble } */ | ||
| 10104 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10105 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10106 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10107 | +/* { dg-add-options arm_neon } */ | ||
| 10108 | |||
| 10109 | #include "arm_neon.h" | ||
| 10110 | |||
| 10111 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c | ||
| 10112 | =================================================================== | ||
| 10113 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c | ||
| 10114 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c | ||
| 10115 | @@ -3,7 +3,8 @@ | ||
| 10116 | |||
| 10117 | /* { dg-do assemble } */ | ||
| 10118 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10119 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10120 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10121 | +/* { dg-add-options arm_neon } */ | ||
| 10122 | |||
| 10123 | #include "arm_neon.h" | ||
| 10124 | |||
| 10125 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c | ||
| 10126 | =================================================================== | ||
| 10127 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c | ||
| 10128 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c | ||
| 10129 | @@ -3,7 +3,8 @@ | ||
| 10130 | |||
| 10131 | /* { dg-do assemble } */ | ||
| 10132 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10133 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10134 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10135 | +/* { dg-add-options arm_neon } */ | ||
| 10136 | |||
| 10137 | #include "arm_neon.h" | ||
| 10138 | |||
| 10139 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4f32.c | ||
| 10140 | =================================================================== | ||
| 10141 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4f32.c | ||
| 10142 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4f32.c | ||
| 10143 | @@ -3,7 +3,8 @@ | ||
| 10144 | |||
| 10145 | /* { dg-do assemble } */ | ||
| 10146 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10147 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10148 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10149 | +/* { dg-add-options arm_neon } */ | ||
| 10150 | |||
| 10151 | #include "arm_neon.h" | ||
| 10152 | |||
| 10153 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4p16.c | ||
| 10154 | =================================================================== | ||
| 10155 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4p16.c | ||
| 10156 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4p16.c | ||
| 10157 | @@ -3,7 +3,8 @@ | ||
| 10158 | |||
| 10159 | /* { dg-do assemble } */ | ||
| 10160 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10161 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10162 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10163 | +/* { dg-add-options arm_neon } */ | ||
| 10164 | |||
| 10165 | #include "arm_neon.h" | ||
| 10166 | |||
| 10167 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4p8.c | ||
| 10168 | =================================================================== | ||
| 10169 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4p8.c | ||
| 10170 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4p8.c | ||
| 10171 | @@ -3,7 +3,8 @@ | ||
| 10172 | |||
| 10173 | /* { dg-do assemble } */ | ||
| 10174 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10175 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10176 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10177 | +/* { dg-add-options arm_neon } */ | ||
| 10178 | |||
| 10179 | #include "arm_neon.h" | ||
| 10180 | |||
| 10181 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s16.c | ||
| 10182 | =================================================================== | ||
| 10183 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s16.c | ||
| 10184 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s16.c | ||
| 10185 | @@ -3,7 +3,8 @@ | ||
| 10186 | |||
| 10187 | /* { dg-do assemble } */ | ||
| 10188 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10189 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10190 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10191 | +/* { dg-add-options arm_neon } */ | ||
| 10192 | |||
| 10193 | #include "arm_neon.h" | ||
| 10194 | |||
| 10195 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s32.c | ||
| 10196 | =================================================================== | ||
| 10197 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s32.c | ||
| 10198 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s32.c | ||
| 10199 | @@ -3,7 +3,8 @@ | ||
| 10200 | |||
| 10201 | /* { dg-do assemble } */ | ||
| 10202 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10203 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10204 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10205 | +/* { dg-add-options arm_neon } */ | ||
| 10206 | |||
| 10207 | #include "arm_neon.h" | ||
| 10208 | |||
| 10209 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s64.c | ||
| 10210 | =================================================================== | ||
| 10211 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s64.c | ||
| 10212 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s64.c | ||
| 10213 | @@ -3,7 +3,8 @@ | ||
| 10214 | |||
| 10215 | /* { dg-do assemble } */ | ||
| 10216 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10217 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10218 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10219 | +/* { dg-add-options arm_neon } */ | ||
| 10220 | |||
| 10221 | #include "arm_neon.h" | ||
| 10222 | |||
| 10223 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s8.c | ||
| 10224 | =================================================================== | ||
| 10225 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s8.c | ||
| 10226 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4s8.c | ||
| 10227 | @@ -3,7 +3,8 @@ | ||
| 10228 | |||
| 10229 | /* { dg-do assemble } */ | ||
| 10230 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10231 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10232 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10233 | +/* { dg-add-options arm_neon } */ | ||
| 10234 | |||
| 10235 | #include "arm_neon.h" | ||
| 10236 | |||
| 10237 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u16.c | ||
| 10238 | =================================================================== | ||
| 10239 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u16.c | ||
| 10240 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u16.c | ||
| 10241 | @@ -3,7 +3,8 @@ | ||
| 10242 | |||
| 10243 | /* { dg-do assemble } */ | ||
| 10244 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10245 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10246 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10247 | +/* { dg-add-options arm_neon } */ | ||
| 10248 | |||
| 10249 | #include "arm_neon.h" | ||
| 10250 | |||
| 10251 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u32.c | ||
| 10252 | =================================================================== | ||
| 10253 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u32.c | ||
| 10254 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u32.c | ||
| 10255 | @@ -3,7 +3,8 @@ | ||
| 10256 | |||
| 10257 | /* { dg-do assemble } */ | ||
| 10258 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10259 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10260 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10261 | +/* { dg-add-options arm_neon } */ | ||
| 10262 | |||
| 10263 | #include "arm_neon.h" | ||
| 10264 | |||
| 10265 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u64.c | ||
| 10266 | =================================================================== | ||
| 10267 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u64.c | ||
| 10268 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u64.c | ||
| 10269 | @@ -3,7 +3,8 @@ | ||
| 10270 | |||
| 10271 | /* { dg-do assemble } */ | ||
| 10272 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10273 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10274 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10275 | +/* { dg-add-options arm_neon } */ | ||
| 10276 | |||
| 10277 | #include "arm_neon.h" | ||
| 10278 | |||
| 10279 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u8.c | ||
| 10280 | =================================================================== | ||
| 10281 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u8.c | ||
| 10282 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vld4u8.c | ||
| 10283 | @@ -3,7 +3,8 @@ | ||
| 10284 | |||
| 10285 | /* { dg-do assemble } */ | ||
| 10286 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10287 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10288 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10289 | +/* { dg-add-options arm_neon } */ | ||
| 10290 | |||
| 10291 | #include "arm_neon.h" | ||
| 10292 | |||
| 10293 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c | ||
| 10294 | =================================================================== | ||
| 10295 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c | ||
| 10296 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c | ||
| 10297 | @@ -3,7 +3,8 @@ | ||
| 10298 | |||
| 10299 | /* { dg-do assemble } */ | ||
| 10300 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10301 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10302 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10303 | +/* { dg-add-options arm_neon } */ | ||
| 10304 | |||
| 10305 | #include "arm_neon.h" | ||
| 10306 | |||
| 10307 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c | ||
| 10308 | =================================================================== | ||
| 10309 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c | ||
| 10310 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c | ||
| 10311 | @@ -3,7 +3,8 @@ | ||
| 10312 | |||
| 10313 | /* { dg-do assemble } */ | ||
| 10314 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10315 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10316 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10317 | +/* { dg-add-options arm_neon } */ | ||
| 10318 | |||
| 10319 | #include "arm_neon.h" | ||
| 10320 | |||
| 10321 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c | ||
| 10322 | =================================================================== | ||
| 10323 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c | ||
| 10324 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c | ||
| 10325 | @@ -3,7 +3,8 @@ | ||
| 10326 | |||
| 10327 | /* { dg-do assemble } */ | ||
| 10328 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10329 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10330 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10331 | +/* { dg-add-options arm_neon } */ | ||
| 10332 | |||
| 10333 | #include "arm_neon.h" | ||
| 10334 | |||
| 10335 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c | ||
| 10336 | =================================================================== | ||
| 10337 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c | ||
| 10338 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c | ||
| 10339 | @@ -3,7 +3,8 @@ | ||
| 10340 | |||
| 10341 | /* { dg-do assemble } */ | ||
| 10342 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10343 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10344 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10345 | +/* { dg-add-options arm_neon } */ | ||
| 10346 | |||
| 10347 | #include "arm_neon.h" | ||
| 10348 | |||
| 10349 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c | ||
| 10350 | =================================================================== | ||
| 10351 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c | ||
| 10352 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c | ||
| 10353 | @@ -3,7 +3,8 @@ | ||
| 10354 | |||
| 10355 | /* { dg-do assemble } */ | ||
| 10356 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10357 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10358 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10359 | +/* { dg-add-options arm_neon } */ | ||
| 10360 | |||
| 10361 | #include "arm_neon.h" | ||
| 10362 | |||
| 10363 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c | ||
| 10364 | =================================================================== | ||
| 10365 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c | ||
| 10366 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c | ||
| 10367 | @@ -3,7 +3,8 @@ | ||
| 10368 | |||
| 10369 | /* { dg-do assemble } */ | ||
| 10370 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10371 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10372 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10373 | +/* { dg-add-options arm_neon } */ | ||
| 10374 | |||
| 10375 | #include "arm_neon.h" | ||
| 10376 | |||
| 10377 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c | ||
| 10378 | =================================================================== | ||
| 10379 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c | ||
| 10380 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c | ||
| 10381 | @@ -3,7 +3,8 @@ | ||
| 10382 | |||
| 10383 | /* { dg-do assemble } */ | ||
| 10384 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10385 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10386 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10387 | +/* { dg-add-options arm_neon } */ | ||
| 10388 | |||
| 10389 | #include "arm_neon.h" | ||
| 10390 | |||
| 10391 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c | ||
| 10392 | =================================================================== | ||
| 10393 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c | ||
| 10394 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c | ||
| 10395 | @@ -3,7 +3,8 @@ | ||
| 10396 | |||
| 10397 | /* { dg-do assemble } */ | ||
| 10398 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10399 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10400 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10401 | +/* { dg-add-options arm_neon } */ | ||
| 10402 | |||
| 10403 | #include "arm_neon.h" | ||
| 10404 | |||
| 10405 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c | ||
| 10406 | =================================================================== | ||
| 10407 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c | ||
| 10408 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c | ||
| 10409 | @@ -3,7 +3,8 @@ | ||
| 10410 | |||
| 10411 | /* { dg-do assemble } */ | ||
| 10412 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10413 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10414 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10415 | +/* { dg-add-options arm_neon } */ | ||
| 10416 | |||
| 10417 | #include "arm_neon.h" | ||
| 10418 | |||
| 10419 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c | ||
| 10420 | =================================================================== | ||
| 10421 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c | ||
| 10422 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c | ||
| 10423 | @@ -3,7 +3,8 @@ | ||
| 10424 | |||
| 10425 | /* { dg-do assemble } */ | ||
| 10426 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10427 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10428 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10429 | +/* { dg-add-options arm_neon } */ | ||
| 10430 | |||
| 10431 | #include "arm_neon.h" | ||
| 10432 | |||
| 10433 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c | ||
| 10434 | =================================================================== | ||
| 10435 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c | ||
| 10436 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c | ||
| 10437 | @@ -3,7 +3,8 @@ | ||
| 10438 | |||
| 10439 | /* { dg-do assemble } */ | ||
| 10440 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10441 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10442 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10443 | +/* { dg-add-options arm_neon } */ | ||
| 10444 | |||
| 10445 | #include "arm_neon.h" | ||
| 10446 | |||
| 10447 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c | ||
| 10448 | =================================================================== | ||
| 10449 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c | ||
| 10450 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c | ||
| 10451 | @@ -3,7 +3,8 @@ | ||
| 10452 | |||
| 10453 | /* { dg-do assemble } */ | ||
| 10454 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10455 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10456 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10457 | +/* { dg-add-options arm_neon } */ | ||
| 10458 | |||
| 10459 | #include "arm_neon.h" | ||
| 10460 | |||
| 10461 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c | ||
| 10462 | =================================================================== | ||
| 10463 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c | ||
| 10464 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c | ||
| 10465 | @@ -3,7 +3,8 @@ | ||
| 10466 | |||
| 10467 | /* { dg-do assemble } */ | ||
| 10468 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10469 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10470 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10471 | +/* { dg-add-options arm_neon } */ | ||
| 10472 | |||
| 10473 | #include "arm_neon.h" | ||
| 10474 | |||
| 10475 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c | ||
| 10476 | =================================================================== | ||
| 10477 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c | ||
| 10478 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c | ||
| 10479 | @@ -3,7 +3,8 @@ | ||
| 10480 | |||
| 10481 | /* { dg-do assemble } */ | ||
| 10482 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10483 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10484 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10485 | +/* { dg-add-options arm_neon } */ | ||
| 10486 | |||
| 10487 | #include "arm_neon.h" | ||
| 10488 | |||
| 10489 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQf32.c | ||
| 10490 | =================================================================== | ||
| 10491 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQf32.c | ||
| 10492 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQf32.c | ||
| 10493 | @@ -3,7 +3,8 @@ | ||
| 10494 | |||
| 10495 | /* { dg-do assemble } */ | ||
| 10496 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10497 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10498 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10499 | +/* { dg-add-options arm_neon } */ | ||
| 10500 | |||
| 10501 | #include "arm_neon.h" | ||
| 10502 | |||
| 10503 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQs16.c | ||
| 10504 | =================================================================== | ||
| 10505 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQs16.c | ||
| 10506 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQs16.c | ||
| 10507 | @@ -3,7 +3,8 @@ | ||
| 10508 | |||
| 10509 | /* { dg-do assemble } */ | ||
| 10510 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10511 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10512 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10513 | +/* { dg-add-options arm_neon } */ | ||
| 10514 | |||
| 10515 | #include "arm_neon.h" | ||
| 10516 | |||
| 10517 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQs32.c | ||
| 10518 | =================================================================== | ||
| 10519 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQs32.c | ||
| 10520 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQs32.c | ||
| 10521 | @@ -3,7 +3,8 @@ | ||
| 10522 | |||
| 10523 | /* { dg-do assemble } */ | ||
| 10524 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10525 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10526 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10527 | +/* { dg-add-options arm_neon } */ | ||
| 10528 | |||
| 10529 | #include "arm_neon.h" | ||
| 10530 | |||
| 10531 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQs8.c | ||
| 10532 | =================================================================== | ||
| 10533 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQs8.c | ||
| 10534 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQs8.c | ||
| 10535 | @@ -3,7 +3,8 @@ | ||
| 10536 | |||
| 10537 | /* { dg-do assemble } */ | ||
| 10538 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10539 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10540 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10541 | +/* { dg-add-options arm_neon } */ | ||
| 10542 | |||
| 10543 | #include "arm_neon.h" | ||
| 10544 | |||
| 10545 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQu16.c | ||
| 10546 | =================================================================== | ||
| 10547 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQu16.c | ||
| 10548 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQu16.c | ||
| 10549 | @@ -3,7 +3,8 @@ | ||
| 10550 | |||
| 10551 | /* { dg-do assemble } */ | ||
| 10552 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10553 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10554 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10555 | +/* { dg-add-options arm_neon } */ | ||
| 10556 | |||
| 10557 | #include "arm_neon.h" | ||
| 10558 | |||
| 10559 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQu32.c | ||
| 10560 | =================================================================== | ||
| 10561 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQu32.c | ||
| 10562 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQu32.c | ||
| 10563 | @@ -3,7 +3,8 @@ | ||
| 10564 | |||
| 10565 | /* { dg-do assemble } */ | ||
| 10566 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10567 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10568 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10569 | +/* { dg-add-options arm_neon } */ | ||
| 10570 | |||
| 10571 | #include "arm_neon.h" | ||
| 10572 | |||
| 10573 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQu8.c | ||
| 10574 | =================================================================== | ||
| 10575 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminQu8.c | ||
| 10576 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminQu8.c | ||
| 10577 | @@ -3,7 +3,8 @@ | ||
| 10578 | |||
| 10579 | /* { dg-do assemble } */ | ||
| 10580 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10581 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10582 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10583 | +/* { dg-add-options arm_neon } */ | ||
| 10584 | |||
| 10585 | #include "arm_neon.h" | ||
| 10586 | |||
| 10587 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminf32.c | ||
| 10588 | =================================================================== | ||
| 10589 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminf32.c | ||
| 10590 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminf32.c | ||
| 10591 | @@ -3,7 +3,8 @@ | ||
| 10592 | |||
| 10593 | /* { dg-do assemble } */ | ||
| 10594 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10595 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10596 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10597 | +/* { dg-add-options arm_neon } */ | ||
| 10598 | |||
| 10599 | #include "arm_neon.h" | ||
| 10600 | |||
| 10601 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmins16.c | ||
| 10602 | =================================================================== | ||
| 10603 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmins16.c | ||
| 10604 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmins16.c | ||
| 10605 | @@ -3,7 +3,8 @@ | ||
| 10606 | |||
| 10607 | /* { dg-do assemble } */ | ||
| 10608 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10609 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10610 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10611 | +/* { dg-add-options arm_neon } */ | ||
| 10612 | |||
| 10613 | #include "arm_neon.h" | ||
| 10614 | |||
| 10615 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmins32.c | ||
| 10616 | =================================================================== | ||
| 10617 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmins32.c | ||
| 10618 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmins32.c | ||
| 10619 | @@ -3,7 +3,8 @@ | ||
| 10620 | |||
| 10621 | /* { dg-do assemble } */ | ||
| 10622 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10623 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10624 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10625 | +/* { dg-add-options arm_neon } */ | ||
| 10626 | |||
| 10627 | #include "arm_neon.h" | ||
| 10628 | |||
| 10629 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmins8.c | ||
| 10630 | =================================================================== | ||
| 10631 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmins8.c | ||
| 10632 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmins8.c | ||
| 10633 | @@ -3,7 +3,8 @@ | ||
| 10634 | |||
| 10635 | /* { dg-do assemble } */ | ||
| 10636 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10637 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10638 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10639 | +/* { dg-add-options arm_neon } */ | ||
| 10640 | |||
| 10641 | #include "arm_neon.h" | ||
| 10642 | |||
| 10643 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminu16.c | ||
| 10644 | =================================================================== | ||
| 10645 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminu16.c | ||
| 10646 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminu16.c | ||
| 10647 | @@ -3,7 +3,8 @@ | ||
| 10648 | |||
| 10649 | /* { dg-do assemble } */ | ||
| 10650 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10651 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10652 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10653 | +/* { dg-add-options arm_neon } */ | ||
| 10654 | |||
| 10655 | #include "arm_neon.h" | ||
| 10656 | |||
| 10657 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminu32.c | ||
| 10658 | =================================================================== | ||
| 10659 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminu32.c | ||
| 10660 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminu32.c | ||
| 10661 | @@ -3,7 +3,8 @@ | ||
| 10662 | |||
| 10663 | /* { dg-do assemble } */ | ||
| 10664 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10665 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10666 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10667 | +/* { dg-add-options arm_neon } */ | ||
| 10668 | |||
| 10669 | #include "arm_neon.h" | ||
| 10670 | |||
| 10671 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminu8.c | ||
| 10672 | =================================================================== | ||
| 10673 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vminu8.c | ||
| 10674 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vminu8.c | ||
| 10675 | @@ -3,7 +3,8 @@ | ||
| 10676 | |||
| 10677 | /* { dg-do assemble } */ | ||
| 10678 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10679 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10680 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10681 | +/* { dg-add-options arm_neon } */ | ||
| 10682 | |||
| 10683 | #include "arm_neon.h" | ||
| 10684 | |||
| 10685 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c | ||
| 10686 | =================================================================== | ||
| 10687 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c | ||
| 10688 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c | ||
| 10689 | @@ -3,7 +3,8 @@ | ||
| 10690 | |||
| 10691 | /* { dg-do assemble } */ | ||
| 10692 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10693 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10694 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10695 | +/* { dg-add-options arm_neon } */ | ||
| 10696 | |||
| 10697 | #include "arm_neon.h" | ||
| 10698 | |||
| 10699 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c | ||
| 10700 | =================================================================== | ||
| 10701 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c | ||
| 10702 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c | ||
| 10703 | @@ -3,7 +3,8 @@ | ||
| 10704 | |||
| 10705 | /* { dg-do assemble } */ | ||
| 10706 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10707 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10708 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10709 | +/* { dg-add-options arm_neon } */ | ||
| 10710 | |||
| 10711 | #include "arm_neon.h" | ||
| 10712 | |||
| 10713 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c | ||
| 10714 | =================================================================== | ||
| 10715 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c | ||
| 10716 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c | ||
| 10717 | @@ -3,7 +3,8 @@ | ||
| 10718 | |||
| 10719 | /* { dg-do assemble } */ | ||
| 10720 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10721 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10722 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10723 | +/* { dg-add-options arm_neon } */ | ||
| 10724 | |||
| 10725 | #include "arm_neon.h" | ||
| 10726 | |||
| 10727 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c | ||
| 10728 | =================================================================== | ||
| 10729 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c | ||
| 10730 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c | ||
| 10731 | @@ -3,7 +3,8 @@ | ||
| 10732 | |||
| 10733 | /* { dg-do assemble } */ | ||
| 10734 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10735 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10736 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10737 | +/* { dg-add-options arm_neon } */ | ||
| 10738 | |||
| 10739 | #include "arm_neon.h" | ||
| 10740 | |||
| 10741 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c | ||
| 10742 | =================================================================== | ||
| 10743 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c | ||
| 10744 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c | ||
| 10745 | @@ -3,7 +3,8 @@ | ||
| 10746 | |||
| 10747 | /* { dg-do assemble } */ | ||
| 10748 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10749 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10750 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10751 | +/* { dg-add-options arm_neon } */ | ||
| 10752 | |||
| 10753 | #include "arm_neon.h" | ||
| 10754 | |||
| 10755 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c | ||
| 10756 | =================================================================== | ||
| 10757 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c | ||
| 10758 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c | ||
| 10759 | @@ -3,7 +3,8 @@ | ||
| 10760 | |||
| 10761 | /* { dg-do assemble } */ | ||
| 10762 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10763 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10764 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10765 | +/* { dg-add-options arm_neon } */ | ||
| 10766 | |||
| 10767 | #include "arm_neon.h" | ||
| 10768 | |||
| 10769 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c | ||
| 10770 | =================================================================== | ||
| 10771 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c | ||
| 10772 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c | ||
| 10773 | @@ -3,7 +3,8 @@ | ||
| 10774 | |||
| 10775 | /* { dg-do assemble } */ | ||
| 10776 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10777 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10778 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10779 | +/* { dg-add-options arm_neon } */ | ||
| 10780 | |||
| 10781 | #include "arm_neon.h" | ||
| 10782 | |||
| 10783 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c | ||
| 10784 | =================================================================== | ||
| 10785 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c | ||
| 10786 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c | ||
| 10787 | @@ -3,7 +3,8 @@ | ||
| 10788 | |||
| 10789 | /* { dg-do assemble } */ | ||
| 10790 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10791 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10792 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10793 | +/* { dg-add-options arm_neon } */ | ||
| 10794 | |||
| 10795 | #include "arm_neon.h" | ||
| 10796 | |||
| 10797 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c | ||
| 10798 | =================================================================== | ||
| 10799 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c | ||
| 10800 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c | ||
| 10801 | @@ -3,7 +3,8 @@ | ||
| 10802 | |||
| 10803 | /* { dg-do assemble } */ | ||
| 10804 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10805 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10806 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10807 | +/* { dg-add-options arm_neon } */ | ||
| 10808 | |||
| 10809 | #include "arm_neon.h" | ||
| 10810 | |||
| 10811 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c | ||
| 10812 | =================================================================== | ||
| 10813 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c | ||
| 10814 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c | ||
| 10815 | @@ -3,7 +3,8 @@ | ||
| 10816 | |||
| 10817 | /* { dg-do assemble } */ | ||
| 10818 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10819 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10820 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10821 | +/* { dg-add-options arm_neon } */ | ||
| 10822 | |||
| 10823 | #include "arm_neon.h" | ||
| 10824 | |||
| 10825 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c | ||
| 10826 | =================================================================== | ||
| 10827 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c | ||
| 10828 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c | ||
| 10829 | @@ -3,7 +3,8 @@ | ||
| 10830 | |||
| 10831 | /* { dg-do assemble } */ | ||
| 10832 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10833 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10834 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10835 | +/* { dg-add-options arm_neon } */ | ||
| 10836 | |||
| 10837 | #include "arm_neon.h" | ||
| 10838 | |||
| 10839 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c | ||
| 10840 | =================================================================== | ||
| 10841 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c | ||
| 10842 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c | ||
| 10843 | @@ -3,7 +3,8 @@ | ||
| 10844 | |||
| 10845 | /* { dg-do assemble } */ | ||
| 10846 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10847 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10848 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10849 | +/* { dg-add-options arm_neon } */ | ||
| 10850 | |||
| 10851 | #include "arm_neon.h" | ||
| 10852 | |||
| 10853 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c | ||
| 10854 | =================================================================== | ||
| 10855 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c | ||
| 10856 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c | ||
| 10857 | @@ -3,7 +3,8 @@ | ||
| 10858 | |||
| 10859 | /* { dg-do assemble } */ | ||
| 10860 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10861 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10862 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10863 | +/* { dg-add-options arm_neon } */ | ||
| 10864 | |||
| 10865 | #include "arm_neon.h" | ||
| 10866 | |||
| 10867 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c | ||
| 10868 | =================================================================== | ||
| 10869 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c | ||
| 10870 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c | ||
| 10871 | @@ -3,7 +3,8 @@ | ||
| 10872 | |||
| 10873 | /* { dg-do assemble } */ | ||
| 10874 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10875 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10876 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10877 | +/* { dg-add-options arm_neon } */ | ||
| 10878 | |||
| 10879 | #include "arm_neon.h" | ||
| 10880 | |||
| 10881 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c | ||
| 10882 | =================================================================== | ||
| 10883 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c | ||
| 10884 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c | ||
| 10885 | @@ -3,7 +3,8 @@ | ||
| 10886 | |||
| 10887 | /* { dg-do assemble } */ | ||
| 10888 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10889 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10890 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10891 | +/* { dg-add-options arm_neon } */ | ||
| 10892 | |||
| 10893 | #include "arm_neon.h" | ||
| 10894 | |||
| 10895 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c | ||
| 10896 | =================================================================== | ||
| 10897 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c | ||
| 10898 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c | ||
| 10899 | @@ -3,7 +3,8 @@ | ||
| 10900 | |||
| 10901 | /* { dg-do assemble } */ | ||
| 10902 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10903 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10904 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10905 | +/* { dg-add-options arm_neon } */ | ||
| 10906 | |||
| 10907 | #include "arm_neon.h" | ||
| 10908 | |||
| 10909 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c | ||
| 10910 | =================================================================== | ||
| 10911 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c | ||
| 10912 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c | ||
| 10913 | @@ -3,7 +3,8 @@ | ||
| 10914 | |||
| 10915 | /* { dg-do assemble } */ | ||
| 10916 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10917 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10918 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10919 | +/* { dg-add-options arm_neon } */ | ||
| 10920 | |||
| 10921 | #include "arm_neon.h" | ||
| 10922 | |||
| 10923 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c | ||
| 10924 | =================================================================== | ||
| 10925 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c | ||
| 10926 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c | ||
| 10927 | @@ -3,7 +3,8 @@ | ||
| 10928 | |||
| 10929 | /* { dg-do assemble } */ | ||
| 10930 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10931 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10932 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10933 | +/* { dg-add-options arm_neon } */ | ||
| 10934 | |||
| 10935 | #include "arm_neon.h" | ||
| 10936 | |||
| 10937 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c | ||
| 10938 | =================================================================== | ||
| 10939 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c | ||
| 10940 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c | ||
| 10941 | @@ -3,7 +3,8 @@ | ||
| 10942 | |||
| 10943 | /* { dg-do assemble } */ | ||
| 10944 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10945 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10946 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10947 | +/* { dg-add-options arm_neon } */ | ||
| 10948 | |||
| 10949 | #include "arm_neon.h" | ||
| 10950 | |||
| 10951 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c | ||
| 10952 | =================================================================== | ||
| 10953 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c | ||
| 10954 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c | ||
| 10955 | @@ -3,7 +3,8 @@ | ||
| 10956 | |||
| 10957 | /* { dg-do assemble } */ | ||
| 10958 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10959 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10960 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10961 | +/* { dg-add-options arm_neon } */ | ||
| 10962 | |||
| 10963 | #include "arm_neon.h" | ||
| 10964 | |||
| 10965 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c | ||
| 10966 | =================================================================== | ||
| 10967 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c | ||
| 10968 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c | ||
| 10969 | @@ -3,7 +3,8 @@ | ||
| 10970 | |||
| 10971 | /* { dg-do assemble } */ | ||
| 10972 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10973 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10974 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10975 | +/* { dg-add-options arm_neon } */ | ||
| 10976 | |||
| 10977 | #include "arm_neon.h" | ||
| 10978 | |||
| 10979 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c | ||
| 10980 | =================================================================== | ||
| 10981 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c | ||
| 10982 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c | ||
| 10983 | @@ -3,7 +3,8 @@ | ||
| 10984 | |||
| 10985 | /* { dg-do assemble } */ | ||
| 10986 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 10987 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 10988 | +/* { dg-options "-save-temps -O0" } */ | ||
| 10989 | +/* { dg-add-options arm_neon } */ | ||
| 10990 | |||
| 10991 | #include "arm_neon.h" | ||
| 10992 | |||
| 10993 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c | ||
| 10994 | =================================================================== | ||
| 10995 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c | ||
| 10996 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c | ||
| 10997 | @@ -3,7 +3,8 @@ | ||
| 10998 | |||
| 10999 | /* { dg-do assemble } */ | ||
| 11000 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11001 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11002 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11003 | +/* { dg-add-options arm_neon } */ | ||
| 11004 | |||
| 11005 | #include "arm_neon.h" | ||
| 11006 | |||
| 11007 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c | ||
| 11008 | =================================================================== | ||
| 11009 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c | ||
| 11010 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c | ||
| 11011 | @@ -3,7 +3,8 @@ | ||
| 11012 | |||
| 11013 | /* { dg-do assemble } */ | ||
| 11014 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11015 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11016 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11017 | +/* { dg-add-options arm_neon } */ | ||
| 11018 | |||
| 11019 | #include "arm_neon.h" | ||
| 11020 | |||
| 11021 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c | ||
| 11022 | =================================================================== | ||
| 11023 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c | ||
| 11024 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c | ||
| 11025 | @@ -3,7 +3,8 @@ | ||
| 11026 | |||
| 11027 | /* { dg-do assemble } */ | ||
| 11028 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11029 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11030 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11031 | +/* { dg-add-options arm_neon } */ | ||
| 11032 | |||
| 11033 | #include "arm_neon.h" | ||
| 11034 | |||
| 11035 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c | ||
| 11036 | =================================================================== | ||
| 11037 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c | ||
| 11038 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c | ||
| 11039 | @@ -3,7 +3,8 @@ | ||
| 11040 | |||
| 11041 | /* { dg-do assemble } */ | ||
| 11042 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11043 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11044 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11045 | +/* { dg-add-options arm_neon } */ | ||
| 11046 | |||
| 11047 | #include "arm_neon.h" | ||
| 11048 | |||
| 11049 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c | ||
| 11050 | =================================================================== | ||
| 11051 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c | ||
| 11052 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c | ||
| 11053 | @@ -3,7 +3,8 @@ | ||
| 11054 | |||
| 11055 | /* { dg-do assemble } */ | ||
| 11056 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11057 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11058 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11059 | +/* { dg-add-options arm_neon } */ | ||
| 11060 | |||
| 11061 | #include "arm_neon.h" | ||
| 11062 | |||
| 11063 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c | ||
| 11064 | =================================================================== | ||
| 11065 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c | ||
| 11066 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c | ||
| 11067 | @@ -3,7 +3,8 @@ | ||
| 11068 | |||
| 11069 | /* { dg-do assemble } */ | ||
| 11070 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11071 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11072 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11073 | +/* { dg-add-options arm_neon } */ | ||
| 11074 | |||
| 11075 | #include "arm_neon.h" | ||
| 11076 | |||
| 11077 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c | ||
| 11078 | =================================================================== | ||
| 11079 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c | ||
| 11080 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c | ||
| 11081 | @@ -3,7 +3,8 @@ | ||
| 11082 | |||
| 11083 | /* { dg-do assemble } */ | ||
| 11084 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11085 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11086 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11087 | +/* { dg-add-options arm_neon } */ | ||
| 11088 | |||
| 11089 | #include "arm_neon.h" | ||
| 11090 | |||
| 11091 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c | ||
| 11092 | =================================================================== | ||
| 11093 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c | ||
| 11094 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c | ||
| 11095 | @@ -3,7 +3,8 @@ | ||
| 11096 | |||
| 11097 | /* { dg-do assemble } */ | ||
| 11098 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11099 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11100 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11101 | +/* { dg-add-options arm_neon } */ | ||
| 11102 | |||
| 11103 | #include "arm_neon.h" | ||
| 11104 | |||
| 11105 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c | ||
| 11106 | =================================================================== | ||
| 11107 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c | ||
| 11108 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c | ||
| 11109 | @@ -3,7 +3,8 @@ | ||
| 11110 | |||
| 11111 | /* { dg-do assemble } */ | ||
| 11112 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11113 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11114 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11115 | +/* { dg-add-options arm_neon } */ | ||
| 11116 | |||
| 11117 | #include "arm_neon.h" | ||
| 11118 | |||
| 11119 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c | ||
| 11120 | =================================================================== | ||
| 11121 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c | ||
| 11122 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c | ||
| 11123 | @@ -3,7 +3,8 @@ | ||
| 11124 | |||
| 11125 | /* { dg-do assemble } */ | ||
| 11126 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11127 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11128 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11129 | +/* { dg-add-options arm_neon } */ | ||
| 11130 | |||
| 11131 | #include "arm_neon.h" | ||
| 11132 | |||
| 11133 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c | ||
| 11134 | =================================================================== | ||
| 11135 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c | ||
| 11136 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c | ||
| 11137 | @@ -3,7 +3,8 @@ | ||
| 11138 | |||
| 11139 | /* { dg-do assemble } */ | ||
| 11140 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11141 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11142 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11143 | +/* { dg-add-options arm_neon } */ | ||
| 11144 | |||
| 11145 | #include "arm_neon.h" | ||
| 11146 | |||
| 11147 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c | ||
| 11148 | =================================================================== | ||
| 11149 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c | ||
| 11150 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c | ||
| 11151 | @@ -3,7 +3,8 @@ | ||
| 11152 | |||
| 11153 | /* { dg-do assemble } */ | ||
| 11154 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11155 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11156 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11157 | +/* { dg-add-options arm_neon } */ | ||
| 11158 | |||
| 11159 | #include "arm_neon.h" | ||
| 11160 | |||
| 11161 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c | ||
| 11162 | =================================================================== | ||
| 11163 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c | ||
| 11164 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c | ||
| 11165 | @@ -3,7 +3,8 @@ | ||
| 11166 | |||
| 11167 | /* { dg-do assemble } */ | ||
| 11168 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11169 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11170 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11171 | +/* { dg-add-options arm_neon } */ | ||
| 11172 | |||
| 11173 | #include "arm_neon.h" | ||
| 11174 | |||
| 11175 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c | ||
| 11176 | =================================================================== | ||
| 11177 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c | ||
| 11178 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c | ||
| 11179 | @@ -3,7 +3,8 @@ | ||
| 11180 | |||
| 11181 | /* { dg-do assemble } */ | ||
| 11182 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11183 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11184 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11185 | +/* { dg-add-options arm_neon } */ | ||
| 11186 | |||
| 11187 | #include "arm_neon.h" | ||
| 11188 | |||
| 11189 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlals16.c | ||
| 11190 | =================================================================== | ||
| 11191 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlals16.c | ||
| 11192 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlals16.c | ||
| 11193 | @@ -3,7 +3,8 @@ | ||
| 11194 | |||
| 11195 | /* { dg-do assemble } */ | ||
| 11196 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11197 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11198 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11199 | +/* { dg-add-options arm_neon } */ | ||
| 11200 | |||
| 11201 | #include "arm_neon.h" | ||
| 11202 | |||
| 11203 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlals32.c | ||
| 11204 | =================================================================== | ||
| 11205 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlals32.c | ||
| 11206 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlals32.c | ||
| 11207 | @@ -3,7 +3,8 @@ | ||
| 11208 | |||
| 11209 | /* { dg-do assemble } */ | ||
| 11210 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11211 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11212 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11213 | +/* { dg-add-options arm_neon } */ | ||
| 11214 | |||
| 11215 | #include "arm_neon.h" | ||
| 11216 | |||
| 11217 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlals8.c | ||
| 11218 | =================================================================== | ||
| 11219 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlals8.c | ||
| 11220 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlals8.c | ||
| 11221 | @@ -3,7 +3,8 @@ | ||
| 11222 | |||
| 11223 | /* { dg-do assemble } */ | ||
| 11224 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11225 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11226 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11227 | +/* { dg-add-options arm_neon } */ | ||
| 11228 | |||
| 11229 | #include "arm_neon.h" | ||
| 11230 | |||
| 11231 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c | ||
| 11232 | =================================================================== | ||
| 11233 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c | ||
| 11234 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c | ||
| 11235 | @@ -3,7 +3,8 @@ | ||
| 11236 | |||
| 11237 | /* { dg-do assemble } */ | ||
| 11238 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11239 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11240 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11241 | +/* { dg-add-options arm_neon } */ | ||
| 11242 | |||
| 11243 | #include "arm_neon.h" | ||
| 11244 | |||
| 11245 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c | ||
| 11246 | =================================================================== | ||
| 11247 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c | ||
| 11248 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c | ||
| 11249 | @@ -3,7 +3,8 @@ | ||
| 11250 | |||
| 11251 | /* { dg-do assemble } */ | ||
| 11252 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11253 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11254 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11255 | +/* { dg-add-options arm_neon } */ | ||
| 11256 | |||
| 11257 | #include "arm_neon.h" | ||
| 11258 | |||
| 11259 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c | ||
| 11260 | =================================================================== | ||
| 11261 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c | ||
| 11262 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c | ||
| 11263 | @@ -3,7 +3,8 @@ | ||
| 11264 | |||
| 11265 | /* { dg-do assemble } */ | ||
| 11266 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11267 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11268 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11269 | +/* { dg-add-options arm_neon } */ | ||
| 11270 | |||
| 11271 | #include "arm_neon.h" | ||
| 11272 | |||
| 11273 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlas16.c | ||
| 11274 | =================================================================== | ||
| 11275 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlas16.c | ||
| 11276 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlas16.c | ||
| 11277 | @@ -3,7 +3,8 @@ | ||
| 11278 | |||
| 11279 | /* { dg-do assemble } */ | ||
| 11280 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11281 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11282 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11283 | +/* { dg-add-options arm_neon } */ | ||
| 11284 | |||
| 11285 | #include "arm_neon.h" | ||
| 11286 | |||
| 11287 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlas32.c | ||
| 11288 | =================================================================== | ||
| 11289 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlas32.c | ||
| 11290 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlas32.c | ||
| 11291 | @@ -3,7 +3,8 @@ | ||
| 11292 | |||
| 11293 | /* { dg-do assemble } */ | ||
| 11294 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11295 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11296 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11297 | +/* { dg-add-options arm_neon } */ | ||
| 11298 | |||
| 11299 | #include "arm_neon.h" | ||
| 11300 | |||
| 11301 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlas8.c | ||
| 11302 | =================================================================== | ||
| 11303 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlas8.c | ||
| 11304 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlas8.c | ||
| 11305 | @@ -3,7 +3,8 @@ | ||
| 11306 | |||
| 11307 | /* { dg-do assemble } */ | ||
| 11308 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11309 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11310 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11311 | +/* { dg-add-options arm_neon } */ | ||
| 11312 | |||
| 11313 | #include "arm_neon.h" | ||
| 11314 | |||
| 11315 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlau16.c | ||
| 11316 | =================================================================== | ||
| 11317 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlau16.c | ||
| 11318 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlau16.c | ||
| 11319 | @@ -3,7 +3,8 @@ | ||
| 11320 | |||
| 11321 | /* { dg-do assemble } */ | ||
| 11322 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11323 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11324 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11325 | +/* { dg-add-options arm_neon } */ | ||
| 11326 | |||
| 11327 | #include "arm_neon.h" | ||
| 11328 | |||
| 11329 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlau32.c | ||
| 11330 | =================================================================== | ||
| 11331 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlau32.c | ||
| 11332 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlau32.c | ||
| 11333 | @@ -3,7 +3,8 @@ | ||
| 11334 | |||
| 11335 | /* { dg-do assemble } */ | ||
| 11336 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11337 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11338 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11339 | +/* { dg-add-options arm_neon } */ | ||
| 11340 | |||
| 11341 | #include "arm_neon.h" | ||
| 11342 | |||
| 11343 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlau8.c | ||
| 11344 | =================================================================== | ||
| 11345 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlau8.c | ||
| 11346 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlau8.c | ||
| 11347 | @@ -3,7 +3,8 @@ | ||
| 11348 | |||
| 11349 | /* { dg-do assemble } */ | ||
| 11350 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11351 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11352 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11353 | +/* { dg-add-options arm_neon } */ | ||
| 11354 | |||
| 11355 | #include "arm_neon.h" | ||
| 11356 | |||
| 11357 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c | ||
| 11358 | =================================================================== | ||
| 11359 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c | ||
| 11360 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c | ||
| 11361 | @@ -3,7 +3,8 @@ | ||
| 11362 | |||
| 11363 | /* { dg-do assemble } */ | ||
| 11364 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11365 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11366 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11367 | +/* { dg-add-options arm_neon } */ | ||
| 11368 | |||
| 11369 | #include "arm_neon.h" | ||
| 11370 | |||
| 11371 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c | ||
| 11372 | =================================================================== | ||
| 11373 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c | ||
| 11374 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c | ||
| 11375 | @@ -3,7 +3,8 @@ | ||
| 11376 | |||
| 11377 | /* { dg-do assemble } */ | ||
| 11378 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11379 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11380 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11381 | +/* { dg-add-options arm_neon } */ | ||
| 11382 | |||
| 11383 | #include "arm_neon.h" | ||
| 11384 | |||
| 11385 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c | ||
| 11386 | =================================================================== | ||
| 11387 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c | ||
| 11388 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c | ||
| 11389 | @@ -3,7 +3,8 @@ | ||
| 11390 | |||
| 11391 | /* { dg-do assemble } */ | ||
| 11392 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11393 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11394 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11395 | +/* { dg-add-options arm_neon } */ | ||
| 11396 | |||
| 11397 | #include "arm_neon.h" | ||
| 11398 | |||
| 11399 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c | ||
| 11400 | =================================================================== | ||
| 11401 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c | ||
| 11402 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c | ||
| 11403 | @@ -3,7 +3,8 @@ | ||
| 11404 | |||
| 11405 | /* { dg-do assemble } */ | ||
| 11406 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11407 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11408 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11409 | +/* { dg-add-options arm_neon } */ | ||
| 11410 | |||
| 11411 | #include "arm_neon.h" | ||
| 11412 | |||
| 11413 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c | ||
| 11414 | =================================================================== | ||
| 11415 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c | ||
| 11416 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c | ||
| 11417 | @@ -3,7 +3,8 @@ | ||
| 11418 | |||
| 11419 | /* { dg-do assemble } */ | ||
| 11420 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11421 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11422 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11423 | +/* { dg-add-options arm_neon } */ | ||
| 11424 | |||
| 11425 | #include "arm_neon.h" | ||
| 11426 | |||
| 11427 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c | ||
| 11428 | =================================================================== | ||
| 11429 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c | ||
| 11430 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c | ||
| 11431 | @@ -3,7 +3,8 @@ | ||
| 11432 | |||
| 11433 | /* { dg-do assemble } */ | ||
| 11434 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11435 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11436 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11437 | +/* { dg-add-options arm_neon } */ | ||
| 11438 | |||
| 11439 | #include "arm_neon.h" | ||
| 11440 | |||
| 11441 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c | ||
| 11442 | =================================================================== | ||
| 11443 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c | ||
| 11444 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c | ||
| 11445 | @@ -3,7 +3,8 @@ | ||
| 11446 | |||
| 11447 | /* { dg-do assemble } */ | ||
| 11448 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11449 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11450 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11451 | +/* { dg-add-options arm_neon } */ | ||
| 11452 | |||
| 11453 | #include "arm_neon.h" | ||
| 11454 | |||
| 11455 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c | ||
| 11456 | =================================================================== | ||
| 11457 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c | ||
| 11458 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c | ||
| 11459 | @@ -3,7 +3,8 @@ | ||
| 11460 | |||
| 11461 | /* { dg-do assemble } */ | ||
| 11462 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11463 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11464 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11465 | +/* { dg-add-options arm_neon } */ | ||
| 11466 | |||
| 11467 | #include "arm_neon.h" | ||
| 11468 | |||
| 11469 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c | ||
| 11470 | =================================================================== | ||
| 11471 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c | ||
| 11472 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c | ||
| 11473 | @@ -3,7 +3,8 @@ | ||
| 11474 | |||
| 11475 | /* { dg-do assemble } */ | ||
| 11476 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11477 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11478 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11479 | +/* { dg-add-options arm_neon } */ | ||
| 11480 | |||
| 11481 | #include "arm_neon.h" | ||
| 11482 | |||
| 11483 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c | ||
| 11484 | =================================================================== | ||
| 11485 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c | ||
| 11486 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c | ||
| 11487 | @@ -3,7 +3,8 @@ | ||
| 11488 | |||
| 11489 | /* { dg-do assemble } */ | ||
| 11490 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11491 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11492 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11493 | +/* { dg-add-options arm_neon } */ | ||
| 11494 | |||
| 11495 | #include "arm_neon.h" | ||
| 11496 | |||
| 11497 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c | ||
| 11498 | =================================================================== | ||
| 11499 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c | ||
| 11500 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c | ||
| 11501 | @@ -3,7 +3,8 @@ | ||
| 11502 | |||
| 11503 | /* { dg-do assemble } */ | ||
| 11504 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11505 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11506 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11507 | +/* { dg-add-options arm_neon } */ | ||
| 11508 | |||
| 11509 | #include "arm_neon.h" | ||
| 11510 | |||
| 11511 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c | ||
| 11512 | =================================================================== | ||
| 11513 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c | ||
| 11514 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c | ||
| 11515 | @@ -3,7 +3,8 @@ | ||
| 11516 | |||
| 11517 | /* { dg-do assemble } */ | ||
| 11518 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11519 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11520 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11521 | +/* { dg-add-options arm_neon } */ | ||
| 11522 | |||
| 11523 | #include "arm_neon.h" | ||
| 11524 | |||
| 11525 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c | ||
| 11526 | =================================================================== | ||
| 11527 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c | ||
| 11528 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c | ||
| 11529 | @@ -3,7 +3,8 @@ | ||
| 11530 | |||
| 11531 | /* { dg-do assemble } */ | ||
| 11532 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11533 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11534 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11535 | +/* { dg-add-options arm_neon } */ | ||
| 11536 | |||
| 11537 | #include "arm_neon.h" | ||
| 11538 | |||
| 11539 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c | ||
| 11540 | =================================================================== | ||
| 11541 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c | ||
| 11542 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c | ||
| 11543 | @@ -3,7 +3,8 @@ | ||
| 11544 | |||
| 11545 | /* { dg-do assemble } */ | ||
| 11546 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11547 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11548 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11549 | +/* { dg-add-options arm_neon } */ | ||
| 11550 | |||
| 11551 | #include "arm_neon.h" | ||
| 11552 | |||
| 11553 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c | ||
| 11554 | =================================================================== | ||
| 11555 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c | ||
| 11556 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c | ||
| 11557 | @@ -3,7 +3,8 @@ | ||
| 11558 | |||
| 11559 | /* { dg-do assemble } */ | ||
| 11560 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11561 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11562 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11563 | +/* { dg-add-options arm_neon } */ | ||
| 11564 | |||
| 11565 | #include "arm_neon.h" | ||
| 11566 | |||
| 11567 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c | ||
| 11568 | =================================================================== | ||
| 11569 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c | ||
| 11570 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c | ||
| 11571 | @@ -3,7 +3,8 @@ | ||
| 11572 | |||
| 11573 | /* { dg-do assemble } */ | ||
| 11574 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11575 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11576 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11577 | +/* { dg-add-options arm_neon } */ | ||
| 11578 | |||
| 11579 | #include "arm_neon.h" | ||
| 11580 | |||
| 11581 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c | ||
| 11582 | =================================================================== | ||
| 11583 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c | ||
| 11584 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c | ||
| 11585 | @@ -3,7 +3,8 @@ | ||
| 11586 | |||
| 11587 | /* { dg-do assemble } */ | ||
| 11588 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11589 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11590 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11591 | +/* { dg-add-options arm_neon } */ | ||
| 11592 | |||
| 11593 | #include "arm_neon.h" | ||
| 11594 | |||
| 11595 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c | ||
| 11596 | =================================================================== | ||
| 11597 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c | ||
| 11598 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c | ||
| 11599 | @@ -3,7 +3,8 @@ | ||
| 11600 | |||
| 11601 | /* { dg-do assemble } */ | ||
| 11602 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11603 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11604 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11605 | +/* { dg-add-options arm_neon } */ | ||
| 11606 | |||
| 11607 | #include "arm_neon.h" | ||
| 11608 | |||
| 11609 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c | ||
| 11610 | =================================================================== | ||
| 11611 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c | ||
| 11612 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c | ||
| 11613 | @@ -3,7 +3,8 @@ | ||
| 11614 | |||
| 11615 | /* { dg-do assemble } */ | ||
| 11616 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11617 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11618 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11619 | +/* { dg-add-options arm_neon } */ | ||
| 11620 | |||
| 11621 | #include "arm_neon.h" | ||
| 11622 | |||
| 11623 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c | ||
| 11624 | =================================================================== | ||
| 11625 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c | ||
| 11626 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c | ||
| 11627 | @@ -3,7 +3,8 @@ | ||
| 11628 | |||
| 11629 | /* { dg-do assemble } */ | ||
| 11630 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11631 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11632 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11633 | +/* { dg-add-options arm_neon } */ | ||
| 11634 | |||
| 11635 | #include "arm_neon.h" | ||
| 11636 | |||
| 11637 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c | ||
| 11638 | =================================================================== | ||
| 11639 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c | ||
| 11640 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c | ||
| 11641 | @@ -3,7 +3,8 @@ | ||
| 11642 | |||
| 11643 | /* { dg-do assemble } */ | ||
| 11644 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11645 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11646 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11647 | +/* { dg-add-options arm_neon } */ | ||
| 11648 | |||
| 11649 | #include "arm_neon.h" | ||
| 11650 | |||
| 11651 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c | ||
| 11652 | =================================================================== | ||
| 11653 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c | ||
| 11654 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c | ||
| 11655 | @@ -3,7 +3,8 @@ | ||
| 11656 | |||
| 11657 | /* { dg-do assemble } */ | ||
| 11658 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11659 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11660 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11661 | +/* { dg-add-options arm_neon } */ | ||
| 11662 | |||
| 11663 | #include "arm_neon.h" | ||
| 11664 | |||
| 11665 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c | ||
| 11666 | =================================================================== | ||
| 11667 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c | ||
| 11668 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c | ||
| 11669 | @@ -3,7 +3,8 @@ | ||
| 11670 | |||
| 11671 | /* { dg-do assemble } */ | ||
| 11672 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11673 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11674 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11675 | +/* { dg-add-options arm_neon } */ | ||
| 11676 | |||
| 11677 | #include "arm_neon.h" | ||
| 11678 | |||
| 11679 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c | ||
| 11680 | =================================================================== | ||
| 11681 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c | ||
| 11682 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c | ||
| 11683 | @@ -3,7 +3,8 @@ | ||
| 11684 | |||
| 11685 | /* { dg-do assemble } */ | ||
| 11686 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11687 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11688 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11689 | +/* { dg-add-options arm_neon } */ | ||
| 11690 | |||
| 11691 | #include "arm_neon.h" | ||
| 11692 | |||
| 11693 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c | ||
| 11694 | =================================================================== | ||
| 11695 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c | ||
| 11696 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c | ||
| 11697 | @@ -3,7 +3,8 @@ | ||
| 11698 | |||
| 11699 | /* { dg-do assemble } */ | ||
| 11700 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11701 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11702 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11703 | +/* { dg-add-options arm_neon } */ | ||
| 11704 | |||
| 11705 | #include "arm_neon.h" | ||
| 11706 | |||
| 11707 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c | ||
| 11708 | =================================================================== | ||
| 11709 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c | ||
| 11710 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c | ||
| 11711 | @@ -3,7 +3,8 @@ | ||
| 11712 | |||
| 11713 | /* { dg-do assemble } */ | ||
| 11714 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11715 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11716 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11717 | +/* { dg-add-options arm_neon } */ | ||
| 11718 | |||
| 11719 | #include "arm_neon.h" | ||
| 11720 | |||
| 11721 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c | ||
| 11722 | =================================================================== | ||
| 11723 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c | ||
| 11724 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c | ||
| 11725 | @@ -3,7 +3,8 @@ | ||
| 11726 | |||
| 11727 | /* { dg-do assemble } */ | ||
| 11728 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11729 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11730 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11731 | +/* { dg-add-options arm_neon } */ | ||
| 11732 | |||
| 11733 | #include "arm_neon.h" | ||
| 11734 | |||
| 11735 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c | ||
| 11736 | =================================================================== | ||
| 11737 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c | ||
| 11738 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c | ||
| 11739 | @@ -3,7 +3,8 @@ | ||
| 11740 | |||
| 11741 | /* { dg-do assemble } */ | ||
| 11742 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11743 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11744 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11745 | +/* { dg-add-options arm_neon } */ | ||
| 11746 | |||
| 11747 | #include "arm_neon.h" | ||
| 11748 | |||
| 11749 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c | ||
| 11750 | =================================================================== | ||
| 11751 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c | ||
| 11752 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c | ||
| 11753 | @@ -3,7 +3,8 @@ | ||
| 11754 | |||
| 11755 | /* { dg-do assemble } */ | ||
| 11756 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11757 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11758 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11759 | +/* { dg-add-options arm_neon } */ | ||
| 11760 | |||
| 11761 | #include "arm_neon.h" | ||
| 11762 | |||
| 11763 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c | ||
| 11764 | =================================================================== | ||
| 11765 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c | ||
| 11766 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c | ||
| 11767 | @@ -3,7 +3,8 @@ | ||
| 11768 | |||
| 11769 | /* { dg-do assemble } */ | ||
| 11770 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11771 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11772 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11773 | +/* { dg-add-options arm_neon } */ | ||
| 11774 | |||
| 11775 | #include "arm_neon.h" | ||
| 11776 | |||
| 11777 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c | ||
| 11778 | =================================================================== | ||
| 11779 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c | ||
| 11780 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c | ||
| 11781 | @@ -3,7 +3,8 @@ | ||
| 11782 | |||
| 11783 | /* { dg-do assemble } */ | ||
| 11784 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11785 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11786 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11787 | +/* { dg-add-options arm_neon } */ | ||
| 11788 | |||
| 11789 | #include "arm_neon.h" | ||
| 11790 | |||
| 11791 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c | ||
| 11792 | =================================================================== | ||
| 11793 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c | ||
| 11794 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c | ||
| 11795 | @@ -3,7 +3,8 @@ | ||
| 11796 | |||
| 11797 | /* { dg-do assemble } */ | ||
| 11798 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11799 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11800 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11801 | +/* { dg-add-options arm_neon } */ | ||
| 11802 | |||
| 11803 | #include "arm_neon.h" | ||
| 11804 | |||
| 11805 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c | ||
| 11806 | =================================================================== | ||
| 11807 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c | ||
| 11808 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c | ||
| 11809 | @@ -3,7 +3,8 @@ | ||
| 11810 | |||
| 11811 | /* { dg-do assemble } */ | ||
| 11812 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11813 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11814 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11815 | +/* { dg-add-options arm_neon } */ | ||
| 11816 | |||
| 11817 | #include "arm_neon.h" | ||
| 11818 | |||
| 11819 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c | ||
| 11820 | =================================================================== | ||
| 11821 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c | ||
| 11822 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c | ||
| 11823 | @@ -3,7 +3,8 @@ | ||
| 11824 | |||
| 11825 | /* { dg-do assemble } */ | ||
| 11826 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11827 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11828 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11829 | +/* { dg-add-options arm_neon } */ | ||
| 11830 | |||
| 11831 | #include "arm_neon.h" | ||
| 11832 | |||
| 11833 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c | ||
| 11834 | =================================================================== | ||
| 11835 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c | ||
| 11836 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c | ||
| 11837 | @@ -3,7 +3,8 @@ | ||
| 11838 | |||
| 11839 | /* { dg-do assemble } */ | ||
| 11840 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11841 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11842 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11843 | +/* { dg-add-options arm_neon } */ | ||
| 11844 | |||
| 11845 | #include "arm_neon.h" | ||
| 11846 | |||
| 11847 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c | ||
| 11848 | =================================================================== | ||
| 11849 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c | ||
| 11850 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c | ||
| 11851 | @@ -3,7 +3,8 @@ | ||
| 11852 | |||
| 11853 | /* { dg-do assemble } */ | ||
| 11854 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11855 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11856 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11857 | +/* { dg-add-options arm_neon } */ | ||
| 11858 | |||
| 11859 | #include "arm_neon.h" | ||
| 11860 | |||
| 11861 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c | ||
| 11862 | =================================================================== | ||
| 11863 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c | ||
| 11864 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c | ||
| 11865 | @@ -3,7 +3,8 @@ | ||
| 11866 | |||
| 11867 | /* { dg-do assemble } */ | ||
| 11868 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11869 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11870 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11871 | +/* { dg-add-options arm_neon } */ | ||
| 11872 | |||
| 11873 | #include "arm_neon.h" | ||
| 11874 | |||
| 11875 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c | ||
| 11876 | =================================================================== | ||
| 11877 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c | ||
| 11878 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c | ||
| 11879 | @@ -3,7 +3,8 @@ | ||
| 11880 | |||
| 11881 | /* { dg-do assemble } */ | ||
| 11882 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11883 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11884 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11885 | +/* { dg-add-options arm_neon } */ | ||
| 11886 | |||
| 11887 | #include "arm_neon.h" | ||
| 11888 | |||
| 11889 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c | ||
| 11890 | =================================================================== | ||
| 11891 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c | ||
| 11892 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c | ||
| 11893 | @@ -3,7 +3,8 @@ | ||
| 11894 | |||
| 11895 | /* { dg-do assemble } */ | ||
| 11896 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11897 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11898 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11899 | +/* { dg-add-options arm_neon } */ | ||
| 11900 | |||
| 11901 | #include "arm_neon.h" | ||
| 11902 | |||
| 11903 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c | ||
| 11904 | =================================================================== | ||
| 11905 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c | ||
| 11906 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c | ||
| 11907 | @@ -3,7 +3,8 @@ | ||
| 11908 | |||
| 11909 | /* { dg-do assemble } */ | ||
| 11910 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11911 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11912 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11913 | +/* { dg-add-options arm_neon } */ | ||
| 11914 | |||
| 11915 | #include "arm_neon.h" | ||
| 11916 | |||
| 11917 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c | ||
| 11918 | =================================================================== | ||
| 11919 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c | ||
| 11920 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c | ||
| 11921 | @@ -3,7 +3,8 @@ | ||
| 11922 | |||
| 11923 | /* { dg-do assemble } */ | ||
| 11924 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11925 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11926 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11927 | +/* { dg-add-options arm_neon } */ | ||
| 11928 | |||
| 11929 | #include "arm_neon.h" | ||
| 11930 | |||
| 11931 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c | ||
| 11932 | =================================================================== | ||
| 11933 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c | ||
| 11934 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c | ||
| 11935 | @@ -3,7 +3,8 @@ | ||
| 11936 | |||
| 11937 | /* { dg-do assemble } */ | ||
| 11938 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11939 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11940 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11941 | +/* { dg-add-options arm_neon } */ | ||
| 11942 | |||
| 11943 | #include "arm_neon.h" | ||
| 11944 | |||
| 11945 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlss16.c | ||
| 11946 | =================================================================== | ||
| 11947 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlss16.c | ||
| 11948 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlss16.c | ||
| 11949 | @@ -3,7 +3,8 @@ | ||
| 11950 | |||
| 11951 | /* { dg-do assemble } */ | ||
| 11952 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11953 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11954 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11955 | +/* { dg-add-options arm_neon } */ | ||
| 11956 | |||
| 11957 | #include "arm_neon.h" | ||
| 11958 | |||
| 11959 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlss32.c | ||
| 11960 | =================================================================== | ||
| 11961 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlss32.c | ||
| 11962 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlss32.c | ||
| 11963 | @@ -3,7 +3,8 @@ | ||
| 11964 | |||
| 11965 | /* { dg-do assemble } */ | ||
| 11966 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11967 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11968 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11969 | +/* { dg-add-options arm_neon } */ | ||
| 11970 | |||
| 11971 | #include "arm_neon.h" | ||
| 11972 | |||
| 11973 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlss8.c | ||
| 11974 | =================================================================== | ||
| 11975 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlss8.c | ||
| 11976 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlss8.c | ||
| 11977 | @@ -3,7 +3,8 @@ | ||
| 11978 | |||
| 11979 | /* { dg-do assemble } */ | ||
| 11980 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11981 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11982 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11983 | +/* { dg-add-options arm_neon } */ | ||
| 11984 | |||
| 11985 | #include "arm_neon.h" | ||
| 11986 | |||
| 11987 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c | ||
| 11988 | =================================================================== | ||
| 11989 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c | ||
| 11990 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c | ||
| 11991 | @@ -3,7 +3,8 @@ | ||
| 11992 | |||
| 11993 | /* { dg-do assemble } */ | ||
| 11994 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 11995 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 11996 | +/* { dg-options "-save-temps -O0" } */ | ||
| 11997 | +/* { dg-add-options arm_neon } */ | ||
| 11998 | |||
| 11999 | #include "arm_neon.h" | ||
| 12000 | |||
| 12001 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c | ||
| 12002 | =================================================================== | ||
| 12003 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c | ||
| 12004 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c | ||
| 12005 | @@ -3,7 +3,8 @@ | ||
| 12006 | |||
| 12007 | /* { dg-do assemble } */ | ||
| 12008 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12009 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12010 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12011 | +/* { dg-add-options arm_neon } */ | ||
| 12012 | |||
| 12013 | #include "arm_neon.h" | ||
| 12014 | |||
| 12015 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c | ||
| 12016 | =================================================================== | ||
| 12017 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c | ||
| 12018 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c | ||
| 12019 | @@ -3,7 +3,8 @@ | ||
| 12020 | |||
| 12021 | /* { dg-do assemble } */ | ||
| 12022 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12023 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12024 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12025 | +/* { dg-add-options arm_neon } */ | ||
| 12026 | |||
| 12027 | #include "arm_neon.h" | ||
| 12028 | |||
| 12029 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c | ||
| 12030 | =================================================================== | ||
| 12031 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c | ||
| 12032 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c | ||
| 12033 | @@ -3,7 +3,8 @@ | ||
| 12034 | |||
| 12035 | /* { dg-do assemble } */ | ||
| 12036 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12037 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12038 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12039 | +/* { dg-add-options arm_neon } */ | ||
| 12040 | |||
| 12041 | #include "arm_neon.h" | ||
| 12042 | |||
| 12043 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c | ||
| 12044 | =================================================================== | ||
| 12045 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c | ||
| 12046 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c | ||
| 12047 | @@ -3,7 +3,8 @@ | ||
| 12048 | |||
| 12049 | /* { dg-do assemble } */ | ||
| 12050 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12051 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12052 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12053 | +/* { dg-add-options arm_neon } */ | ||
| 12054 | |||
| 12055 | #include "arm_neon.h" | ||
| 12056 | |||
| 12057 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c | ||
| 12058 | =================================================================== | ||
| 12059 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c | ||
| 12060 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c | ||
| 12061 | @@ -3,7 +3,8 @@ | ||
| 12062 | |||
| 12063 | /* { dg-do assemble } */ | ||
| 12064 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12065 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12066 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12067 | +/* { dg-add-options arm_neon } */ | ||
| 12068 | |||
| 12069 | #include "arm_neon.h" | ||
| 12070 | |||
| 12071 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c | ||
| 12072 | =================================================================== | ||
| 12073 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c | ||
| 12074 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c | ||
| 12075 | @@ -3,7 +3,8 @@ | ||
| 12076 | |||
| 12077 | /* { dg-do assemble } */ | ||
| 12078 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12079 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12080 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12081 | +/* { dg-add-options arm_neon } */ | ||
| 12082 | |||
| 12083 | #include "arm_neon.h" | ||
| 12084 | |||
| 12085 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c | ||
| 12086 | =================================================================== | ||
| 12087 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c | ||
| 12088 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c | ||
| 12089 | @@ -3,7 +3,8 @@ | ||
| 12090 | |||
| 12091 | /* { dg-do assemble } */ | ||
| 12092 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12093 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12094 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12095 | +/* { dg-add-options arm_neon } */ | ||
| 12096 | |||
| 12097 | #include "arm_neon.h" | ||
| 12098 | |||
| 12099 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c | ||
| 12100 | =================================================================== | ||
| 12101 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c | ||
| 12102 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c | ||
| 12103 | @@ -3,7 +3,8 @@ | ||
| 12104 | |||
| 12105 | /* { dg-do assemble } */ | ||
| 12106 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12107 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12108 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12109 | +/* { dg-add-options arm_neon } */ | ||
| 12110 | |||
| 12111 | #include "arm_neon.h" | ||
| 12112 | |||
| 12113 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c | ||
| 12114 | =================================================================== | ||
| 12115 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c | ||
| 12116 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c | ||
| 12117 | @@ -3,7 +3,8 @@ | ||
| 12118 | |||
| 12119 | /* { dg-do assemble } */ | ||
| 12120 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12121 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12122 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12123 | +/* { dg-add-options arm_neon } */ | ||
| 12124 | |||
| 12125 | #include "arm_neon.h" | ||
| 12126 | |||
| 12127 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c | ||
| 12128 | =================================================================== | ||
| 12129 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c | ||
| 12130 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c | ||
| 12131 | @@ -3,7 +3,8 @@ | ||
| 12132 | |||
| 12133 | /* { dg-do assemble } */ | ||
| 12134 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12135 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12136 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12137 | +/* { dg-add-options arm_neon } */ | ||
| 12138 | |||
| 12139 | #include "arm_neon.h" | ||
| 12140 | |||
| 12141 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c | ||
| 12142 | =================================================================== | ||
| 12143 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c | ||
| 12144 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c | ||
| 12145 | @@ -3,7 +3,8 @@ | ||
| 12146 | |||
| 12147 | /* { dg-do assemble } */ | ||
| 12148 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12149 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12150 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12151 | +/* { dg-add-options arm_neon } */ | ||
| 12152 | |||
| 12153 | #include "arm_neon.h" | ||
| 12154 | |||
| 12155 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c | ||
| 12156 | =================================================================== | ||
| 12157 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c | ||
| 12158 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c | ||
| 12159 | @@ -3,7 +3,8 @@ | ||
| 12160 | |||
| 12161 | /* { dg-do assemble } */ | ||
| 12162 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12163 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12164 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12165 | +/* { dg-add-options arm_neon } */ | ||
| 12166 | |||
| 12167 | #include "arm_neon.h" | ||
| 12168 | |||
| 12169 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c | ||
| 12170 | =================================================================== | ||
| 12171 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c | ||
| 12172 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c | ||
| 12173 | @@ -3,7 +3,8 @@ | ||
| 12174 | |||
| 12175 | /* { dg-do assemble } */ | ||
| 12176 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12177 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12178 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12179 | +/* { dg-add-options arm_neon } */ | ||
| 12180 | |||
| 12181 | #include "arm_neon.h" | ||
| 12182 | |||
| 12183 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c | ||
| 12184 | =================================================================== | ||
| 12185 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c | ||
| 12186 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c | ||
| 12187 | @@ -3,7 +3,8 @@ | ||
| 12188 | |||
| 12189 | /* { dg-do assemble } */ | ||
| 12190 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12191 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12192 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12193 | +/* { dg-add-options arm_neon } */ | ||
| 12194 | |||
| 12195 | #include "arm_neon.h" | ||
| 12196 | |||
| 12197 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c | ||
| 12198 | =================================================================== | ||
| 12199 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c | ||
| 12200 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c | ||
| 12201 | @@ -3,7 +3,8 @@ | ||
| 12202 | |||
| 12203 | /* { dg-do assemble } */ | ||
| 12204 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12205 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12206 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12207 | +/* { dg-add-options arm_neon } */ | ||
| 12208 | |||
| 12209 | #include "arm_neon.h" | ||
| 12210 | |||
| 12211 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c | ||
| 12212 | =================================================================== | ||
| 12213 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c | ||
| 12214 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c | ||
| 12215 | @@ -3,7 +3,8 @@ | ||
| 12216 | |||
| 12217 | /* { dg-do assemble } */ | ||
| 12218 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12219 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12220 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12221 | +/* { dg-add-options arm_neon } */ | ||
| 12222 | |||
| 12223 | #include "arm_neon.h" | ||
| 12224 | |||
| 12225 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c | ||
| 12226 | =================================================================== | ||
| 12227 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c | ||
| 12228 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c | ||
| 12229 | @@ -3,7 +3,8 @@ | ||
| 12230 | |||
| 12231 | /* { dg-do assemble } */ | ||
| 12232 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12233 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12234 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12235 | +/* { dg-add-options arm_neon } */ | ||
| 12236 | |||
| 12237 | #include "arm_neon.h" | ||
| 12238 | |||
| 12239 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c | ||
| 12240 | =================================================================== | ||
| 12241 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c | ||
| 12242 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c | ||
| 12243 | @@ -3,7 +3,8 @@ | ||
| 12244 | |||
| 12245 | /* { dg-do assemble } */ | ||
| 12246 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12247 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12248 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12249 | +/* { dg-add-options arm_neon } */ | ||
| 12250 | |||
| 12251 | #include "arm_neon.h" | ||
| 12252 | |||
| 12253 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c | ||
| 12254 | =================================================================== | ||
| 12255 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c | ||
| 12256 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c | ||
| 12257 | @@ -3,7 +3,8 @@ | ||
| 12258 | |||
| 12259 | /* { dg-do assemble } */ | ||
| 12260 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12261 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12262 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12263 | +/* { dg-add-options arm_neon } */ | ||
| 12264 | |||
| 12265 | #include "arm_neon.h" | ||
| 12266 | |||
| 12267 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c | ||
| 12268 | =================================================================== | ||
| 12269 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c | ||
| 12270 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c | ||
| 12271 | @@ -3,7 +3,8 @@ | ||
| 12272 | |||
| 12273 | /* { dg-do assemble } */ | ||
| 12274 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12275 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12276 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12277 | +/* { dg-add-options arm_neon } */ | ||
| 12278 | |||
| 12279 | #include "arm_neon.h" | ||
| 12280 | |||
| 12281 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c | ||
| 12282 | =================================================================== | ||
| 12283 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c | ||
| 12284 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c | ||
| 12285 | @@ -3,7 +3,8 @@ | ||
| 12286 | |||
| 12287 | /* { dg-do assemble } */ | ||
| 12288 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12289 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12290 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12291 | +/* { dg-add-options arm_neon } */ | ||
| 12292 | |||
| 12293 | #include "arm_neon.h" | ||
| 12294 | |||
| 12295 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c | ||
| 12296 | =================================================================== | ||
| 12297 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c | ||
| 12298 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c | ||
| 12299 | @@ -3,7 +3,8 @@ | ||
| 12300 | |||
| 12301 | /* { dg-do assemble } */ | ||
| 12302 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12303 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12304 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12305 | +/* { dg-add-options arm_neon } */ | ||
| 12306 | |||
| 12307 | #include "arm_neon.h" | ||
| 12308 | |||
| 12309 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c | ||
| 12310 | =================================================================== | ||
| 12311 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c | ||
| 12312 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c | ||
| 12313 | @@ -3,7 +3,8 @@ | ||
| 12314 | |||
| 12315 | /* { dg-do assemble } */ | ||
| 12316 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12317 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12318 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12319 | +/* { dg-add-options arm_neon } */ | ||
| 12320 | |||
| 12321 | #include "arm_neon.h" | ||
| 12322 | |||
| 12323 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c | ||
| 12324 | =================================================================== | ||
| 12325 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c | ||
| 12326 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c | ||
| 12327 | @@ -3,7 +3,8 @@ | ||
| 12328 | |||
| 12329 | /* { dg-do assemble } */ | ||
| 12330 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12331 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12332 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12333 | +/* { dg-add-options arm_neon } */ | ||
| 12334 | |||
| 12335 | #include "arm_neon.h" | ||
| 12336 | |||
| 12337 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovls16.c | ||
| 12338 | =================================================================== | ||
| 12339 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovls16.c | ||
| 12340 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovls16.c | ||
| 12341 | @@ -3,7 +3,8 @@ | ||
| 12342 | |||
| 12343 | /* { dg-do assemble } */ | ||
| 12344 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12345 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12346 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12347 | +/* { dg-add-options arm_neon } */ | ||
| 12348 | |||
| 12349 | #include "arm_neon.h" | ||
| 12350 | |||
| 12351 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovls32.c | ||
| 12352 | =================================================================== | ||
| 12353 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovls32.c | ||
| 12354 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovls32.c | ||
| 12355 | @@ -3,7 +3,8 @@ | ||
| 12356 | |||
| 12357 | /* { dg-do assemble } */ | ||
| 12358 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12359 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12360 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12361 | +/* { dg-add-options arm_neon } */ | ||
| 12362 | |||
| 12363 | #include "arm_neon.h" | ||
| 12364 | |||
| 12365 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovls8.c | ||
| 12366 | =================================================================== | ||
| 12367 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovls8.c | ||
| 12368 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovls8.c | ||
| 12369 | @@ -3,7 +3,8 @@ | ||
| 12370 | |||
| 12371 | /* { dg-do assemble } */ | ||
| 12372 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12373 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12374 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12375 | +/* { dg-add-options arm_neon } */ | ||
| 12376 | |||
| 12377 | #include "arm_neon.h" | ||
| 12378 | |||
| 12379 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c | ||
| 12380 | =================================================================== | ||
| 12381 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c | ||
| 12382 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c | ||
| 12383 | @@ -3,7 +3,8 @@ | ||
| 12384 | |||
| 12385 | /* { dg-do assemble } */ | ||
| 12386 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12387 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12388 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12389 | +/* { dg-add-options arm_neon } */ | ||
| 12390 | |||
| 12391 | #include "arm_neon.h" | ||
| 12392 | |||
| 12393 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c | ||
| 12394 | =================================================================== | ||
| 12395 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c | ||
| 12396 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c | ||
| 12397 | @@ -3,7 +3,8 @@ | ||
| 12398 | |||
| 12399 | /* { dg-do assemble } */ | ||
| 12400 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12401 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12402 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12403 | +/* { dg-add-options arm_neon } */ | ||
| 12404 | |||
| 12405 | #include "arm_neon.h" | ||
| 12406 | |||
| 12407 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c | ||
| 12408 | =================================================================== | ||
| 12409 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c | ||
| 12410 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c | ||
| 12411 | @@ -3,7 +3,8 @@ | ||
| 12412 | |||
| 12413 | /* { dg-do assemble } */ | ||
| 12414 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12415 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12416 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12417 | +/* { dg-add-options arm_neon } */ | ||
| 12418 | |||
| 12419 | #include "arm_neon.h" | ||
| 12420 | |||
| 12421 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovns16.c | ||
| 12422 | =================================================================== | ||
| 12423 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovns16.c | ||
| 12424 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovns16.c | ||
| 12425 | @@ -3,7 +3,8 @@ | ||
| 12426 | |||
| 12427 | /* { dg-do assemble } */ | ||
| 12428 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12429 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12430 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12431 | +/* { dg-add-options arm_neon } */ | ||
| 12432 | |||
| 12433 | #include "arm_neon.h" | ||
| 12434 | |||
| 12435 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovns32.c | ||
| 12436 | =================================================================== | ||
| 12437 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovns32.c | ||
| 12438 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovns32.c | ||
| 12439 | @@ -3,7 +3,8 @@ | ||
| 12440 | |||
| 12441 | /* { dg-do assemble } */ | ||
| 12442 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12443 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12444 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12445 | +/* { dg-add-options arm_neon } */ | ||
| 12446 | |||
| 12447 | #include "arm_neon.h" | ||
| 12448 | |||
| 12449 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovns64.c | ||
| 12450 | =================================================================== | ||
| 12451 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovns64.c | ||
| 12452 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovns64.c | ||
| 12453 | @@ -3,7 +3,8 @@ | ||
| 12454 | |||
| 12455 | /* { dg-do assemble } */ | ||
| 12456 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12457 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12458 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12459 | +/* { dg-add-options arm_neon } */ | ||
| 12460 | |||
| 12461 | #include "arm_neon.h" | ||
| 12462 | |||
| 12463 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c | ||
| 12464 | =================================================================== | ||
| 12465 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c | ||
| 12466 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c | ||
| 12467 | @@ -3,7 +3,8 @@ | ||
| 12468 | |||
| 12469 | /* { dg-do assemble } */ | ||
| 12470 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12471 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12472 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12473 | +/* { dg-add-options arm_neon } */ | ||
| 12474 | |||
| 12475 | #include "arm_neon.h" | ||
| 12476 | |||
| 12477 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c | ||
| 12478 | =================================================================== | ||
| 12479 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c | ||
| 12480 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c | ||
| 12481 | @@ -3,7 +3,8 @@ | ||
| 12482 | |||
| 12483 | /* { dg-do assemble } */ | ||
| 12484 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12485 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12486 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12487 | +/* { dg-add-options arm_neon } */ | ||
| 12488 | |||
| 12489 | #include "arm_neon.h" | ||
| 12490 | |||
| 12491 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c | ||
| 12492 | =================================================================== | ||
| 12493 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c | ||
| 12494 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c | ||
| 12495 | @@ -3,7 +3,8 @@ | ||
| 12496 | |||
| 12497 | /* { dg-do assemble } */ | ||
| 12498 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12499 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12500 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12501 | +/* { dg-add-options arm_neon } */ | ||
| 12502 | |||
| 12503 | #include "arm_neon.h" | ||
| 12504 | |||
| 12505 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c | ||
| 12506 | =================================================================== | ||
| 12507 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c | ||
| 12508 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c | ||
| 12509 | @@ -3,7 +3,8 @@ | ||
| 12510 | |||
| 12511 | /* { dg-do assemble } */ | ||
| 12512 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12513 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12514 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12515 | +/* { dg-add-options arm_neon } */ | ||
| 12516 | |||
| 12517 | #include "arm_neon.h" | ||
| 12518 | |||
| 12519 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c | ||
| 12520 | =================================================================== | ||
| 12521 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c | ||
| 12522 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c | ||
| 12523 | @@ -3,7 +3,8 @@ | ||
| 12524 | |||
| 12525 | /* { dg-do assemble } */ | ||
| 12526 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12527 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12528 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12529 | +/* { dg-add-options arm_neon } */ | ||
| 12530 | |||
| 12531 | #include "arm_neon.h" | ||
| 12532 | |||
| 12533 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c | ||
| 12534 | =================================================================== | ||
| 12535 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c | ||
| 12536 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c | ||
| 12537 | @@ -3,7 +3,8 @@ | ||
| 12538 | |||
| 12539 | /* { dg-do assemble } */ | ||
| 12540 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12541 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12542 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12543 | +/* { dg-add-options arm_neon } */ | ||
| 12544 | |||
| 12545 | #include "arm_neon.h" | ||
| 12546 | |||
| 12547 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c | ||
| 12548 | =================================================================== | ||
| 12549 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c | ||
| 12550 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c | ||
| 12551 | @@ -3,7 +3,8 @@ | ||
| 12552 | |||
| 12553 | /* { dg-do assemble } */ | ||
| 12554 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12555 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12556 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12557 | +/* { dg-add-options arm_neon } */ | ||
| 12558 | |||
| 12559 | #include "arm_neon.h" | ||
| 12560 | |||
| 12561 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c | ||
| 12562 | =================================================================== | ||
| 12563 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c | ||
| 12564 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c | ||
| 12565 | @@ -3,7 +3,8 @@ | ||
| 12566 | |||
| 12567 | /* { dg-do assemble } */ | ||
| 12568 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12569 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12570 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12571 | +/* { dg-add-options arm_neon } */ | ||
| 12572 | |||
| 12573 | #include "arm_neon.h" | ||
| 12574 | |||
| 12575 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c | ||
| 12576 | =================================================================== | ||
| 12577 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c | ||
| 12578 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c | ||
| 12579 | @@ -3,7 +3,8 @@ | ||
| 12580 | |||
| 12581 | /* { dg-do assemble } */ | ||
| 12582 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12583 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12584 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12585 | +/* { dg-add-options arm_neon } */ | ||
| 12586 | |||
| 12587 | #include "arm_neon.h" | ||
| 12588 | |||
| 12589 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c | ||
| 12590 | =================================================================== | ||
| 12591 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c | ||
| 12592 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c | ||
| 12593 | @@ -3,7 +3,8 @@ | ||
| 12594 | |||
| 12595 | /* { dg-do assemble } */ | ||
| 12596 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12597 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12598 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12599 | +/* { dg-add-options arm_neon } */ | ||
| 12600 | |||
| 12601 | #include "arm_neon.h" | ||
| 12602 | |||
| 12603 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c | ||
| 12604 | =================================================================== | ||
| 12605 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c | ||
| 12606 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c | ||
| 12607 | @@ -3,7 +3,8 @@ | ||
| 12608 | |||
| 12609 | /* { dg-do assemble } */ | ||
| 12610 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12611 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12612 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12613 | +/* { dg-add-options arm_neon } */ | ||
| 12614 | |||
| 12615 | #include "arm_neon.h" | ||
| 12616 | |||
| 12617 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c | ||
| 12618 | =================================================================== | ||
| 12619 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c | ||
| 12620 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c | ||
| 12621 | @@ -3,7 +3,8 @@ | ||
| 12622 | |||
| 12623 | /* { dg-do assemble } */ | ||
| 12624 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12625 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12626 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12627 | +/* { dg-add-options arm_neon } */ | ||
| 12628 | |||
| 12629 | #include "arm_neon.h" | ||
| 12630 | |||
| 12631 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c | ||
| 12632 | =================================================================== | ||
| 12633 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c | ||
| 12634 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c | ||
| 12635 | @@ -3,7 +3,8 @@ | ||
| 12636 | |||
| 12637 | /* { dg-do assemble } */ | ||
| 12638 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12639 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12640 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12641 | +/* { dg-add-options arm_neon } */ | ||
| 12642 | |||
| 12643 | #include "arm_neon.h" | ||
| 12644 | |||
| 12645 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c | ||
| 12646 | =================================================================== | ||
| 12647 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c | ||
| 12648 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c | ||
| 12649 | @@ -3,7 +3,8 @@ | ||
| 12650 | |||
| 12651 | /* { dg-do assemble } */ | ||
| 12652 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12653 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12654 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12655 | +/* { dg-add-options arm_neon } */ | ||
| 12656 | |||
| 12657 | #include "arm_neon.h" | ||
| 12658 | |||
| 12659 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c | ||
| 12660 | =================================================================== | ||
| 12661 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c | ||
| 12662 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c | ||
| 12663 | @@ -3,7 +3,8 @@ | ||
| 12664 | |||
| 12665 | /* { dg-do assemble } */ | ||
| 12666 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12667 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12668 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12669 | +/* { dg-add-options arm_neon } */ | ||
| 12670 | |||
| 12671 | #include "arm_neon.h" | ||
| 12672 | |||
| 12673 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c | ||
| 12674 | =================================================================== | ||
| 12675 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c | ||
| 12676 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c | ||
| 12677 | @@ -3,7 +3,8 @@ | ||
| 12678 | |||
| 12679 | /* { dg-do assemble } */ | ||
| 12680 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12681 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12682 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12683 | +/* { dg-add-options arm_neon } */ | ||
| 12684 | |||
| 12685 | #include "arm_neon.h" | ||
| 12686 | |||
| 12687 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c | ||
| 12688 | =================================================================== | ||
| 12689 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c | ||
| 12690 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c | ||
| 12691 | @@ -3,7 +3,8 @@ | ||
| 12692 | |||
| 12693 | /* { dg-do assemble } */ | ||
| 12694 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12695 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12696 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12697 | +/* { dg-add-options arm_neon } */ | ||
| 12698 | |||
| 12699 | #include "arm_neon.h" | ||
| 12700 | |||
| 12701 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c | ||
| 12702 | =================================================================== | ||
| 12703 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c | ||
| 12704 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c | ||
| 12705 | @@ -3,7 +3,8 @@ | ||
| 12706 | |||
| 12707 | /* { dg-do assemble } */ | ||
| 12708 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12709 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12710 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12711 | +/* { dg-add-options arm_neon } */ | ||
| 12712 | |||
| 12713 | #include "arm_neon.h" | ||
| 12714 | |||
| 12715 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c | ||
| 12716 | =================================================================== | ||
| 12717 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c | ||
| 12718 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c | ||
| 12719 | @@ -3,7 +3,8 @@ | ||
| 12720 | |||
| 12721 | /* { dg-do assemble } */ | ||
| 12722 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12723 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12724 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12725 | +/* { dg-add-options arm_neon } */ | ||
| 12726 | |||
| 12727 | #include "arm_neon.h" | ||
| 12728 | |||
| 12729 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c | ||
| 12730 | =================================================================== | ||
| 12731 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c | ||
| 12732 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c | ||
| 12733 | @@ -3,7 +3,8 @@ | ||
| 12734 | |||
| 12735 | /* { dg-do assemble } */ | ||
| 12736 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12737 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12738 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12739 | +/* { dg-add-options arm_neon } */ | ||
| 12740 | |||
| 12741 | #include "arm_neon.h" | ||
| 12742 | |||
| 12743 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c | ||
| 12744 | =================================================================== | ||
| 12745 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c | ||
| 12746 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c | ||
| 12747 | @@ -3,7 +3,8 @@ | ||
| 12748 | |||
| 12749 | /* { dg-do assemble } */ | ||
| 12750 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12751 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12752 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12753 | +/* { dg-add-options arm_neon } */ | ||
| 12754 | |||
| 12755 | #include "arm_neon.h" | ||
| 12756 | |||
| 12757 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c | ||
| 12758 | =================================================================== | ||
| 12759 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c | ||
| 12760 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c | ||
| 12761 | @@ -3,7 +3,8 @@ | ||
| 12762 | |||
| 12763 | /* { dg-do assemble } */ | ||
| 12764 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12765 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12766 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12767 | +/* { dg-add-options arm_neon } */ | ||
| 12768 | |||
| 12769 | #include "arm_neon.h" | ||
| 12770 | |||
| 12771 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c | ||
| 12772 | =================================================================== | ||
| 12773 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c | ||
| 12774 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c | ||
| 12775 | @@ -3,7 +3,8 @@ | ||
| 12776 | |||
| 12777 | /* { dg-do assemble } */ | ||
| 12778 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12779 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12780 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12781 | +/* { dg-add-options arm_neon } */ | ||
| 12782 | |||
| 12783 | #include "arm_neon.h" | ||
| 12784 | |||
| 12785 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c | ||
| 12786 | =================================================================== | ||
| 12787 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c | ||
| 12788 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c | ||
| 12789 | @@ -3,7 +3,8 @@ | ||
| 12790 | |||
| 12791 | /* { dg-do assemble } */ | ||
| 12792 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12793 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12794 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12795 | +/* { dg-add-options arm_neon } */ | ||
| 12796 | |||
| 12797 | #include "arm_neon.h" | ||
| 12798 | |||
| 12799 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c | ||
| 12800 | =================================================================== | ||
| 12801 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c | ||
| 12802 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c | ||
| 12803 | @@ -3,7 +3,8 @@ | ||
| 12804 | |||
| 12805 | /* { dg-do assemble } */ | ||
| 12806 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12807 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12808 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12809 | +/* { dg-add-options arm_neon } */ | ||
| 12810 | |||
| 12811 | #include "arm_neon.h" | ||
| 12812 | |||
| 12813 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c | ||
| 12814 | =================================================================== | ||
| 12815 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c | ||
| 12816 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c | ||
| 12817 | @@ -3,7 +3,8 @@ | ||
| 12818 | |||
| 12819 | /* { dg-do assemble } */ | ||
| 12820 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12821 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12822 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12823 | +/* { dg-add-options arm_neon } */ | ||
| 12824 | |||
| 12825 | #include "arm_neon.h" | ||
| 12826 | |||
| 12827 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c | ||
| 12828 | =================================================================== | ||
| 12829 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c | ||
| 12830 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c | ||
| 12831 | @@ -3,7 +3,8 @@ | ||
| 12832 | |||
| 12833 | /* { dg-do assemble } */ | ||
| 12834 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12835 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12836 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12837 | +/* { dg-add-options arm_neon } */ | ||
| 12838 | |||
| 12839 | #include "arm_neon.h" | ||
| 12840 | |||
| 12841 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c | ||
| 12842 | =================================================================== | ||
| 12843 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c | ||
| 12844 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c | ||
| 12845 | @@ -3,7 +3,8 @@ | ||
| 12846 | |||
| 12847 | /* { dg-do assemble } */ | ||
| 12848 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12849 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12850 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12851 | +/* { dg-add-options arm_neon } */ | ||
| 12852 | |||
| 12853 | #include "arm_neon.h" | ||
| 12854 | |||
| 12855 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c | ||
| 12856 | =================================================================== | ||
| 12857 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c | ||
| 12858 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c | ||
| 12859 | @@ -3,7 +3,8 @@ | ||
| 12860 | |||
| 12861 | /* { dg-do assemble } */ | ||
| 12862 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12863 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12864 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12865 | +/* { dg-add-options arm_neon } */ | ||
| 12866 | |||
| 12867 | #include "arm_neon.h" | ||
| 12868 | |||
| 12869 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c | ||
| 12870 | =================================================================== | ||
| 12871 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c | ||
| 12872 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c | ||
| 12873 | @@ -3,7 +3,8 @@ | ||
| 12874 | |||
| 12875 | /* { dg-do assemble } */ | ||
| 12876 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12877 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12878 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12879 | +/* { dg-add-options arm_neon } */ | ||
| 12880 | |||
| 12881 | #include "arm_neon.h" | ||
| 12882 | |||
| 12883 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c | ||
| 12884 | =================================================================== | ||
| 12885 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c | ||
| 12886 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c | ||
| 12887 | @@ -3,7 +3,8 @@ | ||
| 12888 | |||
| 12889 | /* { dg-do assemble } */ | ||
| 12890 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12891 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12892 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12893 | +/* { dg-add-options arm_neon } */ | ||
| 12894 | |||
| 12895 | #include "arm_neon.h" | ||
| 12896 | |||
| 12897 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulf32.c | ||
| 12898 | =================================================================== | ||
| 12899 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulf32.c | ||
| 12900 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulf32.c | ||
| 12901 | @@ -3,7 +3,8 @@ | ||
| 12902 | |||
| 12903 | /* { dg-do assemble } */ | ||
| 12904 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12905 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12906 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12907 | +/* { dg-add-options arm_neon } */ | ||
| 12908 | |||
| 12909 | #include "arm_neon.h" | ||
| 12910 | |||
| 12911 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c | ||
| 12912 | =================================================================== | ||
| 12913 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c | ||
| 12914 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c | ||
| 12915 | @@ -3,7 +3,8 @@ | ||
| 12916 | |||
| 12917 | /* { dg-do assemble } */ | ||
| 12918 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12919 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12920 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12921 | +/* { dg-add-options arm_neon } */ | ||
| 12922 | |||
| 12923 | #include "arm_neon.h" | ||
| 12924 | |||
| 12925 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c | ||
| 12926 | =================================================================== | ||
| 12927 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c | ||
| 12928 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c | ||
| 12929 | @@ -3,7 +3,8 @@ | ||
| 12930 | |||
| 12931 | /* { dg-do assemble } */ | ||
| 12932 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12933 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12934 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12935 | +/* { dg-add-options arm_neon } */ | ||
| 12936 | |||
| 12937 | #include "arm_neon.h" | ||
| 12938 | |||
| 12939 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c | ||
| 12940 | =================================================================== | ||
| 12941 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c | ||
| 12942 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c | ||
| 12943 | @@ -3,7 +3,8 @@ | ||
| 12944 | |||
| 12945 | /* { dg-do assemble } */ | ||
| 12946 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12947 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12948 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12949 | +/* { dg-add-options arm_neon } */ | ||
| 12950 | |||
| 12951 | #include "arm_neon.h" | ||
| 12952 | |||
| 12953 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c | ||
| 12954 | =================================================================== | ||
| 12955 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c | ||
| 12956 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c | ||
| 12957 | @@ -3,7 +3,8 @@ | ||
| 12958 | |||
| 12959 | /* { dg-do assemble } */ | ||
| 12960 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12961 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12962 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12963 | +/* { dg-add-options arm_neon } */ | ||
| 12964 | |||
| 12965 | #include "arm_neon.h" | ||
| 12966 | |||
| 12967 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c | ||
| 12968 | =================================================================== | ||
| 12969 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c | ||
| 12970 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c | ||
| 12971 | @@ -3,7 +3,8 @@ | ||
| 12972 | |||
| 12973 | /* { dg-do assemble } */ | ||
| 12974 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12975 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12976 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12977 | +/* { dg-add-options arm_neon } */ | ||
| 12978 | |||
| 12979 | #include "arm_neon.h" | ||
| 12980 | |||
| 12981 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c | ||
| 12982 | =================================================================== | ||
| 12983 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c | ||
| 12984 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c | ||
| 12985 | @@ -3,7 +3,8 @@ | ||
| 12986 | |||
| 12987 | /* { dg-do assemble } */ | ||
| 12988 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 12989 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 12990 | +/* { dg-options "-save-temps -O0" } */ | ||
| 12991 | +/* { dg-add-options arm_neon } */ | ||
| 12992 | |||
| 12993 | #include "arm_neon.h" | ||
| 12994 | |||
| 12995 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c | ||
| 12996 | =================================================================== | ||
| 12997 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c | ||
| 12998 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c | ||
| 12999 | @@ -3,7 +3,8 @@ | ||
| 13000 | |||
| 13001 | /* { dg-do assemble } */ | ||
| 13002 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13003 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13004 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13005 | +/* { dg-add-options arm_neon } */ | ||
| 13006 | |||
| 13007 | #include "arm_neon.h" | ||
| 13008 | |||
| 13009 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c | ||
| 13010 | =================================================================== | ||
| 13011 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c | ||
| 13012 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c | ||
| 13013 | @@ -3,7 +3,8 @@ | ||
| 13014 | |||
| 13015 | /* { dg-do assemble } */ | ||
| 13016 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13017 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13018 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13019 | +/* { dg-add-options arm_neon } */ | ||
| 13020 | |||
| 13021 | #include "arm_neon.h" | ||
| 13022 | |||
| 13023 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullp8.c | ||
| 13024 | =================================================================== | ||
| 13025 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmullp8.c | ||
| 13026 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullp8.c | ||
| 13027 | @@ -3,7 +3,8 @@ | ||
| 13028 | |||
| 13029 | /* { dg-do assemble } */ | ||
| 13030 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13031 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13032 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13033 | +/* { dg-add-options arm_neon } */ | ||
| 13034 | |||
| 13035 | #include "arm_neon.h" | ||
| 13036 | |||
| 13037 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulls16.c | ||
| 13038 | =================================================================== | ||
| 13039 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulls16.c | ||
| 13040 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulls16.c | ||
| 13041 | @@ -3,7 +3,8 @@ | ||
| 13042 | |||
| 13043 | /* { dg-do assemble } */ | ||
| 13044 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13045 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13046 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13047 | +/* { dg-add-options arm_neon } */ | ||
| 13048 | |||
| 13049 | #include "arm_neon.h" | ||
| 13050 | |||
| 13051 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulls32.c | ||
| 13052 | =================================================================== | ||
| 13053 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulls32.c | ||
| 13054 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulls32.c | ||
| 13055 | @@ -3,7 +3,8 @@ | ||
| 13056 | |||
| 13057 | /* { dg-do assemble } */ | ||
| 13058 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13059 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13060 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13061 | +/* { dg-add-options arm_neon } */ | ||
| 13062 | |||
| 13063 | #include "arm_neon.h" | ||
| 13064 | |||
| 13065 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulls8.c | ||
| 13066 | =================================================================== | ||
| 13067 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulls8.c | ||
| 13068 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulls8.c | ||
| 13069 | @@ -3,7 +3,8 @@ | ||
| 13070 | |||
| 13071 | /* { dg-do assemble } */ | ||
| 13072 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13073 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13074 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13075 | +/* { dg-add-options arm_neon } */ | ||
| 13076 | |||
| 13077 | #include "arm_neon.h" | ||
| 13078 | |||
| 13079 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullu16.c | ||
| 13080 | =================================================================== | ||
| 13081 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmullu16.c | ||
| 13082 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullu16.c | ||
| 13083 | @@ -3,7 +3,8 @@ | ||
| 13084 | |||
| 13085 | /* { dg-do assemble } */ | ||
| 13086 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13087 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13088 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13089 | +/* { dg-add-options arm_neon } */ | ||
| 13090 | |||
| 13091 | #include "arm_neon.h" | ||
| 13092 | |||
| 13093 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullu32.c | ||
| 13094 | =================================================================== | ||
| 13095 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmullu32.c | ||
| 13096 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullu32.c | ||
| 13097 | @@ -3,7 +3,8 @@ | ||
| 13098 | |||
| 13099 | /* { dg-do assemble } */ | ||
| 13100 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13101 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13102 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13103 | +/* { dg-add-options arm_neon } */ | ||
| 13104 | |||
| 13105 | #include "arm_neon.h" | ||
| 13106 | |||
| 13107 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullu8.c | ||
| 13108 | =================================================================== | ||
| 13109 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmullu8.c | ||
| 13110 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmullu8.c | ||
| 13111 | @@ -3,7 +3,8 @@ | ||
| 13112 | |||
| 13113 | /* { dg-do assemble } */ | ||
| 13114 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13115 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13116 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13117 | +/* { dg-add-options arm_neon } */ | ||
| 13118 | |||
| 13119 | #include "arm_neon.h" | ||
| 13120 | |||
| 13121 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulp8.c | ||
| 13122 | =================================================================== | ||
| 13123 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulp8.c | ||
| 13124 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulp8.c | ||
| 13125 | @@ -3,7 +3,8 @@ | ||
| 13126 | |||
| 13127 | /* { dg-do assemble } */ | ||
| 13128 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13129 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13130 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13131 | +/* { dg-add-options arm_neon } */ | ||
| 13132 | |||
| 13133 | #include "arm_neon.h" | ||
| 13134 | |||
| 13135 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmuls16.c | ||
| 13136 | =================================================================== | ||
| 13137 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmuls16.c | ||
| 13138 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmuls16.c | ||
| 13139 | @@ -3,7 +3,8 @@ | ||
| 13140 | |||
| 13141 | /* { dg-do assemble } */ | ||
| 13142 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13143 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13144 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13145 | +/* { dg-add-options arm_neon } */ | ||
| 13146 | |||
| 13147 | #include "arm_neon.h" | ||
| 13148 | |||
| 13149 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmuls32.c | ||
| 13150 | =================================================================== | ||
| 13151 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmuls32.c | ||
| 13152 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmuls32.c | ||
| 13153 | @@ -3,7 +3,8 @@ | ||
| 13154 | |||
| 13155 | /* { dg-do assemble } */ | ||
| 13156 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13157 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13158 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13159 | +/* { dg-add-options arm_neon } */ | ||
| 13160 | |||
| 13161 | #include "arm_neon.h" | ||
| 13162 | |||
| 13163 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmuls8.c | ||
| 13164 | =================================================================== | ||
| 13165 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmuls8.c | ||
| 13166 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmuls8.c | ||
| 13167 | @@ -3,7 +3,8 @@ | ||
| 13168 | |||
| 13169 | /* { dg-do assemble } */ | ||
| 13170 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13171 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13172 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13173 | +/* { dg-add-options arm_neon } */ | ||
| 13174 | |||
| 13175 | #include "arm_neon.h" | ||
| 13176 | |||
| 13177 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulu16.c | ||
| 13178 | =================================================================== | ||
| 13179 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulu16.c | ||
| 13180 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulu16.c | ||
| 13181 | @@ -3,7 +3,8 @@ | ||
| 13182 | |||
| 13183 | /* { dg-do assemble } */ | ||
| 13184 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13185 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13186 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13187 | +/* { dg-add-options arm_neon } */ | ||
| 13188 | |||
| 13189 | #include "arm_neon.h" | ||
| 13190 | |||
| 13191 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulu32.c | ||
| 13192 | =================================================================== | ||
| 13193 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulu32.c | ||
| 13194 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulu32.c | ||
| 13195 | @@ -3,7 +3,8 @@ | ||
| 13196 | |||
| 13197 | /* { dg-do assemble } */ | ||
| 13198 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13199 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13200 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13201 | +/* { dg-add-options arm_neon } */ | ||
| 13202 | |||
| 13203 | #include "arm_neon.h" | ||
| 13204 | |||
| 13205 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulu8.c | ||
| 13206 | =================================================================== | ||
| 13207 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmulu8.c | ||
| 13208 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmulu8.c | ||
| 13209 | @@ -3,7 +3,8 @@ | ||
| 13210 | |||
| 13211 | /* { dg-do assemble } */ | ||
| 13212 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13213 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13214 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13215 | +/* { dg-add-options arm_neon } */ | ||
| 13216 | |||
| 13217 | #include "arm_neon.h" | ||
| 13218 | |||
| 13219 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c | ||
| 13220 | =================================================================== | ||
| 13221 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c | ||
| 13222 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c | ||
| 13223 | @@ -3,7 +3,8 @@ | ||
| 13224 | |||
| 13225 | /* { dg-do assemble } */ | ||
| 13226 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13227 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13228 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13229 | +/* { dg-add-options arm_neon } */ | ||
| 13230 | |||
| 13231 | #include "arm_neon.h" | ||
| 13232 | |||
| 13233 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c | ||
| 13234 | =================================================================== | ||
| 13235 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c | ||
| 13236 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c | ||
| 13237 | @@ -3,7 +3,8 @@ | ||
| 13238 | |||
| 13239 | /* { dg-do assemble } */ | ||
| 13240 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13241 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13242 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13243 | +/* { dg-add-options arm_neon } */ | ||
| 13244 | |||
| 13245 | #include "arm_neon.h" | ||
| 13246 | |||
| 13247 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c | ||
| 13248 | =================================================================== | ||
| 13249 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c | ||
| 13250 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c | ||
| 13251 | @@ -3,7 +3,8 @@ | ||
| 13252 | |||
| 13253 | /* { dg-do assemble } */ | ||
| 13254 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13255 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13256 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13257 | +/* { dg-add-options arm_neon } */ | ||
| 13258 | |||
| 13259 | #include "arm_neon.h" | ||
| 13260 | |||
| 13261 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c | ||
| 13262 | =================================================================== | ||
| 13263 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c | ||
| 13264 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c | ||
| 13265 | @@ -3,7 +3,8 @@ | ||
| 13266 | |||
| 13267 | /* { dg-do assemble } */ | ||
| 13268 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13269 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13270 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13271 | +/* { dg-add-options arm_neon } */ | ||
| 13272 | |||
| 13273 | #include "arm_neon.h" | ||
| 13274 | |||
| 13275 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c | ||
| 13276 | =================================================================== | ||
| 13277 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c | ||
| 13278 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c | ||
| 13279 | @@ -3,7 +3,8 @@ | ||
| 13280 | |||
| 13281 | /* { dg-do assemble } */ | ||
| 13282 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13283 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13284 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13285 | +/* { dg-add-options arm_neon } */ | ||
| 13286 | |||
| 13287 | #include "arm_neon.h" | ||
| 13288 | |||
| 13289 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c | ||
| 13290 | =================================================================== | ||
| 13291 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c | ||
| 13292 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c | ||
| 13293 | @@ -3,7 +3,8 @@ | ||
| 13294 | |||
| 13295 | /* { dg-do assemble } */ | ||
| 13296 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13297 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13298 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13299 | +/* { dg-add-options arm_neon } */ | ||
| 13300 | |||
| 13301 | #include "arm_neon.h" | ||
| 13302 | |||
| 13303 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c | ||
| 13304 | =================================================================== | ||
| 13305 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c | ||
| 13306 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c | ||
| 13307 | @@ -3,7 +3,8 @@ | ||
| 13308 | |||
| 13309 | /* { dg-do assemble } */ | ||
| 13310 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13311 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13312 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13313 | +/* { dg-add-options arm_neon } */ | ||
| 13314 | |||
| 13315 | #include "arm_neon.h" | ||
| 13316 | |||
| 13317 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c | ||
| 13318 | =================================================================== | ||
| 13319 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c | ||
| 13320 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c | ||
| 13321 | @@ -3,7 +3,8 @@ | ||
| 13322 | |||
| 13323 | /* { dg-do assemble } */ | ||
| 13324 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13325 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13326 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13327 | +/* { dg-add-options arm_neon } */ | ||
| 13328 | |||
| 13329 | #include "arm_neon.h" | ||
| 13330 | |||
| 13331 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvns16.c | ||
| 13332 | =================================================================== | ||
| 13333 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvns16.c | ||
| 13334 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvns16.c | ||
| 13335 | @@ -3,7 +3,8 @@ | ||
| 13336 | |||
| 13337 | /* { dg-do assemble } */ | ||
| 13338 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13339 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13340 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13341 | +/* { dg-add-options arm_neon } */ | ||
| 13342 | |||
| 13343 | #include "arm_neon.h" | ||
| 13344 | |||
| 13345 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvns32.c | ||
| 13346 | =================================================================== | ||
| 13347 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvns32.c | ||
| 13348 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvns32.c | ||
| 13349 | @@ -3,7 +3,8 @@ | ||
| 13350 | |||
| 13351 | /* { dg-do assemble } */ | ||
| 13352 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13353 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13354 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13355 | +/* { dg-add-options arm_neon } */ | ||
| 13356 | |||
| 13357 | #include "arm_neon.h" | ||
| 13358 | |||
| 13359 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvns8.c | ||
| 13360 | =================================================================== | ||
| 13361 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvns8.c | ||
| 13362 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvns8.c | ||
| 13363 | @@ -3,7 +3,8 @@ | ||
| 13364 | |||
| 13365 | /* { dg-do assemble } */ | ||
| 13366 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13367 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13368 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13369 | +/* { dg-add-options arm_neon } */ | ||
| 13370 | |||
| 13371 | #include "arm_neon.h" | ||
| 13372 | |||
| 13373 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c | ||
| 13374 | =================================================================== | ||
| 13375 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c | ||
| 13376 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c | ||
| 13377 | @@ -3,7 +3,8 @@ | ||
| 13378 | |||
| 13379 | /* { dg-do assemble } */ | ||
| 13380 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13381 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13382 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13383 | +/* { dg-add-options arm_neon } */ | ||
| 13384 | |||
| 13385 | #include "arm_neon.h" | ||
| 13386 | |||
| 13387 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c | ||
| 13388 | =================================================================== | ||
| 13389 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c | ||
| 13390 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c | ||
| 13391 | @@ -3,7 +3,8 @@ | ||
| 13392 | |||
| 13393 | /* { dg-do assemble } */ | ||
| 13394 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13395 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13396 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13397 | +/* { dg-add-options arm_neon } */ | ||
| 13398 | |||
| 13399 | #include "arm_neon.h" | ||
| 13400 | |||
| 13401 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c | ||
| 13402 | =================================================================== | ||
| 13403 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c | ||
| 13404 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c | ||
| 13405 | @@ -3,7 +3,8 @@ | ||
| 13406 | |||
| 13407 | /* { dg-do assemble } */ | ||
| 13408 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13409 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13410 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13411 | +/* { dg-add-options arm_neon } */ | ||
| 13412 | |||
| 13413 | #include "arm_neon.h" | ||
| 13414 | |||
| 13415 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c | ||
| 13416 | =================================================================== | ||
| 13417 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c | ||
| 13418 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c | ||
| 13419 | @@ -3,7 +3,8 @@ | ||
| 13420 | |||
| 13421 | /* { dg-do assemble } */ | ||
| 13422 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13423 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13424 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13425 | +/* { dg-add-options arm_neon } */ | ||
| 13426 | |||
| 13427 | #include "arm_neon.h" | ||
| 13428 | |||
| 13429 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c | ||
| 13430 | =================================================================== | ||
| 13431 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c | ||
| 13432 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c | ||
| 13433 | @@ -3,7 +3,8 @@ | ||
| 13434 | |||
| 13435 | /* { dg-do assemble } */ | ||
| 13436 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13437 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13438 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13439 | +/* { dg-add-options arm_neon } */ | ||
| 13440 | |||
| 13441 | #include "arm_neon.h" | ||
| 13442 | |||
| 13443 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c | ||
| 13444 | =================================================================== | ||
| 13445 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c | ||
| 13446 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c | ||
| 13447 | @@ -3,7 +3,8 @@ | ||
| 13448 | |||
| 13449 | /* { dg-do assemble } */ | ||
| 13450 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13451 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13452 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13453 | +/* { dg-add-options arm_neon } */ | ||
| 13454 | |||
| 13455 | #include "arm_neon.h" | ||
| 13456 | |||
| 13457 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c | ||
| 13458 | =================================================================== | ||
| 13459 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c | ||
| 13460 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c | ||
| 13461 | @@ -3,7 +3,8 @@ | ||
| 13462 | |||
| 13463 | /* { dg-do assemble } */ | ||
| 13464 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13465 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13466 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13467 | +/* { dg-add-options arm_neon } */ | ||
| 13468 | |||
| 13469 | #include "arm_neon.h" | ||
| 13470 | |||
| 13471 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegf32.c | ||
| 13472 | =================================================================== | ||
| 13473 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegf32.c | ||
| 13474 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegf32.c | ||
| 13475 | @@ -3,7 +3,8 @@ | ||
| 13476 | |||
| 13477 | /* { dg-do assemble } */ | ||
| 13478 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13479 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13480 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13481 | +/* { dg-add-options arm_neon } */ | ||
| 13482 | |||
| 13483 | #include "arm_neon.h" | ||
| 13484 | |||
| 13485 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegs16.c | ||
| 13486 | =================================================================== | ||
| 13487 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegs16.c | ||
| 13488 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegs16.c | ||
| 13489 | @@ -3,7 +3,8 @@ | ||
| 13490 | |||
| 13491 | /* { dg-do assemble } */ | ||
| 13492 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13493 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13494 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13495 | +/* { dg-add-options arm_neon } */ | ||
| 13496 | |||
| 13497 | #include "arm_neon.h" | ||
| 13498 | |||
| 13499 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegs32.c | ||
| 13500 | =================================================================== | ||
| 13501 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegs32.c | ||
| 13502 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegs32.c | ||
| 13503 | @@ -3,7 +3,8 @@ | ||
| 13504 | |||
| 13505 | /* { dg-do assemble } */ | ||
| 13506 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13507 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13508 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13509 | +/* { dg-add-options arm_neon } */ | ||
| 13510 | |||
| 13511 | #include "arm_neon.h" | ||
| 13512 | |||
| 13513 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegs8.c | ||
| 13514 | =================================================================== | ||
| 13515 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vnegs8.c | ||
| 13516 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vnegs8.c | ||
| 13517 | @@ -3,7 +3,8 @@ | ||
| 13518 | |||
| 13519 | /* { dg-do assemble } */ | ||
| 13520 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13521 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13522 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13523 | +/* { dg-add-options arm_neon } */ | ||
| 13524 | |||
| 13525 | #include "arm_neon.h" | ||
| 13526 | |||
| 13527 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs16.c | ||
| 13528 | =================================================================== | ||
| 13529 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQs16.c | ||
| 13530 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs16.c | ||
| 13531 | @@ -3,7 +3,8 @@ | ||
| 13532 | |||
| 13533 | /* { dg-do assemble } */ | ||
| 13534 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13535 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13536 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13537 | +/* { dg-add-options arm_neon } */ | ||
| 13538 | |||
| 13539 | #include "arm_neon.h" | ||
| 13540 | |||
| 13541 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs32.c | ||
| 13542 | =================================================================== | ||
| 13543 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQs32.c | ||
| 13544 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs32.c | ||
| 13545 | @@ -3,7 +3,8 @@ | ||
| 13546 | |||
| 13547 | /* { dg-do assemble } */ | ||
| 13548 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13549 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13550 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13551 | +/* { dg-add-options arm_neon } */ | ||
| 13552 | |||
| 13553 | #include "arm_neon.h" | ||
| 13554 | |||
| 13555 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs64.c | ||
| 13556 | =================================================================== | ||
| 13557 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQs64.c | ||
| 13558 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs64.c | ||
| 13559 | @@ -3,7 +3,8 @@ | ||
| 13560 | |||
| 13561 | /* { dg-do assemble } */ | ||
| 13562 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13563 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13564 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13565 | +/* { dg-add-options arm_neon } */ | ||
| 13566 | |||
| 13567 | #include "arm_neon.h" | ||
| 13568 | |||
| 13569 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs8.c | ||
| 13570 | =================================================================== | ||
| 13571 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQs8.c | ||
| 13572 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQs8.c | ||
| 13573 | @@ -3,7 +3,8 @@ | ||
| 13574 | |||
| 13575 | /* { dg-do assemble } */ | ||
| 13576 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13577 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13578 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13579 | +/* { dg-add-options arm_neon } */ | ||
| 13580 | |||
| 13581 | #include "arm_neon.h" | ||
| 13582 | |||
| 13583 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu16.c | ||
| 13584 | =================================================================== | ||
| 13585 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQu16.c | ||
| 13586 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu16.c | ||
| 13587 | @@ -3,7 +3,8 @@ | ||
| 13588 | |||
| 13589 | /* { dg-do assemble } */ | ||
| 13590 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13591 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13592 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13593 | +/* { dg-add-options arm_neon } */ | ||
| 13594 | |||
| 13595 | #include "arm_neon.h" | ||
| 13596 | |||
| 13597 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu32.c | ||
| 13598 | =================================================================== | ||
| 13599 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQu32.c | ||
| 13600 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu32.c | ||
| 13601 | @@ -3,7 +3,8 @@ | ||
| 13602 | |||
| 13603 | /* { dg-do assemble } */ | ||
| 13604 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13605 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13606 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13607 | +/* { dg-add-options arm_neon } */ | ||
| 13608 | |||
| 13609 | #include "arm_neon.h" | ||
| 13610 | |||
| 13611 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu64.c | ||
| 13612 | =================================================================== | ||
| 13613 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQu64.c | ||
| 13614 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu64.c | ||
| 13615 | @@ -3,7 +3,8 @@ | ||
| 13616 | |||
| 13617 | /* { dg-do assemble } */ | ||
| 13618 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13619 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13620 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13621 | +/* { dg-add-options arm_neon } */ | ||
| 13622 | |||
| 13623 | #include "arm_neon.h" | ||
| 13624 | |||
| 13625 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu8.c | ||
| 13626 | =================================================================== | ||
| 13627 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornQu8.c | ||
| 13628 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornQu8.c | ||
| 13629 | @@ -3,7 +3,8 @@ | ||
| 13630 | |||
| 13631 | /* { dg-do assemble } */ | ||
| 13632 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13633 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13634 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13635 | +/* { dg-add-options arm_neon } */ | ||
| 13636 | |||
| 13637 | #include "arm_neon.h" | ||
| 13638 | |||
| 13639 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns16.c | ||
| 13640 | =================================================================== | ||
| 13641 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorns16.c | ||
| 13642 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns16.c | ||
| 13643 | @@ -3,7 +3,8 @@ | ||
| 13644 | |||
| 13645 | /* { dg-do assemble } */ | ||
| 13646 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13647 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13648 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13649 | +/* { dg-add-options arm_neon } */ | ||
| 13650 | |||
| 13651 | #include "arm_neon.h" | ||
| 13652 | |||
| 13653 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns32.c | ||
| 13654 | =================================================================== | ||
| 13655 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorns32.c | ||
| 13656 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns32.c | ||
| 13657 | @@ -3,7 +3,8 @@ | ||
| 13658 | |||
| 13659 | /* { dg-do assemble } */ | ||
| 13660 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13661 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13662 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13663 | +/* { dg-add-options arm_neon } */ | ||
| 13664 | |||
| 13665 | #include "arm_neon.h" | ||
| 13666 | |||
| 13667 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns64.c | ||
| 13668 | =================================================================== | ||
| 13669 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorns64.c | ||
| 13670 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns64.c | ||
| 13671 | @@ -3,7 +3,8 @@ | ||
| 13672 | |||
| 13673 | /* { dg-do assemble } */ | ||
| 13674 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13675 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13676 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13677 | +/* { dg-add-options arm_neon } */ | ||
| 13678 | |||
| 13679 | #include "arm_neon.h" | ||
| 13680 | |||
| 13681 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns8.c | ||
| 13682 | =================================================================== | ||
| 13683 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorns8.c | ||
| 13684 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorns8.c | ||
| 13685 | @@ -3,7 +3,8 @@ | ||
| 13686 | |||
| 13687 | /* { dg-do assemble } */ | ||
| 13688 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13689 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13690 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13691 | +/* { dg-add-options arm_neon } */ | ||
| 13692 | |||
| 13693 | #include "arm_neon.h" | ||
| 13694 | |||
| 13695 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu16.c | ||
| 13696 | =================================================================== | ||
| 13697 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornu16.c | ||
| 13698 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu16.c | ||
| 13699 | @@ -3,7 +3,8 @@ | ||
| 13700 | |||
| 13701 | /* { dg-do assemble } */ | ||
| 13702 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13703 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13704 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13705 | +/* { dg-add-options arm_neon } */ | ||
| 13706 | |||
| 13707 | #include "arm_neon.h" | ||
| 13708 | |||
| 13709 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu32.c | ||
| 13710 | =================================================================== | ||
| 13711 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornu32.c | ||
| 13712 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu32.c | ||
| 13713 | @@ -3,7 +3,8 @@ | ||
| 13714 | |||
| 13715 | /* { dg-do assemble } */ | ||
| 13716 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13717 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13718 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13719 | +/* { dg-add-options arm_neon } */ | ||
| 13720 | |||
| 13721 | #include "arm_neon.h" | ||
| 13722 | |||
| 13723 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu64.c | ||
| 13724 | =================================================================== | ||
| 13725 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornu64.c | ||
| 13726 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu64.c | ||
| 13727 | @@ -3,7 +3,8 @@ | ||
| 13728 | |||
| 13729 | /* { dg-do assemble } */ | ||
| 13730 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13731 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13732 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13733 | +/* { dg-add-options arm_neon } */ | ||
| 13734 | |||
| 13735 | #include "arm_neon.h" | ||
| 13736 | |||
| 13737 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu8.c | ||
| 13738 | =================================================================== | ||
| 13739 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vornu8.c | ||
| 13740 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vornu8.c | ||
| 13741 | @@ -3,7 +3,8 @@ | ||
| 13742 | |||
| 13743 | /* { dg-do assemble } */ | ||
| 13744 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13745 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13746 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13747 | +/* { dg-add-options arm_neon } */ | ||
| 13748 | |||
| 13749 | #include "arm_neon.h" | ||
| 13750 | |||
| 13751 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c | ||
| 13752 | =================================================================== | ||
| 13753 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c | ||
| 13754 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c | ||
| 13755 | @@ -3,7 +3,8 @@ | ||
| 13756 | |||
| 13757 | /* { dg-do assemble } */ | ||
| 13758 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13759 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13760 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13761 | +/* { dg-add-options arm_neon } */ | ||
| 13762 | |||
| 13763 | #include "arm_neon.h" | ||
| 13764 | |||
| 13765 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c | ||
| 13766 | =================================================================== | ||
| 13767 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c | ||
| 13768 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c | ||
| 13769 | @@ -3,7 +3,8 @@ | ||
| 13770 | |||
| 13771 | /* { dg-do assemble } */ | ||
| 13772 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13773 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13774 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13775 | +/* { dg-add-options arm_neon } */ | ||
| 13776 | |||
| 13777 | #include "arm_neon.h" | ||
| 13778 | |||
| 13779 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c | ||
| 13780 | =================================================================== | ||
| 13781 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c | ||
| 13782 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c | ||
| 13783 | @@ -3,7 +3,8 @@ | ||
| 13784 | |||
| 13785 | /* { dg-do assemble } */ | ||
| 13786 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13787 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13788 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13789 | +/* { dg-add-options arm_neon } */ | ||
| 13790 | |||
| 13791 | #include "arm_neon.h" | ||
| 13792 | |||
| 13793 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c | ||
| 13794 | =================================================================== | ||
| 13795 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c | ||
| 13796 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c | ||
| 13797 | @@ -3,7 +3,8 @@ | ||
| 13798 | |||
| 13799 | /* { dg-do assemble } */ | ||
| 13800 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13801 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13802 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13803 | +/* { dg-add-options arm_neon } */ | ||
| 13804 | |||
| 13805 | #include "arm_neon.h" | ||
| 13806 | |||
| 13807 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c | ||
| 13808 | =================================================================== | ||
| 13809 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c | ||
| 13810 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c | ||
| 13811 | @@ -3,7 +3,8 @@ | ||
| 13812 | |||
| 13813 | /* { dg-do assemble } */ | ||
| 13814 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13815 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13816 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13817 | +/* { dg-add-options arm_neon } */ | ||
| 13818 | |||
| 13819 | #include "arm_neon.h" | ||
| 13820 | |||
| 13821 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c | ||
| 13822 | =================================================================== | ||
| 13823 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c | ||
| 13824 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c | ||
| 13825 | @@ -3,7 +3,8 @@ | ||
| 13826 | |||
| 13827 | /* { dg-do assemble } */ | ||
| 13828 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13829 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13830 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13831 | +/* { dg-add-options arm_neon } */ | ||
| 13832 | |||
| 13833 | #include "arm_neon.h" | ||
| 13834 | |||
| 13835 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c | ||
| 13836 | =================================================================== | ||
| 13837 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c | ||
| 13838 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c | ||
| 13839 | @@ -3,7 +3,8 @@ | ||
| 13840 | |||
| 13841 | /* { dg-do assemble } */ | ||
| 13842 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13843 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13844 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13845 | +/* { dg-add-options arm_neon } */ | ||
| 13846 | |||
| 13847 | #include "arm_neon.h" | ||
| 13848 | |||
| 13849 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c | ||
| 13850 | =================================================================== | ||
| 13851 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c | ||
| 13852 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c | ||
| 13853 | @@ -3,7 +3,8 @@ | ||
| 13854 | |||
| 13855 | /* { dg-do assemble } */ | ||
| 13856 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13857 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13858 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13859 | +/* { dg-add-options arm_neon } */ | ||
| 13860 | |||
| 13861 | #include "arm_neon.h" | ||
| 13862 | |||
| 13863 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs16.c | ||
| 13864 | =================================================================== | ||
| 13865 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrs16.c | ||
| 13866 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs16.c | ||
| 13867 | @@ -3,7 +3,8 @@ | ||
| 13868 | |||
| 13869 | /* { dg-do assemble } */ | ||
| 13870 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13871 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13872 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13873 | +/* { dg-add-options arm_neon } */ | ||
| 13874 | |||
| 13875 | #include "arm_neon.h" | ||
| 13876 | |||
| 13877 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs32.c | ||
| 13878 | =================================================================== | ||
| 13879 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrs32.c | ||
| 13880 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs32.c | ||
| 13881 | @@ -3,7 +3,8 @@ | ||
| 13882 | |||
| 13883 | /* { dg-do assemble } */ | ||
| 13884 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13885 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13886 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13887 | +/* { dg-add-options arm_neon } */ | ||
| 13888 | |||
| 13889 | #include "arm_neon.h" | ||
| 13890 | |||
| 13891 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs64.c | ||
| 13892 | =================================================================== | ||
| 13893 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrs64.c | ||
| 13894 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs64.c | ||
| 13895 | @@ -3,7 +3,8 @@ | ||
| 13896 | |||
| 13897 | /* { dg-do assemble } */ | ||
| 13898 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13899 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13900 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13901 | +/* { dg-add-options arm_neon } */ | ||
| 13902 | |||
| 13903 | #include "arm_neon.h" | ||
| 13904 | |||
| 13905 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs8.c | ||
| 13906 | =================================================================== | ||
| 13907 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorrs8.c | ||
| 13908 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorrs8.c | ||
| 13909 | @@ -3,7 +3,8 @@ | ||
| 13910 | |||
| 13911 | /* { dg-do assemble } */ | ||
| 13912 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13913 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13914 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13915 | +/* { dg-add-options arm_neon } */ | ||
| 13916 | |||
| 13917 | #include "arm_neon.h" | ||
| 13918 | |||
| 13919 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru16.c | ||
| 13920 | =================================================================== | ||
| 13921 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorru16.c | ||
| 13922 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru16.c | ||
| 13923 | @@ -3,7 +3,8 @@ | ||
| 13924 | |||
| 13925 | /* { dg-do assemble } */ | ||
| 13926 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13927 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13928 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13929 | +/* { dg-add-options arm_neon } */ | ||
| 13930 | |||
| 13931 | #include "arm_neon.h" | ||
| 13932 | |||
| 13933 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru32.c | ||
| 13934 | =================================================================== | ||
| 13935 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorru32.c | ||
| 13936 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru32.c | ||
| 13937 | @@ -3,7 +3,8 @@ | ||
| 13938 | |||
| 13939 | /* { dg-do assemble } */ | ||
| 13940 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13941 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13942 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13943 | +/* { dg-add-options arm_neon } */ | ||
| 13944 | |||
| 13945 | #include "arm_neon.h" | ||
| 13946 | |||
| 13947 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru64.c | ||
| 13948 | =================================================================== | ||
| 13949 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorru64.c | ||
| 13950 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru64.c | ||
| 13951 | @@ -3,7 +3,8 @@ | ||
| 13952 | |||
| 13953 | /* { dg-do assemble } */ | ||
| 13954 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13955 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13956 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13957 | +/* { dg-add-options arm_neon } */ | ||
| 13958 | |||
| 13959 | #include "arm_neon.h" | ||
| 13960 | |||
| 13961 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru8.c | ||
| 13962 | =================================================================== | ||
| 13963 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vorru8.c | ||
| 13964 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vorru8.c | ||
| 13965 | @@ -3,7 +3,8 @@ | ||
| 13966 | |||
| 13967 | /* { dg-do assemble } */ | ||
| 13968 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13969 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13970 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13971 | +/* { dg-add-options arm_neon } */ | ||
| 13972 | |||
| 13973 | #include "arm_neon.h" | ||
| 13974 | |||
| 13975 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c | ||
| 13976 | =================================================================== | ||
| 13977 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c | ||
| 13978 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c | ||
| 13979 | @@ -3,7 +3,8 @@ | ||
| 13980 | |||
| 13981 | /* { dg-do assemble } */ | ||
| 13982 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13983 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13984 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13985 | +/* { dg-add-options arm_neon } */ | ||
| 13986 | |||
| 13987 | #include "arm_neon.h" | ||
| 13988 | |||
| 13989 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c | ||
| 13990 | =================================================================== | ||
| 13991 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c | ||
| 13992 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c | ||
| 13993 | @@ -3,7 +3,8 @@ | ||
| 13994 | |||
| 13995 | /* { dg-do assemble } */ | ||
| 13996 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 13997 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 13998 | +/* { dg-options "-save-temps -O0" } */ | ||
| 13999 | +/* { dg-add-options arm_neon } */ | ||
| 14000 | |||
| 14001 | #include "arm_neon.h" | ||
| 14002 | |||
| 14003 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c | ||
| 14004 | =================================================================== | ||
| 14005 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c | ||
| 14006 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c | ||
| 14007 | @@ -3,7 +3,8 @@ | ||
| 14008 | |||
| 14009 | /* { dg-do assemble } */ | ||
| 14010 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14011 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14012 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14013 | +/* { dg-add-options arm_neon } */ | ||
| 14014 | |||
| 14015 | #include "arm_neon.h" | ||
| 14016 | |||
| 14017 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c | ||
| 14018 | =================================================================== | ||
| 14019 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c | ||
| 14020 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c | ||
| 14021 | @@ -3,7 +3,8 @@ | ||
| 14022 | |||
| 14023 | /* { dg-do assemble } */ | ||
| 14024 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14025 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14026 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14027 | +/* { dg-add-options arm_neon } */ | ||
| 14028 | |||
| 14029 | #include "arm_neon.h" | ||
| 14030 | |||
| 14031 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c | ||
| 14032 | =================================================================== | ||
| 14033 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c | ||
| 14034 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c | ||
| 14035 | @@ -3,7 +3,8 @@ | ||
| 14036 | |||
| 14037 | /* { dg-do assemble } */ | ||
| 14038 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14039 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14040 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14041 | +/* { dg-add-options arm_neon } */ | ||
| 14042 | |||
| 14043 | #include "arm_neon.h" | ||
| 14044 | |||
| 14045 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c | ||
| 14046 | =================================================================== | ||
| 14047 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c | ||
| 14048 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c | ||
| 14049 | @@ -3,7 +3,8 @@ | ||
| 14050 | |||
| 14051 | /* { dg-do assemble } */ | ||
| 14052 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14053 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14054 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14055 | +/* { dg-add-options arm_neon } */ | ||
| 14056 | |||
| 14057 | #include "arm_neon.h" | ||
| 14058 | |||
| 14059 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadals16.c | ||
| 14060 | =================================================================== | ||
| 14061 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadals16.c | ||
| 14062 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadals16.c | ||
| 14063 | @@ -3,7 +3,8 @@ | ||
| 14064 | |||
| 14065 | /* { dg-do assemble } */ | ||
| 14066 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14067 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14068 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14069 | +/* { dg-add-options arm_neon } */ | ||
| 14070 | |||
| 14071 | #include "arm_neon.h" | ||
| 14072 | |||
| 14073 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadals32.c | ||
| 14074 | =================================================================== | ||
| 14075 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadals32.c | ||
| 14076 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadals32.c | ||
| 14077 | @@ -3,7 +3,8 @@ | ||
| 14078 | |||
| 14079 | /* { dg-do assemble } */ | ||
| 14080 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14081 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14082 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14083 | +/* { dg-add-options arm_neon } */ | ||
| 14084 | |||
| 14085 | #include "arm_neon.h" | ||
| 14086 | |||
| 14087 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadals8.c | ||
| 14088 | =================================================================== | ||
| 14089 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadals8.c | ||
| 14090 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadals8.c | ||
| 14091 | @@ -3,7 +3,8 @@ | ||
| 14092 | |||
| 14093 | /* { dg-do assemble } */ | ||
| 14094 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14095 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14096 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14097 | +/* { dg-add-options arm_neon } */ | ||
| 14098 | |||
| 14099 | #include "arm_neon.h" | ||
| 14100 | |||
| 14101 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c | ||
| 14102 | =================================================================== | ||
| 14103 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c | ||
| 14104 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c | ||
| 14105 | @@ -3,7 +3,8 @@ | ||
| 14106 | |||
| 14107 | /* { dg-do assemble } */ | ||
| 14108 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14109 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14110 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14111 | +/* { dg-add-options arm_neon } */ | ||
| 14112 | |||
| 14113 | #include "arm_neon.h" | ||
| 14114 | |||
| 14115 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c | ||
| 14116 | =================================================================== | ||
| 14117 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c | ||
| 14118 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c | ||
| 14119 | @@ -3,7 +3,8 @@ | ||
| 14120 | |||
| 14121 | /* { dg-do assemble } */ | ||
| 14122 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14123 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14124 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14125 | +/* { dg-add-options arm_neon } */ | ||
| 14126 | |||
| 14127 | #include "arm_neon.h" | ||
| 14128 | |||
| 14129 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c | ||
| 14130 | =================================================================== | ||
| 14131 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c | ||
| 14132 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c | ||
| 14133 | @@ -3,7 +3,8 @@ | ||
| 14134 | |||
| 14135 | /* { dg-do assemble } */ | ||
| 14136 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14137 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14138 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14139 | +/* { dg-add-options arm_neon } */ | ||
| 14140 | |||
| 14141 | #include "arm_neon.h" | ||
| 14142 | |||
| 14143 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c | ||
| 14144 | =================================================================== | ||
| 14145 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c | ||
| 14146 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c | ||
| 14147 | @@ -3,7 +3,8 @@ | ||
| 14148 | |||
| 14149 | /* { dg-do assemble } */ | ||
| 14150 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14151 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14152 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14153 | +/* { dg-add-options arm_neon } */ | ||
| 14154 | |||
| 14155 | #include "arm_neon.h" | ||
| 14156 | |||
| 14157 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c | ||
| 14158 | =================================================================== | ||
| 14159 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c | ||
| 14160 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c | ||
| 14161 | @@ -3,7 +3,8 @@ | ||
| 14162 | |||
| 14163 | /* { dg-do assemble } */ | ||
| 14164 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14165 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14166 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14167 | +/* { dg-add-options arm_neon } */ | ||
| 14168 | |||
| 14169 | #include "arm_neon.h" | ||
| 14170 | |||
| 14171 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c | ||
| 14172 | =================================================================== | ||
| 14173 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c | ||
| 14174 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c | ||
| 14175 | @@ -3,7 +3,8 @@ | ||
| 14176 | |||
| 14177 | /* { dg-do assemble } */ | ||
| 14178 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14179 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14180 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14181 | +/* { dg-add-options arm_neon } */ | ||
| 14182 | |||
| 14183 | #include "arm_neon.h" | ||
| 14184 | |||
| 14185 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c | ||
| 14186 | =================================================================== | ||
| 14187 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c | ||
| 14188 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c | ||
| 14189 | @@ -3,7 +3,8 @@ | ||
| 14190 | |||
| 14191 | /* { dg-do assemble } */ | ||
| 14192 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14193 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14194 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14195 | +/* { dg-add-options arm_neon } */ | ||
| 14196 | |||
| 14197 | #include "arm_neon.h" | ||
| 14198 | |||
| 14199 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c | ||
| 14200 | =================================================================== | ||
| 14201 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c | ||
| 14202 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c | ||
| 14203 | @@ -3,7 +3,8 @@ | ||
| 14204 | |||
| 14205 | /* { dg-do assemble } */ | ||
| 14206 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14207 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14208 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14209 | +/* { dg-add-options arm_neon } */ | ||
| 14210 | |||
| 14211 | #include "arm_neon.h" | ||
| 14212 | |||
| 14213 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c | ||
| 14214 | =================================================================== | ||
| 14215 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c | ||
| 14216 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c | ||
| 14217 | @@ -3,7 +3,8 @@ | ||
| 14218 | |||
| 14219 | /* { dg-do assemble } */ | ||
| 14220 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14221 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14222 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14223 | +/* { dg-add-options arm_neon } */ | ||
| 14224 | |||
| 14225 | #include "arm_neon.h" | ||
| 14226 | |||
| 14227 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c | ||
| 14228 | =================================================================== | ||
| 14229 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c | ||
| 14230 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c | ||
| 14231 | @@ -3,7 +3,8 @@ | ||
| 14232 | |||
| 14233 | /* { dg-do assemble } */ | ||
| 14234 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14235 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14236 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14237 | +/* { dg-add-options arm_neon } */ | ||
| 14238 | |||
| 14239 | #include "arm_neon.h" | ||
| 14240 | |||
| 14241 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c | ||
| 14242 | =================================================================== | ||
| 14243 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c | ||
| 14244 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c | ||
| 14245 | @@ -3,7 +3,8 @@ | ||
| 14246 | |||
| 14247 | /* { dg-do assemble } */ | ||
| 14248 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14249 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14250 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14251 | +/* { dg-add-options arm_neon } */ | ||
| 14252 | |||
| 14253 | #include "arm_neon.h" | ||
| 14254 | |||
| 14255 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c | ||
| 14256 | =================================================================== | ||
| 14257 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c | ||
| 14258 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c | ||
| 14259 | @@ -3,7 +3,8 @@ | ||
| 14260 | |||
| 14261 | /* { dg-do assemble } */ | ||
| 14262 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14263 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14264 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14265 | +/* { dg-add-options arm_neon } */ | ||
| 14266 | |||
| 14267 | #include "arm_neon.h" | ||
| 14268 | |||
| 14269 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c | ||
| 14270 | =================================================================== | ||
| 14271 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c | ||
| 14272 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c | ||
| 14273 | @@ -3,7 +3,8 @@ | ||
| 14274 | |||
| 14275 | /* { dg-do assemble } */ | ||
| 14276 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14277 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14278 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14279 | +/* { dg-add-options arm_neon } */ | ||
| 14280 | |||
| 14281 | #include "arm_neon.h" | ||
| 14282 | |||
| 14283 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c | ||
| 14284 | =================================================================== | ||
| 14285 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c | ||
| 14286 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c | ||
| 14287 | @@ -3,7 +3,8 @@ | ||
| 14288 | |||
| 14289 | /* { dg-do assemble } */ | ||
| 14290 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14291 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14292 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14293 | +/* { dg-add-options arm_neon } */ | ||
| 14294 | |||
| 14295 | #include "arm_neon.h" | ||
| 14296 | |||
| 14297 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c | ||
| 14298 | =================================================================== | ||
| 14299 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c | ||
| 14300 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c | ||
| 14301 | @@ -3,7 +3,8 @@ | ||
| 14302 | |||
| 14303 | /* { dg-do assemble } */ | ||
| 14304 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14305 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14306 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14307 | +/* { dg-add-options arm_neon } */ | ||
| 14308 | |||
| 14309 | #include "arm_neon.h" | ||
| 14310 | |||
| 14311 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c | ||
| 14312 | =================================================================== | ||
| 14313 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c | ||
| 14314 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c | ||
| 14315 | @@ -3,7 +3,8 @@ | ||
| 14316 | |||
| 14317 | /* { dg-do assemble } */ | ||
| 14318 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14319 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14320 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14321 | +/* { dg-add-options arm_neon } */ | ||
| 14322 | |||
| 14323 | #include "arm_neon.h" | ||
| 14324 | |||
| 14325 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadds16.c | ||
| 14326 | =================================================================== | ||
| 14327 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadds16.c | ||
| 14328 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadds16.c | ||
| 14329 | @@ -3,7 +3,8 @@ | ||
| 14330 | |||
| 14331 | /* { dg-do assemble } */ | ||
| 14332 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14333 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14334 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14335 | +/* { dg-add-options arm_neon } */ | ||
| 14336 | |||
| 14337 | #include "arm_neon.h" | ||
| 14338 | |||
| 14339 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadds32.c | ||
| 14340 | =================================================================== | ||
| 14341 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadds32.c | ||
| 14342 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadds32.c | ||
| 14343 | @@ -3,7 +3,8 @@ | ||
| 14344 | |||
| 14345 | /* { dg-do assemble } */ | ||
| 14346 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14347 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14348 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14349 | +/* { dg-add-options arm_neon } */ | ||
| 14350 | |||
| 14351 | #include "arm_neon.h" | ||
| 14352 | |||
| 14353 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadds8.c | ||
| 14354 | =================================================================== | ||
| 14355 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpadds8.c | ||
| 14356 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpadds8.c | ||
| 14357 | @@ -3,7 +3,8 @@ | ||
| 14358 | |||
| 14359 | /* { dg-do assemble } */ | ||
| 14360 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14361 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14362 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14363 | +/* { dg-add-options arm_neon } */ | ||
| 14364 | |||
| 14365 | #include "arm_neon.h" | ||
| 14366 | |||
| 14367 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c | ||
| 14368 | =================================================================== | ||
| 14369 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c | ||
| 14370 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c | ||
| 14371 | @@ -3,7 +3,8 @@ | ||
| 14372 | |||
| 14373 | /* { dg-do assemble } */ | ||
| 14374 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14375 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14376 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14377 | +/* { dg-add-options arm_neon } */ | ||
| 14378 | |||
| 14379 | #include "arm_neon.h" | ||
| 14380 | |||
| 14381 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c | ||
| 14382 | =================================================================== | ||
| 14383 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c | ||
| 14384 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c | ||
| 14385 | @@ -3,7 +3,8 @@ | ||
| 14386 | |||
| 14387 | /* { dg-do assemble } */ | ||
| 14388 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14389 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14390 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14391 | +/* { dg-add-options arm_neon } */ | ||
| 14392 | |||
| 14393 | #include "arm_neon.h" | ||
| 14394 | |||
| 14395 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c | ||
| 14396 | =================================================================== | ||
| 14397 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c | ||
| 14398 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c | ||
| 14399 | @@ -3,7 +3,8 @@ | ||
| 14400 | |||
| 14401 | /* { dg-do assemble } */ | ||
| 14402 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14403 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14404 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14405 | +/* { dg-add-options arm_neon } */ | ||
| 14406 | |||
| 14407 | #include "arm_neon.h" | ||
| 14408 | |||
| 14409 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c | ||
| 14410 | =================================================================== | ||
| 14411 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c | ||
| 14412 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c | ||
| 14413 | @@ -3,7 +3,8 @@ | ||
| 14414 | |||
| 14415 | /* { dg-do assemble } */ | ||
| 14416 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14417 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14418 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14419 | +/* { dg-add-options arm_neon } */ | ||
| 14420 | |||
| 14421 | #include "arm_neon.h" | ||
| 14422 | |||
| 14423 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c | ||
| 14424 | =================================================================== | ||
| 14425 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c | ||
| 14426 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c | ||
| 14427 | @@ -3,7 +3,8 @@ | ||
| 14428 | |||
| 14429 | /* { dg-do assemble } */ | ||
| 14430 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14431 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14432 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14433 | +/* { dg-add-options arm_neon } */ | ||
| 14434 | |||
| 14435 | #include "arm_neon.h" | ||
| 14436 | |||
| 14437 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c | ||
| 14438 | =================================================================== | ||
| 14439 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c | ||
| 14440 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c | ||
| 14441 | @@ -3,7 +3,8 @@ | ||
| 14442 | |||
| 14443 | /* { dg-do assemble } */ | ||
| 14444 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14445 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14446 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14447 | +/* { dg-add-options arm_neon } */ | ||
| 14448 | |||
| 14449 | #include "arm_neon.h" | ||
| 14450 | |||
| 14451 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c | ||
| 14452 | =================================================================== | ||
| 14453 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c | ||
| 14454 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c | ||
| 14455 | @@ -3,7 +3,8 @@ | ||
| 14456 | |||
| 14457 | /* { dg-do assemble } */ | ||
| 14458 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14459 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14460 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14461 | +/* { dg-add-options arm_neon } */ | ||
| 14462 | |||
| 14463 | #include "arm_neon.h" | ||
| 14464 | |||
| 14465 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c | ||
| 14466 | =================================================================== | ||
| 14467 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c | ||
| 14468 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c | ||
| 14469 | @@ -3,7 +3,8 @@ | ||
| 14470 | |||
| 14471 | /* { dg-do assemble } */ | ||
| 14472 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14473 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14474 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14475 | +/* { dg-add-options arm_neon } */ | ||
| 14476 | |||
| 14477 | #include "arm_neon.h" | ||
| 14478 | |||
| 14479 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c | ||
| 14480 | =================================================================== | ||
| 14481 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c | ||
| 14482 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c | ||
| 14483 | @@ -3,7 +3,8 @@ | ||
| 14484 | |||
| 14485 | /* { dg-do assemble } */ | ||
| 14486 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14487 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14488 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14489 | +/* { dg-add-options arm_neon } */ | ||
| 14490 | |||
| 14491 | #include "arm_neon.h" | ||
| 14492 | |||
| 14493 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c | ||
| 14494 | =================================================================== | ||
| 14495 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c | ||
| 14496 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c | ||
| 14497 | @@ -3,7 +3,8 @@ | ||
| 14498 | |||
| 14499 | /* { dg-do assemble } */ | ||
| 14500 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14501 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14502 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14503 | +/* { dg-add-options arm_neon } */ | ||
| 14504 | |||
| 14505 | #include "arm_neon.h" | ||
| 14506 | |||
| 14507 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminf32.c | ||
| 14508 | =================================================================== | ||
| 14509 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpminf32.c | ||
| 14510 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminf32.c | ||
| 14511 | @@ -3,7 +3,8 @@ | ||
| 14512 | |||
| 14513 | /* { dg-do assemble } */ | ||
| 14514 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14515 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14516 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14517 | +/* { dg-add-options arm_neon } */ | ||
| 14518 | |||
| 14519 | #include "arm_neon.h" | ||
| 14520 | |||
| 14521 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmins16.c | ||
| 14522 | =================================================================== | ||
| 14523 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmins16.c | ||
| 14524 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmins16.c | ||
| 14525 | @@ -3,7 +3,8 @@ | ||
| 14526 | |||
| 14527 | /* { dg-do assemble } */ | ||
| 14528 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14529 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14530 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14531 | +/* { dg-add-options arm_neon } */ | ||
| 14532 | |||
| 14533 | #include "arm_neon.h" | ||
| 14534 | |||
| 14535 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmins32.c | ||
| 14536 | =================================================================== | ||
| 14537 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmins32.c | ||
| 14538 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmins32.c | ||
| 14539 | @@ -3,7 +3,8 @@ | ||
| 14540 | |||
| 14541 | /* { dg-do assemble } */ | ||
| 14542 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14543 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14544 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14545 | +/* { dg-add-options arm_neon } */ | ||
| 14546 | |||
| 14547 | #include "arm_neon.h" | ||
| 14548 | |||
| 14549 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmins8.c | ||
| 14550 | =================================================================== | ||
| 14551 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpmins8.c | ||
| 14552 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpmins8.c | ||
| 14553 | @@ -3,7 +3,8 @@ | ||
| 14554 | |||
| 14555 | /* { dg-do assemble } */ | ||
| 14556 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14557 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14558 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14559 | +/* { dg-add-options arm_neon } */ | ||
| 14560 | |||
| 14561 | #include "arm_neon.h" | ||
| 14562 | |||
| 14563 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminu16.c | ||
| 14564 | =================================================================== | ||
| 14565 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpminu16.c | ||
| 14566 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminu16.c | ||
| 14567 | @@ -3,7 +3,8 @@ | ||
| 14568 | |||
| 14569 | /* { dg-do assemble } */ | ||
| 14570 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14571 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14572 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14573 | +/* { dg-add-options arm_neon } */ | ||
| 14574 | |||
| 14575 | #include "arm_neon.h" | ||
| 14576 | |||
| 14577 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminu32.c | ||
| 14578 | =================================================================== | ||
| 14579 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpminu32.c | ||
| 14580 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminu32.c | ||
| 14581 | @@ -3,7 +3,8 @@ | ||
| 14582 | |||
| 14583 | /* { dg-do assemble } */ | ||
| 14584 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14585 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14586 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14587 | +/* { dg-add-options arm_neon } */ | ||
| 14588 | |||
| 14589 | #include "arm_neon.h" | ||
| 14590 | |||
| 14591 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminu8.c | ||
| 14592 | =================================================================== | ||
| 14593 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vpminu8.c | ||
| 14594 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vpminu8.c | ||
| 14595 | @@ -3,7 +3,8 @@ | ||
| 14596 | |||
| 14597 | /* { dg-do assemble } */ | ||
| 14598 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14599 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14600 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14601 | +/* { dg-add-options arm_neon } */ | ||
| 14602 | |||
| 14603 | #include "arm_neon.h" | ||
| 14604 | |||
| 14605 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c | ||
| 14606 | =================================================================== | ||
| 14607 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c | ||
| 14608 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c | ||
| 14609 | @@ -3,7 +3,8 @@ | ||
| 14610 | |||
| 14611 | /* { dg-do assemble } */ | ||
| 14612 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14613 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14614 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14615 | +/* { dg-add-options arm_neon } */ | ||
| 14616 | |||
| 14617 | #include "arm_neon.h" | ||
| 14618 | |||
| 14619 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c | ||
| 14620 | =================================================================== | ||
| 14621 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c | ||
| 14622 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c | ||
| 14623 | @@ -3,7 +3,8 @@ | ||
| 14624 | |||
| 14625 | /* { dg-do assemble } */ | ||
| 14626 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14627 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14628 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14629 | +/* { dg-add-options arm_neon } */ | ||
| 14630 | |||
| 14631 | #include "arm_neon.h" | ||
| 14632 | |||
| 14633 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c | ||
| 14634 | =================================================================== | ||
| 14635 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c | ||
| 14636 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c | ||
| 14637 | @@ -3,7 +3,8 @@ | ||
| 14638 | |||
| 14639 | /* { dg-do assemble } */ | ||
| 14640 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14641 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14642 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14643 | +/* { dg-add-options arm_neon } */ | ||
| 14644 | |||
| 14645 | #include "arm_neon.h" | ||
| 14646 | |||
| 14647 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c | ||
| 14648 | =================================================================== | ||
| 14649 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c | ||
| 14650 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c | ||
| 14651 | @@ -3,7 +3,8 @@ | ||
| 14652 | |||
| 14653 | /* { dg-do assemble } */ | ||
| 14654 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14655 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14656 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14657 | +/* { dg-add-options arm_neon } */ | ||
| 14658 | |||
| 14659 | #include "arm_neon.h" | ||
| 14660 | |||
| 14661 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c | ||
| 14662 | =================================================================== | ||
| 14663 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c | ||
| 14664 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c | ||
| 14665 | @@ -3,7 +3,8 @@ | ||
| 14666 | |||
| 14667 | /* { dg-do assemble } */ | ||
| 14668 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14669 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14670 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14671 | +/* { dg-add-options arm_neon } */ | ||
| 14672 | |||
| 14673 | #include "arm_neon.h" | ||
| 14674 | |||
| 14675 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c | ||
| 14676 | =================================================================== | ||
| 14677 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c | ||
| 14678 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c | ||
| 14679 | @@ -3,7 +3,8 @@ | ||
| 14680 | |||
| 14681 | /* { dg-do assemble } */ | ||
| 14682 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14683 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14684 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14685 | +/* { dg-add-options arm_neon } */ | ||
| 14686 | |||
| 14687 | #include "arm_neon.h" | ||
| 14688 | |||
| 14689 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c | ||
| 14690 | =================================================================== | ||
| 14691 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c | ||
| 14692 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c | ||
| 14693 | @@ -3,7 +3,8 @@ | ||
| 14694 | |||
| 14695 | /* { dg-do assemble } */ | ||
| 14696 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14697 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14698 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14699 | +/* { dg-add-options arm_neon } */ | ||
| 14700 | |||
| 14701 | #include "arm_neon.h" | ||
| 14702 | |||
| 14703 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c | ||
| 14704 | =================================================================== | ||
| 14705 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c | ||
| 14706 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c | ||
| 14707 | @@ -3,7 +3,8 @@ | ||
| 14708 | |||
| 14709 | /* { dg-do assemble } */ | ||
| 14710 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14711 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14712 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14713 | +/* { dg-add-options arm_neon } */ | ||
| 14714 | |||
| 14715 | #include "arm_neon.h" | ||
| 14716 | |||
| 14717 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c | ||
| 14718 | =================================================================== | ||
| 14719 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c | ||
| 14720 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c | ||
| 14721 | @@ -3,7 +3,8 @@ | ||
| 14722 | |||
| 14723 | /* { dg-do assemble } */ | ||
| 14724 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14725 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14726 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14727 | +/* { dg-add-options arm_neon } */ | ||
| 14728 | |||
| 14729 | #include "arm_neon.h" | ||
| 14730 | |||
| 14731 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c | ||
| 14732 | =================================================================== | ||
| 14733 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c | ||
| 14734 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c | ||
| 14735 | @@ -3,7 +3,8 @@ | ||
| 14736 | |||
| 14737 | /* { dg-do assemble } */ | ||
| 14738 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14739 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14740 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14741 | +/* { dg-add-options arm_neon } */ | ||
| 14742 | |||
| 14743 | #include "arm_neon.h" | ||
| 14744 | |||
| 14745 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c | ||
| 14746 | =================================================================== | ||
| 14747 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c | ||
| 14748 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c | ||
| 14749 | @@ -3,7 +3,8 @@ | ||
| 14750 | |||
| 14751 | /* { dg-do assemble } */ | ||
| 14752 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14753 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14754 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14755 | +/* { dg-add-options arm_neon } */ | ||
| 14756 | |||
| 14757 | #include "arm_neon.h" | ||
| 14758 | |||
| 14759 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c | ||
| 14760 | =================================================================== | ||
| 14761 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c | ||
| 14762 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c | ||
| 14763 | @@ -3,7 +3,8 @@ | ||
| 14764 | |||
| 14765 | /* { dg-do assemble } */ | ||
| 14766 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14767 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14768 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14769 | +/* { dg-add-options arm_neon } */ | ||
| 14770 | |||
| 14771 | #include "arm_neon.h" | ||
| 14772 | |||
| 14773 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c | ||
| 14774 | =================================================================== | ||
| 14775 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c | ||
| 14776 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c | ||
| 14777 | @@ -3,7 +3,8 @@ | ||
| 14778 | |||
| 14779 | /* { dg-do assemble } */ | ||
| 14780 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14781 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14782 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14783 | +/* { dg-add-options arm_neon } */ | ||
| 14784 | |||
| 14785 | #include "arm_neon.h" | ||
| 14786 | |||
| 14787 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c | ||
| 14788 | =================================================================== | ||
| 14789 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c | ||
| 14790 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c | ||
| 14791 | @@ -3,7 +3,8 @@ | ||
| 14792 | |||
| 14793 | /* { dg-do assemble } */ | ||
| 14794 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14795 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14796 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14797 | +/* { dg-add-options arm_neon } */ | ||
| 14798 | |||
| 14799 | #include "arm_neon.h" | ||
| 14800 | |||
| 14801 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c | ||
| 14802 | =================================================================== | ||
| 14803 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c | ||
| 14804 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c | ||
| 14805 | @@ -3,7 +3,8 @@ | ||
| 14806 | |||
| 14807 | /* { dg-do assemble } */ | ||
| 14808 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14809 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14810 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14811 | +/* { dg-add-options arm_neon } */ | ||
| 14812 | |||
| 14813 | #include "arm_neon.h" | ||
| 14814 | |||
| 14815 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c | ||
| 14816 | =================================================================== | ||
| 14817 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c | ||
| 14818 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c | ||
| 14819 | @@ -3,7 +3,8 @@ | ||
| 14820 | |||
| 14821 | /* { dg-do assemble } */ | ||
| 14822 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14823 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14824 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14825 | +/* { dg-add-options arm_neon } */ | ||
| 14826 | |||
| 14827 | #include "arm_neon.h" | ||
| 14828 | |||
| 14829 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c | ||
| 14830 | =================================================================== | ||
| 14831 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c | ||
| 14832 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c | ||
| 14833 | @@ -3,7 +3,8 @@ | ||
| 14834 | |||
| 14835 | /* { dg-do assemble } */ | ||
| 14836 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14837 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14838 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14839 | +/* { dg-add-options arm_neon } */ | ||
| 14840 | |||
| 14841 | #include "arm_neon.h" | ||
| 14842 | |||
| 14843 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c | ||
| 14844 | =================================================================== | ||
| 14845 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c | ||
| 14846 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c | ||
| 14847 | @@ -3,7 +3,8 @@ | ||
| 14848 | |||
| 14849 | /* { dg-do assemble } */ | ||
| 14850 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14851 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14852 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14853 | +/* { dg-add-options arm_neon } */ | ||
| 14854 | |||
| 14855 | #include "arm_neon.h" | ||
| 14856 | |||
| 14857 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c | ||
| 14858 | =================================================================== | ||
| 14859 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c | ||
| 14860 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c | ||
| 14861 | @@ -3,7 +3,8 @@ | ||
| 14862 | |||
| 14863 | /* { dg-do assemble } */ | ||
| 14864 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14865 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14866 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14867 | +/* { dg-add-options arm_neon } */ | ||
| 14868 | |||
| 14869 | #include "arm_neon.h" | ||
| 14870 | |||
| 14871 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c | ||
| 14872 | =================================================================== | ||
| 14873 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c | ||
| 14874 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c | ||
| 14875 | @@ -3,7 +3,8 @@ | ||
| 14876 | |||
| 14877 | /* { dg-do assemble } */ | ||
| 14878 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14879 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14880 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14881 | +/* { dg-add-options arm_neon } */ | ||
| 14882 | |||
| 14883 | #include "arm_neon.h" | ||
| 14884 | |||
| 14885 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c | ||
| 14886 | =================================================================== | ||
| 14887 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c | ||
| 14888 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c | ||
| 14889 | @@ -3,7 +3,8 @@ | ||
| 14890 | |||
| 14891 | /* { dg-do assemble } */ | ||
| 14892 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14893 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14894 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14895 | +/* { dg-add-options arm_neon } */ | ||
| 14896 | |||
| 14897 | #include "arm_neon.h" | ||
| 14898 | |||
| 14899 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c | ||
| 14900 | =================================================================== | ||
| 14901 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c | ||
| 14902 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c | ||
| 14903 | @@ -3,7 +3,8 @@ | ||
| 14904 | |||
| 14905 | /* { dg-do assemble } */ | ||
| 14906 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14907 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14908 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14909 | +/* { dg-add-options arm_neon } */ | ||
| 14910 | |||
| 14911 | #include "arm_neon.h" | ||
| 14912 | |||
| 14913 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c | ||
| 14914 | =================================================================== | ||
| 14915 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c | ||
| 14916 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c | ||
| 14917 | @@ -3,7 +3,8 @@ | ||
| 14918 | |||
| 14919 | /* { dg-do assemble } */ | ||
| 14920 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14921 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14922 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14923 | +/* { dg-add-options arm_neon } */ | ||
| 14924 | |||
| 14925 | #include "arm_neon.h" | ||
| 14926 | |||
| 14927 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c | ||
| 14928 | =================================================================== | ||
| 14929 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c | ||
| 14930 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c | ||
| 14931 | @@ -3,7 +3,8 @@ | ||
| 14932 | |||
| 14933 | /* { dg-do assemble } */ | ||
| 14934 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14935 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14936 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14937 | +/* { dg-add-options arm_neon } */ | ||
| 14938 | |||
| 14939 | #include "arm_neon.h" | ||
| 14940 | |||
| 14941 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c | ||
| 14942 | =================================================================== | ||
| 14943 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c | ||
| 14944 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c | ||
| 14945 | @@ -3,7 +3,8 @@ | ||
| 14946 | |||
| 14947 | /* { dg-do assemble } */ | ||
| 14948 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14949 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14950 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14951 | +/* { dg-add-options arm_neon } */ | ||
| 14952 | |||
| 14953 | #include "arm_neon.h" | ||
| 14954 | |||
| 14955 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c | ||
| 14956 | =================================================================== | ||
| 14957 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c | ||
| 14958 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c | ||
| 14959 | @@ -3,7 +3,8 @@ | ||
| 14960 | |||
| 14961 | /* { dg-do assemble } */ | ||
| 14962 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14963 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14964 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14965 | +/* { dg-add-options arm_neon } */ | ||
| 14966 | |||
| 14967 | #include "arm_neon.h" | ||
| 14968 | |||
| 14969 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c | ||
| 14970 | =================================================================== | ||
| 14971 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c | ||
| 14972 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c | ||
| 14973 | @@ -3,7 +3,8 @@ | ||
| 14974 | |||
| 14975 | /* { dg-do assemble } */ | ||
| 14976 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14977 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14978 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14979 | +/* { dg-add-options arm_neon } */ | ||
| 14980 | |||
| 14981 | #include "arm_neon.h" | ||
| 14982 | |||
| 14983 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c | ||
| 14984 | =================================================================== | ||
| 14985 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c | ||
| 14986 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c | ||
| 14987 | @@ -3,7 +3,8 @@ | ||
| 14988 | |||
| 14989 | /* { dg-do assemble } */ | ||
| 14990 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 14991 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 14992 | +/* { dg-options "-save-temps -O0" } */ | ||
| 14993 | +/* { dg-add-options arm_neon } */ | ||
| 14994 | |||
| 14995 | #include "arm_neon.h" | ||
| 14996 | |||
| 14997 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c | ||
| 14998 | =================================================================== | ||
| 14999 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c | ||
| 15000 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c | ||
| 15001 | @@ -3,7 +3,8 @@ | ||
| 15002 | |||
| 15003 | /* { dg-do assemble } */ | ||
| 15004 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15005 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15006 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15007 | +/* { dg-add-options arm_neon } */ | ||
| 15008 | |||
| 15009 | #include "arm_neon.h" | ||
| 15010 | |||
| 15011 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c | ||
| 15012 | =================================================================== | ||
| 15013 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c | ||
| 15014 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c | ||
| 15015 | @@ -3,7 +3,8 @@ | ||
| 15016 | |||
| 15017 | /* { dg-do assemble } */ | ||
| 15018 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15019 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15020 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15021 | +/* { dg-add-options arm_neon } */ | ||
| 15022 | |||
| 15023 | #include "arm_neon.h" | ||
| 15024 | |||
| 15025 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c | ||
| 15026 | =================================================================== | ||
| 15027 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c | ||
| 15028 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c | ||
| 15029 | @@ -3,7 +3,8 @@ | ||
| 15030 | |||
| 15031 | /* { dg-do assemble } */ | ||
| 15032 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15033 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15034 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15035 | +/* { dg-add-options arm_neon } */ | ||
| 15036 | |||
| 15037 | #include "arm_neon.h" | ||
| 15038 | |||
| 15039 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c | ||
| 15040 | =================================================================== | ||
| 15041 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c | ||
| 15042 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c | ||
| 15043 | @@ -3,7 +3,8 @@ | ||
| 15044 | |||
| 15045 | /* { dg-do assemble } */ | ||
| 15046 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15047 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15048 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15049 | +/* { dg-add-options arm_neon } */ | ||
| 15050 | |||
| 15051 | #include "arm_neon.h" | ||
| 15052 | |||
| 15053 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c | ||
| 15054 | =================================================================== | ||
| 15055 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c | ||
| 15056 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c | ||
| 15057 | @@ -3,7 +3,8 @@ | ||
| 15058 | |||
| 15059 | /* { dg-do assemble } */ | ||
| 15060 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15061 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15062 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15063 | +/* { dg-add-options arm_neon } */ | ||
| 15064 | |||
| 15065 | #include "arm_neon.h" | ||
| 15066 | |||
| 15067 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c | ||
| 15068 | =================================================================== | ||
| 15069 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c | ||
| 15070 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c | ||
| 15071 | @@ -3,7 +3,8 @@ | ||
| 15072 | |||
| 15073 | /* { dg-do assemble } */ | ||
| 15074 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15075 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15076 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15077 | +/* { dg-add-options arm_neon } */ | ||
| 15078 | |||
| 15079 | #include "arm_neon.h" | ||
| 15080 | |||
| 15081 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c | ||
| 15082 | =================================================================== | ||
| 15083 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c | ||
| 15084 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c | ||
| 15085 | @@ -3,7 +3,8 @@ | ||
| 15086 | |||
| 15087 | /* { dg-do assemble } */ | ||
| 15088 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15089 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15090 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15091 | +/* { dg-add-options arm_neon } */ | ||
| 15092 | |||
| 15093 | #include "arm_neon.h" | ||
| 15094 | |||
| 15095 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c | ||
| 15096 | =================================================================== | ||
| 15097 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c | ||
| 15098 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c | ||
| 15099 | @@ -3,7 +3,8 @@ | ||
| 15100 | |||
| 15101 | /* { dg-do assemble } */ | ||
| 15102 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15103 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15104 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15105 | +/* { dg-add-options arm_neon } */ | ||
| 15106 | |||
| 15107 | #include "arm_neon.h" | ||
| 15108 | |||
| 15109 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c | ||
| 15110 | =================================================================== | ||
| 15111 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c | ||
| 15112 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c | ||
| 15113 | @@ -3,7 +3,8 @@ | ||
| 15114 | |||
| 15115 | /* { dg-do assemble } */ | ||
| 15116 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15117 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15118 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15119 | +/* { dg-add-options arm_neon } */ | ||
| 15120 | |||
| 15121 | #include "arm_neon.h" | ||
| 15122 | |||
| 15123 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c | ||
| 15124 | =================================================================== | ||
| 15125 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c | ||
| 15126 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c | ||
| 15127 | @@ -3,7 +3,8 @@ | ||
| 15128 | |||
| 15129 | /* { dg-do assemble } */ | ||
| 15130 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15131 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15132 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15133 | +/* { dg-add-options arm_neon } */ | ||
| 15134 | |||
| 15135 | #include "arm_neon.h" | ||
| 15136 | |||
| 15137 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c | ||
| 15138 | =================================================================== | ||
| 15139 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c | ||
| 15140 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c | ||
| 15141 | @@ -3,7 +3,8 @@ | ||
| 15142 | |||
| 15143 | /* { dg-do assemble } */ | ||
| 15144 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15145 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15146 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15147 | +/* { dg-add-options arm_neon } */ | ||
| 15148 | |||
| 15149 | #include "arm_neon.h" | ||
| 15150 | |||
| 15151 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c | ||
| 15152 | =================================================================== | ||
| 15153 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c | ||
| 15154 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c | ||
| 15155 | @@ -3,7 +3,8 @@ | ||
| 15156 | |||
| 15157 | /* { dg-do assemble } */ | ||
| 15158 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15159 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15160 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15161 | +/* { dg-add-options arm_neon } */ | ||
| 15162 | |||
| 15163 | #include "arm_neon.h" | ||
| 15164 | |||
| 15165 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabss16.c | ||
| 15166 | =================================================================== | ||
| 15167 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqabss16.c | ||
| 15168 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabss16.c | ||
| 15169 | @@ -3,7 +3,8 @@ | ||
| 15170 | |||
| 15171 | /* { dg-do assemble } */ | ||
| 15172 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15173 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15174 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15175 | +/* { dg-add-options arm_neon } */ | ||
| 15176 | |||
| 15177 | #include "arm_neon.h" | ||
| 15178 | |||
| 15179 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabss32.c | ||
| 15180 | =================================================================== | ||
| 15181 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqabss32.c | ||
| 15182 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabss32.c | ||
| 15183 | @@ -3,7 +3,8 @@ | ||
| 15184 | |||
| 15185 | /* { dg-do assemble } */ | ||
| 15186 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15187 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15188 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15189 | +/* { dg-add-options arm_neon } */ | ||
| 15190 | |||
| 15191 | #include "arm_neon.h" | ||
| 15192 | |||
| 15193 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabss8.c | ||
| 15194 | =================================================================== | ||
| 15195 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqabss8.c | ||
| 15196 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqabss8.c | ||
| 15197 | @@ -3,7 +3,8 @@ | ||
| 15198 | |||
| 15199 | /* { dg-do assemble } */ | ||
| 15200 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15201 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15202 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15203 | +/* { dg-add-options arm_neon } */ | ||
| 15204 | |||
| 15205 | #include "arm_neon.h" | ||
| 15206 | |||
| 15207 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c | ||
| 15208 | =================================================================== | ||
| 15209 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c | ||
| 15210 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c | ||
| 15211 | @@ -3,7 +3,8 @@ | ||
| 15212 | |||
| 15213 | /* { dg-do assemble } */ | ||
| 15214 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15215 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15216 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15217 | +/* { dg-add-options arm_neon } */ | ||
| 15218 | |||
| 15219 | #include "arm_neon.h" | ||
| 15220 | |||
| 15221 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c | ||
| 15222 | =================================================================== | ||
| 15223 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c | ||
| 15224 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c | ||
| 15225 | @@ -3,7 +3,8 @@ | ||
| 15226 | |||
| 15227 | /* { dg-do assemble } */ | ||
| 15228 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15229 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15230 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15231 | +/* { dg-add-options arm_neon } */ | ||
| 15232 | |||
| 15233 | #include "arm_neon.h" | ||
| 15234 | |||
| 15235 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c | ||
| 15236 | =================================================================== | ||
| 15237 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c | ||
| 15238 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c | ||
| 15239 | @@ -3,7 +3,8 @@ | ||
| 15240 | |||
| 15241 | /* { dg-do assemble } */ | ||
| 15242 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15243 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15244 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15245 | +/* { dg-add-options arm_neon } */ | ||
| 15246 | |||
| 15247 | #include "arm_neon.h" | ||
| 15248 | |||
| 15249 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c | ||
| 15250 | =================================================================== | ||
| 15251 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c | ||
| 15252 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c | ||
| 15253 | @@ -3,7 +3,8 @@ | ||
| 15254 | |||
| 15255 | /* { dg-do assemble } */ | ||
| 15256 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15257 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15258 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15259 | +/* { dg-add-options arm_neon } */ | ||
| 15260 | |||
| 15261 | #include "arm_neon.h" | ||
| 15262 | |||
| 15263 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c | ||
| 15264 | =================================================================== | ||
| 15265 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c | ||
| 15266 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c | ||
| 15267 | @@ -3,7 +3,8 @@ | ||
| 15268 | |||
| 15269 | /* { dg-do assemble } */ | ||
| 15270 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15271 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15272 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15273 | +/* { dg-add-options arm_neon } */ | ||
| 15274 | |||
| 15275 | #include "arm_neon.h" | ||
| 15276 | |||
| 15277 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c | ||
| 15278 | =================================================================== | ||
| 15279 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c | ||
| 15280 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c | ||
| 15281 | @@ -3,7 +3,8 @@ | ||
| 15282 | |||
| 15283 | /* { dg-do assemble } */ | ||
| 15284 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15285 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15286 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15287 | +/* { dg-add-options arm_neon } */ | ||
| 15288 | |||
| 15289 | #include "arm_neon.h" | ||
| 15290 | |||
| 15291 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c | ||
| 15292 | =================================================================== | ||
| 15293 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c | ||
| 15294 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c | ||
| 15295 | @@ -3,7 +3,8 @@ | ||
| 15296 | |||
| 15297 | /* { dg-do assemble } */ | ||
| 15298 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15299 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15300 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15301 | +/* { dg-add-options arm_neon } */ | ||
| 15302 | |||
| 15303 | #include "arm_neon.h" | ||
| 15304 | |||
| 15305 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c | ||
| 15306 | =================================================================== | ||
| 15307 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c | ||
| 15308 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c | ||
| 15309 | @@ -3,7 +3,8 @@ | ||
| 15310 | |||
| 15311 | /* { dg-do assemble } */ | ||
| 15312 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15313 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15314 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15315 | +/* { dg-add-options arm_neon } */ | ||
| 15316 | |||
| 15317 | #include "arm_neon.h" | ||
| 15318 | |||
| 15319 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds16.c | ||
| 15320 | =================================================================== | ||
| 15321 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqadds16.c | ||
| 15322 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds16.c | ||
| 15323 | @@ -3,7 +3,8 @@ | ||
| 15324 | |||
| 15325 | /* { dg-do assemble } */ | ||
| 15326 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15327 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15328 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15329 | +/* { dg-add-options arm_neon } */ | ||
| 15330 | |||
| 15331 | #include "arm_neon.h" | ||
| 15332 | |||
| 15333 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds32.c | ||
| 15334 | =================================================================== | ||
| 15335 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqadds32.c | ||
| 15336 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds32.c | ||
| 15337 | @@ -3,7 +3,8 @@ | ||
| 15338 | |||
| 15339 | /* { dg-do assemble } */ | ||
| 15340 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15341 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15342 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15343 | +/* { dg-add-options arm_neon } */ | ||
| 15344 | |||
| 15345 | #include "arm_neon.h" | ||
| 15346 | |||
| 15347 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds64.c | ||
| 15348 | =================================================================== | ||
| 15349 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqadds64.c | ||
| 15350 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds64.c | ||
| 15351 | @@ -3,7 +3,8 @@ | ||
| 15352 | |||
| 15353 | /* { dg-do assemble } */ | ||
| 15354 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15355 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15356 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15357 | +/* { dg-add-options arm_neon } */ | ||
| 15358 | |||
| 15359 | #include "arm_neon.h" | ||
| 15360 | |||
| 15361 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds8.c | ||
| 15362 | =================================================================== | ||
| 15363 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqadds8.c | ||
| 15364 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqadds8.c | ||
| 15365 | @@ -3,7 +3,8 @@ | ||
| 15366 | |||
| 15367 | /* { dg-do assemble } */ | ||
| 15368 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15369 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15370 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15371 | +/* { dg-add-options arm_neon } */ | ||
| 15372 | |||
| 15373 | #include "arm_neon.h" | ||
| 15374 | |||
| 15375 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c | ||
| 15376 | =================================================================== | ||
| 15377 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c | ||
| 15378 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c | ||
| 15379 | @@ -3,7 +3,8 @@ | ||
| 15380 | |||
| 15381 | /* { dg-do assemble } */ | ||
| 15382 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15383 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15384 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15385 | +/* { dg-add-options arm_neon } */ | ||
| 15386 | |||
| 15387 | #include "arm_neon.h" | ||
| 15388 | |||
| 15389 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c | ||
| 15390 | =================================================================== | ||
| 15391 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c | ||
| 15392 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c | ||
| 15393 | @@ -3,7 +3,8 @@ | ||
| 15394 | |||
| 15395 | /* { dg-do assemble } */ | ||
| 15396 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15397 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15398 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15399 | +/* { dg-add-options arm_neon } */ | ||
| 15400 | |||
| 15401 | #include "arm_neon.h" | ||
| 15402 | |||
| 15403 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c | ||
| 15404 | =================================================================== | ||
| 15405 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c | ||
| 15406 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c | ||
| 15407 | @@ -3,7 +3,8 @@ | ||
| 15408 | |||
| 15409 | /* { dg-do assemble } */ | ||
| 15410 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15411 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15412 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15413 | +/* { dg-add-options arm_neon } */ | ||
| 15414 | |||
| 15415 | #include "arm_neon.h" | ||
| 15416 | |||
| 15417 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c | ||
| 15418 | =================================================================== | ||
| 15419 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c | ||
| 15420 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c | ||
| 15421 | @@ -3,7 +3,8 @@ | ||
| 15422 | |||
| 15423 | /* { dg-do assemble } */ | ||
| 15424 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15425 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15426 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15427 | +/* { dg-add-options arm_neon } */ | ||
| 15428 | |||
| 15429 | #include "arm_neon.h" | ||
| 15430 | |||
| 15431 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c | ||
| 15432 | =================================================================== | ||
| 15433 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c | ||
| 15434 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c | ||
| 15435 | @@ -3,7 +3,8 @@ | ||
| 15436 | |||
| 15437 | /* { dg-do assemble } */ | ||
| 15438 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15439 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15440 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15441 | +/* { dg-add-options arm_neon } */ | ||
| 15442 | |||
| 15443 | #include "arm_neon.h" | ||
| 15444 | |||
| 15445 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c | ||
| 15446 | =================================================================== | ||
| 15447 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c | ||
| 15448 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c | ||
| 15449 | @@ -3,7 +3,8 @@ | ||
| 15450 | |||
| 15451 | /* { dg-do assemble } */ | ||
| 15452 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15453 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15454 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15455 | +/* { dg-add-options arm_neon } */ | ||
| 15456 | |||
| 15457 | #include "arm_neon.h" | ||
| 15458 | |||
| 15459 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c | ||
| 15460 | =================================================================== | ||
| 15461 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c | ||
| 15462 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c | ||
| 15463 | @@ -3,7 +3,8 @@ | ||
| 15464 | |||
| 15465 | /* { dg-do assemble } */ | ||
| 15466 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15467 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15468 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15469 | +/* { dg-add-options arm_neon } */ | ||
| 15470 | |||
| 15471 | #include "arm_neon.h" | ||
| 15472 | |||
| 15473 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c | ||
| 15474 | =================================================================== | ||
| 15475 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c | ||
| 15476 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c | ||
| 15477 | @@ -3,7 +3,8 @@ | ||
| 15478 | |||
| 15479 | /* { dg-do assemble } */ | ||
| 15480 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15481 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15482 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15483 | +/* { dg-add-options arm_neon } */ | ||
| 15484 | |||
| 15485 | #include "arm_neon.h" | ||
| 15486 | |||
| 15487 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c | ||
| 15488 | =================================================================== | ||
| 15489 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c | ||
| 15490 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c | ||
| 15491 | @@ -3,7 +3,8 @@ | ||
| 15492 | |||
| 15493 | /* { dg-do assemble } */ | ||
| 15494 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15495 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15496 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15497 | +/* { dg-add-options arm_neon } */ | ||
| 15498 | |||
| 15499 | #include "arm_neon.h" | ||
| 15500 | |||
| 15501 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c | ||
| 15502 | =================================================================== | ||
| 15503 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c | ||
| 15504 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c | ||
| 15505 | @@ -3,7 +3,8 @@ | ||
| 15506 | |||
| 15507 | /* { dg-do assemble } */ | ||
| 15508 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15509 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15510 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15511 | +/* { dg-add-options arm_neon } */ | ||
| 15512 | |||
| 15513 | #include "arm_neon.h" | ||
| 15514 | |||
| 15515 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c | ||
| 15516 | =================================================================== | ||
| 15517 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c | ||
| 15518 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c | ||
| 15519 | @@ -3,7 +3,8 @@ | ||
| 15520 | |||
| 15521 | /* { dg-do assemble } */ | ||
| 15522 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15523 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15524 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15525 | +/* { dg-add-options arm_neon } */ | ||
| 15526 | |||
| 15527 | #include "arm_neon.h" | ||
| 15528 | |||
| 15529 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c | ||
| 15530 | =================================================================== | ||
| 15531 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c | ||
| 15532 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c | ||
| 15533 | @@ -3,7 +3,8 @@ | ||
| 15534 | |||
| 15535 | /* { dg-do assemble } */ | ||
| 15536 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15537 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15538 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15539 | +/* { dg-add-options arm_neon } */ | ||
| 15540 | |||
| 15541 | #include "arm_neon.h" | ||
| 15542 | |||
| 15543 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c | ||
| 15544 | =================================================================== | ||
| 15545 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c | ||
| 15546 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c | ||
| 15547 | @@ -3,7 +3,8 @@ | ||
| 15548 | |||
| 15549 | /* { dg-do assemble } */ | ||
| 15550 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15551 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15552 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15553 | +/* { dg-add-options arm_neon } */ | ||
| 15554 | |||
| 15555 | #include "arm_neon.h" | ||
| 15556 | |||
| 15557 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c | ||
| 15558 | =================================================================== | ||
| 15559 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c | ||
| 15560 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c | ||
| 15561 | @@ -3,7 +3,8 @@ | ||
| 15562 | |||
| 15563 | /* { dg-do assemble } */ | ||
| 15564 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15565 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15566 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15567 | +/* { dg-add-options arm_neon } */ | ||
| 15568 | |||
| 15569 | #include "arm_neon.h" | ||
| 15570 | |||
| 15571 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c | ||
| 15572 | =================================================================== | ||
| 15573 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c | ||
| 15574 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c | ||
| 15575 | @@ -3,7 +3,8 @@ | ||
| 15576 | |||
| 15577 | /* { dg-do assemble } */ | ||
| 15578 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15579 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15580 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15581 | +/* { dg-add-options arm_neon } */ | ||
| 15582 | |||
| 15583 | #include "arm_neon.h" | ||
| 15584 | |||
| 15585 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c | ||
| 15586 | =================================================================== | ||
| 15587 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c | ||
| 15588 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c | ||
| 15589 | @@ -3,7 +3,8 @@ | ||
| 15590 | |||
| 15591 | /* { dg-do assemble } */ | ||
| 15592 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15593 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15594 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15595 | +/* { dg-add-options arm_neon } */ | ||
| 15596 | |||
| 15597 | #include "arm_neon.h" | ||
| 15598 | |||
| 15599 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c | ||
| 15600 | =================================================================== | ||
| 15601 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c | ||
| 15602 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c | ||
| 15603 | @@ -3,7 +3,8 @@ | ||
| 15604 | |||
| 15605 | /* { dg-do assemble } */ | ||
| 15606 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15607 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15608 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15609 | +/* { dg-add-options arm_neon } */ | ||
| 15610 | |||
| 15611 | #include "arm_neon.h" | ||
| 15612 | |||
| 15613 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c | ||
| 15614 | =================================================================== | ||
| 15615 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c | ||
| 15616 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c | ||
| 15617 | @@ -3,7 +3,8 @@ | ||
| 15618 | |||
| 15619 | /* { dg-do assemble } */ | ||
| 15620 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15621 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15622 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15623 | +/* { dg-add-options arm_neon } */ | ||
| 15624 | |||
| 15625 | #include "arm_neon.h" | ||
| 15626 | |||
| 15627 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c | ||
| 15628 | =================================================================== | ||
| 15629 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c | ||
| 15630 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c | ||
| 15631 | @@ -3,7 +3,8 @@ | ||
| 15632 | |||
| 15633 | /* { dg-do assemble } */ | ||
| 15634 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15635 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15636 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15637 | +/* { dg-add-options arm_neon } */ | ||
| 15638 | |||
| 15639 | #include "arm_neon.h" | ||
| 15640 | |||
| 15641 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c | ||
| 15642 | =================================================================== | ||
| 15643 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c | ||
| 15644 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c | ||
| 15645 | @@ -3,7 +3,8 @@ | ||
| 15646 | |||
| 15647 | /* { dg-do assemble } */ | ||
| 15648 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15649 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15650 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15651 | +/* { dg-add-options arm_neon } */ | ||
| 15652 | |||
| 15653 | #include "arm_neon.h" | ||
| 15654 | |||
| 15655 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c | ||
| 15656 | =================================================================== | ||
| 15657 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c | ||
| 15658 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c | ||
| 15659 | @@ -3,7 +3,8 @@ | ||
| 15660 | |||
| 15661 | /* { dg-do assemble } */ | ||
| 15662 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15663 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15664 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15665 | +/* { dg-add-options arm_neon } */ | ||
| 15666 | |||
| 15667 | #include "arm_neon.h" | ||
| 15668 | |||
| 15669 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c | ||
| 15670 | =================================================================== | ||
| 15671 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c | ||
| 15672 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c | ||
| 15673 | @@ -3,7 +3,8 @@ | ||
| 15674 | |||
| 15675 | /* { dg-do assemble } */ | ||
| 15676 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15677 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15678 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15679 | +/* { dg-add-options arm_neon } */ | ||
| 15680 | |||
| 15681 | #include "arm_neon.h" | ||
| 15682 | |||
| 15683 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c | ||
| 15684 | =================================================================== | ||
| 15685 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c | ||
| 15686 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c | ||
| 15687 | @@ -3,7 +3,8 @@ | ||
| 15688 | |||
| 15689 | /* { dg-do assemble } */ | ||
| 15690 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15691 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15692 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15693 | +/* { dg-add-options arm_neon } */ | ||
| 15694 | |||
| 15695 | #include "arm_neon.h" | ||
| 15696 | |||
| 15697 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c | ||
| 15698 | =================================================================== | ||
| 15699 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c | ||
| 15700 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c | ||
| 15701 | @@ -3,7 +3,8 @@ | ||
| 15702 | |||
| 15703 | /* { dg-do assemble } */ | ||
| 15704 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15705 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15706 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15707 | +/* { dg-add-options arm_neon } */ | ||
| 15708 | |||
| 15709 | #include "arm_neon.h" | ||
| 15710 | |||
| 15711 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c | ||
| 15712 | =================================================================== | ||
| 15713 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c | ||
| 15714 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c | ||
| 15715 | @@ -3,7 +3,8 @@ | ||
| 15716 | |||
| 15717 | /* { dg-do assemble } */ | ||
| 15718 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15719 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15720 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15721 | +/* { dg-add-options arm_neon } */ | ||
| 15722 | |||
| 15723 | #include "arm_neon.h" | ||
| 15724 | |||
| 15725 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c | ||
| 15726 | =================================================================== | ||
| 15727 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c | ||
| 15728 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c | ||
| 15729 | @@ -3,7 +3,8 @@ | ||
| 15730 | |||
| 15731 | /* { dg-do assemble } */ | ||
| 15732 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15733 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15734 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15735 | +/* { dg-add-options arm_neon } */ | ||
| 15736 | |||
| 15737 | #include "arm_neon.h" | ||
| 15738 | |||
| 15739 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c | ||
| 15740 | =================================================================== | ||
| 15741 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c | ||
| 15742 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c | ||
| 15743 | @@ -3,7 +3,8 @@ | ||
| 15744 | |||
| 15745 | /* { dg-do assemble } */ | ||
| 15746 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15747 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15748 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15749 | +/* { dg-add-options arm_neon } */ | ||
| 15750 | |||
| 15751 | #include "arm_neon.h" | ||
| 15752 | |||
| 15753 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c | ||
| 15754 | =================================================================== | ||
| 15755 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c | ||
| 15756 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c | ||
| 15757 | @@ -3,7 +3,8 @@ | ||
| 15758 | |||
| 15759 | /* { dg-do assemble } */ | ||
| 15760 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15761 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15762 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15763 | +/* { dg-add-options arm_neon } */ | ||
| 15764 | |||
| 15765 | #include "arm_neon.h" | ||
| 15766 | |||
| 15767 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c | ||
| 15768 | =================================================================== | ||
| 15769 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c | ||
| 15770 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c | ||
| 15771 | @@ -3,7 +3,8 @@ | ||
| 15772 | |||
| 15773 | /* { dg-do assemble } */ | ||
| 15774 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15775 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15776 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15777 | +/* { dg-add-options arm_neon } */ | ||
| 15778 | |||
| 15779 | #include "arm_neon.h" | ||
| 15780 | |||
| 15781 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c | ||
| 15782 | =================================================================== | ||
| 15783 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c | ||
| 15784 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c | ||
| 15785 | @@ -3,7 +3,8 @@ | ||
| 15786 | |||
| 15787 | /* { dg-do assemble } */ | ||
| 15788 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15789 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15790 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15791 | +/* { dg-add-options arm_neon } */ | ||
| 15792 | |||
| 15793 | #include "arm_neon.h" | ||
| 15794 | |||
| 15795 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c | ||
| 15796 | =================================================================== | ||
| 15797 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c | ||
| 15798 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c | ||
| 15799 | @@ -3,7 +3,8 @@ | ||
| 15800 | |||
| 15801 | /* { dg-do assemble } */ | ||
| 15802 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15803 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15804 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15805 | +/* { dg-add-options arm_neon } */ | ||
| 15806 | |||
| 15807 | #include "arm_neon.h" | ||
| 15808 | |||
| 15809 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c | ||
| 15810 | =================================================================== | ||
| 15811 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c | ||
| 15812 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c | ||
| 15813 | @@ -3,7 +3,8 @@ | ||
| 15814 | |||
| 15815 | /* { dg-do assemble } */ | ||
| 15816 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15817 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15818 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15819 | +/* { dg-add-options arm_neon } */ | ||
| 15820 | |||
| 15821 | #include "arm_neon.h" | ||
| 15822 | |||
| 15823 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c | ||
| 15824 | =================================================================== | ||
| 15825 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c | ||
| 15826 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c | ||
| 15827 | @@ -3,7 +3,8 @@ | ||
| 15828 | |||
| 15829 | /* { dg-do assemble } */ | ||
| 15830 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15831 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15832 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15833 | +/* { dg-add-options arm_neon } */ | ||
| 15834 | |||
| 15835 | #include "arm_neon.h" | ||
| 15836 | |||
| 15837 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c | ||
| 15838 | =================================================================== | ||
| 15839 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c | ||
| 15840 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c | ||
| 15841 | @@ -3,7 +3,8 @@ | ||
| 15842 | |||
| 15843 | /* { dg-do assemble } */ | ||
| 15844 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15845 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15846 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15847 | +/* { dg-add-options arm_neon } */ | ||
| 15848 | |||
| 15849 | #include "arm_neon.h" | ||
| 15850 | |||
| 15851 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c | ||
| 15852 | =================================================================== | ||
| 15853 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c | ||
| 15854 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c | ||
| 15855 | @@ -3,7 +3,8 @@ | ||
| 15856 | |||
| 15857 | /* { dg-do assemble } */ | ||
| 15858 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15859 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15860 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15861 | +/* { dg-add-options arm_neon } */ | ||
| 15862 | |||
| 15863 | #include "arm_neon.h" | ||
| 15864 | |||
| 15865 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c | ||
| 15866 | =================================================================== | ||
| 15867 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c | ||
| 15868 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c | ||
| 15869 | @@ -3,7 +3,8 @@ | ||
| 15870 | |||
| 15871 | /* { dg-do assemble } */ | ||
| 15872 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15873 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15874 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15875 | +/* { dg-add-options arm_neon } */ | ||
| 15876 | |||
| 15877 | #include "arm_neon.h" | ||
| 15878 | |||
| 15879 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c | ||
| 15880 | =================================================================== | ||
| 15881 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c | ||
| 15882 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c | ||
| 15883 | @@ -3,7 +3,8 @@ | ||
| 15884 | |||
| 15885 | /* { dg-do assemble } */ | ||
| 15886 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15887 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15888 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15889 | +/* { dg-add-options arm_neon } */ | ||
| 15890 | |||
| 15891 | #include "arm_neon.h" | ||
| 15892 | |||
| 15893 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c | ||
| 15894 | =================================================================== | ||
| 15895 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c | ||
| 15896 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c | ||
| 15897 | @@ -3,7 +3,8 @@ | ||
| 15898 | |||
| 15899 | /* { dg-do assemble } */ | ||
| 15900 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15901 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15902 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15903 | +/* { dg-add-options arm_neon } */ | ||
| 15904 | |||
| 15905 | #include "arm_neon.h" | ||
| 15906 | |||
| 15907 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c | ||
| 15908 | =================================================================== | ||
| 15909 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c | ||
| 15910 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c | ||
| 15911 | @@ -3,7 +3,8 @@ | ||
| 15912 | |||
| 15913 | /* { dg-do assemble } */ | ||
| 15914 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15915 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15916 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15917 | +/* { dg-add-options arm_neon } */ | ||
| 15918 | |||
| 15919 | #include "arm_neon.h" | ||
| 15920 | |||
| 15921 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c | ||
| 15922 | =================================================================== | ||
| 15923 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c | ||
| 15924 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c | ||
| 15925 | @@ -3,7 +3,8 @@ | ||
| 15926 | |||
| 15927 | /* { dg-do assemble } */ | ||
| 15928 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15929 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15930 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15931 | +/* { dg-add-options arm_neon } */ | ||
| 15932 | |||
| 15933 | #include "arm_neon.h" | ||
| 15934 | |||
| 15935 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c | ||
| 15936 | =================================================================== | ||
| 15937 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c | ||
| 15938 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c | ||
| 15939 | @@ -3,7 +3,8 @@ | ||
| 15940 | |||
| 15941 | /* { dg-do assemble } */ | ||
| 15942 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15943 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15944 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15945 | +/* { dg-add-options arm_neon } */ | ||
| 15946 | |||
| 15947 | #include "arm_neon.h" | ||
| 15948 | |||
| 15949 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c | ||
| 15950 | =================================================================== | ||
| 15951 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c | ||
| 15952 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c | ||
| 15953 | @@ -3,7 +3,8 @@ | ||
| 15954 | |||
| 15955 | /* { dg-do assemble } */ | ||
| 15956 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15957 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15958 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15959 | +/* { dg-add-options arm_neon } */ | ||
| 15960 | |||
| 15961 | #include "arm_neon.h" | ||
| 15962 | |||
| 15963 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c | ||
| 15964 | =================================================================== | ||
| 15965 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c | ||
| 15966 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c | ||
| 15967 | @@ -3,7 +3,8 @@ | ||
| 15968 | |||
| 15969 | /* { dg-do assemble } */ | ||
| 15970 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15971 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15972 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15973 | +/* { dg-add-options arm_neon } */ | ||
| 15974 | |||
| 15975 | #include "arm_neon.h" | ||
| 15976 | |||
| 15977 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c | ||
| 15978 | =================================================================== | ||
| 15979 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c | ||
| 15980 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c | ||
| 15981 | @@ -3,7 +3,8 @@ | ||
| 15982 | |||
| 15983 | /* { dg-do assemble } */ | ||
| 15984 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15985 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 15986 | +/* { dg-options "-save-temps -O0" } */ | ||
| 15987 | +/* { dg-add-options arm_neon } */ | ||
| 15988 | |||
| 15989 | #include "arm_neon.h" | ||
| 15990 | |||
| 15991 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c | ||
| 15992 | =================================================================== | ||
| 15993 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c | ||
| 15994 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c | ||
| 15995 | @@ -3,7 +3,8 @@ | ||
| 15996 | |||
| 15997 | /* { dg-do assemble } */ | ||
| 15998 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15999 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16000 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16001 | +/* { dg-add-options arm_neon } */ | ||
| 16002 | |||
| 16003 | #include "arm_neon.h" | ||
| 16004 | |||
| 16005 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c | ||
| 16006 | =================================================================== | ||
| 16007 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c | ||
| 16008 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c | ||
| 16009 | @@ -3,7 +3,8 @@ | ||
| 16010 | |||
| 16011 | /* { dg-do assemble } */ | ||
| 16012 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16013 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16014 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16015 | +/* { dg-add-options arm_neon } */ | ||
| 16016 | |||
| 16017 | #include "arm_neon.h" | ||
| 16018 | |||
| 16019 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c | ||
| 16020 | =================================================================== | ||
| 16021 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c | ||
| 16022 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c | ||
| 16023 | @@ -3,7 +3,8 @@ | ||
| 16024 | |||
| 16025 | /* { dg-do assemble } */ | ||
| 16026 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16027 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16028 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16029 | +/* { dg-add-options arm_neon } */ | ||
| 16030 | |||
| 16031 | #include "arm_neon.h" | ||
| 16032 | |||
| 16033 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c | ||
| 16034 | =================================================================== | ||
| 16035 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c | ||
| 16036 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c | ||
| 16037 | @@ -3,7 +3,8 @@ | ||
| 16038 | |||
| 16039 | /* { dg-do assemble } */ | ||
| 16040 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16041 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16042 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16043 | +/* { dg-add-options arm_neon } */ | ||
| 16044 | |||
| 16045 | #include "arm_neon.h" | ||
| 16046 | |||
| 16047 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c | ||
| 16048 | =================================================================== | ||
| 16049 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c | ||
| 16050 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c | ||
| 16051 | @@ -3,7 +3,8 @@ | ||
| 16052 | |||
| 16053 | /* { dg-do assemble } */ | ||
| 16054 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16055 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16056 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16057 | +/* { dg-add-options arm_neon } */ | ||
| 16058 | |||
| 16059 | #include "arm_neon.h" | ||
| 16060 | |||
| 16061 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c | ||
| 16062 | =================================================================== | ||
| 16063 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c | ||
| 16064 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c | ||
| 16065 | @@ -3,7 +3,8 @@ | ||
| 16066 | |||
| 16067 | /* { dg-do assemble } */ | ||
| 16068 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16069 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16070 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16071 | +/* { dg-add-options arm_neon } */ | ||
| 16072 | |||
| 16073 | #include "arm_neon.h" | ||
| 16074 | |||
| 16075 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c | ||
| 16076 | =================================================================== | ||
| 16077 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c | ||
| 16078 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c | ||
| 16079 | @@ -3,7 +3,8 @@ | ||
| 16080 | |||
| 16081 | /* { dg-do assemble } */ | ||
| 16082 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16083 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16084 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16085 | +/* { dg-add-options arm_neon } */ | ||
| 16086 | |||
| 16087 | #include "arm_neon.h" | ||
| 16088 | |||
| 16089 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c | ||
| 16090 | =================================================================== | ||
| 16091 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c | ||
| 16092 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c | ||
| 16093 | @@ -3,7 +3,8 @@ | ||
| 16094 | |||
| 16095 | /* { dg-do assemble } */ | ||
| 16096 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16097 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16098 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16099 | +/* { dg-add-options arm_neon } */ | ||
| 16100 | |||
| 16101 | #include "arm_neon.h" | ||
| 16102 | |||
| 16103 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c | ||
| 16104 | =================================================================== | ||
| 16105 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c | ||
| 16106 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c | ||
| 16107 | @@ -3,7 +3,8 @@ | ||
| 16108 | |||
| 16109 | /* { dg-do assemble } */ | ||
| 16110 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16111 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16112 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16113 | +/* { dg-add-options arm_neon } */ | ||
| 16114 | |||
| 16115 | #include "arm_neon.h" | ||
| 16116 | |||
| 16117 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c | ||
| 16118 | =================================================================== | ||
| 16119 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c | ||
| 16120 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c | ||
| 16121 | @@ -3,7 +3,8 @@ | ||
| 16122 | |||
| 16123 | /* { dg-do assemble } */ | ||
| 16124 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16125 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16126 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16127 | +/* { dg-add-options arm_neon } */ | ||
| 16128 | |||
| 16129 | #include "arm_neon.h" | ||
| 16130 | |||
| 16131 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c | ||
| 16132 | =================================================================== | ||
| 16133 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c | ||
| 16134 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c | ||
| 16135 | @@ -3,7 +3,8 @@ | ||
| 16136 | |||
| 16137 | /* { dg-do assemble } */ | ||
| 16138 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16139 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16140 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16141 | +/* { dg-add-options arm_neon } */ | ||
| 16142 | |||
| 16143 | #include "arm_neon.h" | ||
| 16144 | |||
| 16145 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c | ||
| 16146 | =================================================================== | ||
| 16147 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c | ||
| 16148 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c | ||
| 16149 | @@ -3,7 +3,8 @@ | ||
| 16150 | |||
| 16151 | /* { dg-do assemble } */ | ||
| 16152 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16153 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16154 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16155 | +/* { dg-add-options arm_neon } */ | ||
| 16156 | |||
| 16157 | #include "arm_neon.h" | ||
| 16158 | |||
| 16159 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c | ||
| 16160 | =================================================================== | ||
| 16161 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c | ||
| 16162 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c | ||
| 16163 | @@ -3,7 +3,8 @@ | ||
| 16164 | |||
| 16165 | /* { dg-do assemble } */ | ||
| 16166 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16167 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16168 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16169 | +/* { dg-add-options arm_neon } */ | ||
| 16170 | |||
| 16171 | #include "arm_neon.h" | ||
| 16172 | |||
| 16173 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c | ||
| 16174 | =================================================================== | ||
| 16175 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c | ||
| 16176 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c | ||
| 16177 | @@ -3,7 +3,8 @@ | ||
| 16178 | |||
| 16179 | /* { dg-do assemble } */ | ||
| 16180 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16181 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16182 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16183 | +/* { dg-add-options arm_neon } */ | ||
| 16184 | |||
| 16185 | #include "arm_neon.h" | ||
| 16186 | |||
| 16187 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c | ||
| 16188 | =================================================================== | ||
| 16189 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c | ||
| 16190 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c | ||
| 16191 | @@ -3,7 +3,8 @@ | ||
| 16192 | |||
| 16193 | /* { dg-do assemble } */ | ||
| 16194 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16195 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16196 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16197 | +/* { dg-add-options arm_neon } */ | ||
| 16198 | |||
| 16199 | #include "arm_neon.h" | ||
| 16200 | |||
| 16201 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c | ||
| 16202 | =================================================================== | ||
| 16203 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c | ||
| 16204 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c | ||
| 16205 | @@ -3,7 +3,8 @@ | ||
| 16206 | |||
| 16207 | /* { dg-do assemble } */ | ||
| 16208 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16209 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16210 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16211 | +/* { dg-add-options arm_neon } */ | ||
| 16212 | |||
| 16213 | #include "arm_neon.h" | ||
| 16214 | |||
| 16215 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c | ||
| 16216 | =================================================================== | ||
| 16217 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c | ||
| 16218 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c | ||
| 16219 | @@ -3,7 +3,8 @@ | ||
| 16220 | |||
| 16221 | /* { dg-do assemble } */ | ||
| 16222 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16223 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16224 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16225 | +/* { dg-add-options arm_neon } */ | ||
| 16226 | |||
| 16227 | #include "arm_neon.h" | ||
| 16228 | |||
| 16229 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c | ||
| 16230 | =================================================================== | ||
| 16231 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c | ||
| 16232 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c | ||
| 16233 | @@ -3,7 +3,8 @@ | ||
| 16234 | |||
| 16235 | /* { dg-do assemble } */ | ||
| 16236 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16237 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16238 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16239 | +/* { dg-add-options arm_neon } */ | ||
| 16240 | |||
| 16241 | #include "arm_neon.h" | ||
| 16242 | |||
| 16243 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c | ||
| 16244 | =================================================================== | ||
| 16245 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c | ||
| 16246 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c | ||
| 16247 | @@ -3,7 +3,8 @@ | ||
| 16248 | |||
| 16249 | /* { dg-do assemble } */ | ||
| 16250 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16251 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16252 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16253 | +/* { dg-add-options arm_neon } */ | ||
| 16254 | |||
| 16255 | #include "arm_neon.h" | ||
| 16256 | |||
| 16257 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c | ||
| 16258 | =================================================================== | ||
| 16259 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c | ||
| 16260 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c | ||
| 16261 | @@ -3,7 +3,8 @@ | ||
| 16262 | |||
| 16263 | /* { dg-do assemble } */ | ||
| 16264 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16265 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16266 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16267 | +/* { dg-add-options arm_neon } */ | ||
| 16268 | |||
| 16269 | #include "arm_neon.h" | ||
| 16270 | |||
| 16271 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c | ||
| 16272 | =================================================================== | ||
| 16273 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c | ||
| 16274 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c | ||
| 16275 | @@ -3,7 +3,8 @@ | ||
| 16276 | |||
| 16277 | /* { dg-do assemble } */ | ||
| 16278 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16279 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16280 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16281 | +/* { dg-add-options arm_neon } */ | ||
| 16282 | |||
| 16283 | #include "arm_neon.h" | ||
| 16284 | |||
| 16285 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c | ||
| 16286 | =================================================================== | ||
| 16287 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c | ||
| 16288 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c | ||
| 16289 | @@ -3,7 +3,8 @@ | ||
| 16290 | |||
| 16291 | /* { dg-do assemble } */ | ||
| 16292 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16293 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16294 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16295 | +/* { dg-add-options arm_neon } */ | ||
| 16296 | |||
| 16297 | #include "arm_neon.h" | ||
| 16298 | |||
| 16299 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c | ||
| 16300 | =================================================================== | ||
| 16301 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c | ||
| 16302 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c | ||
| 16303 | @@ -3,7 +3,8 @@ | ||
| 16304 | |||
| 16305 | /* { dg-do assemble } */ | ||
| 16306 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16307 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16308 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16309 | +/* { dg-add-options arm_neon } */ | ||
| 16310 | |||
| 16311 | #include "arm_neon.h" | ||
| 16312 | |||
| 16313 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c | ||
| 16314 | =================================================================== | ||
| 16315 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c | ||
| 16316 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c | ||
| 16317 | @@ -3,7 +3,8 @@ | ||
| 16318 | |||
| 16319 | /* { dg-do assemble } */ | ||
| 16320 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16321 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16322 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16323 | +/* { dg-add-options arm_neon } */ | ||
| 16324 | |||
| 16325 | #include "arm_neon.h" | ||
| 16326 | |||
| 16327 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c | ||
| 16328 | =================================================================== | ||
| 16329 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c | ||
| 16330 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c | ||
| 16331 | @@ -3,7 +3,8 @@ | ||
| 16332 | |||
| 16333 | /* { dg-do assemble } */ | ||
| 16334 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16335 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16336 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16337 | +/* { dg-add-options arm_neon } */ | ||
| 16338 | |||
| 16339 | #include "arm_neon.h" | ||
| 16340 | |||
| 16341 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c | ||
| 16342 | =================================================================== | ||
| 16343 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c | ||
| 16344 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c | ||
| 16345 | @@ -3,7 +3,8 @@ | ||
| 16346 | |||
| 16347 | /* { dg-do assemble } */ | ||
| 16348 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16349 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16350 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16351 | +/* { dg-add-options arm_neon } */ | ||
| 16352 | |||
| 16353 | #include "arm_neon.h" | ||
| 16354 | |||
| 16355 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c | ||
| 16356 | =================================================================== | ||
| 16357 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c | ||
| 16358 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c | ||
| 16359 | @@ -3,7 +3,8 @@ | ||
| 16360 | |||
| 16361 | /* { dg-do assemble } */ | ||
| 16362 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16363 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16364 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16365 | +/* { dg-add-options arm_neon } */ | ||
| 16366 | |||
| 16367 | #include "arm_neon.h" | ||
| 16368 | |||
| 16369 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c | ||
| 16370 | =================================================================== | ||
| 16371 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c | ||
| 16372 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c | ||
| 16373 | @@ -3,7 +3,8 @@ | ||
| 16374 | |||
| 16375 | /* { dg-do assemble } */ | ||
| 16376 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16377 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16378 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16379 | +/* { dg-add-options arm_neon } */ | ||
| 16380 | |||
| 16381 | #include "arm_neon.h" | ||
| 16382 | |||
| 16383 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c | ||
| 16384 | =================================================================== | ||
| 16385 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c | ||
| 16386 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c | ||
| 16387 | @@ -3,7 +3,8 @@ | ||
| 16388 | |||
| 16389 | /* { dg-do assemble } */ | ||
| 16390 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16391 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16392 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16393 | +/* { dg-add-options arm_neon } */ | ||
| 16394 | |||
| 16395 | #include "arm_neon.h" | ||
| 16396 | |||
| 16397 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls16.c | ||
| 16398 | =================================================================== | ||
| 16399 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshls16.c | ||
| 16400 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls16.c | ||
| 16401 | @@ -3,7 +3,8 @@ | ||
| 16402 | |||
| 16403 | /* { dg-do assemble } */ | ||
| 16404 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16405 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16406 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16407 | +/* { dg-add-options arm_neon } */ | ||
| 16408 | |||
| 16409 | #include "arm_neon.h" | ||
| 16410 | |||
| 16411 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls32.c | ||
| 16412 | =================================================================== | ||
| 16413 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshls32.c | ||
| 16414 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls32.c | ||
| 16415 | @@ -3,7 +3,8 @@ | ||
| 16416 | |||
| 16417 | /* { dg-do assemble } */ | ||
| 16418 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16419 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16420 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16421 | +/* { dg-add-options arm_neon } */ | ||
| 16422 | |||
| 16423 | #include "arm_neon.h" | ||
| 16424 | |||
| 16425 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls64.c | ||
| 16426 | =================================================================== | ||
| 16427 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshls64.c | ||
| 16428 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls64.c | ||
| 16429 | @@ -3,7 +3,8 @@ | ||
| 16430 | |||
| 16431 | /* { dg-do assemble } */ | ||
| 16432 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16433 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16434 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16435 | +/* { dg-add-options arm_neon } */ | ||
| 16436 | |||
| 16437 | #include "arm_neon.h" | ||
| 16438 | |||
| 16439 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls8.c | ||
| 16440 | =================================================================== | ||
| 16441 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshls8.c | ||
| 16442 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshls8.c | ||
| 16443 | @@ -3,7 +3,8 @@ | ||
| 16444 | |||
| 16445 | /* { dg-do assemble } */ | ||
| 16446 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16447 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16448 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16449 | +/* { dg-add-options arm_neon } */ | ||
| 16450 | |||
| 16451 | #include "arm_neon.h" | ||
| 16452 | |||
| 16453 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c | ||
| 16454 | =================================================================== | ||
| 16455 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c | ||
| 16456 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c | ||
| 16457 | @@ -3,7 +3,8 @@ | ||
| 16458 | |||
| 16459 | /* { dg-do assemble } */ | ||
| 16460 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16461 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16462 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16463 | +/* { dg-add-options arm_neon } */ | ||
| 16464 | |||
| 16465 | #include "arm_neon.h" | ||
| 16466 | |||
| 16467 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c | ||
| 16468 | =================================================================== | ||
| 16469 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c | ||
| 16470 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c | ||
| 16471 | @@ -3,7 +3,8 @@ | ||
| 16472 | |||
| 16473 | /* { dg-do assemble } */ | ||
| 16474 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16475 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16476 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16477 | +/* { dg-add-options arm_neon } */ | ||
| 16478 | |||
| 16479 | #include "arm_neon.h" | ||
| 16480 | |||
| 16481 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c | ||
| 16482 | =================================================================== | ||
| 16483 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c | ||
| 16484 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c | ||
| 16485 | @@ -3,7 +3,8 @@ | ||
| 16486 | |||
| 16487 | /* { dg-do assemble } */ | ||
| 16488 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16489 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16490 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16491 | +/* { dg-add-options arm_neon } */ | ||
| 16492 | |||
| 16493 | #include "arm_neon.h" | ||
| 16494 | |||
| 16495 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c | ||
| 16496 | =================================================================== | ||
| 16497 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c | ||
| 16498 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c | ||
| 16499 | @@ -3,7 +3,8 @@ | ||
| 16500 | |||
| 16501 | /* { dg-do assemble } */ | ||
| 16502 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16503 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16504 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16505 | +/* { dg-add-options arm_neon } */ | ||
| 16506 | |||
| 16507 | #include "arm_neon.h" | ||
| 16508 | |||
| 16509 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c | ||
| 16510 | =================================================================== | ||
| 16511 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c | ||
| 16512 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c | ||
| 16513 | @@ -3,7 +3,8 @@ | ||
| 16514 | |||
| 16515 | /* { dg-do assemble } */ | ||
| 16516 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16517 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16518 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16519 | +/* { dg-add-options arm_neon } */ | ||
| 16520 | |||
| 16521 | #include "arm_neon.h" | ||
| 16522 | |||
| 16523 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c | ||
| 16524 | =================================================================== | ||
| 16525 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c | ||
| 16526 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c | ||
| 16527 | @@ -3,7 +3,8 @@ | ||
| 16528 | |||
| 16529 | /* { dg-do assemble } */ | ||
| 16530 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16531 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16532 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16533 | +/* { dg-add-options arm_neon } */ | ||
| 16534 | |||
| 16535 | #include "arm_neon.h" | ||
| 16536 | |||
| 16537 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c | ||
| 16538 | =================================================================== | ||
| 16539 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c | ||
| 16540 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c | ||
| 16541 | @@ -3,7 +3,8 @@ | ||
| 16542 | |||
| 16543 | /* { dg-do assemble } */ | ||
| 16544 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16545 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16546 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16547 | +/* { dg-add-options arm_neon } */ | ||
| 16548 | |||
| 16549 | #include "arm_neon.h" | ||
| 16550 | |||
| 16551 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c | ||
| 16552 | =================================================================== | ||
| 16553 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c | ||
| 16554 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c | ||
| 16555 | @@ -3,7 +3,8 @@ | ||
| 16556 | |||
| 16557 | /* { dg-do assemble } */ | ||
| 16558 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16559 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16560 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16561 | +/* { dg-add-options arm_neon } */ | ||
| 16562 | |||
| 16563 | #include "arm_neon.h" | ||
| 16564 | |||
| 16565 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c | ||
| 16566 | =================================================================== | ||
| 16567 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c | ||
| 16568 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c | ||
| 16569 | @@ -3,7 +3,8 @@ | ||
| 16570 | |||
| 16571 | /* { dg-do assemble } */ | ||
| 16572 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16573 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16574 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16575 | +/* { dg-add-options arm_neon } */ | ||
| 16576 | |||
| 16577 | #include "arm_neon.h" | ||
| 16578 | |||
| 16579 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c | ||
| 16580 | =================================================================== | ||
| 16581 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c | ||
| 16582 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c | ||
| 16583 | @@ -3,7 +3,8 @@ | ||
| 16584 | |||
| 16585 | /* { dg-do assemble } */ | ||
| 16586 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16587 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16588 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16589 | +/* { dg-add-options arm_neon } */ | ||
| 16590 | |||
| 16591 | #include "arm_neon.h" | ||
| 16592 | |||
| 16593 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c | ||
| 16594 | =================================================================== | ||
| 16595 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c | ||
| 16596 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c | ||
| 16597 | @@ -3,7 +3,8 @@ | ||
| 16598 | |||
| 16599 | /* { dg-do assemble } */ | ||
| 16600 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16601 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16602 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16603 | +/* { dg-add-options arm_neon } */ | ||
| 16604 | |||
| 16605 | #include "arm_neon.h" | ||
| 16606 | |||
| 16607 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c | ||
| 16608 | =================================================================== | ||
| 16609 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c | ||
| 16610 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c | ||
| 16611 | @@ -3,7 +3,8 @@ | ||
| 16612 | |||
| 16613 | /* { dg-do assemble } */ | ||
| 16614 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16615 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16616 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16617 | +/* { dg-add-options arm_neon } */ | ||
| 16618 | |||
| 16619 | #include "arm_neon.h" | ||
| 16620 | |||
| 16621 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c | ||
| 16622 | =================================================================== | ||
| 16623 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c | ||
| 16624 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c | ||
| 16625 | @@ -3,7 +3,8 @@ | ||
| 16626 | |||
| 16627 | /* { dg-do assemble } */ | ||
| 16628 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16629 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16630 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16631 | +/* { dg-add-options arm_neon } */ | ||
| 16632 | |||
| 16633 | #include "arm_neon.h" | ||
| 16634 | |||
| 16635 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c | ||
| 16636 | =================================================================== | ||
| 16637 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c | ||
| 16638 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c | ||
| 16639 | @@ -3,7 +3,8 @@ | ||
| 16640 | |||
| 16641 | /* { dg-do assemble } */ | ||
| 16642 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16643 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16644 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16645 | +/* { dg-add-options arm_neon } */ | ||
| 16646 | |||
| 16647 | #include "arm_neon.h" | ||
| 16648 | |||
| 16649 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c | ||
| 16650 | =================================================================== | ||
| 16651 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c | ||
| 16652 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c | ||
| 16653 | @@ -3,7 +3,8 @@ | ||
| 16654 | |||
| 16655 | /* { dg-do assemble } */ | ||
| 16656 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16657 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16658 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16659 | +/* { dg-add-options arm_neon } */ | ||
| 16660 | |||
| 16661 | #include "arm_neon.h" | ||
| 16662 | |||
| 16663 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c | ||
| 16664 | =================================================================== | ||
| 16665 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c | ||
| 16666 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c | ||
| 16667 | @@ -3,7 +3,8 @@ | ||
| 16668 | |||
| 16669 | /* { dg-do assemble } */ | ||
| 16670 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16671 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16672 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16673 | +/* { dg-add-options arm_neon } */ | ||
| 16674 | |||
| 16675 | #include "arm_neon.h" | ||
| 16676 | |||
| 16677 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c | ||
| 16678 | =================================================================== | ||
| 16679 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c | ||
| 16680 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c | ||
| 16681 | @@ -3,7 +3,8 @@ | ||
| 16682 | |||
| 16683 | /* { dg-do assemble } */ | ||
| 16684 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16685 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16686 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16687 | +/* { dg-add-options arm_neon } */ | ||
| 16688 | |||
| 16689 | #include "arm_neon.h" | ||
| 16690 | |||
| 16691 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c | ||
| 16692 | =================================================================== | ||
| 16693 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c | ||
| 16694 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c | ||
| 16695 | @@ -3,7 +3,8 @@ | ||
| 16696 | |||
| 16697 | /* { dg-do assemble } */ | ||
| 16698 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16699 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16700 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16701 | +/* { dg-add-options arm_neon } */ | ||
| 16702 | |||
| 16703 | #include "arm_neon.h" | ||
| 16704 | |||
| 16705 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c | ||
| 16706 | =================================================================== | ||
| 16707 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c | ||
| 16708 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c | ||
| 16709 | @@ -3,7 +3,8 @@ | ||
| 16710 | |||
| 16711 | /* { dg-do assemble } */ | ||
| 16712 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16713 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16714 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16715 | +/* { dg-add-options arm_neon } */ | ||
| 16716 | |||
| 16717 | #include "arm_neon.h" | ||
| 16718 | |||
| 16719 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c | ||
| 16720 | =================================================================== | ||
| 16721 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c | ||
| 16722 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c | ||
| 16723 | @@ -3,7 +3,8 @@ | ||
| 16724 | |||
| 16725 | /* { dg-do assemble } */ | ||
| 16726 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16727 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16728 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16729 | +/* { dg-add-options arm_neon } */ | ||
| 16730 | |||
| 16731 | #include "arm_neon.h" | ||
| 16732 | |||
| 16733 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c | ||
| 16734 | =================================================================== | ||
| 16735 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c | ||
| 16736 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c | ||
| 16737 | @@ -3,7 +3,8 @@ | ||
| 16738 | |||
| 16739 | /* { dg-do assemble } */ | ||
| 16740 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16741 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16742 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16743 | +/* { dg-add-options arm_neon } */ | ||
| 16744 | |||
| 16745 | #include "arm_neon.h" | ||
| 16746 | |||
| 16747 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c | ||
| 16748 | =================================================================== | ||
| 16749 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c | ||
| 16750 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c | ||
| 16751 | @@ -3,7 +3,8 @@ | ||
| 16752 | |||
| 16753 | /* { dg-do assemble } */ | ||
| 16754 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16755 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16756 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16757 | +/* { dg-add-options arm_neon } */ | ||
| 16758 | |||
| 16759 | #include "arm_neon.h" | ||
| 16760 | |||
| 16761 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c | ||
| 16762 | =================================================================== | ||
| 16763 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c | ||
| 16764 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c | ||
| 16765 | @@ -3,7 +3,8 @@ | ||
| 16766 | |||
| 16767 | /* { dg-do assemble } */ | ||
| 16768 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16769 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16770 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16771 | +/* { dg-add-options arm_neon } */ | ||
| 16772 | |||
| 16773 | #include "arm_neon.h" | ||
| 16774 | |||
| 16775 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c | ||
| 16776 | =================================================================== | ||
| 16777 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c | ||
| 16778 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c | ||
| 16779 | @@ -3,7 +3,8 @@ | ||
| 16780 | |||
| 16781 | /* { dg-do assemble } */ | ||
| 16782 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16783 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16784 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16785 | +/* { dg-add-options arm_neon } */ | ||
| 16786 | |||
| 16787 | #include "arm_neon.h" | ||
| 16788 | |||
| 16789 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c | ||
| 16790 | =================================================================== | ||
| 16791 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c | ||
| 16792 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c | ||
| 16793 | @@ -3,7 +3,8 @@ | ||
| 16794 | |||
| 16795 | /* { dg-do assemble } */ | ||
| 16796 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16797 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16798 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16799 | +/* { dg-add-options arm_neon } */ | ||
| 16800 | |||
| 16801 | #include "arm_neon.h" | ||
| 16802 | |||
| 16803 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c | ||
| 16804 | =================================================================== | ||
| 16805 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c | ||
| 16806 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c | ||
| 16807 | @@ -3,7 +3,8 @@ | ||
| 16808 | |||
| 16809 | /* { dg-do assemble } */ | ||
| 16810 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16811 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16812 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16813 | +/* { dg-add-options arm_neon } */ | ||
| 16814 | |||
| 16815 | #include "arm_neon.h" | ||
| 16816 | |||
| 16817 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c | ||
| 16818 | =================================================================== | ||
| 16819 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c | ||
| 16820 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c | ||
| 16821 | @@ -3,7 +3,8 @@ | ||
| 16822 | |||
| 16823 | /* { dg-do assemble } */ | ||
| 16824 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16825 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16826 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16827 | +/* { dg-add-options arm_neon } */ | ||
| 16828 | |||
| 16829 | #include "arm_neon.h" | ||
| 16830 | |||
| 16831 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c | ||
| 16832 | =================================================================== | ||
| 16833 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c | ||
| 16834 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c | ||
| 16835 | @@ -3,7 +3,8 @@ | ||
| 16836 | |||
| 16837 | /* { dg-do assemble } */ | ||
| 16838 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16839 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16840 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16841 | +/* { dg-add-options arm_neon } */ | ||
| 16842 | |||
| 16843 | #include "arm_neon.h" | ||
| 16844 | |||
| 16845 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c | ||
| 16846 | =================================================================== | ||
| 16847 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c | ||
| 16848 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c | ||
| 16849 | @@ -3,7 +3,8 @@ | ||
| 16850 | |||
| 16851 | /* { dg-do assemble } */ | ||
| 16852 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16853 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16854 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16855 | +/* { dg-add-options arm_neon } */ | ||
| 16856 | |||
| 16857 | #include "arm_neon.h" | ||
| 16858 | |||
| 16859 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c | ||
| 16860 | =================================================================== | ||
| 16861 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c | ||
| 16862 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c | ||
| 16863 | @@ -3,7 +3,8 @@ | ||
| 16864 | |||
| 16865 | /* { dg-do assemble } */ | ||
| 16866 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16867 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16868 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16869 | +/* { dg-add-options arm_neon } */ | ||
| 16870 | |||
| 16871 | #include "arm_neon.h" | ||
| 16872 | |||
| 16873 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c | ||
| 16874 | =================================================================== | ||
| 16875 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c | ||
| 16876 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c | ||
| 16877 | @@ -3,7 +3,8 @@ | ||
| 16878 | |||
| 16879 | /* { dg-do assemble } */ | ||
| 16880 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16881 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16882 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16883 | +/* { dg-add-options arm_neon } */ | ||
| 16884 | |||
| 16885 | #include "arm_neon.h" | ||
| 16886 | |||
| 16887 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c | ||
| 16888 | =================================================================== | ||
| 16889 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c | ||
| 16890 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c | ||
| 16891 | @@ -3,7 +3,8 @@ | ||
| 16892 | |||
| 16893 | /* { dg-do assemble } */ | ||
| 16894 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16895 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16896 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16897 | +/* { dg-add-options arm_neon } */ | ||
| 16898 | |||
| 16899 | #include "arm_neon.h" | ||
| 16900 | |||
| 16901 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c | ||
| 16902 | =================================================================== | ||
| 16903 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c | ||
| 16904 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c | ||
| 16905 | @@ -3,7 +3,8 @@ | ||
| 16906 | |||
| 16907 | /* { dg-do assemble } */ | ||
| 16908 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16909 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16910 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16911 | +/* { dg-add-options arm_neon } */ | ||
| 16912 | |||
| 16913 | #include "arm_neon.h" | ||
| 16914 | |||
| 16915 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c | ||
| 16916 | =================================================================== | ||
| 16917 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c | ||
| 16918 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c | ||
| 16919 | @@ -3,7 +3,8 @@ | ||
| 16920 | |||
| 16921 | /* { dg-do assemble } */ | ||
| 16922 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16923 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16924 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16925 | +/* { dg-add-options arm_neon } */ | ||
| 16926 | |||
| 16927 | #include "arm_neon.h" | ||
| 16928 | |||
| 16929 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c | ||
| 16930 | =================================================================== | ||
| 16931 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c | ||
| 16932 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c | ||
| 16933 | @@ -3,7 +3,8 @@ | ||
| 16934 | |||
| 16935 | /* { dg-do assemble } */ | ||
| 16936 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16937 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16938 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16939 | +/* { dg-add-options arm_neon } */ | ||
| 16940 | |||
| 16941 | #include "arm_neon.h" | ||
| 16942 | |||
| 16943 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c | ||
| 16944 | =================================================================== | ||
| 16945 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c | ||
| 16946 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c | ||
| 16947 | @@ -3,7 +3,8 @@ | ||
| 16948 | |||
| 16949 | /* { dg-do assemble } */ | ||
| 16950 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16951 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16952 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16953 | +/* { dg-add-options arm_neon } */ | ||
| 16954 | |||
| 16955 | #include "arm_neon.h" | ||
| 16956 | |||
| 16957 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c | ||
| 16958 | =================================================================== | ||
| 16959 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c | ||
| 16960 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c | ||
| 16961 | @@ -3,7 +3,8 @@ | ||
| 16962 | |||
| 16963 | /* { dg-do assemble } */ | ||
| 16964 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16965 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16966 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16967 | +/* { dg-add-options arm_neon } */ | ||
| 16968 | |||
| 16969 | #include "arm_neon.h" | ||
| 16970 | |||
| 16971 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c | ||
| 16972 | =================================================================== | ||
| 16973 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c | ||
| 16974 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c | ||
| 16975 | @@ -3,7 +3,8 @@ | ||
| 16976 | |||
| 16977 | /* { dg-do assemble } */ | ||
| 16978 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16979 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16980 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16981 | +/* { dg-add-options arm_neon } */ | ||
| 16982 | |||
| 16983 | #include "arm_neon.h" | ||
| 16984 | |||
| 16985 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c | ||
| 16986 | =================================================================== | ||
| 16987 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c | ||
| 16988 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c | ||
| 16989 | @@ -3,7 +3,8 @@ | ||
| 16990 | |||
| 16991 | /* { dg-do assemble } */ | ||
| 16992 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 16993 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 16994 | +/* { dg-options "-save-temps -O0" } */ | ||
| 16995 | +/* { dg-add-options arm_neon } */ | ||
| 16996 | |||
| 16997 | #include "arm_neon.h" | ||
| 16998 | |||
| 16999 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c | ||
| 17000 | =================================================================== | ||
| 17001 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c | ||
| 17002 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c | ||
| 17003 | @@ -3,7 +3,8 @@ | ||
| 17004 | |||
| 17005 | /* { dg-do assemble } */ | ||
| 17006 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17007 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17008 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17009 | +/* { dg-add-options arm_neon } */ | ||
| 17010 | |||
| 17011 | #include "arm_neon.h" | ||
| 17012 | |||
| 17013 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c | ||
| 17014 | =================================================================== | ||
| 17015 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c | ||
| 17016 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c | ||
| 17017 | @@ -3,7 +3,8 @@ | ||
| 17018 | |||
| 17019 | /* { dg-do assemble } */ | ||
| 17020 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17021 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17022 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17023 | +/* { dg-add-options arm_neon } */ | ||
| 17024 | |||
| 17025 | #include "arm_neon.h" | ||
| 17026 | |||
| 17027 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c | ||
| 17028 | =================================================================== | ||
| 17029 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c | ||
| 17030 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c | ||
| 17031 | @@ -3,7 +3,8 @@ | ||
| 17032 | |||
| 17033 | /* { dg-do assemble } */ | ||
| 17034 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17035 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17036 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17037 | +/* { dg-add-options arm_neon } */ | ||
| 17038 | |||
| 17039 | #include "arm_neon.h" | ||
| 17040 | |||
| 17041 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c | ||
| 17042 | =================================================================== | ||
| 17043 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c | ||
| 17044 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c | ||
| 17045 | @@ -3,7 +3,8 @@ | ||
| 17046 | |||
| 17047 | /* { dg-do assemble } */ | ||
| 17048 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17049 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17050 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17051 | +/* { dg-add-options arm_neon } */ | ||
| 17052 | |||
| 17053 | #include "arm_neon.h" | ||
| 17054 | |||
| 17055 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c | ||
| 17056 | =================================================================== | ||
| 17057 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c | ||
| 17058 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c | ||
| 17059 | @@ -3,7 +3,8 @@ | ||
| 17060 | |||
| 17061 | /* { dg-do assemble } */ | ||
| 17062 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17063 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17064 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17065 | +/* { dg-add-options arm_neon } */ | ||
| 17066 | |||
| 17067 | #include "arm_neon.h" | ||
| 17068 | |||
| 17069 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c | ||
| 17070 | =================================================================== | ||
| 17071 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c | ||
| 17072 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c | ||
| 17073 | @@ -3,7 +3,8 @@ | ||
| 17074 | |||
| 17075 | /* { dg-do assemble } */ | ||
| 17076 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17077 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17078 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17079 | +/* { dg-add-options arm_neon } */ | ||
| 17080 | |||
| 17081 | #include "arm_neon.h" | ||
| 17082 | |||
| 17083 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c | ||
| 17084 | =================================================================== | ||
| 17085 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c | ||
| 17086 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c | ||
| 17087 | @@ -3,7 +3,8 @@ | ||
| 17088 | |||
| 17089 | /* { dg-do assemble } */ | ||
| 17090 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17091 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17092 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17093 | +/* { dg-add-options arm_neon } */ | ||
| 17094 | |||
| 17095 | #include "arm_neon.h" | ||
| 17096 | |||
| 17097 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c | ||
| 17098 | =================================================================== | ||
| 17099 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c | ||
| 17100 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c | ||
| 17101 | @@ -3,7 +3,8 @@ | ||
| 17102 | |||
| 17103 | /* { dg-do assemble } */ | ||
| 17104 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17105 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17106 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17107 | +/* { dg-add-options arm_neon } */ | ||
| 17108 | |||
| 17109 | #include "arm_neon.h" | ||
| 17110 | |||
| 17111 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c | ||
| 17112 | =================================================================== | ||
| 17113 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c | ||
| 17114 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c | ||
| 17115 | @@ -3,7 +3,8 @@ | ||
| 17116 | |||
| 17117 | /* { dg-do assemble } */ | ||
| 17118 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17119 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17120 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17121 | +/* { dg-add-options arm_neon } */ | ||
| 17122 | |||
| 17123 | #include "arm_neon.h" | ||
| 17124 | |||
| 17125 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c | ||
| 17126 | =================================================================== | ||
| 17127 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c | ||
| 17128 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c | ||
| 17129 | @@ -3,7 +3,8 @@ | ||
| 17130 | |||
| 17131 | /* { dg-do assemble } */ | ||
| 17132 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17133 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17134 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17135 | +/* { dg-add-options arm_neon } */ | ||
| 17136 | |||
| 17137 | #include "arm_neon.h" | ||
| 17138 | |||
| 17139 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c | ||
| 17140 | =================================================================== | ||
| 17141 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c | ||
| 17142 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c | ||
| 17143 | @@ -3,7 +3,8 @@ | ||
| 17144 | |||
| 17145 | /* { dg-do assemble } */ | ||
| 17146 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17147 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17148 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17149 | +/* { dg-add-options arm_neon } */ | ||
| 17150 | |||
| 17151 | #include "arm_neon.h" | ||
| 17152 | |||
| 17153 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c | ||
| 17154 | =================================================================== | ||
| 17155 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c | ||
| 17156 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c | ||
| 17157 | @@ -3,7 +3,8 @@ | ||
| 17158 | |||
| 17159 | /* { dg-do assemble } */ | ||
| 17160 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17161 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17162 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17163 | +/* { dg-add-options arm_neon } */ | ||
| 17164 | |||
| 17165 | #include "arm_neon.h" | ||
| 17166 | |||
| 17167 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c | ||
| 17168 | =================================================================== | ||
| 17169 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c | ||
| 17170 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c | ||
| 17171 | @@ -3,7 +3,8 @@ | ||
| 17172 | |||
| 17173 | /* { dg-do assemble } */ | ||
| 17174 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17175 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17176 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17177 | +/* { dg-add-options arm_neon } */ | ||
| 17178 | |||
| 17179 | #include "arm_neon.h" | ||
| 17180 | |||
| 17181 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c | ||
| 17182 | =================================================================== | ||
| 17183 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c | ||
| 17184 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c | ||
| 17185 | @@ -3,7 +3,8 @@ | ||
| 17186 | |||
| 17187 | /* { dg-do assemble } */ | ||
| 17188 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17189 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17190 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17191 | +/* { dg-add-options arm_neon } */ | ||
| 17192 | |||
| 17193 | #include "arm_neon.h" | ||
| 17194 | |||
| 17195 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c | ||
| 17196 | =================================================================== | ||
| 17197 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c | ||
| 17198 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c | ||
| 17199 | @@ -3,7 +3,8 @@ | ||
| 17200 | |||
| 17201 | /* { dg-do assemble } */ | ||
| 17202 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17203 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17204 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17205 | +/* { dg-add-options arm_neon } */ | ||
| 17206 | |||
| 17207 | #include "arm_neon.h" | ||
| 17208 | |||
| 17209 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c | ||
| 17210 | =================================================================== | ||
| 17211 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c | ||
| 17212 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c | ||
| 17213 | @@ -3,7 +3,8 @@ | ||
| 17214 | |||
| 17215 | /* { dg-do assemble } */ | ||
| 17216 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17217 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17218 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17219 | +/* { dg-add-options arm_neon } */ | ||
| 17220 | |||
| 17221 | #include "arm_neon.h" | ||
| 17222 | |||
| 17223 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c | ||
| 17224 | =================================================================== | ||
| 17225 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c | ||
| 17226 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c | ||
| 17227 | @@ -3,7 +3,8 @@ | ||
| 17228 | |||
| 17229 | /* { dg-do assemble } */ | ||
| 17230 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17231 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17232 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17233 | +/* { dg-add-options arm_neon } */ | ||
| 17234 | |||
| 17235 | #include "arm_neon.h" | ||
| 17236 | |||
| 17237 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c | ||
| 17238 | =================================================================== | ||
| 17239 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c | ||
| 17240 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c | ||
| 17241 | @@ -3,7 +3,8 @@ | ||
| 17242 | |||
| 17243 | /* { dg-do assemble } */ | ||
| 17244 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17245 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17246 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17247 | +/* { dg-add-options arm_neon } */ | ||
| 17248 | |||
| 17249 | #include "arm_neon.h" | ||
| 17250 | |||
| 17251 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c | ||
| 17252 | =================================================================== | ||
| 17253 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c | ||
| 17254 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c | ||
| 17255 | @@ -3,7 +3,8 @@ | ||
| 17256 | |||
| 17257 | /* { dg-do assemble } */ | ||
| 17258 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17259 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17260 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17261 | +/* { dg-add-options arm_neon } */ | ||
| 17262 | |||
| 17263 | #include "arm_neon.h" | ||
| 17264 | |||
| 17265 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c | ||
| 17266 | =================================================================== | ||
| 17267 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c | ||
| 17268 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c | ||
| 17269 | @@ -3,7 +3,8 @@ | ||
| 17270 | |||
| 17271 | /* { dg-do assemble } */ | ||
| 17272 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17273 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17274 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17275 | +/* { dg-add-options arm_neon } */ | ||
| 17276 | |||
| 17277 | #include "arm_neon.h" | ||
| 17278 | |||
| 17279 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c | ||
| 17280 | =================================================================== | ||
| 17281 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c | ||
| 17282 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c | ||
| 17283 | @@ -3,7 +3,8 @@ | ||
| 17284 | |||
| 17285 | /* { dg-do assemble } */ | ||
| 17286 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17287 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17288 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17289 | +/* { dg-add-options arm_neon } */ | ||
| 17290 | |||
| 17291 | #include "arm_neon.h" | ||
| 17292 | |||
| 17293 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c | ||
| 17294 | =================================================================== | ||
| 17295 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c | ||
| 17296 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c | ||
| 17297 | @@ -3,7 +3,8 @@ | ||
| 17298 | |||
| 17299 | /* { dg-do assemble } */ | ||
| 17300 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17301 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17302 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17303 | +/* { dg-add-options arm_neon } */ | ||
| 17304 | |||
| 17305 | #include "arm_neon.h" | ||
| 17306 | |||
| 17307 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c | ||
| 17308 | =================================================================== | ||
| 17309 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c | ||
| 17310 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c | ||
| 17311 | @@ -3,7 +3,8 @@ | ||
| 17312 | |||
| 17313 | /* { dg-do assemble } */ | ||
| 17314 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17315 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17316 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17317 | +/* { dg-add-options arm_neon } */ | ||
| 17318 | |||
| 17319 | #include "arm_neon.h" | ||
| 17320 | |||
| 17321 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c | ||
| 17322 | =================================================================== | ||
| 17323 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c | ||
| 17324 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c | ||
| 17325 | @@ -3,7 +3,8 @@ | ||
| 17326 | |||
| 17327 | /* { dg-do assemble } */ | ||
| 17328 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17329 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17330 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17331 | +/* { dg-add-options arm_neon } */ | ||
| 17332 | |||
| 17333 | #include "arm_neon.h" | ||
| 17334 | |||
| 17335 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c | ||
| 17336 | =================================================================== | ||
| 17337 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c | ||
| 17338 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c | ||
| 17339 | @@ -3,7 +3,8 @@ | ||
| 17340 | |||
| 17341 | /* { dg-do assemble } */ | ||
| 17342 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17343 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17344 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17345 | +/* { dg-add-options arm_neon } */ | ||
| 17346 | |||
| 17347 | #include "arm_neon.h" | ||
| 17348 | |||
| 17349 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c | ||
| 17350 | =================================================================== | ||
| 17351 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c | ||
| 17352 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c | ||
| 17353 | @@ -3,7 +3,8 @@ | ||
| 17354 | |||
| 17355 | /* { dg-do assemble } */ | ||
| 17356 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17357 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17358 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17359 | +/* { dg-add-options arm_neon } */ | ||
| 17360 | |||
| 17361 | #include "arm_neon.h" | ||
| 17362 | |||
| 17363 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c | ||
| 17364 | =================================================================== | ||
| 17365 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c | ||
| 17366 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c | ||
| 17367 | @@ -3,7 +3,8 @@ | ||
| 17368 | |||
| 17369 | /* { dg-do assemble } */ | ||
| 17370 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17371 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17372 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17373 | +/* { dg-add-options arm_neon } */ | ||
| 17374 | |||
| 17375 | #include "arm_neon.h" | ||
| 17376 | |||
| 17377 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c | ||
| 17378 | =================================================================== | ||
| 17379 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c | ||
| 17380 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c | ||
| 17381 | @@ -3,7 +3,8 @@ | ||
| 17382 | |||
| 17383 | /* { dg-do assemble } */ | ||
| 17384 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17385 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17386 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17387 | +/* { dg-add-options arm_neon } */ | ||
| 17388 | |||
| 17389 | #include "arm_neon.h" | ||
| 17390 | |||
| 17391 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c | ||
| 17392 | =================================================================== | ||
| 17393 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c | ||
| 17394 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c | ||
| 17395 | @@ -3,7 +3,8 @@ | ||
| 17396 | |||
| 17397 | /* { dg-do assemble } */ | ||
| 17398 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17399 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17400 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17401 | +/* { dg-add-options arm_neon } */ | ||
| 17402 | |||
| 17403 | #include "arm_neon.h" | ||
| 17404 | |||
| 17405 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c | ||
| 17406 | =================================================================== | ||
| 17407 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c | ||
| 17408 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c | ||
| 17409 | @@ -3,7 +3,8 @@ | ||
| 17410 | |||
| 17411 | /* { dg-do assemble } */ | ||
| 17412 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17413 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17414 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17415 | +/* { dg-add-options arm_neon } */ | ||
| 17416 | |||
| 17417 | #include "arm_neon.h" | ||
| 17418 | |||
| 17419 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c | ||
| 17420 | =================================================================== | ||
| 17421 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c | ||
| 17422 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c | ||
| 17423 | @@ -3,7 +3,8 @@ | ||
| 17424 | |||
| 17425 | /* { dg-do assemble } */ | ||
| 17426 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17427 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17428 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17429 | +/* { dg-add-options arm_neon } */ | ||
| 17430 | |||
| 17431 | #include "arm_neon.h" | ||
| 17432 | |||
| 17433 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c | ||
| 17434 | =================================================================== | ||
| 17435 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c | ||
| 17436 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c | ||
| 17437 | @@ -3,7 +3,8 @@ | ||
| 17438 | |||
| 17439 | /* { dg-do assemble } */ | ||
| 17440 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17441 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17442 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17443 | +/* { dg-add-options arm_neon } */ | ||
| 17444 | |||
| 17445 | #include "arm_neon.h" | ||
| 17446 | |||
| 17447 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c | ||
| 17448 | =================================================================== | ||
| 17449 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c | ||
| 17450 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c | ||
| 17451 | @@ -3,7 +3,8 @@ | ||
| 17452 | |||
| 17453 | /* { dg-do assemble } */ | ||
| 17454 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17455 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17456 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17457 | +/* { dg-add-options arm_neon } */ | ||
| 17458 | |||
| 17459 | #include "arm_neon.h" | ||
| 17460 | |||
| 17461 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c | ||
| 17462 | =================================================================== | ||
| 17463 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c | ||
| 17464 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c | ||
| 17465 | @@ -3,7 +3,8 @@ | ||
| 17466 | |||
| 17467 | /* { dg-do assemble } */ | ||
| 17468 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17469 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17470 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17471 | +/* { dg-add-options arm_neon } */ | ||
| 17472 | |||
| 17473 | #include "arm_neon.h" | ||
| 17474 | |||
| 17475 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c | ||
| 17476 | =================================================================== | ||
| 17477 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c | ||
| 17478 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c | ||
| 17479 | @@ -3,7 +3,8 @@ | ||
| 17480 | |||
| 17481 | /* { dg-do assemble } */ | ||
| 17482 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17483 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17484 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17485 | +/* { dg-add-options arm_neon } */ | ||
| 17486 | |||
| 17487 | #include "arm_neon.h" | ||
| 17488 | |||
| 17489 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c | ||
| 17490 | =================================================================== | ||
| 17491 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c | ||
| 17492 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c | ||
| 17493 | @@ -3,7 +3,8 @@ | ||
| 17494 | |||
| 17495 | /* { dg-do assemble } */ | ||
| 17496 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17497 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17498 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17499 | +/* { dg-add-options arm_neon } */ | ||
| 17500 | |||
| 17501 | #include "arm_neon.h" | ||
| 17502 | |||
| 17503 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c | ||
| 17504 | =================================================================== | ||
| 17505 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c | ||
| 17506 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c | ||
| 17507 | @@ -3,7 +3,8 @@ | ||
| 17508 | |||
| 17509 | /* { dg-do assemble } */ | ||
| 17510 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17511 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17512 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17513 | +/* { dg-add-options arm_neon } */ | ||
| 17514 | |||
| 17515 | #include "arm_neon.h" | ||
| 17516 | |||
| 17517 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c | ||
| 17518 | =================================================================== | ||
| 17519 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c | ||
| 17520 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c | ||
| 17521 | @@ -3,7 +3,8 @@ | ||
| 17522 | |||
| 17523 | /* { dg-do assemble } */ | ||
| 17524 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17525 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17526 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17527 | +/* { dg-add-options arm_neon } */ | ||
| 17528 | |||
| 17529 | #include "arm_neon.h" | ||
| 17530 | |||
| 17531 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c | ||
| 17532 | =================================================================== | ||
| 17533 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c | ||
| 17534 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c | ||
| 17535 | @@ -3,7 +3,8 @@ | ||
| 17536 | |||
| 17537 | /* { dg-do assemble } */ | ||
| 17538 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17539 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17540 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17541 | +/* { dg-add-options arm_neon } */ | ||
| 17542 | |||
| 17543 | #include "arm_neon.h" | ||
| 17544 | |||
| 17545 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c | ||
| 17546 | =================================================================== | ||
| 17547 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c | ||
| 17548 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c | ||
| 17549 | @@ -3,7 +3,8 @@ | ||
| 17550 | |||
| 17551 | /* { dg-do assemble } */ | ||
| 17552 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17553 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17554 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17555 | +/* { dg-add-options arm_neon } */ | ||
| 17556 | |||
| 17557 | #include "arm_neon.h" | ||
| 17558 | |||
| 17559 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c | ||
| 17560 | =================================================================== | ||
| 17561 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c | ||
| 17562 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c | ||
| 17563 | @@ -3,7 +3,8 @@ | ||
| 17564 | |||
| 17565 | /* { dg-do assemble } */ | ||
| 17566 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17567 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17568 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17569 | +/* { dg-add-options arm_neon } */ | ||
| 17570 | |||
| 17571 | #include "arm_neon.h" | ||
| 17572 | |||
| 17573 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c | ||
| 17574 | =================================================================== | ||
| 17575 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c | ||
| 17576 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c | ||
| 17577 | @@ -3,7 +3,8 @@ | ||
| 17578 | |||
| 17579 | /* { dg-do assemble } */ | ||
| 17580 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17581 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17582 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17583 | +/* { dg-add-options arm_neon } */ | ||
| 17584 | |||
| 17585 | #include "arm_neon.h" | ||
| 17586 | |||
| 17587 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c | ||
| 17588 | =================================================================== | ||
| 17589 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c | ||
| 17590 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c | ||
| 17591 | @@ -3,7 +3,8 @@ | ||
| 17592 | |||
| 17593 | /* { dg-do assemble } */ | ||
| 17594 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17595 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17596 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17597 | +/* { dg-add-options arm_neon } */ | ||
| 17598 | |||
| 17599 | #include "arm_neon.h" | ||
| 17600 | |||
| 17601 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c | ||
| 17602 | =================================================================== | ||
| 17603 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c | ||
| 17604 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c | ||
| 17605 | @@ -3,7 +3,8 @@ | ||
| 17606 | |||
| 17607 | /* { dg-do assemble } */ | ||
| 17608 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17609 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17610 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17611 | +/* { dg-add-options arm_neon } */ | ||
| 17612 | |||
| 17613 | #include "arm_neon.h" | ||
| 17614 | |||
| 17615 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c | ||
| 17616 | =================================================================== | ||
| 17617 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c | ||
| 17618 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c | ||
| 17619 | @@ -3,7 +3,8 @@ | ||
| 17620 | |||
| 17621 | /* { dg-do assemble } */ | ||
| 17622 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17623 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17624 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17625 | +/* { dg-add-options arm_neon } */ | ||
| 17626 | |||
| 17627 | #include "arm_neon.h" | ||
| 17628 | |||
| 17629 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c | ||
| 17630 | =================================================================== | ||
| 17631 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c | ||
| 17632 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c | ||
| 17633 | @@ -3,7 +3,8 @@ | ||
| 17634 | |||
| 17635 | /* { dg-do assemble } */ | ||
| 17636 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17637 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17638 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17639 | +/* { dg-add-options arm_neon } */ | ||
| 17640 | |||
| 17641 | #include "arm_neon.h" | ||
| 17642 | |||
| 17643 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c | ||
| 17644 | =================================================================== | ||
| 17645 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c | ||
| 17646 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c | ||
| 17647 | @@ -3,7 +3,8 @@ | ||
| 17648 | |||
| 17649 | /* { dg-do assemble } */ | ||
| 17650 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17651 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17652 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17653 | +/* { dg-add-options arm_neon } */ | ||
| 17654 | |||
| 17655 | #include "arm_neon.h" | ||
| 17656 | |||
| 17657 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c | ||
| 17658 | =================================================================== | ||
| 17659 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c | ||
| 17660 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c | ||
| 17661 | @@ -3,7 +3,8 @@ | ||
| 17662 | |||
| 17663 | /* { dg-do assemble } */ | ||
| 17664 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17665 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17666 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17667 | +/* { dg-add-options arm_neon } */ | ||
| 17668 | |||
| 17669 | #include "arm_neon.h" | ||
| 17670 | |||
| 17671 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c | ||
| 17672 | =================================================================== | ||
| 17673 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c | ||
| 17674 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c | ||
| 17675 | @@ -3,7 +3,8 @@ | ||
| 17676 | |||
| 17677 | /* { dg-do assemble } */ | ||
| 17678 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17679 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17680 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17681 | +/* { dg-add-options arm_neon } */ | ||
| 17682 | |||
| 17683 | #include "arm_neon.h" | ||
| 17684 | |||
| 17685 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c | ||
| 17686 | =================================================================== | ||
| 17687 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c | ||
| 17688 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c | ||
| 17689 | @@ -3,7 +3,8 @@ | ||
| 17690 | |||
| 17691 | /* { dg-do assemble } */ | ||
| 17692 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17693 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17694 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17695 | +/* { dg-add-options arm_neon } */ | ||
| 17696 | |||
| 17697 | #include "arm_neon.h" | ||
| 17698 | |||
| 17699 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c | ||
| 17700 | =================================================================== | ||
| 17701 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c | ||
| 17702 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c | ||
| 17703 | @@ -3,7 +3,8 @@ | ||
| 17704 | |||
| 17705 | /* { dg-do assemble } */ | ||
| 17706 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17707 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17708 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17709 | +/* { dg-add-options arm_neon } */ | ||
| 17710 | |||
| 17711 | #include "arm_neon.h" | ||
| 17712 | |||
| 17713 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c | ||
| 17714 | =================================================================== | ||
| 17715 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c | ||
| 17716 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c | ||
| 17717 | @@ -3,7 +3,8 @@ | ||
| 17718 | |||
| 17719 | /* { dg-do assemble } */ | ||
| 17720 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17721 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17722 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17723 | +/* { dg-add-options arm_neon } */ | ||
| 17724 | |||
| 17725 | #include "arm_neon.h" | ||
| 17726 | |||
| 17727 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c | ||
| 17728 | =================================================================== | ||
| 17729 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c | ||
| 17730 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c | ||
| 17731 | @@ -3,7 +3,8 @@ | ||
| 17732 | |||
| 17733 | /* { dg-do assemble } */ | ||
| 17734 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17735 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17736 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17737 | +/* { dg-add-options arm_neon } */ | ||
| 17738 | |||
| 17739 | #include "arm_neon.h" | ||
| 17740 | |||
| 17741 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c | ||
| 17742 | =================================================================== | ||
| 17743 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c | ||
| 17744 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c | ||
| 17745 | @@ -3,7 +3,8 @@ | ||
| 17746 | |||
| 17747 | /* { dg-do assemble } */ | ||
| 17748 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17749 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17750 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17751 | +/* { dg-add-options arm_neon } */ | ||
| 17752 | |||
| 17753 | #include "arm_neon.h" | ||
| 17754 | |||
| 17755 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c | ||
| 17756 | =================================================================== | ||
| 17757 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c | ||
| 17758 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c | ||
| 17759 | @@ -3,7 +3,8 @@ | ||
| 17760 | |||
| 17761 | /* { dg-do assemble } */ | ||
| 17762 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17763 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17764 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17765 | +/* { dg-add-options arm_neon } */ | ||
| 17766 | |||
| 17767 | #include "arm_neon.h" | ||
| 17768 | |||
| 17769 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c | ||
| 17770 | =================================================================== | ||
| 17771 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c | ||
| 17772 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c | ||
| 17773 | @@ -3,7 +3,8 @@ | ||
| 17774 | |||
| 17775 | /* { dg-do assemble } */ | ||
| 17776 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17777 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17778 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17779 | +/* { dg-add-options arm_neon } */ | ||
| 17780 | |||
| 17781 | #include "arm_neon.h" | ||
| 17782 | |||
| 17783 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c | ||
| 17784 | =================================================================== | ||
| 17785 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c | ||
| 17786 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c | ||
| 17787 | @@ -3,7 +3,8 @@ | ||
| 17788 | |||
| 17789 | /* { dg-do assemble } */ | ||
| 17790 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17791 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17792 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17793 | +/* { dg-add-options arm_neon } */ | ||
| 17794 | |||
| 17795 | #include "arm_neon.h" | ||
| 17796 | |||
| 17797 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c | ||
| 17798 | =================================================================== | ||
| 17799 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c | ||
| 17800 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c | ||
| 17801 | @@ -3,7 +3,8 @@ | ||
| 17802 | |||
| 17803 | /* { dg-do assemble } */ | ||
| 17804 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17805 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17806 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17807 | +/* { dg-add-options arm_neon } */ | ||
| 17808 | |||
| 17809 | #include "arm_neon.h" | ||
| 17810 | |||
| 17811 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c | ||
| 17812 | =================================================================== | ||
| 17813 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c | ||
| 17814 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c | ||
| 17815 | @@ -3,7 +3,8 @@ | ||
| 17816 | |||
| 17817 | /* { dg-do assemble } */ | ||
| 17818 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17819 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17820 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17821 | +/* { dg-add-options arm_neon } */ | ||
| 17822 | |||
| 17823 | #include "arm_neon.h" | ||
| 17824 | |||
| 17825 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c | ||
| 17826 | =================================================================== | ||
| 17827 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c | ||
| 17828 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c | ||
| 17829 | @@ -3,7 +3,8 @@ | ||
| 17830 | |||
| 17831 | /* { dg-do assemble } */ | ||
| 17832 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17833 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17834 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17835 | +/* { dg-add-options arm_neon } */ | ||
| 17836 | |||
| 17837 | #include "arm_neon.h" | ||
| 17838 | |||
| 17839 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c | ||
| 17840 | =================================================================== | ||
| 17841 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c | ||
| 17842 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c | ||
| 17843 | @@ -3,7 +3,8 @@ | ||
| 17844 | |||
| 17845 | /* { dg-do assemble } */ | ||
| 17846 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17847 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17848 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17849 | +/* { dg-add-options arm_neon } */ | ||
| 17850 | |||
| 17851 | #include "arm_neon.h" | ||
| 17852 | |||
| 17853 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c | ||
| 17854 | =================================================================== | ||
| 17855 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c | ||
| 17856 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c | ||
| 17857 | @@ -3,7 +3,8 @@ | ||
| 17858 | |||
| 17859 | /* { dg-do assemble } */ | ||
| 17860 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17861 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17862 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17863 | +/* { dg-add-options arm_neon } */ | ||
| 17864 | |||
| 17865 | #include "arm_neon.h" | ||
| 17866 | |||
| 17867 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c | ||
| 17868 | =================================================================== | ||
| 17869 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c | ||
| 17870 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c | ||
| 17871 | @@ -3,7 +3,8 @@ | ||
| 17872 | |||
| 17873 | /* { dg-do assemble } */ | ||
| 17874 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17875 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17876 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17877 | +/* { dg-add-options arm_neon } */ | ||
| 17878 | |||
| 17879 | #include "arm_neon.h" | ||
| 17880 | |||
| 17881 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c | ||
| 17882 | =================================================================== | ||
| 17883 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c | ||
| 17884 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c | ||
| 17885 | @@ -3,7 +3,8 @@ | ||
| 17886 | |||
| 17887 | /* { dg-do assemble } */ | ||
| 17888 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17889 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17890 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17891 | +/* { dg-add-options arm_neon } */ | ||
| 17892 | |||
| 17893 | #include "arm_neon.h" | ||
| 17894 | |||
| 17895 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c | ||
| 17896 | =================================================================== | ||
| 17897 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c | ||
| 17898 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c | ||
| 17899 | @@ -3,7 +3,8 @@ | ||
| 17900 | |||
| 17901 | /* { dg-do assemble } */ | ||
| 17902 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17903 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17904 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17905 | +/* { dg-add-options arm_neon } */ | ||
| 17906 | |||
| 17907 | #include "arm_neon.h" | ||
| 17908 | |||
| 17909 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c | ||
| 17910 | =================================================================== | ||
| 17911 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c | ||
| 17912 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c | ||
| 17913 | @@ -3,7 +3,8 @@ | ||
| 17914 | |||
| 17915 | /* { dg-do assemble } */ | ||
| 17916 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17917 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17918 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17919 | +/* { dg-add-options arm_neon } */ | ||
| 17920 | |||
| 17921 | #include "arm_neon.h" | ||
| 17922 | |||
| 17923 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c | ||
| 17924 | =================================================================== | ||
| 17925 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c | ||
| 17926 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c | ||
| 17927 | @@ -3,7 +3,8 @@ | ||
| 17928 | |||
| 17929 | /* { dg-do assemble } */ | ||
| 17930 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17931 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17932 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17933 | +/* { dg-add-options arm_neon } */ | ||
| 17934 | |||
| 17935 | #include "arm_neon.h" | ||
| 17936 | |||
| 17937 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c | ||
| 17938 | =================================================================== | ||
| 17939 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c | ||
| 17940 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c | ||
| 17941 | @@ -3,7 +3,8 @@ | ||
| 17942 | |||
| 17943 | /* { dg-do assemble } */ | ||
| 17944 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17945 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17946 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17947 | +/* { dg-add-options arm_neon } */ | ||
| 17948 | |||
| 17949 | #include "arm_neon.h" | ||
| 17950 | |||
| 17951 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c | ||
| 17952 | =================================================================== | ||
| 17953 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c | ||
| 17954 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c | ||
| 17955 | @@ -3,7 +3,8 @@ | ||
| 17956 | |||
| 17957 | /* { dg-do assemble } */ | ||
| 17958 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17959 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17960 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17961 | +/* { dg-add-options arm_neon } */ | ||
| 17962 | |||
| 17963 | #include "arm_neon.h" | ||
| 17964 | |||
| 17965 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c | ||
| 17966 | =================================================================== | ||
| 17967 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c | ||
| 17968 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c | ||
| 17969 | @@ -3,7 +3,8 @@ | ||
| 17970 | |||
| 17971 | /* { dg-do assemble } */ | ||
| 17972 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17973 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17974 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17975 | +/* { dg-add-options arm_neon } */ | ||
| 17976 | |||
| 17977 | #include "arm_neon.h" | ||
| 17978 | |||
| 17979 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c | ||
| 17980 | =================================================================== | ||
| 17981 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c | ||
| 17982 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c | ||
| 17983 | @@ -3,7 +3,8 @@ | ||
| 17984 | |||
| 17985 | /* { dg-do assemble } */ | ||
| 17986 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 17987 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 17988 | +/* { dg-options "-save-temps -O0" } */ | ||
| 17989 | +/* { dg-add-options arm_neon } */ | ||
| 17990 | |||
| 17991 | #include "arm_neon.h" | ||
| 17992 | |||
| 17993 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c | ||
| 17994 | =================================================================== | ||
| 17995 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c | ||
| 17996 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c | ||
| 17997 | @@ -3,7 +3,8 @@ | ||
| 17998 | |||
| 17999 | /* { dg-do assemble } */ | ||
| 18000 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18001 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18002 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18003 | +/* { dg-add-options arm_neon } */ | ||
| 18004 | |||
| 18005 | #include "arm_neon.h" | ||
| 18006 | |||
| 18007 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c | ||
| 18008 | =================================================================== | ||
| 18009 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c | ||
| 18010 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c | ||
| 18011 | @@ -3,7 +3,8 @@ | ||
| 18012 | |||
| 18013 | /* { dg-do assemble } */ | ||
| 18014 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18015 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18016 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18017 | +/* { dg-add-options arm_neon } */ | ||
| 18018 | |||
| 18019 | #include "arm_neon.h" | ||
| 18020 | |||
| 18021 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c | ||
| 18022 | =================================================================== | ||
| 18023 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c | ||
| 18024 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c | ||
| 18025 | @@ -3,7 +3,8 @@ | ||
| 18026 | |||
| 18027 | /* { dg-do assemble } */ | ||
| 18028 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18029 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18030 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18031 | +/* { dg-add-options arm_neon } */ | ||
| 18032 | |||
| 18033 | #include "arm_neon.h" | ||
| 18034 | |||
| 18035 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c | ||
| 18036 | =================================================================== | ||
| 18037 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c | ||
| 18038 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c | ||
| 18039 | @@ -3,7 +3,8 @@ | ||
| 18040 | |||
| 18041 | /* { dg-do assemble } */ | ||
| 18042 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18043 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18044 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18045 | +/* { dg-add-options arm_neon } */ | ||
| 18046 | |||
| 18047 | #include "arm_neon.h" | ||
| 18048 | |||
| 18049 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c | ||
| 18050 | =================================================================== | ||
| 18051 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c | ||
| 18052 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c | ||
| 18053 | @@ -3,7 +3,8 @@ | ||
| 18054 | |||
| 18055 | /* { dg-do assemble } */ | ||
| 18056 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18057 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18058 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18059 | +/* { dg-add-options arm_neon } */ | ||
| 18060 | |||
| 18061 | #include "arm_neon.h" | ||
| 18062 | |||
| 18063 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c | ||
| 18064 | =================================================================== | ||
| 18065 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c | ||
| 18066 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c | ||
| 18067 | @@ -3,7 +3,8 @@ | ||
| 18068 | |||
| 18069 | /* { dg-do assemble } */ | ||
| 18070 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18071 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18072 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18073 | +/* { dg-add-options arm_neon } */ | ||
| 18074 | |||
| 18075 | #include "arm_neon.h" | ||
| 18076 | |||
| 18077 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c | ||
| 18078 | =================================================================== | ||
| 18079 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c | ||
| 18080 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c | ||
| 18081 | @@ -3,7 +3,8 @@ | ||
| 18082 | |||
| 18083 | /* { dg-do assemble } */ | ||
| 18084 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18085 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18086 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18087 | +/* { dg-add-options arm_neon } */ | ||
| 18088 | |||
| 18089 | #include "arm_neon.h" | ||
| 18090 | |||
| 18091 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c | ||
| 18092 | =================================================================== | ||
| 18093 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c | ||
| 18094 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c | ||
| 18095 | @@ -3,7 +3,8 @@ | ||
| 18096 | |||
| 18097 | /* { dg-do assemble } */ | ||
| 18098 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18099 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18100 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18101 | +/* { dg-add-options arm_neon } */ | ||
| 18102 | |||
| 18103 | #include "arm_neon.h" | ||
| 18104 | |||
| 18105 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c | ||
| 18106 | =================================================================== | ||
| 18107 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c | ||
| 18108 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c | ||
| 18109 | @@ -3,7 +3,8 @@ | ||
| 18110 | |||
| 18111 | /* { dg-do assemble } */ | ||
| 18112 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18113 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18114 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18115 | +/* { dg-add-options arm_neon } */ | ||
| 18116 | |||
| 18117 | #include "arm_neon.h" | ||
| 18118 | |||
| 18119 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c | ||
| 18120 | =================================================================== | ||
| 18121 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c | ||
| 18122 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c | ||
| 18123 | @@ -3,7 +3,8 @@ | ||
| 18124 | |||
| 18125 | /* { dg-do assemble } */ | ||
| 18126 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18127 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18128 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18129 | +/* { dg-add-options arm_neon } */ | ||
| 18130 | |||
| 18131 | #include "arm_neon.h" | ||
| 18132 | |||
| 18133 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c | ||
| 18134 | =================================================================== | ||
| 18135 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c | ||
| 18136 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c | ||
| 18137 | @@ -3,7 +3,8 @@ | ||
| 18138 | |||
| 18139 | /* { dg-do assemble } */ | ||
| 18140 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18141 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18142 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18143 | +/* { dg-add-options arm_neon } */ | ||
| 18144 | |||
| 18145 | #include "arm_neon.h" | ||
| 18146 | |||
| 18147 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c | ||
| 18148 | =================================================================== | ||
| 18149 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c | ||
| 18150 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c | ||
| 18151 | @@ -3,7 +3,8 @@ | ||
| 18152 | |||
| 18153 | /* { dg-do assemble } */ | ||
| 18154 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18155 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18156 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18157 | +/* { dg-add-options arm_neon } */ | ||
| 18158 | |||
| 18159 | #include "arm_neon.h" | ||
| 18160 | |||
| 18161 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c | ||
| 18162 | =================================================================== | ||
| 18163 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c | ||
| 18164 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c | ||
| 18165 | @@ -3,7 +3,8 @@ | ||
| 18166 | |||
| 18167 | /* { dg-do assemble } */ | ||
| 18168 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18169 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18170 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18171 | +/* { dg-add-options arm_neon } */ | ||
| 18172 | |||
| 18173 | #include "arm_neon.h" | ||
| 18174 | |||
| 18175 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c | ||
| 18176 | =================================================================== | ||
| 18177 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c | ||
| 18178 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c | ||
| 18179 | @@ -3,7 +3,8 @@ | ||
| 18180 | |||
| 18181 | /* { dg-do assemble } */ | ||
| 18182 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18183 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18184 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18185 | +/* { dg-add-options arm_neon } */ | ||
| 18186 | |||
| 18187 | #include "arm_neon.h" | ||
| 18188 | |||
| 18189 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c | ||
| 18190 | =================================================================== | ||
| 18191 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c | ||
| 18192 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c | ||
| 18193 | @@ -3,7 +3,8 @@ | ||
| 18194 | |||
| 18195 | /* { dg-do assemble } */ | ||
| 18196 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18197 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18198 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18199 | +/* { dg-add-options arm_neon } */ | ||
| 18200 | |||
| 18201 | #include "arm_neon.h" | ||
| 18202 | |||
| 18203 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c | ||
| 18204 | =================================================================== | ||
| 18205 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c | ||
| 18206 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c | ||
| 18207 | @@ -3,7 +3,8 @@ | ||
| 18208 | |||
| 18209 | /* { dg-do assemble } */ | ||
| 18210 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18211 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18212 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18213 | +/* { dg-add-options arm_neon } */ | ||
| 18214 | |||
| 18215 | #include "arm_neon.h" | ||
| 18216 | |||
| 18217 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c | ||
| 18218 | =================================================================== | ||
| 18219 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c | ||
| 18220 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c | ||
| 18221 | @@ -3,7 +3,8 @@ | ||
| 18222 | |||
| 18223 | /* { dg-do assemble } */ | ||
| 18224 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18225 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18226 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18227 | +/* { dg-add-options arm_neon } */ | ||
| 18228 | |||
| 18229 | #include "arm_neon.h" | ||
| 18230 | |||
| 18231 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c | ||
| 18232 | =================================================================== | ||
| 18233 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c | ||
| 18234 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c | ||
| 18235 | @@ -3,7 +3,8 @@ | ||
| 18236 | |||
| 18237 | /* { dg-do assemble } */ | ||
| 18238 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18239 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18240 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18241 | +/* { dg-add-options arm_neon } */ | ||
| 18242 | |||
| 18243 | #include "arm_neon.h" | ||
| 18244 | |||
| 18245 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c | ||
| 18246 | =================================================================== | ||
| 18247 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c | ||
| 18248 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c | ||
| 18249 | @@ -3,7 +3,8 @@ | ||
| 18250 | |||
| 18251 | /* { dg-do assemble } */ | ||
| 18252 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18253 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18254 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18255 | +/* { dg-add-options arm_neon } */ | ||
| 18256 | |||
| 18257 | #include "arm_neon.h" | ||
| 18258 | |||
| 18259 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c | ||
| 18260 | =================================================================== | ||
| 18261 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c | ||
| 18262 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c | ||
| 18263 | @@ -3,7 +3,8 @@ | ||
| 18264 | |||
| 18265 | /* { dg-do assemble } */ | ||
| 18266 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18267 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18268 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18269 | +/* { dg-add-options arm_neon } */ | ||
| 18270 | |||
| 18271 | #include "arm_neon.h" | ||
| 18272 | |||
| 18273 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c | ||
| 18274 | =================================================================== | ||
| 18275 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c | ||
| 18276 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c | ||
| 18277 | @@ -3,7 +3,8 @@ | ||
| 18278 | |||
| 18279 | /* { dg-do assemble } */ | ||
| 18280 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18281 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18282 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18283 | +/* { dg-add-options arm_neon } */ | ||
| 18284 | |||
| 18285 | #include "arm_neon.h" | ||
| 18286 | |||
| 18287 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c | ||
| 18288 | =================================================================== | ||
| 18289 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c | ||
| 18290 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c | ||
| 18291 | @@ -3,7 +3,8 @@ | ||
| 18292 | |||
| 18293 | /* { dg-do assemble } */ | ||
| 18294 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18295 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18296 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18297 | +/* { dg-add-options arm_neon } */ | ||
| 18298 | |||
| 18299 | #include "arm_neon.h" | ||
| 18300 | |||
| 18301 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c | ||
| 18302 | =================================================================== | ||
| 18303 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c | ||
| 18304 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c | ||
| 18305 | @@ -3,7 +3,8 @@ | ||
| 18306 | |||
| 18307 | /* { dg-do assemble } */ | ||
| 18308 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18309 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18310 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18311 | +/* { dg-add-options arm_neon } */ | ||
| 18312 | |||
| 18313 | #include "arm_neon.h" | ||
| 18314 | |||
| 18315 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c | ||
| 18316 | =================================================================== | ||
| 18317 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c | ||
| 18318 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c | ||
| 18319 | @@ -3,7 +3,8 @@ | ||
| 18320 | |||
| 18321 | /* { dg-do assemble } */ | ||
| 18322 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18323 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18324 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18325 | +/* { dg-add-options arm_neon } */ | ||
| 18326 | |||
| 18327 | #include "arm_neon.h" | ||
| 18328 | |||
| 18329 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c | ||
| 18330 | =================================================================== | ||
| 18331 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c | ||
| 18332 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c | ||
| 18333 | @@ -3,7 +3,8 @@ | ||
| 18334 | |||
| 18335 | /* { dg-do assemble } */ | ||
| 18336 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18337 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18338 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18339 | +/* { dg-add-options arm_neon } */ | ||
| 18340 | |||
| 18341 | #include "arm_neon.h" | ||
| 18342 | |||
| 18343 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c | ||
| 18344 | =================================================================== | ||
| 18345 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c | ||
| 18346 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c | ||
| 18347 | @@ -3,7 +3,8 @@ | ||
| 18348 | |||
| 18349 | /* { dg-do assemble } */ | ||
| 18350 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18351 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18352 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18353 | +/* { dg-add-options arm_neon } */ | ||
| 18354 | |||
| 18355 | #include "arm_neon.h" | ||
| 18356 | |||
| 18357 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c | ||
| 18358 | =================================================================== | ||
| 18359 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c | ||
| 18360 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c | ||
| 18361 | @@ -3,7 +3,8 @@ | ||
| 18362 | |||
| 18363 | /* { dg-do assemble } */ | ||
| 18364 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18365 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18366 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18367 | +/* { dg-add-options arm_neon } */ | ||
| 18368 | |||
| 18369 | #include "arm_neon.h" | ||
| 18370 | |||
| 18371 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c | ||
| 18372 | =================================================================== | ||
| 18373 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c | ||
| 18374 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c | ||
| 18375 | @@ -3,7 +3,8 @@ | ||
| 18376 | |||
| 18377 | /* { dg-do assemble } */ | ||
| 18378 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18379 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18380 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18381 | +/* { dg-add-options arm_neon } */ | ||
| 18382 | |||
| 18383 | #include "arm_neon.h" | ||
| 18384 | |||
| 18385 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c | ||
| 18386 | =================================================================== | ||
| 18387 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c | ||
| 18388 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c | ||
| 18389 | @@ -3,7 +3,8 @@ | ||
| 18390 | |||
| 18391 | /* { dg-do assemble } */ | ||
| 18392 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18393 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18394 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18395 | +/* { dg-add-options arm_neon } */ | ||
| 18396 | |||
| 18397 | #include "arm_neon.h" | ||
| 18398 | |||
| 18399 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c | ||
| 18400 | =================================================================== | ||
| 18401 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c | ||
| 18402 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c | ||
| 18403 | @@ -3,7 +3,8 @@ | ||
| 18404 | |||
| 18405 | /* { dg-do assemble } */ | ||
| 18406 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18407 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18408 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18409 | +/* { dg-add-options arm_neon } */ | ||
| 18410 | |||
| 18411 | #include "arm_neon.h" | ||
| 18412 | |||
| 18413 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c | ||
| 18414 | =================================================================== | ||
| 18415 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c | ||
| 18416 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c | ||
| 18417 | @@ -3,7 +3,8 @@ | ||
| 18418 | |||
| 18419 | /* { dg-do assemble } */ | ||
| 18420 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18421 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18422 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18423 | +/* { dg-add-options arm_neon } */ | ||
| 18424 | |||
| 18425 | #include "arm_neon.h" | ||
| 18426 | |||
| 18427 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c | ||
| 18428 | =================================================================== | ||
| 18429 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c | ||
| 18430 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c | ||
| 18431 | @@ -3,7 +3,8 @@ | ||
| 18432 | |||
| 18433 | /* { dg-do assemble } */ | ||
| 18434 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18435 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18436 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18437 | +/* { dg-add-options arm_neon } */ | ||
| 18438 | |||
| 18439 | #include "arm_neon.h" | ||
| 18440 | |||
| 18441 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c | ||
| 18442 | =================================================================== | ||
| 18443 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c | ||
| 18444 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c | ||
| 18445 | @@ -3,7 +3,8 @@ | ||
| 18446 | |||
| 18447 | /* { dg-do assemble } */ | ||
| 18448 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18449 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18450 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18451 | +/* { dg-add-options arm_neon } */ | ||
| 18452 | |||
| 18453 | #include "arm_neon.h" | ||
| 18454 | |||
| 18455 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c | ||
| 18456 | =================================================================== | ||
| 18457 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c | ||
| 18458 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c | ||
| 18459 | @@ -3,7 +3,8 @@ | ||
| 18460 | |||
| 18461 | /* { dg-do assemble } */ | ||
| 18462 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18463 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18464 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18465 | +/* { dg-add-options arm_neon } */ | ||
| 18466 | |||
| 18467 | #include "arm_neon.h" | ||
| 18468 | |||
| 18469 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c | ||
| 18470 | =================================================================== | ||
| 18471 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c | ||
| 18472 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c | ||
| 18473 | @@ -3,7 +3,8 @@ | ||
| 18474 | |||
| 18475 | /* { dg-do assemble } */ | ||
| 18476 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18477 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18478 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18479 | +/* { dg-add-options arm_neon } */ | ||
| 18480 | |||
| 18481 | #include "arm_neon.h" | ||
| 18482 | |||
| 18483 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c | ||
| 18484 | =================================================================== | ||
| 18485 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c | ||
| 18486 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c | ||
| 18487 | @@ -3,7 +3,8 @@ | ||
| 18488 | |||
| 18489 | /* { dg-do assemble } */ | ||
| 18490 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18491 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18492 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18493 | +/* { dg-add-options arm_neon } */ | ||
| 18494 | |||
| 18495 | #include "arm_neon.h" | ||
| 18496 | |||
| 18497 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c | ||
| 18498 | =================================================================== | ||
| 18499 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c | ||
| 18500 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c | ||
| 18501 | @@ -3,7 +3,8 @@ | ||
| 18502 | |||
| 18503 | /* { dg-do assemble } */ | ||
| 18504 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18505 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18506 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18507 | +/* { dg-add-options arm_neon } */ | ||
| 18508 | |||
| 18509 | #include "arm_neon.h" | ||
| 18510 | |||
| 18511 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c | ||
| 18512 | =================================================================== | ||
| 18513 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c | ||
| 18514 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c | ||
| 18515 | @@ -3,7 +3,8 @@ | ||
| 18516 | |||
| 18517 | /* { dg-do assemble } */ | ||
| 18518 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18519 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18520 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18521 | +/* { dg-add-options arm_neon } */ | ||
| 18522 | |||
| 18523 | #include "arm_neon.h" | ||
| 18524 | |||
| 18525 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c | ||
| 18526 | =================================================================== | ||
| 18527 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c | ||
| 18528 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c | ||
| 18529 | @@ -3,7 +3,8 @@ | ||
| 18530 | |||
| 18531 | /* { dg-do assemble } */ | ||
| 18532 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18533 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18534 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18535 | +/* { dg-add-options arm_neon } */ | ||
| 18536 | |||
| 18537 | #include "arm_neon.h" | ||
| 18538 | |||
| 18539 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c | ||
| 18540 | =================================================================== | ||
| 18541 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c | ||
| 18542 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c | ||
| 18543 | @@ -3,7 +3,8 @@ | ||
| 18544 | |||
| 18545 | /* { dg-do assemble } */ | ||
| 18546 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18547 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18548 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18549 | +/* { dg-add-options arm_neon } */ | ||
| 18550 | |||
| 18551 | #include "arm_neon.h" | ||
| 18552 | |||
| 18553 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c | ||
| 18554 | =================================================================== | ||
| 18555 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c | ||
| 18556 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c | ||
| 18557 | @@ -3,7 +3,8 @@ | ||
| 18558 | |||
| 18559 | /* { dg-do assemble } */ | ||
| 18560 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18561 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18562 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18563 | +/* { dg-add-options arm_neon } */ | ||
| 18564 | |||
| 18565 | #include "arm_neon.h" | ||
| 18566 | |||
| 18567 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c | ||
| 18568 | =================================================================== | ||
| 18569 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c | ||
| 18570 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c | ||
| 18571 | @@ -3,7 +3,8 @@ | ||
| 18572 | |||
| 18573 | /* { dg-do assemble } */ | ||
| 18574 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18575 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18576 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18577 | +/* { dg-add-options arm_neon } */ | ||
| 18578 | |||
| 18579 | #include "arm_neon.h" | ||
| 18580 | |||
| 18581 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c | ||
| 18582 | =================================================================== | ||
| 18583 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c | ||
| 18584 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c | ||
| 18585 | @@ -3,7 +3,8 @@ | ||
| 18586 | |||
| 18587 | /* { dg-do assemble } */ | ||
| 18588 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18589 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18590 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18591 | +/* { dg-add-options arm_neon } */ | ||
| 18592 | |||
| 18593 | #include "arm_neon.h" | ||
| 18594 | |||
| 18595 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c | ||
| 18596 | =================================================================== | ||
| 18597 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c | ||
| 18598 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c | ||
| 18599 | @@ -3,7 +3,8 @@ | ||
| 18600 | |||
| 18601 | /* { dg-do assemble } */ | ||
| 18602 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18603 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18604 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18605 | +/* { dg-add-options arm_neon } */ | ||
| 18606 | |||
| 18607 | #include "arm_neon.h" | ||
| 18608 | |||
| 18609 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c | ||
| 18610 | =================================================================== | ||
| 18611 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c | ||
| 18612 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c | ||
| 18613 | @@ -3,7 +3,8 @@ | ||
| 18614 | |||
| 18615 | /* { dg-do assemble } */ | ||
| 18616 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18617 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18618 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18619 | +/* { dg-add-options arm_neon } */ | ||
| 18620 | |||
| 18621 | #include "arm_neon.h" | ||
| 18622 | |||
| 18623 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c | ||
| 18624 | =================================================================== | ||
| 18625 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c | ||
| 18626 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c | ||
| 18627 | @@ -3,7 +3,8 @@ | ||
| 18628 | |||
| 18629 | /* { dg-do assemble } */ | ||
| 18630 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18631 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18632 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18633 | +/* { dg-add-options arm_neon } */ | ||
| 18634 | |||
| 18635 | #include "arm_neon.h" | ||
| 18636 | |||
| 18637 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c | ||
| 18638 | =================================================================== | ||
| 18639 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c | ||
| 18640 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c | ||
| 18641 | @@ -3,7 +3,8 @@ | ||
| 18642 | |||
| 18643 | /* { dg-do assemble } */ | ||
| 18644 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18645 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18646 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18647 | +/* { dg-add-options arm_neon } */ | ||
| 18648 | |||
| 18649 | #include "arm_neon.h" | ||
| 18650 | |||
| 18651 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c | ||
| 18652 | =================================================================== | ||
| 18653 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c | ||
| 18654 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c | ||
| 18655 | @@ -3,7 +3,8 @@ | ||
| 18656 | |||
| 18657 | /* { dg-do assemble } */ | ||
| 18658 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18659 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18660 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18661 | +/* { dg-add-options arm_neon } */ | ||
| 18662 | |||
| 18663 | #include "arm_neon.h" | ||
| 18664 | |||
| 18665 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c | ||
| 18666 | =================================================================== | ||
| 18667 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c | ||
| 18668 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c | ||
| 18669 | @@ -3,7 +3,8 @@ | ||
| 18670 | |||
| 18671 | /* { dg-do assemble } */ | ||
| 18672 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18673 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18674 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18675 | +/* { dg-add-options arm_neon } */ | ||
| 18676 | |||
| 18677 | #include "arm_neon.h" | ||
| 18678 | |||
| 18679 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c | ||
| 18680 | =================================================================== | ||
| 18681 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c | ||
| 18682 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c | ||
| 18683 | @@ -3,7 +3,8 @@ | ||
| 18684 | |||
| 18685 | /* { dg-do assemble } */ | ||
| 18686 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18687 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18688 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18689 | +/* { dg-add-options arm_neon } */ | ||
| 18690 | |||
| 18691 | #include "arm_neon.h" | ||
| 18692 | |||
| 18693 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c | ||
| 18694 | =================================================================== | ||
| 18695 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c | ||
| 18696 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c | ||
| 18697 | @@ -3,7 +3,8 @@ | ||
| 18698 | |||
| 18699 | /* { dg-do assemble } */ | ||
| 18700 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18701 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18702 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18703 | +/* { dg-add-options arm_neon } */ | ||
| 18704 | |||
| 18705 | #include "arm_neon.h" | ||
| 18706 | |||
| 18707 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c | ||
| 18708 | =================================================================== | ||
| 18709 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c | ||
| 18710 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c | ||
| 18711 | @@ -3,7 +3,8 @@ | ||
| 18712 | |||
| 18713 | /* { dg-do assemble } */ | ||
| 18714 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18715 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18716 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18717 | +/* { dg-add-options arm_neon } */ | ||
| 18718 | |||
| 18719 | #include "arm_neon.h" | ||
| 18720 | |||
| 18721 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c | ||
| 18722 | =================================================================== | ||
| 18723 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c | ||
| 18724 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c | ||
| 18725 | @@ -3,7 +3,8 @@ | ||
| 18726 | |||
| 18727 | /* { dg-do assemble } */ | ||
| 18728 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18729 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18730 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18731 | +/* { dg-add-options arm_neon } */ | ||
| 18732 | |||
| 18733 | #include "arm_neon.h" | ||
| 18734 | |||
| 18735 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c | ||
| 18736 | =================================================================== | ||
| 18737 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c | ||
| 18738 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c | ||
| 18739 | @@ -3,7 +3,8 @@ | ||
| 18740 | |||
| 18741 | /* { dg-do assemble } */ | ||
| 18742 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18743 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18744 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18745 | +/* { dg-add-options arm_neon } */ | ||
| 18746 | |||
| 18747 | #include "arm_neon.h" | ||
| 18748 | |||
| 18749 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c | ||
| 18750 | =================================================================== | ||
| 18751 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c | ||
| 18752 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c | ||
| 18753 | @@ -3,7 +3,8 @@ | ||
| 18754 | |||
| 18755 | /* { dg-do assemble } */ | ||
| 18756 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18757 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18758 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18759 | +/* { dg-add-options arm_neon } */ | ||
| 18760 | |||
| 18761 | #include "arm_neon.h" | ||
| 18762 | |||
| 18763 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c | ||
| 18764 | =================================================================== | ||
| 18765 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c | ||
| 18766 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c | ||
| 18767 | @@ -3,7 +3,8 @@ | ||
| 18768 | |||
| 18769 | /* { dg-do assemble } */ | ||
| 18770 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18771 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18772 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18773 | +/* { dg-add-options arm_neon } */ | ||
| 18774 | |||
| 18775 | #include "arm_neon.h" | ||
| 18776 | |||
| 18777 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c | ||
| 18778 | =================================================================== | ||
| 18779 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c | ||
| 18780 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c | ||
| 18781 | @@ -3,7 +3,8 @@ | ||
| 18782 | |||
| 18783 | /* { dg-do assemble } */ | ||
| 18784 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18785 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18786 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18787 | +/* { dg-add-options arm_neon } */ | ||
| 18788 | |||
| 18789 | #include "arm_neon.h" | ||
| 18790 | |||
| 18791 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c | ||
| 18792 | =================================================================== | ||
| 18793 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c | ||
| 18794 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c | ||
| 18795 | @@ -3,7 +3,8 @@ | ||
| 18796 | |||
| 18797 | /* { dg-do assemble } */ | ||
| 18798 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18799 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18800 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18801 | +/* { dg-add-options arm_neon } */ | ||
| 18802 | |||
| 18803 | #include "arm_neon.h" | ||
| 18804 | |||
| 18805 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c | ||
| 18806 | =================================================================== | ||
| 18807 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c | ||
| 18808 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c | ||
| 18809 | @@ -3,7 +3,8 @@ | ||
| 18810 | |||
| 18811 | /* { dg-do assemble } */ | ||
| 18812 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18813 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18814 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18815 | +/* { dg-add-options arm_neon } */ | ||
| 18816 | |||
| 18817 | #include "arm_neon.h" | ||
| 18818 | |||
| 18819 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c | ||
| 18820 | =================================================================== | ||
| 18821 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c | ||
| 18822 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c | ||
| 18823 | @@ -3,7 +3,8 @@ | ||
| 18824 | |||
| 18825 | /* { dg-do assemble } */ | ||
| 18826 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18827 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18828 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18829 | +/* { dg-add-options arm_neon } */ | ||
| 18830 | |||
| 18831 | #include "arm_neon.h" | ||
| 18832 | |||
| 18833 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c | ||
| 18834 | =================================================================== | ||
| 18835 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c | ||
| 18836 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c | ||
| 18837 | @@ -3,7 +3,8 @@ | ||
| 18838 | |||
| 18839 | /* { dg-do assemble } */ | ||
| 18840 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18841 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18842 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18843 | +/* { dg-add-options arm_neon } */ | ||
| 18844 | |||
| 18845 | #include "arm_neon.h" | ||
| 18846 | |||
| 18847 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c | ||
| 18848 | =================================================================== | ||
| 18849 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c | ||
| 18850 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c | ||
| 18851 | @@ -3,7 +3,8 @@ | ||
| 18852 | |||
| 18853 | /* { dg-do assemble } */ | ||
| 18854 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18855 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18856 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18857 | +/* { dg-add-options arm_neon } */ | ||
| 18858 | |||
| 18859 | #include "arm_neon.h" | ||
| 18860 | |||
| 18861 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c | ||
| 18862 | =================================================================== | ||
| 18863 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c | ||
| 18864 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c | ||
| 18865 | @@ -3,7 +3,8 @@ | ||
| 18866 | |||
| 18867 | /* { dg-do assemble } */ | ||
| 18868 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18869 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18870 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18871 | +/* { dg-add-options arm_neon } */ | ||
| 18872 | |||
| 18873 | #include "arm_neon.h" | ||
| 18874 | |||
| 18875 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c | ||
| 18876 | =================================================================== | ||
| 18877 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c | ||
| 18878 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c | ||
| 18879 | @@ -3,7 +3,8 @@ | ||
| 18880 | |||
| 18881 | /* { dg-do assemble } */ | ||
| 18882 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18883 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18884 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18885 | +/* { dg-add-options arm_neon } */ | ||
| 18886 | |||
| 18887 | #include "arm_neon.h" | ||
| 18888 | |||
| 18889 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c | ||
| 18890 | =================================================================== | ||
| 18891 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c | ||
| 18892 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c | ||
| 18893 | @@ -3,7 +3,8 @@ | ||
| 18894 | |||
| 18895 | /* { dg-do assemble } */ | ||
| 18896 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18897 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18898 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18899 | +/* { dg-add-options arm_neon } */ | ||
| 18900 | |||
| 18901 | #include "arm_neon.h" | ||
| 18902 | |||
| 18903 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c | ||
| 18904 | =================================================================== | ||
| 18905 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c | ||
| 18906 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c | ||
| 18907 | @@ -3,7 +3,8 @@ | ||
| 18908 | |||
| 18909 | /* { dg-do assemble } */ | ||
| 18910 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18911 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18912 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18913 | +/* { dg-add-options arm_neon } */ | ||
| 18914 | |||
| 18915 | #include "arm_neon.h" | ||
| 18916 | |||
| 18917 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c | ||
| 18918 | =================================================================== | ||
| 18919 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c | ||
| 18920 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c | ||
| 18921 | @@ -3,7 +3,8 @@ | ||
| 18922 | |||
| 18923 | /* { dg-do assemble } */ | ||
| 18924 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18925 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18926 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18927 | +/* { dg-add-options arm_neon } */ | ||
| 18928 | |||
| 18929 | #include "arm_neon.h" | ||
| 18930 | |||
| 18931 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c | ||
| 18932 | =================================================================== | ||
| 18933 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c | ||
| 18934 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c | ||
| 18935 | @@ -3,7 +3,8 @@ | ||
| 18936 | |||
| 18937 | /* { dg-do assemble } */ | ||
| 18938 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18939 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18940 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18941 | +/* { dg-add-options arm_neon } */ | ||
| 18942 | |||
| 18943 | #include "arm_neon.h" | ||
| 18944 | |||
| 18945 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c | ||
| 18946 | =================================================================== | ||
| 18947 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c | ||
| 18948 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c | ||
| 18949 | @@ -3,7 +3,8 @@ | ||
| 18950 | |||
| 18951 | /* { dg-do assemble } */ | ||
| 18952 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18953 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18954 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18955 | +/* { dg-add-options arm_neon } */ | ||
| 18956 | |||
| 18957 | #include "arm_neon.h" | ||
| 18958 | |||
| 18959 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c | ||
| 18960 | =================================================================== | ||
| 18961 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c | ||
| 18962 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c | ||
| 18963 | @@ -3,7 +3,8 @@ | ||
| 18964 | |||
| 18965 | /* { dg-do assemble } */ | ||
| 18966 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18967 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18968 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18969 | +/* { dg-add-options arm_neon } */ | ||
| 18970 | |||
| 18971 | #include "arm_neon.h" | ||
| 18972 | |||
| 18973 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c | ||
| 18974 | =================================================================== | ||
| 18975 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c | ||
| 18976 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c | ||
| 18977 | @@ -3,7 +3,8 @@ | ||
| 18978 | |||
| 18979 | /* { dg-do assemble } */ | ||
| 18980 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18981 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18982 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18983 | +/* { dg-add-options arm_neon } */ | ||
| 18984 | |||
| 18985 | #include "arm_neon.h" | ||
| 18986 | |||
| 18987 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c | ||
| 18988 | =================================================================== | ||
| 18989 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c | ||
| 18990 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c | ||
| 18991 | @@ -3,7 +3,8 @@ | ||
| 18992 | |||
| 18993 | /* { dg-do assemble } */ | ||
| 18994 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 18995 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 18996 | +/* { dg-options "-save-temps -O0" } */ | ||
| 18997 | +/* { dg-add-options arm_neon } */ | ||
| 18998 | |||
| 18999 | #include "arm_neon.h" | ||
| 19000 | |||
| 19001 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c | ||
| 19002 | =================================================================== | ||
| 19003 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c | ||
| 19004 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c | ||
| 19005 | @@ -3,7 +3,8 @@ | ||
| 19006 | |||
| 19007 | /* { dg-do assemble } */ | ||
| 19008 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19009 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19010 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19011 | +/* { dg-add-options arm_neon } */ | ||
| 19012 | |||
| 19013 | #include "arm_neon.h" | ||
| 19014 | |||
| 19015 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c | ||
| 19016 | =================================================================== | ||
| 19017 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c | ||
| 19018 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c | ||
| 19019 | @@ -3,7 +3,8 @@ | ||
| 19020 | |||
| 19021 | /* { dg-do assemble } */ | ||
| 19022 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19023 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19024 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19025 | +/* { dg-add-options arm_neon } */ | ||
| 19026 | |||
| 19027 | #include "arm_neon.h" | ||
| 19028 | |||
| 19029 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c | ||
| 19030 | =================================================================== | ||
| 19031 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c | ||
| 19032 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c | ||
| 19033 | @@ -3,7 +3,8 @@ | ||
| 19034 | |||
| 19035 | /* { dg-do assemble } */ | ||
| 19036 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19037 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19038 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19039 | +/* { dg-add-options arm_neon } */ | ||
| 19040 | |||
| 19041 | #include "arm_neon.h" | ||
| 19042 | |||
| 19043 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c | ||
| 19044 | =================================================================== | ||
| 19045 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c | ||
| 19046 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c | ||
| 19047 | @@ -3,7 +3,8 @@ | ||
| 19048 | |||
| 19049 | /* { dg-do assemble } */ | ||
| 19050 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19051 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19052 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19053 | +/* { dg-add-options arm_neon } */ | ||
| 19054 | |||
| 19055 | #include "arm_neon.h" | ||
| 19056 | |||
| 19057 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c | ||
| 19058 | =================================================================== | ||
| 19059 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c | ||
| 19060 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c | ||
| 19061 | @@ -3,7 +3,8 @@ | ||
| 19062 | |||
| 19063 | /* { dg-do assemble } */ | ||
| 19064 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19065 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19066 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19067 | +/* { dg-add-options arm_neon } */ | ||
| 19068 | |||
| 19069 | #include "arm_neon.h" | ||
| 19070 | |||
| 19071 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c | ||
| 19072 | =================================================================== | ||
| 19073 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c | ||
| 19074 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c | ||
| 19075 | @@ -3,7 +3,8 @@ | ||
| 19076 | |||
| 19077 | /* { dg-do assemble } */ | ||
| 19078 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19079 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19080 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19081 | +/* { dg-add-options arm_neon } */ | ||
| 19082 | |||
| 19083 | #include "arm_neon.h" | ||
| 19084 | |||
| 19085 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c | ||
| 19086 | =================================================================== | ||
| 19087 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c | ||
| 19088 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c | ||
| 19089 | @@ -3,7 +3,8 @@ | ||
| 19090 | |||
| 19091 | /* { dg-do assemble } */ | ||
| 19092 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19093 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19094 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19095 | +/* { dg-add-options arm_neon } */ | ||
| 19096 | |||
| 19097 | #include "arm_neon.h" | ||
| 19098 | |||
| 19099 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c | ||
| 19100 | =================================================================== | ||
| 19101 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c | ||
| 19102 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c | ||
| 19103 | @@ -3,7 +3,8 @@ | ||
| 19104 | |||
| 19105 | /* { dg-do assemble } */ | ||
| 19106 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19107 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19108 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19109 | +/* { dg-add-options arm_neon } */ | ||
| 19110 | |||
| 19111 | #include "arm_neon.h" | ||
| 19112 | |||
| 19113 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c | ||
| 19114 | =================================================================== | ||
| 19115 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c | ||
| 19116 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c | ||
| 19117 | @@ -3,7 +3,8 @@ | ||
| 19118 | |||
| 19119 | /* { dg-do assemble } */ | ||
| 19120 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19121 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19122 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19123 | +/* { dg-add-options arm_neon } */ | ||
| 19124 | |||
| 19125 | #include "arm_neon.h" | ||
| 19126 | |||
| 19127 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c | ||
| 19128 | =================================================================== | ||
| 19129 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c | ||
| 19130 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c | ||
| 19131 | @@ -3,7 +3,8 @@ | ||
| 19132 | |||
| 19133 | /* { dg-do assemble } */ | ||
| 19134 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19135 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19136 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19137 | +/* { dg-add-options arm_neon } */ | ||
| 19138 | |||
| 19139 | #include "arm_neon.h" | ||
| 19140 | |||
| 19141 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c | ||
| 19142 | =================================================================== | ||
| 19143 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c | ||
| 19144 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c | ||
| 19145 | @@ -3,7 +3,8 @@ | ||
| 19146 | |||
| 19147 | /* { dg-do assemble } */ | ||
| 19148 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19149 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19150 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19151 | +/* { dg-add-options arm_neon } */ | ||
| 19152 | |||
| 19153 | #include "arm_neon.h" | ||
| 19154 | |||
| 19155 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c | ||
| 19156 | =================================================================== | ||
| 19157 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c | ||
| 19158 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c | ||
| 19159 | @@ -3,7 +3,8 @@ | ||
| 19160 | |||
| 19161 | /* { dg-do assemble } */ | ||
| 19162 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19163 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19164 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19165 | +/* { dg-add-options arm_neon } */ | ||
| 19166 | |||
| 19167 | #include "arm_neon.h" | ||
| 19168 | |||
| 19169 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c | ||
| 19170 | =================================================================== | ||
| 19171 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c | ||
| 19172 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c | ||
| 19173 | @@ -3,7 +3,8 @@ | ||
| 19174 | |||
| 19175 | /* { dg-do assemble } */ | ||
| 19176 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19177 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19178 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19179 | +/* { dg-add-options arm_neon } */ | ||
| 19180 | |||
| 19181 | #include "arm_neon.h" | ||
| 19182 | |||
| 19183 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c | ||
| 19184 | =================================================================== | ||
| 19185 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c | ||
| 19186 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c | ||
| 19187 | @@ -3,7 +3,8 @@ | ||
| 19188 | |||
| 19189 | /* { dg-do assemble } */ | ||
| 19190 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19191 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19192 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19193 | +/* { dg-add-options arm_neon } */ | ||
| 19194 | |||
| 19195 | #include "arm_neon.h" | ||
| 19196 | |||
| 19197 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c | ||
| 19198 | =================================================================== | ||
| 19199 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c | ||
| 19200 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c | ||
| 19201 | @@ -3,7 +3,8 @@ | ||
| 19202 | |||
| 19203 | /* { dg-do assemble } */ | ||
| 19204 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19205 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19206 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19207 | +/* { dg-add-options arm_neon } */ | ||
| 19208 | |||
| 19209 | #include "arm_neon.h" | ||
| 19210 | |||
| 19211 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c | ||
| 19212 | =================================================================== | ||
| 19213 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c | ||
| 19214 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c | ||
| 19215 | @@ -3,7 +3,8 @@ | ||
| 19216 | |||
| 19217 | /* { dg-do assemble } */ | ||
| 19218 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19219 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19220 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19221 | +/* { dg-add-options arm_neon } */ | ||
| 19222 | |||
| 19223 | #include "arm_neon.h" | ||
| 19224 | |||
| 19225 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c | ||
| 19226 | =================================================================== | ||
| 19227 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c | ||
| 19228 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c | ||
| 19229 | @@ -3,7 +3,8 @@ | ||
| 19230 | |||
| 19231 | /* { dg-do assemble } */ | ||
| 19232 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19233 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19234 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19235 | +/* { dg-add-options arm_neon } */ | ||
| 19236 | |||
| 19237 | #include "arm_neon.h" | ||
| 19238 | |||
| 19239 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c | ||
| 19240 | =================================================================== | ||
| 19241 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c | ||
| 19242 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c | ||
| 19243 | @@ -3,7 +3,8 @@ | ||
| 19244 | |||
| 19245 | /* { dg-do assemble } */ | ||
| 19246 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19247 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19248 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19249 | +/* { dg-add-options arm_neon } */ | ||
| 19250 | |||
| 19251 | #include "arm_neon.h" | ||
| 19252 | |||
| 19253 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c | ||
| 19254 | =================================================================== | ||
| 19255 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c | ||
| 19256 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c | ||
| 19257 | @@ -3,7 +3,8 @@ | ||
| 19258 | |||
| 19259 | /* { dg-do assemble } */ | ||
| 19260 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19261 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19262 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19263 | +/* { dg-add-options arm_neon } */ | ||
| 19264 | |||
| 19265 | #include "arm_neon.h" | ||
| 19266 | |||
| 19267 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c | ||
| 19268 | =================================================================== | ||
| 19269 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c | ||
| 19270 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c | ||
| 19271 | @@ -3,7 +3,8 @@ | ||
| 19272 | |||
| 19273 | /* { dg-do assemble } */ | ||
| 19274 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19275 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19276 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19277 | +/* { dg-add-options arm_neon } */ | ||
| 19278 | |||
| 19279 | #include "arm_neon.h" | ||
| 19280 | |||
| 19281 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c | ||
| 19282 | =================================================================== | ||
| 19283 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c | ||
| 19284 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c | ||
| 19285 | @@ -3,7 +3,8 @@ | ||
| 19286 | |||
| 19287 | /* { dg-do assemble } */ | ||
| 19288 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19289 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19290 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19291 | +/* { dg-add-options arm_neon } */ | ||
| 19292 | |||
| 19293 | #include "arm_neon.h" | ||
| 19294 | |||
| 19295 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c | ||
| 19296 | =================================================================== | ||
| 19297 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c | ||
| 19298 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c | ||
| 19299 | @@ -3,7 +3,8 @@ | ||
| 19300 | |||
| 19301 | /* { dg-do assemble } */ | ||
| 19302 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19303 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19304 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19305 | +/* { dg-add-options arm_neon } */ | ||
| 19306 | |||
| 19307 | #include "arm_neon.h" | ||
| 19308 | |||
| 19309 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c | ||
| 19310 | =================================================================== | ||
| 19311 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c | ||
| 19312 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c | ||
| 19313 | @@ -3,7 +3,8 @@ | ||
| 19314 | |||
| 19315 | /* { dg-do assemble } */ | ||
| 19316 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19317 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19318 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19319 | +/* { dg-add-options arm_neon } */ | ||
| 19320 | |||
| 19321 | #include "arm_neon.h" | ||
| 19322 | |||
| 19323 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c | ||
| 19324 | =================================================================== | ||
| 19325 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c | ||
| 19326 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c | ||
| 19327 | @@ -3,7 +3,8 @@ | ||
| 19328 | |||
| 19329 | /* { dg-do assemble } */ | ||
| 19330 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19331 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19332 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19333 | +/* { dg-add-options arm_neon } */ | ||
| 19334 | |||
| 19335 | #include "arm_neon.h" | ||
| 19336 | |||
| 19337 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c | ||
| 19338 | =================================================================== | ||
| 19339 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c | ||
| 19340 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c | ||
| 19341 | @@ -3,7 +3,8 @@ | ||
| 19342 | |||
| 19343 | /* { dg-do assemble } */ | ||
| 19344 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19345 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19346 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19347 | +/* { dg-add-options arm_neon } */ | ||
| 19348 | |||
| 19349 | #include "arm_neon.h" | ||
| 19350 | |||
| 19351 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c | ||
| 19352 | =================================================================== | ||
| 19353 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c | ||
| 19354 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c | ||
| 19355 | @@ -3,7 +3,8 @@ | ||
| 19356 | |||
| 19357 | /* { dg-do assemble } */ | ||
| 19358 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19359 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19360 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19361 | +/* { dg-add-options arm_neon } */ | ||
| 19362 | |||
| 19363 | #include "arm_neon.h" | ||
| 19364 | |||
| 19365 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c | ||
| 19366 | =================================================================== | ||
| 19367 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c | ||
| 19368 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c | ||
| 19369 | @@ -3,7 +3,8 @@ | ||
| 19370 | |||
| 19371 | /* { dg-do assemble } */ | ||
| 19372 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19373 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19374 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19375 | +/* { dg-add-options arm_neon } */ | ||
| 19376 | |||
| 19377 | #include "arm_neon.h" | ||
| 19378 | |||
| 19379 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c | ||
| 19380 | =================================================================== | ||
| 19381 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c | ||
| 19382 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c | ||
| 19383 | @@ -3,7 +3,8 @@ | ||
| 19384 | |||
| 19385 | /* { dg-do assemble } */ | ||
| 19386 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19387 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19388 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19389 | +/* { dg-add-options arm_neon } */ | ||
| 19390 | |||
| 19391 | #include "arm_neon.h" | ||
| 19392 | |||
| 19393 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c | ||
| 19394 | =================================================================== | ||
| 19395 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c | ||
| 19396 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c | ||
| 19397 | @@ -3,7 +3,8 @@ | ||
| 19398 | |||
| 19399 | /* { dg-do assemble } */ | ||
| 19400 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19401 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19402 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19403 | +/* { dg-add-options arm_neon } */ | ||
| 19404 | |||
| 19405 | #include "arm_neon.h" | ||
| 19406 | |||
| 19407 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c | ||
| 19408 | =================================================================== | ||
| 19409 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c | ||
| 19410 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c | ||
| 19411 | @@ -3,7 +3,8 @@ | ||
| 19412 | |||
| 19413 | /* { dg-do assemble } */ | ||
| 19414 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19415 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19416 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19417 | +/* { dg-add-options arm_neon } */ | ||
| 19418 | |||
| 19419 | #include "arm_neon.h" | ||
| 19420 | |||
| 19421 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c | ||
| 19422 | =================================================================== | ||
| 19423 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c | ||
| 19424 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c | ||
| 19425 | @@ -3,7 +3,8 @@ | ||
| 19426 | |||
| 19427 | /* { dg-do assemble } */ | ||
| 19428 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19429 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19430 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19431 | +/* { dg-add-options arm_neon } */ | ||
| 19432 | |||
| 19433 | #include "arm_neon.h" | ||
| 19434 | |||
| 19435 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c | ||
| 19436 | =================================================================== | ||
| 19437 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c | ||
| 19438 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c | ||
| 19439 | @@ -3,7 +3,8 @@ | ||
| 19440 | |||
| 19441 | /* { dg-do assemble } */ | ||
| 19442 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19443 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19444 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19445 | +/* { dg-add-options arm_neon } */ | ||
| 19446 | |||
| 19447 | #include "arm_neon.h" | ||
| 19448 | |||
| 19449 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c | ||
| 19450 | =================================================================== | ||
| 19451 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c | ||
| 19452 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c | ||
| 19453 | @@ -3,7 +3,8 @@ | ||
| 19454 | |||
| 19455 | /* { dg-do assemble } */ | ||
| 19456 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19457 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19458 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19459 | +/* { dg-add-options arm_neon } */ | ||
| 19460 | |||
| 19461 | #include "arm_neon.h" | ||
| 19462 | |||
| 19463 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c | ||
| 19464 | =================================================================== | ||
| 19465 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c | ||
| 19466 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c | ||
| 19467 | @@ -3,7 +3,8 @@ | ||
| 19468 | |||
| 19469 | /* { dg-do assemble } */ | ||
| 19470 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19471 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19472 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19473 | +/* { dg-add-options arm_neon } */ | ||
| 19474 | |||
| 19475 | #include "arm_neon.h" | ||
| 19476 | |||
| 19477 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c | ||
| 19478 | =================================================================== | ||
| 19479 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c | ||
| 19480 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c | ||
| 19481 | @@ -3,7 +3,8 @@ | ||
| 19482 | |||
| 19483 | /* { dg-do assemble } */ | ||
| 19484 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19485 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19486 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19487 | +/* { dg-add-options arm_neon } */ | ||
| 19488 | |||
| 19489 | #include "arm_neon.h" | ||
| 19490 | |||
| 19491 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c | ||
| 19492 | =================================================================== | ||
| 19493 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c | ||
| 19494 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c | ||
| 19495 | @@ -3,7 +3,8 @@ | ||
| 19496 | |||
| 19497 | /* { dg-do assemble } */ | ||
| 19498 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19499 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19500 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19501 | +/* { dg-add-options arm_neon } */ | ||
| 19502 | |||
| 19503 | #include "arm_neon.h" | ||
| 19504 | |||
| 19505 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c | ||
| 19506 | =================================================================== | ||
| 19507 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c | ||
| 19508 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c | ||
| 19509 | @@ -3,7 +3,8 @@ | ||
| 19510 | |||
| 19511 | /* { dg-do assemble } */ | ||
| 19512 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19513 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19514 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19515 | +/* { dg-add-options arm_neon } */ | ||
| 19516 | |||
| 19517 | #include "arm_neon.h" | ||
| 19518 | |||
| 19519 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c | ||
| 19520 | =================================================================== | ||
| 19521 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c | ||
| 19522 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c | ||
| 19523 | @@ -3,7 +3,8 @@ | ||
| 19524 | |||
| 19525 | /* { dg-do assemble } */ | ||
| 19526 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19527 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19528 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19529 | +/* { dg-add-options arm_neon } */ | ||
| 19530 | |||
| 19531 | #include "arm_neon.h" | ||
| 19532 | |||
| 19533 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c | ||
| 19534 | =================================================================== | ||
| 19535 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c | ||
| 19536 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c | ||
| 19537 | @@ -3,7 +3,8 @@ | ||
| 19538 | |||
| 19539 | /* { dg-do assemble } */ | ||
| 19540 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19541 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19542 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19543 | +/* { dg-add-options arm_neon } */ | ||
| 19544 | |||
| 19545 | #include "arm_neon.h" | ||
| 19546 | |||
| 19547 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c | ||
| 19548 | =================================================================== | ||
| 19549 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c | ||
| 19550 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c | ||
| 19551 | @@ -3,7 +3,8 @@ | ||
| 19552 | |||
| 19553 | /* { dg-do assemble } */ | ||
| 19554 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19555 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19556 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19557 | +/* { dg-add-options arm_neon } */ | ||
| 19558 | |||
| 19559 | #include "arm_neon.h" | ||
| 19560 | |||
| 19561 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c | ||
| 19562 | =================================================================== | ||
| 19563 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c | ||
| 19564 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c | ||
| 19565 | @@ -3,7 +3,8 @@ | ||
| 19566 | |||
| 19567 | /* { dg-do assemble } */ | ||
| 19568 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19569 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19570 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19571 | +/* { dg-add-options arm_neon } */ | ||
| 19572 | |||
| 19573 | #include "arm_neon.h" | ||
| 19574 | |||
| 19575 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c | ||
| 19576 | =================================================================== | ||
| 19577 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c | ||
| 19578 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c | ||
| 19579 | @@ -3,7 +3,8 @@ | ||
| 19580 | |||
| 19581 | /* { dg-do assemble } */ | ||
| 19582 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19583 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19584 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19585 | +/* { dg-add-options arm_neon } */ | ||
| 19586 | |||
| 19587 | #include "arm_neon.h" | ||
| 19588 | |||
| 19589 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c | ||
| 19590 | =================================================================== | ||
| 19591 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c | ||
| 19592 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c | ||
| 19593 | @@ -3,7 +3,8 @@ | ||
| 19594 | |||
| 19595 | /* { dg-do assemble } */ | ||
| 19596 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19597 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19598 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19599 | +/* { dg-add-options arm_neon } */ | ||
| 19600 | |||
| 19601 | #include "arm_neon.h" | ||
| 19602 | |||
| 19603 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c | ||
| 19604 | =================================================================== | ||
| 19605 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c | ||
| 19606 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c | ||
| 19607 | @@ -3,7 +3,8 @@ | ||
| 19608 | |||
| 19609 | /* { dg-do assemble } */ | ||
| 19610 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19611 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19612 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19613 | +/* { dg-add-options arm_neon } */ | ||
| 19614 | |||
| 19615 | #include "arm_neon.h" | ||
| 19616 | |||
| 19617 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c | ||
| 19618 | =================================================================== | ||
| 19619 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c | ||
| 19620 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c | ||
| 19621 | @@ -3,7 +3,8 @@ | ||
| 19622 | |||
| 19623 | /* { dg-do assemble } */ | ||
| 19624 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19625 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19626 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19627 | +/* { dg-add-options arm_neon } */ | ||
| 19628 | |||
| 19629 | #include "arm_neon.h" | ||
| 19630 | |||
| 19631 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c | ||
| 19632 | =================================================================== | ||
| 19633 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c | ||
| 19634 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c | ||
| 19635 | @@ -3,7 +3,8 @@ | ||
| 19636 | |||
| 19637 | /* { dg-do assemble } */ | ||
| 19638 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19639 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19640 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19641 | +/* { dg-add-options arm_neon } */ | ||
| 19642 | |||
| 19643 | #include "arm_neon.h" | ||
| 19644 | |||
| 19645 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c | ||
| 19646 | =================================================================== | ||
| 19647 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c | ||
| 19648 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c | ||
| 19649 | @@ -3,7 +3,8 @@ | ||
| 19650 | |||
| 19651 | /* { dg-do assemble } */ | ||
| 19652 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19653 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19654 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19655 | +/* { dg-add-options arm_neon } */ | ||
| 19656 | |||
| 19657 | #include "arm_neon.h" | ||
| 19658 | |||
| 19659 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c | ||
| 19660 | =================================================================== | ||
| 19661 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c | ||
| 19662 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c | ||
| 19663 | @@ -3,7 +3,8 @@ | ||
| 19664 | |||
| 19665 | /* { dg-do assemble } */ | ||
| 19666 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19667 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19668 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19669 | +/* { dg-add-options arm_neon } */ | ||
| 19670 | |||
| 19671 | #include "arm_neon.h" | ||
| 19672 | |||
| 19673 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c | ||
| 19674 | =================================================================== | ||
| 19675 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c | ||
| 19676 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c | ||
| 19677 | @@ -3,7 +3,8 @@ | ||
| 19678 | |||
| 19679 | /* { dg-do assemble } */ | ||
| 19680 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19681 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19682 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19683 | +/* { dg-add-options arm_neon } */ | ||
| 19684 | |||
| 19685 | #include "arm_neon.h" | ||
| 19686 | |||
| 19687 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c | ||
| 19688 | =================================================================== | ||
| 19689 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c | ||
| 19690 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c | ||
| 19691 | @@ -3,7 +3,8 @@ | ||
| 19692 | |||
| 19693 | /* { dg-do assemble } */ | ||
| 19694 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19695 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19696 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19697 | +/* { dg-add-options arm_neon } */ | ||
| 19698 | |||
| 19699 | #include "arm_neon.h" | ||
| 19700 | |||
| 19701 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c | ||
| 19702 | =================================================================== | ||
| 19703 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c | ||
| 19704 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c | ||
| 19705 | @@ -3,7 +3,8 @@ | ||
| 19706 | |||
| 19707 | /* { dg-do assemble } */ | ||
| 19708 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19709 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19710 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19711 | +/* { dg-add-options arm_neon } */ | ||
| 19712 | |||
| 19713 | #include "arm_neon.h" | ||
| 19714 | |||
| 19715 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c | ||
| 19716 | =================================================================== | ||
| 19717 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c | ||
| 19718 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c | ||
| 19719 | @@ -3,7 +3,8 @@ | ||
| 19720 | |||
| 19721 | /* { dg-do assemble } */ | ||
| 19722 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19723 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19724 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19725 | +/* { dg-add-options arm_neon } */ | ||
| 19726 | |||
| 19727 | #include "arm_neon.h" | ||
| 19728 | |||
| 19729 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c | ||
| 19730 | =================================================================== | ||
| 19731 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c | ||
| 19732 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c | ||
| 19733 | @@ -3,7 +3,8 @@ | ||
| 19734 | |||
| 19735 | /* { dg-do assemble } */ | ||
| 19736 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19737 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19738 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19739 | +/* { dg-add-options arm_neon } */ | ||
| 19740 | |||
| 19741 | #include "arm_neon.h" | ||
| 19742 | |||
| 19743 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c | ||
| 19744 | =================================================================== | ||
| 19745 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c | ||
| 19746 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c | ||
| 19747 | @@ -3,7 +3,8 @@ | ||
| 19748 | |||
| 19749 | /* { dg-do assemble } */ | ||
| 19750 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19751 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19752 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19753 | +/* { dg-add-options arm_neon } */ | ||
| 19754 | |||
| 19755 | #include "arm_neon.h" | ||
| 19756 | |||
| 19757 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c | ||
| 19758 | =================================================================== | ||
| 19759 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c | ||
| 19760 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c | ||
| 19761 | @@ -3,7 +3,8 @@ | ||
| 19762 | |||
| 19763 | /* { dg-do assemble } */ | ||
| 19764 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19765 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19766 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19767 | +/* { dg-add-options arm_neon } */ | ||
| 19768 | |||
| 19769 | #include "arm_neon.h" | ||
| 19770 | |||
| 19771 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c | ||
| 19772 | =================================================================== | ||
| 19773 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c | ||
| 19774 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c | ||
| 19775 | @@ -3,7 +3,8 @@ | ||
| 19776 | |||
| 19777 | /* { dg-do assemble } */ | ||
| 19778 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19779 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19780 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19781 | +/* { dg-add-options arm_neon } */ | ||
| 19782 | |||
| 19783 | #include "arm_neon.h" | ||
| 19784 | |||
| 19785 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c | ||
| 19786 | =================================================================== | ||
| 19787 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c | ||
| 19788 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c | ||
| 19789 | @@ -3,7 +3,8 @@ | ||
| 19790 | |||
| 19791 | /* { dg-do assemble } */ | ||
| 19792 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19793 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19794 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19795 | +/* { dg-add-options arm_neon } */ | ||
| 19796 | |||
| 19797 | #include "arm_neon.h" | ||
| 19798 | |||
| 19799 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c | ||
| 19800 | =================================================================== | ||
| 19801 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c | ||
| 19802 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c | ||
| 19803 | @@ -3,7 +3,8 @@ | ||
| 19804 | |||
| 19805 | /* { dg-do assemble } */ | ||
| 19806 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19807 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19808 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19809 | +/* { dg-add-options arm_neon } */ | ||
| 19810 | |||
| 19811 | #include "arm_neon.h" | ||
| 19812 | |||
| 19813 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c | ||
| 19814 | =================================================================== | ||
| 19815 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c | ||
| 19816 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c | ||
| 19817 | @@ -3,7 +3,8 @@ | ||
| 19818 | |||
| 19819 | /* { dg-do assemble } */ | ||
| 19820 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19821 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19822 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19823 | +/* { dg-add-options arm_neon } */ | ||
| 19824 | |||
| 19825 | #include "arm_neon.h" | ||
| 19826 | |||
| 19827 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c | ||
| 19828 | =================================================================== | ||
| 19829 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c | ||
| 19830 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c | ||
| 19831 | @@ -3,7 +3,8 @@ | ||
| 19832 | |||
| 19833 | /* { dg-do assemble } */ | ||
| 19834 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19835 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19836 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19837 | +/* { dg-add-options arm_neon } */ | ||
| 19838 | |||
| 19839 | #include "arm_neon.h" | ||
| 19840 | |||
| 19841 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c | ||
| 19842 | =================================================================== | ||
| 19843 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c | ||
| 19844 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c | ||
| 19845 | @@ -3,7 +3,8 @@ | ||
| 19846 | |||
| 19847 | /* { dg-do assemble } */ | ||
| 19848 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19849 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19850 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19851 | +/* { dg-add-options arm_neon } */ | ||
| 19852 | |||
| 19853 | #include "arm_neon.h" | ||
| 19854 | |||
| 19855 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c | ||
| 19856 | =================================================================== | ||
| 19857 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c | ||
| 19858 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c | ||
| 19859 | @@ -3,7 +3,8 @@ | ||
| 19860 | |||
| 19861 | /* { dg-do assemble } */ | ||
| 19862 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19863 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19864 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19865 | +/* { dg-add-options arm_neon } */ | ||
| 19866 | |||
| 19867 | #include "arm_neon.h" | ||
| 19868 | |||
| 19869 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c | ||
| 19870 | =================================================================== | ||
| 19871 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c | ||
| 19872 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c | ||
| 19873 | @@ -3,7 +3,8 @@ | ||
| 19874 | |||
| 19875 | /* { dg-do assemble } */ | ||
| 19876 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19877 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19878 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19879 | +/* { dg-add-options arm_neon } */ | ||
| 19880 | |||
| 19881 | #include "arm_neon.h" | ||
| 19882 | |||
| 19883 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c | ||
| 19884 | =================================================================== | ||
| 19885 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c | ||
| 19886 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c | ||
| 19887 | @@ -3,7 +3,8 @@ | ||
| 19888 | |||
| 19889 | /* { dg-do assemble } */ | ||
| 19890 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19891 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19892 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19893 | +/* { dg-add-options arm_neon } */ | ||
| 19894 | |||
| 19895 | #include "arm_neon.h" | ||
| 19896 | |||
| 19897 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c | ||
| 19898 | =================================================================== | ||
| 19899 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c | ||
| 19900 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c | ||
| 19901 | @@ -3,7 +3,8 @@ | ||
| 19902 | |||
| 19903 | /* { dg-do assemble } */ | ||
| 19904 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19905 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19906 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19907 | +/* { dg-add-options arm_neon } */ | ||
| 19908 | |||
| 19909 | #include "arm_neon.h" | ||
| 19910 | |||
| 19911 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c | ||
| 19912 | =================================================================== | ||
| 19913 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c | ||
| 19914 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c | ||
| 19915 | @@ -3,7 +3,8 @@ | ||
| 19916 | |||
| 19917 | /* { dg-do assemble } */ | ||
| 19918 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19919 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19920 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19921 | +/* { dg-add-options arm_neon } */ | ||
| 19922 | |||
| 19923 | #include "arm_neon.h" | ||
| 19924 | |||
| 19925 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c | ||
| 19926 | =================================================================== | ||
| 19927 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c | ||
| 19928 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c | ||
| 19929 | @@ -3,7 +3,8 @@ | ||
| 19930 | |||
| 19931 | /* { dg-do assemble } */ | ||
| 19932 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19933 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19934 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19935 | +/* { dg-add-options arm_neon } */ | ||
| 19936 | |||
| 19937 | #include "arm_neon.h" | ||
| 19938 | |||
| 19939 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c | ||
| 19940 | =================================================================== | ||
| 19941 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c | ||
| 19942 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c | ||
| 19943 | @@ -3,7 +3,8 @@ | ||
| 19944 | |||
| 19945 | /* { dg-do assemble } */ | ||
| 19946 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19947 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19948 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19949 | +/* { dg-add-options arm_neon } */ | ||
| 19950 | |||
| 19951 | #include "arm_neon.h" | ||
| 19952 | |||
| 19953 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c | ||
| 19954 | =================================================================== | ||
| 19955 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c | ||
| 19956 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c | ||
| 19957 | @@ -3,7 +3,8 @@ | ||
| 19958 | |||
| 19959 | /* { dg-do assemble } */ | ||
| 19960 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19961 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19962 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19963 | +/* { dg-add-options arm_neon } */ | ||
| 19964 | |||
| 19965 | #include "arm_neon.h" | ||
| 19966 | |||
| 19967 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c | ||
| 19968 | =================================================================== | ||
| 19969 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c | ||
| 19970 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c | ||
| 19971 | @@ -3,7 +3,8 @@ | ||
| 19972 | |||
| 19973 | /* { dg-do assemble } */ | ||
| 19974 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19975 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19976 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19977 | +/* { dg-add-options arm_neon } */ | ||
| 19978 | |||
| 19979 | #include "arm_neon.h" | ||
| 19980 | |||
| 19981 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c | ||
| 19982 | =================================================================== | ||
| 19983 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c | ||
| 19984 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c | ||
| 19985 | @@ -3,7 +3,8 @@ | ||
| 19986 | |||
| 19987 | /* { dg-do assemble } */ | ||
| 19988 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 19989 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 19990 | +/* { dg-options "-save-temps -O0" } */ | ||
| 19991 | +/* { dg-add-options arm_neon } */ | ||
| 19992 | |||
| 19993 | #include "arm_neon.h" | ||
| 19994 | |||
| 19995 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c | ||
| 19996 | =================================================================== | ||
| 19997 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c | ||
| 19998 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c | ||
| 19999 | @@ -3,7 +3,8 @@ | ||
| 20000 | |||
| 20001 | /* { dg-do assemble } */ | ||
| 20002 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20003 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20004 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20005 | +/* { dg-add-options arm_neon } */ | ||
| 20006 | |||
| 20007 | #include "arm_neon.h" | ||
| 20008 | |||
| 20009 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c | ||
| 20010 | =================================================================== | ||
| 20011 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c | ||
| 20012 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c | ||
| 20013 | @@ -3,7 +3,8 @@ | ||
| 20014 | |||
| 20015 | /* { dg-do assemble } */ | ||
| 20016 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20017 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20018 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20019 | +/* { dg-add-options arm_neon } */ | ||
| 20020 | |||
| 20021 | #include "arm_neon.h" | ||
| 20022 | |||
| 20023 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c | ||
| 20024 | =================================================================== | ||
| 20025 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c | ||
| 20026 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c | ||
| 20027 | @@ -3,7 +3,8 @@ | ||
| 20028 | |||
| 20029 | /* { dg-do assemble } */ | ||
| 20030 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20031 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20032 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20033 | +/* { dg-add-options arm_neon } */ | ||
| 20034 | |||
| 20035 | #include "arm_neon.h" | ||
| 20036 | |||
| 20037 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c | ||
| 20038 | =================================================================== | ||
| 20039 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c | ||
| 20040 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c | ||
| 20041 | @@ -3,7 +3,8 @@ | ||
| 20042 | |||
| 20043 | /* { dg-do assemble } */ | ||
| 20044 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20045 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20046 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20047 | +/* { dg-add-options arm_neon } */ | ||
| 20048 | |||
| 20049 | #include "arm_neon.h" | ||
| 20050 | |||
| 20051 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c | ||
| 20052 | =================================================================== | ||
| 20053 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c | ||
| 20054 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c | ||
| 20055 | @@ -3,7 +3,8 @@ | ||
| 20056 | |||
| 20057 | /* { dg-do assemble } */ | ||
| 20058 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20059 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20060 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20061 | +/* { dg-add-options arm_neon } */ | ||
| 20062 | |||
| 20063 | #include "arm_neon.h" | ||
| 20064 | |||
| 20065 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c | ||
| 20066 | =================================================================== | ||
| 20067 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c | ||
| 20068 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c | ||
| 20069 | @@ -3,7 +3,8 @@ | ||
| 20070 | |||
| 20071 | /* { dg-do assemble } */ | ||
| 20072 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20073 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20074 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20075 | +/* { dg-add-options arm_neon } */ | ||
| 20076 | |||
| 20077 | #include "arm_neon.h" | ||
| 20078 | |||
| 20079 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c | ||
| 20080 | =================================================================== | ||
| 20081 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c | ||
| 20082 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c | ||
| 20083 | @@ -3,7 +3,8 @@ | ||
| 20084 | |||
| 20085 | /* { dg-do assemble } */ | ||
| 20086 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20087 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20088 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20089 | +/* { dg-add-options arm_neon } */ | ||
| 20090 | |||
| 20091 | #include "arm_neon.h" | ||
| 20092 | |||
| 20093 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c | ||
| 20094 | =================================================================== | ||
| 20095 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c | ||
| 20096 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c | ||
| 20097 | @@ -3,7 +3,8 @@ | ||
| 20098 | |||
| 20099 | /* { dg-do assemble } */ | ||
| 20100 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20101 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20102 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20103 | +/* { dg-add-options arm_neon } */ | ||
| 20104 | |||
| 20105 | #include "arm_neon.h" | ||
| 20106 | |||
| 20107 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c | ||
| 20108 | =================================================================== | ||
| 20109 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c | ||
| 20110 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c | ||
| 20111 | @@ -3,7 +3,8 @@ | ||
| 20112 | |||
| 20113 | /* { dg-do assemble } */ | ||
| 20114 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20115 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20116 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20117 | +/* { dg-add-options arm_neon } */ | ||
| 20118 | |||
| 20119 | #include "arm_neon.h" | ||
| 20120 | |||
| 20121 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c | ||
| 20122 | =================================================================== | ||
| 20123 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c | ||
| 20124 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c | ||
| 20125 | @@ -3,7 +3,8 @@ | ||
| 20126 | |||
| 20127 | /* { dg-do assemble } */ | ||
| 20128 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20129 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20130 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20131 | +/* { dg-add-options arm_neon } */ | ||
| 20132 | |||
| 20133 | #include "arm_neon.h" | ||
| 20134 | |||
| 20135 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c | ||
| 20136 | =================================================================== | ||
| 20137 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c | ||
| 20138 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c | ||
| 20139 | @@ -3,7 +3,8 @@ | ||
| 20140 | |||
| 20141 | /* { dg-do assemble } */ | ||
| 20142 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20143 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20144 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20145 | +/* { dg-add-options arm_neon } */ | ||
| 20146 | |||
| 20147 | #include "arm_neon.h" | ||
| 20148 | |||
| 20149 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c | ||
| 20150 | =================================================================== | ||
| 20151 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c | ||
| 20152 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c | ||
| 20153 | @@ -3,7 +3,8 @@ | ||
| 20154 | |||
| 20155 | /* { dg-do assemble } */ | ||
| 20156 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20157 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20158 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20159 | +/* { dg-add-options arm_neon } */ | ||
| 20160 | |||
| 20161 | #include "arm_neon.h" | ||
| 20162 | |||
| 20163 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c | ||
| 20164 | =================================================================== | ||
| 20165 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c | ||
| 20166 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c | ||
| 20167 | @@ -3,7 +3,8 @@ | ||
| 20168 | |||
| 20169 | /* { dg-do assemble } */ | ||
| 20170 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20171 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20172 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20173 | +/* { dg-add-options arm_neon } */ | ||
| 20174 | |||
| 20175 | #include "arm_neon.h" | ||
| 20176 | |||
| 20177 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c | ||
| 20178 | =================================================================== | ||
| 20179 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c | ||
| 20180 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c | ||
| 20181 | @@ -3,7 +3,8 @@ | ||
| 20182 | |||
| 20183 | /* { dg-do assemble } */ | ||
| 20184 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20185 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20186 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20187 | +/* { dg-add-options arm_neon } */ | ||
| 20188 | |||
| 20189 | #include "arm_neon.h" | ||
| 20190 | |||
| 20191 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c | ||
| 20192 | =================================================================== | ||
| 20193 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c | ||
| 20194 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c | ||
| 20195 | @@ -3,7 +3,8 @@ | ||
| 20196 | |||
| 20197 | /* { dg-do assemble } */ | ||
| 20198 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20199 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20200 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20201 | +/* { dg-add-options arm_neon } */ | ||
| 20202 | |||
| 20203 | #include "arm_neon.h" | ||
| 20204 | |||
| 20205 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c | ||
| 20206 | =================================================================== | ||
| 20207 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c | ||
| 20208 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c | ||
| 20209 | @@ -3,7 +3,8 @@ | ||
| 20210 | |||
| 20211 | /* { dg-do assemble } */ | ||
| 20212 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20213 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20214 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20215 | +/* { dg-add-options arm_neon } */ | ||
| 20216 | |||
| 20217 | #include "arm_neon.h" | ||
| 20218 | |||
| 20219 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c | ||
| 20220 | =================================================================== | ||
| 20221 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c | ||
| 20222 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c | ||
| 20223 | @@ -3,7 +3,8 @@ | ||
| 20224 | |||
| 20225 | /* { dg-do assemble } */ | ||
| 20226 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20227 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20228 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20229 | +/* { dg-add-options arm_neon } */ | ||
| 20230 | |||
| 20231 | #include "arm_neon.h" | ||
| 20232 | |||
| 20233 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c | ||
| 20234 | =================================================================== | ||
| 20235 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c | ||
| 20236 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c | ||
| 20237 | @@ -3,7 +3,8 @@ | ||
| 20238 | |||
| 20239 | /* { dg-do assemble } */ | ||
| 20240 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20241 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20242 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20243 | +/* { dg-add-options arm_neon } */ | ||
| 20244 | |||
| 20245 | #include "arm_neon.h" | ||
| 20246 | |||
| 20247 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c | ||
| 20248 | =================================================================== | ||
| 20249 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c | ||
| 20250 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c | ||
| 20251 | @@ -3,7 +3,8 @@ | ||
| 20252 | |||
| 20253 | /* { dg-do assemble } */ | ||
| 20254 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20255 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20256 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20257 | +/* { dg-add-options arm_neon } */ | ||
| 20258 | |||
| 20259 | #include "arm_neon.h" | ||
| 20260 | |||
| 20261 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c | ||
| 20262 | =================================================================== | ||
| 20263 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c | ||
| 20264 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c | ||
| 20265 | @@ -3,7 +3,8 @@ | ||
| 20266 | |||
| 20267 | /* { dg-do assemble } */ | ||
| 20268 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20269 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20270 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20271 | +/* { dg-add-options arm_neon } */ | ||
| 20272 | |||
| 20273 | #include "arm_neon.h" | ||
| 20274 | |||
| 20275 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c | ||
| 20276 | =================================================================== | ||
| 20277 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c | ||
| 20278 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c | ||
| 20279 | @@ -3,7 +3,8 @@ | ||
| 20280 | |||
| 20281 | /* { dg-do assemble } */ | ||
| 20282 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20283 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20284 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20285 | +/* { dg-add-options arm_neon } */ | ||
| 20286 | |||
| 20287 | #include "arm_neon.h" | ||
| 20288 | |||
| 20289 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c | ||
| 20290 | =================================================================== | ||
| 20291 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c | ||
| 20292 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c | ||
| 20293 | @@ -3,7 +3,8 @@ | ||
| 20294 | |||
| 20295 | /* { dg-do assemble } */ | ||
| 20296 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20297 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20298 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20299 | +/* { dg-add-options arm_neon } */ | ||
| 20300 | |||
| 20301 | #include "arm_neon.h" | ||
| 20302 | |||
| 20303 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c | ||
| 20304 | =================================================================== | ||
| 20305 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c | ||
| 20306 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c | ||
| 20307 | @@ -3,7 +3,8 @@ | ||
| 20308 | |||
| 20309 | /* { dg-do assemble } */ | ||
| 20310 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20311 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20312 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20313 | +/* { dg-add-options arm_neon } */ | ||
| 20314 | |||
| 20315 | #include "arm_neon.h" | ||
| 20316 | |||
| 20317 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c | ||
| 20318 | =================================================================== | ||
| 20319 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c | ||
| 20320 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c | ||
| 20321 | @@ -3,7 +3,8 @@ | ||
| 20322 | |||
| 20323 | /* { dg-do assemble } */ | ||
| 20324 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20325 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20326 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20327 | +/* { dg-add-options arm_neon } */ | ||
| 20328 | |||
| 20329 | #include "arm_neon.h" | ||
| 20330 | |||
| 20331 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c | ||
| 20332 | =================================================================== | ||
| 20333 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c | ||
| 20334 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c | ||
| 20335 | @@ -3,7 +3,8 @@ | ||
| 20336 | |||
| 20337 | /* { dg-do assemble } */ | ||
| 20338 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20339 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20340 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20341 | +/* { dg-add-options arm_neon } */ | ||
| 20342 | |||
| 20343 | #include "arm_neon.h" | ||
| 20344 | |||
| 20345 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c | ||
| 20346 | =================================================================== | ||
| 20347 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c | ||
| 20348 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c | ||
| 20349 | @@ -3,7 +3,8 @@ | ||
| 20350 | |||
| 20351 | /* { dg-do assemble } */ | ||
| 20352 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20353 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20354 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20355 | +/* { dg-add-options arm_neon } */ | ||
| 20356 | |||
| 20357 | #include "arm_neon.h" | ||
| 20358 | |||
| 20359 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c | ||
| 20360 | =================================================================== | ||
| 20361 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c | ||
| 20362 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c | ||
| 20363 | @@ -3,7 +3,8 @@ | ||
| 20364 | |||
| 20365 | /* { dg-do assemble } */ | ||
| 20366 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20367 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20368 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20369 | +/* { dg-add-options arm_neon } */ | ||
| 20370 | |||
| 20371 | #include "arm_neon.h" | ||
| 20372 | |||
| 20373 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c | ||
| 20374 | =================================================================== | ||
| 20375 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c | ||
| 20376 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c | ||
| 20377 | @@ -3,7 +3,8 @@ | ||
| 20378 | |||
| 20379 | /* { dg-do assemble } */ | ||
| 20380 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20381 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20382 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20383 | +/* { dg-add-options arm_neon } */ | ||
| 20384 | |||
| 20385 | #include "arm_neon.h" | ||
| 20386 | |||
| 20387 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c | ||
| 20388 | =================================================================== | ||
| 20389 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c | ||
| 20390 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c | ||
| 20391 | @@ -3,7 +3,8 @@ | ||
| 20392 | |||
| 20393 | /* { dg-do assemble } */ | ||
| 20394 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20395 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20396 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20397 | +/* { dg-add-options arm_neon } */ | ||
| 20398 | |||
| 20399 | #include "arm_neon.h" | ||
| 20400 | |||
| 20401 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c | ||
| 20402 | =================================================================== | ||
| 20403 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c | ||
| 20404 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c | ||
| 20405 | @@ -3,7 +3,8 @@ | ||
| 20406 | |||
| 20407 | /* { dg-do assemble } */ | ||
| 20408 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20409 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20410 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20411 | +/* { dg-add-options arm_neon } */ | ||
| 20412 | |||
| 20413 | #include "arm_neon.h" | ||
| 20414 | |||
| 20415 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c | ||
| 20416 | =================================================================== | ||
| 20417 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c | ||
| 20418 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c | ||
| 20419 | @@ -3,7 +3,8 @@ | ||
| 20420 | |||
| 20421 | /* { dg-do assemble } */ | ||
| 20422 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20423 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20424 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20425 | +/* { dg-add-options arm_neon } */ | ||
| 20426 | |||
| 20427 | #include "arm_neon.h" | ||
| 20428 | |||
| 20429 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c | ||
| 20430 | =================================================================== | ||
| 20431 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c | ||
| 20432 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c | ||
| 20433 | @@ -3,7 +3,8 @@ | ||
| 20434 | |||
| 20435 | /* { dg-do assemble } */ | ||
| 20436 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20437 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20438 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20439 | +/* { dg-add-options arm_neon } */ | ||
| 20440 | |||
| 20441 | #include "arm_neon.h" | ||
| 20442 | |||
| 20443 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c | ||
| 20444 | =================================================================== | ||
| 20445 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c | ||
| 20446 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c | ||
| 20447 | @@ -3,7 +3,8 @@ | ||
| 20448 | |||
| 20449 | /* { dg-do assemble } */ | ||
| 20450 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20451 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20452 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20453 | +/* { dg-add-options arm_neon } */ | ||
| 20454 | |||
| 20455 | #include "arm_neon.h" | ||
| 20456 | |||
| 20457 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c | ||
| 20458 | =================================================================== | ||
| 20459 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c | ||
| 20460 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c | ||
| 20461 | @@ -3,7 +3,8 @@ | ||
| 20462 | |||
| 20463 | /* { dg-do assemble } */ | ||
| 20464 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20465 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20466 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20467 | +/* { dg-add-options arm_neon } */ | ||
| 20468 | |||
| 20469 | #include "arm_neon.h" | ||
| 20470 | |||
| 20471 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c | ||
| 20472 | =================================================================== | ||
| 20473 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c | ||
| 20474 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c | ||
| 20475 | @@ -3,7 +3,8 @@ | ||
| 20476 | |||
| 20477 | /* { dg-do assemble } */ | ||
| 20478 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20479 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20480 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20481 | +/* { dg-add-options arm_neon } */ | ||
| 20482 | |||
| 20483 | #include "arm_neon.h" | ||
| 20484 | |||
| 20485 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c | ||
| 20486 | =================================================================== | ||
| 20487 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c | ||
| 20488 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c | ||
| 20489 | @@ -3,7 +3,8 @@ | ||
| 20490 | |||
| 20491 | /* { dg-do assemble } */ | ||
| 20492 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20493 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20494 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20495 | +/* { dg-add-options arm_neon } */ | ||
| 20496 | |||
| 20497 | #include "arm_neon.h" | ||
| 20498 | |||
| 20499 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c | ||
| 20500 | =================================================================== | ||
| 20501 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c | ||
| 20502 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c | ||
| 20503 | @@ -3,7 +3,8 @@ | ||
| 20504 | |||
| 20505 | /* { dg-do assemble } */ | ||
| 20506 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20507 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20508 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20509 | +/* { dg-add-options arm_neon } */ | ||
| 20510 | |||
| 20511 | #include "arm_neon.h" | ||
| 20512 | |||
| 20513 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c | ||
| 20514 | =================================================================== | ||
| 20515 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c | ||
| 20516 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c | ||
| 20517 | @@ -3,7 +3,8 @@ | ||
| 20518 | |||
| 20519 | /* { dg-do assemble } */ | ||
| 20520 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20521 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20522 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20523 | +/* { dg-add-options arm_neon } */ | ||
| 20524 | |||
| 20525 | #include "arm_neon.h" | ||
| 20526 | |||
| 20527 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c | ||
| 20528 | =================================================================== | ||
| 20529 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c | ||
| 20530 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c | ||
| 20531 | @@ -3,7 +3,8 @@ | ||
| 20532 | |||
| 20533 | /* { dg-do assemble } */ | ||
| 20534 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20535 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20536 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20537 | +/* { dg-add-options arm_neon } */ | ||
| 20538 | |||
| 20539 | #include "arm_neon.h" | ||
| 20540 | |||
| 20541 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c | ||
| 20542 | =================================================================== | ||
| 20543 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c | ||
| 20544 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c | ||
| 20545 | @@ -3,7 +3,8 @@ | ||
| 20546 | |||
| 20547 | /* { dg-do assemble } */ | ||
| 20548 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20549 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20550 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20551 | +/* { dg-add-options arm_neon } */ | ||
| 20552 | |||
| 20553 | #include "arm_neon.h" | ||
| 20554 | |||
| 20555 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c | ||
| 20556 | =================================================================== | ||
| 20557 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c | ||
| 20558 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c | ||
| 20559 | @@ -3,7 +3,8 @@ | ||
| 20560 | |||
| 20561 | /* { dg-do assemble } */ | ||
| 20562 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20563 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20564 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20565 | +/* { dg-add-options arm_neon } */ | ||
| 20566 | |||
| 20567 | #include "arm_neon.h" | ||
| 20568 | |||
| 20569 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c | ||
| 20570 | =================================================================== | ||
| 20571 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c | ||
| 20572 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c | ||
| 20573 | @@ -3,7 +3,8 @@ | ||
| 20574 | |||
| 20575 | /* { dg-do assemble } */ | ||
| 20576 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20577 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20578 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20579 | +/* { dg-add-options arm_neon } */ | ||
| 20580 | |||
| 20581 | #include "arm_neon.h" | ||
| 20582 | |||
| 20583 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c | ||
| 20584 | =================================================================== | ||
| 20585 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c | ||
| 20586 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c | ||
| 20587 | @@ -3,7 +3,8 @@ | ||
| 20588 | |||
| 20589 | /* { dg-do assemble } */ | ||
| 20590 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20591 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20592 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20593 | +/* { dg-add-options arm_neon } */ | ||
| 20594 | |||
| 20595 | #include "arm_neon.h" | ||
| 20596 | |||
| 20597 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c | ||
| 20598 | =================================================================== | ||
| 20599 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c | ||
| 20600 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c | ||
| 20601 | @@ -3,7 +3,8 @@ | ||
| 20602 | |||
| 20603 | /* { dg-do assemble } */ | ||
| 20604 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20605 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20606 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20607 | +/* { dg-add-options arm_neon } */ | ||
| 20608 | |||
| 20609 | #include "arm_neon.h" | ||
| 20610 | |||
| 20611 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c | ||
| 20612 | =================================================================== | ||
| 20613 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c | ||
| 20614 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c | ||
| 20615 | @@ -3,7 +3,8 @@ | ||
| 20616 | |||
| 20617 | /* { dg-do assemble } */ | ||
| 20618 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20619 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20620 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20621 | +/* { dg-add-options arm_neon } */ | ||
| 20622 | |||
| 20623 | #include "arm_neon.h" | ||
| 20624 | |||
| 20625 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c | ||
| 20626 | =================================================================== | ||
| 20627 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c | ||
| 20628 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c | ||
| 20629 | @@ -3,7 +3,8 @@ | ||
| 20630 | |||
| 20631 | /* { dg-do assemble } */ | ||
| 20632 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20633 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20634 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20635 | +/* { dg-add-options arm_neon } */ | ||
| 20636 | |||
| 20637 | #include "arm_neon.h" | ||
| 20638 | |||
| 20639 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c | ||
| 20640 | =================================================================== | ||
| 20641 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c | ||
| 20642 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c | ||
| 20643 | @@ -3,7 +3,8 @@ | ||
| 20644 | |||
| 20645 | /* { dg-do assemble } */ | ||
| 20646 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20647 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20648 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20649 | +/* { dg-add-options arm_neon } */ | ||
| 20650 | |||
| 20651 | #include "arm_neon.h" | ||
| 20652 | |||
| 20653 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c | ||
| 20654 | =================================================================== | ||
| 20655 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c | ||
| 20656 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c | ||
| 20657 | @@ -3,7 +3,8 @@ | ||
| 20658 | |||
| 20659 | /* { dg-do assemble } */ | ||
| 20660 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20661 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20662 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20663 | +/* { dg-add-options arm_neon } */ | ||
| 20664 | |||
| 20665 | #include "arm_neon.h" | ||
| 20666 | |||
| 20667 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c | ||
| 20668 | =================================================================== | ||
| 20669 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c | ||
| 20670 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c | ||
| 20671 | @@ -3,7 +3,8 @@ | ||
| 20672 | |||
| 20673 | /* { dg-do assemble } */ | ||
| 20674 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20675 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20676 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20677 | +/* { dg-add-options arm_neon } */ | ||
| 20678 | |||
| 20679 | #include "arm_neon.h" | ||
| 20680 | |||
| 20681 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c | ||
| 20682 | =================================================================== | ||
| 20683 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c | ||
| 20684 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c | ||
| 20685 | @@ -3,7 +3,8 @@ | ||
| 20686 | |||
| 20687 | /* { dg-do assemble } */ | ||
| 20688 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20689 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20690 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20691 | +/* { dg-add-options arm_neon } */ | ||
| 20692 | |||
| 20693 | #include "arm_neon.h" | ||
| 20694 | |||
| 20695 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c | ||
| 20696 | =================================================================== | ||
| 20697 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c | ||
| 20698 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c | ||
| 20699 | @@ -3,7 +3,8 @@ | ||
| 20700 | |||
| 20701 | /* { dg-do assemble } */ | ||
| 20702 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20703 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20704 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20705 | +/* { dg-add-options arm_neon } */ | ||
| 20706 | |||
| 20707 | #include "arm_neon.h" | ||
| 20708 | |||
| 20709 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c | ||
| 20710 | =================================================================== | ||
| 20711 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c | ||
| 20712 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c | ||
| 20713 | @@ -3,7 +3,8 @@ | ||
| 20714 | |||
| 20715 | /* { dg-do assemble } */ | ||
| 20716 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20717 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20718 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20719 | +/* { dg-add-options arm_neon } */ | ||
| 20720 | |||
| 20721 | #include "arm_neon.h" | ||
| 20722 | |||
| 20723 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c | ||
| 20724 | =================================================================== | ||
| 20725 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c | ||
| 20726 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c | ||
| 20727 | @@ -3,7 +3,8 @@ | ||
| 20728 | |||
| 20729 | /* { dg-do assemble } */ | ||
| 20730 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20731 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20732 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20733 | +/* { dg-add-options arm_neon } */ | ||
| 20734 | |||
| 20735 | #include "arm_neon.h" | ||
| 20736 | |||
| 20737 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c | ||
| 20738 | =================================================================== | ||
| 20739 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c | ||
| 20740 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c | ||
| 20741 | @@ -3,7 +3,8 @@ | ||
| 20742 | |||
| 20743 | /* { dg-do assemble } */ | ||
| 20744 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20745 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20746 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20747 | +/* { dg-add-options arm_neon } */ | ||
| 20748 | |||
| 20749 | #include "arm_neon.h" | ||
| 20750 | |||
| 20751 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c | ||
| 20752 | =================================================================== | ||
| 20753 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c | ||
| 20754 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c | ||
| 20755 | @@ -3,7 +3,8 @@ | ||
| 20756 | |||
| 20757 | /* { dg-do assemble } */ | ||
| 20758 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20759 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20760 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20761 | +/* { dg-add-options arm_neon } */ | ||
| 20762 | |||
| 20763 | #include "arm_neon.h" | ||
| 20764 | |||
| 20765 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c | ||
| 20766 | =================================================================== | ||
| 20767 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c | ||
| 20768 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c | ||
| 20769 | @@ -3,7 +3,8 @@ | ||
| 20770 | |||
| 20771 | /* { dg-do assemble } */ | ||
| 20772 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20773 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20774 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20775 | +/* { dg-add-options arm_neon } */ | ||
| 20776 | |||
| 20777 | #include "arm_neon.h" | ||
| 20778 | |||
| 20779 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c | ||
| 20780 | =================================================================== | ||
| 20781 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c | ||
| 20782 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c | ||
| 20783 | @@ -3,7 +3,8 @@ | ||
| 20784 | |||
| 20785 | /* { dg-do assemble } */ | ||
| 20786 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20787 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20788 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20789 | +/* { dg-add-options arm_neon } */ | ||
| 20790 | |||
| 20791 | #include "arm_neon.h" | ||
| 20792 | |||
| 20793 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c | ||
| 20794 | =================================================================== | ||
| 20795 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c | ||
| 20796 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c | ||
| 20797 | @@ -3,7 +3,8 @@ | ||
| 20798 | |||
| 20799 | /* { dg-do assemble } */ | ||
| 20800 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20801 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20802 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20803 | +/* { dg-add-options arm_neon } */ | ||
| 20804 | |||
| 20805 | #include "arm_neon.h" | ||
| 20806 | |||
| 20807 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c | ||
| 20808 | =================================================================== | ||
| 20809 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c | ||
| 20810 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c | ||
| 20811 | @@ -3,7 +3,8 @@ | ||
| 20812 | |||
| 20813 | /* { dg-do assemble } */ | ||
| 20814 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20815 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20816 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20817 | +/* { dg-add-options arm_neon } */ | ||
| 20818 | |||
| 20819 | #include "arm_neon.h" | ||
| 20820 | |||
| 20821 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c | ||
| 20822 | =================================================================== | ||
| 20823 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c | ||
| 20824 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c | ||
| 20825 | @@ -3,7 +3,8 @@ | ||
| 20826 | |||
| 20827 | /* { dg-do assemble } */ | ||
| 20828 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20829 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20830 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20831 | +/* { dg-add-options arm_neon } */ | ||
| 20832 | |||
| 20833 | #include "arm_neon.h" | ||
| 20834 | |||
| 20835 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c | ||
| 20836 | =================================================================== | ||
| 20837 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c | ||
| 20838 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c | ||
| 20839 | @@ -3,7 +3,8 @@ | ||
| 20840 | |||
| 20841 | /* { dg-do assemble } */ | ||
| 20842 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20843 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20844 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20845 | +/* { dg-add-options arm_neon } */ | ||
| 20846 | |||
| 20847 | #include "arm_neon.h" | ||
| 20848 | |||
| 20849 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c | ||
| 20850 | =================================================================== | ||
| 20851 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c | ||
| 20852 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c | ||
| 20853 | @@ -3,7 +3,8 @@ | ||
| 20854 | |||
| 20855 | /* { dg-do assemble } */ | ||
| 20856 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20857 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20858 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20859 | +/* { dg-add-options arm_neon } */ | ||
| 20860 | |||
| 20861 | #include "arm_neon.h" | ||
| 20862 | |||
| 20863 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c | ||
| 20864 | =================================================================== | ||
| 20865 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c | ||
| 20866 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c | ||
| 20867 | @@ -3,7 +3,8 @@ | ||
| 20868 | |||
| 20869 | /* { dg-do assemble } */ | ||
| 20870 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20871 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20872 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20873 | +/* { dg-add-options arm_neon } */ | ||
| 20874 | |||
| 20875 | #include "arm_neon.h" | ||
| 20876 | |||
| 20877 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c | ||
| 20878 | =================================================================== | ||
| 20879 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c | ||
| 20880 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c | ||
| 20881 | @@ -3,7 +3,8 @@ | ||
| 20882 | |||
| 20883 | /* { dg-do assemble } */ | ||
| 20884 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20885 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20886 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20887 | +/* { dg-add-options arm_neon } */ | ||
| 20888 | |||
| 20889 | #include "arm_neon.h" | ||
| 20890 | |||
| 20891 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c | ||
| 20892 | =================================================================== | ||
| 20893 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c | ||
| 20894 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c | ||
| 20895 | @@ -3,7 +3,8 @@ | ||
| 20896 | |||
| 20897 | /* { dg-do assemble } */ | ||
| 20898 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20899 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20900 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20901 | +/* { dg-add-options arm_neon } */ | ||
| 20902 | |||
| 20903 | #include "arm_neon.h" | ||
| 20904 | |||
| 20905 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c | ||
| 20906 | =================================================================== | ||
| 20907 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c | ||
| 20908 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c | ||
| 20909 | @@ -3,7 +3,8 @@ | ||
| 20910 | |||
| 20911 | /* { dg-do assemble } */ | ||
| 20912 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20913 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20914 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20915 | +/* { dg-add-options arm_neon } */ | ||
| 20916 | |||
| 20917 | #include "arm_neon.h" | ||
| 20918 | |||
| 20919 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c | ||
| 20920 | =================================================================== | ||
| 20921 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c | ||
| 20922 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c | ||
| 20923 | @@ -3,7 +3,8 @@ | ||
| 20924 | |||
| 20925 | /* { dg-do assemble } */ | ||
| 20926 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20927 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20928 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20929 | +/* { dg-add-options arm_neon } */ | ||
| 20930 | |||
| 20931 | #include "arm_neon.h" | ||
| 20932 | |||
| 20933 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c | ||
| 20934 | =================================================================== | ||
| 20935 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c | ||
| 20936 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c | ||
| 20937 | @@ -3,7 +3,8 @@ | ||
| 20938 | |||
| 20939 | /* { dg-do assemble } */ | ||
| 20940 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20941 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20942 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20943 | +/* { dg-add-options arm_neon } */ | ||
| 20944 | |||
| 20945 | #include "arm_neon.h" | ||
| 20946 | |||
| 20947 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c | ||
| 20948 | =================================================================== | ||
| 20949 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c | ||
| 20950 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c | ||
| 20951 | @@ -3,7 +3,8 @@ | ||
| 20952 | |||
| 20953 | /* { dg-do assemble } */ | ||
| 20954 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20955 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20956 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20957 | +/* { dg-add-options arm_neon } */ | ||
| 20958 | |||
| 20959 | #include "arm_neon.h" | ||
| 20960 | |||
| 20961 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c | ||
| 20962 | =================================================================== | ||
| 20963 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c | ||
| 20964 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c | ||
| 20965 | @@ -3,7 +3,8 @@ | ||
| 20966 | |||
| 20967 | /* { dg-do assemble } */ | ||
| 20968 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20969 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20970 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20971 | +/* { dg-add-options arm_neon } */ | ||
| 20972 | |||
| 20973 | #include "arm_neon.h" | ||
| 20974 | |||
| 20975 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c | ||
| 20976 | =================================================================== | ||
| 20977 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c | ||
| 20978 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c | ||
| 20979 | @@ -3,7 +3,8 @@ | ||
| 20980 | |||
| 20981 | /* { dg-do assemble } */ | ||
| 20982 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20983 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20984 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20985 | +/* { dg-add-options arm_neon } */ | ||
| 20986 | |||
| 20987 | #include "arm_neon.h" | ||
| 20988 | |||
| 20989 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c | ||
| 20990 | =================================================================== | ||
| 20991 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c | ||
| 20992 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c | ||
| 20993 | @@ -3,7 +3,8 @@ | ||
| 20994 | |||
| 20995 | /* { dg-do assemble } */ | ||
| 20996 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 20997 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 20998 | +/* { dg-options "-save-temps -O0" } */ | ||
| 20999 | +/* { dg-add-options arm_neon } */ | ||
| 21000 | |||
| 21001 | #include "arm_neon.h" | ||
| 21002 | |||
| 21003 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c | ||
| 21004 | =================================================================== | ||
| 21005 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c | ||
| 21006 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c | ||
| 21007 | @@ -3,7 +3,8 @@ | ||
| 21008 | |||
| 21009 | /* { dg-do assemble } */ | ||
| 21010 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21011 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21012 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21013 | +/* { dg-add-options arm_neon } */ | ||
| 21014 | |||
| 21015 | #include "arm_neon.h" | ||
| 21016 | |||
| 21017 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c | ||
| 21018 | =================================================================== | ||
| 21019 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c | ||
| 21020 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c | ||
| 21021 | @@ -3,7 +3,8 @@ | ||
| 21022 | |||
| 21023 | /* { dg-do assemble } */ | ||
| 21024 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21025 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21026 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21027 | +/* { dg-add-options arm_neon } */ | ||
| 21028 | |||
| 21029 | #include "arm_neon.h" | ||
| 21030 | |||
| 21031 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c | ||
| 21032 | =================================================================== | ||
| 21033 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c | ||
| 21034 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c | ||
| 21035 | @@ -3,7 +3,8 @@ | ||
| 21036 | |||
| 21037 | /* { dg-do assemble } */ | ||
| 21038 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21039 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21040 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21041 | +/* { dg-add-options arm_neon } */ | ||
| 21042 | |||
| 21043 | #include "arm_neon.h" | ||
| 21044 | |||
| 21045 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c | ||
| 21046 | =================================================================== | ||
| 21047 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c | ||
| 21048 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c | ||
| 21049 | @@ -3,7 +3,8 @@ | ||
| 21050 | |||
| 21051 | /* { dg-do assemble } */ | ||
| 21052 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21053 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21054 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21055 | +/* { dg-add-options arm_neon } */ | ||
| 21056 | |||
| 21057 | #include "arm_neon.h" | ||
| 21058 | |||
| 21059 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c | ||
| 21060 | =================================================================== | ||
| 21061 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c | ||
| 21062 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c | ||
| 21063 | @@ -3,7 +3,8 @@ | ||
| 21064 | |||
| 21065 | /* { dg-do assemble } */ | ||
| 21066 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21067 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21068 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21069 | +/* { dg-add-options arm_neon } */ | ||
| 21070 | |||
| 21071 | #include "arm_neon.h" | ||
| 21072 | |||
| 21073 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c | ||
| 21074 | =================================================================== | ||
| 21075 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c | ||
| 21076 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c | ||
| 21077 | @@ -3,7 +3,8 @@ | ||
| 21078 | |||
| 21079 | /* { dg-do assemble } */ | ||
| 21080 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21081 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21082 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21083 | +/* { dg-add-options arm_neon } */ | ||
| 21084 | |||
| 21085 | #include "arm_neon.h" | ||
| 21086 | |||
| 21087 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c | ||
| 21088 | =================================================================== | ||
| 21089 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c | ||
| 21090 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c | ||
| 21091 | @@ -3,7 +3,8 @@ | ||
| 21092 | |||
| 21093 | /* { dg-do assemble } */ | ||
| 21094 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21095 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21096 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21097 | +/* { dg-add-options arm_neon } */ | ||
| 21098 | |||
| 21099 | #include "arm_neon.h" | ||
| 21100 | |||
| 21101 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c | ||
| 21102 | =================================================================== | ||
| 21103 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c | ||
| 21104 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c | ||
| 21105 | @@ -3,7 +3,8 @@ | ||
| 21106 | |||
| 21107 | /* { dg-do assemble } */ | ||
| 21108 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21109 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21110 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21111 | +/* { dg-add-options arm_neon } */ | ||
| 21112 | |||
| 21113 | #include "arm_neon.h" | ||
| 21114 | |||
| 21115 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c | ||
| 21116 | =================================================================== | ||
| 21117 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c | ||
| 21118 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c | ||
| 21119 | @@ -3,7 +3,8 @@ | ||
| 21120 | |||
| 21121 | /* { dg-do assemble } */ | ||
| 21122 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21123 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21124 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21125 | +/* { dg-add-options arm_neon } */ | ||
| 21126 | |||
| 21127 | #include "arm_neon.h" | ||
| 21128 | |||
| 21129 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c | ||
| 21130 | =================================================================== | ||
| 21131 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c | ||
| 21132 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c | ||
| 21133 | @@ -3,7 +3,8 @@ | ||
| 21134 | |||
| 21135 | /* { dg-do assemble } */ | ||
| 21136 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21137 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21138 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21139 | +/* { dg-add-options arm_neon } */ | ||
| 21140 | |||
| 21141 | #include "arm_neon.h" | ||
| 21142 | |||
| 21143 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c | ||
| 21144 | =================================================================== | ||
| 21145 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c | ||
| 21146 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c | ||
| 21147 | @@ -3,7 +3,8 @@ | ||
| 21148 | |||
| 21149 | /* { dg-do assemble } */ | ||
| 21150 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21151 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21152 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21153 | +/* { dg-add-options arm_neon } */ | ||
| 21154 | |||
| 21155 | #include "arm_neon.h" | ||
| 21156 | |||
| 21157 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c | ||
| 21158 | =================================================================== | ||
| 21159 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c | ||
| 21160 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c | ||
| 21161 | @@ -3,7 +3,8 @@ | ||
| 21162 | |||
| 21163 | /* { dg-do assemble } */ | ||
| 21164 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21165 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21166 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21167 | +/* { dg-add-options arm_neon } */ | ||
| 21168 | |||
| 21169 | #include "arm_neon.h" | ||
| 21170 | |||
| 21171 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c | ||
| 21172 | =================================================================== | ||
| 21173 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c | ||
| 21174 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c | ||
| 21175 | @@ -3,7 +3,8 @@ | ||
| 21176 | |||
| 21177 | /* { dg-do assemble } */ | ||
| 21178 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21179 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21180 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21181 | +/* { dg-add-options arm_neon } */ | ||
| 21182 | |||
| 21183 | #include "arm_neon.h" | ||
| 21184 | |||
| 21185 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c | ||
| 21186 | =================================================================== | ||
| 21187 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c | ||
| 21188 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c | ||
| 21189 | @@ -3,7 +3,8 @@ | ||
| 21190 | |||
| 21191 | /* { dg-do assemble } */ | ||
| 21192 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21193 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21194 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21195 | +/* { dg-add-options arm_neon } */ | ||
| 21196 | |||
| 21197 | #include "arm_neon.h" | ||
| 21198 | |||
| 21199 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c | ||
| 21200 | =================================================================== | ||
| 21201 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c | ||
| 21202 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c | ||
| 21203 | @@ -3,7 +3,8 @@ | ||
| 21204 | |||
| 21205 | /* { dg-do assemble } */ | ||
| 21206 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21207 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21208 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21209 | +/* { dg-add-options arm_neon } */ | ||
| 21210 | |||
| 21211 | #include "arm_neon.h" | ||
| 21212 | |||
| 21213 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c | ||
| 21214 | =================================================================== | ||
| 21215 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c | ||
| 21216 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c | ||
| 21217 | @@ -3,7 +3,8 @@ | ||
| 21218 | |||
| 21219 | /* { dg-do assemble } */ | ||
| 21220 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21221 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21222 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21223 | +/* { dg-add-options arm_neon } */ | ||
| 21224 | |||
| 21225 | #include "arm_neon.h" | ||
| 21226 | |||
| 21227 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c | ||
| 21228 | =================================================================== | ||
| 21229 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c | ||
| 21230 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c | ||
| 21231 | @@ -3,7 +3,8 @@ | ||
| 21232 | |||
| 21233 | /* { dg-do assemble } */ | ||
| 21234 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21235 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21236 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21237 | +/* { dg-add-options arm_neon } */ | ||
| 21238 | |||
| 21239 | #include "arm_neon.h" | ||
| 21240 | |||
| 21241 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c | ||
| 21242 | =================================================================== | ||
| 21243 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c | ||
| 21244 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c | ||
| 21245 | @@ -3,7 +3,8 @@ | ||
| 21246 | |||
| 21247 | /* { dg-do assemble } */ | ||
| 21248 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21249 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21250 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21251 | +/* { dg-add-options arm_neon } */ | ||
| 21252 | |||
| 21253 | #include "arm_neon.h" | ||
| 21254 | |||
| 21255 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c | ||
| 21256 | =================================================================== | ||
| 21257 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c | ||
| 21258 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c | ||
| 21259 | @@ -3,7 +3,8 @@ | ||
| 21260 | |||
| 21261 | /* { dg-do assemble } */ | ||
| 21262 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21263 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21264 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21265 | +/* { dg-add-options arm_neon } */ | ||
| 21266 | |||
| 21267 | #include "arm_neon.h" | ||
| 21268 | |||
| 21269 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c | ||
| 21270 | =================================================================== | ||
| 21271 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c | ||
| 21272 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c | ||
| 21273 | @@ -3,7 +3,8 @@ | ||
| 21274 | |||
| 21275 | /* { dg-do assemble } */ | ||
| 21276 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21277 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21278 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21279 | +/* { dg-add-options arm_neon } */ | ||
| 21280 | |||
| 21281 | #include "arm_neon.h" | ||
| 21282 | |||
| 21283 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c | ||
| 21284 | =================================================================== | ||
| 21285 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c | ||
| 21286 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c | ||
| 21287 | @@ -3,7 +3,8 @@ | ||
| 21288 | |||
| 21289 | /* { dg-do assemble } */ | ||
| 21290 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21291 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21292 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21293 | +/* { dg-add-options arm_neon } */ | ||
| 21294 | |||
| 21295 | #include "arm_neon.h" | ||
| 21296 | |||
| 21297 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c | ||
| 21298 | =================================================================== | ||
| 21299 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c | ||
| 21300 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c | ||
| 21301 | @@ -3,7 +3,8 @@ | ||
| 21302 | |||
| 21303 | /* { dg-do assemble } */ | ||
| 21304 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21305 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21306 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21307 | +/* { dg-add-options arm_neon } */ | ||
| 21308 | |||
| 21309 | #include "arm_neon.h" | ||
| 21310 | |||
| 21311 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c | ||
| 21312 | =================================================================== | ||
| 21313 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c | ||
| 21314 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c | ||
| 21315 | @@ -3,7 +3,8 @@ | ||
| 21316 | |||
| 21317 | /* { dg-do assemble } */ | ||
| 21318 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21319 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21320 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21321 | +/* { dg-add-options arm_neon } */ | ||
| 21322 | |||
| 21323 | #include "arm_neon.h" | ||
| 21324 | |||
| 21325 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c | ||
| 21326 | =================================================================== | ||
| 21327 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c | ||
| 21328 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c | ||
| 21329 | @@ -3,7 +3,8 @@ | ||
| 21330 | |||
| 21331 | /* { dg-do assemble } */ | ||
| 21332 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21333 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21334 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21335 | +/* { dg-add-options arm_neon } */ | ||
| 21336 | |||
| 21337 | #include "arm_neon.h" | ||
| 21338 | |||
| 21339 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c | ||
| 21340 | =================================================================== | ||
| 21341 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c | ||
| 21342 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c | ||
| 21343 | @@ -3,7 +3,8 @@ | ||
| 21344 | |||
| 21345 | /* { dg-do assemble } */ | ||
| 21346 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21347 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21348 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21349 | +/* { dg-add-options arm_neon } */ | ||
| 21350 | |||
| 21351 | #include "arm_neon.h" | ||
| 21352 | |||
| 21353 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c | ||
| 21354 | =================================================================== | ||
| 21355 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c | ||
| 21356 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c | ||
| 21357 | @@ -3,7 +3,8 @@ | ||
| 21358 | |||
| 21359 | /* { dg-do assemble } */ | ||
| 21360 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21361 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21362 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21363 | +/* { dg-add-options arm_neon } */ | ||
| 21364 | |||
| 21365 | #include "arm_neon.h" | ||
| 21366 | |||
| 21367 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c | ||
| 21368 | =================================================================== | ||
| 21369 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c | ||
| 21370 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c | ||
| 21371 | @@ -3,7 +3,8 @@ | ||
| 21372 | |||
| 21373 | /* { dg-do assemble } */ | ||
| 21374 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21375 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21376 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21377 | +/* { dg-add-options arm_neon } */ | ||
| 21378 | |||
| 21379 | #include "arm_neon.h" | ||
| 21380 | |||
| 21381 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c | ||
| 21382 | =================================================================== | ||
| 21383 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c | ||
| 21384 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c | ||
| 21385 | @@ -3,7 +3,8 @@ | ||
| 21386 | |||
| 21387 | /* { dg-do assemble } */ | ||
| 21388 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21389 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21390 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21391 | +/* { dg-add-options arm_neon } */ | ||
| 21392 | |||
| 21393 | #include "arm_neon.h" | ||
| 21394 | |||
| 21395 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c | ||
| 21396 | =================================================================== | ||
| 21397 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c | ||
| 21398 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c | ||
| 21399 | @@ -3,7 +3,8 @@ | ||
| 21400 | |||
| 21401 | /* { dg-do assemble } */ | ||
| 21402 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21403 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21404 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21405 | +/* { dg-add-options arm_neon } */ | ||
| 21406 | |||
| 21407 | #include "arm_neon.h" | ||
| 21408 | |||
| 21409 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c | ||
| 21410 | =================================================================== | ||
| 21411 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c | ||
| 21412 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c | ||
| 21413 | @@ -3,7 +3,8 @@ | ||
| 21414 | |||
| 21415 | /* { dg-do assemble } */ | ||
| 21416 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21417 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21418 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21419 | +/* { dg-add-options arm_neon } */ | ||
| 21420 | |||
| 21421 | #include "arm_neon.h" | ||
| 21422 | |||
| 21423 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c | ||
| 21424 | =================================================================== | ||
| 21425 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c | ||
| 21426 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c | ||
| 21427 | @@ -3,7 +3,8 @@ | ||
| 21428 | |||
| 21429 | /* { dg-do assemble } */ | ||
| 21430 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21431 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21432 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21433 | +/* { dg-add-options arm_neon } */ | ||
| 21434 | |||
| 21435 | #include "arm_neon.h" | ||
| 21436 | |||
| 21437 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c | ||
| 21438 | =================================================================== | ||
| 21439 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c | ||
| 21440 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c | ||
| 21441 | @@ -3,7 +3,8 @@ | ||
| 21442 | |||
| 21443 | /* { dg-do assemble } */ | ||
| 21444 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21445 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21446 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21447 | +/* { dg-add-options arm_neon } */ | ||
| 21448 | |||
| 21449 | #include "arm_neon.h" | ||
| 21450 | |||
| 21451 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls16.c | ||
| 21452 | =================================================================== | ||
| 21453 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshls16.c | ||
| 21454 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls16.c | ||
| 21455 | @@ -3,7 +3,8 @@ | ||
| 21456 | |||
| 21457 | /* { dg-do assemble } */ | ||
| 21458 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21459 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21460 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21461 | +/* { dg-add-options arm_neon } */ | ||
| 21462 | |||
| 21463 | #include "arm_neon.h" | ||
| 21464 | |||
| 21465 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls32.c | ||
| 21466 | =================================================================== | ||
| 21467 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshls32.c | ||
| 21468 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls32.c | ||
| 21469 | @@ -3,7 +3,8 @@ | ||
| 21470 | |||
| 21471 | /* { dg-do assemble } */ | ||
| 21472 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21473 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21474 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21475 | +/* { dg-add-options arm_neon } */ | ||
| 21476 | |||
| 21477 | #include "arm_neon.h" | ||
| 21478 | |||
| 21479 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls64.c | ||
| 21480 | =================================================================== | ||
| 21481 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshls64.c | ||
| 21482 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls64.c | ||
| 21483 | @@ -3,7 +3,8 @@ | ||
| 21484 | |||
| 21485 | /* { dg-do assemble } */ | ||
| 21486 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21487 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21488 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21489 | +/* { dg-add-options arm_neon } */ | ||
| 21490 | |||
| 21491 | #include "arm_neon.h" | ||
| 21492 | |||
| 21493 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls8.c | ||
| 21494 | =================================================================== | ||
| 21495 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshls8.c | ||
| 21496 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshls8.c | ||
| 21497 | @@ -3,7 +3,8 @@ | ||
| 21498 | |||
| 21499 | /* { dg-do assemble } */ | ||
| 21500 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21501 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21502 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21503 | +/* { dg-add-options arm_neon } */ | ||
| 21504 | |||
| 21505 | #include "arm_neon.h" | ||
| 21506 | |||
| 21507 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu16.c | ||
| 21508 | =================================================================== | ||
| 21509 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlu16.c | ||
| 21510 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu16.c | ||
| 21511 | @@ -3,7 +3,8 @@ | ||
| 21512 | |||
| 21513 | /* { dg-do assemble } */ | ||
| 21514 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21515 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21516 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21517 | +/* { dg-add-options arm_neon } */ | ||
| 21518 | |||
| 21519 | #include "arm_neon.h" | ||
| 21520 | |||
| 21521 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu32.c | ||
| 21522 | =================================================================== | ||
| 21523 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlu32.c | ||
| 21524 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu32.c | ||
| 21525 | @@ -3,7 +3,8 @@ | ||
| 21526 | |||
| 21527 | /* { dg-do assemble } */ | ||
| 21528 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21529 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21530 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21531 | +/* { dg-add-options arm_neon } */ | ||
| 21532 | |||
| 21533 | #include "arm_neon.h" | ||
| 21534 | |||
| 21535 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu64.c | ||
| 21536 | =================================================================== | ||
| 21537 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlu64.c | ||
| 21538 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu64.c | ||
| 21539 | @@ -3,7 +3,8 @@ | ||
| 21540 | |||
| 21541 | /* { dg-do assemble } */ | ||
| 21542 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21543 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21544 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21545 | +/* { dg-add-options arm_neon } */ | ||
| 21546 | |||
| 21547 | #include "arm_neon.h" | ||
| 21548 | |||
| 21549 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu8.c | ||
| 21550 | =================================================================== | ||
| 21551 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshlu8.c | ||
| 21552 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshlu8.c | ||
| 21553 | @@ -3,7 +3,8 @@ | ||
| 21554 | |||
| 21555 | /* { dg-do assemble } */ | ||
| 21556 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21557 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21558 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21559 | +/* { dg-add-options arm_neon } */ | ||
| 21560 | |||
| 21561 | #include "arm_neon.h" | ||
| 21562 | |||
| 21563 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c | ||
| 21564 | =================================================================== | ||
| 21565 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c | ||
| 21566 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c | ||
| 21567 | @@ -3,7 +3,8 @@ | ||
| 21568 | |||
| 21569 | /* { dg-do assemble } */ | ||
| 21570 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21571 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21572 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21573 | +/* { dg-add-options arm_neon } */ | ||
| 21574 | |||
| 21575 | #include "arm_neon.h" | ||
| 21576 | |||
| 21577 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c | ||
| 21578 | =================================================================== | ||
| 21579 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c | ||
| 21580 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c | ||
| 21581 | @@ -3,7 +3,8 @@ | ||
| 21582 | |||
| 21583 | /* { dg-do assemble } */ | ||
| 21584 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21585 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21586 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21587 | +/* { dg-add-options arm_neon } */ | ||
| 21588 | |||
| 21589 | #include "arm_neon.h" | ||
| 21590 | |||
| 21591 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c | ||
| 21592 | =================================================================== | ||
| 21593 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c | ||
| 21594 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c | ||
| 21595 | @@ -3,7 +3,8 @@ | ||
| 21596 | |||
| 21597 | /* { dg-do assemble } */ | ||
| 21598 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21599 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21600 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21601 | +/* { dg-add-options arm_neon } */ | ||
| 21602 | |||
| 21603 | #include "arm_neon.h" | ||
| 21604 | |||
| 21605 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c | ||
| 21606 | =================================================================== | ||
| 21607 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c | ||
| 21608 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c | ||
| 21609 | @@ -3,7 +3,8 @@ | ||
| 21610 | |||
| 21611 | /* { dg-do assemble } */ | ||
| 21612 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21613 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21614 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21615 | +/* { dg-add-options arm_neon } */ | ||
| 21616 | |||
| 21617 | #include "arm_neon.h" | ||
| 21618 | |||
| 21619 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c | ||
| 21620 | =================================================================== | ||
| 21621 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c | ||
| 21622 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c | ||
| 21623 | @@ -3,7 +3,8 @@ | ||
| 21624 | |||
| 21625 | /* { dg-do assemble } */ | ||
| 21626 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21627 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21628 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21629 | +/* { dg-add-options arm_neon } */ | ||
| 21630 | |||
| 21631 | #include "arm_neon.h" | ||
| 21632 | |||
| 21633 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c | ||
| 21634 | =================================================================== | ||
| 21635 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c | ||
| 21636 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c | ||
| 21637 | @@ -3,7 +3,8 @@ | ||
| 21638 | |||
| 21639 | /* { dg-do assemble } */ | ||
| 21640 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21641 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21642 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21643 | +/* { dg-add-options arm_neon } */ | ||
| 21644 | |||
| 21645 | #include "arm_neon.h" | ||
| 21646 | |||
| 21647 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c | ||
| 21648 | =================================================================== | ||
| 21649 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c | ||
| 21650 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c | ||
| 21651 | @@ -3,7 +3,8 @@ | ||
| 21652 | |||
| 21653 | /* { dg-do assemble } */ | ||
| 21654 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21655 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21656 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21657 | +/* { dg-add-options arm_neon } */ | ||
| 21658 | |||
| 21659 | #include "arm_neon.h" | ||
| 21660 | |||
| 21661 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c | ||
| 21662 | =================================================================== | ||
| 21663 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c | ||
| 21664 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c | ||
| 21665 | @@ -3,7 +3,8 @@ | ||
| 21666 | |||
| 21667 | /* { dg-do assemble } */ | ||
| 21668 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21669 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21670 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21671 | +/* { dg-add-options arm_neon } */ | ||
| 21672 | |||
| 21673 | #include "arm_neon.h" | ||
| 21674 | |||
| 21675 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c | ||
| 21676 | =================================================================== | ||
| 21677 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c | ||
| 21678 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c | ||
| 21679 | @@ -3,7 +3,8 @@ | ||
| 21680 | |||
| 21681 | /* { dg-do assemble } */ | ||
| 21682 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21683 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21684 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21685 | +/* { dg-add-options arm_neon } */ | ||
| 21686 | |||
| 21687 | #include "arm_neon.h" | ||
| 21688 | |||
| 21689 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c | ||
| 21690 | =================================================================== | ||
| 21691 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c | ||
| 21692 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c | ||
| 21693 | @@ -3,7 +3,8 @@ | ||
| 21694 | |||
| 21695 | /* { dg-do assemble } */ | ||
| 21696 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21697 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21698 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21699 | +/* { dg-add-options arm_neon } */ | ||
| 21700 | |||
| 21701 | #include "arm_neon.h" | ||
| 21702 | |||
| 21703 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c | ||
| 21704 | =================================================================== | ||
| 21705 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c | ||
| 21706 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c | ||
| 21707 | @@ -3,7 +3,8 @@ | ||
| 21708 | |||
| 21709 | /* { dg-do assemble } */ | ||
| 21710 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21711 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21712 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21713 | +/* { dg-add-options arm_neon } */ | ||
| 21714 | |||
| 21715 | #include "arm_neon.h" | ||
| 21716 | |||
| 21717 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c | ||
| 21718 | =================================================================== | ||
| 21719 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c | ||
| 21720 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c | ||
| 21721 | @@ -3,7 +3,8 @@ | ||
| 21722 | |||
| 21723 | /* { dg-do assemble } */ | ||
| 21724 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21725 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21726 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21727 | +/* { dg-add-options arm_neon } */ | ||
| 21728 | |||
| 21729 | #include "arm_neon.h" | ||
| 21730 | |||
| 21731 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c | ||
| 21732 | =================================================================== | ||
| 21733 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c | ||
| 21734 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c | ||
| 21735 | @@ -3,7 +3,8 @@ | ||
| 21736 | |||
| 21737 | /* { dg-do assemble } */ | ||
| 21738 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21739 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21740 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21741 | +/* { dg-add-options arm_neon } */ | ||
| 21742 | |||
| 21743 | #include "arm_neon.h" | ||
| 21744 | |||
| 21745 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c | ||
| 21746 | =================================================================== | ||
| 21747 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c | ||
| 21748 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c | ||
| 21749 | @@ -3,7 +3,8 @@ | ||
| 21750 | |||
| 21751 | /* { dg-do assemble } */ | ||
| 21752 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21753 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21754 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21755 | +/* { dg-add-options arm_neon } */ | ||
| 21756 | |||
| 21757 | #include "arm_neon.h" | ||
| 21758 | |||
| 21759 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c | ||
| 21760 | =================================================================== | ||
| 21761 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c | ||
| 21762 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c | ||
| 21763 | @@ -3,7 +3,8 @@ | ||
| 21764 | |||
| 21765 | /* { dg-do assemble } */ | ||
| 21766 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21767 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21768 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21769 | +/* { dg-add-options arm_neon } */ | ||
| 21770 | |||
| 21771 | #include "arm_neon.h" | ||
| 21772 | |||
| 21773 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c | ||
| 21774 | =================================================================== | ||
| 21775 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c | ||
| 21776 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c | ||
| 21777 | @@ -3,7 +3,8 @@ | ||
| 21778 | |||
| 21779 | /* { dg-do assemble } */ | ||
| 21780 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21781 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21782 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21783 | +/* { dg-add-options arm_neon } */ | ||
| 21784 | |||
| 21785 | #include "arm_neon.h" | ||
| 21786 | |||
| 21787 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c | ||
| 21788 | =================================================================== | ||
| 21789 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c | ||
| 21790 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c | ||
| 21791 | @@ -3,7 +3,8 @@ | ||
| 21792 | |||
| 21793 | /* { dg-do assemble } */ | ||
| 21794 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21795 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21796 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21797 | +/* { dg-add-options arm_neon } */ | ||
| 21798 | |||
| 21799 | #include "arm_neon.h" | ||
| 21800 | |||
| 21801 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c | ||
| 21802 | =================================================================== | ||
| 21803 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c | ||
| 21804 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c | ||
| 21805 | @@ -3,7 +3,8 @@ | ||
| 21806 | |||
| 21807 | /* { dg-do assemble } */ | ||
| 21808 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21809 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21810 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21811 | +/* { dg-add-options arm_neon } */ | ||
| 21812 | |||
| 21813 | #include "arm_neon.h" | ||
| 21814 | |||
| 21815 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c | ||
| 21816 | =================================================================== | ||
| 21817 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c | ||
| 21818 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c | ||
| 21819 | @@ -3,7 +3,8 @@ | ||
| 21820 | |||
| 21821 | /* { dg-do assemble } */ | ||
| 21822 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21823 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21824 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21825 | +/* { dg-add-options arm_neon } */ | ||
| 21826 | |||
| 21827 | #include "arm_neon.h" | ||
| 21828 | |||
| 21829 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c | ||
| 21830 | =================================================================== | ||
| 21831 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c | ||
| 21832 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c | ||
| 21833 | @@ -3,7 +3,8 @@ | ||
| 21834 | |||
| 21835 | /* { dg-do assemble } */ | ||
| 21836 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21837 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21838 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21839 | +/* { dg-add-options arm_neon } */ | ||
| 21840 | |||
| 21841 | #include "arm_neon.h" | ||
| 21842 | |||
| 21843 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c | ||
| 21844 | =================================================================== | ||
| 21845 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c | ||
| 21846 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c | ||
| 21847 | @@ -3,7 +3,8 @@ | ||
| 21848 | |||
| 21849 | /* { dg-do assemble } */ | ||
| 21850 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21851 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21852 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21853 | +/* { dg-add-options arm_neon } */ | ||
| 21854 | |||
| 21855 | #include "arm_neon.h" | ||
| 21856 | |||
| 21857 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c | ||
| 21858 | =================================================================== | ||
| 21859 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c | ||
| 21860 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c | ||
| 21861 | @@ -3,7 +3,8 @@ | ||
| 21862 | |||
| 21863 | /* { dg-do assemble } */ | ||
| 21864 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21865 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21866 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21867 | +/* { dg-add-options arm_neon } */ | ||
| 21868 | |||
| 21869 | #include "arm_neon.h" | ||
| 21870 | |||
| 21871 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c | ||
| 21872 | =================================================================== | ||
| 21873 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c | ||
| 21874 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c | ||
| 21875 | @@ -3,7 +3,8 @@ | ||
| 21876 | |||
| 21877 | /* { dg-do assemble } */ | ||
| 21878 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21879 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21880 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21881 | +/* { dg-add-options arm_neon } */ | ||
| 21882 | |||
| 21883 | #include "arm_neon.h" | ||
| 21884 | |||
| 21885 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c | ||
| 21886 | =================================================================== | ||
| 21887 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c | ||
| 21888 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c | ||
| 21889 | @@ -3,7 +3,8 @@ | ||
| 21890 | |||
| 21891 | /* { dg-do assemble } */ | ||
| 21892 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21893 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21894 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21895 | +/* { dg-add-options arm_neon } */ | ||
| 21896 | |||
| 21897 | #include "arm_neon.h" | ||
| 21898 | |||
| 21899 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c | ||
| 21900 | =================================================================== | ||
| 21901 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c | ||
| 21902 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c | ||
| 21903 | @@ -3,7 +3,8 @@ | ||
| 21904 | |||
| 21905 | /* { dg-do assemble } */ | ||
| 21906 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21907 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21908 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21909 | +/* { dg-add-options arm_neon } */ | ||
| 21910 | |||
| 21911 | #include "arm_neon.h" | ||
| 21912 | |||
| 21913 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c | ||
| 21914 | =================================================================== | ||
| 21915 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c | ||
| 21916 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c | ||
| 21917 | @@ -3,7 +3,8 @@ | ||
| 21918 | |||
| 21919 | /* { dg-do assemble } */ | ||
| 21920 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21921 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21922 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21923 | +/* { dg-add-options arm_neon } */ | ||
| 21924 | |||
| 21925 | #include "arm_neon.h" | ||
| 21926 | |||
| 21927 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c | ||
| 21928 | =================================================================== | ||
| 21929 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c | ||
| 21930 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c | ||
| 21931 | @@ -3,7 +3,8 @@ | ||
| 21932 | |||
| 21933 | /* { dg-do assemble } */ | ||
| 21934 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21935 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21936 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21937 | +/* { dg-add-options arm_neon } */ | ||
| 21938 | |||
| 21939 | #include "arm_neon.h" | ||
| 21940 | |||
| 21941 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c | ||
| 21942 | =================================================================== | ||
| 21943 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c | ||
| 21944 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c | ||
| 21945 | @@ -3,7 +3,8 @@ | ||
| 21946 | |||
| 21947 | /* { dg-do assemble } */ | ||
| 21948 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21949 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21950 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21951 | +/* { dg-add-options arm_neon } */ | ||
| 21952 | |||
| 21953 | #include "arm_neon.h" | ||
| 21954 | |||
| 21955 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c | ||
| 21956 | =================================================================== | ||
| 21957 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c | ||
| 21958 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c | ||
| 21959 | @@ -3,7 +3,8 @@ | ||
| 21960 | |||
| 21961 | /* { dg-do assemble } */ | ||
| 21962 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21963 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21964 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21965 | +/* { dg-add-options arm_neon } */ | ||
| 21966 | |||
| 21967 | #include "arm_neon.h" | ||
| 21968 | |||
| 21969 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c | ||
| 21970 | =================================================================== | ||
| 21971 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c | ||
| 21972 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c | ||
| 21973 | @@ -3,7 +3,8 @@ | ||
| 21974 | |||
| 21975 | /* { dg-do assemble } */ | ||
| 21976 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21977 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21978 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21979 | +/* { dg-add-options arm_neon } */ | ||
| 21980 | |||
| 21981 | #include "arm_neon.h" | ||
| 21982 | |||
| 21983 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c | ||
| 21984 | =================================================================== | ||
| 21985 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c | ||
| 21986 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c | ||
| 21987 | @@ -3,7 +3,8 @@ | ||
| 21988 | |||
| 21989 | /* { dg-do assemble } */ | ||
| 21990 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 21991 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 21992 | +/* { dg-options "-save-temps -O0" } */ | ||
| 21993 | +/* { dg-add-options arm_neon } */ | ||
| 21994 | |||
| 21995 | #include "arm_neon.h" | ||
| 21996 | |||
| 21997 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c | ||
| 21998 | =================================================================== | ||
| 21999 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c | ||
| 22000 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c | ||
| 22001 | @@ -3,7 +3,8 @@ | ||
| 22002 | |||
| 22003 | /* { dg-do assemble } */ | ||
| 22004 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22005 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22006 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22007 | +/* { dg-add-options arm_neon } */ | ||
| 22008 | |||
| 22009 | #include "arm_neon.h" | ||
| 22010 | |||
| 22011 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c | ||
| 22012 | =================================================================== | ||
| 22013 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c | ||
| 22014 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c | ||
| 22015 | @@ -3,7 +3,8 @@ | ||
| 22016 | |||
| 22017 | /* { dg-do assemble } */ | ||
| 22018 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22019 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22020 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22021 | +/* { dg-add-options arm_neon } */ | ||
| 22022 | |||
| 22023 | #include "arm_neon.h" | ||
| 22024 | |||
| 22025 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c | ||
| 22026 | =================================================================== | ||
| 22027 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c | ||
| 22028 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c | ||
| 22029 | @@ -3,7 +3,8 @@ | ||
| 22030 | |||
| 22031 | /* { dg-do assemble } */ | ||
| 22032 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22033 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22034 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22035 | +/* { dg-add-options arm_neon } */ | ||
| 22036 | |||
| 22037 | #include "arm_neon.h" | ||
| 22038 | |||
| 22039 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c | ||
| 22040 | =================================================================== | ||
| 22041 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c | ||
| 22042 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c | ||
| 22043 | @@ -3,7 +3,8 @@ | ||
| 22044 | |||
| 22045 | /* { dg-do assemble } */ | ||
| 22046 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22047 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22048 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22049 | +/* { dg-add-options arm_neon } */ | ||
| 22050 | |||
| 22051 | #include "arm_neon.h" | ||
| 22052 | |||
| 22053 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c | ||
| 22054 | =================================================================== | ||
| 22055 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c | ||
| 22056 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c | ||
| 22057 | @@ -3,7 +3,8 @@ | ||
| 22058 | |||
| 22059 | /* { dg-do assemble } */ | ||
| 22060 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22061 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22062 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22063 | +/* { dg-add-options arm_neon } */ | ||
| 22064 | |||
| 22065 | #include "arm_neon.h" | ||
| 22066 | |||
| 22067 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c | ||
| 22068 | =================================================================== | ||
| 22069 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c | ||
| 22070 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c | ||
| 22071 | @@ -3,7 +3,8 @@ | ||
| 22072 | |||
| 22073 | /* { dg-do assemble } */ | ||
| 22074 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22075 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22076 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22077 | +/* { dg-add-options arm_neon } */ | ||
| 22078 | |||
| 22079 | #include "arm_neon.h" | ||
| 22080 | |||
| 22081 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c | ||
| 22082 | =================================================================== | ||
| 22083 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c | ||
| 22084 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c | ||
| 22085 | @@ -3,7 +3,8 @@ | ||
| 22086 | |||
| 22087 | /* { dg-do assemble } */ | ||
| 22088 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22089 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22090 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22091 | +/* { dg-add-options arm_neon } */ | ||
| 22092 | |||
| 22093 | #include "arm_neon.h" | ||
| 22094 | |||
| 22095 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c | ||
| 22096 | =================================================================== | ||
| 22097 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c | ||
| 22098 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c | ||
| 22099 | @@ -3,7 +3,8 @@ | ||
| 22100 | |||
| 22101 | /* { dg-do assemble } */ | ||
| 22102 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22103 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22104 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22105 | +/* { dg-add-options arm_neon } */ | ||
| 22106 | |||
| 22107 | #include "arm_neon.h" | ||
| 22108 | |||
| 22109 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c | ||
| 22110 | =================================================================== | ||
| 22111 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c | ||
| 22112 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c | ||
| 22113 | @@ -3,7 +3,8 @@ | ||
| 22114 | |||
| 22115 | /* { dg-do assemble } */ | ||
| 22116 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22117 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22118 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22119 | +/* { dg-add-options arm_neon } */ | ||
| 22120 | |||
| 22121 | #include "arm_neon.h" | ||
| 22122 | |||
| 22123 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c | ||
| 22124 | =================================================================== | ||
| 22125 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c | ||
| 22126 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c | ||
| 22127 | @@ -3,7 +3,8 @@ | ||
| 22128 | |||
| 22129 | /* { dg-do assemble } */ | ||
| 22130 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22131 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22132 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22133 | +/* { dg-add-options arm_neon } */ | ||
| 22134 | |||
| 22135 | #include "arm_neon.h" | ||
| 22136 | |||
| 22137 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c | ||
| 22138 | =================================================================== | ||
| 22139 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c | ||
| 22140 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c | ||
| 22141 | @@ -3,7 +3,8 @@ | ||
| 22142 | |||
| 22143 | /* { dg-do assemble } */ | ||
| 22144 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22145 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22146 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22147 | +/* { dg-add-options arm_neon } */ | ||
| 22148 | |||
| 22149 | #include "arm_neon.h" | ||
| 22150 | |||
| 22151 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c | ||
| 22152 | =================================================================== | ||
| 22153 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c | ||
| 22154 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c | ||
| 22155 | @@ -3,7 +3,8 @@ | ||
| 22156 | |||
| 22157 | /* { dg-do assemble } */ | ||
| 22158 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22159 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22160 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22161 | +/* { dg-add-options arm_neon } */ | ||
| 22162 | |||
| 22163 | #include "arm_neon.h" | ||
| 22164 | |||
| 22165 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c | ||
| 22166 | =================================================================== | ||
| 22167 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c | ||
| 22168 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c | ||
| 22169 | @@ -3,7 +3,8 @@ | ||
| 22170 | |||
| 22171 | /* { dg-do assemble } */ | ||
| 22172 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22173 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22174 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22175 | +/* { dg-add-options arm_neon } */ | ||
| 22176 | |||
| 22177 | #include "arm_neon.h" | ||
| 22178 | |||
| 22179 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c | ||
| 22180 | =================================================================== | ||
| 22181 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c | ||
| 22182 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c | ||
| 22183 | @@ -3,7 +3,8 @@ | ||
| 22184 | |||
| 22185 | /* { dg-do assemble } */ | ||
| 22186 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22187 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22188 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22189 | +/* { dg-add-options arm_neon } */ | ||
| 22190 | |||
| 22191 | #include "arm_neon.h" | ||
| 22192 | |||
| 22193 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c | ||
| 22194 | =================================================================== | ||
| 22195 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c | ||
| 22196 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c | ||
| 22197 | @@ -3,7 +3,8 @@ | ||
| 22198 | |||
| 22199 | /* { dg-do assemble } */ | ||
| 22200 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22201 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22202 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22203 | +/* { dg-add-options arm_neon } */ | ||
| 22204 | |||
| 22205 | #include "arm_neon.h" | ||
| 22206 | |||
| 22207 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c | ||
| 22208 | =================================================================== | ||
| 22209 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c | ||
| 22210 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c | ||
| 22211 | @@ -3,7 +3,8 @@ | ||
| 22212 | |||
| 22213 | /* { dg-do assemble } */ | ||
| 22214 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22215 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22216 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22217 | +/* { dg-add-options arm_neon } */ | ||
| 22218 | |||
| 22219 | #include "arm_neon.h" | ||
| 22220 | |||
| 22221 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c | ||
| 22222 | =================================================================== | ||
| 22223 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c | ||
| 22224 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c | ||
| 22225 | @@ -3,7 +3,8 @@ | ||
| 22226 | |||
| 22227 | /* { dg-do assemble } */ | ||
| 22228 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22229 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22230 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22231 | +/* { dg-add-options arm_neon } */ | ||
| 22232 | |||
| 22233 | #include "arm_neon.h" | ||
| 22234 | |||
| 22235 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c | ||
| 22236 | =================================================================== | ||
| 22237 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c | ||
| 22238 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c | ||
| 22239 | @@ -3,7 +3,8 @@ | ||
| 22240 | |||
| 22241 | /* { dg-do assemble } */ | ||
| 22242 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22243 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22244 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22245 | +/* { dg-add-options arm_neon } */ | ||
| 22246 | |||
| 22247 | #include "arm_neon.h" | ||
| 22248 | |||
| 22249 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c | ||
| 22250 | =================================================================== | ||
| 22251 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c | ||
| 22252 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c | ||
| 22253 | @@ -3,7 +3,8 @@ | ||
| 22254 | |||
| 22255 | /* { dg-do assemble } */ | ||
| 22256 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22257 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22258 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22259 | +/* { dg-add-options arm_neon } */ | ||
| 22260 | |||
| 22261 | #include "arm_neon.h" | ||
| 22262 | |||
| 22263 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c | ||
| 22264 | =================================================================== | ||
| 22265 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c | ||
| 22266 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c | ||
| 22267 | @@ -3,7 +3,8 @@ | ||
| 22268 | |||
| 22269 | /* { dg-do assemble } */ | ||
| 22270 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22271 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22272 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22273 | +/* { dg-add-options arm_neon } */ | ||
| 22274 | |||
| 22275 | #include "arm_neon.h" | ||
| 22276 | |||
| 22277 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c | ||
| 22278 | =================================================================== | ||
| 22279 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c | ||
| 22280 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c | ||
| 22281 | @@ -3,7 +3,8 @@ | ||
| 22282 | |||
| 22283 | /* { dg-do assemble } */ | ||
| 22284 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22285 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22286 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22287 | +/* { dg-add-options arm_neon } */ | ||
| 22288 | |||
| 22289 | #include "arm_neon.h" | ||
| 22290 | |||
| 22291 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c | ||
| 22292 | =================================================================== | ||
| 22293 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c | ||
| 22294 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c | ||
| 22295 | @@ -3,7 +3,8 @@ | ||
| 22296 | |||
| 22297 | /* { dg-do assemble } */ | ||
| 22298 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22299 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22300 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22301 | +/* { dg-add-options arm_neon } */ | ||
| 22302 | |||
| 22303 | #include "arm_neon.h" | ||
| 22304 | |||
| 22305 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c | ||
| 22306 | =================================================================== | ||
| 22307 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c | ||
| 22308 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c | ||
| 22309 | @@ -3,7 +3,8 @@ | ||
| 22310 | |||
| 22311 | /* { dg-do assemble } */ | ||
| 22312 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22313 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22314 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22315 | +/* { dg-add-options arm_neon } */ | ||
| 22316 | |||
| 22317 | #include "arm_neon.h" | ||
| 22318 | |||
| 22319 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c | ||
| 22320 | =================================================================== | ||
| 22321 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c | ||
| 22322 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c | ||
| 22323 | @@ -3,7 +3,8 @@ | ||
| 22324 | |||
| 22325 | /* { dg-do assemble } */ | ||
| 22326 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22327 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22328 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22329 | +/* { dg-add-options arm_neon } */ | ||
| 22330 | |||
| 22331 | #include "arm_neon.h" | ||
| 22332 | |||
| 22333 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c | ||
| 22334 | =================================================================== | ||
| 22335 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c | ||
| 22336 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c | ||
| 22337 | @@ -3,7 +3,8 @@ | ||
| 22338 | |||
| 22339 | /* { dg-do assemble } */ | ||
| 22340 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22341 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22342 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22343 | +/* { dg-add-options arm_neon } */ | ||
| 22344 | |||
| 22345 | #include "arm_neon.h" | ||
| 22346 | |||
| 22347 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c | ||
| 22348 | =================================================================== | ||
| 22349 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c | ||
| 22350 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c | ||
| 22351 | @@ -3,7 +3,8 @@ | ||
| 22352 | |||
| 22353 | /* { dg-do assemble } */ | ||
| 22354 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22355 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22356 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22357 | +/* { dg-add-options arm_neon } */ | ||
| 22358 | |||
| 22359 | #include "arm_neon.h" | ||
| 22360 | |||
| 22361 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c | ||
| 22362 | =================================================================== | ||
| 22363 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c | ||
| 22364 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c | ||
| 22365 | @@ -3,7 +3,8 @@ | ||
| 22366 | |||
| 22367 | /* { dg-do assemble } */ | ||
| 22368 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22369 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22370 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22371 | +/* { dg-add-options arm_neon } */ | ||
| 22372 | |||
| 22373 | #include "arm_neon.h" | ||
| 22374 | |||
| 22375 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c | ||
| 22376 | =================================================================== | ||
| 22377 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c | ||
| 22378 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c | ||
| 22379 | @@ -3,7 +3,8 @@ | ||
| 22380 | |||
| 22381 | /* { dg-do assemble } */ | ||
| 22382 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22383 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22384 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22385 | +/* { dg-add-options arm_neon } */ | ||
| 22386 | |||
| 22387 | #include "arm_neon.h" | ||
| 22388 | |||
| 22389 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c | ||
| 22390 | =================================================================== | ||
| 22391 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c | ||
| 22392 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c | ||
| 22393 | @@ -3,7 +3,8 @@ | ||
| 22394 | |||
| 22395 | /* { dg-do assemble } */ | ||
| 22396 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22397 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22398 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22399 | +/* { dg-add-options arm_neon } */ | ||
| 22400 | |||
| 22401 | #include "arm_neon.h" | ||
| 22402 | |||
| 22403 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c | ||
| 22404 | =================================================================== | ||
| 22405 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c | ||
| 22406 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c | ||
| 22407 | @@ -3,7 +3,8 @@ | ||
| 22408 | |||
| 22409 | /* { dg-do assemble } */ | ||
| 22410 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22411 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22412 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22413 | +/* { dg-add-options arm_neon } */ | ||
| 22414 | |||
| 22415 | #include "arm_neon.h" | ||
| 22416 | |||
| 22417 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c | ||
| 22418 | =================================================================== | ||
| 22419 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c | ||
| 22420 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c | ||
| 22421 | @@ -3,7 +3,8 @@ | ||
| 22422 | |||
| 22423 | /* { dg-do assemble } */ | ||
| 22424 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22425 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22426 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22427 | +/* { dg-add-options arm_neon } */ | ||
| 22428 | |||
| 22429 | #include "arm_neon.h" | ||
| 22430 | |||
| 22431 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c | ||
| 22432 | =================================================================== | ||
| 22433 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c | ||
| 22434 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c | ||
| 22435 | @@ -3,7 +3,8 @@ | ||
| 22436 | |||
| 22437 | /* { dg-do assemble } */ | ||
| 22438 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22439 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22440 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22441 | +/* { dg-add-options arm_neon } */ | ||
| 22442 | |||
| 22443 | #include "arm_neon.h" | ||
| 22444 | |||
| 22445 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c | ||
| 22446 | =================================================================== | ||
| 22447 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c | ||
| 22448 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c | ||
| 22449 | @@ -3,7 +3,8 @@ | ||
| 22450 | |||
| 22451 | /* { dg-do assemble } */ | ||
| 22452 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22453 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22454 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22455 | +/* { dg-add-options arm_neon } */ | ||
| 22456 | |||
| 22457 | #include "arm_neon.h" | ||
| 22458 | |||
| 22459 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c | ||
| 22460 | =================================================================== | ||
| 22461 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c | ||
| 22462 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c | ||
| 22463 | @@ -3,7 +3,8 @@ | ||
| 22464 | |||
| 22465 | /* { dg-do assemble } */ | ||
| 22466 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22467 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22468 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22469 | +/* { dg-add-options arm_neon } */ | ||
| 22470 | |||
| 22471 | #include "arm_neon.h" | ||
| 22472 | |||
| 22473 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c | ||
| 22474 | =================================================================== | ||
| 22475 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c | ||
| 22476 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c | ||
| 22477 | @@ -3,7 +3,8 @@ | ||
| 22478 | |||
| 22479 | /* { dg-do assemble } */ | ||
| 22480 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22481 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22482 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22483 | +/* { dg-add-options arm_neon } */ | ||
| 22484 | |||
| 22485 | #include "arm_neon.h" | ||
| 22486 | |||
| 22487 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c | ||
| 22488 | =================================================================== | ||
| 22489 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c | ||
| 22490 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c | ||
| 22491 | @@ -3,7 +3,8 @@ | ||
| 22492 | |||
| 22493 | /* { dg-do assemble } */ | ||
| 22494 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22495 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22496 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22497 | +/* { dg-add-options arm_neon } */ | ||
| 22498 | |||
| 22499 | #include "arm_neon.h" | ||
| 22500 | |||
| 22501 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c | ||
| 22502 | =================================================================== | ||
| 22503 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c | ||
| 22504 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c | ||
| 22505 | @@ -3,7 +3,8 @@ | ||
| 22506 | |||
| 22507 | /* { dg-do assemble } */ | ||
| 22508 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22509 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22510 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22511 | +/* { dg-add-options arm_neon } */ | ||
| 22512 | |||
| 22513 | #include "arm_neon.h" | ||
| 22514 | |||
| 22515 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c | ||
| 22516 | =================================================================== | ||
| 22517 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c | ||
| 22518 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c | ||
| 22519 | @@ -3,7 +3,8 @@ | ||
| 22520 | |||
| 22521 | /* { dg-do assemble } */ | ||
| 22522 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22523 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22524 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22525 | +/* { dg-add-options arm_neon } */ | ||
| 22526 | |||
| 22527 | #include "arm_neon.h" | ||
| 22528 | |||
| 22529 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c | ||
| 22530 | =================================================================== | ||
| 22531 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c | ||
| 22532 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c | ||
| 22533 | @@ -3,7 +3,8 @@ | ||
| 22534 | |||
| 22535 | /* { dg-do assemble } */ | ||
| 22536 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22537 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22538 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22539 | +/* { dg-add-options arm_neon } */ | ||
| 22540 | |||
| 22541 | #include "arm_neon.h" | ||
| 22542 | |||
| 22543 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c | ||
| 22544 | =================================================================== | ||
| 22545 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c | ||
| 22546 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c | ||
| 22547 | @@ -3,7 +3,8 @@ | ||
| 22548 | |||
| 22549 | /* { dg-do assemble } */ | ||
| 22550 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22551 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22552 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22553 | +/* { dg-add-options arm_neon } */ | ||
| 22554 | |||
| 22555 | #include "arm_neon.h" | ||
| 22556 | |||
| 22557 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c | ||
| 22558 | =================================================================== | ||
| 22559 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c | ||
| 22560 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c | ||
| 22561 | @@ -3,7 +3,8 @@ | ||
| 22562 | |||
| 22563 | /* { dg-do assemble } */ | ||
| 22564 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22565 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22566 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22567 | +/* { dg-add-options arm_neon } */ | ||
| 22568 | |||
| 22569 | #include "arm_neon.h" | ||
| 22570 | |||
| 22571 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c | ||
| 22572 | =================================================================== | ||
| 22573 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c | ||
| 22574 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c | ||
| 22575 | @@ -3,7 +3,8 @@ | ||
| 22576 | |||
| 22577 | /* { dg-do assemble } */ | ||
| 22578 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22579 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22580 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22581 | +/* { dg-add-options arm_neon } */ | ||
| 22582 | |||
| 22583 | #include "arm_neon.h" | ||
| 22584 | |||
| 22585 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c | ||
| 22586 | =================================================================== | ||
| 22587 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c | ||
| 22588 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c | ||
| 22589 | @@ -3,7 +3,8 @@ | ||
| 22590 | |||
| 22591 | /* { dg-do assemble } */ | ||
| 22592 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22593 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22594 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22595 | +/* { dg-add-options arm_neon } */ | ||
| 22596 | |||
| 22597 | #include "arm_neon.h" | ||
| 22598 | |||
| 22599 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c | ||
| 22600 | =================================================================== | ||
| 22601 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c | ||
| 22602 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c | ||
| 22603 | @@ -3,7 +3,8 @@ | ||
| 22604 | |||
| 22605 | /* { dg-do assemble } */ | ||
| 22606 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22607 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22608 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22609 | +/* { dg-add-options arm_neon } */ | ||
| 22610 | |||
| 22611 | #include "arm_neon.h" | ||
| 22612 | |||
| 22613 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c | ||
| 22614 | =================================================================== | ||
| 22615 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c | ||
| 22616 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c | ||
| 22617 | @@ -3,7 +3,8 @@ | ||
| 22618 | |||
| 22619 | /* { dg-do assemble } */ | ||
| 22620 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22621 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22622 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22623 | +/* { dg-add-options arm_neon } */ | ||
| 22624 | |||
| 22625 | #include "arm_neon.h" | ||
| 22626 | |||
| 22627 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c | ||
| 22628 | =================================================================== | ||
| 22629 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c | ||
| 22630 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c | ||
| 22631 | @@ -3,7 +3,8 @@ | ||
| 22632 | |||
| 22633 | /* { dg-do assemble } */ | ||
| 22634 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22635 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22636 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22637 | +/* { dg-add-options arm_neon } */ | ||
| 22638 | |||
| 22639 | #include "arm_neon.h" | ||
| 22640 | |||
| 22641 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c | ||
| 22642 | =================================================================== | ||
| 22643 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c | ||
| 22644 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c | ||
| 22645 | @@ -3,7 +3,8 @@ | ||
| 22646 | |||
| 22647 | /* { dg-do assemble } */ | ||
| 22648 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22649 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22650 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22651 | +/* { dg-add-options arm_neon } */ | ||
| 22652 | |||
| 22653 | #include "arm_neon.h" | ||
| 22654 | |||
| 22655 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c | ||
| 22656 | =================================================================== | ||
| 22657 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c | ||
| 22658 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c | ||
| 22659 | @@ -3,7 +3,8 @@ | ||
| 22660 | |||
| 22661 | /* { dg-do assemble } */ | ||
| 22662 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22663 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22664 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22665 | +/* { dg-add-options arm_neon } */ | ||
| 22666 | |||
| 22667 | #include "arm_neon.h" | ||
| 22668 | |||
| 22669 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c | ||
| 22670 | =================================================================== | ||
| 22671 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c | ||
| 22672 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c | ||
| 22673 | @@ -3,7 +3,8 @@ | ||
| 22674 | |||
| 22675 | /* { dg-do assemble } */ | ||
| 22676 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22677 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22678 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22679 | +/* { dg-add-options arm_neon } */ | ||
| 22680 | |||
| 22681 | #include "arm_neon.h" | ||
| 22682 | |||
| 22683 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c | ||
| 22684 | =================================================================== | ||
| 22685 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c | ||
| 22686 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c | ||
| 22687 | @@ -3,7 +3,8 @@ | ||
| 22688 | |||
| 22689 | /* { dg-do assemble } */ | ||
| 22690 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22691 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22692 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22693 | +/* { dg-add-options arm_neon } */ | ||
| 22694 | |||
| 22695 | #include "arm_neon.h" | ||
| 22696 | |||
| 22697 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c | ||
| 22698 | =================================================================== | ||
| 22699 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c | ||
| 22700 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c | ||
| 22701 | @@ -3,7 +3,8 @@ | ||
| 22702 | |||
| 22703 | /* { dg-do assemble } */ | ||
| 22704 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22705 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22706 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22707 | +/* { dg-add-options arm_neon } */ | ||
| 22708 | |||
| 22709 | #include "arm_neon.h" | ||
| 22710 | |||
| 22711 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c | ||
| 22712 | =================================================================== | ||
| 22713 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c | ||
| 22714 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c | ||
| 22715 | @@ -3,7 +3,8 @@ | ||
| 22716 | |||
| 22717 | /* { dg-do assemble } */ | ||
| 22718 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22719 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22720 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22721 | +/* { dg-add-options arm_neon } */ | ||
| 22722 | |||
| 22723 | #include "arm_neon.h" | ||
| 22724 | |||
| 22725 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c | ||
| 22726 | =================================================================== | ||
| 22727 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c | ||
| 22728 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c | ||
| 22729 | @@ -3,7 +3,8 @@ | ||
| 22730 | |||
| 22731 | /* { dg-do assemble } */ | ||
| 22732 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22733 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22734 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22735 | +/* { dg-add-options arm_neon } */ | ||
| 22736 | |||
| 22737 | #include "arm_neon.h" | ||
| 22738 | |||
| 22739 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c | ||
| 22740 | =================================================================== | ||
| 22741 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c | ||
| 22742 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c | ||
| 22743 | @@ -3,7 +3,8 @@ | ||
| 22744 | |||
| 22745 | /* { dg-do assemble } */ | ||
| 22746 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22747 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22748 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22749 | +/* { dg-add-options arm_neon } */ | ||
| 22750 | |||
| 22751 | #include "arm_neon.h" | ||
| 22752 | |||
| 22753 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c | ||
| 22754 | =================================================================== | ||
| 22755 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c | ||
| 22756 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c | ||
| 22757 | @@ -3,7 +3,8 @@ | ||
| 22758 | |||
| 22759 | /* { dg-do assemble } */ | ||
| 22760 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22761 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22762 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22763 | +/* { dg-add-options arm_neon } */ | ||
| 22764 | |||
| 22765 | #include "arm_neon.h" | ||
| 22766 | |||
| 22767 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c | ||
| 22768 | =================================================================== | ||
| 22769 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c | ||
| 22770 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c | ||
| 22771 | @@ -3,7 +3,8 @@ | ||
| 22772 | |||
| 22773 | /* { dg-do assemble } */ | ||
| 22774 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22775 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22776 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22777 | +/* { dg-add-options arm_neon } */ | ||
| 22778 | |||
| 22779 | #include "arm_neon.h" | ||
| 22780 | |||
| 22781 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c | ||
| 22782 | =================================================================== | ||
| 22783 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c | ||
| 22784 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c | ||
| 22785 | @@ -3,7 +3,8 @@ | ||
| 22786 | |||
| 22787 | /* { dg-do assemble } */ | ||
| 22788 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22789 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22790 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22791 | +/* { dg-add-options arm_neon } */ | ||
| 22792 | |||
| 22793 | #include "arm_neon.h" | ||
| 22794 | |||
| 22795 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c | ||
| 22796 | =================================================================== | ||
| 22797 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c | ||
| 22798 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c | ||
| 22799 | @@ -3,7 +3,8 @@ | ||
| 22800 | |||
| 22801 | /* { dg-do assemble } */ | ||
| 22802 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22803 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22804 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22805 | +/* { dg-add-options arm_neon } */ | ||
| 22806 | |||
| 22807 | #include "arm_neon.h" | ||
| 22808 | |||
| 22809 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c | ||
| 22810 | =================================================================== | ||
| 22811 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c | ||
| 22812 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c | ||
| 22813 | @@ -3,7 +3,8 @@ | ||
| 22814 | |||
| 22815 | /* { dg-do assemble } */ | ||
| 22816 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22817 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22818 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22819 | +/* { dg-add-options arm_neon } */ | ||
| 22820 | |||
| 22821 | #include "arm_neon.h" | ||
| 22822 | |||
| 22823 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c | ||
| 22824 | =================================================================== | ||
| 22825 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c | ||
| 22826 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c | ||
| 22827 | @@ -3,7 +3,8 @@ | ||
| 22828 | |||
| 22829 | /* { dg-do assemble } */ | ||
| 22830 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22831 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22832 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22833 | +/* { dg-add-options arm_neon } */ | ||
| 22834 | |||
| 22835 | #include "arm_neon.h" | ||
| 22836 | |||
| 22837 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c | ||
| 22838 | =================================================================== | ||
| 22839 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c | ||
| 22840 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c | ||
| 22841 | @@ -3,7 +3,8 @@ | ||
| 22842 | |||
| 22843 | /* { dg-do assemble } */ | ||
| 22844 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22845 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22846 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22847 | +/* { dg-add-options arm_neon } */ | ||
| 22848 | |||
| 22849 | #include "arm_neon.h" | ||
| 22850 | |||
| 22851 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c | ||
| 22852 | =================================================================== | ||
| 22853 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c | ||
| 22854 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c | ||
| 22855 | @@ -3,7 +3,8 @@ | ||
| 22856 | |||
| 22857 | /* { dg-do assemble } */ | ||
| 22858 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22859 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22860 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22861 | +/* { dg-add-options arm_neon } */ | ||
| 22862 | |||
| 22863 | #include "arm_neon.h" | ||
| 22864 | |||
| 22865 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c | ||
| 22866 | =================================================================== | ||
| 22867 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c | ||
| 22868 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c | ||
| 22869 | @@ -3,7 +3,8 @@ | ||
| 22870 | |||
| 22871 | /* { dg-do assemble } */ | ||
| 22872 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22873 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22874 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22875 | +/* { dg-add-options arm_neon } */ | ||
| 22876 | |||
| 22877 | #include "arm_neon.h" | ||
| 22878 | |||
| 22879 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c | ||
| 22880 | =================================================================== | ||
| 22881 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c | ||
| 22882 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c | ||
| 22883 | @@ -3,7 +3,8 @@ | ||
| 22884 | |||
| 22885 | /* { dg-do assemble } */ | ||
| 22886 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22887 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22888 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22889 | +/* { dg-add-options arm_neon } */ | ||
| 22890 | |||
| 22891 | #include "arm_neon.h" | ||
| 22892 | |||
| 22893 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c | ||
| 22894 | =================================================================== | ||
| 22895 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c | ||
| 22896 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c | ||
| 22897 | @@ -3,7 +3,8 @@ | ||
| 22898 | |||
| 22899 | /* { dg-do assemble } */ | ||
| 22900 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22901 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22902 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22903 | +/* { dg-add-options arm_neon } */ | ||
| 22904 | |||
| 22905 | #include "arm_neon.h" | ||
| 22906 | |||
| 22907 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c | ||
| 22908 | =================================================================== | ||
| 22909 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c | ||
| 22910 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c | ||
| 22911 | @@ -3,7 +3,8 @@ | ||
| 22912 | |||
| 22913 | /* { dg-do assemble } */ | ||
| 22914 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22915 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22916 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22917 | +/* { dg-add-options arm_neon } */ | ||
| 22918 | |||
| 22919 | #include "arm_neon.h" | ||
| 22920 | |||
| 22921 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c | ||
| 22922 | =================================================================== | ||
| 22923 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c | ||
| 22924 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c | ||
| 22925 | @@ -3,7 +3,8 @@ | ||
| 22926 | |||
| 22927 | /* { dg-do assemble } */ | ||
| 22928 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22929 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22930 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22931 | +/* { dg-add-options arm_neon } */ | ||
| 22932 | |||
| 22933 | #include "arm_neon.h" | ||
| 22934 | |||
| 22935 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c | ||
| 22936 | =================================================================== | ||
| 22937 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c | ||
| 22938 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c | ||
| 22939 | @@ -3,7 +3,8 @@ | ||
| 22940 | |||
| 22941 | /* { dg-do assemble } */ | ||
| 22942 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22943 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22944 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22945 | +/* { dg-add-options arm_neon } */ | ||
| 22946 | |||
| 22947 | #include "arm_neon.h" | ||
| 22948 | |||
| 22949 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c | ||
| 22950 | =================================================================== | ||
| 22951 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c | ||
| 22952 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c | ||
| 22953 | @@ -3,7 +3,8 @@ | ||
| 22954 | |||
| 22955 | /* { dg-do assemble } */ | ||
| 22956 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22957 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22958 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22959 | +/* { dg-add-options arm_neon } */ | ||
| 22960 | |||
| 22961 | #include "arm_neon.h" | ||
| 22962 | |||
| 22963 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c | ||
| 22964 | =================================================================== | ||
| 22965 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c | ||
| 22966 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c | ||
| 22967 | @@ -3,7 +3,8 @@ | ||
| 22968 | |||
| 22969 | /* { dg-do assemble } */ | ||
| 22970 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22971 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22972 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22973 | +/* { dg-add-options arm_neon } */ | ||
| 22974 | |||
| 22975 | #include "arm_neon.h" | ||
| 22976 | |||
| 22977 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c | ||
| 22978 | =================================================================== | ||
| 22979 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c | ||
| 22980 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c | ||
| 22981 | @@ -3,7 +3,8 @@ | ||
| 22982 | |||
| 22983 | /* { dg-do assemble } */ | ||
| 22984 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22985 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 22986 | +/* { dg-options "-save-temps -O0" } */ | ||
| 22987 | +/* { dg-add-options arm_neon } */ | ||
| 22988 | |||
| 22989 | #include "arm_neon.h" | ||
| 22990 | |||
| 22991 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c | ||
| 22992 | =================================================================== | ||
| 22993 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c | ||
| 22994 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c | ||
| 22995 | @@ -3,7 +3,8 @@ | ||
| 22996 | |||
| 22997 | /* { dg-do assemble } */ | ||
| 22998 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 22999 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23000 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23001 | +/* { dg-add-options arm_neon } */ | ||
| 23002 | |||
| 23003 | #include "arm_neon.h" | ||
| 23004 | |||
| 23005 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c | ||
| 23006 | =================================================================== | ||
| 23007 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c | ||
| 23008 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c | ||
| 23009 | @@ -3,7 +3,8 @@ | ||
| 23010 | |||
| 23011 | /* { dg-do assemble } */ | ||
| 23012 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23013 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23014 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23015 | +/* { dg-add-options arm_neon } */ | ||
| 23016 | |||
| 23017 | #include "arm_neon.h" | ||
| 23018 | |||
| 23019 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c | ||
| 23020 | =================================================================== | ||
| 23021 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c | ||
| 23022 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c | ||
| 23023 | @@ -3,7 +3,8 @@ | ||
| 23024 | |||
| 23025 | /* { dg-do assemble } */ | ||
| 23026 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23027 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23028 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23029 | +/* { dg-add-options arm_neon } */ | ||
| 23030 | |||
| 23031 | #include "arm_neon.h" | ||
| 23032 | |||
| 23033 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c | ||
| 23034 | =================================================================== | ||
| 23035 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c | ||
| 23036 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c | ||
| 23037 | @@ -3,7 +3,8 @@ | ||
| 23038 | |||
| 23039 | /* { dg-do assemble } */ | ||
| 23040 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23041 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23042 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23043 | +/* { dg-add-options arm_neon } */ | ||
| 23044 | |||
| 23045 | #include "arm_neon.h" | ||
| 23046 | |||
| 23047 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c | ||
| 23048 | =================================================================== | ||
| 23049 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c | ||
| 23050 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c | ||
| 23051 | @@ -3,7 +3,8 @@ | ||
| 23052 | |||
| 23053 | /* { dg-do assemble } */ | ||
| 23054 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23055 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23056 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23057 | +/* { dg-add-options arm_neon } */ | ||
| 23058 | |||
| 23059 | #include "arm_neon.h" | ||
| 23060 | |||
| 23061 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c | ||
| 23062 | =================================================================== | ||
| 23063 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c | ||
| 23064 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c | ||
| 23065 | @@ -3,7 +3,8 @@ | ||
| 23066 | |||
| 23067 | /* { dg-do assemble } */ | ||
| 23068 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23069 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23070 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23071 | +/* { dg-add-options arm_neon } */ | ||
| 23072 | |||
| 23073 | #include "arm_neon.h" | ||
| 23074 | |||
| 23075 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c | ||
| 23076 | =================================================================== | ||
| 23077 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c | ||
| 23078 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c | ||
| 23079 | @@ -3,7 +3,8 @@ | ||
| 23080 | |||
| 23081 | /* { dg-do assemble } */ | ||
| 23082 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23083 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23084 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23085 | +/* { dg-add-options arm_neon } */ | ||
| 23086 | |||
| 23087 | #include "arm_neon.h" | ||
| 23088 | |||
| 23089 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c | ||
| 23090 | =================================================================== | ||
| 23091 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c | ||
| 23092 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c | ||
| 23093 | @@ -3,7 +3,8 @@ | ||
| 23094 | |||
| 23095 | /* { dg-do assemble } */ | ||
| 23096 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23097 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23098 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23099 | +/* { dg-add-options arm_neon } */ | ||
| 23100 | |||
| 23101 | #include "arm_neon.h" | ||
| 23102 | |||
| 23103 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c | ||
| 23104 | =================================================================== | ||
| 23105 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c | ||
| 23106 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c | ||
| 23107 | @@ -3,7 +3,8 @@ | ||
| 23108 | |||
| 23109 | /* { dg-do assemble } */ | ||
| 23110 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23111 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23112 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23113 | +/* { dg-add-options arm_neon } */ | ||
| 23114 | |||
| 23115 | #include "arm_neon.h" | ||
| 23116 | |||
| 23117 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1f32.c | ||
| 23118 | =================================================================== | ||
| 23119 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1f32.c | ||
| 23120 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1f32.c | ||
| 23121 | @@ -3,7 +3,8 @@ | ||
| 23122 | |||
| 23123 | /* { dg-do assemble } */ | ||
| 23124 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23125 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23126 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23127 | +/* { dg-add-options arm_neon } */ | ||
| 23128 | |||
| 23129 | #include "arm_neon.h" | ||
| 23130 | |||
| 23131 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1p16.c | ||
| 23132 | =================================================================== | ||
| 23133 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1p16.c | ||
| 23134 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1p16.c | ||
| 23135 | @@ -3,7 +3,8 @@ | ||
| 23136 | |||
| 23137 | /* { dg-do assemble } */ | ||
| 23138 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23139 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23140 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23141 | +/* { dg-add-options arm_neon } */ | ||
| 23142 | |||
| 23143 | #include "arm_neon.h" | ||
| 23144 | |||
| 23145 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1p8.c | ||
| 23146 | =================================================================== | ||
| 23147 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1p8.c | ||
| 23148 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1p8.c | ||
| 23149 | @@ -3,7 +3,8 @@ | ||
| 23150 | |||
| 23151 | /* { dg-do assemble } */ | ||
| 23152 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23153 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23154 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23155 | +/* { dg-add-options arm_neon } */ | ||
| 23156 | |||
| 23157 | #include "arm_neon.h" | ||
| 23158 | |||
| 23159 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s16.c | ||
| 23160 | =================================================================== | ||
| 23161 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s16.c | ||
| 23162 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s16.c | ||
| 23163 | @@ -3,7 +3,8 @@ | ||
| 23164 | |||
| 23165 | /* { dg-do assemble } */ | ||
| 23166 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23167 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23168 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23169 | +/* { dg-add-options arm_neon } */ | ||
| 23170 | |||
| 23171 | #include "arm_neon.h" | ||
| 23172 | |||
| 23173 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s32.c | ||
| 23174 | =================================================================== | ||
| 23175 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s32.c | ||
| 23176 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s32.c | ||
| 23177 | @@ -3,7 +3,8 @@ | ||
| 23178 | |||
| 23179 | /* { dg-do assemble } */ | ||
| 23180 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23181 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23182 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23183 | +/* { dg-add-options arm_neon } */ | ||
| 23184 | |||
| 23185 | #include "arm_neon.h" | ||
| 23186 | |||
| 23187 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s64.c | ||
| 23188 | =================================================================== | ||
| 23189 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s64.c | ||
| 23190 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s64.c | ||
| 23191 | @@ -3,7 +3,8 @@ | ||
| 23192 | |||
| 23193 | /* { dg-do assemble } */ | ||
| 23194 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23195 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23196 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23197 | +/* { dg-add-options arm_neon } */ | ||
| 23198 | |||
| 23199 | #include "arm_neon.h" | ||
| 23200 | |||
| 23201 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s8.c | ||
| 23202 | =================================================================== | ||
| 23203 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s8.c | ||
| 23204 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1s8.c | ||
| 23205 | @@ -3,7 +3,8 @@ | ||
| 23206 | |||
| 23207 | /* { dg-do assemble } */ | ||
| 23208 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23209 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23210 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23211 | +/* { dg-add-options arm_neon } */ | ||
| 23212 | |||
| 23213 | #include "arm_neon.h" | ||
| 23214 | |||
| 23215 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u16.c | ||
| 23216 | =================================================================== | ||
| 23217 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u16.c | ||
| 23218 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u16.c | ||
| 23219 | @@ -3,7 +3,8 @@ | ||
| 23220 | |||
| 23221 | /* { dg-do assemble } */ | ||
| 23222 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23223 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23224 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23225 | +/* { dg-add-options arm_neon } */ | ||
| 23226 | |||
| 23227 | #include "arm_neon.h" | ||
| 23228 | |||
| 23229 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u32.c | ||
| 23230 | =================================================================== | ||
| 23231 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u32.c | ||
| 23232 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u32.c | ||
| 23233 | @@ -3,7 +3,8 @@ | ||
| 23234 | |||
| 23235 | /* { dg-do assemble } */ | ||
| 23236 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23237 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23238 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23239 | +/* { dg-add-options arm_neon } */ | ||
| 23240 | |||
| 23241 | #include "arm_neon.h" | ||
| 23242 | |||
| 23243 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u64.c | ||
| 23244 | =================================================================== | ||
| 23245 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u64.c | ||
| 23246 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u64.c | ||
| 23247 | @@ -3,7 +3,8 @@ | ||
| 23248 | |||
| 23249 | /* { dg-do assemble } */ | ||
| 23250 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23251 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23252 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23253 | +/* { dg-add-options arm_neon } */ | ||
| 23254 | |||
| 23255 | #include "arm_neon.h" | ||
| 23256 | |||
| 23257 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u8.c | ||
| 23258 | =================================================================== | ||
| 23259 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u8.c | ||
| 23260 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst1u8.c | ||
| 23261 | @@ -3,7 +3,8 @@ | ||
| 23262 | |||
| 23263 | /* { dg-do assemble } */ | ||
| 23264 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23265 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23266 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23267 | +/* { dg-add-options arm_neon } */ | ||
| 23268 | |||
| 23269 | #include "arm_neon.h" | ||
| 23270 | |||
| 23271 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c | ||
| 23272 | =================================================================== | ||
| 23273 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c | ||
| 23274 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c | ||
| 23275 | @@ -3,7 +3,8 @@ | ||
| 23276 | |||
| 23277 | /* { dg-do assemble } */ | ||
| 23278 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23279 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23280 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23281 | +/* { dg-add-options arm_neon } */ | ||
| 23282 | |||
| 23283 | #include "arm_neon.h" | ||
| 23284 | |||
| 23285 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c | ||
| 23286 | =================================================================== | ||
| 23287 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c | ||
| 23288 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c | ||
| 23289 | @@ -3,7 +3,8 @@ | ||
| 23290 | |||
| 23291 | /* { dg-do assemble } */ | ||
| 23292 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23293 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23294 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23295 | +/* { dg-add-options arm_neon } */ | ||
| 23296 | |||
| 23297 | #include "arm_neon.h" | ||
| 23298 | |||
| 23299 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c | ||
| 23300 | =================================================================== | ||
| 23301 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c | ||
| 23302 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c | ||
| 23303 | @@ -3,7 +3,8 @@ | ||
| 23304 | |||
| 23305 | /* { dg-do assemble } */ | ||
| 23306 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23307 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23308 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23309 | +/* { dg-add-options arm_neon } */ | ||
| 23310 | |||
| 23311 | #include "arm_neon.h" | ||
| 23312 | |||
| 23313 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c | ||
| 23314 | =================================================================== | ||
| 23315 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c | ||
| 23316 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c | ||
| 23317 | @@ -3,7 +3,8 @@ | ||
| 23318 | |||
| 23319 | /* { dg-do assemble } */ | ||
| 23320 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23321 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23322 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23323 | +/* { dg-add-options arm_neon } */ | ||
| 23324 | |||
| 23325 | #include "arm_neon.h" | ||
| 23326 | |||
| 23327 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c | ||
| 23328 | =================================================================== | ||
| 23329 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c | ||
| 23330 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c | ||
| 23331 | @@ -3,7 +3,8 @@ | ||
| 23332 | |||
| 23333 | /* { dg-do assemble } */ | ||
| 23334 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23335 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23336 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23337 | +/* { dg-add-options arm_neon } */ | ||
| 23338 | |||
| 23339 | #include "arm_neon.h" | ||
| 23340 | |||
| 23341 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c | ||
| 23342 | =================================================================== | ||
| 23343 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c | ||
| 23344 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c | ||
| 23345 | @@ -3,7 +3,8 @@ | ||
| 23346 | |||
| 23347 | /* { dg-do assemble } */ | ||
| 23348 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23349 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23350 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23351 | +/* { dg-add-options arm_neon } */ | ||
| 23352 | |||
| 23353 | #include "arm_neon.h" | ||
| 23354 | |||
| 23355 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c | ||
| 23356 | =================================================================== | ||
| 23357 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c | ||
| 23358 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c | ||
| 23359 | @@ -3,7 +3,8 @@ | ||
| 23360 | |||
| 23361 | /* { dg-do assemble } */ | ||
| 23362 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23363 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23364 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23365 | +/* { dg-add-options arm_neon } */ | ||
| 23366 | |||
| 23367 | #include "arm_neon.h" | ||
| 23368 | |||
| 23369 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c | ||
| 23370 | =================================================================== | ||
| 23371 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c | ||
| 23372 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c | ||
| 23373 | @@ -3,7 +3,8 @@ | ||
| 23374 | |||
| 23375 | /* { dg-do assemble } */ | ||
| 23376 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23377 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23378 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23379 | +/* { dg-add-options arm_neon } */ | ||
| 23380 | |||
| 23381 | #include "arm_neon.h" | ||
| 23382 | |||
| 23383 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c | ||
| 23384 | =================================================================== | ||
| 23385 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c | ||
| 23386 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c | ||
| 23387 | @@ -3,7 +3,8 @@ | ||
| 23388 | |||
| 23389 | /* { dg-do assemble } */ | ||
| 23390 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23391 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23392 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23393 | +/* { dg-add-options arm_neon } */ | ||
| 23394 | |||
| 23395 | #include "arm_neon.h" | ||
| 23396 | |||
| 23397 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c | ||
| 23398 | =================================================================== | ||
| 23399 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c | ||
| 23400 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c | ||
| 23401 | @@ -3,7 +3,8 @@ | ||
| 23402 | |||
| 23403 | /* { dg-do assemble } */ | ||
| 23404 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23405 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23406 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23407 | +/* { dg-add-options arm_neon } */ | ||
| 23408 | |||
| 23409 | #include "arm_neon.h" | ||
| 23410 | |||
| 23411 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c | ||
| 23412 | =================================================================== | ||
| 23413 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c | ||
| 23414 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c | ||
| 23415 | @@ -3,7 +3,8 @@ | ||
| 23416 | |||
| 23417 | /* { dg-do assemble } */ | ||
| 23418 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23419 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23420 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23421 | +/* { dg-add-options arm_neon } */ | ||
| 23422 | |||
| 23423 | #include "arm_neon.h" | ||
| 23424 | |||
| 23425 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c | ||
| 23426 | =================================================================== | ||
| 23427 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c | ||
| 23428 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c | ||
| 23429 | @@ -3,7 +3,8 @@ | ||
| 23430 | |||
| 23431 | /* { dg-do assemble } */ | ||
| 23432 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23433 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23434 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23435 | +/* { dg-add-options arm_neon } */ | ||
| 23436 | |||
| 23437 | #include "arm_neon.h" | ||
| 23438 | |||
| 23439 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c | ||
| 23440 | =================================================================== | ||
| 23441 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c | ||
| 23442 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c | ||
| 23443 | @@ -3,7 +3,8 @@ | ||
| 23444 | |||
| 23445 | /* { dg-do assemble } */ | ||
| 23446 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23447 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23448 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23449 | +/* { dg-add-options arm_neon } */ | ||
| 23450 | |||
| 23451 | #include "arm_neon.h" | ||
| 23452 | |||
| 23453 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c | ||
| 23454 | =================================================================== | ||
| 23455 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c | ||
| 23456 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c | ||
| 23457 | @@ -3,7 +3,8 @@ | ||
| 23458 | |||
| 23459 | /* { dg-do assemble } */ | ||
| 23460 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23461 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23462 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23463 | +/* { dg-add-options arm_neon } */ | ||
| 23464 | |||
| 23465 | #include "arm_neon.h" | ||
| 23466 | |||
| 23467 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c | ||
| 23468 | =================================================================== | ||
| 23469 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c | ||
| 23470 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c | ||
| 23471 | @@ -3,7 +3,8 @@ | ||
| 23472 | |||
| 23473 | /* { dg-do assemble } */ | ||
| 23474 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23475 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23476 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23477 | +/* { dg-add-options arm_neon } */ | ||
| 23478 | |||
| 23479 | #include "arm_neon.h" | ||
| 23480 | |||
| 23481 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c | ||
| 23482 | =================================================================== | ||
| 23483 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c | ||
| 23484 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c | ||
| 23485 | @@ -3,7 +3,8 @@ | ||
| 23486 | |||
| 23487 | /* { dg-do assemble } */ | ||
| 23488 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23489 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23490 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23491 | +/* { dg-add-options arm_neon } */ | ||
| 23492 | |||
| 23493 | #include "arm_neon.h" | ||
| 23494 | |||
| 23495 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c | ||
| 23496 | =================================================================== | ||
| 23497 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c | ||
| 23498 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c | ||
| 23499 | @@ -3,7 +3,8 @@ | ||
| 23500 | |||
| 23501 | /* { dg-do assemble } */ | ||
| 23502 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23503 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23504 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23505 | +/* { dg-add-options arm_neon } */ | ||
| 23506 | |||
| 23507 | #include "arm_neon.h" | ||
| 23508 | |||
| 23509 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c | ||
| 23510 | =================================================================== | ||
| 23511 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c | ||
| 23512 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c | ||
| 23513 | @@ -3,7 +3,8 @@ | ||
| 23514 | |||
| 23515 | /* { dg-do assemble } */ | ||
| 23516 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23517 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23518 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23519 | +/* { dg-add-options arm_neon } */ | ||
| 23520 | |||
| 23521 | #include "arm_neon.h" | ||
| 23522 | |||
| 23523 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c | ||
| 23524 | =================================================================== | ||
| 23525 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c | ||
| 23526 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c | ||
| 23527 | @@ -3,7 +3,8 @@ | ||
| 23528 | |||
| 23529 | /* { dg-do assemble } */ | ||
| 23530 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23531 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23532 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23533 | +/* { dg-add-options arm_neon } */ | ||
| 23534 | |||
| 23535 | #include "arm_neon.h" | ||
| 23536 | |||
| 23537 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c | ||
| 23538 | =================================================================== | ||
| 23539 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c | ||
| 23540 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c | ||
| 23541 | @@ -3,7 +3,8 @@ | ||
| 23542 | |||
| 23543 | /* { dg-do assemble } */ | ||
| 23544 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23545 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23546 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23547 | +/* { dg-add-options arm_neon } */ | ||
| 23548 | |||
| 23549 | #include "arm_neon.h" | ||
| 23550 | |||
| 23551 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c | ||
| 23552 | =================================================================== | ||
| 23553 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c | ||
| 23554 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c | ||
| 23555 | @@ -3,7 +3,8 @@ | ||
| 23556 | |||
| 23557 | /* { dg-do assemble } */ | ||
| 23558 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23559 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23560 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23561 | +/* { dg-add-options arm_neon } */ | ||
| 23562 | |||
| 23563 | #include "arm_neon.h" | ||
| 23564 | |||
| 23565 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c | ||
| 23566 | =================================================================== | ||
| 23567 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c | ||
| 23568 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c | ||
| 23569 | @@ -3,7 +3,8 @@ | ||
| 23570 | |||
| 23571 | /* { dg-do assemble } */ | ||
| 23572 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23573 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23574 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23575 | +/* { dg-add-options arm_neon } */ | ||
| 23576 | |||
| 23577 | #include "arm_neon.h" | ||
| 23578 | |||
| 23579 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c | ||
| 23580 | =================================================================== | ||
| 23581 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c | ||
| 23582 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c | ||
| 23583 | @@ -3,7 +3,8 @@ | ||
| 23584 | |||
| 23585 | /* { dg-do assemble } */ | ||
| 23586 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23587 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23588 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23589 | +/* { dg-add-options arm_neon } */ | ||
| 23590 | |||
| 23591 | #include "arm_neon.h" | ||
| 23592 | |||
| 23593 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c | ||
| 23594 | =================================================================== | ||
| 23595 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c | ||
| 23596 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c | ||
| 23597 | @@ -3,7 +3,8 @@ | ||
| 23598 | |||
| 23599 | /* { dg-do assemble } */ | ||
| 23600 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23601 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23602 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23603 | +/* { dg-add-options arm_neon } */ | ||
| 23604 | |||
| 23605 | #include "arm_neon.h" | ||
| 23606 | |||
| 23607 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2f32.c | ||
| 23608 | =================================================================== | ||
| 23609 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2f32.c | ||
| 23610 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2f32.c | ||
| 23611 | @@ -3,7 +3,8 @@ | ||
| 23612 | |||
| 23613 | /* { dg-do assemble } */ | ||
| 23614 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23615 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23616 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23617 | +/* { dg-add-options arm_neon } */ | ||
| 23618 | |||
| 23619 | #include "arm_neon.h" | ||
| 23620 | |||
| 23621 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2p16.c | ||
| 23622 | =================================================================== | ||
| 23623 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2p16.c | ||
| 23624 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2p16.c | ||
| 23625 | @@ -3,7 +3,8 @@ | ||
| 23626 | |||
| 23627 | /* { dg-do assemble } */ | ||
| 23628 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23629 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23630 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23631 | +/* { dg-add-options arm_neon } */ | ||
| 23632 | |||
| 23633 | #include "arm_neon.h" | ||
| 23634 | |||
| 23635 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2p8.c | ||
| 23636 | =================================================================== | ||
| 23637 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2p8.c | ||
| 23638 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2p8.c | ||
| 23639 | @@ -3,7 +3,8 @@ | ||
| 23640 | |||
| 23641 | /* { dg-do assemble } */ | ||
| 23642 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23643 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23644 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23645 | +/* { dg-add-options arm_neon } */ | ||
| 23646 | |||
| 23647 | #include "arm_neon.h" | ||
| 23648 | |||
| 23649 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s16.c | ||
| 23650 | =================================================================== | ||
| 23651 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s16.c | ||
| 23652 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s16.c | ||
| 23653 | @@ -3,7 +3,8 @@ | ||
| 23654 | |||
| 23655 | /* { dg-do assemble } */ | ||
| 23656 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23657 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23658 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23659 | +/* { dg-add-options arm_neon } */ | ||
| 23660 | |||
| 23661 | #include "arm_neon.h" | ||
| 23662 | |||
| 23663 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s32.c | ||
| 23664 | =================================================================== | ||
| 23665 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s32.c | ||
| 23666 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s32.c | ||
| 23667 | @@ -3,7 +3,8 @@ | ||
| 23668 | |||
| 23669 | /* { dg-do assemble } */ | ||
| 23670 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23671 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23672 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23673 | +/* { dg-add-options arm_neon } */ | ||
| 23674 | |||
| 23675 | #include "arm_neon.h" | ||
| 23676 | |||
| 23677 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s64.c | ||
| 23678 | =================================================================== | ||
| 23679 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s64.c | ||
| 23680 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s64.c | ||
| 23681 | @@ -3,7 +3,8 @@ | ||
| 23682 | |||
| 23683 | /* { dg-do assemble } */ | ||
| 23684 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23685 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23686 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23687 | +/* { dg-add-options arm_neon } */ | ||
| 23688 | |||
| 23689 | #include "arm_neon.h" | ||
| 23690 | |||
| 23691 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s8.c | ||
| 23692 | =================================================================== | ||
| 23693 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s8.c | ||
| 23694 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2s8.c | ||
| 23695 | @@ -3,7 +3,8 @@ | ||
| 23696 | |||
| 23697 | /* { dg-do assemble } */ | ||
| 23698 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23699 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23700 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23701 | +/* { dg-add-options arm_neon } */ | ||
| 23702 | |||
| 23703 | #include "arm_neon.h" | ||
| 23704 | |||
| 23705 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u16.c | ||
| 23706 | =================================================================== | ||
| 23707 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u16.c | ||
| 23708 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u16.c | ||
| 23709 | @@ -3,7 +3,8 @@ | ||
| 23710 | |||
| 23711 | /* { dg-do assemble } */ | ||
| 23712 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23713 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23714 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23715 | +/* { dg-add-options arm_neon } */ | ||
| 23716 | |||
| 23717 | #include "arm_neon.h" | ||
| 23718 | |||
| 23719 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u32.c | ||
| 23720 | =================================================================== | ||
| 23721 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u32.c | ||
| 23722 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u32.c | ||
| 23723 | @@ -3,7 +3,8 @@ | ||
| 23724 | |||
| 23725 | /* { dg-do assemble } */ | ||
| 23726 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23727 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23728 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23729 | +/* { dg-add-options arm_neon } */ | ||
| 23730 | |||
| 23731 | #include "arm_neon.h" | ||
| 23732 | |||
| 23733 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u64.c | ||
| 23734 | =================================================================== | ||
| 23735 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u64.c | ||
| 23736 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u64.c | ||
| 23737 | @@ -3,7 +3,8 @@ | ||
| 23738 | |||
| 23739 | /* { dg-do assemble } */ | ||
| 23740 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23741 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23742 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23743 | +/* { dg-add-options arm_neon } */ | ||
| 23744 | |||
| 23745 | #include "arm_neon.h" | ||
| 23746 | |||
| 23747 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u8.c | ||
| 23748 | =================================================================== | ||
| 23749 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u8.c | ||
| 23750 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst2u8.c | ||
| 23751 | @@ -3,7 +3,8 @@ | ||
| 23752 | |||
| 23753 | /* { dg-do assemble } */ | ||
| 23754 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23755 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23756 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23757 | +/* { dg-add-options arm_neon } */ | ||
| 23758 | |||
| 23759 | #include "arm_neon.h" | ||
| 23760 | |||
| 23761 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c | ||
| 23762 | =================================================================== | ||
| 23763 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c | ||
| 23764 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c | ||
| 23765 | @@ -3,7 +3,8 @@ | ||
| 23766 | |||
| 23767 | /* { dg-do assemble } */ | ||
| 23768 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23769 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23770 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23771 | +/* { dg-add-options arm_neon } */ | ||
| 23772 | |||
| 23773 | #include "arm_neon.h" | ||
| 23774 | |||
| 23775 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c | ||
| 23776 | =================================================================== | ||
| 23777 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c | ||
| 23778 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c | ||
| 23779 | @@ -3,7 +3,8 @@ | ||
| 23780 | |||
| 23781 | /* { dg-do assemble } */ | ||
| 23782 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23783 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23784 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23785 | +/* { dg-add-options arm_neon } */ | ||
| 23786 | |||
| 23787 | #include "arm_neon.h" | ||
| 23788 | |||
| 23789 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c | ||
| 23790 | =================================================================== | ||
| 23791 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c | ||
| 23792 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c | ||
| 23793 | @@ -3,7 +3,8 @@ | ||
| 23794 | |||
| 23795 | /* { dg-do assemble } */ | ||
| 23796 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23797 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23798 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23799 | +/* { dg-add-options arm_neon } */ | ||
| 23800 | |||
| 23801 | #include "arm_neon.h" | ||
| 23802 | |||
| 23803 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c | ||
| 23804 | =================================================================== | ||
| 23805 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c | ||
| 23806 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c | ||
| 23807 | @@ -3,7 +3,8 @@ | ||
| 23808 | |||
| 23809 | /* { dg-do assemble } */ | ||
| 23810 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23811 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23812 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23813 | +/* { dg-add-options arm_neon } */ | ||
| 23814 | |||
| 23815 | #include "arm_neon.h" | ||
| 23816 | |||
| 23817 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c | ||
| 23818 | =================================================================== | ||
| 23819 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c | ||
| 23820 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c | ||
| 23821 | @@ -3,7 +3,8 @@ | ||
| 23822 | |||
| 23823 | /* { dg-do assemble } */ | ||
| 23824 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23825 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23826 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23827 | +/* { dg-add-options arm_neon } */ | ||
| 23828 | |||
| 23829 | #include "arm_neon.h" | ||
| 23830 | |||
| 23831 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c | ||
| 23832 | =================================================================== | ||
| 23833 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c | ||
| 23834 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c | ||
| 23835 | @@ -3,7 +3,8 @@ | ||
| 23836 | |||
| 23837 | /* { dg-do assemble } */ | ||
| 23838 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23839 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23840 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23841 | +/* { dg-add-options arm_neon } */ | ||
| 23842 | |||
| 23843 | #include "arm_neon.h" | ||
| 23844 | |||
| 23845 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c | ||
| 23846 | =================================================================== | ||
| 23847 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c | ||
| 23848 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c | ||
| 23849 | @@ -3,7 +3,8 @@ | ||
| 23850 | |||
| 23851 | /* { dg-do assemble } */ | ||
| 23852 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23853 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23854 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23855 | +/* { dg-add-options arm_neon } */ | ||
| 23856 | |||
| 23857 | #include "arm_neon.h" | ||
| 23858 | |||
| 23859 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c | ||
| 23860 | =================================================================== | ||
| 23861 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c | ||
| 23862 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c | ||
| 23863 | @@ -3,7 +3,8 @@ | ||
| 23864 | |||
| 23865 | /* { dg-do assemble } */ | ||
| 23866 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23867 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23868 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23869 | +/* { dg-add-options arm_neon } */ | ||
| 23870 | |||
| 23871 | #include "arm_neon.h" | ||
| 23872 | |||
| 23873 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c | ||
| 23874 | =================================================================== | ||
| 23875 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c | ||
| 23876 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c | ||
| 23877 | @@ -3,7 +3,8 @@ | ||
| 23878 | |||
| 23879 | /* { dg-do assemble } */ | ||
| 23880 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23881 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23882 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23883 | +/* { dg-add-options arm_neon } */ | ||
| 23884 | |||
| 23885 | #include "arm_neon.h" | ||
| 23886 | |||
| 23887 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c | ||
| 23888 | =================================================================== | ||
| 23889 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c | ||
| 23890 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c | ||
| 23891 | @@ -3,7 +3,8 @@ | ||
| 23892 | |||
| 23893 | /* { dg-do assemble } */ | ||
| 23894 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23895 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23896 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23897 | +/* { dg-add-options arm_neon } */ | ||
| 23898 | |||
| 23899 | #include "arm_neon.h" | ||
| 23900 | |||
| 23901 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c | ||
| 23902 | =================================================================== | ||
| 23903 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c | ||
| 23904 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c | ||
| 23905 | @@ -3,7 +3,8 @@ | ||
| 23906 | |||
| 23907 | /* { dg-do assemble } */ | ||
| 23908 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23909 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23910 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23911 | +/* { dg-add-options arm_neon } */ | ||
| 23912 | |||
| 23913 | #include "arm_neon.h" | ||
| 23914 | |||
| 23915 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c | ||
| 23916 | =================================================================== | ||
| 23917 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c | ||
| 23918 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c | ||
| 23919 | @@ -3,7 +3,8 @@ | ||
| 23920 | |||
| 23921 | /* { dg-do assemble } */ | ||
| 23922 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23923 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23924 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23925 | +/* { dg-add-options arm_neon } */ | ||
| 23926 | |||
| 23927 | #include "arm_neon.h" | ||
| 23928 | |||
| 23929 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c | ||
| 23930 | =================================================================== | ||
| 23931 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c | ||
| 23932 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c | ||
| 23933 | @@ -3,7 +3,8 @@ | ||
| 23934 | |||
| 23935 | /* { dg-do assemble } */ | ||
| 23936 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23937 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23938 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23939 | +/* { dg-add-options arm_neon } */ | ||
| 23940 | |||
| 23941 | #include "arm_neon.h" | ||
| 23942 | |||
| 23943 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c | ||
| 23944 | =================================================================== | ||
| 23945 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c | ||
| 23946 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c | ||
| 23947 | @@ -3,7 +3,8 @@ | ||
| 23948 | |||
| 23949 | /* { dg-do assemble } */ | ||
| 23950 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23951 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23952 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23953 | +/* { dg-add-options arm_neon } */ | ||
| 23954 | |||
| 23955 | #include "arm_neon.h" | ||
| 23956 | |||
| 23957 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c | ||
| 23958 | =================================================================== | ||
| 23959 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c | ||
| 23960 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c | ||
| 23961 | @@ -3,7 +3,8 @@ | ||
| 23962 | |||
| 23963 | /* { dg-do assemble } */ | ||
| 23964 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23965 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23966 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23967 | +/* { dg-add-options arm_neon } */ | ||
| 23968 | |||
| 23969 | #include "arm_neon.h" | ||
| 23970 | |||
| 23971 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c | ||
| 23972 | =================================================================== | ||
| 23973 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c | ||
| 23974 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c | ||
| 23975 | @@ -3,7 +3,8 @@ | ||
| 23976 | |||
| 23977 | /* { dg-do assemble } */ | ||
| 23978 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23979 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23980 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23981 | +/* { dg-add-options arm_neon } */ | ||
| 23982 | |||
| 23983 | #include "arm_neon.h" | ||
| 23984 | |||
| 23985 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c | ||
| 23986 | =================================================================== | ||
| 23987 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c | ||
| 23988 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c | ||
| 23989 | @@ -3,7 +3,8 @@ | ||
| 23990 | |||
| 23991 | /* { dg-do assemble } */ | ||
| 23992 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 23993 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 23994 | +/* { dg-options "-save-temps -O0" } */ | ||
| 23995 | +/* { dg-add-options arm_neon } */ | ||
| 23996 | |||
| 23997 | #include "arm_neon.h" | ||
| 23998 | |||
| 23999 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c | ||
| 24000 | =================================================================== | ||
| 24001 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c | ||
| 24002 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c | ||
| 24003 | @@ -3,7 +3,8 @@ | ||
| 24004 | |||
| 24005 | /* { dg-do assemble } */ | ||
| 24006 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24007 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24008 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24009 | +/* { dg-add-options arm_neon } */ | ||
| 24010 | |||
| 24011 | #include "arm_neon.h" | ||
| 24012 | |||
| 24013 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c | ||
| 24014 | =================================================================== | ||
| 24015 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c | ||
| 24016 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c | ||
| 24017 | @@ -3,7 +3,8 @@ | ||
| 24018 | |||
| 24019 | /* { dg-do assemble } */ | ||
| 24020 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24021 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24022 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24023 | +/* { dg-add-options arm_neon } */ | ||
| 24024 | |||
| 24025 | #include "arm_neon.h" | ||
| 24026 | |||
| 24027 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c | ||
| 24028 | =================================================================== | ||
| 24029 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c | ||
| 24030 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c | ||
| 24031 | @@ -3,7 +3,8 @@ | ||
| 24032 | |||
| 24033 | /* { dg-do assemble } */ | ||
| 24034 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24035 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24036 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24037 | +/* { dg-add-options arm_neon } */ | ||
| 24038 | |||
| 24039 | #include "arm_neon.h" | ||
| 24040 | |||
| 24041 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c | ||
| 24042 | =================================================================== | ||
| 24043 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c | ||
| 24044 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c | ||
| 24045 | @@ -3,7 +3,8 @@ | ||
| 24046 | |||
| 24047 | /* { dg-do assemble } */ | ||
| 24048 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24049 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24050 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24051 | +/* { dg-add-options arm_neon } */ | ||
| 24052 | |||
| 24053 | #include "arm_neon.h" | ||
| 24054 | |||
| 24055 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c | ||
| 24056 | =================================================================== | ||
| 24057 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c | ||
| 24058 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c | ||
| 24059 | @@ -3,7 +3,8 @@ | ||
| 24060 | |||
| 24061 | /* { dg-do assemble } */ | ||
| 24062 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24063 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24064 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24065 | +/* { dg-add-options arm_neon } */ | ||
| 24066 | |||
| 24067 | #include "arm_neon.h" | ||
| 24068 | |||
| 24069 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c | ||
| 24070 | =================================================================== | ||
| 24071 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c | ||
| 24072 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c | ||
| 24073 | @@ -3,7 +3,8 @@ | ||
| 24074 | |||
| 24075 | /* { dg-do assemble } */ | ||
| 24076 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24077 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24078 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24079 | +/* { dg-add-options arm_neon } */ | ||
| 24080 | |||
| 24081 | #include "arm_neon.h" | ||
| 24082 | |||
| 24083 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c | ||
| 24084 | =================================================================== | ||
| 24085 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c | ||
| 24086 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c | ||
| 24087 | @@ -3,7 +3,8 @@ | ||
| 24088 | |||
| 24089 | /* { dg-do assemble } */ | ||
| 24090 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24091 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24092 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24093 | +/* { dg-add-options arm_neon } */ | ||
| 24094 | |||
| 24095 | #include "arm_neon.h" | ||
| 24096 | |||
| 24097 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3f32.c | ||
| 24098 | =================================================================== | ||
| 24099 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3f32.c | ||
| 24100 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3f32.c | ||
| 24101 | @@ -3,7 +3,8 @@ | ||
| 24102 | |||
| 24103 | /* { dg-do assemble } */ | ||
| 24104 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24105 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24106 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24107 | +/* { dg-add-options arm_neon } */ | ||
| 24108 | |||
| 24109 | #include "arm_neon.h" | ||
| 24110 | |||
| 24111 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3p16.c | ||
| 24112 | =================================================================== | ||
| 24113 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3p16.c | ||
| 24114 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3p16.c | ||
| 24115 | @@ -3,7 +3,8 @@ | ||
| 24116 | |||
| 24117 | /* { dg-do assemble } */ | ||
| 24118 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24119 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24120 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24121 | +/* { dg-add-options arm_neon } */ | ||
| 24122 | |||
| 24123 | #include "arm_neon.h" | ||
| 24124 | |||
| 24125 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3p8.c | ||
| 24126 | =================================================================== | ||
| 24127 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3p8.c | ||
| 24128 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3p8.c | ||
| 24129 | @@ -3,7 +3,8 @@ | ||
| 24130 | |||
| 24131 | /* { dg-do assemble } */ | ||
| 24132 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24133 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24134 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24135 | +/* { dg-add-options arm_neon } */ | ||
| 24136 | |||
| 24137 | #include "arm_neon.h" | ||
| 24138 | |||
| 24139 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s16.c | ||
| 24140 | =================================================================== | ||
| 24141 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s16.c | ||
| 24142 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s16.c | ||
| 24143 | @@ -3,7 +3,8 @@ | ||
| 24144 | |||
| 24145 | /* { dg-do assemble } */ | ||
| 24146 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24147 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24148 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24149 | +/* { dg-add-options arm_neon } */ | ||
| 24150 | |||
| 24151 | #include "arm_neon.h" | ||
| 24152 | |||
| 24153 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s32.c | ||
| 24154 | =================================================================== | ||
| 24155 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s32.c | ||
| 24156 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s32.c | ||
| 24157 | @@ -3,7 +3,8 @@ | ||
| 24158 | |||
| 24159 | /* { dg-do assemble } */ | ||
| 24160 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24161 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24162 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24163 | +/* { dg-add-options arm_neon } */ | ||
| 24164 | |||
| 24165 | #include "arm_neon.h" | ||
| 24166 | |||
| 24167 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s64.c | ||
| 24168 | =================================================================== | ||
| 24169 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s64.c | ||
| 24170 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s64.c | ||
| 24171 | @@ -3,7 +3,8 @@ | ||
| 24172 | |||
| 24173 | /* { dg-do assemble } */ | ||
| 24174 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24175 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24176 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24177 | +/* { dg-add-options arm_neon } */ | ||
| 24178 | |||
| 24179 | #include "arm_neon.h" | ||
| 24180 | |||
| 24181 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s8.c | ||
| 24182 | =================================================================== | ||
| 24183 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s8.c | ||
| 24184 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3s8.c | ||
| 24185 | @@ -3,7 +3,8 @@ | ||
| 24186 | |||
| 24187 | /* { dg-do assemble } */ | ||
| 24188 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24189 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24190 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24191 | +/* { dg-add-options arm_neon } */ | ||
| 24192 | |||
| 24193 | #include "arm_neon.h" | ||
| 24194 | |||
| 24195 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u16.c | ||
| 24196 | =================================================================== | ||
| 24197 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u16.c | ||
| 24198 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u16.c | ||
| 24199 | @@ -3,7 +3,8 @@ | ||
| 24200 | |||
| 24201 | /* { dg-do assemble } */ | ||
| 24202 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24203 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24204 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24205 | +/* { dg-add-options arm_neon } */ | ||
| 24206 | |||
| 24207 | #include "arm_neon.h" | ||
| 24208 | |||
| 24209 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u32.c | ||
| 24210 | =================================================================== | ||
| 24211 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u32.c | ||
| 24212 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u32.c | ||
| 24213 | @@ -3,7 +3,8 @@ | ||
| 24214 | |||
| 24215 | /* { dg-do assemble } */ | ||
| 24216 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24217 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24218 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24219 | +/* { dg-add-options arm_neon } */ | ||
| 24220 | |||
| 24221 | #include "arm_neon.h" | ||
| 24222 | |||
| 24223 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u64.c | ||
| 24224 | =================================================================== | ||
| 24225 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u64.c | ||
| 24226 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u64.c | ||
| 24227 | @@ -3,7 +3,8 @@ | ||
| 24228 | |||
| 24229 | /* { dg-do assemble } */ | ||
| 24230 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24231 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24232 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24233 | +/* { dg-add-options arm_neon } */ | ||
| 24234 | |||
| 24235 | #include "arm_neon.h" | ||
| 24236 | |||
| 24237 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u8.c | ||
| 24238 | =================================================================== | ||
| 24239 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u8.c | ||
| 24240 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst3u8.c | ||
| 24241 | @@ -3,7 +3,8 @@ | ||
| 24242 | |||
| 24243 | /* { dg-do assemble } */ | ||
| 24244 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24245 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24246 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24247 | +/* { dg-add-options arm_neon } */ | ||
| 24248 | |||
| 24249 | #include "arm_neon.h" | ||
| 24250 | |||
| 24251 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c | ||
| 24252 | =================================================================== | ||
| 24253 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c | ||
| 24254 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c | ||
| 24255 | @@ -3,7 +3,8 @@ | ||
| 24256 | |||
| 24257 | /* { dg-do assemble } */ | ||
| 24258 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24259 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24260 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24261 | +/* { dg-add-options arm_neon } */ | ||
| 24262 | |||
| 24263 | #include "arm_neon.h" | ||
| 24264 | |||
| 24265 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c | ||
| 24266 | =================================================================== | ||
| 24267 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c | ||
| 24268 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c | ||
| 24269 | @@ -3,7 +3,8 @@ | ||
| 24270 | |||
| 24271 | /* { dg-do assemble } */ | ||
| 24272 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24273 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24274 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24275 | +/* { dg-add-options arm_neon } */ | ||
| 24276 | |||
| 24277 | #include "arm_neon.h" | ||
| 24278 | |||
| 24279 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c | ||
| 24280 | =================================================================== | ||
| 24281 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c | ||
| 24282 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c | ||
| 24283 | @@ -3,7 +3,8 @@ | ||
| 24284 | |||
| 24285 | /* { dg-do assemble } */ | ||
| 24286 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24287 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24288 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24289 | +/* { dg-add-options arm_neon } */ | ||
| 24290 | |||
| 24291 | #include "arm_neon.h" | ||
| 24292 | |||
| 24293 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c | ||
| 24294 | =================================================================== | ||
| 24295 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c | ||
| 24296 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c | ||
| 24297 | @@ -3,7 +3,8 @@ | ||
| 24298 | |||
| 24299 | /* { dg-do assemble } */ | ||
| 24300 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24301 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24302 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24303 | +/* { dg-add-options arm_neon } */ | ||
| 24304 | |||
| 24305 | #include "arm_neon.h" | ||
| 24306 | |||
| 24307 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c | ||
| 24308 | =================================================================== | ||
| 24309 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c | ||
| 24310 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c | ||
| 24311 | @@ -3,7 +3,8 @@ | ||
| 24312 | |||
| 24313 | /* { dg-do assemble } */ | ||
| 24314 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24315 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24316 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24317 | +/* { dg-add-options arm_neon } */ | ||
| 24318 | |||
| 24319 | #include "arm_neon.h" | ||
| 24320 | |||
| 24321 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c | ||
| 24322 | =================================================================== | ||
| 24323 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c | ||
| 24324 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c | ||
| 24325 | @@ -3,7 +3,8 @@ | ||
| 24326 | |||
| 24327 | /* { dg-do assemble } */ | ||
| 24328 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24329 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24330 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24331 | +/* { dg-add-options arm_neon } */ | ||
| 24332 | |||
| 24333 | #include "arm_neon.h" | ||
| 24334 | |||
| 24335 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c | ||
| 24336 | =================================================================== | ||
| 24337 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c | ||
| 24338 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c | ||
| 24339 | @@ -3,7 +3,8 @@ | ||
| 24340 | |||
| 24341 | /* { dg-do assemble } */ | ||
| 24342 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24343 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24344 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24345 | +/* { dg-add-options arm_neon } */ | ||
| 24346 | |||
| 24347 | #include "arm_neon.h" | ||
| 24348 | |||
| 24349 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c | ||
| 24350 | =================================================================== | ||
| 24351 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c | ||
| 24352 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c | ||
| 24353 | @@ -3,7 +3,8 @@ | ||
| 24354 | |||
| 24355 | /* { dg-do assemble } */ | ||
| 24356 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24357 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24358 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24359 | +/* { dg-add-options arm_neon } */ | ||
| 24360 | |||
| 24361 | #include "arm_neon.h" | ||
| 24362 | |||
| 24363 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c | ||
| 24364 | =================================================================== | ||
| 24365 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c | ||
| 24366 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c | ||
| 24367 | @@ -3,7 +3,8 @@ | ||
| 24368 | |||
| 24369 | /* { dg-do assemble } */ | ||
| 24370 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24371 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24372 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24373 | +/* { dg-add-options arm_neon } */ | ||
| 24374 | |||
| 24375 | #include "arm_neon.h" | ||
| 24376 | |||
| 24377 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c | ||
| 24378 | =================================================================== | ||
| 24379 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c | ||
| 24380 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c | ||
| 24381 | @@ -3,7 +3,8 @@ | ||
| 24382 | |||
| 24383 | /* { dg-do assemble } */ | ||
| 24384 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24385 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24386 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24387 | +/* { dg-add-options arm_neon } */ | ||
| 24388 | |||
| 24389 | #include "arm_neon.h" | ||
| 24390 | |||
| 24391 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c | ||
| 24392 | =================================================================== | ||
| 24393 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c | ||
| 24394 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c | ||
| 24395 | @@ -3,7 +3,8 @@ | ||
| 24396 | |||
| 24397 | /* { dg-do assemble } */ | ||
| 24398 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24399 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24400 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24401 | +/* { dg-add-options arm_neon } */ | ||
| 24402 | |||
| 24403 | #include "arm_neon.h" | ||
| 24404 | |||
| 24405 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c | ||
| 24406 | =================================================================== | ||
| 24407 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c | ||
| 24408 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c | ||
| 24409 | @@ -3,7 +3,8 @@ | ||
| 24410 | |||
| 24411 | /* { dg-do assemble } */ | ||
| 24412 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24413 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24414 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24415 | +/* { dg-add-options arm_neon } */ | ||
| 24416 | |||
| 24417 | #include "arm_neon.h" | ||
| 24418 | |||
| 24419 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c | ||
| 24420 | =================================================================== | ||
| 24421 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c | ||
| 24422 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c | ||
| 24423 | @@ -3,7 +3,8 @@ | ||
| 24424 | |||
| 24425 | /* { dg-do assemble } */ | ||
| 24426 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24427 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24428 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24429 | +/* { dg-add-options arm_neon } */ | ||
| 24430 | |||
| 24431 | #include "arm_neon.h" | ||
| 24432 | |||
| 24433 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c | ||
| 24434 | =================================================================== | ||
| 24435 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c | ||
| 24436 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c | ||
| 24437 | @@ -3,7 +3,8 @@ | ||
| 24438 | |||
| 24439 | /* { dg-do assemble } */ | ||
| 24440 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24441 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24442 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24443 | +/* { dg-add-options arm_neon } */ | ||
| 24444 | |||
| 24445 | #include "arm_neon.h" | ||
| 24446 | |||
| 24447 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c | ||
| 24448 | =================================================================== | ||
| 24449 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c | ||
| 24450 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c | ||
| 24451 | @@ -3,7 +3,8 @@ | ||
| 24452 | |||
| 24453 | /* { dg-do assemble } */ | ||
| 24454 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24455 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24456 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24457 | +/* { dg-add-options arm_neon } */ | ||
| 24458 | |||
| 24459 | #include "arm_neon.h" | ||
| 24460 | |||
| 24461 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c | ||
| 24462 | =================================================================== | ||
| 24463 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c | ||
| 24464 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c | ||
| 24465 | @@ -3,7 +3,8 @@ | ||
| 24466 | |||
| 24467 | /* { dg-do assemble } */ | ||
| 24468 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24469 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24470 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24471 | +/* { dg-add-options arm_neon } */ | ||
| 24472 | |||
| 24473 | #include "arm_neon.h" | ||
| 24474 | |||
| 24475 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c | ||
| 24476 | =================================================================== | ||
| 24477 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c | ||
| 24478 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c | ||
| 24479 | @@ -3,7 +3,8 @@ | ||
| 24480 | |||
| 24481 | /* { dg-do assemble } */ | ||
| 24482 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24483 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24484 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24485 | +/* { dg-add-options arm_neon } */ | ||
| 24486 | |||
| 24487 | #include "arm_neon.h" | ||
| 24488 | |||
| 24489 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c | ||
| 24490 | =================================================================== | ||
| 24491 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c | ||
| 24492 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c | ||
| 24493 | @@ -3,7 +3,8 @@ | ||
| 24494 | |||
| 24495 | /* { dg-do assemble } */ | ||
| 24496 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24497 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24498 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24499 | +/* { dg-add-options arm_neon } */ | ||
| 24500 | |||
| 24501 | #include "arm_neon.h" | ||
| 24502 | |||
| 24503 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c | ||
| 24504 | =================================================================== | ||
| 24505 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c | ||
| 24506 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c | ||
| 24507 | @@ -3,7 +3,8 @@ | ||
| 24508 | |||
| 24509 | /* { dg-do assemble } */ | ||
| 24510 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24511 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24512 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24513 | +/* { dg-add-options arm_neon } */ | ||
| 24514 | |||
| 24515 | #include "arm_neon.h" | ||
| 24516 | |||
| 24517 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c | ||
| 24518 | =================================================================== | ||
| 24519 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c | ||
| 24520 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c | ||
| 24521 | @@ -3,7 +3,8 @@ | ||
| 24522 | |||
| 24523 | /* { dg-do assemble } */ | ||
| 24524 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24525 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24526 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24527 | +/* { dg-add-options arm_neon } */ | ||
| 24528 | |||
| 24529 | #include "arm_neon.h" | ||
| 24530 | |||
| 24531 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c | ||
| 24532 | =================================================================== | ||
| 24533 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c | ||
| 24534 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c | ||
| 24535 | @@ -3,7 +3,8 @@ | ||
| 24536 | |||
| 24537 | /* { dg-do assemble } */ | ||
| 24538 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24539 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24540 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24541 | +/* { dg-add-options arm_neon } */ | ||
| 24542 | |||
| 24543 | #include "arm_neon.h" | ||
| 24544 | |||
| 24545 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c | ||
| 24546 | =================================================================== | ||
| 24547 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c | ||
| 24548 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c | ||
| 24549 | @@ -3,7 +3,8 @@ | ||
| 24550 | |||
| 24551 | /* { dg-do assemble } */ | ||
| 24552 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24553 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24554 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24555 | +/* { dg-add-options arm_neon } */ | ||
| 24556 | |||
| 24557 | #include "arm_neon.h" | ||
| 24558 | |||
| 24559 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c | ||
| 24560 | =================================================================== | ||
| 24561 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c | ||
| 24562 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c | ||
| 24563 | @@ -3,7 +3,8 @@ | ||
| 24564 | |||
| 24565 | /* { dg-do assemble } */ | ||
| 24566 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24567 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24568 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24569 | +/* { dg-add-options arm_neon } */ | ||
| 24570 | |||
| 24571 | #include "arm_neon.h" | ||
| 24572 | |||
| 24573 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c | ||
| 24574 | =================================================================== | ||
| 24575 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c | ||
| 24576 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c | ||
| 24577 | @@ -3,7 +3,8 @@ | ||
| 24578 | |||
| 24579 | /* { dg-do assemble } */ | ||
| 24580 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24581 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24582 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24583 | +/* { dg-add-options arm_neon } */ | ||
| 24584 | |||
| 24585 | #include "arm_neon.h" | ||
| 24586 | |||
| 24587 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4f32.c | ||
| 24588 | =================================================================== | ||
| 24589 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4f32.c | ||
| 24590 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4f32.c | ||
| 24591 | @@ -3,7 +3,8 @@ | ||
| 24592 | |||
| 24593 | /* { dg-do assemble } */ | ||
| 24594 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24595 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24596 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24597 | +/* { dg-add-options arm_neon } */ | ||
| 24598 | |||
| 24599 | #include "arm_neon.h" | ||
| 24600 | |||
| 24601 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4p16.c | ||
| 24602 | =================================================================== | ||
| 24603 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4p16.c | ||
| 24604 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4p16.c | ||
| 24605 | @@ -3,7 +3,8 @@ | ||
| 24606 | |||
| 24607 | /* { dg-do assemble } */ | ||
| 24608 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24609 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24610 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24611 | +/* { dg-add-options arm_neon } */ | ||
| 24612 | |||
| 24613 | #include "arm_neon.h" | ||
| 24614 | |||
| 24615 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4p8.c | ||
| 24616 | =================================================================== | ||
| 24617 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4p8.c | ||
| 24618 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4p8.c | ||
| 24619 | @@ -3,7 +3,8 @@ | ||
| 24620 | |||
| 24621 | /* { dg-do assemble } */ | ||
| 24622 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24623 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24624 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24625 | +/* { dg-add-options arm_neon } */ | ||
| 24626 | |||
| 24627 | #include "arm_neon.h" | ||
| 24628 | |||
| 24629 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s16.c | ||
| 24630 | =================================================================== | ||
| 24631 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s16.c | ||
| 24632 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s16.c | ||
| 24633 | @@ -3,7 +3,8 @@ | ||
| 24634 | |||
| 24635 | /* { dg-do assemble } */ | ||
| 24636 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24637 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24638 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24639 | +/* { dg-add-options arm_neon } */ | ||
| 24640 | |||
| 24641 | #include "arm_neon.h" | ||
| 24642 | |||
| 24643 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s32.c | ||
| 24644 | =================================================================== | ||
| 24645 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s32.c | ||
| 24646 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s32.c | ||
| 24647 | @@ -3,7 +3,8 @@ | ||
| 24648 | |||
| 24649 | /* { dg-do assemble } */ | ||
| 24650 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24651 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24652 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24653 | +/* { dg-add-options arm_neon } */ | ||
| 24654 | |||
| 24655 | #include "arm_neon.h" | ||
| 24656 | |||
| 24657 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s64.c | ||
| 24658 | =================================================================== | ||
| 24659 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s64.c | ||
| 24660 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s64.c | ||
| 24661 | @@ -3,7 +3,8 @@ | ||
| 24662 | |||
| 24663 | /* { dg-do assemble } */ | ||
| 24664 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24665 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24666 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24667 | +/* { dg-add-options arm_neon } */ | ||
| 24668 | |||
| 24669 | #include "arm_neon.h" | ||
| 24670 | |||
| 24671 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s8.c | ||
| 24672 | =================================================================== | ||
| 24673 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s8.c | ||
| 24674 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4s8.c | ||
| 24675 | @@ -3,7 +3,8 @@ | ||
| 24676 | |||
| 24677 | /* { dg-do assemble } */ | ||
| 24678 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24679 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24680 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24681 | +/* { dg-add-options arm_neon } */ | ||
| 24682 | |||
| 24683 | #include "arm_neon.h" | ||
| 24684 | |||
| 24685 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u16.c | ||
| 24686 | =================================================================== | ||
| 24687 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u16.c | ||
| 24688 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u16.c | ||
| 24689 | @@ -3,7 +3,8 @@ | ||
| 24690 | |||
| 24691 | /* { dg-do assemble } */ | ||
| 24692 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24693 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24694 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24695 | +/* { dg-add-options arm_neon } */ | ||
| 24696 | |||
| 24697 | #include "arm_neon.h" | ||
| 24698 | |||
| 24699 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u32.c | ||
| 24700 | =================================================================== | ||
| 24701 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u32.c | ||
| 24702 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u32.c | ||
| 24703 | @@ -3,7 +3,8 @@ | ||
| 24704 | |||
| 24705 | /* { dg-do assemble } */ | ||
| 24706 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24707 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24708 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24709 | +/* { dg-add-options arm_neon } */ | ||
| 24710 | |||
| 24711 | #include "arm_neon.h" | ||
| 24712 | |||
| 24713 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u64.c | ||
| 24714 | =================================================================== | ||
| 24715 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u64.c | ||
| 24716 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u64.c | ||
| 24717 | @@ -3,7 +3,8 @@ | ||
| 24718 | |||
| 24719 | /* { dg-do assemble } */ | ||
| 24720 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24721 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24722 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24723 | +/* { dg-add-options arm_neon } */ | ||
| 24724 | |||
| 24725 | #include "arm_neon.h" | ||
| 24726 | |||
| 24727 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u8.c | ||
| 24728 | =================================================================== | ||
| 24729 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u8.c | ||
| 24730 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vst4u8.c | ||
| 24731 | @@ -3,7 +3,8 @@ | ||
| 24732 | |||
| 24733 | /* { dg-do assemble } */ | ||
| 24734 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24735 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24736 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24737 | +/* { dg-add-options arm_neon } */ | ||
| 24738 | |||
| 24739 | #include "arm_neon.h" | ||
| 24740 | |||
| 24741 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c | ||
| 24742 | =================================================================== | ||
| 24743 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c | ||
| 24744 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c | ||
| 24745 | @@ -3,7 +3,8 @@ | ||
| 24746 | |||
| 24747 | /* { dg-do assemble } */ | ||
| 24748 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24749 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24750 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24751 | +/* { dg-add-options arm_neon } */ | ||
| 24752 | |||
| 24753 | #include "arm_neon.h" | ||
| 24754 | |||
| 24755 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c | ||
| 24756 | =================================================================== | ||
| 24757 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c | ||
| 24758 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c | ||
| 24759 | @@ -3,7 +3,8 @@ | ||
| 24760 | |||
| 24761 | /* { dg-do assemble } */ | ||
| 24762 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24763 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24764 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24765 | +/* { dg-add-options arm_neon } */ | ||
| 24766 | |||
| 24767 | #include "arm_neon.h" | ||
| 24768 | |||
| 24769 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c | ||
| 24770 | =================================================================== | ||
| 24771 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c | ||
| 24772 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c | ||
| 24773 | @@ -3,7 +3,8 @@ | ||
| 24774 | |||
| 24775 | /* { dg-do assemble } */ | ||
| 24776 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24777 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24778 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24779 | +/* { dg-add-options arm_neon } */ | ||
| 24780 | |||
| 24781 | #include "arm_neon.h" | ||
| 24782 | |||
| 24783 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c | ||
| 24784 | =================================================================== | ||
| 24785 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c | ||
| 24786 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c | ||
| 24787 | @@ -3,7 +3,8 @@ | ||
| 24788 | |||
| 24789 | /* { dg-do assemble } */ | ||
| 24790 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24791 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24792 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24793 | +/* { dg-add-options arm_neon } */ | ||
| 24794 | |||
| 24795 | #include "arm_neon.h" | ||
| 24796 | |||
| 24797 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c | ||
| 24798 | =================================================================== | ||
| 24799 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c | ||
| 24800 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c | ||
| 24801 | @@ -3,7 +3,8 @@ | ||
| 24802 | |||
| 24803 | /* { dg-do assemble } */ | ||
| 24804 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24805 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24806 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24807 | +/* { dg-add-options arm_neon } */ | ||
| 24808 | |||
| 24809 | #include "arm_neon.h" | ||
| 24810 | |||
| 24811 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c | ||
| 24812 | =================================================================== | ||
| 24813 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c | ||
| 24814 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c | ||
| 24815 | @@ -3,7 +3,8 @@ | ||
| 24816 | |||
| 24817 | /* { dg-do assemble } */ | ||
| 24818 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24819 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24820 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24821 | +/* { dg-add-options arm_neon } */ | ||
| 24822 | |||
| 24823 | #include "arm_neon.h" | ||
| 24824 | |||
| 24825 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c | ||
| 24826 | =================================================================== | ||
| 24827 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c | ||
| 24828 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c | ||
| 24829 | @@ -3,7 +3,8 @@ | ||
| 24830 | |||
| 24831 | /* { dg-do assemble } */ | ||
| 24832 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24833 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24834 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24835 | +/* { dg-add-options arm_neon } */ | ||
| 24836 | |||
| 24837 | #include "arm_neon.h" | ||
| 24838 | |||
| 24839 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c | ||
| 24840 | =================================================================== | ||
| 24841 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c | ||
| 24842 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c | ||
| 24843 | @@ -3,7 +3,8 @@ | ||
| 24844 | |||
| 24845 | /* { dg-do assemble } */ | ||
| 24846 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24847 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24848 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24849 | +/* { dg-add-options arm_neon } */ | ||
| 24850 | |||
| 24851 | #include "arm_neon.h" | ||
| 24852 | |||
| 24853 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c | ||
| 24854 | =================================================================== | ||
| 24855 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c | ||
| 24856 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c | ||
| 24857 | @@ -3,7 +3,8 @@ | ||
| 24858 | |||
| 24859 | /* { dg-do assemble } */ | ||
| 24860 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24861 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24862 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24863 | +/* { dg-add-options arm_neon } */ | ||
| 24864 | |||
| 24865 | #include "arm_neon.h" | ||
| 24866 | |||
| 24867 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubf32.c | ||
| 24868 | =================================================================== | ||
| 24869 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubf32.c | ||
| 24870 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubf32.c | ||
| 24871 | @@ -3,7 +3,8 @@ | ||
| 24872 | |||
| 24873 | /* { dg-do assemble } */ | ||
| 24874 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24875 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24876 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24877 | +/* { dg-add-options arm_neon } */ | ||
| 24878 | |||
| 24879 | #include "arm_neon.h" | ||
| 24880 | |||
| 24881 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c | ||
| 24882 | =================================================================== | ||
| 24883 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c | ||
| 24884 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c | ||
| 24885 | @@ -3,7 +3,8 @@ | ||
| 24886 | |||
| 24887 | /* { dg-do assemble } */ | ||
| 24888 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24889 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24890 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24891 | +/* { dg-add-options arm_neon } */ | ||
| 24892 | |||
| 24893 | #include "arm_neon.h" | ||
| 24894 | |||
| 24895 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c | ||
| 24896 | =================================================================== | ||
| 24897 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c | ||
| 24898 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c | ||
| 24899 | @@ -3,7 +3,8 @@ | ||
| 24900 | |||
| 24901 | /* { dg-do assemble } */ | ||
| 24902 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24903 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24904 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24905 | +/* { dg-add-options arm_neon } */ | ||
| 24906 | |||
| 24907 | #include "arm_neon.h" | ||
| 24908 | |||
| 24909 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c | ||
| 24910 | =================================================================== | ||
| 24911 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c | ||
| 24912 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c | ||
| 24913 | @@ -3,7 +3,8 @@ | ||
| 24914 | |||
| 24915 | /* { dg-do assemble } */ | ||
| 24916 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24917 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24918 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24919 | +/* { dg-add-options arm_neon } */ | ||
| 24920 | |||
| 24921 | #include "arm_neon.h" | ||
| 24922 | |||
| 24923 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c | ||
| 24924 | =================================================================== | ||
| 24925 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c | ||
| 24926 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c | ||
| 24927 | @@ -3,7 +3,8 @@ | ||
| 24928 | |||
| 24929 | /* { dg-do assemble } */ | ||
| 24930 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24931 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24932 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24933 | +/* { dg-add-options arm_neon } */ | ||
| 24934 | |||
| 24935 | #include "arm_neon.h" | ||
| 24936 | |||
| 24937 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c | ||
| 24938 | =================================================================== | ||
| 24939 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c | ||
| 24940 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c | ||
| 24941 | @@ -3,7 +3,8 @@ | ||
| 24942 | |||
| 24943 | /* { dg-do assemble } */ | ||
| 24944 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24945 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24946 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24947 | +/* { dg-add-options arm_neon } */ | ||
| 24948 | |||
| 24949 | #include "arm_neon.h" | ||
| 24950 | |||
| 24951 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c | ||
| 24952 | =================================================================== | ||
| 24953 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c | ||
| 24954 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c | ||
| 24955 | @@ -3,7 +3,8 @@ | ||
| 24956 | |||
| 24957 | /* { dg-do assemble } */ | ||
| 24958 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24959 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24960 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24961 | +/* { dg-add-options arm_neon } */ | ||
| 24962 | |||
| 24963 | #include "arm_neon.h" | ||
| 24964 | |||
| 24965 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubls16.c | ||
| 24966 | =================================================================== | ||
| 24967 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubls16.c | ||
| 24968 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubls16.c | ||
| 24969 | @@ -3,7 +3,8 @@ | ||
| 24970 | |||
| 24971 | /* { dg-do assemble } */ | ||
| 24972 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24973 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24974 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24975 | +/* { dg-add-options arm_neon } */ | ||
| 24976 | |||
| 24977 | #include "arm_neon.h" | ||
| 24978 | |||
| 24979 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubls32.c | ||
| 24980 | =================================================================== | ||
| 24981 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubls32.c | ||
| 24982 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubls32.c | ||
| 24983 | @@ -3,7 +3,8 @@ | ||
| 24984 | |||
| 24985 | /* { dg-do assemble } */ | ||
| 24986 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 24987 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 24988 | +/* { dg-options "-save-temps -O0" } */ | ||
| 24989 | +/* { dg-add-options arm_neon } */ | ||
| 24990 | |||
| 24991 | #include "arm_neon.h" | ||
| 24992 | |||
| 24993 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubls8.c | ||
| 24994 | =================================================================== | ||
| 24995 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubls8.c | ||
| 24996 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubls8.c | ||
| 24997 | @@ -3,7 +3,8 @@ | ||
| 24998 | |||
| 24999 | /* { dg-do assemble } */ | ||
| 25000 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25001 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25002 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25003 | +/* { dg-add-options arm_neon } */ | ||
| 25004 | |||
| 25005 | #include "arm_neon.h" | ||
| 25006 | |||
| 25007 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsublu16.c | ||
| 25008 | =================================================================== | ||
| 25009 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsublu16.c | ||
| 25010 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsublu16.c | ||
| 25011 | @@ -3,7 +3,8 @@ | ||
| 25012 | |||
| 25013 | /* { dg-do assemble } */ | ||
| 25014 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25015 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25016 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25017 | +/* { dg-add-options arm_neon } */ | ||
| 25018 | |||
| 25019 | #include "arm_neon.h" | ||
| 25020 | |||
| 25021 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsublu32.c | ||
| 25022 | =================================================================== | ||
| 25023 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsublu32.c | ||
| 25024 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsublu32.c | ||
| 25025 | @@ -3,7 +3,8 @@ | ||
| 25026 | |||
| 25027 | /* { dg-do assemble } */ | ||
| 25028 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25029 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25030 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25031 | +/* { dg-add-options arm_neon } */ | ||
| 25032 | |||
| 25033 | #include "arm_neon.h" | ||
| 25034 | |||
| 25035 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsublu8.c | ||
| 25036 | =================================================================== | ||
| 25037 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsublu8.c | ||
| 25038 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsublu8.c | ||
| 25039 | @@ -3,7 +3,8 @@ | ||
| 25040 | |||
| 25041 | /* { dg-do assemble } */ | ||
| 25042 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25043 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25044 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25045 | +/* { dg-add-options arm_neon } */ | ||
| 25046 | |||
| 25047 | #include "arm_neon.h" | ||
| 25048 | |||
| 25049 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs16.c | ||
| 25050 | =================================================================== | ||
| 25051 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubs16.c | ||
| 25052 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs16.c | ||
| 25053 | @@ -3,7 +3,8 @@ | ||
| 25054 | |||
| 25055 | /* { dg-do assemble } */ | ||
| 25056 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25057 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25058 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25059 | +/* { dg-add-options arm_neon } */ | ||
| 25060 | |||
| 25061 | #include "arm_neon.h" | ||
| 25062 | |||
| 25063 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs32.c | ||
| 25064 | =================================================================== | ||
| 25065 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubs32.c | ||
| 25066 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs32.c | ||
| 25067 | @@ -3,7 +3,8 @@ | ||
| 25068 | |||
| 25069 | /* { dg-do assemble } */ | ||
| 25070 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25071 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25072 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25073 | +/* { dg-add-options arm_neon } */ | ||
| 25074 | |||
| 25075 | #include "arm_neon.h" | ||
| 25076 | |||
| 25077 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs64.c | ||
| 25078 | =================================================================== | ||
| 25079 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubs64.c | ||
| 25080 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs64.c | ||
| 25081 | @@ -3,7 +3,8 @@ | ||
| 25082 | |||
| 25083 | /* { dg-do assemble } */ | ||
| 25084 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25085 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25086 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25087 | +/* { dg-add-options arm_neon } */ | ||
| 25088 | |||
| 25089 | #include "arm_neon.h" | ||
| 25090 | |||
| 25091 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs8.c | ||
| 25092 | =================================================================== | ||
| 25093 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubs8.c | ||
| 25094 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubs8.c | ||
| 25095 | @@ -3,7 +3,8 @@ | ||
| 25096 | |||
| 25097 | /* { dg-do assemble } */ | ||
| 25098 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25099 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25100 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25101 | +/* { dg-add-options arm_neon } */ | ||
| 25102 | |||
| 25103 | #include "arm_neon.h" | ||
| 25104 | |||
| 25105 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu16.c | ||
| 25106 | =================================================================== | ||
| 25107 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubu16.c | ||
| 25108 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu16.c | ||
| 25109 | @@ -3,7 +3,8 @@ | ||
| 25110 | |||
| 25111 | /* { dg-do assemble } */ | ||
| 25112 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25113 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25114 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25115 | +/* { dg-add-options arm_neon } */ | ||
| 25116 | |||
| 25117 | #include "arm_neon.h" | ||
| 25118 | |||
| 25119 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu32.c | ||
| 25120 | =================================================================== | ||
| 25121 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubu32.c | ||
| 25122 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu32.c | ||
| 25123 | @@ -3,7 +3,8 @@ | ||
| 25124 | |||
| 25125 | /* { dg-do assemble } */ | ||
| 25126 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25127 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25128 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25129 | +/* { dg-add-options arm_neon } */ | ||
| 25130 | |||
| 25131 | #include "arm_neon.h" | ||
| 25132 | |||
| 25133 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu64.c | ||
| 25134 | =================================================================== | ||
| 25135 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubu64.c | ||
| 25136 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu64.c | ||
| 25137 | @@ -3,7 +3,8 @@ | ||
| 25138 | |||
| 25139 | /* { dg-do assemble } */ | ||
| 25140 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25141 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25142 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25143 | +/* { dg-add-options arm_neon } */ | ||
| 25144 | |||
| 25145 | #include "arm_neon.h" | ||
| 25146 | |||
| 25147 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu8.c | ||
| 25148 | =================================================================== | ||
| 25149 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubu8.c | ||
| 25150 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubu8.c | ||
| 25151 | @@ -3,7 +3,8 @@ | ||
| 25152 | |||
| 25153 | /* { dg-do assemble } */ | ||
| 25154 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25155 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25156 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25157 | +/* { dg-add-options arm_neon } */ | ||
| 25158 | |||
| 25159 | #include "arm_neon.h" | ||
| 25160 | |||
| 25161 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubws16.c | ||
| 25162 | =================================================================== | ||
| 25163 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubws16.c | ||
| 25164 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubws16.c | ||
| 25165 | @@ -3,7 +3,8 @@ | ||
| 25166 | |||
| 25167 | /* { dg-do assemble } */ | ||
| 25168 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25169 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25170 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25171 | +/* { dg-add-options arm_neon } */ | ||
| 25172 | |||
| 25173 | #include "arm_neon.h" | ||
| 25174 | |||
| 25175 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubws32.c | ||
| 25176 | =================================================================== | ||
| 25177 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubws32.c | ||
| 25178 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubws32.c | ||
| 25179 | @@ -3,7 +3,8 @@ | ||
| 25180 | |||
| 25181 | /* { dg-do assemble } */ | ||
| 25182 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25183 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25184 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25185 | +/* { dg-add-options arm_neon } */ | ||
| 25186 | |||
| 25187 | #include "arm_neon.h" | ||
| 25188 | |||
| 25189 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubws8.c | ||
| 25190 | =================================================================== | ||
| 25191 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubws8.c | ||
| 25192 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubws8.c | ||
| 25193 | @@ -3,7 +3,8 @@ | ||
| 25194 | |||
| 25195 | /* { dg-do assemble } */ | ||
| 25196 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25197 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25198 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25199 | +/* { dg-add-options arm_neon } */ | ||
| 25200 | |||
| 25201 | #include "arm_neon.h" | ||
| 25202 | |||
| 25203 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c | ||
| 25204 | =================================================================== | ||
| 25205 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c | ||
| 25206 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c | ||
| 25207 | @@ -3,7 +3,8 @@ | ||
| 25208 | |||
| 25209 | /* { dg-do assemble } */ | ||
| 25210 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25211 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25212 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25213 | +/* { dg-add-options arm_neon } */ | ||
| 25214 | |||
| 25215 | #include "arm_neon.h" | ||
| 25216 | |||
| 25217 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c | ||
| 25218 | =================================================================== | ||
| 25219 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c | ||
| 25220 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c | ||
| 25221 | @@ -3,7 +3,8 @@ | ||
| 25222 | |||
| 25223 | /* { dg-do assemble } */ | ||
| 25224 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25225 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25226 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25227 | +/* { dg-add-options arm_neon } */ | ||
| 25228 | |||
| 25229 | #include "arm_neon.h" | ||
| 25230 | |||
| 25231 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c | ||
| 25232 | =================================================================== | ||
| 25233 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c | ||
| 25234 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c | ||
| 25235 | @@ -3,7 +3,8 @@ | ||
| 25236 | |||
| 25237 | /* { dg-do assemble } */ | ||
| 25238 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25239 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25240 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25241 | +/* { dg-add-options arm_neon } */ | ||
| 25242 | |||
| 25243 | #include "arm_neon.h" | ||
| 25244 | |||
| 25245 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c | ||
| 25246 | =================================================================== | ||
| 25247 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c | ||
| 25248 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c | ||
| 25249 | @@ -3,7 +3,8 @@ | ||
| 25250 | |||
| 25251 | /* { dg-do assemble } */ | ||
| 25252 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25253 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25254 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25255 | +/* { dg-add-options arm_neon } */ | ||
| 25256 | |||
| 25257 | #include "arm_neon.h" | ||
| 25258 | |||
| 25259 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c | ||
| 25260 | =================================================================== | ||
| 25261 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c | ||
| 25262 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c | ||
| 25263 | @@ -3,7 +3,8 @@ | ||
| 25264 | |||
| 25265 | /* { dg-do assemble } */ | ||
| 25266 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25267 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25268 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25269 | +/* { dg-add-options arm_neon } */ | ||
| 25270 | |||
| 25271 | #include "arm_neon.h" | ||
| 25272 | |||
| 25273 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c | ||
| 25274 | =================================================================== | ||
| 25275 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c | ||
| 25276 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c | ||
| 25277 | @@ -3,7 +3,8 @@ | ||
| 25278 | |||
| 25279 | /* { dg-do assemble } */ | ||
| 25280 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25281 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25282 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25283 | +/* { dg-add-options arm_neon } */ | ||
| 25284 | |||
| 25285 | #include "arm_neon.h" | ||
| 25286 | |||
| 25287 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c | ||
| 25288 | =================================================================== | ||
| 25289 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c | ||
| 25290 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c | ||
| 25291 | @@ -3,7 +3,8 @@ | ||
| 25292 | |||
| 25293 | /* { dg-do assemble } */ | ||
| 25294 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25295 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25296 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25297 | +/* { dg-add-options arm_neon } */ | ||
| 25298 | |||
| 25299 | #include "arm_neon.h" | ||
| 25300 | |||
| 25301 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c | ||
| 25302 | =================================================================== | ||
| 25303 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c | ||
| 25304 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c | ||
| 25305 | @@ -3,7 +3,8 @@ | ||
| 25306 | |||
| 25307 | /* { dg-do assemble } */ | ||
| 25308 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25309 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25310 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25311 | +/* { dg-add-options arm_neon } */ | ||
| 25312 | |||
| 25313 | #include "arm_neon.h" | ||
| 25314 | |||
| 25315 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c | ||
| 25316 | =================================================================== | ||
| 25317 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c | ||
| 25318 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c | ||
| 25319 | @@ -3,7 +3,8 @@ | ||
| 25320 | |||
| 25321 | /* { dg-do assemble } */ | ||
| 25322 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25323 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25324 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25325 | +/* { dg-add-options arm_neon } */ | ||
| 25326 | |||
| 25327 | #include "arm_neon.h" | ||
| 25328 | |||
| 25329 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c | ||
| 25330 | =================================================================== | ||
| 25331 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c | ||
| 25332 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c | ||
| 25333 | @@ -3,7 +3,8 @@ | ||
| 25334 | |||
| 25335 | /* { dg-do assemble } */ | ||
| 25336 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25337 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25338 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25339 | +/* { dg-add-options arm_neon } */ | ||
| 25340 | |||
| 25341 | #include "arm_neon.h" | ||
| 25342 | |||
| 25343 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c | ||
| 25344 | =================================================================== | ||
| 25345 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c | ||
| 25346 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c | ||
| 25347 | @@ -3,7 +3,8 @@ | ||
| 25348 | |||
| 25349 | /* { dg-do assemble } */ | ||
| 25350 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25351 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25352 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25353 | +/* { dg-add-options arm_neon } */ | ||
| 25354 | |||
| 25355 | #include "arm_neon.h" | ||
| 25356 | |||
| 25357 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c | ||
| 25358 | =================================================================== | ||
| 25359 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c | ||
| 25360 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c | ||
| 25361 | @@ -3,7 +3,8 @@ | ||
| 25362 | |||
| 25363 | /* { dg-do assemble } */ | ||
| 25364 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25365 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25366 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25367 | +/* { dg-add-options arm_neon } */ | ||
| 25368 | |||
| 25369 | #include "arm_neon.h" | ||
| 25370 | |||
| 25371 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c | ||
| 25372 | =================================================================== | ||
| 25373 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c | ||
| 25374 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c | ||
| 25375 | @@ -3,7 +3,8 @@ | ||
| 25376 | |||
| 25377 | /* { dg-do assemble } */ | ||
| 25378 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25379 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25380 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25381 | +/* { dg-add-options arm_neon } */ | ||
| 25382 | |||
| 25383 | #include "arm_neon.h" | ||
| 25384 | |||
| 25385 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c | ||
| 25386 | =================================================================== | ||
| 25387 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c | ||
| 25388 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c | ||
| 25389 | @@ -3,7 +3,8 @@ | ||
| 25390 | |||
| 25391 | /* { dg-do assemble } */ | ||
| 25392 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25393 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25394 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25395 | +/* { dg-add-options arm_neon } */ | ||
| 25396 | |||
| 25397 | #include "arm_neon.h" | ||
| 25398 | |||
| 25399 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c | ||
| 25400 | =================================================================== | ||
| 25401 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c | ||
| 25402 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c | ||
| 25403 | @@ -3,7 +3,8 @@ | ||
| 25404 | |||
| 25405 | /* { dg-do assemble } */ | ||
| 25406 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25407 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25408 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25409 | +/* { dg-add-options arm_neon } */ | ||
| 25410 | |||
| 25411 | #include "arm_neon.h" | ||
| 25412 | |||
| 25413 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c | ||
| 25414 | =================================================================== | ||
| 25415 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c | ||
| 25416 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c | ||
| 25417 | @@ -3,7 +3,8 @@ | ||
| 25418 | |||
| 25419 | /* { dg-do assemble } */ | ||
| 25420 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25421 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25422 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25423 | +/* { dg-add-options arm_neon } */ | ||
| 25424 | |||
| 25425 | #include "arm_neon.h" | ||
| 25426 | |||
| 25427 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c | ||
| 25428 | =================================================================== | ||
| 25429 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c | ||
| 25430 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c | ||
| 25431 | @@ -3,7 +3,8 @@ | ||
| 25432 | |||
| 25433 | /* { dg-do assemble } */ | ||
| 25434 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25435 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25436 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25437 | +/* { dg-add-options arm_neon } */ | ||
| 25438 | |||
| 25439 | #include "arm_neon.h" | ||
| 25440 | |||
| 25441 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c | ||
| 25442 | =================================================================== | ||
| 25443 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c | ||
| 25444 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c | ||
| 25445 | @@ -3,7 +3,8 @@ | ||
| 25446 | |||
| 25447 | /* { dg-do assemble } */ | ||
| 25448 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25449 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25450 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25451 | +/* { dg-add-options arm_neon } */ | ||
| 25452 | |||
| 25453 | #include "arm_neon.h" | ||
| 25454 | |||
| 25455 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c | ||
| 25456 | =================================================================== | ||
| 25457 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c | ||
| 25458 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c | ||
| 25459 | @@ -3,7 +3,8 @@ | ||
| 25460 | |||
| 25461 | /* { dg-do assemble } */ | ||
| 25462 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25463 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25464 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25465 | +/* { dg-add-options arm_neon } */ | ||
| 25466 | |||
| 25467 | #include "arm_neon.h" | ||
| 25468 | |||
| 25469 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c | ||
| 25470 | =================================================================== | ||
| 25471 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c | ||
| 25472 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c | ||
| 25473 | @@ -3,7 +3,8 @@ | ||
| 25474 | |||
| 25475 | /* { dg-do assemble } */ | ||
| 25476 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25477 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25478 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25479 | +/* { dg-add-options arm_neon } */ | ||
| 25480 | |||
| 25481 | #include "arm_neon.h" | ||
| 25482 | |||
| 25483 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c | ||
| 25484 | =================================================================== | ||
| 25485 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c | ||
| 25486 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c | ||
| 25487 | @@ -3,7 +3,8 @@ | ||
| 25488 | |||
| 25489 | /* { dg-do assemble } */ | ||
| 25490 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25491 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25492 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25493 | +/* { dg-add-options arm_neon } */ | ||
| 25494 | |||
| 25495 | #include "arm_neon.h" | ||
| 25496 | |||
| 25497 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c | ||
| 25498 | =================================================================== | ||
| 25499 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c | ||
| 25500 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c | ||
| 25501 | @@ -3,7 +3,8 @@ | ||
| 25502 | |||
| 25503 | /* { dg-do assemble } */ | ||
| 25504 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25505 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25506 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25507 | +/* { dg-add-options arm_neon } */ | ||
| 25508 | |||
| 25509 | #include "arm_neon.h" | ||
| 25510 | |||
| 25511 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c | ||
| 25512 | =================================================================== | ||
| 25513 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c | ||
| 25514 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c | ||
| 25515 | @@ -3,7 +3,8 @@ | ||
| 25516 | |||
| 25517 | /* { dg-do assemble } */ | ||
| 25518 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25519 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25520 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25521 | +/* { dg-add-options arm_neon } */ | ||
| 25522 | |||
| 25523 | #include "arm_neon.h" | ||
| 25524 | |||
| 25525 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c | ||
| 25526 | =================================================================== | ||
| 25527 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c | ||
| 25528 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c | ||
| 25529 | @@ -3,7 +3,8 @@ | ||
| 25530 | |||
| 25531 | /* { dg-do assemble } */ | ||
| 25532 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25533 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25534 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25535 | +/* { dg-add-options arm_neon } */ | ||
| 25536 | |||
| 25537 | #include "arm_neon.h" | ||
| 25538 | |||
| 25539 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c | ||
| 25540 | =================================================================== | ||
| 25541 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c | ||
| 25542 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c | ||
| 25543 | @@ -3,7 +3,8 @@ | ||
| 25544 | |||
| 25545 | /* { dg-do assemble } */ | ||
| 25546 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25547 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25548 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25549 | +/* { dg-add-options arm_neon } */ | ||
| 25550 | |||
| 25551 | #include "arm_neon.h" | ||
| 25552 | |||
| 25553 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c | ||
| 25554 | =================================================================== | ||
| 25555 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c | ||
| 25556 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c | ||
| 25557 | @@ -3,7 +3,8 @@ | ||
| 25558 | |||
| 25559 | /* { dg-do assemble } */ | ||
| 25560 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25561 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25562 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25563 | +/* { dg-add-options arm_neon } */ | ||
| 25564 | |||
| 25565 | #include "arm_neon.h" | ||
| 25566 | |||
| 25567 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c | ||
| 25568 | =================================================================== | ||
| 25569 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c | ||
| 25570 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c | ||
| 25571 | @@ -3,7 +3,8 @@ | ||
| 25572 | |||
| 25573 | /* { dg-do assemble } */ | ||
| 25574 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25575 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25576 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25577 | +/* { dg-add-options arm_neon } */ | ||
| 25578 | |||
| 25579 | #include "arm_neon.h" | ||
| 25580 | |||
| 25581 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c | ||
| 25582 | =================================================================== | ||
| 25583 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c | ||
| 25584 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c | ||
| 25585 | @@ -3,7 +3,8 @@ | ||
| 25586 | |||
| 25587 | /* { dg-do assemble } */ | ||
| 25588 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25589 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25590 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25591 | +/* { dg-add-options arm_neon } */ | ||
| 25592 | |||
| 25593 | #include "arm_neon.h" | ||
| 25594 | |||
| 25595 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c | ||
| 25596 | =================================================================== | ||
| 25597 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c | ||
| 25598 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c | ||
| 25599 | @@ -3,7 +3,8 @@ | ||
| 25600 | |||
| 25601 | /* { dg-do assemble } */ | ||
| 25602 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25603 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25604 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25605 | +/* { dg-add-options arm_neon } */ | ||
| 25606 | |||
| 25607 | #include "arm_neon.h" | ||
| 25608 | |||
| 25609 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c | ||
| 25610 | =================================================================== | ||
| 25611 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c | ||
| 25612 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c | ||
| 25613 | @@ -3,7 +3,8 @@ | ||
| 25614 | |||
| 25615 | /* { dg-do assemble } */ | ||
| 25616 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25617 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25618 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25619 | +/* { dg-add-options arm_neon } */ | ||
| 25620 | |||
| 25621 | #include "arm_neon.h" | ||
| 25622 | |||
| 25623 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c | ||
| 25624 | =================================================================== | ||
| 25625 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c | ||
| 25626 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c | ||
| 25627 | @@ -3,7 +3,8 @@ | ||
| 25628 | |||
| 25629 | /* { dg-do assemble } */ | ||
| 25630 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25631 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25632 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25633 | +/* { dg-add-options arm_neon } */ | ||
| 25634 | |||
| 25635 | #include "arm_neon.h" | ||
| 25636 | |||
| 25637 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c | ||
| 25638 | =================================================================== | ||
| 25639 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c | ||
| 25640 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c | ||
| 25641 | @@ -3,7 +3,8 @@ | ||
| 25642 | |||
| 25643 | /* { dg-do assemble } */ | ||
| 25644 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25645 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25646 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25647 | +/* { dg-add-options arm_neon } */ | ||
| 25648 | |||
| 25649 | #include "arm_neon.h" | ||
| 25650 | |||
| 25651 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c | ||
| 25652 | =================================================================== | ||
| 25653 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c | ||
| 25654 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c | ||
| 25655 | @@ -3,7 +3,8 @@ | ||
| 25656 | |||
| 25657 | /* { dg-do assemble } */ | ||
| 25658 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25659 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25660 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25661 | +/* { dg-add-options arm_neon } */ | ||
| 25662 | |||
| 25663 | #include "arm_neon.h" | ||
| 25664 | |||
| 25665 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c | ||
| 25666 | =================================================================== | ||
| 25667 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c | ||
| 25668 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c | ||
| 25669 | @@ -3,7 +3,8 @@ | ||
| 25670 | |||
| 25671 | /* { dg-do assemble } */ | ||
| 25672 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25673 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25674 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25675 | +/* { dg-add-options arm_neon } */ | ||
| 25676 | |||
| 25677 | #include "arm_neon.h" | ||
| 25678 | |||
| 25679 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c | ||
| 25680 | =================================================================== | ||
| 25681 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c | ||
| 25682 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c | ||
| 25683 | @@ -3,7 +3,8 @@ | ||
| 25684 | |||
| 25685 | /* { dg-do assemble } */ | ||
| 25686 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25687 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25688 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25689 | +/* { dg-add-options arm_neon } */ | ||
| 25690 | |||
| 25691 | #include "arm_neon.h" | ||
| 25692 | |||
| 25693 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c | ||
| 25694 | =================================================================== | ||
| 25695 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c | ||
| 25696 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c | ||
| 25697 | @@ -3,7 +3,8 @@ | ||
| 25698 | |||
| 25699 | /* { dg-do assemble } */ | ||
| 25700 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25701 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25702 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25703 | +/* { dg-add-options arm_neon } */ | ||
| 25704 | |||
| 25705 | #include "arm_neon.h" | ||
| 25706 | |||
| 25707 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c | ||
| 25708 | =================================================================== | ||
| 25709 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c | ||
| 25710 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c | ||
| 25711 | @@ -3,7 +3,8 @@ | ||
| 25712 | |||
| 25713 | /* { dg-do assemble } */ | ||
| 25714 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25715 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25716 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25717 | +/* { dg-add-options arm_neon } */ | ||
| 25718 | |||
| 25719 | #include "arm_neon.h" | ||
| 25720 | |||
| 25721 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c | ||
| 25722 | =================================================================== | ||
| 25723 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c | ||
| 25724 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c | ||
| 25725 | @@ -3,7 +3,8 @@ | ||
| 25726 | |||
| 25727 | /* { dg-do assemble } */ | ||
| 25728 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25729 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25730 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25731 | +/* { dg-add-options arm_neon } */ | ||
| 25732 | |||
| 25733 | #include "arm_neon.h" | ||
| 25734 | |||
| 25735 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c | ||
| 25736 | =================================================================== | ||
| 25737 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c | ||
| 25738 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c | ||
| 25739 | @@ -3,7 +3,8 @@ | ||
| 25740 | |||
| 25741 | /* { dg-do assemble } */ | ||
| 25742 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25743 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25744 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25745 | +/* { dg-add-options arm_neon } */ | ||
| 25746 | |||
| 25747 | #include "arm_neon.h" | ||
| 25748 | |||
| 25749 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrns16.c | ||
| 25750 | =================================================================== | ||
| 25751 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrns16.c | ||
| 25752 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrns16.c | ||
| 25753 | @@ -3,7 +3,8 @@ | ||
| 25754 | |||
| 25755 | /* { dg-do assemble } */ | ||
| 25756 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25757 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25758 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25759 | +/* { dg-add-options arm_neon } */ | ||
| 25760 | |||
| 25761 | #include "arm_neon.h" | ||
| 25762 | |||
| 25763 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrns32.c | ||
| 25764 | =================================================================== | ||
| 25765 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrns32.c | ||
| 25766 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrns32.c | ||
| 25767 | @@ -3,7 +3,8 @@ | ||
| 25768 | |||
| 25769 | /* { dg-do assemble } */ | ||
| 25770 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25771 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25772 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25773 | +/* { dg-add-options arm_neon } */ | ||
| 25774 | |||
| 25775 | #include "arm_neon.h" | ||
| 25776 | |||
| 25777 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrns8.c | ||
| 25778 | =================================================================== | ||
| 25779 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrns8.c | ||
| 25780 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrns8.c | ||
| 25781 | @@ -3,7 +3,8 @@ | ||
| 25782 | |||
| 25783 | /* { dg-do assemble } */ | ||
| 25784 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25785 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25786 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25787 | +/* { dg-add-options arm_neon } */ | ||
| 25788 | |||
| 25789 | #include "arm_neon.h" | ||
| 25790 | |||
| 25791 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c | ||
| 25792 | =================================================================== | ||
| 25793 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c | ||
| 25794 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c | ||
| 25795 | @@ -3,7 +3,8 @@ | ||
| 25796 | |||
| 25797 | /* { dg-do assemble } */ | ||
| 25798 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25799 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25800 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25801 | +/* { dg-add-options arm_neon } */ | ||
| 25802 | |||
| 25803 | #include "arm_neon.h" | ||
| 25804 | |||
| 25805 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c | ||
| 25806 | =================================================================== | ||
| 25807 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c | ||
| 25808 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c | ||
| 25809 | @@ -3,7 +3,8 @@ | ||
| 25810 | |||
| 25811 | /* { dg-do assemble } */ | ||
| 25812 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25813 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25814 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25815 | +/* { dg-add-options arm_neon } */ | ||
| 25816 | |||
| 25817 | #include "arm_neon.h" | ||
| 25818 | |||
| 25819 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c | ||
| 25820 | =================================================================== | ||
| 25821 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c | ||
| 25822 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c | ||
| 25823 | @@ -3,7 +3,8 @@ | ||
| 25824 | |||
| 25825 | /* { dg-do assemble } */ | ||
| 25826 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25827 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25828 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25829 | +/* { dg-add-options arm_neon } */ | ||
| 25830 | |||
| 25831 | #include "arm_neon.h" | ||
| 25832 | |||
| 25833 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c | ||
| 25834 | =================================================================== | ||
| 25835 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c | ||
| 25836 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c | ||
| 25837 | @@ -3,7 +3,8 @@ | ||
| 25838 | |||
| 25839 | /* { dg-do assemble } */ | ||
| 25840 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25841 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25842 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25843 | +/* { dg-add-options arm_neon } */ | ||
| 25844 | |||
| 25845 | #include "arm_neon.h" | ||
| 25846 | |||
| 25847 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c | ||
| 25848 | =================================================================== | ||
| 25849 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c | ||
| 25850 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c | ||
| 25851 | @@ -3,7 +3,8 @@ | ||
| 25852 | |||
| 25853 | /* { dg-do assemble } */ | ||
| 25854 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25855 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25856 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25857 | +/* { dg-add-options arm_neon } */ | ||
| 25858 | |||
| 25859 | #include "arm_neon.h" | ||
| 25860 | |||
| 25861 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c | ||
| 25862 | =================================================================== | ||
| 25863 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c | ||
| 25864 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c | ||
| 25865 | @@ -3,7 +3,8 @@ | ||
| 25866 | |||
| 25867 | /* { dg-do assemble } */ | ||
| 25868 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25869 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25870 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25871 | +/* { dg-add-options arm_neon } */ | ||
| 25872 | |||
| 25873 | #include "arm_neon.h" | ||
| 25874 | |||
| 25875 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c | ||
| 25876 | =================================================================== | ||
| 25877 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c | ||
| 25878 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c | ||
| 25879 | @@ -3,7 +3,8 @@ | ||
| 25880 | |||
| 25881 | /* { dg-do assemble } */ | ||
| 25882 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25883 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25884 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25885 | +/* { dg-add-options arm_neon } */ | ||
| 25886 | |||
| 25887 | #include "arm_neon.h" | ||
| 25888 | |||
| 25889 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c | ||
| 25890 | =================================================================== | ||
| 25891 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c | ||
| 25892 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c | ||
| 25893 | @@ -3,7 +3,8 @@ | ||
| 25894 | |||
| 25895 | /* { dg-do assemble } */ | ||
| 25896 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25897 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25898 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25899 | +/* { dg-add-options arm_neon } */ | ||
| 25900 | |||
| 25901 | #include "arm_neon.h" | ||
| 25902 | |||
| 25903 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c | ||
| 25904 | =================================================================== | ||
| 25905 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c | ||
| 25906 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c | ||
| 25907 | @@ -3,7 +3,8 @@ | ||
| 25908 | |||
| 25909 | /* { dg-do assemble } */ | ||
| 25910 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25911 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25912 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25913 | +/* { dg-add-options arm_neon } */ | ||
| 25914 | |||
| 25915 | #include "arm_neon.h" | ||
| 25916 | |||
| 25917 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c | ||
| 25918 | =================================================================== | ||
| 25919 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c | ||
| 25920 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c | ||
| 25921 | @@ -3,7 +3,8 @@ | ||
| 25922 | |||
| 25923 | /* { dg-do assemble } */ | ||
| 25924 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25925 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25926 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25927 | +/* { dg-add-options arm_neon } */ | ||
| 25928 | |||
| 25929 | #include "arm_neon.h" | ||
| 25930 | |||
| 25931 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstp8.c | ||
| 25932 | =================================================================== | ||
| 25933 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstp8.c | ||
| 25934 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstp8.c | ||
| 25935 | @@ -3,7 +3,8 @@ | ||
| 25936 | |||
| 25937 | /* { dg-do assemble } */ | ||
| 25938 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25939 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25940 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25941 | +/* { dg-add-options arm_neon } */ | ||
| 25942 | |||
| 25943 | #include "arm_neon.h" | ||
| 25944 | |||
| 25945 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtsts16.c | ||
| 25946 | =================================================================== | ||
| 25947 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtsts16.c | ||
| 25948 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtsts16.c | ||
| 25949 | @@ -3,7 +3,8 @@ | ||
| 25950 | |||
| 25951 | /* { dg-do assemble } */ | ||
| 25952 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25953 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25954 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25955 | +/* { dg-add-options arm_neon } */ | ||
| 25956 | |||
| 25957 | #include "arm_neon.h" | ||
| 25958 | |||
| 25959 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtsts32.c | ||
| 25960 | =================================================================== | ||
| 25961 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtsts32.c | ||
| 25962 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtsts32.c | ||
| 25963 | @@ -3,7 +3,8 @@ | ||
| 25964 | |||
| 25965 | /* { dg-do assemble } */ | ||
| 25966 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25967 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25968 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25969 | +/* { dg-add-options arm_neon } */ | ||
| 25970 | |||
| 25971 | #include "arm_neon.h" | ||
| 25972 | |||
| 25973 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtsts8.c | ||
| 25974 | =================================================================== | ||
| 25975 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtsts8.c | ||
| 25976 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtsts8.c | ||
| 25977 | @@ -3,7 +3,8 @@ | ||
| 25978 | |||
| 25979 | /* { dg-do assemble } */ | ||
| 25980 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25981 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25982 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25983 | +/* { dg-add-options arm_neon } */ | ||
| 25984 | |||
| 25985 | #include "arm_neon.h" | ||
| 25986 | |||
| 25987 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstu16.c | ||
| 25988 | =================================================================== | ||
| 25989 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstu16.c | ||
| 25990 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstu16.c | ||
| 25991 | @@ -3,7 +3,8 @@ | ||
| 25992 | |||
| 25993 | /* { dg-do assemble } */ | ||
| 25994 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 25995 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 25996 | +/* { dg-options "-save-temps -O0" } */ | ||
| 25997 | +/* { dg-add-options arm_neon } */ | ||
| 25998 | |||
| 25999 | #include "arm_neon.h" | ||
| 26000 | |||
| 26001 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstu32.c | ||
| 26002 | =================================================================== | ||
| 26003 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstu32.c | ||
| 26004 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstu32.c | ||
| 26005 | @@ -3,7 +3,8 @@ | ||
| 26006 | |||
| 26007 | /* { dg-do assemble } */ | ||
| 26008 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26009 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26010 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26011 | +/* { dg-add-options arm_neon } */ | ||
| 26012 | |||
| 26013 | #include "arm_neon.h" | ||
| 26014 | |||
| 26015 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstu8.c | ||
| 26016 | =================================================================== | ||
| 26017 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vtstu8.c | ||
| 26018 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vtstu8.c | ||
| 26019 | @@ -3,7 +3,8 @@ | ||
| 26020 | |||
| 26021 | /* { dg-do assemble } */ | ||
| 26022 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26023 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26024 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26025 | +/* { dg-add-options arm_neon } */ | ||
| 26026 | |||
| 26027 | #include "arm_neon.h" | ||
| 26028 | |||
| 26029 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c | ||
| 26030 | =================================================================== | ||
| 26031 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c | ||
| 26032 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c | ||
| 26033 | @@ -3,7 +3,8 @@ | ||
| 26034 | |||
| 26035 | /* { dg-do assemble } */ | ||
| 26036 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26037 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26038 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26039 | +/* { dg-add-options arm_neon } */ | ||
| 26040 | |||
| 26041 | #include "arm_neon.h" | ||
| 26042 | |||
| 26043 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c | ||
| 26044 | =================================================================== | ||
| 26045 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c | ||
| 26046 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c | ||
| 26047 | @@ -3,7 +3,8 @@ | ||
| 26048 | |||
| 26049 | /* { dg-do assemble } */ | ||
| 26050 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26051 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26052 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26053 | +/* { dg-add-options arm_neon } */ | ||
| 26054 | |||
| 26055 | #include "arm_neon.h" | ||
| 26056 | |||
| 26057 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c | ||
| 26058 | =================================================================== | ||
| 26059 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c | ||
| 26060 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c | ||
| 26061 | @@ -3,7 +3,8 @@ | ||
| 26062 | |||
| 26063 | /* { dg-do assemble } */ | ||
| 26064 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26065 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26066 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26067 | +/* { dg-add-options arm_neon } */ | ||
| 26068 | |||
| 26069 | #include "arm_neon.h" | ||
| 26070 | |||
| 26071 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c | ||
| 26072 | =================================================================== | ||
| 26073 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c | ||
| 26074 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c | ||
| 26075 | @@ -3,7 +3,8 @@ | ||
| 26076 | |||
| 26077 | /* { dg-do assemble } */ | ||
| 26078 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26079 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26080 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26081 | +/* { dg-add-options arm_neon } */ | ||
| 26082 | |||
| 26083 | #include "arm_neon.h" | ||
| 26084 | |||
| 26085 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c | ||
| 26086 | =================================================================== | ||
| 26087 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c | ||
| 26088 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c | ||
| 26089 | @@ -3,7 +3,8 @@ | ||
| 26090 | |||
| 26091 | /* { dg-do assemble } */ | ||
| 26092 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26093 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26094 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26095 | +/* { dg-add-options arm_neon } */ | ||
| 26096 | |||
| 26097 | #include "arm_neon.h" | ||
| 26098 | |||
| 26099 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c | ||
| 26100 | =================================================================== | ||
| 26101 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c | ||
| 26102 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c | ||
| 26103 | @@ -3,7 +3,8 @@ | ||
| 26104 | |||
| 26105 | /* { dg-do assemble } */ | ||
| 26106 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26107 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26108 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26109 | +/* { dg-add-options arm_neon } */ | ||
| 26110 | |||
| 26111 | #include "arm_neon.h" | ||
| 26112 | |||
| 26113 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c | ||
| 26114 | =================================================================== | ||
| 26115 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c | ||
| 26116 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c | ||
| 26117 | @@ -3,7 +3,8 @@ | ||
| 26118 | |||
| 26119 | /* { dg-do assemble } */ | ||
| 26120 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26121 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26122 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26123 | +/* { dg-add-options arm_neon } */ | ||
| 26124 | |||
| 26125 | #include "arm_neon.h" | ||
| 26126 | |||
| 26127 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c | ||
| 26128 | =================================================================== | ||
| 26129 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c | ||
| 26130 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c | ||
| 26131 | @@ -3,7 +3,8 @@ | ||
| 26132 | |||
| 26133 | /* { dg-do assemble } */ | ||
| 26134 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26135 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26136 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26137 | +/* { dg-add-options arm_neon } */ | ||
| 26138 | |||
| 26139 | #include "arm_neon.h" | ||
| 26140 | |||
| 26141 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c | ||
| 26142 | =================================================================== | ||
| 26143 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c | ||
| 26144 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c | ||
| 26145 | @@ -3,7 +3,8 @@ | ||
| 26146 | |||
| 26147 | /* { dg-do assemble } */ | ||
| 26148 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26149 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26150 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26151 | +/* { dg-add-options arm_neon } */ | ||
| 26152 | |||
| 26153 | #include "arm_neon.h" | ||
| 26154 | |||
| 26155 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c | ||
| 26156 | =================================================================== | ||
| 26157 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c | ||
| 26158 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c | ||
| 26159 | @@ -3,7 +3,8 @@ | ||
| 26160 | |||
| 26161 | /* { dg-do assemble } */ | ||
| 26162 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26163 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26164 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26165 | +/* { dg-add-options arm_neon } */ | ||
| 26166 | |||
| 26167 | #include "arm_neon.h" | ||
| 26168 | |||
| 26169 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c | ||
| 26170 | =================================================================== | ||
| 26171 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c | ||
| 26172 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c | ||
| 26173 | @@ -3,7 +3,8 @@ | ||
| 26174 | |||
| 26175 | /* { dg-do assemble } */ | ||
| 26176 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26177 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26178 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26179 | +/* { dg-add-options arm_neon } */ | ||
| 26180 | |||
| 26181 | #include "arm_neon.h" | ||
| 26182 | |||
| 26183 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c | ||
| 26184 | =================================================================== | ||
| 26185 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c | ||
| 26186 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c | ||
| 26187 | @@ -3,7 +3,8 @@ | ||
| 26188 | |||
| 26189 | /* { dg-do assemble } */ | ||
| 26190 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26191 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26192 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26193 | +/* { dg-add-options arm_neon } */ | ||
| 26194 | |||
| 26195 | #include "arm_neon.h" | ||
| 26196 | |||
| 26197 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzps16.c | ||
| 26198 | =================================================================== | ||
| 26199 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzps16.c | ||
| 26200 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzps16.c | ||
| 26201 | @@ -3,7 +3,8 @@ | ||
| 26202 | |||
| 26203 | /* { dg-do assemble } */ | ||
| 26204 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26205 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26206 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26207 | +/* { dg-add-options arm_neon } */ | ||
| 26208 | |||
| 26209 | #include "arm_neon.h" | ||
| 26210 | |||
| 26211 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzps32.c | ||
| 26212 | =================================================================== | ||
| 26213 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzps32.c | ||
| 26214 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzps32.c | ||
| 26215 | @@ -3,7 +3,8 @@ | ||
| 26216 | |||
| 26217 | /* { dg-do assemble } */ | ||
| 26218 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26219 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26220 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26221 | +/* { dg-add-options arm_neon } */ | ||
| 26222 | |||
| 26223 | #include "arm_neon.h" | ||
| 26224 | |||
| 26225 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzps8.c | ||
| 26226 | =================================================================== | ||
| 26227 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzps8.c | ||
| 26228 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzps8.c | ||
| 26229 | @@ -3,7 +3,8 @@ | ||
| 26230 | |||
| 26231 | /* { dg-do assemble } */ | ||
| 26232 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26233 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26234 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26235 | +/* { dg-add-options arm_neon } */ | ||
| 26236 | |||
| 26237 | #include "arm_neon.h" | ||
| 26238 | |||
| 26239 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c | ||
| 26240 | =================================================================== | ||
| 26241 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c | ||
| 26242 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c | ||
| 26243 | @@ -3,7 +3,8 @@ | ||
| 26244 | |||
| 26245 | /* { dg-do assemble } */ | ||
| 26246 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26247 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26248 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26249 | +/* { dg-add-options arm_neon } */ | ||
| 26250 | |||
| 26251 | #include "arm_neon.h" | ||
| 26252 | |||
| 26253 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c | ||
| 26254 | =================================================================== | ||
| 26255 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c | ||
| 26256 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c | ||
| 26257 | @@ -3,7 +3,8 @@ | ||
| 26258 | |||
| 26259 | /* { dg-do assemble } */ | ||
| 26260 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26261 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26262 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26263 | +/* { dg-add-options arm_neon } */ | ||
| 26264 | |||
| 26265 | #include "arm_neon.h" | ||
| 26266 | |||
| 26267 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c | ||
| 26268 | =================================================================== | ||
| 26269 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c | ||
| 26270 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c | ||
| 26271 | @@ -3,7 +3,8 @@ | ||
| 26272 | |||
| 26273 | /* { dg-do assemble } */ | ||
| 26274 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26275 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26276 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26277 | +/* { dg-add-options arm_neon } */ | ||
| 26278 | |||
| 26279 | #include "arm_neon.h" | ||
| 26280 | |||
| 26281 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c | ||
| 26282 | =================================================================== | ||
| 26283 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c | ||
| 26284 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c | ||
| 26285 | @@ -3,7 +3,8 @@ | ||
| 26286 | |||
| 26287 | /* { dg-do assemble } */ | ||
| 26288 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26289 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26290 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26291 | +/* { dg-add-options arm_neon } */ | ||
| 26292 | |||
| 26293 | #include "arm_neon.h" | ||
| 26294 | |||
| 26295 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c | ||
| 26296 | =================================================================== | ||
| 26297 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c | ||
| 26298 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c | ||
| 26299 | @@ -3,7 +3,8 @@ | ||
| 26300 | |||
| 26301 | /* { dg-do assemble } */ | ||
| 26302 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26303 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26304 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26305 | +/* { dg-add-options arm_neon } */ | ||
| 26306 | |||
| 26307 | #include "arm_neon.h" | ||
| 26308 | |||
| 26309 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c | ||
| 26310 | =================================================================== | ||
| 26311 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c | ||
| 26312 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c | ||
| 26313 | @@ -3,7 +3,8 @@ | ||
| 26314 | |||
| 26315 | /* { dg-do assemble } */ | ||
| 26316 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26317 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26318 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26319 | +/* { dg-add-options arm_neon } */ | ||
| 26320 | |||
| 26321 | #include "arm_neon.h" | ||
| 26322 | |||
| 26323 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c | ||
| 26324 | =================================================================== | ||
| 26325 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c | ||
| 26326 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c | ||
| 26327 | @@ -3,7 +3,8 @@ | ||
| 26328 | |||
| 26329 | /* { dg-do assemble } */ | ||
| 26330 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26331 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26332 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26333 | +/* { dg-add-options arm_neon } */ | ||
| 26334 | |||
| 26335 | #include "arm_neon.h" | ||
| 26336 | |||
| 26337 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c | ||
| 26338 | =================================================================== | ||
| 26339 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c | ||
| 26340 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c | ||
| 26341 | @@ -3,7 +3,8 @@ | ||
| 26342 | |||
| 26343 | /* { dg-do assemble } */ | ||
| 26344 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26345 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26346 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26347 | +/* { dg-add-options arm_neon } */ | ||
| 26348 | |||
| 26349 | #include "arm_neon.h" | ||
| 26350 | |||
| 26351 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c | ||
| 26352 | =================================================================== | ||
| 26353 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c | ||
| 26354 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c | ||
| 26355 | @@ -3,7 +3,8 @@ | ||
| 26356 | |||
| 26357 | /* { dg-do assemble } */ | ||
| 26358 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26359 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26360 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26361 | +/* { dg-add-options arm_neon } */ | ||
| 26362 | |||
| 26363 | #include "arm_neon.h" | ||
| 26364 | |||
| 26365 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c | ||
| 26366 | =================================================================== | ||
| 26367 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c | ||
| 26368 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c | ||
| 26369 | @@ -3,7 +3,8 @@ | ||
| 26370 | |||
| 26371 | /* { dg-do assemble } */ | ||
| 26372 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26373 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26374 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26375 | +/* { dg-add-options arm_neon } */ | ||
| 26376 | |||
| 26377 | #include "arm_neon.h" | ||
| 26378 | |||
| 26379 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c | ||
| 26380 | =================================================================== | ||
| 26381 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c | ||
| 26382 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c | ||
| 26383 | @@ -3,7 +3,8 @@ | ||
| 26384 | |||
| 26385 | /* { dg-do assemble } */ | ||
| 26386 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26387 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26388 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26389 | +/* { dg-add-options arm_neon } */ | ||
| 26390 | |||
| 26391 | #include "arm_neon.h" | ||
| 26392 | |||
| 26393 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c | ||
| 26394 | =================================================================== | ||
| 26395 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c | ||
| 26396 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c | ||
| 26397 | @@ -3,7 +3,8 @@ | ||
| 26398 | |||
| 26399 | /* { dg-do assemble } */ | ||
| 26400 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26401 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26402 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26403 | +/* { dg-add-options arm_neon } */ | ||
| 26404 | |||
| 26405 | #include "arm_neon.h" | ||
| 26406 | |||
| 26407 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipf32.c | ||
| 26408 | =================================================================== | ||
| 26409 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipf32.c | ||
| 26410 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipf32.c | ||
| 26411 | @@ -3,7 +3,8 @@ | ||
| 26412 | |||
| 26413 | /* { dg-do assemble } */ | ||
| 26414 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26415 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26416 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26417 | +/* { dg-add-options arm_neon } */ | ||
| 26418 | |||
| 26419 | #include "arm_neon.h" | ||
| 26420 | |||
| 26421 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipp16.c | ||
| 26422 | =================================================================== | ||
| 26423 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipp16.c | ||
| 26424 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipp16.c | ||
| 26425 | @@ -3,7 +3,8 @@ | ||
| 26426 | |||
| 26427 | /* { dg-do assemble } */ | ||
| 26428 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26429 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26430 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26431 | +/* { dg-add-options arm_neon } */ | ||
| 26432 | |||
| 26433 | #include "arm_neon.h" | ||
| 26434 | |||
| 26435 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipp8.c | ||
| 26436 | =================================================================== | ||
| 26437 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipp8.c | ||
| 26438 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipp8.c | ||
| 26439 | @@ -3,7 +3,8 @@ | ||
| 26440 | |||
| 26441 | /* { dg-do assemble } */ | ||
| 26442 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26443 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26444 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26445 | +/* { dg-add-options arm_neon } */ | ||
| 26446 | |||
| 26447 | #include "arm_neon.h" | ||
| 26448 | |||
| 26449 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzips16.c | ||
| 26450 | =================================================================== | ||
| 26451 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzips16.c | ||
| 26452 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzips16.c | ||
| 26453 | @@ -3,7 +3,8 @@ | ||
| 26454 | |||
| 26455 | /* { dg-do assemble } */ | ||
| 26456 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26457 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26458 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26459 | +/* { dg-add-options arm_neon } */ | ||
| 26460 | |||
| 26461 | #include "arm_neon.h" | ||
| 26462 | |||
| 26463 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzips32.c | ||
| 26464 | =================================================================== | ||
| 26465 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzips32.c | ||
| 26466 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzips32.c | ||
| 26467 | @@ -3,7 +3,8 @@ | ||
| 26468 | |||
| 26469 | /* { dg-do assemble } */ | ||
| 26470 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26471 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26472 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26473 | +/* { dg-add-options arm_neon } */ | ||
| 26474 | |||
| 26475 | #include "arm_neon.h" | ||
| 26476 | |||
| 26477 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzips8.c | ||
| 26478 | =================================================================== | ||
| 26479 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzips8.c | ||
| 26480 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzips8.c | ||
| 26481 | @@ -3,7 +3,8 @@ | ||
| 26482 | |||
| 26483 | /* { dg-do assemble } */ | ||
| 26484 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26485 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26486 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26487 | +/* { dg-add-options arm_neon } */ | ||
| 26488 | |||
| 26489 | #include "arm_neon.h" | ||
| 26490 | |||
| 26491 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipu16.c | ||
| 26492 | =================================================================== | ||
| 26493 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipu16.c | ||
| 26494 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipu16.c | ||
| 26495 | @@ -3,7 +3,8 @@ | ||
| 26496 | |||
| 26497 | /* { dg-do assemble } */ | ||
| 26498 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26499 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26500 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26501 | +/* { dg-add-options arm_neon } */ | ||
| 26502 | |||
| 26503 | #include "arm_neon.h" | ||
| 26504 | |||
| 26505 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipu32.c | ||
| 26506 | =================================================================== | ||
| 26507 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipu32.c | ||
| 26508 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipu32.c | ||
| 26509 | @@ -3,7 +3,8 @@ | ||
| 26510 | |||
| 26511 | /* { dg-do assemble } */ | ||
| 26512 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26513 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26514 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26515 | +/* { dg-add-options arm_neon } */ | ||
| 26516 | |||
| 26517 | #include "arm_neon.h" | ||
| 26518 | |||
| 26519 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipu8.c | ||
| 26520 | =================================================================== | ||
| 26521 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/neon/vzipu8.c | ||
| 26522 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/neon/vzipu8.c | ||
| 26523 | @@ -3,7 +3,8 @@ | ||
| 26524 | |||
| 26525 | /* { dg-do assemble } */ | ||
| 26526 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 26527 | -/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ | ||
| 26528 | +/* { dg-options "-save-temps -O0" } */ | ||
| 26529 | +/* { dg-add-options arm_neon } */ | ||
| 26530 | |||
| 26531 | #include "arm_neon.h" | ||
| 26532 | |||
| 26533 | Index: gcc-4_5-branch/gcc/testsuite/gfortran.dg/vect/vect.exp | ||
| 26534 | =================================================================== | ||
| 26535 | --- gcc-4_5-branch.orig/gcc/testsuite/gfortran.dg/vect/vect.exp | ||
| 26536 | +++ gcc-4_5-branch/gcc/testsuite/gfortran.dg/vect/vect.exp | ||
| 26537 | @@ -105,7 +105,7 @@ if [istarget "powerpc-*paired*"] { | ||
| 26538 | } elseif [istarget "ia64-*-*"] { | ||
| 26539 | set dg-do-what-default run | ||
| 26540 | } elseif [is-effective-target arm_neon_ok] { | ||
| 26541 | - lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp" | ||
| 26542 | + eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""] | ||
| 26543 | if [is-effective-target arm_neon_hw] { | ||
| 26544 | set dg-do-what-default run | ||
| 26545 | } else { | ||
| 26546 | Index: gcc-4_5-branch/gcc/testsuite/lib/target-supports.exp | ||
| 26547 | =================================================================== | ||
| 26548 | --- gcc-4_5-branch.orig/gcc/testsuite/lib/target-supports.exp | ||
| 26549 | +++ gcc-4_5-branch/gcc/testsuite/lib/target-supports.exp | ||
| 26550 | @@ -1695,19 +1695,87 @@ proc check_effective_target_arm_hard_vfp | ||
| 26551 | } | ||
| 26552 | } | ||
| 26553 | |||
| 26554 | +# Add the options needed for NEON. We need either -mfloat-abi=softfp | ||
| 26555 | +# or -mfloat-abi=hard, but if one is already specified by the | ||
| 26556 | +# multilib, use it. Similarly, if a -mfpu option already enables | ||
| 26557 | +# NEON, do not add -mfpu=neon. | ||
| 26558 | + | ||
| 26559 | +proc add_options_for_arm_neon { flags } { | ||
| 26560 | + if { ! [check_effective_target_arm_neon_ok] } { | ||
| 26561 | + return "$flags" | ||
| 26562 | + } | ||
| 26563 | + global et_arm_neon_flags | ||
| 26564 | + return "$flags $et_arm_neon_flags" | ||
| 26565 | +} | ||
| 26566 | + | ||
| 26567 | # Return 1 if this is an ARM target supporting -mfpu=neon | ||
| 26568 | -# -mfloat-abi=softfp. Some multilibs may be incompatible with these | ||
| 26569 | -# options. | ||
| 26570 | +# -mfloat-abi=softfp or equivalent options. Some multilibs may be | ||
| 26571 | +# incompatible with these options. Also set et_arm_neon_flags to the | ||
| 26572 | +# best options to add. | ||
| 26573 | + | ||
| 26574 | +proc check_effective_target_arm_neon_ok_nocache { } { | ||
| 26575 | + global et_arm_neon_flags | ||
| 26576 | + set et_arm_neon_flags "" | ||
| 26577 | + if { [check_effective_target_arm32] } { | ||
| 26578 | + foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp"} { | ||
| 26579 | + if { [check_no_compiler_messages_nocache arm_neon_ok object { | ||
| 26580 | + #include "arm_neon.h" | ||
| 26581 | + int dummy; | ||
| 26582 | + } "$flags"] } { | ||
| 26583 | + set et_arm_neon_flags $flags | ||
| 26584 | + return 1 | ||
| 26585 | + } | ||
| 26586 | + } | ||
| 26587 | + } | ||
| 26588 | + | ||
| 26589 | + return 0 | ||
| 26590 | +} | ||
| 26591 | |||
| 26592 | proc check_effective_target_arm_neon_ok { } { | ||
| 26593 | + return [check_cached_effective_target arm_neon_ok \ | ||
| 26594 | + check_effective_target_arm_neon_ok_nocache] | ||
| 26595 | +} | ||
| 26596 | + | ||
| 26597 | +# Add the options needed for NEON. We need either -mfloat-abi=softfp | ||
| 26598 | +# or -mfloat-abi=hard, but if one is already specified by the | ||
| 26599 | +# multilib, use it. | ||
| 26600 | + | ||
| 26601 | +proc add_options_for_arm_neon_fp16 { flags } { | ||
| 26602 | + if { ! [check_effective_target_arm_neon_fp16_ok] } { | ||
| 26603 | + return "$flags" | ||
| 26604 | + } | ||
| 26605 | + global et_arm_neon_fp16_flags | ||
| 26606 | + return "$flags $et_arm_neon_fp16_flags" | ||
| 26607 | +} | ||
| 26608 | + | ||
| 26609 | +# Return 1 if this is an ARM target supporting -mfpu=neon-fp16 | ||
| 26610 | +# -mfloat-abi=softfp or equivalent options. Some multilibs may be | ||
| 26611 | +# incompatible with these options. Also set et_arm_neon_flags to the | ||
| 26612 | +# best options to add. | ||
| 26613 | + | ||
| 26614 | +proc check_effective_target_arm_neon_fp16_ok_nocache { } { | ||
| 26615 | + global et_arm_neon_fp16_flags | ||
| 26616 | + set et_arm_neon_fp16_flags "" | ||
| 26617 | if { [check_effective_target_arm32] } { | ||
| 26618 | - return [check_no_compiler_messages arm_neon_ok object { | ||
| 26619 | - #include "arm_neon.h" | ||
| 26620 | - int dummy; | ||
| 26621 | - } "-mfpu=neon -mfloat-abi=softfp"] | ||
| 26622 | - } else { | ||
| 26623 | - return 0 | ||
| 26624 | + # Always add -mfpu=neon-fp16, since there is no preprocessor | ||
| 26625 | + # macro for FP16 support. | ||
| 26626 | + foreach flags {"-mfpu=neon-fp16" "-mfpu=neon-fp16 -mfloat-abi=softfp"} { | ||
| 26627 | + if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object { | ||
| 26628 | + #include "arm_neon.h" | ||
| 26629 | + int dummy; | ||
| 26630 | + } "$flags"] } { | ||
| 26631 | + set et_arm_neon_fp16_flags $flags | ||
| 26632 | + return 1 | ||
| 26633 | + } | ||
| 26634 | + } | ||
| 26635 | } | ||
| 26636 | + | ||
| 26637 | + return 0 | ||
| 26638 | +} | ||
| 26639 | + | ||
| 26640 | +proc check_effective_target_arm_neon_fp16_ok { } { | ||
| 26641 | + return [check_cached_effective_target arm_neon_fp16_ok \ | ||
| 26642 | + check_effective_target_arm_neon_fp16_ok_nocache] | ||
| 26643 | } | ||
| 26644 | |||
| 26645 | # Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be | ||
| 26646 | @@ -1746,7 +1814,7 @@ proc check_effective_target_arm_neon_hw | ||
| 26647 | : "0" (a), "w" (b)); | ||
| 26648 | return (a != 1); | ||
| 26649 | } | ||
| 26650 | - } "-mfpu=neon -mfloat-abi=softfp"] | ||
| 26651 | + } [add_options_for_arm_neon ""]] | ||
| 26652 | } | ||
| 26653 | |||
| 26654 | # Return 1 if this is a ARM target with NEON enabled. | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99299.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99299.patch deleted file mode 100644 index 7dea4303a..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99299.patch +++ /dev/null | |||
| @@ -1,62 +0,0 @@ | |||
| 1 | 2010-07-07 Sandra Loosemore <sandra@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ 4.4: | ||
| 4 | |||
| 5 | 2010-03-08 Paul Brook <paul@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * doc/invoke.texi: Document ARM -mcpu=cortex-m4. | ||
| 9 | * config/arm/arm.c (all_architectures): Change v7e-m default to | ||
| 10 | cortexm4. | ||
| 11 | * config/arm/arm-cores.def: Add cortex-m4. | ||
| 12 | * config/arm/arm-tune.md: Regenerate. | ||
| 13 | |||
| 14 | === modified file 'gcc/config/arm/arm-cores.def' | ||
| 15 | --- old/gcc/config/arm/arm-cores.def 2009-11-20 17:37:30 +0000 | ||
| 16 | +++ new/gcc/config/arm/arm-cores.def 2010-07-29 15:53:39 +0000 | ||
| 17 | @@ -123,6 +123,7 @@ | ||
| 18 | ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, 9e) | ||
| 19 | ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e) | ||
| 20 | ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e) | ||
| 21 | +ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, 9e) | ||
| 22 | ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e) | ||
| 23 | ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e) | ||
| 24 | ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, 9e) | ||
| 25 | |||
| 26 | === modified file 'gcc/config/arm/arm-tune.md' | ||
| 27 | --- old/gcc/config/arm/arm-tune.md 2009-11-20 17:37:30 +0000 | ||
| 28 | +++ new/gcc/config/arm/arm-tune.md 2010-07-29 15:53:39 +0000 | ||
| 29 | @@ -1,5 +1,5 @@ | ||
| 30 | ;; -*- buffer-read-only: t -*- | ||
| 31 | ;; Generated automatically by gentune.sh from arm-cores.def | ||
| 32 | (define_attr "tune" | ||
| 33 | - "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1,cortexm0" | ||
| 34 | + "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0" | ||
| 35 | (const (symbol_ref "((enum attr_tune) arm_tune)"))) | ||
| 36 | |||
| 37 | === modified file 'gcc/config/arm/arm.c' | ||
| 38 | --- old/gcc/config/arm/arm.c 2010-04-02 07:32:00 +0000 | ||
| 39 | +++ new/gcc/config/arm/arm.c 2010-07-29 15:53:39 +0000 | ||
| 40 | @@ -782,7 +782,7 @@ | ||
| 41 | {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL}, | ||
| 42 | {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL}, | ||
| 43 | {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL}, | ||
| 44 | - {"armv7e-m", cortexm3, "7EM", FL_CO_PROC | FL_FOR_ARCH7EM, NULL}, | ||
| 45 | + {"armv7e-m", cortexm4, "7EM", FL_CO_PROC | FL_FOR_ARCH7EM, NULL}, | ||
| 46 | {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, | ||
| 47 | {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, | ||
| 48 | {"iwmmxt2", iwmmxt2, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, | ||
| 49 | |||
| 50 | === modified file 'gcc/doc/invoke.texi' | ||
| 51 | --- old/gcc/doc/invoke.texi 2010-07-29 14:59:35 +0000 | ||
| 52 | +++ new/gcc/doc/invoke.texi 2010-07-29 15:53:39 +0000 | ||
| 53 | @@ -9826,7 +9826,7 @@ | ||
| 54 | @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp}, | ||
| 55 | @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s}, | ||
| 56 | @samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9}, | ||
| 57 | -@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m3}, | ||
| 58 | +@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3}, | ||
| 59 | @samp{cortex-m1}, | ||
| 60 | @samp{cortex-m0}, | ||
| 61 | @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. | ||
| 62 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch deleted file mode 100644 index ae417a18f..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch +++ /dev/null | |||
| @@ -1,3094 +0,0 @@ | |||
| 1 | 2010-07-08 Sandra Loosemore <sandra@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from upstream (originally from Sourcery G++ 4.4): | ||
| 4 | |||
| 5 | 2010-07-02 Sandra Loosemore <sandra@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * config/arm/neon.md (vec_extractv2di): Correct error in register | ||
| 9 | numbering to reconcile with neon_vget_lanev2di. | ||
| 10 | |||
| 11 | 2010-07-02 Sandra Loosemore <sandra@codesourcery.com> | ||
| 12 | |||
| 13 | gcc/ | ||
| 14 | * config/arm/arm.c (neon_vdup_constant): Expand into canonical RTL | ||
| 15 | instead of an unspec. | ||
| 16 | (neon_expand_vector_init): Likewise. | ||
| 17 | * config/arm/neon.md (UNSPEC_VCOMBINE): Delete. | ||
| 18 | (UNSPEC_VDUP_LANE): Delete. | ||
| 19 | (UNSPEC VDUP_N): Delete. | ||
| 20 | (UNSPEC_VGET_HIGH): Delete. | ||
| 21 | (UNSPEC_VGET_LANE): Delete. | ||
| 22 | (UNSPEC_VGET_LOW): Delete. | ||
| 23 | (UNSPEC_VMVN): Delete. | ||
| 24 | (UNSPEC_VSET_LANE): Delete. | ||
| 25 | (V_double_vector_mode): New. | ||
| 26 | (vec_set<mode>_internal): Make code emitted match that for the | ||
| 27 | corresponding intrinsics. | ||
| 28 | (vec_setv2di_internal): Likewise. | ||
| 29 | (neon_vget_lanedi): Rewrite to expand into emit_move_insn. | ||
| 30 | (neon_vget_lanev2di): Rewrite to expand into vec_extractv2di. | ||
| 31 | (neon_vset_lane<mode>): Combine double and quad patterns and | ||
| 32 | expand into vec_set<mode>_internal instead of UNSPEC_VSET_LANE. | ||
| 33 | (neon_vset_lanedi): Rewrite to expand into emit_move_insn. | ||
| 34 | (neon_vdup_n<mode>): Rewrite RTL without unspec. | ||
| 35 | (neon_vdup_ndi): Rewrite as define_expand and use emit_move_insn. | ||
| 36 | (neon_vdup_nv2di): Rewrite RTL without unspec and merge with | ||
| 37 | with neon_vdup_lanev2di, adjusting the pattern from the latter | ||
| 38 | to be predicable for consistency. | ||
| 39 | (neon_vdup_lane<mode>_internal): New. | ||
| 40 | (neon_vdup_lane<mode>): Turn into a define_expand and rewrite | ||
| 41 | to avoid using an unspec. | ||
| 42 | (neon_vdup_lanedi): Rewrite RTL pattern to avoid unspec. | ||
| 43 | (neon_vdup_lanev2di): Turn into a define_expand. | ||
| 44 | (neon_vcombine): Rewrite pattern to eliminate UNPSEC_VCOMBINE. | ||
| 45 | (neon_vget_high<mode>): Replace with.... | ||
| 46 | (neon_vget_highv16qi): New pattern using canonical RTL. | ||
| 47 | (neon_vget_highv8hi): Likewise. | ||
| 48 | (neon_vget_highv4si): Likewise. | ||
| 49 | (neon_vget_highv4sf): Likewise. | ||
| 50 | (neon_vget_highv2di): Likewise. | ||
| 51 | (neon_vget_low<mode>): Replace with.... | ||
| 52 | (neon_vget_lowv16qi): New pattern using canonical RTL. | ||
| 53 | (neon_vget_lowv8hi): Likewise. | ||
| 54 | (neon_vget_lowv4si): Likewise. | ||
| 55 | (neon_vget_lowv4sf): Likewise. | ||
| 56 | (neon_vget_lowv2di): Likewise. | ||
| 57 | |||
| 58 | * config/arm/neon.ml (Vget_lane): Add No_op attribute to suppress | ||
| 59 | test for this emitting vmov. | ||
| 60 | (Vset_lane): Likewise. | ||
| 61 | (Vdup_n): Likewise. | ||
| 62 | (Vmov_n): Likewise. | ||
| 63 | |||
| 64 | * doc/arm-neon-intrinsics.texi: Regenerated. | ||
| 65 | |||
| 66 | gcc/testsuite/ | ||
| 67 | * gcc.target/arm/neon/vdup_ns64.c: Regenerated. | ||
| 68 | * gcc.target/arm/neon/vdup_nu64.c: Regenerated. | ||
| 69 | * gcc.target/arm/neon/vdupQ_ns64.c: Regenerated. | ||
| 70 | * gcc.target/arm/neon/vdupQ_nu64.c: Regenerated. | ||
| 71 | * gcc.target/arm/neon/vmov_ns64.c: Regenerated. | ||
| 72 | * gcc.target/arm/neon/vmov_nu64.c: Regenerated. | ||
| 73 | * gcc.target/arm/neon/vmovQ_ns64.c: Regenerated. | ||
| 74 | * gcc.target/arm/neon/vmovQ_nu64.c: Regenerated. | ||
| 75 | * gcc.target/arm/neon/vget_lanes64.c: Regenerated. | ||
| 76 | * gcc.target/arm/neon/vget_laneu64.c: Regenerated. | ||
| 77 | * gcc.target/arm/neon/vset_lanes64.c: Regenerated. | ||
| 78 | * gcc.target/arm/neon/vset_laneu64.c: Regenerated. | ||
| 79 | * gcc.target/arm/neon-vdup_ns64.c: New. | ||
| 80 | * gcc.target/arm/neon-vdup_nu64.c: New. | ||
| 81 | * gcc.target/arm/neon-vdupQ_ns64.c: New. | ||
| 82 | * gcc.target/arm/neon-vdupQ_nu64.c: New. | ||
| 83 | * gcc.target/arm/neon-vdupQ_lanes64.c: New. | ||
| 84 | * gcc.target/arm/neon-vdupQ_laneu64.c: New. | ||
| 85 | * gcc.target/arm/neon-vmov_ns64.c: New. | ||
| 86 | * gcc.target/arm/neon-vmov_nu64.c: New. | ||
| 87 | * gcc.target/arm/neon-vmovQ_ns64.c: New. | ||
| 88 | * gcc.target/arm/neon-vmovQ_nu64.c: New. | ||
| 89 | * gcc.target/arm/neon-vget_lanes64.c: New. | ||
| 90 | * gcc.target/arm/neon-vget_laneu64.c: New. | ||
| 91 | * gcc.target/arm/neon-vset_lanes64.c: New. | ||
| 92 | * gcc.target/arm/neon-vset_laneu64.c: New. | ||
| 93 | |||
| 94 | 2010-07-02 Sandra Loosemore <sandra@codesourcery.com> | ||
| 95 | Julian Brown <julian@codesourcery.com> | ||
| 96 | |||
| 97 | gcc/ | ||
| 98 | * config/arm/neon.md (UNSPEC_VABA): Delete. | ||
| 99 | (UNSPEC_VABAL): Delete. | ||
| 100 | (UNSPEC_VABS): Delete. | ||
| 101 | (UNSPEC_VMUL_N): Delete. | ||
| 102 | (adddi3_neon): New. | ||
| 103 | (subdi3_neon): New. | ||
| 104 | (mul<mode>3add<mode>_neon): Make the pattern named. | ||
| 105 | (mul<mode>3neg<mode>add<mode>_neon): Likewise. | ||
| 106 | (neon_vadd<mode>): Replace with define_expand, and move the remaining | ||
| 107 | unspec parts... | ||
| 108 | (neon_vadd<mode>_unspec): ...to this. | ||
| 109 | (neon_vmla<mode>, neon_vmla<mode>_unspec): Likewise. | ||
| 110 | (neon_vlms<mode>, neon_vmls<mode>_unspec): Likewise. | ||
| 111 | (neon_vsub<mode>, neon_vsub<mode>_unspec): Likewise. | ||
| 112 | (neon_vaba<mode>): Rewrite in terms of vabd. | ||
| 113 | (neon_vabal<mode>): Rewrite in terms of vabdl. | ||
| 114 | (neon_vabs<mode>): Rewrite without unspec. | ||
| 115 | * config/arm/arm.md (*arm_adddi3): Disable for TARGET_NEON. | ||
| 116 | (*arm_subdi3): Likewise. | ||
| 117 | * config/arm/neon.ml (Vadd, Vsub): Split out 64-bit variants and add | ||
| 118 | No_op attribute to disable assembly output checks. | ||
| 119 | * config/arm/arm_neon.h: Regenerated. | ||
| 120 | * doc/arm-neon-intrinsics.texi: Regenerated. | ||
| 121 | |||
| 122 | gcc/testsuite/ | ||
| 123 | * gcc.target/arm/neon/vadds64.c: Regenerated. | ||
| 124 | * gcc.target/arm/neon/vaddu64.c: Regenerated. | ||
| 125 | * gcc.target/arm/neon/vsubs64.c: Regenerated. | ||
| 126 | * gcc.target/arm/neon/vsubu64.c: Regenerated. | ||
| 127 | * gcc.target/arm/neon-vmla-1.c: Add -ffast-math to options. | ||
| 128 | * gcc.target/arm/neon-vmls-1.c: Likewise. | ||
| 129 | * gcc.target/arm/neon-vsubs64.c: New execution test. | ||
| 130 | * gcc.target/arm/neon-vsubu64.c: New execution test. | ||
| 131 | * gcc.target/arm/neon-vadds64.c: New execution test. | ||
| 132 | * gcc.target/arm/neon-vaddu64.c: New execution test. | ||
| 133 | |||
| 134 | === modified file 'gcc/config/arm/arm.c' | ||
| 135 | --- old/gcc/config/arm/arm.c 2010-07-29 15:53:39 +0000 | ||
| 136 | +++ new/gcc/config/arm/arm.c 2010-07-29 15:59:12 +0000 | ||
| 137 | @@ -8110,8 +8110,7 @@ | ||
| 138 | load. */ | ||
| 139 | |||
| 140 | x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0)); | ||
| 141 | - return gen_rtx_UNSPEC (mode, gen_rtvec (1, x), | ||
| 142 | - UNSPEC_VDUP_N); | ||
| 143 | + return gen_rtx_VEC_DUPLICATE (mode, x); | ||
| 144 | } | ||
| 145 | |||
| 146 | /* Generate code to load VALS, which is a PARALLEL containing only | ||
| 147 | @@ -8207,8 +8206,7 @@ | ||
| 148 | { | ||
| 149 | x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0)); | ||
| 150 | emit_insn (gen_rtx_SET (VOIDmode, target, | ||
| 151 | - gen_rtx_UNSPEC (mode, gen_rtvec (1, x), | ||
| 152 | - UNSPEC_VDUP_N))); | ||
| 153 | + gen_rtx_VEC_DUPLICATE (mode, x))); | ||
| 154 | return; | ||
| 155 | } | ||
| 156 | |||
| 157 | @@ -8217,7 +8215,7 @@ | ||
| 158 | if (n_var == 1) | ||
| 159 | { | ||
| 160 | rtx copy = copy_rtx (vals); | ||
| 161 | - rtvec ops; | ||
| 162 | + rtx index = GEN_INT (one_var); | ||
| 163 | |||
| 164 | /* Load constant part of vector, substitute neighboring value for | ||
| 165 | varying element. */ | ||
| 166 | @@ -8226,9 +8224,38 @@ | ||
| 167 | |||
| 168 | /* Insert variable. */ | ||
| 169 | x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var)); | ||
| 170 | - ops = gen_rtvec (3, x, target, GEN_INT (one_var)); | ||
| 171 | - emit_insn (gen_rtx_SET (VOIDmode, target, | ||
| 172 | - gen_rtx_UNSPEC (mode, ops, UNSPEC_VSET_LANE))); | ||
| 173 | + switch (mode) | ||
| 174 | + { | ||
| 175 | + case V8QImode: | ||
| 176 | + emit_insn (gen_neon_vset_lanev8qi (target, x, target, index)); | ||
| 177 | + break; | ||
| 178 | + case V16QImode: | ||
| 179 | + emit_insn (gen_neon_vset_lanev16qi (target, x, target, index)); | ||
| 180 | + break; | ||
| 181 | + case V4HImode: | ||
| 182 | + emit_insn (gen_neon_vset_lanev4hi (target, x, target, index)); | ||
| 183 | + break; | ||
| 184 | + case V8HImode: | ||
| 185 | + emit_insn (gen_neon_vset_lanev8hi (target, x, target, index)); | ||
| 186 | + break; | ||
| 187 | + case V2SImode: | ||
| 188 | + emit_insn (gen_neon_vset_lanev2si (target, x, target, index)); | ||
| 189 | + break; | ||
| 190 | + case V4SImode: | ||
| 191 | + emit_insn (gen_neon_vset_lanev4si (target, x, target, index)); | ||
| 192 | + break; | ||
| 193 | + case V2SFmode: | ||
| 194 | + emit_insn (gen_neon_vset_lanev2sf (target, x, target, index)); | ||
| 195 | + break; | ||
| 196 | + case V4SFmode: | ||
| 197 | + emit_insn (gen_neon_vset_lanev4sf (target, x, target, index)); | ||
| 198 | + break; | ||
| 199 | + case V2DImode: | ||
| 200 | + emit_insn (gen_neon_vset_lanev2di (target, x, target, index)); | ||
| 201 | + break; | ||
| 202 | + default: | ||
| 203 | + gcc_unreachable (); | ||
| 204 | + } | ||
| 205 | return; | ||
| 206 | } | ||
| 207 | |||
| 208 | |||
| 209 | === modified file 'gcc/config/arm/arm.md' | ||
| 210 | --- old/gcc/config/arm/arm.md 2010-04-02 18:54:46 +0000 | ||
| 211 | +++ new/gcc/config/arm/arm.md 2010-07-29 15:59:12 +0000 | ||
| 212 | @@ -497,9 +497,10 @@ | ||
| 213 | (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") | ||
| 214 | (match_operand:DI 2 "s_register_operand" "r, 0"))) | ||
| 215 | (clobber (reg:CC CC_REGNUM))] | ||
| 216 | - "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" | ||
| 217 | + "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && !TARGET_NEON" | ||
| 218 | "#" | ||
| 219 | - "TARGET_32BIT && reload_completed" | ||
| 220 | + "TARGET_32BIT && reload_completed | ||
| 221 | + && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))" | ||
| 222 | [(parallel [(set (reg:CC_C CC_REGNUM) | ||
| 223 | (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) | ||
| 224 | (match_dup 1))) | ||
| 225 | @@ -997,7 +998,7 @@ | ||
| 226 | (minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0") | ||
| 227 | (match_operand:DI 2 "s_register_operand" "r,0,0"))) | ||
| 228 | (clobber (reg:CC CC_REGNUM))] | ||
| 229 | - "TARGET_32BIT" | ||
| 230 | + "TARGET_32BIT && !TARGET_NEON" | ||
| 231 | "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2" | ||
| 232 | [(set_attr "conds" "clob") | ||
| 233 | (set_attr "length" "8")] | ||
| 234 | @@ -1784,6 +1785,7 @@ | ||
| 235 | [(match_operand:DI 1 "s_register_operand" "") | ||
| 236 | (match_operand:DI 2 "s_register_operand" "")]))] | ||
| 237 | "TARGET_32BIT && reload_completed | ||
| 238 | + && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0]))) | ||
| 239 | && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" | ||
| 240 | [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)])) | ||
| 241 | (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))] | ||
| 242 | @@ -1857,11 +1859,19 @@ | ||
| 243 | }" | ||
| 244 | ) | ||
| 245 | |||
| 246 | -(define_insn "anddi3" | ||
| 247 | +(define_expand "anddi3" | ||
| 248 | + [(set (match_operand:DI 0 "s_register_operand" "") | ||
| 249 | + (and:DI (match_operand:DI 1 "s_register_operand" "") | ||
| 250 | + (match_operand:DI 2 "neon_inv_logic_op2" "")))] | ||
| 251 | + "TARGET_32BIT" | ||
| 252 | + "" | ||
| 253 | +) | ||
| 254 | + | ||
| 255 | +(define_insn "*anddi3_insn" | ||
| 256 | [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") | ||
| 257 | (and:DI (match_operand:DI 1 "s_register_operand" "%0,r") | ||
| 258 | (match_operand:DI 2 "s_register_operand" "r,r")))] | ||
| 259 | - "TARGET_32BIT && ! TARGET_IWMMXT" | ||
| 260 | + "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" | ||
| 261 | "#" | ||
| 262 | [(set_attr "length" "8")] | ||
| 263 | ) | ||
| 264 | @@ -2461,7 +2471,9 @@ | ||
| 265 | (match_operand:DI 2 "s_register_operand" "r,0")))] | ||
| 266 | "TARGET_32BIT" | ||
| 267 | "#" | ||
| 268 | - "TARGET_32BIT && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" | ||
| 269 | + "TARGET_32BIT && reload_completed | ||
| 270 | + && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0]))) | ||
| 271 | + && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" | ||
| 272 | [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2))) | ||
| 273 | (set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))] | ||
| 274 | " | ||
| 275 | @@ -2585,11 +2597,19 @@ | ||
| 276 | [(set_attr "conds" "set")] | ||
| 277 | ) | ||
| 278 | |||
| 279 | -(define_insn "iordi3" | ||
| 280 | +(define_expand "iordi3" | ||
| 281 | + [(set (match_operand:DI 0 "s_register_operand" "") | ||
| 282 | + (ior:DI (match_operand:DI 1 "s_register_operand" "") | ||
| 283 | + (match_operand:DI 2 "neon_logic_op2" "")))] | ||
| 284 | + "TARGET_32BIT" | ||
| 285 | + "" | ||
| 286 | +) | ||
| 287 | + | ||
| 288 | +(define_insn "*iordi3_insn" | ||
| 289 | [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") | ||
| 290 | (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r") | ||
| 291 | (match_operand:DI 2 "s_register_operand" "r,r")))] | ||
| 292 | - "TARGET_32BIT && ! TARGET_IWMMXT" | ||
| 293 | + "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" | ||
| 294 | "#" | ||
| 295 | [(set_attr "length" "8") | ||
| 296 | (set_attr "predicable" "yes")] | ||
| 297 | @@ -2715,11 +2735,19 @@ | ||
| 298 | [(set_attr "conds" "set")] | ||
| 299 | ) | ||
| 300 | |||
| 301 | -(define_insn "xordi3" | ||
| 302 | +(define_expand "xordi3" | ||
| 303 | + [(set (match_operand:DI 0 "s_register_operand" "") | ||
| 304 | + (xor:DI (match_operand:DI 1 "s_register_operand" "") | ||
| 305 | + (match_operand:DI 2 "s_register_operand" "")))] | ||
| 306 | + "TARGET_32BIT" | ||
| 307 | + "" | ||
| 308 | +) | ||
| 309 | + | ||
| 310 | +(define_insn "*xordi3_insn" | ||
| 311 | [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") | ||
| 312 | (xor:DI (match_operand:DI 1 "s_register_operand" "%0,r") | ||
| 313 | (match_operand:DI 2 "s_register_operand" "r,r")))] | ||
| 314 | - "TARGET_32BIT && !TARGET_IWMMXT" | ||
| 315 | + "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON" | ||
| 316 | "#" | ||
| 317 | [(set_attr "length" "8") | ||
| 318 | (set_attr "predicable" "yes")] | ||
| 319 | |||
| 320 | === modified file 'gcc/config/arm/arm_neon.h' | ||
| 321 | --- old/gcc/config/arm/arm_neon.h 2009-11-03 17:58:59 +0000 | ||
| 322 | +++ new/gcc/config/arm/arm_neon.h 2010-07-29 15:59:12 +0000 | ||
| 323 | @@ -414,12 +414,6 @@ | ||
| 324 | return (int32x2_t)__builtin_neon_vaddv2si (__a, __b, 1); | ||
| 325 | } | ||
| 326 | |||
| 327 | -__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 328 | -vadd_s64 (int64x1_t __a, int64x1_t __b) | ||
| 329 | -{ | ||
| 330 | - return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1); | ||
| 331 | -} | ||
| 332 | - | ||
| 333 | __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) | ||
| 334 | vadd_f32 (float32x2_t __a, float32x2_t __b) | ||
| 335 | { | ||
| 336 | @@ -444,6 +438,12 @@ | ||
| 337 | return (uint32x2_t)__builtin_neon_vaddv2si ((int32x2_t) __a, (int32x2_t) __b, 0); | ||
| 338 | } | ||
| 339 | |||
| 340 | +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 341 | +vadd_s64 (int64x1_t __a, int64x1_t __b) | ||
| 342 | +{ | ||
| 343 | + return (int64x1_t)__builtin_neon_vadddi (__a, __b, 1); | ||
| 344 | +} | ||
| 345 | + | ||
| 346 | __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) | ||
| 347 | vadd_u64 (uint64x1_t __a, uint64x1_t __b) | ||
| 348 | { | ||
| 349 | @@ -1368,12 +1368,6 @@ | ||
| 350 | return (int32x2_t)__builtin_neon_vsubv2si (__a, __b, 1); | ||
| 351 | } | ||
| 352 | |||
| 353 | -__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 354 | -vsub_s64 (int64x1_t __a, int64x1_t __b) | ||
| 355 | -{ | ||
| 356 | - return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1); | ||
| 357 | -} | ||
| 358 | - | ||
| 359 | __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) | ||
| 360 | vsub_f32 (float32x2_t __a, float32x2_t __b) | ||
| 361 | { | ||
| 362 | @@ -1398,6 +1392,12 @@ | ||
| 363 | return (uint32x2_t)__builtin_neon_vsubv2si ((int32x2_t) __a, (int32x2_t) __b, 0); | ||
| 364 | } | ||
| 365 | |||
| 366 | +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 367 | +vsub_s64 (int64x1_t __a, int64x1_t __b) | ||
| 368 | +{ | ||
| 369 | + return (int64x1_t)__builtin_neon_vsubdi (__a, __b, 1); | ||
| 370 | +} | ||
| 371 | + | ||
| 372 | __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) | ||
| 373 | vsub_u64 (uint64x1_t __a, uint64x1_t __b) | ||
| 374 | { | ||
| 375 | @@ -5808,12 +5808,6 @@ | ||
| 376 | return (int32x2_t)__builtin_neon_vget_lowv4si (__a); | ||
| 377 | } | ||
| 378 | |||
| 379 | -__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 380 | -vget_low_s64 (int64x2_t __a) | ||
| 381 | -{ | ||
| 382 | - return (int64x1_t)__builtin_neon_vget_lowv2di (__a); | ||
| 383 | -} | ||
| 384 | - | ||
| 385 | __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) | ||
| 386 | vget_low_f32 (float32x4_t __a) | ||
| 387 | { | ||
| 388 | @@ -5838,12 +5832,6 @@ | ||
| 389 | return (uint32x2_t)__builtin_neon_vget_lowv4si ((int32x4_t) __a); | ||
| 390 | } | ||
| 391 | |||
| 392 | -__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) | ||
| 393 | -vget_low_u64 (uint64x2_t __a) | ||
| 394 | -{ | ||
| 395 | - return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a); | ||
| 396 | -} | ||
| 397 | - | ||
| 398 | __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) | ||
| 399 | vget_low_p8 (poly8x16_t __a) | ||
| 400 | { | ||
| 401 | @@ -5856,6 +5844,18 @@ | ||
| 402 | return (poly16x4_t)__builtin_neon_vget_lowv8hi ((int16x8_t) __a); | ||
| 403 | } | ||
| 404 | |||
| 405 | +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 406 | +vget_low_s64 (int64x2_t __a) | ||
| 407 | +{ | ||
| 408 | + return (int64x1_t)__builtin_neon_vget_lowv2di (__a); | ||
| 409 | +} | ||
| 410 | + | ||
| 411 | +__extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) | ||
| 412 | +vget_low_u64 (uint64x2_t __a) | ||
| 413 | +{ | ||
| 414 | + return (uint64x1_t)__builtin_neon_vget_lowv2di ((int64x2_t) __a); | ||
| 415 | +} | ||
| 416 | + | ||
| 417 | __extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) | ||
| 418 | vcvt_s32_f32 (float32x2_t __a) | ||
| 419 | { | ||
| 420 | @@ -10386,12 +10386,6 @@ | ||
| 421 | return (int32x2_t)__builtin_neon_vandv2si (__a, __b, 1); | ||
| 422 | } | ||
| 423 | |||
| 424 | -__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 425 | -vand_s64 (int64x1_t __a, int64x1_t __b) | ||
| 426 | -{ | ||
| 427 | - return (int64x1_t)__builtin_neon_vanddi (__a, __b, 1); | ||
| 428 | -} | ||
| 429 | - | ||
| 430 | __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) | ||
| 431 | vand_u8 (uint8x8_t __a, uint8x8_t __b) | ||
| 432 | { | ||
| 433 | @@ -10410,6 +10404,12 @@ | ||
| 434 | return (uint32x2_t)__builtin_neon_vandv2si ((int32x2_t) __a, (int32x2_t) __b, 0); | ||
| 435 | } | ||
| 436 | |||
| 437 | +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 438 | +vand_s64 (int64x1_t __a, int64x1_t __b) | ||
| 439 | +{ | ||
| 440 | + return (int64x1_t)__builtin_neon_vanddi (__a, __b, 1); | ||
| 441 | +} | ||
| 442 | + | ||
| 443 | __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) | ||
| 444 | vand_u64 (uint64x1_t __a, uint64x1_t __b) | ||
| 445 | { | ||
| 446 | @@ -10482,12 +10482,6 @@ | ||
| 447 | return (int32x2_t)__builtin_neon_vorrv2si (__a, __b, 1); | ||
| 448 | } | ||
| 449 | |||
| 450 | -__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 451 | -vorr_s64 (int64x1_t __a, int64x1_t __b) | ||
| 452 | -{ | ||
| 453 | - return (int64x1_t)__builtin_neon_vorrdi (__a, __b, 1); | ||
| 454 | -} | ||
| 455 | - | ||
| 456 | __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) | ||
| 457 | vorr_u8 (uint8x8_t __a, uint8x8_t __b) | ||
| 458 | { | ||
| 459 | @@ -10506,6 +10500,12 @@ | ||
| 460 | return (uint32x2_t)__builtin_neon_vorrv2si ((int32x2_t) __a, (int32x2_t) __b, 0); | ||
| 461 | } | ||
| 462 | |||
| 463 | +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 464 | +vorr_s64 (int64x1_t __a, int64x1_t __b) | ||
| 465 | +{ | ||
| 466 | + return (int64x1_t)__builtin_neon_vorrdi (__a, __b, 1); | ||
| 467 | +} | ||
| 468 | + | ||
| 469 | __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) | ||
| 470 | vorr_u64 (uint64x1_t __a, uint64x1_t __b) | ||
| 471 | { | ||
| 472 | @@ -10578,12 +10578,6 @@ | ||
| 473 | return (int32x2_t)__builtin_neon_veorv2si (__a, __b, 1); | ||
| 474 | } | ||
| 475 | |||
| 476 | -__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 477 | -veor_s64 (int64x1_t __a, int64x1_t __b) | ||
| 478 | -{ | ||
| 479 | - return (int64x1_t)__builtin_neon_veordi (__a, __b, 1); | ||
| 480 | -} | ||
| 481 | - | ||
| 482 | __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) | ||
| 483 | veor_u8 (uint8x8_t __a, uint8x8_t __b) | ||
| 484 | { | ||
| 485 | @@ -10602,6 +10596,12 @@ | ||
| 486 | return (uint32x2_t)__builtin_neon_veorv2si ((int32x2_t) __a, (int32x2_t) __b, 0); | ||
| 487 | } | ||
| 488 | |||
| 489 | +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 490 | +veor_s64 (int64x1_t __a, int64x1_t __b) | ||
| 491 | +{ | ||
| 492 | + return (int64x1_t)__builtin_neon_veordi (__a, __b, 1); | ||
| 493 | +} | ||
| 494 | + | ||
| 495 | __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) | ||
| 496 | veor_u64 (uint64x1_t __a, uint64x1_t __b) | ||
| 497 | { | ||
| 498 | @@ -10674,12 +10674,6 @@ | ||
| 499 | return (int32x2_t)__builtin_neon_vbicv2si (__a, __b, 1); | ||
| 500 | } | ||
| 501 | |||
| 502 | -__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 503 | -vbic_s64 (int64x1_t __a, int64x1_t __b) | ||
| 504 | -{ | ||
| 505 | - return (int64x1_t)__builtin_neon_vbicdi (__a, __b, 1); | ||
| 506 | -} | ||
| 507 | - | ||
| 508 | __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) | ||
| 509 | vbic_u8 (uint8x8_t __a, uint8x8_t __b) | ||
| 510 | { | ||
| 511 | @@ -10698,6 +10692,12 @@ | ||
| 512 | return (uint32x2_t)__builtin_neon_vbicv2si ((int32x2_t) __a, (int32x2_t) __b, 0); | ||
| 513 | } | ||
| 514 | |||
| 515 | +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 516 | +vbic_s64 (int64x1_t __a, int64x1_t __b) | ||
| 517 | +{ | ||
| 518 | + return (int64x1_t)__builtin_neon_vbicdi (__a, __b, 1); | ||
| 519 | +} | ||
| 520 | + | ||
| 521 | __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) | ||
| 522 | vbic_u64 (uint64x1_t __a, uint64x1_t __b) | ||
| 523 | { | ||
| 524 | @@ -10770,12 +10770,6 @@ | ||
| 525 | return (int32x2_t)__builtin_neon_vornv2si (__a, __b, 1); | ||
| 526 | } | ||
| 527 | |||
| 528 | -__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 529 | -vorn_s64 (int64x1_t __a, int64x1_t __b) | ||
| 530 | -{ | ||
| 531 | - return (int64x1_t)__builtin_neon_vorndi (__a, __b, 1); | ||
| 532 | -} | ||
| 533 | - | ||
| 534 | __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__)) | ||
| 535 | vorn_u8 (uint8x8_t __a, uint8x8_t __b) | ||
| 536 | { | ||
| 537 | @@ -10794,6 +10788,12 @@ | ||
| 538 | return (uint32x2_t)__builtin_neon_vornv2si ((int32x2_t) __a, (int32x2_t) __b, 0); | ||
| 539 | } | ||
| 540 | |||
| 541 | +__extension__ static __inline int64x1_t __attribute__ ((__always_inline__)) | ||
| 542 | +vorn_s64 (int64x1_t __a, int64x1_t __b) | ||
| 543 | +{ | ||
| 544 | + return (int64x1_t)__builtin_neon_vorndi (__a, __b, 1); | ||
| 545 | +} | ||
| 546 | + | ||
| 547 | __extension__ static __inline uint64x1_t __attribute__ ((__always_inline__)) | ||
| 548 | vorn_u64 (uint64x1_t __a, uint64x1_t __b) | ||
| 549 | { | ||
| 550 | |||
| 551 | === modified file 'gcc/config/arm/neon.md' | ||
| 552 | --- old/gcc/config/arm/neon.md 2009-11-11 14:23:03 +0000 | ||
| 553 | +++ new/gcc/config/arm/neon.md 2010-07-29 15:59:12 +0000 | ||
| 554 | @@ -22,17 +22,12 @@ | ||
| 555 | (define_constants | ||
| 556 | [(UNSPEC_ASHIFT_SIGNED 65) | ||
| 557 | (UNSPEC_ASHIFT_UNSIGNED 66) | ||
| 558 | - (UNSPEC_VABA 67) | ||
| 559 | - (UNSPEC_VABAL 68) | ||
| 560 | (UNSPEC_VABD 69) | ||
| 561 | (UNSPEC_VABDL 70) | ||
| 562 | - (UNSPEC_VABS 71) | ||
| 563 | (UNSPEC_VADD 72) | ||
| 564 | (UNSPEC_VADDHN 73) | ||
| 565 | (UNSPEC_VADDL 74) | ||
| 566 | (UNSPEC_VADDW 75) | ||
| 567 | - (UNSPEC_VAND 76) | ||
| 568 | - (UNSPEC_VBIC 77) | ||
| 569 | (UNSPEC_VBSL 78) | ||
| 570 | (UNSPEC_VCAGE 79) | ||
| 571 | (UNSPEC_VCAGT 80) | ||
| 572 | @@ -40,18 +35,9 @@ | ||
| 573 | (UNSPEC_VCGE 82) | ||
| 574 | (UNSPEC_VCGT 83) | ||
| 575 | (UNSPEC_VCLS 84) | ||
| 576 | - (UNSPEC_VCLZ 85) | ||
| 577 | - (UNSPEC_VCNT 86) | ||
| 578 | - (UNSPEC_VCOMBINE 87) | ||
| 579 | (UNSPEC_VCVT 88) | ||
| 580 | (UNSPEC_VCVT_N 89) | ||
| 581 | - (UNSPEC_VDUP_LANE 90) | ||
| 582 | - (UNSPEC_VDUP_N 91) | ||
| 583 | - (UNSPEC_VEOR 92) | ||
| 584 | (UNSPEC_VEXT 93) | ||
| 585 | - (UNSPEC_VGET_HIGH 94) | ||
| 586 | - (UNSPEC_VGET_LANE 95) | ||
| 587 | - (UNSPEC_VGET_LOW 96) | ||
| 588 | (UNSPEC_VHADD 97) | ||
| 589 | (UNSPEC_VHSUB 98) | ||
| 590 | (UNSPEC_VLD1 99) | ||
| 591 | @@ -86,10 +72,6 @@ | ||
| 592 | (UNSPEC_VMULL 128) | ||
| 593 | (UNSPEC_VMUL_LANE 129) | ||
| 594 | (UNSPEC_VMULL_LANE 130) | ||
| 595 | - (UNSPEC_VMUL_N 131) | ||
| 596 | - (UNSPEC_VMVN 132) | ||
| 597 | - (UNSPEC_VORN 133) | ||
| 598 | - (UNSPEC_VORR 134) | ||
| 599 | (UNSPEC_VPADAL 135) | ||
| 600 | (UNSPEC_VPADD 136) | ||
| 601 | (UNSPEC_VPADDL 137) | ||
| 602 | @@ -125,7 +107,6 @@ | ||
| 603 | (UNSPEC_VREV64 167) | ||
| 604 | (UNSPEC_VRSQRTE 168) | ||
| 605 | (UNSPEC_VRSQRTS 169) | ||
| 606 | - (UNSPEC_VSET_LANE 170) | ||
| 607 | (UNSPEC_VSHL 171) | ||
| 608 | (UNSPEC_VSHLL_N 172) | ||
| 609 | (UNSPEC_VSHL_N 173) | ||
| 610 | @@ -335,6 +316,14 @@ | ||
| 611 | (V4HI "V2SI") (V8HI "V4SI") | ||
| 612 | (V2SI "DI") (V4SI "V2DI")]) | ||
| 613 | |||
| 614 | +;; Double-sized modes with the same element size. | ||
| 615 | +;; Used for neon_vdup_lane, where the second operand is double-sized | ||
| 616 | +;; even when the first one is quad. | ||
| 617 | +(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") | ||
| 618 | + (V4SI "V2SI") (V4SF "V2SF") | ||
| 619 | + (V8QI "V8QI") (V4HI "V4HI") | ||
| 620 | + (V2SI "V2SI") (V2SF "V2SF")]) | ||
| 621 | + | ||
| 622 | ;; Mode of result of comparison operations (and bit-select operand 1). | ||
| 623 | (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") | ||
| 624 | (V4HI "V4HI") (V8HI "V8HI") | ||
| 625 | @@ -688,7 +677,7 @@ | ||
| 626 | elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; | ||
| 627 | operands[2] = GEN_INT (elt); | ||
| 628 | |||
| 629 | - return "vmov%?.<V_uf_sclr>\t%P0[%c2], %1"; | ||
| 630 | + return "vmov%?.<V_sz_elem>\t%P0[%c2], %1"; | ||
| 631 | } | ||
| 632 | [(set_attr "predicable" "yes") | ||
| 633 | (set_attr "neon_type" "neon_mcr")]) | ||
| 634 | @@ -714,7 +703,7 @@ | ||
| 635 | operands[0] = gen_rtx_REG (<V_HALF>mode, regno + hi); | ||
| 636 | operands[2] = GEN_INT (elt); | ||
| 637 | |||
| 638 | - return "vmov%?.<V_uf_sclr>\t%P0[%c2], %1"; | ||
| 639 | + return "vmov%?.<V_sz_elem>\t%P0[%c2], %1"; | ||
| 640 | } | ||
| 641 | [(set_attr "predicable" "yes") | ||
| 642 | (set_attr "neon_type" "neon_mcr")] | ||
| 643 | @@ -734,7 +723,7 @@ | ||
| 644 | |||
| 645 | operands[0] = gen_rtx_REG (DImode, regno); | ||
| 646 | |||
| 647 | - return "vmov%?.64\t%P0, %Q1, %R1"; | ||
| 648 | + return "vmov%?\t%P0, %Q1, %R1"; | ||
| 649 | } | ||
| 650 | [(set_attr "predicable" "yes") | ||
| 651 | (set_attr "neon_type" "neon_mcr_2_mcrr")] | ||
| 652 | @@ -802,11 +791,11 @@ | ||
| 653 | (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] | ||
| 654 | "TARGET_NEON" | ||
| 655 | { | ||
| 656 | - int regno = REGNO (operands[1]) + INTVAL (operands[2]); | ||
| 657 | + int regno = REGNO (operands[1]) + 2 * INTVAL (operands[2]); | ||
| 658 | |||
| 659 | operands[1] = gen_rtx_REG (DImode, regno); | ||
| 660 | |||
| 661 | - return "vmov%?.64\t%Q0, %R0, %P1"; | ||
| 662 | + return "vmov%?\t%Q0, %R0, %P1 @ v2di"; | ||
| 663 | } | ||
| 664 | [(set_attr "predicable" "yes") | ||
| 665 | (set_attr "neon_type" "neon_int_1")] | ||
| 666 | @@ -823,11 +812,8 @@ | ||
| 667 | |||
| 668 | ;; Doubleword and quadword arithmetic. | ||
| 669 | |||
| 670 | -;; NOTE: vadd/vsub and some other instructions also support 64-bit integer | ||
| 671 | -;; element size, which we could potentially use for "long long" operations. We | ||
| 672 | -;; don't want to do this at present though, because moving values from the | ||
| 673 | -;; vector unit to the ARM core is currently slow and 64-bit addition (etc.) is | ||
| 674 | -;; easy to do with ARM instructions anyway. | ||
| 675 | +;; NOTE: some other instructions also support 64-bit integer | ||
| 676 | +;; element size, which we could potentially use for "long long" operations. | ||
| 677 | |||
| 678 | (define_insn "*add<mode>3_neon" | ||
| 679 | [(set (match_operand:VDQ 0 "s_register_operand" "=w") | ||
| 680 | @@ -843,6 +829,26 @@ | ||
| 681 | (const_string "neon_int_1")))] | ||
| 682 | ) | ||
| 683 | |||
| 684 | +(define_insn "adddi3_neon" | ||
| 685 | + [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r") | ||
| 686 | + (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0") | ||
| 687 | + (match_operand:DI 2 "s_register_operand" "w,r,0"))) | ||
| 688 | + (clobber (reg:CC CC_REGNUM))] | ||
| 689 | + "TARGET_NEON" | ||
| 690 | +{ | ||
| 691 | + switch (which_alternative) | ||
| 692 | + { | ||
| 693 | + case 0: return "vadd.i64\t%P0, %P1, %P2"; | ||
| 694 | + case 1: return "#"; | ||
| 695 | + case 2: return "#"; | ||
| 696 | + default: gcc_unreachable (); | ||
| 697 | + } | ||
| 698 | +} | ||
| 699 | + [(set_attr "neon_type" "neon_int_1,*,*") | ||
| 700 | + (set_attr "conds" "*,clob,clob") | ||
| 701 | + (set_attr "length" "*,8,8")] | ||
| 702 | +) | ||
| 703 | + | ||
| 704 | (define_insn "*sub<mode>3_neon" | ||
| 705 | [(set (match_operand:VDQ 0 "s_register_operand" "=w") | ||
| 706 | (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w") | ||
| 707 | @@ -857,6 +863,27 @@ | ||
| 708 | (const_string "neon_int_2")))] | ||
| 709 | ) | ||
| 710 | |||
| 711 | +(define_insn "subdi3_neon" | ||
| 712 | + [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r") | ||
| 713 | + (minus:DI (match_operand:DI 1 "s_register_operand" "w,0,r,0") | ||
| 714 | + (match_operand:DI 2 "s_register_operand" "w,r,0,0"))) | ||
| 715 | + (clobber (reg:CC CC_REGNUM))] | ||
| 716 | + "TARGET_NEON" | ||
| 717 | +{ | ||
| 718 | + switch (which_alternative) | ||
| 719 | + { | ||
| 720 | + case 0: return "vsub.i64\t%P0, %P1, %P2"; | ||
| 721 | + case 1: /* fall through */ | ||
| 722 | + case 2: /* fall through */ | ||
| 723 | + case 3: return "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"; | ||
| 724 | + default: gcc_unreachable (); | ||
| 725 | + } | ||
| 726 | +} | ||
| 727 | + [(set_attr "neon_type" "neon_int_2,*,*,*") | ||
| 728 | + (set_attr "conds" "*,clob,clob,clob") | ||
| 729 | + (set_attr "length" "*,8,8,8")] | ||
| 730 | +) | ||
| 731 | + | ||
| 732 | (define_insn "*mul<mode>3_neon" | ||
| 733 | [(set (match_operand:VDQ 0 "s_register_operand" "=w") | ||
| 734 | (mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w") | ||
| 735 | @@ -878,7 +905,7 @@ | ||
| 736 | (const_string "neon_mul_qqq_8_16_32_ddd_32")))))] | ||
| 737 | ) | ||
| 738 | |||
| 739 | -(define_insn "*mul<mode>3add<mode>_neon" | ||
| 740 | +(define_insn "mul<mode>3add<mode>_neon" | ||
| 741 | [(set (match_operand:VDQ 0 "s_register_operand" "=w") | ||
| 742 | (plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w") | ||
| 743 | (match_operand:VDQ 3 "s_register_operand" "w")) | ||
| 744 | @@ -900,7 +927,7 @@ | ||
| 745 | (const_string "neon_mla_qqq_32_qqd_32_scalar")))))] | ||
| 746 | ) | ||
| 747 | |||
| 748 | -(define_insn "*mul<mode>3neg<mode>add<mode>_neon" | ||
| 749 | +(define_insn "mul<mode>3neg<mode>add<mode>_neon" | ||
| 750 | [(set (match_operand:VDQ 0 "s_register_operand" "=w") | ||
| 751 | (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0") | ||
| 752 | (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w") | ||
| 753 | @@ -940,10 +967,9 @@ | ||
| 754 | ) | ||
| 755 | |||
| 756 | (define_insn "iordi3_neon" | ||
| 757 | - [(set (match_operand:DI 0 "s_register_operand" "=w,w") | ||
| 758 | - (unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0") | ||
| 759 | - (match_operand:DI 2 "neon_logic_op2" "w,Dl")] | ||
| 760 | - UNSPEC_VORR))] | ||
| 761 | + [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r") | ||
| 762 | + (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r") | ||
| 763 | + (match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r")))] | ||
| 764 | "TARGET_NEON" | ||
| 765 | { | ||
| 766 | switch (which_alternative) | ||
| 767 | @@ -951,10 +977,13 @@ | ||
| 768 | case 0: return "vorr\t%P0, %P1, %P2"; | ||
| 769 | case 1: return neon_output_logic_immediate ("vorr", &operands[2], | ||
| 770 | DImode, 0, VALID_NEON_QREG_MODE (DImode)); | ||
| 771 | + case 2: return "#"; | ||
| 772 | + case 3: return "#"; | ||
| 773 | default: gcc_unreachable (); | ||
| 774 | } | ||
| 775 | } | ||
| 776 | - [(set_attr "neon_type" "neon_int_1")] | ||
| 777 | + [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") | ||
| 778 | + (set_attr "length" "*,*,8,8")] | ||
| 779 | ) | ||
| 780 | |||
| 781 | ;; The concrete forms of the Neon immediate-logic instructions are vbic and | ||
| 782 | @@ -980,10 +1009,9 @@ | ||
| 783 | ) | ||
| 784 | |||
| 785 | (define_insn "anddi3_neon" | ||
| 786 | - [(set (match_operand:DI 0 "s_register_operand" "=w,w") | ||
| 787 | - (unspec:DI [(match_operand:DI 1 "s_register_operand" "w,0") | ||
| 788 | - (match_operand:DI 2 "neon_inv_logic_op2" "w,DL")] | ||
| 789 | - UNSPEC_VAND))] | ||
| 790 | + [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r") | ||
| 791 | + (and:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r") | ||
| 792 | + (match_operand:DI 2 "neon_inv_logic_op2" "w,DL,r,r")))] | ||
| 793 | "TARGET_NEON" | ||
| 794 | { | ||
| 795 | switch (which_alternative) | ||
| 796 | @@ -991,10 +1019,13 @@ | ||
| 797 | case 0: return "vand\t%P0, %P1, %P2"; | ||
| 798 | case 1: return neon_output_logic_immediate ("vand", &operands[2], | ||
| 799 | DImode, 1, VALID_NEON_QREG_MODE (DImode)); | ||
| 800 | + case 2: return "#"; | ||
| 801 | + case 3: return "#"; | ||
| 802 | default: gcc_unreachable (); | ||
| 803 | } | ||
| 804 | } | ||
| 805 | - [(set_attr "neon_type" "neon_int_1")] | ||
| 806 | + [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") | ||
| 807 | + (set_attr "length" "*,*,8,8")] | ||
| 808 | ) | ||
| 809 | |||
| 810 | (define_insn "orn<mode>3_neon" | ||
| 811 | @@ -1007,13 +1038,16 @@ | ||
| 812 | ) | ||
| 813 | |||
| 814 | (define_insn "orndi3_neon" | ||
| 815 | - [(set (match_operand:DI 0 "s_register_operand" "=w") | ||
| 816 | - (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") | ||
| 817 | - (match_operand:DI 2 "s_register_operand" "w")] | ||
| 818 | - UNSPEC_VORN))] | ||
| 819 | + [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r") | ||
| 820 | + (ior:DI (match_operand:DI 1 "s_register_operand" "w,r,0") | ||
| 821 | + (not:DI (match_operand:DI 2 "s_register_operand" "w,0,r"))))] | ||
| 822 | "TARGET_NEON" | ||
| 823 | - "vorn\t%P0, %P1, %P2" | ||
| 824 | - [(set_attr "neon_type" "neon_int_1")] | ||
| 825 | + "@ | ||
| 826 | + vorn\t%P0, %P1, %P2 | ||
| 827 | + # | ||
| 828 | + #" | ||
| 829 | + [(set_attr "neon_type" "neon_int_1,*,*") | ||
| 830 | + (set_attr "length" "*,8,8")] | ||
| 831 | ) | ||
| 832 | |||
| 833 | (define_insn "bic<mode>3_neon" | ||
| 834 | @@ -1025,14 +1059,18 @@ | ||
| 835 | [(set_attr "neon_type" "neon_int_1")] | ||
| 836 | ) | ||
| 837 | |||
| 838 | +;; Compare to *anddi_notdi_di. | ||
| 839 | (define_insn "bicdi3_neon" | ||
| 840 | - [(set (match_operand:DI 0 "s_register_operand" "=w") | ||
| 841 | - (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") | ||
| 842 | - (match_operand:DI 2 "s_register_operand" "w")] | ||
| 843 | - UNSPEC_VBIC))] | ||
| 844 | + [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r") | ||
| 845 | + (and:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,r,0")) | ||
| 846 | + (match_operand:DI 1 "s_register_operand" "w,0,r")))] | ||
| 847 | "TARGET_NEON" | ||
| 848 | - "vbic\t%P0, %P1, %P2" | ||
| 849 | - [(set_attr "neon_type" "neon_int_1")] | ||
| 850 | + "@ | ||
| 851 | + vbic\t%P0, %P1, %P2 | ||
| 852 | + # | ||
| 853 | + #" | ||
| 854 | + [(set_attr "neon_type" "neon_int_1,*,*") | ||
| 855 | + (set_attr "length" "*,8,8")] | ||
| 856 | ) | ||
| 857 | |||
| 858 | (define_insn "xor<mode>3" | ||
| 859 | @@ -1045,13 +1083,16 @@ | ||
| 860 | ) | ||
| 861 | |||
| 862 | (define_insn "xordi3_neon" | ||
| 863 | - [(set (match_operand:DI 0 "s_register_operand" "=w") | ||
| 864 | - (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") | ||
| 865 | - (match_operand:DI 2 "s_register_operand" "w")] | ||
| 866 | - UNSPEC_VEOR))] | ||
| 867 | + [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r") | ||
| 868 | + (xor:DI (match_operand:DI 1 "s_register_operand" "%w,0,r") | ||
| 869 | + (match_operand:DI 2 "s_register_operand" "w,r,r")))] | ||
| 870 | "TARGET_NEON" | ||
| 871 | - "veor\t%P0, %P1, %P2" | ||
| 872 | - [(set_attr "neon_type" "neon_int_1")] | ||
| 873 | + "@ | ||
| 874 | + veor\t%P0, %P1, %P2 | ||
| 875 | + # | ||
| 876 | + #" | ||
| 877 | + [(set_attr "neon_type" "neon_int_1,*,*") | ||
| 878 | + (set_attr "length" "*,8,8")] | ||
| 879 | ) | ||
| 880 | |||
| 881 | (define_insn "one_cmpl<mode>2" | ||
| 882 | @@ -1711,11 +1752,37 @@ | ||
| 883 | |||
| 884 | ; good for plain vadd, vaddq. | ||
| 885 | |||
| 886 | -(define_insn "neon_vadd<mode>" | ||
| 887 | +(define_expand "neon_vadd<mode>" | ||
| 888 | + [(match_operand:VDQX 0 "s_register_operand" "=w") | ||
| 889 | + (match_operand:VDQX 1 "s_register_operand" "w") | ||
| 890 | + (match_operand:VDQX 2 "s_register_operand" "w") | ||
| 891 | + (match_operand:SI 3 "immediate_operand" "i")] | ||
| 892 | + "TARGET_NEON" | ||
| 893 | +{ | ||
| 894 | + if (!<Is_float_mode> || flag_unsafe_math_optimizations) | ||
| 895 | + emit_insn (gen_add<mode>3 (operands[0], operands[1], operands[2])); | ||
| 896 | + else | ||
| 897 | + emit_insn (gen_neon_vadd<mode>_unspec (operands[0], operands[1], | ||
| 898 | + operands[2])); | ||
| 899 | + DONE; | ||
| 900 | +}) | ||
| 901 | + | ||
| 902 | +; Note that NEON operations don't support the full IEEE 754 standard: in | ||
| 903 | +; particular, denormal values are flushed to zero. This means that GCC cannot | ||
| 904 | +; use those instructions for autovectorization, etc. unless | ||
| 905 | +; -funsafe-math-optimizations is in effect (in which case flush-to-zero | ||
| 906 | +; behaviour is permissible). Intrinsic operations (provided by the arm_neon.h | ||
| 907 | +; header) must work in either case: if -funsafe-math-optimizations is given, | ||
| 908 | +; intrinsics expand to "canonical" RTL where possible, otherwise intrinsics | ||
| 909 | +; expand to unspecs (which may potentially limit the extent to which they might | ||
| 910 | +; be optimized by generic code). | ||
| 911 | + | ||
| 912 | +; Used for intrinsics when flag_unsafe_math_optimizations is false. | ||
| 913 | + | ||
| 914 | +(define_insn "neon_vadd<mode>_unspec" | ||
| 915 | [(set (match_operand:VDQX 0 "s_register_operand" "=w") | ||
| 916 | (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w") | ||
| 917 | - (match_operand:VDQX 2 "s_register_operand" "w") | ||
| 918 | - (match_operand:SI 3 "immediate_operand" "i")] | ||
| 919 | + (match_operand:VDQX 2 "s_register_operand" "w")] | ||
| 920 | UNSPEC_VADD))] | ||
| 921 | "TARGET_NEON" | ||
| 922 | "vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" | ||
| 923 | @@ -1788,6 +1855,8 @@ | ||
| 924 | [(set_attr "neon_type" "neon_int_4")] | ||
| 925 | ) | ||
| 926 | |||
| 927 | +;; We cannot replace this unspec with mul<mode>3 because of the odd | ||
| 928 | +;; polynomial multiplication case that can specified by operand 3. | ||
| 929 | (define_insn "neon_vmul<mode>" | ||
| 930 | [(set (match_operand:VDQW 0 "s_register_operand" "=w") | ||
| 931 | (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w") | ||
| 932 | @@ -1811,13 +1880,31 @@ | ||
| 933 | (const_string "neon_mul_qqq_8_16_32_ddd_32")))))] | ||
| 934 | ) | ||
| 935 | |||
| 936 | -(define_insn "neon_vmla<mode>" | ||
| 937 | - [(set (match_operand:VDQW 0 "s_register_operand" "=w") | ||
| 938 | - (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") | ||
| 939 | - (match_operand:VDQW 2 "s_register_operand" "w") | ||
| 940 | - (match_operand:VDQW 3 "s_register_operand" "w") | ||
| 941 | - (match_operand:SI 4 "immediate_operand" "i")] | ||
| 942 | - UNSPEC_VMLA))] | ||
| 943 | +(define_expand "neon_vmla<mode>" | ||
| 944 | + [(match_operand:VDQW 0 "s_register_operand" "=w") | ||
| 945 | + (match_operand:VDQW 1 "s_register_operand" "0") | ||
| 946 | + (match_operand:VDQW 2 "s_register_operand" "w") | ||
| 947 | + (match_operand:VDQW 3 "s_register_operand" "w") | ||
| 948 | + (match_operand:SI 4 "immediate_operand" "i")] | ||
| 949 | + "TARGET_NEON" | ||
| 950 | +{ | ||
| 951 | + if (!<Is_float_mode> || flag_unsafe_math_optimizations) | ||
| 952 | + emit_insn (gen_mul<mode>3add<mode>_neon (operands[0], operands[1], | ||
| 953 | + operands[2], operands[3])); | ||
| 954 | + else | ||
| 955 | + emit_insn (gen_neon_vmla<mode>_unspec (operands[0], operands[1], | ||
| 956 | + operands[2], operands[3])); | ||
| 957 | + DONE; | ||
| 958 | +}) | ||
| 959 | + | ||
| 960 | +; Used for intrinsics when flag_unsafe_math_optimizations is false. | ||
| 961 | + | ||
| 962 | +(define_insn "neon_vmla<mode>_unspec" | ||
| 963 | + [(set (match_operand:VDQ 0 "s_register_operand" "=w") | ||
| 964 | + (unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "0") | ||
| 965 | + (match_operand:VDQ 2 "s_register_operand" "w") | ||
| 966 | + (match_operand:VDQ 3 "s_register_operand" "w")] | ||
| 967 | + UNSPEC_VMLA))] | ||
| 968 | "TARGET_NEON" | ||
| 969 | "vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3" | ||
| 970 | [(set (attr "neon_type") | ||
| 971 | @@ -1850,13 +1937,31 @@ | ||
| 972 | (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))] | ||
| 973 | ) | ||
| 974 | |||
| 975 | -(define_insn "neon_vmls<mode>" | ||
| 976 | - [(set (match_operand:VDQW 0 "s_register_operand" "=w") | ||
| 977 | - (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") | ||
| 978 | - (match_operand:VDQW 2 "s_register_operand" "w") | ||
| 979 | - (match_operand:VDQW 3 "s_register_operand" "w") | ||
| 980 | - (match_operand:SI 4 "immediate_operand" "i")] | ||
| 981 | - UNSPEC_VMLS))] | ||
| 982 | +(define_expand "neon_vmls<mode>" | ||
| 983 | + [(match_operand:VDQW 0 "s_register_operand" "=w") | ||
| 984 | + (match_operand:VDQW 1 "s_register_operand" "0") | ||
| 985 | + (match_operand:VDQW 2 "s_register_operand" "w") | ||
| 986 | + (match_operand:VDQW 3 "s_register_operand" "w") | ||
| 987 | + (match_operand:SI 4 "immediate_operand" "i")] | ||
| 988 | + "TARGET_NEON" | ||
| 989 | +{ | ||
| 990 | + if (!<Is_float_mode> || flag_unsafe_math_optimizations) | ||
| 991 | + emit_insn (gen_mul<mode>3neg<mode>add<mode>_neon (operands[0], | ||
| 992 | + operands[1], operands[2], operands[3])); | ||
| 993 | + else | ||
| 994 | + emit_insn (gen_neon_vmls<mode>_unspec (operands[0], operands[1], | ||
| 995 | + operands[2], operands[3])); | ||
| 996 | + DONE; | ||
| 997 | +}) | ||
| 998 | + | ||
| 999 | +; Used for intrinsics when flag_unsafe_math_optimizations is false. | ||
| 1000 | + | ||
| 1001 | +(define_insn "neon_vmls<mode>_unspec" | ||
| 1002 | + [(set (match_operand:VDQ 0 "s_register_operand" "=w") | ||
| 1003 | + (unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "0") | ||
| 1004 | + (match_operand:VDQ 2 "s_register_operand" "w") | ||
| 1005 | + (match_operand:VDQ 3 "s_register_operand" "w")] | ||
| 1006 | + UNSPEC_VMLS))] | ||
| 1007 | "TARGET_NEON" | ||
| 1008 | "vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3" | ||
| 1009 | [(set (attr "neon_type") | ||
| 1010 | @@ -1966,11 +2071,27 @@ | ||
| 1011 | (const_string "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))] | ||
| 1012 | ) | ||
| 1013 | |||
| 1014 | -(define_insn "neon_vsub<mode>" | ||
| 1015 | +(define_expand "neon_vsub<mode>" | ||
| 1016 | + [(match_operand:VDQX 0 "s_register_operand" "=w") | ||
| 1017 | + (match_operand:VDQX 1 "s_register_operand" "w") | ||
| 1018 | + (match_operand:VDQX 2 "s_register_operand" "w") | ||
| 1019 | + (match_operand:SI 3 "immediate_operand" "i")] | ||
| 1020 | + "TARGET_NEON" | ||
| 1021 | +{ | ||
| 1022 | + if (!<Is_float_mode> || flag_unsafe_math_optimizations) | ||
| 1023 | + emit_insn (gen_sub<mode>3 (operands[0], operands[1], operands[2])); | ||
| 1024 | + else | ||
| 1025 | + emit_insn (gen_neon_vsub<mode>_unspec (operands[0], operands[1], | ||
| 1026 | + operands[2])); | ||
| 1027 | + DONE; | ||
| 1028 | +}) | ||
| 1029 | + | ||
| 1030 | +; Used for intrinsics when flag_unsafe_math_optimizations is false. | ||
| 1031 | + | ||
| 1032 | +(define_insn "neon_vsub<mode>_unspec" | ||
| 1033 | [(set (match_operand:VDQX 0 "s_register_operand" "=w") | ||
| 1034 | (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w") | ||
| 1035 | - (match_operand:VDQX 2 "s_register_operand" "w") | ||
| 1036 | - (match_operand:SI 3 "immediate_operand" "i")] | ||
| 1037 | + (match_operand:VDQX 2 "s_register_operand" "w")] | ||
| 1038 | UNSPEC_VSUB))] | ||
| 1039 | "TARGET_NEON" | ||
| 1040 | "vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" | ||
| 1041 | @@ -2153,11 +2274,11 @@ | ||
| 1042 | |||
| 1043 | (define_insn "neon_vaba<mode>" | ||
| 1044 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | ||
| 1045 | - (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "0") | ||
| 1046 | - (match_operand:VDQIW 2 "s_register_operand" "w") | ||
| 1047 | - (match_operand:VDQIW 3 "s_register_operand" "w") | ||
| 1048 | - (match_operand:SI 4 "immediate_operand" "i")] | ||
| 1049 | - UNSPEC_VABA))] | ||
| 1050 | + (plus:VDQIW (match_operand:VDQIW 1 "s_register_operand" "0") | ||
| 1051 | + (unspec:VDQIW [(match_operand:VDQIW 2 "s_register_operand" "w") | ||
| 1052 | + (match_operand:VDQIW 3 "s_register_operand" "w") | ||
| 1053 | + (match_operand:SI 4 "immediate_operand" "i")] | ||
| 1054 | + UNSPEC_VABD)))] | ||
| 1055 | "TARGET_NEON" | ||
| 1056 | "vaba.%T4%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3" | ||
| 1057 | [(set (attr "neon_type") | ||
| 1058 | @@ -2167,11 +2288,11 @@ | ||
| 1059 | |||
| 1060 | (define_insn "neon_vabal<mode>" | ||
| 1061 | [(set (match_operand:<V_widen> 0 "s_register_operand" "=w") | ||
| 1062 | - (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0") | ||
| 1063 | - (match_operand:VW 2 "s_register_operand" "w") | ||
| 1064 | - (match_operand:VW 3 "s_register_operand" "w") | ||
| 1065 | - (match_operand:SI 4 "immediate_operand" "i")] | ||
| 1066 | - UNSPEC_VABAL))] | ||
| 1067 | + (plus:<V_widen> (match_operand:<V_widen> 1 "s_register_operand" "0") | ||
| 1068 | + (unspec:<V_widen> [(match_operand:VW 2 "s_register_operand" "w") | ||
| 1069 | + (match_operand:VW 3 "s_register_operand" "w") | ||
| 1070 | + (match_operand:SI 4 "immediate_operand" "i")] | ||
| 1071 | + UNSPEC_VABDL)))] | ||
| 1072 | "TARGET_NEON" | ||
| 1073 | "vabal.%T4%#<V_sz_elem>\t%q0, %P2, %P3" | ||
| 1074 | [(set_attr "neon_type" "neon_vaba")] | ||
| 1075 | @@ -2302,22 +2423,15 @@ | ||
| 1076 | (const_string "neon_fp_vrecps_vrsqrts_qqq")))] | ||
| 1077 | ) | ||
| 1078 | |||
| 1079 | -(define_insn "neon_vabs<mode>" | ||
| 1080 | - [(set (match_operand:VDQW 0 "s_register_operand" "=w") | ||
| 1081 | - (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "w") | ||
| 1082 | - (match_operand:SI 2 "immediate_operand" "i")] | ||
| 1083 | - UNSPEC_VABS))] | ||
| 1084 | +(define_expand "neon_vabs<mode>" | ||
| 1085 | + [(match_operand:VDQW 0 "s_register_operand" "") | ||
| 1086 | + (match_operand:VDQW 1 "s_register_operand" "") | ||
| 1087 | + (match_operand:SI 2 "immediate_operand" "")] | ||
| 1088 | "TARGET_NEON" | ||
| 1089 | - "vabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1" | ||
| 1090 | - [(set (attr "neon_type") | ||
| 1091 | - (if_then_else (ior (ne (symbol_ref "<Is_float_mode>") (const_int 0)) | ||
| 1092 | - (ne (symbol_ref "<Is_float_mode>") (const_int 0))) | ||
| 1093 | - (if_then_else | ||
| 1094 | - (ne (symbol_ref "<Is_d_reg>") (const_int 0)) | ||
| 1095 | - (const_string "neon_fp_vadd_ddd_vabs_dd") | ||
| 1096 | - (const_string "neon_fp_vadd_qqq_vabs_qq")) | ||
| 1097 | - (const_string "neon_vqneg_vqabs")))] | ||
| 1098 | -) | ||
| 1099 | +{ | ||
| 1100 | + emit_insn (gen_abs<mode>2 (operands[0], operands[1])); | ||
| 1101 | + DONE; | ||
| 1102 | +}) | ||
| 1103 | |||
| 1104 | (define_insn "neon_vqabs<mode>" | ||
| 1105 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | ||
| 1106 | @@ -2359,26 +2473,42 @@ | ||
| 1107 | [(set_attr "neon_type" "neon_int_1")] | ||
| 1108 | ) | ||
| 1109 | |||
| 1110 | -(define_insn "neon_vclz<mode>" | ||
| 1111 | +(define_insn "clz<mode>2" | ||
| 1112 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | ||
| 1113 | - (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | ||
| 1114 | - (match_operand:SI 2 "immediate_operand" "i")] | ||
| 1115 | - UNSPEC_VCLZ))] | ||
| 1116 | + (clz:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")))] | ||
| 1117 | "TARGET_NEON" | ||
| 1118 | "vclz.<V_if_elem>\t%<V_reg>0, %<V_reg>1" | ||
| 1119 | [(set_attr "neon_type" "neon_int_1")] | ||
| 1120 | ) | ||
| 1121 | |||
| 1122 | -(define_insn "neon_vcnt<mode>" | ||
| 1123 | +(define_expand "neon_vclz<mode>" | ||
| 1124 | + [(match_operand:VDQIW 0 "s_register_operand" "") | ||
| 1125 | + (match_operand:VDQIW 1 "s_register_operand" "") | ||
| 1126 | + (match_operand:SI 2 "immediate_operand" "")] | ||
| 1127 | + "TARGET_NEON" | ||
| 1128 | +{ | ||
| 1129 | + emit_insn (gen_clz<mode>2 (operands[0], operands[1])); | ||
| 1130 | + DONE; | ||
| 1131 | +}) | ||
| 1132 | + | ||
| 1133 | +(define_insn "popcount<mode>2" | ||
| 1134 | [(set (match_operand:VE 0 "s_register_operand" "=w") | ||
| 1135 | - (unspec:VE [(match_operand:VE 1 "s_register_operand" "w") | ||
| 1136 | - (match_operand:SI 2 "immediate_operand" "i")] | ||
| 1137 | - UNSPEC_VCNT))] | ||
| 1138 | + (popcount:VE (match_operand:VE 1 "s_register_operand" "w")))] | ||
| 1139 | "TARGET_NEON" | ||
| 1140 | "vcnt.<V_sz_elem>\t%<V_reg>0, %<V_reg>1" | ||
| 1141 | [(set_attr "neon_type" "neon_int_1")] | ||
| 1142 | ) | ||
| 1143 | |||
| 1144 | +(define_expand "neon_vcnt<mode>" | ||
| 1145 | + [(match_operand:VE 0 "s_register_operand" "=w") | ||
| 1146 | + (match_operand:VE 1 "s_register_operand" "w") | ||
| 1147 | + (match_operand:SI 2 "immediate_operand" "i")] | ||
| 1148 | + "TARGET_NEON" | ||
| 1149 | +{ | ||
| 1150 | + emit_insn (gen_popcount<mode>2 (operands[0], operands[1])); | ||
| 1151 | + DONE; | ||
| 1152 | +}) | ||
| 1153 | + | ||
| 1154 | (define_insn "neon_vrecpe<mode>" | ||
| 1155 | [(set (match_operand:V32 0 "s_register_operand" "=w") | ||
| 1156 | (unspec:V32 [(match_operand:V32 1 "s_register_operand" "w") | ||
| 1157 | @@ -2555,126 +2685,65 @@ | ||
| 1158 | ; Operand 3 (info word) is ignored because it does nothing useful with 64-bit | ||
| 1159 | ; elements. | ||
| 1160 | |||
| 1161 | -(define_insn "neon_vget_lanedi" | ||
| 1162 | - [(set (match_operand:DI 0 "s_register_operand" "=r") | ||
| 1163 | - (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") | ||
| 1164 | - (match_operand:SI 2 "immediate_operand" "i") | ||
| 1165 | - (match_operand:SI 3 "immediate_operand" "i")] | ||
| 1166 | - UNSPEC_VGET_LANE))] | ||
| 1167 | +(define_expand "neon_vget_lanedi" | ||
| 1168 | + [(match_operand:DI 0 "s_register_operand" "=r") | ||
| 1169 | + (match_operand:DI 1 "s_register_operand" "w") | ||
| 1170 | + (match_operand:SI 2 "immediate_operand" "i") | ||
| 1171 | + (match_operand:SI 3 "immediate_operand" "i")] | ||
| 1172 | "TARGET_NEON" | ||
| 1173 | { | ||
| 1174 | neon_lane_bounds (operands[2], 0, 1); | ||
| 1175 | - return "vmov%?\t%Q0, %R0, %P1 @ di"; | ||
| 1176 | -} | ||
| 1177 | - [(set_attr "predicable" "yes") | ||
| 1178 | - (set_attr "neon_type" "neon_bp_simple")] | ||
| 1179 | -) | ||
| 1180 | + emit_move_insn (operands[0], operands[1]); | ||
| 1181 | + DONE; | ||
| 1182 | +}) | ||
| 1183 | |||
| 1184 | -(define_insn "neon_vget_lanev2di" | ||
| 1185 | - [(set (match_operand:DI 0 "s_register_operand" "=r") | ||
| 1186 | - (unspec:DI [(match_operand:V2DI 1 "s_register_operand" "w") | ||
| 1187 | - (match_operand:SI 2 "immediate_operand" "i") | ||
| 1188 | - (match_operand:SI 3 "immediate_operand" "i")] | ||
| 1189 | - UNSPEC_VGET_LANE))] | ||
| 1190 | +(define_expand "neon_vget_lanev2di" | ||
| 1191 | + [(match_operand:DI 0 "s_register_operand" "=r") | ||
| 1192 | + (match_operand:V2DI 1 "s_register_operand" "w") | ||
| 1193 | + (match_operand:SI 2 "immediate_operand" "i") | ||
| 1194 | + (match_operand:SI 3 "immediate_operand" "i")] | ||
| 1195 | "TARGET_NEON" | ||
| 1196 | { | ||
| 1197 | - rtx ops[2]; | ||
| 1198 | - unsigned int regno = REGNO (operands[1]); | ||
| 1199 | - unsigned int elt = INTVAL (operands[2]); | ||
| 1200 | - | ||
| 1201 | neon_lane_bounds (operands[2], 0, 2); | ||
| 1202 | - | ||
| 1203 | - ops[0] = operands[0]; | ||
| 1204 | - ops[1] = gen_rtx_REG (DImode, regno + 2 * elt); | ||
| 1205 | - output_asm_insn ("vmov%?\t%Q0, %R0, %P1 @ v2di", ops); | ||
| 1206 | - | ||
| 1207 | - return ""; | ||
| 1208 | -} | ||
| 1209 | - [(set_attr "predicable" "yes") | ||
| 1210 | - (set_attr "neon_type" "neon_bp_simple")] | ||
| 1211 | -) | ||
| 1212 | - | ||
| 1213 | -(define_insn "neon_vset_lane<mode>" | ||
| 1214 | - [(set (match_operand:VD 0 "s_register_operand" "=w") | ||
| 1215 | - (unspec:VD [(match_operand:<V_elem> 1 "s_register_operand" "r") | ||
| 1216 | - (match_operand:VD 2 "s_register_operand" "0") | ||
| 1217 | - (match_operand:SI 3 "immediate_operand" "i")] | ||
| 1218 | - UNSPEC_VSET_LANE))] | ||
| 1219 | + emit_insn (gen_vec_extractv2di (operands[0], operands[1], operands[2])); | ||
| 1220 | + DONE; | ||
| 1221 | +}) | ||
| 1222 | + | ||
| 1223 | +(define_expand "neon_vset_lane<mode>" | ||
| 1224 | + [(match_operand:VDQ 0 "s_register_operand" "=w") | ||
| 1225 | + (match_operand:<V_elem> 1 "s_register_operand" "r") | ||
| 1226 | + (match_operand:VDQ 2 "s_register_operand" "0") | ||
| 1227 | + (match_operand:SI 3 "immediate_operand" "i")] | ||
| 1228 | "TARGET_NEON" | ||
| 1229 | { | ||
| 1230 | + unsigned int elt = INTVAL (operands[3]); | ||
| 1231 | neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode)); | ||
| 1232 | - return "vmov%?.<V_sz_elem>\t%P0[%c3], %1"; | ||
| 1233 | -} | ||
| 1234 | - [(set_attr "predicable" "yes") | ||
| 1235 | - (set_attr "neon_type" "neon_bp_simple")] | ||
| 1236 | -) | ||
| 1237 | + | ||
| 1238 | + if (BYTES_BIG_ENDIAN) | ||
| 1239 | + { | ||
| 1240 | + unsigned int reg_nelts | ||
| 1241 | + = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode)); | ||
| 1242 | + elt ^= reg_nelts - 1; | ||
| 1243 | + } | ||
| 1244 | + | ||
| 1245 | + emit_insn (gen_vec_set<mode>_internal (operands[0], operands[1], | ||
| 1246 | + GEN_INT (1 << elt), operands[2])); | ||
| 1247 | + DONE; | ||
| 1248 | +}) | ||
| 1249 | |||
| 1250 | ; See neon_vget_lanedi comment for reasons operands 2 & 3 are ignored. | ||
| 1251 | |||
| 1252 | -(define_insn "neon_vset_lanedi" | ||
| 1253 | - [(set (match_operand:DI 0 "s_register_operand" "=w") | ||
| 1254 | - (unspec:DI [(match_operand:DI 1 "s_register_operand" "r") | ||
| 1255 | - (match_operand:DI 2 "s_register_operand" "0") | ||
| 1256 | - (match_operand:SI 3 "immediate_operand" "i")] | ||
| 1257 | - UNSPEC_VSET_LANE))] | ||
| 1258 | +(define_expand "neon_vset_lanedi" | ||
| 1259 | + [(match_operand:DI 0 "s_register_operand" "=w") | ||
| 1260 | + (match_operand:DI 1 "s_register_operand" "r") | ||
| 1261 | + (match_operand:DI 2 "s_register_operand" "0") | ||
| 1262 | + (match_operand:SI 3 "immediate_operand" "i")] | ||
| 1263 | "TARGET_NEON" | ||
| 1264 | { | ||
| 1265 | neon_lane_bounds (operands[3], 0, 1); | ||
| 1266 | - return "vmov%?\t%P0, %Q1, %R1 @ di"; | ||
| 1267 | -} | ||
| 1268 | - [(set_attr "predicable" "yes") | ||
| 1269 | - (set_attr "neon_type" "neon_bp_simple")] | ||
| 1270 | -) | ||
| 1271 | - | ||
| 1272 | -(define_insn "neon_vset_lane<mode>" | ||
| 1273 | - [(set (match_operand:VQ 0 "s_register_operand" "=w") | ||
| 1274 | - (unspec:VQ [(match_operand:<V_elem> 1 "s_register_operand" "r") | ||
| 1275 | - (match_operand:VQ 2 "s_register_operand" "0") | ||
| 1276 | - (match_operand:SI 3 "immediate_operand" "i")] | ||
| 1277 | - UNSPEC_VSET_LANE))] | ||
| 1278 | - "TARGET_NEON" | ||
| 1279 | -{ | ||
| 1280 | - rtx ops[4]; | ||
| 1281 | - unsigned int regno = REGNO (operands[0]); | ||
| 1282 | - unsigned int halfelts = GET_MODE_NUNITS (<MODE>mode) / 2; | ||
| 1283 | - unsigned int elt = INTVAL (operands[3]); | ||
| 1284 | - | ||
| 1285 | - neon_lane_bounds (operands[3], 0, halfelts * 2); | ||
| 1286 | - | ||
| 1287 | - ops[0] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts)); | ||
| 1288 | - ops[1] = operands[1]; | ||
| 1289 | - ops[2] = GEN_INT (elt % halfelts); | ||
| 1290 | - output_asm_insn ("vmov%?.<V_sz_elem>\t%P0[%c2], %1", ops); | ||
| 1291 | - | ||
| 1292 | - return ""; | ||
| 1293 | -} | ||
| 1294 | - [(set_attr "predicable" "yes") | ||
| 1295 | - (set_attr "neon_type" "neon_bp_simple")] | ||
| 1296 | -) | ||
| 1297 | - | ||
| 1298 | -(define_insn "neon_vset_lanev2di" | ||
| 1299 | - [(set (match_operand:V2DI 0 "s_register_operand" "=w") | ||
| 1300 | - (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r") | ||
| 1301 | - (match_operand:V2DI 2 "s_register_operand" "0") | ||
| 1302 | - (match_operand:SI 3 "immediate_operand" "i")] | ||
| 1303 | - UNSPEC_VSET_LANE))] | ||
| 1304 | - "TARGET_NEON" | ||
| 1305 | -{ | ||
| 1306 | - rtx ops[2]; | ||
| 1307 | - unsigned int regno = REGNO (operands[0]); | ||
| 1308 | - unsigned int elt = INTVAL (operands[3]); | ||
| 1309 | - | ||
| 1310 | - neon_lane_bounds (operands[3], 0, 2); | ||
| 1311 | - | ||
| 1312 | - ops[0] = gen_rtx_REG (DImode, regno + 2 * elt); | ||
| 1313 | - ops[1] = operands[1]; | ||
| 1314 | - output_asm_insn ("vmov%?\t%P0, %Q1, %R1 @ v2di", ops); | ||
| 1315 | - | ||
| 1316 | - return ""; | ||
| 1317 | -} | ||
| 1318 | - [(set_attr "predicable" "yes") | ||
| 1319 | - (set_attr "neon_type" "neon_bp_simple")] | ||
| 1320 | -) | ||
| 1321 | + emit_move_insn (operands[0], operands[1]); | ||
| 1322 | + DONE; | ||
| 1323 | +}) | ||
| 1324 | |||
| 1325 | (define_expand "neon_vcreate<mode>" | ||
| 1326 | [(match_operand:VDX 0 "s_register_operand" "") | ||
| 1327 | @@ -2688,8 +2757,7 @@ | ||
| 1328 | |||
| 1329 | (define_insn "neon_vdup_n<mode>" | ||
| 1330 | [(set (match_operand:VX 0 "s_register_operand" "=w") | ||
| 1331 | - (unspec:VX [(match_operand:<V_elem> 1 "s_register_operand" "r")] | ||
| 1332 | - UNSPEC_VDUP_N))] | ||
| 1333 | + (vec_duplicate:VX (match_operand:<V_elem> 1 "s_register_operand" "r")))] | ||
| 1334 | "TARGET_NEON" | ||
| 1335 | "vdup%?.<V_sz_elem>\t%<V_reg>0, %1" | ||
| 1336 | ;; Assume this schedules like vmov. | ||
| 1337 | @@ -2699,8 +2767,7 @@ | ||
| 1338 | |||
| 1339 | (define_insn "neon_vdup_n<mode>" | ||
| 1340 | [(set (match_operand:V32 0 "s_register_operand" "=w,w") | ||
| 1341 | - (unspec:V32 [(match_operand:<V_elem> 1 "s_register_operand" "r,t")] | ||
| 1342 | - UNSPEC_VDUP_N))] | ||
| 1343 | + (vec_duplicate:V32 (match_operand:<V_elem> 1 "s_register_operand" "r,t")))] | ||
| 1344 | "TARGET_NEON" | ||
| 1345 | "@ | ||
| 1346 | vdup%?.<V_sz_elem>\t%<V_reg>0, %1 | ||
| 1347 | @@ -2710,61 +2777,76 @@ | ||
| 1348 | (set_attr "neon_type" "neon_bp_simple")] | ||
| 1349 | ) | ||
| 1350 | |||
| 1351 | -(define_insn "neon_vdup_ndi" | ||
| 1352 | - [(set (match_operand:DI 0 "s_register_operand" "=w") | ||
| 1353 | - (unspec:DI [(match_operand:DI 1 "s_register_operand" "r")] | ||
| 1354 | - UNSPEC_VDUP_N))] | ||
| 1355 | +(define_expand "neon_vdup_ndi" | ||
| 1356 | + [(match_operand:DI 0 "s_register_operand" "=w") | ||
| 1357 | + (match_operand:DI 1 "s_register_operand" "r")] | ||
| 1358 | "TARGET_NEON" | ||
| 1359 | - "vmov%?\t%P0, %Q1, %R1" | ||
| 1360 | - [(set_attr "predicable" "yes") | ||
| 1361 | - (set_attr "neon_type" "neon_bp_simple")] | ||
| 1362 | +{ | ||
| 1363 | + emit_move_insn (operands[0], operands[1]); | ||
| 1364 | + DONE; | ||
| 1365 | +} | ||
| 1366 | ) | ||
| 1367 | |||
| 1368 | (define_insn "neon_vdup_nv2di" | ||
| 1369 | - [(set (match_operand:V2DI 0 "s_register_operand" "=w") | ||
| 1370 | - (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r")] | ||
| 1371 | - UNSPEC_VDUP_N))] | ||
| 1372 | + [(set (match_operand:V2DI 0 "s_register_operand" "=w,w") | ||
| 1373 | + (vec_duplicate:V2DI (match_operand:DI 1 "s_register_operand" "r,w")))] | ||
| 1374 | "TARGET_NEON" | ||
| 1375 | - "vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1" | ||
| 1376 | + "@ | ||
| 1377 | + vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1 | ||
| 1378 | + vmov%?\t%e0, %P1\;vmov%?\t%f0, %P1" | ||
| 1379 | [(set_attr "predicable" "yes") | ||
| 1380 | (set_attr "length" "8") | ||
| 1381 | (set_attr "neon_type" "neon_bp_simple")] | ||
| 1382 | ) | ||
| 1383 | |||
| 1384 | -(define_insn "neon_vdup_lane<mode>" | ||
| 1385 | - [(set (match_operand:VD 0 "s_register_operand" "=w") | ||
| 1386 | - (unspec:VD [(match_operand:VD 1 "s_register_operand" "w") | ||
| 1387 | - (match_operand:SI 2 "immediate_operand" "i")] | ||
| 1388 | - UNSPEC_VDUP_LANE))] | ||
| 1389 | +(define_insn "neon_vdup_lane<mode>_internal" | ||
| 1390 | + [(set (match_operand:VDQW 0 "s_register_operand" "=w") | ||
| 1391 | + (vec_duplicate:VDQW | ||
| 1392 | + (vec_select:<V_elem> | ||
| 1393 | + (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w") | ||
| 1394 | + (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] | ||
| 1395 | "TARGET_NEON" | ||
| 1396 | { | ||
| 1397 | - neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<MODE>mode)); | ||
| 1398 | - return "vdup.<V_sz_elem>\t%P0, %P1[%c2]"; | ||
| 1399 | + if (BYTES_BIG_ENDIAN) | ||
| 1400 | + { | ||
| 1401 | + int elt = INTVAL (operands[2]); | ||
| 1402 | + elt = GET_MODE_NUNITS (<V_double_vector_mode>mode) - 1 - elt; | ||
| 1403 | + operands[2] = GEN_INT (elt); | ||
| 1404 | + } | ||
| 1405 | + if (<Is_d_reg>) | ||
| 1406 | + return "vdup.<V_sz_elem>\t%P0, %P1[%c2]"; | ||
| 1407 | + else | ||
| 1408 | + return "vdup.<V_sz_elem>\t%q0, %P1[%c2]"; | ||
| 1409 | } | ||
| 1410 | ;; Assume this schedules like vmov. | ||
| 1411 | [(set_attr "neon_type" "neon_bp_simple")] | ||
| 1412 | ) | ||
| 1413 | |||
| 1414 | -(define_insn "neon_vdup_lane<mode>" | ||
| 1415 | - [(set (match_operand:VQ 0 "s_register_operand" "=w") | ||
| 1416 | - (unspec:VQ [(match_operand:<V_HALF> 1 "s_register_operand" "w") | ||
| 1417 | - (match_operand:SI 2 "immediate_operand" "i")] | ||
| 1418 | - UNSPEC_VDUP_LANE))] | ||
| 1419 | +(define_expand "neon_vdup_lane<mode>" | ||
| 1420 | + [(match_operand:VDQW 0 "s_register_operand" "=w") | ||
| 1421 | + (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w") | ||
| 1422 | + (match_operand:SI 2 "immediate_operand" "i")] | ||
| 1423 | "TARGET_NEON" | ||
| 1424 | { | ||
| 1425 | - neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<V_HALF>mode)); | ||
| 1426 | - return "vdup.<V_sz_elem>\t%q0, %P1[%c2]"; | ||
| 1427 | -} | ||
| 1428 | - ;; Assume this schedules like vmov. | ||
| 1429 | - [(set_attr "neon_type" "neon_bp_simple")] | ||
| 1430 | -) | ||
| 1431 | + neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<V_double_vector_mode>mode)); | ||
| 1432 | + if (BYTES_BIG_ENDIAN) | ||
| 1433 | + { | ||
| 1434 | + unsigned int elt = INTVAL (operands[2]); | ||
| 1435 | + unsigned int reg_nelts | ||
| 1436 | + = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<V_double_vector_mode>mode)); | ||
| 1437 | + elt ^= reg_nelts - 1; | ||
| 1438 | + operands[2] = GEN_INT (elt); | ||
| 1439 | + } | ||
| 1440 | + emit_insn (gen_neon_vdup_lane<mode>_internal (operands[0], operands[1], | ||
| 1441 | + operands[2])); | ||
| 1442 | + DONE; | ||
| 1443 | +}) | ||
| 1444 | |||
| 1445 | ; Scalar index is ignored, since only zero is valid here. | ||
| 1446 | (define_expand "neon_vdup_lanedi" | ||
| 1447 | - [(set (match_operand:DI 0 "s_register_operand" "=w") | ||
| 1448 | - (unspec:DI [(match_operand:DI 1 "s_register_operand" "w") | ||
| 1449 | - (match_operand:SI 2 "immediate_operand" "i")] | ||
| 1450 | - UNSPEC_VDUP_LANE))] | ||
| 1451 | + [(match_operand:DI 0 "s_register_operand" "=w") | ||
| 1452 | + (match_operand:DI 1 "s_register_operand" "w") | ||
| 1453 | + (match_operand:SI 2 "immediate_operand" "i")] | ||
| 1454 | "TARGET_NEON" | ||
| 1455 | { | ||
| 1456 | neon_lane_bounds (operands[2], 0, 1); | ||
| 1457 | @@ -2772,20 +2854,17 @@ | ||
| 1458 | DONE; | ||
| 1459 | }) | ||
| 1460 | |||
| 1461 | -; Likewise. | ||
| 1462 | -(define_insn "neon_vdup_lanev2di" | ||
| 1463 | - [(set (match_operand:V2DI 0 "s_register_operand" "=w") | ||
| 1464 | - (unspec:V2DI [(match_operand:DI 1 "s_register_operand" "w") | ||
| 1465 | - (match_operand:SI 2 "immediate_operand" "i")] | ||
| 1466 | - UNSPEC_VDUP_LANE))] | ||
| 1467 | +; Likewise for v2di, as the DImode second operand has only a single element. | ||
| 1468 | +(define_expand "neon_vdup_lanev2di" | ||
| 1469 | + [(match_operand:V2DI 0 "s_register_operand" "=w") | ||
| 1470 | + (match_operand:DI 1 "s_register_operand" "w") | ||
| 1471 | + (match_operand:SI 2 "immediate_operand" "i")] | ||
| 1472 | "TARGET_NEON" | ||
| 1473 | { | ||
| 1474 | neon_lane_bounds (operands[2], 0, 1); | ||
| 1475 | - return "vmov\t%e0, %P1\;vmov\t%f0, %P1"; | ||
| 1476 | -} | ||
| 1477 | - [(set_attr "length" "8") | ||
| 1478 | - (set_attr "neon_type" "neon_bp_simple")] | ||
| 1479 | -) | ||
| 1480 | + emit_insn (gen_neon_vdup_nv2di (operands[0], operands[1])); | ||
| 1481 | + DONE; | ||
| 1482 | +}) | ||
| 1483 | |||
| 1484 | ;; In this insn, operand 1 should be low, and operand 2 the high part of the | ||
| 1485 | ;; dest vector. | ||
| 1486 | @@ -2796,9 +2875,8 @@ | ||
| 1487 | |||
| 1488 | (define_insn "neon_vcombine<mode>" | ||
| 1489 | [(set (match_operand:<V_DOUBLE> 0 "s_register_operand" "=w") | ||
| 1490 | - (unspec:<V_DOUBLE> [(match_operand:VDX 1 "s_register_operand" "w") | ||
| 1491 | - (match_operand:VDX 2 "s_register_operand" "w")] | ||
| 1492 | - UNSPEC_VCOMBINE))] | ||
| 1493 | + (vec_concat:<V_DOUBLE> (match_operand:VDX 1 "s_register_operand" "w") | ||
| 1494 | + (match_operand:VDX 2 "s_register_operand" "w")))] | ||
| 1495 | "TARGET_NEON" | ||
| 1496 | { | ||
| 1497 | int dest = REGNO (operands[0]); | ||
| 1498 | @@ -2838,27 +2916,171 @@ | ||
| 1499 | (set_attr "neon_type" "neon_bp_simple")] | ||
| 1500 | ) | ||
| 1501 | |||
| 1502 | -(define_insn "neon_vget_high<mode>" | ||
| 1503 | - [(set (match_operand:<V_HALF> 0 "s_register_operand" "=w") | ||
| 1504 | - (unspec:<V_HALF> [(match_operand:VQX 1 "s_register_operand" "w")] | ||
| 1505 | - UNSPEC_VGET_HIGH))] | ||
| 1506 | - "TARGET_NEON" | ||
| 1507 | -{ | ||
| 1508 | - int dest = REGNO (operands[0]); | ||
| 1509 | - int src = REGNO (operands[1]); | ||
| 1510 | - | ||
| 1511 | - if (dest != src + 2) | ||
| 1512 | - return "vmov\t%P0, %f1"; | ||
| 1513 | - else | ||
| 1514 | - return ""; | ||
| 1515 | -} | ||
| 1516 | - [(set_attr "neon_type" "neon_bp_simple")] | ||
| 1517 | -) | ||
| 1518 | - | ||
| 1519 | -(define_insn "neon_vget_low<mode>" | ||
| 1520 | - [(set (match_operand:<V_HALF> 0 "s_register_operand" "=w") | ||
| 1521 | - (unspec:<V_HALF> [(match_operand:VQX 1 "s_register_operand" "w")] | ||
| 1522 | - UNSPEC_VGET_LOW))] | ||
| 1523 | +(define_insn "neon_vget_highv16qi" | ||
| 1524 | + [(set (match_operand:V8QI 0 "s_register_operand" "=w") | ||
| 1525 | + (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w") | ||
| 1526 | + (parallel [(const_int 8) (const_int 9) | ||
| 1527 | + (const_int 10) (const_int 11) | ||
| 1528 | + (const_int 12) (const_int 13) | ||
| 1529 | + (const_int 14) (const_int 15)])))] | ||
| 1530 | + "TARGET_NEON" | ||
| 1531 | +{ | ||
| 1532 | + int dest = REGNO (operands[0]); | ||
| 1533 | + int src = REGNO (operands[1]); | ||
| 1534 | + | ||
| 1535 | + if (dest != src + 2) | ||
| 1536 | + return "vmov\t%P0, %f1"; | ||
| 1537 | + else | ||
| 1538 | + return ""; | ||
| 1539 | +} | ||
| 1540 | + [(set_attr "neon_type" "neon_bp_simple")] | ||
| 1541 | +) | ||
| 1542 | + | ||
| 1543 | +(define_insn "neon_vget_highv8hi" | ||
| 1544 | + [(set (match_operand:V4HI 0 "s_register_operand" "=w") | ||
| 1545 | + (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w") | ||
| 1546 | + (parallel [(const_int 4) (const_int 5) | ||
| 1547 | + (const_int 6) (const_int 7)])))] | ||
| 1548 | + "TARGET_NEON" | ||
| 1549 | +{ | ||
| 1550 | + int dest = REGNO (operands[0]); | ||
| 1551 | + int src = REGNO (operands[1]); | ||
| 1552 | + | ||
| 1553 | + if (dest != src + 2) | ||
| 1554 | + return "vmov\t%P0, %f1"; | ||
| 1555 | + else | ||
| 1556 | + return ""; | ||
| 1557 | +} | ||
| 1558 | + [(set_attr "neon_type" "neon_bp_simple")] | ||
| 1559 | +) | ||
| 1560 | + | ||
| 1561 | +(define_insn "neon_vget_highv4si" | ||
| 1562 | + [(set (match_operand:V2SI 0 "s_register_operand" "=w") | ||
| 1563 | + (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w") | ||
| 1564 | + (parallel [(const_int 2) (const_int 3)])))] | ||
| 1565 | + "TARGET_NEON" | ||
| 1566 | +{ | ||
| 1567 | + int dest = REGNO (operands[0]); | ||
| 1568 | + int src = REGNO (operands[1]); | ||
| 1569 | + | ||
| 1570 | + if (dest != src + 2) | ||
| 1571 | + return "vmov\t%P0, %f1"; | ||
| 1572 | + else | ||
| 1573 | + return ""; | ||
| 1574 | +} | ||
| 1575 | + [(set_attr "neon_type" "neon_bp_simple")] | ||
| 1576 | +) | ||
| 1577 | + | ||
| 1578 | +(define_insn "neon_vget_highv4sf" | ||
| 1579 | + [(set (match_operand:V2SF 0 "s_register_operand" "=w") | ||
| 1580 | + (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w") | ||
| 1581 | + (parallel [(const_int 2) (const_int 3)])))] | ||
| 1582 | + "TARGET_NEON" | ||
| 1583 | +{ | ||
| 1584 | + int dest = REGNO (operands[0]); | ||
| 1585 | + int src = REGNO (operands[1]); | ||
| 1586 | + | ||
| 1587 | + if (dest != src + 2) | ||
| 1588 | + return "vmov\t%P0, %f1"; | ||
| 1589 | + else | ||
| 1590 | + return ""; | ||
| 1591 | +} | ||
| 1592 | + [(set_attr "neon_type" "neon_bp_simple")] | ||
| 1593 | +) | ||
| 1594 | + | ||
| 1595 | +(define_insn "neon_vget_highv2di" | ||
| 1596 | + [(set (match_operand:DI 0 "s_register_operand" "=w") | ||
| 1597 | + (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w") | ||
| 1598 | + (parallel [(const_int 1)])))] | ||
| 1599 | + "TARGET_NEON" | ||
| 1600 | +{ | ||
| 1601 | + int dest = REGNO (operands[0]); | ||
| 1602 | + int src = REGNO (operands[1]); | ||
| 1603 | + | ||
| 1604 | + if (dest != src + 2) | ||
| 1605 | + return "vmov\t%P0, %f1"; | ||
| 1606 | + else | ||
| 1607 | + return ""; | ||
| 1608 | +} | ||
| 1609 | + [(set_attr "neon_type" "neon_bp_simple")] | ||
| 1610 | +) | ||
| 1611 | + | ||
| 1612 | +(define_insn "neon_vget_lowv16qi" | ||
| 1613 | + [(set (match_operand:V8QI 0 "s_register_operand" "=w") | ||
| 1614 | + (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w") | ||
| 1615 | + (parallel [(const_int 0) (const_int 1) | ||
| 1616 | + (const_int 2) (const_int 3) | ||
| 1617 | + (const_int 4) (const_int 5) | ||
| 1618 | + (const_int 6) (const_int 7)])))] | ||
| 1619 | + "TARGET_NEON" | ||
| 1620 | +{ | ||
| 1621 | + int dest = REGNO (operands[0]); | ||
| 1622 | + int src = REGNO (operands[1]); | ||
| 1623 | + | ||
| 1624 | + if (dest != src) | ||
| 1625 | + return "vmov\t%P0, %e1"; | ||
| 1626 | + else | ||
| 1627 | + return ""; | ||
| 1628 | +} | ||
| 1629 | + [(set_attr "neon_type" "neon_bp_simple")] | ||
| 1630 | +) | ||
| 1631 | + | ||
| 1632 | +(define_insn "neon_vget_lowv8hi" | ||
| 1633 | + [(set (match_operand:V4HI 0 "s_register_operand" "=w") | ||
| 1634 | + (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w") | ||
| 1635 | + (parallel [(const_int 0) (const_int 1) | ||
| 1636 | + (const_int 2) (const_int 3)])))] | ||
| 1637 | + "TARGET_NEON" | ||
| 1638 | +{ | ||
| 1639 | + int dest = REGNO (operands[0]); | ||
| 1640 | + int src = REGNO (operands[1]); | ||
| 1641 | + | ||
| 1642 | + if (dest != src) | ||
| 1643 | + return "vmov\t%P0, %e1"; | ||
| 1644 | + else | ||
| 1645 | + return ""; | ||
| 1646 | +} | ||
| 1647 | + [(set_attr "neon_type" "neon_bp_simple")] | ||
| 1648 | +) | ||
| 1649 | + | ||
| 1650 | +(define_insn "neon_vget_lowv4si" | ||
| 1651 | + [(set (match_operand:V2SI 0 "s_register_operand" "=w") | ||
| 1652 | + (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w") | ||
| 1653 | + (parallel [(const_int 0) (const_int 1)])))] | ||
| 1654 | + "TARGET_NEON" | ||
| 1655 | +{ | ||
| 1656 | + int dest = REGNO (operands[0]); | ||
| 1657 | + int src = REGNO (operands[1]); | ||
| 1658 | + | ||
| 1659 | + if (dest != src) | ||
| 1660 | + return "vmov\t%P0, %e1"; | ||
| 1661 | + else | ||
| 1662 | + return ""; | ||
| 1663 | +} | ||
| 1664 | + [(set_attr "neon_type" "neon_bp_simple")] | ||
| 1665 | +) | ||
| 1666 | + | ||
| 1667 | +(define_insn "neon_vget_lowv4sf" | ||
| 1668 | + [(set (match_operand:V2SF 0 "s_register_operand" "=w") | ||
| 1669 | + (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w") | ||
| 1670 | + (parallel [(const_int 0) (const_int 1)])))] | ||
| 1671 | + "TARGET_NEON" | ||
| 1672 | +{ | ||
| 1673 | + int dest = REGNO (operands[0]); | ||
| 1674 | + int src = REGNO (operands[1]); | ||
| 1675 | + | ||
| 1676 | + if (dest != src) | ||
| 1677 | + return "vmov\t%P0, %e1"; | ||
| 1678 | + else | ||
| 1679 | + return ""; | ||
| 1680 | +} | ||
| 1681 | + [(set_attr "neon_type" "neon_bp_simple")] | ||
| 1682 | +) | ||
| 1683 | + | ||
| 1684 | +(define_insn "neon_vget_lowv2di" | ||
| 1685 | + [(set (match_operand:DI 0 "s_register_operand" "=w") | ||
| 1686 | + (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w") | ||
| 1687 | + (parallel [(const_int 0)])))] | ||
| 1688 | "TARGET_NEON" | ||
| 1689 | { | ||
| 1690 | int dest = REGNO (operands[0]); | ||
| 1691 | |||
| 1692 | === modified file 'gcc/config/arm/neon.ml' | ||
| 1693 | --- old/gcc/config/arm/neon.ml 2010-01-19 14:21:14 +0000 | ||
| 1694 | +++ new/gcc/config/arm/neon.ml 2010-07-29 15:59:12 +0000 | ||
| 1695 | @@ -709,7 +709,8 @@ | ||
| 1696 | let ops = | ||
| 1697 | [ | ||
| 1698 | (* Addition. *) | ||
| 1699 | - Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_64; | ||
| 1700 | + Vadd, [], All (3, Dreg), "vadd", sign_invar_2, F32 :: su_8_32; | ||
| 1701 | + Vadd, [No_op], All (3, Dreg), "vadd", sign_invar_2, [S64; U64]; | ||
| 1702 | Vadd, [], All (3, Qreg), "vaddQ", sign_invar_2, F32 :: su_8_64; | ||
| 1703 | Vadd, [], Long, "vaddl", elts_same_2, su_8_32; | ||
| 1704 | Vadd, [], Wide, "vaddw", elts_same_2, su_8_32; | ||
| 1705 | @@ -758,7 +759,8 @@ | ||
| 1706 | Vmls, [Saturating; Doubling], Long, "vqdmlsl", elts_same_io, [S16; S32]; | ||
| 1707 | |||
| 1708 | (* Subtraction. *) | ||
| 1709 | - Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_64; | ||
| 1710 | + Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_32; | ||
| 1711 | + Vsub, [No_op], All (3, Dreg), "vsub", sign_invar_2, [S64; U64]; | ||
| 1712 | Vsub, [], All (3, Qreg), "vsubQ", sign_invar_2, F32 :: su_8_64; | ||
| 1713 | Vsub, [], Long, "vsubl", elts_same_2, su_8_32; | ||
| 1714 | Vsub, [], Wide, "vsubw", elts_same_2, su_8_32; | ||
| 1715 | @@ -967,7 +969,8 @@ | ||
| 1716 | Use_operands [| Corereg; Dreg; Immed |], | ||
| 1717 | "vget_lane", get_lane, pf_su_8_32; | ||
| 1718 | Vget_lane, | ||
| 1719 | - [InfoWord; | ||
| 1720 | + [No_op; | ||
| 1721 | + InfoWord; | ||
| 1722 | Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]]; | ||
| 1723 | Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)], | ||
| 1724 | Use_operands [| Corereg; Dreg; Immed |], | ||
| 1725 | @@ -989,7 +992,8 @@ | ||
| 1726 | Instruction_name ["vmov"]], | ||
| 1727 | Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane", | ||
| 1728 | set_lane, pf_su_8_32; | ||
| 1729 | - Vset_lane, [Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]; | ||
| 1730 | + Vset_lane, [No_op; | ||
| 1731 | + Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]; | ||
| 1732 | Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)], | ||
| 1733 | Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane", | ||
| 1734 | set_lane_notype, [S64; U64]; | ||
| 1735 | @@ -1017,7 +1021,8 @@ | ||
| 1736 | Use_operands [| Dreg; Corereg |], "vdup_n", bits_1, | ||
| 1737 | pf_su_8_32; | ||
| 1738 | Vdup_n, | ||
| 1739 | - [Instruction_name ["vmov"]; | ||
| 1740 | + [No_op; | ||
| 1741 | + Instruction_name ["vmov"]; | ||
| 1742 | Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]], | ||
| 1743 | Use_operands [| Dreg; Corereg |], "vdup_n", notype_1, | ||
| 1744 | [S64; U64]; | ||
| 1745 | @@ -1028,7 +1033,8 @@ | ||
| 1746 | Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1, | ||
| 1747 | pf_su_8_32; | ||
| 1748 | Vdup_n, | ||
| 1749 | - [Instruction_name ["vmov"]; | ||
| 1750 | + [No_op; | ||
| 1751 | + Instruction_name ["vmov"]; | ||
| 1752 | Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]; | ||
| 1753 | Use_operands [| Dreg; Corereg; Corereg |]]], | ||
| 1754 | Use_operands [| Qreg; Corereg |], "vdupQ_n", notype_1, | ||
| 1755 | @@ -1043,7 +1049,8 @@ | ||
| 1756 | Use_operands [| Dreg; Corereg |], | ||
| 1757 | "vmov_n", bits_1, pf_su_8_32; | ||
| 1758 | Vmov_n, | ||
| 1759 | - [Builtin_name "vdup_n"; | ||
| 1760 | + [No_op; | ||
| 1761 | + Builtin_name "vdup_n"; | ||
| 1762 | Instruction_name ["vmov"]; | ||
| 1763 | Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]], | ||
| 1764 | Use_operands [| Dreg; Corereg |], | ||
| 1765 | @@ -1056,7 +1063,8 @@ | ||
| 1766 | Use_operands [| Qreg; Corereg |], | ||
| 1767 | "vmovQ_n", bits_1, pf_su_8_32; | ||
| 1768 | Vmov_n, | ||
| 1769 | - [Builtin_name "vdupQ_n"; | ||
| 1770 | + [No_op; | ||
| 1771 | + Builtin_name "vdupQ_n"; | ||
| 1772 | Instruction_name ["vmov"]; | ||
| 1773 | Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]; | ||
| 1774 | Use_operands [| Dreg; Corereg; Corereg |]]], | ||
| 1775 | @@ -1613,23 +1621,28 @@ | ||
| 1776 | store_3, [P16; F32; U16; U32; S16; S32]; | ||
| 1777 | |||
| 1778 | (* Logical operations. And. *) | ||
| 1779 | - Vand, [], All (3, Dreg), "vand", notype_2, su_8_64; | ||
| 1780 | + Vand, [], All (3, Dreg), "vand", notype_2, su_8_32; | ||
| 1781 | + Vand, [No_op], All (3, Dreg), "vand", notype_2, [S64; U64]; | ||
| 1782 | Vand, [], All (3, Qreg), "vandQ", notype_2, su_8_64; | ||
| 1783 | |||
| 1784 | (* Or. *) | ||
| 1785 | - Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_64; | ||
| 1786 | + Vorr, [], All (3, Dreg), "vorr", notype_2, su_8_32; | ||
| 1787 | + Vorr, [No_op], All (3, Dreg), "vorr", notype_2, [S64; U64]; | ||
| 1788 | Vorr, [], All (3, Qreg), "vorrQ", notype_2, su_8_64; | ||
| 1789 | |||
| 1790 | (* Eor. *) | ||
| 1791 | - Veor, [], All (3, Dreg), "veor", notype_2, su_8_64; | ||
| 1792 | + Veor, [], All (3, Dreg), "veor", notype_2, su_8_32; | ||
| 1793 | + Veor, [No_op], All (3, Dreg), "veor", notype_2, [S64; U64]; | ||
| 1794 | Veor, [], All (3, Qreg), "veorQ", notype_2, su_8_64; | ||
| 1795 | |||
| 1796 | (* Bic (And-not). *) | ||
| 1797 | - Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_64; | ||
| 1798 | + Vbic, [], All (3, Dreg), "vbic", notype_2, su_8_32; | ||
| 1799 | + Vbic, [No_op], All (3, Dreg), "vbic", notype_2, [S64; U64]; | ||
| 1800 | Vbic, [], All (3, Qreg), "vbicQ", notype_2, su_8_64; | ||
| 1801 | |||
| 1802 | (* Or-not. *) | ||
| 1803 | - Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_64; | ||
| 1804 | + Vorn, [], All (3, Dreg), "vorn", notype_2, su_8_32; | ||
| 1805 | + Vorn, [No_op], All (3, Dreg), "vorn", notype_2, [S64; U64]; | ||
| 1806 | Vorn, [], All (3, Qreg), "vornQ", notype_2, su_8_64; | ||
| 1807 | ] | ||
| 1808 | |||
| 1809 | |||
| 1810 | === modified file 'gcc/config/arm/predicates.md' | ||
| 1811 | --- old/gcc/config/arm/predicates.md 2009-07-15 09:12:22 +0000 | ||
| 1812 | +++ new/gcc/config/arm/predicates.md 2010-07-29 15:59:12 +0000 | ||
| 1813 | @@ -499,13 +499,15 @@ | ||
| 1814 | (define_predicate "imm_for_neon_logic_operand" | ||
| 1815 | (match_code "const_vector") | ||
| 1816 | { | ||
| 1817 | - return neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL); | ||
| 1818 | + return (TARGET_NEON | ||
| 1819 | + && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL)); | ||
| 1820 | }) | ||
| 1821 | |||
| 1822 | (define_predicate "imm_for_neon_inv_logic_operand" | ||
| 1823 | (match_code "const_vector") | ||
| 1824 | { | ||
| 1825 | - return neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL); | ||
| 1826 | + return (TARGET_NEON | ||
| 1827 | + && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL)); | ||
| 1828 | }) | ||
| 1829 | |||
| 1830 | (define_predicate "neon_logic_op2" | ||
| 1831 | |||
| 1832 | === modified file 'gcc/doc/arm-neon-intrinsics.texi' | ||
| 1833 | --- old/gcc/doc/arm-neon-intrinsics.texi 2009-11-18 17:06:46 +0000 | ||
| 1834 | +++ new/gcc/doc/arm-neon-intrinsics.texi 2010-07-29 15:59:12 +0000 | ||
| 1835 | @@ -43,20 +43,18 @@ | ||
| 1836 | |||
| 1837 | |||
| 1838 | @itemize @bullet | ||
| 1839 | +@item float32x2_t vadd_f32 (float32x2_t, float32x2_t) | ||
| 1840 | +@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}} | ||
| 1841 | +@end itemize | ||
| 1842 | + | ||
| 1843 | + | ||
| 1844 | +@itemize @bullet | ||
| 1845 | @item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t) | ||
| 1846 | -@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}} | ||
| 1847 | @end itemize | ||
| 1848 | |||
| 1849 | |||
| 1850 | @itemize @bullet | ||
| 1851 | @item int64x1_t vadd_s64 (int64x1_t, int64x1_t) | ||
| 1852 | -@*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{d0}, @var{d0}, @var{d0}} | ||
| 1853 | -@end itemize | ||
| 1854 | - | ||
| 1855 | - | ||
| 1856 | -@itemize @bullet | ||
| 1857 | -@item float32x2_t vadd_f32 (float32x2_t, float32x2_t) | ||
| 1858 | -@*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}} | ||
| 1859 | @end itemize | ||
| 1860 | |||
| 1861 | |||
| 1862 | @@ -1013,20 +1011,18 @@ | ||
| 1863 | |||
| 1864 | |||
| 1865 | @itemize @bullet | ||
| 1866 | +@item float32x2_t vsub_f32 (float32x2_t, float32x2_t) | ||
| 1867 | +@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}} | ||
| 1868 | +@end itemize | ||
| 1869 | + | ||
| 1870 | + | ||
| 1871 | +@itemize @bullet | ||
| 1872 | @item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t) | ||
| 1873 | -@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}} | ||
| 1874 | @end itemize | ||
| 1875 | |||
| 1876 | |||
| 1877 | @itemize @bullet | ||
| 1878 | @item int64x1_t vsub_s64 (int64x1_t, int64x1_t) | ||
| 1879 | -@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}} | ||
| 1880 | -@end itemize | ||
| 1881 | - | ||
| 1882 | - | ||
| 1883 | -@itemize @bullet | ||
| 1884 | -@item float32x2_t vsub_f32 (float32x2_t, float32x2_t) | ||
| 1885 | -@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}} | ||
| 1886 | @end itemize | ||
| 1887 | |||
| 1888 | |||
| 1889 | @@ -4750,13 +4746,11 @@ | ||
| 1890 | |||
| 1891 | @itemize @bullet | ||
| 1892 | @item uint64_t vget_lane_u64 (uint64x1_t, const int) | ||
| 1893 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} | ||
| 1894 | @end itemize | ||
| 1895 | |||
| 1896 | |||
| 1897 | @itemize @bullet | ||
| 1898 | @item int64_t vget_lane_s64 (int64x1_t, const int) | ||
| 1899 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} | ||
| 1900 | @end itemize | ||
| 1901 | |||
| 1902 | |||
| 1903 | @@ -4886,13 +4880,11 @@ | ||
| 1904 | |||
| 1905 | @itemize @bullet | ||
| 1906 | @item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int) | ||
| 1907 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} | ||
| 1908 | @end itemize | ||
| 1909 | |||
| 1910 | |||
| 1911 | @itemize @bullet | ||
| 1912 | @item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int) | ||
| 1913 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} | ||
| 1914 | @end itemize | ||
| 1915 | |||
| 1916 | |||
| 1917 | @@ -5081,13 +5073,11 @@ | ||
| 1918 | |||
| 1919 | @itemize @bullet | ||
| 1920 | @item uint64x1_t vdup_n_u64 (uint64_t) | ||
| 1921 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} | ||
| 1922 | @end itemize | ||
| 1923 | |||
| 1924 | |||
| 1925 | @itemize @bullet | ||
| 1926 | @item int64x1_t vdup_n_s64 (int64_t) | ||
| 1927 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} | ||
| 1928 | @end itemize | ||
| 1929 | |||
| 1930 | |||
| 1931 | @@ -5147,13 +5137,11 @@ | ||
| 1932 | |||
| 1933 | @itemize @bullet | ||
| 1934 | @item uint64x2_t vdupq_n_u64 (uint64_t) | ||
| 1935 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} | ||
| 1936 | @end itemize | ||
| 1937 | |||
| 1938 | |||
| 1939 | @itemize @bullet | ||
| 1940 | @item int64x2_t vdupq_n_s64 (int64_t) | ||
| 1941 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} | ||
| 1942 | @end itemize | ||
| 1943 | |||
| 1944 | |||
| 1945 | @@ -5213,13 +5201,11 @@ | ||
| 1946 | |||
| 1947 | @itemize @bullet | ||
| 1948 | @item uint64x1_t vmov_n_u64 (uint64_t) | ||
| 1949 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} | ||
| 1950 | @end itemize | ||
| 1951 | |||
| 1952 | |||
| 1953 | @itemize @bullet | ||
| 1954 | @item int64x1_t vmov_n_s64 (int64_t) | ||
| 1955 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} | ||
| 1956 | @end itemize | ||
| 1957 | |||
| 1958 | |||
| 1959 | @@ -5279,13 +5265,11 @@ | ||
| 1960 | |||
| 1961 | @itemize @bullet | ||
| 1962 | @item uint64x2_t vmovq_n_u64 (uint64_t) | ||
| 1963 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} | ||
| 1964 | @end itemize | ||
| 1965 | |||
| 1966 | |||
| 1967 | @itemize @bullet | ||
| 1968 | @item int64x2_t vmovq_n_s64 (int64_t) | ||
| 1969 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}} | ||
| 1970 | @end itemize | ||
| 1971 | |||
| 1972 | |||
| 1973 | @@ -5572,18 +5556,6 @@ | ||
| 1974 | |||
| 1975 | |||
| 1976 | @itemize @bullet | ||
| 1977 | -@item uint64x1_t vget_low_u64 (uint64x2_t) | ||
| 1978 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} | ||
| 1979 | -@end itemize | ||
| 1980 | - | ||
| 1981 | - | ||
| 1982 | -@itemize @bullet | ||
| 1983 | -@item int64x1_t vget_low_s64 (int64x2_t) | ||
| 1984 | -@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} | ||
| 1985 | -@end itemize | ||
| 1986 | - | ||
| 1987 | - | ||
| 1988 | -@itemize @bullet | ||
| 1989 | @item float32x2_t vget_low_f32 (float32x4_t) | ||
| 1990 | @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}} | ||
| 1991 | @end itemize | ||
| 1992 | @@ -5601,6 +5573,16 @@ | ||
| 1993 | @end itemize | ||
| 1994 | |||
| 1995 | |||
| 1996 | +@itemize @bullet | ||
| 1997 | +@item uint64x1_t vget_low_u64 (uint64x2_t) | ||
| 1998 | +@end itemize | ||
| 1999 | + | ||
| 2000 | + | ||
| 2001 | +@itemize @bullet | ||
| 2002 | +@item int64x1_t vget_low_s64 (int64x2_t) | ||
| 2003 | +@end itemize | ||
| 2004 | + | ||
| 2005 | + | ||
| 2006 | |||
| 2007 | |||
| 2008 | @subsubsection Conversions | ||
| 2009 | @@ -9727,13 +9709,11 @@ | ||
| 2010 | |||
| 2011 | @itemize @bullet | ||
| 2012 | @item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t) | ||
| 2013 | -@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}} | ||
| 2014 | @end itemize | ||
| 2015 | |||
| 2016 | |||
| 2017 | @itemize @bullet | ||
| 2018 | @item int64x1_t vand_s64 (int64x1_t, int64x1_t) | ||
| 2019 | -@*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}} | ||
| 2020 | @end itemize | ||
| 2021 | |||
| 2022 | |||
| 2023 | @@ -9827,13 +9807,11 @@ | ||
| 2024 | |||
| 2025 | @itemize @bullet | ||
| 2026 | @item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t) | ||
| 2027 | -@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}} | ||
| 2028 | @end itemize | ||
| 2029 | |||
| 2030 | |||
| 2031 | @itemize @bullet | ||
| 2032 | @item int64x1_t vorr_s64 (int64x1_t, int64x1_t) | ||
| 2033 | -@*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}} | ||
| 2034 | @end itemize | ||
| 2035 | |||
| 2036 | |||
| 2037 | @@ -9927,13 +9905,11 @@ | ||
| 2038 | |||
| 2039 | @itemize @bullet | ||
| 2040 | @item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t) | ||
| 2041 | -@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}} | ||
| 2042 | @end itemize | ||
| 2043 | |||
| 2044 | |||
| 2045 | @itemize @bullet | ||
| 2046 | @item int64x1_t veor_s64 (int64x1_t, int64x1_t) | ||
| 2047 | -@*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}} | ||
| 2048 | @end itemize | ||
| 2049 | |||
| 2050 | |||
| 2051 | @@ -10027,13 +10003,11 @@ | ||
| 2052 | |||
| 2053 | @itemize @bullet | ||
| 2054 | @item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t) | ||
| 2055 | -@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}} | ||
| 2056 | @end itemize | ||
| 2057 | |||
| 2058 | |||
| 2059 | @itemize @bullet | ||
| 2060 | @item int64x1_t vbic_s64 (int64x1_t, int64x1_t) | ||
| 2061 | -@*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}} | ||
| 2062 | @end itemize | ||
| 2063 | |||
| 2064 | |||
| 2065 | @@ -10127,13 +10101,11 @@ | ||
| 2066 | |||
| 2067 | @itemize @bullet | ||
| 2068 | @item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t) | ||
| 2069 | -@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}} | ||
| 2070 | @end itemize | ||
| 2071 | |||
| 2072 | |||
| 2073 | @itemize @bullet | ||
| 2074 | @item int64x1_t vorn_s64 (int64x1_t, int64x1_t) | ||
| 2075 | -@*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}} | ||
| 2076 | @end itemize | ||
| 2077 | |||
| 2078 | |||
| 2079 | |||
| 2080 | === added file 'gcc/testsuite/gcc.target/arm/neon-vadds64.c' | ||
| 2081 | --- old/gcc/testsuite/gcc.target/arm/neon-vadds64.c 1970-01-01 00:00:00 +0000 | ||
| 2082 | +++ new/gcc/testsuite/gcc.target/arm/neon-vadds64.c 2010-07-29 15:59:12 +0000 | ||
| 2083 | @@ -0,0 +1,21 @@ | ||
| 2084 | +/* Test the `vadd_s64' ARM Neon intrinsic. */ | ||
| 2085 | + | ||
| 2086 | +/* { dg-do run } */ | ||
| 2087 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2088 | +/* { dg-options "-O0" } */ | ||
| 2089 | +/* { dg-add-options arm_neon } */ | ||
| 2090 | + | ||
| 2091 | +#include "arm_neon.h" | ||
| 2092 | +#include <stdlib.h> | ||
| 2093 | + | ||
| 2094 | +int main (void) | ||
| 2095 | +{ | ||
| 2096 | + int64x1_t out_int64x1_t = 0; | ||
| 2097 | + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; | ||
| 2098 | + int64x1_t arg1_int64x1_t = (int64x1_t)0x00000000deadbeefLL; | ||
| 2099 | + | ||
| 2100 | + out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 2101 | + if (out_int64x1_t != (int64x1_t)0xdeadbeefdeadbeefLL) | ||
| 2102 | + abort(); | ||
| 2103 | + return 0; | ||
| 2104 | +} | ||
| 2105 | |||
| 2106 | === added file 'gcc/testsuite/gcc.target/arm/neon-vaddu64.c' | ||
| 2107 | --- old/gcc/testsuite/gcc.target/arm/neon-vaddu64.c 1970-01-01 00:00:00 +0000 | ||
| 2108 | +++ new/gcc/testsuite/gcc.target/arm/neon-vaddu64.c 2010-07-29 15:59:12 +0000 | ||
| 2109 | @@ -0,0 +1,21 @@ | ||
| 2110 | +/* Test the `vadd_u64' ARM Neon intrinsic. */ | ||
| 2111 | + | ||
| 2112 | +/* { dg-do run } */ | ||
| 2113 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2114 | +/* { dg-options "-O0" } */ | ||
| 2115 | +/* { dg-add-options arm_neon } */ | ||
| 2116 | + | ||
| 2117 | +#include "arm_neon.h" | ||
| 2118 | +#include <stdlib.h> | ||
| 2119 | + | ||
| 2120 | +int main (void) | ||
| 2121 | +{ | ||
| 2122 | + uint64x1_t out_uint64x1_t = 0; | ||
| 2123 | + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; | ||
| 2124 | + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x00000000deadbeefLL; | ||
| 2125 | + | ||
| 2126 | + out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 2127 | + if (out_uint64x1_t != (uint64x1_t)0xdeadbeefdeadbeefLL) | ||
| 2128 | + abort(); | ||
| 2129 | + return 0; | ||
| 2130 | +} | ||
| 2131 | |||
| 2132 | === added file 'gcc/testsuite/gcc.target/arm/neon-vands64.c' | ||
| 2133 | --- old/gcc/testsuite/gcc.target/arm/neon-vands64.c 1970-01-01 00:00:00 +0000 | ||
| 2134 | +++ new/gcc/testsuite/gcc.target/arm/neon-vands64.c 2010-07-29 15:59:12 +0000 | ||
| 2135 | @@ -0,0 +1,21 @@ | ||
| 2136 | +/* Test the `vand_s64' ARM Neon intrinsic. */ | ||
| 2137 | + | ||
| 2138 | +/* { dg-do run } */ | ||
| 2139 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2140 | +/* { dg-options "-O0" } */ | ||
| 2141 | +/* { dg-add-options arm_neon } */ | ||
| 2142 | + | ||
| 2143 | +#include "arm_neon.h" | ||
| 2144 | +#include <stdlib.h> | ||
| 2145 | + | ||
| 2146 | +int main (void) | ||
| 2147 | +{ | ||
| 2148 | + int64x1_t out_int64x1_t = 0; | ||
| 2149 | + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; | ||
| 2150 | + int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; | ||
| 2151 | + | ||
| 2152 | + out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 2153 | + if (out_int64x1_t != (int64x1_t)0xdead000000000000LL) | ||
| 2154 | + abort(); | ||
| 2155 | + return 0; | ||
| 2156 | +} | ||
| 2157 | |||
| 2158 | === added file 'gcc/testsuite/gcc.target/arm/neon-vandu64.c' | ||
| 2159 | --- old/gcc/testsuite/gcc.target/arm/neon-vandu64.c 1970-01-01 00:00:00 +0000 | ||
| 2160 | +++ new/gcc/testsuite/gcc.target/arm/neon-vandu64.c 2010-07-29 15:59:12 +0000 | ||
| 2161 | @@ -0,0 +1,21 @@ | ||
| 2162 | +/* Test the `vand_u64' ARM Neon intrinsic. */ | ||
| 2163 | + | ||
| 2164 | +/* { dg-do run } */ | ||
| 2165 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2166 | +/* { dg-options "-O0" } */ | ||
| 2167 | +/* { dg-add-options arm_neon } */ | ||
| 2168 | + | ||
| 2169 | +#include "arm_neon.h" | ||
| 2170 | +#include <stdlib.h> | ||
| 2171 | + | ||
| 2172 | +int main (void) | ||
| 2173 | +{ | ||
| 2174 | + uint64x1_t out_uint64x1_t = 0; | ||
| 2175 | + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; | ||
| 2176 | + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; | ||
| 2177 | + | ||
| 2178 | + out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 2179 | + if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL) | ||
| 2180 | + abort(); | ||
| 2181 | + return 0; | ||
| 2182 | +} | ||
| 2183 | |||
| 2184 | === added file 'gcc/testsuite/gcc.target/arm/neon-vbics64.c' | ||
| 2185 | --- old/gcc/testsuite/gcc.target/arm/neon-vbics64.c 1970-01-01 00:00:00 +0000 | ||
| 2186 | +++ new/gcc/testsuite/gcc.target/arm/neon-vbics64.c 2010-07-29 15:59:12 +0000 | ||
| 2187 | @@ -0,0 +1,21 @@ | ||
| 2188 | +/* Test the `vbic_s64' ARM Neon intrinsic. */ | ||
| 2189 | + | ||
| 2190 | +/* { dg-do run } */ | ||
| 2191 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2192 | +/* { dg-options "-O0" } */ | ||
| 2193 | +/* { dg-add-options arm_neon } */ | ||
| 2194 | + | ||
| 2195 | +#include "arm_neon.h" | ||
| 2196 | +#include <stdlib.h> | ||
| 2197 | + | ||
| 2198 | +int main (void) | ||
| 2199 | +{ | ||
| 2200 | + int64x1_t out_int64x1_t = 0; | ||
| 2201 | + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; | ||
| 2202 | + int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL); | ||
| 2203 | + | ||
| 2204 | + out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 2205 | + if (out_int64x1_t != (int64x1_t)0xdead000000000000LL) | ||
| 2206 | + abort(); | ||
| 2207 | + return 0; | ||
| 2208 | +} | ||
| 2209 | |||
| 2210 | === added file 'gcc/testsuite/gcc.target/arm/neon-vbicu64.c' | ||
| 2211 | --- old/gcc/testsuite/gcc.target/arm/neon-vbicu64.c 1970-01-01 00:00:00 +0000 | ||
| 2212 | +++ new/gcc/testsuite/gcc.target/arm/neon-vbicu64.c 2010-07-29 15:59:12 +0000 | ||
| 2213 | @@ -0,0 +1,21 @@ | ||
| 2214 | +/* Test the `vbic_u64' ARM Neon intrinsic. */ | ||
| 2215 | + | ||
| 2216 | +/* { dg-do run } */ | ||
| 2217 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2218 | +/* { dg-options "-O0" } */ | ||
| 2219 | +/* { dg-add-options arm_neon } */ | ||
| 2220 | + | ||
| 2221 | +#include "arm_neon.h" | ||
| 2222 | +#include <stdlib.h> | ||
| 2223 | + | ||
| 2224 | +int main (void) | ||
| 2225 | +{ | ||
| 2226 | + uint64x1_t out_uint64x1_t = 0; | ||
| 2227 | + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; | ||
| 2228 | + uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL); | ||
| 2229 | + | ||
| 2230 | + out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 2231 | + if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL) | ||
| 2232 | + abort(); | ||
| 2233 | + return 0; | ||
| 2234 | +} | ||
| 2235 | |||
| 2236 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c' | ||
| 2237 | --- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c 1970-01-01 00:00:00 +0000 | ||
| 2238 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c 2010-07-29 15:59:12 +0000 | ||
| 2239 | @@ -0,0 +1,22 @@ | ||
| 2240 | +/* Test the `vdupq_lanes64' ARM Neon intrinsic. */ | ||
| 2241 | + | ||
| 2242 | +/* { dg-do run } */ | ||
| 2243 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2244 | +/* { dg-options "-O0" } */ | ||
| 2245 | +/* { dg-add-options arm_neon } */ | ||
| 2246 | + | ||
| 2247 | +#include "arm_neon.h" | ||
| 2248 | +#include <stdlib.h> | ||
| 2249 | + | ||
| 2250 | +int main (void) | ||
| 2251 | +{ | ||
| 2252 | + int64x2_t out_int64x2_t = {0, 0}; | ||
| 2253 | + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; | ||
| 2254 | + | ||
| 2255 | + out_int64x2_t = vdupq_lane_s64 ((int64x1_t)arg0_int64_t, 0); | ||
| 2256 | + if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) | ||
| 2257 | + abort(); | ||
| 2258 | + if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) | ||
| 2259 | + abort(); | ||
| 2260 | + return 0; | ||
| 2261 | +} | ||
| 2262 | |||
| 2263 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c' | ||
| 2264 | --- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c 1970-01-01 00:00:00 +0000 | ||
| 2265 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c 2010-07-29 15:59:12 +0000 | ||
| 2266 | @@ -0,0 +1,22 @@ | ||
| 2267 | +/* Test the `vdupq_laneu64' ARM Neon intrinsic. */ | ||
| 2268 | + | ||
| 2269 | +/* { dg-do run } */ | ||
| 2270 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2271 | +/* { dg-options "-O0" } */ | ||
| 2272 | +/* { dg-add-options arm_neon } */ | ||
| 2273 | + | ||
| 2274 | +#include "arm_neon.h" | ||
| 2275 | +#include <stdlib.h> | ||
| 2276 | + | ||
| 2277 | +int main (void) | ||
| 2278 | +{ | ||
| 2279 | + uint64x2_t out_uint64x2_t = {0, 0}; | ||
| 2280 | + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; | ||
| 2281 | + | ||
| 2282 | + out_uint64x2_t = vdupq_lane_u64 ((uint64x1_t)arg0_uint64_t, 0); | ||
| 2283 | + if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) | ||
| 2284 | + abort(); | ||
| 2285 | + if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) | ||
| 2286 | + abort(); | ||
| 2287 | + return 0; | ||
| 2288 | +} | ||
| 2289 | |||
| 2290 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c' | ||
| 2291 | --- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c 1970-01-01 00:00:00 +0000 | ||
| 2292 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c 2010-07-29 15:59:12 +0000 | ||
| 2293 | @@ -0,0 +1,22 @@ | ||
| 2294 | +/* Test the `vdupq_ns64' ARM Neon intrinsic. */ | ||
| 2295 | + | ||
| 2296 | +/* { dg-do run } */ | ||
| 2297 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2298 | +/* { dg-options "-O0" } */ | ||
| 2299 | +/* { dg-add-options arm_neon } */ | ||
| 2300 | + | ||
| 2301 | +#include "arm_neon.h" | ||
| 2302 | +#include <stdlib.h> | ||
| 2303 | + | ||
| 2304 | +int main (void) | ||
| 2305 | +{ | ||
| 2306 | + int64x2_t out_int64x2_t = {0, 0}; | ||
| 2307 | + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; | ||
| 2308 | + | ||
| 2309 | + out_int64x2_t = vdupq_n_s64 (arg0_int64_t); | ||
| 2310 | + if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) | ||
| 2311 | + abort(); | ||
| 2312 | + if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) | ||
| 2313 | + abort(); | ||
| 2314 | + return 0; | ||
| 2315 | +} | ||
| 2316 | |||
| 2317 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c' | ||
| 2318 | --- old/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c 1970-01-01 00:00:00 +0000 | ||
| 2319 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c 2010-07-29 15:59:12 +0000 | ||
| 2320 | @@ -0,0 +1,22 @@ | ||
| 2321 | +/* Test the `vdupq_nu64' ARM Neon intrinsic. */ | ||
| 2322 | + | ||
| 2323 | +/* { dg-do run } */ | ||
| 2324 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2325 | +/* { dg-options "-O0" } */ | ||
| 2326 | +/* { dg-add-options arm_neon } */ | ||
| 2327 | + | ||
| 2328 | +#include "arm_neon.h" | ||
| 2329 | +#include <stdlib.h> | ||
| 2330 | + | ||
| 2331 | +int main (void) | ||
| 2332 | +{ | ||
| 2333 | + uint64x2_t out_uint64x2_t = {0, 0}; | ||
| 2334 | + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; | ||
| 2335 | + | ||
| 2336 | + out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t); | ||
| 2337 | + if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) | ||
| 2338 | + abort(); | ||
| 2339 | + if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) | ||
| 2340 | + abort(); | ||
| 2341 | + return 0; | ||
| 2342 | +} | ||
| 2343 | |||
| 2344 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c' | ||
| 2345 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c 1970-01-01 00:00:00 +0000 | ||
| 2346 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c 2010-07-29 15:59:12 +0000 | ||
| 2347 | @@ -0,0 +1,20 @@ | ||
| 2348 | +/* Test the `vdup_ns64' ARM Neon intrinsic. */ | ||
| 2349 | + | ||
| 2350 | +/* { dg-do run } */ | ||
| 2351 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2352 | +/* { dg-options "-O0" } */ | ||
| 2353 | +/* { dg-add-options arm_neon } */ | ||
| 2354 | + | ||
| 2355 | +#include "arm_neon.h" | ||
| 2356 | +#include <stdlib.h> | ||
| 2357 | + | ||
| 2358 | +int main (void) | ||
| 2359 | +{ | ||
| 2360 | + int64x1_t out_int64x1_t = 0; | ||
| 2361 | + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; | ||
| 2362 | + | ||
| 2363 | + out_int64x1_t = vdup_n_s64 (arg0_int64_t); | ||
| 2364 | + if ((int64_t)out_int64x1_t != arg0_int64_t) | ||
| 2365 | + abort(); | ||
| 2366 | + return 0; | ||
| 2367 | +} | ||
| 2368 | |||
| 2369 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c' | ||
| 2370 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c 1970-01-01 00:00:00 +0000 | ||
| 2371 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c 2010-07-29 15:59:12 +0000 | ||
| 2372 | @@ -0,0 +1,20 @@ | ||
| 2373 | +/* Test the `vdup_nu64' ARM Neon intrinsic. */ | ||
| 2374 | + | ||
| 2375 | +/* { dg-do run } */ | ||
| 2376 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2377 | +/* { dg-options "-O0" } */ | ||
| 2378 | +/* { dg-add-options arm_neon } */ | ||
| 2379 | + | ||
| 2380 | +#include "arm_neon.h" | ||
| 2381 | +#include <stdlib.h> | ||
| 2382 | + | ||
| 2383 | +int main (void) | ||
| 2384 | +{ | ||
| 2385 | + uint64x1_t out_uint64x1_t = 0; | ||
| 2386 | + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; | ||
| 2387 | + | ||
| 2388 | + out_uint64x1_t = vdup_n_u64 (arg0_uint64_t); | ||
| 2389 | + if ((uint64_t)out_uint64x1_t != arg0_uint64_t) | ||
| 2390 | + abort(); | ||
| 2391 | + return 0; | ||
| 2392 | +} | ||
| 2393 | |||
| 2394 | === added file 'gcc/testsuite/gcc.target/arm/neon-veors64.c' | ||
| 2395 | --- old/gcc/testsuite/gcc.target/arm/neon-veors64.c 1970-01-01 00:00:00 +0000 | ||
| 2396 | +++ new/gcc/testsuite/gcc.target/arm/neon-veors64.c 2010-07-29 15:59:12 +0000 | ||
| 2397 | @@ -0,0 +1,21 @@ | ||
| 2398 | +/* Test the `veor_s64' ARM Neon intrinsic. */ | ||
| 2399 | + | ||
| 2400 | +/* { dg-do run } */ | ||
| 2401 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2402 | +/* { dg-options "-O0" } */ | ||
| 2403 | +/* { dg-add-options arm_neon } */ | ||
| 2404 | + | ||
| 2405 | +#include "arm_neon.h" | ||
| 2406 | +#include <stdlib.h> | ||
| 2407 | + | ||
| 2408 | +int main (void) | ||
| 2409 | +{ | ||
| 2410 | + int64x1_t out_int64x1_t = 0; | ||
| 2411 | + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; | ||
| 2412 | + int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; | ||
| 2413 | + | ||
| 2414 | + out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 2415 | + if (out_int64x1_t != (int64x1_t)0x0000beef0000beefLL) | ||
| 2416 | + abort(); | ||
| 2417 | + return 0; | ||
| 2418 | +} | ||
| 2419 | |||
| 2420 | === added file 'gcc/testsuite/gcc.target/arm/neon-veoru64.c' | ||
| 2421 | --- old/gcc/testsuite/gcc.target/arm/neon-veoru64.c 1970-01-01 00:00:00 +0000 | ||
| 2422 | +++ new/gcc/testsuite/gcc.target/arm/neon-veoru64.c 2010-07-29 15:59:12 +0000 | ||
| 2423 | @@ -0,0 +1,21 @@ | ||
| 2424 | +/* Test the `veor_u64' ARM Neon intrinsic. */ | ||
| 2425 | + | ||
| 2426 | +/* { dg-do run } */ | ||
| 2427 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2428 | +/* { dg-options "-O0" } */ | ||
| 2429 | +/* { dg-add-options arm_neon } */ | ||
| 2430 | + | ||
| 2431 | +#include "arm_neon.h" | ||
| 2432 | +#include <stdlib.h> | ||
| 2433 | + | ||
| 2434 | +int main (void) | ||
| 2435 | +{ | ||
| 2436 | + uint64x1_t out_uint64x1_t = 0; | ||
| 2437 | + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; | ||
| 2438 | + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; | ||
| 2439 | + | ||
| 2440 | + out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 2441 | + if (out_uint64x1_t != (uint64x1_t)0x0000beef0000beefLL) | ||
| 2442 | + abort(); | ||
| 2443 | + return 0; | ||
| 2444 | +} | ||
| 2445 | |||
| 2446 | === added file 'gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c' | ||
| 2447 | --- old/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c 1970-01-01 00:00:00 +0000 | ||
| 2448 | +++ new/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c 2010-07-29 15:59:12 +0000 | ||
| 2449 | @@ -0,0 +1,20 @@ | ||
| 2450 | +/* Test the `vget_lane_s64' ARM Neon intrinsic. */ | ||
| 2451 | + | ||
| 2452 | +/* { dg-do run } */ | ||
| 2453 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2454 | +/* { dg-options "-O0" } */ | ||
| 2455 | +/* { dg-add-options arm_neon } */ | ||
| 2456 | + | ||
| 2457 | +#include "arm_neon.h" | ||
| 2458 | +#include <stdlib.h> | ||
| 2459 | + | ||
| 2460 | +int main (void) | ||
| 2461 | +{ | ||
| 2462 | + int64_t out_int64_t = 0; | ||
| 2463 | + int64x1_t arg0_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL; | ||
| 2464 | + | ||
| 2465 | + out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0); | ||
| 2466 | + if (out_int64_t != (int64_t)arg0_int64x1_t) | ||
| 2467 | + abort(); | ||
| 2468 | + return 0; | ||
| 2469 | +} | ||
| 2470 | |||
| 2471 | === added file 'gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c' | ||
| 2472 | --- old/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c 1970-01-01 00:00:00 +0000 | ||
| 2473 | +++ new/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c 2010-07-29 15:59:12 +0000 | ||
| 2474 | @@ -0,0 +1,20 @@ | ||
| 2475 | +/* Test the `vget_lane_u64' ARM Neon intrinsic. */ | ||
| 2476 | + | ||
| 2477 | +/* { dg-do run } */ | ||
| 2478 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2479 | +/* { dg-options "-O0" } */ | ||
| 2480 | +/* { dg-add-options arm_neon } */ | ||
| 2481 | + | ||
| 2482 | +#include "arm_neon.h" | ||
| 2483 | +#include <stdlib.h> | ||
| 2484 | + | ||
| 2485 | +int main (void) | ||
| 2486 | +{ | ||
| 2487 | + uint64_t out_uint64_t = 0; | ||
| 2488 | + uint64x1_t arg0_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL; | ||
| 2489 | + | ||
| 2490 | + out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0); | ||
| 2491 | + if (out_uint64_t != (uint64_t)arg0_uint64x1_t) | ||
| 2492 | + abort(); | ||
| 2493 | + return 0; | ||
| 2494 | +} | ||
| 2495 | |||
| 2496 | === modified file 'gcc/testsuite/gcc.target/arm/neon-vmla-1.c' | ||
| 2497 | --- old/gcc/testsuite/gcc.target/arm/neon-vmla-1.c 2010-07-29 15:38:15 +0000 | ||
| 2498 | +++ new/gcc/testsuite/gcc.target/arm/neon-vmla-1.c 2010-07-29 15:59:12 +0000 | ||
| 2499 | @@ -1,5 +1,5 @@ | ||
| 2500 | /* { dg-require-effective-target arm_neon_hw } */ | ||
| 2501 | -/* { dg-options "-O2 -ftree-vectorize" } */ | ||
| 2502 | +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ | ||
| 2503 | /* { dg-add-options arm_neon } */ | ||
| 2504 | /* { dg-final { scan-assembler "vmla\\.f32" } } */ | ||
| 2505 | |||
| 2506 | |||
| 2507 | === modified file 'gcc/testsuite/gcc.target/arm/neon-vmls-1.c' | ||
| 2508 | --- old/gcc/testsuite/gcc.target/arm/neon-vmls-1.c 2010-07-29 15:38:15 +0000 | ||
| 2509 | +++ new/gcc/testsuite/gcc.target/arm/neon-vmls-1.c 2010-07-29 15:59:12 +0000 | ||
| 2510 | @@ -1,5 +1,5 @@ | ||
| 2511 | /* { dg-require-effective-target arm_neon_hw } */ | ||
| 2512 | -/* { dg-options "-O2 -ftree-vectorize" } */ | ||
| 2513 | +/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ | ||
| 2514 | /* { dg-add-options arm_neon } */ | ||
| 2515 | /* { dg-final { scan-assembler "vmls\\.f32" } } */ | ||
| 2516 | |||
| 2517 | |||
| 2518 | === added file 'gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c' | ||
| 2519 | --- old/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c 1970-01-01 00:00:00 +0000 | ||
| 2520 | +++ new/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c 2010-07-29 15:59:12 +0000 | ||
| 2521 | @@ -0,0 +1,22 @@ | ||
| 2522 | +/* Test the `vmovq_ns64' ARM Neon intrinsic. */ | ||
| 2523 | + | ||
| 2524 | +/* { dg-do run } */ | ||
| 2525 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2526 | +/* { dg-options "-O0" } */ | ||
| 2527 | +/* { dg-add-options arm_neon } */ | ||
| 2528 | + | ||
| 2529 | +#include "arm_neon.h" | ||
| 2530 | +#include <stdlib.h> | ||
| 2531 | + | ||
| 2532 | +int main (void) | ||
| 2533 | +{ | ||
| 2534 | + int64x2_t out_int64x2_t = {0, 0}; | ||
| 2535 | + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; | ||
| 2536 | + | ||
| 2537 | + out_int64x2_t = vmovq_n_s64 (arg0_int64_t); | ||
| 2538 | + if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t) | ||
| 2539 | + abort(); | ||
| 2540 | + if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t) | ||
| 2541 | + abort(); | ||
| 2542 | + return 0; | ||
| 2543 | +} | ||
| 2544 | |||
| 2545 | === added file 'gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c' | ||
| 2546 | --- old/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c 1970-01-01 00:00:00 +0000 | ||
| 2547 | +++ new/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c 2010-07-29 15:59:12 +0000 | ||
| 2548 | @@ -0,0 +1,23 @@ | ||
| 2549 | +/* Test the `vmovq_nu64' ARM Neon intrinsic. */ | ||
| 2550 | + | ||
| 2551 | +/* { dg-do run } */ | ||
| 2552 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2553 | +/* { dg-options "-O0" } */ | ||
| 2554 | +/* { dg-add-options arm_neon } */ | ||
| 2555 | + | ||
| 2556 | +#include "arm_neon.h" | ||
| 2557 | +#include <stdlib.h> | ||
| 2558 | + | ||
| 2559 | +int main (void) | ||
| 2560 | +{ | ||
| 2561 | + uint64x2_t out_uint64x2_t = {0, 0}; | ||
| 2562 | + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; | ||
| 2563 | + | ||
| 2564 | + out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t); | ||
| 2565 | + if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t) | ||
| 2566 | + abort(); | ||
| 2567 | + if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t) | ||
| 2568 | + abort(); | ||
| 2569 | + return 0; | ||
| 2570 | +} | ||
| 2571 | + | ||
| 2572 | |||
| 2573 | === added file 'gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c' | ||
| 2574 | --- old/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c 1970-01-01 00:00:00 +0000 | ||
| 2575 | +++ new/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c 2010-07-29 15:59:12 +0000 | ||
| 2576 | @@ -0,0 +1,20 @@ | ||
| 2577 | +/* Test the `vmov_ns64' ARM Neon intrinsic. */ | ||
| 2578 | + | ||
| 2579 | +/* { dg-do run } */ | ||
| 2580 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2581 | +/* { dg-options "-O0" } */ | ||
| 2582 | +/* { dg-add-options arm_neon } */ | ||
| 2583 | + | ||
| 2584 | +#include "arm_neon.h" | ||
| 2585 | +#include <stdlib.h> | ||
| 2586 | + | ||
| 2587 | +int main (void) | ||
| 2588 | +{ | ||
| 2589 | + int64x1_t out_int64x1_t = 0; | ||
| 2590 | + int64_t arg0_int64_t = (int64_t) 0xdeadbeef; | ||
| 2591 | + | ||
| 2592 | + out_int64x1_t = vmov_n_s64 (arg0_int64_t); | ||
| 2593 | + if ((int64_t)out_int64x1_t != arg0_int64_t) | ||
| 2594 | + abort(); | ||
| 2595 | + return 0; | ||
| 2596 | +} | ||
| 2597 | |||
| 2598 | === added file 'gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c' | ||
| 2599 | --- old/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c 1970-01-01 00:00:00 +0000 | ||
| 2600 | +++ new/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c 2010-07-29 15:59:12 +0000 | ||
| 2601 | @@ -0,0 +1,20 @@ | ||
| 2602 | +/* Test the `vmov_nu64' ARM Neon intrinsic. */ | ||
| 2603 | + | ||
| 2604 | +/* { dg-do run } */ | ||
| 2605 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2606 | +/* { dg-options "-O0" } */ | ||
| 2607 | +/* { dg-add-options arm_neon } */ | ||
| 2608 | + | ||
| 2609 | +#include "arm_neon.h" | ||
| 2610 | +#include <stdlib.h> | ||
| 2611 | + | ||
| 2612 | +int main (void) | ||
| 2613 | +{ | ||
| 2614 | + uint64x1_t out_uint64x1_t = 0; | ||
| 2615 | + uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef; | ||
| 2616 | + | ||
| 2617 | + out_uint64x1_t = vmov_n_u64 (arg0_uint64_t); | ||
| 2618 | + if ((uint64_t)out_uint64x1_t != arg0_uint64_t) | ||
| 2619 | + abort(); | ||
| 2620 | + return 0; | ||
| 2621 | +} | ||
| 2622 | |||
| 2623 | === added file 'gcc/testsuite/gcc.target/arm/neon-vorns64.c' | ||
| 2624 | --- old/gcc/testsuite/gcc.target/arm/neon-vorns64.c 1970-01-01 00:00:00 +0000 | ||
| 2625 | +++ new/gcc/testsuite/gcc.target/arm/neon-vorns64.c 2010-07-29 15:59:12 +0000 | ||
| 2626 | @@ -0,0 +1,21 @@ | ||
| 2627 | +/* Test the `vorn_s64' ARM Neon intrinsic. */ | ||
| 2628 | + | ||
| 2629 | +/* { dg-do run } */ | ||
| 2630 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2631 | +/* { dg-options "-O0" } */ | ||
| 2632 | +/* { dg-add-options arm_neon } */ | ||
| 2633 | + | ||
| 2634 | +#include "arm_neon.h" | ||
| 2635 | +#include <stdlib.h> | ||
| 2636 | + | ||
| 2637 | +int main (void) | ||
| 2638 | +{ | ||
| 2639 | + int64x1_t out_int64x1_t = 0; | ||
| 2640 | + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; | ||
| 2641 | + int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL); | ||
| 2642 | + | ||
| 2643 | + out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 2644 | + if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL) | ||
| 2645 | + abort(); | ||
| 2646 | + return 0; | ||
| 2647 | +} | ||
| 2648 | |||
| 2649 | === added file 'gcc/testsuite/gcc.target/arm/neon-vornu64.c' | ||
| 2650 | --- old/gcc/testsuite/gcc.target/arm/neon-vornu64.c 1970-01-01 00:00:00 +0000 | ||
| 2651 | +++ new/gcc/testsuite/gcc.target/arm/neon-vornu64.c 2010-07-29 15:59:12 +0000 | ||
| 2652 | @@ -0,0 +1,21 @@ | ||
| 2653 | +/* Test the `vorn_u64' ARM Neon intrinsic. */ | ||
| 2654 | + | ||
| 2655 | +/* { dg-do run } */ | ||
| 2656 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2657 | +/* { dg-options "-O0" } */ | ||
| 2658 | +/* { dg-add-options arm_neon } */ | ||
| 2659 | + | ||
| 2660 | +#include "arm_neon.h" | ||
| 2661 | +#include <stdlib.h> | ||
| 2662 | + | ||
| 2663 | +int main (void) | ||
| 2664 | +{ | ||
| 2665 | + uint64x1_t out_uint64x1_t = 0; | ||
| 2666 | + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; | ||
| 2667 | + uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL); | ||
| 2668 | + | ||
| 2669 | + out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 2670 | + if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL) | ||
| 2671 | + abort(); | ||
| 2672 | + return 0; | ||
| 2673 | +} | ||
| 2674 | |||
| 2675 | === added file 'gcc/testsuite/gcc.target/arm/neon-vorrs64.c' | ||
| 2676 | --- old/gcc/testsuite/gcc.target/arm/neon-vorrs64.c 1970-01-01 00:00:00 +0000 | ||
| 2677 | +++ new/gcc/testsuite/gcc.target/arm/neon-vorrs64.c 2010-07-29 15:59:12 +0000 | ||
| 2678 | @@ -0,0 +1,21 @@ | ||
| 2679 | +/* Test the `vorr_s64' ARM Neon intrinsic. */ | ||
| 2680 | + | ||
| 2681 | +/* { dg-do run } */ | ||
| 2682 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2683 | +/* { dg-options "-O0" } */ | ||
| 2684 | +/* { dg-add-options arm_neon } */ | ||
| 2685 | + | ||
| 2686 | +#include "arm_neon.h" | ||
| 2687 | +#include <stdlib.h> | ||
| 2688 | + | ||
| 2689 | +int main (void) | ||
| 2690 | +{ | ||
| 2691 | + int64x1_t out_int64x1_t = 0; | ||
| 2692 | + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL; | ||
| 2693 | + int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL; | ||
| 2694 | + | ||
| 2695 | + out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 2696 | + if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL) | ||
| 2697 | + abort(); | ||
| 2698 | + return 0; | ||
| 2699 | +} | ||
| 2700 | |||
| 2701 | === added file 'gcc/testsuite/gcc.target/arm/neon-vorru64.c' | ||
| 2702 | --- old/gcc/testsuite/gcc.target/arm/neon-vorru64.c 1970-01-01 00:00:00 +0000 | ||
| 2703 | +++ new/gcc/testsuite/gcc.target/arm/neon-vorru64.c 2010-07-29 15:59:12 +0000 | ||
| 2704 | @@ -0,0 +1,21 @@ | ||
| 2705 | +/* Test the `vorr_u64' ARM Neon intrinsic. */ | ||
| 2706 | + | ||
| 2707 | +/* { dg-do run } */ | ||
| 2708 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2709 | +/* { dg-options "-O0" } */ | ||
| 2710 | +/* { dg-add-options arm_neon } */ | ||
| 2711 | + | ||
| 2712 | +#include "arm_neon.h" | ||
| 2713 | +#include <stdlib.h> | ||
| 2714 | + | ||
| 2715 | +int main (void) | ||
| 2716 | +{ | ||
| 2717 | + uint64x1_t out_uint64x1_t = 0; | ||
| 2718 | + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL; | ||
| 2719 | + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL; | ||
| 2720 | + | ||
| 2721 | + out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 2722 | + if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL) | ||
| 2723 | + abort(); | ||
| 2724 | + return 0; | ||
| 2725 | +} | ||
| 2726 | |||
| 2727 | === added file 'gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c' | ||
| 2728 | --- old/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c 1970-01-01 00:00:00 +0000 | ||
| 2729 | +++ new/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c 2010-07-29 15:59:12 +0000 | ||
| 2730 | @@ -0,0 +1,21 @@ | ||
| 2731 | +/* Test the `vset_lane_s64' ARM Neon intrinsic. */ | ||
| 2732 | + | ||
| 2733 | +/* { dg-do run } */ | ||
| 2734 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2735 | +/* { dg-options "-O0" } */ | ||
| 2736 | +/* { dg-add-options arm_neon } */ | ||
| 2737 | + | ||
| 2738 | +#include "arm_neon.h" | ||
| 2739 | +#include <stdlib.h> | ||
| 2740 | + | ||
| 2741 | +int main (void) | ||
| 2742 | +{ | ||
| 2743 | + int64x1_t out_int64x1_t = 0; | ||
| 2744 | + int64_t arg0_int64_t = 0xf00f00f00LL; | ||
| 2745 | + int64x1_t arg1_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL; | ||
| 2746 | + | ||
| 2747 | + out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); | ||
| 2748 | + if ((int64_t)out_int64x1_t != arg0_int64_t) | ||
| 2749 | + abort(); | ||
| 2750 | + return 0; | ||
| 2751 | +} | ||
| 2752 | |||
| 2753 | === added file 'gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c' | ||
| 2754 | --- old/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c 1970-01-01 00:00:00 +0000 | ||
| 2755 | +++ new/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c 2010-07-29 15:59:12 +0000 | ||
| 2756 | @@ -0,0 +1,21 @@ | ||
| 2757 | +/* Test the `vset_lane_s64' ARM Neon intrinsic. */ | ||
| 2758 | + | ||
| 2759 | +/* { dg-do run } */ | ||
| 2760 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2761 | +/* { dg-options "-O0" } */ | ||
| 2762 | +/* { dg-add-options arm_neon } */ | ||
| 2763 | + | ||
| 2764 | +#include "arm_neon.h" | ||
| 2765 | +#include <stdlib.h> | ||
| 2766 | + | ||
| 2767 | +int main (void) | ||
| 2768 | +{ | ||
| 2769 | + uint64x1_t out_uint64x1_t = 0; | ||
| 2770 | + uint64_t arg0_uint64_t = 0xf00f00f00LL; | ||
| 2771 | + uint64x1_t arg1_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL; | ||
| 2772 | + | ||
| 2773 | + out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); | ||
| 2774 | + if ((uint64_t)out_uint64x1_t != arg0_uint64_t) | ||
| 2775 | + abort(); | ||
| 2776 | + return 0; | ||
| 2777 | +} | ||
| 2778 | |||
| 2779 | === added file 'gcc/testsuite/gcc.target/arm/neon-vsubs64.c' | ||
| 2780 | --- old/gcc/testsuite/gcc.target/arm/neon-vsubs64.c 1970-01-01 00:00:00 +0000 | ||
| 2781 | +++ new/gcc/testsuite/gcc.target/arm/neon-vsubs64.c 2010-07-29 15:59:12 +0000 | ||
| 2782 | @@ -0,0 +1,21 @@ | ||
| 2783 | +/* Test the `vsub_s64' ARM Neon intrinsic. */ | ||
| 2784 | + | ||
| 2785 | +/* { dg-do run } */ | ||
| 2786 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2787 | +/* { dg-options "-O0" } */ | ||
| 2788 | +/* { dg-add-options arm_neon } */ | ||
| 2789 | + | ||
| 2790 | +#include "arm_neon.h" | ||
| 2791 | +#include <stdlib.h> | ||
| 2792 | + | ||
| 2793 | +int main (void) | ||
| 2794 | +{ | ||
| 2795 | + int64x1_t out_int64x1_t = 0; | ||
| 2796 | + int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeefdeadbeefLL; | ||
| 2797 | + int64x1_t arg1_int64x1_t = (int64x1_t)0x0000beefdead0000LL; | ||
| 2798 | + | ||
| 2799 | + out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 2800 | + if (out_int64x1_t != (int64x1_t)0xdead00000000beefLL) | ||
| 2801 | + abort(); | ||
| 2802 | + return 0; | ||
| 2803 | +} | ||
| 2804 | |||
| 2805 | === added file 'gcc/testsuite/gcc.target/arm/neon-vsubu64.c' | ||
| 2806 | --- old/gcc/testsuite/gcc.target/arm/neon-vsubu64.c 1970-01-01 00:00:00 +0000 | ||
| 2807 | +++ new/gcc/testsuite/gcc.target/arm/neon-vsubu64.c 2010-07-29 15:59:12 +0000 | ||
| 2808 | @@ -0,0 +1,21 @@ | ||
| 2809 | +/* Test the `vsub_u64' ARM Neon intrinsic. */ | ||
| 2810 | + | ||
| 2811 | +/* { dg-do run } */ | ||
| 2812 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2813 | +/* { dg-options "-O0" } */ | ||
| 2814 | +/* { dg-add-options arm_neon } */ | ||
| 2815 | + | ||
| 2816 | +#include "arm_neon.h" | ||
| 2817 | +#include <stdlib.h> | ||
| 2818 | + | ||
| 2819 | +int main (void) | ||
| 2820 | +{ | ||
| 2821 | + uint64x1_t out_uint64x1_t = 0; | ||
| 2822 | + uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeefdeadbeefLL; | ||
| 2823 | + uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x0000beefdead0000LL; | ||
| 2824 | + | ||
| 2825 | + out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 2826 | + if (out_uint64x1_t != (uint64x1_t)0xdead00000000beefLL) | ||
| 2827 | + abort(); | ||
| 2828 | + return 0; | ||
| 2829 | +} | ||
| 2830 | |||
| 2831 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vadds64.c' | ||
| 2832 | --- old/gcc/testsuite/gcc.target/arm/neon/vadds64.c 2010-07-29 15:38:15 +0000 | ||
| 2833 | +++ new/gcc/testsuite/gcc.target/arm/neon/vadds64.c 2010-07-29 15:59:12 +0000 | ||
| 2834 | @@ -17,5 +17,4 @@ | ||
| 2835 | out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 2836 | } | ||
| 2837 | |||
| 2838 | -/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2839 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2840 | |||
| 2841 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu64.c' | ||
| 2842 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddu64.c 2010-07-29 15:38:15 +0000 | ||
| 2843 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddu64.c 2010-07-29 15:59:12 +0000 | ||
| 2844 | @@ -17,5 +17,4 @@ | ||
| 2845 | out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 2846 | } | ||
| 2847 | |||
| 2848 | -/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2849 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2850 | |||
| 2851 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vands64.c' | ||
| 2852 | --- old/gcc/testsuite/gcc.target/arm/neon/vands64.c 2010-07-29 15:38:15 +0000 | ||
| 2853 | +++ new/gcc/testsuite/gcc.target/arm/neon/vands64.c 2010-07-29 15:59:12 +0000 | ||
| 2854 | @@ -17,5 +17,4 @@ | ||
| 2855 | out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 2856 | } | ||
| 2857 | |||
| 2858 | -/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2859 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2860 | |||
| 2861 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vandu64.c' | ||
| 2862 | --- old/gcc/testsuite/gcc.target/arm/neon/vandu64.c 2010-07-29 15:38:15 +0000 | ||
| 2863 | +++ new/gcc/testsuite/gcc.target/arm/neon/vandu64.c 2010-07-29 15:59:12 +0000 | ||
| 2864 | @@ -17,5 +17,4 @@ | ||
| 2865 | out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 2866 | } | ||
| 2867 | |||
| 2868 | -/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2869 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2870 | |||
| 2871 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbics64.c' | ||
| 2872 | --- old/gcc/testsuite/gcc.target/arm/neon/vbics64.c 2010-07-29 15:38:15 +0000 | ||
| 2873 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbics64.c 2010-07-29 15:59:12 +0000 | ||
| 2874 | @@ -17,5 +17,4 @@ | ||
| 2875 | out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 2876 | } | ||
| 2877 | |||
| 2878 | -/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2879 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2880 | |||
| 2881 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu64.c' | ||
| 2882 | --- old/gcc/testsuite/gcc.target/arm/neon/vbicu64.c 2010-07-29 15:38:15 +0000 | ||
| 2883 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbicu64.c 2010-07-29 15:59:12 +0000 | ||
| 2884 | @@ -17,5 +17,4 @@ | ||
| 2885 | out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 2886 | } | ||
| 2887 | |||
| 2888 | -/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2889 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2890 | |||
| 2891 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c' | ||
| 2892 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 2893 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c 2010-07-29 15:59:12 +0000 | ||
| 2894 | @@ -16,6 +16,4 @@ | ||
| 2895 | out_int64x2_t = vdupq_n_s64 (arg0_int64_t); | ||
| 2896 | } | ||
| 2897 | |||
| 2898 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2899 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2900 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2901 | |||
| 2902 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c' | ||
| 2903 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 2904 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c 2010-07-29 15:59:12 +0000 | ||
| 2905 | @@ -16,6 +16,4 @@ | ||
| 2906 | out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t); | ||
| 2907 | } | ||
| 2908 | |||
| 2909 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2910 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2911 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2912 | |||
| 2913 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c' | ||
| 2914 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 2915 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c 2010-07-29 15:59:12 +0000 | ||
| 2916 | @@ -16,5 +16,4 @@ | ||
| 2917 | out_int64x1_t = vdup_n_s64 (arg0_int64_t); | ||
| 2918 | } | ||
| 2919 | |||
| 2920 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2921 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2922 | |||
| 2923 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c' | ||
| 2924 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 2925 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c 2010-07-29 15:59:12 +0000 | ||
| 2926 | @@ -16,5 +16,4 @@ | ||
| 2927 | out_uint64x1_t = vdup_n_u64 (arg0_uint64_t); | ||
| 2928 | } | ||
| 2929 | |||
| 2930 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2931 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2932 | |||
| 2933 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veors64.c' | ||
| 2934 | --- old/gcc/testsuite/gcc.target/arm/neon/veors64.c 2010-07-29 15:38:15 +0000 | ||
| 2935 | +++ new/gcc/testsuite/gcc.target/arm/neon/veors64.c 2010-07-29 15:59:12 +0000 | ||
| 2936 | @@ -17,5 +17,4 @@ | ||
| 2937 | out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 2938 | } | ||
| 2939 | |||
| 2940 | -/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2941 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2942 | |||
| 2943 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veoru64.c' | ||
| 2944 | --- old/gcc/testsuite/gcc.target/arm/neon/veoru64.c 2010-07-29 15:38:15 +0000 | ||
| 2945 | +++ new/gcc/testsuite/gcc.target/arm/neon/veoru64.c 2010-07-29 15:59:12 +0000 | ||
| 2946 | @@ -17,5 +17,4 @@ | ||
| 2947 | out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 2948 | } | ||
| 2949 | |||
| 2950 | -/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2951 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2952 | |||
| 2953 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c' | ||
| 2954 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c 2010-07-29 15:38:15 +0000 | ||
| 2955 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c 2010-07-29 15:59:12 +0000 | ||
| 2956 | @@ -16,5 +16,4 @@ | ||
| 2957 | out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0); | ||
| 2958 | } | ||
| 2959 | |||
| 2960 | -/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2961 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2962 | |||
| 2963 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c' | ||
| 2964 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c 2010-07-29 15:38:15 +0000 | ||
| 2965 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c 2010-07-29 15:59:12 +0000 | ||
| 2966 | @@ -16,5 +16,4 @@ | ||
| 2967 | out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0); | ||
| 2968 | } | ||
| 2969 | |||
| 2970 | -/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2971 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2972 | |||
| 2973 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c' | ||
| 2974 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 2975 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c 2010-07-29 15:59:12 +0000 | ||
| 2976 | @@ -16,6 +16,4 @@ | ||
| 2977 | out_int64x2_t = vmovq_n_s64 (arg0_int64_t); | ||
| 2978 | } | ||
| 2979 | |||
| 2980 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2981 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2982 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2983 | |||
| 2984 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c' | ||
| 2985 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 2986 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c 2010-07-29 15:59:12 +0000 | ||
| 2987 | @@ -16,6 +16,4 @@ | ||
| 2988 | out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t); | ||
| 2989 | } | ||
| 2990 | |||
| 2991 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2992 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2993 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2994 | |||
| 2995 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c' | ||
| 2996 | --- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 2997 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c 2010-07-29 15:59:12 +0000 | ||
| 2998 | @@ -16,5 +16,4 @@ | ||
| 2999 | out_int64x1_t = vmov_n_s64 (arg0_int64_t); | ||
| 3000 | } | ||
| 3001 | |||
| 3002 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3003 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3004 | |||
| 3005 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c' | ||
| 3006 | --- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 3007 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c 2010-07-29 15:59:12 +0000 | ||
| 3008 | @@ -16,5 +16,4 @@ | ||
| 3009 | out_uint64x1_t = vmov_n_u64 (arg0_uint64_t); | ||
| 3010 | } | ||
| 3011 | |||
| 3012 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3013 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3014 | |||
| 3015 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorns64.c' | ||
| 3016 | --- old/gcc/testsuite/gcc.target/arm/neon/vorns64.c 2010-07-29 15:38:15 +0000 | ||
| 3017 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorns64.c 2010-07-29 15:59:12 +0000 | ||
| 3018 | @@ -17,5 +17,4 @@ | ||
| 3019 | out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 3020 | } | ||
| 3021 | |||
| 3022 | -/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3023 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3024 | |||
| 3025 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vornu64.c' | ||
| 3026 | --- old/gcc/testsuite/gcc.target/arm/neon/vornu64.c 2010-07-29 15:38:15 +0000 | ||
| 3027 | +++ new/gcc/testsuite/gcc.target/arm/neon/vornu64.c 2010-07-29 15:59:12 +0000 | ||
| 3028 | @@ -17,5 +17,4 @@ | ||
| 3029 | out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 3030 | } | ||
| 3031 | |||
| 3032 | -/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3033 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3034 | |||
| 3035 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs64.c' | ||
| 3036 | --- old/gcc/testsuite/gcc.target/arm/neon/vorrs64.c 2010-07-29 15:38:15 +0000 | ||
| 3037 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorrs64.c 2010-07-29 15:59:12 +0000 | ||
| 3038 | @@ -17,5 +17,4 @@ | ||
| 3039 | out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 3040 | } | ||
| 3041 | |||
| 3042 | -/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3043 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3044 | |||
| 3045 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorru64.c' | ||
| 3046 | --- old/gcc/testsuite/gcc.target/arm/neon/vorru64.c 2010-07-29 15:38:15 +0000 | ||
| 3047 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorru64.c 2010-07-29 15:59:12 +0000 | ||
| 3048 | @@ -17,5 +17,4 @@ | ||
| 3049 | out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 3050 | } | ||
| 3051 | |||
| 3052 | -/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3053 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3054 | |||
| 3055 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c' | ||
| 3056 | --- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c 2010-07-29 15:38:15 +0000 | ||
| 3057 | +++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c 2010-07-29 15:59:12 +0000 | ||
| 3058 | @@ -17,5 +17,4 @@ | ||
| 3059 | out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); | ||
| 3060 | } | ||
| 3061 | |||
| 3062 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3063 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3064 | |||
| 3065 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c' | ||
| 3066 | --- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c 2010-07-29 15:38:15 +0000 | ||
| 3067 | +++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c 2010-07-29 15:59:12 +0000 | ||
| 3068 | @@ -17,5 +17,4 @@ | ||
| 3069 | out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); | ||
| 3070 | } | ||
| 3071 | |||
| 3072 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3073 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3074 | |||
| 3075 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs64.c' | ||
| 3076 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubs64.c 2010-07-29 15:38:15 +0000 | ||
| 3077 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubs64.c 2010-07-29 15:59:12 +0000 | ||
| 3078 | @@ -17,5 +17,4 @@ | ||
| 3079 | out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 3080 | } | ||
| 3081 | |||
| 3082 | -/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3083 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3084 | |||
| 3085 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu64.c' | ||
| 3086 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubu64.c 2010-07-29 15:38:15 +0000 | ||
| 3087 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubu64.c 2010-07-29 15:59:12 +0000 | ||
| 3088 | @@ -17,5 +17,4 @@ | ||
| 3089 | out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 3090 | } | ||
| 3091 | |||
| 3092 | -/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3093 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3094 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99301.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99301.patch deleted file mode 100644 index 0943130de..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99301.patch +++ /dev/null | |||
| @@ -1,674 +0,0 @@ | |||
| 1 | 2010-07-02 Daniel Jacobowitz <dan@codesourcery.com> | ||
| 2 | Julian Brown <julian@codesourcery.com> | ||
| 3 | Sandra Loosemore <sandra@codesourcery.com> | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * config/arm/arm.c (arm_canonicalize_comparison): Canonicalize DImode | ||
| 7 | comparisons. Adjust to take both operands. | ||
| 8 | (arm_select_cc_mode): Handle DImode comparisons. | ||
| 9 | (arm_gen_compare_reg): Generate a scratch register for DImode | ||
| 10 | comparisons which require one. Use xor for Thumb equality checks. | ||
| 11 | (arm_const_double_by_immediates): New. | ||
| 12 | (arm_print_operand): Allow 'Q' and 'R' for constants. | ||
| 13 | (get_arm_condition_code): Handle new CC_CZmode and CC_NCVmode. | ||
| 14 | * config/arm/arm.h (CANONICALIZE_COMPARISON): Always use | ||
| 15 | arm_canonicalize_comparison. | ||
| 16 | * config/arm/arm-modes.def: Add CC_CZmode and CC_NCVmode. | ||
| 17 | * config/arm/arm-protos.h (arm_canonicalize_comparison): Update | ||
| 18 | prototype. | ||
| 19 | (arm_const_double_by_immediates): Declare. | ||
| 20 | * config/arm/constraints.md (Di): New constraint. | ||
| 21 | * config/arm/predicates.md (arm_immediate_di_operand) | ||
| 22 | (arm_di_operand, cmpdi_operand): New. | ||
| 23 | * config/arm/arm.md (cbranchdi4): Handle non-Cirrus also. | ||
| 24 | (*arm_cmpdi_insn, *arm_cmpdi_unsigned) | ||
| 25 | (*arm_cmpdi_zero, *thumb_cmpdi_zero): New insns. | ||
| 26 | (cstoredi4): Handle non-Cirrus also. | ||
| 27 | |||
| 28 | gcc/testsuite/ | ||
| 29 | * gcc.c-torture/execute/20100416-1.c: New test case. | ||
| 30 | |||
| 31 | 2010-07-08 Sandra Loosemore <sandra@codesourcery.com> | ||
| 32 | |||
| 33 | Backport from upstream (originally from Sourcery G++ 4.4): | ||
| 34 | |||
| 35 | 2010-07-02 Sandra Loosemore <sandra@codesourcery.com> | ||
| 36 | |||
| 37 | gcc/ | ||
| 38 | |||
| 39 | === modified file 'gcc/config/arm/arm-modes.def' | ||
| 40 | Index: gcc-4.5.3/gcc/config/arm/arm-modes.def | ||
| 41 | =================================================================== | ||
| 42 | --- gcc-4.5.3.orig/gcc/config/arm/arm-modes.def | ||
| 43 | +++ gcc-4.5.3/gcc/config/arm/arm-modes.def | ||
| 44 | @@ -35,10 +35,16 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_form | ||
| 45 | CC_NOOVmode should be used with SImode integer equalities. | ||
| 46 | CC_Zmode should be used if only the Z flag is set correctly | ||
| 47 | CC_Nmode should be used if only the N (sign) flag is set correctly | ||
| 48 | + CC_CZmode should be used if only the C and Z flags are correct | ||
| 49 | + (used for DImode unsigned comparisons). | ||
| 50 | + CC_NCVmode should be used if only the N, C, and V flags are correct | ||
| 51 | + (used for DImode signed comparisons). | ||
| 52 | CCmode should be used otherwise. */ | ||
| 53 | |||
| 54 | CC_MODE (CC_NOOV); | ||
| 55 | CC_MODE (CC_Z); | ||
| 56 | +CC_MODE (CC_CZ); | ||
| 57 | +CC_MODE (CC_NCV); | ||
| 58 | CC_MODE (CC_SWP); | ||
| 59 | CC_MODE (CCFP); | ||
| 60 | CC_MODE (CCFPE); | ||
| 61 | Index: gcc-4.5.3/gcc/config/arm/arm-protos.h | ||
| 62 | =================================================================== | ||
| 63 | --- gcc-4.5.3.orig/gcc/config/arm/arm-protos.h | ||
| 64 | +++ gcc-4.5.3/gcc/config/arm/arm-protos.h | ||
| 65 | @@ -49,8 +49,7 @@ extern int arm_hard_regno_mode_ok (unsig | ||
| 66 | extern int const_ok_for_arm (HOST_WIDE_INT); | ||
| 67 | extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx, | ||
| 68 | HOST_WIDE_INT, rtx, rtx, int); | ||
| 69 | -extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, enum machine_mode, | ||
| 70 | - rtx *); | ||
| 71 | +extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *); | ||
| 72 | extern int legitimate_pic_operand_p (rtx); | ||
| 73 | extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx); | ||
| 74 | extern rtx legitimize_tls_address (rtx, rtx); | ||
| 75 | @@ -116,6 +115,7 @@ extern void arm_reload_in_hi (rtx *); | ||
| 76 | extern void arm_reload_out_hi (rtx *); | ||
| 77 | extern int arm_const_double_inline_cost (rtx); | ||
| 78 | extern bool arm_const_double_by_parts (rtx); | ||
| 79 | +extern bool arm_const_double_by_immediates (rtx); | ||
| 80 | extern const char *fp_immediate_constant (rtx); | ||
| 81 | extern void arm_emit_call_insn (rtx, rtx); | ||
| 82 | extern const char *output_call (rtx *); | ||
| 83 | Index: gcc-4.5.3/gcc/config/arm/arm.c | ||
| 84 | =================================================================== | ||
| 85 | --- gcc-4.5.3.orig/gcc/config/arm/arm.c | ||
| 86 | +++ gcc-4.5.3/gcc/config/arm/arm.c | ||
| 87 | @@ -3191,13 +3191,82 @@ arm_gen_constant (enum rtx_code code, en | ||
| 88 | immediate value easier to load. */ | ||
| 89 | |||
| 90 | enum rtx_code | ||
| 91 | -arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode, | ||
| 92 | - rtx * op1) | ||
| 93 | +arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1) | ||
| 94 | { | ||
| 95 | - unsigned HOST_WIDE_INT i = INTVAL (*op1); | ||
| 96 | - unsigned HOST_WIDE_INT maxval; | ||
| 97 | + enum machine_mode mode; | ||
| 98 | + unsigned HOST_WIDE_INT i, maxval; | ||
| 99 | + | ||
| 100 | + mode = GET_MODE (*op0); | ||
| 101 | + if (mode == VOIDmode) | ||
| 102 | + mode = GET_MODE (*op1); | ||
| 103 | + | ||
| 104 | maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1; | ||
| 105 | |||
| 106 | + /* For DImode, we have GE/LT/GEU/LTU comparisons. In ARM mode | ||
| 107 | + we can also use cmp/cmpeq for GTU/LEU. GT/LE must be either | ||
| 108 | + reversed or (for constant OP1) adjusted to GE/LT. Similarly | ||
| 109 | + for GTU/LEU in Thumb mode. */ | ||
| 110 | + if (mode == DImode) | ||
| 111 | + { | ||
| 112 | + rtx tem; | ||
| 113 | + | ||
| 114 | + /* To keep things simple, always use the Cirrus cfcmp64 if it is | ||
| 115 | + available. */ | ||
| 116 | + if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK) | ||
| 117 | + return code; | ||
| 118 | + | ||
| 119 | + if (code == GT || code == LE | ||
| 120 | + || (!TARGET_ARM && (code == GTU || code == LEU))) | ||
| 121 | + { | ||
| 122 | + /* Missing comparison. First try to use an available | ||
| 123 | + comparison. */ | ||
| 124 | + if (GET_CODE (*op1) == CONST_INT) | ||
| 125 | + { | ||
| 126 | + i = INTVAL (*op1); | ||
| 127 | + switch (code) | ||
| 128 | + { | ||
| 129 | + case GT: | ||
| 130 | + case LE: | ||
| 131 | + if (i != maxval | ||
| 132 | + && arm_const_double_by_immediates (GEN_INT (i + 1))) | ||
| 133 | + { | ||
| 134 | + *op1 = GEN_INT (i + 1); | ||
| 135 | + return code == GT ? GE : LT; | ||
| 136 | + } | ||
| 137 | + break; | ||
| 138 | + case GTU: | ||
| 139 | + case LEU: | ||
| 140 | + if (i != ~((unsigned HOST_WIDE_INT) 0) | ||
| 141 | + && arm_const_double_by_immediates (GEN_INT (i + 1))) | ||
| 142 | + { | ||
| 143 | + *op1 = GEN_INT (i + 1); | ||
| 144 | + return code == GTU ? GEU : LTU; | ||
| 145 | + } | ||
| 146 | + break; | ||
| 147 | + default: | ||
| 148 | + gcc_unreachable (); | ||
| 149 | + } | ||
| 150 | + } | ||
| 151 | + | ||
| 152 | + /* If that did not work, reverse the condition. */ | ||
| 153 | + tem = *op0; | ||
| 154 | + *op0 = *op1; | ||
| 155 | + *op1 = tem; | ||
| 156 | + return swap_condition (code); | ||
| 157 | + } | ||
| 158 | + | ||
| 159 | + return code; | ||
| 160 | + } | ||
| 161 | + | ||
| 162 | + /* Comparisons smaller than DImode. Only adjust comparisons against | ||
| 163 | + an out-of-range constant. */ | ||
| 164 | + if (GET_CODE (*op1) != CONST_INT | ||
| 165 | + || const_ok_for_arm (INTVAL (*op1)) | ||
| 166 | + || const_ok_for_arm (- INTVAL (*op1))) | ||
| 167 | + return code; | ||
| 168 | + | ||
| 169 | + i = INTVAL (*op1); | ||
| 170 | + | ||
| 171 | switch (code) | ||
| 172 | { | ||
| 173 | case EQ: | ||
| 174 | @@ -9913,6 +9982,55 @@ arm_select_cc_mode (enum rtx_code op, rt | ||
| 175 | && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) | ||
| 176 | return CC_Cmode; | ||
| 177 | |||
| 178 | + if (GET_MODE (x) == DImode || GET_MODE (y) == DImode) | ||
| 179 | + { | ||
| 180 | + /* To keep things simple, always use the Cirrus cfcmp64 if it is | ||
| 181 | + available. */ | ||
| 182 | + if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK) | ||
| 183 | + return CCmode; | ||
| 184 | + | ||
| 185 | + switch (op) | ||
| 186 | + { | ||
| 187 | + case EQ: | ||
| 188 | + case NE: | ||
| 189 | + /* A DImode comparison against zero can be implemented by | ||
| 190 | + or'ing the two halves together. */ | ||
| 191 | + if (y == const0_rtx) | ||
| 192 | + return CC_Zmode; | ||
| 193 | + | ||
| 194 | + /* We can do an equality test in three Thumb instructions. */ | ||
| 195 | + if (!TARGET_ARM) | ||
| 196 | + return CC_Zmode; | ||
| 197 | + | ||
| 198 | + /* FALLTHROUGH */ | ||
| 199 | + | ||
| 200 | + case LTU: | ||
| 201 | + case LEU: | ||
| 202 | + case GTU: | ||
| 203 | + case GEU: | ||
| 204 | + /* DImode unsigned comparisons can be implemented by cmp + | ||
| 205 | + cmpeq without a scratch register. Not worth doing in | ||
| 206 | + Thumb-2. */ | ||
| 207 | + if (TARGET_ARM) | ||
| 208 | + return CC_CZmode; | ||
| 209 | + | ||
| 210 | + /* FALLTHROUGH */ | ||
| 211 | + | ||
| 212 | + case LT: | ||
| 213 | + case LE: | ||
| 214 | + case GT: | ||
| 215 | + case GE: | ||
| 216 | + /* DImode signed and unsigned comparisons can be implemented | ||
| 217 | + by cmp + sbcs with a scratch register, but that does not | ||
| 218 | + set the Z flag - we must reverse GT/LE/GTU/LEU. */ | ||
| 219 | + gcc_assert (op != EQ && op != NE); | ||
| 220 | + return CC_NCVmode; | ||
| 221 | + | ||
| 222 | + default: | ||
| 223 | + gcc_unreachable (); | ||
| 224 | + } | ||
| 225 | + } | ||
| 226 | + | ||
| 227 | return CCmode; | ||
| 228 | } | ||
| 229 | |||
| 230 | @@ -9922,10 +10040,39 @@ arm_select_cc_mode (enum rtx_code op, rt | ||
| 231 | rtx | ||
| 232 | arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) | ||
| 233 | { | ||
| 234 | - enum machine_mode mode = SELECT_CC_MODE (code, x, y); | ||
| 235 | - rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); | ||
| 236 | + enum machine_mode mode; | ||
| 237 | + rtx cc_reg; | ||
| 238 | + int dimode_comparison = GET_MODE (x) == DImode || GET_MODE (y) == DImode; | ||
| 239 | |||
| 240 | - emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); | ||
| 241 | + /* We might have X as a constant, Y as a register because of the predicates | ||
| 242 | + used for cmpdi. If so, force X to a register here. */ | ||
| 243 | + if (dimode_comparison && !REG_P (x)) | ||
| 244 | + x = force_reg (DImode, x); | ||
| 245 | + | ||
| 246 | + mode = SELECT_CC_MODE (code, x, y); | ||
| 247 | + cc_reg = gen_rtx_REG (mode, CC_REGNUM); | ||
| 248 | + | ||
| 249 | + if (dimode_comparison | ||
| 250 | + && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) | ||
| 251 | + && mode != CC_CZmode) | ||
| 252 | + { | ||
| 253 | + rtx clobber, set; | ||
| 254 | + | ||
| 255 | + /* To compare two non-zero values for equality, XOR them and | ||
| 256 | + then compare against zero. Not used for ARM mode; there | ||
| 257 | + CC_CZmode is cheaper. */ | ||
| 258 | + if (mode == CC_Zmode && y != const0_rtx) | ||
| 259 | + { | ||
| 260 | + x = expand_binop (DImode, xor_optab, x, y, NULL_RTX, 0, OPTAB_WIDEN); | ||
| 261 | + y = const0_rtx; | ||
| 262 | + } | ||
| 263 | + /* A scratch register is required. */ | ||
| 264 | + clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)); | ||
| 265 | + set = gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)); | ||
| 266 | + emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); | ||
| 267 | + } | ||
| 268 | + else | ||
| 269 | + emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); | ||
| 270 | |||
| 271 | return cc_reg; | ||
| 272 | } | ||
| 273 | @@ -11254,6 +11401,34 @@ arm_const_double_by_parts (rtx val) | ||
| 274 | return false; | ||
| 275 | } | ||
| 276 | |||
| 277 | +/* Return true if it is possible to inline both the high and low parts | ||
| 278 | + of a 64-bit constant into 32-bit data processing instructions. */ | ||
| 279 | +bool | ||
| 280 | +arm_const_double_by_immediates (rtx val) | ||
| 281 | +{ | ||
| 282 | + enum machine_mode mode = GET_MODE (val); | ||
| 283 | + rtx part; | ||
| 284 | + | ||
| 285 | + if (mode == VOIDmode) | ||
| 286 | + mode = DImode; | ||
| 287 | + | ||
| 288 | + part = gen_highpart_mode (SImode, mode, val); | ||
| 289 | + | ||
| 290 | + gcc_assert (GET_CODE (part) == CONST_INT); | ||
| 291 | + | ||
| 292 | + if (!const_ok_for_arm (INTVAL (part))) | ||
| 293 | + return false; | ||
| 294 | + | ||
| 295 | + part = gen_lowpart (SImode, val); | ||
| 296 | + | ||
| 297 | + gcc_assert (GET_CODE (part) == CONST_INT); | ||
| 298 | + | ||
| 299 | + if (!const_ok_for_arm (INTVAL (part))) | ||
| 300 | + return false; | ||
| 301 | + | ||
| 302 | + return true; | ||
| 303 | +} | ||
| 304 | + | ||
| 305 | /* Scan INSN and note any of its operands that need fixing. | ||
| 306 | If DO_PUSHES is false we do not actually push any of the fixups | ||
| 307 | needed. The function returns TRUE if any fixups were needed/pushed. | ||
| 308 | @@ -15150,8 +15325,18 @@ arm_print_operand (FILE *stream, rtx x, | ||
| 309 | the value being loaded is big-wordian or little-wordian. The | ||
| 310 | order of the two register loads can matter however, if the address | ||
| 311 | of the memory location is actually held in one of the registers | ||
| 312 | - being overwritten by the load. */ | ||
| 313 | + being overwritten by the load. | ||
| 314 | + | ||
| 315 | + The 'Q' and 'R' constraints are also available for 64-bit | ||
| 316 | + constants. */ | ||
| 317 | case 'Q': | ||
| 318 | + if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) | ||
| 319 | + { | ||
| 320 | + rtx part = gen_lowpart (SImode, x); | ||
| 321 | + fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part)); | ||
| 322 | + return; | ||
| 323 | + } | ||
| 324 | + | ||
| 325 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) | ||
| 326 | { | ||
| 327 | output_operand_lossage ("invalid operand for code '%c'", code); | ||
| 328 | @@ -15162,6 +15347,18 @@ arm_print_operand (FILE *stream, rtx x, | ||
| 329 | return; | ||
| 330 | |||
| 331 | case 'R': | ||
| 332 | + if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) | ||
| 333 | + { | ||
| 334 | + enum machine_mode mode = GET_MODE (x); | ||
| 335 | + rtx part; | ||
| 336 | + | ||
| 337 | + if (mode == VOIDmode) | ||
| 338 | + mode = DImode; | ||
| 339 | + part = gen_highpart_mode (SImode, mode, x); | ||
| 340 | + fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part)); | ||
| 341 | + return; | ||
| 342 | + } | ||
| 343 | + | ||
| 344 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) | ||
| 345 | { | ||
| 346 | output_operand_lossage ("invalid operand for code '%c'", code); | ||
| 347 | @@ -15854,6 +16051,28 @@ get_arm_condition_code (rtx comparison) | ||
| 348 | default: gcc_unreachable (); | ||
| 349 | } | ||
| 350 | |||
| 351 | + case CC_CZmode: | ||
| 352 | + switch (comp_code) | ||
| 353 | + { | ||
| 354 | + case NE: return ARM_NE; | ||
| 355 | + case EQ: return ARM_EQ; | ||
| 356 | + case GEU: return ARM_CS; | ||
| 357 | + case GTU: return ARM_HI; | ||
| 358 | + case LEU: return ARM_LS; | ||
| 359 | + case LTU: return ARM_CC; | ||
| 360 | + default: gcc_unreachable (); | ||
| 361 | + } | ||
| 362 | + | ||
| 363 | + case CC_NCVmode: | ||
| 364 | + switch (comp_code) | ||
| 365 | + { | ||
| 366 | + case GE: return ARM_GE; | ||
| 367 | + case LT: return ARM_LT; | ||
| 368 | + case GEU: return ARM_CS; | ||
| 369 | + case LTU: return ARM_CC; | ||
| 370 | + default: gcc_unreachable (); | ||
| 371 | + } | ||
| 372 | + | ||
| 373 | case CCmode: | ||
| 374 | switch (comp_code) | ||
| 375 | { | ||
| 376 | Index: gcc-4.5.3/gcc/config/arm/arm.h | ||
| 377 | =================================================================== | ||
| 378 | --- gcc-4.5.3.orig/gcc/config/arm/arm.h | ||
| 379 | +++ gcc-4.5.3/gcc/config/arm/arm.h | ||
| 380 | @@ -2253,19 +2253,7 @@ extern int making_const_table; | ||
| 381 | : reverse_condition (code)) | ||
| 382 | |||
| 383 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ | ||
| 384 | - do \ | ||
| 385 | - { \ | ||
| 386 | - if (GET_CODE (OP1) == CONST_INT \ | ||
| 387 | - && ! (const_ok_for_arm (INTVAL (OP1)) \ | ||
| 388 | - || (const_ok_for_arm (- INTVAL (OP1))))) \ | ||
| 389 | - { \ | ||
| 390 | - rtx const_op = OP1; \ | ||
| 391 | - CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \ | ||
| 392 | - &const_op); \ | ||
| 393 | - OP1 = const_op; \ | ||
| 394 | - } \ | ||
| 395 | - } \ | ||
| 396 | - while (0) | ||
| 397 | + (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1)) | ||
| 398 | |||
| 399 | /* The arm5 clz instruction returns 32. */ | ||
| 400 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) | ||
| 401 | Index: gcc-4.5.3/gcc/config/arm/arm.md | ||
| 402 | =================================================================== | ||
| 403 | --- gcc-4.5.3.orig/gcc/config/arm/arm.md | ||
| 404 | +++ gcc-4.5.3/gcc/config/arm/arm.md | ||
| 405 | @@ -6718,17 +6718,45 @@ | ||
| 406 | operands[3])); DONE;" | ||
| 407 | ) | ||
| 408 | |||
| 409 | -;; this uses the Cirrus DI compare instruction | ||
| 410 | (define_expand "cbranchdi4" | ||
| 411 | [(set (pc) (if_then_else | ||
| 412 | (match_operator 0 "arm_comparison_operator" | ||
| 413 | - [(match_operand:DI 1 "cirrus_fp_register" "") | ||
| 414 | - (match_operand:DI 2 "cirrus_fp_register" "")]) | ||
| 415 | + [(match_operand:DI 1 "cmpdi_operand" "") | ||
| 416 | + (match_operand:DI 2 "cmpdi_operand" "")]) | ||
| 417 | (label_ref (match_operand 3 "" "")) | ||
| 418 | (pc)))] | ||
| 419 | - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" | ||
| 420 | - "emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2], | ||
| 421 | - operands[3])); DONE;" | ||
| 422 | + "TARGET_32BIT" | ||
| 423 | + "{ | ||
| 424 | + rtx swap = NULL_RTX; | ||
| 425 | + enum rtx_code code = GET_CODE (operands[0]); | ||
| 426 | + | ||
| 427 | + /* We should not have two constants. */ | ||
| 428 | + gcc_assert (GET_MODE (operands[1]) == DImode | ||
| 429 | + || GET_MODE (operands[2]) == DImode); | ||
| 430 | + | ||
| 431 | + /* Flip unimplemented DImode comparisons to a form that | ||
| 432 | + arm_gen_compare_reg can handle. */ | ||
| 433 | + switch (code) | ||
| 434 | + { | ||
| 435 | + case GT: | ||
| 436 | + swap = gen_rtx_LT (VOIDmode, operands[2], operands[1]); break; | ||
| 437 | + case LE: | ||
| 438 | + swap = gen_rtx_GE (VOIDmode, operands[2], operands[1]); break; | ||
| 439 | + case GTU: | ||
| 440 | + swap = gen_rtx_LTU (VOIDmode, operands[2], operands[1]); break; | ||
| 441 | + case LEU: | ||
| 442 | + swap = gen_rtx_GEU (VOIDmode, operands[2], operands[1]); break; | ||
| 443 | + default: | ||
| 444 | + break; | ||
| 445 | + } | ||
| 446 | + if (swap) | ||
| 447 | + emit_jump_insn (gen_cbranch_cc (swap, operands[2], operands[1], | ||
| 448 | + operands[3])); | ||
| 449 | + else | ||
| 450 | + emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2], | ||
| 451 | + operands[3])); | ||
| 452 | + DONE; | ||
| 453 | + }" | ||
| 454 | ) | ||
| 455 | |||
| 456 | (define_insn "*cbranchsi4_insn" | ||
| 457 | @@ -7880,6 +7908,52 @@ | ||
| 458 | (const_string "alu_shift_reg")))] | ||
| 459 | ) | ||
| 460 | |||
| 461 | +;; DImode comparisons. The generic code generates branches that | ||
| 462 | +;; if-conversion can not reduce to a conditional compare, so we do | ||
| 463 | +;; that directly. | ||
| 464 | + | ||
| 465 | +(define_insn "*arm_cmpdi_insn" | ||
| 466 | + [(set (reg:CC_NCV CC_REGNUM) | ||
| 467 | + (compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r") | ||
| 468 | + (match_operand:DI 1 "arm_di_operand" "rDi"))) | ||
| 469 | + (clobber (match_scratch:SI 2 "=r"))] | ||
| 470 | + "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" | ||
| 471 | + "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1" | ||
| 472 | + [(set_attr "conds" "set") | ||
| 473 | + (set_attr "length" "8")] | ||
| 474 | +) | ||
| 475 | + | ||
| 476 | +(define_insn "*arm_cmpdi_unsigned" | ||
| 477 | + [(set (reg:CC_CZ CC_REGNUM) | ||
| 478 | + (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r") | ||
| 479 | + (match_operand:DI 1 "arm_di_operand" "rDi")))] | ||
| 480 | + "TARGET_ARM" | ||
| 481 | + "cmp%?\\t%R0, %R1\;cmpeq\\t%Q0, %Q1" | ||
| 482 | + [(set_attr "conds" "set") | ||
| 483 | + (set_attr "length" "8")] | ||
| 484 | +) | ||
| 485 | + | ||
| 486 | +(define_insn "*arm_cmpdi_zero" | ||
| 487 | + [(set (reg:CC_Z CC_REGNUM) | ||
| 488 | + (compare:CC_Z (match_operand:DI 0 "s_register_operand" "r") | ||
| 489 | + (const_int 0))) | ||
| 490 | + (clobber (match_scratch:SI 1 "=r"))] | ||
| 491 | + "TARGET_32BIT" | ||
| 492 | + "orr%.\\t%1, %Q0, %R0" | ||
| 493 | + [(set_attr "conds" "set")] | ||
| 494 | +) | ||
| 495 | + | ||
| 496 | +(define_insn "*thumb_cmpdi_zero" | ||
| 497 | + [(set (reg:CC_Z CC_REGNUM) | ||
| 498 | + (compare:CC_Z (match_operand:DI 0 "s_register_operand" "l") | ||
| 499 | + (const_int 0))) | ||
| 500 | + (clobber (match_scratch:SI 1 "=l"))] | ||
| 501 | + "TARGET_THUMB1" | ||
| 502 | + "orr\\t%1, %Q0, %R0" | ||
| 503 | + [(set_attr "conds" "set") | ||
| 504 | + (set_attr "length" "2")] | ||
| 505 | +) | ||
| 506 | + | ||
| 507 | ;; Cirrus SF compare instruction | ||
| 508 | (define_insn "*cirrus_cmpsf" | ||
| 509 | [(set (reg:CCFP CC_REGNUM) | ||
| 510 | @@ -8183,17 +8257,44 @@ | ||
| 511 | operands[2], operands[3])); DONE;" | ||
| 512 | ) | ||
| 513 | |||
| 514 | -;; this uses the Cirrus DI compare instruction | ||
| 515 | (define_expand "cstoredi4" | ||
| 516 | [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 517 | (match_operator:SI 1 "arm_comparison_operator" | ||
| 518 | - [(match_operand:DI 2 "cirrus_fp_register" "") | ||
| 519 | - (match_operand:DI 3 "cirrus_fp_register" "")]))] | ||
| 520 | - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" | ||
| 521 | - "emit_insn (gen_cstore_cc (operands[0], operands[1], | ||
| 522 | - operands[2], operands[3])); DONE;" | ||
| 523 | -) | ||
| 524 | + [(match_operand:DI 2 "cmpdi_operand" "") | ||
| 525 | + (match_operand:DI 3 "cmpdi_operand" "")]))] | ||
| 526 | + "TARGET_32BIT" | ||
| 527 | + "{ | ||
| 528 | + rtx swap = NULL_RTX; | ||
| 529 | + enum rtx_code code = GET_CODE (operands[1]); | ||
| 530 | |||
| 531 | + /* We should not have two constants. */ | ||
| 532 | + gcc_assert (GET_MODE (operands[2]) == DImode | ||
| 533 | + || GET_MODE (operands[3]) == DImode); | ||
| 534 | + | ||
| 535 | + /* Flip unimplemented DImode comparisons to a form that | ||
| 536 | + arm_gen_compare_reg can handle. */ | ||
| 537 | + switch (code) | ||
| 538 | + { | ||
| 539 | + case GT: | ||
| 540 | + swap = gen_rtx_LT (VOIDmode, operands[3], operands[2]); break; | ||
| 541 | + case LE: | ||
| 542 | + swap = gen_rtx_GE (VOIDmode, operands[3], operands[2]); break; | ||
| 543 | + case GTU: | ||
| 544 | + swap = gen_rtx_LTU (VOIDmode, operands[3], operands[2]); break; | ||
| 545 | + case LEU: | ||
| 546 | + swap = gen_rtx_GEU (VOIDmode, operands[3], operands[2]); break; | ||
| 547 | + default: | ||
| 548 | + break; | ||
| 549 | + } | ||
| 550 | + if (swap) | ||
| 551 | + emit_insn (gen_cstore_cc (operands[0], swap, operands[3], | ||
| 552 | + operands[2])); | ||
| 553 | + else | ||
| 554 | + emit_insn (gen_cstore_cc (operands[0], operands[1], operands[2], | ||
| 555 | + operands[3])); | ||
| 556 | + DONE; | ||
| 557 | + }" | ||
| 558 | +) | ||
| 559 | |||
| 560 | (define_expand "cstoresi_eq0_thumb1" | ||
| 561 | [(parallel | ||
| 562 | Index: gcc-4.5.3/gcc/config/arm/constraints.md | ||
| 563 | =================================================================== | ||
| 564 | --- gcc-4.5.3.orig/gcc/config/arm/constraints.md | ||
| 565 | +++ gcc-4.5.3/gcc/config/arm/constraints.md | ||
| 566 | @@ -29,7 +29,7 @@ | ||
| 567 | ;; in Thumb-1 state: I, J, K, L, M, N, O | ||
| 568 | |||
| 569 | ;; The following multi-letter normal constraints have been used: | ||
| 570 | -;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy | ||
| 571 | +;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di | ||
| 572 | ;; in Thumb-1 state: Pa, Pb | ||
| 573 | ;; in Thumb-2 state: Ps, Pt | ||
| 574 | |||
| 575 | @@ -191,6 +191,13 @@ | ||
| 576 | (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4 | ||
| 577 | && !(optimize_size || arm_ld_sched)"))) | ||
| 578 | |||
| 579 | +(define_constraint "Di" | ||
| 580 | + "@internal | ||
| 581 | + In ARM/Thumb-2 state a const_int or const_double where both the high | ||
| 582 | + and low SImode words can be generated as immediates in 32-bit instructions." | ||
| 583 | + (and (match_code "const_double,const_int") | ||
| 584 | + (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)"))) | ||
| 585 | + | ||
| 586 | (define_constraint "Dn" | ||
| 587 | "@internal | ||
| 588 | In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov | ||
| 589 | Index: gcc-4.5.3/gcc/config/arm/predicates.md | ||
| 590 | =================================================================== | ||
| 591 | --- gcc-4.5.3.orig/gcc/config/arm/predicates.md | ||
| 592 | +++ gcc-4.5.3/gcc/config/arm/predicates.md | ||
| 593 | @@ -101,6 +101,12 @@ | ||
| 594 | (and (match_code "const_int") | ||
| 595 | (match_test "const_ok_for_arm (INTVAL (op))"))) | ||
| 596 | |||
| 597 | +;; A constant value which fits into two instructions, each taking | ||
| 598 | +;; an arithmetic constant operand for one of the words. | ||
| 599 | +(define_predicate "arm_immediate_di_operand" | ||
| 600 | + (and (match_code "const_int,const_double") | ||
| 601 | + (match_test "arm_const_double_by_immediates (op)"))) | ||
| 602 | + | ||
| 603 | (define_predicate "arm_neg_immediate_operand" | ||
| 604 | (and (match_code "const_int") | ||
| 605 | (match_test "const_ok_for_arm (-INTVAL (op))"))) | ||
| 606 | @@ -130,6 +136,10 @@ | ||
| 607 | (ior (match_operand 0 "arm_rhs_operand") | ||
| 608 | (match_operand 0 "arm_not_immediate_operand"))) | ||
| 609 | |||
| 610 | +(define_predicate "arm_di_operand" | ||
| 611 | + (ior (match_operand 0 "s_register_operand") | ||
| 612 | + (match_operand 0 "arm_immediate_di_operand"))) | ||
| 613 | + | ||
| 614 | ;; True if the operand is a memory reference which contains an | ||
| 615 | ;; offsettable address. | ||
| 616 | (define_predicate "offsettable_memory_operand" | ||
| 617 | @@ -538,3 +548,12 @@ | ||
| 618 | (and (match_code "const_int") | ||
| 619 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15"))) | ||
| 620 | |||
| 621 | +;; Predicates for named expanders that overlap multiple ISAs. | ||
| 622 | + | ||
| 623 | +(define_predicate "cmpdi_operand" | ||
| 624 | + (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK") | ||
| 625 | + (and (match_test "TARGET_ARM") | ||
| 626 | + (match_operand 0 "cirrus_fp_register")) | ||
| 627 | + (and (match_test "TARGET_32BIT") | ||
| 628 | + (match_operand 0 "arm_di_operand")))) | ||
| 629 | + | ||
| 630 | Index: gcc-4.5.3/gcc/testsuite/gcc.c-torture/execute/20100416-1.c | ||
| 631 | =================================================================== | ||
| 632 | --- /dev/null | ||
| 633 | +++ gcc-4.5.3/gcc/testsuite/gcc.c-torture/execute/20100416-1.c | ||
| 634 | @@ -0,0 +1,40 @@ | ||
| 635 | +void abort(void); | ||
| 636 | + | ||
| 637 | +int | ||
| 638 | +movegt(int x, int y, long long a) | ||
| 639 | +{ | ||
| 640 | + int i; | ||
| 641 | + int ret = 0; | ||
| 642 | + for (i = 0; i < y; i++) | ||
| 643 | + { | ||
| 644 | + if (a >= (long long) 0xf000000000000000LL) | ||
| 645 | + ret = x; | ||
| 646 | + else | ||
| 647 | + ret = y; | ||
| 648 | + } | ||
| 649 | + return ret; | ||
| 650 | +} | ||
| 651 | + | ||
| 652 | +struct test | ||
| 653 | +{ | ||
| 654 | + long long val; | ||
| 655 | + int ret; | ||
| 656 | +} tests[] = { | ||
| 657 | + { 0xf000000000000000LL, -1 }, | ||
| 658 | + { 0xefffffffffffffffLL, 1 }, | ||
| 659 | + { 0xf000000000000001LL, -1 }, | ||
| 660 | + { 0x0000000000000000LL, -1 }, | ||
| 661 | + { 0x8000000000000000LL, 1 }, | ||
| 662 | +}; | ||
| 663 | + | ||
| 664 | +int | ||
| 665 | +main() | ||
| 666 | +{ | ||
| 667 | + int i; | ||
| 668 | + for (i = 0; i < sizeof (tests) / sizeof (tests[0]); i++) | ||
| 669 | + { | ||
| 670 | + if (movegt (-1, 1, tests[i].val) != tests[i].ret) | ||
| 671 | + abort (); | ||
| 672 | + } | ||
| 673 | + return 0; | ||
| 674 | +} | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch deleted file mode 100644 index 635d3f8bd..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch +++ /dev/null | |||
| @@ -1,244 +0,0 @@ | |||
| 1 | 2010-07-09 Sandra Loosemore <sandra@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline (originally on Sourcery G++ 4.4): | ||
| 4 | |||
| 5 | 2010-07-02 Julian Brown <julian@codesourcery.com> | ||
| 6 | Sandra Loosemore <sandra@codesourcery.com> | ||
| 7 | |||
| 8 | PR target/43703 | ||
| 9 | |||
| 10 | gcc/ | ||
| 11 | * config/arm/vec-common.md (add<mode>3, sub<mode>3, smin<mode>3) | ||
| 12 | (smax<mode>3): Disable for NEON float modes when | ||
| 13 | flag_unsafe_math_optimizations is false. | ||
| 14 | * config/arm/neon.md (*add<mode>3_neon, *sub<mode>3_neon) | ||
| 15 | (*mul<mode>3_neon) | ||
| 16 | (mul<mode>3add<mode>_neon, mul<mode>3neg<mode>add<mode>_neon) | ||
| 17 | (reduc_splus_<mode>, reduc_smin_<mode>, reduc_smax_<mode>): Disable | ||
| 18 | for NEON float modes when flag_unsafe_math_optimizations is false. | ||
| 19 | (quad_halves_<code>v4sf): Only enable if flag_unsafe_math_optimizations | ||
| 20 | is true. | ||
| 21 | * doc/invoke.texi (ARM Options): Add note about floating point | ||
| 22 | vectorization requiring -funsafe-math-optimizations. | ||
| 23 | |||
| 24 | gcc/testsuite/ | ||
| 25 | * gcc.dg/vect/vect.exp: Add -ffast-math for NEON. | ||
| 26 | * gcc.dg/vect/vect-reduc-6.c: Add XFAIL for NEON. | ||
| 27 | |||
| 28 | 2010-07-08 Sandra Loosemore <sandra@codesourcery.com> | ||
| 29 | |||
| 30 | Backport from upstream (originally from Sourcery G++ 4.4): | ||
| 31 | |||
| 32 | === modified file 'gcc/config/arm/neon.md' | ||
| 33 | --- old/gcc/config/arm/neon.md 2010-07-29 15:59:12 +0000 | ||
| 34 | +++ new/gcc/config/arm/neon.md 2010-07-29 17:03:20 +0000 | ||
| 35 | @@ -819,7 +819,7 @@ | ||
| 36 | [(set (match_operand:VDQ 0 "s_register_operand" "=w") | ||
| 37 | (plus:VDQ (match_operand:VDQ 1 "s_register_operand" "w") | ||
| 38 | (match_operand:VDQ 2 "s_register_operand" "w")))] | ||
| 39 | - "TARGET_NEON" | ||
| 40 | + "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | ||
| 41 | "vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" | ||
| 42 | [(set (attr "neon_type") | ||
| 43 | (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0)) | ||
| 44 | @@ -853,7 +853,7 @@ | ||
| 45 | [(set (match_operand:VDQ 0 "s_register_operand" "=w") | ||
| 46 | (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w") | ||
| 47 | (match_operand:VDQ 2 "s_register_operand" "w")))] | ||
| 48 | - "TARGET_NEON" | ||
| 49 | + "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | ||
| 50 | "vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" | ||
| 51 | [(set (attr "neon_type") | ||
| 52 | (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0)) | ||
| 53 | @@ -888,7 +888,7 @@ | ||
| 54 | [(set (match_operand:VDQ 0 "s_register_operand" "=w") | ||
| 55 | (mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w") | ||
| 56 | (match_operand:VDQ 2 "s_register_operand" "w")))] | ||
| 57 | - "TARGET_NEON" | ||
| 58 | + "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | ||
| 59 | "vmul.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" | ||
| 60 | [(set (attr "neon_type") | ||
| 61 | (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0)) | ||
| 62 | @@ -910,7 +910,7 @@ | ||
| 63 | (plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w") | ||
| 64 | (match_operand:VDQ 3 "s_register_operand" "w")) | ||
| 65 | (match_operand:VDQ 1 "s_register_operand" "0")))] | ||
| 66 | - "TARGET_NEON" | ||
| 67 | + "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | ||
| 68 | "vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3" | ||
| 69 | [(set (attr "neon_type") | ||
| 70 | (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0)) | ||
| 71 | @@ -932,7 +932,7 @@ | ||
| 72 | (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0") | ||
| 73 | (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w") | ||
| 74 | (match_operand:VDQ 3 "s_register_operand" "w"))))] | ||
| 75 | - "TARGET_NEON" | ||
| 76 | + "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | ||
| 77 | "vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3" | ||
| 78 | [(set (attr "neon_type") | ||
| 79 | (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0)) | ||
| 80 | @@ -1361,7 +1361,7 @@ | ||
| 81 | (parallel [(const_int 0) (const_int 1)])) | ||
| 82 | (vec_select:V2SF (match_dup 1) | ||
| 83 | (parallel [(const_int 2) (const_int 3)]))))] | ||
| 84 | - "TARGET_NEON" | ||
| 85 | + "TARGET_NEON && flag_unsafe_math_optimizations" | ||
| 86 | "<VQH_mnem>.f32\t%P0, %e1, %f1" | ||
| 87 | [(set_attr "vqh_mnem" "<VQH_mnem>") | ||
| 88 | (set (attr "neon_type") | ||
| 89 | @@ -1496,7 +1496,7 @@ | ||
| 90 | (define_expand "reduc_splus_<mode>" | ||
| 91 | [(match_operand:VD 0 "s_register_operand" "") | ||
| 92 | (match_operand:VD 1 "s_register_operand" "")] | ||
| 93 | - "TARGET_NEON" | ||
| 94 | + "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | ||
| 95 | { | ||
| 96 | neon_pairwise_reduce (operands[0], operands[1], <MODE>mode, | ||
| 97 | &gen_neon_vpadd_internal<mode>); | ||
| 98 | @@ -1506,7 +1506,7 @@ | ||
| 99 | (define_expand "reduc_splus_<mode>" | ||
| 100 | [(match_operand:VQ 0 "s_register_operand" "") | ||
| 101 | (match_operand:VQ 1 "s_register_operand" "")] | ||
| 102 | - "TARGET_NEON" | ||
| 103 | + "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | ||
| 104 | { | ||
| 105 | rtx step1 = gen_reg_rtx (<V_HALF>mode); | ||
| 106 | rtx res_d = gen_reg_rtx (<V_HALF>mode); | ||
| 107 | @@ -1541,7 +1541,7 @@ | ||
| 108 | (define_expand "reduc_smin_<mode>" | ||
| 109 | [(match_operand:VD 0 "s_register_operand" "") | ||
| 110 | (match_operand:VD 1 "s_register_operand" "")] | ||
| 111 | - "TARGET_NEON" | ||
| 112 | + "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | ||
| 113 | { | ||
| 114 | neon_pairwise_reduce (operands[0], operands[1], <MODE>mode, | ||
| 115 | &gen_neon_vpsmin<mode>); | ||
| 116 | @@ -1551,7 +1551,7 @@ | ||
| 117 | (define_expand "reduc_smin_<mode>" | ||
| 118 | [(match_operand:VQ 0 "s_register_operand" "") | ||
| 119 | (match_operand:VQ 1 "s_register_operand" "")] | ||
| 120 | - "TARGET_NEON" | ||
| 121 | + "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | ||
| 122 | { | ||
| 123 | rtx step1 = gen_reg_rtx (<V_HALF>mode); | ||
| 124 | rtx res_d = gen_reg_rtx (<V_HALF>mode); | ||
| 125 | @@ -1566,7 +1566,7 @@ | ||
| 126 | (define_expand "reduc_smax_<mode>" | ||
| 127 | [(match_operand:VD 0 "s_register_operand" "") | ||
| 128 | (match_operand:VD 1 "s_register_operand" "")] | ||
| 129 | - "TARGET_NEON" | ||
| 130 | + "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | ||
| 131 | { | ||
| 132 | neon_pairwise_reduce (operands[0], operands[1], <MODE>mode, | ||
| 133 | &gen_neon_vpsmax<mode>); | ||
| 134 | @@ -1576,7 +1576,7 @@ | ||
| 135 | (define_expand "reduc_smax_<mode>" | ||
| 136 | [(match_operand:VQ 0 "s_register_operand" "") | ||
| 137 | (match_operand:VQ 1 "s_register_operand" "")] | ||
| 138 | - "TARGET_NEON" | ||
| 139 | + "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | ||
| 140 | { | ||
| 141 | rtx step1 = gen_reg_rtx (<V_HALF>mode); | ||
| 142 | rtx res_d = gen_reg_rtx (<V_HALF>mode); | ||
| 143 | |||
| 144 | === modified file 'gcc/config/arm/vec-common.md' | ||
| 145 | --- old/gcc/config/arm/vec-common.md 2009-11-11 14:23:03 +0000 | ||
| 146 | +++ new/gcc/config/arm/vec-common.md 2010-07-29 17:03:20 +0000 | ||
| 147 | @@ -57,7 +57,8 @@ | ||
| 148 | [(set (match_operand:VALL 0 "s_register_operand" "") | ||
| 149 | (plus:VALL (match_operand:VALL 1 "s_register_operand" "") | ||
| 150 | (match_operand:VALL 2 "s_register_operand" "")))] | ||
| 151 | - "TARGET_NEON | ||
| 152 | + "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) | ||
| 153 | + || flag_unsafe_math_optimizations)) | ||
| 154 | || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" | ||
| 155 | { | ||
| 156 | }) | ||
| 157 | @@ -66,7 +67,8 @@ | ||
| 158 | [(set (match_operand:VALL 0 "s_register_operand" "") | ||
| 159 | (minus:VALL (match_operand:VALL 1 "s_register_operand" "") | ||
| 160 | (match_operand:VALL 2 "s_register_operand" "")))] | ||
| 161 | - "TARGET_NEON | ||
| 162 | + "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) | ||
| 163 | + || flag_unsafe_math_optimizations)) | ||
| 164 | || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" | ||
| 165 | { | ||
| 166 | }) | ||
| 167 | @@ -75,7 +77,9 @@ | ||
| 168 | [(set (match_operand:VALLW 0 "s_register_operand" "") | ||
| 169 | (mult:VALLW (match_operand:VALLW 1 "s_register_operand" "") | ||
| 170 | (match_operand:VALLW 2 "s_register_operand" "")))] | ||
| 171 | - "TARGET_NEON || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)" | ||
| 172 | + "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) | ||
| 173 | + || flag_unsafe_math_optimizations)) | ||
| 174 | + || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)" | ||
| 175 | { | ||
| 176 | }) | ||
| 177 | |||
| 178 | @@ -83,7 +87,8 @@ | ||
| 179 | [(set (match_operand:VALLW 0 "s_register_operand" "") | ||
| 180 | (smin:VALLW (match_operand:VALLW 1 "s_register_operand" "") | ||
| 181 | (match_operand:VALLW 2 "s_register_operand" "")))] | ||
| 182 | - "TARGET_NEON | ||
| 183 | + "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) | ||
| 184 | + || flag_unsafe_math_optimizations)) | ||
| 185 | || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" | ||
| 186 | { | ||
| 187 | }) | ||
| 188 | @@ -101,7 +106,8 @@ | ||
| 189 | [(set (match_operand:VALLW 0 "s_register_operand" "") | ||
| 190 | (smax:VALLW (match_operand:VALLW 1 "s_register_operand" "") | ||
| 191 | (match_operand:VALLW 2 "s_register_operand" "")))] | ||
| 192 | - "TARGET_NEON | ||
| 193 | + "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) | ||
| 194 | + || flag_unsafe_math_optimizations)) | ||
| 195 | || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" | ||
| 196 | { | ||
| 197 | }) | ||
| 198 | |||
| 199 | === modified file 'gcc/doc/invoke.texi' | ||
| 200 | --- old/gcc/doc/invoke.texi 2010-07-29 15:53:39 +0000 | ||
| 201 | +++ new/gcc/doc/invoke.texi 2010-07-29 17:03:20 +0000 | ||
| 202 | @@ -9874,6 +9874,14 @@ | ||
| 203 | If @option{-msoft-float} is specified this specifies the format of | ||
| 204 | floating point values. | ||
| 205 | |||
| 206 | +If the selected floating-point hardware includes the NEON extension | ||
| 207 | +(e.g. @option{-mfpu}=@samp{neon}), note that floating-point | ||
| 208 | +operations will not be used by GCC's auto-vectorization pass unless | ||
| 209 | +@option{-funsafe-math-optimizations} is also specified. This is | ||
| 210 | +because NEON hardware does not fully implement the IEEE 754 standard for | ||
| 211 | +floating-point arithmetic (in particular denormal values are treated as | ||
| 212 | +zero), so the use of NEON instructions may lead to a loss of precision. | ||
| 213 | + | ||
| 214 | @item -mfp16-format=@var{name} | ||
| 215 | @opindex mfp16-format | ||
| 216 | Specify the format of the @code{__fp16} half-precision floating-point type. | ||
| 217 | |||
| 218 | === modified file 'gcc/testsuite/gcc.dg/vect/vect-reduc-6.c' | ||
| 219 | --- old/gcc/testsuite/gcc.dg/vect/vect-reduc-6.c 2007-09-04 12:05:19 +0000 | ||
| 220 | +++ new/gcc/testsuite/gcc.dg/vect/vect-reduc-6.c 2010-07-29 17:03:20 +0000 | ||
| 221 | @@ -49,5 +49,6 @@ | ||
| 222 | } | ||
| 223 | |||
| 224 | /* need -ffast-math to vectorizer these loops. */ | ||
| 225 | -/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" } } */ | ||
| 226 | +/* ARM NEON passes -ffast-math to these tests, so expect this to fail. */ | ||
| 227 | +/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail arm_neon_ok } } } */ | ||
| 228 | /* { dg-final { cleanup-tree-dump "vect" } } */ | ||
| 229 | |||
| 230 | === modified file 'gcc/testsuite/gcc.dg/vect/vect.exp' | ||
| 231 | --- old/gcc/testsuite/gcc.dg/vect/vect.exp 2010-07-29 15:38:15 +0000 | ||
| 232 | +++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2010-07-29 17:03:20 +0000 | ||
| 233 | @@ -102,6 +102,10 @@ | ||
| 234 | set dg-do-what-default run | ||
| 235 | } elseif [is-effective-target arm_neon_ok] { | ||
| 236 | eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""] | ||
| 237 | + # NEON does not support denormals, so is not used for vectorization by | ||
| 238 | + # default to avoid loss of precision. We must pass -ffast-math to test | ||
| 239 | + # vectorization of float operations. | ||
| 240 | + lappend DEFAULT_VECTCFLAGS "-ffast-math" | ||
| 241 | if [is-effective-target arm_neon_hw] { | ||
| 242 | set dg-do-what-default run | ||
| 243 | } else { | ||
| 244 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99303.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99303.patch deleted file mode 100644 index 53d1d08d5..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99303.patch +++ /dev/null | |||
| @@ -1,131 +0,0 @@ | |||
| 1 | Merge from Sourcery G++ 4.4: | ||
| 2 | |||
| 3 | 2009-05-21 Sandra Loosemore <sandra@codesourcery.com> | ||
| 4 | |||
| 5 | Merge from Sourcery G++ 4.3: | ||
| 6 | |||
| 7 | 2009-04-04 Sandra Loosemore <sandra@codesourcery.com> | ||
| 8 | |||
| 9 | Issue #5104 | ||
| 10 | PR tree-optimization/39604 | ||
| 11 | |||
| 12 | gcc/testsuite | ||
| 13 | * g++.dg/tree-ssa/sink-1.C: New. | ||
| 14 | |||
| 15 | gcc/ | ||
| 16 | * tree_ssa-sink.c (sink_code_in_bb): Do not sink statements out | ||
| 17 | of a lexical block containing variable definitions. | ||
| 18 | |||
| 19 | 2010-07-09 Sandra Loosemore <sandra@codesourcery.com> | ||
| 20 | |||
| 21 | Backport from mainline (originally on Sourcery G++ 4.4): | ||
| 22 | |||
| 23 | 2010-07-02 Julian Brown <julian@codesourcery.com> | ||
| 24 | |||
| 25 | === added file 'gcc/testsuite/g++.dg/tree-ssa/sink-1.C' | ||
| 26 | --- old/gcc/testsuite/g++.dg/tree-ssa/sink-1.C 1970-01-01 00:00:00 +0000 | ||
| 27 | +++ new/gcc/testsuite/g++.dg/tree-ssa/sink-1.C 2010-07-30 12:14:18 +0000 | ||
| 28 | @@ -0,0 +1,50 @@ | ||
| 29 | +/* { dg-do run } */ | ||
| 30 | +/* { dg-options "-O1" } */ | ||
| 31 | + | ||
| 32 | +class A { | ||
| 33 | + public: | ||
| 34 | + A() {} | ||
| 35 | + virtual ~A() {} | ||
| 36 | + void * dostuff(); | ||
| 37 | + | ||
| 38 | + virtual int dovirtual() = 0; | ||
| 39 | +}; | ||
| 40 | + | ||
| 41 | + | ||
| 42 | +class B : public A { | ||
| 43 | + public: | ||
| 44 | + B() {} | ||
| 45 | + int dovirtual() { return 0;} | ||
| 46 | + virtual ~B() {}; | ||
| 47 | +}; | ||
| 48 | + | ||
| 49 | +class C : public B { | ||
| 50 | + public: | ||
| 51 | + C() {} | ||
| 52 | + virtual ~C() {}; | ||
| 53 | +}; | ||
| 54 | + | ||
| 55 | +void* A::dostuff() | ||
| 56 | +{ | ||
| 57 | + return (void*)dovirtual(); | ||
| 58 | +} | ||
| 59 | + | ||
| 60 | +/* tree-ssa-sink was sinking the inlined destructor for STUFF out of | ||
| 61 | + the first inner block and into the second one, where it was ending up | ||
| 62 | + after the inlined constructor for STUFF2. This is bad because | ||
| 63 | + cfgexpand aliases STUFF and STUFF2 to the same storage at -O1 | ||
| 64 | + (i.e., without -fstrict-aliasing), with the result that STUFF2's | ||
| 65 | + vtable was getting trashed. */ | ||
| 66 | + | ||
| 67 | +int main() { | ||
| 68 | + { | ||
| 69 | + B stuff; | ||
| 70 | + stuff.dostuff(); | ||
| 71 | + } | ||
| 72 | + { | ||
| 73 | + C stuff2; | ||
| 74 | + stuff2.dostuff(); | ||
| 75 | + } | ||
| 76 | + return 0; | ||
| 77 | +} | ||
| 78 | + | ||
| 79 | |||
| 80 | === modified file 'gcc/tree-ssa-sink.c' | ||
| 81 | --- old/gcc/tree-ssa-sink.c 2009-11-28 16:21:00 +0000 | ||
| 82 | +++ new/gcc/tree-ssa-sink.c 2010-07-30 12:14:18 +0000 | ||
| 83 | @@ -470,6 +470,47 @@ | ||
| 84 | last = false; | ||
| 85 | continue; | ||
| 86 | } | ||
| 87 | + | ||
| 88 | + /* We cannot move statements that contain references to block-scope | ||
| 89 | + variables out of that block, as this may lead to incorrect aliasing | ||
| 90 | + when we lay out the stack frame in cfgexpand.c. | ||
| 91 | + In lieu of more sophisticated analysis, be very conservative here | ||
| 92 | + and prohibit moving any statement that references memory out of a | ||
| 93 | + block with variables. */ | ||
| 94 | + if (gimple_references_memory_p (stmt)) | ||
| 95 | + { | ||
| 96 | + tree fromblock = gimple_block (stmt); | ||
| 97 | + while (fromblock | ||
| 98 | + && fromblock != current_function_decl | ||
| 99 | + && !BLOCK_VARS (fromblock)) | ||
| 100 | + fromblock = BLOCK_SUPERCONTEXT (fromblock); | ||
| 101 | + if (fromblock && fromblock != current_function_decl) | ||
| 102 | + { | ||
| 103 | + gimple tostmt; | ||
| 104 | + tree toblock; | ||
| 105 | + | ||
| 106 | + if (gsi_end_p (togsi)) | ||
| 107 | + tostmt = gimple_seq_last_stmt (gsi_seq (togsi)); | ||
| 108 | + else | ||
| 109 | + tostmt = gsi_stmt (togsi); | ||
| 110 | + if (tostmt) | ||
| 111 | + toblock = gimple_block (tostmt); | ||
| 112 | + else | ||
| 113 | + toblock = NULL; | ||
| 114 | + while (toblock | ||
| 115 | + && toblock != current_function_decl | ||
| 116 | + && toblock != fromblock) | ||
| 117 | + toblock = BLOCK_SUPERCONTEXT (toblock); | ||
| 118 | + if (!toblock || toblock != fromblock) | ||
| 119 | + { | ||
| 120 | + if (!gsi_end_p (gsi)) | ||
| 121 | + gsi_prev (&gsi); | ||
| 122 | + last = false; | ||
| 123 | + continue; | ||
| 124 | + } | ||
| 125 | + } | ||
| 126 | + } | ||
| 127 | + | ||
| 128 | if (dump_file) | ||
| 129 | { | ||
| 130 | fprintf (dump_file, "Sinking "); | ||
| 131 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99304.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99304.patch deleted file mode 100644 index ab1296347..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99304.patch +++ /dev/null | |||
| @@ -1,81 +0,0 @@ | |||
| 1 | 2010-07-10 Yao Qi <yao@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ 4.4: | ||
| 4 | |||
| 5 | 2009-05-28 Julian Brown <julian@codesourcery.com> | ||
| 6 | |||
| 7 | Merged from Sourcery G++ 4.3: | ||
| 8 | |||
| 9 | libgcc/ | ||
| 10 | * config.host (arm*-*-linux*, arm*-*-uclinux*, arm*-*-eabi*) | ||
| 11 | (arm*-*-symbianelf): Add arm/t-divmod-ef to tmake_file. | ||
| 12 | * Makefile.in (LIB2_DIVMOD_EXCEPTION_FLAGS): Set to previous | ||
| 13 | default if not set by a target-specific Makefile fragment. | ||
| 14 | (lib2-divmod-o, lib2-divmod-s-o): Use above. | ||
| 15 | * config/arm/t-divmod-ef: New. | ||
| 16 | |||
| 17 | 2010-07-09 Sandra Loosemore <sandra@codesourcery.com> | ||
| 18 | |||
| 19 | Merge from Sourcery G++ 4.4: | ||
| 20 | |||
| 21 | === modified file 'libgcc/Makefile.in' | ||
| 22 | --- old/libgcc/Makefile.in 2010-03-30 12:08:52 +0000 | ||
| 23 | +++ new/libgcc/Makefile.in 2010-07-30 12:21:02 +0000 | ||
| 24 | @@ -400,18 +400,24 @@ | ||
| 25 | endif | ||
| 26 | endif | ||
| 27 | |||
| 28 | +ifeq ($(LIB2_DIVMOD_EXCEPTION_FLAGS),) | ||
| 29 | +# Provide default flags for compiling divmod functions, if they haven't been | ||
| 30 | +# set already by a target-specific Makefile fragment. | ||
| 31 | +LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions -fnon-call-exceptions | ||
| 32 | +endif | ||
| 33 | + | ||
| 34 | # Build LIB2_DIVMOD_FUNCS. | ||
| 35 | lib2-divmod-o = $(patsubst %,%$(objext),$(LIB2_DIVMOD_FUNCS)) | ||
| 36 | $(lib2-divmod-o): %$(objext): $(gcc_srcdir)/libgcc2.c | ||
| 37 | $(gcc_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \ | ||
| 38 | - -fexceptions -fnon-call-exceptions $(vis_hide) | ||
| 39 | + $(LIB2_DIVMOD_EXCEPTION_FLAGS) $(vis_hide) | ||
| 40 | libgcc-objects += $(lib2-divmod-o) | ||
| 41 | |||
| 42 | ifeq ($(enable_shared),yes) | ||
| 43 | lib2-divmod-s-o = $(patsubst %,%_s$(objext),$(LIB2_DIVMOD_FUNCS)) | ||
| 44 | $(lib2-divmod-s-o): %_s$(objext): $(gcc_srcdir)/libgcc2.c | ||
| 45 | $(gcc_s_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \ | ||
| 46 | - -fexceptions -fnon-call-exceptions | ||
| 47 | + $(LIB2_DIVMOD_EXCEPTION_FLAGS) | ||
| 48 | libgcc-s-objects += $(lib2-divmod-s-o) | ||
| 49 | endif | ||
| 50 | |||
| 51 | |||
| 52 | === modified file 'libgcc/config.host' | ||
| 53 | --- old/libgcc/config.host 2010-04-02 02:02:18 +0000 | ||
| 54 | +++ new/libgcc/config.host 2010-07-30 12:21:02 +0000 | ||
| 55 | @@ -208,12 +208,15 @@ | ||
| 56 | arm*-*-netbsd*) | ||
| 57 | ;; | ||
| 58 | arm*-*-linux*) # ARM GNU/Linux with ELF | ||
| 59 | + tmake_file="${tmake_file} arm/t-divmod-ef" | ||
| 60 | ;; | ||
| 61 | arm*-*-uclinux*) # ARM ucLinux | ||
| 62 | + tmake_file="${tmake_file} arm/t-divmod-ef" | ||
| 63 | ;; | ||
| 64 | arm*-*-ecos-elf) | ||
| 65 | ;; | ||
| 66 | arm*-*-eabi* | arm*-*-symbianelf* ) | ||
| 67 | + tmake_file="${tmake_file} arm/t-divmod-ef" | ||
| 68 | ;; | ||
| 69 | arm*-*-rtems*) | ||
| 70 | ;; | ||
| 71 | |||
| 72 | === added directory 'libgcc/config/arm' | ||
| 73 | === added file 'libgcc/config/arm/t-divmod-ef' | ||
| 74 | --- old/libgcc/config/arm/t-divmod-ef 1970-01-01 00:00:00 +0000 | ||
| 75 | +++ new/libgcc/config/arm/t-divmod-ef 2010-07-30 12:21:02 +0000 | ||
| 76 | @@ -0,0 +1,4 @@ | ||
| 77 | +# On ARM, specifying -fnon-call-exceptions will needlessly pull in | ||
| 78 | +# the unwinder in simple programs which use 64-bit division. Omitting | ||
| 79 | +# the option is safe. | ||
| 80 | +LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions | ||
| 81 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99305.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99305.patch deleted file mode 100644 index ed25334df..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99305.patch +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | 2009-09-02 Daniel Jacobowitz <dan@codesourcery.com> | ||
| 2 | |||
| 3 | libgcc/ | ||
| 4 | * shared-object.mk (c_flags-$(base)$(objext)): New. | ||
| 5 | ($(base)$(objext)): Use above. | ||
| 6 | ($(base)_s$(objext)): Likewise. | ||
| 7 | * static-object.mk (c_flags-$(base)$(objext)): New. | ||
| 8 | ($(base)$(objext)): Use above. | ||
| 9 | |||
| 10 | 2010-07-10 Yao Qi <yao@codesourcery.com> | ||
| 11 | |||
| 12 | Merge from Sourcery G++ 4.4: | ||
| 13 | |||
| 14 | 2009-05-28 Julian Brown <julian@codesourcery.com> | ||
| 15 | |||
| 16 | Merged from Sourcery G++ 4.3: | ||
| 17 | |||
| 18 | === modified file 'libgcc/shared-object.mk' | ||
| 19 | --- old/libgcc/shared-object.mk 2008-07-03 18:22:00 +0000 | ||
| 20 | +++ new/libgcc/shared-object.mk 2010-07-30 13:11:02 +0000 | ||
| 21 | @@ -8,11 +8,13 @@ | ||
| 22 | |||
| 23 | ifeq ($(suffix $o),.c) | ||
| 24 | |||
| 25 | +c_flags-$(base)$(objext) := $(c_flags) | ||
| 26 | $(base)$(objext): $o | ||
| 27 | - $(gcc_compile) $(c_flags) -c $< $(vis_hide) | ||
| 28 | + $(gcc_compile) $(c_flags-$@) -c $< $(vis_hide) | ||
| 29 | |||
| 30 | +c_flags-$(base)_s$(objext) := $(c_flags) | ||
| 31 | $(base)_s$(objext): $o | ||
| 32 | - $(gcc_s_compile) $(c_flags) -c $< | ||
| 33 | + $(gcc_s_compile) $(c_flags-$@) -c $< | ||
| 34 | |||
| 35 | else | ||
| 36 | |||
| 37 | |||
| 38 | === modified file 'libgcc/static-object.mk' | ||
| 39 | --- old/libgcc/static-object.mk 2007-01-04 04:22:37 +0000 | ||
| 40 | +++ new/libgcc/static-object.mk 2010-07-30 13:11:02 +0000 | ||
| 41 | @@ -8,8 +8,9 @@ | ||
| 42 | |||
| 43 | ifeq ($(suffix $o),.c) | ||
| 44 | |||
| 45 | +c_flags-$(base)$(objext) := $(c_flags) | ||
| 46 | $(base)$(objext): $o | ||
| 47 | - $(gcc_compile) $(c_flags) -c $< $(vis_hide) | ||
| 48 | + $(gcc_compile) $(c_flags-$@) -c $< $(vis_hide) | ||
| 49 | |||
| 50 | else | ||
| 51 | |||
| 52 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99306.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99306.patch deleted file mode 100644 index 423cd5652..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99306.patch +++ /dev/null | |||
| @@ -1,1401 +0,0 @@ | |||
| 1 | 2010-07-10 Sandra Loosemore <sandra@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-05-08 Sandra Loosemore <sandra@codesourcery.com> | ||
| 6 | |||
| 7 | PR middle-end/28685 | ||
| 8 | |||
| 9 | gcc/ | ||
| 10 | * tree-ssa-reassoc.c (eliminate_redundant_comparison): New function. | ||
| 11 | (optimize_ops_list): Call it. | ||
| 12 | |||
| 13 | gcc/testsuite/ | ||
| 14 | * gcc.dg/pr28685-1.c: New file. | ||
| 15 | |||
| 16 | 2010-06-08 Sandra Loosemore <sandra@codesourcery.com> | ||
| 17 | |||
| 18 | PR tree-optimization/39874 | ||
| 19 | PR middle-end/28685 | ||
| 20 | |||
| 21 | gcc/ | ||
| 22 | * gimple.h (maybe_fold_and_comparisons, maybe_fold_or_comparisons): | ||
| 23 | Declare. | ||
| 24 | * gimple-fold.c (canonicalize_bool, same_bool_comparison_p, | ||
| 25 | same_bool_result_p): New. | ||
| 26 | (and_var_with_comparison, and_var_with_comparison_1, | ||
| 27 | and_comparisons_1, and_comparisons, maybe_fold_and_comparisons): New. | ||
| 28 | (or_var_with_comparison, or_var_with_comparison_1, | ||
| 29 | or_comparisons_1, or_comparisons, maybe_fold_or_comparisons): New. | ||
| 30 | * tree-ssa-reassoc.c (eliminate_redundant_comparison): Use | ||
| 31 | maybe_fold_and_comparisons or maybe_fold_or_comparisons instead | ||
| 32 | of combine_comparisons. | ||
| 33 | * tree-ssa-ifcombine.c (ifcombine_ifandif, ifcombine_iforif): Likewise. | ||
| 34 | |||
| 35 | gcc/testsuite/ | ||
| 36 | * gcc.dg/pr39874.c: New file. | ||
| 37 | |||
| 38 | 2010-07-10 Yao Qi <yao@codesourcery.com> | ||
| 39 | |||
| 40 | Merge from Sourcery G++ 4.4: | ||
| 41 | |||
| 42 | === modified file 'gcc/gimple.h' | ||
| 43 | --- old/gcc/gimple.h 2010-04-02 18:54:46 +0000 | ||
| 44 | +++ new/gcc/gimple.h 2010-07-30 13:21:51 +0000 | ||
| 45 | @@ -4743,4 +4743,9 @@ | ||
| 46 | |||
| 47 | extern void dump_gimple_statistics (void); | ||
| 48 | |||
| 49 | +extern tree maybe_fold_and_comparisons (enum tree_code, tree, tree, | ||
| 50 | + enum tree_code, tree, tree); | ||
| 51 | +extern tree maybe_fold_or_comparisons (enum tree_code, tree, tree, | ||
| 52 | + enum tree_code, tree, tree); | ||
| 53 | + | ||
| 54 | #endif /* GCC_GIMPLE_H */ | ||
| 55 | |||
| 56 | === added file 'gcc/testsuite/gcc.dg/pr28685-1.c' | ||
| 57 | --- old/gcc/testsuite/gcc.dg/pr28685-1.c 1970-01-01 00:00:00 +0000 | ||
| 58 | +++ new/gcc/testsuite/gcc.dg/pr28685-1.c 2010-07-30 13:21:51 +0000 | ||
| 59 | @@ -0,0 +1,50 @@ | ||
| 60 | +/* { dg-do compile } */ | ||
| 61 | +/* { dg-options "-O2 -fdump-tree-optimized" } */ | ||
| 62 | + | ||
| 63 | +/* Should produce <=. */ | ||
| 64 | +int test1 (int a, int b) | ||
| 65 | +{ | ||
| 66 | + return (a < b || a == b); | ||
| 67 | +} | ||
| 68 | + | ||
| 69 | +/* Should produce <=. */ | ||
| 70 | +int test2 (int a, int b) | ||
| 71 | +{ | ||
| 72 | + int lt = a < b; | ||
| 73 | + int eq = a == b; | ||
| 74 | + | ||
| 75 | + return (lt || eq); | ||
| 76 | +} | ||
| 77 | + | ||
| 78 | +/* Should produce <= (just deleting redundant test). */ | ||
| 79 | +int test3 (int a, int b) | ||
| 80 | +{ | ||
| 81 | + int lt = a <= b; | ||
| 82 | + int eq = a == b; | ||
| 83 | + | ||
| 84 | + return (lt || eq); | ||
| 85 | +} | ||
| 86 | + | ||
| 87 | +/* Should produce <= (operands reversed to test the swap logic). */ | ||
| 88 | +int test4 (int a, int b) | ||
| 89 | +{ | ||
| 90 | + int lt = a < b; | ||
| 91 | + int eq = b == a; | ||
| 92 | + | ||
| 93 | + return (lt || eq); | ||
| 94 | +} | ||
| 95 | + | ||
| 96 | +/* Should produce constant 0. */ | ||
| 97 | +int test5 (int a, int b) | ||
| 98 | +{ | ||
| 99 | + int lt = a < b; | ||
| 100 | + int eq = a == b; | ||
| 101 | + | ||
| 102 | + return (lt && eq); | ||
| 103 | +} | ||
| 104 | + | ||
| 105 | +/* { dg-final { scan-tree-dump-times " <= " 4 "optimized" } } */ | ||
| 106 | +/* { dg-final { scan-tree-dump-times "return 0" 1 "optimized" } } */ | ||
| 107 | +/* { dg-final { scan-tree-dump-not " < " "optimized" } } */ | ||
| 108 | +/* { dg-final { scan-tree-dump-not " == " "optimized" } } */ | ||
| 109 | +/* { dg-final { cleanup-tree-dump "optimized" } } */ | ||
| 110 | |||
| 111 | === added file 'gcc/testsuite/gcc.dg/pr39874.c' | ||
| 112 | --- old/gcc/testsuite/gcc.dg/pr39874.c 1970-01-01 00:00:00 +0000 | ||
| 113 | +++ new/gcc/testsuite/gcc.dg/pr39874.c 2010-07-30 13:21:51 +0000 | ||
| 114 | @@ -0,0 +1,29 @@ | ||
| 115 | +/* { dg-do compile } */ | ||
| 116 | +/* { dg-options "-O2 -fdump-tree-optimized" } */ | ||
| 117 | + | ||
| 118 | +extern void func(); | ||
| 119 | + | ||
| 120 | +void test1(char *signature) | ||
| 121 | +{ | ||
| 122 | + char ch = signature[0]; | ||
| 123 | + if (ch == 15 || ch == 3) | ||
| 124 | + { | ||
| 125 | + if (ch == 15) func(); | ||
| 126 | + } | ||
| 127 | +} | ||
| 128 | + | ||
| 129 | + | ||
| 130 | +void test2(char *signature) | ||
| 131 | +{ | ||
| 132 | + char ch = signature[0]; | ||
| 133 | + if (ch == 15 || ch == 3) | ||
| 134 | + { | ||
| 135 | + if (ch > 14) func(); | ||
| 136 | + } | ||
| 137 | +} | ||
| 138 | + | ||
| 139 | +/* { dg-final { scan-tree-dump-times " == 15" 2 "optimized" } } */ | ||
| 140 | +/* { dg-final { scan-tree-dump-not " == 3" "optimized" } } */ | ||
| 141 | +/* { dg-final { cleanup-tree-dump "optimized" } } */ | ||
| 142 | + | ||
| 143 | + | ||
| 144 | |||
| 145 | === modified file 'gcc/tree-ssa-ccp.c' | ||
| 146 | --- old/gcc/tree-ssa-ccp.c 2010-04-02 15:50:04 +0000 | ||
| 147 | +++ new/gcc/tree-ssa-ccp.c 2010-07-30 13:21:51 +0000 | ||
| 148 | @@ -3176,6 +3176,1056 @@ | ||
| 149 | return changed; | ||
| 150 | } | ||
| 151 | |||
| 152 | +/* Canonicalize and possibly invert the boolean EXPR; return NULL_TREE | ||
| 153 | + if EXPR is null or we don't know how. | ||
| 154 | + If non-null, the result always has boolean type. */ | ||
| 155 | + | ||
| 156 | +static tree | ||
| 157 | +canonicalize_bool (tree expr, bool invert) | ||
| 158 | +{ | ||
| 159 | + if (!expr) | ||
| 160 | + return NULL_TREE; | ||
| 161 | + else if (invert) | ||
| 162 | + { | ||
| 163 | + if (integer_nonzerop (expr)) | ||
| 164 | + return boolean_false_node; | ||
| 165 | + else if (integer_zerop (expr)) | ||
| 166 | + return boolean_true_node; | ||
| 167 | + else if (TREE_CODE (expr) == SSA_NAME) | ||
| 168 | + return fold_build2 (EQ_EXPR, boolean_type_node, expr, | ||
| 169 | + build_int_cst (TREE_TYPE (expr), 0)); | ||
| 170 | + else if (TREE_CODE_CLASS (TREE_CODE (expr)) == tcc_comparison) | ||
| 171 | + return fold_build2 (invert_tree_comparison (TREE_CODE (expr), false), | ||
| 172 | + boolean_type_node, | ||
| 173 | + TREE_OPERAND (expr, 0), | ||
| 174 | + TREE_OPERAND (expr, 1)); | ||
| 175 | + else | ||
| 176 | + return NULL_TREE; | ||
| 177 | + } | ||
| 178 | + else | ||
| 179 | + { | ||
| 180 | + if (TREE_CODE (TREE_TYPE (expr)) == BOOLEAN_TYPE) | ||
| 181 | + return expr; | ||
| 182 | + if (integer_nonzerop (expr)) | ||
| 183 | + return boolean_true_node; | ||
| 184 | + else if (integer_zerop (expr)) | ||
| 185 | + return boolean_false_node; | ||
| 186 | + else if (TREE_CODE (expr) == SSA_NAME) | ||
| 187 | + return fold_build2 (NE_EXPR, boolean_type_node, expr, | ||
| 188 | + build_int_cst (TREE_TYPE (expr), 0)); | ||
| 189 | + else if (TREE_CODE_CLASS (TREE_CODE (expr)) == tcc_comparison) | ||
| 190 | + return fold_build2 (TREE_CODE (expr), | ||
| 191 | + boolean_type_node, | ||
| 192 | + TREE_OPERAND (expr, 0), | ||
| 193 | + TREE_OPERAND (expr, 1)); | ||
| 194 | + else | ||
| 195 | + return NULL_TREE; | ||
| 196 | + } | ||
| 197 | +} | ||
| 198 | + | ||
| 199 | +/* Check to see if a boolean expression EXPR is logically equivalent to the | ||
| 200 | + comparison (OP1 CODE OP2). Check for various identities involving | ||
| 201 | + SSA_NAMEs. */ | ||
| 202 | + | ||
| 203 | +static bool | ||
| 204 | +same_bool_comparison_p (const_tree expr, enum tree_code code, | ||
| 205 | + const_tree op1, const_tree op2) | ||
| 206 | +{ | ||
| 207 | + gimple s; | ||
| 208 | + | ||
| 209 | + /* The obvious case. */ | ||
| 210 | + if (TREE_CODE (expr) == code | ||
| 211 | + && operand_equal_p (TREE_OPERAND (expr, 0), op1, 0) | ||
| 212 | + && operand_equal_p (TREE_OPERAND (expr, 1), op2, 0)) | ||
| 213 | + return true; | ||
| 214 | + | ||
| 215 | + /* Check for comparing (name, name != 0) and the case where expr | ||
| 216 | + is an SSA_NAME with a definition matching the comparison. */ | ||
| 217 | + if (TREE_CODE (expr) == SSA_NAME | ||
| 218 | + && TREE_CODE (TREE_TYPE (expr)) == BOOLEAN_TYPE) | ||
| 219 | + { | ||
| 220 | + if (operand_equal_p (expr, op1, 0)) | ||
| 221 | + return ((code == NE_EXPR && integer_zerop (op2)) | ||
| 222 | + || (code == EQ_EXPR && integer_nonzerop (op2))); | ||
| 223 | + s = SSA_NAME_DEF_STMT (expr); | ||
| 224 | + if (is_gimple_assign (s) | ||
| 225 | + && gimple_assign_rhs_code (s) == code | ||
| 226 | + && operand_equal_p (gimple_assign_rhs1 (s), op1, 0) | ||
| 227 | + && operand_equal_p (gimple_assign_rhs2 (s), op2, 0)) | ||
| 228 | + return true; | ||
| 229 | + } | ||
| 230 | + | ||
| 231 | + /* If op1 is of the form (name != 0) or (name == 0), and the definition | ||
| 232 | + of name is a comparison, recurse. */ | ||
| 233 | + if (TREE_CODE (op1) == SSA_NAME | ||
| 234 | + && TREE_CODE (TREE_TYPE (op1)) == BOOLEAN_TYPE) | ||
| 235 | + { | ||
| 236 | + s = SSA_NAME_DEF_STMT (op1); | ||
| 237 | + if (is_gimple_assign (s) | ||
| 238 | + && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison) | ||
| 239 | + { | ||
| 240 | + enum tree_code c = gimple_assign_rhs_code (s); | ||
| 241 | + if ((c == NE_EXPR && integer_zerop (op2)) | ||
| 242 | + || (c == EQ_EXPR && integer_nonzerop (op2))) | ||
| 243 | + return same_bool_comparison_p (expr, c, | ||
| 244 | + gimple_assign_rhs1 (s), | ||
| 245 | + gimple_assign_rhs2 (s)); | ||
| 246 | + if ((c == EQ_EXPR && integer_zerop (op2)) | ||
| 247 | + || (c == NE_EXPR && integer_nonzerop (op2))) | ||
| 248 | + return same_bool_comparison_p (expr, | ||
| 249 | + invert_tree_comparison (c, false), | ||
| 250 | + gimple_assign_rhs1 (s), | ||
| 251 | + gimple_assign_rhs2 (s)); | ||
| 252 | + } | ||
| 253 | + } | ||
| 254 | + return false; | ||
| 255 | +} | ||
| 256 | + | ||
| 257 | +/* Check to see if two boolean expressions OP1 and OP2 are logically | ||
| 258 | + equivalent. */ | ||
| 259 | + | ||
| 260 | +static bool | ||
| 261 | +same_bool_result_p (const_tree op1, const_tree op2) | ||
| 262 | +{ | ||
| 263 | + /* Simple cases first. */ | ||
| 264 | + if (operand_equal_p (op1, op2, 0)) | ||
| 265 | + return true; | ||
| 266 | + | ||
| 267 | + /* Check the cases where at least one of the operands is a comparison. | ||
| 268 | + These are a bit smarter than operand_equal_p in that they apply some | ||
| 269 | + identifies on SSA_NAMEs. */ | ||
| 270 | + if (TREE_CODE_CLASS (TREE_CODE (op2)) == tcc_comparison | ||
| 271 | + && same_bool_comparison_p (op1, TREE_CODE (op2), | ||
| 272 | + TREE_OPERAND (op2, 0), | ||
| 273 | + TREE_OPERAND (op2, 1))) | ||
| 274 | + return true; | ||
| 275 | + if (TREE_CODE_CLASS (TREE_CODE (op1)) == tcc_comparison | ||
| 276 | + && same_bool_comparison_p (op2, TREE_CODE (op1), | ||
| 277 | + TREE_OPERAND (op1, 0), | ||
| 278 | + TREE_OPERAND (op1, 1))) | ||
| 279 | + return true; | ||
| 280 | + | ||
| 281 | + /* Default case. */ | ||
| 282 | + return false; | ||
| 283 | +} | ||
| 284 | + | ||
| 285 | +/* Forward declarations for some mutually recursive functions. */ | ||
| 286 | + | ||
| 287 | +static tree | ||
| 288 | +and_comparisons_1 (enum tree_code code1, tree op1a, tree op1b, | ||
| 289 | + enum tree_code code2, tree op2a, tree op2b); | ||
| 290 | +static tree | ||
| 291 | +and_var_with_comparison (tree var, bool invert, | ||
| 292 | + enum tree_code code2, tree op2a, tree op2b); | ||
| 293 | +static tree | ||
| 294 | +and_var_with_comparison_1 (gimple stmt, | ||
| 295 | + enum tree_code code2, tree op2a, tree op2b); | ||
| 296 | +static tree | ||
| 297 | +or_comparisons_1 (enum tree_code code1, tree op1a, tree op1b, | ||
| 298 | + enum tree_code code2, tree op2a, tree op2b); | ||
| 299 | +static tree | ||
| 300 | +or_var_with_comparison (tree var, bool invert, | ||
| 301 | + enum tree_code code2, tree op2a, tree op2b); | ||
| 302 | +static tree | ||
| 303 | +or_var_with_comparison_1 (gimple stmt, | ||
| 304 | + enum tree_code code2, tree op2a, tree op2b); | ||
| 305 | + | ||
| 306 | +/* Helper function for and_comparisons_1: try to simplify the AND of the | ||
| 307 | + ssa variable VAR with the comparison specified by (OP2A CODE2 OP2B). | ||
| 308 | + If INVERT is true, invert the value of the VAR before doing the AND. | ||
| 309 | + Return NULL_EXPR if we can't simplify this to a single expression. */ | ||
| 310 | + | ||
| 311 | +static tree | ||
| 312 | +and_var_with_comparison (tree var, bool invert, | ||
| 313 | + enum tree_code code2, tree op2a, tree op2b) | ||
| 314 | +{ | ||
| 315 | + tree t; | ||
| 316 | + gimple stmt = SSA_NAME_DEF_STMT (var); | ||
| 317 | + | ||
| 318 | + /* We can only deal with variables whose definitions are assignments. */ | ||
| 319 | + if (!is_gimple_assign (stmt)) | ||
| 320 | + return NULL_TREE; | ||
| 321 | + | ||
| 322 | + /* If we have an inverted comparison, apply DeMorgan's law and rewrite | ||
| 323 | + !var AND (op2a code2 op2b) => !(var OR !(op2a code2 op2b)) | ||
| 324 | + Then we only have to consider the simpler non-inverted cases. */ | ||
| 325 | + if (invert) | ||
| 326 | + t = or_var_with_comparison_1 (stmt, | ||
| 327 | + invert_tree_comparison (code2, false), | ||
| 328 | + op2a, op2b); | ||
| 329 | + else | ||
| 330 | + t = and_var_with_comparison_1 (stmt, code2, op2a, op2b); | ||
| 331 | + return canonicalize_bool (t, invert); | ||
| 332 | +} | ||
| 333 | + | ||
| 334 | +/* Try to simplify the AND of the ssa variable defined by the assignment | ||
| 335 | + STMT with the comparison specified by (OP2A CODE2 OP2B). | ||
| 336 | + Return NULL_EXPR if we can't simplify this to a single expression. */ | ||
| 337 | + | ||
| 338 | +static tree | ||
| 339 | +and_var_with_comparison_1 (gimple stmt, | ||
| 340 | + enum tree_code code2, tree op2a, tree op2b) | ||
| 341 | +{ | ||
| 342 | + tree var = gimple_assign_lhs (stmt); | ||
| 343 | + tree true_test_var = NULL_TREE; | ||
| 344 | + tree false_test_var = NULL_TREE; | ||
| 345 | + enum tree_code innercode = gimple_assign_rhs_code (stmt); | ||
| 346 | + | ||
| 347 | + /* Check for identities like (var AND (var == 0)) => false. */ | ||
| 348 | + if (TREE_CODE (op2a) == SSA_NAME | ||
| 349 | + && TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE) | ||
| 350 | + { | ||
| 351 | + if ((code2 == NE_EXPR && integer_zerop (op2b)) | ||
| 352 | + || (code2 == EQ_EXPR && integer_nonzerop (op2b))) | ||
| 353 | + { | ||
| 354 | + true_test_var = op2a; | ||
| 355 | + if (var == true_test_var) | ||
| 356 | + return var; | ||
| 357 | + } | ||
| 358 | + else if ((code2 == EQ_EXPR && integer_zerop (op2b)) | ||
| 359 | + || (code2 == NE_EXPR && integer_nonzerop (op2b))) | ||
| 360 | + { | ||
| 361 | + false_test_var = op2a; | ||
| 362 | + if (var == false_test_var) | ||
| 363 | + return boolean_false_node; | ||
| 364 | + } | ||
| 365 | + } | ||
| 366 | + | ||
| 367 | + /* If the definition is a comparison, recurse on it. */ | ||
| 368 | + if (TREE_CODE_CLASS (innercode) == tcc_comparison) | ||
| 369 | + { | ||
| 370 | + tree t = and_comparisons_1 (innercode, | ||
| 371 | + gimple_assign_rhs1 (stmt), | ||
| 372 | + gimple_assign_rhs2 (stmt), | ||
| 373 | + code2, | ||
| 374 | + op2a, | ||
| 375 | + op2b); | ||
| 376 | + if (t) | ||
| 377 | + return t; | ||
| 378 | + } | ||
| 379 | + | ||
| 380 | + /* If the definition is an AND or OR expression, we may be able to | ||
| 381 | + simplify by reassociating. */ | ||
| 382 | + if (innercode == TRUTH_AND_EXPR | ||
| 383 | + || innercode == TRUTH_OR_EXPR | ||
| 384 | + || (TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE | ||
| 385 | + && (innercode == BIT_AND_EXPR || innercode == BIT_IOR_EXPR))) | ||
| 386 | + { | ||
| 387 | + tree inner1 = gimple_assign_rhs1 (stmt); | ||
| 388 | + tree inner2 = gimple_assign_rhs2 (stmt); | ||
| 389 | + gimple s; | ||
| 390 | + tree t; | ||
| 391 | + tree partial = NULL_TREE; | ||
| 392 | + bool is_and = (innercode == TRUTH_AND_EXPR || innercode == BIT_AND_EXPR); | ||
| 393 | + | ||
| 394 | + /* Check for boolean identities that don't require recursive examination | ||
| 395 | + of inner1/inner2: | ||
| 396 | + inner1 AND (inner1 AND inner2) => inner1 AND inner2 => var | ||
| 397 | + inner1 AND (inner1 OR inner2) => inner1 | ||
| 398 | + !inner1 AND (inner1 AND inner2) => false | ||
| 399 | + !inner1 AND (inner1 OR inner2) => !inner1 AND inner2 | ||
| 400 | + Likewise for similar cases involving inner2. */ | ||
| 401 | + if (inner1 == true_test_var) | ||
| 402 | + return (is_and ? var : inner1); | ||
| 403 | + else if (inner2 == true_test_var) | ||
| 404 | + return (is_and ? var : inner2); | ||
| 405 | + else if (inner1 == false_test_var) | ||
| 406 | + return (is_and | ||
| 407 | + ? boolean_false_node | ||
| 408 | + : and_var_with_comparison (inner2, false, code2, op2a, op2b)); | ||
| 409 | + else if (inner2 == false_test_var) | ||
| 410 | + return (is_and | ||
| 411 | + ? boolean_false_node | ||
| 412 | + : and_var_with_comparison (inner1, false, code2, op2a, op2b)); | ||
| 413 | + | ||
| 414 | + /* Next, redistribute/reassociate the AND across the inner tests. | ||
| 415 | + Compute the first partial result, (inner1 AND (op2a code op2b)) */ | ||
| 416 | + if (TREE_CODE (inner1) == SSA_NAME | ||
| 417 | + && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner1)) | ||
| 418 | + && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison | ||
| 419 | + && (t = maybe_fold_and_comparisons (gimple_assign_rhs_code (s), | ||
| 420 | + gimple_assign_rhs1 (s), | ||
| 421 | + gimple_assign_rhs2 (s), | ||
| 422 | + code2, op2a, op2b))) | ||
| 423 | + { | ||
| 424 | + /* Handle the AND case, where we are reassociating: | ||
| 425 | + (inner1 AND inner2) AND (op2a code2 op2b) | ||
| 426 | + => (t AND inner2) | ||
| 427 | + If the partial result t is a constant, we win. Otherwise | ||
| 428 | + continue on to try reassociating with the other inner test. */ | ||
| 429 | + if (is_and) | ||
| 430 | + { | ||
| 431 | + if (integer_onep (t)) | ||
| 432 | + return inner2; | ||
| 433 | + else if (integer_zerop (t)) | ||
| 434 | + return boolean_false_node; | ||
| 435 | + } | ||
| 436 | + | ||
| 437 | + /* Handle the OR case, where we are redistributing: | ||
| 438 | + (inner1 OR inner2) AND (op2a code2 op2b) | ||
| 439 | + => (t OR (inner2 AND (op2a code2 op2b))) */ | ||
| 440 | + else | ||
| 441 | + { | ||
| 442 | + if (integer_onep (t)) | ||
| 443 | + return boolean_true_node; | ||
| 444 | + else | ||
| 445 | + /* Save partial result for later. */ | ||
| 446 | + partial = t; | ||
| 447 | + } | ||
| 448 | + } | ||
| 449 | + | ||
| 450 | + /* Compute the second partial result, (inner2 AND (op2a code op2b)) */ | ||
| 451 | + if (TREE_CODE (inner2) == SSA_NAME | ||
| 452 | + && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner2)) | ||
| 453 | + && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison | ||
| 454 | + && (t = maybe_fold_and_comparisons (gimple_assign_rhs_code (s), | ||
| 455 | + gimple_assign_rhs1 (s), | ||
| 456 | + gimple_assign_rhs2 (s), | ||
| 457 | + code2, op2a, op2b))) | ||
| 458 | + { | ||
| 459 | + /* Handle the AND case, where we are reassociating: | ||
| 460 | + (inner1 AND inner2) AND (op2a code2 op2b) | ||
| 461 | + => (inner1 AND t) */ | ||
| 462 | + if (is_and) | ||
| 463 | + { | ||
| 464 | + if (integer_onep (t)) | ||
| 465 | + return inner1; | ||
| 466 | + else if (integer_zerop (t)) | ||
| 467 | + return boolean_false_node; | ||
| 468 | + } | ||
| 469 | + | ||
| 470 | + /* Handle the OR case. where we are redistributing: | ||
| 471 | + (inner1 OR inner2) AND (op2a code2 op2b) | ||
| 472 | + => (t OR (inner1 AND (op2a code2 op2b))) | ||
| 473 | + => (t OR partial) */ | ||
| 474 | + else | ||
| 475 | + { | ||
| 476 | + if (integer_onep (t)) | ||
| 477 | + return boolean_true_node; | ||
| 478 | + else if (partial) | ||
| 479 | + { | ||
| 480 | + /* We already got a simplification for the other | ||
| 481 | + operand to the redistributed OR expression. The | ||
| 482 | + interesting case is when at least one is false. | ||
| 483 | + Or, if both are the same, we can apply the identity | ||
| 484 | + (x OR x) == x. */ | ||
| 485 | + if (integer_zerop (partial)) | ||
| 486 | + return t; | ||
| 487 | + else if (integer_zerop (t)) | ||
| 488 | + return partial; | ||
| 489 | + else if (same_bool_result_p (t, partial)) | ||
| 490 | + return t; | ||
| 491 | + } | ||
| 492 | + } | ||
| 493 | + } | ||
| 494 | + } | ||
| 495 | + return NULL_TREE; | ||
| 496 | +} | ||
| 497 | + | ||
| 498 | +/* Try to simplify the AND of two comparisons defined by | ||
| 499 | + (OP1A CODE1 OP1B) and (OP2A CODE2 OP2B), respectively. | ||
| 500 | + If this can be done without constructing an intermediate value, | ||
| 501 | + return the resulting tree; otherwise NULL_TREE is returned. | ||
| 502 | + This function is deliberately asymmetric as it recurses on SSA_DEFs | ||
| 503 | + in the first comparison but not the second. */ | ||
| 504 | + | ||
| 505 | +static tree | ||
| 506 | +and_comparisons_1 (enum tree_code code1, tree op1a, tree op1b, | ||
| 507 | + enum tree_code code2, tree op2a, tree op2b) | ||
| 508 | +{ | ||
| 509 | + /* First check for ((x CODE1 y) AND (x CODE2 y)). */ | ||
| 510 | + if (operand_equal_p (op1a, op2a, 0) | ||
| 511 | + && operand_equal_p (op1b, op2b, 0)) | ||
| 512 | + { | ||
| 513 | + tree t = combine_comparisons (UNKNOWN_LOCATION, | ||
| 514 | + TRUTH_ANDIF_EXPR, code1, code2, | ||
| 515 | + boolean_type_node, op1a, op1b); | ||
| 516 | + if (t) | ||
| 517 | + return t; | ||
| 518 | + } | ||
| 519 | + | ||
| 520 | + /* Likewise the swapped case of the above. */ | ||
| 521 | + if (operand_equal_p (op1a, op2b, 0) | ||
| 522 | + && operand_equal_p (op1b, op2a, 0)) | ||
| 523 | + { | ||
| 524 | + tree t = combine_comparisons (UNKNOWN_LOCATION, | ||
| 525 | + TRUTH_ANDIF_EXPR, code1, | ||
| 526 | + swap_tree_comparison (code2), | ||
| 527 | + boolean_type_node, op1a, op1b); | ||
| 528 | + if (t) | ||
| 529 | + return t; | ||
| 530 | + } | ||
| 531 | + | ||
| 532 | + /* If both comparisons are of the same value against constants, we might | ||
| 533 | + be able to merge them. */ | ||
| 534 | + if (operand_equal_p (op1a, op2a, 0) | ||
| 535 | + && TREE_CODE (op1b) == INTEGER_CST | ||
| 536 | + && TREE_CODE (op2b) == INTEGER_CST) | ||
| 537 | + { | ||
| 538 | + int cmp = tree_int_cst_compare (op1b, op2b); | ||
| 539 | + | ||
| 540 | + /* If we have (op1a == op1b), we should either be able to | ||
| 541 | + return that or FALSE, depending on whether the constant op1b | ||
| 542 | + also satisfies the other comparison against op2b. */ | ||
| 543 | + if (code1 == EQ_EXPR) | ||
| 544 | + { | ||
| 545 | + bool done = true; | ||
| 546 | + bool val; | ||
| 547 | + switch (code2) | ||
| 548 | + { | ||
| 549 | + case EQ_EXPR: val = (cmp == 0); break; | ||
| 550 | + case NE_EXPR: val = (cmp != 0); break; | ||
| 551 | + case LT_EXPR: val = (cmp < 0); break; | ||
| 552 | + case GT_EXPR: val = (cmp > 0); break; | ||
| 553 | + case LE_EXPR: val = (cmp <= 0); break; | ||
| 554 | + case GE_EXPR: val = (cmp >= 0); break; | ||
| 555 | + default: done = false; | ||
| 556 | + } | ||
| 557 | + if (done) | ||
| 558 | + { | ||
| 559 | + if (val) | ||
| 560 | + return fold_build2 (code1, boolean_type_node, op1a, op1b); | ||
| 561 | + else | ||
| 562 | + return boolean_false_node; | ||
| 563 | + } | ||
| 564 | + } | ||
| 565 | + /* Likewise if the second comparison is an == comparison. */ | ||
| 566 | + else if (code2 == EQ_EXPR) | ||
| 567 | + { | ||
| 568 | + bool done = true; | ||
| 569 | + bool val; | ||
| 570 | + switch (code1) | ||
| 571 | + { | ||
| 572 | + case EQ_EXPR: val = (cmp == 0); break; | ||
| 573 | + case NE_EXPR: val = (cmp != 0); break; | ||
| 574 | + case LT_EXPR: val = (cmp > 0); break; | ||
| 575 | + case GT_EXPR: val = (cmp < 0); break; | ||
| 576 | + case LE_EXPR: val = (cmp >= 0); break; | ||
| 577 | + case GE_EXPR: val = (cmp <= 0); break; | ||
| 578 | + default: done = false; | ||
| 579 | + } | ||
| 580 | + if (done) | ||
| 581 | + { | ||
| 582 | + if (val) | ||
| 583 | + return fold_build2 (code2, boolean_type_node, op2a, op2b); | ||
| 584 | + else | ||
| 585 | + return boolean_false_node; | ||
| 586 | + } | ||
| 587 | + } | ||
| 588 | + | ||
| 589 | + /* Same business with inequality tests. */ | ||
| 590 | + else if (code1 == NE_EXPR) | ||
| 591 | + { | ||
| 592 | + bool val; | ||
| 593 | + switch (code2) | ||
| 594 | + { | ||
| 595 | + case EQ_EXPR: val = (cmp != 0); break; | ||
| 596 | + case NE_EXPR: val = (cmp == 0); break; | ||
| 597 | + case LT_EXPR: val = (cmp >= 0); break; | ||
| 598 | + case GT_EXPR: val = (cmp <= 0); break; | ||
| 599 | + case LE_EXPR: val = (cmp > 0); break; | ||
| 600 | + case GE_EXPR: val = (cmp < 0); break; | ||
| 601 | + default: | ||
| 602 | + val = false; | ||
| 603 | + } | ||
| 604 | + if (val) | ||
| 605 | + return fold_build2 (code2, boolean_type_node, op2a, op2b); | ||
| 606 | + } | ||
| 607 | + else if (code2 == NE_EXPR) | ||
| 608 | + { | ||
| 609 | + bool val; | ||
| 610 | + switch (code1) | ||
| 611 | + { | ||
| 612 | + case EQ_EXPR: val = (cmp == 0); break; | ||
| 613 | + case NE_EXPR: val = (cmp != 0); break; | ||
| 614 | + case LT_EXPR: val = (cmp <= 0); break; | ||
| 615 | + case GT_EXPR: val = (cmp >= 0); break; | ||
| 616 | + case LE_EXPR: val = (cmp < 0); break; | ||
| 617 | + case GE_EXPR: val = (cmp > 0); break; | ||
| 618 | + default: | ||
| 619 | + val = false; | ||
| 620 | + } | ||
| 621 | + if (val) | ||
| 622 | + return fold_build2 (code1, boolean_type_node, op1a, op1b); | ||
| 623 | + } | ||
| 624 | + | ||
| 625 | + /* Chose the more restrictive of two < or <= comparisons. */ | ||
| 626 | + else if ((code1 == LT_EXPR || code1 == LE_EXPR) | ||
| 627 | + && (code2 == LT_EXPR || code2 == LE_EXPR)) | ||
| 628 | + { | ||
| 629 | + if ((cmp < 0) || (cmp == 0 && code1 == LT_EXPR)) | ||
| 630 | + return fold_build2 (code1, boolean_type_node, op1a, op1b); | ||
| 631 | + else | ||
| 632 | + return fold_build2 (code2, boolean_type_node, op2a, op2b); | ||
| 633 | + } | ||
| 634 | + | ||
| 635 | + /* Likewise chose the more restrictive of two > or >= comparisons. */ | ||
| 636 | + else if ((code1 == GT_EXPR || code1 == GE_EXPR) | ||
| 637 | + && (code2 == GT_EXPR || code2 == GE_EXPR)) | ||
| 638 | + { | ||
| 639 | + if ((cmp > 0) || (cmp == 0 && code1 == GT_EXPR)) | ||
| 640 | + return fold_build2 (code1, boolean_type_node, op1a, op1b); | ||
| 641 | + else | ||
| 642 | + return fold_build2 (code2, boolean_type_node, op2a, op2b); | ||
| 643 | + } | ||
| 644 | + | ||
| 645 | + /* Check for singleton ranges. */ | ||
| 646 | + else if (cmp == 0 | ||
| 647 | + && ((code1 == LE_EXPR && code2 == GE_EXPR) | ||
| 648 | + || (code1 == GE_EXPR && code2 == LE_EXPR))) | ||
| 649 | + return fold_build2 (EQ_EXPR, boolean_type_node, op1a, op2b); | ||
| 650 | + | ||
| 651 | + /* Check for disjoint ranges. */ | ||
| 652 | + else if (cmp <= 0 | ||
| 653 | + && (code1 == LT_EXPR || code1 == LE_EXPR) | ||
| 654 | + && (code2 == GT_EXPR || code2 == GE_EXPR)) | ||
| 655 | + return boolean_false_node; | ||
| 656 | + else if (cmp >= 0 | ||
| 657 | + && (code1 == GT_EXPR || code1 == GE_EXPR) | ||
| 658 | + && (code2 == LT_EXPR || code2 == LE_EXPR)) | ||
| 659 | + return boolean_false_node; | ||
| 660 | + } | ||
| 661 | + | ||
| 662 | + /* Perhaps the first comparison is (NAME != 0) or (NAME == 1) where | ||
| 663 | + NAME's definition is a truth value. See if there are any simplifications | ||
| 664 | + that can be done against the NAME's definition. */ | ||
| 665 | + if (TREE_CODE (op1a) == SSA_NAME | ||
| 666 | + && (code1 == NE_EXPR || code1 == EQ_EXPR) | ||
| 667 | + && (integer_zerop (op1b) || integer_onep (op1b))) | ||
| 668 | + { | ||
| 669 | + bool invert = ((code1 == EQ_EXPR && integer_zerop (op1b)) | ||
| 670 | + || (code1 == NE_EXPR && integer_onep (op1b))); | ||
| 671 | + gimple stmt = SSA_NAME_DEF_STMT (op1a); | ||
| 672 | + switch (gimple_code (stmt)) | ||
| 673 | + { | ||
| 674 | + case GIMPLE_ASSIGN: | ||
| 675 | + /* Try to simplify by copy-propagating the definition. */ | ||
| 676 | + return and_var_with_comparison (op1a, invert, code2, op2a, op2b); | ||
| 677 | + | ||
| 678 | + case GIMPLE_PHI: | ||
| 679 | + /* If every argument to the PHI produces the same result when | ||
| 680 | + ANDed with the second comparison, we win. | ||
| 681 | + Do not do this unless the type is bool since we need a bool | ||
| 682 | + result here anyway. */ | ||
| 683 | + if (TREE_CODE (TREE_TYPE (op1a)) == BOOLEAN_TYPE) | ||
| 684 | + { | ||
| 685 | + tree result = NULL_TREE; | ||
| 686 | + unsigned i; | ||
| 687 | + for (i = 0; i < gimple_phi_num_args (stmt); i++) | ||
| 688 | + { | ||
| 689 | + tree arg = gimple_phi_arg_def (stmt, i); | ||
| 690 | + | ||
| 691 | + /* If this PHI has itself as an argument, ignore it. | ||
| 692 | + If all the other args produce the same result, | ||
| 693 | + we're still OK. */ | ||
| 694 | + if (arg == gimple_phi_result (stmt)) | ||
| 695 | + continue; | ||
| 696 | + else if (TREE_CODE (arg) == INTEGER_CST) | ||
| 697 | + { | ||
| 698 | + if (invert ? integer_nonzerop (arg) : integer_zerop (arg)) | ||
| 699 | + { | ||
| 700 | + if (!result) | ||
| 701 | + result = boolean_false_node; | ||
| 702 | + else if (!integer_zerop (result)) | ||
| 703 | + return NULL_TREE; | ||
| 704 | + } | ||
| 705 | + else if (!result) | ||
| 706 | + result = fold_build2 (code2, boolean_type_node, | ||
| 707 | + op2a, op2b); | ||
| 708 | + else if (!same_bool_comparison_p (result, | ||
| 709 | + code2, op2a, op2b)) | ||
| 710 | + return NULL_TREE; | ||
| 711 | + } | ||
| 712 | + else if (TREE_CODE (arg) == SSA_NAME) | ||
| 713 | + { | ||
| 714 | + tree temp = and_var_with_comparison (arg, invert, | ||
| 715 | + code2, op2a, op2b); | ||
| 716 | + if (!temp) | ||
| 717 | + return NULL_TREE; | ||
| 718 | + else if (!result) | ||
| 719 | + result = temp; | ||
| 720 | + else if (!same_bool_result_p (result, temp)) | ||
| 721 | + return NULL_TREE; | ||
| 722 | + } | ||
| 723 | + else | ||
| 724 | + return NULL_TREE; | ||
| 725 | + } | ||
| 726 | + return result; | ||
| 727 | + } | ||
| 728 | + | ||
| 729 | + default: | ||
| 730 | + break; | ||
| 731 | + } | ||
| 732 | + } | ||
| 733 | + return NULL_TREE; | ||
| 734 | +} | ||
| 735 | + | ||
| 736 | +/* Try to simplify the AND of two comparisons, specified by | ||
| 737 | + (OP1A CODE1 OP1B) and (OP2B CODE2 OP2B), respectively. | ||
| 738 | + If this can be simplified to a single expression (without requiring | ||
| 739 | + introducing more SSA variables to hold intermediate values), | ||
| 740 | + return the resulting tree. Otherwise return NULL_TREE. | ||
| 741 | + If the result expression is non-null, it has boolean type. */ | ||
| 742 | + | ||
| 743 | +tree | ||
| 744 | +maybe_fold_and_comparisons (enum tree_code code1, tree op1a, tree op1b, | ||
| 745 | + enum tree_code code2, tree op2a, tree op2b) | ||
| 746 | +{ | ||
| 747 | + tree t = and_comparisons_1 (code1, op1a, op1b, code2, op2a, op2b); | ||
| 748 | + if (t) | ||
| 749 | + return t; | ||
| 750 | + else | ||
| 751 | + return and_comparisons_1 (code2, op2a, op2b, code1, op1a, op1b); | ||
| 752 | +} | ||
| 753 | + | ||
| 754 | +/* Helper function for or_comparisons_1: try to simplify the OR of the | ||
| 755 | + ssa variable VAR with the comparison specified by (OP2A CODE2 OP2B). | ||
| 756 | + If INVERT is true, invert the value of VAR before doing the OR. | ||
| 757 | + Return NULL_EXPR if we can't simplify this to a single expression. */ | ||
| 758 | + | ||
| 759 | +static tree | ||
| 760 | +or_var_with_comparison (tree var, bool invert, | ||
| 761 | + enum tree_code code2, tree op2a, tree op2b) | ||
| 762 | +{ | ||
| 763 | + tree t; | ||
| 764 | + gimple stmt = SSA_NAME_DEF_STMT (var); | ||
| 765 | + | ||
| 766 | + /* We can only deal with variables whose definitions are assignments. */ | ||
| 767 | + if (!is_gimple_assign (stmt)) | ||
| 768 | + return NULL_TREE; | ||
| 769 | + | ||
| 770 | + /* If we have an inverted comparison, apply DeMorgan's law and rewrite | ||
| 771 | + !var OR (op2a code2 op2b) => !(var AND !(op2a code2 op2b)) | ||
| 772 | + Then we only have to consider the simpler non-inverted cases. */ | ||
| 773 | + if (invert) | ||
| 774 | + t = and_var_with_comparison_1 (stmt, | ||
| 775 | + invert_tree_comparison (code2, false), | ||
| 776 | + op2a, op2b); | ||
| 777 | + else | ||
| 778 | + t = or_var_with_comparison_1 (stmt, code2, op2a, op2b); | ||
| 779 | + return canonicalize_bool (t, invert); | ||
| 780 | +} | ||
| 781 | + | ||
| 782 | +/* Try to simplify the OR of the ssa variable defined by the assignment | ||
| 783 | + STMT with the comparison specified by (OP2A CODE2 OP2B). | ||
| 784 | + Return NULL_EXPR if we can't simplify this to a single expression. */ | ||
| 785 | + | ||
| 786 | +static tree | ||
| 787 | +or_var_with_comparison_1 (gimple stmt, | ||
| 788 | + enum tree_code code2, tree op2a, tree op2b) | ||
| 789 | +{ | ||
| 790 | + tree var = gimple_assign_lhs (stmt); | ||
| 791 | + tree true_test_var = NULL_TREE; | ||
| 792 | + tree false_test_var = NULL_TREE; | ||
| 793 | + enum tree_code innercode = gimple_assign_rhs_code (stmt); | ||
| 794 | + | ||
| 795 | + /* Check for identities like (var OR (var != 0)) => true . */ | ||
| 796 | + if (TREE_CODE (op2a) == SSA_NAME | ||
| 797 | + && TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE) | ||
| 798 | + { | ||
| 799 | + if ((code2 == NE_EXPR && integer_zerop (op2b)) | ||
| 800 | + || (code2 == EQ_EXPR && integer_nonzerop (op2b))) | ||
| 801 | + { | ||
| 802 | + true_test_var = op2a; | ||
| 803 | + if (var == true_test_var) | ||
| 804 | + return var; | ||
| 805 | + } | ||
| 806 | + else if ((code2 == EQ_EXPR && integer_zerop (op2b)) | ||
| 807 | + || (code2 == NE_EXPR && integer_nonzerop (op2b))) | ||
| 808 | + { | ||
| 809 | + false_test_var = op2a; | ||
| 810 | + if (var == false_test_var) | ||
| 811 | + return boolean_true_node; | ||
| 812 | + } | ||
| 813 | + } | ||
| 814 | + | ||
| 815 | + /* If the definition is a comparison, recurse on it. */ | ||
| 816 | + if (TREE_CODE_CLASS (innercode) == tcc_comparison) | ||
| 817 | + { | ||
| 818 | + tree t = or_comparisons_1 (innercode, | ||
| 819 | + gimple_assign_rhs1 (stmt), | ||
| 820 | + gimple_assign_rhs2 (stmt), | ||
| 821 | + code2, | ||
| 822 | + op2a, | ||
| 823 | + op2b); | ||
| 824 | + if (t) | ||
| 825 | + return t; | ||
| 826 | + } | ||
| 827 | + | ||
| 828 | + /* If the definition is an AND or OR expression, we may be able to | ||
| 829 | + simplify by reassociating. */ | ||
| 830 | + if (innercode == TRUTH_AND_EXPR | ||
| 831 | + || innercode == TRUTH_OR_EXPR | ||
| 832 | + || (TREE_CODE (TREE_TYPE (var)) == BOOLEAN_TYPE | ||
| 833 | + && (innercode == BIT_AND_EXPR || innercode == BIT_IOR_EXPR))) | ||
| 834 | + { | ||
| 835 | + tree inner1 = gimple_assign_rhs1 (stmt); | ||
| 836 | + tree inner2 = gimple_assign_rhs2 (stmt); | ||
| 837 | + gimple s; | ||
| 838 | + tree t; | ||
| 839 | + tree partial = NULL_TREE; | ||
| 840 | + bool is_or = (innercode == TRUTH_OR_EXPR || innercode == BIT_IOR_EXPR); | ||
| 841 | + | ||
| 842 | + /* Check for boolean identities that don't require recursive examination | ||
| 843 | + of inner1/inner2: | ||
| 844 | + inner1 OR (inner1 OR inner2) => inner1 OR inner2 => var | ||
| 845 | + inner1 OR (inner1 AND inner2) => inner1 | ||
| 846 | + !inner1 OR (inner1 OR inner2) => true | ||
| 847 | + !inner1 OR (inner1 AND inner2) => !inner1 OR inner2 | ||
| 848 | + */ | ||
| 849 | + if (inner1 == true_test_var) | ||
| 850 | + return (is_or ? var : inner1); | ||
| 851 | + else if (inner2 == true_test_var) | ||
| 852 | + return (is_or ? var : inner2); | ||
| 853 | + else if (inner1 == false_test_var) | ||
| 854 | + return (is_or | ||
| 855 | + ? boolean_true_node | ||
| 856 | + : or_var_with_comparison (inner2, false, code2, op2a, op2b)); | ||
| 857 | + else if (inner2 == false_test_var) | ||
| 858 | + return (is_or | ||
| 859 | + ? boolean_true_node | ||
| 860 | + : or_var_with_comparison (inner1, false, code2, op2a, op2b)); | ||
| 861 | + | ||
| 862 | + /* Next, redistribute/reassociate the OR across the inner tests. | ||
| 863 | + Compute the first partial result, (inner1 OR (op2a code op2b)) */ | ||
| 864 | + if (TREE_CODE (inner1) == SSA_NAME | ||
| 865 | + && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner1)) | ||
| 866 | + && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison | ||
| 867 | + && (t = maybe_fold_or_comparisons (gimple_assign_rhs_code (s), | ||
| 868 | + gimple_assign_rhs1 (s), | ||
| 869 | + gimple_assign_rhs2 (s), | ||
| 870 | + code2, op2a, op2b))) | ||
| 871 | + { | ||
| 872 | + /* Handle the OR case, where we are reassociating: | ||
| 873 | + (inner1 OR inner2) OR (op2a code2 op2b) | ||
| 874 | + => (t OR inner2) | ||
| 875 | + If the partial result t is a constant, we win. Otherwise | ||
| 876 | + continue on to try reassociating with the other inner test. */ | ||
| 877 | + if (innercode == TRUTH_OR_EXPR) | ||
| 878 | + { | ||
| 879 | + if (integer_onep (t)) | ||
| 880 | + return boolean_true_node; | ||
| 881 | + else if (integer_zerop (t)) | ||
| 882 | + return inner2; | ||
| 883 | + } | ||
| 884 | + | ||
| 885 | + /* Handle the AND case, where we are redistributing: | ||
| 886 | + (inner1 AND inner2) OR (op2a code2 op2b) | ||
| 887 | + => (t AND (inner2 OR (op2a code op2b))) */ | ||
| 888 | + else | ||
| 889 | + { | ||
| 890 | + if (integer_zerop (t)) | ||
| 891 | + return boolean_false_node; | ||
| 892 | + else | ||
| 893 | + /* Save partial result for later. */ | ||
| 894 | + partial = t; | ||
| 895 | + } | ||
| 896 | + } | ||
| 897 | + | ||
| 898 | + /* Compute the second partial result, (inner2 OR (op2a code op2b)) */ | ||
| 899 | + if (TREE_CODE (inner2) == SSA_NAME | ||
| 900 | + && is_gimple_assign (s = SSA_NAME_DEF_STMT (inner2)) | ||
| 901 | + && TREE_CODE_CLASS (gimple_assign_rhs_code (s)) == tcc_comparison | ||
| 902 | + && (t = maybe_fold_or_comparisons (gimple_assign_rhs_code (s), | ||
| 903 | + gimple_assign_rhs1 (s), | ||
| 904 | + gimple_assign_rhs2 (s), | ||
| 905 | + code2, op2a, op2b))) | ||
| 906 | + { | ||
| 907 | + /* Handle the OR case, where we are reassociating: | ||
| 908 | + (inner1 OR inner2) OR (op2a code2 op2b) | ||
| 909 | + => (inner1 OR t) */ | ||
| 910 | + if (innercode == TRUTH_OR_EXPR) | ||
| 911 | + { | ||
| 912 | + if (integer_zerop (t)) | ||
| 913 | + return inner1; | ||
| 914 | + else if (integer_onep (t)) | ||
| 915 | + return boolean_true_node; | ||
| 916 | + } | ||
| 917 | + | ||
| 918 | + /* Handle the AND case, where we are redistributing: | ||
| 919 | + (inner1 AND inner2) OR (op2a code2 op2b) | ||
| 920 | + => (t AND (inner1 OR (op2a code2 op2b))) | ||
| 921 | + => (t AND partial) */ | ||
| 922 | + else | ||
| 923 | + { | ||
| 924 | + if (integer_zerop (t)) | ||
| 925 | + return boolean_false_node; | ||
| 926 | + else if (partial) | ||
| 927 | + { | ||
| 928 | + /* We already got a simplification for the other | ||
| 929 | + operand to the redistributed AND expression. The | ||
| 930 | + interesting case is when at least one is true. | ||
| 931 | + Or, if both are the same, we can apply the identity | ||
| 932 | + (x AND x) == true. */ | ||
| 933 | + if (integer_onep (partial)) | ||
| 934 | + return t; | ||
| 935 | + else if (integer_onep (t)) | ||
| 936 | + return partial; | ||
| 937 | + else if (same_bool_result_p (t, partial)) | ||
| 938 | + return boolean_true_node; | ||
| 939 | + } | ||
| 940 | + } | ||
| 941 | + } | ||
| 942 | + } | ||
| 943 | + return NULL_TREE; | ||
| 944 | +} | ||
| 945 | + | ||
| 946 | +/* Try to simplify the OR of two comparisons defined by | ||
| 947 | + (OP1A CODE1 OP1B) and (OP2A CODE2 OP2B), respectively. | ||
| 948 | + If this can be done without constructing an intermediate value, | ||
| 949 | + return the resulting tree; otherwise NULL_TREE is returned. | ||
| 950 | + This function is deliberately asymmetric as it recurses on SSA_DEFs | ||
| 951 | + in the first comparison but not the second. */ | ||
| 952 | + | ||
| 953 | +static tree | ||
| 954 | +or_comparisons_1 (enum tree_code code1, tree op1a, tree op1b, | ||
| 955 | + enum tree_code code2, tree op2a, tree op2b) | ||
| 956 | +{ | ||
| 957 | + /* First check for ((x CODE1 y) OR (x CODE2 y)). */ | ||
| 958 | + if (operand_equal_p (op1a, op2a, 0) | ||
| 959 | + && operand_equal_p (op1b, op2b, 0)) | ||
| 960 | + { | ||
| 961 | + tree t = combine_comparisons (UNKNOWN_LOCATION, | ||
| 962 | + TRUTH_ORIF_EXPR, code1, code2, | ||
| 963 | + boolean_type_node, op1a, op1b); | ||
| 964 | + if (t) | ||
| 965 | + return t; | ||
| 966 | + } | ||
| 967 | + | ||
| 968 | + /* Likewise the swapped case of the above. */ | ||
| 969 | + if (operand_equal_p (op1a, op2b, 0) | ||
| 970 | + && operand_equal_p (op1b, op2a, 0)) | ||
| 971 | + { | ||
| 972 | + tree t = combine_comparisons (UNKNOWN_LOCATION, | ||
| 973 | + TRUTH_ORIF_EXPR, code1, | ||
| 974 | + swap_tree_comparison (code2), | ||
| 975 | + boolean_type_node, op1a, op1b); | ||
| 976 | + if (t) | ||
| 977 | + return t; | ||
| 978 | + } | ||
| 979 | + | ||
| 980 | + /* If both comparisons are of the same value against constants, we might | ||
| 981 | + be able to merge them. */ | ||
| 982 | + if (operand_equal_p (op1a, op2a, 0) | ||
| 983 | + && TREE_CODE (op1b) == INTEGER_CST | ||
| 984 | + && TREE_CODE (op2b) == INTEGER_CST) | ||
| 985 | + { | ||
| 986 | + int cmp = tree_int_cst_compare (op1b, op2b); | ||
| 987 | + | ||
| 988 | + /* If we have (op1a != op1b), we should either be able to | ||
| 989 | + return that or TRUE, depending on whether the constant op1b | ||
| 990 | + also satisfies the other comparison against op2b. */ | ||
| 991 | + if (code1 == NE_EXPR) | ||
| 992 | + { | ||
| 993 | + bool done = true; | ||
| 994 | + bool val; | ||
| 995 | + switch (code2) | ||
| 996 | + { | ||
| 997 | + case EQ_EXPR: val = (cmp == 0); break; | ||
| 998 | + case NE_EXPR: val = (cmp != 0); break; | ||
| 999 | + case LT_EXPR: val = (cmp < 0); break; | ||
| 1000 | + case GT_EXPR: val = (cmp > 0); break; | ||
| 1001 | + case LE_EXPR: val = (cmp <= 0); break; | ||
| 1002 | + case GE_EXPR: val = (cmp >= 0); break; | ||
| 1003 | + default: done = false; | ||
| 1004 | + } | ||
| 1005 | + if (done) | ||
| 1006 | + { | ||
| 1007 | + if (val) | ||
| 1008 | + return boolean_true_node; | ||
| 1009 | + else | ||
| 1010 | + return fold_build2 (code1, boolean_type_node, op1a, op1b); | ||
| 1011 | + } | ||
| 1012 | + } | ||
| 1013 | + /* Likewise if the second comparison is a != comparison. */ | ||
| 1014 | + else if (code2 == NE_EXPR) | ||
| 1015 | + { | ||
| 1016 | + bool done = true; | ||
| 1017 | + bool val; | ||
| 1018 | + switch (code1) | ||
| 1019 | + { | ||
| 1020 | + case EQ_EXPR: val = (cmp == 0); break; | ||
| 1021 | + case NE_EXPR: val = (cmp != 0); break; | ||
| 1022 | + case LT_EXPR: val = (cmp > 0); break; | ||
| 1023 | + case GT_EXPR: val = (cmp < 0); break; | ||
| 1024 | + case LE_EXPR: val = (cmp >= 0); break; | ||
| 1025 | + case GE_EXPR: val = (cmp <= 0); break; | ||
| 1026 | + default: done = false; | ||
| 1027 | + } | ||
| 1028 | + if (done) | ||
| 1029 | + { | ||
| 1030 | + if (val) | ||
| 1031 | + return boolean_true_node; | ||
| 1032 | + else | ||
| 1033 | + return fold_build2 (code2, boolean_type_node, op2a, op2b); | ||
| 1034 | + } | ||
| 1035 | + } | ||
| 1036 | + | ||
| 1037 | + /* See if an equality test is redundant with the other comparison. */ | ||
| 1038 | + else if (code1 == EQ_EXPR) | ||
| 1039 | + { | ||
| 1040 | + bool val; | ||
| 1041 | + switch (code2) | ||
| 1042 | + { | ||
| 1043 | + case EQ_EXPR: val = (cmp == 0); break; | ||
| 1044 | + case NE_EXPR: val = (cmp != 0); break; | ||
| 1045 | + case LT_EXPR: val = (cmp < 0); break; | ||
| 1046 | + case GT_EXPR: val = (cmp > 0); break; | ||
| 1047 | + case LE_EXPR: val = (cmp <= 0); break; | ||
| 1048 | + case GE_EXPR: val = (cmp >= 0); break; | ||
| 1049 | + default: | ||
| 1050 | + val = false; | ||
| 1051 | + } | ||
| 1052 | + if (val) | ||
| 1053 | + return fold_build2 (code2, boolean_type_node, op2a, op2b); | ||
| 1054 | + } | ||
| 1055 | + else if (code2 == EQ_EXPR) | ||
| 1056 | + { | ||
| 1057 | + bool val; | ||
| 1058 | + switch (code1) | ||
| 1059 | + { | ||
| 1060 | + case EQ_EXPR: val = (cmp == 0); break; | ||
| 1061 | + case NE_EXPR: val = (cmp != 0); break; | ||
| 1062 | + case LT_EXPR: val = (cmp > 0); break; | ||
| 1063 | + case GT_EXPR: val = (cmp < 0); break; | ||
| 1064 | + case LE_EXPR: val = (cmp >= 0); break; | ||
| 1065 | + case GE_EXPR: val = (cmp <= 0); break; | ||
| 1066 | + default: | ||
| 1067 | + val = false; | ||
| 1068 | + } | ||
| 1069 | + if (val) | ||
| 1070 | + return fold_build2 (code1, boolean_type_node, op1a, op1b); | ||
| 1071 | + } | ||
| 1072 | + | ||
| 1073 | + /* Chose the less restrictive of two < or <= comparisons. */ | ||
| 1074 | + else if ((code1 == LT_EXPR || code1 == LE_EXPR) | ||
| 1075 | + && (code2 == LT_EXPR || code2 == LE_EXPR)) | ||
| 1076 | + { | ||
| 1077 | + if ((cmp < 0) || (cmp == 0 && code1 == LT_EXPR)) | ||
| 1078 | + return fold_build2 (code2, boolean_type_node, op2a, op2b); | ||
| 1079 | + else | ||
| 1080 | + return fold_build2 (code1, boolean_type_node, op1a, op1b); | ||
| 1081 | + } | ||
| 1082 | + | ||
| 1083 | + /* Likewise chose the less restrictive of two > or >= comparisons. */ | ||
| 1084 | + else if ((code1 == GT_EXPR || code1 == GE_EXPR) | ||
| 1085 | + && (code2 == GT_EXPR || code2 == GE_EXPR)) | ||
| 1086 | + { | ||
| 1087 | + if ((cmp > 0) || (cmp == 0 && code1 == GT_EXPR)) | ||
| 1088 | + return fold_build2 (code2, boolean_type_node, op2a, op2b); | ||
| 1089 | + else | ||
| 1090 | + return fold_build2 (code1, boolean_type_node, op1a, op1b); | ||
| 1091 | + } | ||
| 1092 | + | ||
| 1093 | + /* Check for singleton ranges. */ | ||
| 1094 | + else if (cmp == 0 | ||
| 1095 | + && ((code1 == LT_EXPR && code2 == GT_EXPR) | ||
| 1096 | + || (code1 == GT_EXPR && code2 == LT_EXPR))) | ||
| 1097 | + return fold_build2 (NE_EXPR, boolean_type_node, op1a, op2b); | ||
| 1098 | + | ||
| 1099 | + /* Check for less/greater pairs that don't restrict the range at all. */ | ||
| 1100 | + else if (cmp >= 0 | ||
| 1101 | + && (code1 == LT_EXPR || code1 == LE_EXPR) | ||
| 1102 | + && (code2 == GT_EXPR || code2 == GE_EXPR)) | ||
| 1103 | + return boolean_true_node; | ||
| 1104 | + else if (cmp <= 0 | ||
| 1105 | + && (code1 == GT_EXPR || code1 == GE_EXPR) | ||
| 1106 | + && (code2 == LT_EXPR || code2 == LE_EXPR)) | ||
| 1107 | + return boolean_true_node; | ||
| 1108 | + } | ||
| 1109 | + | ||
| 1110 | + /* Perhaps the first comparison is (NAME != 0) or (NAME == 1) where | ||
| 1111 | + NAME's definition is a truth value. See if there are any simplifications | ||
| 1112 | + that can be done against the NAME's definition. */ | ||
| 1113 | + if (TREE_CODE (op1a) == SSA_NAME | ||
| 1114 | + && (code1 == NE_EXPR || code1 == EQ_EXPR) | ||
| 1115 | + && (integer_zerop (op1b) || integer_onep (op1b))) | ||
| 1116 | + { | ||
| 1117 | + bool invert = ((code1 == EQ_EXPR && integer_zerop (op1b)) | ||
| 1118 | + || (code1 == NE_EXPR && integer_onep (op1b))); | ||
| 1119 | + gimple stmt = SSA_NAME_DEF_STMT (op1a); | ||
| 1120 | + switch (gimple_code (stmt)) | ||
| 1121 | + { | ||
| 1122 | + case GIMPLE_ASSIGN: | ||
| 1123 | + /* Try to simplify by copy-propagating the definition. */ | ||
| 1124 | + return or_var_with_comparison (op1a, invert, code2, op2a, op2b); | ||
| 1125 | + | ||
| 1126 | + case GIMPLE_PHI: | ||
| 1127 | + /* If every argument to the PHI produces the same result when | ||
| 1128 | + ORed with the second comparison, we win. | ||
| 1129 | + Do not do this unless the type is bool since we need a bool | ||
| 1130 | + result here anyway. */ | ||
| 1131 | + if (TREE_CODE (TREE_TYPE (op1a)) == BOOLEAN_TYPE) | ||
| 1132 | + { | ||
| 1133 | + tree result = NULL_TREE; | ||
| 1134 | + unsigned i; | ||
| 1135 | + for (i = 0; i < gimple_phi_num_args (stmt); i++) | ||
| 1136 | + { | ||
| 1137 | + tree arg = gimple_phi_arg_def (stmt, i); | ||
| 1138 | + | ||
| 1139 | + /* If this PHI has itself as an argument, ignore it. | ||
| 1140 | + If all the other args produce the same result, | ||
| 1141 | + we're still OK. */ | ||
| 1142 | + if (arg == gimple_phi_result (stmt)) | ||
| 1143 | + continue; | ||
| 1144 | + else if (TREE_CODE (arg) == INTEGER_CST) | ||
| 1145 | + { | ||
| 1146 | + if (invert ? integer_zerop (arg) : integer_nonzerop (arg)) | ||
| 1147 | + { | ||
| 1148 | + if (!result) | ||
| 1149 | + result = boolean_true_node; | ||
| 1150 | + else if (!integer_onep (result)) | ||
| 1151 | + return NULL_TREE; | ||
| 1152 | + } | ||
| 1153 | + else if (!result) | ||
| 1154 | + result = fold_build2 (code2, boolean_type_node, | ||
| 1155 | + op2a, op2b); | ||
| 1156 | + else if (!same_bool_comparison_p (result, | ||
| 1157 | + code2, op2a, op2b)) | ||
| 1158 | + return NULL_TREE; | ||
| 1159 | + } | ||
| 1160 | + else if (TREE_CODE (arg) == SSA_NAME) | ||
| 1161 | + { | ||
| 1162 | + tree temp = or_var_with_comparison (arg, invert, | ||
| 1163 | + code2, op2a, op2b); | ||
| 1164 | + if (!temp) | ||
| 1165 | + return NULL_TREE; | ||
| 1166 | + else if (!result) | ||
| 1167 | + result = temp; | ||
| 1168 | + else if (!same_bool_result_p (result, temp)) | ||
| 1169 | + return NULL_TREE; | ||
| 1170 | + } | ||
| 1171 | + else | ||
| 1172 | + return NULL_TREE; | ||
| 1173 | + } | ||
| 1174 | + return result; | ||
| 1175 | + } | ||
| 1176 | + | ||
| 1177 | + default: | ||
| 1178 | + break; | ||
| 1179 | + } | ||
| 1180 | + } | ||
| 1181 | + return NULL_TREE; | ||
| 1182 | +} | ||
| 1183 | + | ||
| 1184 | +/* Try to simplify the OR of two comparisons, specified by | ||
| 1185 | + (OP1A CODE1 OP1B) and (OP2B CODE2 OP2B), respectively. | ||
| 1186 | + If this can be simplified to a single expression (without requiring | ||
| 1187 | + introducing more SSA variables to hold intermediate values), | ||
| 1188 | + return the resulting tree. Otherwise return NULL_TREE. | ||
| 1189 | + If the result expression is non-null, it has boolean type. */ | ||
| 1190 | + | ||
| 1191 | +tree | ||
| 1192 | +maybe_fold_or_comparisons (enum tree_code code1, tree op1a, tree op1b, | ||
| 1193 | + enum tree_code code2, tree op2a, tree op2b) | ||
| 1194 | +{ | ||
| 1195 | + tree t = or_comparisons_1 (code1, op1a, op1b, code2, op2a, op2b); | ||
| 1196 | + if (t) | ||
| 1197 | + return t; | ||
| 1198 | + else | ||
| 1199 | + return or_comparisons_1 (code2, op2a, op2b, code1, op1a, op1b); | ||
| 1200 | +} | ||
| 1201 | + | ||
| 1202 | /* Try to optimize out __builtin_stack_restore. Optimize it out | ||
| 1203 | if there is another __builtin_stack_restore in the same basic | ||
| 1204 | block and no calls or ASM_EXPRs are in between, or if this block's | ||
| 1205 | |||
| 1206 | === modified file 'gcc/tree-ssa-ifcombine.c' | ||
| 1207 | --- old/gcc/tree-ssa-ifcombine.c 2009-11-25 10:55:54 +0000 | ||
| 1208 | +++ new/gcc/tree-ssa-ifcombine.c 2010-07-30 13:21:51 +0000 | ||
| 1209 | @@ -366,21 +366,16 @@ | ||
| 1210 | |||
| 1211 | /* See if we have two comparisons that we can merge into one. */ | ||
| 1212 | else if (TREE_CODE_CLASS (gimple_cond_code (inner_cond)) == tcc_comparison | ||
| 1213 | - && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison | ||
| 1214 | - && operand_equal_p (gimple_cond_lhs (inner_cond), | ||
| 1215 | - gimple_cond_lhs (outer_cond), 0) | ||
| 1216 | - && operand_equal_p (gimple_cond_rhs (inner_cond), | ||
| 1217 | - gimple_cond_rhs (outer_cond), 0)) | ||
| 1218 | + && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison) | ||
| 1219 | { | ||
| 1220 | - enum tree_code code1 = gimple_cond_code (inner_cond); | ||
| 1221 | - enum tree_code code2 = gimple_cond_code (outer_cond); | ||
| 1222 | tree t; | ||
| 1223 | |||
| 1224 | - if (!(t = combine_comparisons (UNKNOWN_LOCATION, | ||
| 1225 | - TRUTH_ANDIF_EXPR, code1, code2, | ||
| 1226 | - boolean_type_node, | ||
| 1227 | - gimple_cond_lhs (outer_cond), | ||
| 1228 | - gimple_cond_rhs (outer_cond)))) | ||
| 1229 | + if (!(t = maybe_fold_and_comparisons (gimple_cond_code (inner_cond), | ||
| 1230 | + gimple_cond_lhs (inner_cond), | ||
| 1231 | + gimple_cond_rhs (inner_cond), | ||
| 1232 | + gimple_cond_code (outer_cond), | ||
| 1233 | + gimple_cond_lhs (outer_cond), | ||
| 1234 | + gimple_cond_rhs (outer_cond)))) | ||
| 1235 | return false; | ||
| 1236 | t = canonicalize_cond_expr_cond (t); | ||
| 1237 | if (!t) | ||
| 1238 | @@ -518,22 +513,17 @@ | ||
| 1239 | /* See if we have two comparisons that we can merge into one. | ||
| 1240 | This happens for C++ operator overloading where for example | ||
| 1241 | GE_EXPR is implemented as GT_EXPR || EQ_EXPR. */ | ||
| 1242 | - else if (TREE_CODE_CLASS (gimple_cond_code (inner_cond)) == tcc_comparison | ||
| 1243 | - && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison | ||
| 1244 | - && operand_equal_p (gimple_cond_lhs (inner_cond), | ||
| 1245 | - gimple_cond_lhs (outer_cond), 0) | ||
| 1246 | - && operand_equal_p (gimple_cond_rhs (inner_cond), | ||
| 1247 | - gimple_cond_rhs (outer_cond), 0)) | ||
| 1248 | + else if (TREE_CODE_CLASS (gimple_cond_code (inner_cond)) == tcc_comparison | ||
| 1249 | + && TREE_CODE_CLASS (gimple_cond_code (outer_cond)) == tcc_comparison) | ||
| 1250 | { | ||
| 1251 | - enum tree_code code1 = gimple_cond_code (inner_cond); | ||
| 1252 | - enum tree_code code2 = gimple_cond_code (outer_cond); | ||
| 1253 | tree t; | ||
| 1254 | |||
| 1255 | - if (!(t = combine_comparisons (UNKNOWN_LOCATION, | ||
| 1256 | - TRUTH_ORIF_EXPR, code1, code2, | ||
| 1257 | - boolean_type_node, | ||
| 1258 | - gimple_cond_lhs (outer_cond), | ||
| 1259 | - gimple_cond_rhs (outer_cond)))) | ||
| 1260 | + if (!(t = maybe_fold_or_comparisons (gimple_cond_code (inner_cond), | ||
| 1261 | + gimple_cond_lhs (inner_cond), | ||
| 1262 | + gimple_cond_rhs (inner_cond), | ||
| 1263 | + gimple_cond_code (outer_cond), | ||
| 1264 | + gimple_cond_lhs (outer_cond), | ||
| 1265 | + gimple_cond_rhs (outer_cond)))) | ||
| 1266 | return false; | ||
| 1267 | t = canonicalize_cond_expr_cond (t); | ||
| 1268 | if (!t) | ||
| 1269 | |||
| 1270 | === modified file 'gcc/tree-ssa-reassoc.c' | ||
| 1271 | --- old/gcc/tree-ssa-reassoc.c 2010-01-13 15:04:38 +0000 | ||
| 1272 | +++ new/gcc/tree-ssa-reassoc.c 2010-07-30 13:21:51 +0000 | ||
| 1273 | @@ -1159,6 +1159,117 @@ | ||
| 1274 | return changed; | ||
| 1275 | } | ||
| 1276 | |||
| 1277 | +/* If OPCODE is BIT_IOR_EXPR or BIT_AND_EXPR and CURR is a comparison | ||
| 1278 | + expression, examine the other OPS to see if any of them are comparisons | ||
| 1279 | + of the same values, which we may be able to combine or eliminate. | ||
| 1280 | + For example, we can rewrite (a < b) | (a == b) as (a <= b). */ | ||
| 1281 | + | ||
| 1282 | +static bool | ||
| 1283 | +eliminate_redundant_comparison (enum tree_code opcode, | ||
| 1284 | + VEC (operand_entry_t, heap) **ops, | ||
| 1285 | + unsigned int currindex, | ||
| 1286 | + operand_entry_t curr) | ||
| 1287 | +{ | ||
| 1288 | + tree op1, op2; | ||
| 1289 | + enum tree_code lcode, rcode; | ||
| 1290 | + gimple def1, def2; | ||
| 1291 | + int i; | ||
| 1292 | + operand_entry_t oe; | ||
| 1293 | + | ||
| 1294 | + if (opcode != BIT_IOR_EXPR && opcode != BIT_AND_EXPR) | ||
| 1295 | + return false; | ||
| 1296 | + | ||
| 1297 | + /* Check that CURR is a comparison. */ | ||
| 1298 | + if (TREE_CODE (curr->op) != SSA_NAME) | ||
| 1299 | + return false; | ||
| 1300 | + def1 = SSA_NAME_DEF_STMT (curr->op); | ||
| 1301 | + if (!is_gimple_assign (def1)) | ||
| 1302 | + return false; | ||
| 1303 | + lcode = gimple_assign_rhs_code (def1); | ||
| 1304 | + if (TREE_CODE_CLASS (lcode) != tcc_comparison) | ||
| 1305 | + return false; | ||
| 1306 | + op1 = gimple_assign_rhs1 (def1); | ||
| 1307 | + op2 = gimple_assign_rhs2 (def1); | ||
| 1308 | + | ||
| 1309 | + /* Now look for a similar comparison in the remaining OPS. */ | ||
| 1310 | + for (i = currindex + 1; | ||
| 1311 | + VEC_iterate (operand_entry_t, *ops, i, oe); | ||
| 1312 | + i++) | ||
| 1313 | + { | ||
| 1314 | + tree t; | ||
| 1315 | + | ||
| 1316 | + if (TREE_CODE (oe->op) != SSA_NAME) | ||
| 1317 | + continue; | ||
| 1318 | + def2 = SSA_NAME_DEF_STMT (oe->op); | ||
| 1319 | + if (!is_gimple_assign (def2)) | ||
| 1320 | + continue; | ||
| 1321 | + rcode = gimple_assign_rhs_code (def2); | ||
| 1322 | + if (TREE_CODE_CLASS (rcode) != tcc_comparison) | ||
| 1323 | + continue; | ||
| 1324 | + | ||
| 1325 | + /* If we got here, we have a match. See if we can combine the | ||
| 1326 | + two comparisons. */ | ||
| 1327 | + if (opcode == BIT_IOR_EXPR) | ||
| 1328 | + t = maybe_fold_or_comparisons (lcode, op1, op2, | ||
| 1329 | + rcode, gimple_assign_rhs1 (def2), | ||
| 1330 | + gimple_assign_rhs2 (def2)); | ||
| 1331 | + else | ||
| 1332 | + t = maybe_fold_and_comparisons (lcode, op1, op2, | ||
| 1333 | + rcode, gimple_assign_rhs1 (def2), | ||
| 1334 | + gimple_assign_rhs2 (def2)); | ||
| 1335 | + if (!t) | ||
| 1336 | + continue; | ||
| 1337 | + | ||
| 1338 | + /* maybe_fold_and_comparisons and maybe_fold_or_comparisons | ||
| 1339 | + always give us a boolean_type_node value back. If the original | ||
| 1340 | + BIT_AND_EXPR or BIT_IOR_EXPR was of a wider integer type, | ||
| 1341 | + we need to convert. */ | ||
| 1342 | + if (!useless_type_conversion_p (TREE_TYPE (curr->op), TREE_TYPE (t))) | ||
| 1343 | + t = fold_convert (TREE_TYPE (curr->op), t); | ||
| 1344 | + | ||
| 1345 | + if (dump_file && (dump_flags & TDF_DETAILS)) | ||
| 1346 | + { | ||
| 1347 | + fprintf (dump_file, "Equivalence: "); | ||
| 1348 | + print_generic_expr (dump_file, curr->op, 0); | ||
| 1349 | + fprintf (dump_file, " %s ", op_symbol_code (opcode)); | ||
| 1350 | + print_generic_expr (dump_file, oe->op, 0); | ||
| 1351 | + fprintf (dump_file, " -> "); | ||
| 1352 | + print_generic_expr (dump_file, t, 0); | ||
| 1353 | + fprintf (dump_file, "\n"); | ||
| 1354 | + } | ||
| 1355 | + | ||
| 1356 | + /* Now we can delete oe, as it has been subsumed by the new combined | ||
| 1357 | + expression t. */ | ||
| 1358 | + VEC_ordered_remove (operand_entry_t, *ops, i); | ||
| 1359 | + reassociate_stats.ops_eliminated ++; | ||
| 1360 | + | ||
| 1361 | + /* If t is the same as curr->op, we're done. Otherwise we must | ||
| 1362 | + replace curr->op with t. Special case is if we got a constant | ||
| 1363 | + back, in which case we add it to the end instead of in place of | ||
| 1364 | + the current entry. */ | ||
| 1365 | + if (TREE_CODE (t) == INTEGER_CST) | ||
| 1366 | + { | ||
| 1367 | + VEC_ordered_remove (operand_entry_t, *ops, currindex); | ||
| 1368 | + add_to_ops_vec (ops, t); | ||
| 1369 | + } | ||
| 1370 | + else if (!operand_equal_p (t, curr->op, 0)) | ||
| 1371 | + { | ||
| 1372 | + tree tmpvar; | ||
| 1373 | + gimple sum; | ||
| 1374 | + enum tree_code subcode; | ||
| 1375 | + tree newop1; | ||
| 1376 | + tree newop2; | ||
| 1377 | + tmpvar = create_tmp_var (TREE_TYPE (t), NULL); | ||
| 1378 | + add_referenced_var (tmpvar); | ||
| 1379 | + extract_ops_from_tree (t, &subcode, &newop1, &newop2); | ||
| 1380 | + sum = build_and_add_sum (tmpvar, newop1, newop2, subcode); | ||
| 1381 | + curr->op = gimple_get_lhs (sum); | ||
| 1382 | + } | ||
| 1383 | + return true; | ||
| 1384 | + } | ||
| 1385 | + | ||
| 1386 | + return false; | ||
| 1387 | +} | ||
| 1388 | |||
| 1389 | /* Perform various identities and other optimizations on the list of | ||
| 1390 | operand entries, stored in OPS. The tree code for the binary | ||
| 1391 | @@ -1220,7 +1331,8 @@ | ||
| 1392 | if (eliminate_not_pairs (opcode, ops, i, oe)) | ||
| 1393 | return; | ||
| 1394 | if (eliminate_duplicate_pair (opcode, ops, &done, i, oe, oelast) | ||
| 1395 | - || (!done && eliminate_plus_minus_pair (opcode, ops, i, oe))) | ||
| 1396 | + || (!done && eliminate_plus_minus_pair (opcode, ops, i, oe)) | ||
| 1397 | + || (!done && eliminate_redundant_comparison (opcode, ops, i, oe))) | ||
| 1398 | { | ||
| 1399 | if (done) | ||
| 1400 | return; | ||
| 1401 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99307.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99307.patch deleted file mode 100644 index 9c936d4fa..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99307.patch +++ /dev/null | |||
| @@ -1,138 +0,0 @@ | |||
| 1 | 2010-07-12 Yao Qi <yao@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ 4.4: | ||
| 4 | |||
| 5 | 2009-10-06 Paul Brook <paul@codesourcery.com> | ||
| 6 | Issue #3869 | ||
| 7 | gcc/ | ||
| 8 | * target.h (gcc_target): Add warn_func_result. | ||
| 9 | * target-def.h (TARGET_WARN_FUNC_RESULT): Define and use. | ||
| 10 | * tree-cfg.h (execute_warn_function_return): Use | ||
| 11 | targetm.warn_func_result. | ||
| 12 | * config/arm/arm.c (TARGET_WARN_FUNC_RESULT): Define. | ||
| 13 | (arm_warn_func_result): New function. | ||
| 14 | |||
| 15 | gcc/testuite/ | ||
| 16 | * gcc.target/arm/naked-3.c: New test. | ||
| 17 | |||
| 18 | 2010-07-10 Sandra Loosemore <sandra@codesourcery.com> | ||
| 19 | |||
| 20 | Backport from mainline: | ||
| 21 | |||
| 22 | === modified file 'gcc/config/arm/arm.c' | ||
| 23 | --- old/gcc/config/arm/arm.c 2010-07-29 16:58:56 +0000 | ||
| 24 | +++ new/gcc/config/arm/arm.c 2010-07-30 13:58:02 +0000 | ||
| 25 | @@ -214,6 +214,7 @@ | ||
| 26 | static int arm_issue_rate (void); | ||
| 27 | static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; | ||
| 28 | static bool arm_allocate_stack_slots_for_args (void); | ||
| 29 | +static bool arm_warn_func_result (void); | ||
| 30 | static const char *arm_invalid_parameter_type (const_tree t); | ||
| 31 | static const char *arm_invalid_return_type (const_tree t); | ||
| 32 | static tree arm_promoted_type (const_tree t); | ||
| 33 | @@ -378,6 +379,9 @@ | ||
| 34 | #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS | ||
| 35 | #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address | ||
| 36 | |||
| 37 | +#undef TARGET_WARN_FUNC_RESULT | ||
| 38 | +#define TARGET_WARN_FUNC_RESULT arm_warn_func_result | ||
| 39 | + | ||
| 40 | #undef TARGET_DEFAULT_SHORT_ENUMS | ||
| 41 | #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums | ||
| 42 | |||
| 43 | @@ -2008,6 +2012,14 @@ | ||
| 44 | return !IS_NAKED (arm_current_func_type ()); | ||
| 45 | } | ||
| 46 | |||
| 47 | +static bool | ||
| 48 | +arm_warn_func_result (void) | ||
| 49 | +{ | ||
| 50 | + /* Naked functions are implemented entirely in assembly, including the | ||
| 51 | + return sequence, so suppress warnings about this. */ | ||
| 52 | + return !IS_NAKED (arm_current_func_type ()); | ||
| 53 | +} | ||
| 54 | + | ||
| 55 | |||
| 56 | /* Output assembler code for a block containing the constant parts | ||
| 57 | of a trampoline, leaving space for the variable parts. | ||
| 58 | |||
| 59 | === modified file 'gcc/target-def.h' | ||
| 60 | --- old/gcc/target-def.h 2010-03-24 20:44:48 +0000 | ||
| 61 | +++ new/gcc/target-def.h 2010-07-30 13:58:02 +0000 | ||
| 62 | @@ -212,6 +212,10 @@ | ||
| 63 | #define TARGET_EXTRA_LIVE_ON_ENTRY hook_void_bitmap | ||
| 64 | #endif | ||
| 65 | |||
| 66 | +#ifndef TARGET_WARN_FUNC_RESULT | ||
| 67 | +#define TARGET_WARN_FUNC_RESULT hook_bool_void_true | ||
| 68 | +#endif | ||
| 69 | + | ||
| 70 | #ifndef TARGET_ASM_FILE_START_APP_OFF | ||
| 71 | #define TARGET_ASM_FILE_START_APP_OFF false | ||
| 72 | #endif | ||
| 73 | @@ -1020,6 +1024,7 @@ | ||
| 74 | TARGET_EMUTLS, \ | ||
| 75 | TARGET_OPTION_HOOKS, \ | ||
| 76 | TARGET_EXTRA_LIVE_ON_ENTRY, \ | ||
| 77 | + TARGET_WARN_FUNC_RESULT, \ | ||
| 78 | TARGET_UNWIND_TABLES_DEFAULT, \ | ||
| 79 | TARGET_HAVE_NAMED_SECTIONS, \ | ||
| 80 | TARGET_HAVE_SWITCHABLE_BSS_SECTIONS, \ | ||
| 81 | |||
| 82 | === modified file 'gcc/target.h' | ||
| 83 | --- old/gcc/target.h 2010-03-27 10:27:39 +0000 | ||
| 84 | +++ new/gcc/target.h 2010-07-30 13:58:02 +0000 | ||
| 85 | @@ -1171,6 +1171,10 @@ | ||
| 86 | bits in the bitmap passed in. */ | ||
| 87 | void (*live_on_entry) (bitmap); | ||
| 88 | |||
| 89 | + /* Return false if warnings about missing return statements or suspect | ||
| 90 | + noreturn attributes should be suppressed for the current function. */ | ||
| 91 | + bool (*warn_func_result) (void); | ||
| 92 | + | ||
| 93 | /* True if unwinding tables should be generated by default. */ | ||
| 94 | bool unwind_tables_default; | ||
| 95 | |||
| 96 | |||
| 97 | === added file 'gcc/testsuite/gcc.target/arm/naked-3.c' | ||
| 98 | --- old/gcc/testsuite/gcc.target/arm/naked-3.c 1970-01-01 00:00:00 +0000 | ||
| 99 | +++ new/gcc/testsuite/gcc.target/arm/naked-3.c 2010-07-30 13:58:02 +0000 | ||
| 100 | @@ -0,0 +1,15 @@ | ||
| 101 | +/* { dg-do compile } */ | ||
| 102 | +/* { dg-options "-O2 -Wall" } */ | ||
| 103 | +/* Check that we do not get warnings about missing return statements | ||
| 104 | + or bogus looking noreturn functions. */ | ||
| 105 | +int __attribute__((naked)) | ||
| 106 | +foo(void) | ||
| 107 | +{ | ||
| 108 | + __asm__ volatile ("mov r0, #1\r\nbx lr\n"); | ||
| 109 | +} | ||
| 110 | + | ||
| 111 | +int __attribute__((naked,noreturn)) | ||
| 112 | +bar(void) | ||
| 113 | +{ | ||
| 114 | + __asm__ volatile ("frob r0\n"); | ||
| 115 | +} | ||
| 116 | |||
| 117 | === modified file 'gcc/tree-cfg.c' | ||
| 118 | --- old/gcc/tree-cfg.c 2010-03-16 12:31:38 +0000 | ||
| 119 | +++ new/gcc/tree-cfg.c 2010-07-30 13:58:02 +0000 | ||
| 120 | @@ -47,6 +47,7 @@ | ||
| 121 | #include "value-prof.h" | ||
| 122 | #include "pointer-set.h" | ||
| 123 | #include "tree-inline.h" | ||
| 124 | +#include "target.h" | ||
| 125 | |||
| 126 | /* This file contains functions for building the Control Flow Graph (CFG) | ||
| 127 | for a function tree. */ | ||
| 128 | @@ -7092,6 +7093,9 @@ | ||
| 129 | edge e; | ||
| 130 | edge_iterator ei; | ||
| 131 | |||
| 132 | + if (!targetm.warn_func_result()) | ||
| 133 | + return 0; | ||
| 134 | + | ||
| 135 | /* If we have a path to EXIT, then we do return. */ | ||
| 136 | if (TREE_THIS_VOLATILE (cfun->decl) | ||
| 137 | && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0) | ||
| 138 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99308.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99308.patch deleted file mode 100644 index bf35a2ed4..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99308.patch +++ /dev/null | |||
| @@ -1,112 +0,0 @@ | |||
| 1 | 2010-07-15 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline (originally from Sourcery G++ 4.4): | ||
| 4 | |||
| 5 | gcc/cp/ | ||
| 6 | 2010-04-07 Jie Zhang <jie@codesourcery.com> | ||
| 7 | |||
| 8 | PR c++/42556 | ||
| 9 | * typeck2.c (split_nonconstant_init_1): Drop empty CONSTRUCTOR | ||
| 10 | when all of its elements are non-constant and have been split out. | ||
| 11 | |||
| 12 | gcc/testsuite/ | ||
| 13 | 2010-04-07 Jie Zhang <jie@codesourcery.com> | ||
| 14 | |||
| 15 | PR c++/42556 | ||
| 16 | * g++.dg/init/pr42556.C: New test. | ||
| 17 | |||
| 18 | 2010-07-12 Yao Qi <yao@codesourcery.com> | ||
| 19 | |||
| 20 | Merge from Sourcery G++ 4.4: | ||
| 21 | |||
| 22 | === modified file 'gcc/cp/typeck2.c' | ||
| 23 | --- old/gcc/cp/typeck2.c 2010-02-23 18:32:20 +0000 | ||
| 24 | +++ new/gcc/cp/typeck2.c 2010-07-30 14:05:57 +0000 | ||
| 25 | @@ -549,13 +549,15 @@ | ||
| 26 | expression to which INIT should be assigned. INIT is a CONSTRUCTOR. */ | ||
| 27 | |||
| 28 | static void | ||
| 29 | -split_nonconstant_init_1 (tree dest, tree init) | ||
| 30 | +split_nonconstant_init_1 (tree dest, tree *initp) | ||
| 31 | { | ||
| 32 | unsigned HOST_WIDE_INT idx; | ||
| 33 | + tree init = *initp; | ||
| 34 | tree field_index, value; | ||
| 35 | tree type = TREE_TYPE (dest); | ||
| 36 | tree inner_type = NULL; | ||
| 37 | bool array_type_p = false; | ||
| 38 | + HOST_WIDE_INT num_type_elements, num_initialized_elements; | ||
| 39 | |||
| 40 | switch (TREE_CODE (type)) | ||
| 41 | { | ||
| 42 | @@ -567,6 +569,7 @@ | ||
| 43 | case RECORD_TYPE: | ||
| 44 | case UNION_TYPE: | ||
| 45 | case QUAL_UNION_TYPE: | ||
| 46 | + num_initialized_elements = 0; | ||
| 47 | FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (init), idx, | ||
| 48 | field_index, value) | ||
| 49 | { | ||
| 50 | @@ -589,12 +592,13 @@ | ||
| 51 | sub = build3 (COMPONENT_REF, inner_type, dest, field_index, | ||
| 52 | NULL_TREE); | ||
| 53 | |||
| 54 | - split_nonconstant_init_1 (sub, value); | ||
| 55 | + split_nonconstant_init_1 (sub, &value); | ||
| 56 | } | ||
| 57 | else if (!initializer_constant_valid_p (value, inner_type)) | ||
| 58 | { | ||
| 59 | tree code; | ||
| 60 | tree sub; | ||
| 61 | + HOST_WIDE_INT inner_elements; | ||
| 62 | |||
| 63 | /* FIXME: Ordered removal is O(1) so the whole function is | ||
| 64 | worst-case quadratic. This could be fixed using an aside | ||
| 65 | @@ -617,9 +621,22 @@ | ||
| 66 | code = build2 (INIT_EXPR, inner_type, sub, value); | ||
| 67 | code = build_stmt (input_location, EXPR_STMT, code); | ||
| 68 | add_stmt (code); | ||
| 69 | + | ||
| 70 | + inner_elements = count_type_elements (inner_type, true); | ||
| 71 | + if (inner_elements < 0) | ||
| 72 | + num_initialized_elements = -1; | ||
| 73 | + else if (num_initialized_elements >= 0) | ||
| 74 | + num_initialized_elements += inner_elements; | ||
| 75 | continue; | ||
| 76 | } | ||
| 77 | } | ||
| 78 | + | ||
| 79 | + num_type_elements = count_type_elements (type, true); | ||
| 80 | + /* If all elements of the initializer are non-constant and | ||
| 81 | + have been split out, we don't need the empty CONSTRUCTOR. */ | ||
| 82 | + if (num_type_elements > 0 | ||
| 83 | + && num_type_elements == num_initialized_elements) | ||
| 84 | + *initp = NULL; | ||
| 85 | break; | ||
| 86 | |||
| 87 | case VECTOR_TYPE: | ||
| 88 | @@ -655,7 +672,7 @@ | ||
| 89 | if (TREE_CODE (init) == CONSTRUCTOR) | ||
| 90 | { | ||
| 91 | code = push_stmt_list (); | ||
| 92 | - split_nonconstant_init_1 (dest, init); | ||
| 93 | + split_nonconstant_init_1 (dest, &init); | ||
| 94 | code = pop_stmt_list (code); | ||
| 95 | DECL_INITIAL (dest) = init; | ||
| 96 | TREE_READONLY (dest) = 0; | ||
| 97 | |||
| 98 | === added file 'gcc/testsuite/g++.dg/init/pr42556.C' | ||
| 99 | --- old/gcc/testsuite/g++.dg/init/pr42556.C 1970-01-01 00:00:00 +0000 | ||
| 100 | +++ new/gcc/testsuite/g++.dg/init/pr42556.C 2010-07-30 14:05:57 +0000 | ||
| 101 | @@ -0,0 +1,10 @@ | ||
| 102 | +// { dg-do compile } | ||
| 103 | +// { dg-options "-fdump-tree-gimple" } | ||
| 104 | + | ||
| 105 | +void foo (int a, int b, int c, int d) | ||
| 106 | +{ | ||
| 107 | + int v[4] = {a, b, c, d}; | ||
| 108 | +} | ||
| 109 | + | ||
| 110 | +// { dg-final { scan-tree-dump-not "v = {}" "gimple" } } | ||
| 111 | +// { dg-final { cleanup-tree-dump "gimple" } } | ||
| 112 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99310.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99310.patch deleted file mode 100644 index da95fba79..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99310.patch +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | Backport from mainline (originally from Sourcery G++ 4.4): | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | 2010-07-07 Jie Zhang <jie@codesourcery.com> | ||
| 5 | * genautomata.c (output_automata_list_min_issue_delay_code): | ||
| 6 | Correctly decompress min_issue_delay. | ||
| 7 | |||
| 8 | 2010-07-15 Jie Zhang <jie@codesourcery.com> | ||
| 9 | |||
| 10 | Issue #8980 | ||
| 11 | |||
| 12 | Backport from mainline (originally from Sourcery G++ 4.4): | ||
| 13 | |||
| 14 | === modified file 'gcc/genautomata.c' | ||
| 15 | --- old/gcc/genautomata.c 2009-11-25 10:55:54 +0000 | ||
| 16 | +++ new/gcc/genautomata.c 2010-07-30 14:21:58 +0000 | ||
| 17 | @@ -7865,12 +7865,15 @@ | ||
| 18 | { | ||
| 19 | fprintf (output_file, ") / %d];\n", | ||
| 20 | automaton->min_issue_delay_table_compression_factor); | ||
| 21 | - fprintf (output_file, " %s = (%s >> (8 - (", | ||
| 22 | + fprintf (output_file, " %s = (%s >> (8 - ((", | ||
| 23 | TEMPORARY_VARIABLE_NAME, TEMPORARY_VARIABLE_NAME); | ||
| 24 | output_translate_vect_name (output_file, automaton); | ||
| 25 | + fprintf (output_file, " [%s] + ", INTERNAL_INSN_CODE_NAME); | ||
| 26 | + fprintf (output_file, "%s->", CHIP_PARAMETER_NAME); | ||
| 27 | + output_chip_member_name (output_file, automaton); | ||
| 28 | + fprintf (output_file, " * %d)", automaton->insn_equiv_classes_num); | ||
| 29 | fprintf | ||
| 30 | - (output_file, " [%s] %% %d + 1) * %d)) & %d;\n", | ||
| 31 | - INTERNAL_INSN_CODE_NAME, | ||
| 32 | + (output_file, " %% %d + 1) * %d)) & %d;\n", | ||
| 33 | automaton->min_issue_delay_table_compression_factor, | ||
| 34 | 8 / automaton->min_issue_delay_table_compression_factor, | ||
| 35 | (1 << (8 / automaton->min_issue_delay_table_compression_factor)) | ||
| 36 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99312.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99312.patch deleted file mode 100644 index 9f0c98e9c..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99312.patch +++ /dev/null | |||
| @@ -1,714 +0,0 @@ | |||
| 1 | 2010-07-15 Sandra Loosemore <sandra@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-06-09 Sandra Loosemore <sandra@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * tree-ssa-loop-ivopts.c (adjust_setup_cost): New function. | ||
| 9 | (get_computation_cost_at): Use it. | ||
| 10 | (determine_use_iv_cost_condition): Likewise. | ||
| 11 | (determine_iv_cost): Likewise. | ||
| 12 | |||
| 13 | 2010-07-05 Sandra Loosemore <sandra@codesourcery.com> | ||
| 14 | |||
| 15 | PR middle-end/42505 | ||
| 16 | |||
| 17 | gcc/ | ||
| 18 | * tree-ssa-loop-ivopts.c (determine_set_costs): Delete obsolete | ||
| 19 | comments about cost model. | ||
| 20 | (try_add_cand_for): Add second strategy for choosing initial set | ||
| 21 | based on original IVs, controlled by ORIGINALP argument. | ||
| 22 | (get_initial_solution): Add ORIGINALP argument. | ||
| 23 | (find_optimal_iv_set_1): New function, split from find_optimal_iv_set. | ||
| 24 | (find_optimal_iv_set): Try two different strategies for choosing | ||
| 25 | the IV set, and return the one with lower cost. | ||
| 26 | |||
| 27 | gcc/testsuite/ | ||
| 28 | * gcc.target/arm/pr42505.c: New test case. | ||
| 29 | |||
| 30 | 2010-07-10 Sandra Loosemore <sandra@codesourcery.com> | ||
| 31 | |||
| 32 | PR middle-end/42505 | ||
| 33 | |||
| 34 | gcc/ | ||
| 35 | * tree-inline.c (estimate_num_insns): Refactor builtin complexity | ||
| 36 | lookup code into.... | ||
| 37 | * builtins.c (is_simple_builtin, is_inexpensive_builtin): ...these | ||
| 38 | new functions. | ||
| 39 | * tree.h (is_simple_builtin, is_inexpensive_builtin): Declare. | ||
| 40 | * cfgloopanal.c (target_clobbered_regs): Define. | ||
| 41 | (init_set_costs): Initialize target_clobbered_regs. | ||
| 42 | (estimate_reg_pressure_cost): Add call_p argument. When true, | ||
| 43 | adjust the number of available registers to exclude the | ||
| 44 | call-clobbered registers. | ||
| 45 | * cfgloop.h (target_clobbered_regs): Declare. | ||
| 46 | (estimate_reg_pressure_cost): Adjust declaration. | ||
| 47 | * tree-ssa-loop-ivopts.c (struct ivopts_data): Add body_includes_call. | ||
| 48 | (ivopts_global_cost_for_size): Pass it to estimate_reg_pressure_cost. | ||
| 49 | (determine_set_costs): Dump target_clobbered_regs. | ||
| 50 | (loop_body_includes_call): New function. | ||
| 51 | (tree_ssa_iv_optimize_loop): Use it to initialize new field. | ||
| 52 | * loop-invariant.c (gain_for_invariant): Adjust arguments to pass | ||
| 53 | call_p flag through. | ||
| 54 | (best_gain_for_invariant): Likewise. | ||
| 55 | (find_invariants_to_move): Likewise. | ||
| 56 | (move_single_loop_invariants): Likewise, using already-computed | ||
| 57 | has_call field. | ||
| 58 | |||
| 59 | 2010-07-15 Jie Zhang <jie@codesourcery.com> | ||
| 60 | |||
| 61 | Issue #8497, #8893 | ||
| 62 | |||
| 63 | === modified file 'gcc/builtins.c' | ||
| 64 | --- old/gcc/builtins.c 2010-04-13 12:47:11 +0000 | ||
| 65 | +++ new/gcc/builtins.c 2010-08-02 13:51:23 +0000 | ||
| 66 | @@ -13624,3 +13624,123 @@ | ||
| 67 | break; | ||
| 68 | } | ||
| 69 | } | ||
| 70 | + | ||
| 71 | +/* Return true if DECL is a builtin that expands to a constant or similarly | ||
| 72 | + simple code. */ | ||
| 73 | +bool | ||
| 74 | +is_simple_builtin (tree decl) | ||
| 75 | +{ | ||
| 76 | + if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL) | ||
| 77 | + switch (DECL_FUNCTION_CODE (decl)) | ||
| 78 | + { | ||
| 79 | + /* Builtins that expand to constants. */ | ||
| 80 | + case BUILT_IN_CONSTANT_P: | ||
| 81 | + case BUILT_IN_EXPECT: | ||
| 82 | + case BUILT_IN_OBJECT_SIZE: | ||
| 83 | + case BUILT_IN_UNREACHABLE: | ||
| 84 | + /* Simple register moves or loads from stack. */ | ||
| 85 | + case BUILT_IN_RETURN_ADDRESS: | ||
| 86 | + case BUILT_IN_EXTRACT_RETURN_ADDR: | ||
| 87 | + case BUILT_IN_FROB_RETURN_ADDR: | ||
| 88 | + case BUILT_IN_RETURN: | ||
| 89 | + case BUILT_IN_AGGREGATE_INCOMING_ADDRESS: | ||
| 90 | + case BUILT_IN_FRAME_ADDRESS: | ||
| 91 | + case BUILT_IN_VA_END: | ||
| 92 | + case BUILT_IN_STACK_SAVE: | ||
| 93 | + case BUILT_IN_STACK_RESTORE: | ||
| 94 | + /* Exception state returns or moves registers around. */ | ||
| 95 | + case BUILT_IN_EH_FILTER: | ||
| 96 | + case BUILT_IN_EH_POINTER: | ||
| 97 | + case BUILT_IN_EH_COPY_VALUES: | ||
| 98 | + return true; | ||
| 99 | + | ||
| 100 | + default: | ||
| 101 | + return false; | ||
| 102 | + } | ||
| 103 | + | ||
| 104 | + return false; | ||
| 105 | +} | ||
| 106 | + | ||
| 107 | +/* Return true if DECL is a builtin that is not expensive, i.e., they are | ||
| 108 | + most probably expanded inline into reasonably simple code. This is a | ||
| 109 | + superset of is_simple_builtin. */ | ||
| 110 | +bool | ||
| 111 | +is_inexpensive_builtin (tree decl) | ||
| 112 | +{ | ||
| 113 | + if (!decl) | ||
| 114 | + return false; | ||
| 115 | + else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_MD) | ||
| 116 | + return true; | ||
| 117 | + else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL) | ||
| 118 | + switch (DECL_FUNCTION_CODE (decl)) | ||
| 119 | + { | ||
| 120 | + case BUILT_IN_ABS: | ||
| 121 | + case BUILT_IN_ALLOCA: | ||
| 122 | + case BUILT_IN_BSWAP32: | ||
| 123 | + case BUILT_IN_BSWAP64: | ||
| 124 | + case BUILT_IN_CLZ: | ||
| 125 | + case BUILT_IN_CLZIMAX: | ||
| 126 | + case BUILT_IN_CLZL: | ||
| 127 | + case BUILT_IN_CLZLL: | ||
| 128 | + case BUILT_IN_CTZ: | ||
| 129 | + case BUILT_IN_CTZIMAX: | ||
| 130 | + case BUILT_IN_CTZL: | ||
| 131 | + case BUILT_IN_CTZLL: | ||
| 132 | + case BUILT_IN_FFS: | ||
| 133 | + case BUILT_IN_FFSIMAX: | ||
| 134 | + case BUILT_IN_FFSL: | ||
| 135 | + case BUILT_IN_FFSLL: | ||
| 136 | + case BUILT_IN_IMAXABS: | ||
| 137 | + case BUILT_IN_FINITE: | ||
| 138 | + case BUILT_IN_FINITEF: | ||
| 139 | + case BUILT_IN_FINITEL: | ||
| 140 | + case BUILT_IN_FINITED32: | ||
| 141 | + case BUILT_IN_FINITED64: | ||
| 142 | + case BUILT_IN_FINITED128: | ||
| 143 | + case BUILT_IN_FPCLASSIFY: | ||
| 144 | + case BUILT_IN_ISFINITE: | ||
| 145 | + case BUILT_IN_ISINF_SIGN: | ||
| 146 | + case BUILT_IN_ISINF: | ||
| 147 | + case BUILT_IN_ISINFF: | ||
| 148 | + case BUILT_IN_ISINFL: | ||
| 149 | + case BUILT_IN_ISINFD32: | ||
| 150 | + case BUILT_IN_ISINFD64: | ||
| 151 | + case BUILT_IN_ISINFD128: | ||
| 152 | + case BUILT_IN_ISNAN: | ||
| 153 | + case BUILT_IN_ISNANF: | ||
| 154 | + case BUILT_IN_ISNANL: | ||
| 155 | + case BUILT_IN_ISNAND32: | ||
| 156 | + case BUILT_IN_ISNAND64: | ||
| 157 | + case BUILT_IN_ISNAND128: | ||
| 158 | + case BUILT_IN_ISNORMAL: | ||
| 159 | + case BUILT_IN_ISGREATER: | ||
| 160 | + case BUILT_IN_ISGREATEREQUAL: | ||
| 161 | + case BUILT_IN_ISLESS: | ||
| 162 | + case BUILT_IN_ISLESSEQUAL: | ||
| 163 | + case BUILT_IN_ISLESSGREATER: | ||
| 164 | + case BUILT_IN_ISUNORDERED: | ||
| 165 | + case BUILT_IN_VA_ARG_PACK: | ||
| 166 | + case BUILT_IN_VA_ARG_PACK_LEN: | ||
| 167 | + case BUILT_IN_VA_COPY: | ||
| 168 | + case BUILT_IN_TRAP: | ||
| 169 | + case BUILT_IN_SAVEREGS: | ||
| 170 | + case BUILT_IN_POPCOUNTL: | ||
| 171 | + case BUILT_IN_POPCOUNTLL: | ||
| 172 | + case BUILT_IN_POPCOUNTIMAX: | ||
| 173 | + case BUILT_IN_POPCOUNT: | ||
| 174 | + case BUILT_IN_PARITYL: | ||
| 175 | + case BUILT_IN_PARITYLL: | ||
| 176 | + case BUILT_IN_PARITYIMAX: | ||
| 177 | + case BUILT_IN_PARITY: | ||
| 178 | + case BUILT_IN_LABS: | ||
| 179 | + case BUILT_IN_LLABS: | ||
| 180 | + case BUILT_IN_PREFETCH: | ||
| 181 | + return true; | ||
| 182 | + | ||
| 183 | + default: | ||
| 184 | + return is_simple_builtin (decl); | ||
| 185 | + } | ||
| 186 | + | ||
| 187 | + return false; | ||
| 188 | +} | ||
| 189 | + | ||
| 190 | |||
| 191 | === modified file 'gcc/cfgloop.h' | ||
| 192 | --- old/gcc/cfgloop.h 2009-11-25 10:55:54 +0000 | ||
| 193 | +++ new/gcc/cfgloop.h 2010-08-02 13:51:23 +0000 | ||
| 194 | @@ -622,13 +622,14 @@ | ||
| 195 | /* The properties of the target. */ | ||
| 196 | |||
| 197 | extern unsigned target_avail_regs; | ||
| 198 | +extern unsigned target_clobbered_regs; | ||
| 199 | extern unsigned target_res_regs; | ||
| 200 | extern unsigned target_reg_cost [2]; | ||
| 201 | extern unsigned target_spill_cost [2]; | ||
| 202 | |||
| 203 | /* Register pressure estimation for induction variable optimizations & loop | ||
| 204 | invariant motion. */ | ||
| 205 | -extern unsigned estimate_reg_pressure_cost (unsigned, unsigned, bool); | ||
| 206 | +extern unsigned estimate_reg_pressure_cost (unsigned, unsigned, bool, bool); | ||
| 207 | extern void init_set_costs (void); | ||
| 208 | |||
| 209 | /* Loop optimizer initialization. */ | ||
| 210 | |||
| 211 | === modified file 'gcc/cfgloopanal.c' | ||
| 212 | --- old/gcc/cfgloopanal.c 2009-09-30 08:57:56 +0000 | ||
| 213 | +++ new/gcc/cfgloopanal.c 2010-08-02 13:51:23 +0000 | ||
| 214 | @@ -320,6 +320,8 @@ | ||
| 215 | /* The properties of the target. */ | ||
| 216 | |||
| 217 | unsigned target_avail_regs; /* Number of available registers. */ | ||
| 218 | +unsigned target_clobbered_regs; /* Number of available registers that are | ||
| 219 | + call-clobbered. */ | ||
| 220 | unsigned target_res_regs; /* Number of registers reserved for temporary | ||
| 221 | expressions. */ | ||
| 222 | unsigned target_reg_cost[2]; /* The cost for register when there still | ||
| 223 | @@ -342,10 +344,15 @@ | ||
| 224 | unsigned i; | ||
| 225 | |||
| 226 | target_avail_regs = 0; | ||
| 227 | + target_clobbered_regs = 0; | ||
| 228 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 229 | if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i) | ||
| 230 | && !fixed_regs[i]) | ||
| 231 | - target_avail_regs++; | ||
| 232 | + { | ||
| 233 | + target_avail_regs++; | ||
| 234 | + if (call_used_regs[i]) | ||
| 235 | + target_clobbered_regs++; | ||
| 236 | + } | ||
| 237 | |||
| 238 | target_res_regs = 3; | ||
| 239 | |||
| 240 | @@ -379,20 +386,29 @@ | ||
| 241 | |||
| 242 | /* Estimates cost of increased register pressure caused by making N_NEW new | ||
| 243 | registers live around the loop. N_OLD is the number of registers live | ||
| 244 | - around the loop. */ | ||
| 245 | + around the loop. If CALL_P is true, also take into account that | ||
| 246 | + call-used registers may be clobbered in the loop body, reducing the | ||
| 247 | + number of available registers before we spill. */ | ||
| 248 | |||
| 249 | unsigned | ||
| 250 | -estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed) | ||
| 251 | +estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed, | ||
| 252 | + bool call_p) | ||
| 253 | { | ||
| 254 | unsigned cost; | ||
| 255 | unsigned regs_needed = n_new + n_old; | ||
| 256 | + unsigned available_regs = target_avail_regs; | ||
| 257 | + | ||
| 258 | + /* If there is a call in the loop body, the call-clobbered registers | ||
| 259 | + are not available for loop invariants. */ | ||
| 260 | + if (call_p) | ||
| 261 | + available_regs = available_regs - target_clobbered_regs; | ||
| 262 | |||
| 263 | /* If we have enough registers, we should use them and not restrict | ||
| 264 | the transformations unnecessarily. */ | ||
| 265 | - if (regs_needed + target_res_regs <= target_avail_regs) | ||
| 266 | + if (regs_needed + target_res_regs <= available_regs) | ||
| 267 | return 0; | ||
| 268 | |||
| 269 | - if (regs_needed <= target_avail_regs) | ||
| 270 | + if (regs_needed <= available_regs) | ||
| 271 | /* If we are close to running out of registers, try to preserve | ||
| 272 | them. */ | ||
| 273 | cost = target_reg_cost [speed] * n_new; | ||
| 274 | |||
| 275 | === modified file 'gcc/loop-invariant.c' | ||
| 276 | --- old/gcc/loop-invariant.c 2010-04-02 18:54:46 +0000 | ||
| 277 | +++ new/gcc/loop-invariant.c 2010-08-02 13:51:23 +0000 | ||
| 278 | @@ -1173,11 +1173,13 @@ | ||
| 279 | /* Calculates gain for eliminating invariant INV. REGS_USED is the number | ||
| 280 | of registers used in the loop, NEW_REGS is the number of new variables | ||
| 281 | already added due to the invariant motion. The number of registers needed | ||
| 282 | - for it is stored in *REGS_NEEDED. */ | ||
| 283 | + for it is stored in *REGS_NEEDED. SPEED and CALL_P are flags passed | ||
| 284 | + through to estimate_reg_pressure_cost. */ | ||
| 285 | |||
| 286 | static int | ||
| 287 | gain_for_invariant (struct invariant *inv, unsigned *regs_needed, | ||
| 288 | - unsigned *new_regs, unsigned regs_used, bool speed) | ||
| 289 | + unsigned *new_regs, unsigned regs_used, | ||
| 290 | + bool speed, bool call_p) | ||
| 291 | { | ||
| 292 | int comp_cost, size_cost; | ||
| 293 | |||
| 294 | @@ -1188,9 +1190,9 @@ | ||
| 295 | if (! flag_ira_loop_pressure) | ||
| 296 | { | ||
| 297 | size_cost = (estimate_reg_pressure_cost (new_regs[0] + regs_needed[0], | ||
| 298 | - regs_used, speed) | ||
| 299 | + regs_used, speed, call_p) | ||
| 300 | - estimate_reg_pressure_cost (new_regs[0], | ||
| 301 | - regs_used, speed)); | ||
| 302 | + regs_used, speed, call_p)); | ||
| 303 | } | ||
| 304 | else | ||
| 305 | { | ||
| 306 | @@ -1245,7 +1247,8 @@ | ||
| 307 | |||
| 308 | static int | ||
| 309 | best_gain_for_invariant (struct invariant **best, unsigned *regs_needed, | ||
| 310 | - unsigned *new_regs, unsigned regs_used, bool speed) | ||
| 311 | + unsigned *new_regs, unsigned regs_used, | ||
| 312 | + bool speed, bool call_p) | ||
| 313 | { | ||
| 314 | struct invariant *inv; | ||
| 315 | int i, gain = 0, again; | ||
| 316 | @@ -1261,7 +1264,7 @@ | ||
| 317 | continue; | ||
| 318 | |||
| 319 | again = gain_for_invariant (inv, aregs_needed, new_regs, regs_used, | ||
| 320 | - speed); | ||
| 321 | + speed, call_p); | ||
| 322 | if (again > gain) | ||
| 323 | { | ||
| 324 | gain = again; | ||
| 325 | @@ -1314,7 +1317,7 @@ | ||
| 326 | /* Determines which invariants to move. */ | ||
| 327 | |||
| 328 | static void | ||
| 329 | -find_invariants_to_move (bool speed) | ||
| 330 | +find_invariants_to_move (bool speed, bool call_p) | ||
| 331 | { | ||
| 332 | int gain; | ||
| 333 | unsigned i, regs_used, regs_needed[N_REG_CLASSES], new_regs[N_REG_CLASSES]; | ||
| 334 | @@ -1353,7 +1356,8 @@ | ||
| 335 | new_regs[ira_reg_class_cover[i]] = 0; | ||
| 336 | } | ||
| 337 | while ((gain = best_gain_for_invariant (&inv, regs_needed, | ||
| 338 | - new_regs, regs_used, speed)) > 0) | ||
| 339 | + new_regs, regs_used, | ||
| 340 | + speed, call_p)) > 0) | ||
| 341 | { | ||
| 342 | set_move_mark (inv->invno, gain); | ||
| 343 | if (! flag_ira_loop_pressure) | ||
| 344 | @@ -1554,7 +1558,8 @@ | ||
| 345 | init_inv_motion_data (); | ||
| 346 | |||
| 347 | find_invariants (loop); | ||
| 348 | - find_invariants_to_move (optimize_loop_for_speed_p (loop)); | ||
| 349 | + find_invariants_to_move (optimize_loop_for_speed_p (loop), | ||
| 350 | + LOOP_DATA (loop)->has_call); | ||
| 351 | move_invariants (loop); | ||
| 352 | |||
| 353 | free_inv_motion_data (); | ||
| 354 | |||
| 355 | === added file 'gcc/testsuite/gcc.target/arm/pr42505.c' | ||
| 356 | --- old/gcc/testsuite/gcc.target/arm/pr42505.c 1970-01-01 00:00:00 +0000 | ||
| 357 | +++ new/gcc/testsuite/gcc.target/arm/pr42505.c 2010-08-02 13:51:23 +0000 | ||
| 358 | @@ -0,0 +1,23 @@ | ||
| 359 | +/* { dg-options "-mthumb -Os -march=armv5te" } */ | ||
| 360 | +/* { dg-require-effective-target arm_thumb1_ok } */ | ||
| 361 | +/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */ | ||
| 362 | + | ||
| 363 | +struct A { | ||
| 364 | + int f1; | ||
| 365 | + int f2; | ||
| 366 | +}; | ||
| 367 | + | ||
| 368 | +int func(int c); | ||
| 369 | + | ||
| 370 | +/* This function should not need to spill anything to the stack. */ | ||
| 371 | +int test(struct A* src, struct A* dst, int count) | ||
| 372 | +{ | ||
| 373 | + while (count--) { | ||
| 374 | + if (!func(src->f2)) { | ||
| 375 | + return 0; | ||
| 376 | + } | ||
| 377 | + *dst++ = *src++; | ||
| 378 | + } | ||
| 379 | + | ||
| 380 | + return 1; | ||
| 381 | +} | ||
| 382 | |||
| 383 | === modified file 'gcc/tree-inline.c' | ||
| 384 | --- old/gcc/tree-inline.c 2010-03-18 20:07:13 +0000 | ||
| 385 | +++ new/gcc/tree-inline.c 2010-08-02 13:51:23 +0000 | ||
| 386 | @@ -3246,34 +3246,13 @@ | ||
| 387 | if (POINTER_TYPE_P (funtype)) | ||
| 388 | funtype = TREE_TYPE (funtype); | ||
| 389 | |||
| 390 | - if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_MD) | ||
| 391 | + if (is_simple_builtin (decl)) | ||
| 392 | + return 0; | ||
| 393 | + else if (is_inexpensive_builtin (decl)) | ||
| 394 | cost = weights->target_builtin_call_cost; | ||
| 395 | else | ||
| 396 | cost = weights->call_cost; | ||
| 397 | |||
| 398 | - if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL) | ||
| 399 | - switch (DECL_FUNCTION_CODE (decl)) | ||
| 400 | - { | ||
| 401 | - case BUILT_IN_CONSTANT_P: | ||
| 402 | - return 0; | ||
| 403 | - case BUILT_IN_EXPECT: | ||
| 404 | - return 0; | ||
| 405 | - | ||
| 406 | - /* Prefetch instruction is not expensive. */ | ||
| 407 | - case BUILT_IN_PREFETCH: | ||
| 408 | - cost = weights->target_builtin_call_cost; | ||
| 409 | - break; | ||
| 410 | - | ||
| 411 | - /* Exception state returns or moves registers around. */ | ||
| 412 | - case BUILT_IN_EH_FILTER: | ||
| 413 | - case BUILT_IN_EH_POINTER: | ||
| 414 | - case BUILT_IN_EH_COPY_VALUES: | ||
| 415 | - return 0; | ||
| 416 | - | ||
| 417 | - default: | ||
| 418 | - break; | ||
| 419 | - } | ||
| 420 | - | ||
| 421 | if (decl) | ||
| 422 | funtype = TREE_TYPE (decl); | ||
| 423 | |||
| 424 | |||
| 425 | === modified file 'gcc/tree-ssa-loop-ivopts.c' | ||
| 426 | --- old/gcc/tree-ssa-loop-ivopts.c 2010-04-01 15:18:07 +0000 | ||
| 427 | +++ new/gcc/tree-ssa-loop-ivopts.c 2010-08-02 13:51:23 +0000 | ||
| 428 | @@ -257,6 +257,9 @@ | ||
| 429 | |||
| 430 | /* Are we optimizing for speed? */ | ||
| 431 | bool speed; | ||
| 432 | + | ||
| 433 | + /* Whether the loop body includes any function calls. */ | ||
| 434 | + bool body_includes_call; | ||
| 435 | }; | ||
| 436 | |||
| 437 | /* An assignment of iv candidates to uses. */ | ||
| 438 | @@ -2926,6 +2929,20 @@ | ||
| 439 | return get_computation_at (loop, use, cand, use->stmt); | ||
| 440 | } | ||
| 441 | |||
| 442 | +/* Adjust the cost COST for being in loop setup rather than loop body. | ||
| 443 | + If we're optimizing for space, the loop setup overhead is constant; | ||
| 444 | + if we're optimizing for speed, amortize it over the per-iteration cost. */ | ||
| 445 | +static unsigned | ||
| 446 | +adjust_setup_cost (struct ivopts_data *data, unsigned cost) | ||
| 447 | +{ | ||
| 448 | + if (cost == INFTY) | ||
| 449 | + return cost; | ||
| 450 | + else if (optimize_loop_for_speed_p (data->current_loop)) | ||
| 451 | + return cost / AVG_LOOP_NITER (data->current_loop); | ||
| 452 | + else | ||
| 453 | + return cost; | ||
| 454 | +} | ||
| 455 | + | ||
| 456 | /* Returns cost of addition in MODE. */ | ||
| 457 | |||
| 458 | static unsigned | ||
| 459 | @@ -3838,8 +3855,8 @@ | ||
| 460 | /* Symbol + offset should be compile-time computable so consider that they | ||
| 461 | are added once to the variable, if present. */ | ||
| 462 | if (var_present && (symbol_present || offset)) | ||
| 463 | - cost.cost += add_cost (TYPE_MODE (ctype), speed) | ||
| 464 | - / AVG_LOOP_NITER (data->current_loop); | ||
| 465 | + cost.cost += adjust_setup_cost (data, | ||
| 466 | + add_cost (TYPE_MODE (ctype), speed)); | ||
| 467 | |||
| 468 | /* Having offset does not affect runtime cost in case it is added to | ||
| 469 | symbol, but it increases complexity. */ | ||
| 470 | @@ -4104,7 +4121,7 @@ | ||
| 471 | elim_cost = force_var_cost (data, bound, &depends_on_elim); | ||
| 472 | /* The bound is a loop invariant, so it will be only computed | ||
| 473 | once. */ | ||
| 474 | - elim_cost.cost /= AVG_LOOP_NITER (data->current_loop); | ||
| 475 | + elim_cost.cost = adjust_setup_cost (data, elim_cost.cost); | ||
| 476 | } | ||
| 477 | else | ||
| 478 | elim_cost = infinite_cost; | ||
| 479 | @@ -4351,7 +4368,7 @@ | ||
| 480 | cost_base = force_var_cost (data, base, NULL); | ||
| 481 | cost_step = add_cost (TYPE_MODE (TREE_TYPE (base)), data->speed); | ||
| 482 | |||
| 483 | - cost = cost_step + cost_base.cost / AVG_LOOP_NITER (current_loop); | ||
| 484 | + cost = cost_step + adjust_setup_cost (data, cost_base.cost); | ||
| 485 | |||
| 486 | /* Prefer the original ivs unless we may gain something by replacing it. | ||
| 487 | The reason is to make debugging simpler; so this is not relevant for | ||
| 488 | @@ -4404,7 +4421,8 @@ | ||
| 489 | { | ||
| 490 | /* We add size to the cost, so that we prefer eliminating ivs | ||
| 491 | if possible. */ | ||
| 492 | - return size + estimate_reg_pressure_cost (size, data->regs_used, data->speed); | ||
| 493 | + return size + estimate_reg_pressure_cost (size, data->regs_used, data->speed, | ||
| 494 | + data->body_includes_call); | ||
| 495 | } | ||
| 496 | |||
| 497 | /* For each size of the induction variable set determine the penalty. */ | ||
| 498 | @@ -4419,30 +4437,11 @@ | ||
| 499 | struct loop *loop = data->current_loop; | ||
| 500 | bitmap_iterator bi; | ||
| 501 | |||
| 502 | - /* We use the following model (definitely improvable, especially the | ||
| 503 | - cost function -- TODO): | ||
| 504 | - | ||
| 505 | - We estimate the number of registers available (using MD data), name it A. | ||
| 506 | - | ||
| 507 | - We estimate the number of registers used by the loop, name it U. This | ||
| 508 | - number is obtained as the number of loop phi nodes (not counting virtual | ||
| 509 | - registers and bivs) + the number of variables from outside of the loop. | ||
| 510 | - | ||
| 511 | - We set a reserve R (free regs that are used for temporary computations, | ||
| 512 | - etc.). For now the reserve is a constant 3. | ||
| 513 | - | ||
| 514 | - Let I be the number of induction variables. | ||
| 515 | - | ||
| 516 | - -- if U + I + R <= A, the cost is I * SMALL_COST (just not to encourage | ||
| 517 | - make a lot of ivs without a reason). | ||
| 518 | - -- if A - R < U + I <= A, the cost is I * PRES_COST | ||
| 519 | - -- if U + I > A, the cost is I * PRES_COST and | ||
| 520 | - number of uses * SPILL_COST * (U + I - A) / (U + I) is added. */ | ||
| 521 | - | ||
| 522 | if (dump_file && (dump_flags & TDF_DETAILS)) | ||
| 523 | { | ||
| 524 | fprintf (dump_file, "Global costs:\n"); | ||
| 525 | fprintf (dump_file, " target_avail_regs %d\n", target_avail_regs); | ||
| 526 | + fprintf (dump_file, " target_clobbered_regs %d\n", target_clobbered_regs); | ||
| 527 | fprintf (dump_file, " target_reg_cost %d\n", target_reg_cost[data->speed]); | ||
| 528 | fprintf (dump_file, " target_spill_cost %d\n", target_spill_cost[data->speed]); | ||
| 529 | } | ||
| 530 | @@ -5062,11 +5061,13 @@ | ||
| 531 | } | ||
| 532 | |||
| 533 | /* Tries to extend the sets IVS in the best possible way in order | ||
| 534 | - to express the USE. */ | ||
| 535 | + to express the USE. If ORIGINALP is true, prefer candidates from | ||
| 536 | + the original set of IVs, otherwise favor important candidates not | ||
| 537 | + based on any memory object. */ | ||
| 538 | |||
| 539 | static bool | ||
| 540 | try_add_cand_for (struct ivopts_data *data, struct iv_ca *ivs, | ||
| 541 | - struct iv_use *use) | ||
| 542 | + struct iv_use *use, bool originalp) | ||
| 543 | { | ||
| 544 | comp_cost best_cost, act_cost; | ||
| 545 | unsigned i; | ||
| 546 | @@ -5085,7 +5086,8 @@ | ||
| 547 | iv_ca_set_no_cp (data, ivs, use); | ||
| 548 | } | ||
| 549 | |||
| 550 | - /* First try important candidates not based on any memory object. Only if | ||
| 551 | + /* If ORIGINALP is true, try to find the original IV for the use. Otherwise | ||
| 552 | + first try important candidates not based on any memory object. Only if | ||
| 553 | this fails, try the specific ones. Rationale -- in loops with many | ||
| 554 | variables the best choice often is to use just one generic biv. If we | ||
| 555 | added here many ivs specific to the uses, the optimization algorithm later | ||
| 556 | @@ -5097,7 +5099,10 @@ | ||
| 557 | { | ||
| 558 | cand = iv_cand (data, i); | ||
| 559 | |||
| 560 | - if (cand->iv->base_object != NULL_TREE) | ||
| 561 | + if (originalp && cand->pos !=IP_ORIGINAL) | ||
| 562 | + continue; | ||
| 563 | + | ||
| 564 | + if (!originalp && cand->iv->base_object != NULL_TREE) | ||
| 565 | continue; | ||
| 566 | |||
| 567 | if (iv_ca_cand_used_p (ivs, cand)) | ||
| 568 | @@ -5133,8 +5138,13 @@ | ||
| 569 | continue; | ||
| 570 | |||
| 571 | /* Already tried this. */ | ||
| 572 | - if (cand->important && cand->iv->base_object == NULL_TREE) | ||
| 573 | - continue; | ||
| 574 | + if (cand->important) | ||
| 575 | + { | ||
| 576 | + if (originalp && cand->pos == IP_ORIGINAL) | ||
| 577 | + continue; | ||
| 578 | + if (!originalp && cand->iv->base_object == NULL_TREE) | ||
| 579 | + continue; | ||
| 580 | + } | ||
| 581 | |||
| 582 | if (iv_ca_cand_used_p (ivs, cand)) | ||
| 583 | continue; | ||
| 584 | @@ -5168,13 +5178,13 @@ | ||
| 585 | /* Finds an initial assignment of candidates to uses. */ | ||
| 586 | |||
| 587 | static struct iv_ca * | ||
| 588 | -get_initial_solution (struct ivopts_data *data) | ||
| 589 | +get_initial_solution (struct ivopts_data *data, bool originalp) | ||
| 590 | { | ||
| 591 | struct iv_ca *ivs = iv_ca_new (data); | ||
| 592 | unsigned i; | ||
| 593 | |||
| 594 | for (i = 0; i < n_iv_uses (data); i++) | ||
| 595 | - if (!try_add_cand_for (data, ivs, iv_use (data, i))) | ||
| 596 | + if (!try_add_cand_for (data, ivs, iv_use (data, i), originalp)) | ||
| 597 | { | ||
| 598 | iv_ca_free (&ivs); | ||
| 599 | return NULL; | ||
| 600 | @@ -5246,14 +5256,12 @@ | ||
| 601 | solution and remove the unused ivs while this improves the cost. */ | ||
| 602 | |||
| 603 | static struct iv_ca * | ||
| 604 | -find_optimal_iv_set (struct ivopts_data *data) | ||
| 605 | +find_optimal_iv_set_1 (struct ivopts_data *data, bool originalp) | ||
| 606 | { | ||
| 607 | - unsigned i; | ||
| 608 | struct iv_ca *set; | ||
| 609 | - struct iv_use *use; | ||
| 610 | |||
| 611 | /* Get the initial solution. */ | ||
| 612 | - set = get_initial_solution (data); | ||
| 613 | + set = get_initial_solution (data, originalp); | ||
| 614 | if (!set) | ||
| 615 | { | ||
| 616 | if (dump_file && (dump_flags & TDF_DETAILS)) | ||
| 617 | @@ -5276,11 +5284,46 @@ | ||
| 618 | } | ||
| 619 | } | ||
| 620 | |||
| 621 | + return set; | ||
| 622 | +} | ||
| 623 | + | ||
| 624 | +static struct iv_ca * | ||
| 625 | +find_optimal_iv_set (struct ivopts_data *data) | ||
| 626 | +{ | ||
| 627 | + unsigned i; | ||
| 628 | + struct iv_ca *set, *origset; | ||
| 629 | + struct iv_use *use; | ||
| 630 | + comp_cost cost, origcost; | ||
| 631 | + | ||
| 632 | + /* Determine the cost based on a strategy that starts with original IVs, | ||
| 633 | + and try again using a strategy that prefers candidates not based | ||
| 634 | + on any IVs. */ | ||
| 635 | + origset = find_optimal_iv_set_1 (data, true); | ||
| 636 | + set = find_optimal_iv_set_1 (data, false); | ||
| 637 | + | ||
| 638 | + if (!origset && !set) | ||
| 639 | + return NULL; | ||
| 640 | + | ||
| 641 | + origcost = origset ? iv_ca_cost (origset) : infinite_cost; | ||
| 642 | + cost = set ? iv_ca_cost (set) : infinite_cost; | ||
| 643 | + | ||
| 644 | if (dump_file && (dump_flags & TDF_DETAILS)) | ||
| 645 | { | ||
| 646 | - comp_cost cost = iv_ca_cost (set); | ||
| 647 | - fprintf (dump_file, "Final cost %d (complexity %d)\n\n", cost.cost, cost.complexity); | ||
| 648 | - } | ||
| 649 | + fprintf (dump_file, "Original cost %d (complexity %d)\n\n", | ||
| 650 | + origcost.cost, origcost.complexity); | ||
| 651 | + fprintf (dump_file, "Final cost %d (complexity %d)\n\n", | ||
| 652 | + cost.cost, cost.complexity); | ||
| 653 | + } | ||
| 654 | + | ||
| 655 | + /* Choose the one with the best cost. */ | ||
| 656 | + if (compare_costs (origcost, cost) <= 0) | ||
| 657 | + { | ||
| 658 | + if (set) | ||
| 659 | + iv_ca_free (&set); | ||
| 660 | + set = origset; | ||
| 661 | + } | ||
| 662 | + else if (origset) | ||
| 663 | + iv_ca_free (&origset); | ||
| 664 | |||
| 665 | for (i = 0; i < n_iv_uses (data); i++) | ||
| 666 | { | ||
| 667 | @@ -5768,6 +5811,25 @@ | ||
| 668 | VEC_free (iv_cand_p, heap, data->iv_candidates); | ||
| 669 | } | ||
| 670 | |||
| 671 | +/* Returns true if the loop body BODY includes any function calls. */ | ||
| 672 | + | ||
| 673 | +static bool | ||
| 674 | +loop_body_includes_call (basic_block *body, unsigned num_nodes) | ||
| 675 | +{ | ||
| 676 | + gimple_stmt_iterator gsi; | ||
| 677 | + unsigned i; | ||
| 678 | + | ||
| 679 | + for (i = 0; i < num_nodes; i++) | ||
| 680 | + for (gsi = gsi_start_bb (body[i]); !gsi_end_p (gsi); gsi_next (&gsi)) | ||
| 681 | + { | ||
| 682 | + gimple stmt = gsi_stmt (gsi); | ||
| 683 | + if (is_gimple_call (stmt) | ||
| 684 | + && !is_inexpensive_builtin (gimple_call_fndecl (stmt))) | ||
| 685 | + return true; | ||
| 686 | + } | ||
| 687 | + return false; | ||
| 688 | +} | ||
| 689 | + | ||
| 690 | /* Optimizes the LOOP. Returns true if anything changed. */ | ||
| 691 | |||
| 692 | static bool | ||
| 693 | @@ -5799,6 +5861,7 @@ | ||
| 694 | } | ||
| 695 | |||
| 696 | body = get_loop_body (loop); | ||
| 697 | + data->body_includes_call = loop_body_includes_call (body, loop->num_nodes); | ||
| 698 | renumber_gimple_stmt_uids_in_blocks (body, loop->num_nodes); | ||
| 699 | free (body); | ||
| 700 | |||
| 701 | |||
| 702 | === modified file 'gcc/tree.h' | ||
| 703 | --- old/gcc/tree.h 2010-04-02 18:54:46 +0000 | ||
| 704 | +++ new/gcc/tree.h 2010-08-02 13:51:23 +0000 | ||
| 705 | @@ -4962,6 +4962,8 @@ | ||
| 706 | extern bool merge_ranges (int *, tree *, tree *, int, tree, tree, int, | ||
| 707 | tree, tree); | ||
| 708 | extern void set_builtin_user_assembler_name (tree decl, const char *asmspec); | ||
| 709 | +extern bool is_simple_builtin (tree); | ||
| 710 | +extern bool is_inexpensive_builtin (tree); | ||
| 711 | |||
| 712 | /* In convert.c */ | ||
| 713 | extern tree strip_float_extensions (tree); | ||
| 714 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99313.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99313.patch deleted file mode 100644 index eadce6ec6..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99313.patch +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | 2010-07-15 Yao Qi <yao@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ 4.4: | ||
| 4 | |||
| 5 | 2010-02-25 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * tree.c (initializer_zerop): Handle STRING_CST. | ||
| 9 | |||
| 10 | 2010-07-15 Sandra Loosemore <sandra@codesourcery.com> | ||
| 11 | |||
| 12 | Backport from mainline: | ||
| 13 | |||
| 14 | === modified file 'gcc/tree.c' | ||
| 15 | --- old/gcc/tree.c 2010-04-01 15:18:07 +0000 | ||
| 16 | +++ new/gcc/tree.c 2010-08-02 16:32:37 +0000 | ||
| 17 | @@ -9335,6 +9335,19 @@ | ||
| 18 | return true; | ||
| 19 | } | ||
| 20 | |||
| 21 | + case STRING_CST: | ||
| 22 | + { | ||
| 23 | + int i; | ||
| 24 | + | ||
| 25 | + /* We need to loop through all elements to handle cases like | ||
| 26 | + "\0" and "\0foobar". */ | ||
| 27 | + for (i = 0; i < TREE_STRING_LENGTH (init); ++i) | ||
| 28 | + if (TREE_STRING_POINTER (init)[i] != '\0') | ||
| 29 | + return false; | ||
| 30 | + | ||
| 31 | + return true; | ||
| 32 | + } | ||
| 33 | + | ||
| 34 | default: | ||
| 35 | return false; | ||
| 36 | } | ||
| 37 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99314.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99314.patch deleted file mode 100644 index 216fcac72..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99314.patch +++ /dev/null | |||
| @@ -1,433 +0,0 @@ | |||
| 1 | 2010-07-16 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #7688 | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | 2010-07-12 Jie Zhang <jie@codesourcery.com> | ||
| 9 | * postreload.c (reg_symbol_ref[]): New. | ||
| 10 | (move2add_use_add2_insn): New. | ||
| 11 | (move2add_use_add3_insn): New. | ||
| 12 | (reload_cse_move2add): Handle SYMBOL + OFFSET case. | ||
| 13 | (move2add_note_store): Likewise. | ||
| 14 | |||
| 15 | 2010-07-15 Yao Qi <yao@codesourcery.com> | ||
| 16 | |||
| 17 | Merge from Sourcery G++ 4.4: | ||
| 18 | |||
| 19 | === modified file 'gcc/postreload.c' | ||
| 20 | --- old/gcc/postreload.c 2010-03-16 10:50:42 +0000 | ||
| 21 | +++ new/gcc/postreload.c 2010-08-02 16:55:34 +0000 | ||
| 22 | @@ -1160,17 +1160,19 @@ | ||
| 23 | information about register contents we have would be costly, so we | ||
| 24 | use move2add_last_label_luid to note where the label is and then | ||
| 25 | later disable any optimization that would cross it. | ||
| 26 | - reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if | ||
| 27 | - reg_set_luid[n] is greater than move2add_last_label_luid. */ | ||
| 28 | + reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n] | ||
| 29 | + are only valid if reg_set_luid[n] is greater than | ||
| 30 | + move2add_last_label_luid. */ | ||
| 31 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; | ||
| 32 | |||
| 33 | /* If reg_base_reg[n] is negative, register n has been set to | ||
| 34 | - reg_offset[n] in mode reg_mode[n] . | ||
| 35 | + reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n]. | ||
| 36 | If reg_base_reg[n] is non-negative, register n has been set to the | ||
| 37 | sum of reg_offset[n] and the value of register reg_base_reg[n] | ||
| 38 | before reg_set_luid[n], calculated in mode reg_mode[n] . */ | ||
| 39 | static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; | ||
| 40 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; | ||
| 41 | +static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER]; | ||
| 42 | static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; | ||
| 43 | |||
| 44 | /* move2add_luid is linearly increased while scanning the instructions | ||
| 45 | @@ -1190,6 +1192,151 @@ | ||
| 46 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \ | ||
| 47 | GET_MODE_BITSIZE (INMODE)))) | ||
| 48 | |||
| 49 | +/* This function is called with INSN that sets REG to (SYM + OFF), | ||
| 50 | + while REG is known to already have value (SYM + offset). | ||
| 51 | + This function tries to change INSN into an add instruction | ||
| 52 | + (set (REG) (plus (REG) (OFF - offset))) using the known value. | ||
| 53 | + It also updates the information about REG's known value. */ | ||
| 54 | + | ||
| 55 | +static void | ||
| 56 | +move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn) | ||
| 57 | +{ | ||
| 58 | + rtx pat = PATTERN (insn); | ||
| 59 | + rtx src = SET_SRC (pat); | ||
| 60 | + int regno = REGNO (reg); | ||
| 61 | + rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno], | ||
| 62 | + GET_MODE (reg)); | ||
| 63 | + bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | ||
| 64 | + | ||
| 65 | + /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | ||
| 66 | + use (set (reg) (reg)) instead. | ||
| 67 | + We don't delete this insn, nor do we convert it into a | ||
| 68 | + note, to avoid losing register notes or the return | ||
| 69 | + value flag. jump2 already knows how to get rid of | ||
| 70 | + no-op moves. */ | ||
| 71 | + if (new_src == const0_rtx) | ||
| 72 | + { | ||
| 73 | + /* If the constants are different, this is a | ||
| 74 | + truncation, that, if turned into (set (reg) | ||
| 75 | + (reg)), would be discarded. Maybe we should | ||
| 76 | + try a truncMN pattern? */ | ||
| 77 | + if (INTVAL (off) == reg_offset [regno]) | ||
| 78 | + validate_change (insn, &SET_SRC (pat), reg, 0); | ||
| 79 | + } | ||
| 80 | + else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed) | ||
| 81 | + && have_add2_insn (reg, new_src)) | ||
| 82 | + { | ||
| 83 | + rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); | ||
| 84 | + validate_change (insn, &SET_SRC (pat), tem, 0); | ||
| 85 | + } | ||
| 86 | + else if (sym == NULL_RTX && GET_MODE (reg) != BImode) | ||
| 87 | + { | ||
| 88 | + enum machine_mode narrow_mode; | ||
| 89 | + for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | ||
| 90 | + narrow_mode != VOIDmode | ||
| 91 | + && narrow_mode != GET_MODE (reg); | ||
| 92 | + narrow_mode = GET_MODE_WIDER_MODE (narrow_mode)) | ||
| 93 | + { | ||
| 94 | + if (have_insn_for (STRICT_LOW_PART, narrow_mode) | ||
| 95 | + && ((reg_offset[regno] | ||
| 96 | + & ~GET_MODE_MASK (narrow_mode)) | ||
| 97 | + == (INTVAL (off) | ||
| 98 | + & ~GET_MODE_MASK (narrow_mode)))) | ||
| 99 | + { | ||
| 100 | + rtx narrow_reg = gen_rtx_REG (narrow_mode, | ||
| 101 | + REGNO (reg)); | ||
| 102 | + rtx narrow_src = gen_int_mode (INTVAL (off), | ||
| 103 | + narrow_mode); | ||
| 104 | + rtx new_set = | ||
| 105 | + gen_rtx_SET (VOIDmode, | ||
| 106 | + gen_rtx_STRICT_LOW_PART (VOIDmode, | ||
| 107 | + narrow_reg), | ||
| 108 | + narrow_src); | ||
| 109 | + if (validate_change (insn, &PATTERN (insn), | ||
| 110 | + new_set, 0)) | ||
| 111 | + break; | ||
| 112 | + } | ||
| 113 | + } | ||
| 114 | + } | ||
| 115 | + reg_set_luid[regno] = move2add_luid; | ||
| 116 | + reg_base_reg[regno] = -1; | ||
| 117 | + reg_mode[regno] = GET_MODE (reg); | ||
| 118 | + reg_symbol_ref[regno] = sym; | ||
| 119 | + reg_offset[regno] = INTVAL (off); | ||
| 120 | +} | ||
| 121 | + | ||
| 122 | + | ||
| 123 | +/* This function is called with INSN that sets REG to (SYM + OFF), | ||
| 124 | + but REG doesn't have known value (SYM + offset). This function | ||
| 125 | + tries to find another register which is known to already have | ||
| 126 | + value (SYM + offset) and change INSN into an add instruction | ||
| 127 | + (set (REG) (plus (the found register) (OFF - offset))) if such | ||
| 128 | + a register is found. It also updates the information about | ||
| 129 | + REG's known value. */ | ||
| 130 | + | ||
| 131 | +static void | ||
| 132 | +move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn) | ||
| 133 | +{ | ||
| 134 | + rtx pat = PATTERN (insn); | ||
| 135 | + rtx src = SET_SRC (pat); | ||
| 136 | + int regno = REGNO (reg); | ||
| 137 | + int min_cost = INT_MAX; | ||
| 138 | + int min_regno; | ||
| 139 | + bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | ||
| 140 | + int i; | ||
| 141 | + | ||
| 142 | + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 143 | + if (reg_set_luid[i] > move2add_last_label_luid | ||
| 144 | + && reg_mode[i] == GET_MODE (reg) | ||
| 145 | + && reg_base_reg[i] < 0 | ||
| 146 | + && reg_symbol_ref[i] != NULL_RTX | ||
| 147 | + && rtx_equal_p (sym, reg_symbol_ref[i])) | ||
| 148 | + { | ||
| 149 | + rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i], | ||
| 150 | + GET_MODE (reg)); | ||
| 151 | + /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | ||
| 152 | + use (set (reg) (reg)) instead. | ||
| 153 | + We don't delete this insn, nor do we convert it into a | ||
| 154 | + note, to avoid losing register notes or the return | ||
| 155 | + value flag. jump2 already knows how to get rid of | ||
| 156 | + no-op moves. */ | ||
| 157 | + if (new_src == const0_rtx) | ||
| 158 | + { | ||
| 159 | + min_cost = 0; | ||
| 160 | + min_regno = i; | ||
| 161 | + break; | ||
| 162 | + } | ||
| 163 | + else | ||
| 164 | + { | ||
| 165 | + int cost = rtx_cost (new_src, PLUS, speed); | ||
| 166 | + if (cost < min_cost) | ||
| 167 | + { | ||
| 168 | + min_cost = cost; | ||
| 169 | + min_regno = i; | ||
| 170 | + } | ||
| 171 | + } | ||
| 172 | + } | ||
| 173 | + | ||
| 174 | + if (min_cost < rtx_cost (src, SET, speed)) | ||
| 175 | + { | ||
| 176 | + rtx tem; | ||
| 177 | + | ||
| 178 | + tem = gen_rtx_REG (GET_MODE (reg), min_regno); | ||
| 179 | + if (i != min_regno) | ||
| 180 | + { | ||
| 181 | + rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno], | ||
| 182 | + GET_MODE (reg)); | ||
| 183 | + tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); | ||
| 184 | + } | ||
| 185 | + validate_change (insn, &SET_SRC (pat), tem, 0); | ||
| 186 | + } | ||
| 187 | + reg_set_luid[regno] = move2add_luid; | ||
| 188 | + reg_base_reg[regno] = -1; | ||
| 189 | + reg_mode[regno] = GET_MODE (reg); | ||
| 190 | + reg_symbol_ref[regno] = sym; | ||
| 191 | + reg_offset[regno] = INTVAL (off); | ||
| 192 | +} | ||
| 193 | + | ||
| 194 | static void | ||
| 195 | reload_cse_move2add (rtx first) | ||
| 196 | { | ||
| 197 | @@ -1197,7 +1344,13 @@ | ||
| 198 | rtx insn; | ||
| 199 | |||
| 200 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | ||
| 201 | - reg_set_luid[i] = 0; | ||
| 202 | + { | ||
| 203 | + reg_set_luid[i] = 0; | ||
| 204 | + reg_offset[i] = 0; | ||
| 205 | + reg_base_reg[i] = 0; | ||
| 206 | + reg_symbol_ref[i] = NULL_RTX; | ||
| 207 | + reg_mode[i] = VOIDmode; | ||
| 208 | + } | ||
| 209 | |||
| 210 | move2add_last_label_luid = 0; | ||
| 211 | move2add_luid = 2; | ||
| 212 | @@ -1245,65 +1398,11 @@ | ||
| 213 | (set (STRICT_LOW_PART (REGX)) (CONST_INT B)) | ||
| 214 | */ | ||
| 215 | |||
| 216 | - if (CONST_INT_P (src) && reg_base_reg[regno] < 0) | ||
| 217 | + if (CONST_INT_P (src) | ||
| 218 | + && reg_base_reg[regno] < 0 | ||
| 219 | + && reg_symbol_ref[regno] == NULL_RTX) | ||
| 220 | { | ||
| 221 | - rtx new_src = gen_int_mode (INTVAL (src) - reg_offset[regno], | ||
| 222 | - GET_MODE (reg)); | ||
| 223 | - bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | ||
| 224 | - | ||
| 225 | - /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | ||
| 226 | - use (set (reg) (reg)) instead. | ||
| 227 | - We don't delete this insn, nor do we convert it into a | ||
| 228 | - note, to avoid losing register notes or the return | ||
| 229 | - value flag. jump2 already knows how to get rid of | ||
| 230 | - no-op moves. */ | ||
| 231 | - if (new_src == const0_rtx) | ||
| 232 | - { | ||
| 233 | - /* If the constants are different, this is a | ||
| 234 | - truncation, that, if turned into (set (reg) | ||
| 235 | - (reg)), would be discarded. Maybe we should | ||
| 236 | - try a truncMN pattern? */ | ||
| 237 | - if (INTVAL (src) == reg_offset [regno]) | ||
| 238 | - validate_change (insn, &SET_SRC (pat), reg, 0); | ||
| 239 | - } | ||
| 240 | - else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed) | ||
| 241 | - && have_add2_insn (reg, new_src)) | ||
| 242 | - { | ||
| 243 | - rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); | ||
| 244 | - validate_change (insn, &SET_SRC (pat), tem, 0); | ||
| 245 | - } | ||
| 246 | - else if (GET_MODE (reg) != BImode) | ||
| 247 | - { | ||
| 248 | - enum machine_mode narrow_mode; | ||
| 249 | - for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | ||
| 250 | - narrow_mode != VOIDmode | ||
| 251 | - && narrow_mode != GET_MODE (reg); | ||
| 252 | - narrow_mode = GET_MODE_WIDER_MODE (narrow_mode)) | ||
| 253 | - { | ||
| 254 | - if (have_insn_for (STRICT_LOW_PART, narrow_mode) | ||
| 255 | - && ((reg_offset[regno] | ||
| 256 | - & ~GET_MODE_MASK (narrow_mode)) | ||
| 257 | - == (INTVAL (src) | ||
| 258 | - & ~GET_MODE_MASK (narrow_mode)))) | ||
| 259 | - { | ||
| 260 | - rtx narrow_reg = gen_rtx_REG (narrow_mode, | ||
| 261 | - REGNO (reg)); | ||
| 262 | - rtx narrow_src = gen_int_mode (INTVAL (src), | ||
| 263 | - narrow_mode); | ||
| 264 | - rtx new_set = | ||
| 265 | - gen_rtx_SET (VOIDmode, | ||
| 266 | - gen_rtx_STRICT_LOW_PART (VOIDmode, | ||
| 267 | - narrow_reg), | ||
| 268 | - narrow_src); | ||
| 269 | - if (validate_change (insn, &PATTERN (insn), | ||
| 270 | - new_set, 0)) | ||
| 271 | - break; | ||
| 272 | - } | ||
| 273 | - } | ||
| 274 | - } | ||
| 275 | - reg_set_luid[regno] = move2add_luid; | ||
| 276 | - reg_mode[regno] = GET_MODE (reg); | ||
| 277 | - reg_offset[regno] = INTVAL (src); | ||
| 278 | + move2add_use_add2_insn (reg, NULL_RTX, src, insn); | ||
| 279 | continue; | ||
| 280 | } | ||
| 281 | |||
| 282 | @@ -1373,6 +1472,51 @@ | ||
| 283 | } | ||
| 284 | } | ||
| 285 | } | ||
| 286 | + | ||
| 287 | + /* Try to transform | ||
| 288 | + (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | ||
| 289 | + ... | ||
| 290 | + (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B)))) | ||
| 291 | + to | ||
| 292 | + (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) | ||
| 293 | + ... | ||
| 294 | + (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */ | ||
| 295 | + if ((GET_CODE (src) == SYMBOL_REF | ||
| 296 | + || (GET_CODE (src) == CONST | ||
| 297 | + && GET_CODE (XEXP (src, 0)) == PLUS | ||
| 298 | + && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF | ||
| 299 | + && CONST_INT_P (XEXP (XEXP (src, 0), 1)))) | ||
| 300 | + && dbg_cnt (cse2_move2add)) | ||
| 301 | + { | ||
| 302 | + rtx sym, off; | ||
| 303 | + | ||
| 304 | + if (GET_CODE (src) == SYMBOL_REF) | ||
| 305 | + { | ||
| 306 | + sym = src; | ||
| 307 | + off = const0_rtx; | ||
| 308 | + } | ||
| 309 | + else | ||
| 310 | + { | ||
| 311 | + sym = XEXP (XEXP (src, 0), 0); | ||
| 312 | + off = XEXP (XEXP (src, 0), 1); | ||
| 313 | + } | ||
| 314 | + | ||
| 315 | + /* If the reg already contains the value which is sum of | ||
| 316 | + sym and some constant value, we can use an add2 insn. */ | ||
| 317 | + if (reg_set_luid[regno] > move2add_last_label_luid | ||
| 318 | + && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]) | ||
| 319 | + && reg_base_reg[regno] < 0 | ||
| 320 | + && reg_symbol_ref[regno] != NULL_RTX | ||
| 321 | + && rtx_equal_p (sym, reg_symbol_ref[regno])) | ||
| 322 | + move2add_use_add2_insn (reg, sym, off, insn); | ||
| 323 | + | ||
| 324 | + /* Otherwise, we have to find a register whose value is sum | ||
| 325 | + of sym and some constant value. */ | ||
| 326 | + else | ||
| 327 | + move2add_use_add3_insn (reg, sym, off, insn); | ||
| 328 | + | ||
| 329 | + continue; | ||
| 330 | + } | ||
| 331 | } | ||
| 332 | |||
| 333 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | ||
| 334 | @@ -1386,7 +1530,7 @@ | ||
| 335 | reg_set_luid[regno] = 0; | ||
| 336 | } | ||
| 337 | } | ||
| 338 | - note_stores (PATTERN (insn), move2add_note_store, NULL); | ||
| 339 | + note_stores (PATTERN (insn), move2add_note_store, insn); | ||
| 340 | |||
| 341 | /* If INSN is a conditional branch, we try to extract an | ||
| 342 | implicit set out of it. */ | ||
| 343 | @@ -1408,7 +1552,7 @@ | ||
| 344 | { | ||
| 345 | rtx implicit_set = | ||
| 346 | gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1)); | ||
| 347 | - move2add_note_store (SET_DEST (implicit_set), implicit_set, 0); | ||
| 348 | + move2add_note_store (SET_DEST (implicit_set), implicit_set, insn); | ||
| 349 | } | ||
| 350 | } | ||
| 351 | |||
| 352 | @@ -1426,13 +1570,15 @@ | ||
| 353 | } | ||
| 354 | } | ||
| 355 | |||
| 356 | -/* SET is a SET or CLOBBER that sets DST. | ||
| 357 | +/* SET is a SET or CLOBBER that sets DST. DATA is the insn which | ||
| 358 | + contains SET. | ||
| 359 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. | ||
| 360 | Called from reload_cse_move2add via note_stores. */ | ||
| 361 | |||
| 362 | static void | ||
| 363 | -move2add_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) | ||
| 364 | +move2add_note_store (rtx dst, const_rtx set, void *data) | ||
| 365 | { | ||
| 366 | + rtx insn = (rtx) data; | ||
| 367 | unsigned int regno = 0; | ||
| 368 | unsigned int nregs = 0; | ||
| 369 | unsigned int i; | ||
| 370 | @@ -1466,6 +1612,38 @@ | ||
| 371 | nregs = hard_regno_nregs[regno][mode]; | ||
| 372 | |||
| 373 | if (SCALAR_INT_MODE_P (GET_MODE (dst)) | ||
| 374 | + && nregs == 1 && GET_CODE (set) == SET) | ||
| 375 | + { | ||
| 376 | + rtx note, sym = NULL_RTX; | ||
| 377 | + HOST_WIDE_INT off; | ||
| 378 | + | ||
| 379 | + note = find_reg_equal_equiv_note (insn); | ||
| 380 | + if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) | ||
| 381 | + { | ||
| 382 | + sym = XEXP (note, 0); | ||
| 383 | + off = 0; | ||
| 384 | + } | ||
| 385 | + else if (note && GET_CODE (XEXP (note, 0)) == CONST | ||
| 386 | + && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS | ||
| 387 | + && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF | ||
| 388 | + && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1))) | ||
| 389 | + { | ||
| 390 | + sym = XEXP (XEXP (XEXP (note, 0), 0), 0); | ||
| 391 | + off = INTVAL (XEXP (XEXP (XEXP (note, 0), 0), 1)); | ||
| 392 | + } | ||
| 393 | + | ||
| 394 | + if (sym != NULL_RTX) | ||
| 395 | + { | ||
| 396 | + reg_base_reg[regno] = -1; | ||
| 397 | + reg_symbol_ref[regno] = sym; | ||
| 398 | + reg_offset[regno] = off; | ||
| 399 | + reg_mode[regno] = mode; | ||
| 400 | + reg_set_luid[regno] = move2add_luid; | ||
| 401 | + return; | ||
| 402 | + } | ||
| 403 | + } | ||
| 404 | + | ||
| 405 | + if (SCALAR_INT_MODE_P (GET_MODE (dst)) | ||
| 406 | && nregs == 1 && GET_CODE (set) == SET | ||
| 407 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT | ||
| 408 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) | ||
| 409 | @@ -1525,6 +1703,7 @@ | ||
| 410 | case CONST_INT: | ||
| 411 | /* Start tracking the register as a constant. */ | ||
| 412 | reg_base_reg[regno] = -1; | ||
| 413 | + reg_symbol_ref[regno] = NULL_RTX; | ||
| 414 | reg_offset[regno] = INTVAL (SET_SRC (set)); | ||
| 415 | /* We assign the same luid to all registers set to constants. */ | ||
| 416 | reg_set_luid[regno] = move2add_last_label_luid + 1; | ||
| 417 | @@ -1545,6 +1724,7 @@ | ||
| 418 | if (reg_set_luid[base_regno] <= move2add_last_label_luid) | ||
| 419 | { | ||
| 420 | reg_base_reg[base_regno] = base_regno; | ||
| 421 | + reg_symbol_ref[base_regno] = NULL_RTX; | ||
| 422 | reg_offset[base_regno] = 0; | ||
| 423 | reg_set_luid[base_regno] = move2add_luid; | ||
| 424 | reg_mode[base_regno] = mode; | ||
| 425 | @@ -1558,6 +1738,7 @@ | ||
| 426 | /* Copy base information from our base register. */ | ||
| 427 | reg_set_luid[regno] = reg_set_luid[base_regno]; | ||
| 428 | reg_base_reg[regno] = reg_base_reg[base_regno]; | ||
| 429 | + reg_symbol_ref[regno] = reg_symbol_ref[base_regno]; | ||
| 430 | |||
| 431 | /* Compute the sum of the offsets or constants. */ | ||
| 432 | reg_offset[regno] = trunc_int_for_mode (offset | ||
| 433 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99315.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99315.patch deleted file mode 100644 index 3d5dd5f9a..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99315.patch +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | 2010-08-03 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | 2010-07-28 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 7 | * config/arm/arm.c (arm_pcs_default): Remove static. | ||
| 8 | * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_PCS or | ||
| 9 | __ARM_PCS_VFP to indicate soft/hard-float calling convention. | ||
| 10 | (arm_pcs_default): Declare. | ||
| 11 | |||
| 12 | 2010-07-16 Jie Zhang <jie@codesourcery.com> | ||
| 13 | |||
| 14 | Issue #7688 | ||
| 15 | |||
| 16 | === modified file 'gcc/config/arm/arm.c' | ||
| 17 | --- old/gcc/config/arm/arm.c 2010-08-02 13:42:24 +0000 | ||
| 18 | +++ new/gcc/config/arm/arm.c 2010-08-03 13:55:46 +0000 | ||
| 19 | @@ -704,7 +704,7 @@ | ||
| 20 | /* The maximum number of insns to be used when loading a constant. */ | ||
| 21 | static int arm_constant_limit = 3; | ||
| 22 | |||
| 23 | -static enum arm_pcs arm_pcs_default; | ||
| 24 | +enum arm_pcs arm_pcs_default; | ||
| 25 | |||
| 26 | /* For an explanation of these variables, see final_prescan_insn below. */ | ||
| 27 | int arm_ccfsm_state; | ||
| 28 | |||
| 29 | === modified file 'gcc/config/arm/arm.h' | ||
| 30 | --- old/gcc/config/arm/arm.h 2010-07-29 16:58:56 +0000 | ||
| 31 | +++ new/gcc/config/arm/arm.h 2010-08-03 10:40:56 +0000 | ||
| 32 | @@ -94,7 +94,13 @@ | ||
| 33 | if (arm_arch_iwmmxt) \ | ||
| 34 | builtin_define ("__IWMMXT__"); \ | ||
| 35 | if (TARGET_AAPCS_BASED) \ | ||
| 36 | - builtin_define ("__ARM_EABI__"); \ | ||
| 37 | + { \ | ||
| 38 | + if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ | ||
| 39 | + builtin_define ("__ARM_PCS_VFP"); \ | ||
| 40 | + else if (arm_pcs_default == ARM_PCS_AAPCS) \ | ||
| 41 | + builtin_define ("__ARM_PCS"); \ | ||
| 42 | + builtin_define ("__ARM_EABI__"); \ | ||
| 43 | + } \ | ||
| 44 | } while (0) | ||
| 45 | |||
| 46 | /* The various ARM cores. */ | ||
| 47 | @@ -1648,6 +1654,9 @@ | ||
| 48 | ARM_PCS_UNKNOWN | ||
| 49 | }; | ||
| 50 | |||
| 51 | +/* Default procedure calling standard of current compilation unit. */ | ||
| 52 | +extern enum arm_pcs arm_pcs_default; | ||
| 53 | + | ||
| 54 | /* A C type for declaring a variable that is used as the first argument of | ||
| 55 | `FUNCTION_ARG' and other related values. */ | ||
| 56 | typedef struct | ||
| 57 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99316.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99316.patch deleted file mode 100644 index c7f92b6fc..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99316.patch +++ /dev/null | |||
| @@ -1,76 +0,0 @@ | |||
| 1 | 2010-07-20 Yao Qi <yao@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ 4.4: | ||
| 4 | 2010-06-07 Kazu Hirata <kazu@codesourcery.com> | ||
| 5 | |||
| 6 | Issue #8535 | ||
| 7 | |||
| 8 | Backport from mainline: | ||
| 9 | gcc/ | ||
| 10 | 2010-06-07 Kazu Hirata <kazu@codesourcery.com> | ||
| 11 | PR rtl-optimization/44404 | ||
| 12 | * auto-inc-dec.c (find_inc): Use reg_overlap_mentioned_p instead | ||
| 13 | of count_occurrences to see if it's safe to modify mem_insn.insn. | ||
| 14 | |||
| 15 | gcc/testsuite/ | ||
| 16 | 2010-06-07 Kazu Hirata <kazu@codesourcery.com> | ||
| 17 | PR rtl-optimization/44404 | ||
| 18 | * gcc.dg/pr44404.c: New. | ||
| 19 | |||
| 20 | 2010-08-03 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 21 | |||
| 22 | Backport from mainline: | ||
| 23 | |||
| 24 | === modified file 'gcc/auto-inc-dec.c' | ||
| 25 | --- old/gcc/auto-inc-dec.c 2010-04-02 18:54:46 +0000 | ||
| 26 | +++ new/gcc/auto-inc-dec.c 2010-08-05 11:30:21 +0000 | ||
| 27 | @@ -1068,7 +1068,7 @@ | ||
| 28 | /* For the post_add to work, the result_reg of the inc must not be | ||
| 29 | used in the mem insn since this will become the new index | ||
| 30 | register. */ | ||
| 31 | - if (count_occurrences (PATTERN (mem_insn.insn), inc_insn.reg_res, 1) != 0) | ||
| 32 | + if (reg_overlap_mentioned_p (inc_insn.reg_res, PATTERN (mem_insn.insn))) | ||
| 33 | { | ||
| 34 | if (dump_file) | ||
| 35 | fprintf (dump_file, "base reg replacement failure.\n"); | ||
| 36 | |||
| 37 | === added file 'gcc/testsuite/gcc.dg/pr44404.c' | ||
| 38 | --- old/gcc/testsuite/gcc.dg/pr44404.c 1970-01-01 00:00:00 +0000 | ||
| 39 | +++ new/gcc/testsuite/gcc.dg/pr44404.c 2010-08-05 11:30:21 +0000 | ||
| 40 | @@ -0,0 +1,35 @@ | ||
| 41 | +/* PR rtl-optimization/44404 | ||
| 42 | + foo() used to be miscompiled on ARM due to a bug in auto-inc-dec.c, | ||
| 43 | + which resulted in "strb r1, [r1], #-36". */ | ||
| 44 | + | ||
| 45 | +/* { dg-do run } */ | ||
| 46 | +/* { dg-options "-O2 -fno-unroll-loops" } */ | ||
| 47 | + | ||
| 48 | +extern char *strcpy (char *, const char *); | ||
| 49 | +extern int strcmp (const char*, const char*); | ||
| 50 | +extern void abort (void); | ||
| 51 | + | ||
| 52 | +char buf[128]; | ||
| 53 | + | ||
| 54 | +void __attribute__((noinline)) | ||
| 55 | +bar (int a, const char *p) | ||
| 56 | +{ | ||
| 57 | + if (strcmp (p, "0123456789abcdefghijklmnopqrstuvwxyz") != 0) | ||
| 58 | + abort (); | ||
| 59 | +} | ||
| 60 | + | ||
| 61 | +void __attribute__((noinline)) | ||
| 62 | +foo (int a) | ||
| 63 | +{ | ||
| 64 | + if (a) | ||
| 65 | + bar (0, buf); | ||
| 66 | + strcpy (buf, "0123456789abcdefghijklmnopqrstuvwxyz"); | ||
| 67 | + bar (0, buf); | ||
| 68 | +} | ||
| 69 | + | ||
| 70 | +int | ||
| 71 | +main (void) | ||
| 72 | +{ | ||
| 73 | + foo (0); | ||
| 74 | + return 0; | ||
| 75 | +} | ||
| 76 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99318.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99318.patch deleted file mode 100644 index ad4943a0a..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99318.patch +++ /dev/null | |||
| @@ -1,118 +0,0 @@ | |||
| 1 | 2010-07-24 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #9079 | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | 2010-07-23 Jie Zhang <jie@codesourcery.com> | ||
| 9 | PR target/44290 | ||
| 10 | * attribs.c (decl_attributes): Insert "noinline" and "noclone" | ||
| 11 | if "naked". | ||
| 12 | * tree-sra.c (ipa_sra_preliminary_function_checks): Return | ||
| 13 | false if ! tree_versionable_function_p. | ||
| 14 | |||
| 15 | gcc/testsuite/ | ||
| 16 | 2010-07-23 Jie Zhang <jie@codesourcery.com> | ||
| 17 | PR target/44290 | ||
| 18 | * gcc.dg/pr44290-1.c: New test. | ||
| 19 | * gcc.dg/pr44290-2.c: New test. | ||
| 20 | |||
| 21 | 2010-07-22 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 22 | |||
| 23 | Backport from FSF GCC 4.5 branch to fix PR45015: | ||
| 24 | |||
| 25 | === modified file 'gcc/attribs.c' | ||
| 26 | --- old/gcc/attribs.c 2010-04-02 18:54:46 +0000 | ||
| 27 | +++ new/gcc/attribs.c 2010-08-05 11:39:36 +0000 | ||
| 28 | @@ -278,6 +278,19 @@ | ||
| 29 | TREE_VALUE (cur_attr) = chainon (opts, TREE_VALUE (cur_attr)); | ||
| 30 | } | ||
| 31 | |||
| 32 | + /* A "naked" function attribute implies "noinline" and "noclone" for | ||
| 33 | + those targets that support it. */ | ||
| 34 | + if (TREE_CODE (*node) == FUNCTION_DECL | ||
| 35 | + && lookup_attribute_spec (get_identifier ("naked")) | ||
| 36 | + && lookup_attribute ("naked", attributes) != NULL) | ||
| 37 | + { | ||
| 38 | + if (lookup_attribute ("noinline", attributes) == NULL) | ||
| 39 | + attributes = tree_cons (get_identifier ("noinline"), NULL, attributes); | ||
| 40 | + | ||
| 41 | + if (lookup_attribute ("noclone", attributes) == NULL) | ||
| 42 | + attributes = tree_cons (get_identifier ("noclone"), NULL, attributes); | ||
| 43 | + } | ||
| 44 | + | ||
| 45 | targetm.insert_attributes (*node, &attributes); | ||
| 46 | |||
| 47 | for (a = attributes; a; a = TREE_CHAIN (a)) | ||
| 48 | |||
| 49 | === added file 'gcc/testsuite/gcc.dg/pr44290-1.c' | ||
| 50 | --- old/gcc/testsuite/gcc.dg/pr44290-1.c 1970-01-01 00:00:00 +0000 | ||
| 51 | +++ new/gcc/testsuite/gcc.dg/pr44290-1.c 2010-08-05 11:39:36 +0000 | ||
| 52 | @@ -0,0 +1,18 @@ | ||
| 53 | +/* { dg-do compile { target arm*-*-* avr-*-* mcore-*-* rx-*-* spu-*-* } } */ | ||
| 54 | +/* { dg-options "-O2 -fdump-tree-optimized" } */ | ||
| 55 | + | ||
| 56 | +static void __attribute__((naked)) | ||
| 57 | +foo(void *from, void *to) | ||
| 58 | +{ | ||
| 59 | + asm volatile("dummy"::"r"(from), "r"(to)); | ||
| 60 | +} | ||
| 61 | + | ||
| 62 | +unsigned int fie[2]; | ||
| 63 | + | ||
| 64 | +void fum(void *to) | ||
| 65 | +{ | ||
| 66 | + foo(fie, to); | ||
| 67 | +} | ||
| 68 | + | ||
| 69 | +/* { dg-final { scan-tree-dump "foo \\\(void \\\* from, void \\\* to\\\)" "optimized" } } */ | ||
| 70 | +/* { dg-final { cleanup-tree-dump "optimized" } } */ | ||
| 71 | |||
| 72 | === added file 'gcc/testsuite/gcc.dg/pr44290-2.c' | ||
| 73 | --- old/gcc/testsuite/gcc.dg/pr44290-2.c 1970-01-01 00:00:00 +0000 | ||
| 74 | +++ new/gcc/testsuite/gcc.dg/pr44290-2.c 2010-08-05 11:39:36 +0000 | ||
| 75 | @@ -0,0 +1,24 @@ | ||
| 76 | +/* { dg-do compile { target arm*-*-* avr-*-* mcore-*-* rx-*-* spu-*-* } } */ | ||
| 77 | +/* { dg-options "-O2 -fdump-tree-optimized" } */ | ||
| 78 | + | ||
| 79 | +static unsigned long __attribute__((naked)) | ||
| 80 | +foo (unsigned long base) | ||
| 81 | +{ | ||
| 82 | + asm volatile ("dummy"); | ||
| 83 | +} | ||
| 84 | +unsigned long | ||
| 85 | +bar (void) | ||
| 86 | +{ | ||
| 87 | + static int start, set; | ||
| 88 | + | ||
| 89 | + if (!set) | ||
| 90 | + { | ||
| 91 | + set = 1; | ||
| 92 | + start = foo (0); | ||
| 93 | + } | ||
| 94 | + | ||
| 95 | + return foo (start); | ||
| 96 | +} | ||
| 97 | + | ||
| 98 | +/* { dg-final { scan-tree-dump "foo \\\(long unsigned int base\\\)" "optimized" } } */ | ||
| 99 | +/* { dg-final { cleanup-tree-dump "optimized" } } */ | ||
| 100 | |||
| 101 | === modified file 'gcc/tree-sra.c' | ||
| 102 | --- old/gcc/tree-sra.c 2010-03-17 12:02:35 +0000 | ||
| 103 | +++ new/gcc/tree-sra.c 2010-08-05 11:39:36 +0000 | ||
| 104 | @@ -4096,6 +4096,13 @@ | ||
| 105 | static bool | ||
| 106 | ipa_sra_preliminary_function_checks (struct cgraph_node *node) | ||
| 107 | { | ||
| 108 | + if (!tree_versionable_function_p (current_function_decl)) | ||
| 109 | + { | ||
| 110 | + if (dump_file) | ||
| 111 | + fprintf (dump_file, "Function isn't allowed to be versioned.\n"); | ||
| 112 | + return false; | ||
| 113 | + } | ||
| 114 | + | ||
| 115 | if (!cgraph_node_can_be_local_p (node)) | ||
| 116 | { | ||
| 117 | if (dump_file) | ||
| 118 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99319.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99319.patch deleted file mode 100644 index a649c9542..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99319.patch +++ /dev/null | |||
| @@ -1,197 +0,0 @@ | |||
| 1 | 2010-07-24 Sandra Loosemore <sandra@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-04-10 Wei Guozhi <carrot@google.com> | ||
| 6 | |||
| 7 | PR target/42601 | ||
| 8 | gcc/ | ||
| 9 | * config/arm/arm.c (arm_pic_static_addr): New function. | ||
| 10 | (legitimize_pic_address): Call arm_pic_static_addr when it detects | ||
| 11 | a static symbol. | ||
| 12 | (arm_output_addr_const_extra): Output expression for new pattern. | ||
| 13 | * config/arm/arm.md (UNSPEC_SYMBOL_OFFSET): New unspec symbol. | ||
| 14 | |||
| 15 | 2010-07-22 Sandra Loosemore <sandra@codesourcery.com> | ||
| 16 | |||
| 17 | PR tree-optimization/39839 | ||
| 18 | gcc/testsuite/ | ||
| 19 | * gcc.target/arm/pr39839.c: New test case. | ||
| 20 | |||
| 21 | 2010-07-24 Jie Zhang <jie@codesourcery.com> | ||
| 22 | |||
| 23 | Issue #9079 | ||
| 24 | |||
| 25 | === modified file 'gcc/config/arm/arm.c' | ||
| 26 | --- old/gcc/config/arm/arm.c 2010-08-03 13:55:46 +0000 | ||
| 27 | +++ new/gcc/config/arm/arm.c 2010-08-05 12:06:40 +0000 | ||
| 28 | @@ -225,6 +225,7 @@ | ||
| 29 | static void arm_asm_trampoline_template (FILE *); | ||
| 30 | static void arm_trampoline_init (rtx, tree, rtx); | ||
| 31 | static rtx arm_trampoline_adjust_address (rtx); | ||
| 32 | +static rtx arm_pic_static_addr (rtx orig, rtx reg); | ||
| 33 | |||
| 34 | |||
| 35 | /* Table of machine attributes. */ | ||
| 36 | @@ -4986,29 +4987,16 @@ | ||
| 37 | { | ||
| 38 | rtx pic_ref, address; | ||
| 39 | rtx insn; | ||
| 40 | - int subregs = 0; | ||
| 41 | - | ||
| 42 | - /* If this function doesn't have a pic register, create one now. */ | ||
| 43 | - require_pic_register (); | ||
| 44 | |||
| 45 | if (reg == 0) | ||
| 46 | { | ||
| 47 | gcc_assert (can_create_pseudo_p ()); | ||
| 48 | reg = gen_reg_rtx (Pmode); | ||
| 49 | - | ||
| 50 | - subregs = 1; | ||
| 51 | + address = gen_reg_rtx (Pmode); | ||
| 52 | } | ||
| 53 | - | ||
| 54 | - if (subregs) | ||
| 55 | - address = gen_reg_rtx (Pmode); | ||
| 56 | else | ||
| 57 | address = reg; | ||
| 58 | |||
| 59 | - if (TARGET_32BIT) | ||
| 60 | - emit_insn (gen_pic_load_addr_32bit (address, orig)); | ||
| 61 | - else /* TARGET_THUMB1 */ | ||
| 62 | - emit_insn (gen_pic_load_addr_thumb1 (address, orig)); | ||
| 63 | - | ||
| 64 | /* VxWorks does not impose a fixed gap between segments; the run-time | ||
| 65 | gap can be different from the object-file gap. We therefore can't | ||
| 66 | use GOTOFF unless we are absolutely sure that the symbol is in the | ||
| 67 | @@ -5020,16 +5008,23 @@ | ||
| 68 | SYMBOL_REF_LOCAL_P (orig))) | ||
| 69 | && NEED_GOT_RELOC | ||
| 70 | && !TARGET_VXWORKS_RTP) | ||
| 71 | - pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address); | ||
| 72 | + insn = arm_pic_static_addr (orig, reg); | ||
| 73 | else | ||
| 74 | { | ||
| 75 | + /* If this function doesn't have a pic register, create one now. */ | ||
| 76 | + require_pic_register (); | ||
| 77 | + | ||
| 78 | + if (TARGET_32BIT) | ||
| 79 | + emit_insn (gen_pic_load_addr_32bit (address, orig)); | ||
| 80 | + else /* TARGET_THUMB1 */ | ||
| 81 | + emit_insn (gen_pic_load_addr_thumb1 (address, orig)); | ||
| 82 | + | ||
| 83 | pic_ref = gen_const_mem (Pmode, | ||
| 84 | gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, | ||
| 85 | address)); | ||
| 86 | + insn = emit_move_insn (reg, pic_ref); | ||
| 87 | } | ||
| 88 | |||
| 89 | - insn = emit_move_insn (reg, pic_ref); | ||
| 90 | - | ||
| 91 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | ||
| 92 | by loop. */ | ||
| 93 | set_unique_reg_note (insn, REG_EQUAL, orig); | ||
| 94 | @@ -5236,6 +5231,43 @@ | ||
| 95 | emit_use (pic_reg); | ||
| 96 | } | ||
| 97 | |||
| 98 | +/* Generate code to load the address of a static var when flag_pic is set. */ | ||
| 99 | +static rtx | ||
| 100 | +arm_pic_static_addr (rtx orig, rtx reg) | ||
| 101 | +{ | ||
| 102 | + rtx l1, labelno, offset_rtx, insn; | ||
| 103 | + | ||
| 104 | + gcc_assert (flag_pic); | ||
| 105 | + | ||
| 106 | + /* We use an UNSPEC rather than a LABEL_REF because this label | ||
| 107 | + never appears in the code stream. */ | ||
| 108 | + labelno = GEN_INT (pic_labelno++); | ||
| 109 | + l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | ||
| 110 | + l1 = gen_rtx_CONST (VOIDmode, l1); | ||
| 111 | + | ||
| 112 | + /* On the ARM the PC register contains 'dot + 8' at the time of the | ||
| 113 | + addition, on the Thumb it is 'dot + 4'. */ | ||
| 114 | + offset_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4); | ||
| 115 | + offset_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, orig, offset_rtx), | ||
| 116 | + UNSPEC_SYMBOL_OFFSET); | ||
| 117 | + offset_rtx = gen_rtx_CONST (Pmode, offset_rtx); | ||
| 118 | + | ||
| 119 | + if (TARGET_32BIT) | ||
| 120 | + { | ||
| 121 | + emit_insn (gen_pic_load_addr_32bit (reg, offset_rtx)); | ||
| 122 | + if (TARGET_ARM) | ||
| 123 | + insn = emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); | ||
| 124 | + else | ||
| 125 | + insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); | ||
| 126 | + } | ||
| 127 | + else /* TARGET_THUMB1 */ | ||
| 128 | + { | ||
| 129 | + emit_insn (gen_pic_load_addr_thumb1 (reg, offset_rtx)); | ||
| 130 | + insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); | ||
| 131 | + } | ||
| 132 | + | ||
| 133 | + return insn; | ||
| 134 | +} | ||
| 135 | |||
| 136 | /* Return nonzero if X is valid as an ARM state addressing register. */ | ||
| 137 | static int | ||
| 138 | @@ -21461,6 +21493,16 @@ | ||
| 139 | fputc (')', fp); | ||
| 140 | return TRUE; | ||
| 141 | } | ||
| 142 | + else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SYMBOL_OFFSET) | ||
| 143 | + { | ||
| 144 | + output_addr_const (fp, XVECEXP (x, 0, 0)); | ||
| 145 | + if (GOT_PCREL) | ||
| 146 | + fputs ("+.", fp); | ||
| 147 | + fputs ("-(", fp); | ||
| 148 | + output_addr_const (fp, XVECEXP (x, 0, 1)); | ||
| 149 | + fputc (')', fp); | ||
| 150 | + return TRUE; | ||
| 151 | + } | ||
| 152 | else if (GET_CODE (x) == CONST_VECTOR) | ||
| 153 | return arm_emit_vector_const (fp, x); | ||
| 154 | |||
| 155 | |||
| 156 | === modified file 'gcc/config/arm/arm.md' | ||
| 157 | --- old/gcc/config/arm/arm.md 2010-07-30 14:17:05 +0000 | ||
| 158 | +++ new/gcc/config/arm/arm.md 2010-08-05 12:06:40 +0000 | ||
| 159 | @@ -101,6 +101,8 @@ | ||
| 160 | ; a given symbolic address. | ||
| 161 | (UNSPEC_THUMB1_CASESI 25) ; A Thumb1 compressed dispatch-table call. | ||
| 162 | (UNSPEC_RBIT 26) ; rbit operation. | ||
| 163 | + (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from | ||
| 164 | + ; another symbolic address. | ||
| 165 | ] | ||
| 166 | ) | ||
| 167 | |||
| 168 | |||
| 169 | === added file 'gcc/testsuite/gcc.target/arm/pr39839.c' | ||
| 170 | --- old/gcc/testsuite/gcc.target/arm/pr39839.c 1970-01-01 00:00:00 +0000 | ||
| 171 | +++ new/gcc/testsuite/gcc.target/arm/pr39839.c 2010-08-05 12:06:40 +0000 | ||
| 172 | @@ -0,0 +1,24 @@ | ||
| 173 | +/* { dg-options "-mthumb -Os -march=armv5te -mthumb-interwork -fpic" } */ | ||
| 174 | +/* { dg-require-effective-target arm_thumb1_ok } */ | ||
| 175 | +/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */ | ||
| 176 | + | ||
| 177 | +struct S | ||
| 178 | +{ | ||
| 179 | + int count; | ||
| 180 | + char *addr; | ||
| 181 | +}; | ||
| 182 | + | ||
| 183 | +void func(const char*, const char*, int, const char*); | ||
| 184 | + | ||
| 185 | +/* This function should not need to spill to the stack. */ | ||
| 186 | +void test(struct S *p) | ||
| 187 | +{ | ||
| 188 | + int off = p->count; | ||
| 189 | + while (p->count >= 0) | ||
| 190 | + { | ||
| 191 | + const char *s = "xyz"; | ||
| 192 | + if (*p->addr) s = "pqr"; | ||
| 193 | + func("abcde", p->addr + off, off, s); | ||
| 194 | + p->count--; | ||
| 195 | + } | ||
| 196 | +} | ||
| 197 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99320.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99320.patch deleted file mode 100644 index 669523218..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99320.patch +++ /dev/null | |||
| @@ -1,138 +0,0 @@ | |||
| 1 | 2010-08-05 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/testsuite/ | ||
| 4 | * gcc.dg/vect/vect-shift-2.c: Revert all previous changes. | ||
| 5 | * gcc.dg/vect/vect-shift-4.c: New file. | ||
| 6 | |||
| 7 | 2010-07-20 Yao Qi <yao@codesourcery.com> | ||
| 8 | |||
| 9 | Merge from Sourcery G++ 4.4: | ||
| 10 | 2009-06-16 Daniel Jacobowitz <dan@codesourcery.com> | ||
| 11 | |||
| 12 | Merge from Sourcery G++ 4.3: | ||
| 13 | 2008-12-03 Daniel Jacobowitz <dan@codesourcery.com> | ||
| 14 | |||
| 15 | gcc/testsuite/ | ||
| 16 | * gcc.dg/vect/vect-shift-2.c, gcc.dg/vect/vect-shift-3.c: New. | ||
| 17 | * lib/target-supports.exp (check_effective_target_vect_shift_char): New | ||
| 18 | function. | ||
| 19 | |||
| 20 | 2010-07-24 Sandra Loosemore <sandra@codesourcery.com> | ||
| 21 | |||
| 22 | Backport from mainline: | ||
| 23 | |||
| 24 | === added file 'gcc/testsuite/gcc.dg/vect/vect-shift-3.c' | ||
| 25 | --- old/gcc/testsuite/gcc.dg/vect/vect-shift-3.c 1970-01-01 00:00:00 +0000 | ||
| 26 | +++ new/gcc/testsuite/gcc.dg/vect/vect-shift-3.c 2010-08-05 14:13:43 +0000 | ||
| 27 | @@ -0,0 +1,37 @@ | ||
| 28 | +/* { dg-require-effective-target vect_shift } */ | ||
| 29 | +/* { dg-require-effective-target vect_int } */ | ||
| 30 | + | ||
| 31 | +#include "tree-vect.h" | ||
| 32 | + | ||
| 33 | +#define N 32 | ||
| 34 | + | ||
| 35 | +unsigned short dst[N] __attribute__((aligned(N))); | ||
| 36 | +unsigned short src[N] __attribute__((aligned(N))); | ||
| 37 | + | ||
| 38 | +__attribute__ ((noinline)) | ||
| 39 | +void array_shift(void) | ||
| 40 | +{ | ||
| 41 | + int i; | ||
| 42 | + for (i = 0; i < N; i++) | ||
| 43 | + dst[i] = src[i] >> 3; | ||
| 44 | +} | ||
| 45 | + | ||
| 46 | +int main() | ||
| 47 | +{ | ||
| 48 | + volatile int i; | ||
| 49 | + check_vect (); | ||
| 50 | + | ||
| 51 | + for (i = 0; i < N; i++) | ||
| 52 | + src[i] = i << 3; | ||
| 53 | + | ||
| 54 | + array_shift (); | ||
| 55 | + | ||
| 56 | + for (i = 0; i < N; i++) | ||
| 57 | + if (dst[i] != i) | ||
| 58 | + abort (); | ||
| 59 | + | ||
| 60 | + return 0; | ||
| 61 | +} | ||
| 62 | + | ||
| 63 | +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ | ||
| 64 | +/* { dg-final { cleanup-tree-dump "vect" } } */ | ||
| 65 | |||
| 66 | === added file 'gcc/testsuite/gcc.dg/vect/vect-shift-4.c' | ||
| 67 | --- old/gcc/testsuite/gcc.dg/vect/vect-shift-4.c 1970-01-01 00:00:00 +0000 | ||
| 68 | +++ new/gcc/testsuite/gcc.dg/vect/vect-shift-4.c 2010-08-05 14:13:43 +0000 | ||
| 69 | @@ -0,0 +1,37 @@ | ||
| 70 | +/* { dg-require-effective-target vect_shift_char } */ | ||
| 71 | +/* { dg-require-effective-target vect_int } */ | ||
| 72 | + | ||
| 73 | +#include "tree-vect.h" | ||
| 74 | + | ||
| 75 | +#define N 32 | ||
| 76 | + | ||
| 77 | +unsigned char dst[N] __attribute__((aligned(N))); | ||
| 78 | +unsigned char src[N] __attribute__((aligned(N))); | ||
| 79 | + | ||
| 80 | +__attribute__ ((noinline)) | ||
| 81 | +void array_shift(void) | ||
| 82 | +{ | ||
| 83 | + int i; | ||
| 84 | + for (i = 0; i < N; i++) | ||
| 85 | + dst[i] = src[i] >> 3; | ||
| 86 | +} | ||
| 87 | + | ||
| 88 | +int main() | ||
| 89 | +{ | ||
| 90 | + volatile int i; | ||
| 91 | + check_vect (); | ||
| 92 | + | ||
| 93 | + for (i = 0; i < N; i++) | ||
| 94 | + src[i] = i << 3; | ||
| 95 | + | ||
| 96 | + array_shift (); | ||
| 97 | + | ||
| 98 | + for (i = 0; i < N; i++) | ||
| 99 | + if (dst[i] != i) | ||
| 100 | + abort (); | ||
| 101 | + | ||
| 102 | + return 0; | ||
| 103 | +} | ||
| 104 | + | ||
| 105 | +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ | ||
| 106 | +/* { dg-final { cleanup-tree-dump "vect" } } */ | ||
| 107 | |||
| 108 | === modified file 'gcc/testsuite/lib/target-supports.exp' | ||
| 109 | --- old/gcc/testsuite/lib/target-supports.exp 2010-07-29 15:38:15 +0000 | ||
| 110 | +++ new/gcc/testsuite/lib/target-supports.exp 2010-08-05 14:13:43 +0000 | ||
| 111 | @@ -2001,6 +2001,26 @@ | ||
| 112 | return $et_vect_shift_saved | ||
| 113 | } | ||
| 114 | |||
| 115 | +# Return 1 if the target supports hardware vector shift operation for char. | ||
| 116 | + | ||
| 117 | +proc check_effective_target_vect_shift_char { } { | ||
| 118 | + global et_vect_shift_char_saved | ||
| 119 | + | ||
| 120 | + if [info exists et_vect_shift_char_saved] { | ||
| 121 | + verbose "check_effective_target_vect_shift_char: using cached result" 2 | ||
| 122 | + } else { | ||
| 123 | + set et_vect_shift_char_saved 0 | ||
| 124 | + if { ([istarget powerpc*-*-*] | ||
| 125 | + && ![istarget powerpc-*-linux*paired*]) | ||
| 126 | + || [check_effective_target_arm32] } { | ||
| 127 | + set et_vect_shift_char_saved 1 | ||
| 128 | + } | ||
| 129 | + } | ||
| 130 | + | ||
| 131 | + verbose "check_effective_target_vect_shift_char: returning $et_vect_shift_char_saved" 2 | ||
| 132 | + return $et_vect_shift_char_saved | ||
| 133 | +} | ||
| 134 | + | ||
| 135 | # Return 1 if the target supports hardware vectors of long, 0 otherwise. | ||
| 136 | # | ||
| 137 | # This can change for different subtargets so do not cache the result. | ||
| 138 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99321.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99321.patch deleted file mode 100644 index b122ab10f..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99321.patch +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ 4.4: | ||
| 4 | |||
| 5 | 2007-07-05 Mark Shinwell <shinwell@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * config/arm/arm.h (BRANCH_COST): Set to 1 when optimizing for size | ||
| 9 | on Thumb-2. | ||
| 10 | |||
| 11 | 2010-08-05 Andrew Stubbs <ams@codesourcery.com> | ||
| 12 | |||
| 13 | gcc/testsuite/ | ||
| 14 | |||
| 15 | === modified file 'gcc/config/arm/arm.h' | ||
| 16 | --- old/gcc/config/arm/arm.h 2010-08-03 10:40:56 +0000 | ||
| 17 | +++ new/gcc/config/arm/arm.h 2010-08-05 14:29:52 +0000 | ||
| 18 | @@ -2210,7 +2210,8 @@ | ||
| 19 | /* Try to generate sequences that don't involve branches, we can then use | ||
| 20 | conditional instructions */ | ||
| 21 | #define BRANCH_COST(speed_p, predictable_p) \ | ||
| 22 | - (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0)) | ||
| 23 | + (TARGET_32BIT ? (TARGET_THUMB2 && optimize_size ? 1 : 4) \ | ||
| 24 | + : (optimize > 0 ? 2 : 0)) | ||
| 25 | |||
| 26 | /* Position Independent Code. */ | ||
| 27 | /* We decide which register to use based on the compilation options and | ||
| 28 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99322.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99322.patch deleted file mode 100644 index 6962c1cec..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99322.patch +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | 2007-06-06 Joseph Myers <joseph@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * config/arm/arm.h (VALID_IWMMXT_REG_MODE): Allow SImode. | ||
| 5 | (ARM_LEGITIMIZE_RELOAD_ADDRESS): Reduce range allowed for SImode | ||
| 6 | offsets with iWMMXt. | ||
| 7 | * config/arm/arm.c (arm_hard_regno_mode_ok): Update for change to | ||
| 8 | VALID_IWMMXT_REG_MODE. | ||
| 9 | |||
| 10 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 11 | |||
| 12 | Merge from Sourcery G++ 4.4: | ||
| 13 | |||
| 14 | 2007-07-05 Mark Shinwell <shinwell@codesourcery.com> | ||
| 15 | |||
| 16 | gcc/ | ||
| 17 | |||
| 18 | === modified file 'gcc/config/arm/arm.c' | ||
| 19 | --- old/gcc/config/arm/arm.c 2010-08-05 12:06:40 +0000 | ||
| 20 | +++ new/gcc/config/arm/arm.c 2010-08-05 14:33:31 +0000 | ||
| 21 | @@ -16538,7 +16538,7 @@ | ||
| 22 | return mode == SImode; | ||
| 23 | |||
| 24 | if (IS_IWMMXT_REGNUM (regno)) | ||
| 25 | - return VALID_IWMMXT_REG_MODE (mode); | ||
| 26 | + return VALID_IWMMXT_REG_MODE (mode) && mode != SImode; | ||
| 27 | } | ||
| 28 | |||
| 29 | /* We allow almost any value to be stored in the general registers. | ||
| 30 | |||
| 31 | === modified file 'gcc/config/arm/arm.h' | ||
| 32 | --- old/gcc/config/arm/arm.h 2010-08-05 14:29:52 +0000 | ||
| 33 | +++ new/gcc/config/arm/arm.h 2010-08-05 14:33:31 +0000 | ||
| 34 | @@ -1077,7 +1077,7 @@ | ||
| 35 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | ||
| 36 | |||
| 37 | #define VALID_IWMMXT_REG_MODE(MODE) \ | ||
| 38 | - (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) | ||
| 39 | + (arm_vector_mode_supported_p (MODE) || (MODE) == DImode || (MODE) == SImode) | ||
| 40 | |||
| 41 | /* Modes valid for Neon D registers. */ | ||
| 42 | #define VALID_NEON_DREG_MODE(MODE) \ | ||
| 43 | @@ -1364,6 +1364,9 @@ | ||
| 44 | else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \ | ||
| 45 | /* Need to be careful, -256 is not a valid offset. */ \ | ||
| 46 | low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ | ||
| 47 | + else if (TARGET_REALLY_IWMMXT && MODE == SImode) \ | ||
| 48 | + /* Need to be careful, -1024 is not a valid offset. */ \ | ||
| 49 | + low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ | ||
| 50 | else if (MODE == SImode \ | ||
| 51 | || (MODE == SFmode && TARGET_SOFT_FLOAT) \ | ||
| 52 | || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ | ||
| 53 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99323.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99323.patch deleted file mode 100644 index 38b6fa3f0..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99323.patch +++ /dev/null | |||
| @@ -1,688 +0,0 @@ | |||
| 1 | Vladimir Prus <vladimir@codesourcery.com> | ||
| 2 | Julian Brown <julian@codesourcery.com> | ||
| 3 | |||
| 4 | gcc/ | ||
| 5 | * config/arm/arm.c (arm_override_options): Warn if mlow-irq-latency is | ||
| 6 | specified in Thumb mode. | ||
| 7 | (load_multiple_sequence): Return 0 if low irq latency is requested. | ||
| 8 | (store_multiple_sequence): Likewise. | ||
| 9 | (arm_gen_load_multiple): Load registers one-by-one if low irq latency | ||
| 10 | is requested. | ||
| 11 | (arm_gen_store_multiple): Likewise. | ||
| 12 | (vfp_output_fldmd): When low_irq_latency is non zero, pop each | ||
| 13 | register separately. | ||
| 14 | (vfp_emit_fstmd): When low_irq_latency is non zero, save each register | ||
| 15 | separately. | ||
| 16 | (arm_get_vfp_saved_size): Adjust saved register size calculation for | ||
| 17 | the above changes. | ||
| 18 | (print_pop_reg_by_ldr): New. | ||
| 19 | (arm_output_epilogue): Use print_pop_reg_by_ldr when low irq latency | ||
| 20 | is requested. | ||
| 21 | (emit_multi_reg_push): Push registers separately if low irq latency | ||
| 22 | is requested. | ||
| 23 | * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Set __low_irq_latency__. | ||
| 24 | (low_irq_latency): Define. | ||
| 25 | (USE_RETURN_INSN): Don't use return insn when low irq latency is | ||
| 26 | requested. | ||
| 27 | * config/arm/lib1funcs.asm (do_pop, do_push): Define as variadic | ||
| 28 | macros. When __low_irq_latency__ is defined, push and pop registers | ||
| 29 | individually. | ||
| 30 | (div0): Use correct punctuation. | ||
| 31 | * config/arm/ieee754-df.S: Adjust syntax of using do_push. | ||
| 32 | * config/arm/ieee754-sf.S: Likewise. | ||
| 33 | * config/arm/bpabi.S: Likewise. | ||
| 34 | * config/arm/arm.opt (mlow-irq-latency): New option. | ||
| 35 | * config/arm/predicates.md (load_multiple_operation): Return false is | ||
| 36 | low irq latency is requested. | ||
| 37 | (store_multiple_operation): Likewise. | ||
| 38 | * config/arm/arm.md (movmemqi): Don't use it if low irq latency is | ||
| 39 | requested. | ||
| 40 | * doc/invoke.texi (-mlow-irq-latency): Add documentation. | ||
| 41 | |||
| 42 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 43 | |||
| 44 | Merge from Sourcery G++ 4.4: | ||
| 45 | |||
| 46 | 2007-06-06 Joseph Myers <joseph@codesourcery.com> | ||
| 47 | |||
| 48 | gcc/ | ||
| 49 | |||
| 50 | === modified file 'gcc/config/arm/arm.c' | ||
| 51 | --- old/gcc/config/arm/arm.c 2010-08-05 14:33:31 +0000 | ||
| 52 | +++ new/gcc/config/arm/arm.c 2010-08-05 15:20:54 +0000 | ||
| 53 | @@ -1884,6 +1884,13 @@ | ||
| 54 | |||
| 55 | /* Register global variables with the garbage collector. */ | ||
| 56 | arm_add_gc_roots (); | ||
| 57 | + | ||
| 58 | + if (low_irq_latency && TARGET_THUMB) | ||
| 59 | + { | ||
| 60 | + warning (0, | ||
| 61 | + "-mlow-irq-latency has no effect when compiling for Thumb"); | ||
| 62 | + low_irq_latency = 0; | ||
| 63 | + } | ||
| 64 | } | ||
| 65 | |||
| 66 | static void | ||
| 67 | @@ -9053,6 +9060,9 @@ | ||
| 68 | int base_reg = -1; | ||
| 69 | int i; | ||
| 70 | |||
| 71 | + if (low_irq_latency) | ||
| 72 | + return 0; | ||
| 73 | + | ||
| 74 | /* Can only handle 2, 3, or 4 insns at present, | ||
| 75 | though could be easily extended if required. */ | ||
| 76 | gcc_assert (nops >= 2 && nops <= 4); | ||
| 77 | @@ -9282,6 +9292,9 @@ | ||
| 78 | int base_reg = -1; | ||
| 79 | int i; | ||
| 80 | |||
| 81 | + if (low_irq_latency) | ||
| 82 | + return 0; | ||
| 83 | + | ||
| 84 | /* Can only handle 2, 3, or 4 insns at present, though could be easily | ||
| 85 | extended if required. */ | ||
| 86 | gcc_assert (nops >= 2 && nops <= 4); | ||
| 87 | @@ -9489,7 +9502,7 @@ | ||
| 88 | |||
| 89 | As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | ||
| 90 | for counts of 3 or 4 regs. */ | ||
| 91 | - if (arm_tune_xscale && count <= 2 && ! optimize_size) | ||
| 92 | + if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size)) | ||
| 93 | { | ||
| 94 | rtx seq; | ||
| 95 | |||
| 96 | @@ -9552,7 +9565,7 @@ | ||
| 97 | |||
| 98 | /* See arm_gen_load_multiple for discussion of | ||
| 99 | the pros/cons of ldm/stm usage for XScale. */ | ||
| 100 | - if (arm_tune_xscale && count <= 2 && ! optimize_size) | ||
| 101 | + if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size)) | ||
| 102 | { | ||
| 103 | rtx seq; | ||
| 104 | |||
| 105 | @@ -11795,6 +11808,21 @@ | ||
| 106 | vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count) | ||
| 107 | { | ||
| 108 | int i; | ||
| 109 | + int offset; | ||
| 110 | + | ||
| 111 | + if (low_irq_latency) | ||
| 112 | + { | ||
| 113 | + /* Output a sequence of FLDD instructions. */ | ||
| 114 | + offset = 0; | ||
| 115 | + for (i = reg; i < reg + count; ++i, offset += 8) | ||
| 116 | + { | ||
| 117 | + fputc ('\t', stream); | ||
| 118 | + asm_fprintf (stream, "fldd\td%d, [%r,#%d]\n", i, base, offset); | ||
| 119 | + } | ||
| 120 | + asm_fprintf (stream, "\tadd\tsp, sp, #%d\n", count * 8); | ||
| 121 | + return; | ||
| 122 | + } | ||
| 123 | + | ||
| 124 | |||
| 125 | /* Workaround ARM10 VFPr1 bug. */ | ||
| 126 | if (count == 2 && !arm_arch6) | ||
| 127 | @@ -11865,6 +11893,56 @@ | ||
| 128 | rtx tmp, reg; | ||
| 129 | int i; | ||
| 130 | |||
| 131 | + if (low_irq_latency) | ||
| 132 | + { | ||
| 133 | + int saved_size; | ||
| 134 | + rtx sp_insn; | ||
| 135 | + | ||
| 136 | + if (!count) | ||
| 137 | + return 0; | ||
| 138 | + | ||
| 139 | + saved_size = count * GET_MODE_SIZE (DFmode); | ||
| 140 | + | ||
| 141 | + /* Since fstd does not have postdecrement addressing mode, | ||
| 142 | + we first decrement stack pointer and then use base+offset | ||
| 143 | + stores for VFP registers. The ARM EABI unwind information | ||
| 144 | + can't easily describe base+offset loads, so we attach | ||
| 145 | + a note for the effects of the whole block in the first insn, | ||
| 146 | + and avoid marking the subsequent instructions | ||
| 147 | + with RTX_FRAME_RELATED_P. */ | ||
| 148 | + sp_insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | ||
| 149 | + GEN_INT (-saved_size)); | ||
| 150 | + sp_insn = emit_insn (sp_insn); | ||
| 151 | + RTX_FRAME_RELATED_P (sp_insn) = 1; | ||
| 152 | + | ||
| 153 | + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); | ||
| 154 | + XVECEXP (dwarf, 0, 0) = | ||
| 155 | + gen_rtx_SET (VOIDmode, stack_pointer_rtx, | ||
| 156 | + plus_constant (stack_pointer_rtx, -saved_size)); | ||
| 157 | + | ||
| 158 | + /* push double VFP registers to stack */ | ||
| 159 | + for (i = 0; i < count; ++i ) | ||
| 160 | + { | ||
| 161 | + rtx reg; | ||
| 162 | + rtx mem; | ||
| 163 | + rtx addr; | ||
| 164 | + rtx insn; | ||
| 165 | + reg = gen_rtx_REG (DFmode, base_reg + 2*i); | ||
| 166 | + addr = (i == 0) ? stack_pointer_rtx | ||
| 167 | + : gen_rtx_PLUS (SImode, stack_pointer_rtx, | ||
| 168 | + GEN_INT (i * GET_MODE_SIZE (DFmode))); | ||
| 169 | + mem = gen_frame_mem (DFmode, addr); | ||
| 170 | + insn = emit_move_insn (mem, reg); | ||
| 171 | + XVECEXP (dwarf, 0, i+1) = | ||
| 172 | + gen_rtx_SET (VOIDmode, mem, reg); | ||
| 173 | + } | ||
| 174 | + | ||
| 175 | + REG_NOTES (sp_insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | ||
| 176 | + REG_NOTES (sp_insn)); | ||
| 177 | + | ||
| 178 | + return saved_size; | ||
| 179 | + } | ||
| 180 | + | ||
| 181 | /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two | ||
| 182 | register pairs are stored by a store multiple insn. We avoid this | ||
| 183 | by pushing an extra pair. */ | ||
| 184 | @@ -13307,7 +13385,7 @@ | ||
| 185 | if (count > 0) | ||
| 186 | { | ||
| 187 | /* Workaround ARM10 VFPr1 bug. */ | ||
| 188 | - if (count == 2 && !arm_arch6) | ||
| 189 | + if (count == 2 && !arm_arch6 && !low_irq_latency) | ||
| 190 | count++; | ||
| 191 | saved += count * 8; | ||
| 192 | } | ||
| 193 | @@ -13645,6 +13723,41 @@ | ||
| 194 | |||
| 195 | } | ||
| 196 | |||
| 197 | +/* Generate to STREAM a code sequence that pops registers identified | ||
| 198 | + in REGS_MASK from SP. SP is incremented as the result. | ||
| 199 | +*/ | ||
| 200 | +static void | ||
| 201 | +print_pop_reg_by_ldr (FILE *stream, int regs_mask, int rfe) | ||
| 202 | +{ | ||
| 203 | + int reg; | ||
| 204 | + | ||
| 205 | + gcc_assert (! (regs_mask & (1 << SP_REGNUM))); | ||
| 206 | + | ||
| 207 | + for (reg = 0; reg < PC_REGNUM; ++reg) | ||
| 208 | + if (regs_mask & (1 << reg)) | ||
| 209 | + asm_fprintf (stream, "\tldr\t%r, [%r], #4\n", | ||
| 210 | + reg, SP_REGNUM); | ||
| 211 | + | ||
| 212 | + if (regs_mask & (1 << PC_REGNUM)) | ||
| 213 | + { | ||
| 214 | + if (rfe) | ||
| 215 | + /* When returning from exception, we need to | ||
| 216 | + copy SPSR to CPSR. There are two ways to do | ||
| 217 | + that: the ldm instruction with "^" suffix, | ||
| 218 | + and movs instruction. The latter would | ||
| 219 | + require that we load from stack to some | ||
| 220 | + scratch register, and then move to PC. | ||
| 221 | + Therefore, we'd need extra instruction and | ||
| 222 | + have to make sure we actually have a spare | ||
| 223 | + register. Using ldm with a single register | ||
| 224 | + is simler. */ | ||
| 225 | + asm_fprintf (stream, "\tldm\tsp!, {pc}^\n"); | ||
| 226 | + else | ||
| 227 | + asm_fprintf (stream, "\tldr\t%r, [%r], #4\n", | ||
| 228 | + PC_REGNUM, SP_REGNUM); | ||
| 229 | + } | ||
| 230 | +} | ||
| 231 | + | ||
| 232 | const char * | ||
| 233 | arm_output_epilogue (rtx sibling) | ||
| 234 | { | ||
| 235 | @@ -14018,22 +14131,19 @@ | ||
| 236 | to load use the LDR instruction - it is faster. For Thumb-2 | ||
| 237 | always use pop and the assembler will pick the best instruction.*/ | ||
| 238 | if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM) | ||
| 239 | - && !IS_INTERRUPT(func_type)) | ||
| 240 | + && !IS_INTERRUPT (func_type)) | ||
| 241 | { | ||
| 242 | asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); | ||
| 243 | } | ||
| 244 | else if (saved_regs_mask) | ||
| 245 | { | ||
| 246 | - if (saved_regs_mask & (1 << SP_REGNUM)) | ||
| 247 | - /* Note - write back to the stack register is not enabled | ||
| 248 | - (i.e. "ldmfd sp!..."). We know that the stack pointer is | ||
| 249 | - in the list of registers and if we add writeback the | ||
| 250 | - instruction becomes UNPREDICTABLE. */ | ||
| 251 | - print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, | ||
| 252 | - rfe); | ||
| 253 | - else if (TARGET_ARM) | ||
| 254 | - print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask, | ||
| 255 | - rfe); | ||
| 256 | + gcc_assert ( ! (saved_regs_mask & (1 << SP_REGNUM))); | ||
| 257 | + if (TARGET_ARM) | ||
| 258 | + if (low_irq_latency) | ||
| 259 | + print_pop_reg_by_ldr (f, saved_regs_mask, rfe); | ||
| 260 | + else | ||
| 261 | + print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask, | ||
| 262 | + rfe); | ||
| 263 | else | ||
| 264 | print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0); | ||
| 265 | } | ||
| 266 | @@ -14154,6 +14264,32 @@ | ||
| 267 | |||
| 268 | gcc_assert (num_regs && num_regs <= 16); | ||
| 269 | |||
| 270 | + if (low_irq_latency) | ||
| 271 | + { | ||
| 272 | + rtx insn = 0; | ||
| 273 | + | ||
| 274 | + /* Emit a series of ldr instructions rather rather than a single ldm. */ | ||
| 275 | + /* TODO: Use ldrd where possible. */ | ||
| 276 | + gcc_assert (! (mask & (1 << SP_REGNUM))); | ||
| 277 | + | ||
| 278 | + for (i = LAST_ARM_REGNUM; i >= 0; --i) | ||
| 279 | + { | ||
| 280 | + if (mask & (1 << i)) | ||
| 281 | + | ||
| 282 | + { | ||
| 283 | + rtx reg, where, mem; | ||
| 284 | + | ||
| 285 | + reg = gen_rtx_REG (SImode, i); | ||
| 286 | + where = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); | ||
| 287 | + mem = gen_rtx_MEM (SImode, where); | ||
| 288 | + insn = emit_move_insn (mem, reg); | ||
| 289 | + RTX_FRAME_RELATED_P (insn) = 1; | ||
| 290 | + } | ||
| 291 | + } | ||
| 292 | + | ||
| 293 | + return insn; | ||
| 294 | + } | ||
| 295 | + | ||
| 296 | /* We don't record the PC in the dwarf frame information. */ | ||
| 297 | num_dwarf_regs = num_regs; | ||
| 298 | if (mask & (1 << PC_REGNUM)) | ||
| 299 | |||
| 300 | === modified file 'gcc/config/arm/arm.h' | ||
| 301 | --- old/gcc/config/arm/arm.h 2010-08-05 14:33:31 +0000 | ||
| 302 | +++ new/gcc/config/arm/arm.h 2010-08-05 15:20:54 +0000 | ||
| 303 | @@ -101,6 +101,8 @@ | ||
| 304 | builtin_define ("__ARM_PCS"); \ | ||
| 305 | builtin_define ("__ARM_EABI__"); \ | ||
| 306 | } \ | ||
| 307 | + if (low_irq_latency) \ | ||
| 308 | + builtin_define ("__low_irq_latency__"); \ | ||
| 309 | } while (0) | ||
| 310 | |||
| 311 | /* The various ARM cores. */ | ||
| 312 | @@ -449,6 +451,10 @@ | ||
| 313 | /* Nonzero if chip supports integer division instruction. */ | ||
| 314 | extern int arm_arch_hwdiv; | ||
| 315 | |||
| 316 | +/* Nonzero if we should minimize interrupt latency of the | ||
| 317 | + generated code. */ | ||
| 318 | +extern int low_irq_latency; | ||
| 319 | + | ||
| 320 | #ifndef TARGET_DEFAULT | ||
| 321 | #define TARGET_DEFAULT (MASK_APCS_FRAME) | ||
| 322 | #endif | ||
| 323 | @@ -1823,9 +1829,10 @@ | ||
| 324 | /* Determine if the epilogue should be output as RTL. | ||
| 325 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | ||
| 326 | /* This is disabled for Thumb-2 because it will confuse the | ||
| 327 | - conditional insn counter. */ | ||
| 328 | + conditional insn counter. | ||
| 329 | + Do not use a return insn if we're avoiding ldm/stm instructions. */ | ||
| 330 | #define USE_RETURN_INSN(ISCOND) \ | ||
| 331 | - (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0) | ||
| 332 | + ((TARGET_ARM && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0) | ||
| 333 | |||
| 334 | /* Definitions for register eliminations. | ||
| 335 | |||
| 336 | |||
| 337 | === modified file 'gcc/config/arm/arm.md' | ||
| 338 | --- old/gcc/config/arm/arm.md 2010-08-05 12:06:40 +0000 | ||
| 339 | +++ new/gcc/config/arm/arm.md 2010-08-05 15:20:54 +0000 | ||
| 340 | @@ -6587,7 +6587,7 @@ | ||
| 341 | (match_operand:BLK 1 "general_operand" "") | ||
| 342 | (match_operand:SI 2 "const_int_operand" "") | ||
| 343 | (match_operand:SI 3 "const_int_operand" "")] | ||
| 344 | - "TARGET_EITHER" | ||
| 345 | + "TARGET_EITHER && !low_irq_latency" | ||
| 346 | " | ||
| 347 | if (TARGET_32BIT) | ||
| 348 | { | ||
| 349 | |||
| 350 | === modified file 'gcc/config/arm/arm.opt' | ||
| 351 | --- old/gcc/config/arm/arm.opt 2009-06-18 11:24:10 +0000 | ||
| 352 | +++ new/gcc/config/arm/arm.opt 2010-08-05 15:20:54 +0000 | ||
| 353 | @@ -161,6 +161,10 @@ | ||
| 354 | Target Report Mask(NEON_VECTORIZE_QUAD) | ||
| 355 | Use Neon quad-word (rather than double-word) registers for vectorization | ||
| 356 | |||
| 357 | +mlow-irq-latency | ||
| 358 | +Target Report Var(low_irq_latency) | ||
| 359 | +Try to reduce interrupt latency of the generated code | ||
| 360 | + | ||
| 361 | mword-relocations | ||
| 362 | Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) | ||
| 363 | Only generate absolute relocations on word sized values. | ||
| 364 | |||
| 365 | === modified file 'gcc/config/arm/bpabi.S' | ||
| 366 | --- old/gcc/config/arm/bpabi.S 2009-12-17 15:37:23 +0000 | ||
| 367 | +++ new/gcc/config/arm/bpabi.S 2010-08-05 15:20:54 +0000 | ||
| 368 | @@ -116,16 +116,17 @@ | ||
| 369 | test_div_by_zero signed | ||
| 370 | |||
| 371 | sub sp, sp, #8 | ||
| 372 | -#if defined(__thumb2__) | ||
| 373 | +/* Low latency and Thumb-2 do_push implementations can't push sp directly. */ | ||
| 374 | +#if defined(__thumb2__) || defined(__irq_low_latency__) | ||
| 375 | mov ip, sp | ||
| 376 | - push {ip, lr} | ||
| 377 | + do_push (ip, lr) | ||
| 378 | #else | ||
| 379 | - do_push {sp, lr} | ||
| 380 | + stmfd sp!, {sp, lr} | ||
| 381 | #endif | ||
| 382 | bl SYM(__gnu_ldivmod_helper) __PLT__ | ||
| 383 | ldr lr, [sp, #4] | ||
| 384 | add sp, sp, #8 | ||
| 385 | - do_pop {r2, r3} | ||
| 386 | + do_pop (r2, r3) | ||
| 387 | RET | ||
| 388 | |||
| 389 | #endif /* L_aeabi_ldivmod */ | ||
| 390 | @@ -136,16 +137,17 @@ | ||
| 391 | test_div_by_zero unsigned | ||
| 392 | |||
| 393 | sub sp, sp, #8 | ||
| 394 | -#if defined(__thumb2__) | ||
| 395 | +/* Low latency and Thumb-2 do_push implementations can't push sp directly. */ | ||
| 396 | +#if defined(__thumb2__) || defined(__irq_low_latency__) | ||
| 397 | mov ip, sp | ||
| 398 | - push {ip, lr} | ||
| 399 | + do_push (ip, lr) | ||
| 400 | #else | ||
| 401 | - do_push {sp, lr} | ||
| 402 | + stmfd sp!, {sp, lr} | ||
| 403 | #endif | ||
| 404 | bl SYM(__gnu_uldivmod_helper) __PLT__ | ||
| 405 | ldr lr, [sp, #4] | ||
| 406 | add sp, sp, #8 | ||
| 407 | - do_pop {r2, r3} | ||
| 408 | + do_pop (r2, r3) | ||
| 409 | RET | ||
| 410 | |||
| 411 | #endif /* L_aeabi_divmod */ | ||
| 412 | |||
| 413 | === modified file 'gcc/config/arm/ieee754-df.S' | ||
| 414 | --- old/gcc/config/arm/ieee754-df.S 2009-06-05 12:52:36 +0000 | ||
| 415 | +++ new/gcc/config/arm/ieee754-df.S 2010-08-05 15:20:54 +0000 | ||
| 416 | @@ -83,7 +83,7 @@ | ||
| 417 | ARM_FUNC_START adddf3 | ||
| 418 | ARM_FUNC_ALIAS aeabi_dadd adddf3 | ||
| 419 | |||
| 420 | -1: do_push {r4, r5, lr} | ||
| 421 | +1: do_push (r4, r5, lr) | ||
| 422 | |||
| 423 | @ Look for zeroes, equal values, INF, or NAN. | ||
| 424 | shift1 lsl, r4, xh, #1 | ||
| 425 | @@ -427,7 +427,7 @@ | ||
| 426 | do_it eq, t | ||
| 427 | moveq r1, #0 | ||
| 428 | RETc(eq) | ||
| 429 | - do_push {r4, r5, lr} | ||
| 430 | + do_push (r4, r5, lr) | ||
| 431 | mov r4, #0x400 @ initial exponent | ||
| 432 | add r4, r4, #(52-1 - 1) | ||
| 433 | mov r5, #0 @ sign bit is 0 | ||
| 434 | @@ -447,7 +447,7 @@ | ||
| 435 | do_it eq, t | ||
| 436 | moveq r1, #0 | ||
| 437 | RETc(eq) | ||
| 438 | - do_push {r4, r5, lr} | ||
| 439 | + do_push (r4, r5, lr) | ||
| 440 | mov r4, #0x400 @ initial exponent | ||
| 441 | add r4, r4, #(52-1 - 1) | ||
| 442 | ands r5, r0, #0x80000000 @ sign bit in r5 | ||
| 443 | @@ -481,7 +481,7 @@ | ||
| 444 | RETc(eq) @ we are done already. | ||
| 445 | |||
| 446 | @ value was denormalized. We can normalize it now. | ||
| 447 | - do_push {r4, r5, lr} | ||
| 448 | + do_push (r4, r5, lr) | ||
| 449 | mov r4, #0x380 @ setup corresponding exponent | ||
| 450 | and r5, xh, #0x80000000 @ move sign bit in r5 | ||
| 451 | bic xh, xh, #0x80000000 | ||
| 452 | @@ -508,9 +508,9 @@ | ||
| 453 | @ compatibility. | ||
| 454 | adr ip, LSYM(f0_ret) | ||
| 455 | @ Push pc as well so that RETLDM works correctly. | ||
| 456 | - do_push {r4, r5, ip, lr, pc} | ||
| 457 | + do_push (r4, r5, ip, lr, pc) | ||
| 458 | #else | ||
| 459 | - do_push {r4, r5, lr} | ||
| 460 | + do_push (r4, r5, lr) | ||
| 461 | #endif | ||
| 462 | |||
| 463 | mov r5, #0 | ||
| 464 | @@ -534,9 +534,9 @@ | ||
| 465 | @ compatibility. | ||
| 466 | adr ip, LSYM(f0_ret) | ||
| 467 | @ Push pc as well so that RETLDM works correctly. | ||
| 468 | - do_push {r4, r5, ip, lr, pc} | ||
| 469 | + do_push (r4, r5, ip, lr, pc) | ||
| 470 | #else | ||
| 471 | - do_push {r4, r5, lr} | ||
| 472 | + do_push (r4, r5, lr) | ||
| 473 | #endif | ||
| 474 | |||
| 475 | ands r5, ah, #0x80000000 @ sign bit in r5 | ||
| 476 | @@ -585,7 +585,7 @@ | ||
| 477 | @ Legacy code expects the result to be returned in f0. Copy it | ||
| 478 | @ there as well. | ||
| 479 | LSYM(f0_ret): | ||
| 480 | - do_push {r0, r1} | ||
| 481 | + do_push (r0, r1) | ||
| 482 | ldfd f0, [sp], #8 | ||
| 483 | RETLDM | ||
| 484 | |||
| 485 | @@ -602,7 +602,7 @@ | ||
| 486 | |||
| 487 | ARM_FUNC_START muldf3 | ||
| 488 | ARM_FUNC_ALIAS aeabi_dmul muldf3 | ||
| 489 | - do_push {r4, r5, r6, lr} | ||
| 490 | + do_push (r4, r5, r6, lr) | ||
| 491 | |||
| 492 | @ Mask out exponents, trap any zero/denormal/INF/NAN. | ||
| 493 | mov ip, #0xff | ||
| 494 | @@ -910,7 +910,7 @@ | ||
| 495 | ARM_FUNC_START divdf3 | ||
| 496 | ARM_FUNC_ALIAS aeabi_ddiv divdf3 | ||
| 497 | |||
| 498 | - do_push {r4, r5, r6, lr} | ||
| 499 | + do_push (r4, r5, r6, lr) | ||
| 500 | |||
| 501 | @ Mask out exponents, trap any zero/denormal/INF/NAN. | ||
| 502 | mov ip, #0xff | ||
| 503 | @@ -1195,7 +1195,7 @@ | ||
| 504 | |||
| 505 | @ The status-returning routines are required to preserve all | ||
| 506 | @ registers except ip, lr, and cpsr. | ||
| 507 | -6: do_push {r0, lr} | ||
| 508 | +6: do_push (r0, lr) | ||
| 509 | ARM_CALL cmpdf2 | ||
| 510 | @ Set the Z flag correctly, and the C flag unconditionally. | ||
| 511 | cmp r0, #0 | ||
| 512 | |||
| 513 | === modified file 'gcc/config/arm/ieee754-sf.S' | ||
| 514 | --- old/gcc/config/arm/ieee754-sf.S 2009-06-05 12:52:36 +0000 | ||
| 515 | +++ new/gcc/config/arm/ieee754-sf.S 2010-08-05 15:20:54 +0000 | ||
| 516 | @@ -481,7 +481,7 @@ | ||
| 517 | and r3, ip, #0x80000000 | ||
| 518 | |||
| 519 | @ Well, no way to make it shorter without the umull instruction. | ||
| 520 | - do_push {r3, r4, r5} | ||
| 521 | + do_push (r3, r4, r5) | ||
| 522 | mov r4, r0, lsr #16 | ||
| 523 | mov r5, r1, lsr #16 | ||
| 524 | bic r0, r0, r4, lsl #16 | ||
| 525 | @@ -492,7 +492,7 @@ | ||
| 526 | mla r0, r4, r1, r0 | ||
| 527 | adds r3, r3, r0, lsl #16 | ||
| 528 | adc r1, ip, r0, lsr #16 | ||
| 529 | - do_pop {r0, r4, r5} | ||
| 530 | + do_pop (r0, r4, r5) | ||
| 531 | |||
| 532 | #else | ||
| 533 | |||
| 534 | @@ -882,7 +882,7 @@ | ||
| 535 | |||
| 536 | @ The status-returning routines are required to preserve all | ||
| 537 | @ registers except ip, lr, and cpsr. | ||
| 538 | -6: do_push {r0, r1, r2, r3, lr} | ||
| 539 | +6: do_push (r0, r1, r2, r3, lr) | ||
| 540 | ARM_CALL cmpsf2 | ||
| 541 | @ Set the Z flag correctly, and the C flag unconditionally. | ||
| 542 | cmp r0, #0 | ||
| 543 | |||
| 544 | === modified file 'gcc/config/arm/lib1funcs.asm' | ||
| 545 | --- old/gcc/config/arm/lib1funcs.asm 2010-04-02 18:54:46 +0000 | ||
| 546 | +++ new/gcc/config/arm/lib1funcs.asm 2010-08-05 15:20:54 +0000 | ||
| 547 | @@ -254,8 +254,8 @@ | ||
| 548 | .macro shift1 op, arg0, arg1, arg2 | ||
| 549 | \op \arg0, \arg1, \arg2 | ||
| 550 | .endm | ||
| 551 | -#define do_push push | ||
| 552 | -#define do_pop pop | ||
| 553 | +#define do_push(...) push {__VA_ARGS__} | ||
| 554 | +#define do_pop(...) pop {__VA_ARGS__} | ||
| 555 | #define COND(op1, op2, cond) op1 ## op2 ## cond | ||
| 556 | /* Perform an arithmetic operation with a variable shift operand. This | ||
| 557 | requires two instructions and a scratch register on Thumb-2. */ | ||
| 558 | @@ -269,8 +269,42 @@ | ||
| 559 | .macro shift1 op, arg0, arg1, arg2 | ||
| 560 | mov \arg0, \arg1, \op \arg2 | ||
| 561 | .endm | ||
| 562 | -#define do_push stmfd sp!, | ||
| 563 | -#define do_pop ldmfd sp!, | ||
| 564 | +#if defined(__low_irq_latency__) | ||
| 565 | +#define do_push(...) \ | ||
| 566 | + _buildN1(do_push, _buildC1(__VA_ARGS__))( __VA_ARGS__) | ||
| 567 | +#define _buildN1(BASE, X) _buildN2(BASE, X) | ||
| 568 | +#define _buildN2(BASE, X) BASE##X | ||
| 569 | +#define _buildC1(...) _buildC2(__VA_ARGS__,9,8,7,6,5,4,3,2,1) | ||
| 570 | +#define _buildC2(a1,a2,a3,a4,a5,a6,a7,a8,a9,c,...) c | ||
| 571 | + | ||
| 572 | +#define do_push1(r1) str r1, [sp, #-4]! | ||
| 573 | +#define do_push2(r1, r2) str r2, [sp, #-4]! ; str r1, [sp, #-4]! | ||
| 574 | +#define do_push3(r1, r2, r3) str r3, [sp, #-4]! ; str r2, [sp, #-4]!; str r1, [sp, #-4]! | ||
| 575 | +#define do_push4(r1, r2, r3, r4) \ | ||
| 576 | + do_push3 (r2, r3, r4);\ | ||
| 577 | + do_push1 (r1) | ||
| 578 | +#define do_push5(r1, r2, r3, r4, r5) \ | ||
| 579 | + do_push4 (r2, r3, r4, r5);\ | ||
| 580 | + do_push1 (r1) | ||
| 581 | + | ||
| 582 | +#define do_pop(...) \ | ||
| 583 | +_buildN1(do_pop, _buildC1(__VA_ARGS__))( __VA_ARGS__) | ||
| 584 | + | ||
| 585 | +#define do_pop1(r1) ldr r1, [sp], #4 | ||
| 586 | +#define do_pop2(r1, r2) ldr r1, [sp], #4 ; ldr r2, [sp], #4 | ||
| 587 | +#define do_pop3(r1, r2, r3) ldr r1, [sp], #4 ; str r2, [sp], #4; str r3, [sp], #4 | ||
| 588 | +#define do_pop4(r1, r2, r3, r4) \ | ||
| 589 | + do_pop1 (r1);\ | ||
| 590 | + do_pup3 (r2, r3, r4) | ||
| 591 | +#define do_pop5(r1, r2, r3, r4, r5) \ | ||
| 592 | + do_pop1 (r1);\ | ||
| 593 | + do_pop4 (r2, r3, r4, r5) | ||
| 594 | +#else | ||
| 595 | +#define do_push(...) stmfd sp!, { __VA_ARGS__} | ||
| 596 | +#define do_pop(...) ldmfd sp!, {__VA_ARGS__} | ||
| 597 | +#endif | ||
| 598 | + | ||
| 599 | + | ||
| 600 | #define COND(op1, op2, cond) op1 ## cond ## op2 | ||
| 601 | .macro shiftop name, dest, src1, src2, shiftop, shiftreg, tmp | ||
| 602 | \name \dest, \src1, \src2, \shiftop \shiftreg | ||
| 603 | @@ -1260,7 +1294,7 @@ | ||
| 604 | ARM_FUNC_START div0 | ||
| 605 | #endif | ||
| 606 | |||
| 607 | - do_push {r1, lr} | ||
| 608 | + do_push (r1, lr) | ||
| 609 | mov r0, #SIGFPE | ||
| 610 | bl SYM(raise) __PLT__ | ||
| 611 | RETLDM r1 | ||
| 612 | @@ -1277,7 +1311,7 @@ | ||
| 613 | #if defined __ARM_EABI__ && defined __linux__ | ||
| 614 | @ EABI GNU/Linux call to cacheflush syscall. | ||
| 615 | ARM_FUNC_START clear_cache | ||
| 616 | - do_push {r7} | ||
| 617 | + do_push (r7) | ||
| 618 | #if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__) | ||
| 619 | movw r7, #2 | ||
| 620 | movt r7, #0xf | ||
| 621 | @@ -1287,7 +1321,7 @@ | ||
| 622 | #endif | ||
| 623 | mov r2, #0 | ||
| 624 | swi 0 | ||
| 625 | - do_pop {r7} | ||
| 626 | + do_pop (r7) | ||
| 627 | RET | ||
| 628 | FUNC_END clear_cache | ||
| 629 | #else | ||
| 630 | @@ -1490,7 +1524,7 @@ | ||
| 631 | push {r4, lr} | ||
| 632 | # else | ||
| 633 | ARM_FUNC_START clzdi2 | ||
| 634 | - do_push {r4, lr} | ||
| 635 | + do_push (r4, lr) | ||
| 636 | # endif | ||
| 637 | cmp xxh, #0 | ||
| 638 | bne 1f | ||
| 639 | |||
| 640 | === modified file 'gcc/config/arm/predicates.md' | ||
| 641 | --- old/gcc/config/arm/predicates.md 2010-07-30 14:17:05 +0000 | ||
| 642 | +++ new/gcc/config/arm/predicates.md 2010-08-05 15:20:54 +0000 | ||
| 643 | @@ -328,6 +328,9 @@ | ||
| 644 | HOST_WIDE_INT i = 1, base = 0; | ||
| 645 | rtx elt; | ||
| 646 | |||
| 647 | + if (low_irq_latency) | ||
| 648 | + return false; | ||
| 649 | + | ||
| 650 | if (count <= 1 | ||
| 651 | || GET_CODE (XVECEXP (op, 0, 0)) != SET) | ||
| 652 | return false; | ||
| 653 | @@ -385,6 +388,9 @@ | ||
| 654 | HOST_WIDE_INT i = 1, base = 0; | ||
| 655 | rtx elt; | ||
| 656 | |||
| 657 | + if (low_irq_latency) | ||
| 658 | + return false; | ||
| 659 | + | ||
| 660 | if (count <= 1 | ||
| 661 | || GET_CODE (XVECEXP (op, 0, 0)) != SET) | ||
| 662 | return false; | ||
| 663 | |||
| 664 | === modified file 'gcc/doc/invoke.texi' | ||
| 665 | --- old/gcc/doc/invoke.texi 2010-07-29 17:03:20 +0000 | ||
| 666 | +++ new/gcc/doc/invoke.texi 2010-08-05 15:20:54 +0000 | ||
| 667 | @@ -469,6 +469,7 @@ | ||
| 668 | -mtpcs-frame -mtpcs-leaf-frame @gol | ||
| 669 | -mcaller-super-interworking -mcallee-super-interworking @gol | ||
| 670 | -mtp=@var{name} @gol | ||
| 671 | +-mlow-irq-latency @gol | ||
| 672 | -mword-relocations @gol | ||
| 673 | -mfix-cortex-m3-ldrd} | ||
| 674 | |||
| 675 | @@ -9489,6 +9490,12 @@ | ||
| 676 | @code{,}, @code{!}, @code{|}, and @code{*} as needed. | ||
| 677 | |||
| 678 | |||
| 679 | +@item -mlow-irq-latency | ||
| 680 | +@opindex mlow-irq-latency | ||
| 681 | +Avoid instructions with high interrupt latency when generating | ||
| 682 | +code. This can increase code size and reduce performance. | ||
| 683 | +The option is off by default. | ||
| 684 | + | ||
| 685 | @end table | ||
| 686 | |||
| 687 | The conditional text @code{X} in a %@{@code{S}:@code{X}@} or similar | ||
| 688 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99324.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99324.patch deleted file mode 100644 index 40b368862..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99324.patch +++ /dev/null | |||
| @@ -1,109 +0,0 @@ | |||
| 1 | Julian Brown <julian@codesourcery.com> | ||
| 2 | Mark Shinwell <mark@codesourcery.com> | ||
| 3 | |||
| 4 | gcc/ | ||
| 5 | * regrename.c (addresses.h): Move include of addresses.h after | ||
| 6 | include of flags.h. | ||
| 7 | * recog.c: Likewise. | ||
| 8 | * regcprop.c: Likewise. | ||
| 9 | * config/arm/arm.h (CLASS_LIKELY_SPILLED_P): Check against | ||
| 10 | LO_REGS only for Thumb-1. | ||
| 11 | (MODE_BASE_REG_CLASS): Restrict base registers to those which can | ||
| 12 | be used in short instructions when optimising for size on Thumb-2. | ||
| 13 | |||
| 14 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 15 | |||
| 16 | Merge from Sourcery G++ 4.4: | ||
| 17 | |||
| 18 | Vladimir Prus <vladimir@codesourcery.com> | ||
| 19 | Julian Brown <julian@codesourcery.com> | ||
| 20 | |||
| 21 | |||
| 22 | === modified file 'gcc/config/arm/arm.h' | ||
| 23 | --- old/gcc/config/arm/arm.h 2010-08-05 15:20:54 +0000 | ||
| 24 | +++ new/gcc/config/arm/arm.h 2010-08-05 15:28:47 +0000 | ||
| 25 | @@ -1254,11 +1254,14 @@ | ||
| 26 | || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ | ||
| 27 | : 0) | ||
| 28 | |||
| 29 | -/* We need to define this for LO_REGS on thumb. Otherwise we can end up | ||
| 30 | - using r0-r4 for function arguments, r7 for the stack frame and don't | ||
| 31 | - have enough left over to do doubleword arithmetic. */ | ||
| 32 | +/* We need to define this for LO_REGS on Thumb-1. Otherwise we can end up | ||
| 33 | + using r0-r4 for function arguments, r7 for the stack frame and don't have | ||
| 34 | + enough left over to do doubleword arithmetic. For Thumb-2 all the | ||
| 35 | + potentially problematic instructions accept high registers so this is not | ||
| 36 | + necessary. Care needs to be taken to avoid adding new Thumb-2 patterns | ||
| 37 | + that require many low registers. */ | ||
| 38 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | ||
| 39 | - ((TARGET_THUMB && (CLASS) == LO_REGS) \ | ||
| 40 | + ((TARGET_THUMB1 && (CLASS) == LO_REGS) \ | ||
| 41 | || (CLASS) == CC_REG) | ||
| 42 | |||
| 43 | /* The class value for index registers, and the one for base regs. */ | ||
| 44 | @@ -1269,7 +1272,7 @@ | ||
| 45 | when addressing quantities in QI or HI mode; if we don't know the | ||
| 46 | mode, then we must be conservative. */ | ||
| 47 | #define MODE_BASE_REG_CLASS(MODE) \ | ||
| 48 | - (TARGET_32BIT ? CORE_REGS : \ | ||
| 49 | + (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \ | ||
| 50 | (((MODE) == SImode) ? BASE_REGS : LO_REGS)) | ||
| 51 | |||
| 52 | /* For Thumb we can not support SP+reg addressing, so we return LO_REGS | ||
| 53 | |||
| 54 | === modified file 'gcc/recog.c' | ||
| 55 | --- old/gcc/recog.c 2010-04-02 18:54:46 +0000 | ||
| 56 | +++ new/gcc/recog.c 2010-08-05 15:28:47 +0000 | ||
| 57 | @@ -31,10 +31,10 @@ | ||
| 58 | #include "hard-reg-set.h" | ||
| 59 | #include "recog.h" | ||
| 60 | #include "regs.h" | ||
| 61 | -#include "addresses.h" | ||
| 62 | #include "expr.h" | ||
| 63 | #include "function.h" | ||
| 64 | #include "flags.h" | ||
| 65 | +#include "addresses.h" | ||
| 66 | #include "real.h" | ||
| 67 | #include "toplev.h" | ||
| 68 | #include "basic-block.h" | ||
| 69 | |||
| 70 | === modified file 'gcc/regcprop.c' | ||
| 71 | --- old/gcc/regcprop.c 2010-02-26 11:01:28 +0000 | ||
| 72 | +++ new/gcc/regcprop.c 2010-08-05 15:28:47 +0000 | ||
| 73 | @@ -26,7 +26,6 @@ | ||
| 74 | #include "tm_p.h" | ||
| 75 | #include "insn-config.h" | ||
| 76 | #include "regs.h" | ||
| 77 | -#include "addresses.h" | ||
| 78 | #include "hard-reg-set.h" | ||
| 79 | #include "basic-block.h" | ||
| 80 | #include "reload.h" | ||
| 81 | @@ -34,6 +33,7 @@ | ||
| 82 | #include "function.h" | ||
| 83 | #include "recog.h" | ||
| 84 | #include "flags.h" | ||
| 85 | +#include "addresses.h" | ||
| 86 | #include "toplev.h" | ||
| 87 | #include "obstack.h" | ||
| 88 | #include "timevar.h" | ||
| 89 | |||
| 90 | === modified file 'gcc/regrename.c' | ||
| 91 | --- old/gcc/regrename.c 2010-04-02 18:54:46 +0000 | ||
| 92 | +++ new/gcc/regrename.c 2010-08-05 15:28:47 +0000 | ||
| 93 | @@ -26,7 +26,6 @@ | ||
| 94 | #include "tm_p.h" | ||
| 95 | #include "insn-config.h" | ||
| 96 | #include "regs.h" | ||
| 97 | -#include "addresses.h" | ||
| 98 | #include "hard-reg-set.h" | ||
| 99 | #include "basic-block.h" | ||
| 100 | #include "reload.h" | ||
| 101 | @@ -34,6 +33,7 @@ | ||
| 102 | #include "function.h" | ||
| 103 | #include "recog.h" | ||
| 104 | #include "flags.h" | ||
| 105 | +#include "addresses.h" | ||
| 106 | #include "toplev.h" | ||
| 107 | #include "obstack.h" | ||
| 108 | #include "timevar.h" | ||
| 109 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99325.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99325.patch deleted file mode 100644 index 0dbb3dbf7..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99325.patch +++ /dev/null | |||
| @@ -1,174 +0,0 @@ | |||
| 1 | http://gcc.gnu.org/ml/gcc-patches/2006-04/msg00811.html | ||
| 2 | |||
| 3 | Kazu Hirata <kazu@codesourcery.com> | ||
| 4 | |||
| 5 | gcc/testsuite/ | ||
| 6 | * gcc.target/arm/vfp-ldmdbd.c, gcc.target/arm/vfp-ldmdbs.c, | ||
| 7 | gcc.target/arm/vfp-ldmiad.c, gcc.target/arm/vfp-ldmias.c, | ||
| 8 | gcc.target/arm/vfp-stmdbd.c, gcc.target/arm/vfp-stmdbs.c, | ||
| 9 | gcc.target/arm/vfp-stmiad.c, gcc.target/arm/vfp-stmias.c: New. | ||
| 10 | |||
| 11 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 12 | |||
| 13 | Merge from Sourcery G++ 4.4: | ||
| 14 | |||
| 15 | Julian Brown <julian@codesourcery.com> | ||
| 16 | Mark Shinwell <mark@codesourcery.com> | ||
| 17 | |||
| 18 | |||
| 19 | === added file 'gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c' | ||
| 20 | --- old/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c 1970-01-01 00:00:00 +0000 | ||
| 21 | +++ new/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c 2010-08-05 15:37:24 +0000 | ||
| 22 | @@ -0,0 +1,15 @@ | ||
| 23 | +/* { dg-do compile } */ | ||
| 24 | +/* { dg-require-effective-target arm_vfp_ok } */ | ||
| 25 | +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ | ||
| 26 | + | ||
| 27 | +extern void bar (double); | ||
| 28 | + | ||
| 29 | +void | ||
| 30 | +foo (double *p, double a, int n) | ||
| 31 | +{ | ||
| 32 | + do | ||
| 33 | + bar (*--p + a); | ||
| 34 | + while (n--); | ||
| 35 | +} | ||
| 36 | + | ||
| 37 | +/* { dg-final { scan-assembler "fldmdbd" } } */ | ||
| 38 | |||
| 39 | === added file 'gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c' | ||
| 40 | --- old/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c 1970-01-01 00:00:00 +0000 | ||
| 41 | +++ new/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c 2010-08-05 15:37:24 +0000 | ||
| 42 | @@ -0,0 +1,15 @@ | ||
| 43 | +/* { dg-do compile } */ | ||
| 44 | +/* { dg-require-effective-target arm_vfp_ok } */ | ||
| 45 | +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ | ||
| 46 | + | ||
| 47 | +extern void baz (float); | ||
| 48 | + | ||
| 49 | +void | ||
| 50 | +foo (float *p, float a, int n) | ||
| 51 | +{ | ||
| 52 | + do | ||
| 53 | + bar (*--p + a); | ||
| 54 | + while (n--); | ||
| 55 | +} | ||
| 56 | + | ||
| 57 | +/* { dg-final { scan-assembler "fldmdbs" } } */ | ||
| 58 | |||
| 59 | === added file 'gcc/testsuite/gcc.target/arm/vfp-ldmiad.c' | ||
| 60 | --- old/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c 1970-01-01 00:00:00 +0000 | ||
| 61 | +++ new/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c 2010-08-05 15:37:24 +0000 | ||
| 62 | @@ -0,0 +1,15 @@ | ||
| 63 | +/* { dg-do compile } */ | ||
| 64 | +/* { dg-require-effective-target arm_vfp_ok } */ | ||
| 65 | +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ | ||
| 66 | + | ||
| 67 | +extern void bar (double); | ||
| 68 | + | ||
| 69 | +void | ||
| 70 | +foo (double *p, double a, int n) | ||
| 71 | +{ | ||
| 72 | + do | ||
| 73 | + bar (*p++ + a); | ||
| 74 | + while (n--); | ||
| 75 | +} | ||
| 76 | + | ||
| 77 | +/* { dg-final { scan-assembler "fldmiad" } } */ | ||
| 78 | |||
| 79 | === added file 'gcc/testsuite/gcc.target/arm/vfp-ldmias.c' | ||
| 80 | --- old/gcc/testsuite/gcc.target/arm/vfp-ldmias.c 1970-01-01 00:00:00 +0000 | ||
| 81 | +++ new/gcc/testsuite/gcc.target/arm/vfp-ldmias.c 2010-08-05 15:37:24 +0000 | ||
| 82 | @@ -0,0 +1,15 @@ | ||
| 83 | +/* { dg-do compile } */ | ||
| 84 | +/* { dg-require-effective-target arm_vfp_ok } */ | ||
| 85 | +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ | ||
| 86 | + | ||
| 87 | +extern void baz (float); | ||
| 88 | + | ||
| 89 | +void | ||
| 90 | +foo (float *p, float a, int n) | ||
| 91 | +{ | ||
| 92 | + do | ||
| 93 | + bar (*p++ + a); | ||
| 94 | + while (n--); | ||
| 95 | +} | ||
| 96 | + | ||
| 97 | +/* { dg-final { scan-assembler "fldmias" } } */ | ||
| 98 | |||
| 99 | === added file 'gcc/testsuite/gcc.target/arm/vfp-stmdbd.c' | ||
| 100 | --- old/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c 1970-01-01 00:00:00 +0000 | ||
| 101 | +++ new/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c 2010-08-05 15:37:24 +0000 | ||
| 102 | @@ -0,0 +1,14 @@ | ||
| 103 | +/* { dg-do compile } */ | ||
| 104 | +/* { dg-require-effective-target arm_vfp_ok } */ | ||
| 105 | +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ | ||
| 106 | + | ||
| 107 | +void | ||
| 108 | +foo (double *p, double a, double b, int n) | ||
| 109 | +{ | ||
| 110 | + double c = a + b; | ||
| 111 | + do | ||
| 112 | + *--p = c; | ||
| 113 | + while (n--); | ||
| 114 | +} | ||
| 115 | + | ||
| 116 | +/* { dg-final { scan-assembler "fstmdbd" } } */ | ||
| 117 | |||
| 118 | === added file 'gcc/testsuite/gcc.target/arm/vfp-stmdbs.c' | ||
| 119 | --- old/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c 1970-01-01 00:00:00 +0000 | ||
| 120 | +++ new/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c 2010-08-05 15:37:24 +0000 | ||
| 121 | @@ -0,0 +1,14 @@ | ||
| 122 | +/* { dg-do compile } */ | ||
| 123 | +/* { dg-require-effective-target arm_vfp_ok } */ | ||
| 124 | +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ | ||
| 125 | + | ||
| 126 | +void | ||
| 127 | +foo (float *p, float a, float b, int n) | ||
| 128 | +{ | ||
| 129 | + float c = a + b; | ||
| 130 | + do | ||
| 131 | + *--p = c; | ||
| 132 | + while (n--); | ||
| 133 | +} | ||
| 134 | + | ||
| 135 | +/* { dg-final { scan-assembler "fstmdbs" } } */ | ||
| 136 | |||
| 137 | === added file 'gcc/testsuite/gcc.target/arm/vfp-stmiad.c' | ||
| 138 | --- old/gcc/testsuite/gcc.target/arm/vfp-stmiad.c 1970-01-01 00:00:00 +0000 | ||
| 139 | +++ new/gcc/testsuite/gcc.target/arm/vfp-stmiad.c 2010-08-05 15:37:24 +0000 | ||
| 140 | @@ -0,0 +1,14 @@ | ||
| 141 | +/* { dg-do compile } */ | ||
| 142 | +/* { dg-require-effective-target arm_vfp_ok } */ | ||
| 143 | +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ | ||
| 144 | + | ||
| 145 | +void | ||
| 146 | +foo (double *p, double a, double b, int n) | ||
| 147 | +{ | ||
| 148 | + double c = a + b; | ||
| 149 | + do | ||
| 150 | + *p++ = c; | ||
| 151 | + while (n--); | ||
| 152 | +} | ||
| 153 | + | ||
| 154 | +/* { dg-final { scan-assembler "fstmiad" } } */ | ||
| 155 | |||
| 156 | === added file 'gcc/testsuite/gcc.target/arm/vfp-stmias.c' | ||
| 157 | --- old/gcc/testsuite/gcc.target/arm/vfp-stmias.c 1970-01-01 00:00:00 +0000 | ||
| 158 | +++ new/gcc/testsuite/gcc.target/arm/vfp-stmias.c 2010-08-05 15:37:24 +0000 | ||
| 159 | @@ -0,0 +1,14 @@ | ||
| 160 | +/* { dg-do compile } */ | ||
| 161 | +/* { dg-require-effective-target arm_vfp_ok } */ | ||
| 162 | +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ | ||
| 163 | + | ||
| 164 | +void | ||
| 165 | +foo (float *p, float a, float b, int n) | ||
| 166 | +{ | ||
| 167 | + float c = a + b; | ||
| 168 | + do | ||
| 169 | + *p++ = c; | ||
| 170 | + while (n--); | ||
| 171 | +} | ||
| 172 | + | ||
| 173 | +/* { dg-final { scan-assembler "fstmias" } } */ | ||
| 174 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99326.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99326.patch deleted file mode 100644 index 59b598ba7..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99326.patch +++ /dev/null | |||
| @@ -1,86 +0,0 @@ | |||
| 1 | |||
| 2 | http://gcc.gnu.org/ml/gcc-patches/2006-03/msg00038.html | ||
| 3 | |||
| 4 | * g++.dg/other/armv7m-1.C: New. | ||
| 5 | |||
| 6 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 7 | |||
| 8 | Merge from Sourcery G++ 4.4: | ||
| 9 | |||
| 10 | http://gcc.gnu.org/ml/gcc-patches/2006-04/msg00811.html | ||
| 11 | |||
| 12 | |||
| 13 | === added file 'gcc/testsuite/g++.dg/other/armv7m-1.C' | ||
| 14 | --- old/gcc/testsuite/g++.dg/other/armv7m-1.C 1970-01-01 00:00:00 +0000 | ||
| 15 | +++ new/gcc/testsuite/g++.dg/other/armv7m-1.C 2010-08-05 16:23:43 +0000 | ||
| 16 | @@ -0,0 +1,69 @@ | ||
| 17 | +/* { dg-do run { target arm*-*-* } } */ | ||
| 18 | +/* Test Armv7m interrupt routines. */ | ||
| 19 | +#include <stdlib.h> | ||
| 20 | + | ||
| 21 | +#ifdef __ARM_ARCH_7M__ | ||
| 22 | +void __attribute__((interrupt)) | ||
| 23 | +foo(void) | ||
| 24 | +{ | ||
| 25 | + long long n; | ||
| 26 | + long p; | ||
| 27 | + asm volatile ("" : "=r" (p) : "0" (&n)); | ||
| 28 | + if (p & 4) | ||
| 29 | + abort (); | ||
| 30 | + return; | ||
| 31 | +} | ||
| 32 | + | ||
| 33 | +void __attribute__((interrupt)) | ||
| 34 | +bar(void) | ||
| 35 | +{ | ||
| 36 | + throw 42; | ||
| 37 | +} | ||
| 38 | + | ||
| 39 | +int main() | ||
| 40 | +{ | ||
| 41 | + int a; | ||
| 42 | + int before; | ||
| 43 | + int after; | ||
| 44 | + volatile register int sp asm("sp"); | ||
| 45 | + | ||
| 46 | + asm volatile ("mov %0, sp\n" | ||
| 47 | + "blx %2\n" | ||
| 48 | + "mov %1, sp\n" | ||
| 49 | + : "=&r" (before), "=r" (after) : "r" (foo) | ||
| 50 | + : "memory", "cc", "r0", "r1", "r2", "r3", "ip", "lr"); | ||
| 51 | + if (before != after) | ||
| 52 | + abort(); | ||
| 53 | + asm volatile ("mov %0, sp\n" | ||
| 54 | + "sub sp, sp, #4\n" | ||
| 55 | + "blx %2\n" | ||
| 56 | + "add sp, sp, #4\n" | ||
| 57 | + "mov %1, sp\n" | ||
| 58 | + : "=&r" (before), "=r" (after) : "r" (foo) | ||
| 59 | + : "memory", "cc", "r0", "r1", "r2", "r3", "ip", "lr"); | ||
| 60 | + if (before != after) | ||
| 61 | + abort(); | ||
| 62 | + before = sp; | ||
| 63 | + try | ||
| 64 | + { | ||
| 65 | + bar(); | ||
| 66 | + } | ||
| 67 | + catch (int i) | ||
| 68 | + { | ||
| 69 | + if (i != 42) | ||
| 70 | + abort(); | ||
| 71 | + } | ||
| 72 | + catch (...) | ||
| 73 | + { | ||
| 74 | + abort(); | ||
| 75 | + } | ||
| 76 | + if (before != sp) | ||
| 77 | + abort(); | ||
| 78 | + exit(0); | ||
| 79 | +} | ||
| 80 | +#else | ||
| 81 | +int main() | ||
| 82 | +{ | ||
| 83 | + exit (0); | ||
| 84 | +} | ||
| 85 | +#endif | ||
| 86 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch deleted file mode 100644 index 5d489aab6..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch +++ /dev/null | |||
| @@ -1,132 +0,0 @@ | |||
| 1 | Backport from FSF mainline: | ||
| 2 | |||
| 3 | Mark Shinwell <shinwell@codesourcery.com> | ||
| 4 | Julian Brown <julian@codesourcery.com> | ||
| 5 | |||
| 6 | gcc/ | ||
| 7 | * config/arm/thumb2.md (thumb2_movsi_insn): Split ldr and str | ||
| 8 | alternatives according to use of high and low regs. | ||
| 9 | * config/arm/vfp.md (thumb2_movsi_vfp): Likewise. | ||
| 10 | * config/arm/arm.h (CONDITIONAL_REGISTER_USAGE): Use high regs when | ||
| 11 | optimizing for size on Thumb-2. | ||
| 12 | |||
| 13 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 14 | |||
| 15 | Merge from Sourcery G++ 4.4: | ||
| 16 | |||
| 17 | http://gcc.gnu.org/ml/gcc-patches/2006-03/msg00038.html | ||
| 18 | |||
| 19 | === modified file 'gcc/config/arm/arm.h' | ||
| 20 | --- old/gcc/config/arm/arm.h 2010-08-05 15:28:47 +0000 | ||
| 21 | +++ new/gcc/config/arm/arm.h 2010-08-05 16:34:46 +0000 | ||
| 22 | @@ -783,12 +783,11 @@ | ||
| 23 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | ||
| 24 | } \ | ||
| 25 | \ | ||
| 26 | - if (TARGET_THUMB && optimize_size) \ | ||
| 27 | - { \ | ||
| 28 | - /* When optimizing for size, it's better not to use \ | ||
| 29 | - the HI regs, because of the overhead of stacking \ | ||
| 30 | - them. */ \ | ||
| 31 | - /* ??? Is this still true for thumb2? */ \ | ||
| 32 | + if (TARGET_THUMB1 && optimize_size) \ | ||
| 33 | + { \ | ||
| 34 | + /* When optimizing for size on Thumb-1, it's better not \ | ||
| 35 | + to use the HI regs, because of the overhead of \ | ||
| 36 | + stacking them. */ \ | ||
| 37 | for (regno = FIRST_HI_REGNUM; \ | ||
| 38 | regno <= LAST_HI_REGNUM; ++regno) \ | ||
| 39 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | ||
| 40 | |||
| 41 | === modified file 'gcc/config/arm/thumb2.md' | ||
| 42 | --- old/gcc/config/arm/thumb2.md 2010-04-02 07:32:00 +0000 | ||
| 43 | +++ new/gcc/config/arm/thumb2.md 2010-08-05 16:34:46 +0000 | ||
| 44 | @@ -223,9 +223,14 @@ | ||
| 45 | (set_attr "neg_pool_range" "*,*,*,0,*")] | ||
| 46 | ) | ||
| 47 | |||
| 48 | +;; We have two alternatives here for memory loads (and similarly for stores) | ||
| 49 | +;; to reflect the fact that the permissible constant pool ranges differ | ||
| 50 | +;; between ldr instructions taking low regs and ldr instructions taking high | ||
| 51 | +;; regs. The high register alternatives are not taken into account when | ||
| 52 | +;; choosing register preferences in order to reflect their expense. | ||
| 53 | (define_insn "*thumb2_movsi_insn" | ||
| 54 | - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m") | ||
| 55 | - (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,rk"))] | ||
| 56 | + [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l, *hk,m,*m") | ||
| 57 | + (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,*mi,l,*hk"))] | ||
| 58 | "TARGET_THUMB2 && ! TARGET_IWMMXT | ||
| 59 | && !(TARGET_HARD_FLOAT && TARGET_VFP) | ||
| 60 | && ( register_operand (operands[0], SImode) | ||
| 61 | @@ -236,11 +241,13 @@ | ||
| 62 | mvn%?\\t%0, #%B1 | ||
| 63 | movw%?\\t%0, %1 | ||
| 64 | ldr%?\\t%0, %1 | ||
| 65 | + ldr%?\\t%0, %1 | ||
| 66 | + str%?\\t%1, %0 | ||
| 67 | str%?\\t%1, %0" | ||
| 68 | - [(set_attr "type" "*,*,*,*,load1,store1") | ||
| 69 | + [(set_attr "type" "*,*,*,*,load1,load1,store1,store1") | ||
| 70 | (set_attr "predicable" "yes") | ||
| 71 | - (set_attr "pool_range" "*,*,*,*,4096,*") | ||
| 72 | - (set_attr "neg_pool_range" "*,*,*,*,0,*")] | ||
| 73 | + (set_attr "pool_range" "*,*,*,*,1020,4096,*,*") | ||
| 74 | + (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")] | ||
| 75 | ) | ||
| 76 | |||
| 77 | (define_insn "tls_load_dot_plus_four" | ||
| 78 | |||
| 79 | === modified file 'gcc/config/arm/vfp.md' | ||
| 80 | --- old/gcc/config/arm/vfp.md 2010-07-30 14:17:05 +0000 | ||
| 81 | +++ new/gcc/config/arm/vfp.md 2010-08-05 16:34:46 +0000 | ||
| 82 | @@ -86,9 +86,11 @@ | ||
| 83 | (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] | ||
| 84 | ) | ||
| 85 | |||
| 86 | +;; See thumb2.md:thumb2_movsi_insn for an explanation of the split | ||
| 87 | +;; high/low register alternatives for loads and stores here. | ||
| 88 | (define_insn "*thumb2_movsi_vfp" | ||
| 89 | - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv") | ||
| 90 | - (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))] | ||
| 91 | + [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l,*hk,m,*m,*t,r, *t,*t, *Uv") | ||
| 92 | + (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,*mi,l,*hk,r,*t,*t,*Uvi,*t"))] | ||
| 93 | "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT | ||
| 94 | && ( s_register_operand (operands[0], SImode) | ||
| 95 | || s_register_operand (operands[1], SImode))" | ||
| 96 | @@ -102,25 +104,27 @@ | ||
| 97 | case 3: | ||
| 98 | return \"movw%?\\t%0, %1\"; | ||
| 99 | case 4: | ||
| 100 | + case 5: | ||
| 101 | return \"ldr%?\\t%0, %1\"; | ||
| 102 | - case 5: | ||
| 103 | + case 6: | ||
| 104 | + case 7: | ||
| 105 | return \"str%?\\t%1, %0\"; | ||
| 106 | - case 6: | ||
| 107 | + case 8: | ||
| 108 | return \"fmsr%?\\t%0, %1\\t%@ int\"; | ||
| 109 | - case 7: | ||
| 110 | + case 9: | ||
| 111 | return \"fmrs%?\\t%0, %1\\t%@ int\"; | ||
| 112 | - case 8: | ||
| 113 | + case 10: | ||
| 114 | return \"fcpys%?\\t%0, %1\\t%@ int\"; | ||
| 115 | - case 9: case 10: | ||
| 116 | + case 11: case 12: | ||
| 117 | return output_move_vfp (operands); | ||
| 118 | default: | ||
| 119 | gcc_unreachable (); | ||
| 120 | } | ||
| 121 | " | ||
| 122 | [(set_attr "predicable" "yes") | ||
| 123 | - (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_load,f_store") | ||
| 124 | - (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") | ||
| 125 | - (set_attr "neg_pool_range" "*,*,*,*, 0,*,*,*,*,1008,*")] | ||
| 126 | + (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store") | ||
| 127 | + (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*") | ||
| 128 | + (set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] | ||
| 129 | ) | ||
| 130 | |||
| 131 | |||
| 132 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99332.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99332.patch deleted file mode 100644 index 3e6361130..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99332.patch +++ /dev/null | |||
| @@ -1,68 +0,0 @@ | |||
| 1 | 2010-08-06 Yao Qi <yao@codesourcery.com> | ||
| 2 | |||
| 3 | LP: #612011 | ||
| 4 | gcc/ | ||
| 5 | * config/arm/arm.c (output_move_double): Fix typo generating | ||
| 6 | instructions ('ldr'->'str'). | ||
| 7 | |||
| 8 | gcc/testsuite/ | ||
| 9 | * gcc.target/arm/pr45094.c: New test. | ||
| 10 | |||
| 11 | 2010-08-02 Ulrich Weigand <uweigand@de.ibm.com> | ||
| 12 | |||
| 13 | LP: #604874 | ||
| 14 | |||
| 15 | === modified file 'gcc/config/arm/arm.c' | ||
| 16 | --- old/gcc/config/arm/arm.c 2010-08-10 13:31:21 +0000 | ||
| 17 | +++ new/gcc/config/arm/arm.c 2010-08-10 14:03:02 +0000 | ||
| 18 | @@ -12506,13 +12506,13 @@ | ||
| 19 | { | ||
| 20 | if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) | ||
| 21 | { | ||
| 22 | - output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); | ||
| 23 | - output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); | ||
| 24 | + output_asm_insn ("str%?\t%0, [%1, %2]!", otherops); | ||
| 25 | + output_asm_insn ("str%?\t%H0, [%1, #4]", otherops); | ||
| 26 | } | ||
| 27 | else | ||
| 28 | { | ||
| 29 | - output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); | ||
| 30 | - output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); | ||
| 31 | + output_asm_insn ("str%?\t%H0, [%1, #4]", otherops); | ||
| 32 | + output_asm_insn ("str%?\t%0, [%1], %2", otherops); | ||
| 33 | } | ||
| 34 | } | ||
| 35 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) | ||
| 36 | |||
| 37 | === added file 'gcc/testsuite/gcc.target/arm/pr45094.c' | ||
| 38 | --- old/gcc/testsuite/gcc.target/arm/pr45094.c 1970-01-01 00:00:00 +0000 | ||
| 39 | +++ new/gcc/testsuite/gcc.target/arm/pr45094.c 2010-08-06 05:10:03 +0000 | ||
| 40 | @@ -0,0 +1,27 @@ | ||
| 41 | +/* { dg-do run } */ | ||
| 42 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 43 | +/* { dg-options "-O2 -mcpu=cortex-a8" } */ | ||
| 44 | +/* { dg-add-options arm_neon } */ | ||
| 45 | + | ||
| 46 | +#include <stdlib.h> | ||
| 47 | + | ||
| 48 | +long long buffer[32]; | ||
| 49 | + | ||
| 50 | +void __attribute__((noinline)) f(long long *p, int n) | ||
| 51 | +{ | ||
| 52 | + while (--n >= 0) | ||
| 53 | + { | ||
| 54 | + *p = 1; | ||
| 55 | + p += 32; | ||
| 56 | + } | ||
| 57 | +} | ||
| 58 | + | ||
| 59 | +int main(void) | ||
| 60 | +{ | ||
| 61 | + f(buffer, 1); | ||
| 62 | + | ||
| 63 | + if (!buffer[0]) | ||
| 64 | + abort(); | ||
| 65 | + | ||
| 66 | + return 0; | ||
| 67 | +} | ||
| 68 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99335.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99335.patch deleted file mode 100644 index f75a74091..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99335.patch +++ /dev/null | |||
| @@ -1,138 +0,0 @@ | |||
| 1 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ 4.4: | ||
| 4 | |||
| 5 | Mark Shinwell <shinwell@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * config/arm/vfp.md (*arm_movsi_vfp, *thumb2_movsi_vfp) | ||
| 9 | (*arm_movdi_vfp, *thumb2_movdi_vfp, *movsf_vfp, *thumb2_movsf_vfp) | ||
| 10 | (*movdf_vfp, *thumb2_movdf_vfp, *movsfcc_vfp, *thumb2_movsfcc_vfp) | ||
| 11 | (*movdfcc_vfp, *thumb2_movdfcc_vfp): Add neon_type. | ||
| 12 | * config/arm/arm.md (neon_type): Update comment. | ||
| 13 | |||
| 14 | 2010-08-10 Andrew Stubbs <ams@codesourcery.com> | ||
| 15 | |||
| 16 | gcc/ | ||
| 17 | |||
| 18 | === modified file 'gcc/config/arm/arm.md' | ||
| 19 | --- old/gcc/config/arm/arm.md 2010-08-10 13:31:21 +0000 | ||
| 20 | +++ new/gcc/config/arm/arm.md 2010-08-12 11:29:02 +0000 | ||
| 21 | @@ -255,8 +255,6 @@ | ||
| 22 | (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched"))) | ||
| 23 | |||
| 24 | ;; Classification of NEON instructions for scheduling purposes. | ||
| 25 | -;; Do not set this attribute and the "type" attribute together in | ||
| 26 | -;; any one instruction pattern. | ||
| 27 | (define_attr "neon_type" | ||
| 28 | "neon_int_1,\ | ||
| 29 | neon_int_2,\ | ||
| 30 | |||
| 31 | === modified file 'gcc/config/arm/vfp.md' | ||
| 32 | --- old/gcc/config/arm/vfp.md 2010-08-10 13:31:21 +0000 | ||
| 33 | +++ new/gcc/config/arm/vfp.md 2010-08-12 11:29:02 +0000 | ||
| 34 | @@ -82,6 +82,7 @@ | ||
| 35 | " | ||
| 36 | [(set_attr "predicable" "yes") | ||
| 37 | (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") | ||
| 38 | + (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") | ||
| 39 | (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") | ||
| 40 | (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] | ||
| 41 | ) | ||
| 42 | @@ -123,6 +124,7 @@ | ||
| 43 | " | ||
| 44 | [(set_attr "predicable" "yes") | ||
| 45 | (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store") | ||
| 46 | + (set_attr "neon_type" "*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") | ||
| 47 | (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*") | ||
| 48 | (set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")] | ||
| 49 | ) | ||
| 50 | @@ -160,6 +162,7 @@ | ||
| 51 | } | ||
| 52 | " | ||
| 53 | [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") | ||
| 54 | + (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") | ||
| 55 | (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) | ||
| 56 | (eq_attr "alternative" "5") | ||
| 57 | (if_then_else | ||
| 58 | @@ -198,6 +201,7 @@ | ||
| 59 | } | ||
| 60 | " | ||
| 61 | [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store") | ||
| 62 | + (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") | ||
| 63 | (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) | ||
| 64 | (eq_attr "alternative" "5") | ||
| 65 | (if_then_else | ||
| 66 | @@ -352,6 +356,7 @@ | ||
| 67 | [(set_attr "predicable" "yes") | ||
| 68 | (set_attr "type" | ||
| 69 | "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*") | ||
| 70 | + (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") | ||
| 71 | (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*") | ||
| 72 | (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")] | ||
| 73 | ) | ||
| 74 | @@ -388,6 +393,7 @@ | ||
| 75 | [(set_attr "predicable" "yes") | ||
| 76 | (set_attr "type" | ||
| 77 | "r_2_f,f_2_r,fconsts,f_load,f_store,load1,store1,fcpys,*") | ||
| 78 | + (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*") | ||
| 79 | (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*") | ||
| 80 | (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")] | ||
| 81 | ) | ||
| 82 | @@ -430,6 +436,7 @@ | ||
| 83 | " | ||
| 84 | [(set_attr "type" | ||
| 85 | "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*") | ||
| 86 | + (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*") | ||
| 87 | (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8) | ||
| 88 | (eq_attr "alternative" "7") | ||
| 89 | (if_then_else | ||
| 90 | @@ -474,6 +481,7 @@ | ||
| 91 | " | ||
| 92 | [(set_attr "type" | ||
| 93 | "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*") | ||
| 94 | + (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*") | ||
| 95 | (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8) | ||
| 96 | (eq_attr "alternative" "7") | ||
| 97 | (if_then_else | ||
| 98 | @@ -509,7 +517,8 @@ | ||
| 99 | fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" | ||
| 100 | [(set_attr "conds" "use") | ||
| 101 | (set_attr "length" "4,4,8,4,4,8,4,4,8") | ||
| 102 | - (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] | ||
| 103 | + (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") | ||
| 104 | + (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")] | ||
| 105 | ) | ||
| 106 | |||
| 107 | (define_insn "*thumb2_movsfcc_vfp" | ||
| 108 | @@ -532,7 +541,8 @@ | ||
| 109 | ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1" | ||
| 110 | [(set_attr "conds" "use") | ||
| 111 | (set_attr "length" "6,6,10,6,6,10,6,6,10") | ||
| 112 | - (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] | ||
| 113 | + (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") | ||
| 114 | + (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")] | ||
| 115 | ) | ||
| 116 | |||
| 117 | (define_insn "*movdfcc_vfp" | ||
| 118 | @@ -555,7 +565,8 @@ | ||
| 119 | fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" | ||
| 120 | [(set_attr "conds" "use") | ||
| 121 | (set_attr "length" "4,4,8,4,4,8,4,4,8") | ||
| 122 | - (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] | ||
| 123 | + (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") | ||
| 124 | + (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")] | ||
| 125 | ) | ||
| 126 | |||
| 127 | (define_insn "*thumb2_movdfcc_vfp" | ||
| 128 | @@ -578,7 +589,8 @@ | ||
| 129 | ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1" | ||
| 130 | [(set_attr "conds" "use") | ||
| 131 | (set_attr "length" "6,6,10,6,6,10,6,6,10") | ||
| 132 | - (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")] | ||
| 133 | + (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r") | ||
| 134 | + (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")] | ||
| 135 | ) | ||
| 136 | |||
| 137 | |||
| 138 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99336.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99336.patch deleted file mode 100644 index 9b5656094..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99336.patch +++ /dev/null | |||
| @@ -1,95 +0,0 @@ | |||
| 1 | gcc/ | ||
| 2 | * config/arm/arm.c (arm_override_options): Override alignments if | ||
| 3 | tuning for Cortex-A8. | ||
| 4 | (create_fix_barrier, arm_reorg): If aligning to jumps or loops, | ||
| 5 | make labels have a size. | ||
| 6 | * config/arm/arm.md (VUNSPEC_ALIGN16, VUNSPEC_ALIGN32): New constants. | ||
| 7 | (align_16, align_32): New patterns. | ||
| 8 | |||
| 9 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 10 | |||
| 11 | Merge from Sourcery G++ 4.4: | ||
| 12 | |||
| 13 | Mark Shinwell <shinwell@codesourcery.com> | ||
| 14 | |||
| 15 | |||
| 16 | === modified file 'gcc/config/arm/arm.c' | ||
| 17 | --- old/gcc/config/arm/arm.c 2010-08-10 14:03:02 +0000 | ||
| 18 | +++ new/gcc/config/arm/arm.c 2010-08-12 11:33:54 +0000 | ||
| 19 | @@ -1449,6 +1449,16 @@ | ||
| 20 | chosen. */ | ||
| 21 | gcc_assert (arm_tune != arm_none); | ||
| 22 | |||
| 23 | + if (arm_tune == cortexa8 && optimize >= 3) | ||
| 24 | + { | ||
| 25 | + /* These alignments were experimentally determined to improve SPECint | ||
| 26 | + performance on SPECCPU 2000. */ | ||
| 27 | + if (align_functions <= 0) | ||
| 28 | + align_functions = 16; | ||
| 29 | + if (align_jumps <= 0) | ||
| 30 | + align_jumps = 16; | ||
| 31 | + } | ||
| 32 | + | ||
| 33 | tune_flags = all_cores[(int)arm_tune].flags; | ||
| 34 | |||
| 35 | if (target_fp16_format_name) | ||
| 36 | @@ -11263,7 +11273,10 @@ | ||
| 37 | gcc_assert (GET_CODE (from) != BARRIER); | ||
| 38 | |||
| 39 | /* Count the length of this insn. */ | ||
| 40 | - count += get_attr_length (from); | ||
| 41 | + if (LABEL_P (from) && (align_jumps > 0 || align_loops > 0)) | ||
| 42 | + count += MAX (align_jumps, align_loops); | ||
| 43 | + else | ||
| 44 | + count += get_attr_length (from); | ||
| 45 | |||
| 46 | /* If there is a jump table, add its length. */ | ||
| 47 | tmp = is_jump_table (from); | ||
| 48 | @@ -11603,6 +11616,8 @@ | ||
| 49 | insn = table; | ||
| 50 | } | ||
| 51 | } | ||
| 52 | + else if (LABEL_P (insn) && (align_jumps > 0 || align_loops > 0)) | ||
| 53 | + address += MAX (align_jumps, align_loops); | ||
| 54 | } | ||
| 55 | |||
| 56 | fix = minipool_fix_head; | ||
| 57 | |||
| 58 | === modified file 'gcc/config/arm/arm.md' | ||
| 59 | --- old/gcc/config/arm/arm.md 2010-08-12 11:29:02 +0000 | ||
| 60 | +++ new/gcc/config/arm/arm.md 2010-08-12 11:33:54 +0000 | ||
| 61 | @@ -135,6 +135,8 @@ | ||
| 62 | (VUNSPEC_WCMP_EQ 12) ; Used by the iWMMXt WCMPEQ instructions | ||
| 63 | (VUNSPEC_WCMP_GTU 13) ; Used by the iWMMXt WCMPGTU instructions | ||
| 64 | (VUNSPEC_WCMP_GT 14) ; Used by the iwMMXT WCMPGT instructions | ||
| 65 | + (VUNSPEC_ALIGN16 15) ; Used to force 16-byte alignment. | ||
| 66 | + (VUNSPEC_ALIGN32 16) ; Used to force 32-byte alignment. | ||
| 67 | (VUNSPEC_EH_RETURN 20); Use to override the return address for exception | ||
| 68 | ; handling. | ||
| 69 | ] | ||
| 70 | @@ -11042,6 +11044,24 @@ | ||
| 71 | " | ||
| 72 | ) | ||
| 73 | |||
| 74 | +(define_insn "align_16" | ||
| 75 | + [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN16)] | ||
| 76 | + "TARGET_EITHER" | ||
| 77 | + "* | ||
| 78 | + assemble_align (128); | ||
| 79 | + return \"\"; | ||
| 80 | + " | ||
| 81 | +) | ||
| 82 | + | ||
| 83 | +(define_insn "align_32" | ||
| 84 | + [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN32)] | ||
| 85 | + "TARGET_EITHER" | ||
| 86 | + "* | ||
| 87 | + assemble_align (256); | ||
| 88 | + return \"\"; | ||
| 89 | + " | ||
| 90 | +) | ||
| 91 | + | ||
| 92 | (define_insn "consttable_end" | ||
| 93 | [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)] | ||
| 94 | "TARGET_EITHER" | ||
| 95 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99337.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99337.patch deleted file mode 100644 index 850acb31b..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99337.patch +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | 2008-09-08 Daniel Jacobowitz <dan@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * config/arm/unwind-arm.c (__gnu_unwind_pr_common): Correct test | ||
| 5 | for barrier handlers. | ||
| 6 | |||
| 7 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 8 | |||
| 9 | Merge from Sourcery G++ 4.4: | ||
| 10 | |||
| 11 | gcc/ | ||
| 12 | * config/arm/arm.c (arm_override_options): Override alignments if | ||
| 13 | tuning for Cortex-A8. | ||
| 14 | |||
| 15 | === modified file 'gcc/config/arm/unwind-arm.c' | ||
| 16 | --- old/gcc/config/arm/unwind-arm.c 2009-10-30 14:55:10 +0000 | ||
| 17 | +++ new/gcc/config/arm/unwind-arm.c 2010-08-12 12:39:35 +0000 | ||
| 18 | @@ -1196,8 +1196,6 @@ | ||
| 19 | ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1]; | ||
| 20 | |||
| 21 | if (data[0] & uint32_highbit) | ||
| 22 | - phase2_call_unexpected_after_unwind = 1; | ||
| 23 | - else | ||
| 24 | { | ||
| 25 | data += rtti_count + 1; | ||
| 26 | /* Setup for entry to the handler. */ | ||
| 27 | @@ -1207,6 +1205,8 @@ | ||
| 28 | _Unwind_SetGR (context, 0, (_uw) ucbp); | ||
| 29 | return _URC_INSTALL_CONTEXT; | ||
| 30 | } | ||
| 31 | + else | ||
| 32 | + phase2_call_unexpected_after_unwind = 1; | ||
| 33 | } | ||
| 34 | if (data[0] & uint32_highbit) | ||
| 35 | data++; | ||
| 36 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99338.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99338.patch deleted file mode 100644 index 632e80caf..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99338.patch +++ /dev/null | |||
| @@ -1,111 +0,0 @@ | |||
| 1 | 2009-06-23 Kazu Hirata <kazu@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #4613 | ||
| 4 | gcc/ | ||
| 5 | * config/arm/arm.c (arm_rtx_costs_1): Teach that the cost of MLS | ||
| 6 | is the same as its underlying multiplication. | ||
| 7 | * config/arm/arm.md (two splitters): New. | ||
| 8 | * config/arm/predicates.md (binary_operator): New. | ||
| 9 | |||
| 10 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 11 | |||
| 12 | Merge from Sourcery G++ 4.4: | ||
| 13 | |||
| 14 | 2008-09-08 Daniel Jacobowitz <dan@codesourcery.com> | ||
| 15 | |||
| 16 | gcc/ | ||
| 17 | |||
| 18 | === modified file 'gcc/config/arm/arm.c' | ||
| 19 | --- old/gcc/config/arm/arm.c 2010-08-12 11:33:54 +0000 | ||
| 20 | +++ new/gcc/config/arm/arm.c 2010-08-12 13:35:39 +0000 | ||
| 21 | @@ -6604,6 +6604,19 @@ | ||
| 22 | return true; | ||
| 23 | } | ||
| 24 | |||
| 25 | + /* MLS is just as expensive as its underlying multiplication. | ||
| 26 | + Exclude a shift by a constant, which is expressed as a | ||
| 27 | + multiplication. */ | ||
| 28 | + if (TARGET_32BIT && arm_arch_thumb2 | ||
| 29 | + && GET_CODE (XEXP (x, 1)) == MULT | ||
| 30 | + && ! (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | ||
| 31 | + && ((INTVAL (XEXP (XEXP (x, 1), 1)) & | ||
| 32 | + (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0))) | ||
| 33 | + { | ||
| 34 | + /* The cost comes from the cost of the multiply. */ | ||
| 35 | + return false; | ||
| 36 | + } | ||
| 37 | + | ||
| 38 | /* Fall through */ | ||
| 39 | |||
| 40 | case PLUS: | ||
| 41 | |||
| 42 | === modified file 'gcc/config/arm/arm.md' | ||
| 43 | --- old/gcc/config/arm/arm.md 2010-08-12 11:33:54 +0000 | ||
| 44 | +++ new/gcc/config/arm/arm.md 2010-08-12 13:35:39 +0000 | ||
| 45 | @@ -1355,6 +1355,49 @@ | ||
| 46 | (set_attr "predicable" "yes")] | ||
| 47 | ) | ||
| 48 | |||
| 49 | +; The combiner cannot combine the first and last insns in the | ||
| 50 | +; following sequence because of the intervening insn, so help the | ||
| 51 | +; combiner with this splitter. The combiner does attempt to split | ||
| 52 | +; this particular combination but does not know this exact split. | ||
| 53 | +; Note that the combiner puts the constant at the outermost operation | ||
| 54 | +; as a part of canonicalization. | ||
| 55 | +; | ||
| 56 | +; mul r3, r2, r1 | ||
| 57 | +; <add/sub> r3, r3, <constant> | ||
| 58 | +; add r3, r3, r4 | ||
| 59 | + | ||
| 60 | +(define_split | ||
| 61 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 62 | + (match_operator:SI 1 "plusminus_operator" | ||
| 63 | + [(plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "") | ||
| 64 | + (match_operand:SI 3 "s_register_operand" "")) | ||
| 65 | + (match_operand:SI 4 "s_register_operand" "")) | ||
| 66 | + (match_operand:SI 5 "arm_immediate_operand" "")]))] | ||
| 67 | + "TARGET_32BIT" | ||
| 68 | + [(set (match_dup 0) | ||
| 69 | + (plus:SI (mult:SI (match_dup 2) (match_dup 3)) | ||
| 70 | + (match_dup 4))) | ||
| 71 | + (set (match_dup 0) | ||
| 72 | + (match_op_dup:SI 1 [(match_dup 0) (match_dup 5)]))] | ||
| 73 | + "") | ||
| 74 | + | ||
| 75 | +; Likewise for MLS. MLS is available only on select architectures. | ||
| 76 | + | ||
| 77 | +(define_split | ||
| 78 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 79 | + (match_operator:SI 1 "plusminus_operator" | ||
| 80 | + [(minus:SI (match_operand:SI 2 "s_register_operand" "") | ||
| 81 | + (mult:SI (match_operand:SI 3 "s_register_operand" "") | ||
| 82 | + (match_operand:SI 4 "s_register_operand" ""))) | ||
| 83 | + (match_operand:SI 5 "arm_immediate_operand" "")]))] | ||
| 84 | + "TARGET_32BIT && arm_arch_thumb2" | ||
| 85 | + [(set (match_dup 0) | ||
| 86 | + (minus:SI (match_dup 2) | ||
| 87 | + (mult:SI (match_dup 3) (match_dup 4)))) | ||
| 88 | + (set (match_dup 0) | ||
| 89 | + (match_op_dup:SI 1 [(match_dup 0) (match_dup 5)]))] | ||
| 90 | + "") | ||
| 91 | + | ||
| 92 | (define_insn "*mulsi3addsi_compare0" | ||
| 93 | [(set (reg:CC_NOOV CC_REGNUM) | ||
| 94 | (compare:CC_NOOV | ||
| 95 | |||
| 96 | === modified file 'gcc/config/arm/predicates.md' | ||
| 97 | --- old/gcc/config/arm/predicates.md 2010-08-10 13:31:21 +0000 | ||
| 98 | +++ new/gcc/config/arm/predicates.md 2010-08-12 13:35:39 +0000 | ||
| 99 | @@ -197,6 +197,11 @@ | ||
| 100 | (and (match_code "plus,minus,ior,xor,and") | ||
| 101 | (match_test "mode == GET_MODE (op)"))) | ||
| 102 | |||
| 103 | +;; True for plus/minus operators | ||
| 104 | +(define_special_predicate "plusminus_operator" | ||
| 105 | + (and (match_code "plus,minus") | ||
| 106 | + (match_test "mode == GET_MODE (op)"))) | ||
| 107 | + | ||
| 108 | ;; True for logical binary operators. | ||
| 109 | (define_special_predicate "logical_binary_operator" | ||
| 110 | (and (match_code "ior,xor,and") | ||
| 111 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99339.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99339.patch deleted file mode 100644 index f4a8e80ab..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99339.patch +++ /dev/null | |||
| @@ -1,236 +0,0 @@ | |||
| 1 | Backport from FSF mainline: | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * gengtype-lex.l: Add HARD_REG_SET. | ||
| 5 | * expr.c (expand_expr_real_1): Record writes to hard registers. | ||
| 6 | * function.h (rtl_data): Add asm_clobbers. | ||
| 7 | * ira.c (compute_regs_asm_clobbered): Use crtl->asm_clobbers. | ||
| 8 | (ira_setup_eliminable_regset): Remove regs_asm_clobbered. | ||
| 9 | Use crtl->asm_clobbers. | ||
| 10 | |||
| 11 | gcc/testsuite/ | ||
| 12 | * gcc.target/arm/frame-pointer-1.c: New test. | ||
| 13 | * gcc.target/i386/pr9771-1.c: Move code out of main to allow frame | ||
| 14 | pointer elimination. | ||
| 15 | |||
| 16 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 17 | |||
| 18 | Merge from Sourcery G++ 4.4: | ||
| 19 | |||
| 20 | 2009-06-23 Kazu Hirata <kazu@codesourcery.com> | ||
| 21 | |||
| 22 | === modified file 'gcc/expr.c' | ||
| 23 | --- old/gcc/expr.c 2010-05-31 14:45:06 +0000 | ||
| 24 | +++ new/gcc/expr.c 2010-08-12 13:51:16 +0000 | ||
| 25 | @@ -8458,6 +8458,19 @@ | ||
| 26 | expand_decl_rtl: | ||
| 27 | gcc_assert (decl_rtl); | ||
| 28 | decl_rtl = copy_rtx (decl_rtl); | ||
| 29 | + /* Record writes to register variables. */ | ||
| 30 | + if (modifier == EXPAND_WRITE && REG_P (decl_rtl) | ||
| 31 | + && REGNO (decl_rtl) < FIRST_PSEUDO_REGISTER) | ||
| 32 | + { | ||
| 33 | + int i = REGNO (decl_rtl); | ||
| 34 | + int nregs = hard_regno_nregs[i][GET_MODE (decl_rtl)]; | ||
| 35 | + while (nregs) | ||
| 36 | + { | ||
| 37 | + SET_HARD_REG_BIT (crtl->asm_clobbers, i); | ||
| 38 | + i++; | ||
| 39 | + nregs--; | ||
| 40 | + } | ||
| 41 | + } | ||
| 42 | |||
| 43 | /* Ensure variable marked as used even if it doesn't go through | ||
| 44 | a parser. If it hasn't be used yet, write out an external | ||
| 45 | |||
| 46 | === modified file 'gcc/function.h' | ||
| 47 | --- old/gcc/function.h 2009-11-25 10:55:54 +0000 | ||
| 48 | +++ new/gcc/function.h 2010-08-12 13:51:16 +0000 | ||
| 49 | @@ -25,6 +25,7 @@ | ||
| 50 | #include "tree.h" | ||
| 51 | #include "hashtab.h" | ||
| 52 | #include "vecprim.h" | ||
| 53 | +#include "hard-reg-set.h" | ||
| 54 | |||
| 55 | /* Stack of pending (incomplete) sequences saved by `start_sequence'. | ||
| 56 | Each element describes one pending sequence. | ||
| 57 | @@ -433,6 +434,12 @@ | ||
| 58 | TREE_NOTHROW (current_function_decl) it is set even for overwritable | ||
| 59 | function where currently compiled version of it is nothrow. */ | ||
| 60 | bool nothrow; | ||
| 61 | + | ||
| 62 | + /* Like regs_ever_live, but 1 if a reg is set or clobbered from an | ||
| 63 | + asm. Unlike regs_ever_live, elements of this array corresponding | ||
| 64 | + to eliminable regs (like the frame pointer) are set if an asm | ||
| 65 | + sets them. */ | ||
| 66 | + HARD_REG_SET asm_clobbers; | ||
| 67 | }; | ||
| 68 | |||
| 69 | #define return_label (crtl->x_return_label) | ||
| 70 | |||
| 71 | === modified file 'gcc/gengtype-lex.l' | ||
| 72 | --- old/gcc/gengtype-lex.l 2009-11-21 10:24:25 +0000 | ||
| 73 | +++ new/gcc/gengtype-lex.l 2010-08-12 13:51:16 +0000 | ||
| 74 | @@ -49,7 +49,7 @@ | ||
| 75 | ID [[:alpha:]_][[:alnum:]_]* | ||
| 76 | WS [[:space:]]+ | ||
| 77 | HWS [ \t\r\v\f]* | ||
| 78 | -IWORD short|long|(un)?signed|char|int|HOST_WIDE_INT|HOST_WIDEST_INT|bool|size_t|BOOL_BITFIELD|CPPCHAR_SIGNED_T|ino_t|dev_t | ||
| 79 | +IWORD short|long|(un)?signed|char|int|HOST_WIDE_INT|HOST_WIDEST_INT|bool|size_t|BOOL_BITFIELD|CPPCHAR_SIGNED_T|ino_t|dev_t|HARD_REG_SET | ||
| 80 | ITYPE {IWORD}({WS}{IWORD})* | ||
| 81 | EOID [^[:alnum:]_] | ||
| 82 | |||
| 83 | |||
| 84 | === modified file 'gcc/ira.c' | ||
| 85 | --- old/gcc/ira.c 2010-03-31 01:44:10 +0000 | ||
| 86 | +++ new/gcc/ira.c 2010-08-12 13:51:16 +0000 | ||
| 87 | @@ -1385,14 +1385,12 @@ | ||
| 88 | return for_each_rtx (&insn, insn_contains_asm_1, NULL); | ||
| 89 | } | ||
| 90 | |||
| 91 | -/* Set up regs_asm_clobbered. */ | ||
| 92 | +/* Add register clobbers from asm statements. */ | ||
| 93 | static void | ||
| 94 | -compute_regs_asm_clobbered (char *regs_asm_clobbered) | ||
| 95 | +compute_regs_asm_clobbered (void) | ||
| 96 | { | ||
| 97 | basic_block bb; | ||
| 98 | |||
| 99 | - memset (regs_asm_clobbered, 0, sizeof (char) * FIRST_PSEUDO_REGISTER); | ||
| 100 | - | ||
| 101 | FOR_EACH_BB (bb) | ||
| 102 | { | ||
| 103 | rtx insn; | ||
| 104 | @@ -1413,7 +1411,7 @@ | ||
| 105 | + hard_regno_nregs[dregno][mode] - 1; | ||
| 106 | |||
| 107 | for (i = dregno; i <= end; ++i) | ||
| 108 | - regs_asm_clobbered[i] = 1; | ||
| 109 | + SET_HARD_REG_BIT(crtl->asm_clobbers, i); | ||
| 110 | } | ||
| 111 | } | ||
| 112 | } | ||
| 113 | @@ -1425,12 +1423,6 @@ | ||
| 114 | void | ||
| 115 | ira_setup_eliminable_regset (void) | ||
| 116 | { | ||
| 117 | - /* Like regs_ever_live, but 1 if a reg is set or clobbered from an | ||
| 118 | - asm. Unlike regs_ever_live, elements of this array corresponding | ||
| 119 | - to eliminable regs (like the frame pointer) are set if an asm | ||
| 120 | - sets them. */ | ||
| 121 | - char *regs_asm_clobbered | ||
| 122 | - = (char *) alloca (FIRST_PSEUDO_REGISTER * sizeof (char)); | ||
| 123 | #ifdef ELIMINABLE_REGS | ||
| 124 | int i; | ||
| 125 | static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; | ||
| 126 | @@ -1454,7 +1446,8 @@ | ||
| 127 | COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs); | ||
| 128 | CLEAR_HARD_REG_SET (eliminable_regset); | ||
| 129 | |||
| 130 | - compute_regs_asm_clobbered (regs_asm_clobbered); | ||
| 131 | + compute_regs_asm_clobbered (); | ||
| 132 | + | ||
| 133 | /* Build the regset of all eliminable registers and show we can't | ||
| 134 | use those that we already know won't be eliminated. */ | ||
| 135 | #ifdef ELIMINABLE_REGS | ||
| 136 | @@ -1464,7 +1457,7 @@ | ||
| 137 | = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to) | ||
| 138 | || (eliminables[i].to == STACK_POINTER_REGNUM && need_fp)); | ||
| 139 | |||
| 140 | - if (! regs_asm_clobbered[eliminables[i].from]) | ||
| 141 | + if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from)) | ||
| 142 | { | ||
| 143 | SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); | ||
| 144 | |||
| 145 | @@ -1478,7 +1471,7 @@ | ||
| 146 | df_set_regs_ever_live (eliminables[i].from, true); | ||
| 147 | } | ||
| 148 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | ||
| 149 | - if (! regs_asm_clobbered[HARD_FRAME_POINTER_REGNUM]) | ||
| 150 | + if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) | ||
| 151 | { | ||
| 152 | SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM); | ||
| 153 | if (need_fp) | ||
| 154 | @@ -1492,7 +1485,7 @@ | ||
| 155 | #endif | ||
| 156 | |||
| 157 | #else | ||
| 158 | - if (! regs_asm_clobbered[FRAME_POINTER_REGNUM]) | ||
| 159 | + if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) | ||
| 160 | { | ||
| 161 | SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM); | ||
| 162 | if (need_fp) | ||
| 163 | |||
| 164 | === added file 'gcc/testsuite/gcc.target/arm/frame-pointer-1.c' | ||
| 165 | --- old/gcc/testsuite/gcc.target/arm/frame-pointer-1.c 1970-01-01 00:00:00 +0000 | ||
| 166 | +++ new/gcc/testsuite/gcc.target/arm/frame-pointer-1.c 2010-08-12 13:51:16 +0000 | ||
| 167 | @@ -0,0 +1,42 @@ | ||
| 168 | +/* Check local register variables using a register conventionally | ||
| 169 | + used as the frame pointer aren't clobbered under high register pressure. */ | ||
| 170 | +/* { dg-do run } */ | ||
| 171 | +/* { dg-options "-Os -mthumb -fomit-frame-pointer" } */ | ||
| 172 | + | ||
| 173 | +#include <stdlib.h> | ||
| 174 | + | ||
| 175 | +int global=5; | ||
| 176 | + | ||
| 177 | +void __attribute__((noinline)) foo(int p1, int p2, int p3, int p4) | ||
| 178 | +{ | ||
| 179 | + if (global != 5 || p1 != 1 || p2 != 2 || p3 != 3 || p4 != 4) | ||
| 180 | + abort(); | ||
| 181 | +} | ||
| 182 | + | ||
| 183 | +int __attribute__((noinline)) test(int a, int b, int c, int d) | ||
| 184 | +{ | ||
| 185 | + register unsigned long r __asm__("r7") = 0xdeadbeef; | ||
| 186 | + int e; | ||
| 187 | + | ||
| 188 | + /* ABCD are live after the call which should be enough | ||
| 189 | + to cause r7 to be used if it weren't for the register variable. */ | ||
| 190 | + foo(a,b,c,d); | ||
| 191 | + | ||
| 192 | + e = 0; | ||
| 193 | + __asm__ __volatile__ ("mov %0, %2" | ||
| 194 | + : "=r" (e) | ||
| 195 | + : "0" (e), "r" (r)); | ||
| 196 | + | ||
| 197 | + global = a+b+c+d; | ||
| 198 | + | ||
| 199 | + return e; | ||
| 200 | +} | ||
| 201 | + | ||
| 202 | +int main() | ||
| 203 | +{ | ||
| 204 | + if (test(1, 2, 3, 4) != 0xdeadbeef) | ||
| 205 | + abort(); | ||
| 206 | + if (global != 10) | ||
| 207 | + abort(); | ||
| 208 | + return 0; | ||
| 209 | +} | ||
| 210 | |||
| 211 | === modified file 'gcc/testsuite/gcc.target/i386/pr9771-1.c' | ||
| 212 | --- old/gcc/testsuite/gcc.target/i386/pr9771-1.c 2007-08-22 08:59:14 +0000 | ||
| 213 | +++ new/gcc/testsuite/gcc.target/i386/pr9771-1.c 2010-08-12 13:51:16 +0000 | ||
| 214 | @@ -28,7 +28,10 @@ | ||
| 215 | *adr = save; | ||
| 216 | } | ||
| 217 | |||
| 218 | -int main() | ||
| 219 | +/* This must not be inlined becuase main() requires the frame pointer | ||
| 220 | + for stack alignment. */ | ||
| 221 | +void test(void) __attribute__((noinline)); | ||
| 222 | +void test(void) | ||
| 223 | { | ||
| 224 | B = &x; | ||
| 225 | |||
| 226 | @@ -42,3 +45,9 @@ | ||
| 227 | exit(0); | ||
| 228 | } | ||
| 229 | |||
| 230 | +int main() | ||
| 231 | +{ | ||
| 232 | + test(); | ||
| 233 | + return 0; | ||
| 234 | + | ||
| 235 | +} | ||
| 236 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99340.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99340.patch deleted file mode 100644 index 31fa99a2e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99340.patch +++ /dev/null | |||
| @@ -1,43 +0,0 @@ | |||
| 1 | Merge from Sourcery G++ 4.4: | ||
| 2 | |||
| 3 | 2009-08-26 Kazu Hirata <kazu@codesourcery.com> | ||
| 4 | |||
| 5 | Issue #6089 | ||
| 6 | gcc/ | ||
| 7 | * config/arm/arm.c (arm_rtx_costs_1): Don't special case for | ||
| 8 | Thumb-2 in the MINUS case. | ||
| 9 | |||
| 10 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 11 | |||
| 12 | Backport from FSF mainline: | ||
| 13 | |||
| 14 | gcc/ | ||
| 15 | |||
| 16 | === modified file 'gcc/config/arm/arm.c' | ||
| 17 | --- old/gcc/config/arm/arm.c 2010-08-12 13:35:39 +0000 | ||
| 18 | +++ new/gcc/config/arm/arm.c 2010-08-12 14:08:29 +0000 | ||
| 19 | @@ -6494,23 +6494,6 @@ | ||
| 20 | return true; | ||
| 21 | |||
| 22 | case MINUS: | ||
| 23 | - if (TARGET_THUMB2) | ||
| 24 | - { | ||
| 25 | - if (GET_MODE_CLASS (mode) == MODE_FLOAT) | ||
| 26 | - { | ||
| 27 | - if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | ||
| 28 | - *total = COSTS_N_INSNS (1); | ||
| 29 | - else | ||
| 30 | - *total = COSTS_N_INSNS (20); | ||
| 31 | - } | ||
| 32 | - else | ||
| 33 | - *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | ||
| 34 | - /* Thumb2 does not have RSB, so all arguments must be | ||
| 35 | - registers (subtracting a constant is canonicalized as | ||
| 36 | - addition of the negated constant). */ | ||
| 37 | - return false; | ||
| 38 | - } | ||
| 39 | - | ||
| 40 | if (mode == DImode) | ||
| 41 | { | ||
| 42 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | ||
| 43 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99341.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99341.patch deleted file mode 100644 index d9073123c..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99341.patch +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | 2009-08-26 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/config/arm/ | ||
| 4 | * uclinux-eabi.h (LINK_GCC_C_SEQUENCE_SPEC): Override definition | ||
| 5 | for uclinux. | ||
| 6 | |||
| 7 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 8 | |||
| 9 | Merge from Sourcery G++ 4.4: | ||
| 10 | |||
| 11 | 2009-08-26 Kazu Hirata <kazu@codesourcery.com> | ||
| 12 | |||
| 13 | |||
| 14 | === modified file 'gcc/config/arm/uclinux-eabi.h' | ||
| 15 | --- old/gcc/config/arm/uclinux-eabi.h 2009-02-20 15:20:38 +0000 | ||
| 16 | +++ new/gcc/config/arm/uclinux-eabi.h 2010-08-12 15:23:21 +0000 | ||
| 17 | @@ -50,6 +50,10 @@ | ||
| 18 | #undef ARM_DEFAULT_ABI | ||
| 19 | #define ARM_DEFAULT_ABI ARM_ABI_AAPCS_LINUX | ||
| 20 | |||
| 21 | +#undef LINK_GCC_C_SEQUENCE_SPEC | ||
| 22 | +#define LINK_GCC_C_SEQUENCE_SPEC \ | ||
| 23 | + "--start-group %G %L --end-group" | ||
| 24 | + | ||
| 25 | /* Clear the instruction cache from `beg' to `end'. This makes an | ||
| 26 | inline system call to SYS_cacheflush. */ | ||
| 27 | #undef CLEAR_INSN_CACHE | ||
| 28 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch deleted file mode 100644 index 02db2b4e7..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch +++ /dev/null | |||
| @@ -1,76 +0,0 @@ | |||
| 1 | 2010-05-25 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * config/arm/arm.c (arm_tune_cortex_a5): New. | ||
| 5 | (arm_override_options): Set above. Set max_insns_skipped to 1 for | ||
| 6 | Cortex-A5. | ||
| 7 | * config/arm/arm.h (arm_tune_cortex_a5): Add declaration. | ||
| 8 | (BRANCH_COST): Set to zero for Cortex-A5 unless optimising for | ||
| 9 | size. | ||
| 10 | |||
| 11 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 12 | |||
| 13 | Merge from Sourcery G++ 4.4: | ||
| 14 | |||
| 15 | 2009-08-26 Julian Brown <julian@codesourcery.com> | ||
| 16 | |||
| 17 | gcc/config/arm/ | ||
| 18 | |||
| 19 | === modified file 'gcc/config/arm/arm.c' | ||
| 20 | --- old/gcc/config/arm/arm.c 2010-08-12 14:08:29 +0000 | ||
| 21 | +++ new/gcc/config/arm/arm.c 2010-08-12 16:18:41 +0000 | ||
| 22 | @@ -671,6 +671,9 @@ | ||
| 23 | This typically means an ARM6 or ARM7 with MMU or MPU. */ | ||
| 24 | int arm_tune_wbuf = 0; | ||
| 25 | |||
| 26 | +/* Nonzero if tuning for Cortex-A5. */ | ||
| 27 | +int arm_tune_cortex_a5 = 0; | ||
| 28 | + | ||
| 29 | /* Nonzero if tuning for Cortex-A9. */ | ||
| 30 | int arm_tune_cortex_a9 = 0; | ||
| 31 | |||
| 32 | @@ -1582,6 +1585,7 @@ | ||
| 33 | arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; | ||
| 34 | arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; | ||
| 35 | arm_arch_hwdiv = (insn_flags & FL_DIV) != 0; | ||
| 36 | + arm_tune_cortex_a5 = (arm_tune == cortexa5) != 0; | ||
| 37 | arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; | ||
| 38 | |||
| 39 | /* If we are not using the default (ARM mode) section anchor offset | ||
| 40 | @@ -1880,6 +1884,11 @@ | ||
| 41 | that is worth skipping is shorter. */ | ||
| 42 | if (arm_tune_strongarm) | ||
| 43 | max_insns_skipped = 3; | ||
| 44 | + | ||
| 45 | + /* Branches can be dual-issued on Cortex-A5, so conditional execution is | ||
| 46 | + less appealing. */ | ||
| 47 | + if (arm_tune_cortex_a5) | ||
| 48 | + max_insns_skipped = 1; | ||
| 49 | } | ||
| 50 | |||
| 51 | /* Hot/Cold partitioning is not currently supported, since we can't | ||
| 52 | |||
| 53 | === modified file 'gcc/config/arm/arm.h' | ||
| 54 | --- old/gcc/config/arm/arm.h 2010-08-05 16:34:46 +0000 | ||
| 55 | +++ new/gcc/config/arm/arm.h 2010-08-12 16:18:41 +0000 | ||
| 56 | @@ -435,6 +435,9 @@ | ||
| 57 | /* Nonzero if tuning for stores via the write buffer. */ | ||
| 58 | extern int arm_tune_wbuf; | ||
| 59 | |||
| 60 | +/* Nonzero if tuning for Cortex-A5. */ | ||
| 61 | +extern int arm_tune_cortex_a5; | ||
| 62 | + | ||
| 63 | /* Nonzero if tuning for Cortex-A9. */ | ||
| 64 | extern int arm_tune_cortex_a9; | ||
| 65 | |||
| 66 | @@ -2222,7 +2225,8 @@ | ||
| 67 | /* Try to generate sequences that don't involve branches, we can then use | ||
| 68 | conditional instructions */ | ||
| 69 | #define BRANCH_COST(speed_p, predictable_p) \ | ||
| 70 | - (TARGET_32BIT ? (TARGET_THUMB2 && optimize_size ? 1 : 4) \ | ||
| 71 | + (TARGET_32BIT ? ((arm_tune_cortex_a5 && !optimize_size) ? 0 \ | ||
| 72 | + : (TARGET_THUMB2 && optimize_size ? 1 : 4)) \ | ||
| 73 | : (optimize > 0 ? 2 : 0)) | ||
| 74 | |||
| 75 | /* Position Independent Code. */ | ||
| 76 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99343.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99343.patch deleted file mode 100644 index 86b2d8109..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99343.patch +++ /dev/null | |||
| @@ -1,132 +0,0 @@ | |||
| 1 | Backport from FSF mainline: | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * config/arm/thumb2.md (*thumb2_addsi3_compare0): New. | ||
| 5 | (*thumb2_addsi3_compare0_scratch): New. | ||
| 6 | * config/arm/constraints.md (Pv): New. | ||
| 7 | * config/arm/arm.md (*addsi3_compare0): Remove FIXME comment. Use | ||
| 8 | for ARM mode only. | ||
| 9 | (*addsi3_compare0_scratch): Likewise. | ||
| 10 | |||
| 11 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 12 | |||
| 13 | Merge from Sourcery G++ 4.4: | ||
| 14 | |||
| 15 | 2010-05-25 Julian Brown <julian@codesourcery.com> | ||
| 16 | |||
| 17 | === modified file 'gcc/config/arm/arm.md' | ||
| 18 | --- old/gcc/config/arm/arm.md 2010-08-12 13:35:39 +0000 | ||
| 19 | +++ new/gcc/config/arm/arm.md 2010-08-12 16:47:21 +0000 | ||
| 20 | @@ -701,7 +701,6 @@ | ||
| 21 | "" | ||
| 22 | ) | ||
| 23 | |||
| 24 | -;; ??? Make Thumb-2 variants which prefer low regs | ||
| 25 | (define_insn "*addsi3_compare0" | ||
| 26 | [(set (reg:CC_NOOV CC_REGNUM) | ||
| 27 | (compare:CC_NOOV | ||
| 28 | @@ -710,7 +709,7 @@ | ||
| 29 | (const_int 0))) | ||
| 30 | (set (match_operand:SI 0 "s_register_operand" "=r,r") | ||
| 31 | (plus:SI (match_dup 1) (match_dup 2)))] | ||
| 32 | - "TARGET_32BIT" | ||
| 33 | + "TARGET_ARM" | ||
| 34 | "@ | ||
| 35 | add%.\\t%0, %1, %2 | ||
| 36 | sub%.\\t%0, %1, #%n2" | ||
| 37 | @@ -723,7 +722,7 @@ | ||
| 38 | (plus:SI (match_operand:SI 0 "s_register_operand" "r, r") | ||
| 39 | (match_operand:SI 1 "arm_add_operand" "rI,L")) | ||
| 40 | (const_int 0)))] | ||
| 41 | - "TARGET_32BIT" | ||
| 42 | + "TARGET_ARM" | ||
| 43 | "@ | ||
| 44 | cmn%?\\t%0, %1 | ||
| 45 | cmp%?\\t%0, #%n1" | ||
| 46 | |||
| 47 | === modified file 'gcc/config/arm/constraints.md' | ||
| 48 | --- old/gcc/config/arm/constraints.md 2010-07-29 16:58:56 +0000 | ||
| 49 | +++ new/gcc/config/arm/constraints.md 2010-08-12 16:47:21 +0000 | ||
| 50 | @@ -31,7 +31,7 @@ | ||
| 51 | ;; The following multi-letter normal constraints have been used: | ||
| 52 | ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di | ||
| 53 | ;; in Thumb-1 state: Pa, Pb | ||
| 54 | -;; in Thumb-2 state: Ps, Pt | ||
| 55 | +;; in Thumb-2 state: Ps, Pt, Pv | ||
| 56 | |||
| 57 | ;; The following memory constraints have been used: | ||
| 58 | ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us | ||
| 59 | @@ -158,6 +158,11 @@ | ||
| 60 | (and (match_code "const_int") | ||
| 61 | (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7"))) | ||
| 62 | |||
| 63 | +(define_constraint "Pv" | ||
| 64 | + "@internal In Thumb-2 state a constant in the range -255 to 0" | ||
| 65 | + (and (match_code "const_int") | ||
| 66 | + (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0"))) | ||
| 67 | + | ||
| 68 | (define_constraint "G" | ||
| 69 | "In ARM/Thumb-2 state a valid FPA immediate constant." | ||
| 70 | (and (match_code "const_double") | ||
| 71 | |||
| 72 | === modified file 'gcc/config/arm/thumb2.md' | ||
| 73 | --- old/gcc/config/arm/thumb2.md 2010-08-05 16:34:46 +0000 | ||
| 74 | +++ new/gcc/config/arm/thumb2.md 2010-08-12 16:47:21 +0000 | ||
| 75 | @@ -1241,6 +1241,56 @@ | ||
| 76 | (set_attr "length" "2")] | ||
| 77 | ) | ||
| 78 | |||
| 79 | +(define_insn "*thumb2_addsi3_compare0" | ||
| 80 | + [(set (reg:CC_NOOV CC_REGNUM) | ||
| 81 | + (compare:CC_NOOV | ||
| 82 | + (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r") | ||
| 83 | + (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL")) | ||
| 84 | + (const_int 0))) | ||
| 85 | + (set (match_operand:SI 0 "s_register_operand" "=l,l,r") | ||
| 86 | + (plus:SI (match_dup 1) (match_dup 2)))] | ||
| 87 | + "TARGET_THUMB2" | ||
| 88 | + "* | ||
| 89 | + HOST_WIDE_INT val; | ||
| 90 | + | ||
| 91 | + if (GET_CODE (operands[2]) == CONST_INT) | ||
| 92 | + val = INTVAL (operands[2]); | ||
| 93 | + else | ||
| 94 | + val = 0; | ||
| 95 | + | ||
| 96 | + if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val))) | ||
| 97 | + return \"subs\\t%0, %1, #%n2\"; | ||
| 98 | + else | ||
| 99 | + return \"adds\\t%0, %1, %2\"; | ||
| 100 | + " | ||
| 101 | + [(set_attr "conds" "set") | ||
| 102 | + (set_attr "length" "2,2,4")] | ||
| 103 | +) | ||
| 104 | + | ||
| 105 | +(define_insn "*thumb2_addsi3_compare0_scratch" | ||
| 106 | + [(set (reg:CC_NOOV CC_REGNUM) | ||
| 107 | + (compare:CC_NOOV | ||
| 108 | + (plus:SI (match_operand:SI 0 "s_register_operand" "l, r") | ||
| 109 | + (match_operand:SI 1 "arm_add_operand" "lPv,rIL")) | ||
| 110 | + (const_int 0)))] | ||
| 111 | + "TARGET_THUMB2" | ||
| 112 | + "* | ||
| 113 | + HOST_WIDE_INT val; | ||
| 114 | + | ||
| 115 | + if (GET_CODE (operands[1]) == CONST_INT) | ||
| 116 | + val = INTVAL (operands[1]); | ||
| 117 | + else | ||
| 118 | + val = 0; | ||
| 119 | + | ||
| 120 | + if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val))) | ||
| 121 | + return \"cmp\\t%0, #%n1\"; | ||
| 122 | + else | ||
| 123 | + return \"cmn\\t%0, %1\"; | ||
| 124 | + " | ||
| 125 | + [(set_attr "conds" "set") | ||
| 126 | + (set_attr "length" "2,4")] | ||
| 127 | +) | ||
| 128 | + | ||
| 129 | ;; 16-bit encodings of "muls" and "mul<c>". We only use these when | ||
| 130 | ;; optimizing for size since "muls" is slow on all known | ||
| 131 | ;; implementations and since "mul<c>" will be generated by | ||
| 132 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99344.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99344.patch deleted file mode 100644 index d03ee9406..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99344.patch +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | 2010-02-03 Daniel Gutson <dgutson@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #6472 | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * config/arm/lib1funcs.asm (__ARM_ARCH__): __ARM_ARCH_7EM__ | ||
| 7 | added to the preprocessor condition. | ||
| 8 | |||
| 9 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 10 | |||
| 11 | Backport from FSF mainline: | ||
| 12 | |||
| 13 | gcc/ | ||
| 14 | * config/arm/thumb2.md (*thumb2_addsi3_compare0): New. | ||
| 15 | (*thumb2_addsi3_compare0_scratch): New. | ||
| 16 | |||
| 17 | === modified file 'gcc/config/arm/lib1funcs.asm' | ||
| 18 | --- old/gcc/config/arm/lib1funcs.asm 2010-08-05 15:20:54 +0000 | ||
| 19 | +++ new/gcc/config/arm/lib1funcs.asm 2010-08-12 16:49:44 +0000 | ||
| 20 | @@ -104,7 +104,8 @@ | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ | ||
| 24 | - || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) | ||
| 25 | + || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ | ||
| 26 | + || defined(__ARM_ARCH_7EM__) | ||
| 27 | # define __ARM_ARCH__ 7 | ||
| 28 | #endif | ||
| 29 | |||
| 30 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99345.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99345.patch deleted file mode 100644 index 757e66c8b..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99345.patch +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | Merge from Sourcery G++ 4.4: | ||
| 2 | |||
| 3 | 2010-02-04 Daniel Jacobowitz <dan@codesourcery.com> | ||
| 4 | |||
| 5 | Issue #7197 - backtrace() through throw() | ||
| 6 | |||
| 7 | libstdc++-v3/ | ||
| 8 | * libsupc++/eh_personality.cc (PERSONALITY_FUNCTION): For | ||
| 9 | ARM EABI, skip handlers for _US_VIRTUAL_UNWIND_FRAME | ||
| 10 | | _US_FORCE_UNWIND. | ||
| 11 | |||
| 12 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 13 | |||
| 14 | Backport from FSF mainline: | ||
| 15 | |||
| 16 | 2010-02-03 Daniel Gutson <dgutson@codesourcery.com> | ||
| 17 | |||
| 18 | === modified file 'libstdc++-v3/libsupc++/eh_personality.cc' | ||
| 19 | --- old/libstdc++-v3/libsupc++/eh_personality.cc 2010-02-17 05:43:24 +0000 | ||
| 20 | +++ new/libstdc++-v3/libsupc++/eh_personality.cc 2010-08-12 16:53:10 +0000 | ||
| 21 | @@ -383,6 +383,8 @@ | ||
| 22 | switch (state & _US_ACTION_MASK) | ||
| 23 | { | ||
| 24 | case _US_VIRTUAL_UNWIND_FRAME: | ||
| 25 | + if (state & _US_FORCE_UNWIND) | ||
| 26 | + CONTINUE_UNWINDING; | ||
| 27 | actions = _UA_SEARCH_PHASE; | ||
| 28 | break; | ||
| 29 | |||
| 30 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch deleted file mode 100644 index 480719515..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch +++ /dev/null | |||
| @@ -1,170 +0,0 @@ | |||
| 1 | Backport from FSF mainline: | ||
| 2 | |||
| 3 | Julian Brown <julian@codesourcery.com> | ||
| 4 | Mark Mitchell <mark@codesourcery.com> | ||
| 5 | |||
| 6 | gcc/ | ||
| 7 | * config/arm/arm.c (arm_function_ok_for_sibcall): Only forbid | ||
| 8 | sibling calls for Thumb-1. | ||
| 9 | * config/arm/arm.h (USE_RETURN_INSN): Enable for Thumb-2. | ||
| 10 | * config/arm/arm.md (*call_symbol, *call_value_symbol): Use for | ||
| 11 | Thumb-2. | ||
| 12 | (*call_insn, *call_value_insn): Don't use for Thumb-2. | ||
| 13 | (sibcall, sibcall_value, *sibcall_insn, *sibcall_value_insn): Use | ||
| 14 | for Thumb-2. | ||
| 15 | (return): New expander. | ||
| 16 | (*arm_return): New name for ARM return insn. | ||
| 17 | * config/arm/thumb2.md (*thumb2_return): New insn pattern. | ||
| 18 | |||
| 19 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 20 | |||
| 21 | Merge from Sourcery G++ 4.4: | ||
| 22 | |||
| 23 | 2010-02-04 Daniel Jacobowitz <dan@codesourcery.com> | ||
| 24 | |||
| 25 | === modified file 'gcc/config/arm/arm.c' | ||
| 26 | --- old/gcc/config/arm/arm.c 2010-08-12 16:18:41 +0000 | ||
| 27 | +++ new/gcc/config/arm/arm.c 2010-08-13 10:30:35 +0000 | ||
| 28 | @@ -4886,8 +4886,8 @@ | ||
| 29 | return false; | ||
| 30 | |||
| 31 | /* Never tailcall something for which we have no decl, or if we | ||
| 32 | - are in Thumb mode. */ | ||
| 33 | - if (decl == NULL || TARGET_THUMB) | ||
| 34 | + are generating code for Thumb-1. */ | ||
| 35 | + if (decl == NULL || TARGET_THUMB1) | ||
| 36 | return false; | ||
| 37 | |||
| 38 | /* The PIC register is live on entry to VxWorks PLT entries, so we | ||
| 39 | |||
| 40 | === modified file 'gcc/config/arm/arm.h' | ||
| 41 | --- old/gcc/config/arm/arm.h 2010-08-12 16:18:41 +0000 | ||
| 42 | +++ new/gcc/config/arm/arm.h 2010-08-13 10:30:35 +0000 | ||
| 43 | @@ -1833,11 +1833,8 @@ | ||
| 44 | |||
| 45 | /* Determine if the epilogue should be output as RTL. | ||
| 46 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | ||
| 47 | -/* This is disabled for Thumb-2 because it will confuse the | ||
| 48 | - conditional insn counter. | ||
| 49 | - Do not use a return insn if we're avoiding ldm/stm instructions. */ | ||
| 50 | #define USE_RETURN_INSN(ISCOND) \ | ||
| 51 | - ((TARGET_ARM && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0) | ||
| 52 | + ((TARGET_32BIT && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0) | ||
| 53 | |||
| 54 | /* Definitions for register eliminations. | ||
| 55 | |||
| 56 | |||
| 57 | === modified file 'gcc/config/arm/arm.md' | ||
| 58 | --- old/gcc/config/arm/arm.md 2010-08-12 16:47:21 +0000 | ||
| 59 | +++ new/gcc/config/arm/arm.md 2010-08-13 10:30:35 +0000 | ||
| 60 | @@ -8798,7 +8798,7 @@ | ||
| 61 | (match_operand 1 "" "")) | ||
| 62 | (use (match_operand 2 "" "")) | ||
| 63 | (clobber (reg:SI LR_REGNUM))] | ||
| 64 | - "TARGET_ARM | ||
| 65 | + "TARGET_32BIT | ||
| 66 | && (GET_CODE (operands[0]) == SYMBOL_REF) | ||
| 67 | && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" | ||
| 68 | "* | ||
| 69 | @@ -8814,7 +8814,7 @@ | ||
| 70 | (match_operand:SI 2 "" ""))) | ||
| 71 | (use (match_operand 3 "" "")) | ||
| 72 | (clobber (reg:SI LR_REGNUM))] | ||
| 73 | - "TARGET_ARM | ||
| 74 | + "TARGET_32BIT | ||
| 75 | && (GET_CODE (operands[1]) == SYMBOL_REF) | ||
| 76 | && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" | ||
| 77 | "* | ||
| 78 | @@ -8829,7 +8829,7 @@ | ||
| 79 | (match_operand:SI 1 "" "")) | ||
| 80 | (use (match_operand 2 "" "")) | ||
| 81 | (clobber (reg:SI LR_REGNUM))] | ||
| 82 | - "TARGET_THUMB | ||
| 83 | + "TARGET_THUMB1 | ||
| 84 | && GET_CODE (operands[0]) == SYMBOL_REF | ||
| 85 | && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))" | ||
| 86 | "bl\\t%a0" | ||
| 87 | @@ -8843,7 +8843,7 @@ | ||
| 88 | (match_operand 2 "" ""))) | ||
| 89 | (use (match_operand 3 "" "")) | ||
| 90 | (clobber (reg:SI LR_REGNUM))] | ||
| 91 | - "TARGET_THUMB | ||
| 92 | + "TARGET_THUMB1 | ||
| 93 | && GET_CODE (operands[1]) == SYMBOL_REF | ||
| 94 | && !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))" | ||
| 95 | "bl\\t%a1" | ||
| 96 | @@ -8857,7 +8857,7 @@ | ||
| 97 | (match_operand 1 "general_operand" "")) | ||
| 98 | (return) | ||
| 99 | (use (match_operand 2 "" ""))])] | ||
| 100 | - "TARGET_ARM" | ||
| 101 | + "TARGET_32BIT" | ||
| 102 | " | ||
| 103 | { | ||
| 104 | if (operands[2] == NULL_RTX) | ||
| 105 | @@ -8871,7 +8871,7 @@ | ||
| 106 | (match_operand 2 "general_operand" ""))) | ||
| 107 | (return) | ||
| 108 | (use (match_operand 3 "" ""))])] | ||
| 109 | - "TARGET_ARM" | ||
| 110 | + "TARGET_32BIT" | ||
| 111 | " | ||
| 112 | { | ||
| 113 | if (operands[3] == NULL_RTX) | ||
| 114 | @@ -8884,7 +8884,7 @@ | ||
| 115 | (match_operand 1 "" "")) | ||
| 116 | (return) | ||
| 117 | (use (match_operand 2 "" ""))] | ||
| 118 | - "TARGET_ARM && GET_CODE (operands[0]) == SYMBOL_REF" | ||
| 119 | + "TARGET_32BIT && GET_CODE (operands[0]) == SYMBOL_REF" | ||
| 120 | "* | ||
| 121 | return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; | ||
| 122 | " | ||
| 123 | @@ -8897,15 +8897,20 @@ | ||
| 124 | (match_operand 2 "" ""))) | ||
| 125 | (return) | ||
| 126 | (use (match_operand 3 "" ""))] | ||
| 127 | - "TARGET_ARM && GET_CODE (operands[1]) == SYMBOL_REF" | ||
| 128 | + "TARGET_32BIT && GET_CODE (operands[1]) == SYMBOL_REF" | ||
| 129 | "* | ||
| 130 | return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; | ||
| 131 | " | ||
| 132 | [(set_attr "type" "call")] | ||
| 133 | ) | ||
| 134 | |||
| 135 | +(define_expand "return" | ||
| 136 | + [(return)] | ||
| 137 | + "TARGET_32BIT && USE_RETURN_INSN (FALSE)" | ||
| 138 | + "") | ||
| 139 | + | ||
| 140 | ;; Often the return insn will be the same as loading from memory, so set attr | ||
| 141 | -(define_insn "return" | ||
| 142 | +(define_insn "*arm_return" | ||
| 143 | [(return)] | ||
| 144 | "TARGET_ARM && USE_RETURN_INSN (FALSE)" | ||
| 145 | "* | ||
| 146 | |||
| 147 | === modified file 'gcc/config/arm/thumb2.md' | ||
| 148 | --- old/gcc/config/arm/thumb2.md 2010-08-12 16:47:21 +0000 | ||
| 149 | +++ new/gcc/config/arm/thumb2.md 2010-08-13 10:30:35 +0000 | ||
| 150 | @@ -1054,6 +1054,19 @@ | ||
| 151 | (set_attr "length" "20")] | ||
| 152 | ) | ||
| 153 | |||
| 154 | +;; Note: this is not predicable, to avoid issues with linker-generated | ||
| 155 | +;; interworking stubs. | ||
| 156 | +(define_insn "*thumb2_return" | ||
| 157 | + [(return)] | ||
| 158 | + "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)" | ||
| 159 | + "* | ||
| 160 | + { | ||
| 161 | + return output_return_instruction (const_true_rtx, TRUE, FALSE); | ||
| 162 | + }" | ||
| 163 | + [(set_attr "type" "load1") | ||
| 164 | + (set_attr "length" "12")] | ||
| 165 | +) | ||
| 166 | + | ||
| 167 | (define_insn_and_split "thumb2_eh_return" | ||
| 168 | [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")] | ||
| 169 | VUNSPEC_EH_RETURN) | ||
| 170 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99348.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99348.patch deleted file mode 100644 index f99938a7f..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99348.patch +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | 2010-02-23 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * calls.c (precompute_register_parameters): Avoid generating a | ||
| 5 | register move if optimizing for size. | ||
| 6 | |||
| 7 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 8 | |||
| 9 | Merge from Sourcery G++ 4.4: | ||
| 10 | |||
| 11 | 2010-02-15 Julian Brown <julian@codesourcery.com> | ||
| 12 | |||
| 13 | Issue #7486 | ||
| 14 | |||
| 15 | === modified file 'gcc/calls.c' | ||
| 16 | --- old/gcc/calls.c 2010-04-02 18:54:46 +0000 | ||
| 17 | +++ new/gcc/calls.c 2010-08-13 10:50:45 +0000 | ||
| 18 | @@ -703,7 +703,9 @@ | ||
| 19 | |||
| 20 | For small register classes, also do this if this call uses | ||
| 21 | register parameters. This is to avoid reload conflicts while | ||
| 22 | - loading the parameters registers. */ | ||
| 23 | + loading the parameters registers. | ||
| 24 | + | ||
| 25 | + Avoid creating the extra move if optimizing for size. */ | ||
| 26 | |||
| 27 | else if ((! (REG_P (args[i].value) | ||
| 28 | || (GET_CODE (args[i].value) == SUBREG | ||
| 29 | @@ -711,6 +713,7 @@ | ||
| 30 | && args[i].mode != BLKmode | ||
| 31 | && rtx_cost (args[i].value, SET, optimize_insn_for_speed_p ()) | ||
| 32 | > COSTS_N_INSNS (1) | ||
| 33 | + && !optimize_size | ||
| 34 | && ((SMALL_REGISTER_CLASSES && *reg_parm_seen) | ||
| 35 | || optimize)) | ||
| 36 | args[i].value = copy_to_mode_reg (args[i].mode, args[i].value); | ||
| 37 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99349.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99349.patch deleted file mode 100644 index a95b649e4..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99349.patch +++ /dev/null | |||
| @@ -1,401 +0,0 @@ | |||
| 1 | * config/arm/arm.c (thumb2_size_rtx_costs): New. | ||
| 2 | (arm_rtx_costs): Call above for Thumb-2. | ||
| 3 | |||
| 4 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 5 | |||
| 6 | Merge from Sourcery G++ 4.4: | ||
| 7 | |||
| 8 | 2010-02-23 Julian Brown <julian@codesourcery.com> | ||
| 9 | |||
| 10 | gcc/ | ||
| 11 | * calls.c (precompute_register_parameters): Avoid generating a | ||
| 12 | register move if optimizing for size. | ||
| 13 | |||
| 14 | |||
| 15 | === modified file 'gcc/config/arm/arm.c' | ||
| 16 | --- old/gcc/config/arm/arm.c 2010-08-13 10:43:42 +0000 | ||
| 17 | +++ new/gcc/config/arm/arm.c 2010-08-13 10:55:28 +0000 | ||
| 18 | @@ -141,6 +141,7 @@ | ||
| 19 | static bool arm_have_conditional_execution (void); | ||
| 20 | static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool); | ||
| 21 | static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); | ||
| 22 | +static bool thumb2_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); | ||
| 23 | static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | ||
| 24 | static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | ||
| 25 | static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | ||
| 26 | @@ -7316,14 +7317,372 @@ | ||
| 27 | } | ||
| 28 | } | ||
| 29 | |||
| 30 | +static bool | ||
| 31 | +thumb2_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, | ||
| 32 | + int *total) | ||
| 33 | +{ | ||
| 34 | + /* Attempt to give a lower cost to RTXs which can optimistically be | ||
| 35 | + represented as short insns, assuming that the right conditions will hold | ||
| 36 | + later (e.g. low registers will be chosen if a short insn requires them). | ||
| 37 | + | ||
| 38 | + Note that we don't make wide insns cost twice as much as narrow insns, | ||
| 39 | + because we can't prove that a particular RTX will actually use a narrow | ||
| 40 | + insn, because not enough information is available (e.g., we don't know | ||
| 41 | + which hard registers pseudos will be assigned). Consider these to be | ||
| 42 | + "expected" sizes/weightings. | ||
| 43 | + | ||
| 44 | + (COSTS_NARROW_INSNS has the same weight as COSTS_N_INSNS.) */ | ||
| 45 | + | ||
| 46 | +#define COSTS_NARROW_INSNS(N) ((N) * 4) | ||
| 47 | +#define COSTS_WIDE_INSNS(N) ((N) * 6) | ||
| 48 | +#define THUMB2_LIBCALL_COST COSTS_WIDE_INSNS (2) | ||
| 49 | + enum machine_mode mode = GET_MODE (x); | ||
| 50 | + | ||
| 51 | + switch (code) | ||
| 52 | + { | ||
| 53 | + case MEM: | ||
| 54 | + if (REG_P (XEXP (x, 0))) | ||
| 55 | + { | ||
| 56 | + /* Hopefully this will use a narrow ldm/stm insn. */ | ||
| 57 | + *total = COSTS_NARROW_INSNS (1); | ||
| 58 | + return true; | ||
| 59 | + } | ||
| 60 | + else if ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF | ||
| 61 | + && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))) | ||
| 62 | + || reg_mentioned_p (virtual_stack_vars_rtx, XEXP (x, 0)) | ||
| 63 | + || reg_mentioned_p (stack_pointer_rtx, XEXP (x, 0))) | ||
| 64 | + { | ||
| 65 | + *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)); | ||
| 66 | + return true; | ||
| 67 | + } | ||
| 68 | + else if (GET_CODE (XEXP (x, 0)) == PLUS) | ||
| 69 | + { | ||
| 70 | + rtx plus = XEXP (x, 0); | ||
| 71 | + | ||
| 72 | + if (GET_CODE (XEXP (plus, 1)) == CONST_INT) | ||
| 73 | + { | ||
| 74 | + HOST_WIDE_INT cst = INTVAL (XEXP (plus, 1)); | ||
| 75 | + | ||
| 76 | + if (cst >= 0 && cst < 256) | ||
| 77 | + *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)); | ||
| 78 | + else | ||
| 79 | + *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); | ||
| 80 | + | ||
| 81 | + *total += rtx_cost (XEXP (plus, 0), code, false); | ||
| 82 | + | ||
| 83 | + return true; | ||
| 84 | + } | ||
| 85 | + } | ||
| 86 | + | ||
| 87 | + *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)); | ||
| 88 | + return false; | ||
| 89 | + | ||
| 90 | + case DIV: | ||
| 91 | + case MOD: | ||
| 92 | + case UDIV: | ||
| 93 | + case UMOD: | ||
| 94 | + if (arm_arch_hwdiv) | ||
| 95 | + *total = COSTS_WIDE_INSNS (1); | ||
| 96 | + else | ||
| 97 | + *total = THUMB2_LIBCALL_COST; | ||
| 98 | + return false; | ||
| 99 | + | ||
| 100 | + case ROTATE: | ||
| 101 | + if (mode == SImode && REG_P (XEXP (x, 1))) | ||
| 102 | + { | ||
| 103 | + *total = COSTS_WIDE_INSNS (1) + COSTS_NARROW_INSNS (1) | ||
| 104 | + + rtx_cost (XEXP (x, 0), code, false); | ||
| 105 | + return true; | ||
| 106 | + } | ||
| 107 | + /* Fall through */ | ||
| 108 | + | ||
| 109 | + case ASHIFT: | ||
| 110 | + case LSHIFTRT: | ||
| 111 | + case ASHIFTRT: | ||
| 112 | + if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) | ||
| 113 | + { | ||
| 114 | + *total = COSTS_WIDE_INSNS (3) + rtx_cost (XEXP (x, 0), code, false); | ||
| 115 | + return true; | ||
| 116 | + } | ||
| 117 | + else if (mode == SImode) | ||
| 118 | + { | ||
| 119 | + *total = COSTS_NARROW_INSNS (1); | ||
| 120 | + return false; | ||
| 121 | + } | ||
| 122 | + | ||
| 123 | + /* Needs a libcall. */ | ||
| 124 | + *total = THUMB2_LIBCALL_COST; | ||
| 125 | + return false; | ||
| 126 | + | ||
| 127 | + case ROTATERT: | ||
| 128 | + if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) | ||
| 129 | + { | ||
| 130 | + *total = COSTS_WIDE_INSNS (3) + rtx_cost (XEXP (x, 0), code, false); | ||
| 131 | + return true; | ||
| 132 | + } | ||
| 133 | + else if (mode == SImode) | ||
| 134 | + { | ||
| 135 | + if (GET_CODE (XEXP (x, 1)) == CONST_INT) | ||
| 136 | + *total = COSTS_WIDE_INSNS (1) + rtx_cost (XEXP (x, 0), code, false); | ||
| 137 | + else | ||
| 138 | + *total = COSTS_NARROW_INSNS (1) | ||
| 139 | + + rtx_cost (XEXP (x, 0), code, false); | ||
| 140 | + return true; | ||
| 141 | + } | ||
| 142 | + | ||
| 143 | + /* Needs a libcall. */ | ||
| 144 | + *total = THUMB2_LIBCALL_COST; | ||
| 145 | + return false; | ||
| 146 | + | ||
| 147 | + case MINUS: | ||
| 148 | + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT | ||
| 149 | + && (mode == SFmode || !TARGET_VFP_SINGLE)) | ||
| 150 | + { | ||
| 151 | + *total = COSTS_WIDE_INSNS (1); | ||
| 152 | + return false; | ||
| 153 | + } | ||
| 154 | + | ||
| 155 | + if (mode == SImode) | ||
| 156 | + { | ||
| 157 | + enum rtx_code subcode0 = GET_CODE (XEXP (x, 0)); | ||
| 158 | + enum rtx_code subcode1 = GET_CODE (XEXP (x, 1)); | ||
| 159 | + | ||
| 160 | + if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT | ||
| 161 | + || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT | ||
| 162 | + || subcode1 == ROTATE || subcode1 == ROTATERT | ||
| 163 | + || subcode1 == ASHIFT || subcode1 == LSHIFTRT | ||
| 164 | + || subcode1 == ASHIFTRT) | ||
| 165 | + { | ||
| 166 | + /* It's just the cost of the two operands. */ | ||
| 167 | + *total = 0; | ||
| 168 | + return false; | ||
| 169 | + } | ||
| 170 | + | ||
| 171 | + if (subcode1 == CONST_INT) | ||
| 172 | + { | ||
| 173 | + HOST_WIDE_INT cst = INTVAL (XEXP (x, 1)); | ||
| 174 | + | ||
| 175 | + if (cst >= 0 && cst < 256) | ||
| 176 | + *total = COSTS_NARROW_INSNS (1); | ||
| 177 | + else | ||
| 178 | + *total = COSTS_WIDE_INSNS (1); | ||
| 179 | + | ||
| 180 | + *total += rtx_cost (XEXP (x, 0), code, false); | ||
| 181 | + | ||
| 182 | + return true; | ||
| 183 | + } | ||
| 184 | + | ||
| 185 | + *total = COSTS_NARROW_INSNS (1); | ||
| 186 | + return false; | ||
| 187 | + } | ||
| 188 | + | ||
| 189 | + *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); | ||
| 190 | + return false; | ||
| 191 | + | ||
| 192 | + case PLUS: | ||
| 193 | + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT | ||
| 194 | + && (mode == SFmode || !TARGET_VFP_SINGLE)) | ||
| 195 | + { | ||
| 196 | + *total = COSTS_WIDE_INSNS (1); | ||
| 197 | + return false; | ||
| 198 | + } | ||
| 199 | + | ||
| 200 | + /* Fall through */ | ||
| 201 | + case AND: case XOR: case IOR: | ||
| 202 | + if (mode == SImode) | ||
| 203 | + { | ||
| 204 | + enum rtx_code subcode = GET_CODE (XEXP (x, 0)); | ||
| 205 | + | ||
| 206 | + if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT | ||
| 207 | + || subcode == LSHIFTRT || subcode == ASHIFTRT | ||
| 208 | + || (code == AND && subcode == NOT)) | ||
| 209 | + { | ||
| 210 | + /* It's just the cost of the two operands. */ | ||
| 211 | + *total = 0; | ||
| 212 | + return false; | ||
| 213 | + } | ||
| 214 | + | ||
| 215 | + if (code == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | ||
| 216 | + { | ||
| 217 | + HOST_WIDE_INT cst = INTVAL (XEXP (x, 1)); | ||
| 218 | + | ||
| 219 | + if ((reg_mentioned_p (virtual_stack_vars_rtx, XEXP (x, 0)) | ||
| 220 | + || reg_mentioned_p (stack_pointer_rtx, XEXP (x, 0))) | ||
| 221 | + && cst > -512 && cst < 1024) | ||
| 222 | + /* Only approximately correct, depending on destination | ||
| 223 | + register. */ | ||
| 224 | + *total = COSTS_NARROW_INSNS (1); | ||
| 225 | + else if (cst > -256 && cst < 256) | ||
| 226 | + *total = COSTS_NARROW_INSNS (1); | ||
| 227 | + else | ||
| 228 | + *total = COSTS_WIDE_INSNS (1); | ||
| 229 | + | ||
| 230 | + *total += rtx_cost (XEXP (x, 0), code, false); | ||
| 231 | + | ||
| 232 | + return true; | ||
| 233 | + } | ||
| 234 | + | ||
| 235 | + if (subcode == MULT | ||
| 236 | + && power_of_two_operand (XEXP (XEXP (x, 0), 1), mode)) | ||
| 237 | + { | ||
| 238 | + *total = COSTS_WIDE_INSNS (1) | ||
| 239 | + + rtx_cost (XEXP (x, 1), code, false); | ||
| 240 | + return true; | ||
| 241 | + } | ||
| 242 | + } | ||
| 243 | + | ||
| 244 | + *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)); | ||
| 245 | + return false; | ||
| 246 | + | ||
| 247 | + case MULT: | ||
| 248 | + if (mode == SImode && GET_CODE (XEXP (x, 1)) != CONST_INT) | ||
| 249 | + { | ||
| 250 | + /* Might be using muls. */ | ||
| 251 | + *total = COSTS_NARROW_INSNS (1); | ||
| 252 | + return false; | ||
| 253 | + } | ||
| 254 | + *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); | ||
| 255 | + return false; | ||
| 256 | + | ||
| 257 | + case NEG: | ||
| 258 | + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT | ||
| 259 | + && (mode == SFmode || !TARGET_VFP_SINGLE)) | ||
| 260 | + { | ||
| 261 | + *total = COSTS_WIDE_INSNS (1); | ||
| 262 | + return false; | ||
| 263 | + } | ||
| 264 | + | ||
| 265 | + /* Fall through */ | ||
| 266 | + case NOT: | ||
| 267 | + if (mode == SImode) | ||
| 268 | + { | ||
| 269 | + *total = COSTS_NARROW_INSNS (1); | ||
| 270 | + return false; | ||
| 271 | + } | ||
| 272 | + *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); | ||
| 273 | + return false; | ||
| 274 | + | ||
| 275 | + case IF_THEN_ELSE: | ||
| 276 | + *total = COSTS_NARROW_INSNS (1); | ||
| 277 | + return false; | ||
| 278 | + | ||
| 279 | + case COMPARE: | ||
| 280 | + if (cc_register (XEXP (x, 0), VOIDmode)) | ||
| 281 | + *total = 0; | ||
| 282 | + else | ||
| 283 | + *total = COSTS_NARROW_INSNS (1); | ||
| 284 | + return false; | ||
| 285 | + | ||
| 286 | + case ABS: | ||
| 287 | + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT | ||
| 288 | + && (mode == SFmode || !TARGET_VFP_SINGLE)) | ||
| 289 | + *total = COSTS_WIDE_INSNS (1); | ||
| 290 | + else | ||
| 291 | + *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)) * 2; | ||
| 292 | + return false; | ||
| 293 | + | ||
| 294 | + case SIGN_EXTEND: | ||
| 295 | + if (GET_MODE_SIZE (mode) <= 4) | ||
| 296 | + *total = GET_CODE (XEXP (x, 0)) == MEM ? 0 : COSTS_NARROW_INSNS (1); | ||
| 297 | + else | ||
| 298 | + *total = COSTS_NARROW_INSNS (1) | ||
| 299 | + + COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); | ||
| 300 | + return false; | ||
| 301 | + | ||
| 302 | + case ZERO_EXTEND: | ||
| 303 | + if (GET_MODE_SIZE (mode) > 4) | ||
| 304 | + *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode) - 1); | ||
| 305 | + else if (GET_CODE (XEXP (x, 0)) == MEM) | ||
| 306 | + *total = 0; | ||
| 307 | + else | ||
| 308 | + *total = COSTS_NARROW_INSNS (1); | ||
| 309 | + return false; | ||
| 310 | + | ||
| 311 | + case CONST_INT: | ||
| 312 | + { | ||
| 313 | + HOST_WIDE_INT cst = INTVAL (x); | ||
| 314 | + | ||
| 315 | + switch (outer_code) | ||
| 316 | + { | ||
| 317 | + case PLUS: | ||
| 318 | + if (cst > -256 && cst < 256) | ||
| 319 | + *total = 0; | ||
| 320 | + else | ||
| 321 | + /* See note about optabs below. */ | ||
| 322 | + *total = COSTS_N_INSNS (1); | ||
| 323 | + return true; | ||
| 324 | + | ||
| 325 | + case MINUS: | ||
| 326 | + case COMPARE: | ||
| 327 | + if (cst >= 0 && cst < 256) | ||
| 328 | + *total = 0; | ||
| 329 | + else | ||
| 330 | + /* See note about optabs below. */ | ||
| 331 | + *total = COSTS_N_INSNS (1); | ||
| 332 | + return true; | ||
| 333 | + | ||
| 334 | + case ASHIFT: | ||
| 335 | + case ASHIFTRT: | ||
| 336 | + case LSHIFTRT: | ||
| 337 | + *total = 0; | ||
| 338 | + return true; | ||
| 339 | + | ||
| 340 | + default: | ||
| 341 | + /* Constants are compared explicitly against COSTS_N_INSNS (1) in | ||
| 342 | + optabs.c, creating an alternative, larger code sequence for more | ||
| 343 | + expensive constants). So, it doesn't pay to make some constants | ||
| 344 | + cost more than this. */ | ||
| 345 | + *total = COSTS_N_INSNS (1); | ||
| 346 | + } | ||
| 347 | + return true; | ||
| 348 | + } | ||
| 349 | + | ||
| 350 | + case CONST: | ||
| 351 | + case LABEL_REF: | ||
| 352 | + case SYMBOL_REF: | ||
| 353 | + *total = COSTS_WIDE_INSNS (2); | ||
| 354 | + return true; | ||
| 355 | + | ||
| 356 | + case CONST_DOUBLE: | ||
| 357 | + *total = COSTS_WIDE_INSNS (4); | ||
| 358 | + return true; | ||
| 359 | + | ||
| 360 | + case HIGH: | ||
| 361 | + case LO_SUM: | ||
| 362 | + /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the | ||
| 363 | + cost of these slightly. */ | ||
| 364 | + *total = COSTS_WIDE_INSNS (1) + 1; | ||
| 365 | + return true; | ||
| 366 | + | ||
| 367 | + default: | ||
| 368 | + if (mode != VOIDmode) | ||
| 369 | + *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode)); | ||
| 370 | + else | ||
| 371 | + /* A guess (inherited from arm_size_rtx_costs). */ | ||
| 372 | + *total = COSTS_WIDE_INSNS (4); | ||
| 373 | + return false; | ||
| 374 | + } | ||
| 375 | + | ||
| 376 | + return true; | ||
| 377 | +#undef THUMB2_LIBCALL_COST | ||
| 378 | +#undef COSTS_WIDE_INSNS | ||
| 379 | +#undef COSTS_NARROW_INSNS | ||
| 380 | +} | ||
| 381 | + | ||
| 382 | /* RTX costs when optimizing for size. */ | ||
| 383 | static bool | ||
| 384 | arm_rtx_costs (rtx x, int code, int outer_code, int *total, | ||
| 385 | bool speed) | ||
| 386 | { | ||
| 387 | if (!speed) | ||
| 388 | - return arm_size_rtx_costs (x, (enum rtx_code) code, | ||
| 389 | - (enum rtx_code) outer_code, total); | ||
| 390 | + { | ||
| 391 | + if (TARGET_THUMB2) | ||
| 392 | + return thumb2_size_rtx_costs (x, (enum rtx_code) code, | ||
| 393 | + (enum rtx_code) outer_code, total); | ||
| 394 | + else | ||
| 395 | + return arm_size_rtx_costs (x, (enum rtx_code) code, | ||
| 396 | + (enum rtx_code) outer_code, total); | ||
| 397 | + } | ||
| 398 | else | ||
| 399 | return all_cores[(int)arm_tune].rtx_costs (x, (enum rtx_code) code, | ||
| 400 | (enum rtx_code) outer_code, | ||
| 401 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99350.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99350.patch deleted file mode 100644 index 3f66f9d15..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99350.patch +++ /dev/null | |||
| @@ -1,184 +0,0 @@ | |||
| 1 | Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #7122 | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * config/arm/vfp.md (movdf_vfp): Add load double 0.0 case. | ||
| 7 | (thumb2_movdf_vfp): Likewise. Require that one of the operands be a | ||
| 8 | register. | ||
| 9 | * config/arm/constraints.md (D0): New constraint. | ||
| 10 | |||
| 11 | gcc/testsuite/ | ||
| 12 | * gcc.target/arm/neon-load-df0.c: New test. | ||
| 13 | |||
| 14 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 15 | |||
| 16 | Merge from Sourcery G++ 4.4: | ||
| 17 | |||
| 18 | 2010-02-23 Julian Brown <julian@codesourcery.com> | ||
| 19 | |||
| 20 | gcc/ | ||
| 21 | |||
| 22 | === modified file 'gcc/config/arm/constraints.md' | ||
| 23 | --- old/gcc/config/arm/constraints.md 2010-08-12 16:47:21 +0000 | ||
| 24 | +++ new/gcc/config/arm/constraints.md 2010-08-13 10:59:06 +0000 | ||
| 25 | @@ -29,7 +29,7 @@ | ||
| 26 | ;; in Thumb-1 state: I, J, K, L, M, N, O | ||
| 27 | |||
| 28 | ;; The following multi-letter normal constraints have been used: | ||
| 29 | -;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di | ||
| 30 | +;; in ARM/Thumb-2 state: D0, Da, Db, Dc, Di, Dn, Dl, DL, Dv, Dy | ||
| 31 | ;; in Thumb-1 state: Pa, Pb | ||
| 32 | ;; in Thumb-2 state: Ps, Pt, Pv | ||
| 33 | |||
| 34 | @@ -173,6 +173,13 @@ | ||
| 35 | (and (match_code "const_double") | ||
| 36 | (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)"))) | ||
| 37 | |||
| 38 | +(define_constraint "D0" | ||
| 39 | + "@internal | ||
| 40 | + In ARM/Thumb-2 state a 0.0 floating point constant which can | ||
| 41 | + be loaded with a Neon vmov immediate instruction." | ||
| 42 | + (and (match_code "const_double") | ||
| 43 | + (match_test "TARGET_NEON && op == CONST0_RTX (mode)"))) | ||
| 44 | + | ||
| 45 | (define_constraint "Da" | ||
| 46 | "@internal | ||
| 47 | In ARM/Thumb-2 state a const_int, const_double or const_vector that can | ||
| 48 | |||
| 49 | === modified file 'gcc/config/arm/vfp.md' | ||
| 50 | --- old/gcc/config/arm/vfp.md 2010-08-12 11:29:02 +0000 | ||
| 51 | +++ new/gcc/config/arm/vfp.md 2010-08-13 10:59:06 +0000 | ||
| 52 | @@ -402,8 +402,8 @@ | ||
| 53 | ;; DFmode moves | ||
| 54 | |||
| 55 | (define_insn "*movdf_vfp" | ||
| 56 | - [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r") | ||
| 57 | - (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))] | ||
| 58 | + [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w, r, m,w ,Uv,w,r") | ||
| 59 | + (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,D0,mF,r,UvF,w, w,r"))] | ||
| 60 | "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP | ||
| 61 | && ( register_operand (operands[0], DFmode) | ||
| 62 | || register_operand (operands[1], DFmode))" | ||
| 63 | @@ -418,16 +418,18 @@ | ||
| 64 | case 2: | ||
| 65 | gcc_assert (TARGET_VFP_DOUBLE); | ||
| 66 | return \"fconstd%?\\t%P0, #%G1\"; | ||
| 67 | - case 3: case 4: | ||
| 68 | + case 3: | ||
| 69 | + return \"vmov.i32\\t%P0, #0\"; | ||
| 70 | + case 4: case 5: | ||
| 71 | return output_move_double (operands); | ||
| 72 | - case 5: case 6: | ||
| 73 | + case 6: case 7: | ||
| 74 | return output_move_vfp (operands); | ||
| 75 | - case 7: | ||
| 76 | + case 8: | ||
| 77 | if (TARGET_VFP_SINGLE) | ||
| 78 | return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\"; | ||
| 79 | else | ||
| 80 | return \"fcpyd%?\\t%P0, %P1\"; | ||
| 81 | - case 8: | ||
| 82 | + case 9: | ||
| 83 | return \"#\"; | ||
| 84 | default: | ||
| 85 | gcc_unreachable (); | ||
| 86 | @@ -435,10 +437,10 @@ | ||
| 87 | } | ||
| 88 | " | ||
| 89 | [(set_attr "type" | ||
| 90 | - "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*") | ||
| 91 | - (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*") | ||
| 92 | - (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8) | ||
| 93 | - (eq_attr "alternative" "7") | ||
| 94 | + "r_2_f,f_2_r,fconstd,*,f_loadd,f_stored,load2,store2,ffarithd,*") | ||
| 95 | + (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,neon_vmov,*,*,*,*,neon_vmov,*") | ||
| 96 | + (set (attr "length") (cond [(eq_attr "alternative" "4,5,9") (const_int 8) | ||
| 97 | + (eq_attr "alternative" "8") | ||
| 98 | (if_then_else | ||
| 99 | (eq (symbol_ref "TARGET_VFP_SINGLE") | ||
| 100 | (const_int 1)) | ||
| 101 | @@ -446,14 +448,16 @@ | ||
| 102 | (const_int 4))] | ||
| 103 | (const_int 4))) | ||
| 104 | (set_attr "predicable" "yes") | ||
| 105 | - (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*") | ||
| 106 | - (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")] | ||
| 107 | + (set_attr "pool_range" "*,*,*,*,1020,*,1020,*,*,*") | ||
| 108 | + (set_attr "neg_pool_range" "*,*,*,*,1008,*,1008,*,*,*")] | ||
| 109 | ) | ||
| 110 | |||
| 111 | (define_insn "*thumb2_movdf_vfp" | ||
| 112 | - [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r") | ||
| 113 | - (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))] | ||
| 114 | - "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP" | ||
| 115 | + [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,r, m,w ,Uv,w,r") | ||
| 116 | + (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,D0,mF,r,UvF,w, w,r"))] | ||
| 117 | + "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP | ||
| 118 | + && ( register_operand (operands[0], DFmode) | ||
| 119 | + || register_operand (operands[1], DFmode))" | ||
| 120 | "* | ||
| 121 | { | ||
| 122 | switch (which_alternative) | ||
| 123 | @@ -465,11 +469,13 @@ | ||
| 124 | case 2: | ||
| 125 | gcc_assert (TARGET_VFP_DOUBLE); | ||
| 126 | return \"fconstd%?\\t%P0, #%G1\"; | ||
| 127 | - case 3: case 4: case 8: | ||
| 128 | + case 3: | ||
| 129 | + return \"vmov.i32\\t%P0, #0\"; | ||
| 130 | + case 4: case 5: case 9: | ||
| 131 | return output_move_double (operands); | ||
| 132 | - case 5: case 6: | ||
| 133 | + case 6: case 7: | ||
| 134 | return output_move_vfp (operands); | ||
| 135 | - case 7: | ||
| 136 | + case 8: | ||
| 137 | if (TARGET_VFP_SINGLE) | ||
| 138 | return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\"; | ||
| 139 | else | ||
| 140 | @@ -480,18 +486,18 @@ | ||
| 141 | } | ||
| 142 | " | ||
| 143 | [(set_attr "type" | ||
| 144 | - "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*") | ||
| 145 | - (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*") | ||
| 146 | - (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8) | ||
| 147 | - (eq_attr "alternative" "7") | ||
| 148 | + "r_2_f,f_2_r,fconstd,*,load2,store2,f_load,f_store,ffarithd,*") | ||
| 149 | + (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,neon_vmov,*,*,*,*,neon_vmov,*") | ||
| 150 | + (set (attr "length") (cond [(eq_attr "alternative" "4,5,9") (const_int 8) | ||
| 151 | + (eq_attr "alternative" "8") | ||
| 152 | (if_then_else | ||
| 153 | (eq (symbol_ref "TARGET_VFP_SINGLE") | ||
| 154 | (const_int 1)) | ||
| 155 | (const_int 8) | ||
| 156 | (const_int 4))] | ||
| 157 | (const_int 4))) | ||
| 158 | - (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*") | ||
| 159 | - (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")] | ||
| 160 | + (set_attr "pool_range" "*,*,*,*,4096,*,1020,*,*,*") | ||
| 161 | + (set_attr "neg_pool_range" "*,*,*,*,0,*,1008,*,*,*")] | ||
| 162 | ) | ||
| 163 | |||
| 164 | |||
| 165 | |||
| 166 | === added file 'gcc/testsuite/gcc.target/arm/neon-load-df0.c' | ||
| 167 | --- old/gcc/testsuite/gcc.target/arm/neon-load-df0.c 1970-01-01 00:00:00 +0000 | ||
| 168 | +++ new/gcc/testsuite/gcc.target/arm/neon-load-df0.c 2010-08-13 10:59:06 +0000 | ||
| 169 | @@ -0,0 +1,14 @@ | ||
| 170 | +/* Test the optimization of loading 0.0 for ARM Neon. */ | ||
| 171 | + | ||
| 172 | +/* { dg-do compile } */ | ||
| 173 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 174 | +/* { dg-options "-O2" } */ | ||
| 175 | +/* { dg-add-options arm_neon } */ | ||
| 176 | + | ||
| 177 | +double x; | ||
| 178 | +void bar () | ||
| 179 | +{ | ||
| 180 | + x = 0.0; | ||
| 181 | +} | ||
| 182 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[dD\]\[0-9\]+, #0\n" } } */ | ||
| 183 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 184 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99351.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99351.patch deleted file mode 100644 index aa3b3eb85..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99351.patch +++ /dev/null | |||
| @@ -1,548 +0,0 @@ | |||
| 1 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ 4.4: | ||
| 4 | |||
| 5 | Jie Zhang <jie@codesourcery.com> | ||
| 6 | Issue #7122 | ||
| 7 | |||
| 8 | gcc/ | ||
| 9 | * config/arm/arm.c (arm_rtx_costs_1): Adjust cost for | ||
| 10 | CONST_VECTOR. | ||
| 11 | (arm_size_rtx_costs): Likewise. | ||
| 12 | (thumb2_size_rtx_costs): Likewise. | ||
| 13 | (neon_valid_immediate): Add a case for double 0.0. | ||
| 14 | |||
| 15 | gcc/testsuite/ | ||
| 16 | * gcc.target/arm/neon-vdup-1.c: New test case. | ||
| 17 | * gcc.target/arm/neon-vdup-2.c: New test case. | ||
| 18 | * gcc.target/arm/neon-vdup-3.c: New test case. | ||
| 19 | * gcc.target/arm/neon-vdup-4.c: New test case. | ||
| 20 | * gcc.target/arm/neon-vdup-5.c: New test case. | ||
| 21 | * gcc.target/arm/neon-vdup-6.c: New test case. | ||
| 22 | * gcc.target/arm/neon-vdup-7.c: New test case. | ||
| 23 | * gcc.target/arm/neon-vdup-8.c: New test case. | ||
| 24 | * gcc.target/arm/neon-vdup-9.c: New test case. | ||
| 25 | * gcc.target/arm/neon-vdup-10.c: New test case. | ||
| 26 | * gcc.target/arm/neon-vdup-11.c: New test case. | ||
| 27 | * gcc.target/arm/neon-vdup-12.c: New test case. | ||
| 28 | * gcc.target/arm/neon-vdup-13.c: New test case. | ||
| 29 | * gcc.target/arm/neon-vdup-14.c: New test case. | ||
| 30 | * gcc.target/arm/neon-vdup-15.c: New test case. | ||
| 31 | * gcc.target/arm/neon-vdup-16.c: New test case. | ||
| 32 | * gcc.target/arm/neon-vdup-17.c: New test case. | ||
| 33 | * gcc.target/arm/neon-vdup-18.c: New test case. | ||
| 34 | * gcc.target/arm/neon-vdup-19.c: New test case. | ||
| 35 | |||
| 36 | |||
| 37 | === modified file 'gcc/config/arm/arm.c' | ||
| 38 | --- old/gcc/config/arm/arm.c 2010-08-13 10:55:28 +0000 | ||
| 39 | +++ new/gcc/config/arm/arm.c 2010-08-13 11:02:47 +0000 | ||
| 40 | @@ -7061,6 +7061,17 @@ | ||
| 41 | *total = COSTS_N_INSNS (4); | ||
| 42 | return true; | ||
| 43 | |||
| 44 | + case CONST_VECTOR: | ||
| 45 | + if (TARGET_NEON | ||
| 46 | + && TARGET_HARD_FLOAT | ||
| 47 | + && outer == SET | ||
| 48 | + && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) | ||
| 49 | + && neon_immediate_valid_for_move (x, mode, NULL, NULL)) | ||
| 50 | + *total = COSTS_N_INSNS (1); | ||
| 51 | + else | ||
| 52 | + *total = COSTS_N_INSNS (4); | ||
| 53 | + return true; | ||
| 54 | + | ||
| 55 | default: | ||
| 56 | *total = COSTS_N_INSNS (4); | ||
| 57 | return false; | ||
| 58 | @@ -7301,6 +7312,17 @@ | ||
| 59 | *total = COSTS_N_INSNS (4); | ||
| 60 | return true; | ||
| 61 | |||
| 62 | + case CONST_VECTOR: | ||
| 63 | + if (TARGET_NEON | ||
| 64 | + && TARGET_HARD_FLOAT | ||
| 65 | + && outer_code == SET | ||
| 66 | + && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) | ||
| 67 | + && neon_immediate_valid_for_move (x, mode, NULL, NULL)) | ||
| 68 | + *total = COSTS_N_INSNS (1); | ||
| 69 | + else | ||
| 70 | + *total = COSTS_N_INSNS (4); | ||
| 71 | + return true; | ||
| 72 | + | ||
| 73 | case HIGH: | ||
| 74 | case LO_SUM: | ||
| 75 | /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the | ||
| 76 | @@ -7647,6 +7669,17 @@ | ||
| 77 | *total = COSTS_WIDE_INSNS (4); | ||
| 78 | return true; | ||
| 79 | |||
| 80 | + case CONST_VECTOR: | ||
| 81 | + if (TARGET_NEON | ||
| 82 | + && TARGET_HARD_FLOAT | ||
| 83 | + && outer_code == SET | ||
| 84 | + && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) | ||
| 85 | + && neon_immediate_valid_for_move (x, mode, NULL, NULL)) | ||
| 86 | + *total = COSTS_WIDE_INSNS (1); | ||
| 87 | + else | ||
| 88 | + *total = COSTS_WIDE_INSNS (4); | ||
| 89 | + return true; | ||
| 90 | + | ||
| 91 | case HIGH: | ||
| 92 | case LO_SUM: | ||
| 93 | /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the | ||
| 94 | @@ -8315,11 +8348,14 @@ | ||
| 95 | vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd | ||
| 96 | eeeeeeee ffffffff gggggggg hhhhhhhh | ||
| 97 | vmov f32 18 aBbbbbbc defgh000 00000000 00000000 | ||
| 98 | + vmov f32 19 00000000 00000000 00000000 00000000 | ||
| 99 | |||
| 100 | For case 18, B = !b. Representable values are exactly those accepted by | ||
| 101 | vfp3_const_double_index, but are output as floating-point numbers rather | ||
| 102 | than indices. | ||
| 103 | |||
| 104 | + For case 19, we will change it to vmov.i32 when assembling. | ||
| 105 | + | ||
| 106 | Variants 0-5 (inclusive) may also be used as immediates for the second | ||
| 107 | operand of VORR/VBIC instructions. | ||
| 108 | |||
| 109 | @@ -8362,7 +8398,7 @@ | ||
| 110 | rtx el0 = CONST_VECTOR_ELT (op, 0); | ||
| 111 | REAL_VALUE_TYPE r0; | ||
| 112 | |||
| 113 | - if (!vfp3_const_double_rtx (el0)) | ||
| 114 | + if (!vfp3_const_double_rtx (el0) && el0 != CONST0_RTX (GET_MODE (el0))) | ||
| 115 | return -1; | ||
| 116 | |||
| 117 | REAL_VALUE_FROM_CONST_DOUBLE (r0, el0); | ||
| 118 | @@ -8384,7 +8420,10 @@ | ||
| 119 | if (elementwidth) | ||
| 120 | *elementwidth = 0; | ||
| 121 | |||
| 122 | - return 18; | ||
| 123 | + if (el0 == CONST0_RTX (GET_MODE (el0))) | ||
| 124 | + return 19; | ||
| 125 | + else | ||
| 126 | + return 18; | ||
| 127 | } | ||
| 128 | |||
| 129 | /* Splat vector constant out into a byte vector. */ | ||
| 130 | |||
| 131 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-1.c' | ||
| 132 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-1.c 1970-01-01 00:00:00 +0000 | ||
| 133 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-1.c 2010-08-13 11:02:47 +0000 | ||
| 134 | @@ -0,0 +1,17 @@ | ||
| 135 | +/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic. */ | ||
| 136 | + | ||
| 137 | +/* { dg-do compile } */ | ||
| 138 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 139 | +/* { dg-options "-O2" } */ | ||
| 140 | +/* { dg-add-options arm_neon } */ | ||
| 141 | + | ||
| 142 | +#include <arm_neon.h> | ||
| 143 | + | ||
| 144 | +float32x4_t out_float32x4_t; | ||
| 145 | +void test_vdupq_nf32 (void) | ||
| 146 | +{ | ||
| 147 | + out_float32x4_t = vdupq_n_f32 (0.0); | ||
| 148 | +} | ||
| 149 | + | ||
| 150 | +/* { dg-final { scan-assembler "vmov\.f32\[ \]+\[qQ\]\[0-9\]+, #0\.0\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 151 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 152 | |||
| 153 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-10.c' | ||
| 154 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-10.c 1970-01-01 00:00:00 +0000 | ||
| 155 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-10.c 2010-08-13 11:02:47 +0000 | ||
| 156 | @@ -0,0 +1,17 @@ | ||
| 157 | +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ | ||
| 158 | + | ||
| 159 | +/* { dg-do compile } */ | ||
| 160 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 161 | +/* { dg-options "-O2" } */ | ||
| 162 | +/* { dg-add-options arm_neon } */ | ||
| 163 | + | ||
| 164 | +#include <arm_neon.h> | ||
| 165 | + | ||
| 166 | +uint32x4_t out_uint32x4_t; | ||
| 167 | +void test_vdupq_nu32 (void) | ||
| 168 | +{ | ||
| 169 | + out_uint32x4_t = vdupq_n_u32 (~0x12000000); | ||
| 170 | +} | ||
| 171 | + | ||
| 172 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #3992977407\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 173 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 174 | |||
| 175 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-11.c' | ||
| 176 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-11.c 1970-01-01 00:00:00 +0000 | ||
| 177 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-11.c 2010-08-13 11:02:47 +0000 | ||
| 178 | @@ -0,0 +1,17 @@ | ||
| 179 | +/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ | ||
| 180 | + | ||
| 181 | +/* { dg-do compile } */ | ||
| 182 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 183 | +/* { dg-options "-O2" } */ | ||
| 184 | +/* { dg-add-options arm_neon } */ | ||
| 185 | + | ||
| 186 | +#include <arm_neon.h> | ||
| 187 | + | ||
| 188 | +uint16x8_t out_uint16x8_t; | ||
| 189 | +void test_vdupq_nu16 (void) | ||
| 190 | +{ | ||
| 191 | + out_uint16x8_t = vdupq_n_u16 (0x12); | ||
| 192 | +} | ||
| 193 | + | ||
| 194 | +/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 195 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 196 | |||
| 197 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-12.c' | ||
| 198 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-12.c 1970-01-01 00:00:00 +0000 | ||
| 199 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-12.c 2010-08-13 11:02:47 +0000 | ||
| 200 | @@ -0,0 +1,17 @@ | ||
| 201 | +/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ | ||
| 202 | + | ||
| 203 | +/* { dg-do compile } */ | ||
| 204 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 205 | +/* { dg-options "-O2" } */ | ||
| 206 | +/* { dg-add-options arm_neon } */ | ||
| 207 | + | ||
| 208 | +#include <arm_neon.h> | ||
| 209 | + | ||
| 210 | +uint16x8_t out_uint16x8_t; | ||
| 211 | +void test_vdupq_nu16 (void) | ||
| 212 | +{ | ||
| 213 | + out_uint16x8_t = vdupq_n_u16 (0x1200); | ||
| 214 | +} | ||
| 215 | + | ||
| 216 | +/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 217 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 218 | |||
| 219 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-13.c' | ||
| 220 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-13.c 1970-01-01 00:00:00 +0000 | ||
| 221 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-13.c 2010-08-13 11:02:47 +0000 | ||
| 222 | @@ -0,0 +1,17 @@ | ||
| 223 | +/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ | ||
| 224 | + | ||
| 225 | +/* { dg-do compile } */ | ||
| 226 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 227 | +/* { dg-options "-O2" } */ | ||
| 228 | +/* { dg-add-options arm_neon } */ | ||
| 229 | + | ||
| 230 | +#include <arm_neon.h> | ||
| 231 | + | ||
| 232 | +uint16x8_t out_uint16x8_t; | ||
| 233 | +void test_vdupq_nu16 (void) | ||
| 234 | +{ | ||
| 235 | + out_uint16x8_t = vdupq_n_u16 (~0x12); | ||
| 236 | +} | ||
| 237 | + | ||
| 238 | +/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #65517\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 239 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 240 | |||
| 241 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-14.c' | ||
| 242 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-14.c 1970-01-01 00:00:00 +0000 | ||
| 243 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-14.c 2010-08-13 11:02:47 +0000 | ||
| 244 | @@ -0,0 +1,17 @@ | ||
| 245 | +/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */ | ||
| 246 | + | ||
| 247 | +/* { dg-do compile } */ | ||
| 248 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 249 | +/* { dg-options "-O2" } */ | ||
| 250 | +/* { dg-add-options arm_neon } */ | ||
| 251 | + | ||
| 252 | +#include <arm_neon.h> | ||
| 253 | + | ||
| 254 | +uint16x8_t out_uint16x8_t; | ||
| 255 | +void test_vdupq_nu16 (void) | ||
| 256 | +{ | ||
| 257 | + out_uint16x8_t = vdupq_n_u16 (~0x1200); | ||
| 258 | +} | ||
| 259 | + | ||
| 260 | +/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #60927\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 261 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 262 | |||
| 263 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-15.c' | ||
| 264 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-15.c 1970-01-01 00:00:00 +0000 | ||
| 265 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-15.c 2010-08-13 11:02:47 +0000 | ||
| 266 | @@ -0,0 +1,17 @@ | ||
| 267 | +/* Test the optimization of `vdupq_n_u8' ARM Neon intrinsic. */ | ||
| 268 | + | ||
| 269 | +/* { dg-do compile } */ | ||
| 270 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 271 | +/* { dg-options "-O2" } */ | ||
| 272 | +/* { dg-add-options arm_neon } */ | ||
| 273 | + | ||
| 274 | +#include <arm_neon.h> | ||
| 275 | + | ||
| 276 | +uint8x16_t out_uint8x16_t; | ||
| 277 | +void test_vdupq_nu8 (void) | ||
| 278 | +{ | ||
| 279 | + out_uint8x16_t = vdupq_n_u8 (0x12); | ||
| 280 | +} | ||
| 281 | + | ||
| 282 | +/* { dg-final { scan-assembler "vmov\.i8\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 283 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 284 | |||
| 285 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-16.c' | ||
| 286 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-16.c 1970-01-01 00:00:00 +0000 | ||
| 287 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-16.c 2010-08-13 11:02:47 +0000 | ||
| 288 | @@ -0,0 +1,17 @@ | ||
| 289 | +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ | ||
| 290 | + | ||
| 291 | +/* { dg-do compile } */ | ||
| 292 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 293 | +/* { dg-options "-O2" } */ | ||
| 294 | +/* { dg-add-options arm_neon } */ | ||
| 295 | + | ||
| 296 | +#include <arm_neon.h> | ||
| 297 | + | ||
| 298 | +uint32x4_t out_uint32x4_t; | ||
| 299 | +void test_vdupq_nu32 (void) | ||
| 300 | +{ | ||
| 301 | + out_uint32x4_t = vdupq_n_u32 (0x12ff); | ||
| 302 | +} | ||
| 303 | + | ||
| 304 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4863\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 305 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 306 | |||
| 307 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-17.c' | ||
| 308 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-17.c 1970-01-01 00:00:00 +0000 | ||
| 309 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-17.c 2010-08-13 11:02:47 +0000 | ||
| 310 | @@ -0,0 +1,17 @@ | ||
| 311 | +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ | ||
| 312 | + | ||
| 313 | +/* { dg-do compile } */ | ||
| 314 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 315 | +/* { dg-options "-O2" } */ | ||
| 316 | +/* { dg-add-options arm_neon } */ | ||
| 317 | + | ||
| 318 | +#include <arm_neon.h> | ||
| 319 | + | ||
| 320 | +uint32x4_t out_uint32x4_t; | ||
| 321 | +void test_vdupq_nu32 (void) | ||
| 322 | +{ | ||
| 323 | + out_uint32x4_t = vdupq_n_u32 (0x12ffff); | ||
| 324 | +} | ||
| 325 | + | ||
| 326 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #1245183\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 327 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 328 | |||
| 329 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-18.c' | ||
| 330 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-18.c 1970-01-01 00:00:00 +0000 | ||
| 331 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-18.c 2010-08-13 11:02:47 +0000 | ||
| 332 | @@ -0,0 +1,17 @@ | ||
| 333 | +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ | ||
| 334 | + | ||
| 335 | +/* { dg-do compile } */ | ||
| 336 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 337 | +/* { dg-options "-O2" } */ | ||
| 338 | +/* { dg-add-options arm_neon } */ | ||
| 339 | + | ||
| 340 | +#include <arm_neon.h> | ||
| 341 | + | ||
| 342 | +uint32x4_t out_uint32x4_t; | ||
| 343 | +void test_vdupq_nu32 (void) | ||
| 344 | +{ | ||
| 345 | + out_uint32x4_t = vdupq_n_u32 (~0x12ff); | ||
| 346 | +} | ||
| 347 | + | ||
| 348 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294962432\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 349 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 350 | |||
| 351 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-19.c' | ||
| 352 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-19.c 1970-01-01 00:00:00 +0000 | ||
| 353 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-19.c 2010-08-13 11:02:47 +0000 | ||
| 354 | @@ -0,0 +1,17 @@ | ||
| 355 | +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ | ||
| 356 | + | ||
| 357 | +/* { dg-do compile } */ | ||
| 358 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 359 | +/* { dg-options "-O2" } */ | ||
| 360 | +/* { dg-add-options arm_neon } */ | ||
| 361 | + | ||
| 362 | +#include <arm_neon.h> | ||
| 363 | + | ||
| 364 | +uint32x4_t out_uint32x4_t; | ||
| 365 | +void test_vdupq_nu32 (void) | ||
| 366 | +{ | ||
| 367 | + out_uint32x4_t = vdupq_n_u32 (~0x12ffff); | ||
| 368 | +} | ||
| 369 | + | ||
| 370 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4293722112\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 371 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 372 | |||
| 373 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-2.c' | ||
| 374 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-2.c 1970-01-01 00:00:00 +0000 | ||
| 375 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-2.c 2010-08-13 11:02:47 +0000 | ||
| 376 | @@ -0,0 +1,17 @@ | ||
| 377 | +/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic. */ | ||
| 378 | + | ||
| 379 | +/* { dg-do compile } */ | ||
| 380 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 381 | +/* { dg-options "-O2" } */ | ||
| 382 | +/* { dg-add-options arm_neon } */ | ||
| 383 | + | ||
| 384 | +#include <arm_neon.h> | ||
| 385 | + | ||
| 386 | +float32x4_t out_float32x4_t; | ||
| 387 | +void test_vdupq_nf32 (void) | ||
| 388 | +{ | ||
| 389 | + out_float32x4_t = vdupq_n_f32 (0.125); | ||
| 390 | +} | ||
| 391 | + | ||
| 392 | +/* { dg-final { scan-assembler "vmov\.f32\[ \]+\[qQ\]\[0-9\]+, #1\.25e-1\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 393 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 394 | |||
| 395 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-3.c' | ||
| 396 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-3.c 1970-01-01 00:00:00 +0000 | ||
| 397 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-3.c 2010-08-13 11:02:47 +0000 | ||
| 398 | @@ -0,0 +1,17 @@ | ||
| 399 | +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ | ||
| 400 | + | ||
| 401 | +/* { dg-do compile } */ | ||
| 402 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 403 | +/* { dg-options "-O2" } */ | ||
| 404 | +/* { dg-add-options arm_neon } */ | ||
| 405 | + | ||
| 406 | +#include <arm_neon.h> | ||
| 407 | + | ||
| 408 | +uint32x4_t out_uint32x4_t; | ||
| 409 | +void test_vdupq_nu32 (void) | ||
| 410 | +{ | ||
| 411 | + out_uint32x4_t = vdupq_n_u32 (0x12); | ||
| 412 | +} | ||
| 413 | + | ||
| 414 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 415 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 416 | |||
| 417 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-4.c' | ||
| 418 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-4.c 1970-01-01 00:00:00 +0000 | ||
| 419 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-4.c 2010-08-13 11:02:47 +0000 | ||
| 420 | @@ -0,0 +1,17 @@ | ||
| 421 | +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ | ||
| 422 | + | ||
| 423 | +/* { dg-do compile } */ | ||
| 424 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 425 | +/* { dg-options "-O2" } */ | ||
| 426 | +/* { dg-add-options arm_neon } */ | ||
| 427 | + | ||
| 428 | +#include <arm_neon.h> | ||
| 429 | + | ||
| 430 | +uint32x4_t out_uint32x4_t; | ||
| 431 | +void test_vdupq_nu32 (void) | ||
| 432 | +{ | ||
| 433 | + out_uint32x4_t = vdupq_n_u32 (0x1200); | ||
| 434 | +} | ||
| 435 | + | ||
| 436 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 437 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 438 | |||
| 439 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-5.c' | ||
| 440 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-5.c 1970-01-01 00:00:00 +0000 | ||
| 441 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-5.c 2010-08-13 11:02:47 +0000 | ||
| 442 | @@ -0,0 +1,17 @@ | ||
| 443 | +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ | ||
| 444 | + | ||
| 445 | +/* { dg-do compile } */ | ||
| 446 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 447 | +/* { dg-options "-O2" } */ | ||
| 448 | +/* { dg-add-options arm_neon } */ | ||
| 449 | + | ||
| 450 | +#include <arm_neon.h> | ||
| 451 | + | ||
| 452 | +uint32x4_t out_uint32x4_t; | ||
| 453 | +void test_vdupq_nu32 (void) | ||
| 454 | +{ | ||
| 455 | + out_uint32x4_t = vdupq_n_u32 (0x120000); | ||
| 456 | +} | ||
| 457 | + | ||
| 458 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #1179648\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 459 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 460 | |||
| 461 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-6.c' | ||
| 462 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-6.c 1970-01-01 00:00:00 +0000 | ||
| 463 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-6.c 2010-08-13 11:02:47 +0000 | ||
| 464 | @@ -0,0 +1,17 @@ | ||
| 465 | +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ | ||
| 466 | + | ||
| 467 | +/* { dg-do compile } */ | ||
| 468 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 469 | +/* { dg-options "-O2" } */ | ||
| 470 | +/* { dg-add-options arm_neon } */ | ||
| 471 | + | ||
| 472 | +#include <arm_neon.h> | ||
| 473 | + | ||
| 474 | +uint32x4_t out_uint32x4_t; | ||
| 475 | +void test_vdupq_nu32 (void) | ||
| 476 | +{ | ||
| 477 | + out_uint32x4_t = vdupq_n_u32 (0x12000000); | ||
| 478 | +} | ||
| 479 | + | ||
| 480 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #301989888\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 481 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 482 | |||
| 483 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-7.c' | ||
| 484 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-7.c 1970-01-01 00:00:00 +0000 | ||
| 485 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-7.c 2010-08-13 11:02:47 +0000 | ||
| 486 | @@ -0,0 +1,17 @@ | ||
| 487 | +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ | ||
| 488 | + | ||
| 489 | +/* { dg-do compile } */ | ||
| 490 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 491 | +/* { dg-options "-O2" } */ | ||
| 492 | +/* { dg-add-options arm_neon } */ | ||
| 493 | + | ||
| 494 | +#include <arm_neon.h> | ||
| 495 | + | ||
| 496 | +uint32x4_t out_uint32x4_t; | ||
| 497 | +void test_vdupq_nu32 (void) | ||
| 498 | +{ | ||
| 499 | + out_uint32x4_t = vdupq_n_u32 (~0x12); | ||
| 500 | +} | ||
| 501 | + | ||
| 502 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294967277\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 503 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 504 | |||
| 505 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-8.c' | ||
| 506 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-8.c 1970-01-01 00:00:00 +0000 | ||
| 507 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-8.c 2010-08-13 11:02:47 +0000 | ||
| 508 | @@ -0,0 +1,17 @@ | ||
| 509 | +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ | ||
| 510 | + | ||
| 511 | +/* { dg-do compile } */ | ||
| 512 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 513 | +/* { dg-options "-O2" } */ | ||
| 514 | +/* { dg-add-options arm_neon } */ | ||
| 515 | + | ||
| 516 | +#include <arm_neon.h> | ||
| 517 | + | ||
| 518 | +uint32x4_t out_uint32x4_t; | ||
| 519 | +void test_vdupq_nu32 (void) | ||
| 520 | +{ | ||
| 521 | + out_uint32x4_t = vdupq_n_u32 (~0x1200); | ||
| 522 | +} | ||
| 523 | + | ||
| 524 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294962687\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 525 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 526 | |||
| 527 | === added file 'gcc/testsuite/gcc.target/arm/neon-vdup-9.c' | ||
| 528 | --- old/gcc/testsuite/gcc.target/arm/neon-vdup-9.c 1970-01-01 00:00:00 +0000 | ||
| 529 | +++ new/gcc/testsuite/gcc.target/arm/neon-vdup-9.c 2010-08-13 11:02:47 +0000 | ||
| 530 | @@ -0,0 +1,17 @@ | ||
| 531 | +/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */ | ||
| 532 | + | ||
| 533 | +/* { dg-do compile } */ | ||
| 534 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 535 | +/* { dg-options "-O2" } */ | ||
| 536 | +/* { dg-add-options arm_neon } */ | ||
| 537 | + | ||
| 538 | +#include <arm_neon.h> | ||
| 539 | + | ||
| 540 | +uint32x4_t out_uint32x4_t; | ||
| 541 | +void test_vdupq_nu32 (void) | ||
| 542 | +{ | ||
| 543 | + out_uint32x4_t = vdupq_n_u32 (~0x120000); | ||
| 544 | +} | ||
| 545 | + | ||
| 546 | +/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4293787647\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 547 | +/* { dg-final { cleanup-saved-temps } } */ | ||
| 548 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99352.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99352.patch deleted file mode 100644 index 8d48ada2f..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99352.patch +++ /dev/null | |||
| @@ -1,118 +0,0 @@ | |||
| 1 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ 4.4: | ||
| 4 | |||
| 5 | 2010-04-07 Thomas Schwinge <thomas@codesourcery.com> | ||
| 6 | Daniel Jacobowitz <dan@codesourcery.com> | ||
| 7 | |||
| 8 | Issue #6715 | ||
| 9 | |||
| 10 | PR debug/40521 | ||
| 11 | |||
| 12 | gcc/ | ||
| 13 | * dwarf2out.c (NEED_UNWIND_TABLES): Define. | ||
| 14 | (dwarf2out_do_frame, dwarf2out_do_cfi_asm, dwarf2out_begin_prologue) | ||
| 15 | (dwarf2out_frame_finish, dwarf2out_assembly_start): Use it. | ||
| 16 | (dwarf2out_assembly_start): Correct logic for TARGET_UNWIND_INFO. | ||
| 17 | * config/arm/arm.h (DWARF2_UNWIND_INFO): Remove definition. | ||
| 18 | * config/arm/bpabi.h (DWARF2_UNWIND_INFO): Define to zero. | ||
| 19 | |||
| 20 | |||
| 21 | === modified file 'gcc/config/arm/arm.h' | ||
| 22 | --- old/gcc/config/arm/arm.h 2010-08-13 10:30:35 +0000 | ||
| 23 | +++ new/gcc/config/arm/arm.h 2010-08-13 11:11:15 +0000 | ||
| 24 | @@ -932,9 +932,6 @@ | ||
| 25 | #define MUST_USE_SJLJ_EXCEPTIONS 1 | ||
| 26 | #endif | ||
| 27 | |||
| 28 | -/* We can generate DWARF2 Unwind info, even though we don't use it. */ | ||
| 29 | -#define DWARF2_UNWIND_INFO 1 | ||
| 30 | - | ||
| 31 | /* Use r0 and r1 to pass exception handling information. */ | ||
| 32 | #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) | ||
| 33 | |||
| 34 | |||
| 35 | === modified file 'gcc/config/arm/bpabi.h' | ||
| 36 | --- old/gcc/config/arm/bpabi.h 2009-11-20 17:37:30 +0000 | ||
| 37 | +++ new/gcc/config/arm/bpabi.h 2010-08-13 11:11:15 +0000 | ||
| 38 | @@ -26,6 +26,7 @@ | ||
| 39 | #define TARGET_BPABI (TARGET_AAPCS_BASED) | ||
| 40 | |||
| 41 | /* BPABI targets use EABI frame unwinding tables. */ | ||
| 42 | +#define DWARF2_UNWIND_INFO 0 | ||
| 43 | #define TARGET_UNWIND_INFO 1 | ||
| 44 | |||
| 45 | /* Section 4.1 of the AAPCS requires the use of VFP format. */ | ||
| 46 | |||
| 47 | === modified file 'gcc/dwarf2out.c' | ||
| 48 | --- old/gcc/dwarf2out.c 2010-07-01 11:31:19 +0000 | ||
| 49 | +++ new/gcc/dwarf2out.c 2010-08-13 11:11:15 +0000 | ||
| 50 | @@ -124,6 +124,9 @@ | ||
| 51 | # endif | ||
| 52 | #endif | ||
| 53 | |||
| 54 | +#define NEED_UNWIND_TABLES \ | ||
| 55 | + (flag_unwind_tables || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS)) | ||
| 56 | + | ||
| 57 | /* Map register numbers held in the call frame info that gcc has | ||
| 58 | collected using DWARF_FRAME_REGNUM to those that should be output in | ||
| 59 | .debug_frame and .eh_frame. */ | ||
| 60 | @@ -147,9 +150,7 @@ | ||
| 61 | || write_symbols == VMS_AND_DWARF2_DEBUG | ||
| 62 | || DWARF2_FRAME_INFO || saved_do_cfi_asm | ||
| 63 | #ifdef DWARF2_UNWIND_INFO | ||
| 64 | - || (DWARF2_UNWIND_INFO | ||
| 65 | - && (flag_unwind_tables | ||
| 66 | - || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS))) | ||
| 67 | + || (DWARF2_UNWIND_INFO && NEED_UNWIND_TABLES) | ||
| 68 | #endif | ||
| 69 | ); | ||
| 70 | } | ||
| 71 | @@ -185,7 +186,7 @@ | ||
| 72 | #ifdef TARGET_UNWIND_INFO | ||
| 73 | return false; | ||
| 74 | #else | ||
| 75 | - if (USING_SJLJ_EXCEPTIONS || (!flag_unwind_tables && !flag_exceptions)) | ||
| 76 | + if (!NEED_UNWIND_TABLES) | ||
| 77 | return false; | ||
| 78 | #endif | ||
| 79 | } | ||
| 80 | @@ -3906,8 +3907,7 @@ | ||
| 81 | /* ??? current_function_func_begin_label is also used by except.c | ||
| 82 | for call-site information. We must emit this label if it might | ||
| 83 | be used. */ | ||
| 84 | - if ((! flag_exceptions || USING_SJLJ_EXCEPTIONS) | ||
| 85 | - && ! dwarf2out_do_frame ()) | ||
| 86 | + if (! NEED_UNWIND_TABLES && ! dwarf2out_do_frame ()) | ||
| 87 | return; | ||
| 88 | #else | ||
| 89 | if (! dwarf2out_do_frame ()) | ||
| 90 | @@ -4067,7 +4067,7 @@ | ||
| 91 | |||
| 92 | #ifndef TARGET_UNWIND_INFO | ||
| 93 | /* Output another copy for the unwinder. */ | ||
| 94 | - if (! USING_SJLJ_EXCEPTIONS && (flag_unwind_tables || flag_exceptions)) | ||
| 95 | + if (NEED_UNWIND_TABLES) | ||
| 96 | output_call_frame_info (1); | ||
| 97 | #endif | ||
| 98 | } | ||
| 99 | @@ -20732,10 +20732,15 @@ | ||
| 100 | { | ||
| 101 | if (HAVE_GAS_CFI_SECTIONS_DIRECTIVE && dwarf2out_do_cfi_asm ()) | ||
| 102 | { | ||
| 103 | -#ifndef TARGET_UNWIND_INFO | ||
| 104 | - if (USING_SJLJ_EXCEPTIONS || (!flag_unwind_tables && !flag_exceptions)) | ||
| 105 | -#endif | ||
| 106 | +#ifdef TARGET_UNWIND_INFO | ||
| 107 | + /* We're only ever interested in .debug_frame. */ | ||
| 108 | + fprintf (asm_out_file, "\t.cfi_sections\t.debug_frame\n"); | ||
| 109 | +#else | ||
| 110 | + /* GAS defaults to emitting .eh_frame only, and .debug_frame is not | ||
| 111 | + wanted in case that the former one is present. */ | ||
| 112 | + if (! NEED_UNWIND_TABLES) | ||
| 113 | fprintf (asm_out_file, "\t.cfi_sections\t.debug_frame\n"); | ||
| 114 | +#endif | ||
| 115 | } | ||
| 116 | } | ||
| 117 | |||
| 118 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99353.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99353.patch deleted file mode 100644 index 239251d2b..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99353.patch +++ /dev/null | |||
| @@ -1,298 +0,0 @@ | |||
| 1 | 2010-04-08 Bernd Schmidt <bernds@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #6952 | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * ira-costs.c (record_reg_classes): Ignore alternatives that are | ||
| 7 | not enabled. | ||
| 8 | * config/arm/vfp.md (arm_movdi_vfp): Enable only when not tuning | ||
| 9 | for Cortex-A8. | ||
| 10 | (arm_movdi_vfp_cortexa8): New pattern. | ||
| 11 | * config/arm/neon.md (adddi3_neon, subdi3_neon, anddi3_neon, | ||
| 12 | iordi3_neon, xordi3_neon): Add alternatives to discourage Neon | ||
| 13 | instructions when tuning for Cortex-A8. Set attribute "alt_tune". | ||
| 14 | * config/arm/arm.md (define_attr "alt_tune", define_attr "enabled"): | ||
| 15 | New. | ||
| 16 | |||
| 17 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 18 | |||
| 19 | Merge from Sourcery G++ 4.4: | ||
| 20 | |||
| 21 | 2010-04-07 Thomas Schwinge <thomas@codesourcery.com> | ||
| 22 | Daniel Jacobowitz <dan@codesourcery.com> | ||
| 23 | |||
| 24 | |||
| 25 | === modified file 'gcc/config/arm/arm.md' | ||
| 26 | --- old/gcc/config/arm/arm.md 2010-08-13 10:30:35 +0000 | ||
| 27 | +++ new/gcc/config/arm/arm.md 2010-08-13 11:40:17 +0000 | ||
| 28 | @@ -432,6 +432,20 @@ | ||
| 29 | (const_string "yes") | ||
| 30 | (const_string "no")))) | ||
| 31 | |||
| 32 | +; Specifies which machine an alternative is tuned for. Used to compute | ||
| 33 | +; attribute ENABLED. | ||
| 34 | +(define_attr "alt_tune" "all,onlya8,nota8" (const_string "all")) | ||
| 35 | + | ||
| 36 | +(define_attr "enabled" "" | ||
| 37 | + (cond [(and (eq_attr "alt_tune" "onlya8") | ||
| 38 | + (not (eq_attr "tune" "cortexa8"))) | ||
| 39 | + (const_int 0) | ||
| 40 | + | ||
| 41 | + (and (eq_attr "alt_tune" "nota8") | ||
| 42 | + (eq_attr "tune" "cortexa8")) | ||
| 43 | + (const_int 0)] | ||
| 44 | + (const_int 1))) | ||
| 45 | + | ||
| 46 | (include "arm-generic.md") | ||
| 47 | (include "arm926ejs.md") | ||
| 48 | (include "arm1020e.md") | ||
| 49 | |||
| 50 | === modified file 'gcc/config/arm/neon.md' | ||
| 51 | --- old/gcc/config/arm/neon.md 2010-08-10 13:31:21 +0000 | ||
| 52 | +++ new/gcc/config/arm/neon.md 2010-08-13 11:40:17 +0000 | ||
| 53 | @@ -827,23 +827,25 @@ | ||
| 54 | ) | ||
| 55 | |||
| 56 | (define_insn "adddi3_neon" | ||
| 57 | - [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r") | ||
| 58 | - (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0") | ||
| 59 | - (match_operand:DI 2 "s_register_operand" "w,r,0"))) | ||
| 60 | + [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r") | ||
| 61 | + (plus:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0") | ||
| 62 | + (match_operand:DI 2 "s_register_operand" "w,w,r,0"))) | ||
| 63 | (clobber (reg:CC CC_REGNUM))] | ||
| 64 | "TARGET_NEON" | ||
| 65 | { | ||
| 66 | switch (which_alternative) | ||
| 67 | { | ||
| 68 | - case 0: return "vadd.i64\t%P0, %P1, %P2"; | ||
| 69 | - case 1: return "#"; | ||
| 70 | + case 0: /* fall through */ | ||
| 71 | + case 1: return "vadd.i64\t%P0, %P1, %P2"; | ||
| 72 | case 2: return "#"; | ||
| 73 | + case 3: return "#"; | ||
| 74 | default: gcc_unreachable (); | ||
| 75 | } | ||
| 76 | } | ||
| 77 | - [(set_attr "neon_type" "neon_int_1,*,*") | ||
| 78 | - (set_attr "conds" "*,clob,clob") | ||
| 79 | - (set_attr "length" "*,8,8")] | ||
| 80 | + [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") | ||
| 81 | + (set_attr "conds" "*,*,clob,clob") | ||
| 82 | + (set_attr "length" "*,*,8,8") | ||
| 83 | + (set_attr "alt_tune" "nota8,onlya8,*,*")] | ||
| 84 | ) | ||
| 85 | |||
| 86 | (define_insn "*sub<mode>3_neon" | ||
| 87 | @@ -861,24 +863,26 @@ | ||
| 88 | ) | ||
| 89 | |||
| 90 | (define_insn "subdi3_neon" | ||
| 91 | - [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r") | ||
| 92 | - (minus:DI (match_operand:DI 1 "s_register_operand" "w,0,r,0") | ||
| 93 | - (match_operand:DI 2 "s_register_operand" "w,r,0,0"))) | ||
| 94 | + [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r,?&r") | ||
| 95 | + (minus:DI (match_operand:DI 1 "s_register_operand" "w,w,0,r,0") | ||
| 96 | + (match_operand:DI 2 "s_register_operand" "w,w,r,0,0"))) | ||
| 97 | (clobber (reg:CC CC_REGNUM))] | ||
| 98 | "TARGET_NEON" | ||
| 99 | { | ||
| 100 | switch (which_alternative) | ||
| 101 | { | ||
| 102 | - case 0: return "vsub.i64\t%P0, %P1, %P2"; | ||
| 103 | - case 1: /* fall through */ | ||
| 104 | - case 2: /* fall through */ | ||
| 105 | - case 3: return "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"; | ||
| 106 | + case 0: /* fall through */ | ||
| 107 | + case 1: return "vsub.i64\t%P0, %P1, %P2"; | ||
| 108 | + case 2: /* fall through */ | ||
| 109 | + case 3: /* fall through */ | ||
| 110 | + case 4: return "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2"; | ||
| 111 | default: gcc_unreachable (); | ||
| 112 | } | ||
| 113 | } | ||
| 114 | - [(set_attr "neon_type" "neon_int_2,*,*,*") | ||
| 115 | - (set_attr "conds" "*,clob,clob,clob") | ||
| 116 | - (set_attr "length" "*,8,8,8")] | ||
| 117 | + [(set_attr "neon_type" "neon_int_2,neon_int_2,*,*,*") | ||
| 118 | + (set_attr "conds" "*,*,clob,clob,clob") | ||
| 119 | + (set_attr "length" "*,*,8,8,8") | ||
| 120 | + (set_attr "alt_tune" "nota8,onlya8,*,*,*")] | ||
| 121 | ) | ||
| 122 | |||
| 123 | (define_insn "*mul<mode>3_neon" | ||
| 124 | @@ -964,23 +968,26 @@ | ||
| 125 | ) | ||
| 126 | |||
| 127 | (define_insn "iordi3_neon" | ||
| 128 | - [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r") | ||
| 129 | - (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r") | ||
| 130 | - (match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r")))] | ||
| 131 | + [(set (match_operand:DI 0 "s_register_operand" "=w,?w,w,?w,?&r,?&r") | ||
| 132 | + (ior:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0,0,r") | ||
| 133 | + (match_operand:DI 2 "neon_logic_op2" "w,w,Dl,Dl,r,r")))] | ||
| 134 | "TARGET_NEON" | ||
| 135 | { | ||
| 136 | switch (which_alternative) | ||
| 137 | { | ||
| 138 | - case 0: return "vorr\t%P0, %P1, %P2"; | ||
| 139 | - case 1: return neon_output_logic_immediate ("vorr", &operands[2], | ||
| 140 | + case 0: /* fall through */ | ||
| 141 | + case 1: return "vorr\t%P0, %P1, %P2"; | ||
| 142 | + case 2: /* fall through */ | ||
| 143 | + case 3: return neon_output_logic_immediate ("vorr", &operands[2], | ||
| 144 | DImode, 0, VALID_NEON_QREG_MODE (DImode)); | ||
| 145 | - case 2: return "#"; | ||
| 146 | - case 3: return "#"; | ||
| 147 | + case 4: return "#"; | ||
| 148 | + case 5: return "#"; | ||
| 149 | default: gcc_unreachable (); | ||
| 150 | } | ||
| 151 | } | ||
| 152 | - [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") | ||
| 153 | - (set_attr "length" "*,*,8,8")] | ||
| 154 | + [(set_attr "neon_type" "neon_int_1,neon_int_1,neon_int_1,neon_int_1,*,*") | ||
| 155 | + (set_attr "length" "*,*,*,*,8,8") | ||
| 156 | + (set_attr "alt_tune" "nota8,onlya8,nota8,onlya8,*,*")] | ||
| 157 | ) | ||
| 158 | |||
| 159 | ;; The concrete forms of the Neon immediate-logic instructions are vbic and | ||
| 160 | @@ -1006,23 +1013,26 @@ | ||
| 161 | ) | ||
| 162 | |||
| 163 | (define_insn "anddi3_neon" | ||
| 164 | - [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r") | ||
| 165 | - (and:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r") | ||
| 166 | - (match_operand:DI 2 "neon_inv_logic_op2" "w,DL,r,r")))] | ||
| 167 | + [(set (match_operand:DI 0 "s_register_operand" "=w,?w,w,?w,?&r,?&r") | ||
| 168 | + (and:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0,0,r") | ||
| 169 | + (match_operand:DI 2 "neon_inv_logic_op2" "w,w,DL,DL,r,r")))] | ||
| 170 | "TARGET_NEON" | ||
| 171 | { | ||
| 172 | switch (which_alternative) | ||
| 173 | { | ||
| 174 | - case 0: return "vand\t%P0, %P1, %P2"; | ||
| 175 | - case 1: return neon_output_logic_immediate ("vand", &operands[2], | ||
| 176 | + case 0: /* fall through */ | ||
| 177 | + case 1: return "vand\t%P0, %P1, %P2"; | ||
| 178 | + case 2: /* fall through */ | ||
| 179 | + case 3: return neon_output_logic_immediate ("vand", &operands[2], | ||
| 180 | DImode, 1, VALID_NEON_QREG_MODE (DImode)); | ||
| 181 | - case 2: return "#"; | ||
| 182 | - case 3: return "#"; | ||
| 183 | + case 4: return "#"; | ||
| 184 | + case 5: return "#"; | ||
| 185 | default: gcc_unreachable (); | ||
| 186 | } | ||
| 187 | } | ||
| 188 | - [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") | ||
| 189 | - (set_attr "length" "*,*,8,8")] | ||
| 190 | + [(set_attr "neon_type" "neon_int_1,neon_int_1,neon_int_1,neon_int_1,*,*") | ||
| 191 | + (set_attr "length" "*,*,*,*,8,8") | ||
| 192 | + (set_attr "alt_tune" "nota8,onlya8,nota8,onlya8,*,*")] | ||
| 193 | ) | ||
| 194 | |||
| 195 | (define_insn "orn<mode>3_neon" | ||
| 196 | @@ -1080,16 +1090,18 @@ | ||
| 197 | ) | ||
| 198 | |||
| 199 | (define_insn "xordi3_neon" | ||
| 200 | - [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r") | ||
| 201 | - (xor:DI (match_operand:DI 1 "s_register_operand" "%w,0,r") | ||
| 202 | - (match_operand:DI 2 "s_register_operand" "w,r,r")))] | ||
| 203 | + [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r") | ||
| 204 | + (xor:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,r") | ||
| 205 | + (match_operand:DI 2 "s_register_operand" "w,w,r,r")))] | ||
| 206 | "TARGET_NEON" | ||
| 207 | "@ | ||
| 208 | veor\t%P0, %P1, %P2 | ||
| 209 | + veor\t%P0, %P1, %P2 | ||
| 210 | # | ||
| 211 | #" | ||
| 212 | - [(set_attr "neon_type" "neon_int_1,*,*") | ||
| 213 | - (set_attr "length" "*,8,8")] | ||
| 214 | + [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*") | ||
| 215 | + (set_attr "length" "*,*,8,8") | ||
| 216 | + (set_attr "alt_tune" "nota8,onlya8,*,*")] | ||
| 217 | ) | ||
| 218 | |||
| 219 | (define_insn "one_cmpl<mode>2" | ||
| 220 | |||
| 221 | === modified file 'gcc/config/arm/vfp.md' | ||
| 222 | --- old/gcc/config/arm/vfp.md 2010-08-13 10:59:06 +0000 | ||
| 223 | +++ new/gcc/config/arm/vfp.md 2010-08-13 11:40:17 +0000 | ||
| 224 | @@ -133,9 +133,51 @@ | ||
| 225 | ;; DImode moves | ||
| 226 | |||
| 227 | (define_insn "*arm_movdi_vfp" | ||
| 228 | - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv") | ||
| 229 | - (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] | ||
| 230 | - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP | ||
| 231 | + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,w,r,w,w, Uv") | ||
| 232 | + (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] | ||
| 233 | + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8 | ||
| 234 | + && ( register_operand (operands[0], DImode) | ||
| 235 | + || register_operand (operands[1], DImode))" | ||
| 236 | + "* | ||
| 237 | + switch (which_alternative) | ||
| 238 | + { | ||
| 239 | + case 0: | ||
| 240 | + return \"#\"; | ||
| 241 | + case 1: | ||
| 242 | + case 2: | ||
| 243 | + return output_move_double (operands); | ||
| 244 | + case 3: | ||
| 245 | + return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; | ||
| 246 | + case 4: | ||
| 247 | + return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; | ||
| 248 | + case 5: | ||
| 249 | + if (TARGET_VFP_SINGLE) | ||
| 250 | + return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\"; | ||
| 251 | + else | ||
| 252 | + return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; | ||
| 253 | + case 6: case 7: | ||
| 254 | + return output_move_vfp (operands); | ||
| 255 | + default: | ||
| 256 | + gcc_unreachable (); | ||
| 257 | + } | ||
| 258 | + " | ||
| 259 | + [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored") | ||
| 260 | + (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*") | ||
| 261 | + (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8) | ||
| 262 | + (eq_attr "alternative" "5") | ||
| 263 | + (if_then_else | ||
| 264 | + (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1)) | ||
| 265 | + (const_int 8) | ||
| 266 | + (const_int 4))] | ||
| 267 | + (const_int 4))) | ||
| 268 | + (set_attr "pool_range" "*,1020,*,*,*,*,1020,*") | ||
| 269 | + (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")] | ||
| 270 | +) | ||
| 271 | + | ||
| 272 | +(define_insn "*arm_movdi_vfp_cortexa8" | ||
| 273 | + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,!r,w,w, Uv") | ||
| 274 | + (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))] | ||
| 275 | + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8 | ||
| 276 | && ( register_operand (operands[0], DImode) | ||
| 277 | || register_operand (operands[1], DImode))" | ||
| 278 | "* | ||
| 279 | |||
| 280 | === modified file 'gcc/ira-costs.c' | ||
| 281 | --- old/gcc/ira-costs.c 2009-11-25 10:55:54 +0000 | ||
| 282 | +++ new/gcc/ira-costs.c 2010-08-13 11:40:17 +0000 | ||
| 283 | @@ -224,6 +224,14 @@ | ||
| 284 | int alt_fail = 0; | ||
| 285 | int alt_cost = 0, op_cost_add; | ||
| 286 | |||
| 287 | + if (!recog_data.alternative_enabled_p[alt]) | ||
| 288 | + { | ||
| 289 | + for (i = 0; i < recog_data.n_operands; i++) | ||
| 290 | + constraints[i] = skip_alternative (constraints[i]); | ||
| 291 | + | ||
| 292 | + continue; | ||
| 293 | + } | ||
| 294 | + | ||
| 295 | for (i = 0; i < n_ops; i++) | ||
| 296 | { | ||
| 297 | unsigned char c; | ||
| 298 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99354.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99354.patch deleted file mode 100644 index 743e2751c..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99354.patch +++ /dev/null | |||
| @@ -1,384 +0,0 @@ | |||
| 1 | Richard Earnshaw <rearnsha@arm.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * doc/tm.texi (OVERLAPPING_REGISTER_NAMES): Document new macro. | ||
| 5 | * output.h (decode_reg_name_and_count): Declare. | ||
| 6 | * varasm.c (decode_reg_name_and_count): New function. | ||
| 7 | (decode_reg_name): Reimplement using decode_reg_name_and_count. | ||
| 8 | * reginfo.c (fix_register): Use decode_reg_name_and_count and | ||
| 9 | iterate over all regs used. | ||
| 10 | * stmt.c (expand_asm_operands): Likewise. | ||
| 11 | * config/arm/aout.h (OVERLAPPING_REGISTER_NAMES): Define. | ||
| 12 | (ADDITIONAL_REGISTER_NAMES): Remove aliases that overlap | ||
| 13 | multiple machine registers. | ||
| 14 | |||
| 15 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 16 | |||
| 17 | Merge from Sourcery G++ 4.4: | ||
| 18 | |||
| 19 | 2010-04-08 Bernd Schmidt <bernds@codesourcery.com> | ||
| 20 | |||
| 21 | Issue #6952 | ||
| 22 | |||
| 23 | === modified file 'gcc/config/arm/aout.h' | ||
| 24 | --- old/gcc/config/arm/aout.h 2009-06-21 19:48:15 +0000 | ||
| 25 | +++ new/gcc/config/arm/aout.h 2010-08-13 11:53:46 +0000 | ||
| 26 | @@ -163,31 +163,45 @@ | ||
| 27 | {"mvdx12", 39}, \ | ||
| 28 | {"mvdx13", 40}, \ | ||
| 29 | {"mvdx14", 41}, \ | ||
| 30 | - {"mvdx15", 42}, \ | ||
| 31 | - {"d0", 63}, {"q0", 63}, \ | ||
| 32 | - {"d1", 65}, \ | ||
| 33 | - {"d2", 67}, {"q1", 67}, \ | ||
| 34 | - {"d3", 69}, \ | ||
| 35 | - {"d4", 71}, {"q2", 71}, \ | ||
| 36 | - {"d5", 73}, \ | ||
| 37 | - {"d6", 75}, {"q3", 75}, \ | ||
| 38 | - {"d7", 77}, \ | ||
| 39 | - {"d8", 79}, {"q4", 79}, \ | ||
| 40 | - {"d9", 81}, \ | ||
| 41 | - {"d10", 83}, {"q5", 83}, \ | ||
| 42 | - {"d11", 85}, \ | ||
| 43 | - {"d12", 87}, {"q6", 87}, \ | ||
| 44 | - {"d13", 89}, \ | ||
| 45 | - {"d14", 91}, {"q7", 91}, \ | ||
| 46 | - {"d15", 93}, \ | ||
| 47 | - {"q8", 95}, \ | ||
| 48 | - {"q9", 99}, \ | ||
| 49 | - {"q10", 103}, \ | ||
| 50 | - {"q11", 107}, \ | ||
| 51 | - {"q12", 111}, \ | ||
| 52 | - {"q13", 115}, \ | ||
| 53 | - {"q14", 119}, \ | ||
| 54 | - {"q15", 123} \ | ||
| 55 | + {"mvdx15", 42} \ | ||
| 56 | +} | ||
| 57 | +#endif | ||
| 58 | + | ||
| 59 | +#ifndef OVERLAPPING_REGISTER_NAMES | ||
| 60 | +#define OVERLAPPING_REGISTER_NAMES \ | ||
| 61 | +{ \ | ||
| 62 | + {"d0", 63, 2}, \ | ||
| 63 | + {"d1", 65, 2}, \ | ||
| 64 | + {"d2", 67, 2}, \ | ||
| 65 | + {"d3", 69, 2}, \ | ||
| 66 | + {"d4", 71, 2}, \ | ||
| 67 | + {"d5", 73, 2}, \ | ||
| 68 | + {"d6", 75, 2}, \ | ||
| 69 | + {"d7", 77, 2}, \ | ||
| 70 | + {"d8", 79, 2}, \ | ||
| 71 | + {"d9", 81, 2}, \ | ||
| 72 | + {"d10", 83, 2}, \ | ||
| 73 | + {"d11", 85, 2}, \ | ||
| 74 | + {"d12", 87, 2}, \ | ||
| 75 | + {"d13", 89, 2}, \ | ||
| 76 | + {"d14", 91, 2}, \ | ||
| 77 | + {"d15", 93, 2}, \ | ||
| 78 | + {"q0", 63, 4}, \ | ||
| 79 | + {"q1", 67, 4}, \ | ||
| 80 | + {"q2", 71, 4}, \ | ||
| 81 | + {"q3", 75, 4}, \ | ||
| 82 | + {"q4", 79, 4}, \ | ||
| 83 | + {"q5", 83, 4}, \ | ||
| 84 | + {"q6", 87, 4}, \ | ||
| 85 | + {"q7", 91, 4}, \ | ||
| 86 | + {"q8", 95, 4}, \ | ||
| 87 | + {"q9", 99, 4}, \ | ||
| 88 | + {"q10", 103, 4}, \ | ||
| 89 | + {"q11", 107, 4}, \ | ||
| 90 | + {"q12", 111, 4}, \ | ||
| 91 | + {"q13", 115, 4}, \ | ||
| 92 | + {"q14", 119, 4}, \ | ||
| 93 | + {"q15", 123, 4} \ | ||
| 94 | } | ||
| 95 | #endif | ||
| 96 | |||
| 97 | |||
| 98 | === modified file 'gcc/doc/tm.texi' | ||
| 99 | --- old/gcc/doc/tm.texi 2010-06-24 20:06:37 +0000 | ||
| 100 | +++ new/gcc/doc/tm.texi 2010-08-13 11:53:46 +0000 | ||
| 101 | @@ -8339,6 +8339,22 @@ | ||
| 102 | to registers using alternate names. | ||
| 103 | @end defmac | ||
| 104 | |||
| 105 | +@defmac OVERLAPPING_REGISTER_NAMES | ||
| 106 | +If defined, a C initializer for an array of structures containing a | ||
| 107 | +name, a register number and a count of the number of consecutive | ||
| 108 | +machine registers the name overlaps. This macro defines additional | ||
| 109 | +names for hard registers, thus allowing the @code{asm} option in | ||
| 110 | +declarations to refer to registers using alternate names. Unlike | ||
| 111 | +@code{ADDITIONAL_REGISTER_NAMES}, this macro should be used when the | ||
| 112 | +register name implies multiple underlying registers. | ||
| 113 | + | ||
| 114 | +This macro should be used when it is important that a clobber in an | ||
| 115 | +@code{asm} statement clobbers all the underlying values implied by the | ||
| 116 | +register name. For example, on ARM, clobbering the double-precision | ||
| 117 | +VFP register ``d0'' implies clobbering both single-precision registers | ||
| 118 | +``s0'' and ``s1''. | ||
| 119 | +@end defmac | ||
| 120 | + | ||
| 121 | @defmac ASM_OUTPUT_OPCODE (@var{stream}, @var{ptr}) | ||
| 122 | Define this macro if you are using an unusual assembler that | ||
| 123 | requires different names for the machine instructions. | ||
| 124 | |||
| 125 | === modified file 'gcc/output.h' | ||
| 126 | --- old/gcc/output.h 2009-10-26 21:57:10 +0000 | ||
| 127 | +++ new/gcc/output.h 2010-08-13 11:53:46 +0000 | ||
| 128 | @@ -173,6 +173,11 @@ | ||
| 129 | Prefixes such as % are optional. */ | ||
| 130 | extern int decode_reg_name (const char *); | ||
| 131 | |||
| 132 | +/* Similar to decode_reg_name, but takes an extra parameter that is a | ||
| 133 | + pointer to the number of (internal) registers described by the | ||
| 134 | + external name. */ | ||
| 135 | +extern int decode_reg_name_and_count (const char *, int *); | ||
| 136 | + | ||
| 137 | extern void assemble_alias (tree, tree); | ||
| 138 | |||
| 139 | extern void default_assemble_visibility (tree, int); | ||
| 140 | |||
| 141 | === modified file 'gcc/reginfo.c' | ||
| 142 | --- old/gcc/reginfo.c 2010-04-19 09:04:43 +0000 | ||
| 143 | +++ new/gcc/reginfo.c 2010-08-13 11:53:46 +0000 | ||
| 144 | @@ -799,36 +799,41 @@ | ||
| 145 | fix_register (const char *name, int fixed, int call_used) | ||
| 146 | { | ||
| 147 | int i; | ||
| 148 | + int reg, nregs; | ||
| 149 | |||
| 150 | /* Decode the name and update the primary form of | ||
| 151 | the register info. */ | ||
| 152 | |||
| 153 | - if ((i = decode_reg_name (name)) >= 0) | ||
| 154 | + if ((reg = decode_reg_name_and_count (name, &nregs)) >= 0) | ||
| 155 | { | ||
| 156 | - if ((i == STACK_POINTER_REGNUM | ||
| 157 | + gcc_assert (nregs >= 1); | ||
| 158 | + for (i = reg; i < reg + nregs; i++) | ||
| 159 | + { | ||
| 160 | + if ((i == STACK_POINTER_REGNUM | ||
| 161 | #ifdef HARD_FRAME_POINTER_REGNUM | ||
| 162 | - || i == HARD_FRAME_POINTER_REGNUM | ||
| 163 | + || i == HARD_FRAME_POINTER_REGNUM | ||
| 164 | #else | ||
| 165 | - || i == FRAME_POINTER_REGNUM | ||
| 166 | + || i == FRAME_POINTER_REGNUM | ||
| 167 | #endif | ||
| 168 | - ) | ||
| 169 | - && (fixed == 0 || call_used == 0)) | ||
| 170 | - { | ||
| 171 | - static const char * const what_option[2][2] = { | ||
| 172 | - { "call-saved", "call-used" }, | ||
| 173 | - { "no-such-option", "fixed" }}; | ||
| 174 | + ) | ||
| 175 | + && (fixed == 0 || call_used == 0)) | ||
| 176 | + { | ||
| 177 | + static const char * const what_option[2][2] = { | ||
| 178 | + { "call-saved", "call-used" }, | ||
| 179 | + { "no-such-option", "fixed" }}; | ||
| 180 | |||
| 181 | - error ("can't use '%s' as a %s register", name, | ||
| 182 | - what_option[fixed][call_used]); | ||
| 183 | - } | ||
| 184 | - else | ||
| 185 | - { | ||
| 186 | - fixed_regs[i] = fixed; | ||
| 187 | - call_used_regs[i] = call_used; | ||
| 188 | + error ("can't use '%s' as a %s register", name, | ||
| 189 | + what_option[fixed][call_used]); | ||
| 190 | + } | ||
| 191 | + else | ||
| 192 | + { | ||
| 193 | + fixed_regs[i] = fixed; | ||
| 194 | + call_used_regs[i] = call_used; | ||
| 195 | #ifdef CALL_REALLY_USED_REGISTERS | ||
| 196 | - if (fixed == 0) | ||
| 197 | - call_really_used_regs[i] = call_used; | ||
| 198 | + if (fixed == 0) | ||
| 199 | + call_really_used_regs[i] = call_used; | ||
| 200 | #endif | ||
| 201 | + } | ||
| 202 | } | ||
| 203 | } | ||
| 204 | else | ||
| 205 | |||
| 206 | === modified file 'gcc/stmt.c' | ||
| 207 | --- old/gcc/stmt.c 2010-02-19 09:53:51 +0000 | ||
| 208 | +++ new/gcc/stmt.c 2010-08-13 11:53:46 +0000 | ||
| 209 | @@ -684,13 +684,14 @@ | ||
| 210 | for (tail = clobbers; tail; tail = TREE_CHAIN (tail)) | ||
| 211 | { | ||
| 212 | const char *regname; | ||
| 213 | + int nregs; | ||
| 214 | |||
| 215 | if (TREE_VALUE (tail) == error_mark_node) | ||
| 216 | return; | ||
| 217 | regname = TREE_STRING_POINTER (TREE_VALUE (tail)); | ||
| 218 | |||
| 219 | - i = decode_reg_name (regname); | ||
| 220 | - if (i >= 0 || i == -4) | ||
| 221 | + i = decode_reg_name_and_count (regname, &nregs); | ||
| 222 | + if (i == -4) | ||
| 223 | ++nclobbers; | ||
| 224 | else if (i == -2) | ||
| 225 | error ("unknown register name %qs in %<asm%>", regname); | ||
| 226 | @@ -698,14 +699,21 @@ | ||
| 227 | /* Mark clobbered registers. */ | ||
| 228 | if (i >= 0) | ||
| 229 | { | ||
| 230 | - /* Clobbering the PIC register is an error. */ | ||
| 231 | - if (i == (int) PIC_OFFSET_TABLE_REGNUM) | ||
| 232 | + int reg; | ||
| 233 | + | ||
| 234 | + for (reg = i; reg < i + nregs; reg++) | ||
| 235 | { | ||
| 236 | - error ("PIC register %qs clobbered in %<asm%>", regname); | ||
| 237 | - return; | ||
| 238 | + ++nclobbers; | ||
| 239 | + | ||
| 240 | + /* Clobbering the PIC register is an error. */ | ||
| 241 | + if (reg == (int) PIC_OFFSET_TABLE_REGNUM) | ||
| 242 | + { | ||
| 243 | + error ("PIC register clobbered by %qs in %<asm%>", regname); | ||
| 244 | + return; | ||
| 245 | + } | ||
| 246 | + | ||
| 247 | + SET_HARD_REG_BIT (clobbered_regs, reg); | ||
| 248 | } | ||
| 249 | - | ||
| 250 | - SET_HARD_REG_BIT (clobbered_regs, i); | ||
| 251 | } | ||
| 252 | } | ||
| 253 | |||
| 254 | @@ -1026,7 +1034,8 @@ | ||
| 255 | for (tail = clobbers; tail; tail = TREE_CHAIN (tail)) | ||
| 256 | { | ||
| 257 | const char *regname = TREE_STRING_POINTER (TREE_VALUE (tail)); | ||
| 258 | - int j = decode_reg_name (regname); | ||
| 259 | + int reg, nregs; | ||
| 260 | + int j = decode_reg_name_and_count (regname, &nregs); | ||
| 261 | rtx clobbered_reg; | ||
| 262 | |||
| 263 | if (j < 0) | ||
| 264 | @@ -1048,30 +1057,39 @@ | ||
| 265 | continue; | ||
| 266 | } | ||
| 267 | |||
| 268 | - /* Use QImode since that's guaranteed to clobber just one reg. */ | ||
| 269 | - clobbered_reg = gen_rtx_REG (QImode, j); | ||
| 270 | - | ||
| 271 | - /* Do sanity check for overlap between clobbers and respectively | ||
| 272 | - input and outputs that hasn't been handled. Such overlap | ||
| 273 | - should have been detected and reported above. */ | ||
| 274 | - if (!clobber_conflict_found) | ||
| 275 | + for (reg = j; reg < j + nregs; reg++) | ||
| 276 | { | ||
| 277 | - int opno; | ||
| 278 | - | ||
| 279 | - /* We test the old body (obody) contents to avoid tripping | ||
| 280 | - over the under-construction body. */ | ||
| 281 | - for (opno = 0; opno < noutputs; opno++) | ||
| 282 | - if (reg_overlap_mentioned_p (clobbered_reg, output_rtx[opno])) | ||
| 283 | - internal_error ("asm clobber conflict with output operand"); | ||
| 284 | - | ||
| 285 | - for (opno = 0; opno < ninputs - ninout; opno++) | ||
| 286 | - if (reg_overlap_mentioned_p (clobbered_reg, | ||
| 287 | - ASM_OPERANDS_INPUT (obody, opno))) | ||
| 288 | - internal_error ("asm clobber conflict with input operand"); | ||
| 289 | + /* Use QImode since that's guaranteed to clobber just | ||
| 290 | + * one reg. */ | ||
| 291 | + clobbered_reg = gen_rtx_REG (QImode, reg); | ||
| 292 | + | ||
| 293 | + /* Do sanity check for overlap between clobbers and | ||
| 294 | + respectively input and outputs that hasn't been | ||
| 295 | + handled. Such overlap should have been detected and | ||
| 296 | + reported above. */ | ||
| 297 | + if (!clobber_conflict_found) | ||
| 298 | + { | ||
| 299 | + int opno; | ||
| 300 | + | ||
| 301 | + /* We test the old body (obody) contents to avoid | ||
| 302 | + tripping over the under-construction body. */ | ||
| 303 | + for (opno = 0; opno < noutputs; opno++) | ||
| 304 | + if (reg_overlap_mentioned_p (clobbered_reg, | ||
| 305 | + output_rtx[opno])) | ||
| 306 | + internal_error | ||
| 307 | + ("asm clobber conflict with output operand"); | ||
| 308 | + | ||
| 309 | + for (opno = 0; opno < ninputs - ninout; opno++) | ||
| 310 | + if (reg_overlap_mentioned_p (clobbered_reg, | ||
| 311 | + ASM_OPERANDS_INPUT (obody, | ||
| 312 | + opno))) | ||
| 313 | + internal_error | ||
| 314 | + ("asm clobber conflict with input operand"); | ||
| 315 | + } | ||
| 316 | + | ||
| 317 | + XVECEXP (body, 0, i++) | ||
| 318 | + = gen_rtx_CLOBBER (VOIDmode, clobbered_reg); | ||
| 319 | } | ||
| 320 | - | ||
| 321 | - XVECEXP (body, 0, i++) | ||
| 322 | - = gen_rtx_CLOBBER (VOIDmode, clobbered_reg); | ||
| 323 | } | ||
| 324 | |||
| 325 | if (nlabels > 0) | ||
| 326 | |||
| 327 | === modified file 'gcc/varasm.c' | ||
| 328 | --- old/gcc/varasm.c 2010-03-27 11:56:30 +0000 | ||
| 329 | +++ new/gcc/varasm.c 2010-08-13 11:53:46 +0000 | ||
| 330 | @@ -1043,8 +1043,11 @@ | ||
| 331 | Prefixes such as % are optional. */ | ||
| 332 | |||
| 333 | int | ||
| 334 | -decode_reg_name (const char *asmspec) | ||
| 335 | +decode_reg_name_and_count (const char *asmspec, int *pnregs) | ||
| 336 | { | ||
| 337 | + /* Presume just one register is clobbered. */ | ||
| 338 | + *pnregs = 1; | ||
| 339 | + | ||
| 340 | if (asmspec != 0) | ||
| 341 | { | ||
| 342 | int i; | ||
| 343 | @@ -1070,6 +1073,25 @@ | ||
| 344 | && ! strcmp (asmspec, strip_reg_name (reg_names[i]))) | ||
| 345 | return i; | ||
| 346 | |||
| 347 | +#ifdef OVERLAPPING_REGISTER_NAMES | ||
| 348 | + { | ||
| 349 | + static const struct | ||
| 350 | + { | ||
| 351 | + const char *const name; | ||
| 352 | + const int number; | ||
| 353 | + const int nregs; | ||
| 354 | + } table[] = OVERLAPPING_REGISTER_NAMES; | ||
| 355 | + | ||
| 356 | + for (i = 0; i < (int) ARRAY_SIZE (table); i++) | ||
| 357 | + if (table[i].name[0] | ||
| 358 | + && ! strcmp (asmspec, table[i].name)) | ||
| 359 | + { | ||
| 360 | + *pnregs = table[i].nregs; | ||
| 361 | + return table[i].number; | ||
| 362 | + } | ||
| 363 | + } | ||
| 364 | +#endif /* OVERLAPPING_REGISTER_NAMES */ | ||
| 365 | + | ||
| 366 | #ifdef ADDITIONAL_REGISTER_NAMES | ||
| 367 | { | ||
| 368 | static const struct { const char *const name; const int number; } table[] | ||
| 369 | @@ -1093,6 +1115,14 @@ | ||
| 370 | |||
| 371 | return -1; | ||
| 372 | } | ||
| 373 | + | ||
| 374 | +int | ||
| 375 | +decode_reg_name (const char *name) | ||
| 376 | +{ | ||
| 377 | + int count; | ||
| 378 | + return decode_reg_name_and_count (name, &count); | ||
| 379 | +} | ||
| 380 | + | ||
| 381 | |||
| 382 | /* Return true if DECL's initializer is suitable for a BSS section. */ | ||
| 383 | |||
| 384 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99355.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99355.patch deleted file mode 100644 index b47c2ceb4..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99355.patch +++ /dev/null | |||
| @@ -1,181 +0,0 @@ | |||
| 1 | 2010-04-12 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #7178 | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * config/arm/arm.c (arm_init_libfuncs): Change __gnu_f2h_ieee to | ||
| 7 | __aeabi_f2h, __gnu_f2h_alternative to __aeabi_f2h_alt, __gnu_h2f_ieee | ||
| 8 | to __aeabi_h2f, and __gnu_h2f_alternative to __aeabi_h2f_alt. | ||
| 9 | * config/arm/fp16.c (__gnu_f2h_internal): Change return type to | ||
| 10 | unsigned int. Change 'sign' variable likewise. | ||
| 11 | (__gnu_h2f_internal): Set to static inline. | ||
| 12 | Change return type to unsigned int. Change 'sign' variable likewise. | ||
| 13 | (ALIAS): New define. | ||
| 14 | (__gnu_f2h_ieee): Change unsigned short to unsigned int. | ||
| 15 | (__gnu_h2f_ieee): Likewise. | ||
| 16 | (__gnu_f2h_alternative): Likewise. | ||
| 17 | (__gnu_h2f_alternative): Likewise. | ||
| 18 | (__aeabi_f2h, __aeabi_h2f): New aliases. | ||
| 19 | (__aeabi_f2h_alt, __aeabi_h2f_alt): Likewise. | ||
| 20 | * config/arm/sfp-machine.h (__extendhfsf2): Set to __aeabi_h2f. | ||
| 21 | (__truncsfhf2): Set to __aeabi_f2h. | ||
| 22 | |||
| 23 | gcc/testsuite/ | ||
| 24 | * g++.dg/ext/arm-fp16/arm-fp16-ops-5.C: Check for __aeabi_h2f | ||
| 25 | and __aeabi_f2h. | ||
| 26 | * g++.dg/ext/arm-fp16/arm-fp16-ops-6.C: Likewise. | ||
| 27 | * gcc.dg/torture/arm-fp16-ops-5.c: Likewise. | ||
| 28 | * gcc.dg/torture/arm-fp16-ops-6.c: Likewise. | ||
| 29 | |||
| 30 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 31 | |||
| 32 | Merge from Sourcery G++ 4.4: | ||
| 33 | |||
| 34 | Richard Earnshaw <rearnsha@arm.com> | ||
| 35 | |||
| 36 | gcc/ | ||
| 37 | |||
| 38 | === modified file 'gcc/config/arm/arm.c' | ||
| 39 | --- old/gcc/config/arm/arm.c 2010-08-13 11:02:47 +0000 | ||
| 40 | +++ new/gcc/config/arm/arm.c 2010-08-13 14:08:20 +0000 | ||
| 41 | @@ -1054,12 +1054,12 @@ | ||
| 42 | /* Conversions. */ | ||
| 43 | set_conv_libfunc (trunc_optab, HFmode, SFmode, | ||
| 44 | (arm_fp16_format == ARM_FP16_FORMAT_IEEE | ||
| 45 | - ? "__gnu_f2h_ieee" | ||
| 46 | - : "__gnu_f2h_alternative")); | ||
| 47 | + ? "__aeabi_f2h" | ||
| 48 | + : "__aeabi_f2h_alt")); | ||
| 49 | set_conv_libfunc (sext_optab, SFmode, HFmode, | ||
| 50 | (arm_fp16_format == ARM_FP16_FORMAT_IEEE | ||
| 51 | - ? "__gnu_h2f_ieee" | ||
| 52 | - : "__gnu_h2f_alternative")); | ||
| 53 | + ? "__aeabi_h2f" | ||
| 54 | + : "__aeabi_h2f_alt")); | ||
| 55 | |||
| 56 | /* Arithmetic. */ | ||
| 57 | set_optab_libfunc (add_optab, HFmode, NULL); | ||
| 58 | |||
| 59 | === modified file 'gcc/config/arm/fp16.c' | ||
| 60 | --- old/gcc/config/arm/fp16.c 2009-06-18 11:26:37 +0000 | ||
| 61 | +++ new/gcc/config/arm/fp16.c 2010-08-13 14:08:20 +0000 | ||
| 62 | @@ -22,10 +22,10 @@ | ||
| 63 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | ||
| 64 | <http://www.gnu.org/licenses/>. */ | ||
| 65 | |||
| 66 | -static inline unsigned short | ||
| 67 | +static inline unsigned int | ||
| 68 | __gnu_f2h_internal(unsigned int a, int ieee) | ||
| 69 | { | ||
| 70 | - unsigned short sign = (a >> 16) & 0x8000; | ||
| 71 | + unsigned int sign = (a >> 16) & 0x8000; | ||
| 72 | int aexp = (a >> 23) & 0xff; | ||
| 73 | unsigned int mantissa = a & 0x007fffff; | ||
| 74 | unsigned int mask; | ||
| 75 | @@ -95,10 +95,10 @@ | ||
| 76 | return sign | (((aexp + 14) << 10) + (mantissa >> 13)); | ||
| 77 | } | ||
| 78 | |||
| 79 | -unsigned int | ||
| 80 | -__gnu_h2f_internal(unsigned short a, int ieee) | ||
| 81 | +static inline unsigned int | ||
| 82 | +__gnu_h2f_internal(unsigned int a, int ieee) | ||
| 83 | { | ||
| 84 | - unsigned int sign = (unsigned int)(a & 0x8000) << 16; | ||
| 85 | + unsigned int sign = (a & 0x00008000) << 16; | ||
| 86 | int aexp = (a >> 10) & 0x1f; | ||
| 87 | unsigned int mantissa = a & 0x3ff; | ||
| 88 | |||
| 89 | @@ -120,26 +120,33 @@ | ||
| 90 | return sign | (((aexp + 0x70) << 23) + (mantissa << 13)); | ||
| 91 | } | ||
| 92 | |||
| 93 | -unsigned short | ||
| 94 | +#define ALIAS(src, dst) \ | ||
| 95 | + typeof (src) dst __attribute__ ((alias (#src))); | ||
| 96 | + | ||
| 97 | +unsigned int | ||
| 98 | __gnu_f2h_ieee(unsigned int a) | ||
| 99 | { | ||
| 100 | return __gnu_f2h_internal(a, 1); | ||
| 101 | } | ||
| 102 | +ALIAS (__gnu_f2h_ieee, __aeabi_f2h) | ||
| 103 | |||
| 104 | unsigned int | ||
| 105 | -__gnu_h2f_ieee(unsigned short a) | ||
| 106 | +__gnu_h2f_ieee(unsigned int a) | ||
| 107 | { | ||
| 108 | return __gnu_h2f_internal(a, 1); | ||
| 109 | } | ||
| 110 | +ALIAS (__gnu_h2f_ieee, __aeabi_h2f) | ||
| 111 | |||
| 112 | -unsigned short | ||
| 113 | +unsigned int | ||
| 114 | __gnu_f2h_alternative(unsigned int x) | ||
| 115 | { | ||
| 116 | return __gnu_f2h_internal(x, 0); | ||
| 117 | } | ||
| 118 | +ALIAS (__gnu_f2h_alternative, __aeabi_f2h_alt) | ||
| 119 | |||
| 120 | unsigned int | ||
| 121 | -__gnu_h2f_alternative(unsigned short a) | ||
| 122 | +__gnu_h2f_alternative(unsigned int a) | ||
| 123 | { | ||
| 124 | return __gnu_h2f_internal(a, 0); | ||
| 125 | } | ||
| 126 | +ALIAS (__gnu_h2f_alternative, __aeabi_h2f_alt) | ||
| 127 | |||
| 128 | === modified file 'gcc/config/arm/sfp-machine.h' | ||
| 129 | --- old/gcc/config/arm/sfp-machine.h 2009-06-18 11:26:37 +0000 | ||
| 130 | +++ new/gcc/config/arm/sfp-machine.h 2010-08-13 14:08:20 +0000 | ||
| 131 | @@ -99,7 +99,7 @@ | ||
| 132 | #define __fixdfdi __aeabi_d2lz | ||
| 133 | #define __fixunsdfdi __aeabi_d2ulz | ||
| 134 | #define __floatdidf __aeabi_l2d | ||
| 135 | -#define __extendhfsf2 __gnu_h2f_ieee | ||
| 136 | -#define __truncsfhf2 __gnu_f2h_ieee | ||
| 137 | +#define __extendhfsf2 __aeabi_h2f | ||
| 138 | +#define __truncsfhf2 __aeabi_f2h | ||
| 139 | |||
| 140 | #endif /* __ARM_EABI__ */ | ||
| 141 | |||
| 142 | === modified file 'gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C' | ||
| 143 | --- old/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C 2010-07-29 15:38:15 +0000 | ||
| 144 | +++ new/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C 2010-08-13 14:08:20 +0000 | ||
| 145 | @@ -13,3 +13,5 @@ | ||
| 146 | /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */ | ||
| 147 | /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */ | ||
| 148 | /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */ | ||
| 149 | +/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */ | ||
| 150 | +/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */ | ||
| 151 | |||
| 152 | === modified file 'gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C' | ||
| 153 | --- old/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C 2010-07-29 15:38:15 +0000 | ||
| 154 | +++ new/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C 2010-08-13 14:08:20 +0000 | ||
| 155 | @@ -13,3 +13,5 @@ | ||
| 156 | /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */ | ||
| 157 | /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */ | ||
| 158 | /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */ | ||
| 159 | +/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */ | ||
| 160 | +/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */ | ||
| 161 | |||
| 162 | === modified file 'gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c' | ||
| 163 | --- old/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c 2010-07-29 15:38:15 +0000 | ||
| 164 | +++ new/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c 2010-08-13 14:08:20 +0000 | ||
| 165 | @@ -13,3 +13,5 @@ | ||
| 166 | /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */ | ||
| 167 | /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */ | ||
| 168 | /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */ | ||
| 169 | +/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */ | ||
| 170 | +/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */ | ||
| 171 | |||
| 172 | === modified file 'gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c' | ||
| 173 | --- old/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c 2010-07-29 15:38:15 +0000 | ||
| 174 | +++ new/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c 2010-08-13 14:08:20 +0000 | ||
| 175 | @@ -13,3 +13,5 @@ | ||
| 176 | /* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */ | ||
| 177 | /* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */ | ||
| 178 | /* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */ | ||
| 179 | +/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */ | ||
| 180 | +/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */ | ||
| 181 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99356.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99356.patch deleted file mode 100644 index 64efbc759..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99356.patch +++ /dev/null | |||
| @@ -1,376 +0,0 @@ | |||
| 1 | |||
| 2 | 2010-04-11 Julian Brown <julian@codesourcery.com> | ||
| 3 | |||
| 4 | Issue #7326 | ||
| 5 | |||
| 6 | gcc/ | ||
| 7 | * config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5. | ||
| 8 | * config/arm/arm.md (generic_sched): No for Cortex-A5. | ||
| 9 | (generic_vfp): Likewise. | ||
| 10 | (cortex-a5.md): Include. | ||
| 11 | * config/arm/cortex-a5.md: New. | ||
| 12 | |||
| 13 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 14 | |||
| 15 | Merge from Sourcery G++ 4.4: | ||
| 16 | |||
| 17 | 2010-04-12 Andrew Stubbs <ams@codesourcery.com> | ||
| 18 | |||
| 19 | |||
| 20 | === modified file 'gcc/config/arm/arm.c' | ||
| 21 | --- old/gcc/config/arm/arm.c 2010-08-13 14:08:20 +0000 | ||
| 22 | +++ new/gcc/config/arm/arm.c 2010-08-13 15:15:12 +0000 | ||
| 23 | @@ -22262,6 +22262,7 @@ | ||
| 24 | { | ||
| 25 | case cortexr4: | ||
| 26 | case cortexr4f: | ||
| 27 | + case cortexa5: | ||
| 28 | case cortexa8: | ||
| 29 | case cortexa9: | ||
| 30 | return 2; | ||
| 31 | |||
| 32 | === modified file 'gcc/config/arm/arm.md' | ||
| 33 | --- old/gcc/config/arm/arm.md 2010-08-13 11:40:17 +0000 | ||
| 34 | +++ new/gcc/config/arm/arm.md 2010-08-13 15:15:12 +0000 | ||
| 35 | @@ -419,7 +419,7 @@ | ||
| 36 | |||
| 37 | (define_attr "generic_sched" "yes,no" | ||
| 38 | (const (if_then_else | ||
| 39 | - (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9") | ||
| 40 | + (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9") | ||
| 41 | (eq_attr "tune_cortexr4" "yes")) | ||
| 42 | (const_string "no") | ||
| 43 | (const_string "yes")))) | ||
| 44 | @@ -427,7 +427,7 @@ | ||
| 45 | (define_attr "generic_vfp" "yes,no" | ||
| 46 | (const (if_then_else | ||
| 47 | (and (eq_attr "fpu" "vfp") | ||
| 48 | - (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9") | ||
| 49 | + (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9") | ||
| 50 | (eq_attr "tune_cortexr4" "no")) | ||
| 51 | (const_string "yes") | ||
| 52 | (const_string "no")))) | ||
| 53 | @@ -451,6 +451,7 @@ | ||
| 54 | (include "arm1020e.md") | ||
| 55 | (include "arm1026ejs.md") | ||
| 56 | (include "arm1136jfs.md") | ||
| 57 | +(include "cortex-a5.md") | ||
| 58 | (include "cortex-a8.md") | ||
| 59 | (include "cortex-a9.md") | ||
| 60 | (include "cortex-r4.md") | ||
| 61 | |||
| 62 | === added file 'gcc/config/arm/cortex-a5.md' | ||
| 63 | --- old/gcc/config/arm/cortex-a5.md 1970-01-01 00:00:00 +0000 | ||
| 64 | +++ new/gcc/config/arm/cortex-a5.md 2010-08-13 15:15:12 +0000 | ||
| 65 | @@ -0,0 +1,310 @@ | ||
| 66 | +;; ARM Cortex-A5 pipeline description | ||
| 67 | +;; Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 68 | +;; Contributed by CodeSourcery. | ||
| 69 | +;; | ||
| 70 | +;; This file is part of GCC. | ||
| 71 | +;; | ||
| 72 | +;; GCC is free software; you can redistribute it and/or modify it | ||
| 73 | +;; under the terms of the GNU General Public License as published by | ||
| 74 | +;; the Free Software Foundation; either version 3, or (at your option) | ||
| 75 | +;; any later version. | ||
| 76 | +;; | ||
| 77 | +;; GCC is distributed in the hope that it will be useful, but | ||
| 78 | +;; WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 79 | +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 80 | +;; General Public License for more details. | ||
| 81 | +;; | ||
| 82 | +;; You should have received a copy of the GNU General Public License | ||
| 83 | +;; along with GCC; see the file COPYING3. If not see | ||
| 84 | +;; <http://www.gnu.org/licenses/>. | ||
| 85 | + | ||
| 86 | +(define_automaton "cortex_a5") | ||
| 87 | + | ||
| 88 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 89 | +;; Functional units. | ||
| 90 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 91 | + | ||
| 92 | +;; The integer (ALU) pipeline. There are five DPU pipeline stages. However the | ||
| 93 | +;; decode/issue stages operate the same for all instructions, so do not model | ||
| 94 | +;; them. We only need to model the first execute stage because instructions | ||
| 95 | +;; always advance one stage per cycle in order. Only branch instructions may | ||
| 96 | +;; dual-issue, so a single unit covers all of the LS, ALU, MAC and FPU | ||
| 97 | +;; pipelines. | ||
| 98 | + | ||
| 99 | +(define_cpu_unit "cortex_a5_ex1" "cortex_a5") | ||
| 100 | + | ||
| 101 | +;; The branch pipeline. Branches can dual-issue with other instructions | ||
| 102 | +;; (except when those instructions take multiple cycles to issue). | ||
| 103 | + | ||
| 104 | +(define_cpu_unit "cortex_a5_branch" "cortex_a5") | ||
| 105 | + | ||
| 106 | +;; Pseudo-unit for blocking the multiply pipeline when a double-precision | ||
| 107 | +;; multiply is in progress. | ||
| 108 | + | ||
| 109 | +(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5") | ||
| 110 | + | ||
| 111 | +;; The floating-point add pipeline (ex1/f1 stage), used to model the usage | ||
| 112 | +;; of the add pipeline by fmac instructions, etc. | ||
| 113 | + | ||
| 114 | +(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5") | ||
| 115 | + | ||
| 116 | +;; Floating-point div/sqrt (long latency, out-of-order completion). | ||
| 117 | + | ||
| 118 | +(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5") | ||
| 119 | + | ||
| 120 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 121 | +;; ALU instructions. | ||
| 122 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 123 | + | ||
| 124 | +(define_insn_reservation "cortex_a5_alu" 2 | ||
| 125 | + (and (eq_attr "tune" "cortexa5") | ||
| 126 | + (eq_attr "type" "alu")) | ||
| 127 | + "cortex_a5_ex1") | ||
| 128 | + | ||
| 129 | +(define_insn_reservation "cortex_a5_alu_shift" 2 | ||
| 130 | + (and (eq_attr "tune" "cortexa5") | ||
| 131 | + (eq_attr "type" "alu_shift,alu_shift_reg")) | ||
| 132 | + "cortex_a5_ex1") | ||
| 133 | + | ||
| 134 | +;; Forwarding path for unshifted operands. | ||
| 135 | + | ||
| 136 | +(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" | ||
| 137 | + "cortex_a5_alu") | ||
| 138 | + | ||
| 139 | +(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" | ||
| 140 | + "cortex_a5_alu_shift" | ||
| 141 | + "arm_no_early_alu_shift_dep") | ||
| 142 | + | ||
| 143 | +;; The multiplier pipeline can forward results from wr stage only (so I don't | ||
| 144 | +;; think there's any need to specify bypasses). | ||
| 145 | + | ||
| 146 | +(define_insn_reservation "cortex_a5_mul" 2 | ||
| 147 | + (and (eq_attr "tune" "cortexa5") | ||
| 148 | + (eq_attr "type" "mult")) | ||
| 149 | + "cortex_a5_ex1") | ||
| 150 | + | ||
| 151 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 152 | +;; Load/store instructions. | ||
| 153 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 154 | + | ||
| 155 | +;; Address-generation happens in the issue stage, which is one stage behind | ||
| 156 | +;; the ex1 stage (the first stage we care about for scheduling purposes). The | ||
| 157 | +;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr. | ||
| 158 | + | ||
| 159 | +;; FIXME: These might not be entirely accurate for load2, load3, load4. I think | ||
| 160 | +;; they make sense since there's a 32-bit interface between the DPU and the DCU, | ||
| 161 | +;; so we can't load more than that per cycle. The store2, store3, store4 | ||
| 162 | +;; reservations are similarly guessed. | ||
| 163 | + | ||
| 164 | +(define_insn_reservation "cortex_a5_load1" 2 | ||
| 165 | + (and (eq_attr "tune" "cortexa5") | ||
| 166 | + (eq_attr "type" "load_byte,load1")) | ||
| 167 | + "cortex_a5_ex1") | ||
| 168 | + | ||
| 169 | +(define_insn_reservation "cortex_a5_store1" 0 | ||
| 170 | + (and (eq_attr "tune" "cortexa5") | ||
| 171 | + (eq_attr "type" "store1")) | ||
| 172 | + "cortex_a5_ex1") | ||
| 173 | + | ||
| 174 | +(define_insn_reservation "cortex_a5_load2" 3 | ||
| 175 | + (and (eq_attr "tune" "cortexa5") | ||
| 176 | + (eq_attr "type" "load2")) | ||
| 177 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 178 | + | ||
| 179 | +(define_insn_reservation "cortex_a5_store2" 0 | ||
| 180 | + (and (eq_attr "tune" "cortexa5") | ||
| 181 | + (eq_attr "type" "store2")) | ||
| 182 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 183 | + | ||
| 184 | +(define_insn_reservation "cortex_a5_load3" 4 | ||
| 185 | + (and (eq_attr "tune" "cortexa5") | ||
| 186 | + (eq_attr "type" "load3")) | ||
| 187 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ | ||
| 188 | + cortex_a5_ex1") | ||
| 189 | + | ||
| 190 | +(define_insn_reservation "cortex_a5_store3" 0 | ||
| 191 | + (and (eq_attr "tune" "cortexa5") | ||
| 192 | + (eq_attr "type" "store3")) | ||
| 193 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ | ||
| 194 | + cortex_a5_ex1") | ||
| 195 | + | ||
| 196 | +(define_insn_reservation "cortex_a5_load4" 5 | ||
| 197 | + (and (eq_attr "tune" "cortexa5") | ||
| 198 | + (eq_attr "type" "load3")) | ||
| 199 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ | ||
| 200 | + cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 201 | + | ||
| 202 | +(define_insn_reservation "cortex_a5_store4" 0 | ||
| 203 | + (and (eq_attr "tune" "cortexa5") | ||
| 204 | + (eq_attr "type" "store3")) | ||
| 205 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ | ||
| 206 | + cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 207 | + | ||
| 208 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 209 | +;; Branches. | ||
| 210 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 211 | + | ||
| 212 | +;; Direct branches are the only instructions we can dual-issue (also IT and | ||
| 213 | +;; nop, but those aren't very interesting for scheduling). (The latency here | ||
| 214 | +;; is meant to represent when the branch actually takes place, but may not be | ||
| 215 | +;; entirely correct.) | ||
| 216 | + | ||
| 217 | +(define_insn_reservation "cortex_a5_branch" 3 | ||
| 218 | + (and (eq_attr "tune" "cortexa5") | ||
| 219 | + (eq_attr "type" "branch,call")) | ||
| 220 | + "cortex_a5_branch") | ||
| 221 | + | ||
| 222 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 223 | +;; Floating-point arithmetic. | ||
| 224 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 225 | + | ||
| 226 | +(define_insn_reservation "cortex_a5_fpalu" 4 | ||
| 227 | + (and (eq_attr "tune" "cortexa5") | ||
| 228 | + (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ | ||
| 229 | + fcmps, fcmpd")) | ||
| 230 | + "cortex_a5_ex1+cortex_a5_fpadd_pipe") | ||
| 231 | + | ||
| 232 | +;; For fconsts and fconstd, 8-bit immediate data is passed directly from | ||
| 233 | +;; f1 to f3 (which I think reduces the latency by one cycle). | ||
| 234 | + | ||
| 235 | +(define_insn_reservation "cortex_a5_fconst" 3 | ||
| 236 | + (and (eq_attr "tune" "cortexa5") | ||
| 237 | + (eq_attr "type" "fconsts,fconstd")) | ||
| 238 | + "cortex_a5_ex1+cortex_a5_fpadd_pipe") | ||
| 239 | + | ||
| 240 | +;; We should try not to attempt to issue a single-precision multiplication in | ||
| 241 | +;; the middle of a double-precision multiplication operation (the usage of | ||
| 242 | +;; cortex_a5_fpmul_pipe). | ||
| 243 | + | ||
| 244 | +(define_insn_reservation "cortex_a5_fpmuls" 4 | ||
| 245 | + (and (eq_attr "tune" "cortexa5") | ||
| 246 | + (eq_attr "type" "fmuls")) | ||
| 247 | + "cortex_a5_ex1+cortex_a5_fpmul_pipe") | ||
| 248 | + | ||
| 249 | +;; For single-precision multiply-accumulate, the add (accumulate) is issued | ||
| 250 | +;; whilst the multiply is in F4. The multiply result can then be forwarded | ||
| 251 | +;; from F5 to F1. The issue unit is only used once (when we first start | ||
| 252 | +;; processing the instruction), but the usage of the FP add pipeline could | ||
| 253 | +;; block other instructions attempting to use it simultaneously. We try to | ||
| 254 | +;; avoid that using cortex_a5_fpadd_pipe. | ||
| 255 | + | ||
| 256 | +(define_insn_reservation "cortex_a5_fpmacs" 8 | ||
| 257 | + (and (eq_attr "tune" "cortexa5") | ||
| 258 | + (eq_attr "type" "fmacs")) | ||
| 259 | + "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") | ||
| 260 | + | ||
| 261 | +;; Non-multiply instructions can issue in the middle two instructions of a | ||
| 262 | +;; double-precision multiply. Note that it isn't entirely clear when a branch | ||
| 263 | +;; can dual-issue when a multi-cycle multiplication is in progress; we ignore | ||
| 264 | +;; that for now though. | ||
| 265 | + | ||
| 266 | +(define_insn_reservation "cortex_a5_fpmuld" 7 | ||
| 267 | + (and (eq_attr "tune" "cortexa5") | ||
| 268 | + (eq_attr "type" "fmuld")) | ||
| 269 | + "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ | ||
| 270 | + cortex_a5_ex1+cortex_a5_fpmul_pipe") | ||
| 271 | + | ||
| 272 | +(define_insn_reservation "cortex_a5_fpmacd" 11 | ||
| 273 | + (and (eq_attr "tune" "cortexa5") | ||
| 274 | + (eq_attr "type" "fmacd")) | ||
| 275 | + "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ | ||
| 276 | + cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") | ||
| 277 | + | ||
| 278 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 279 | +;; Floating-point divide/square root instructions. | ||
| 280 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 281 | + | ||
| 282 | +;; ??? Not sure if the 14 cycles taken for single-precision divide to complete | ||
| 283 | +;; includes the time taken for the special instruction used to collect the | ||
| 284 | +;; result to travel down the multiply pipeline, or not. Assuming so. (If | ||
| 285 | +;; that's wrong, the latency should be increased by a few cycles.) | ||
| 286 | + | ||
| 287 | +;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the | ||
| 288 | +;; multiply pipeline to collect the divide/square-root result. | ||
| 289 | + | ||
| 290 | +(define_insn_reservation "cortex_a5_fdivs" 14 | ||
| 291 | + (and (eq_attr "tune" "cortexa5") | ||
| 292 | + (eq_attr "type" "fdivs")) | ||
| 293 | + "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13") | ||
| 294 | + | ||
| 295 | +;; ??? Similarly for fdivd. | ||
| 296 | + | ||
| 297 | +(define_insn_reservation "cortex_a5_fdivd" 29 | ||
| 298 | + (and (eq_attr "tune" "cortexa5") | ||
| 299 | + (eq_attr "type" "fdivd")) | ||
| 300 | + "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28") | ||
| 301 | + | ||
| 302 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 303 | +;; VFP to/from core transfers. | ||
| 304 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 305 | + | ||
| 306 | +;; FP loads take data from wr/rot/f3. Might need to define bypasses to model | ||
| 307 | +;; this? | ||
| 308 | + | ||
| 309 | +;; Core-to-VFP transfers use the multiply pipeline. | ||
| 310 | +;; Not sure about this at all... I think we need some bypasses too. | ||
| 311 | + | ||
| 312 | +(define_insn_reservation "cortex_a5_r2f" 4 | ||
| 313 | + (and (eq_attr "tune" "cortexa5") | ||
| 314 | + (eq_attr "type" "r_2_f")) | ||
| 315 | + "cortex_a5_ex1") | ||
| 316 | + | ||
| 317 | +;; Not sure about this either. 6.8.7 says "Additionally, the store pipe used | ||
| 318 | +;; for store and FP->core register transfers can forward into the F2 and F3 | ||
| 319 | +;; stages." | ||
| 320 | +;; This doesn't correspond to what we have though. | ||
| 321 | + | ||
| 322 | +(define_insn_reservation "cortex_a5_f2r" 2 | ||
| 323 | + (and (eq_attr "tune" "cortexa5") | ||
| 324 | + (eq_attr "type" "f_2_r")) | ||
| 325 | + "cortex_a5_ex1") | ||
| 326 | + | ||
| 327 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 328 | +;; VFP flag transfer. | ||
| 329 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 330 | + | ||
| 331 | +;; ??? The flag forwarding described in section 6.8.11 of the Cortex-A5 DPU | ||
| 332 | +;; specification (from fmstat to the ex2 stage of the second instruction) is | ||
| 333 | +;; not modeled at present. | ||
| 334 | + | ||
| 335 | +(define_insn_reservation "cortex_a5_f_flags" 4 | ||
| 336 | + (and (eq_attr "tune" "cortexa5") | ||
| 337 | + (eq_attr "type" "f_flag")) | ||
| 338 | + "cortex_a5_ex1") | ||
| 339 | + | ||
| 340 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 341 | +;; VFP load/store. | ||
| 342 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 343 | + | ||
| 344 | +(define_insn_reservation "cortex_a5_f_loads" 4 | ||
| 345 | + (and (eq_attr "tune" "cortexa5") | ||
| 346 | + (eq_attr "type" "f_loads")) | ||
| 347 | + "cortex_a5_ex1") | ||
| 348 | + | ||
| 349 | +(define_insn_reservation "cortex_a5_f_loadd" 5 | ||
| 350 | + (and (eq_attr "tune" "cortexa5") | ||
| 351 | + (eq_attr "type" "f_load,f_loadd")) | ||
| 352 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 353 | + | ||
| 354 | +(define_insn_reservation "cortex_a5_f_stores" 0 | ||
| 355 | + (and (eq_attr "tune" "cortexa5") | ||
| 356 | + (eq_attr "type" "f_stores")) | ||
| 357 | + "cortex_a5_ex1") | ||
| 358 | + | ||
| 359 | +(define_insn_reservation "cortex_a5_f_stored" 0 | ||
| 360 | + (and (eq_attr "tune" "cortexa5") | ||
| 361 | + (eq_attr "type" "f_store,f_stored")) | ||
| 362 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 363 | + | ||
| 364 | +;; Load-to-use for floating-point values has a penalty of one cycle, i.e. a | ||
| 365 | +;; latency of two (6.8.3). | ||
| 366 | + | ||
| 367 | +(define_bypass 2 "cortex_a5_f_loads" | ||
| 368 | + "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ | ||
| 369 | + cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ | ||
| 370 | + cortex_a5_f2r") | ||
| 371 | + | ||
| 372 | +(define_bypass 3 "cortex_a5_f_loadd" | ||
| 373 | + "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ | ||
| 374 | + cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ | ||
| 375 | + cortex_a5_f2r") | ||
| 376 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99357.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99357.patch deleted file mode 100644 index bbdd38b55..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99357.patch +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | 2010-06-12 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * config/arm/vfp.md (arm_movsi_vfp): Set neon_type correctly | ||
| 5 | for neon_ldr and neon_str instructions. | ||
| 6 | |||
| 7 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 8 | |||
| 9 | Merge from Sourcery G++ 4.4: | ||
| 10 | |||
| 11 | 2010-04-11 Julian Brown <julian@codesourcery.com> | ||
| 12 | |||
| 13 | Issue #7326 | ||
| 14 | |||
| 15 | === modified file 'gcc/config/arm/vfp.md' | ||
| 16 | --- old/gcc/config/arm/vfp.md 2010-08-13 11:40:17 +0000 | ||
| 17 | +++ new/gcc/config/arm/vfp.md 2010-08-13 15:28:31 +0000 | ||
| 18 | @@ -82,7 +82,7 @@ | ||
| 19 | " | ||
| 20 | [(set_attr "predicable" "yes") | ||
| 21 | (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") | ||
| 22 | - (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") | ||
| 23 | + (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,neon_ldr,neon_str") | ||
| 24 | (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*") | ||
| 25 | (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")] | ||
| 26 | ) | ||
| 27 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99358.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99358.patch deleted file mode 100644 index eedcf62d1..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99358.patch +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | 2010-06-14 Paul Brook <paul@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #8879 | ||
| 4 | gcc/ | ||
| 5 | * config/arm/arm.c (use_vfp_abi): Add sorry() for Thumb-1 | ||
| 6 | hard-float ABI. | ||
| 7 | |||
| 8 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 9 | |||
| 10 | Merge from Sourcery G++ 4.4: | ||
| 11 | |||
| 12 | 2010-06-12 Jie Zhang <jie@codesourcery.com> | ||
| 13 | |||
| 14 | |||
| 15 | === modified file 'gcc/config/arm/arm.c' | ||
| 16 | --- old/gcc/config/arm/arm.c 2010-08-13 15:15:12 +0000 | ||
| 17 | +++ new/gcc/config/arm/arm.c 2010-08-13 15:37:39 +0000 | ||
| 18 | @@ -3969,7 +3969,18 @@ | ||
| 19 | use_vfp_abi (enum arm_pcs pcs_variant, bool is_double) | ||
| 20 | { | ||
| 21 | if (pcs_variant == ARM_PCS_AAPCS_VFP) | ||
| 22 | - return true; | ||
| 23 | + { | ||
| 24 | + static bool seen_thumb1_vfp = false; | ||
| 25 | + | ||
| 26 | + if (TARGET_THUMB1 && !seen_thumb1_vfp) | ||
| 27 | + { | ||
| 28 | + sorry ("Thumb-1 hard-float VFP ABI"); | ||
| 29 | + /* sorry() is not immediately fatal, so only display this once. */ | ||
| 30 | + seen_thumb1_vfp = true; | ||
| 31 | + } | ||
| 32 | + | ||
| 33 | + return true; | ||
| 34 | + } | ||
| 35 | |||
| 36 | if (pcs_variant != ARM_PCS_AAPCS_LOCAL) | ||
| 37 | return false; | ||
| 38 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99359.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99359.patch deleted file mode 100644 index 92dfe0038..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99359.patch +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | 2010-07-28 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from FSF mainline: | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * config/arm/thumb2.md (*thumb2_movdf_soft_insn): Fix alternatives | ||
| 7 | for pool ranges. | ||
| 8 | |||
| 9 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 10 | |||
| 11 | Merge from Sourcery G++ 4.4: | ||
| 12 | |||
| 13 | === modified file 'gcc/config/arm/thumb2.md' | ||
| 14 | --- old/gcc/config/arm/thumb2.md 2010-08-13 10:30:35 +0000 | ||
| 15 | +++ new/gcc/config/arm/thumb2.md 2010-08-13 16:00:58 +0000 | ||
| 16 | @@ -319,8 +319,8 @@ | ||
| 17 | " | ||
| 18 | [(set_attr "length" "8,12,16,8,8") | ||
| 19 | (set_attr "type" "*,*,*,load2,store2") | ||
| 20 | - (set_attr "pool_range" "1020") | ||
| 21 | - (set_attr "neg_pool_range" "0")] | ||
| 22 | + (set_attr "pool_range" "*,*,*,1020,*") | ||
| 23 | + (set_attr "neg_pool_range" "*,*,*,0,*")] | ||
| 24 | ) | ||
| 25 | |||
| 26 | (define_insn "*thumb2_cmpsi_shiftsi" | ||
| 27 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99360.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99360.patch deleted file mode 100644 index a58dd2441..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99360.patch +++ /dev/null | |||
| @@ -1,1759 +0,0 @@ | |||
| 1 | 2010-07-28 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 2 | |||
| 3 | Backport code hoisting improvements from mainline: | ||
| 4 | |||
| 5 | 2010-07-28 Jakub Jelinek <jakub@redhat.com> | ||
| 6 | PR debug/45105 | ||
| 7 | * gcc.dg/pr45105.c: New test. | ||
| 8 | |||
| 9 | 2010-07-28 Jakub Jelinek <jakub@redhat.com> | ||
| 10 | PR debug/45105 | ||
| 11 | * gcse.c (hoist_code): Use FOR_BB_INSNS macro. | ||
| 12 | |||
| 13 | 2010-07-28 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 14 | PR rtl-optimization/45107 | ||
| 15 | * gcc.dg/pr45107.c: New test. | ||
| 16 | |||
| 17 | 2010-07-28 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 18 | PR rtl-optimization/45107 | ||
| 19 | * gcse.c (hash_scan_set): Use max_distance for gcse-las. | ||
| 20 | |||
| 21 | 2010-07-28 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 22 | PR rtl-optimization/45101 | ||
| 23 | * gcc.dg/pr45101.c: New test. | ||
| 24 | |||
| 25 | 2010-07-28 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 26 | PR rtl-optimization/45101 | ||
| 27 | * gcse.c (hash_scan_set): Fix argument ordering of insert_expr_in_table | ||
| 28 | for gcse-las. | ||
| 29 | |||
| 30 | 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 31 | PR rtl-optimization/40956 | ||
| 32 | PR target/42495 | ||
| 33 | PR middle-end/42574 | ||
| 34 | * gcc.target/arm/pr40956.c, gcc.target/arm/pr42495.c, | ||
| 35 | * gcc.target/arm/pr42574.c: Add tests. | ||
| 36 | |||
| 37 | 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 38 | * config/arm/arm.c (params.h): Include. | ||
| 39 | (arm_override_options): Tune gcse-unrestricted-cost. | ||
| 40 | * config/arm/t-arm (arm.o): Define dependencies. | ||
| 41 | |||
| 42 | 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 43 | PR target/42495 | ||
| 44 | PR middle-end/42574 | ||
| 45 | * basic-block.h (get_dominated_to_depth): Declare. | ||
| 46 | * dominance.c (get_dominated_to_depth): New function, use | ||
| 47 | get_all_dominated_blocks as a base. | ||
| 48 | (get_all_dominated_blocks): Use get_dominated_to_depth. | ||
| 49 | * gcse.c (occr_t, VEC (occr_t, heap)): Define. | ||
| 50 | (hoist_exprs): Remove. | ||
| 51 | (alloc_code_hoist_mem, free_code_hoist_mem): Update. | ||
| 52 | (compute_code_hoist_vbeinout): Add debug print outs. | ||
| 53 | (hoist_code): Partially rewrite, simplify. Use get_dominated_to_depth. | ||
| 54 | * params.def (PARAM_MAX_HOIST_DEPTH): New parameter to avoid | ||
| 55 | quadratic behavior. | ||
| 56 | * params.h (MAX_HOIST_DEPTH): New macro. | ||
| 57 | * doc/invoke.texi (max-hoist-depth): Document. | ||
| 58 | |||
| 59 | 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 60 | PR rtl-optimization/40956 | ||
| 61 | * config/arm/arm.c (thumb1_size_rtx_costs): Fix cost of simple | ||
| 62 | constants. | ||
| 63 | |||
| 64 | 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 65 | PR target/42495 | ||
| 66 | PR middle-end/42574 | ||
| 67 | * config/arm/arm.c (legitimize_pic_address): Use | ||
| 68 | gen_calculate_pic_address pattern to emit calculation of PIC address. | ||
| 69 | (will_be_in_index_register): New function. | ||
| 70 | (arm_legitimate_address_outer_p, thumb2_legitimate_address_p,) | ||
| 71 | (thumb1_legitimate_address_p): Use it provided !strict_p. | ||
| 72 | * config/arm/arm.md (calculate_pic_address): New expand and split. | ||
| 73 | |||
| 74 | 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 75 | PR target/42495 | ||
| 76 | PR middle-end/42574 | ||
| 77 | * config/arm/arm.c (thumb1_size_rtx_costs): Add cost for "J" constants. | ||
| 78 | * config/arm/arm.md (define_split "J", define_split "K"): Make | ||
| 79 | IRA/reload friendly. | ||
| 80 | |||
| 81 | 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 82 | * gcse.c (insert_insn_end_basic_block): Update signature, remove | ||
| 83 | unused checks. | ||
| 84 | (pre_edge_insert, hoist_code): Update. | ||
| 85 | |||
| 86 | 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 87 | PR target/42495 | ||
| 88 | PR middle-end/42574 | ||
| 89 | * gcse.c (hoist_expr_reaches_here_p): Remove excessive check. | ||
| 90 | |||
| 91 | 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 92 | * gcse.c (hoist_code): Generate new pseudo for every new set insn. | ||
| 93 | |||
| 94 | 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 95 | PR rtl-optimization/40956 | ||
| 96 | PR target/42495 | ||
| 97 | PR middle-end/42574 | ||
| 98 | * gcse.c (compute_code_hoist_vbeinout): Consider more expressions | ||
| 99 | for hoisting. | ||
| 100 | (hoist_code): Count occurences in current block too. | ||
| 101 | |||
| 102 | 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 103 | * gcse.c (struct expr:max_distance): New field. | ||
| 104 | (doing_code_hoisting_p): New static variable. | ||
| 105 | (want_to_gcse_p): Change signature. Allow constrained hoisting of | ||
| 106 | simple expressions, don't change behavior for PRE. Set max_distance. | ||
| 107 | (insert_expr_in_table): Set new max_distance field. | ||
| 108 | (hash_scan_set): Update. | ||
| 109 | (hoist_expr_reaches_here_p): Stop search after max_distance | ||
| 110 | instructions. | ||
| 111 | (find_occr_in_bb): New static function. Use it in ... | ||
| 112 | (hoist_code): Calculate sizes of basic block before any changes are | ||
| 113 | done. Pass max_distance to hoist_expr_reaches_here_p. | ||
| 114 | (one_code_hoisting_pass): Set doing_code_hoisting_p. | ||
| 115 | * params.def (PARAM_GCSE_COST_DISTANCE_RATIO,) | ||
| 116 | (PARAM_GCSE_UNRESTRICTED_COST): New parameters. | ||
| 117 | * params.h (GCSE_COST_DISTANCE_RATIO, GCSE_UNRESTRICTED_COST): New | ||
| 118 | macros. | ||
| 119 | * doc/invoke.texi (gcse-cost-distance-ratio, gcse-unrestricted-cost): | ||
| 120 | Document. | ||
| 121 | |||
| 122 | 2010-07-27 Jeff Law <law@redhat.com> | ||
| 123 | Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 124 | * gcse.c (compute_transpout, transpout): Remove, move logic | ||
| 125 | to prune_expressions. | ||
| 126 | (compute_pre_data): Move pruning of trapping expressions ... | ||
| 127 | (prune_expressions): ... here. New static function. | ||
| 128 | (compute_code_hoist_data): Use it. | ||
| 129 | (alloc_code_hoist_mem, free_code_hoist_mem, hoist_code): Update. | ||
| 130 | |||
| 131 | 2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 132 | * dbgcnt.def (hoist_insn): New debug counter. | ||
| 133 | * gcse.c (hoist_code): Use it. | ||
| 134 | |||
| 135 | 2010-07-28 Julian Brown <julian@codesourcery.com> | ||
| 136 | |||
| 137 | Backport from FSF mainline: | ||
| 138 | |||
| 139 | === modified file 'gcc/basic-block.h' | ||
| 140 | --- old/gcc/basic-block.h 2010-04-02 18:54:46 +0000 | ||
| 141 | +++ new/gcc/basic-block.h 2010-08-16 09:41:58 +0000 | ||
| 142 | @@ -932,6 +932,8 @@ | ||
| 143 | extern VEC (basic_block, heap) *get_dominated_by_region (enum cdi_direction, | ||
| 144 | basic_block *, | ||
| 145 | unsigned); | ||
| 146 | +extern VEC (basic_block, heap) *get_dominated_to_depth (enum cdi_direction, | ||
| 147 | + basic_block, int); | ||
| 148 | extern VEC (basic_block, heap) *get_all_dominated_blocks (enum cdi_direction, | ||
| 149 | basic_block); | ||
| 150 | extern void add_to_dominance_info (enum cdi_direction, basic_block); | ||
| 151 | |||
| 152 | === modified file 'gcc/config/arm/arm.c' | ||
| 153 | --- old/gcc/config/arm/arm.c 2010-08-13 15:37:39 +0000 | ||
| 154 | +++ new/gcc/config/arm/arm.c 2010-08-16 09:41:58 +0000 | ||
| 155 | @@ -56,6 +56,7 @@ | ||
| 156 | #include "df.h" | ||
| 157 | #include "intl.h" | ||
| 158 | #include "libfuncs.h" | ||
| 159 | +#include "params.h" | ||
| 160 | |||
| 161 | /* Forward definitions of types. */ | ||
| 162 | typedef struct minipool_node Mnode; | ||
| 163 | @@ -1902,6 +1903,14 @@ | ||
| 164 | flag_reorder_blocks = 1; | ||
| 165 | } | ||
| 166 | |||
| 167 | + if (!PARAM_SET_P (PARAM_GCSE_UNRESTRICTED_COST) | ||
| 168 | + && flag_pic) | ||
| 169 | + /* Hoisting PIC address calculations more aggressively provides a small, | ||
| 170 | + but measurable, size reduction for PIC code. Therefore, we decrease | ||
| 171 | + the bar for unrestricted expression hoisting to the cost of PIC address | ||
| 172 | + calculation, which is 2 instructions. */ | ||
| 173 | + set_param_value ("gcse-unrestricted-cost", 2); | ||
| 174 | + | ||
| 175 | /* Register global variables with the garbage collector. */ | ||
| 176 | arm_add_gc_roots (); | ||
| 177 | |||
| 178 | @@ -5070,17 +5079,13 @@ | ||
| 179 | if (GET_CODE (orig) == SYMBOL_REF | ||
| 180 | || GET_CODE (orig) == LABEL_REF) | ||
| 181 | { | ||
| 182 | - rtx pic_ref, address; | ||
| 183 | rtx insn; | ||
| 184 | |||
| 185 | if (reg == 0) | ||
| 186 | { | ||
| 187 | gcc_assert (can_create_pseudo_p ()); | ||
| 188 | reg = gen_reg_rtx (Pmode); | ||
| 189 | - address = gen_reg_rtx (Pmode); | ||
| 190 | } | ||
| 191 | - else | ||
| 192 | - address = reg; | ||
| 193 | |||
| 194 | /* VxWorks does not impose a fixed gap between segments; the run-time | ||
| 195 | gap can be different from the object-file gap. We therefore can't | ||
| 196 | @@ -5096,18 +5101,21 @@ | ||
| 197 | insn = arm_pic_static_addr (orig, reg); | ||
| 198 | else | ||
| 199 | { | ||
| 200 | + rtx pat; | ||
| 201 | + rtx mem; | ||
| 202 | + | ||
| 203 | /* If this function doesn't have a pic register, create one now. */ | ||
| 204 | require_pic_register (); | ||
| 205 | |||
| 206 | - if (TARGET_32BIT) | ||
| 207 | - emit_insn (gen_pic_load_addr_32bit (address, orig)); | ||
| 208 | - else /* TARGET_THUMB1 */ | ||
| 209 | - emit_insn (gen_pic_load_addr_thumb1 (address, orig)); | ||
| 210 | - | ||
| 211 | - pic_ref = gen_const_mem (Pmode, | ||
| 212 | - gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, | ||
| 213 | - address)); | ||
| 214 | - insn = emit_move_insn (reg, pic_ref); | ||
| 215 | + pat = gen_calculate_pic_address (reg, cfun->machine->pic_reg, orig); | ||
| 216 | + | ||
| 217 | + /* Make the MEM as close to a constant as possible. */ | ||
| 218 | + mem = SET_SRC (pat); | ||
| 219 | + gcc_assert (MEM_P (mem) && !MEM_VOLATILE_P (mem)); | ||
| 220 | + MEM_READONLY_P (mem) = 1; | ||
| 221 | + MEM_NOTRAP_P (mem) = 1; | ||
| 222 | + | ||
| 223 | + insn = emit_insn (pat); | ||
| 224 | } | ||
| 225 | |||
| 226 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | ||
| 227 | @@ -5387,6 +5395,15 @@ | ||
| 228 | return FALSE; | ||
| 229 | } | ||
| 230 | |||
| 231 | +/* Return true if X will surely end up in an index register after next | ||
| 232 | + splitting pass. */ | ||
| 233 | +static bool | ||
| 234 | +will_be_in_index_register (const_rtx x) | ||
| 235 | +{ | ||
| 236 | + /* arm.md: calculate_pic_address will split this into a register. */ | ||
| 237 | + return GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_SYM; | ||
| 238 | +} | ||
| 239 | + | ||
| 240 | /* Return nonzero if X is a valid ARM state address operand. */ | ||
| 241 | int | ||
| 242 | arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer, | ||
| 243 | @@ -5444,8 +5461,9 @@ | ||
| 244 | rtx xop1 = XEXP (x, 1); | ||
| 245 | |||
| 246 | return ((arm_address_register_rtx_p (xop0, strict_p) | ||
| 247 | - && GET_CODE(xop1) == CONST_INT | ||
| 248 | - && arm_legitimate_index_p (mode, xop1, outer, strict_p)) | ||
| 249 | + && ((GET_CODE(xop1) == CONST_INT | ||
| 250 | + && arm_legitimate_index_p (mode, xop1, outer, strict_p)) | ||
| 251 | + || (!strict_p && will_be_in_index_register (xop1)))) | ||
| 252 | || (arm_address_register_rtx_p (xop1, strict_p) | ||
| 253 | && arm_legitimate_index_p (mode, xop0, outer, strict_p))); | ||
| 254 | } | ||
| 255 | @@ -5531,7 +5549,8 @@ | ||
| 256 | rtx xop1 = XEXP (x, 1); | ||
| 257 | |||
| 258 | return ((arm_address_register_rtx_p (xop0, strict_p) | ||
| 259 | - && thumb2_legitimate_index_p (mode, xop1, strict_p)) | ||
| 260 | + && (thumb2_legitimate_index_p (mode, xop1, strict_p) | ||
| 261 | + || (!strict_p && will_be_in_index_register (xop1)))) | ||
| 262 | || (arm_address_register_rtx_p (xop1, strict_p) | ||
| 263 | && thumb2_legitimate_index_p (mode, xop0, strict_p))); | ||
| 264 | } | ||
| 265 | @@ -5834,7 +5853,8 @@ | ||
| 266 | && XEXP (x, 0) != frame_pointer_rtx | ||
| 267 | && XEXP (x, 1) != frame_pointer_rtx | ||
| 268 | && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) | ||
| 269 | - && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p)) | ||
| 270 | + && (thumb1_index_register_rtx_p (XEXP (x, 1), strict_p) | ||
| 271 | + || (!strict_p && will_be_in_index_register (XEXP (x, 1))))) | ||
| 272 | return 1; | ||
| 273 | |||
| 274 | /* REG+const has 5-7 bit offset for non-SP registers. */ | ||
| 275 | @@ -6413,12 +6433,16 @@ | ||
| 276 | |||
| 277 | case CONST_INT: | ||
| 278 | if (outer == SET) | ||
| 279 | - { | ||
| 280 | - if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | ||
| 281 | - return 0; | ||
| 282 | - if (thumb_shiftable_const (INTVAL (x))) | ||
| 283 | - return COSTS_N_INSNS (2); | ||
| 284 | - return COSTS_N_INSNS (3); | ||
| 285 | + { | ||
| 286 | + if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | ||
| 287 | + return COSTS_N_INSNS (1); | ||
| 288 | + /* See split "TARGET_THUMB1 && satisfies_constraint_J". */ | ||
| 289 | + if (INTVAL (x) >= -255 && INTVAL (x) <= -1) | ||
| 290 | + return COSTS_N_INSNS (2); | ||
| 291 | + /* See split "TARGET_THUMB1 && satisfies_constraint_K". */ | ||
| 292 | + if (thumb_shiftable_const (INTVAL (x))) | ||
| 293 | + return COSTS_N_INSNS (2); | ||
| 294 | + return COSTS_N_INSNS (3); | ||
| 295 | } | ||
| 296 | else if ((outer == PLUS || outer == COMPARE) | ||
| 297 | && INTVAL (x) < 256 && INTVAL (x) > -256) | ||
| 298 | @@ -7110,6 +7134,12 @@ | ||
| 299 | a single register, otherwise it costs one insn per word. */ | ||
| 300 | if (REG_P (XEXP (x, 0))) | ||
| 301 | *total = COSTS_N_INSNS (1); | ||
| 302 | + else if (flag_pic | ||
| 303 | + && GET_CODE (XEXP (x, 0)) == PLUS | ||
| 304 | + && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) | ||
| 305 | + /* This will be split into two instructions. | ||
| 306 | + See arm.md:calculate_pic_address. */ | ||
| 307 | + *total = COSTS_N_INSNS (2); | ||
| 308 | else | ||
| 309 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | ||
| 310 | return true; | ||
| 311 | |||
| 312 | === modified file 'gcc/config/arm/arm.md' | ||
| 313 | --- old/gcc/config/arm/arm.md 2010-08-13 15:15:12 +0000 | ||
| 314 | +++ new/gcc/config/arm/arm.md 2010-08-16 09:41:58 +0000 | ||
| 315 | @@ -5290,17 +5290,21 @@ | ||
| 316 | [(set (match_operand:SI 0 "register_operand" "") | ||
| 317 | (match_operand:SI 1 "const_int_operand" ""))] | ||
| 318 | "TARGET_THUMB1 && satisfies_constraint_J (operands[1])" | ||
| 319 | - [(set (match_dup 0) (match_dup 1)) | ||
| 320 | - (set (match_dup 0) (neg:SI (match_dup 0)))] | ||
| 321 | - "operands[1] = GEN_INT (- INTVAL (operands[1]));" | ||
| 322 | + [(set (match_dup 2) (match_dup 1)) | ||
| 323 | + (set (match_dup 0) (neg:SI (match_dup 2)))] | ||
| 324 | + " | ||
| 325 | + { | ||
| 326 | + operands[1] = GEN_INT (- INTVAL (operands[1])); | ||
| 327 | + operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0]; | ||
| 328 | + }" | ||
| 329 | ) | ||
| 330 | |||
| 331 | (define_split | ||
| 332 | [(set (match_operand:SI 0 "register_operand" "") | ||
| 333 | (match_operand:SI 1 "const_int_operand" ""))] | ||
| 334 | "TARGET_THUMB1 && satisfies_constraint_K (operands[1])" | ||
| 335 | - [(set (match_dup 0) (match_dup 1)) | ||
| 336 | - (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))] | ||
| 337 | + [(set (match_dup 2) (match_dup 1)) | ||
| 338 | + (set (match_dup 0) (ashift:SI (match_dup 2) (match_dup 3)))] | ||
| 339 | " | ||
| 340 | { | ||
| 341 | unsigned HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffffffffu; | ||
| 342 | @@ -5311,12 +5315,13 @@ | ||
| 343 | if ((val & (mask << i)) == val) | ||
| 344 | break; | ||
| 345 | |||
| 346 | - /* Shouldn't happen, but we don't want to split if the shift is zero. */ | ||
| 347 | + /* Don't split if the shift is zero. */ | ||
| 348 | if (i == 0) | ||
| 349 | FAIL; | ||
| 350 | |||
| 351 | operands[1] = GEN_INT (val >> i); | ||
| 352 | - operands[2] = GEN_INT (i); | ||
| 353 | + operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0]; | ||
| 354 | + operands[3] = GEN_INT (i); | ||
| 355 | }" | ||
| 356 | ) | ||
| 357 | |||
| 358 | @@ -5325,6 +5330,34 @@ | ||
| 359 | ;; we use an unspec. The offset will be loaded from a constant pool entry, | ||
| 360 | ;; since that is the only type of relocation we can use. | ||
| 361 | |||
| 362 | +;; Wrap calculation of the whole PIC address in a single pattern for the | ||
| 363 | +;; benefit of optimizers, particularly, PRE and HOIST. Calculation of | ||
| 364 | +;; a PIC address involves two loads from memory, so we want to CSE it | ||
| 365 | +;; as often as possible. | ||
| 366 | +;; This pattern will be split into one of the pic_load_addr_* patterns | ||
| 367 | +;; and a move after GCSE optimizations. | ||
| 368 | +;; | ||
| 369 | +;; Note: Update arm.c: legitimize_pic_address() when changing this pattern. | ||
| 370 | +(define_expand "calculate_pic_address" | ||
| 371 | + [(set (match_operand:SI 0 "register_operand" "") | ||
| 372 | + (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "") | ||
| 373 | + (unspec:SI [(match_operand:SI 2 "" "")] | ||
| 374 | + UNSPEC_PIC_SYM))))] | ||
| 375 | + "flag_pic" | ||
| 376 | +) | ||
| 377 | + | ||
| 378 | +;; Split calculate_pic_address into pic_load_addr_* and a move. | ||
| 379 | +(define_split | ||
| 380 | + [(set (match_operand:SI 0 "register_operand" "") | ||
| 381 | + (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "") | ||
| 382 | + (unspec:SI [(match_operand:SI 2 "" "")] | ||
| 383 | + UNSPEC_PIC_SYM))))] | ||
| 384 | + "flag_pic" | ||
| 385 | + [(set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_PIC_SYM)) | ||
| 386 | + (set (match_dup 0) (mem:SI (plus:SI (match_dup 1) (match_dup 3))))] | ||
| 387 | + "operands[3] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];" | ||
| 388 | +) | ||
| 389 | + | ||
| 390 | ;; The rather odd constraints on the following are to force reload to leave | ||
| 391 | ;; the insn alone, and to force the minipool generation pass to then move | ||
| 392 | ;; the GOT symbol to memory. | ||
| 393 | |||
| 394 | === modified file 'gcc/config/arm/t-arm' | ||
| 395 | --- old/gcc/config/arm/t-arm 2009-06-21 19:48:15 +0000 | ||
| 396 | +++ new/gcc/config/arm/t-arm 2010-08-16 09:41:58 +0000 | ||
| 397 | @@ -45,6 +45,15 @@ | ||
| 398 | $(srcdir)/config/arm/arm-cores.def > \ | ||
| 399 | $(srcdir)/config/arm/arm-tune.md | ||
| 400 | |||
| 401 | +arm.o: $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ | ||
| 402 | + $(RTL_H) $(TREE_H) $(OBSTACK_H) $(REGS_H) hard-reg-set.h \ | ||
| 403 | + insn-config.h conditions.h output.h \ | ||
| 404 | + $(INSN_ATTR_H) $(FLAGS_H) reload.h $(FUNCTION_H) \ | ||
| 405 | + $(EXPR_H) $(OPTABS_H) toplev.h $(RECOG_H) $(CGRAPH_H) \ | ||
| 406 | + $(GGC_H) except.h $(C_PRAGMA_H) $(INTEGRATE_H) $(TM_P_H) \ | ||
| 407 | + $(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \ | ||
| 408 | + intl.h libfuncs.h $(PARAMS_H) | ||
| 409 | + | ||
| 410 | arm-c.o: $(srcdir)/config/arm/arm-c.c $(CONFIG_H) $(SYSTEM_H) \ | ||
| 411 | coretypes.h $(TM_H) $(TREE_H) output.h $(C_COMMON_H) | ||
| 412 | $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ | ||
| 413 | |||
| 414 | === modified file 'gcc/dbgcnt.def' | ||
| 415 | --- old/gcc/dbgcnt.def 2009-11-25 10:55:54 +0000 | ||
| 416 | +++ new/gcc/dbgcnt.def 2010-08-16 09:41:58 +0000 | ||
| 417 | @@ -158,6 +158,7 @@ | ||
| 418 | DEBUG_COUNTER (global_alloc_at_func) | ||
| 419 | DEBUG_COUNTER (global_alloc_at_reg) | ||
| 420 | DEBUG_COUNTER (hoist) | ||
| 421 | +DEBUG_COUNTER (hoist_insn) | ||
| 422 | DEBUG_COUNTER (ia64_sched2) | ||
| 423 | DEBUG_COUNTER (if_conversion) | ||
| 424 | DEBUG_COUNTER (if_after_combine) | ||
| 425 | |||
| 426 | === modified file 'gcc/doc/invoke.texi' | ||
| 427 | --- old/gcc/doc/invoke.texi 2010-08-05 15:20:54 +0000 | ||
| 428 | +++ new/gcc/doc/invoke.texi 2010-08-16 09:41:58 +0000 | ||
| 429 | @@ -8086,6 +8086,29 @@ | ||
| 430 | vectorization needs to be greater than the value specified by this option | ||
| 431 | to allow vectorization. The default value is 0. | ||
| 432 | |||
| 433 | +@item gcse-cost-distance-ratio | ||
| 434 | +Scaling factor in calculation of maximum distance an expression | ||
| 435 | +can be moved by GCSE optimizations. This is currently supported only in | ||
| 436 | +code hoisting pass. The bigger the ratio, the more agressive code hoisting | ||
| 437 | +will be with simple expressions, i.e., the expressions which have cost | ||
| 438 | +less than @option{gcse-unrestricted-cost}. Specifying 0 will disable | ||
| 439 | +hoisting of simple expressions. The default value is 10. | ||
| 440 | + | ||
| 441 | +@item gcse-unrestricted-cost | ||
| 442 | +Cost, roughly measured as the cost of a single typical machine | ||
| 443 | +instruction, at which GCSE optimizations will not constrain | ||
| 444 | +the distance an expression can travel. This is currently | ||
| 445 | +supported only in code hoisting pass. The lesser the cost, | ||
| 446 | +the more aggressive code hoisting will be. Specifying 0 will | ||
| 447 | +allow all expressions to travel unrestricted distances. | ||
| 448 | +The default value is 3. | ||
| 449 | + | ||
| 450 | +@item max-hoist-depth | ||
| 451 | +The depth of search in the dominator tree for expressions to hoist. | ||
| 452 | +This is used to avoid quadratic behavior in hoisting algorithm. | ||
| 453 | +The value of 0 will avoid limiting the search, but may slow down compilation | ||
| 454 | +of huge functions. The default value is 30. | ||
| 455 | + | ||
| 456 | @item max-unrolled-insns | ||
| 457 | The maximum number of instructions that a loop should have if that loop | ||
| 458 | is unrolled, and if the loop is unrolled, it determines how many times | ||
| 459 | |||
| 460 | === modified file 'gcc/dominance.c' | ||
| 461 | --- old/gcc/dominance.c 2010-04-02 18:54:46 +0000 | ||
| 462 | +++ new/gcc/dominance.c 2010-08-16 09:41:58 +0000 | ||
| 463 | @@ -782,16 +782,20 @@ | ||
| 464 | } | ||
| 465 | |||
| 466 | /* Returns the list of basic blocks including BB dominated by BB, in the | ||
| 467 | - direction DIR. The vector will be sorted in preorder. */ | ||
| 468 | + direction DIR up to DEPTH in the dominator tree. The DEPTH of zero will | ||
| 469 | + produce a vector containing all dominated blocks. The vector will be sorted | ||
| 470 | + in preorder. */ | ||
| 471 | |||
| 472 | VEC (basic_block, heap) * | ||
| 473 | -get_all_dominated_blocks (enum cdi_direction dir, basic_block bb) | ||
| 474 | +get_dominated_to_depth (enum cdi_direction dir, basic_block bb, int depth) | ||
| 475 | { | ||
| 476 | VEC(basic_block, heap) *bbs = NULL; | ||
| 477 | unsigned i; | ||
| 478 | + unsigned next_level_start; | ||
| 479 | |||
| 480 | i = 0; | ||
| 481 | VEC_safe_push (basic_block, heap, bbs, bb); | ||
| 482 | + next_level_start = 1; /* = VEC_length (basic_block, bbs); */ | ||
| 483 | |||
| 484 | do | ||
| 485 | { | ||
| 486 | @@ -802,12 +806,24 @@ | ||
| 487 | son; | ||
| 488 | son = next_dom_son (dir, son)) | ||
| 489 | VEC_safe_push (basic_block, heap, bbs, son); | ||
| 490 | + | ||
| 491 | + if (i == next_level_start && --depth) | ||
| 492 | + next_level_start = VEC_length (basic_block, bbs); | ||
| 493 | } | ||
| 494 | - while (i < VEC_length (basic_block, bbs)); | ||
| 495 | + while (i < next_level_start); | ||
| 496 | |||
| 497 | return bbs; | ||
| 498 | } | ||
| 499 | |||
| 500 | +/* Returns the list of basic blocks including BB dominated by BB, in the | ||
| 501 | + direction DIR. The vector will be sorted in preorder. */ | ||
| 502 | + | ||
| 503 | +VEC (basic_block, heap) * | ||
| 504 | +get_all_dominated_blocks (enum cdi_direction dir, basic_block bb) | ||
| 505 | +{ | ||
| 506 | + return get_dominated_to_depth (dir, bb, 0); | ||
| 507 | +} | ||
| 508 | + | ||
| 509 | /* Redirect all edges pointing to BB to TO. */ | ||
| 510 | void | ||
| 511 | redirect_immediate_dominators (enum cdi_direction dir, basic_block bb, | ||
| 512 | |||
| 513 | === modified file 'gcc/gcse.c' | ||
| 514 | --- old/gcc/gcse.c 2010-03-16 10:50:42 +0000 | ||
| 515 | +++ new/gcc/gcse.c 2010-08-16 09:41:58 +0000 | ||
| 516 | @@ -296,6 +296,12 @@ | ||
| 517 | The value is the newly created pseudo-reg to record a copy of the | ||
| 518 | expression in all the places that reach the redundant copy. */ | ||
| 519 | rtx reaching_reg; | ||
| 520 | + /* Maximum distance in instructions this expression can travel. | ||
| 521 | + We avoid moving simple expressions for more than a few instructions | ||
| 522 | + to keep register pressure under control. | ||
| 523 | + A value of "0" removes restrictions on how far the expression can | ||
| 524 | + travel. */ | ||
| 525 | + int max_distance; | ||
| 526 | }; | ||
| 527 | |||
| 528 | /* Occurrence of an expression. | ||
| 529 | @@ -317,6 +323,10 @@ | ||
| 530 | char copied_p; | ||
| 531 | }; | ||
| 532 | |||
| 533 | +typedef struct occr *occr_t; | ||
| 534 | +DEF_VEC_P (occr_t); | ||
| 535 | +DEF_VEC_ALLOC_P (occr_t, heap); | ||
| 536 | + | ||
| 537 | /* Expression and copy propagation hash tables. | ||
| 538 | Each hash table is an array of buckets. | ||
| 539 | ??? It is known that if it were an array of entries, structure elements | ||
| 540 | @@ -419,6 +429,9 @@ | ||
| 541 | /* Number of global copies propagated. */ | ||
| 542 | static int global_copy_prop_count; | ||
| 543 | |||
| 544 | +/* Doing code hoisting. */ | ||
| 545 | +static bool doing_code_hoisting_p = false; | ||
| 546 | + | ||
| 547 | /* For available exprs */ | ||
| 548 | static sbitmap *ae_kill; | ||
| 549 | |||
| 550 | @@ -432,12 +445,12 @@ | ||
| 551 | static void hash_scan_set (rtx, rtx, struct hash_table_d *); | ||
| 552 | static void hash_scan_clobber (rtx, rtx, struct hash_table_d *); | ||
| 553 | static void hash_scan_call (rtx, rtx, struct hash_table_d *); | ||
| 554 | -static int want_to_gcse_p (rtx); | ||
| 555 | +static int want_to_gcse_p (rtx, int *); | ||
| 556 | static bool gcse_constant_p (const_rtx); | ||
| 557 | static int oprs_unchanged_p (const_rtx, const_rtx, int); | ||
| 558 | static int oprs_anticipatable_p (const_rtx, const_rtx); | ||
| 559 | static int oprs_available_p (const_rtx, const_rtx); | ||
| 560 | -static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int, | ||
| 561 | +static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int, int, | ||
| 562 | struct hash_table_d *); | ||
| 563 | static void insert_set_in_table (rtx, rtx, struct hash_table_d *); | ||
| 564 | static unsigned int hash_expr (const_rtx, enum machine_mode, int *, int); | ||
| 565 | @@ -462,7 +475,6 @@ | ||
| 566 | static void alloc_cprop_mem (int, int); | ||
| 567 | static void free_cprop_mem (void); | ||
| 568 | static void compute_transp (const_rtx, int, sbitmap *, int); | ||
| 569 | -static void compute_transpout (void); | ||
| 570 | static void compute_local_properties (sbitmap *, sbitmap *, sbitmap *, | ||
| 571 | struct hash_table_d *); | ||
| 572 | static void compute_cprop_data (void); | ||
| 573 | @@ -486,7 +498,7 @@ | ||
| 574 | static void compute_pre_data (void); | ||
| 575 | static int pre_expr_reaches_here_p (basic_block, struct expr *, | ||
| 576 | basic_block); | ||
| 577 | -static void insert_insn_end_basic_block (struct expr *, basic_block, int); | ||
| 578 | +static void insert_insn_end_basic_block (struct expr *, basic_block); | ||
| 579 | static void pre_insert_copy_insn (struct expr *, rtx); | ||
| 580 | static void pre_insert_copies (void); | ||
| 581 | static int pre_delete (void); | ||
| 582 | @@ -497,7 +509,8 @@ | ||
| 583 | static void free_code_hoist_mem (void); | ||
| 584 | static void compute_code_hoist_vbeinout (void); | ||
| 585 | static void compute_code_hoist_data (void); | ||
| 586 | -static int hoist_expr_reaches_here_p (basic_block, int, basic_block, char *); | ||
| 587 | +static int hoist_expr_reaches_here_p (basic_block, int, basic_block, char *, | ||
| 588 | + int, int *); | ||
| 589 | static int hoist_code (void); | ||
| 590 | static int one_code_hoisting_pass (void); | ||
| 591 | static rtx process_insert_insn (struct expr *); | ||
| 592 | @@ -755,7 +768,7 @@ | ||
| 593 | GCSE. */ | ||
| 594 | |||
| 595 | static int | ||
| 596 | -want_to_gcse_p (rtx x) | ||
| 597 | +want_to_gcse_p (rtx x, int *max_distance_ptr) | ||
| 598 | { | ||
| 599 | #ifdef STACK_REGS | ||
| 600 | /* On register stack architectures, don't GCSE constants from the | ||
| 601 | @@ -765,18 +778,67 @@ | ||
| 602 | x = avoid_constant_pool_reference (x); | ||
| 603 | #endif | ||
| 604 | |||
| 605 | + /* GCSE'ing constants: | ||
| 606 | + | ||
| 607 | + We do not specifically distinguish between constant and non-constant | ||
| 608 | + expressions in PRE and Hoist. We use rtx_cost below to limit | ||
| 609 | + the maximum distance simple expressions can travel. | ||
| 610 | + | ||
| 611 | + Nevertheless, constants are much easier to GCSE, and, hence, | ||
| 612 | + it is easy to overdo the optimizations. Usually, excessive PRE and | ||
| 613 | + Hoisting of constant leads to increased register pressure. | ||
| 614 | + | ||
| 615 | + RA can deal with this by rematerialing some of the constants. | ||
| 616 | + Therefore, it is important that the back-end generates sets of constants | ||
| 617 | + in a way that allows reload rematerialize them under high register | ||
| 618 | + pressure, i.e., a pseudo register with REG_EQUAL to constant | ||
| 619 | + is set only once. Failing to do so will result in IRA/reload | ||
| 620 | + spilling such constants under high register pressure instead of | ||
| 621 | + rematerializing them. */ | ||
| 622 | + | ||
| 623 | switch (GET_CODE (x)) | ||
| 624 | { | ||
| 625 | case REG: | ||
| 626 | case SUBREG: | ||
| 627 | - case CONST_INT: | ||
| 628 | - case CONST_DOUBLE: | ||
| 629 | - case CONST_FIXED: | ||
| 630 | - case CONST_VECTOR: | ||
| 631 | case CALL: | ||
| 632 | return 0; | ||
| 633 | |||
| 634 | + case CONST_INT: | ||
| 635 | + case CONST_DOUBLE: | ||
| 636 | + case CONST_FIXED: | ||
| 637 | + case CONST_VECTOR: | ||
| 638 | + if (!doing_code_hoisting_p) | ||
| 639 | + /* Do not PRE constants. */ | ||
| 640 | + return 0; | ||
| 641 | + | ||
| 642 | + /* FALLTHRU */ | ||
| 643 | + | ||
| 644 | default: | ||
| 645 | + if (doing_code_hoisting_p) | ||
| 646 | + /* PRE doesn't implement max_distance restriction. */ | ||
| 647 | + { | ||
| 648 | + int cost; | ||
| 649 | + int max_distance; | ||
| 650 | + | ||
| 651 | + gcc_assert (!optimize_function_for_speed_p (cfun) | ||
| 652 | + && optimize_function_for_size_p (cfun)); | ||
| 653 | + cost = rtx_cost (x, SET, 0); | ||
| 654 | + | ||
| 655 | + if (cost < COSTS_N_INSNS (GCSE_UNRESTRICTED_COST)) | ||
| 656 | + { | ||
| 657 | + max_distance = (GCSE_COST_DISTANCE_RATIO * cost) / 10; | ||
| 658 | + if (max_distance == 0) | ||
| 659 | + return 0; | ||
| 660 | + | ||
| 661 | + gcc_assert (max_distance > 0); | ||
| 662 | + } | ||
| 663 | + else | ||
| 664 | + max_distance = 0; | ||
| 665 | + | ||
| 666 | + if (max_distance_ptr) | ||
| 667 | + *max_distance_ptr = max_distance; | ||
| 668 | + } | ||
| 669 | + | ||
| 670 | return can_assign_to_reg_without_clobbers_p (x); | ||
| 671 | } | ||
| 672 | } | ||
| 673 | @@ -1090,11 +1152,14 @@ | ||
| 674 | It is only used if X is a CONST_INT. | ||
| 675 | |||
| 676 | ANTIC_P is nonzero if X is an anticipatable expression. | ||
| 677 | - AVAIL_P is nonzero if X is an available expression. */ | ||
| 678 | + AVAIL_P is nonzero if X is an available expression. | ||
| 679 | + | ||
| 680 | + MAX_DISTANCE is the maximum distance in instructions this expression can | ||
| 681 | + be moved. */ | ||
| 682 | |||
| 683 | static void | ||
| 684 | insert_expr_in_table (rtx x, enum machine_mode mode, rtx insn, int antic_p, | ||
| 685 | - int avail_p, struct hash_table_d *table) | ||
| 686 | + int avail_p, int max_distance, struct hash_table_d *table) | ||
| 687 | { | ||
| 688 | int found, do_not_record_p; | ||
| 689 | unsigned int hash; | ||
| 690 | @@ -1137,7 +1202,11 @@ | ||
| 691 | cur_expr->next_same_hash = NULL; | ||
| 692 | cur_expr->antic_occr = NULL; | ||
| 693 | cur_expr->avail_occr = NULL; | ||
| 694 | + gcc_assert (max_distance >= 0); | ||
| 695 | + cur_expr->max_distance = max_distance; | ||
| 696 | } | ||
| 697 | + else | ||
| 698 | + gcc_assert (cur_expr->max_distance == max_distance); | ||
| 699 | |||
| 700 | /* Now record the occurrence(s). */ | ||
| 701 | if (antic_p) | ||
| 702 | @@ -1238,6 +1307,8 @@ | ||
| 703 | cur_expr->next_same_hash = NULL; | ||
| 704 | cur_expr->antic_occr = NULL; | ||
| 705 | cur_expr->avail_occr = NULL; | ||
| 706 | + /* Not used for set_p tables. */ | ||
| 707 | + cur_expr->max_distance = 0; | ||
| 708 | } | ||
| 709 | |||
| 710 | /* Now record the occurrence. */ | ||
| 711 | @@ -1307,6 +1378,7 @@ | ||
| 712 | { | ||
| 713 | unsigned int regno = REGNO (dest); | ||
| 714 | rtx tmp; | ||
| 715 | + int max_distance = 0; | ||
| 716 | |||
| 717 | /* See if a REG_EQUAL note shows this equivalent to a simpler expression. | ||
| 718 | |||
| 719 | @@ -1329,7 +1401,7 @@ | ||
| 720 | && !REG_P (src) | ||
| 721 | && (table->set_p | ||
| 722 | ? gcse_constant_p (XEXP (note, 0)) | ||
| 723 | - : want_to_gcse_p (XEXP (note, 0)))) | ||
| 724 | + : want_to_gcse_p (XEXP (note, 0), NULL))) | ||
| 725 | src = XEXP (note, 0), pat = gen_rtx_SET (VOIDmode, dest, src); | ||
| 726 | |||
| 727 | /* Only record sets of pseudo-regs in the hash table. */ | ||
| 728 | @@ -1344,7 +1416,7 @@ | ||
| 729 | can't do the same thing at the rtl level. */ | ||
| 730 | && !can_throw_internal (insn) | ||
| 731 | /* Is SET_SRC something we want to gcse? */ | ||
| 732 | - && want_to_gcse_p (src) | ||
| 733 | + && want_to_gcse_p (src, &max_distance) | ||
| 734 | /* Don't CSE a nop. */ | ||
| 735 | && ! set_noop_p (pat) | ||
| 736 | /* Don't GCSE if it has attached REG_EQUIV note. | ||
| 737 | @@ -1368,7 +1440,8 @@ | ||
| 738 | int avail_p = (oprs_available_p (src, insn) | ||
| 739 | && ! JUMP_P (insn)); | ||
| 740 | |||
| 741 | - insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, table); | ||
| 742 | + insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, | ||
| 743 | + max_distance, table); | ||
| 744 | } | ||
| 745 | |||
| 746 | /* Record sets for constant/copy propagation. */ | ||
| 747 | @@ -1394,6 +1467,7 @@ | ||
| 748 | else if (flag_gcse_las && REG_P (src) && MEM_P (dest)) | ||
| 749 | { | ||
| 750 | unsigned int regno = REGNO (src); | ||
| 751 | + int max_distance = 0; | ||
| 752 | |||
| 753 | /* Do not do this for constant/copy propagation. */ | ||
| 754 | if (! table->set_p | ||
| 755 | @@ -1405,7 +1479,7 @@ | ||
| 756 | do that easily for EH edges so disable GCSE on these for now. */ | ||
| 757 | && !can_throw_internal (insn) | ||
| 758 | /* Is SET_DEST something we want to gcse? */ | ||
| 759 | - && want_to_gcse_p (dest) | ||
| 760 | + && want_to_gcse_p (dest, &max_distance) | ||
| 761 | /* Don't CSE a nop. */ | ||
| 762 | && ! set_noop_p (pat) | ||
| 763 | /* Don't GCSE if it has attached REG_EQUIV note. | ||
| 764 | @@ -1427,7 +1501,7 @@ | ||
| 765 | |||
| 766 | /* Record the memory expression (DEST) in the hash table. */ | ||
| 767 | insert_expr_in_table (dest, GET_MODE (dest), insn, | ||
| 768 | - antic_p, avail_p, table); | ||
| 769 | + antic_p, avail_p, max_distance, table); | ||
| 770 | } | ||
| 771 | } | ||
| 772 | } | ||
| 773 | @@ -1513,8 +1587,8 @@ | ||
| 774 | if (flat_table[i] != 0) | ||
| 775 | { | ||
| 776 | expr = flat_table[i]; | ||
| 777 | - fprintf (file, "Index %d (hash value %d)\n ", | ||
| 778 | - expr->bitmap_index, hash_val[i]); | ||
| 779 | + fprintf (file, "Index %d (hash value %d; max distance %d)\n ", | ||
| 780 | + expr->bitmap_index, hash_val[i], expr->max_distance); | ||
| 781 | print_rtl (file, expr->expr); | ||
| 782 | fprintf (file, "\n"); | ||
| 783 | } | ||
| 784 | @@ -3168,11 +3242,6 @@ | ||
| 785 | /* Nonzero for expressions that are transparent in the block. */ | ||
| 786 | static sbitmap *transp; | ||
| 787 | |||
| 788 | -/* Nonzero for expressions that are transparent at the end of the block. | ||
| 789 | - This is only zero for expressions killed by abnormal critical edge | ||
| 790 | - created by a calls. */ | ||
| 791 | -static sbitmap *transpout; | ||
| 792 | - | ||
| 793 | /* Nonzero for expressions that are computed (available) in the block. */ | ||
| 794 | static sbitmap *comp; | ||
| 795 | |||
| 796 | @@ -3236,28 +3305,105 @@ | ||
| 797 | pre_optimal = pre_redundant = pre_insert_map = pre_delete_map = NULL; | ||
| 798 | } | ||
| 799 | |||
| 800 | -/* Top level routine to do the dataflow analysis needed by PRE. */ | ||
| 801 | +/* Remove certain expressions from anticipatable and transparent | ||
| 802 | + sets of basic blocks that have incoming abnormal edge. | ||
| 803 | + For PRE remove potentially trapping expressions to avoid placing | ||
| 804 | + them on abnormal edges. For hoisting remove memory references that | ||
| 805 | + can be clobbered by calls. */ | ||
| 806 | |||
| 807 | static void | ||
| 808 | -compute_pre_data (void) | ||
| 809 | +prune_expressions (bool pre_p) | ||
| 810 | { | ||
| 811 | - sbitmap trapping_expr; | ||
| 812 | - basic_block bb; | ||
| 813 | + sbitmap prune_exprs; | ||
| 814 | unsigned int ui; | ||
| 815 | - | ||
| 816 | - compute_local_properties (transp, comp, antloc, &expr_hash_table); | ||
| 817 | - sbitmap_vector_zero (ae_kill, last_basic_block); | ||
| 818 | - | ||
| 819 | - /* Collect expressions which might trap. */ | ||
| 820 | - trapping_expr = sbitmap_alloc (expr_hash_table.n_elems); | ||
| 821 | - sbitmap_zero (trapping_expr); | ||
| 822 | + basic_block bb; | ||
| 823 | + | ||
| 824 | + prune_exprs = sbitmap_alloc (expr_hash_table.n_elems); | ||
| 825 | + sbitmap_zero (prune_exprs); | ||
| 826 | for (ui = 0; ui < expr_hash_table.size; ui++) | ||
| 827 | { | ||
| 828 | struct expr *e; | ||
| 829 | for (e = expr_hash_table.table[ui]; e != NULL; e = e->next_same_hash) | ||
| 830 | - if (may_trap_p (e->expr)) | ||
| 831 | - SET_BIT (trapping_expr, e->bitmap_index); | ||
| 832 | - } | ||
| 833 | + { | ||
| 834 | + /* Note potentially trapping expressions. */ | ||
| 835 | + if (may_trap_p (e->expr)) | ||
| 836 | + { | ||
| 837 | + SET_BIT (prune_exprs, e->bitmap_index); | ||
| 838 | + continue; | ||
| 839 | + } | ||
| 840 | + | ||
| 841 | + if (!pre_p && MEM_P (e->expr)) | ||
| 842 | + /* Note memory references that can be clobbered by a call. | ||
| 843 | + We do not split abnormal edges in hoisting, so would | ||
| 844 | + a memory reference get hoisted along an abnormal edge, | ||
| 845 | + it would be placed /before/ the call. Therefore, only | ||
| 846 | + constant memory references can be hoisted along abnormal | ||
| 847 | + edges. */ | ||
| 848 | + { | ||
| 849 | + if (GET_CODE (XEXP (e->expr, 0)) == SYMBOL_REF | ||
| 850 | + && CONSTANT_POOL_ADDRESS_P (XEXP (e->expr, 0))) | ||
| 851 | + continue; | ||
| 852 | + | ||
| 853 | + if (MEM_READONLY_P (e->expr) | ||
| 854 | + && !MEM_VOLATILE_P (e->expr) | ||
| 855 | + && MEM_NOTRAP_P (e->expr)) | ||
| 856 | + /* Constant memory reference, e.g., a PIC address. */ | ||
| 857 | + continue; | ||
| 858 | + | ||
| 859 | + /* ??? Optimally, we would use interprocedural alias | ||
| 860 | + analysis to determine if this mem is actually killed | ||
| 861 | + by this call. */ | ||
| 862 | + | ||
| 863 | + SET_BIT (prune_exprs, e->bitmap_index); | ||
| 864 | + } | ||
| 865 | + } | ||
| 866 | + } | ||
| 867 | + | ||
| 868 | + FOR_EACH_BB (bb) | ||
| 869 | + { | ||
| 870 | + edge e; | ||
| 871 | + edge_iterator ei; | ||
| 872 | + | ||
| 873 | + /* If the current block is the destination of an abnormal edge, we | ||
| 874 | + kill all trapping (for PRE) and memory (for hoist) expressions | ||
| 875 | + because we won't be able to properly place the instruction on | ||
| 876 | + the edge. So make them neither anticipatable nor transparent. | ||
| 877 | + This is fairly conservative. | ||
| 878 | + | ||
| 879 | + ??? For hoisting it may be necessary to check for set-and-jump | ||
| 880 | + instructions here, not just for abnormal edges. The general problem | ||
| 881 | + is that when an expression cannot not be placed right at the end of | ||
| 882 | + a basic block we should account for any side-effects of a subsequent | ||
| 883 | + jump instructions that could clobber the expression. It would | ||
| 884 | + be best to implement this check along the lines of | ||
| 885 | + hoist_expr_reaches_here_p where the target block is already known | ||
| 886 | + and, hence, there's no need to conservatively prune expressions on | ||
| 887 | + "intermediate" set-and-jump instructions. */ | ||
| 888 | + FOR_EACH_EDGE (e, ei, bb->preds) | ||
| 889 | + if ((e->flags & EDGE_ABNORMAL) | ||
| 890 | + && (pre_p || CALL_P (BB_END (e->src)))) | ||
| 891 | + { | ||
| 892 | + sbitmap_difference (antloc[bb->index], | ||
| 893 | + antloc[bb->index], prune_exprs); | ||
| 894 | + sbitmap_difference (transp[bb->index], | ||
| 895 | + transp[bb->index], prune_exprs); | ||
| 896 | + break; | ||
| 897 | + } | ||
| 898 | + } | ||
| 899 | + | ||
| 900 | + sbitmap_free (prune_exprs); | ||
| 901 | +} | ||
| 902 | + | ||
| 903 | +/* Top level routine to do the dataflow analysis needed by PRE. */ | ||
| 904 | + | ||
| 905 | +static void | ||
| 906 | +compute_pre_data (void) | ||
| 907 | +{ | ||
| 908 | + basic_block bb; | ||
| 909 | + | ||
| 910 | + compute_local_properties (transp, comp, antloc, &expr_hash_table); | ||
| 911 | + prune_expressions (true); | ||
| 912 | + sbitmap_vector_zero (ae_kill, last_basic_block); | ||
| 913 | |||
| 914 | /* Compute ae_kill for each basic block using: | ||
| 915 | |||
| 916 | @@ -3266,21 +3412,6 @@ | ||
| 917 | |||
| 918 | FOR_EACH_BB (bb) | ||
| 919 | { | ||
| 920 | - edge e; | ||
| 921 | - edge_iterator ei; | ||
| 922 | - | ||
| 923 | - /* If the current block is the destination of an abnormal edge, we | ||
| 924 | - kill all trapping expressions because we won't be able to properly | ||
| 925 | - place the instruction on the edge. So make them neither | ||
| 926 | - anticipatable nor transparent. This is fairly conservative. */ | ||
| 927 | - FOR_EACH_EDGE (e, ei, bb->preds) | ||
| 928 | - if (e->flags & EDGE_ABNORMAL) | ||
| 929 | - { | ||
| 930 | - sbitmap_difference (antloc[bb->index], antloc[bb->index], trapping_expr); | ||
| 931 | - sbitmap_difference (transp[bb->index], transp[bb->index], trapping_expr); | ||
| 932 | - break; | ||
| 933 | - } | ||
| 934 | - | ||
| 935 | sbitmap_a_or_b (ae_kill[bb->index], transp[bb->index], comp[bb->index]); | ||
| 936 | sbitmap_not (ae_kill[bb->index], ae_kill[bb->index]); | ||
| 937 | } | ||
| 938 | @@ -3291,7 +3422,6 @@ | ||
| 939 | antloc = NULL; | ||
| 940 | sbitmap_vector_free (ae_kill); | ||
| 941 | ae_kill = NULL; | ||
| 942 | - sbitmap_free (trapping_expr); | ||
| 943 | } | ||
| 944 | |||
| 945 | /* PRE utilities */ | ||
| 946 | @@ -3406,14 +3536,10 @@ | ||
| 947 | |||
| 948 | /* Add EXPR to the end of basic block BB. | ||
| 949 | |||
| 950 | - This is used by both the PRE and code hoisting. | ||
| 951 | - | ||
| 952 | - For PRE, we want to verify that the expr is either transparent | ||
| 953 | - or locally anticipatable in the target block. This check makes | ||
| 954 | - no sense for code hoisting. */ | ||
| 955 | + This is used by both the PRE and code hoisting. */ | ||
| 956 | |||
| 957 | static void | ||
| 958 | -insert_insn_end_basic_block (struct expr *expr, basic_block bb, int pre) | ||
| 959 | +insert_insn_end_basic_block (struct expr *expr, basic_block bb) | ||
| 960 | { | ||
| 961 | rtx insn = BB_END (bb); | ||
| 962 | rtx new_insn; | ||
| 963 | @@ -3440,12 +3566,6 @@ | ||
| 964 | #ifdef HAVE_cc0 | ||
| 965 | rtx note; | ||
| 966 | #endif | ||
| 967 | - /* It should always be the case that we can put these instructions | ||
| 968 | - anywhere in the basic block with performing PRE optimizations. | ||
| 969 | - Check this. */ | ||
| 970 | - gcc_assert (!NONJUMP_INSN_P (insn) || !pre | ||
| 971 | - || TEST_BIT (antloc[bb->index], expr->bitmap_index) | ||
| 972 | - || TEST_BIT (transp[bb->index], expr->bitmap_index)); | ||
| 973 | |||
| 974 | /* If this is a jump table, then we can't insert stuff here. Since | ||
| 975 | we know the previous real insn must be the tablejump, we insert | ||
| 976 | @@ -3482,15 +3602,7 @@ | ||
| 977 | /* Keeping in mind SMALL_REGISTER_CLASSES and parameters in registers, | ||
| 978 | we search backward and place the instructions before the first | ||
| 979 | parameter is loaded. Do this for everyone for consistency and a | ||
| 980 | - presumption that we'll get better code elsewhere as well. | ||
| 981 | - | ||
| 982 | - It should always be the case that we can put these instructions | ||
| 983 | - anywhere in the basic block with performing PRE optimizations. | ||
| 984 | - Check this. */ | ||
| 985 | - | ||
| 986 | - gcc_assert (!pre | ||
| 987 | - || TEST_BIT (antloc[bb->index], expr->bitmap_index) | ||
| 988 | - || TEST_BIT (transp[bb->index], expr->bitmap_index)); | ||
| 989 | + presumption that we'll get better code elsewhere as well. */ | ||
| 990 | |||
| 991 | /* Since different machines initialize their parameter registers | ||
| 992 | in different orders, assume nothing. Collect the set of all | ||
| 993 | @@ -3587,7 +3699,7 @@ | ||
| 994 | now. */ | ||
| 995 | |||
| 996 | if (eg->flags & EDGE_ABNORMAL) | ||
| 997 | - insert_insn_end_basic_block (index_map[j], bb, 0); | ||
| 998 | + insert_insn_end_basic_block (index_map[j], bb); | ||
| 999 | else | ||
| 1000 | { | ||
| 1001 | insn = process_insert_insn (index_map[j]); | ||
| 1002 | @@ -4046,61 +4158,12 @@ | ||
| 1003 | } | ||
| 1004 | } | ||
| 1005 | |||
| 1006 | -/* Compute transparent outgoing information for each block. | ||
| 1007 | - | ||
| 1008 | - An expression is transparent to an edge unless it is killed by | ||
| 1009 | - the edge itself. This can only happen with abnormal control flow, | ||
| 1010 | - when the edge is traversed through a call. This happens with | ||
| 1011 | - non-local labels and exceptions. | ||
| 1012 | - | ||
| 1013 | - This would not be necessary if we split the edge. While this is | ||
| 1014 | - normally impossible for abnormal critical edges, with some effort | ||
| 1015 | - it should be possible with exception handling, since we still have | ||
| 1016 | - control over which handler should be invoked. But due to increased | ||
| 1017 | - EH table sizes, this may not be worthwhile. */ | ||
| 1018 | - | ||
| 1019 | -static void | ||
| 1020 | -compute_transpout (void) | ||
| 1021 | -{ | ||
| 1022 | - basic_block bb; | ||
| 1023 | - unsigned int i; | ||
| 1024 | - struct expr *expr; | ||
| 1025 | - | ||
| 1026 | - sbitmap_vector_ones (transpout, last_basic_block); | ||
| 1027 | - | ||
| 1028 | - FOR_EACH_BB (bb) | ||
| 1029 | - { | ||
| 1030 | - /* Note that flow inserted a nop at the end of basic blocks that | ||
| 1031 | - end in call instructions for reasons other than abnormal | ||
| 1032 | - control flow. */ | ||
| 1033 | - if (! CALL_P (BB_END (bb))) | ||
| 1034 | - continue; | ||
| 1035 | - | ||
| 1036 | - for (i = 0; i < expr_hash_table.size; i++) | ||
| 1037 | - for (expr = expr_hash_table.table[i]; expr ; expr = expr->next_same_hash) | ||
| 1038 | - if (MEM_P (expr->expr)) | ||
| 1039 | - { | ||
| 1040 | - if (GET_CODE (XEXP (expr->expr, 0)) == SYMBOL_REF | ||
| 1041 | - && CONSTANT_POOL_ADDRESS_P (XEXP (expr->expr, 0))) | ||
| 1042 | - continue; | ||
| 1043 | - | ||
| 1044 | - /* ??? Optimally, we would use interprocedural alias | ||
| 1045 | - analysis to determine if this mem is actually killed | ||
| 1046 | - by this call. */ | ||
| 1047 | - RESET_BIT (transpout[bb->index], expr->bitmap_index); | ||
| 1048 | - } | ||
| 1049 | - } | ||
| 1050 | -} | ||
| 1051 | - | ||
| 1052 | /* Code Hoisting variables and subroutines. */ | ||
| 1053 | |||
| 1054 | /* Very busy expressions. */ | ||
| 1055 | static sbitmap *hoist_vbein; | ||
| 1056 | static sbitmap *hoist_vbeout; | ||
| 1057 | |||
| 1058 | -/* Hoistable expressions. */ | ||
| 1059 | -static sbitmap *hoist_exprs; | ||
| 1060 | - | ||
| 1061 | /* ??? We could compute post dominators and run this algorithm in | ||
| 1062 | reverse to perform tail merging, doing so would probably be | ||
| 1063 | more effective than the tail merging code in jump.c. | ||
| 1064 | @@ -4119,8 +4182,6 @@ | ||
| 1065 | |||
| 1066 | hoist_vbein = sbitmap_vector_alloc (n_blocks, n_exprs); | ||
| 1067 | hoist_vbeout = sbitmap_vector_alloc (n_blocks, n_exprs); | ||
| 1068 | - hoist_exprs = sbitmap_vector_alloc (n_blocks, n_exprs); | ||
| 1069 | - transpout = sbitmap_vector_alloc (n_blocks, n_exprs); | ||
| 1070 | } | ||
| 1071 | |||
| 1072 | /* Free vars used for code hoisting analysis. */ | ||
| 1073 | @@ -4134,8 +4195,6 @@ | ||
| 1074 | |||
| 1075 | sbitmap_vector_free (hoist_vbein); | ||
| 1076 | sbitmap_vector_free (hoist_vbeout); | ||
| 1077 | - sbitmap_vector_free (hoist_exprs); | ||
| 1078 | - sbitmap_vector_free (transpout); | ||
| 1079 | |||
| 1080 | free_dominance_info (CDI_DOMINATORS); | ||
| 1081 | } | ||
| 1082 | @@ -4166,8 +4225,15 @@ | ||
| 1083 | FOR_EACH_BB_REVERSE (bb) | ||
| 1084 | { | ||
| 1085 | if (bb->next_bb != EXIT_BLOCK_PTR) | ||
| 1086 | - sbitmap_intersection_of_succs (hoist_vbeout[bb->index], | ||
| 1087 | - hoist_vbein, bb->index); | ||
| 1088 | + { | ||
| 1089 | + sbitmap_intersection_of_succs (hoist_vbeout[bb->index], | ||
| 1090 | + hoist_vbein, bb->index); | ||
| 1091 | + | ||
| 1092 | + /* Include expressions in VBEout that are calculated | ||
| 1093 | + in BB and available at its end. */ | ||
| 1094 | + sbitmap_a_or_b (hoist_vbeout[bb->index], | ||
| 1095 | + hoist_vbeout[bb->index], comp[bb->index]); | ||
| 1096 | + } | ||
| 1097 | |||
| 1098 | changed |= sbitmap_a_or_b_and_c_cg (hoist_vbein[bb->index], | ||
| 1099 | antloc[bb->index], | ||
| 1100 | @@ -4179,7 +4245,17 @@ | ||
| 1101 | } | ||
| 1102 | |||
| 1103 | if (dump_file) | ||
| 1104 | - fprintf (dump_file, "hoisting vbeinout computation: %d passes\n", passes); | ||
| 1105 | + { | ||
| 1106 | + fprintf (dump_file, "hoisting vbeinout computation: %d passes\n", passes); | ||
| 1107 | + | ||
| 1108 | + FOR_EACH_BB (bb) | ||
| 1109 | + { | ||
| 1110 | + fprintf (dump_file, "vbein (%d): ", bb->index); | ||
| 1111 | + dump_sbitmap_file (dump_file, hoist_vbein[bb->index]); | ||
| 1112 | + fprintf (dump_file, "vbeout(%d): ", bb->index); | ||
| 1113 | + dump_sbitmap_file (dump_file, hoist_vbeout[bb->index]); | ||
| 1114 | + } | ||
| 1115 | + } | ||
| 1116 | } | ||
| 1117 | |||
| 1118 | /* Top level routine to do the dataflow analysis needed by code hoisting. */ | ||
| 1119 | @@ -4188,7 +4264,7 @@ | ||
| 1120 | compute_code_hoist_data (void) | ||
| 1121 | { | ||
| 1122 | compute_local_properties (transp, comp, antloc, &expr_hash_table); | ||
| 1123 | - compute_transpout (); | ||
| 1124 | + prune_expressions (false); | ||
| 1125 | compute_code_hoist_vbeinout (); | ||
| 1126 | calculate_dominance_info (CDI_DOMINATORS); | ||
| 1127 | if (dump_file) | ||
| 1128 | @@ -4197,6 +4273,8 @@ | ||
| 1129 | |||
| 1130 | /* Determine if the expression identified by EXPR_INDEX would | ||
| 1131 | reach BB unimpared if it was placed at the end of EXPR_BB. | ||
| 1132 | + Stop the search if the expression would need to be moved more | ||
| 1133 | + than DISTANCE instructions. | ||
| 1134 | |||
| 1135 | It's unclear exactly what Muchnick meant by "unimpared". It seems | ||
| 1136 | to me that the expression must either be computed or transparent in | ||
| 1137 | @@ -4209,12 +4287,24 @@ | ||
| 1138 | paths. */ | ||
| 1139 | |||
| 1140 | static int | ||
| 1141 | -hoist_expr_reaches_here_p (basic_block expr_bb, int expr_index, basic_block bb, char *visited) | ||
| 1142 | +hoist_expr_reaches_here_p (basic_block expr_bb, int expr_index, basic_block bb, | ||
| 1143 | + char *visited, int distance, int *bb_size) | ||
| 1144 | { | ||
| 1145 | edge pred; | ||
| 1146 | edge_iterator ei; | ||
| 1147 | int visited_allocated_locally = 0; | ||
| 1148 | |||
| 1149 | + /* Terminate the search if distance, for which EXPR is allowed to move, | ||
| 1150 | + is exhausted. */ | ||
| 1151 | + if (distance > 0) | ||
| 1152 | + { | ||
| 1153 | + distance -= bb_size[bb->index]; | ||
| 1154 | + | ||
| 1155 | + if (distance <= 0) | ||
| 1156 | + return 0; | ||
| 1157 | + } | ||
| 1158 | + else | ||
| 1159 | + gcc_assert (distance == 0); | ||
| 1160 | |||
| 1161 | if (visited == NULL) | ||
| 1162 | { | ||
| 1163 | @@ -4233,9 +4323,6 @@ | ||
| 1164 | else if (visited[pred_bb->index]) | ||
| 1165 | continue; | ||
| 1166 | |||
| 1167 | - /* Does this predecessor generate this expression? */ | ||
| 1168 | - else if (TEST_BIT (comp[pred_bb->index], expr_index)) | ||
| 1169 | - break; | ||
| 1170 | else if (! TEST_BIT (transp[pred_bb->index], expr_index)) | ||
| 1171 | break; | ||
| 1172 | |||
| 1173 | @@ -4243,8 +4330,8 @@ | ||
| 1174 | else | ||
| 1175 | { | ||
| 1176 | visited[pred_bb->index] = 1; | ||
| 1177 | - if (! hoist_expr_reaches_here_p (expr_bb, expr_index, | ||
| 1178 | - pred_bb, visited)) | ||
| 1179 | + if (! hoist_expr_reaches_here_p (expr_bb, expr_index, pred_bb, | ||
| 1180 | + visited, distance, bb_size)) | ||
| 1181 | break; | ||
| 1182 | } | ||
| 1183 | } | ||
| 1184 | @@ -4254,20 +4341,33 @@ | ||
| 1185 | return (pred == NULL); | ||
| 1186 | } | ||
| 1187 | |||
| 1188 | +/* Find occurence in BB. */ | ||
| 1189 | +static struct occr * | ||
| 1190 | +find_occr_in_bb (struct occr *occr, basic_block bb) | ||
| 1191 | +{ | ||
| 1192 | + /* Find the right occurrence of this expression. */ | ||
| 1193 | + while (occr && BLOCK_FOR_INSN (occr->insn) != bb) | ||
| 1194 | + occr = occr->next; | ||
| 1195 | + | ||
| 1196 | + return occr; | ||
| 1197 | +} | ||
| 1198 | + | ||
| 1199 | /* Actually perform code hoisting. */ | ||
| 1200 | |||
| 1201 | static int | ||
| 1202 | hoist_code (void) | ||
| 1203 | { | ||
| 1204 | basic_block bb, dominated; | ||
| 1205 | + VEC (basic_block, heap) *dom_tree_walk; | ||
| 1206 | + unsigned int dom_tree_walk_index; | ||
| 1207 | VEC (basic_block, heap) *domby; | ||
| 1208 | unsigned int i,j; | ||
| 1209 | struct expr **index_map; | ||
| 1210 | struct expr *expr; | ||
| 1211 | + int *to_bb_head; | ||
| 1212 | + int *bb_size; | ||
| 1213 | int changed = 0; | ||
| 1214 | |||
| 1215 | - sbitmap_vector_zero (hoist_exprs, last_basic_block); | ||
| 1216 | - | ||
| 1217 | /* Compute a mapping from expression number (`bitmap_index') to | ||
| 1218 | hash table entry. */ | ||
| 1219 | |||
| 1220 | @@ -4276,28 +4376,98 @@ | ||
| 1221 | for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash) | ||
| 1222 | index_map[expr->bitmap_index] = expr; | ||
| 1223 | |||
| 1224 | + /* Calculate sizes of basic blocks and note how far | ||
| 1225 | + each instruction is from the start of its block. We then use this | ||
| 1226 | + data to restrict distance an expression can travel. */ | ||
| 1227 | + | ||
| 1228 | + to_bb_head = XCNEWVEC (int, get_max_uid ()); | ||
| 1229 | + bb_size = XCNEWVEC (int, last_basic_block); | ||
| 1230 | + | ||
| 1231 | + FOR_EACH_BB (bb) | ||
| 1232 | + { | ||
| 1233 | + rtx insn; | ||
| 1234 | + int to_head; | ||
| 1235 | + | ||
| 1236 | + to_head = 0; | ||
| 1237 | + FOR_BB_INSNS (bb, insn) | ||
| 1238 | + { | ||
| 1239 | + /* Don't count debug instructions to avoid them affecting | ||
| 1240 | + decision choices. */ | ||
| 1241 | + if (NONDEBUG_INSN_P (insn)) | ||
| 1242 | + to_bb_head[INSN_UID (insn)] = to_head++; | ||
| 1243 | + } | ||
| 1244 | + | ||
| 1245 | + bb_size[bb->index] = to_head; | ||
| 1246 | + } | ||
| 1247 | + | ||
| 1248 | + gcc_assert (EDGE_COUNT (ENTRY_BLOCK_PTR->succs) == 1 | ||
| 1249 | + && (EDGE_SUCC (ENTRY_BLOCK_PTR, 0)->dest | ||
| 1250 | + == ENTRY_BLOCK_PTR->next_bb)); | ||
| 1251 | + | ||
| 1252 | + dom_tree_walk = get_all_dominated_blocks (CDI_DOMINATORS, | ||
| 1253 | + ENTRY_BLOCK_PTR->next_bb); | ||
| 1254 | + | ||
| 1255 | /* Walk over each basic block looking for potentially hoistable | ||
| 1256 | expressions, nothing gets hoisted from the entry block. */ | ||
| 1257 | - FOR_EACH_BB (bb) | ||
| 1258 | + for (dom_tree_walk_index = 0; | ||
| 1259 | + VEC_iterate (basic_block, dom_tree_walk, dom_tree_walk_index, bb); | ||
| 1260 | + dom_tree_walk_index++) | ||
| 1261 | { | ||
| 1262 | - int found = 0; | ||
| 1263 | - int insn_inserted_p; | ||
| 1264 | - | ||
| 1265 | - domby = get_dominated_by (CDI_DOMINATORS, bb); | ||
| 1266 | + domby = get_dominated_to_depth (CDI_DOMINATORS, bb, MAX_HOIST_DEPTH); | ||
| 1267 | + | ||
| 1268 | + if (VEC_length (basic_block, domby) == 0) | ||
| 1269 | + continue; | ||
| 1270 | + | ||
| 1271 | /* Examine each expression that is very busy at the exit of this | ||
| 1272 | block. These are the potentially hoistable expressions. */ | ||
| 1273 | for (i = 0; i < hoist_vbeout[bb->index]->n_bits; i++) | ||
| 1274 | { | ||
| 1275 | - int hoistable = 0; | ||
| 1276 | - | ||
| 1277 | - if (TEST_BIT (hoist_vbeout[bb->index], i) | ||
| 1278 | - && TEST_BIT (transpout[bb->index], i)) | ||
| 1279 | + if (TEST_BIT (hoist_vbeout[bb->index], i)) | ||
| 1280 | { | ||
| 1281 | + /* Current expression. */ | ||
| 1282 | + struct expr *expr = index_map[i]; | ||
| 1283 | + /* Number of occurences of EXPR that can be hoisted to BB. */ | ||
| 1284 | + int hoistable = 0; | ||
| 1285 | + /* Basic blocks that have occurences reachable from BB. */ | ||
| 1286 | + bitmap_head _from_bbs, *from_bbs = &_from_bbs; | ||
| 1287 | + /* Occurences reachable from BB. */ | ||
| 1288 | + VEC (occr_t, heap) *occrs_to_hoist = NULL; | ||
| 1289 | + /* We want to insert the expression into BB only once, so | ||
| 1290 | + note when we've inserted it. */ | ||
| 1291 | + int insn_inserted_p; | ||
| 1292 | + occr_t occr; | ||
| 1293 | + | ||
| 1294 | + bitmap_initialize (from_bbs, 0); | ||
| 1295 | + | ||
| 1296 | + /* If an expression is computed in BB and is available at end of | ||
| 1297 | + BB, hoist all occurences dominated by BB to BB. */ | ||
| 1298 | + if (TEST_BIT (comp[bb->index], i)) | ||
| 1299 | + { | ||
| 1300 | + occr = find_occr_in_bb (expr->antic_occr, bb); | ||
| 1301 | + | ||
| 1302 | + if (occr) | ||
| 1303 | + { | ||
| 1304 | + /* An occurence might've been already deleted | ||
| 1305 | + while processing a dominator of BB. */ | ||
| 1306 | + if (occr->deleted_p) | ||
| 1307 | + gcc_assert (MAX_HOIST_DEPTH > 1); | ||
| 1308 | + else | ||
| 1309 | + { | ||
| 1310 | + gcc_assert (NONDEBUG_INSN_P (occr->insn)); | ||
| 1311 | + hoistable++; | ||
| 1312 | + } | ||
| 1313 | + } | ||
| 1314 | + else | ||
| 1315 | + hoistable++; | ||
| 1316 | + } | ||
| 1317 | + | ||
| 1318 | /* We've found a potentially hoistable expression, now | ||
| 1319 | we look at every block BB dominates to see if it | ||
| 1320 | computes the expression. */ | ||
| 1321 | for (j = 0; VEC_iterate (basic_block, domby, j, dominated); j++) | ||
| 1322 | { | ||
| 1323 | + int max_distance; | ||
| 1324 | + | ||
| 1325 | /* Ignore self dominance. */ | ||
| 1326 | if (bb == dominated) | ||
| 1327 | continue; | ||
| 1328 | @@ -4307,17 +4477,43 @@ | ||
| 1329 | if (!TEST_BIT (antloc[dominated->index], i)) | ||
| 1330 | continue; | ||
| 1331 | |||
| 1332 | + occr = find_occr_in_bb (expr->antic_occr, dominated); | ||
| 1333 | + gcc_assert (occr); | ||
| 1334 | + | ||
| 1335 | + /* An occurence might've been already deleted | ||
| 1336 | + while processing a dominator of BB. */ | ||
| 1337 | + if (occr->deleted_p) | ||
| 1338 | + { | ||
| 1339 | + gcc_assert (MAX_HOIST_DEPTH > 1); | ||
| 1340 | + continue; | ||
| 1341 | + } | ||
| 1342 | + gcc_assert (NONDEBUG_INSN_P (occr->insn)); | ||
| 1343 | + | ||
| 1344 | + max_distance = expr->max_distance; | ||
| 1345 | + if (max_distance > 0) | ||
| 1346 | + /* Adjust MAX_DISTANCE to account for the fact that | ||
| 1347 | + OCCR won't have to travel all of DOMINATED, but | ||
| 1348 | + only part of it. */ | ||
| 1349 | + max_distance += (bb_size[dominated->index] | ||
| 1350 | + - to_bb_head[INSN_UID (occr->insn)]); | ||
| 1351 | + | ||
| 1352 | /* Note if the expression would reach the dominated block | ||
| 1353 | unimpared if it was placed at the end of BB. | ||
| 1354 | |||
| 1355 | Keep track of how many times this expression is hoistable | ||
| 1356 | from a dominated block into BB. */ | ||
| 1357 | - if (hoist_expr_reaches_here_p (bb, i, dominated, NULL)) | ||
| 1358 | - hoistable++; | ||
| 1359 | + if (hoist_expr_reaches_here_p (bb, i, dominated, NULL, | ||
| 1360 | + max_distance, bb_size)) | ||
| 1361 | + { | ||
| 1362 | + hoistable++; | ||
| 1363 | + VEC_safe_push (occr_t, heap, | ||
| 1364 | + occrs_to_hoist, occr); | ||
| 1365 | + bitmap_set_bit (from_bbs, dominated->index); | ||
| 1366 | + } | ||
| 1367 | } | ||
| 1368 | |||
| 1369 | /* If we found more than one hoistable occurrence of this | ||
| 1370 | - expression, then note it in the bitmap of expressions to | ||
| 1371 | + expression, then note it in the vector of expressions to | ||
| 1372 | hoist. It makes no sense to hoist things which are computed | ||
| 1373 | in only one BB, and doing so tends to pessimize register | ||
| 1374 | allocation. One could increase this value to try harder | ||
| 1375 | @@ -4326,91 +4522,80 @@ | ||
| 1376 | the vast majority of hoistable expressions are only movable | ||
| 1377 | from two successors, so raising this threshold is likely | ||
| 1378 | to nullify any benefit we get from code hoisting. */ | ||
| 1379 | - if (hoistable > 1) | ||
| 1380 | - { | ||
| 1381 | - SET_BIT (hoist_exprs[bb->index], i); | ||
| 1382 | - found = 1; | ||
| 1383 | - } | ||
| 1384 | - } | ||
| 1385 | - } | ||
| 1386 | - /* If we found nothing to hoist, then quit now. */ | ||
| 1387 | - if (! found) | ||
| 1388 | - { | ||
| 1389 | - VEC_free (basic_block, heap, domby); | ||
| 1390 | - continue; | ||
| 1391 | - } | ||
| 1392 | - | ||
| 1393 | - /* Loop over all the hoistable expressions. */ | ||
| 1394 | - for (i = 0; i < hoist_exprs[bb->index]->n_bits; i++) | ||
| 1395 | - { | ||
| 1396 | - /* We want to insert the expression into BB only once, so | ||
| 1397 | - note when we've inserted it. */ | ||
| 1398 | - insn_inserted_p = 0; | ||
| 1399 | - | ||
| 1400 | - /* These tests should be the same as the tests above. */ | ||
| 1401 | - if (TEST_BIT (hoist_exprs[bb->index], i)) | ||
| 1402 | - { | ||
| 1403 | - /* We've found a potentially hoistable expression, now | ||
| 1404 | - we look at every block BB dominates to see if it | ||
| 1405 | - computes the expression. */ | ||
| 1406 | - for (j = 0; VEC_iterate (basic_block, domby, j, dominated); j++) | ||
| 1407 | - { | ||
| 1408 | - /* Ignore self dominance. */ | ||
| 1409 | - if (bb == dominated) | ||
| 1410 | - continue; | ||
| 1411 | - | ||
| 1412 | - /* We've found a dominated block, now see if it computes | ||
| 1413 | - the busy expression and whether or not moving that | ||
| 1414 | - expression to the "beginning" of that block is safe. */ | ||
| 1415 | - if (!TEST_BIT (antloc[dominated->index], i)) | ||
| 1416 | - continue; | ||
| 1417 | - | ||
| 1418 | - /* The expression is computed in the dominated block and | ||
| 1419 | - it would be safe to compute it at the start of the | ||
| 1420 | - dominated block. Now we have to determine if the | ||
| 1421 | - expression would reach the dominated block if it was | ||
| 1422 | - placed at the end of BB. */ | ||
| 1423 | - if (hoist_expr_reaches_here_p (bb, i, dominated, NULL)) | ||
| 1424 | - { | ||
| 1425 | - struct expr *expr = index_map[i]; | ||
| 1426 | - struct occr *occr = expr->antic_occr; | ||
| 1427 | - rtx insn; | ||
| 1428 | - rtx set; | ||
| 1429 | - | ||
| 1430 | - /* Find the right occurrence of this expression. */ | ||
| 1431 | - while (BLOCK_FOR_INSN (occr->insn) != dominated && occr) | ||
| 1432 | - occr = occr->next; | ||
| 1433 | - | ||
| 1434 | - gcc_assert (occr); | ||
| 1435 | - insn = occr->insn; | ||
| 1436 | - set = single_set (insn); | ||
| 1437 | - gcc_assert (set); | ||
| 1438 | - | ||
| 1439 | - /* Create a pseudo-reg to store the result of reaching | ||
| 1440 | - expressions into. Get the mode for the new pseudo | ||
| 1441 | - from the mode of the original destination pseudo. */ | ||
| 1442 | - if (expr->reaching_reg == NULL) | ||
| 1443 | - expr->reaching_reg | ||
| 1444 | - = gen_reg_rtx_and_attrs (SET_DEST (set)); | ||
| 1445 | - | ||
| 1446 | - gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), insn); | ||
| 1447 | - delete_insn (insn); | ||
| 1448 | - occr->deleted_p = 1; | ||
| 1449 | - changed = 1; | ||
| 1450 | - gcse_subst_count++; | ||
| 1451 | - | ||
| 1452 | - if (!insn_inserted_p) | ||
| 1453 | - { | ||
| 1454 | - insert_insn_end_basic_block (index_map[i], bb, 0); | ||
| 1455 | - insn_inserted_p = 1; | ||
| 1456 | - } | ||
| 1457 | - } | ||
| 1458 | - } | ||
| 1459 | + if (hoistable > 1 && dbg_cnt (hoist_insn)) | ||
| 1460 | + { | ||
| 1461 | + /* If (hoistable != VEC_length), then there is | ||
| 1462 | + an occurence of EXPR in BB itself. Don't waste | ||
| 1463 | + time looking for LCA in this case. */ | ||
| 1464 | + if ((unsigned) hoistable | ||
| 1465 | + == VEC_length (occr_t, occrs_to_hoist)) | ||
| 1466 | + { | ||
| 1467 | + basic_block lca; | ||
| 1468 | + | ||
| 1469 | + lca = nearest_common_dominator_for_set (CDI_DOMINATORS, | ||
| 1470 | + from_bbs); | ||
| 1471 | + if (lca != bb) | ||
| 1472 | + /* Punt, it's better to hoist these occurences to | ||
| 1473 | + LCA. */ | ||
| 1474 | + VEC_free (occr_t, heap, occrs_to_hoist); | ||
| 1475 | + } | ||
| 1476 | + } | ||
| 1477 | + else | ||
| 1478 | + /* Punt, no point hoisting a single occurence. */ | ||
| 1479 | + VEC_free (occr_t, heap, occrs_to_hoist); | ||
| 1480 | + | ||
| 1481 | + insn_inserted_p = 0; | ||
| 1482 | + | ||
| 1483 | + /* Walk through occurences of I'th expressions we want | ||
| 1484 | + to hoist to BB and make the transformations. */ | ||
| 1485 | + for (j = 0; | ||
| 1486 | + VEC_iterate (occr_t, occrs_to_hoist, j, occr); | ||
| 1487 | + j++) | ||
| 1488 | + { | ||
| 1489 | + rtx insn; | ||
| 1490 | + rtx set; | ||
| 1491 | + | ||
| 1492 | + gcc_assert (!occr->deleted_p); | ||
| 1493 | + | ||
| 1494 | + insn = occr->insn; | ||
| 1495 | + set = single_set (insn); | ||
| 1496 | + gcc_assert (set); | ||
| 1497 | + | ||
| 1498 | + /* Create a pseudo-reg to store the result of reaching | ||
| 1499 | + expressions into. Get the mode for the new pseudo | ||
| 1500 | + from the mode of the original destination pseudo. | ||
| 1501 | + | ||
| 1502 | + It is important to use new pseudos whenever we | ||
| 1503 | + emit a set. This will allow reload to use | ||
| 1504 | + rematerialization for such registers. */ | ||
| 1505 | + if (!insn_inserted_p) | ||
| 1506 | + expr->reaching_reg | ||
| 1507 | + = gen_reg_rtx_and_attrs (SET_DEST (set)); | ||
| 1508 | + | ||
| 1509 | + gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), | ||
| 1510 | + insn); | ||
| 1511 | + delete_insn (insn); | ||
| 1512 | + occr->deleted_p = 1; | ||
| 1513 | + changed = 1; | ||
| 1514 | + gcse_subst_count++; | ||
| 1515 | + | ||
| 1516 | + if (!insn_inserted_p) | ||
| 1517 | + { | ||
| 1518 | + insert_insn_end_basic_block (expr, bb); | ||
| 1519 | + insn_inserted_p = 1; | ||
| 1520 | + } | ||
| 1521 | + } | ||
| 1522 | + | ||
| 1523 | + VEC_free (occr_t, heap, occrs_to_hoist); | ||
| 1524 | + bitmap_clear (from_bbs); | ||
| 1525 | } | ||
| 1526 | } | ||
| 1527 | VEC_free (basic_block, heap, domby); | ||
| 1528 | } | ||
| 1529 | |||
| 1530 | + VEC_free (basic_block, heap, dom_tree_walk); | ||
| 1531 | + free (bb_size); | ||
| 1532 | + free (to_bb_head); | ||
| 1533 | free (index_map); | ||
| 1534 | |||
| 1535 | return changed; | ||
| 1536 | @@ -4433,6 +4618,8 @@ | ||
| 1537 | || is_too_expensive (_("GCSE disabled"))) | ||
| 1538 | return 0; | ||
| 1539 | |||
| 1540 | + doing_code_hoisting_p = true; | ||
| 1541 | + | ||
| 1542 | /* We need alias. */ | ||
| 1543 | init_alias_analysis (); | ||
| 1544 | |||
| 1545 | @@ -4468,6 +4655,8 @@ | ||
| 1546 | gcse_subst_count, gcse_create_count); | ||
| 1547 | } | ||
| 1548 | |||
| 1549 | + doing_code_hoisting_p = false; | ||
| 1550 | + | ||
| 1551 | return changed; | ||
| 1552 | } | ||
| 1553 | |||
| 1554 | |||
| 1555 | === modified file 'gcc/params.def' | ||
| 1556 | --- old/gcc/params.def 2010-04-02 18:54:46 +0000 | ||
| 1557 | +++ new/gcc/params.def 2010-08-16 09:41:58 +0000 | ||
| 1558 | @@ -219,6 +219,29 @@ | ||
| 1559 | "gcse-after-reload-critical-fraction", | ||
| 1560 | "The threshold ratio of critical edges execution count that permit performing redundancy elimination after reload", | ||
| 1561 | 10, 0, 0) | ||
| 1562 | + | ||
| 1563 | +/* GCSE will use GCSE_COST_DISTANCE_RATION as a scaling factor | ||
| 1564 | + to calculate maximum distance for which an expression is allowed to move | ||
| 1565 | + from its rtx_cost. */ | ||
| 1566 | +DEFPARAM(PARAM_GCSE_COST_DISTANCE_RATIO, | ||
| 1567 | + "gcse-cost-distance-ratio", | ||
| 1568 | + "Scaling factor in calculation of maximum distance an expression can be moved by GCSE optimizations", | ||
| 1569 | + 10, 0, 0) | ||
| 1570 | +/* GCSE won't restrict distance for which an expression with rtx_cost greater | ||
| 1571 | + than COSTS_N_INSN(GCSE_UNRESTRICTED_COST) is allowed to move. */ | ||
| 1572 | +DEFPARAM(PARAM_GCSE_UNRESTRICTED_COST, | ||
| 1573 | + "gcse-unrestricted-cost", | ||
| 1574 | + "Cost at which GCSE optimizations will not constraint the distance an expression can travel", | ||
| 1575 | + 3, 0, 0) | ||
| 1576 | + | ||
| 1577 | +/* How deep from a given basic block the dominator tree should be searched | ||
| 1578 | + for expressions to hoist to the block. The value of 0 will avoid limiting | ||
| 1579 | + the search. */ | ||
| 1580 | +DEFPARAM(PARAM_MAX_HOIST_DEPTH, | ||
| 1581 | + "max-hoist-depth", | ||
| 1582 | + "Maximum depth of search in the dominator tree for expressions to hoist", | ||
| 1583 | + 30, 0, 0) | ||
| 1584 | + | ||
| 1585 | /* This parameter limits the number of insns in a loop that will be unrolled, | ||
| 1586 | and by how much the loop is unrolled. | ||
| 1587 | |||
| 1588 | |||
| 1589 | === modified file 'gcc/params.h' | ||
| 1590 | --- old/gcc/params.h 2009-12-01 19:12:29 +0000 | ||
| 1591 | +++ new/gcc/params.h 2010-08-16 09:41:58 +0000 | ||
| 1592 | @@ -125,6 +125,12 @@ | ||
| 1593 | PARAM_VALUE (PARAM_GCSE_AFTER_RELOAD_PARTIAL_FRACTION) | ||
| 1594 | #define GCSE_AFTER_RELOAD_CRITICAL_FRACTION \ | ||
| 1595 | PARAM_VALUE (PARAM_GCSE_AFTER_RELOAD_CRITICAL_FRACTION) | ||
| 1596 | +#define GCSE_COST_DISTANCE_RATIO \ | ||
| 1597 | + PARAM_VALUE (PARAM_GCSE_COST_DISTANCE_RATIO) | ||
| 1598 | +#define GCSE_UNRESTRICTED_COST \ | ||
| 1599 | + PARAM_VALUE (PARAM_GCSE_UNRESTRICTED_COST) | ||
| 1600 | +#define MAX_HOIST_DEPTH \ | ||
| 1601 | + PARAM_VALUE (PARAM_MAX_HOIST_DEPTH) | ||
| 1602 | #define MAX_UNROLLED_INSNS \ | ||
| 1603 | PARAM_VALUE (PARAM_MAX_UNROLLED_INSNS) | ||
| 1604 | #define MAX_SMS_LOOP_NUMBER \ | ||
| 1605 | |||
| 1606 | === added file 'gcc/testsuite/gcc.dg/pr45101.c' | ||
| 1607 | --- old/gcc/testsuite/gcc.dg/pr45101.c 1970-01-01 00:00:00 +0000 | ||
| 1608 | +++ new/gcc/testsuite/gcc.dg/pr45101.c 2010-08-16 09:41:58 +0000 | ||
| 1609 | @@ -0,0 +1,15 @@ | ||
| 1610 | +/* PR rtl-optimization/45101 */ | ||
| 1611 | +/* { dg-do compile } */ | ||
| 1612 | +/* { dg-options "-O2 -fgcse -fgcse-las" } */ | ||
| 1613 | + | ||
| 1614 | +struct | ||
| 1615 | +{ | ||
| 1616 | + int i; | ||
| 1617 | +} *s; | ||
| 1618 | + | ||
| 1619 | +extern void bar (void); | ||
| 1620 | + | ||
| 1621 | +void foo () | ||
| 1622 | +{ | ||
| 1623 | + !s ? s->i++ : bar (); | ||
| 1624 | +} | ||
| 1625 | |||
| 1626 | === added file 'gcc/testsuite/gcc.dg/pr45105.c' | ||
| 1627 | --- old/gcc/testsuite/gcc.dg/pr45105.c 1970-01-01 00:00:00 +0000 | ||
| 1628 | +++ new/gcc/testsuite/gcc.dg/pr45105.c 2010-08-16 09:41:58 +0000 | ||
| 1629 | @@ -0,0 +1,27 @@ | ||
| 1630 | +/* PR debug/45105 */ | ||
| 1631 | +/* { dg-do compile } */ | ||
| 1632 | +/* { dg-options "-Os -fcompare-debug" } */ | ||
| 1633 | + | ||
| 1634 | +extern int *baz (int *, int *); | ||
| 1635 | + | ||
| 1636 | +void | ||
| 1637 | +bar (int *p1, int *p2) | ||
| 1638 | +{ | ||
| 1639 | + int n = *baz (0, 0); | ||
| 1640 | + p1[n] = p2[n]; | ||
| 1641 | +} | ||
| 1642 | + | ||
| 1643 | +void | ||
| 1644 | +foo (int *p, int l) | ||
| 1645 | +{ | ||
| 1646 | + int a1[32]; | ||
| 1647 | + int a2[32]; | ||
| 1648 | + baz (a1, a2); | ||
| 1649 | + while (l) | ||
| 1650 | + { | ||
| 1651 | + if (l & 1) | ||
| 1652 | + p = baz (a2, p); | ||
| 1653 | + l--; | ||
| 1654 | + bar (a1, a2); | ||
| 1655 | + } | ||
| 1656 | +} | ||
| 1657 | |||
| 1658 | === added file 'gcc/testsuite/gcc.dg/pr45107.c' | ||
| 1659 | --- old/gcc/testsuite/gcc.dg/pr45107.c 1970-01-01 00:00:00 +0000 | ||
| 1660 | +++ new/gcc/testsuite/gcc.dg/pr45107.c 2010-08-16 09:41:58 +0000 | ||
| 1661 | @@ -0,0 +1,13 @@ | ||
| 1662 | +/* PR rtl-optimization/45107 */ | ||
| 1663 | +/* { dg-do compile } */ | ||
| 1664 | +/* { dg-options "-Os -fgcse-las" } */ | ||
| 1665 | + | ||
| 1666 | +extern void bar(int *); | ||
| 1667 | + | ||
| 1668 | +int foo (int *p) | ||
| 1669 | +{ | ||
| 1670 | + int i = *p; | ||
| 1671 | + if (i != 1) | ||
| 1672 | + bar(&i); | ||
| 1673 | + *p = i; | ||
| 1674 | +} | ||
| 1675 | |||
| 1676 | === added file 'gcc/testsuite/gcc.target/arm/pr40956.c' | ||
| 1677 | --- old/gcc/testsuite/gcc.target/arm/pr40956.c 1970-01-01 00:00:00 +0000 | ||
| 1678 | +++ new/gcc/testsuite/gcc.target/arm/pr40956.c 2010-08-16 09:41:58 +0000 | ||
| 1679 | @@ -0,0 +1,14 @@ | ||
| 1680 | +/* { dg-options "-mthumb -Os -fpic -march=armv5te" } */ | ||
| 1681 | +/* { dg-require-effective-target arm_thumb1_ok } */ | ||
| 1682 | +/* { dg-require-effective-target fpic } */ | ||
| 1683 | +/* Make sure the constant "0" is loaded into register only once. */ | ||
| 1684 | +/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 } } */ | ||
| 1685 | + | ||
| 1686 | +int foo(int p, int* q) | ||
| 1687 | +{ | ||
| 1688 | + if (p!=9) | ||
| 1689 | + *q = 0; | ||
| 1690 | + else | ||
| 1691 | + *(q+1) = 0; | ||
| 1692 | + return 3; | ||
| 1693 | +} | ||
| 1694 | |||
| 1695 | === added file 'gcc/testsuite/gcc.target/arm/pr42495.c' | ||
| 1696 | --- old/gcc/testsuite/gcc.target/arm/pr42495.c 1970-01-01 00:00:00 +0000 | ||
| 1697 | +++ new/gcc/testsuite/gcc.target/arm/pr42495.c 2010-08-16 09:41:58 +0000 | ||
| 1698 | @@ -0,0 +1,31 @@ | ||
| 1699 | +/* { dg-options "-mthumb -Os -fpic -march=armv5te -fdump-rtl-hoist" } */ | ||
| 1700 | +/* { dg-require-effective-target arm_thumb1_ok } */ | ||
| 1701 | +/* { dg-require-effective-target fpic } */ | ||
| 1702 | +/* Make sure all calculations of gObj's address get hoisted to one location. */ | ||
| 1703 | +/* { dg-final { scan-rtl-dump "PRE/HOIST: end of bb .* copying expression" "hoist" } } */ | ||
| 1704 | + | ||
| 1705 | +struct st_a { | ||
| 1706 | + int data; | ||
| 1707 | +}; | ||
| 1708 | + | ||
| 1709 | +struct st_b { | ||
| 1710 | + struct st_a *p_a; | ||
| 1711 | + struct st_b *next; | ||
| 1712 | +}; | ||
| 1713 | + | ||
| 1714 | +extern struct st_b gObj; | ||
| 1715 | +extern void foo(int, struct st_b*); | ||
| 1716 | + | ||
| 1717 | +int goo(struct st_b * obj) { | ||
| 1718 | + struct st_a *pa; | ||
| 1719 | + if (gObj.p_a->data != 0) { | ||
| 1720 | + foo(gObj.p_a->data, obj); | ||
| 1721 | + } | ||
| 1722 | + pa = obj->p_a; | ||
| 1723 | + if (pa == 0) { | ||
| 1724 | + return 0; | ||
| 1725 | + } else if (pa == gObj.p_a) { | ||
| 1726 | + return 0; | ||
| 1727 | + } | ||
| 1728 | + return pa->data; | ||
| 1729 | +} | ||
| 1730 | |||
| 1731 | === added file 'gcc/testsuite/gcc.target/arm/pr42574.c' | ||
| 1732 | --- old/gcc/testsuite/gcc.target/arm/pr42574.c 1970-01-01 00:00:00 +0000 | ||
| 1733 | +++ new/gcc/testsuite/gcc.target/arm/pr42574.c 2010-08-16 09:41:58 +0000 | ||
| 1734 | @@ -0,0 +1,24 @@ | ||
| 1735 | +/* { dg-options "-mthumb -Os -fpic -march=armv5te" } */ | ||
| 1736 | +/* { dg-require-effective-target arm_thumb1_ok } */ | ||
| 1737 | +/* { dg-require-effective-target fpic } */ | ||
| 1738 | +/* Make sure the address of glob.c is calculated only once and using | ||
| 1739 | + a logical shift for the offset (200<<1). */ | ||
| 1740 | +/* { dg-final { scan-assembler-times "lsl" 1 } } */ | ||
| 1741 | + | ||
| 1742 | +struct A { | ||
| 1743 | + char a[400]; | ||
| 1744 | + float* c; | ||
| 1745 | +}; | ||
| 1746 | +struct A glob; | ||
| 1747 | +void func(); | ||
| 1748 | +void func1(float*); | ||
| 1749 | +int func2(float*, int*); | ||
| 1750 | +void func3(float*); | ||
| 1751 | + | ||
| 1752 | +void test(int *p) { | ||
| 1753 | + func1(glob.c); | ||
| 1754 | + if (func2(glob.c, p)) { | ||
| 1755 | + func(); | ||
| 1756 | + } | ||
| 1757 | + func3(glob.c); | ||
| 1758 | +} | ||
| 1759 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99361.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99361.patch deleted file mode 100644 index db9e63917..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99361.patch +++ /dev/null | |||
| @@ -1,17586 +0,0 @@ | |||
| 1 | 2010-08-04 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * config/arm/neon-testgen.ml (regexps): Allow any characters | ||
| 5 | in comments after assembly instructions. | ||
| 6 | |||
| 7 | gcc/testsuite/ | ||
| 8 | * gcc.target/arm/neon/vfp-shift-a2t2.c: Allow any characters in | ||
| 9 | comments after assembly instructions. | ||
| 10 | * gcc.target/arm/neon/v*.c: Regenerate. | ||
| 11 | |||
| 12 | 2010-07-28 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 13 | |||
| 14 | Backport code hoisting improvements from mainline: | ||
| 15 | |||
| 16 | === modified file 'gcc/config/arm/neon-testgen.ml' | ||
| 17 | --- old/gcc/config/arm/neon-testgen.ml 2010-07-29 15:38:15 +0000 | ||
| 18 | +++ new/gcc/config/arm/neon-testgen.ml 2010-08-20 13:27:11 +0000 | ||
| 19 | @@ -257,7 +257,7 @@ | ||
| 20 | intrinsic expands to. Watch out for any writeback character and | ||
| 21 | comments after the instruction. *) | ||
| 22 | let regexps = List.map (fun regexp -> insn_regexp ^ "\\[ \t\\]+" ^ regexp ^ | ||
| 23 | - "!?\\(\\[ \t\\]+@\\[a-zA-Z0-9 \\]+\\)?\\n") | ||
| 24 | + "!?\\(\\[ \t\\]+@.*\\)?\\n") | ||
| 25 | (analyze_all_shapes features shape analyze_shape) | ||
| 26 | in | ||
| 27 | (* Emit file and function prologues. *) | ||
| 28 | |||
| 29 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c' | ||
| 30 | --- old/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c 2010-07-29 15:38:15 +0000 | ||
| 31 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c 2010-08-20 13:27:11 +0000 | ||
| 32 | @@ -17,5 +17,5 @@ | ||
| 33 | out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 34 | } | ||
| 35 | |||
| 36 | -/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 37 | +/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 38 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 39 | |||
| 40 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c' | ||
| 41 | --- old/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c 2010-07-29 15:38:15 +0000 | ||
| 42 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c 2010-08-20 13:27:11 +0000 | ||
| 43 | @@ -17,5 +17,5 @@ | ||
| 44 | out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 45 | } | ||
| 46 | |||
| 47 | -/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 48 | +/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 49 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 50 | |||
| 51 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c' | ||
| 52 | --- old/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c 2010-07-29 15:38:15 +0000 | ||
| 53 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c 2010-08-20 13:27:11 +0000 | ||
| 54 | @@ -17,5 +17,5 @@ | ||
| 55 | out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 56 | } | ||
| 57 | |||
| 58 | -/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 59 | +/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 60 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 61 | |||
| 62 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c' | ||
| 63 | --- old/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c 2010-07-29 15:38:15 +0000 | ||
| 64 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c 2010-08-20 13:27:11 +0000 | ||
| 65 | @@ -17,5 +17,5 @@ | ||
| 66 | out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 67 | } | ||
| 68 | |||
| 69 | -/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 70 | +/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 71 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 72 | |||
| 73 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c' | ||
| 74 | --- old/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c 2010-07-29 15:38:15 +0000 | ||
| 75 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c 2010-08-20 13:27:11 +0000 | ||
| 76 | @@ -17,5 +17,5 @@ | ||
| 77 | out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 78 | } | ||
| 79 | |||
| 80 | -/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 81 | +/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 82 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 83 | |||
| 84 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c' | ||
| 85 | --- old/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c 2010-07-29 15:38:15 +0000 | ||
| 86 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c 2010-08-20 13:27:11 +0000 | ||
| 87 | @@ -17,5 +17,5 @@ | ||
| 88 | out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 89 | } | ||
| 90 | |||
| 91 | -/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 92 | +/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 93 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 94 | |||
| 95 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c' | ||
| 96 | --- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c 2010-07-29 15:38:15 +0000 | ||
| 97 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c 2010-08-20 13:27:11 +0000 | ||
| 98 | @@ -17,5 +17,5 @@ | ||
| 99 | out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 100 | } | ||
| 101 | |||
| 102 | -/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 103 | +/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 104 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 105 | |||
| 106 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c' | ||
| 107 | --- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c 2010-07-29 15:38:15 +0000 | ||
| 108 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c 2010-08-20 13:27:11 +0000 | ||
| 109 | @@ -17,5 +17,5 @@ | ||
| 110 | out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 111 | } | ||
| 112 | |||
| 113 | -/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 114 | +/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 115 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 116 | |||
| 117 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c' | ||
| 118 | --- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c 2010-07-29 15:38:15 +0000 | ||
| 119 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c 2010-08-20 13:27:11 +0000 | ||
| 120 | @@ -17,5 +17,5 @@ | ||
| 121 | out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 122 | } | ||
| 123 | |||
| 124 | -/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 125 | +/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 126 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 127 | |||
| 128 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c' | ||
| 129 | --- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c 2010-07-29 15:38:15 +0000 | ||
| 130 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c 2010-08-20 13:27:11 +0000 | ||
| 131 | @@ -17,5 +17,5 @@ | ||
| 132 | out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 133 | } | ||
| 134 | |||
| 135 | -/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 136 | +/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 137 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 138 | |||
| 139 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c' | ||
| 140 | --- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c 2010-07-29 15:38:15 +0000 | ||
| 141 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c 2010-08-20 13:27:11 +0000 | ||
| 142 | @@ -17,5 +17,5 @@ | ||
| 143 | out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 144 | } | ||
| 145 | |||
| 146 | -/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 147 | +/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 148 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 149 | |||
| 150 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c' | ||
| 151 | --- old/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c 2010-07-29 15:38:15 +0000 | ||
| 152 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c 2010-08-20 13:27:11 +0000 | ||
| 153 | @@ -17,5 +17,5 @@ | ||
| 154 | out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 155 | } | ||
| 156 | |||
| 157 | -/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 158 | +/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 159 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 160 | |||
| 161 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRhadds16.c' | ||
| 162 | --- old/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c 2010-07-29 15:38:15 +0000 | ||
| 163 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c 2010-08-20 13:27:11 +0000 | ||
| 164 | @@ -17,5 +17,5 @@ | ||
| 165 | out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 166 | } | ||
| 167 | |||
| 168 | -/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 169 | +/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 170 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 171 | |||
| 172 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRhadds32.c' | ||
| 173 | --- old/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c 2010-07-29 15:38:15 +0000 | ||
| 174 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c 2010-08-20 13:27:11 +0000 | ||
| 175 | @@ -17,5 +17,5 @@ | ||
| 176 | out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 177 | } | ||
| 178 | |||
| 179 | -/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 180 | +/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 181 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 182 | |||
| 183 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRhadds8.c' | ||
| 184 | --- old/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c 2010-07-29 15:38:15 +0000 | ||
| 185 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c 2010-08-20 13:27:11 +0000 | ||
| 186 | @@ -17,5 +17,5 @@ | ||
| 187 | out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 188 | } | ||
| 189 | |||
| 190 | -/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 191 | +/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 192 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 193 | |||
| 194 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c' | ||
| 195 | --- old/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c 2010-07-29 15:38:15 +0000 | ||
| 196 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c 2010-08-20 13:27:11 +0000 | ||
| 197 | @@ -17,5 +17,5 @@ | ||
| 198 | out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 199 | } | ||
| 200 | |||
| 201 | -/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 202 | +/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 203 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 204 | |||
| 205 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c' | ||
| 206 | --- old/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c 2010-07-29 15:38:15 +0000 | ||
| 207 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c 2010-08-20 13:27:11 +0000 | ||
| 208 | @@ -17,5 +17,5 @@ | ||
| 209 | out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 210 | } | ||
| 211 | |||
| 212 | -/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 213 | +/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 214 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 215 | |||
| 216 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c' | ||
| 217 | --- old/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c 2010-07-29 15:38:15 +0000 | ||
| 218 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c 2010-08-20 13:27:11 +0000 | ||
| 219 | @@ -17,5 +17,5 @@ | ||
| 220 | out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 221 | } | ||
| 222 | |||
| 223 | -/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 224 | +/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 225 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 226 | |||
| 227 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c' | ||
| 228 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c 2010-07-29 15:38:15 +0000 | ||
| 229 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c 2010-08-20 13:27:11 +0000 | ||
| 230 | @@ -17,5 +17,5 @@ | ||
| 231 | out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 232 | } | ||
| 233 | |||
| 234 | -/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 235 | +/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 236 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 237 | |||
| 238 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c' | ||
| 239 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c 2010-07-29 15:38:15 +0000 | ||
| 240 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c 2010-08-20 13:27:11 +0000 | ||
| 241 | @@ -17,5 +17,5 @@ | ||
| 242 | out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 243 | } | ||
| 244 | |||
| 245 | -/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 246 | +/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 247 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 248 | |||
| 249 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c' | ||
| 250 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c 2010-07-29 15:38:15 +0000 | ||
| 251 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c 2010-08-20 13:27:11 +0000 | ||
| 252 | @@ -17,5 +17,5 @@ | ||
| 253 | out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 254 | } | ||
| 255 | |||
| 256 | -/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 257 | +/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 258 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 259 | |||
| 260 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c' | ||
| 261 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c 2010-07-29 15:38:15 +0000 | ||
| 262 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c 2010-08-20 13:27:11 +0000 | ||
| 263 | @@ -17,5 +17,5 @@ | ||
| 264 | out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 265 | } | ||
| 266 | |||
| 267 | -/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 268 | +/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 269 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 270 | |||
| 271 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c' | ||
| 272 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c 2010-07-29 15:38:15 +0000 | ||
| 273 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c 2010-08-20 13:27:11 +0000 | ||
| 274 | @@ -17,5 +17,5 @@ | ||
| 275 | out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); | ||
| 276 | } | ||
| 277 | |||
| 278 | -/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 279 | +/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 280 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 281 | |||
| 282 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c' | ||
| 283 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c 2010-07-29 15:38:15 +0000 | ||
| 284 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c 2010-08-20 13:27:11 +0000 | ||
| 285 | @@ -17,5 +17,5 @@ | ||
| 286 | out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); | ||
| 287 | } | ||
| 288 | |||
| 289 | -/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 290 | +/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 291 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 292 | |||
| 293 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c' | ||
| 294 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c 2010-07-29 15:38:15 +0000 | ||
| 295 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c 2010-08-20 13:27:11 +0000 | ||
| 296 | @@ -17,5 +17,5 @@ | ||
| 297 | out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); | ||
| 298 | } | ||
| 299 | |||
| 300 | -/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 301 | +/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 302 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 303 | |||
| 304 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c' | ||
| 305 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c 2010-07-29 15:38:15 +0000 | ||
| 306 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c 2010-08-20 13:27:11 +0000 | ||
| 307 | @@ -17,5 +17,5 @@ | ||
| 308 | out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); | ||
| 309 | } | ||
| 310 | |||
| 311 | -/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 312 | +/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 313 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 314 | |||
| 315 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls16.c' | ||
| 316 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshls16.c 2010-07-29 15:38:15 +0000 | ||
| 317 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshls16.c 2010-08-20 13:27:11 +0000 | ||
| 318 | @@ -17,5 +17,5 @@ | ||
| 319 | out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 320 | } | ||
| 321 | |||
| 322 | -/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 323 | +/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 324 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 325 | |||
| 326 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls32.c' | ||
| 327 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshls32.c 2010-07-29 15:38:15 +0000 | ||
| 328 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshls32.c 2010-08-20 13:27:11 +0000 | ||
| 329 | @@ -17,5 +17,5 @@ | ||
| 330 | out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 331 | } | ||
| 332 | |||
| 333 | -/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 334 | +/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 335 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 336 | |||
| 337 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls64.c' | ||
| 338 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshls64.c 2010-07-29 15:38:15 +0000 | ||
| 339 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshls64.c 2010-08-20 13:27:11 +0000 | ||
| 340 | @@ -17,5 +17,5 @@ | ||
| 341 | out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 342 | } | ||
| 343 | |||
| 344 | -/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 345 | +/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 346 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 347 | |||
| 348 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshls8.c' | ||
| 349 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshls8.c 2010-07-29 15:38:15 +0000 | ||
| 350 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshls8.c 2010-08-20 13:27:11 +0000 | ||
| 351 | @@ -17,5 +17,5 @@ | ||
| 352 | out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 353 | } | ||
| 354 | |||
| 355 | -/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 356 | +/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 357 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 358 | |||
| 359 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu16.c' | ||
| 360 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c 2010-07-29 15:38:15 +0000 | ||
| 361 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c 2010-08-20 13:27:11 +0000 | ||
| 362 | @@ -17,5 +17,5 @@ | ||
| 363 | out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); | ||
| 364 | } | ||
| 365 | |||
| 366 | -/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 367 | +/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 368 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 369 | |||
| 370 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu32.c' | ||
| 371 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c 2010-07-29 15:38:15 +0000 | ||
| 372 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c 2010-08-20 13:27:11 +0000 | ||
| 373 | @@ -17,5 +17,5 @@ | ||
| 374 | out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); | ||
| 375 | } | ||
| 376 | |||
| 377 | -/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 378 | +/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 379 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 380 | |||
| 381 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu64.c' | ||
| 382 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c 2010-07-29 15:38:15 +0000 | ||
| 383 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c 2010-08-20 13:27:11 +0000 | ||
| 384 | @@ -17,5 +17,5 @@ | ||
| 385 | out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); | ||
| 386 | } | ||
| 387 | |||
| 388 | -/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 389 | +/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 390 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 391 | |||
| 392 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshlu8.c' | ||
| 393 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c 2010-07-29 15:38:15 +0000 | ||
| 394 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c 2010-08-20 13:27:11 +0000 | ||
| 395 | @@ -17,5 +17,5 @@ | ||
| 396 | out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); | ||
| 397 | } | ||
| 398 | |||
| 399 | -/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 400 | +/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 401 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 402 | |||
| 403 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c' | ||
| 404 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 405 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 406 | @@ -16,5 +16,5 @@ | ||
| 407 | out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1); | ||
| 408 | } | ||
| 409 | |||
| 410 | -/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 411 | +/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 412 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 413 | |||
| 414 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c' | ||
| 415 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 416 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 417 | @@ -16,5 +16,5 @@ | ||
| 418 | out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1); | ||
| 419 | } | ||
| 420 | |||
| 421 | -/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 422 | +/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 423 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 424 | |||
| 425 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c' | ||
| 426 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 427 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 428 | @@ -16,5 +16,5 @@ | ||
| 429 | out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1); | ||
| 430 | } | ||
| 431 | |||
| 432 | -/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 433 | +/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 434 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 435 | |||
| 436 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c' | ||
| 437 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 438 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 439 | @@ -16,5 +16,5 @@ | ||
| 440 | out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1); | ||
| 441 | } | ||
| 442 | |||
| 443 | -/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 444 | +/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 445 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 446 | |||
| 447 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c' | ||
| 448 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 449 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 450 | @@ -16,5 +16,5 @@ | ||
| 451 | out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1); | ||
| 452 | } | ||
| 453 | |||
| 454 | -/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 455 | +/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 456 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 457 | |||
| 458 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c' | ||
| 459 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 460 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 461 | @@ -16,5 +16,5 @@ | ||
| 462 | out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1); | ||
| 463 | } | ||
| 464 | |||
| 465 | -/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 466 | +/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 467 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 468 | |||
| 469 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c' | ||
| 470 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 471 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 472 | @@ -16,5 +16,5 @@ | ||
| 473 | out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1); | ||
| 474 | } | ||
| 475 | |||
| 476 | -/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 477 | +/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 478 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 479 | |||
| 480 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c' | ||
| 481 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 482 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 483 | @@ -16,5 +16,5 @@ | ||
| 484 | out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1); | ||
| 485 | } | ||
| 486 | |||
| 487 | -/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 488 | +/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 489 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 490 | |||
| 491 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c' | ||
| 492 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 493 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 494 | @@ -16,5 +16,5 @@ | ||
| 495 | out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1); | ||
| 496 | } | ||
| 497 | |||
| 498 | -/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 499 | +/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 500 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 501 | |||
| 502 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c' | ||
| 503 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 504 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 505 | @@ -16,5 +16,5 @@ | ||
| 506 | out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1); | ||
| 507 | } | ||
| 508 | |||
| 509 | -/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 510 | +/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 511 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 512 | |||
| 513 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c' | ||
| 514 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 515 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 516 | @@ -16,5 +16,5 @@ | ||
| 517 | out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1); | ||
| 518 | } | ||
| 519 | |||
| 520 | -/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 521 | +/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 522 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 523 | |||
| 524 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c' | ||
| 525 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 526 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 527 | @@ -16,5 +16,5 @@ | ||
| 528 | out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1); | ||
| 529 | } | ||
| 530 | |||
| 531 | -/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 532 | +/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 533 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 534 | |||
| 535 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c' | ||
| 536 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 537 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 538 | @@ -16,5 +16,5 @@ | ||
| 539 | out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1); | ||
| 540 | } | ||
| 541 | |||
| 542 | -/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 543 | +/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 544 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 545 | |||
| 546 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c' | ||
| 547 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 548 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 549 | @@ -16,5 +16,5 @@ | ||
| 550 | out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1); | ||
| 551 | } | ||
| 552 | |||
| 553 | -/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 554 | +/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 555 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 556 | |||
| 557 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c' | ||
| 558 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 559 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 560 | @@ -16,5 +16,5 @@ | ||
| 561 | out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1); | ||
| 562 | } | ||
| 563 | |||
| 564 | -/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 565 | +/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 566 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 567 | |||
| 568 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c' | ||
| 569 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 570 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 571 | @@ -16,5 +16,5 @@ | ||
| 572 | out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1); | ||
| 573 | } | ||
| 574 | |||
| 575 | -/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 576 | +/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 577 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 578 | |||
| 579 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c' | ||
| 580 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 581 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 582 | @@ -16,5 +16,5 @@ | ||
| 583 | out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1); | ||
| 584 | } | ||
| 585 | |||
| 586 | -/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 587 | +/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 588 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 589 | |||
| 590 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c' | ||
| 591 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 592 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 593 | @@ -16,5 +16,5 @@ | ||
| 594 | out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1); | ||
| 595 | } | ||
| 596 | |||
| 597 | -/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 598 | +/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 599 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 600 | |||
| 601 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c' | ||
| 602 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 603 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 604 | @@ -16,5 +16,5 @@ | ||
| 605 | out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1); | ||
| 606 | } | ||
| 607 | |||
| 608 | -/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 609 | +/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 610 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 611 | |||
| 612 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c' | ||
| 613 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 614 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 615 | @@ -16,5 +16,5 @@ | ||
| 616 | out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1); | ||
| 617 | } | ||
| 618 | |||
| 619 | -/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 620 | +/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 621 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 622 | |||
| 623 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c' | ||
| 624 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 625 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 626 | @@ -16,5 +16,5 @@ | ||
| 627 | out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1); | ||
| 628 | } | ||
| 629 | |||
| 630 | -/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 631 | +/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 632 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 633 | |||
| 634 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c' | ||
| 635 | --- old/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 636 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 637 | @@ -16,5 +16,5 @@ | ||
| 638 | out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1); | ||
| 639 | } | ||
| 640 | |||
| 641 | -/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 642 | +/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 643 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 644 | |||
| 645 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c' | ||
| 646 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 647 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 648 | @@ -17,5 +17,5 @@ | ||
| 649 | out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); | ||
| 650 | } | ||
| 651 | |||
| 652 | -/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 653 | +/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 654 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 655 | |||
| 656 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c' | ||
| 657 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 658 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 659 | @@ -17,5 +17,5 @@ | ||
| 660 | out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); | ||
| 661 | } | ||
| 662 | |||
| 663 | -/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 664 | +/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 665 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 666 | |||
| 667 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c' | ||
| 668 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 669 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 670 | @@ -17,5 +17,5 @@ | ||
| 671 | out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); | ||
| 672 | } | ||
| 673 | |||
| 674 | -/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 675 | +/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 676 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 677 | |||
| 678 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c' | ||
| 679 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 680 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 681 | @@ -17,5 +17,5 @@ | ||
| 682 | out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); | ||
| 683 | } | ||
| 684 | |||
| 685 | -/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 686 | +/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 687 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 688 | |||
| 689 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c' | ||
| 690 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 691 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 692 | @@ -17,5 +17,5 @@ | ||
| 693 | out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); | ||
| 694 | } | ||
| 695 | |||
| 696 | -/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 697 | +/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 698 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 699 | |||
| 700 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c' | ||
| 701 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 702 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 703 | @@ -17,5 +17,5 @@ | ||
| 704 | out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); | ||
| 705 | } | ||
| 706 | |||
| 707 | -/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 708 | +/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 709 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 710 | |||
| 711 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c' | ||
| 712 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 713 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 714 | @@ -17,5 +17,5 @@ | ||
| 715 | out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); | ||
| 716 | } | ||
| 717 | |||
| 718 | -/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 719 | +/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 720 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 721 | |||
| 722 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c' | ||
| 723 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 724 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 725 | @@ -17,5 +17,5 @@ | ||
| 726 | out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); | ||
| 727 | } | ||
| 728 | |||
| 729 | -/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 730 | +/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 731 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 732 | |||
| 733 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c' | ||
| 734 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 735 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 736 | @@ -17,5 +17,5 @@ | ||
| 737 | out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); | ||
| 738 | } | ||
| 739 | |||
| 740 | -/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 741 | +/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 742 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 743 | |||
| 744 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c' | ||
| 745 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 746 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 747 | @@ -17,5 +17,5 @@ | ||
| 748 | out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); | ||
| 749 | } | ||
| 750 | |||
| 751 | -/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 752 | +/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 753 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 754 | |||
| 755 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c' | ||
| 756 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 757 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 758 | @@ -17,5 +17,5 @@ | ||
| 759 | out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); | ||
| 760 | } | ||
| 761 | |||
| 762 | -/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 763 | +/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 764 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 765 | |||
| 766 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c' | ||
| 767 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 768 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 769 | @@ -17,5 +17,5 @@ | ||
| 770 | out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); | ||
| 771 | } | ||
| 772 | |||
| 773 | -/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 774 | +/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 775 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 776 | |||
| 777 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c' | ||
| 778 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 779 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 780 | @@ -17,5 +17,5 @@ | ||
| 781 | out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); | ||
| 782 | } | ||
| 783 | |||
| 784 | -/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 785 | +/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 786 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 787 | |||
| 788 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c' | ||
| 789 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 790 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 791 | @@ -17,5 +17,5 @@ | ||
| 792 | out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); | ||
| 793 | } | ||
| 794 | |||
| 795 | -/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 796 | +/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 797 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 798 | |||
| 799 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c' | ||
| 800 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 801 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 802 | @@ -17,5 +17,5 @@ | ||
| 803 | out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); | ||
| 804 | } | ||
| 805 | |||
| 806 | -/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 807 | +/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 808 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 809 | |||
| 810 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c' | ||
| 811 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 812 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 813 | @@ -17,5 +17,5 @@ | ||
| 814 | out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); | ||
| 815 | } | ||
| 816 | |||
| 817 | -/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 818 | +/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 819 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 820 | |||
| 821 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c' | ||
| 822 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c 2010-07-29 15:38:15 +0000 | ||
| 823 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c 2010-08-20 13:27:11 +0000 | ||
| 824 | @@ -17,5 +17,5 @@ | ||
| 825 | out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 826 | } | ||
| 827 | |||
| 828 | -/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 829 | +/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 830 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 831 | |||
| 832 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c' | ||
| 833 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c 2010-07-29 15:38:15 +0000 | ||
| 834 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c 2010-08-20 13:27:11 +0000 | ||
| 835 | @@ -17,5 +17,5 @@ | ||
| 836 | out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 837 | } | ||
| 838 | |||
| 839 | -/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 840 | +/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 841 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 842 | |||
| 843 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c' | ||
| 844 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c 2010-07-29 15:38:15 +0000 | ||
| 845 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c 2010-08-20 13:27:11 +0000 | ||
| 846 | @@ -17,5 +17,5 @@ | ||
| 847 | out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 848 | } | ||
| 849 | |||
| 850 | -/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 851 | +/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 852 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 853 | |||
| 854 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c' | ||
| 855 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c 2010-07-29 15:38:15 +0000 | ||
| 856 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c 2010-08-20 13:27:11 +0000 | ||
| 857 | @@ -17,5 +17,5 @@ | ||
| 858 | out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 859 | } | ||
| 860 | |||
| 861 | -/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 862 | +/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 863 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 864 | |||
| 865 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c' | ||
| 866 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c 2010-07-29 15:38:15 +0000 | ||
| 867 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c 2010-08-20 13:27:11 +0000 | ||
| 868 | @@ -17,5 +17,5 @@ | ||
| 869 | out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 870 | } | ||
| 871 | |||
| 872 | -/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 873 | +/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 874 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 875 | |||
| 876 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c' | ||
| 877 | --- old/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c 2010-07-29 15:38:15 +0000 | ||
| 878 | +++ new/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c 2010-08-20 13:27:11 +0000 | ||
| 879 | @@ -17,5 +17,5 @@ | ||
| 880 | out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 881 | } | ||
| 882 | |||
| 883 | -/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 884 | +/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 885 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 886 | |||
| 887 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQs16.c' | ||
| 888 | --- old/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c 2010-07-29 15:38:15 +0000 | ||
| 889 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c 2010-08-20 13:27:11 +0000 | ||
| 890 | @@ -18,5 +18,5 @@ | ||
| 891 | out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); | ||
| 892 | } | ||
| 893 | |||
| 894 | -/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 895 | +/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 896 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 897 | |||
| 898 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQs32.c' | ||
| 899 | --- old/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c 2010-07-29 15:38:15 +0000 | ||
| 900 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c 2010-08-20 13:27:11 +0000 | ||
| 901 | @@ -18,5 +18,5 @@ | ||
| 902 | out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); | ||
| 903 | } | ||
| 904 | |||
| 905 | -/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 906 | +/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 907 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 908 | |||
| 909 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQs8.c' | ||
| 910 | --- old/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c 2010-07-29 15:38:15 +0000 | ||
| 911 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c 2010-08-20 13:27:11 +0000 | ||
| 912 | @@ -18,5 +18,5 @@ | ||
| 913 | out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); | ||
| 914 | } | ||
| 915 | |||
| 916 | -/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 917 | +/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 918 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 919 | |||
| 920 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQu16.c' | ||
| 921 | --- old/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c 2010-07-29 15:38:15 +0000 | ||
| 922 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c 2010-08-20 13:27:11 +0000 | ||
| 923 | @@ -18,5 +18,5 @@ | ||
| 924 | out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); | ||
| 925 | } | ||
| 926 | |||
| 927 | -/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 928 | +/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 929 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 930 | |||
| 931 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQu32.c' | ||
| 932 | --- old/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c 2010-07-29 15:38:15 +0000 | ||
| 933 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c 2010-08-20 13:27:11 +0000 | ||
| 934 | @@ -18,5 +18,5 @@ | ||
| 935 | out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); | ||
| 936 | } | ||
| 937 | |||
| 938 | -/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 939 | +/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 940 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 941 | |||
| 942 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabaQu8.c' | ||
| 943 | --- old/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c 2010-07-29 15:38:15 +0000 | ||
| 944 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c 2010-08-20 13:27:11 +0000 | ||
| 945 | @@ -18,5 +18,5 @@ | ||
| 946 | out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); | ||
| 947 | } | ||
| 948 | |||
| 949 | -/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 950 | +/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 951 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 952 | |||
| 953 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabals16.c' | ||
| 954 | --- old/gcc/testsuite/gcc.target/arm/neon/vabals16.c 2010-07-29 15:38:15 +0000 | ||
| 955 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabals16.c 2010-08-20 13:27:11 +0000 | ||
| 956 | @@ -18,5 +18,5 @@ | ||
| 957 | out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); | ||
| 958 | } | ||
| 959 | |||
| 960 | -/* { dg-final { scan-assembler "vabal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 961 | +/* { dg-final { scan-assembler "vabal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 962 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 963 | |||
| 964 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabals32.c' | ||
| 965 | --- old/gcc/testsuite/gcc.target/arm/neon/vabals32.c 2010-07-29 15:38:15 +0000 | ||
| 966 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabals32.c 2010-08-20 13:27:11 +0000 | ||
| 967 | @@ -18,5 +18,5 @@ | ||
| 968 | out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); | ||
| 969 | } | ||
| 970 | |||
| 971 | -/* { dg-final { scan-assembler "vabal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 972 | +/* { dg-final { scan-assembler "vabal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 973 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 974 | |||
| 975 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabals8.c' | ||
| 976 | --- old/gcc/testsuite/gcc.target/arm/neon/vabals8.c 2010-07-29 15:38:15 +0000 | ||
| 977 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabals8.c 2010-08-20 13:27:11 +0000 | ||
| 978 | @@ -18,5 +18,5 @@ | ||
| 979 | out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); | ||
| 980 | } | ||
| 981 | |||
| 982 | -/* { dg-final { scan-assembler "vabal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 983 | +/* { dg-final { scan-assembler "vabal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 984 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 985 | |||
| 986 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabalu16.c' | ||
| 987 | --- old/gcc/testsuite/gcc.target/arm/neon/vabalu16.c 2010-07-29 15:38:15 +0000 | ||
| 988 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabalu16.c 2010-08-20 13:27:11 +0000 | ||
| 989 | @@ -18,5 +18,5 @@ | ||
| 990 | out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); | ||
| 991 | } | ||
| 992 | |||
| 993 | -/* { dg-final { scan-assembler "vabal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 994 | +/* { dg-final { scan-assembler "vabal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 995 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 996 | |||
| 997 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabalu32.c' | ||
| 998 | --- old/gcc/testsuite/gcc.target/arm/neon/vabalu32.c 2010-07-29 15:38:15 +0000 | ||
| 999 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabalu32.c 2010-08-20 13:27:11 +0000 | ||
| 1000 | @@ -18,5 +18,5 @@ | ||
| 1001 | out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); | ||
| 1002 | } | ||
| 1003 | |||
| 1004 | -/* { dg-final { scan-assembler "vabal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1005 | +/* { dg-final { scan-assembler "vabal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1006 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1007 | |||
| 1008 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabalu8.c' | ||
| 1009 | --- old/gcc/testsuite/gcc.target/arm/neon/vabalu8.c 2010-07-29 15:38:15 +0000 | ||
| 1010 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabalu8.c 2010-08-20 13:27:11 +0000 | ||
| 1011 | @@ -18,5 +18,5 @@ | ||
| 1012 | out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); | ||
| 1013 | } | ||
| 1014 | |||
| 1015 | -/* { dg-final { scan-assembler "vabal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1016 | +/* { dg-final { scan-assembler "vabal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1017 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1018 | |||
| 1019 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabas16.c' | ||
| 1020 | --- old/gcc/testsuite/gcc.target/arm/neon/vabas16.c 2010-07-29 15:38:15 +0000 | ||
| 1021 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabas16.c 2010-08-20 13:27:11 +0000 | ||
| 1022 | @@ -18,5 +18,5 @@ | ||
| 1023 | out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); | ||
| 1024 | } | ||
| 1025 | |||
| 1026 | -/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1027 | +/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1028 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1029 | |||
| 1030 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabas32.c' | ||
| 1031 | --- old/gcc/testsuite/gcc.target/arm/neon/vabas32.c 2010-07-29 15:38:15 +0000 | ||
| 1032 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabas32.c 2010-08-20 13:27:11 +0000 | ||
| 1033 | @@ -18,5 +18,5 @@ | ||
| 1034 | out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); | ||
| 1035 | } | ||
| 1036 | |||
| 1037 | -/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1038 | +/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1039 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1040 | |||
| 1041 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabas8.c' | ||
| 1042 | --- old/gcc/testsuite/gcc.target/arm/neon/vabas8.c 2010-07-29 15:38:15 +0000 | ||
| 1043 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabas8.c 2010-08-20 13:27:11 +0000 | ||
| 1044 | @@ -18,5 +18,5 @@ | ||
| 1045 | out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); | ||
| 1046 | } | ||
| 1047 | |||
| 1048 | -/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1049 | +/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1050 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1051 | |||
| 1052 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabau16.c' | ||
| 1053 | --- old/gcc/testsuite/gcc.target/arm/neon/vabau16.c 2010-07-29 15:38:15 +0000 | ||
| 1054 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabau16.c 2010-08-20 13:27:11 +0000 | ||
| 1055 | @@ -18,5 +18,5 @@ | ||
| 1056 | out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); | ||
| 1057 | } | ||
| 1058 | |||
| 1059 | -/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1060 | +/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1061 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1062 | |||
| 1063 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabau32.c' | ||
| 1064 | --- old/gcc/testsuite/gcc.target/arm/neon/vabau32.c 2010-07-29 15:38:15 +0000 | ||
| 1065 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabau32.c 2010-08-20 13:27:11 +0000 | ||
| 1066 | @@ -18,5 +18,5 @@ | ||
| 1067 | out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); | ||
| 1068 | } | ||
| 1069 | |||
| 1070 | -/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1071 | +/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1072 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1073 | |||
| 1074 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabau8.c' | ||
| 1075 | --- old/gcc/testsuite/gcc.target/arm/neon/vabau8.c 2010-07-29 15:38:15 +0000 | ||
| 1076 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabau8.c 2010-08-20 13:27:11 +0000 | ||
| 1077 | @@ -18,5 +18,5 @@ | ||
| 1078 | out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); | ||
| 1079 | } | ||
| 1080 | |||
| 1081 | -/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1082 | +/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1083 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1084 | |||
| 1085 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQf32.c' | ||
| 1086 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c 2010-07-29 15:38:15 +0000 | ||
| 1087 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c 2010-08-20 13:27:11 +0000 | ||
| 1088 | @@ -17,5 +17,5 @@ | ||
| 1089 | out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 1090 | } | ||
| 1091 | |||
| 1092 | -/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1093 | +/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1094 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1095 | |||
| 1096 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQs16.c' | ||
| 1097 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c 2010-07-29 15:38:15 +0000 | ||
| 1098 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c 2010-08-20 13:27:11 +0000 | ||
| 1099 | @@ -17,5 +17,5 @@ | ||
| 1100 | out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 1101 | } | ||
| 1102 | |||
| 1103 | -/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1104 | +/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1105 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1106 | |||
| 1107 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQs32.c' | ||
| 1108 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c 2010-07-29 15:38:15 +0000 | ||
| 1109 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c 2010-08-20 13:27:11 +0000 | ||
| 1110 | @@ -17,5 +17,5 @@ | ||
| 1111 | out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 1112 | } | ||
| 1113 | |||
| 1114 | -/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1115 | +/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1116 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1117 | |||
| 1118 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQs8.c' | ||
| 1119 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c 2010-07-29 15:38:15 +0000 | ||
| 1120 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c 2010-08-20 13:27:11 +0000 | ||
| 1121 | @@ -17,5 +17,5 @@ | ||
| 1122 | out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 1123 | } | ||
| 1124 | |||
| 1125 | -/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1126 | +/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1127 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1128 | |||
| 1129 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQu16.c' | ||
| 1130 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c 2010-07-29 15:38:15 +0000 | ||
| 1131 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c 2010-08-20 13:27:11 +0000 | ||
| 1132 | @@ -17,5 +17,5 @@ | ||
| 1133 | out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 1134 | } | ||
| 1135 | |||
| 1136 | -/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1137 | +/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1138 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1139 | |||
| 1140 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQu32.c' | ||
| 1141 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c 2010-07-29 15:38:15 +0000 | ||
| 1142 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c 2010-08-20 13:27:11 +0000 | ||
| 1143 | @@ -17,5 +17,5 @@ | ||
| 1144 | out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 1145 | } | ||
| 1146 | |||
| 1147 | -/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1148 | +/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1149 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1150 | |||
| 1151 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdQu8.c' | ||
| 1152 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c 2010-07-29 15:38:15 +0000 | ||
| 1153 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c 2010-08-20 13:27:11 +0000 | ||
| 1154 | @@ -17,5 +17,5 @@ | ||
| 1155 | out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 1156 | } | ||
| 1157 | |||
| 1158 | -/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1159 | +/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1160 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1161 | |||
| 1162 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdf32.c' | ||
| 1163 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdf32.c 2010-07-29 15:38:15 +0000 | ||
| 1164 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdf32.c 2010-08-20 13:27:11 +0000 | ||
| 1165 | @@ -17,5 +17,5 @@ | ||
| 1166 | out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 1167 | } | ||
| 1168 | |||
| 1169 | -/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1170 | +/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1171 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1172 | |||
| 1173 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdls16.c' | ||
| 1174 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdls16.c 2010-07-29 15:38:15 +0000 | ||
| 1175 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdls16.c 2010-08-20 13:27:11 +0000 | ||
| 1176 | @@ -17,5 +17,5 @@ | ||
| 1177 | out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 1178 | } | ||
| 1179 | |||
| 1180 | -/* { dg-final { scan-assembler "vabdl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1181 | +/* { dg-final { scan-assembler "vabdl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1182 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1183 | |||
| 1184 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdls32.c' | ||
| 1185 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdls32.c 2010-07-29 15:38:15 +0000 | ||
| 1186 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdls32.c 2010-08-20 13:27:11 +0000 | ||
| 1187 | @@ -17,5 +17,5 @@ | ||
| 1188 | out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 1189 | } | ||
| 1190 | |||
| 1191 | -/* { dg-final { scan-assembler "vabdl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1192 | +/* { dg-final { scan-assembler "vabdl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1193 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1194 | |||
| 1195 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdls8.c' | ||
| 1196 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdls8.c 2010-07-29 15:38:15 +0000 | ||
| 1197 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdls8.c 2010-08-20 13:27:11 +0000 | ||
| 1198 | @@ -17,5 +17,5 @@ | ||
| 1199 | out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 1200 | } | ||
| 1201 | |||
| 1202 | -/* { dg-final { scan-assembler "vabdl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1203 | +/* { dg-final { scan-assembler "vabdl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1204 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1205 | |||
| 1206 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdlu16.c' | ||
| 1207 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c 2010-07-29 15:38:15 +0000 | ||
| 1208 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c 2010-08-20 13:27:11 +0000 | ||
| 1209 | @@ -17,5 +17,5 @@ | ||
| 1210 | out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 1211 | } | ||
| 1212 | |||
| 1213 | -/* { dg-final { scan-assembler "vabdl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1214 | +/* { dg-final { scan-assembler "vabdl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1215 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1216 | |||
| 1217 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdlu32.c' | ||
| 1218 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c 2010-07-29 15:38:15 +0000 | ||
| 1219 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c 2010-08-20 13:27:11 +0000 | ||
| 1220 | @@ -17,5 +17,5 @@ | ||
| 1221 | out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 1222 | } | ||
| 1223 | |||
| 1224 | -/* { dg-final { scan-assembler "vabdl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1225 | +/* { dg-final { scan-assembler "vabdl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1226 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1227 | |||
| 1228 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdlu8.c' | ||
| 1229 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c 2010-07-29 15:38:15 +0000 | ||
| 1230 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c 2010-08-20 13:27:11 +0000 | ||
| 1231 | @@ -17,5 +17,5 @@ | ||
| 1232 | out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 1233 | } | ||
| 1234 | |||
| 1235 | -/* { dg-final { scan-assembler "vabdl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1236 | +/* { dg-final { scan-assembler "vabdl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1237 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1238 | |||
| 1239 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabds16.c' | ||
| 1240 | --- old/gcc/testsuite/gcc.target/arm/neon/vabds16.c 2010-07-29 15:38:15 +0000 | ||
| 1241 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabds16.c 2010-08-20 13:27:11 +0000 | ||
| 1242 | @@ -17,5 +17,5 @@ | ||
| 1243 | out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 1244 | } | ||
| 1245 | |||
| 1246 | -/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1247 | +/* { dg-final { scan-assembler "vabd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1248 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1249 | |||
| 1250 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabds32.c' | ||
| 1251 | --- old/gcc/testsuite/gcc.target/arm/neon/vabds32.c 2010-07-29 15:38:15 +0000 | ||
| 1252 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabds32.c 2010-08-20 13:27:11 +0000 | ||
| 1253 | @@ -17,5 +17,5 @@ | ||
| 1254 | out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 1255 | } | ||
| 1256 | |||
| 1257 | -/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1258 | +/* { dg-final { scan-assembler "vabd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1259 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1260 | |||
| 1261 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabds8.c' | ||
| 1262 | --- old/gcc/testsuite/gcc.target/arm/neon/vabds8.c 2010-07-29 15:38:15 +0000 | ||
| 1263 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabds8.c 2010-08-20 13:27:11 +0000 | ||
| 1264 | @@ -17,5 +17,5 @@ | ||
| 1265 | out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 1266 | } | ||
| 1267 | |||
| 1268 | -/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1269 | +/* { dg-final { scan-assembler "vabd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1270 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1271 | |||
| 1272 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdu16.c' | ||
| 1273 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdu16.c 2010-07-29 15:38:15 +0000 | ||
| 1274 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdu16.c 2010-08-20 13:27:11 +0000 | ||
| 1275 | @@ -17,5 +17,5 @@ | ||
| 1276 | out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 1277 | } | ||
| 1278 | |||
| 1279 | -/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1280 | +/* { dg-final { scan-assembler "vabd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1281 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1282 | |||
| 1283 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdu32.c' | ||
| 1284 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdu32.c 2010-07-29 15:38:15 +0000 | ||
| 1285 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdu32.c 2010-08-20 13:27:11 +0000 | ||
| 1286 | @@ -17,5 +17,5 @@ | ||
| 1287 | out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 1288 | } | ||
| 1289 | |||
| 1290 | -/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1291 | +/* { dg-final { scan-assembler "vabd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1292 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1293 | |||
| 1294 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabdu8.c' | ||
| 1295 | --- old/gcc/testsuite/gcc.target/arm/neon/vabdu8.c 2010-07-29 15:38:15 +0000 | ||
| 1296 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabdu8.c 2010-08-20 13:27:11 +0000 | ||
| 1297 | @@ -17,5 +17,5 @@ | ||
| 1298 | out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 1299 | } | ||
| 1300 | |||
| 1301 | -/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1302 | +/* { dg-final { scan-assembler "vabd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1303 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1304 | |||
| 1305 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQf32.c' | ||
| 1306 | --- old/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c 2010-07-29 15:38:15 +0000 | ||
| 1307 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c 2010-08-20 13:27:11 +0000 | ||
| 1308 | @@ -16,5 +16,5 @@ | ||
| 1309 | out_float32x4_t = vabsq_f32 (arg0_float32x4_t); | ||
| 1310 | } | ||
| 1311 | |||
| 1312 | -/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1313 | +/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1314 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1315 | |||
| 1316 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQs16.c' | ||
| 1317 | --- old/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c 2010-07-29 15:38:15 +0000 | ||
| 1318 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c 2010-08-20 13:27:11 +0000 | ||
| 1319 | @@ -16,5 +16,5 @@ | ||
| 1320 | out_int16x8_t = vabsq_s16 (arg0_int16x8_t); | ||
| 1321 | } | ||
| 1322 | |||
| 1323 | -/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1324 | +/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1325 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1326 | |||
| 1327 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQs32.c' | ||
| 1328 | --- old/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c 2010-07-29 15:38:15 +0000 | ||
| 1329 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c 2010-08-20 13:27:11 +0000 | ||
| 1330 | @@ -16,5 +16,5 @@ | ||
| 1331 | out_int32x4_t = vabsq_s32 (arg0_int32x4_t); | ||
| 1332 | } | ||
| 1333 | |||
| 1334 | -/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1335 | +/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1336 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1337 | |||
| 1338 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabsQs8.c' | ||
| 1339 | --- old/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c 2010-07-29 15:38:15 +0000 | ||
| 1340 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c 2010-08-20 13:27:11 +0000 | ||
| 1341 | @@ -16,5 +16,5 @@ | ||
| 1342 | out_int8x16_t = vabsq_s8 (arg0_int8x16_t); | ||
| 1343 | } | ||
| 1344 | |||
| 1345 | -/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1346 | +/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1347 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1348 | |||
| 1349 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabsf32.c' | ||
| 1350 | --- old/gcc/testsuite/gcc.target/arm/neon/vabsf32.c 2010-07-29 15:38:15 +0000 | ||
| 1351 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabsf32.c 2010-08-20 13:27:11 +0000 | ||
| 1352 | @@ -16,5 +16,5 @@ | ||
| 1353 | out_float32x2_t = vabs_f32 (arg0_float32x2_t); | ||
| 1354 | } | ||
| 1355 | |||
| 1356 | -/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1357 | +/* { dg-final { scan-assembler "vabs\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1358 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1359 | |||
| 1360 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabss16.c' | ||
| 1361 | --- old/gcc/testsuite/gcc.target/arm/neon/vabss16.c 2010-07-29 15:38:15 +0000 | ||
| 1362 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabss16.c 2010-08-20 13:27:11 +0000 | ||
| 1363 | @@ -16,5 +16,5 @@ | ||
| 1364 | out_int16x4_t = vabs_s16 (arg0_int16x4_t); | ||
| 1365 | } | ||
| 1366 | |||
| 1367 | -/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1368 | +/* { dg-final { scan-assembler "vabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1369 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1370 | |||
| 1371 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabss32.c' | ||
| 1372 | --- old/gcc/testsuite/gcc.target/arm/neon/vabss32.c 2010-07-29 15:38:15 +0000 | ||
| 1373 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabss32.c 2010-08-20 13:27:11 +0000 | ||
| 1374 | @@ -16,5 +16,5 @@ | ||
| 1375 | out_int32x2_t = vabs_s32 (arg0_int32x2_t); | ||
| 1376 | } | ||
| 1377 | |||
| 1378 | -/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1379 | +/* { dg-final { scan-assembler "vabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1380 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1381 | |||
| 1382 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vabss8.c' | ||
| 1383 | --- old/gcc/testsuite/gcc.target/arm/neon/vabss8.c 2010-07-29 15:38:15 +0000 | ||
| 1384 | +++ new/gcc/testsuite/gcc.target/arm/neon/vabss8.c 2010-08-20 13:27:11 +0000 | ||
| 1385 | @@ -16,5 +16,5 @@ | ||
| 1386 | out_int8x8_t = vabs_s8 (arg0_int8x8_t); | ||
| 1387 | } | ||
| 1388 | |||
| 1389 | -/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1390 | +/* { dg-final { scan-assembler "vabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1391 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1392 | |||
| 1393 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQf32.c' | ||
| 1394 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c 2010-07-29 15:38:15 +0000 | ||
| 1395 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c 2010-08-20 13:27:11 +0000 | ||
| 1396 | @@ -17,5 +17,5 @@ | ||
| 1397 | out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 1398 | } | ||
| 1399 | |||
| 1400 | -/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1401 | +/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1402 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1403 | |||
| 1404 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs16.c' | ||
| 1405 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c 2010-07-29 15:38:15 +0000 | ||
| 1406 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c 2010-08-20 13:27:11 +0000 | ||
| 1407 | @@ -17,5 +17,5 @@ | ||
| 1408 | out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 1409 | } | ||
| 1410 | |||
| 1411 | -/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1412 | +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1413 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1414 | |||
| 1415 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs32.c' | ||
| 1416 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c 2010-07-29 15:38:15 +0000 | ||
| 1417 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c 2010-08-20 13:27:11 +0000 | ||
| 1418 | @@ -17,5 +17,5 @@ | ||
| 1419 | out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 1420 | } | ||
| 1421 | |||
| 1422 | -/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1423 | +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1424 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1425 | |||
| 1426 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs64.c' | ||
| 1427 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c 2010-07-29 15:38:15 +0000 | ||
| 1428 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c 2010-08-20 13:27:11 +0000 | ||
| 1429 | @@ -17,5 +17,5 @@ | ||
| 1430 | out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 1431 | } | ||
| 1432 | |||
| 1433 | -/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1434 | +/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1435 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1436 | |||
| 1437 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQs8.c' | ||
| 1438 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c 2010-07-29 15:38:15 +0000 | ||
| 1439 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c 2010-08-20 13:27:11 +0000 | ||
| 1440 | @@ -17,5 +17,5 @@ | ||
| 1441 | out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 1442 | } | ||
| 1443 | |||
| 1444 | -/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1445 | +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1446 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1447 | |||
| 1448 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu16.c' | ||
| 1449 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c 2010-07-29 15:38:15 +0000 | ||
| 1450 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c 2010-08-20 13:27:11 +0000 | ||
| 1451 | @@ -17,5 +17,5 @@ | ||
| 1452 | out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 1453 | } | ||
| 1454 | |||
| 1455 | -/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1456 | +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1457 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1458 | |||
| 1459 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu32.c' | ||
| 1460 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c 2010-07-29 15:38:15 +0000 | ||
| 1461 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c 2010-08-20 13:27:11 +0000 | ||
| 1462 | @@ -17,5 +17,5 @@ | ||
| 1463 | out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 1464 | } | ||
| 1465 | |||
| 1466 | -/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1467 | +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1468 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1469 | |||
| 1470 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu64.c' | ||
| 1471 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c 2010-07-29 15:38:15 +0000 | ||
| 1472 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c 2010-08-20 13:27:11 +0000 | ||
| 1473 | @@ -17,5 +17,5 @@ | ||
| 1474 | out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 1475 | } | ||
| 1476 | |||
| 1477 | -/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1478 | +/* { dg-final { scan-assembler "vadd\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1479 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1480 | |||
| 1481 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddQu8.c' | ||
| 1482 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c 2010-07-29 15:38:15 +0000 | ||
| 1483 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c 2010-08-20 13:27:11 +0000 | ||
| 1484 | @@ -17,5 +17,5 @@ | ||
| 1485 | out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 1486 | } | ||
| 1487 | |||
| 1488 | -/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1489 | +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1490 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1491 | |||
| 1492 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddf32.c' | ||
| 1493 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddf32.c 2010-07-29 15:38:15 +0000 | ||
| 1494 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddf32.c 2010-08-20 13:27:11 +0000 | ||
| 1495 | @@ -17,5 +17,5 @@ | ||
| 1496 | out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 1497 | } | ||
| 1498 | |||
| 1499 | -/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1500 | +/* { dg-final { scan-assembler "vadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1501 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1502 | |||
| 1503 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhns16.c' | ||
| 1504 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c 2010-07-29 15:38:15 +0000 | ||
| 1505 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c 2010-08-20 13:27:11 +0000 | ||
| 1506 | @@ -17,5 +17,5 @@ | ||
| 1507 | out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 1508 | } | ||
| 1509 | |||
| 1510 | -/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1511 | +/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1512 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1513 | |||
| 1514 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhns32.c' | ||
| 1515 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c 2010-07-29 15:38:15 +0000 | ||
| 1516 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c 2010-08-20 13:27:11 +0000 | ||
| 1517 | @@ -17,5 +17,5 @@ | ||
| 1518 | out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 1519 | } | ||
| 1520 | |||
| 1521 | -/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1522 | +/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1523 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1524 | |||
| 1525 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhns64.c' | ||
| 1526 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c 2010-07-29 15:38:15 +0000 | ||
| 1527 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c 2010-08-20 13:27:11 +0000 | ||
| 1528 | @@ -17,5 +17,5 @@ | ||
| 1529 | out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 1530 | } | ||
| 1531 | |||
| 1532 | -/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1533 | +/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1534 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1535 | |||
| 1536 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c' | ||
| 1537 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c 2010-07-29 15:38:15 +0000 | ||
| 1538 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c 2010-08-20 13:27:11 +0000 | ||
| 1539 | @@ -17,5 +17,5 @@ | ||
| 1540 | out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 1541 | } | ||
| 1542 | |||
| 1543 | -/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1544 | +/* { dg-final { scan-assembler "vaddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1545 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1546 | |||
| 1547 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c' | ||
| 1548 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c 2010-07-29 15:38:15 +0000 | ||
| 1549 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c 2010-08-20 13:27:11 +0000 | ||
| 1550 | @@ -17,5 +17,5 @@ | ||
| 1551 | out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 1552 | } | ||
| 1553 | |||
| 1554 | -/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1555 | +/* { dg-final { scan-assembler "vaddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1556 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1557 | |||
| 1558 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c' | ||
| 1559 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c 2010-07-29 15:38:15 +0000 | ||
| 1560 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c 2010-08-20 13:27:11 +0000 | ||
| 1561 | @@ -17,5 +17,5 @@ | ||
| 1562 | out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 1563 | } | ||
| 1564 | |||
| 1565 | -/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1566 | +/* { dg-final { scan-assembler "vaddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1567 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1568 | |||
| 1569 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddls16.c' | ||
| 1570 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddls16.c 2010-07-29 15:38:15 +0000 | ||
| 1571 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddls16.c 2010-08-20 13:27:11 +0000 | ||
| 1572 | @@ -17,5 +17,5 @@ | ||
| 1573 | out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 1574 | } | ||
| 1575 | |||
| 1576 | -/* { dg-final { scan-assembler "vaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1577 | +/* { dg-final { scan-assembler "vaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1578 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1579 | |||
| 1580 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddls32.c' | ||
| 1581 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddls32.c 2010-07-29 15:38:15 +0000 | ||
| 1582 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddls32.c 2010-08-20 13:27:11 +0000 | ||
| 1583 | @@ -17,5 +17,5 @@ | ||
| 1584 | out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 1585 | } | ||
| 1586 | |||
| 1587 | -/* { dg-final { scan-assembler "vaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1588 | +/* { dg-final { scan-assembler "vaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1589 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1590 | |||
| 1591 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddls8.c' | ||
| 1592 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddls8.c 2010-07-29 15:38:15 +0000 | ||
| 1593 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddls8.c 2010-08-20 13:27:11 +0000 | ||
| 1594 | @@ -17,5 +17,5 @@ | ||
| 1595 | out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 1596 | } | ||
| 1597 | |||
| 1598 | -/* { dg-final { scan-assembler "vaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1599 | +/* { dg-final { scan-assembler "vaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1600 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1601 | |||
| 1602 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddlu16.c' | ||
| 1603 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c 2010-07-29 15:38:15 +0000 | ||
| 1604 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c 2010-08-20 13:27:11 +0000 | ||
| 1605 | @@ -17,5 +17,5 @@ | ||
| 1606 | out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 1607 | } | ||
| 1608 | |||
| 1609 | -/* { dg-final { scan-assembler "vaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1610 | +/* { dg-final { scan-assembler "vaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1611 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1612 | |||
| 1613 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddlu32.c' | ||
| 1614 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c 2010-07-29 15:38:15 +0000 | ||
| 1615 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c 2010-08-20 13:27:11 +0000 | ||
| 1616 | @@ -17,5 +17,5 @@ | ||
| 1617 | out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 1618 | } | ||
| 1619 | |||
| 1620 | -/* { dg-final { scan-assembler "vaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1621 | +/* { dg-final { scan-assembler "vaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1622 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1623 | |||
| 1624 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddlu8.c' | ||
| 1625 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c 2010-07-29 15:38:15 +0000 | ||
| 1626 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c 2010-08-20 13:27:11 +0000 | ||
| 1627 | @@ -17,5 +17,5 @@ | ||
| 1628 | out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 1629 | } | ||
| 1630 | |||
| 1631 | -/* { dg-final { scan-assembler "vaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1632 | +/* { dg-final { scan-assembler "vaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1633 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1634 | |||
| 1635 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vadds16.c' | ||
| 1636 | --- old/gcc/testsuite/gcc.target/arm/neon/vadds16.c 2010-07-29 15:38:15 +0000 | ||
| 1637 | +++ new/gcc/testsuite/gcc.target/arm/neon/vadds16.c 2010-08-20 13:27:11 +0000 | ||
| 1638 | @@ -17,5 +17,5 @@ | ||
| 1639 | out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 1640 | } | ||
| 1641 | |||
| 1642 | -/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1643 | +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1644 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1645 | |||
| 1646 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vadds32.c' | ||
| 1647 | --- old/gcc/testsuite/gcc.target/arm/neon/vadds32.c 2010-07-29 15:38:15 +0000 | ||
| 1648 | +++ new/gcc/testsuite/gcc.target/arm/neon/vadds32.c 2010-08-20 13:27:11 +0000 | ||
| 1649 | @@ -17,5 +17,5 @@ | ||
| 1650 | out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 1651 | } | ||
| 1652 | |||
| 1653 | -/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1654 | +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1655 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1656 | |||
| 1657 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vadds8.c' | ||
| 1658 | --- old/gcc/testsuite/gcc.target/arm/neon/vadds8.c 2010-07-29 15:38:15 +0000 | ||
| 1659 | +++ new/gcc/testsuite/gcc.target/arm/neon/vadds8.c 2010-08-20 13:27:11 +0000 | ||
| 1660 | @@ -17,5 +17,5 @@ | ||
| 1661 | out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 1662 | } | ||
| 1663 | |||
| 1664 | -/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1665 | +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1666 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1667 | |||
| 1668 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu16.c' | ||
| 1669 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddu16.c 2010-07-29 15:38:15 +0000 | ||
| 1670 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddu16.c 2010-08-20 13:27:11 +0000 | ||
| 1671 | @@ -17,5 +17,5 @@ | ||
| 1672 | out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 1673 | } | ||
| 1674 | |||
| 1675 | -/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1676 | +/* { dg-final { scan-assembler "vadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1677 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1678 | |||
| 1679 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu32.c' | ||
| 1680 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddu32.c 2010-07-29 15:38:15 +0000 | ||
| 1681 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddu32.c 2010-08-20 13:27:11 +0000 | ||
| 1682 | @@ -17,5 +17,5 @@ | ||
| 1683 | out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 1684 | } | ||
| 1685 | |||
| 1686 | -/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1687 | +/* { dg-final { scan-assembler "vadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1688 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1689 | |||
| 1690 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddu8.c' | ||
| 1691 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddu8.c 2010-07-29 15:38:15 +0000 | ||
| 1692 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddu8.c 2010-08-20 13:27:11 +0000 | ||
| 1693 | @@ -17,5 +17,5 @@ | ||
| 1694 | out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 1695 | } | ||
| 1696 | |||
| 1697 | -/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1698 | +/* { dg-final { scan-assembler "vadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1699 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1700 | |||
| 1701 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddws16.c' | ||
| 1702 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddws16.c 2010-07-29 15:38:15 +0000 | ||
| 1703 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddws16.c 2010-08-20 13:27:11 +0000 | ||
| 1704 | @@ -17,5 +17,5 @@ | ||
| 1705 | out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t); | ||
| 1706 | } | ||
| 1707 | |||
| 1708 | -/* { dg-final { scan-assembler "vaddw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1709 | +/* { dg-final { scan-assembler "vaddw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1710 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1711 | |||
| 1712 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddws32.c' | ||
| 1713 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddws32.c 2010-07-29 15:38:15 +0000 | ||
| 1714 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddws32.c 2010-08-20 13:27:11 +0000 | ||
| 1715 | @@ -17,5 +17,5 @@ | ||
| 1716 | out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t); | ||
| 1717 | } | ||
| 1718 | |||
| 1719 | -/* { dg-final { scan-assembler "vaddw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1720 | +/* { dg-final { scan-assembler "vaddw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1721 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1722 | |||
| 1723 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddws8.c' | ||
| 1724 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddws8.c 2010-07-29 15:38:15 +0000 | ||
| 1725 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddws8.c 2010-08-20 13:27:11 +0000 | ||
| 1726 | @@ -17,5 +17,5 @@ | ||
| 1727 | out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t); | ||
| 1728 | } | ||
| 1729 | |||
| 1730 | -/* { dg-final { scan-assembler "vaddw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1731 | +/* { dg-final { scan-assembler "vaddw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1732 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1733 | |||
| 1734 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddwu16.c' | ||
| 1735 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c 2010-07-29 15:38:15 +0000 | ||
| 1736 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c 2010-08-20 13:27:11 +0000 | ||
| 1737 | @@ -17,5 +17,5 @@ | ||
| 1738 | out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t); | ||
| 1739 | } | ||
| 1740 | |||
| 1741 | -/* { dg-final { scan-assembler "vaddw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1742 | +/* { dg-final { scan-assembler "vaddw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1743 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1744 | |||
| 1745 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddwu32.c' | ||
| 1746 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c 2010-07-29 15:38:15 +0000 | ||
| 1747 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c 2010-08-20 13:27:11 +0000 | ||
| 1748 | @@ -17,5 +17,5 @@ | ||
| 1749 | out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t); | ||
| 1750 | } | ||
| 1751 | |||
| 1752 | -/* { dg-final { scan-assembler "vaddw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1753 | +/* { dg-final { scan-assembler "vaddw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1754 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1755 | |||
| 1756 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vaddwu8.c' | ||
| 1757 | --- old/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c 2010-07-29 15:38:15 +0000 | ||
| 1758 | +++ new/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c 2010-08-20 13:27:11 +0000 | ||
| 1759 | @@ -17,5 +17,5 @@ | ||
| 1760 | out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t); | ||
| 1761 | } | ||
| 1762 | |||
| 1763 | -/* { dg-final { scan-assembler "vaddw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1764 | +/* { dg-final { scan-assembler "vaddw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1765 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1766 | |||
| 1767 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs16.c' | ||
| 1768 | --- old/gcc/testsuite/gcc.target/arm/neon/vandQs16.c 2010-07-29 15:38:15 +0000 | ||
| 1769 | +++ new/gcc/testsuite/gcc.target/arm/neon/vandQs16.c 2010-08-20 13:27:11 +0000 | ||
| 1770 | @@ -17,5 +17,5 @@ | ||
| 1771 | out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 1772 | } | ||
| 1773 | |||
| 1774 | -/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1775 | +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1776 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1777 | |||
| 1778 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs32.c' | ||
| 1779 | --- old/gcc/testsuite/gcc.target/arm/neon/vandQs32.c 2010-07-29 15:38:15 +0000 | ||
| 1780 | +++ new/gcc/testsuite/gcc.target/arm/neon/vandQs32.c 2010-08-20 13:27:11 +0000 | ||
| 1781 | @@ -17,5 +17,5 @@ | ||
| 1782 | out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 1783 | } | ||
| 1784 | |||
| 1785 | -/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1786 | +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1787 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1788 | |||
| 1789 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs64.c' | ||
| 1790 | --- old/gcc/testsuite/gcc.target/arm/neon/vandQs64.c 2010-07-29 15:38:15 +0000 | ||
| 1791 | +++ new/gcc/testsuite/gcc.target/arm/neon/vandQs64.c 2010-08-20 13:27:11 +0000 | ||
| 1792 | @@ -17,5 +17,5 @@ | ||
| 1793 | out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 1794 | } | ||
| 1795 | |||
| 1796 | -/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1797 | +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1798 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1799 | |||
| 1800 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vandQs8.c' | ||
| 1801 | --- old/gcc/testsuite/gcc.target/arm/neon/vandQs8.c 2010-07-29 15:38:15 +0000 | ||
| 1802 | +++ new/gcc/testsuite/gcc.target/arm/neon/vandQs8.c 2010-08-20 13:27:11 +0000 | ||
| 1803 | @@ -17,5 +17,5 @@ | ||
| 1804 | out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 1805 | } | ||
| 1806 | |||
| 1807 | -/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1808 | +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1809 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1810 | |||
| 1811 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu16.c' | ||
| 1812 | --- old/gcc/testsuite/gcc.target/arm/neon/vandQu16.c 2010-07-29 15:38:15 +0000 | ||
| 1813 | +++ new/gcc/testsuite/gcc.target/arm/neon/vandQu16.c 2010-08-20 13:27:11 +0000 | ||
| 1814 | @@ -17,5 +17,5 @@ | ||
| 1815 | out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 1816 | } | ||
| 1817 | |||
| 1818 | -/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1819 | +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1820 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1821 | |||
| 1822 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu32.c' | ||
| 1823 | --- old/gcc/testsuite/gcc.target/arm/neon/vandQu32.c 2010-07-29 15:38:15 +0000 | ||
| 1824 | +++ new/gcc/testsuite/gcc.target/arm/neon/vandQu32.c 2010-08-20 13:27:11 +0000 | ||
| 1825 | @@ -17,5 +17,5 @@ | ||
| 1826 | out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 1827 | } | ||
| 1828 | |||
| 1829 | -/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1830 | +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1831 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1832 | |||
| 1833 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu64.c' | ||
| 1834 | --- old/gcc/testsuite/gcc.target/arm/neon/vandQu64.c 2010-07-29 15:38:15 +0000 | ||
| 1835 | +++ new/gcc/testsuite/gcc.target/arm/neon/vandQu64.c 2010-08-20 13:27:11 +0000 | ||
| 1836 | @@ -17,5 +17,5 @@ | ||
| 1837 | out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 1838 | } | ||
| 1839 | |||
| 1840 | -/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1841 | +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1842 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1843 | |||
| 1844 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vandQu8.c' | ||
| 1845 | --- old/gcc/testsuite/gcc.target/arm/neon/vandQu8.c 2010-07-29 15:38:15 +0000 | ||
| 1846 | +++ new/gcc/testsuite/gcc.target/arm/neon/vandQu8.c 2010-08-20 13:27:11 +0000 | ||
| 1847 | @@ -17,5 +17,5 @@ | ||
| 1848 | out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 1849 | } | ||
| 1850 | |||
| 1851 | -/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1852 | +/* { dg-final { scan-assembler "vand\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1853 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1854 | |||
| 1855 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vands16.c' | ||
| 1856 | --- old/gcc/testsuite/gcc.target/arm/neon/vands16.c 2010-07-29 15:38:15 +0000 | ||
| 1857 | +++ new/gcc/testsuite/gcc.target/arm/neon/vands16.c 2010-08-20 13:27:11 +0000 | ||
| 1858 | @@ -17,5 +17,5 @@ | ||
| 1859 | out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 1860 | } | ||
| 1861 | |||
| 1862 | -/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1863 | +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1864 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1865 | |||
| 1866 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vands32.c' | ||
| 1867 | --- old/gcc/testsuite/gcc.target/arm/neon/vands32.c 2010-07-29 15:38:15 +0000 | ||
| 1868 | +++ new/gcc/testsuite/gcc.target/arm/neon/vands32.c 2010-08-20 13:27:11 +0000 | ||
| 1869 | @@ -17,5 +17,5 @@ | ||
| 1870 | out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 1871 | } | ||
| 1872 | |||
| 1873 | -/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1874 | +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1875 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1876 | |||
| 1877 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vands8.c' | ||
| 1878 | --- old/gcc/testsuite/gcc.target/arm/neon/vands8.c 2010-07-29 15:38:15 +0000 | ||
| 1879 | +++ new/gcc/testsuite/gcc.target/arm/neon/vands8.c 2010-08-20 13:27:11 +0000 | ||
| 1880 | @@ -17,5 +17,5 @@ | ||
| 1881 | out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 1882 | } | ||
| 1883 | |||
| 1884 | -/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1885 | +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1886 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1887 | |||
| 1888 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vandu16.c' | ||
| 1889 | --- old/gcc/testsuite/gcc.target/arm/neon/vandu16.c 2010-07-29 15:38:15 +0000 | ||
| 1890 | +++ new/gcc/testsuite/gcc.target/arm/neon/vandu16.c 2010-08-20 13:27:11 +0000 | ||
| 1891 | @@ -17,5 +17,5 @@ | ||
| 1892 | out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 1893 | } | ||
| 1894 | |||
| 1895 | -/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1896 | +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1897 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1898 | |||
| 1899 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vandu32.c' | ||
| 1900 | --- old/gcc/testsuite/gcc.target/arm/neon/vandu32.c 2010-07-29 15:38:15 +0000 | ||
| 1901 | +++ new/gcc/testsuite/gcc.target/arm/neon/vandu32.c 2010-08-20 13:27:11 +0000 | ||
| 1902 | @@ -17,5 +17,5 @@ | ||
| 1903 | out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 1904 | } | ||
| 1905 | |||
| 1906 | -/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1907 | +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1908 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1909 | |||
| 1910 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vandu8.c' | ||
| 1911 | --- old/gcc/testsuite/gcc.target/arm/neon/vandu8.c 2010-07-29 15:38:15 +0000 | ||
| 1912 | +++ new/gcc/testsuite/gcc.target/arm/neon/vandu8.c 2010-08-20 13:27:11 +0000 | ||
| 1913 | @@ -17,5 +17,5 @@ | ||
| 1914 | out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 1915 | } | ||
| 1916 | |||
| 1917 | -/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1918 | +/* { dg-final { scan-assembler "vand\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1919 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1920 | |||
| 1921 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs16.c' | ||
| 1922 | --- old/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c 2010-07-29 15:38:15 +0000 | ||
| 1923 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c 2010-08-20 13:27:11 +0000 | ||
| 1924 | @@ -17,5 +17,5 @@ | ||
| 1925 | out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 1926 | } | ||
| 1927 | |||
| 1928 | -/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1929 | +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1930 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1931 | |||
| 1932 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs32.c' | ||
| 1933 | --- old/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c 2010-07-29 15:38:15 +0000 | ||
| 1934 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c 2010-08-20 13:27:11 +0000 | ||
| 1935 | @@ -17,5 +17,5 @@ | ||
| 1936 | out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 1937 | } | ||
| 1938 | |||
| 1939 | -/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1940 | +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1941 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1942 | |||
| 1943 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs64.c' | ||
| 1944 | --- old/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c 2010-07-29 15:38:15 +0000 | ||
| 1945 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c 2010-08-20 13:27:11 +0000 | ||
| 1946 | @@ -17,5 +17,5 @@ | ||
| 1947 | out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 1948 | } | ||
| 1949 | |||
| 1950 | -/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1951 | +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1952 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1953 | |||
| 1954 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQs8.c' | ||
| 1955 | --- old/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c 2010-07-29 15:38:15 +0000 | ||
| 1956 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c 2010-08-20 13:27:11 +0000 | ||
| 1957 | @@ -17,5 +17,5 @@ | ||
| 1958 | out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 1959 | } | ||
| 1960 | |||
| 1961 | -/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1962 | +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1963 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1964 | |||
| 1965 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu16.c' | ||
| 1966 | --- old/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c 2010-07-29 15:38:15 +0000 | ||
| 1967 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c 2010-08-20 13:27:11 +0000 | ||
| 1968 | @@ -17,5 +17,5 @@ | ||
| 1969 | out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 1970 | } | ||
| 1971 | |||
| 1972 | -/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1973 | +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1974 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1975 | |||
| 1976 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu32.c' | ||
| 1977 | --- old/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c 2010-07-29 15:38:15 +0000 | ||
| 1978 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c 2010-08-20 13:27:11 +0000 | ||
| 1979 | @@ -17,5 +17,5 @@ | ||
| 1980 | out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 1981 | } | ||
| 1982 | |||
| 1983 | -/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1984 | +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1985 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1986 | |||
| 1987 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu64.c' | ||
| 1988 | --- old/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c 2010-07-29 15:38:15 +0000 | ||
| 1989 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c 2010-08-20 13:27:11 +0000 | ||
| 1990 | @@ -17,5 +17,5 @@ | ||
| 1991 | out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 1992 | } | ||
| 1993 | |||
| 1994 | -/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 1995 | +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 1996 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 1997 | |||
| 1998 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbicQu8.c' | ||
| 1999 | --- old/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c 2010-07-29 15:38:15 +0000 | ||
| 2000 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c 2010-08-20 13:27:11 +0000 | ||
| 2001 | @@ -17,5 +17,5 @@ | ||
| 2002 | out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 2003 | } | ||
| 2004 | |||
| 2005 | -/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2006 | +/* { dg-final { scan-assembler "vbic\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2007 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2008 | |||
| 2009 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbics16.c' | ||
| 2010 | --- old/gcc/testsuite/gcc.target/arm/neon/vbics16.c 2010-07-29 15:38:15 +0000 | ||
| 2011 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbics16.c 2010-08-20 13:27:11 +0000 | ||
| 2012 | @@ -17,5 +17,5 @@ | ||
| 2013 | out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 2014 | } | ||
| 2015 | |||
| 2016 | -/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2017 | +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2018 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2019 | |||
| 2020 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbics32.c' | ||
| 2021 | --- old/gcc/testsuite/gcc.target/arm/neon/vbics32.c 2010-07-29 15:38:15 +0000 | ||
| 2022 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbics32.c 2010-08-20 13:27:11 +0000 | ||
| 2023 | @@ -17,5 +17,5 @@ | ||
| 2024 | out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 2025 | } | ||
| 2026 | |||
| 2027 | -/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2028 | +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2029 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2030 | |||
| 2031 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbics8.c' | ||
| 2032 | --- old/gcc/testsuite/gcc.target/arm/neon/vbics8.c 2010-07-29 15:38:15 +0000 | ||
| 2033 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbics8.c 2010-08-20 13:27:11 +0000 | ||
| 2034 | @@ -17,5 +17,5 @@ | ||
| 2035 | out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 2036 | } | ||
| 2037 | |||
| 2038 | -/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2039 | +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2040 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2041 | |||
| 2042 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu16.c' | ||
| 2043 | --- old/gcc/testsuite/gcc.target/arm/neon/vbicu16.c 2010-07-29 15:38:15 +0000 | ||
| 2044 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbicu16.c 2010-08-20 13:27:11 +0000 | ||
| 2045 | @@ -17,5 +17,5 @@ | ||
| 2046 | out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 2047 | } | ||
| 2048 | |||
| 2049 | -/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2050 | +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2051 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2052 | |||
| 2053 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu32.c' | ||
| 2054 | --- old/gcc/testsuite/gcc.target/arm/neon/vbicu32.c 2010-07-29 15:38:15 +0000 | ||
| 2055 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbicu32.c 2010-08-20 13:27:11 +0000 | ||
| 2056 | @@ -17,5 +17,5 @@ | ||
| 2057 | out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 2058 | } | ||
| 2059 | |||
| 2060 | -/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2061 | +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2062 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2063 | |||
| 2064 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbicu8.c' | ||
| 2065 | --- old/gcc/testsuite/gcc.target/arm/neon/vbicu8.c 2010-07-29 15:38:15 +0000 | ||
| 2066 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbicu8.c 2010-08-20 13:27:11 +0000 | ||
| 2067 | @@ -17,5 +17,5 @@ | ||
| 2068 | out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 2069 | } | ||
| 2070 | |||
| 2071 | -/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2072 | +/* { dg-final { scan-assembler "vbic\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2073 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2074 | |||
| 2075 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQf32.c' | ||
| 2076 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c 2010-07-29 15:38:15 +0000 | ||
| 2077 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c 2010-08-20 13:27:11 +0000 | ||
| 2078 | @@ -18,5 +18,5 @@ | ||
| 2079 | out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t); | ||
| 2080 | } | ||
| 2081 | |||
| 2082 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2083 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2084 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2085 | |||
| 2086 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQp16.c' | ||
| 2087 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c 2010-07-29 15:38:15 +0000 | ||
| 2088 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c 2010-08-20 13:27:11 +0000 | ||
| 2089 | @@ -18,5 +18,5 @@ | ||
| 2090 | out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t); | ||
| 2091 | } | ||
| 2092 | |||
| 2093 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2094 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2095 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2096 | |||
| 2097 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQp8.c' | ||
| 2098 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c 2010-07-29 15:38:15 +0000 | ||
| 2099 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c 2010-08-20 13:27:11 +0000 | ||
| 2100 | @@ -18,5 +18,5 @@ | ||
| 2101 | out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t); | ||
| 2102 | } | ||
| 2103 | |||
| 2104 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2105 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2106 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2107 | |||
| 2108 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs16.c' | ||
| 2109 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c 2010-07-29 15:38:15 +0000 | ||
| 2110 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c 2010-08-20 13:27:11 +0000 | ||
| 2111 | @@ -18,5 +18,5 @@ | ||
| 2112 | out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t); | ||
| 2113 | } | ||
| 2114 | |||
| 2115 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2116 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2117 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2118 | |||
| 2119 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs32.c' | ||
| 2120 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c 2010-07-29 15:38:15 +0000 | ||
| 2121 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c 2010-08-20 13:27:11 +0000 | ||
| 2122 | @@ -18,5 +18,5 @@ | ||
| 2123 | out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t); | ||
| 2124 | } | ||
| 2125 | |||
| 2126 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2127 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2128 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2129 | |||
| 2130 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs64.c' | ||
| 2131 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c 2010-07-29 15:38:15 +0000 | ||
| 2132 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c 2010-08-20 13:27:11 +0000 | ||
| 2133 | @@ -18,5 +18,5 @@ | ||
| 2134 | out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t); | ||
| 2135 | } | ||
| 2136 | |||
| 2137 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2138 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2139 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2140 | |||
| 2141 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQs8.c' | ||
| 2142 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c 2010-07-29 15:38:15 +0000 | ||
| 2143 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c 2010-08-20 13:27:11 +0000 | ||
| 2144 | @@ -18,5 +18,5 @@ | ||
| 2145 | out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t); | ||
| 2146 | } | ||
| 2147 | |||
| 2148 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2149 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2150 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2151 | |||
| 2152 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu16.c' | ||
| 2153 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c 2010-07-29 15:38:15 +0000 | ||
| 2154 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c 2010-08-20 13:27:11 +0000 | ||
| 2155 | @@ -18,5 +18,5 @@ | ||
| 2156 | out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); | ||
| 2157 | } | ||
| 2158 | |||
| 2159 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2160 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2161 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2162 | |||
| 2163 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu32.c' | ||
| 2164 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c 2010-07-29 15:38:15 +0000 | ||
| 2165 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c 2010-08-20 13:27:11 +0000 | ||
| 2166 | @@ -18,5 +18,5 @@ | ||
| 2167 | out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); | ||
| 2168 | } | ||
| 2169 | |||
| 2170 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2171 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2172 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2173 | |||
| 2174 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu64.c' | ||
| 2175 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c 2010-07-29 15:38:15 +0000 | ||
| 2176 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c 2010-08-20 13:27:11 +0000 | ||
| 2177 | @@ -18,5 +18,5 @@ | ||
| 2178 | out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t); | ||
| 2179 | } | ||
| 2180 | |||
| 2181 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2182 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2183 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2184 | |||
| 2185 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslQu8.c' | ||
| 2186 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c 2010-07-29 15:38:15 +0000 | ||
| 2187 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c 2010-08-20 13:27:11 +0000 | ||
| 2188 | @@ -18,5 +18,5 @@ | ||
| 2189 | out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); | ||
| 2190 | } | ||
| 2191 | |||
| 2192 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2193 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2194 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2195 | |||
| 2196 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslf32.c' | ||
| 2197 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslf32.c 2010-07-29 15:38:15 +0000 | ||
| 2198 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslf32.c 2010-08-20 13:27:11 +0000 | ||
| 2199 | @@ -18,5 +18,5 @@ | ||
| 2200 | out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t); | ||
| 2201 | } | ||
| 2202 | |||
| 2203 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2204 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2205 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2206 | |||
| 2207 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslp16.c' | ||
| 2208 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslp16.c 2010-07-29 15:38:15 +0000 | ||
| 2209 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslp16.c 2010-08-20 13:27:11 +0000 | ||
| 2210 | @@ -18,5 +18,5 @@ | ||
| 2211 | out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t); | ||
| 2212 | } | ||
| 2213 | |||
| 2214 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2215 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2216 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2217 | |||
| 2218 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslp8.c' | ||
| 2219 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslp8.c 2010-07-29 15:38:15 +0000 | ||
| 2220 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslp8.c 2010-08-20 13:27:11 +0000 | ||
| 2221 | @@ -18,5 +18,5 @@ | ||
| 2222 | out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t); | ||
| 2223 | } | ||
| 2224 | |||
| 2225 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2226 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2227 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2228 | |||
| 2229 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls16.c' | ||
| 2230 | --- old/gcc/testsuite/gcc.target/arm/neon/vbsls16.c 2010-07-29 15:38:15 +0000 | ||
| 2231 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbsls16.c 2010-08-20 13:27:11 +0000 | ||
| 2232 | @@ -18,5 +18,5 @@ | ||
| 2233 | out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t); | ||
| 2234 | } | ||
| 2235 | |||
| 2236 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2237 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2238 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2239 | |||
| 2240 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls32.c' | ||
| 2241 | --- old/gcc/testsuite/gcc.target/arm/neon/vbsls32.c 2010-07-29 15:38:15 +0000 | ||
| 2242 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbsls32.c 2010-08-20 13:27:11 +0000 | ||
| 2243 | @@ -18,5 +18,5 @@ | ||
| 2244 | out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t); | ||
| 2245 | } | ||
| 2246 | |||
| 2247 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2248 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2249 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2250 | |||
| 2251 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls64.c' | ||
| 2252 | --- old/gcc/testsuite/gcc.target/arm/neon/vbsls64.c 2010-07-29 15:38:15 +0000 | ||
| 2253 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbsls64.c 2010-08-20 13:27:11 +0000 | ||
| 2254 | @@ -18,5 +18,5 @@ | ||
| 2255 | out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t); | ||
| 2256 | } | ||
| 2257 | |||
| 2258 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2259 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2260 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2261 | |||
| 2262 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbsls8.c' | ||
| 2263 | --- old/gcc/testsuite/gcc.target/arm/neon/vbsls8.c 2010-07-29 15:38:15 +0000 | ||
| 2264 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbsls8.c 2010-08-20 13:27:11 +0000 | ||
| 2265 | @@ -18,5 +18,5 @@ | ||
| 2266 | out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t); | ||
| 2267 | } | ||
| 2268 | |||
| 2269 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2270 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2271 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2272 | |||
| 2273 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu16.c' | ||
| 2274 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslu16.c 2010-07-29 15:38:15 +0000 | ||
| 2275 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslu16.c 2010-08-20 13:27:11 +0000 | ||
| 2276 | @@ -18,5 +18,5 @@ | ||
| 2277 | out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); | ||
| 2278 | } | ||
| 2279 | |||
| 2280 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2281 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2282 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2283 | |||
| 2284 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu32.c' | ||
| 2285 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslu32.c 2010-07-29 15:38:15 +0000 | ||
| 2286 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslu32.c 2010-08-20 13:27:11 +0000 | ||
| 2287 | @@ -18,5 +18,5 @@ | ||
| 2288 | out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); | ||
| 2289 | } | ||
| 2290 | |||
| 2291 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2292 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2293 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2294 | |||
| 2295 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu64.c' | ||
| 2296 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslu64.c 2010-07-29 15:38:15 +0000 | ||
| 2297 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslu64.c 2010-08-20 13:27:11 +0000 | ||
| 2298 | @@ -18,5 +18,5 @@ | ||
| 2299 | out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t); | ||
| 2300 | } | ||
| 2301 | |||
| 2302 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2303 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2304 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2305 | |||
| 2306 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vbslu8.c' | ||
| 2307 | --- old/gcc/testsuite/gcc.target/arm/neon/vbslu8.c 2010-07-29 15:38:15 +0000 | ||
| 2308 | +++ new/gcc/testsuite/gcc.target/arm/neon/vbslu8.c 2010-08-20 13:27:11 +0000 | ||
| 2309 | @@ -18,5 +18,5 @@ | ||
| 2310 | out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); | ||
| 2311 | } | ||
| 2312 | |||
| 2313 | -/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2314 | +/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2315 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2316 | |||
| 2317 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcageQf32.c' | ||
| 2318 | --- old/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c 2010-07-29 15:38:15 +0000 | ||
| 2319 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c 2010-08-20 13:27:11 +0000 | ||
| 2320 | @@ -17,5 +17,5 @@ | ||
| 2321 | out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 2322 | } | ||
| 2323 | |||
| 2324 | -/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2325 | +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2326 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2327 | |||
| 2328 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcagef32.c' | ||
| 2329 | --- old/gcc/testsuite/gcc.target/arm/neon/vcagef32.c 2010-07-29 15:38:15 +0000 | ||
| 2330 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcagef32.c 2010-08-20 13:27:11 +0000 | ||
| 2331 | @@ -17,5 +17,5 @@ | ||
| 2332 | out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 2333 | } | ||
| 2334 | |||
| 2335 | -/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2336 | +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2337 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2338 | |||
| 2339 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c' | ||
| 2340 | --- old/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c 2010-07-29 15:38:15 +0000 | ||
| 2341 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c 2010-08-20 13:27:11 +0000 | ||
| 2342 | @@ -17,5 +17,5 @@ | ||
| 2343 | out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 2344 | } | ||
| 2345 | |||
| 2346 | -/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2347 | +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2348 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2349 | |||
| 2350 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcagtf32.c' | ||
| 2351 | --- old/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c 2010-07-29 15:38:15 +0000 | ||
| 2352 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c 2010-08-20 13:27:11 +0000 | ||
| 2353 | @@ -17,5 +17,5 @@ | ||
| 2354 | out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 2355 | } | ||
| 2356 | |||
| 2357 | -/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2358 | +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2359 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2360 | |||
| 2361 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c' | ||
| 2362 | --- old/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c 2010-07-29 15:38:15 +0000 | ||
| 2363 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c 2010-08-20 13:27:11 +0000 | ||
| 2364 | @@ -17,5 +17,5 @@ | ||
| 2365 | out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 2366 | } | ||
| 2367 | |||
| 2368 | -/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2369 | +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2370 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2371 | |||
| 2372 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcalef32.c' | ||
| 2373 | --- old/gcc/testsuite/gcc.target/arm/neon/vcalef32.c 2010-07-29 15:38:15 +0000 | ||
| 2374 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcalef32.c 2010-08-20 13:27:11 +0000 | ||
| 2375 | @@ -17,5 +17,5 @@ | ||
| 2376 | out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 2377 | } | ||
| 2378 | |||
| 2379 | -/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2380 | +/* { dg-final { scan-assembler "vacge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2381 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2382 | |||
| 2383 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c' | ||
| 2384 | --- old/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c 2010-07-29 15:38:15 +0000 | ||
| 2385 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c 2010-08-20 13:27:11 +0000 | ||
| 2386 | @@ -17,5 +17,5 @@ | ||
| 2387 | out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 2388 | } | ||
| 2389 | |||
| 2390 | -/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2391 | +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2392 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2393 | |||
| 2394 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcaltf32.c' | ||
| 2395 | --- old/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c 2010-07-29 15:38:15 +0000 | ||
| 2396 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c 2010-08-20 13:27:11 +0000 | ||
| 2397 | @@ -17,5 +17,5 @@ | ||
| 2398 | out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 2399 | } | ||
| 2400 | |||
| 2401 | -/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2402 | +/* { dg-final { scan-assembler "vacgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2403 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2404 | |||
| 2405 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQf32.c' | ||
| 2406 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c 2010-07-29 15:38:15 +0000 | ||
| 2407 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c 2010-08-20 13:27:11 +0000 | ||
| 2408 | @@ -17,5 +17,5 @@ | ||
| 2409 | out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 2410 | } | ||
| 2411 | |||
| 2412 | -/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2413 | +/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2414 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2415 | |||
| 2416 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQp8.c' | ||
| 2417 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c 2010-07-29 15:38:15 +0000 | ||
| 2418 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c 2010-08-20 13:27:11 +0000 | ||
| 2419 | @@ -17,5 +17,5 @@ | ||
| 2420 | out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); | ||
| 2421 | } | ||
| 2422 | |||
| 2423 | -/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2424 | +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2425 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2426 | |||
| 2427 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQs16.c' | ||
| 2428 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c 2010-07-29 15:38:15 +0000 | ||
| 2429 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c 2010-08-20 13:27:11 +0000 | ||
| 2430 | @@ -17,5 +17,5 @@ | ||
| 2431 | out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 2432 | } | ||
| 2433 | |||
| 2434 | -/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2435 | +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2436 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2437 | |||
| 2438 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQs32.c' | ||
| 2439 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c 2010-07-29 15:38:15 +0000 | ||
| 2440 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c 2010-08-20 13:27:11 +0000 | ||
| 2441 | @@ -17,5 +17,5 @@ | ||
| 2442 | out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 2443 | } | ||
| 2444 | |||
| 2445 | -/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2446 | +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2447 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2448 | |||
| 2449 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQs8.c' | ||
| 2450 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c 2010-07-29 15:38:15 +0000 | ||
| 2451 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c 2010-08-20 13:27:11 +0000 | ||
| 2452 | @@ -17,5 +17,5 @@ | ||
| 2453 | out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 2454 | } | ||
| 2455 | |||
| 2456 | -/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2457 | +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2458 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2459 | |||
| 2460 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQu16.c' | ||
| 2461 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c 2010-07-29 15:38:15 +0000 | ||
| 2462 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c 2010-08-20 13:27:11 +0000 | ||
| 2463 | @@ -17,5 +17,5 @@ | ||
| 2464 | out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 2465 | } | ||
| 2466 | |||
| 2467 | -/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2468 | +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2469 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2470 | |||
| 2471 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQu32.c' | ||
| 2472 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c 2010-07-29 15:38:15 +0000 | ||
| 2473 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c 2010-08-20 13:27:11 +0000 | ||
| 2474 | @@ -17,5 +17,5 @@ | ||
| 2475 | out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 2476 | } | ||
| 2477 | |||
| 2478 | -/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2479 | +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2480 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2481 | |||
| 2482 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqQu8.c' | ||
| 2483 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c 2010-07-29 15:38:15 +0000 | ||
| 2484 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c 2010-08-20 13:27:11 +0000 | ||
| 2485 | @@ -17,5 +17,5 @@ | ||
| 2486 | out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 2487 | } | ||
| 2488 | |||
| 2489 | -/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2490 | +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2491 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2492 | |||
| 2493 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqf32.c' | ||
| 2494 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqf32.c 2010-07-29 15:38:15 +0000 | ||
| 2495 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqf32.c 2010-08-20 13:27:11 +0000 | ||
| 2496 | @@ -17,5 +17,5 @@ | ||
| 2497 | out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 2498 | } | ||
| 2499 | |||
| 2500 | -/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2501 | +/* { dg-final { scan-assembler "vceq\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2502 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2503 | |||
| 2504 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqp8.c' | ||
| 2505 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqp8.c 2010-07-29 15:38:15 +0000 | ||
| 2506 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqp8.c 2010-08-20 13:27:11 +0000 | ||
| 2507 | @@ -17,5 +17,5 @@ | ||
| 2508 | out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t); | ||
| 2509 | } | ||
| 2510 | |||
| 2511 | -/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2512 | +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2513 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2514 | |||
| 2515 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqs16.c' | ||
| 2516 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqs16.c 2010-07-29 15:38:15 +0000 | ||
| 2517 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqs16.c 2010-08-20 13:27:11 +0000 | ||
| 2518 | @@ -17,5 +17,5 @@ | ||
| 2519 | out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 2520 | } | ||
| 2521 | |||
| 2522 | -/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2523 | +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2524 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2525 | |||
| 2526 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqs32.c' | ||
| 2527 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqs32.c 2010-07-29 15:38:15 +0000 | ||
| 2528 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqs32.c 2010-08-20 13:27:11 +0000 | ||
| 2529 | @@ -17,5 +17,5 @@ | ||
| 2530 | out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 2531 | } | ||
| 2532 | |||
| 2533 | -/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2534 | +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2535 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2536 | |||
| 2537 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vceqs8.c' | ||
| 2538 | --- old/gcc/testsuite/gcc.target/arm/neon/vceqs8.c 2010-07-29 15:38:15 +0000 | ||
| 2539 | +++ new/gcc/testsuite/gcc.target/arm/neon/vceqs8.c 2010-08-20 13:27:11 +0000 | ||
| 2540 | @@ -17,5 +17,5 @@ | ||
| 2541 | out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 2542 | } | ||
| 2543 | |||
| 2544 | -/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2545 | +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2546 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2547 | |||
| 2548 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcequ16.c' | ||
| 2549 | --- old/gcc/testsuite/gcc.target/arm/neon/vcequ16.c 2010-07-29 15:38:15 +0000 | ||
| 2550 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcequ16.c 2010-08-20 13:27:11 +0000 | ||
| 2551 | @@ -17,5 +17,5 @@ | ||
| 2552 | out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 2553 | } | ||
| 2554 | |||
| 2555 | -/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2556 | +/* { dg-final { scan-assembler "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2557 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2558 | |||
| 2559 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcequ32.c' | ||
| 2560 | --- old/gcc/testsuite/gcc.target/arm/neon/vcequ32.c 2010-07-29 15:38:15 +0000 | ||
| 2561 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcequ32.c 2010-08-20 13:27:11 +0000 | ||
| 2562 | @@ -17,5 +17,5 @@ | ||
| 2563 | out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 2564 | } | ||
| 2565 | |||
| 2566 | -/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2567 | +/* { dg-final { scan-assembler "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2568 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2569 | |||
| 2570 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcequ8.c' | ||
| 2571 | --- old/gcc/testsuite/gcc.target/arm/neon/vcequ8.c 2010-07-29 15:38:15 +0000 | ||
| 2572 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcequ8.c 2010-08-20 13:27:11 +0000 | ||
| 2573 | @@ -17,5 +17,5 @@ | ||
| 2574 | out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 2575 | } | ||
| 2576 | |||
| 2577 | -/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2578 | +/* { dg-final { scan-assembler "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2579 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2580 | |||
| 2581 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c' | ||
| 2582 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c 2010-07-29 15:38:15 +0000 | ||
| 2583 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c 2010-08-20 13:27:11 +0000 | ||
| 2584 | @@ -17,5 +17,5 @@ | ||
| 2585 | out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 2586 | } | ||
| 2587 | |||
| 2588 | -/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2589 | +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2590 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2591 | |||
| 2592 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c' | ||
| 2593 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c 2010-07-29 15:38:15 +0000 | ||
| 2594 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c 2010-08-20 13:27:11 +0000 | ||
| 2595 | @@ -17,5 +17,5 @@ | ||
| 2596 | out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 2597 | } | ||
| 2598 | |||
| 2599 | -/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2600 | +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2601 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2602 | |||
| 2603 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c' | ||
| 2604 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c 2010-07-29 15:38:15 +0000 | ||
| 2605 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c 2010-08-20 13:27:11 +0000 | ||
| 2606 | @@ -17,5 +17,5 @@ | ||
| 2607 | out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 2608 | } | ||
| 2609 | |||
| 2610 | -/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2611 | +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2612 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2613 | |||
| 2614 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c' | ||
| 2615 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c 2010-07-29 15:38:15 +0000 | ||
| 2616 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c 2010-08-20 13:27:11 +0000 | ||
| 2617 | @@ -17,5 +17,5 @@ | ||
| 2618 | out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 2619 | } | ||
| 2620 | |||
| 2621 | -/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2622 | +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2623 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2624 | |||
| 2625 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c' | ||
| 2626 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c 2010-07-29 15:38:15 +0000 | ||
| 2627 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c 2010-08-20 13:27:11 +0000 | ||
| 2628 | @@ -17,5 +17,5 @@ | ||
| 2629 | out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 2630 | } | ||
| 2631 | |||
| 2632 | -/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2633 | +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2634 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2635 | |||
| 2636 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c' | ||
| 2637 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c 2010-07-29 15:38:15 +0000 | ||
| 2638 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c 2010-08-20 13:27:11 +0000 | ||
| 2639 | @@ -17,5 +17,5 @@ | ||
| 2640 | out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 2641 | } | ||
| 2642 | |||
| 2643 | -/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2644 | +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2645 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2646 | |||
| 2647 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c' | ||
| 2648 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c 2010-07-29 15:38:15 +0000 | ||
| 2649 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c 2010-08-20 13:27:11 +0000 | ||
| 2650 | @@ -17,5 +17,5 @@ | ||
| 2651 | out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 2652 | } | ||
| 2653 | |||
| 2654 | -/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2655 | +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2656 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2657 | |||
| 2658 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgef32.c' | ||
| 2659 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgef32.c 2010-07-29 15:38:15 +0000 | ||
| 2660 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgef32.c 2010-08-20 13:27:11 +0000 | ||
| 2661 | @@ -17,5 +17,5 @@ | ||
| 2662 | out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 2663 | } | ||
| 2664 | |||
| 2665 | -/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2666 | +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2667 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2668 | |||
| 2669 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcges16.c' | ||
| 2670 | --- old/gcc/testsuite/gcc.target/arm/neon/vcges16.c 2010-07-29 15:38:15 +0000 | ||
| 2671 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcges16.c 2010-08-20 13:27:11 +0000 | ||
| 2672 | @@ -17,5 +17,5 @@ | ||
| 2673 | out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 2674 | } | ||
| 2675 | |||
| 2676 | -/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2677 | +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2678 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2679 | |||
| 2680 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcges32.c' | ||
| 2681 | --- old/gcc/testsuite/gcc.target/arm/neon/vcges32.c 2010-07-29 15:38:15 +0000 | ||
| 2682 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcges32.c 2010-08-20 13:27:11 +0000 | ||
| 2683 | @@ -17,5 +17,5 @@ | ||
| 2684 | out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 2685 | } | ||
| 2686 | |||
| 2687 | -/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2688 | +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2689 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2690 | |||
| 2691 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcges8.c' | ||
| 2692 | --- old/gcc/testsuite/gcc.target/arm/neon/vcges8.c 2010-07-29 15:38:15 +0000 | ||
| 2693 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcges8.c 2010-08-20 13:27:11 +0000 | ||
| 2694 | @@ -17,5 +17,5 @@ | ||
| 2695 | out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 2696 | } | ||
| 2697 | |||
| 2698 | -/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2699 | +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2700 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2701 | |||
| 2702 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeu16.c' | ||
| 2703 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c 2010-07-29 15:38:15 +0000 | ||
| 2704 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c 2010-08-20 13:27:11 +0000 | ||
| 2705 | @@ -17,5 +17,5 @@ | ||
| 2706 | out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 2707 | } | ||
| 2708 | |||
| 2709 | -/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2710 | +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2711 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2712 | |||
| 2713 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeu32.c' | ||
| 2714 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c 2010-07-29 15:38:15 +0000 | ||
| 2715 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c 2010-08-20 13:27:11 +0000 | ||
| 2716 | @@ -17,5 +17,5 @@ | ||
| 2717 | out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 2718 | } | ||
| 2719 | |||
| 2720 | -/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2721 | +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2722 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2723 | |||
| 2724 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgeu8.c' | ||
| 2725 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c 2010-07-29 15:38:15 +0000 | ||
| 2726 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c 2010-08-20 13:27:11 +0000 | ||
| 2727 | @@ -17,5 +17,5 @@ | ||
| 2728 | out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 2729 | } | ||
| 2730 | |||
| 2731 | -/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2732 | +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2733 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2734 | |||
| 2735 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c' | ||
| 2736 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c 2010-07-29 15:38:15 +0000 | ||
| 2737 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c 2010-08-20 13:27:11 +0000 | ||
| 2738 | @@ -17,5 +17,5 @@ | ||
| 2739 | out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 2740 | } | ||
| 2741 | |||
| 2742 | -/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2743 | +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2744 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2745 | |||
| 2746 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c' | ||
| 2747 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c 2010-07-29 15:38:15 +0000 | ||
| 2748 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c 2010-08-20 13:27:11 +0000 | ||
| 2749 | @@ -17,5 +17,5 @@ | ||
| 2750 | out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 2751 | } | ||
| 2752 | |||
| 2753 | -/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2754 | +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2755 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2756 | |||
| 2757 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c' | ||
| 2758 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c 2010-07-29 15:38:15 +0000 | ||
| 2759 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c 2010-08-20 13:27:11 +0000 | ||
| 2760 | @@ -17,5 +17,5 @@ | ||
| 2761 | out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 2762 | } | ||
| 2763 | |||
| 2764 | -/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2765 | +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2766 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2767 | |||
| 2768 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c' | ||
| 2769 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c 2010-07-29 15:38:15 +0000 | ||
| 2770 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c 2010-08-20 13:27:11 +0000 | ||
| 2771 | @@ -17,5 +17,5 @@ | ||
| 2772 | out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 2773 | } | ||
| 2774 | |||
| 2775 | -/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2776 | +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2777 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2778 | |||
| 2779 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c' | ||
| 2780 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c 2010-07-29 15:38:15 +0000 | ||
| 2781 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c 2010-08-20 13:27:11 +0000 | ||
| 2782 | @@ -17,5 +17,5 @@ | ||
| 2783 | out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 2784 | } | ||
| 2785 | |||
| 2786 | -/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2787 | +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2788 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2789 | |||
| 2790 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c' | ||
| 2791 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c 2010-07-29 15:38:15 +0000 | ||
| 2792 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c 2010-08-20 13:27:11 +0000 | ||
| 2793 | @@ -17,5 +17,5 @@ | ||
| 2794 | out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 2795 | } | ||
| 2796 | |||
| 2797 | -/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2798 | +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2799 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2800 | |||
| 2801 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c' | ||
| 2802 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c 2010-07-29 15:38:15 +0000 | ||
| 2803 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c 2010-08-20 13:27:11 +0000 | ||
| 2804 | @@ -17,5 +17,5 @@ | ||
| 2805 | out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 2806 | } | ||
| 2807 | |||
| 2808 | -/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2809 | +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2810 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2811 | |||
| 2812 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtf32.c' | ||
| 2813 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c 2010-07-29 15:38:15 +0000 | ||
| 2814 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c 2010-08-20 13:27:11 +0000 | ||
| 2815 | @@ -17,5 +17,5 @@ | ||
| 2816 | out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 2817 | } | ||
| 2818 | |||
| 2819 | -/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2820 | +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2821 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2822 | |||
| 2823 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgts16.c' | ||
| 2824 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgts16.c 2010-07-29 15:38:15 +0000 | ||
| 2825 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgts16.c 2010-08-20 13:27:11 +0000 | ||
| 2826 | @@ -17,5 +17,5 @@ | ||
| 2827 | out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 2828 | } | ||
| 2829 | |||
| 2830 | -/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2831 | +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2832 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2833 | |||
| 2834 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgts32.c' | ||
| 2835 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgts32.c 2010-07-29 15:38:15 +0000 | ||
| 2836 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgts32.c 2010-08-20 13:27:11 +0000 | ||
| 2837 | @@ -17,5 +17,5 @@ | ||
| 2838 | out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 2839 | } | ||
| 2840 | |||
| 2841 | -/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2842 | +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2843 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2844 | |||
| 2845 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgts8.c' | ||
| 2846 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgts8.c 2010-07-29 15:38:15 +0000 | ||
| 2847 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgts8.c 2010-08-20 13:27:11 +0000 | ||
| 2848 | @@ -17,5 +17,5 @@ | ||
| 2849 | out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 2850 | } | ||
| 2851 | |||
| 2852 | -/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2853 | +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2854 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2855 | |||
| 2856 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtu16.c' | ||
| 2857 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c 2010-07-29 15:38:15 +0000 | ||
| 2858 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c 2010-08-20 13:27:11 +0000 | ||
| 2859 | @@ -17,5 +17,5 @@ | ||
| 2860 | out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 2861 | } | ||
| 2862 | |||
| 2863 | -/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2864 | +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2865 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2866 | |||
| 2867 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtu32.c' | ||
| 2868 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c 2010-07-29 15:38:15 +0000 | ||
| 2869 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c 2010-08-20 13:27:11 +0000 | ||
| 2870 | @@ -17,5 +17,5 @@ | ||
| 2871 | out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 2872 | } | ||
| 2873 | |||
| 2874 | -/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2875 | +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2876 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2877 | |||
| 2878 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcgtu8.c' | ||
| 2879 | --- old/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c 2010-07-29 15:38:15 +0000 | ||
| 2880 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c 2010-08-20 13:27:11 +0000 | ||
| 2881 | @@ -17,5 +17,5 @@ | ||
| 2882 | out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 2883 | } | ||
| 2884 | |||
| 2885 | -/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2886 | +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2887 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2888 | |||
| 2889 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQf32.c' | ||
| 2890 | --- old/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c 2010-07-29 15:38:15 +0000 | ||
| 2891 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c 2010-08-20 13:27:11 +0000 | ||
| 2892 | @@ -17,5 +17,5 @@ | ||
| 2893 | out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 2894 | } | ||
| 2895 | |||
| 2896 | -/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2897 | +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2898 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2899 | |||
| 2900 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQs16.c' | ||
| 2901 | --- old/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c 2010-07-29 15:38:15 +0000 | ||
| 2902 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c 2010-08-20 13:27:11 +0000 | ||
| 2903 | @@ -17,5 +17,5 @@ | ||
| 2904 | out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 2905 | } | ||
| 2906 | |||
| 2907 | -/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2908 | +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2909 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2910 | |||
| 2911 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQs32.c' | ||
| 2912 | --- old/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c 2010-07-29 15:38:15 +0000 | ||
| 2913 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c 2010-08-20 13:27:11 +0000 | ||
| 2914 | @@ -17,5 +17,5 @@ | ||
| 2915 | out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 2916 | } | ||
| 2917 | |||
| 2918 | -/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2919 | +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2920 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2921 | |||
| 2922 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQs8.c' | ||
| 2923 | --- old/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c 2010-07-29 15:38:15 +0000 | ||
| 2924 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c 2010-08-20 13:27:11 +0000 | ||
| 2925 | @@ -17,5 +17,5 @@ | ||
| 2926 | out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 2927 | } | ||
| 2928 | |||
| 2929 | -/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2930 | +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2931 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2932 | |||
| 2933 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQu16.c' | ||
| 2934 | --- old/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c 2010-07-29 15:38:15 +0000 | ||
| 2935 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c 2010-08-20 13:27:11 +0000 | ||
| 2936 | @@ -17,5 +17,5 @@ | ||
| 2937 | out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 2938 | } | ||
| 2939 | |||
| 2940 | -/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2941 | +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2942 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2943 | |||
| 2944 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQu32.c' | ||
| 2945 | --- old/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c 2010-07-29 15:38:15 +0000 | ||
| 2946 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c 2010-08-20 13:27:11 +0000 | ||
| 2947 | @@ -17,5 +17,5 @@ | ||
| 2948 | out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 2949 | } | ||
| 2950 | |||
| 2951 | -/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2952 | +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2953 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2954 | |||
| 2955 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcleQu8.c' | ||
| 2956 | --- old/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c 2010-07-29 15:38:15 +0000 | ||
| 2957 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c 2010-08-20 13:27:11 +0000 | ||
| 2958 | @@ -17,5 +17,5 @@ | ||
| 2959 | out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 2960 | } | ||
| 2961 | |||
| 2962 | -/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2963 | +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2964 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2965 | |||
| 2966 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclef32.c' | ||
| 2967 | --- old/gcc/testsuite/gcc.target/arm/neon/vclef32.c 2010-07-29 15:38:15 +0000 | ||
| 2968 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclef32.c 2010-08-20 13:27:11 +0000 | ||
| 2969 | @@ -17,5 +17,5 @@ | ||
| 2970 | out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 2971 | } | ||
| 2972 | |||
| 2973 | -/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2974 | +/* { dg-final { scan-assembler "vcge\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2975 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2976 | |||
| 2977 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcles16.c' | ||
| 2978 | --- old/gcc/testsuite/gcc.target/arm/neon/vcles16.c 2010-07-29 15:38:15 +0000 | ||
| 2979 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcles16.c 2010-08-20 13:27:11 +0000 | ||
| 2980 | @@ -17,5 +17,5 @@ | ||
| 2981 | out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 2982 | } | ||
| 2983 | |||
| 2984 | -/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2985 | +/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2986 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2987 | |||
| 2988 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcles32.c' | ||
| 2989 | --- old/gcc/testsuite/gcc.target/arm/neon/vcles32.c 2010-07-29 15:38:15 +0000 | ||
| 2990 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcles32.c 2010-08-20 13:27:11 +0000 | ||
| 2991 | @@ -17,5 +17,5 @@ | ||
| 2992 | out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 2993 | } | ||
| 2994 | |||
| 2995 | -/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 2996 | +/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2997 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2998 | |||
| 2999 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcles8.c' | ||
| 3000 | --- old/gcc/testsuite/gcc.target/arm/neon/vcles8.c 2010-07-29 15:38:15 +0000 | ||
| 3001 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcles8.c 2010-08-20 13:27:11 +0000 | ||
| 3002 | @@ -17,5 +17,5 @@ | ||
| 3003 | out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 3004 | } | ||
| 3005 | |||
| 3006 | -/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3007 | +/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3008 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3009 | |||
| 3010 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcleu16.c' | ||
| 3011 | --- old/gcc/testsuite/gcc.target/arm/neon/vcleu16.c 2010-07-29 15:38:15 +0000 | ||
| 3012 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcleu16.c 2010-08-20 13:27:11 +0000 | ||
| 3013 | @@ -17,5 +17,5 @@ | ||
| 3014 | out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 3015 | } | ||
| 3016 | |||
| 3017 | -/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3018 | +/* { dg-final { scan-assembler "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3019 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3020 | |||
| 3021 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcleu32.c' | ||
| 3022 | --- old/gcc/testsuite/gcc.target/arm/neon/vcleu32.c 2010-07-29 15:38:15 +0000 | ||
| 3023 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcleu32.c 2010-08-20 13:27:11 +0000 | ||
| 3024 | @@ -17,5 +17,5 @@ | ||
| 3025 | out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 3026 | } | ||
| 3027 | |||
| 3028 | -/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3029 | +/* { dg-final { scan-assembler "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3030 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3031 | |||
| 3032 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcleu8.c' | ||
| 3033 | --- old/gcc/testsuite/gcc.target/arm/neon/vcleu8.c 2010-07-29 15:38:15 +0000 | ||
| 3034 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcleu8.c 2010-08-20 13:27:11 +0000 | ||
| 3035 | @@ -17,5 +17,5 @@ | ||
| 3036 | out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 3037 | } | ||
| 3038 | |||
| 3039 | -/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3040 | +/* { dg-final { scan-assembler "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3041 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3042 | |||
| 3043 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclsQs16.c' | ||
| 3044 | --- old/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c 2010-07-29 15:38:15 +0000 | ||
| 3045 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c 2010-08-20 13:27:11 +0000 | ||
| 3046 | @@ -16,5 +16,5 @@ | ||
| 3047 | out_int16x8_t = vclsq_s16 (arg0_int16x8_t); | ||
| 3048 | } | ||
| 3049 | |||
| 3050 | -/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3051 | +/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3052 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3053 | |||
| 3054 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclsQs32.c' | ||
| 3055 | --- old/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c 2010-07-29 15:38:15 +0000 | ||
| 3056 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c 2010-08-20 13:27:11 +0000 | ||
| 3057 | @@ -16,5 +16,5 @@ | ||
| 3058 | out_int32x4_t = vclsq_s32 (arg0_int32x4_t); | ||
| 3059 | } | ||
| 3060 | |||
| 3061 | -/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3062 | +/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3063 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3064 | |||
| 3065 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclsQs8.c' | ||
| 3066 | --- old/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c 2010-07-29 15:38:15 +0000 | ||
| 3067 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c 2010-08-20 13:27:11 +0000 | ||
| 3068 | @@ -16,5 +16,5 @@ | ||
| 3069 | out_int8x16_t = vclsq_s8 (arg0_int8x16_t); | ||
| 3070 | } | ||
| 3071 | |||
| 3072 | -/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3073 | +/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3074 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3075 | |||
| 3076 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclss16.c' | ||
| 3077 | --- old/gcc/testsuite/gcc.target/arm/neon/vclss16.c 2010-07-29 15:38:15 +0000 | ||
| 3078 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclss16.c 2010-08-20 13:27:11 +0000 | ||
| 3079 | @@ -16,5 +16,5 @@ | ||
| 3080 | out_int16x4_t = vcls_s16 (arg0_int16x4_t); | ||
| 3081 | } | ||
| 3082 | |||
| 3083 | -/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3084 | +/* { dg-final { scan-assembler "vcls\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3085 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3086 | |||
| 3087 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclss32.c' | ||
| 3088 | --- old/gcc/testsuite/gcc.target/arm/neon/vclss32.c 2010-07-29 15:38:15 +0000 | ||
| 3089 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclss32.c 2010-08-20 13:27:11 +0000 | ||
| 3090 | @@ -16,5 +16,5 @@ | ||
| 3091 | out_int32x2_t = vcls_s32 (arg0_int32x2_t); | ||
| 3092 | } | ||
| 3093 | |||
| 3094 | -/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3095 | +/* { dg-final { scan-assembler "vcls\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3096 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3097 | |||
| 3098 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclss8.c' | ||
| 3099 | --- old/gcc/testsuite/gcc.target/arm/neon/vclss8.c 2010-07-29 15:38:15 +0000 | ||
| 3100 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclss8.c 2010-08-20 13:27:11 +0000 | ||
| 3101 | @@ -16,5 +16,5 @@ | ||
| 3102 | out_int8x8_t = vcls_s8 (arg0_int8x8_t); | ||
| 3103 | } | ||
| 3104 | |||
| 3105 | -/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3106 | +/* { dg-final { scan-assembler "vcls\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3107 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3108 | |||
| 3109 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQf32.c' | ||
| 3110 | --- old/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c 2010-07-29 15:38:15 +0000 | ||
| 3111 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c 2010-08-20 13:27:11 +0000 | ||
| 3112 | @@ -17,5 +17,5 @@ | ||
| 3113 | out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 3114 | } | ||
| 3115 | |||
| 3116 | -/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3117 | +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3118 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3119 | |||
| 3120 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQs16.c' | ||
| 3121 | --- old/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c 2010-07-29 15:38:15 +0000 | ||
| 3122 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c 2010-08-20 13:27:11 +0000 | ||
| 3123 | @@ -17,5 +17,5 @@ | ||
| 3124 | out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 3125 | } | ||
| 3126 | |||
| 3127 | -/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3128 | +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3129 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3130 | |||
| 3131 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQs32.c' | ||
| 3132 | --- old/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c 2010-07-29 15:38:15 +0000 | ||
| 3133 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c 2010-08-20 13:27:11 +0000 | ||
| 3134 | @@ -17,5 +17,5 @@ | ||
| 3135 | out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 3136 | } | ||
| 3137 | |||
| 3138 | -/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3139 | +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3140 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3141 | |||
| 3142 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQs8.c' | ||
| 3143 | --- old/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c 2010-07-29 15:38:15 +0000 | ||
| 3144 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c 2010-08-20 13:27:11 +0000 | ||
| 3145 | @@ -17,5 +17,5 @@ | ||
| 3146 | out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 3147 | } | ||
| 3148 | |||
| 3149 | -/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3150 | +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3151 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3152 | |||
| 3153 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQu16.c' | ||
| 3154 | --- old/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c 2010-07-29 15:38:15 +0000 | ||
| 3155 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c 2010-08-20 13:27:11 +0000 | ||
| 3156 | @@ -17,5 +17,5 @@ | ||
| 3157 | out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 3158 | } | ||
| 3159 | |||
| 3160 | -/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3161 | +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3162 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3163 | |||
| 3164 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQu32.c' | ||
| 3165 | --- old/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c 2010-07-29 15:38:15 +0000 | ||
| 3166 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c 2010-08-20 13:27:11 +0000 | ||
| 3167 | @@ -17,5 +17,5 @@ | ||
| 3168 | out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 3169 | } | ||
| 3170 | |||
| 3171 | -/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3172 | +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3173 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3174 | |||
| 3175 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcltQu8.c' | ||
| 3176 | --- old/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c 2010-07-29 15:38:15 +0000 | ||
| 3177 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c 2010-08-20 13:27:11 +0000 | ||
| 3178 | @@ -17,5 +17,5 @@ | ||
| 3179 | out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 3180 | } | ||
| 3181 | |||
| 3182 | -/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3183 | +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3184 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3185 | |||
| 3186 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcltf32.c' | ||
| 3187 | --- old/gcc/testsuite/gcc.target/arm/neon/vcltf32.c 2010-07-29 15:38:15 +0000 | ||
| 3188 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcltf32.c 2010-08-20 13:27:11 +0000 | ||
| 3189 | @@ -17,5 +17,5 @@ | ||
| 3190 | out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 3191 | } | ||
| 3192 | |||
| 3193 | -/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3194 | +/* { dg-final { scan-assembler "vcgt\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3195 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3196 | |||
| 3197 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclts16.c' | ||
| 3198 | --- old/gcc/testsuite/gcc.target/arm/neon/vclts16.c 2010-07-29 15:38:15 +0000 | ||
| 3199 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclts16.c 2010-08-20 13:27:11 +0000 | ||
| 3200 | @@ -17,5 +17,5 @@ | ||
| 3201 | out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 3202 | } | ||
| 3203 | |||
| 3204 | -/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3205 | +/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3206 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3207 | |||
| 3208 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclts32.c' | ||
| 3209 | --- old/gcc/testsuite/gcc.target/arm/neon/vclts32.c 2010-07-29 15:38:15 +0000 | ||
| 3210 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclts32.c 2010-08-20 13:27:11 +0000 | ||
| 3211 | @@ -17,5 +17,5 @@ | ||
| 3212 | out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 3213 | } | ||
| 3214 | |||
| 3215 | -/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3216 | +/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3217 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3218 | |||
| 3219 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclts8.c' | ||
| 3220 | --- old/gcc/testsuite/gcc.target/arm/neon/vclts8.c 2010-07-29 15:38:15 +0000 | ||
| 3221 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclts8.c 2010-08-20 13:27:11 +0000 | ||
| 3222 | @@ -17,5 +17,5 @@ | ||
| 3223 | out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 3224 | } | ||
| 3225 | |||
| 3226 | -/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3227 | +/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3228 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3229 | |||
| 3230 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcltu16.c' | ||
| 3231 | --- old/gcc/testsuite/gcc.target/arm/neon/vcltu16.c 2010-07-29 15:38:15 +0000 | ||
| 3232 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcltu16.c 2010-08-20 13:27:11 +0000 | ||
| 3233 | @@ -17,5 +17,5 @@ | ||
| 3234 | out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 3235 | } | ||
| 3236 | |||
| 3237 | -/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3238 | +/* { dg-final { scan-assembler "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3239 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3240 | |||
| 3241 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcltu32.c' | ||
| 3242 | --- old/gcc/testsuite/gcc.target/arm/neon/vcltu32.c 2010-07-29 15:38:15 +0000 | ||
| 3243 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcltu32.c 2010-08-20 13:27:11 +0000 | ||
| 3244 | @@ -17,5 +17,5 @@ | ||
| 3245 | out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 3246 | } | ||
| 3247 | |||
| 3248 | -/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3249 | +/* { dg-final { scan-assembler "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3250 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3251 | |||
| 3252 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcltu8.c' | ||
| 3253 | --- old/gcc/testsuite/gcc.target/arm/neon/vcltu8.c 2010-07-29 15:38:15 +0000 | ||
| 3254 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcltu8.c 2010-08-20 13:27:11 +0000 | ||
| 3255 | @@ -17,5 +17,5 @@ | ||
| 3256 | out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 3257 | } | ||
| 3258 | |||
| 3259 | -/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3260 | +/* { dg-final { scan-assembler "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3261 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3262 | |||
| 3263 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQs16.c' | ||
| 3264 | --- old/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c 2010-07-29 15:38:15 +0000 | ||
| 3265 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c 2010-08-20 13:27:11 +0000 | ||
| 3266 | @@ -16,5 +16,5 @@ | ||
| 3267 | out_int16x8_t = vclzq_s16 (arg0_int16x8_t); | ||
| 3268 | } | ||
| 3269 | |||
| 3270 | -/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3271 | +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3272 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3273 | |||
| 3274 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQs32.c' | ||
| 3275 | --- old/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c 2010-07-29 15:38:15 +0000 | ||
| 3276 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c 2010-08-20 13:27:11 +0000 | ||
| 3277 | @@ -16,5 +16,5 @@ | ||
| 3278 | out_int32x4_t = vclzq_s32 (arg0_int32x4_t); | ||
| 3279 | } | ||
| 3280 | |||
| 3281 | -/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3282 | +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3283 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3284 | |||
| 3285 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQs8.c' | ||
| 3286 | --- old/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c 2010-07-29 15:38:15 +0000 | ||
| 3287 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c 2010-08-20 13:27:11 +0000 | ||
| 3288 | @@ -16,5 +16,5 @@ | ||
| 3289 | out_int8x16_t = vclzq_s8 (arg0_int8x16_t); | ||
| 3290 | } | ||
| 3291 | |||
| 3292 | -/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3293 | +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3294 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3295 | |||
| 3296 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQu16.c' | ||
| 3297 | --- old/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c 2010-07-29 15:38:15 +0000 | ||
| 3298 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c 2010-08-20 13:27:11 +0000 | ||
| 3299 | @@ -16,5 +16,5 @@ | ||
| 3300 | out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t); | ||
| 3301 | } | ||
| 3302 | |||
| 3303 | -/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3304 | +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3305 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3306 | |||
| 3307 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQu32.c' | ||
| 3308 | --- old/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c 2010-07-29 15:38:15 +0000 | ||
| 3309 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c 2010-08-20 13:27:11 +0000 | ||
| 3310 | @@ -16,5 +16,5 @@ | ||
| 3311 | out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t); | ||
| 3312 | } | ||
| 3313 | |||
| 3314 | -/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3315 | +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3316 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3317 | |||
| 3318 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclzQu8.c' | ||
| 3319 | --- old/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c 2010-07-29 15:38:15 +0000 | ||
| 3320 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c 2010-08-20 13:27:11 +0000 | ||
| 3321 | @@ -16,5 +16,5 @@ | ||
| 3322 | out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t); | ||
| 3323 | } | ||
| 3324 | |||
| 3325 | -/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3326 | +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3327 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3328 | |||
| 3329 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclzs16.c' | ||
| 3330 | --- old/gcc/testsuite/gcc.target/arm/neon/vclzs16.c 2010-07-29 15:38:15 +0000 | ||
| 3331 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclzs16.c 2010-08-20 13:27:11 +0000 | ||
| 3332 | @@ -16,5 +16,5 @@ | ||
| 3333 | out_int16x4_t = vclz_s16 (arg0_int16x4_t); | ||
| 3334 | } | ||
| 3335 | |||
| 3336 | -/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3337 | +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3338 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3339 | |||
| 3340 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclzs32.c' | ||
| 3341 | --- old/gcc/testsuite/gcc.target/arm/neon/vclzs32.c 2010-07-29 15:38:15 +0000 | ||
| 3342 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclzs32.c 2010-08-20 13:27:11 +0000 | ||
| 3343 | @@ -16,5 +16,5 @@ | ||
| 3344 | out_int32x2_t = vclz_s32 (arg0_int32x2_t); | ||
| 3345 | } | ||
| 3346 | |||
| 3347 | -/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3348 | +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3349 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3350 | |||
| 3351 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclzs8.c' | ||
| 3352 | --- old/gcc/testsuite/gcc.target/arm/neon/vclzs8.c 2010-07-29 15:38:15 +0000 | ||
| 3353 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclzs8.c 2010-08-20 13:27:11 +0000 | ||
| 3354 | @@ -16,5 +16,5 @@ | ||
| 3355 | out_int8x8_t = vclz_s8 (arg0_int8x8_t); | ||
| 3356 | } | ||
| 3357 | |||
| 3358 | -/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3359 | +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3360 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3361 | |||
| 3362 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclzu16.c' | ||
| 3363 | --- old/gcc/testsuite/gcc.target/arm/neon/vclzu16.c 2010-07-29 15:38:15 +0000 | ||
| 3364 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclzu16.c 2010-08-20 13:27:11 +0000 | ||
| 3365 | @@ -16,5 +16,5 @@ | ||
| 3366 | out_uint16x4_t = vclz_u16 (arg0_uint16x4_t); | ||
| 3367 | } | ||
| 3368 | |||
| 3369 | -/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3370 | +/* { dg-final { scan-assembler "vclz\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3371 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3372 | |||
| 3373 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclzu32.c' | ||
| 3374 | --- old/gcc/testsuite/gcc.target/arm/neon/vclzu32.c 2010-07-29 15:38:15 +0000 | ||
| 3375 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclzu32.c 2010-08-20 13:27:11 +0000 | ||
| 3376 | @@ -16,5 +16,5 @@ | ||
| 3377 | out_uint32x2_t = vclz_u32 (arg0_uint32x2_t); | ||
| 3378 | } | ||
| 3379 | |||
| 3380 | -/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3381 | +/* { dg-final { scan-assembler "vclz\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3382 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3383 | |||
| 3384 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vclzu8.c' | ||
| 3385 | --- old/gcc/testsuite/gcc.target/arm/neon/vclzu8.c 2010-07-29 15:38:15 +0000 | ||
| 3386 | +++ new/gcc/testsuite/gcc.target/arm/neon/vclzu8.c 2010-08-20 13:27:11 +0000 | ||
| 3387 | @@ -16,5 +16,5 @@ | ||
| 3388 | out_uint8x8_t = vclz_u8 (arg0_uint8x8_t); | ||
| 3389 | } | ||
| 3390 | |||
| 3391 | -/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3392 | +/* { dg-final { scan-assembler "vclz\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3393 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3394 | |||
| 3395 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcntQp8.c' | ||
| 3396 | --- old/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c 2010-07-29 15:38:15 +0000 | ||
| 3397 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c 2010-08-20 13:27:11 +0000 | ||
| 3398 | @@ -16,5 +16,5 @@ | ||
| 3399 | out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t); | ||
| 3400 | } | ||
| 3401 | |||
| 3402 | -/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3403 | +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3404 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3405 | |||
| 3406 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcntQs8.c' | ||
| 3407 | --- old/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c 2010-07-29 15:38:15 +0000 | ||
| 3408 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c 2010-08-20 13:27:11 +0000 | ||
| 3409 | @@ -16,5 +16,5 @@ | ||
| 3410 | out_int8x16_t = vcntq_s8 (arg0_int8x16_t); | ||
| 3411 | } | ||
| 3412 | |||
| 3413 | -/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3414 | +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3415 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3416 | |||
| 3417 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcntQu8.c' | ||
| 3418 | --- old/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c 2010-07-29 15:38:15 +0000 | ||
| 3419 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c 2010-08-20 13:27:11 +0000 | ||
| 3420 | @@ -16,5 +16,5 @@ | ||
| 3421 | out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t); | ||
| 3422 | } | ||
| 3423 | |||
| 3424 | -/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3425 | +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3426 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3427 | |||
| 3428 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcntp8.c' | ||
| 3429 | --- old/gcc/testsuite/gcc.target/arm/neon/vcntp8.c 2010-07-29 15:38:15 +0000 | ||
| 3430 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcntp8.c 2010-08-20 13:27:11 +0000 | ||
| 3431 | @@ -16,5 +16,5 @@ | ||
| 3432 | out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t); | ||
| 3433 | } | ||
| 3434 | |||
| 3435 | -/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3436 | +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3437 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3438 | |||
| 3439 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcnts8.c' | ||
| 3440 | --- old/gcc/testsuite/gcc.target/arm/neon/vcnts8.c 2010-07-29 15:38:15 +0000 | ||
| 3441 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcnts8.c 2010-08-20 13:27:11 +0000 | ||
| 3442 | @@ -16,5 +16,5 @@ | ||
| 3443 | out_int8x8_t = vcnt_s8 (arg0_int8x8_t); | ||
| 3444 | } | ||
| 3445 | |||
| 3446 | -/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3447 | +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3448 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3449 | |||
| 3450 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcntu8.c' | ||
| 3451 | --- old/gcc/testsuite/gcc.target/arm/neon/vcntu8.c 2010-07-29 15:38:15 +0000 | ||
| 3452 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcntu8.c 2010-08-20 13:27:11 +0000 | ||
| 3453 | @@ -16,5 +16,5 @@ | ||
| 3454 | out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t); | ||
| 3455 | } | ||
| 3456 | |||
| 3457 | -/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3458 | +/* { dg-final { scan-assembler "vcnt\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3459 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3460 | |||
| 3461 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c' | ||
| 3462 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c 2010-07-29 15:38:15 +0000 | ||
| 3463 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c 2010-08-20 13:27:11 +0000 | ||
| 3464 | @@ -16,5 +16,5 @@ | ||
| 3465 | out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1); | ||
| 3466 | } | ||
| 3467 | |||
| 3468 | -/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3469 | +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3470 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3471 | |||
| 3472 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c' | ||
| 3473 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c 2010-07-29 15:38:15 +0000 | ||
| 3474 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c 2010-08-20 13:27:11 +0000 | ||
| 3475 | @@ -16,5 +16,5 @@ | ||
| 3476 | out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1); | ||
| 3477 | } | ||
| 3478 | |||
| 3479 | -/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3480 | +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3481 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3482 | |||
| 3483 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c' | ||
| 3484 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c 2010-07-29 15:38:15 +0000 | ||
| 3485 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c 2010-08-20 13:27:11 +0000 | ||
| 3486 | @@ -16,5 +16,5 @@ | ||
| 3487 | out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1); | ||
| 3488 | } | ||
| 3489 | |||
| 3490 | -/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3491 | +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3492 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3493 | |||
| 3494 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c' | ||
| 3495 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c 2010-07-29 15:38:15 +0000 | ||
| 3496 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c 2010-08-20 13:27:11 +0000 | ||
| 3497 | @@ -16,5 +16,5 @@ | ||
| 3498 | out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1); | ||
| 3499 | } | ||
| 3500 | |||
| 3501 | -/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3502 | +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3503 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3504 | |||
| 3505 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c' | ||
| 3506 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c 2010-07-29 15:38:15 +0000 | ||
| 3507 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c 2010-08-20 13:27:11 +0000 | ||
| 3508 | @@ -16,5 +16,5 @@ | ||
| 3509 | out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t); | ||
| 3510 | } | ||
| 3511 | |||
| 3512 | -/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3513 | +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3514 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3515 | |||
| 3516 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c' | ||
| 3517 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c 2010-07-29 15:38:15 +0000 | ||
| 3518 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c 2010-08-20 13:27:11 +0000 | ||
| 3519 | @@ -16,5 +16,5 @@ | ||
| 3520 | out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t); | ||
| 3521 | } | ||
| 3522 | |||
| 3523 | -/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3524 | +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3525 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3526 | |||
| 3527 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c' | ||
| 3528 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c 2010-07-29 15:38:15 +0000 | ||
| 3529 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c 2010-08-20 13:27:11 +0000 | ||
| 3530 | @@ -16,5 +16,5 @@ | ||
| 3531 | out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t); | ||
| 3532 | } | ||
| 3533 | |||
| 3534 | -/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3535 | +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3536 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3537 | |||
| 3538 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c' | ||
| 3539 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c 2010-07-29 15:38:15 +0000 | ||
| 3540 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c 2010-08-20 13:27:11 +0000 | ||
| 3541 | @@ -16,5 +16,5 @@ | ||
| 3542 | out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t); | ||
| 3543 | } | ||
| 3544 | |||
| 3545 | -/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3546 | +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3547 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3548 | |||
| 3549 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c' | ||
| 3550 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c 2010-07-29 15:38:15 +0000 | ||
| 3551 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c 2010-08-20 13:27:11 +0000 | ||
| 3552 | @@ -16,5 +16,5 @@ | ||
| 3553 | out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1); | ||
| 3554 | } | ||
| 3555 | |||
| 3556 | -/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3557 | +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3558 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3559 | |||
| 3560 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c' | ||
| 3561 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c 2010-07-29 15:38:15 +0000 | ||
| 3562 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c 2010-08-20 13:27:11 +0000 | ||
| 3563 | @@ -16,5 +16,5 @@ | ||
| 3564 | out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1); | ||
| 3565 | } | ||
| 3566 | |||
| 3567 | -/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3568 | +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3569 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3570 | |||
| 3571 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c' | ||
| 3572 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c 2010-07-29 15:38:15 +0000 | ||
| 3573 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c 2010-08-20 13:27:11 +0000 | ||
| 3574 | @@ -16,5 +16,5 @@ | ||
| 3575 | out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1); | ||
| 3576 | } | ||
| 3577 | |||
| 3578 | -/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3579 | +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3580 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3581 | |||
| 3582 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c' | ||
| 3583 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c 2010-07-29 15:38:15 +0000 | ||
| 3584 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c 2010-08-20 13:27:11 +0000 | ||
| 3585 | @@ -16,5 +16,5 @@ | ||
| 3586 | out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1); | ||
| 3587 | } | ||
| 3588 | |||
| 3589 | -/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3590 | +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3591 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3592 | |||
| 3593 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c' | ||
| 3594 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c 2010-07-29 15:38:15 +0000 | ||
| 3595 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c 2010-08-20 13:27:11 +0000 | ||
| 3596 | @@ -16,5 +16,5 @@ | ||
| 3597 | out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t); | ||
| 3598 | } | ||
| 3599 | |||
| 3600 | -/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3601 | +/* { dg-final { scan-assembler "vcvt\.f32.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3602 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3603 | |||
| 3604 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c' | ||
| 3605 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c 2010-07-29 15:38:15 +0000 | ||
| 3606 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c 2010-08-20 13:27:11 +0000 | ||
| 3607 | @@ -16,5 +16,5 @@ | ||
| 3608 | out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t); | ||
| 3609 | } | ||
| 3610 | |||
| 3611 | -/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3612 | +/* { dg-final { scan-assembler "vcvt\.f32.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3613 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3614 | |||
| 3615 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c' | ||
| 3616 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c 2010-07-29 15:38:15 +0000 | ||
| 3617 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c 2010-08-20 13:27:11 +0000 | ||
| 3618 | @@ -16,5 +16,5 @@ | ||
| 3619 | out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t); | ||
| 3620 | } | ||
| 3621 | |||
| 3622 | -/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3623 | +/* { dg-final { scan-assembler "vcvt\.s32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3624 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3625 | |||
| 3626 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c' | ||
| 3627 | --- old/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c 2010-07-29 15:38:15 +0000 | ||
| 3628 | +++ new/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c 2010-08-20 13:27:11 +0000 | ||
| 3629 | @@ -16,5 +16,5 @@ | ||
| 3630 | out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t); | ||
| 3631 | } | ||
| 3632 | |||
| 3633 | -/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3634 | +/* { dg-final { scan-assembler "vcvt\.u32.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3635 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3636 | |||
| 3637 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c' | ||
| 3638 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 3639 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 3640 | @@ -16,5 +16,5 @@ | ||
| 3641 | out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1); | ||
| 3642 | } | ||
| 3643 | |||
| 3644 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3645 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3646 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3647 | |||
| 3648 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c' | ||
| 3649 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 3650 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 3651 | @@ -16,5 +16,5 @@ | ||
| 3652 | out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1); | ||
| 3653 | } | ||
| 3654 | |||
| 3655 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3656 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3657 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3658 | |||
| 3659 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c' | ||
| 3660 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 3661 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 3662 | @@ -16,5 +16,5 @@ | ||
| 3663 | out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1); | ||
| 3664 | } | ||
| 3665 | |||
| 3666 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3667 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3668 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3669 | |||
| 3670 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c' | ||
| 3671 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 3672 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 3673 | @@ -16,5 +16,5 @@ | ||
| 3674 | out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1); | ||
| 3675 | } | ||
| 3676 | |||
| 3677 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3678 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3679 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3680 | |||
| 3681 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c' | ||
| 3682 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 3683 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 3684 | @@ -16,5 +16,5 @@ | ||
| 3685 | out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1); | ||
| 3686 | } | ||
| 3687 | |||
| 3688 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3689 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3690 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3691 | |||
| 3692 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c' | ||
| 3693 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 3694 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 3695 | @@ -16,5 +16,5 @@ | ||
| 3696 | out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1); | ||
| 3697 | } | ||
| 3698 | |||
| 3699 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3700 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3701 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3702 | |||
| 3703 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c' | ||
| 3704 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 3705 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 3706 | @@ -16,5 +16,5 @@ | ||
| 3707 | out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1); | ||
| 3708 | } | ||
| 3709 | |||
| 3710 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3711 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3712 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3713 | |||
| 3714 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c' | ||
| 3715 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 3716 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 3717 | @@ -16,5 +16,5 @@ | ||
| 3718 | out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1); | ||
| 3719 | } | ||
| 3720 | |||
| 3721 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3722 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3723 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3724 | |||
| 3725 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c' | ||
| 3726 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 3727 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 3728 | @@ -16,5 +16,5 @@ | ||
| 3729 | out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1); | ||
| 3730 | } | ||
| 3731 | |||
| 3732 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3733 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3734 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3735 | |||
| 3736 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c' | ||
| 3737 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c 2010-07-29 15:38:15 +0000 | ||
| 3738 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c 2010-08-20 13:27:11 +0000 | ||
| 3739 | @@ -16,5 +16,5 @@ | ||
| 3740 | out_float32x4_t = vdupq_n_f32 (arg0_float32_t); | ||
| 3741 | } | ||
| 3742 | |||
| 3743 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3744 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3745 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3746 | |||
| 3747 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c' | ||
| 3748 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c 2010-07-29 15:38:15 +0000 | ||
| 3749 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c 2010-08-20 13:27:11 +0000 | ||
| 3750 | @@ -16,5 +16,5 @@ | ||
| 3751 | out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t); | ||
| 3752 | } | ||
| 3753 | |||
| 3754 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3755 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3756 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3757 | |||
| 3758 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c' | ||
| 3759 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c 2010-07-29 15:38:15 +0000 | ||
| 3760 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c 2010-08-20 13:27:11 +0000 | ||
| 3761 | @@ -16,5 +16,5 @@ | ||
| 3762 | out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t); | ||
| 3763 | } | ||
| 3764 | |||
| 3765 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3766 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3767 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3768 | |||
| 3769 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c' | ||
| 3770 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 3771 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 3772 | @@ -16,5 +16,5 @@ | ||
| 3773 | out_int16x8_t = vdupq_n_s16 (arg0_int16_t); | ||
| 3774 | } | ||
| 3775 | |||
| 3776 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3777 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3778 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3779 | |||
| 3780 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c' | ||
| 3781 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 3782 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 3783 | @@ -16,5 +16,5 @@ | ||
| 3784 | out_int32x4_t = vdupq_n_s32 (arg0_int32_t); | ||
| 3785 | } | ||
| 3786 | |||
| 3787 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3788 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3789 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3790 | |||
| 3791 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c' | ||
| 3792 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 3793 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 3794 | @@ -16,5 +16,5 @@ | ||
| 3795 | out_int8x16_t = vdupq_n_s8 (arg0_int8_t); | ||
| 3796 | } | ||
| 3797 | |||
| 3798 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3799 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3800 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3801 | |||
| 3802 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c' | ||
| 3803 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 3804 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 3805 | @@ -16,5 +16,5 @@ | ||
| 3806 | out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t); | ||
| 3807 | } | ||
| 3808 | |||
| 3809 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3810 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3811 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3812 | |||
| 3813 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c' | ||
| 3814 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 3815 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 3816 | @@ -16,5 +16,5 @@ | ||
| 3817 | out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t); | ||
| 3818 | } | ||
| 3819 | |||
| 3820 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3821 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3822 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3823 | |||
| 3824 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c' | ||
| 3825 | --- old/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 3826 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 3827 | @@ -16,5 +16,5 @@ | ||
| 3828 | out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t); | ||
| 3829 | } | ||
| 3830 | |||
| 3831 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3832 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3833 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3834 | |||
| 3835 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c' | ||
| 3836 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 3837 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 3838 | @@ -16,5 +16,5 @@ | ||
| 3839 | out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1); | ||
| 3840 | } | ||
| 3841 | |||
| 3842 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3843 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3844 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3845 | |||
| 3846 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c' | ||
| 3847 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 3848 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 3849 | @@ -16,5 +16,5 @@ | ||
| 3850 | out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1); | ||
| 3851 | } | ||
| 3852 | |||
| 3853 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3854 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3855 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3856 | |||
| 3857 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c' | ||
| 3858 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 3859 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 3860 | @@ -16,5 +16,5 @@ | ||
| 3861 | out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1); | ||
| 3862 | } | ||
| 3863 | |||
| 3864 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3865 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3866 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3867 | |||
| 3868 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c' | ||
| 3869 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 3870 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 3871 | @@ -16,5 +16,5 @@ | ||
| 3872 | out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1); | ||
| 3873 | } | ||
| 3874 | |||
| 3875 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3876 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3877 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3878 | |||
| 3879 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c' | ||
| 3880 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 3881 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 3882 | @@ -16,5 +16,5 @@ | ||
| 3883 | out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1); | ||
| 3884 | } | ||
| 3885 | |||
| 3886 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3887 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3888 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3889 | |||
| 3890 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c' | ||
| 3891 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 3892 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 3893 | @@ -16,5 +16,5 @@ | ||
| 3894 | out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1); | ||
| 3895 | } | ||
| 3896 | |||
| 3897 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3898 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3899 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3900 | |||
| 3901 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c' | ||
| 3902 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 3903 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 3904 | @@ -16,5 +16,5 @@ | ||
| 3905 | out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1); | ||
| 3906 | } | ||
| 3907 | |||
| 3908 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3909 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3910 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3911 | |||
| 3912 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c' | ||
| 3913 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 3914 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 3915 | @@ -16,5 +16,5 @@ | ||
| 3916 | out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1); | ||
| 3917 | } | ||
| 3918 | |||
| 3919 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3920 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3921 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3922 | |||
| 3923 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c' | ||
| 3924 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 3925 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 3926 | @@ -16,5 +16,5 @@ | ||
| 3927 | out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1); | ||
| 3928 | } | ||
| 3929 | |||
| 3930 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3931 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3932 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3933 | |||
| 3934 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c' | ||
| 3935 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c 2010-07-29 15:38:15 +0000 | ||
| 3936 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c 2010-08-20 13:27:11 +0000 | ||
| 3937 | @@ -16,5 +16,5 @@ | ||
| 3938 | out_float32x2_t = vdup_n_f32 (arg0_float32_t); | ||
| 3939 | } | ||
| 3940 | |||
| 3941 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3942 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3943 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3944 | |||
| 3945 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_np16.c' | ||
| 3946 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c 2010-07-29 15:38:15 +0000 | ||
| 3947 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c 2010-08-20 13:27:11 +0000 | ||
| 3948 | @@ -16,5 +16,5 @@ | ||
| 3949 | out_poly16x4_t = vdup_n_p16 (arg0_poly16_t); | ||
| 3950 | } | ||
| 3951 | |||
| 3952 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3953 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3954 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3955 | |||
| 3956 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_np8.c' | ||
| 3957 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c 2010-07-29 15:38:15 +0000 | ||
| 3958 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c 2010-08-20 13:27:11 +0000 | ||
| 3959 | @@ -16,5 +16,5 @@ | ||
| 3960 | out_poly8x8_t = vdup_n_p8 (arg0_poly8_t); | ||
| 3961 | } | ||
| 3962 | |||
| 3963 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3964 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3965 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3966 | |||
| 3967 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c' | ||
| 3968 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 3969 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 3970 | @@ -16,5 +16,5 @@ | ||
| 3971 | out_int16x4_t = vdup_n_s16 (arg0_int16_t); | ||
| 3972 | } | ||
| 3973 | |||
| 3974 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3975 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3976 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3977 | |||
| 3978 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c' | ||
| 3979 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 3980 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 3981 | @@ -16,5 +16,5 @@ | ||
| 3982 | out_int32x2_t = vdup_n_s32 (arg0_int32_t); | ||
| 3983 | } | ||
| 3984 | |||
| 3985 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3986 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3987 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3988 | |||
| 3989 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c' | ||
| 3990 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 3991 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 3992 | @@ -16,5 +16,5 @@ | ||
| 3993 | out_int8x8_t = vdup_n_s8 (arg0_int8_t); | ||
| 3994 | } | ||
| 3995 | |||
| 3996 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 3997 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3998 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3999 | |||
| 4000 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c' | ||
| 4001 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 4002 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 4003 | @@ -16,5 +16,5 @@ | ||
| 4004 | out_uint16x4_t = vdup_n_u16 (arg0_uint16_t); | ||
| 4005 | } | ||
| 4006 | |||
| 4007 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4008 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4009 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4010 | |||
| 4011 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c' | ||
| 4012 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 4013 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 4014 | @@ -16,5 +16,5 @@ | ||
| 4015 | out_uint32x2_t = vdup_n_u32 (arg0_uint32_t); | ||
| 4016 | } | ||
| 4017 | |||
| 4018 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4019 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4020 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4021 | |||
| 4022 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c' | ||
| 4023 | --- old/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 4024 | +++ new/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 4025 | @@ -16,5 +16,5 @@ | ||
| 4026 | out_uint8x8_t = vdup_n_u8 (arg0_uint8_t); | ||
| 4027 | } | ||
| 4028 | |||
| 4029 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4030 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4031 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4032 | |||
| 4033 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs16.c' | ||
| 4034 | --- old/gcc/testsuite/gcc.target/arm/neon/veorQs16.c 2010-07-29 15:38:15 +0000 | ||
| 4035 | +++ new/gcc/testsuite/gcc.target/arm/neon/veorQs16.c 2010-08-20 13:27:11 +0000 | ||
| 4036 | @@ -17,5 +17,5 @@ | ||
| 4037 | out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 4038 | } | ||
| 4039 | |||
| 4040 | -/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4041 | +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4042 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4043 | |||
| 4044 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs32.c' | ||
| 4045 | --- old/gcc/testsuite/gcc.target/arm/neon/veorQs32.c 2010-07-29 15:38:15 +0000 | ||
| 4046 | +++ new/gcc/testsuite/gcc.target/arm/neon/veorQs32.c 2010-08-20 13:27:11 +0000 | ||
| 4047 | @@ -17,5 +17,5 @@ | ||
| 4048 | out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 4049 | } | ||
| 4050 | |||
| 4051 | -/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4052 | +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4053 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4054 | |||
| 4055 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs64.c' | ||
| 4056 | --- old/gcc/testsuite/gcc.target/arm/neon/veorQs64.c 2010-07-29 15:38:15 +0000 | ||
| 4057 | +++ new/gcc/testsuite/gcc.target/arm/neon/veorQs64.c 2010-08-20 13:27:11 +0000 | ||
| 4058 | @@ -17,5 +17,5 @@ | ||
| 4059 | out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 4060 | } | ||
| 4061 | |||
| 4062 | -/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4063 | +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4064 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4065 | |||
| 4066 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veorQs8.c' | ||
| 4067 | --- old/gcc/testsuite/gcc.target/arm/neon/veorQs8.c 2010-07-29 15:38:15 +0000 | ||
| 4068 | +++ new/gcc/testsuite/gcc.target/arm/neon/veorQs8.c 2010-08-20 13:27:11 +0000 | ||
| 4069 | @@ -17,5 +17,5 @@ | ||
| 4070 | out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 4071 | } | ||
| 4072 | |||
| 4073 | -/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4074 | +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4075 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4076 | |||
| 4077 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu16.c' | ||
| 4078 | --- old/gcc/testsuite/gcc.target/arm/neon/veorQu16.c 2010-07-29 15:38:15 +0000 | ||
| 4079 | +++ new/gcc/testsuite/gcc.target/arm/neon/veorQu16.c 2010-08-20 13:27:11 +0000 | ||
| 4080 | @@ -17,5 +17,5 @@ | ||
| 4081 | out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 4082 | } | ||
| 4083 | |||
| 4084 | -/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4085 | +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4086 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4087 | |||
| 4088 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu32.c' | ||
| 4089 | --- old/gcc/testsuite/gcc.target/arm/neon/veorQu32.c 2010-07-29 15:38:15 +0000 | ||
| 4090 | +++ new/gcc/testsuite/gcc.target/arm/neon/veorQu32.c 2010-08-20 13:27:11 +0000 | ||
| 4091 | @@ -17,5 +17,5 @@ | ||
| 4092 | out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 4093 | } | ||
| 4094 | |||
| 4095 | -/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4096 | +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4097 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4098 | |||
| 4099 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu64.c' | ||
| 4100 | --- old/gcc/testsuite/gcc.target/arm/neon/veorQu64.c 2010-07-29 15:38:15 +0000 | ||
| 4101 | +++ new/gcc/testsuite/gcc.target/arm/neon/veorQu64.c 2010-08-20 13:27:11 +0000 | ||
| 4102 | @@ -17,5 +17,5 @@ | ||
| 4103 | out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 4104 | } | ||
| 4105 | |||
| 4106 | -/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4107 | +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4108 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4109 | |||
| 4110 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veorQu8.c' | ||
| 4111 | --- old/gcc/testsuite/gcc.target/arm/neon/veorQu8.c 2010-07-29 15:38:15 +0000 | ||
| 4112 | +++ new/gcc/testsuite/gcc.target/arm/neon/veorQu8.c 2010-08-20 13:27:11 +0000 | ||
| 4113 | @@ -17,5 +17,5 @@ | ||
| 4114 | out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 4115 | } | ||
| 4116 | |||
| 4117 | -/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4118 | +/* { dg-final { scan-assembler "veor\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4119 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4120 | |||
| 4121 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veors16.c' | ||
| 4122 | --- old/gcc/testsuite/gcc.target/arm/neon/veors16.c 2010-07-29 15:38:15 +0000 | ||
| 4123 | +++ new/gcc/testsuite/gcc.target/arm/neon/veors16.c 2010-08-20 13:27:11 +0000 | ||
| 4124 | @@ -17,5 +17,5 @@ | ||
| 4125 | out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 4126 | } | ||
| 4127 | |||
| 4128 | -/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4129 | +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4130 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4131 | |||
| 4132 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veors32.c' | ||
| 4133 | --- old/gcc/testsuite/gcc.target/arm/neon/veors32.c 2010-07-29 15:38:15 +0000 | ||
| 4134 | +++ new/gcc/testsuite/gcc.target/arm/neon/veors32.c 2010-08-20 13:27:11 +0000 | ||
| 4135 | @@ -17,5 +17,5 @@ | ||
| 4136 | out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 4137 | } | ||
| 4138 | |||
| 4139 | -/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4140 | +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4141 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4142 | |||
| 4143 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veors8.c' | ||
| 4144 | --- old/gcc/testsuite/gcc.target/arm/neon/veors8.c 2010-07-29 15:38:15 +0000 | ||
| 4145 | +++ new/gcc/testsuite/gcc.target/arm/neon/veors8.c 2010-08-20 13:27:11 +0000 | ||
| 4146 | @@ -17,5 +17,5 @@ | ||
| 4147 | out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 4148 | } | ||
| 4149 | |||
| 4150 | -/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4151 | +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4152 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4153 | |||
| 4154 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veoru16.c' | ||
| 4155 | --- old/gcc/testsuite/gcc.target/arm/neon/veoru16.c 2010-07-29 15:38:15 +0000 | ||
| 4156 | +++ new/gcc/testsuite/gcc.target/arm/neon/veoru16.c 2010-08-20 13:27:11 +0000 | ||
| 4157 | @@ -17,5 +17,5 @@ | ||
| 4158 | out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 4159 | } | ||
| 4160 | |||
| 4161 | -/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4162 | +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4163 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4164 | |||
| 4165 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veoru32.c' | ||
| 4166 | --- old/gcc/testsuite/gcc.target/arm/neon/veoru32.c 2010-07-29 15:38:15 +0000 | ||
| 4167 | +++ new/gcc/testsuite/gcc.target/arm/neon/veoru32.c 2010-08-20 13:27:11 +0000 | ||
| 4168 | @@ -17,5 +17,5 @@ | ||
| 4169 | out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 4170 | } | ||
| 4171 | |||
| 4172 | -/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4173 | +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4174 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4175 | |||
| 4176 | === modified file 'gcc/testsuite/gcc.target/arm/neon/veoru8.c' | ||
| 4177 | --- old/gcc/testsuite/gcc.target/arm/neon/veoru8.c 2010-07-29 15:38:15 +0000 | ||
| 4178 | +++ new/gcc/testsuite/gcc.target/arm/neon/veoru8.c 2010-08-20 13:27:11 +0000 | ||
| 4179 | @@ -17,5 +17,5 @@ | ||
| 4180 | out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 4181 | } | ||
| 4182 | |||
| 4183 | -/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4184 | +/* { dg-final { scan-assembler "veor\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4185 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4186 | |||
| 4187 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextQf32.c' | ||
| 4188 | --- old/gcc/testsuite/gcc.target/arm/neon/vextQf32.c 2010-07-29 15:38:15 +0000 | ||
| 4189 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextQf32.c 2010-08-20 13:27:11 +0000 | ||
| 4190 | @@ -17,5 +17,5 @@ | ||
| 4191 | out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0); | ||
| 4192 | } | ||
| 4193 | |||
| 4194 | -/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4195 | +/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4196 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4197 | |||
| 4198 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextQp16.c' | ||
| 4199 | --- old/gcc/testsuite/gcc.target/arm/neon/vextQp16.c 2010-07-29 15:38:15 +0000 | ||
| 4200 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextQp16.c 2010-08-20 13:27:11 +0000 | ||
| 4201 | @@ -17,5 +17,5 @@ | ||
| 4202 | out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0); | ||
| 4203 | } | ||
| 4204 | |||
| 4205 | -/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4206 | +/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4207 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4208 | |||
| 4209 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextQp8.c' | ||
| 4210 | --- old/gcc/testsuite/gcc.target/arm/neon/vextQp8.c 2010-07-29 15:38:15 +0000 | ||
| 4211 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextQp8.c 2010-08-20 13:27:11 +0000 | ||
| 4212 | @@ -17,5 +17,5 @@ | ||
| 4213 | out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0); | ||
| 4214 | } | ||
| 4215 | |||
| 4216 | -/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4217 | +/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4218 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4219 | |||
| 4220 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs16.c' | ||
| 4221 | --- old/gcc/testsuite/gcc.target/arm/neon/vextQs16.c 2010-07-29 15:38:15 +0000 | ||
| 4222 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextQs16.c 2010-08-20 13:27:11 +0000 | ||
| 4223 | @@ -17,5 +17,5 @@ | ||
| 4224 | out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0); | ||
| 4225 | } | ||
| 4226 | |||
| 4227 | -/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4228 | +/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4229 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4230 | |||
| 4231 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs32.c' | ||
| 4232 | --- old/gcc/testsuite/gcc.target/arm/neon/vextQs32.c 2010-07-29 15:38:15 +0000 | ||
| 4233 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextQs32.c 2010-08-20 13:27:11 +0000 | ||
| 4234 | @@ -17,5 +17,5 @@ | ||
| 4235 | out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0); | ||
| 4236 | } | ||
| 4237 | |||
| 4238 | -/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4239 | +/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4240 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4241 | |||
| 4242 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs64.c' | ||
| 4243 | --- old/gcc/testsuite/gcc.target/arm/neon/vextQs64.c 2010-07-29 15:38:15 +0000 | ||
| 4244 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextQs64.c 2010-08-20 13:27:11 +0000 | ||
| 4245 | @@ -17,5 +17,5 @@ | ||
| 4246 | out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0); | ||
| 4247 | } | ||
| 4248 | |||
| 4249 | -/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4250 | +/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4251 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4252 | |||
| 4253 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextQs8.c' | ||
| 4254 | --- old/gcc/testsuite/gcc.target/arm/neon/vextQs8.c 2010-07-29 15:38:15 +0000 | ||
| 4255 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextQs8.c 2010-08-20 13:27:11 +0000 | ||
| 4256 | @@ -17,5 +17,5 @@ | ||
| 4257 | out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0); | ||
| 4258 | } | ||
| 4259 | |||
| 4260 | -/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4261 | +/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4262 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4263 | |||
| 4264 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu16.c' | ||
| 4265 | --- old/gcc/testsuite/gcc.target/arm/neon/vextQu16.c 2010-07-29 15:38:15 +0000 | ||
| 4266 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextQu16.c 2010-08-20 13:27:11 +0000 | ||
| 4267 | @@ -17,5 +17,5 @@ | ||
| 4268 | out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0); | ||
| 4269 | } | ||
| 4270 | |||
| 4271 | -/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4272 | +/* { dg-final { scan-assembler "vext\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4273 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4274 | |||
| 4275 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu32.c' | ||
| 4276 | --- old/gcc/testsuite/gcc.target/arm/neon/vextQu32.c 2010-07-29 15:38:15 +0000 | ||
| 4277 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextQu32.c 2010-08-20 13:27:11 +0000 | ||
| 4278 | @@ -17,5 +17,5 @@ | ||
| 4279 | out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0); | ||
| 4280 | } | ||
| 4281 | |||
| 4282 | -/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4283 | +/* { dg-final { scan-assembler "vext\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4284 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4285 | |||
| 4286 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu64.c' | ||
| 4287 | --- old/gcc/testsuite/gcc.target/arm/neon/vextQu64.c 2010-07-29 15:38:15 +0000 | ||
| 4288 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextQu64.c 2010-08-20 13:27:11 +0000 | ||
| 4289 | @@ -17,5 +17,5 @@ | ||
| 4290 | out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0); | ||
| 4291 | } | ||
| 4292 | |||
| 4293 | -/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4294 | +/* { dg-final { scan-assembler "vext\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4295 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4296 | |||
| 4297 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextQu8.c' | ||
| 4298 | --- old/gcc/testsuite/gcc.target/arm/neon/vextQu8.c 2010-07-29 15:38:15 +0000 | ||
| 4299 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextQu8.c 2010-08-20 13:27:11 +0000 | ||
| 4300 | @@ -17,5 +17,5 @@ | ||
| 4301 | out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0); | ||
| 4302 | } | ||
| 4303 | |||
| 4304 | -/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4305 | +/* { dg-final { scan-assembler "vext\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4306 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4307 | |||
| 4308 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextf32.c' | ||
| 4309 | --- old/gcc/testsuite/gcc.target/arm/neon/vextf32.c 2010-07-29 15:38:15 +0000 | ||
| 4310 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextf32.c 2010-08-20 13:27:11 +0000 | ||
| 4311 | @@ -17,5 +17,5 @@ | ||
| 4312 | out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0); | ||
| 4313 | } | ||
| 4314 | |||
| 4315 | -/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4316 | +/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4317 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4318 | |||
| 4319 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextp16.c' | ||
| 4320 | --- old/gcc/testsuite/gcc.target/arm/neon/vextp16.c 2010-07-29 15:38:15 +0000 | ||
| 4321 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextp16.c 2010-08-20 13:27:11 +0000 | ||
| 4322 | @@ -17,5 +17,5 @@ | ||
| 4323 | out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0); | ||
| 4324 | } | ||
| 4325 | |||
| 4326 | -/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4327 | +/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4328 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4329 | |||
| 4330 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextp8.c' | ||
| 4331 | --- old/gcc/testsuite/gcc.target/arm/neon/vextp8.c 2010-07-29 15:38:15 +0000 | ||
| 4332 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextp8.c 2010-08-20 13:27:11 +0000 | ||
| 4333 | @@ -17,5 +17,5 @@ | ||
| 4334 | out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0); | ||
| 4335 | } | ||
| 4336 | |||
| 4337 | -/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4338 | +/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4339 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4340 | |||
| 4341 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vexts16.c' | ||
| 4342 | --- old/gcc/testsuite/gcc.target/arm/neon/vexts16.c 2010-07-29 15:38:15 +0000 | ||
| 4343 | +++ new/gcc/testsuite/gcc.target/arm/neon/vexts16.c 2010-08-20 13:27:11 +0000 | ||
| 4344 | @@ -17,5 +17,5 @@ | ||
| 4345 | out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0); | ||
| 4346 | } | ||
| 4347 | |||
| 4348 | -/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4349 | +/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4350 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4351 | |||
| 4352 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vexts32.c' | ||
| 4353 | --- old/gcc/testsuite/gcc.target/arm/neon/vexts32.c 2010-07-29 15:38:15 +0000 | ||
| 4354 | +++ new/gcc/testsuite/gcc.target/arm/neon/vexts32.c 2010-08-20 13:27:11 +0000 | ||
| 4355 | @@ -17,5 +17,5 @@ | ||
| 4356 | out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0); | ||
| 4357 | } | ||
| 4358 | |||
| 4359 | -/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4360 | +/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4361 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4362 | |||
| 4363 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vexts64.c' | ||
| 4364 | --- old/gcc/testsuite/gcc.target/arm/neon/vexts64.c 2010-07-29 15:38:15 +0000 | ||
| 4365 | +++ new/gcc/testsuite/gcc.target/arm/neon/vexts64.c 2010-08-20 13:27:11 +0000 | ||
| 4366 | @@ -17,5 +17,5 @@ | ||
| 4367 | out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0); | ||
| 4368 | } | ||
| 4369 | |||
| 4370 | -/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4371 | +/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4372 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4373 | |||
| 4374 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vexts8.c' | ||
| 4375 | --- old/gcc/testsuite/gcc.target/arm/neon/vexts8.c 2010-07-29 15:38:15 +0000 | ||
| 4376 | +++ new/gcc/testsuite/gcc.target/arm/neon/vexts8.c 2010-08-20 13:27:11 +0000 | ||
| 4377 | @@ -17,5 +17,5 @@ | ||
| 4378 | out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0); | ||
| 4379 | } | ||
| 4380 | |||
| 4381 | -/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4382 | +/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4383 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4384 | |||
| 4385 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextu16.c' | ||
| 4386 | --- old/gcc/testsuite/gcc.target/arm/neon/vextu16.c 2010-07-29 15:38:15 +0000 | ||
| 4387 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextu16.c 2010-08-20 13:27:11 +0000 | ||
| 4388 | @@ -17,5 +17,5 @@ | ||
| 4389 | out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0); | ||
| 4390 | } | ||
| 4391 | |||
| 4392 | -/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4393 | +/* { dg-final { scan-assembler "vext\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4394 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4395 | |||
| 4396 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextu32.c' | ||
| 4397 | --- old/gcc/testsuite/gcc.target/arm/neon/vextu32.c 2010-07-29 15:38:15 +0000 | ||
| 4398 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextu32.c 2010-08-20 13:27:11 +0000 | ||
| 4399 | @@ -17,5 +17,5 @@ | ||
| 4400 | out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0); | ||
| 4401 | } | ||
| 4402 | |||
| 4403 | -/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4404 | +/* { dg-final { scan-assembler "vext\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4405 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4406 | |||
| 4407 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextu64.c' | ||
| 4408 | --- old/gcc/testsuite/gcc.target/arm/neon/vextu64.c 2010-07-29 15:38:15 +0000 | ||
| 4409 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextu64.c 2010-08-20 13:27:11 +0000 | ||
| 4410 | @@ -17,5 +17,5 @@ | ||
| 4411 | out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0); | ||
| 4412 | } | ||
| 4413 | |||
| 4414 | -/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4415 | +/* { dg-final { scan-assembler "vext\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4416 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4417 | |||
| 4418 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vextu8.c' | ||
| 4419 | --- old/gcc/testsuite/gcc.target/arm/neon/vextu8.c 2010-07-29 15:38:15 +0000 | ||
| 4420 | +++ new/gcc/testsuite/gcc.target/arm/neon/vextu8.c 2010-08-20 13:27:11 +0000 | ||
| 4421 | @@ -17,5 +17,5 @@ | ||
| 4422 | out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0); | ||
| 4423 | } | ||
| 4424 | |||
| 4425 | -/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4426 | +/* { dg-final { scan-assembler "vext\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4427 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4428 | |||
| 4429 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c' | ||
| 4430 | --- old/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c 2010-07-29 15:38:15 +0000 | ||
| 4431 | +++ new/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c 2010-08-20 13:27:11 +0000 | ||
| 4432 | @@ -22,7 +22,7 @@ | ||
| 4433 | return vshll_n_u32(a, 32); | ||
| 4434 | } | ||
| 4435 | |||
| 4436 | -/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4437 | -/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4438 | -/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4439 | +/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4440 | +/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4441 | +/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4442 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4443 | |||
| 4444 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c' | ||
| 4445 | --- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 4446 | +++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 4447 | @@ -16,5 +16,5 @@ | ||
| 4448 | out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1); | ||
| 4449 | } | ||
| 4450 | |||
| 4451 | -/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4452 | +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4453 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4454 | |||
| 4455 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c' | ||
| 4456 | --- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 4457 | +++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 4458 | @@ -16,5 +16,5 @@ | ||
| 4459 | out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1); | ||
| 4460 | } | ||
| 4461 | |||
| 4462 | -/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4463 | +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4464 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4465 | |||
| 4466 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c' | ||
| 4467 | --- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 4468 | +++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 4469 | @@ -16,5 +16,5 @@ | ||
| 4470 | out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1); | ||
| 4471 | } | ||
| 4472 | |||
| 4473 | -/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4474 | +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4475 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4476 | |||
| 4477 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c' | ||
| 4478 | --- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 4479 | +++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 4480 | @@ -16,5 +16,5 @@ | ||
| 4481 | out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1); | ||
| 4482 | } | ||
| 4483 | |||
| 4484 | -/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4485 | +/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4486 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4487 | |||
| 4488 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c' | ||
| 4489 | --- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 4490 | +++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 4491 | @@ -16,5 +16,5 @@ | ||
| 4492 | out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1); | ||
| 4493 | } | ||
| 4494 | |||
| 4495 | -/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4496 | +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4497 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4498 | |||
| 4499 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c' | ||
| 4500 | --- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c 2010-07-29 15:38:15 +0000 | ||
| 4501 | +++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c 2010-08-20 13:27:11 +0000 | ||
| 4502 | @@ -16,5 +16,5 @@ | ||
| 4503 | out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0); | ||
| 4504 | } | ||
| 4505 | |||
| 4506 | -/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4507 | +/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4508 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4509 | |||
| 4510 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c' | ||
| 4511 | --- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 4512 | +++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 4513 | @@ -16,5 +16,5 @@ | ||
| 4514 | out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1); | ||
| 4515 | } | ||
| 4516 | |||
| 4517 | -/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4518 | +/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4519 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4520 | |||
| 4521 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c' | ||
| 4522 | --- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 4523 | +++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 4524 | @@ -16,5 +16,5 @@ | ||
| 4525 | out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1); | ||
| 4526 | } | ||
| 4527 | |||
| 4528 | -/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4529 | +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4530 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4531 | |||
| 4532 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c' | ||
| 4533 | --- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 4534 | +++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 4535 | @@ -16,5 +16,5 @@ | ||
| 4536 | out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1); | ||
| 4537 | } | ||
| 4538 | |||
| 4539 | -/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4540 | +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4541 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4542 | |||
| 4543 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c' | ||
| 4544 | --- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c 2010-07-29 15:38:15 +0000 | ||
| 4545 | +++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c 2010-08-20 13:27:11 +0000 | ||
| 4546 | @@ -16,5 +16,5 @@ | ||
| 4547 | out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0); | ||
| 4548 | } | ||
| 4549 | |||
| 4550 | -/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4551 | +/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4552 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4553 | |||
| 4554 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c' | ||
| 4555 | --- old/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 4556 | +++ new/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 4557 | @@ -16,5 +16,5 @@ | ||
| 4558 | out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1); | ||
| 4559 | } | ||
| 4560 | |||
| 4561 | -/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4562 | +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4563 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4564 | |||
| 4565 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c' | ||
| 4566 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 4567 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 4568 | @@ -16,5 +16,5 @@ | ||
| 4569 | out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1); | ||
| 4570 | } | ||
| 4571 | |||
| 4572 | -/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4573 | +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4574 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4575 | |||
| 4576 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c' | ||
| 4577 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 4578 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 4579 | @@ -16,5 +16,5 @@ | ||
| 4580 | out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1); | ||
| 4581 | } | ||
| 4582 | |||
| 4583 | -/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4584 | +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4585 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4586 | |||
| 4587 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c' | ||
| 4588 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 4589 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 4590 | @@ -16,5 +16,5 @@ | ||
| 4591 | out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1); | ||
| 4592 | } | ||
| 4593 | |||
| 4594 | -/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4595 | +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4596 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4597 | |||
| 4598 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c' | ||
| 4599 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 4600 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 4601 | @@ -16,5 +16,5 @@ | ||
| 4602 | out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1); | ||
| 4603 | } | ||
| 4604 | |||
| 4605 | -/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4606 | +/* { dg-final { scan-assembler "vmov\.s16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4607 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4608 | |||
| 4609 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c' | ||
| 4610 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 4611 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 4612 | @@ -16,5 +16,5 @@ | ||
| 4613 | out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1); | ||
| 4614 | } | ||
| 4615 | |||
| 4616 | -/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4617 | +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4618 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4619 | |||
| 4620 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c' | ||
| 4621 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 4622 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 4623 | @@ -16,5 +16,5 @@ | ||
| 4624 | out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1); | ||
| 4625 | } | ||
| 4626 | |||
| 4627 | -/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4628 | +/* { dg-final { scan-assembler "vmov\.s8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4629 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4630 | |||
| 4631 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c' | ||
| 4632 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 4633 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 4634 | @@ -16,5 +16,5 @@ | ||
| 4635 | out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1); | ||
| 4636 | } | ||
| 4637 | |||
| 4638 | -/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4639 | +/* { dg-final { scan-assembler "vmov\.u16\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4640 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4641 | |||
| 4642 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c' | ||
| 4643 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 4644 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 4645 | @@ -16,5 +16,5 @@ | ||
| 4646 | out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1); | ||
| 4647 | } | ||
| 4648 | |||
| 4649 | -/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4650 | +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4651 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4652 | |||
| 4653 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c' | ||
| 4654 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 4655 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 4656 | @@ -16,5 +16,5 @@ | ||
| 4657 | out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1); | ||
| 4658 | } | ||
| 4659 | |||
| 4660 | -/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4661 | +/* { dg-final { scan-assembler "vmov\.u8\[ \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4662 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4663 | |||
| 4664 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c' | ||
| 4665 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c 2010-07-29 15:38:15 +0000 | ||
| 4666 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c 2010-08-20 13:27:11 +0000 | ||
| 4667 | @@ -16,5 +16,5 @@ | ||
| 4668 | out_float32x2_t = vget_low_f32 (arg0_float32x4_t); | ||
| 4669 | } | ||
| 4670 | |||
| 4671 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4672 | +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4673 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4674 | |||
| 4675 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c' | ||
| 4676 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c 2010-07-29 15:38:15 +0000 | ||
| 4677 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c 2010-08-20 13:27:11 +0000 | ||
| 4678 | @@ -16,5 +16,5 @@ | ||
| 4679 | out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t); | ||
| 4680 | } | ||
| 4681 | |||
| 4682 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4683 | +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4684 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4685 | |||
| 4686 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c' | ||
| 4687 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c 2010-07-29 15:38:15 +0000 | ||
| 4688 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c 2010-08-20 13:27:11 +0000 | ||
| 4689 | @@ -16,5 +16,5 @@ | ||
| 4690 | out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t); | ||
| 4691 | } | ||
| 4692 | |||
| 4693 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4694 | +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4695 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4696 | |||
| 4697 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows16.c' | ||
| 4698 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c 2010-07-29 15:38:15 +0000 | ||
| 4699 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c 2010-08-20 13:27:11 +0000 | ||
| 4700 | @@ -16,5 +16,5 @@ | ||
| 4701 | out_int16x4_t = vget_low_s16 (arg0_int16x8_t); | ||
| 4702 | } | ||
| 4703 | |||
| 4704 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4705 | +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4706 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4707 | |||
| 4708 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows32.c' | ||
| 4709 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c 2010-07-29 15:38:15 +0000 | ||
| 4710 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c 2010-08-20 13:27:11 +0000 | ||
| 4711 | @@ -16,5 +16,5 @@ | ||
| 4712 | out_int32x2_t = vget_low_s32 (arg0_int32x4_t); | ||
| 4713 | } | ||
| 4714 | |||
| 4715 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4716 | +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4717 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4718 | |||
| 4719 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lows8.c' | ||
| 4720 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c 2010-07-29 15:38:15 +0000 | ||
| 4721 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c 2010-08-20 13:27:11 +0000 | ||
| 4722 | @@ -16,5 +16,5 @@ | ||
| 4723 | out_int8x8_t = vget_low_s8 (arg0_int8x16_t); | ||
| 4724 | } | ||
| 4725 | |||
| 4726 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4727 | +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4728 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4729 | |||
| 4730 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c' | ||
| 4731 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c 2010-07-29 15:38:15 +0000 | ||
| 4732 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c 2010-08-20 13:27:11 +0000 | ||
| 4733 | @@ -16,5 +16,5 @@ | ||
| 4734 | out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t); | ||
| 4735 | } | ||
| 4736 | |||
| 4737 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4738 | +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4739 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4740 | |||
| 4741 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c' | ||
| 4742 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c 2010-07-29 15:38:15 +0000 | ||
| 4743 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c 2010-08-20 13:27:11 +0000 | ||
| 4744 | @@ -16,5 +16,5 @@ | ||
| 4745 | out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t); | ||
| 4746 | } | ||
| 4747 | |||
| 4748 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4749 | +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4750 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4751 | |||
| 4752 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c' | ||
| 4753 | --- old/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c 2010-07-29 15:38:15 +0000 | ||
| 4754 | +++ new/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c 2010-08-20 13:27:11 +0000 | ||
| 4755 | @@ -16,5 +16,5 @@ | ||
| 4756 | out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t); | ||
| 4757 | } | ||
| 4758 | |||
| 4759 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4760 | +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4761 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4762 | |||
| 4763 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c' | ||
| 4764 | --- old/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c 2010-07-29 15:38:15 +0000 | ||
| 4765 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c 2010-08-20 13:27:11 +0000 | ||
| 4766 | @@ -17,5 +17,5 @@ | ||
| 4767 | out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 4768 | } | ||
| 4769 | |||
| 4770 | -/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4771 | +/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4772 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4773 | |||
| 4774 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c' | ||
| 4775 | --- old/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c 2010-07-29 15:38:15 +0000 | ||
| 4776 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c 2010-08-20 13:27:11 +0000 | ||
| 4777 | @@ -17,5 +17,5 @@ | ||
| 4778 | out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 4779 | } | ||
| 4780 | |||
| 4781 | -/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4782 | +/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4783 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4784 | |||
| 4785 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c' | ||
| 4786 | --- old/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c 2010-07-29 15:38:15 +0000 | ||
| 4787 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c 2010-08-20 13:27:11 +0000 | ||
| 4788 | @@ -17,5 +17,5 @@ | ||
| 4789 | out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 4790 | } | ||
| 4791 | |||
| 4792 | -/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4793 | +/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4794 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4795 | |||
| 4796 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c' | ||
| 4797 | --- old/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c 2010-07-29 15:38:15 +0000 | ||
| 4798 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c 2010-08-20 13:27:11 +0000 | ||
| 4799 | @@ -17,5 +17,5 @@ | ||
| 4800 | out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 4801 | } | ||
| 4802 | |||
| 4803 | -/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4804 | +/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4805 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4806 | |||
| 4807 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c' | ||
| 4808 | --- old/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c 2010-07-29 15:38:15 +0000 | ||
| 4809 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c 2010-08-20 13:27:11 +0000 | ||
| 4810 | @@ -17,5 +17,5 @@ | ||
| 4811 | out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 4812 | } | ||
| 4813 | |||
| 4814 | -/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4815 | +/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4816 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4817 | |||
| 4818 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c' | ||
| 4819 | --- old/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c 2010-07-29 15:38:15 +0000 | ||
| 4820 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c 2010-08-20 13:27:11 +0000 | ||
| 4821 | @@ -17,5 +17,5 @@ | ||
| 4822 | out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 4823 | } | ||
| 4824 | |||
| 4825 | -/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4826 | +/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4827 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4828 | |||
| 4829 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhadds16.c' | ||
| 4830 | --- old/gcc/testsuite/gcc.target/arm/neon/vhadds16.c 2010-07-29 15:38:15 +0000 | ||
| 4831 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhadds16.c 2010-08-20 13:27:11 +0000 | ||
| 4832 | @@ -17,5 +17,5 @@ | ||
| 4833 | out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 4834 | } | ||
| 4835 | |||
| 4836 | -/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4837 | +/* { dg-final { scan-assembler "vhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4838 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4839 | |||
| 4840 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhadds32.c' | ||
| 4841 | --- old/gcc/testsuite/gcc.target/arm/neon/vhadds32.c 2010-07-29 15:38:15 +0000 | ||
| 4842 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhadds32.c 2010-08-20 13:27:11 +0000 | ||
| 4843 | @@ -17,5 +17,5 @@ | ||
| 4844 | out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 4845 | } | ||
| 4846 | |||
| 4847 | -/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4848 | +/* { dg-final { scan-assembler "vhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4849 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4850 | |||
| 4851 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhadds8.c' | ||
| 4852 | --- old/gcc/testsuite/gcc.target/arm/neon/vhadds8.c 2010-07-29 15:38:15 +0000 | ||
| 4853 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhadds8.c 2010-08-20 13:27:11 +0000 | ||
| 4854 | @@ -17,5 +17,5 @@ | ||
| 4855 | out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 4856 | } | ||
| 4857 | |||
| 4858 | -/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4859 | +/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4860 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4861 | |||
| 4862 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddu16.c' | ||
| 4863 | --- old/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c 2010-07-29 15:38:15 +0000 | ||
| 4864 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c 2010-08-20 13:27:11 +0000 | ||
| 4865 | @@ -17,5 +17,5 @@ | ||
| 4866 | out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 4867 | } | ||
| 4868 | |||
| 4869 | -/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4870 | +/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4871 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4872 | |||
| 4873 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddu32.c' | ||
| 4874 | --- old/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c 2010-07-29 15:38:15 +0000 | ||
| 4875 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c 2010-08-20 13:27:11 +0000 | ||
| 4876 | @@ -17,5 +17,5 @@ | ||
| 4877 | out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 4878 | } | ||
| 4879 | |||
| 4880 | -/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4881 | +/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4882 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4883 | |||
| 4884 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhaddu8.c' | ||
| 4885 | --- old/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c 2010-07-29 15:38:15 +0000 | ||
| 4886 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c 2010-08-20 13:27:11 +0000 | ||
| 4887 | @@ -17,5 +17,5 @@ | ||
| 4888 | out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 4889 | } | ||
| 4890 | |||
| 4891 | -/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4892 | +/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4893 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4894 | |||
| 4895 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c' | ||
| 4896 | --- old/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c 2010-07-29 15:38:15 +0000 | ||
| 4897 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c 2010-08-20 13:27:11 +0000 | ||
| 4898 | @@ -17,5 +17,5 @@ | ||
| 4899 | out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 4900 | } | ||
| 4901 | |||
| 4902 | -/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4903 | +/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4904 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4905 | |||
| 4906 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c' | ||
| 4907 | --- old/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c 2010-07-29 15:38:15 +0000 | ||
| 4908 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c 2010-08-20 13:27:11 +0000 | ||
| 4909 | @@ -17,5 +17,5 @@ | ||
| 4910 | out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 4911 | } | ||
| 4912 | |||
| 4913 | -/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4914 | +/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4915 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4916 | |||
| 4917 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c' | ||
| 4918 | --- old/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c 2010-07-29 15:38:15 +0000 | ||
| 4919 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c 2010-08-20 13:27:11 +0000 | ||
| 4920 | @@ -17,5 +17,5 @@ | ||
| 4921 | out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 4922 | } | ||
| 4923 | |||
| 4924 | -/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4925 | +/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4926 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4927 | |||
| 4928 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c' | ||
| 4929 | --- old/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c 2010-07-29 15:38:15 +0000 | ||
| 4930 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c 2010-08-20 13:27:11 +0000 | ||
| 4931 | @@ -17,5 +17,5 @@ | ||
| 4932 | out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 4933 | } | ||
| 4934 | |||
| 4935 | -/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4936 | +/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4937 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4938 | |||
| 4939 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c' | ||
| 4940 | --- old/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c 2010-07-29 15:38:15 +0000 | ||
| 4941 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c 2010-08-20 13:27:11 +0000 | ||
| 4942 | @@ -17,5 +17,5 @@ | ||
| 4943 | out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 4944 | } | ||
| 4945 | |||
| 4946 | -/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4947 | +/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4948 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4949 | |||
| 4950 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c' | ||
| 4951 | --- old/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c 2010-07-29 15:38:15 +0000 | ||
| 4952 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c 2010-08-20 13:27:11 +0000 | ||
| 4953 | @@ -17,5 +17,5 @@ | ||
| 4954 | out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 4955 | } | ||
| 4956 | |||
| 4957 | -/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4958 | +/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4959 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4960 | |||
| 4961 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubs16.c' | ||
| 4962 | --- old/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c 2010-07-29 15:38:15 +0000 | ||
| 4963 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c 2010-08-20 13:27:11 +0000 | ||
| 4964 | @@ -17,5 +17,5 @@ | ||
| 4965 | out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 4966 | } | ||
| 4967 | |||
| 4968 | -/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4969 | +/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4970 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4971 | |||
| 4972 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubs32.c' | ||
| 4973 | --- old/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c 2010-07-29 15:38:15 +0000 | ||
| 4974 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c 2010-08-20 13:27:11 +0000 | ||
| 4975 | @@ -17,5 +17,5 @@ | ||
| 4976 | out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 4977 | } | ||
| 4978 | |||
| 4979 | -/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4980 | +/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4981 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4982 | |||
| 4983 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubs8.c' | ||
| 4984 | --- old/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c 2010-07-29 15:38:15 +0000 | ||
| 4985 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c 2010-08-20 13:27:11 +0000 | ||
| 4986 | @@ -17,5 +17,5 @@ | ||
| 4987 | out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 4988 | } | ||
| 4989 | |||
| 4990 | -/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 4991 | +/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4992 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4993 | |||
| 4994 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubu16.c' | ||
| 4995 | --- old/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c 2010-07-29 15:38:15 +0000 | ||
| 4996 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c 2010-08-20 13:27:11 +0000 | ||
| 4997 | @@ -17,5 +17,5 @@ | ||
| 4998 | out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 4999 | } | ||
| 5000 | |||
| 5001 | -/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5002 | +/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5003 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5004 | |||
| 5005 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubu32.c' | ||
| 5006 | --- old/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c 2010-07-29 15:38:15 +0000 | ||
| 5007 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c 2010-08-20 13:27:11 +0000 | ||
| 5008 | @@ -17,5 +17,5 @@ | ||
| 5009 | out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 5010 | } | ||
| 5011 | |||
| 5012 | -/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5013 | +/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5014 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5015 | |||
| 5016 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vhsubu8.c' | ||
| 5017 | --- old/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c 2010-07-29 15:38:15 +0000 | ||
| 5018 | +++ new/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c 2010-08-20 13:27:11 +0000 | ||
| 5019 | @@ -17,5 +17,5 @@ | ||
| 5020 | out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 5021 | } | ||
| 5022 | |||
| 5023 | -/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5024 | +/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5025 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5026 | |||
| 5027 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c' | ||
| 5028 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2010-07-29 15:38:15 +0000 | ||
| 5029 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2010-08-20 13:27:11 +0000 | ||
| 5030 | @@ -15,5 +15,5 @@ | ||
| 5031 | out_float32x4_t = vld1q_dup_f32 (0); | ||
| 5032 | } | ||
| 5033 | |||
| 5034 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5035 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5036 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5037 | |||
| 5038 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c' | ||
| 5039 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2010-07-29 15:38:15 +0000 | ||
| 5040 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2010-08-20 13:27:11 +0000 | ||
| 5041 | @@ -15,5 +15,5 @@ | ||
| 5042 | out_poly16x8_t = vld1q_dup_p16 (0); | ||
| 5043 | } | ||
| 5044 | |||
| 5045 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5046 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5047 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5048 | |||
| 5049 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c' | ||
| 5050 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2010-07-29 15:38:15 +0000 | ||
| 5051 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2010-08-20 13:27:11 +0000 | ||
| 5052 | @@ -15,5 +15,5 @@ | ||
| 5053 | out_poly8x16_t = vld1q_dup_p8 (0); | ||
| 5054 | } | ||
| 5055 | |||
| 5056 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5057 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5058 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5059 | |||
| 5060 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c' | ||
| 5061 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2010-07-29 15:38:15 +0000 | ||
| 5062 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2010-08-20 13:27:11 +0000 | ||
| 5063 | @@ -15,5 +15,5 @@ | ||
| 5064 | out_int16x8_t = vld1q_dup_s16 (0); | ||
| 5065 | } | ||
| 5066 | |||
| 5067 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5068 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5069 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5070 | |||
| 5071 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c' | ||
| 5072 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2010-07-29 15:38:15 +0000 | ||
| 5073 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2010-08-20 13:27:11 +0000 | ||
| 5074 | @@ -15,5 +15,5 @@ | ||
| 5075 | out_int32x4_t = vld1q_dup_s32 (0); | ||
| 5076 | } | ||
| 5077 | |||
| 5078 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5079 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5080 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5081 | |||
| 5082 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c' | ||
| 5083 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2010-07-29 15:38:15 +0000 | ||
| 5084 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2010-08-20 13:27:11 +0000 | ||
| 5085 | @@ -15,5 +15,5 @@ | ||
| 5086 | out_int64x2_t = vld1q_dup_s64 (0); | ||
| 5087 | } | ||
| 5088 | |||
| 5089 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5090 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5091 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5092 | |||
| 5093 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c' | ||
| 5094 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2010-07-29 15:38:15 +0000 | ||
| 5095 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2010-08-20 13:27:11 +0000 | ||
| 5096 | @@ -15,5 +15,5 @@ | ||
| 5097 | out_int8x16_t = vld1q_dup_s8 (0); | ||
| 5098 | } | ||
| 5099 | |||
| 5100 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5101 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5102 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5103 | |||
| 5104 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c' | ||
| 5105 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2010-07-29 15:38:15 +0000 | ||
| 5106 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2010-08-20 13:27:11 +0000 | ||
| 5107 | @@ -15,5 +15,5 @@ | ||
| 5108 | out_uint16x8_t = vld1q_dup_u16 (0); | ||
| 5109 | } | ||
| 5110 | |||
| 5111 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5112 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5113 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5114 | |||
| 5115 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c' | ||
| 5116 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2010-07-29 15:38:15 +0000 | ||
| 5117 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2010-08-20 13:27:11 +0000 | ||
| 5118 | @@ -15,5 +15,5 @@ | ||
| 5119 | out_uint32x4_t = vld1q_dup_u32 (0); | ||
| 5120 | } | ||
| 5121 | |||
| 5122 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5123 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5124 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5125 | |||
| 5126 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c' | ||
| 5127 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2010-07-29 15:38:15 +0000 | ||
| 5128 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2010-08-20 13:27:11 +0000 | ||
| 5129 | @@ -15,5 +15,5 @@ | ||
| 5130 | out_uint64x2_t = vld1q_dup_u64 (0); | ||
| 5131 | } | ||
| 5132 | |||
| 5133 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5134 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5135 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5136 | |||
| 5137 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c' | ||
| 5138 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2010-07-29 15:38:15 +0000 | ||
| 5139 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2010-08-20 13:27:11 +0000 | ||
| 5140 | @@ -15,5 +15,5 @@ | ||
| 5141 | out_uint8x16_t = vld1q_dup_u8 (0); | ||
| 5142 | } | ||
| 5143 | |||
| 5144 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5145 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5146 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5147 | |||
| 5148 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c' | ||
| 5149 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 5150 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 5151 | @@ -16,5 +16,5 @@ | ||
| 5152 | out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1); | ||
| 5153 | } | ||
| 5154 | |||
| 5155 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5156 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5157 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5158 | |||
| 5159 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c' | ||
| 5160 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 5161 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 5162 | @@ -16,5 +16,5 @@ | ||
| 5163 | out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1); | ||
| 5164 | } | ||
| 5165 | |||
| 5166 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5167 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5168 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5169 | |||
| 5170 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c' | ||
| 5171 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 5172 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 5173 | @@ -16,5 +16,5 @@ | ||
| 5174 | out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1); | ||
| 5175 | } | ||
| 5176 | |||
| 5177 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5178 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5179 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5180 | |||
| 5181 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c' | ||
| 5182 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 5183 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 5184 | @@ -16,5 +16,5 @@ | ||
| 5185 | out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1); | ||
| 5186 | } | ||
| 5187 | |||
| 5188 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5189 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5190 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5191 | |||
| 5192 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c' | ||
| 5193 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 5194 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 5195 | @@ -16,5 +16,5 @@ | ||
| 5196 | out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1); | ||
| 5197 | } | ||
| 5198 | |||
| 5199 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5200 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5201 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5202 | |||
| 5203 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c' | ||
| 5204 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2010-07-29 15:38:15 +0000 | ||
| 5205 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2010-08-20 13:27:11 +0000 | ||
| 5206 | @@ -16,5 +16,5 @@ | ||
| 5207 | out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1); | ||
| 5208 | } | ||
| 5209 | |||
| 5210 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5211 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5212 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5213 | |||
| 5214 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c' | ||
| 5215 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 5216 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 5217 | @@ -16,5 +16,5 @@ | ||
| 5218 | out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1); | ||
| 5219 | } | ||
| 5220 | |||
| 5221 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5222 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5223 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5224 | |||
| 5225 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c' | ||
| 5226 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 5227 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 5228 | @@ -16,5 +16,5 @@ | ||
| 5229 | out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1); | ||
| 5230 | } | ||
| 5231 | |||
| 5232 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5233 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5234 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5235 | |||
| 5236 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c' | ||
| 5237 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 5238 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 5239 | @@ -16,5 +16,5 @@ | ||
| 5240 | out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1); | ||
| 5241 | } | ||
| 5242 | |||
| 5243 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5244 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5245 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5246 | |||
| 5247 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c' | ||
| 5248 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2010-07-29 15:38:15 +0000 | ||
| 5249 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2010-08-20 13:27:11 +0000 | ||
| 5250 | @@ -16,5 +16,5 @@ | ||
| 5251 | out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1); | ||
| 5252 | } | ||
| 5253 | |||
| 5254 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5255 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5256 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5257 | |||
| 5258 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c' | ||
| 5259 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 5260 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 5261 | @@ -16,5 +16,5 @@ | ||
| 5262 | out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1); | ||
| 5263 | } | ||
| 5264 | |||
| 5265 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5266 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5267 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5268 | |||
| 5269 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c' | ||
| 5270 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2010-07-29 15:38:15 +0000 | ||
| 5271 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 5272 | @@ -15,5 +15,5 @@ | ||
| 5273 | out_float32x4_t = vld1q_f32 (0); | ||
| 5274 | } | ||
| 5275 | |||
| 5276 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5277 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5278 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5279 | |||
| 5280 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c' | ||
| 5281 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2010-07-29 15:38:15 +0000 | ||
| 5282 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 5283 | @@ -15,5 +15,5 @@ | ||
| 5284 | out_poly16x8_t = vld1q_p16 (0); | ||
| 5285 | } | ||
| 5286 | |||
| 5287 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5288 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5289 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5290 | |||
| 5291 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c' | ||
| 5292 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2010-07-29 15:38:15 +0000 | ||
| 5293 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 5294 | @@ -15,5 +15,5 @@ | ||
| 5295 | out_poly8x16_t = vld1q_p8 (0); | ||
| 5296 | } | ||
| 5297 | |||
| 5298 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5299 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5300 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5301 | |||
| 5302 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c' | ||
| 5303 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2010-07-29 15:38:15 +0000 | ||
| 5304 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 5305 | @@ -15,5 +15,5 @@ | ||
| 5306 | out_int16x8_t = vld1q_s16 (0); | ||
| 5307 | } | ||
| 5308 | |||
| 5309 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5310 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5311 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5312 | |||
| 5313 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c' | ||
| 5314 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2010-07-29 15:38:15 +0000 | ||
| 5315 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 5316 | @@ -15,5 +15,5 @@ | ||
| 5317 | out_int32x4_t = vld1q_s32 (0); | ||
| 5318 | } | ||
| 5319 | |||
| 5320 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5321 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5322 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5323 | |||
| 5324 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c' | ||
| 5325 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2010-07-29 15:38:15 +0000 | ||
| 5326 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2010-08-20 13:27:11 +0000 | ||
| 5327 | @@ -15,5 +15,5 @@ | ||
| 5328 | out_int64x2_t = vld1q_s64 (0); | ||
| 5329 | } | ||
| 5330 | |||
| 5331 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5332 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5333 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5334 | |||
| 5335 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c' | ||
| 5336 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2010-07-29 15:38:15 +0000 | ||
| 5337 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 5338 | @@ -15,5 +15,5 @@ | ||
| 5339 | out_int8x16_t = vld1q_s8 (0); | ||
| 5340 | } | ||
| 5341 | |||
| 5342 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5343 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5344 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5345 | |||
| 5346 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c' | ||
| 5347 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2010-07-29 15:38:15 +0000 | ||
| 5348 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 5349 | @@ -15,5 +15,5 @@ | ||
| 5350 | out_uint16x8_t = vld1q_u16 (0); | ||
| 5351 | } | ||
| 5352 | |||
| 5353 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5354 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5355 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5356 | |||
| 5357 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c' | ||
| 5358 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2010-07-29 15:38:15 +0000 | ||
| 5359 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 5360 | @@ -15,5 +15,5 @@ | ||
| 5361 | out_uint32x4_t = vld1q_u32 (0); | ||
| 5362 | } | ||
| 5363 | |||
| 5364 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5365 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5366 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5367 | |||
| 5368 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c' | ||
| 5369 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2010-07-29 15:38:15 +0000 | ||
| 5370 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2010-08-20 13:27:11 +0000 | ||
| 5371 | @@ -15,5 +15,5 @@ | ||
| 5372 | out_uint64x2_t = vld1q_u64 (0); | ||
| 5373 | } | ||
| 5374 | |||
| 5375 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5376 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5377 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5378 | |||
| 5379 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c' | ||
| 5380 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2010-07-29 15:38:15 +0000 | ||
| 5381 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 5382 | @@ -15,5 +15,5 @@ | ||
| 5383 | out_uint8x16_t = vld1q_u8 (0); | ||
| 5384 | } | ||
| 5385 | |||
| 5386 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5387 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5388 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5389 | |||
| 5390 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c' | ||
| 5391 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2010-07-29 15:38:15 +0000 | ||
| 5392 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2010-08-20 13:27:11 +0000 | ||
| 5393 | @@ -15,5 +15,5 @@ | ||
| 5394 | out_float32x2_t = vld1_dup_f32 (0); | ||
| 5395 | } | ||
| 5396 | |||
| 5397 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5398 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5399 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5400 | |||
| 5401 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c' | ||
| 5402 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2010-07-29 15:38:15 +0000 | ||
| 5403 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2010-08-20 13:27:11 +0000 | ||
| 5404 | @@ -15,5 +15,5 @@ | ||
| 5405 | out_poly16x4_t = vld1_dup_p16 (0); | ||
| 5406 | } | ||
| 5407 | |||
| 5408 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5409 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5410 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5411 | |||
| 5412 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c' | ||
| 5413 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2010-07-29 15:38:15 +0000 | ||
| 5414 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2010-08-20 13:27:11 +0000 | ||
| 5415 | @@ -15,5 +15,5 @@ | ||
| 5416 | out_poly8x8_t = vld1_dup_p8 (0); | ||
| 5417 | } | ||
| 5418 | |||
| 5419 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5420 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5421 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5422 | |||
| 5423 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c' | ||
| 5424 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2010-07-29 15:38:15 +0000 | ||
| 5425 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2010-08-20 13:27:11 +0000 | ||
| 5426 | @@ -15,5 +15,5 @@ | ||
| 5427 | out_int16x4_t = vld1_dup_s16 (0); | ||
| 5428 | } | ||
| 5429 | |||
| 5430 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5431 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5432 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5433 | |||
| 5434 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c' | ||
| 5435 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2010-07-29 15:38:15 +0000 | ||
| 5436 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2010-08-20 13:27:11 +0000 | ||
| 5437 | @@ -15,5 +15,5 @@ | ||
| 5438 | out_int32x2_t = vld1_dup_s32 (0); | ||
| 5439 | } | ||
| 5440 | |||
| 5441 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5442 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5443 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5444 | |||
| 5445 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c' | ||
| 5446 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2010-07-29 15:38:15 +0000 | ||
| 5447 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2010-08-20 13:27:11 +0000 | ||
| 5448 | @@ -15,5 +15,5 @@ | ||
| 5449 | out_int64x1_t = vld1_dup_s64 (0); | ||
| 5450 | } | ||
| 5451 | |||
| 5452 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5453 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5454 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5455 | |||
| 5456 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c' | ||
| 5457 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2010-07-29 15:38:15 +0000 | ||
| 5458 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2010-08-20 13:27:11 +0000 | ||
| 5459 | @@ -15,5 +15,5 @@ | ||
| 5460 | out_int8x8_t = vld1_dup_s8 (0); | ||
| 5461 | } | ||
| 5462 | |||
| 5463 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5464 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5465 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5466 | |||
| 5467 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c' | ||
| 5468 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2010-07-29 15:38:15 +0000 | ||
| 5469 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2010-08-20 13:27:11 +0000 | ||
| 5470 | @@ -15,5 +15,5 @@ | ||
| 5471 | out_uint16x4_t = vld1_dup_u16 (0); | ||
| 5472 | } | ||
| 5473 | |||
| 5474 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5475 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5476 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5477 | |||
| 5478 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c' | ||
| 5479 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2010-07-29 15:38:15 +0000 | ||
| 5480 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2010-08-20 13:27:11 +0000 | ||
| 5481 | @@ -15,5 +15,5 @@ | ||
| 5482 | out_uint32x2_t = vld1_dup_u32 (0); | ||
| 5483 | } | ||
| 5484 | |||
| 5485 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5486 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5487 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5488 | |||
| 5489 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c' | ||
| 5490 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2010-07-29 15:38:15 +0000 | ||
| 5491 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2010-08-20 13:27:11 +0000 | ||
| 5492 | @@ -15,5 +15,5 @@ | ||
| 5493 | out_uint64x1_t = vld1_dup_u64 (0); | ||
| 5494 | } | ||
| 5495 | |||
| 5496 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5497 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5498 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5499 | |||
| 5500 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c' | ||
| 5501 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2010-07-29 15:38:15 +0000 | ||
| 5502 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2010-08-20 13:27:11 +0000 | ||
| 5503 | @@ -15,5 +15,5 @@ | ||
| 5504 | out_uint8x8_t = vld1_dup_u8 (0); | ||
| 5505 | } | ||
| 5506 | |||
| 5507 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5508 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5509 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5510 | |||
| 5511 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c' | ||
| 5512 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 5513 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 5514 | @@ -16,5 +16,5 @@ | ||
| 5515 | out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1); | ||
| 5516 | } | ||
| 5517 | |||
| 5518 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5519 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5520 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5521 | |||
| 5522 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c' | ||
| 5523 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 5524 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 5525 | @@ -16,5 +16,5 @@ | ||
| 5526 | out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1); | ||
| 5527 | } | ||
| 5528 | |||
| 5529 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5530 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5531 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5532 | |||
| 5533 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c' | ||
| 5534 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 5535 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 5536 | @@ -16,5 +16,5 @@ | ||
| 5537 | out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1); | ||
| 5538 | } | ||
| 5539 | |||
| 5540 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5541 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5542 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5543 | |||
| 5544 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c' | ||
| 5545 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 5546 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 5547 | @@ -16,5 +16,5 @@ | ||
| 5548 | out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1); | ||
| 5549 | } | ||
| 5550 | |||
| 5551 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5552 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5553 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5554 | |||
| 5555 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c' | ||
| 5556 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 5557 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 5558 | @@ -16,5 +16,5 @@ | ||
| 5559 | out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1); | ||
| 5560 | } | ||
| 5561 | |||
| 5562 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5563 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5564 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5565 | |||
| 5566 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c' | ||
| 5567 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2010-07-29 15:38:15 +0000 | ||
| 5568 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2010-08-20 13:27:11 +0000 | ||
| 5569 | @@ -16,5 +16,5 @@ | ||
| 5570 | out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0); | ||
| 5571 | } | ||
| 5572 | |||
| 5573 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5574 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5575 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5576 | |||
| 5577 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c' | ||
| 5578 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 5579 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 5580 | @@ -16,5 +16,5 @@ | ||
| 5581 | out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1); | ||
| 5582 | } | ||
| 5583 | |||
| 5584 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5585 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5586 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5587 | |||
| 5588 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c' | ||
| 5589 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 5590 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 5591 | @@ -16,5 +16,5 @@ | ||
| 5592 | out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1); | ||
| 5593 | } | ||
| 5594 | |||
| 5595 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5596 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5597 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5598 | |||
| 5599 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c' | ||
| 5600 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 5601 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 5602 | @@ -16,5 +16,5 @@ | ||
| 5603 | out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1); | ||
| 5604 | } | ||
| 5605 | |||
| 5606 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5607 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5608 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5609 | |||
| 5610 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c' | ||
| 5611 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2010-07-29 15:38:15 +0000 | ||
| 5612 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2010-08-20 13:27:11 +0000 | ||
| 5613 | @@ -16,5 +16,5 @@ | ||
| 5614 | out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0); | ||
| 5615 | } | ||
| 5616 | |||
| 5617 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5618 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5619 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5620 | |||
| 5621 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c' | ||
| 5622 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 5623 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 5624 | @@ -16,5 +16,5 @@ | ||
| 5625 | out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1); | ||
| 5626 | } | ||
| 5627 | |||
| 5628 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5629 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5630 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5631 | |||
| 5632 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1f32.c' | ||
| 5633 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2010-07-29 15:38:15 +0000 | ||
| 5634 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2010-08-20 13:27:11 +0000 | ||
| 5635 | @@ -15,5 +15,5 @@ | ||
| 5636 | out_float32x2_t = vld1_f32 (0); | ||
| 5637 | } | ||
| 5638 | |||
| 5639 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5640 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5641 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5642 | |||
| 5643 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p16.c' | ||
| 5644 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2010-07-29 15:38:15 +0000 | ||
| 5645 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2010-08-20 13:27:11 +0000 | ||
| 5646 | @@ -15,5 +15,5 @@ | ||
| 5647 | out_poly16x4_t = vld1_p16 (0); | ||
| 5648 | } | ||
| 5649 | |||
| 5650 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5651 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5652 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5653 | |||
| 5654 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p8.c' | ||
| 5655 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2010-07-29 15:38:15 +0000 | ||
| 5656 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2010-08-20 13:27:11 +0000 | ||
| 5657 | @@ -15,5 +15,5 @@ | ||
| 5658 | out_poly8x8_t = vld1_p8 (0); | ||
| 5659 | } | ||
| 5660 | |||
| 5661 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5662 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5663 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5664 | |||
| 5665 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s16.c' | ||
| 5666 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2010-07-29 15:38:15 +0000 | ||
| 5667 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2010-08-20 13:27:11 +0000 | ||
| 5668 | @@ -15,5 +15,5 @@ | ||
| 5669 | out_int16x4_t = vld1_s16 (0); | ||
| 5670 | } | ||
| 5671 | |||
| 5672 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5673 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5674 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5675 | |||
| 5676 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s32.c' | ||
| 5677 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2010-07-29 15:38:15 +0000 | ||
| 5678 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2010-08-20 13:27:11 +0000 | ||
| 5679 | @@ -15,5 +15,5 @@ | ||
| 5680 | out_int32x2_t = vld1_s32 (0); | ||
| 5681 | } | ||
| 5682 | |||
| 5683 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5684 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5685 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5686 | |||
| 5687 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s64.c' | ||
| 5688 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2010-07-29 15:38:15 +0000 | ||
| 5689 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2010-08-20 13:27:11 +0000 | ||
| 5690 | @@ -15,5 +15,5 @@ | ||
| 5691 | out_int64x1_t = vld1_s64 (0); | ||
| 5692 | } | ||
| 5693 | |||
| 5694 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5695 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5696 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5697 | |||
| 5698 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s8.c' | ||
| 5699 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2010-07-29 15:38:15 +0000 | ||
| 5700 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2010-08-20 13:27:11 +0000 | ||
| 5701 | @@ -15,5 +15,5 @@ | ||
| 5702 | out_int8x8_t = vld1_s8 (0); | ||
| 5703 | } | ||
| 5704 | |||
| 5705 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5706 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5707 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5708 | |||
| 5709 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u16.c' | ||
| 5710 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2010-07-29 15:38:15 +0000 | ||
| 5711 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2010-08-20 13:27:11 +0000 | ||
| 5712 | @@ -15,5 +15,5 @@ | ||
| 5713 | out_uint16x4_t = vld1_u16 (0); | ||
| 5714 | } | ||
| 5715 | |||
| 5716 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5717 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5718 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5719 | |||
| 5720 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u32.c' | ||
| 5721 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2010-07-29 15:38:15 +0000 | ||
| 5722 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2010-08-20 13:27:11 +0000 | ||
| 5723 | @@ -15,5 +15,5 @@ | ||
| 5724 | out_uint32x2_t = vld1_u32 (0); | ||
| 5725 | } | ||
| 5726 | |||
| 5727 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5728 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5729 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5730 | |||
| 5731 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u64.c' | ||
| 5732 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2010-07-29 15:38:15 +0000 | ||
| 5733 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2010-08-20 13:27:11 +0000 | ||
| 5734 | @@ -15,5 +15,5 @@ | ||
| 5735 | out_uint64x1_t = vld1_u64 (0); | ||
| 5736 | } | ||
| 5737 | |||
| 5738 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5739 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5740 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5741 | |||
| 5742 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u8.c' | ||
| 5743 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2010-07-29 15:38:15 +0000 | ||
| 5744 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2010-08-20 13:27:11 +0000 | ||
| 5745 | @@ -15,5 +15,5 @@ | ||
| 5746 | out_uint8x8_t = vld1_u8 (0); | ||
| 5747 | } | ||
| 5748 | |||
| 5749 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5750 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5751 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5752 | |||
| 5753 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c' | ||
| 5754 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 5755 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 5756 | @@ -16,5 +16,5 @@ | ||
| 5757 | out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1); | ||
| 5758 | } | ||
| 5759 | |||
| 5760 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5761 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5762 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5763 | |||
| 5764 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c' | ||
| 5765 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 5766 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 5767 | @@ -16,5 +16,5 @@ | ||
| 5768 | out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1); | ||
| 5769 | } | ||
| 5770 | |||
| 5771 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5772 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5773 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5774 | |||
| 5775 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c' | ||
| 5776 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 5777 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 5778 | @@ -16,5 +16,5 @@ | ||
| 5779 | out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1); | ||
| 5780 | } | ||
| 5781 | |||
| 5782 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5783 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5784 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5785 | |||
| 5786 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c' | ||
| 5787 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 5788 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 5789 | @@ -16,5 +16,5 @@ | ||
| 5790 | out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1); | ||
| 5791 | } | ||
| 5792 | |||
| 5793 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5794 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5795 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5796 | |||
| 5797 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c' | ||
| 5798 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 5799 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 5800 | @@ -16,5 +16,5 @@ | ||
| 5801 | out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1); | ||
| 5802 | } | ||
| 5803 | |||
| 5804 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5805 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5806 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5807 | |||
| 5808 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c' | ||
| 5809 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 5810 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 5811 | @@ -16,5 +16,5 @@ | ||
| 5812 | out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1); | ||
| 5813 | } | ||
| 5814 | |||
| 5815 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5816 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5817 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5818 | |||
| 5819 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c' | ||
| 5820 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2010-07-29 15:38:15 +0000 | ||
| 5821 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 5822 | @@ -15,6 +15,6 @@ | ||
| 5823 | out_float32x4x2_t = vld2q_f32 (0); | ||
| 5824 | } | ||
| 5825 | |||
| 5826 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5827 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5828 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5829 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5830 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5831 | |||
| 5832 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c' | ||
| 5833 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2010-07-29 15:38:15 +0000 | ||
| 5834 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 5835 | @@ -15,6 +15,6 @@ | ||
| 5836 | out_poly16x8x2_t = vld2q_p16 (0); | ||
| 5837 | } | ||
| 5838 | |||
| 5839 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5840 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5841 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5842 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5843 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5844 | |||
| 5845 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c' | ||
| 5846 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2010-07-29 15:38:15 +0000 | ||
| 5847 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 5848 | @@ -15,6 +15,6 @@ | ||
| 5849 | out_poly8x16x2_t = vld2q_p8 (0); | ||
| 5850 | } | ||
| 5851 | |||
| 5852 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5853 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5854 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5855 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5856 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5857 | |||
| 5858 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c' | ||
| 5859 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2010-07-29 15:38:15 +0000 | ||
| 5860 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 5861 | @@ -15,6 +15,6 @@ | ||
| 5862 | out_int16x8x2_t = vld2q_s16 (0); | ||
| 5863 | } | ||
| 5864 | |||
| 5865 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5866 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5867 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5868 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5869 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5870 | |||
| 5871 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c' | ||
| 5872 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2010-07-29 15:38:15 +0000 | ||
| 5873 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 5874 | @@ -15,6 +15,6 @@ | ||
| 5875 | out_int32x4x2_t = vld2q_s32 (0); | ||
| 5876 | } | ||
| 5877 | |||
| 5878 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5879 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5880 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5881 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5882 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5883 | |||
| 5884 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c' | ||
| 5885 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2010-07-29 15:38:15 +0000 | ||
| 5886 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 5887 | @@ -15,6 +15,6 @@ | ||
| 5888 | out_int8x16x2_t = vld2q_s8 (0); | ||
| 5889 | } | ||
| 5890 | |||
| 5891 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5892 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5893 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5894 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5895 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5896 | |||
| 5897 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c' | ||
| 5898 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2010-07-29 15:38:15 +0000 | ||
| 5899 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 5900 | @@ -15,6 +15,6 @@ | ||
| 5901 | out_uint16x8x2_t = vld2q_u16 (0); | ||
| 5902 | } | ||
| 5903 | |||
| 5904 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5905 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5906 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5907 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5908 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5909 | |||
| 5910 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c' | ||
| 5911 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2010-07-29 15:38:15 +0000 | ||
| 5912 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 5913 | @@ -15,6 +15,6 @@ | ||
| 5914 | out_uint32x4x2_t = vld2q_u32 (0); | ||
| 5915 | } | ||
| 5916 | |||
| 5917 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5918 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5919 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5920 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5921 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5922 | |||
| 5923 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c' | ||
| 5924 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2010-07-29 15:38:15 +0000 | ||
| 5925 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 5926 | @@ -15,6 +15,6 @@ | ||
| 5927 | out_uint8x16x2_t = vld2q_u8 (0); | ||
| 5928 | } | ||
| 5929 | |||
| 5930 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5931 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5932 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5933 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5934 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5935 | |||
| 5936 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c' | ||
| 5937 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2010-07-29 15:38:15 +0000 | ||
| 5938 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2010-08-20 13:27:11 +0000 | ||
| 5939 | @@ -15,5 +15,5 @@ | ||
| 5940 | out_float32x2x2_t = vld2_dup_f32 (0); | ||
| 5941 | } | ||
| 5942 | |||
| 5943 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5944 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5945 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5946 | |||
| 5947 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c' | ||
| 5948 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2010-07-29 15:38:15 +0000 | ||
| 5949 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2010-08-20 13:27:11 +0000 | ||
| 5950 | @@ -15,5 +15,5 @@ | ||
| 5951 | out_poly16x4x2_t = vld2_dup_p16 (0); | ||
| 5952 | } | ||
| 5953 | |||
| 5954 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5955 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5956 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5957 | |||
| 5958 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c' | ||
| 5959 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2010-07-29 15:38:15 +0000 | ||
| 5960 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2010-08-20 13:27:11 +0000 | ||
| 5961 | @@ -15,5 +15,5 @@ | ||
| 5962 | out_poly8x8x2_t = vld2_dup_p8 (0); | ||
| 5963 | } | ||
| 5964 | |||
| 5965 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5966 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5967 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5968 | |||
| 5969 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c' | ||
| 5970 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2010-07-29 15:38:15 +0000 | ||
| 5971 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2010-08-20 13:27:11 +0000 | ||
| 5972 | @@ -15,5 +15,5 @@ | ||
| 5973 | out_int16x4x2_t = vld2_dup_s16 (0); | ||
| 5974 | } | ||
| 5975 | |||
| 5976 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5977 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5978 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5979 | |||
| 5980 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c' | ||
| 5981 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2010-07-29 15:38:15 +0000 | ||
| 5982 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2010-08-20 13:27:11 +0000 | ||
| 5983 | @@ -15,5 +15,5 @@ | ||
| 5984 | out_int32x2x2_t = vld2_dup_s32 (0); | ||
| 5985 | } | ||
| 5986 | |||
| 5987 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5988 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5989 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5990 | |||
| 5991 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c' | ||
| 5992 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2010-07-29 15:38:15 +0000 | ||
| 5993 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2010-08-20 13:27:11 +0000 | ||
| 5994 | @@ -15,5 +15,5 @@ | ||
| 5995 | out_int64x1x2_t = vld2_dup_s64 (0); | ||
| 5996 | } | ||
| 5997 | |||
| 5998 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 5999 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6000 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6001 | |||
| 6002 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c' | ||
| 6003 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2010-07-29 15:38:15 +0000 | ||
| 6004 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2010-08-20 13:27:11 +0000 | ||
| 6005 | @@ -15,5 +15,5 @@ | ||
| 6006 | out_int8x8x2_t = vld2_dup_s8 (0); | ||
| 6007 | } | ||
| 6008 | |||
| 6009 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6010 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6011 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6012 | |||
| 6013 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c' | ||
| 6014 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2010-07-29 15:38:15 +0000 | ||
| 6015 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2010-08-20 13:27:11 +0000 | ||
| 6016 | @@ -15,5 +15,5 @@ | ||
| 6017 | out_uint16x4x2_t = vld2_dup_u16 (0); | ||
| 6018 | } | ||
| 6019 | |||
| 6020 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6021 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6022 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6023 | |||
| 6024 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c' | ||
| 6025 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2010-07-29 15:38:15 +0000 | ||
| 6026 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2010-08-20 13:27:11 +0000 | ||
| 6027 | @@ -15,5 +15,5 @@ | ||
| 6028 | out_uint32x2x2_t = vld2_dup_u32 (0); | ||
| 6029 | } | ||
| 6030 | |||
| 6031 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6032 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6033 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6034 | |||
| 6035 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c' | ||
| 6036 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2010-07-29 15:38:15 +0000 | ||
| 6037 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2010-08-20 13:27:11 +0000 | ||
| 6038 | @@ -15,5 +15,5 @@ | ||
| 6039 | out_uint64x1x2_t = vld2_dup_u64 (0); | ||
| 6040 | } | ||
| 6041 | |||
| 6042 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6043 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6044 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6045 | |||
| 6046 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c' | ||
| 6047 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2010-07-29 15:38:15 +0000 | ||
| 6048 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2010-08-20 13:27:11 +0000 | ||
| 6049 | @@ -15,5 +15,5 @@ | ||
| 6050 | out_uint8x8x2_t = vld2_dup_u8 (0); | ||
| 6051 | } | ||
| 6052 | |||
| 6053 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6054 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6055 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6056 | |||
| 6057 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c' | ||
| 6058 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 6059 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 6060 | @@ -16,5 +16,5 @@ | ||
| 6061 | out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1); | ||
| 6062 | } | ||
| 6063 | |||
| 6064 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6065 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6066 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6067 | |||
| 6068 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c' | ||
| 6069 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 6070 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 6071 | @@ -16,5 +16,5 @@ | ||
| 6072 | out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1); | ||
| 6073 | } | ||
| 6074 | |||
| 6075 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6076 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6077 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6078 | |||
| 6079 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c' | ||
| 6080 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 6081 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 6082 | @@ -16,5 +16,5 @@ | ||
| 6083 | out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1); | ||
| 6084 | } | ||
| 6085 | |||
| 6086 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6087 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6088 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6089 | |||
| 6090 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c' | ||
| 6091 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 6092 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 6093 | @@ -16,5 +16,5 @@ | ||
| 6094 | out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1); | ||
| 6095 | } | ||
| 6096 | |||
| 6097 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6098 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6099 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6100 | |||
| 6101 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c' | ||
| 6102 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 6103 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 6104 | @@ -16,5 +16,5 @@ | ||
| 6105 | out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1); | ||
| 6106 | } | ||
| 6107 | |||
| 6108 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6109 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6110 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6111 | |||
| 6112 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c' | ||
| 6113 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 6114 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 6115 | @@ -16,5 +16,5 @@ | ||
| 6116 | out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1); | ||
| 6117 | } | ||
| 6118 | |||
| 6119 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6120 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6121 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6122 | |||
| 6123 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c' | ||
| 6124 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 6125 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 6126 | @@ -16,5 +16,5 @@ | ||
| 6127 | out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1); | ||
| 6128 | } | ||
| 6129 | |||
| 6130 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6131 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6132 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6133 | |||
| 6134 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c' | ||
| 6135 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 6136 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 6137 | @@ -16,5 +16,5 @@ | ||
| 6138 | out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1); | ||
| 6139 | } | ||
| 6140 | |||
| 6141 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6142 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6143 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6144 | |||
| 6145 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c' | ||
| 6146 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 6147 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 6148 | @@ -16,5 +16,5 @@ | ||
| 6149 | out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1); | ||
| 6150 | } | ||
| 6151 | |||
| 6152 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6153 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6154 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6155 | |||
| 6156 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2f32.c' | ||
| 6157 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2010-07-29 15:38:15 +0000 | ||
| 6158 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2010-08-20 13:27:11 +0000 | ||
| 6159 | @@ -15,5 +15,5 @@ | ||
| 6160 | out_float32x2x2_t = vld2_f32 (0); | ||
| 6161 | } | ||
| 6162 | |||
| 6163 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6164 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6165 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6166 | |||
| 6167 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p16.c' | ||
| 6168 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2010-07-29 15:38:15 +0000 | ||
| 6169 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2010-08-20 13:27:11 +0000 | ||
| 6170 | @@ -15,5 +15,5 @@ | ||
| 6171 | out_poly16x4x2_t = vld2_p16 (0); | ||
| 6172 | } | ||
| 6173 | |||
| 6174 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6175 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6176 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6177 | |||
| 6178 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p8.c' | ||
| 6179 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2010-07-29 15:38:15 +0000 | ||
| 6180 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2010-08-20 13:27:11 +0000 | ||
| 6181 | @@ -15,5 +15,5 @@ | ||
| 6182 | out_poly8x8x2_t = vld2_p8 (0); | ||
| 6183 | } | ||
| 6184 | |||
| 6185 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6186 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6187 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6188 | |||
| 6189 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s16.c' | ||
| 6190 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2010-07-29 15:38:15 +0000 | ||
| 6191 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2010-08-20 13:27:11 +0000 | ||
| 6192 | @@ -15,5 +15,5 @@ | ||
| 6193 | out_int16x4x2_t = vld2_s16 (0); | ||
| 6194 | } | ||
| 6195 | |||
| 6196 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6197 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6198 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6199 | |||
| 6200 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s32.c' | ||
| 6201 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2010-07-29 15:38:15 +0000 | ||
| 6202 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2010-08-20 13:27:11 +0000 | ||
| 6203 | @@ -15,5 +15,5 @@ | ||
| 6204 | out_int32x2x2_t = vld2_s32 (0); | ||
| 6205 | } | ||
| 6206 | |||
| 6207 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6208 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6209 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6210 | |||
| 6211 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s64.c' | ||
| 6212 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2010-07-29 15:38:15 +0000 | ||
| 6213 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2010-08-20 13:27:11 +0000 | ||
| 6214 | @@ -15,5 +15,5 @@ | ||
| 6215 | out_int64x1x2_t = vld2_s64 (0); | ||
| 6216 | } | ||
| 6217 | |||
| 6218 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6219 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6220 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6221 | |||
| 6222 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s8.c' | ||
| 6223 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2010-07-29 15:38:15 +0000 | ||
| 6224 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2010-08-20 13:27:11 +0000 | ||
| 6225 | @@ -15,5 +15,5 @@ | ||
| 6226 | out_int8x8x2_t = vld2_s8 (0); | ||
| 6227 | } | ||
| 6228 | |||
| 6229 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6230 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6231 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6232 | |||
| 6233 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u16.c' | ||
| 6234 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2010-07-29 15:38:15 +0000 | ||
| 6235 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2010-08-20 13:27:11 +0000 | ||
| 6236 | @@ -15,5 +15,5 @@ | ||
| 6237 | out_uint16x4x2_t = vld2_u16 (0); | ||
| 6238 | } | ||
| 6239 | |||
| 6240 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6241 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6242 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6243 | |||
| 6244 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u32.c' | ||
| 6245 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2010-07-29 15:38:15 +0000 | ||
| 6246 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2010-08-20 13:27:11 +0000 | ||
| 6247 | @@ -15,5 +15,5 @@ | ||
| 6248 | out_uint32x2x2_t = vld2_u32 (0); | ||
| 6249 | } | ||
| 6250 | |||
| 6251 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6252 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6253 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6254 | |||
| 6255 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u64.c' | ||
| 6256 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2010-07-29 15:38:15 +0000 | ||
| 6257 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2010-08-20 13:27:11 +0000 | ||
| 6258 | @@ -15,5 +15,5 @@ | ||
| 6259 | out_uint64x1x2_t = vld2_u64 (0); | ||
| 6260 | } | ||
| 6261 | |||
| 6262 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6263 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6264 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6265 | |||
| 6266 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u8.c' | ||
| 6267 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2010-07-29 15:38:15 +0000 | ||
| 6268 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2010-08-20 13:27:11 +0000 | ||
| 6269 | @@ -15,5 +15,5 @@ | ||
| 6270 | out_uint8x8x2_t = vld2_u8 (0); | ||
| 6271 | } | ||
| 6272 | |||
| 6273 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6274 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6275 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6276 | |||
| 6277 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c' | ||
| 6278 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 6279 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 6280 | @@ -16,5 +16,5 @@ | ||
| 6281 | out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1); | ||
| 6282 | } | ||
| 6283 | |||
| 6284 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6285 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6286 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6287 | |||
| 6288 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c' | ||
| 6289 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 6290 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 6291 | @@ -16,5 +16,5 @@ | ||
| 6292 | out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1); | ||
| 6293 | } | ||
| 6294 | |||
| 6295 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6296 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6297 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6298 | |||
| 6299 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c' | ||
| 6300 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 6301 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 6302 | @@ -16,5 +16,5 @@ | ||
| 6303 | out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1); | ||
| 6304 | } | ||
| 6305 | |||
| 6306 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6307 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6308 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6309 | |||
| 6310 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c' | ||
| 6311 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 6312 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 6313 | @@ -16,5 +16,5 @@ | ||
| 6314 | out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1); | ||
| 6315 | } | ||
| 6316 | |||
| 6317 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6318 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6319 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6320 | |||
| 6321 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c' | ||
| 6322 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 6323 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 6324 | @@ -16,5 +16,5 @@ | ||
| 6325 | out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1); | ||
| 6326 | } | ||
| 6327 | |||
| 6328 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6329 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6330 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6331 | |||
| 6332 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c' | ||
| 6333 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 6334 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 6335 | @@ -16,5 +16,5 @@ | ||
| 6336 | out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1); | ||
| 6337 | } | ||
| 6338 | |||
| 6339 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6340 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6341 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6342 | |||
| 6343 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c' | ||
| 6344 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2010-07-29 15:38:15 +0000 | ||
| 6345 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 6346 | @@ -15,6 +15,6 @@ | ||
| 6347 | out_float32x4x3_t = vld3q_f32 (0); | ||
| 6348 | } | ||
| 6349 | |||
| 6350 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6351 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6352 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6353 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6354 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6355 | |||
| 6356 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c' | ||
| 6357 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2010-07-29 15:38:15 +0000 | ||
| 6358 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 6359 | @@ -15,6 +15,6 @@ | ||
| 6360 | out_poly16x8x3_t = vld3q_p16 (0); | ||
| 6361 | } | ||
| 6362 | |||
| 6363 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6364 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6365 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6366 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6367 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6368 | |||
| 6369 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c' | ||
| 6370 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2010-07-29 15:38:15 +0000 | ||
| 6371 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 6372 | @@ -15,6 +15,6 @@ | ||
| 6373 | out_poly8x16x3_t = vld3q_p8 (0); | ||
| 6374 | } | ||
| 6375 | |||
| 6376 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6377 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6378 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6379 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6380 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6381 | |||
| 6382 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c' | ||
| 6383 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2010-07-29 15:38:15 +0000 | ||
| 6384 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 6385 | @@ -15,6 +15,6 @@ | ||
| 6386 | out_int16x8x3_t = vld3q_s16 (0); | ||
| 6387 | } | ||
| 6388 | |||
| 6389 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6390 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6391 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6392 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6393 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6394 | |||
| 6395 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c' | ||
| 6396 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2010-07-29 15:38:15 +0000 | ||
| 6397 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 6398 | @@ -15,6 +15,6 @@ | ||
| 6399 | out_int32x4x3_t = vld3q_s32 (0); | ||
| 6400 | } | ||
| 6401 | |||
| 6402 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6403 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6404 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6405 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6406 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6407 | |||
| 6408 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c' | ||
| 6409 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2010-07-29 15:38:15 +0000 | ||
| 6410 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 6411 | @@ -15,6 +15,6 @@ | ||
| 6412 | out_int8x16x3_t = vld3q_s8 (0); | ||
| 6413 | } | ||
| 6414 | |||
| 6415 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6416 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6417 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6418 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6419 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6420 | |||
| 6421 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c' | ||
| 6422 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2010-07-29 15:38:15 +0000 | ||
| 6423 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 6424 | @@ -15,6 +15,6 @@ | ||
| 6425 | out_uint16x8x3_t = vld3q_u16 (0); | ||
| 6426 | } | ||
| 6427 | |||
| 6428 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6429 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6430 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6431 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6432 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6433 | |||
| 6434 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c' | ||
| 6435 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2010-07-29 15:38:15 +0000 | ||
| 6436 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 6437 | @@ -15,6 +15,6 @@ | ||
| 6438 | out_uint32x4x3_t = vld3q_u32 (0); | ||
| 6439 | } | ||
| 6440 | |||
| 6441 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6442 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6443 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6444 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6445 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6446 | |||
| 6447 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c' | ||
| 6448 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2010-07-29 15:38:15 +0000 | ||
| 6449 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 6450 | @@ -15,6 +15,6 @@ | ||
| 6451 | out_uint8x16x3_t = vld3q_u8 (0); | ||
| 6452 | } | ||
| 6453 | |||
| 6454 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6455 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6456 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6457 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6458 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6459 | |||
| 6460 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c' | ||
| 6461 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2010-07-29 15:38:15 +0000 | ||
| 6462 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2010-08-20 13:27:11 +0000 | ||
| 6463 | @@ -15,5 +15,5 @@ | ||
| 6464 | out_float32x2x3_t = vld3_dup_f32 (0); | ||
| 6465 | } | ||
| 6466 | |||
| 6467 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6468 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6469 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6470 | |||
| 6471 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c' | ||
| 6472 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2010-07-29 15:38:15 +0000 | ||
| 6473 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2010-08-20 13:27:11 +0000 | ||
| 6474 | @@ -15,5 +15,5 @@ | ||
| 6475 | out_poly16x4x3_t = vld3_dup_p16 (0); | ||
| 6476 | } | ||
| 6477 | |||
| 6478 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6479 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6480 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6481 | |||
| 6482 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c' | ||
| 6483 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2010-07-29 15:38:15 +0000 | ||
| 6484 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2010-08-20 13:27:11 +0000 | ||
| 6485 | @@ -15,5 +15,5 @@ | ||
| 6486 | out_poly8x8x3_t = vld3_dup_p8 (0); | ||
| 6487 | } | ||
| 6488 | |||
| 6489 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6490 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6491 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6492 | |||
| 6493 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c' | ||
| 6494 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2010-07-29 15:38:15 +0000 | ||
| 6495 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2010-08-20 13:27:11 +0000 | ||
| 6496 | @@ -15,5 +15,5 @@ | ||
| 6497 | out_int16x4x3_t = vld3_dup_s16 (0); | ||
| 6498 | } | ||
| 6499 | |||
| 6500 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6501 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6502 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6503 | |||
| 6504 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c' | ||
| 6505 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2010-07-29 15:38:15 +0000 | ||
| 6506 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2010-08-20 13:27:11 +0000 | ||
| 6507 | @@ -15,5 +15,5 @@ | ||
| 6508 | out_int32x2x3_t = vld3_dup_s32 (0); | ||
| 6509 | } | ||
| 6510 | |||
| 6511 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6512 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6513 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6514 | |||
| 6515 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c' | ||
| 6516 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2010-07-29 15:38:15 +0000 | ||
| 6517 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2010-08-20 13:27:11 +0000 | ||
| 6518 | @@ -15,5 +15,5 @@ | ||
| 6519 | out_int64x1x3_t = vld3_dup_s64 (0); | ||
| 6520 | } | ||
| 6521 | |||
| 6522 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6523 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6524 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6525 | |||
| 6526 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c' | ||
| 6527 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2010-07-29 15:38:15 +0000 | ||
| 6528 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2010-08-20 13:27:11 +0000 | ||
| 6529 | @@ -15,5 +15,5 @@ | ||
| 6530 | out_int8x8x3_t = vld3_dup_s8 (0); | ||
| 6531 | } | ||
| 6532 | |||
| 6533 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6534 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6535 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6536 | |||
| 6537 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c' | ||
| 6538 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2010-07-29 15:38:15 +0000 | ||
| 6539 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2010-08-20 13:27:11 +0000 | ||
| 6540 | @@ -15,5 +15,5 @@ | ||
| 6541 | out_uint16x4x3_t = vld3_dup_u16 (0); | ||
| 6542 | } | ||
| 6543 | |||
| 6544 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6545 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6546 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6547 | |||
| 6548 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c' | ||
| 6549 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2010-07-29 15:38:15 +0000 | ||
| 6550 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2010-08-20 13:27:11 +0000 | ||
| 6551 | @@ -15,5 +15,5 @@ | ||
| 6552 | out_uint32x2x3_t = vld3_dup_u32 (0); | ||
| 6553 | } | ||
| 6554 | |||
| 6555 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6556 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6557 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6558 | |||
| 6559 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c' | ||
| 6560 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2010-07-29 15:38:15 +0000 | ||
| 6561 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2010-08-20 13:27:11 +0000 | ||
| 6562 | @@ -15,5 +15,5 @@ | ||
| 6563 | out_uint64x1x3_t = vld3_dup_u64 (0); | ||
| 6564 | } | ||
| 6565 | |||
| 6566 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6567 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6568 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6569 | |||
| 6570 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c' | ||
| 6571 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2010-07-29 15:38:15 +0000 | ||
| 6572 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2010-08-20 13:27:11 +0000 | ||
| 6573 | @@ -15,5 +15,5 @@ | ||
| 6574 | out_uint8x8x3_t = vld3_dup_u8 (0); | ||
| 6575 | } | ||
| 6576 | |||
| 6577 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6578 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6579 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6580 | |||
| 6581 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c' | ||
| 6582 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 6583 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 6584 | @@ -16,5 +16,5 @@ | ||
| 6585 | out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1); | ||
| 6586 | } | ||
| 6587 | |||
| 6588 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6589 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6590 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6591 | |||
| 6592 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c' | ||
| 6593 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 6594 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 6595 | @@ -16,5 +16,5 @@ | ||
| 6596 | out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1); | ||
| 6597 | } | ||
| 6598 | |||
| 6599 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6600 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6601 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6602 | |||
| 6603 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c' | ||
| 6604 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 6605 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 6606 | @@ -16,5 +16,5 @@ | ||
| 6607 | out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1); | ||
| 6608 | } | ||
| 6609 | |||
| 6610 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6611 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6612 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6613 | |||
| 6614 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c' | ||
| 6615 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 6616 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 6617 | @@ -16,5 +16,5 @@ | ||
| 6618 | out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1); | ||
| 6619 | } | ||
| 6620 | |||
| 6621 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6622 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6623 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6624 | |||
| 6625 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c' | ||
| 6626 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 6627 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 6628 | @@ -16,5 +16,5 @@ | ||
| 6629 | out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1); | ||
| 6630 | } | ||
| 6631 | |||
| 6632 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6633 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6634 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6635 | |||
| 6636 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c' | ||
| 6637 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 6638 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 6639 | @@ -16,5 +16,5 @@ | ||
| 6640 | out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1); | ||
| 6641 | } | ||
| 6642 | |||
| 6643 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6644 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6645 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6646 | |||
| 6647 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c' | ||
| 6648 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 6649 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 6650 | @@ -16,5 +16,5 @@ | ||
| 6651 | out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1); | ||
| 6652 | } | ||
| 6653 | |||
| 6654 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6655 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6656 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6657 | |||
| 6658 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c' | ||
| 6659 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 6660 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 6661 | @@ -16,5 +16,5 @@ | ||
| 6662 | out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1); | ||
| 6663 | } | ||
| 6664 | |||
| 6665 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6666 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6667 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6668 | |||
| 6669 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c' | ||
| 6670 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 6671 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 6672 | @@ -16,5 +16,5 @@ | ||
| 6673 | out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1); | ||
| 6674 | } | ||
| 6675 | |||
| 6676 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6677 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6678 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6679 | |||
| 6680 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3f32.c' | ||
| 6681 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2010-07-29 15:38:15 +0000 | ||
| 6682 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2010-08-20 13:27:11 +0000 | ||
| 6683 | @@ -15,5 +15,5 @@ | ||
| 6684 | out_float32x2x3_t = vld3_f32 (0); | ||
| 6685 | } | ||
| 6686 | |||
| 6687 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6688 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6689 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6690 | |||
| 6691 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p16.c' | ||
| 6692 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2010-07-29 15:38:15 +0000 | ||
| 6693 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2010-08-20 13:27:11 +0000 | ||
| 6694 | @@ -15,5 +15,5 @@ | ||
| 6695 | out_poly16x4x3_t = vld3_p16 (0); | ||
| 6696 | } | ||
| 6697 | |||
| 6698 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6699 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6700 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6701 | |||
| 6702 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p8.c' | ||
| 6703 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2010-07-29 15:38:15 +0000 | ||
| 6704 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2010-08-20 13:27:11 +0000 | ||
| 6705 | @@ -15,5 +15,5 @@ | ||
| 6706 | out_poly8x8x3_t = vld3_p8 (0); | ||
| 6707 | } | ||
| 6708 | |||
| 6709 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6710 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6711 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6712 | |||
| 6713 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s16.c' | ||
| 6714 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2010-07-29 15:38:15 +0000 | ||
| 6715 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2010-08-20 13:27:11 +0000 | ||
| 6716 | @@ -15,5 +15,5 @@ | ||
| 6717 | out_int16x4x3_t = vld3_s16 (0); | ||
| 6718 | } | ||
| 6719 | |||
| 6720 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6721 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6722 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6723 | |||
| 6724 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s32.c' | ||
| 6725 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2010-07-29 15:38:15 +0000 | ||
| 6726 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2010-08-20 13:27:11 +0000 | ||
| 6727 | @@ -15,5 +15,5 @@ | ||
| 6728 | out_int32x2x3_t = vld3_s32 (0); | ||
| 6729 | } | ||
| 6730 | |||
| 6731 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6732 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6733 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6734 | |||
| 6735 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s64.c' | ||
| 6736 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2010-07-29 15:38:15 +0000 | ||
| 6737 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2010-08-20 13:27:11 +0000 | ||
| 6738 | @@ -15,5 +15,5 @@ | ||
| 6739 | out_int64x1x3_t = vld3_s64 (0); | ||
| 6740 | } | ||
| 6741 | |||
| 6742 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6743 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6744 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6745 | |||
| 6746 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s8.c' | ||
| 6747 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2010-07-29 15:38:15 +0000 | ||
| 6748 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2010-08-20 13:27:11 +0000 | ||
| 6749 | @@ -15,5 +15,5 @@ | ||
| 6750 | out_int8x8x3_t = vld3_s8 (0); | ||
| 6751 | } | ||
| 6752 | |||
| 6753 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6754 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6755 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6756 | |||
| 6757 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u16.c' | ||
| 6758 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2010-07-29 15:38:15 +0000 | ||
| 6759 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2010-08-20 13:27:11 +0000 | ||
| 6760 | @@ -15,5 +15,5 @@ | ||
| 6761 | out_uint16x4x3_t = vld3_u16 (0); | ||
| 6762 | } | ||
| 6763 | |||
| 6764 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6765 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6766 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6767 | |||
| 6768 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u32.c' | ||
| 6769 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2010-07-29 15:38:15 +0000 | ||
| 6770 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2010-08-20 13:27:11 +0000 | ||
| 6771 | @@ -15,5 +15,5 @@ | ||
| 6772 | out_uint32x2x3_t = vld3_u32 (0); | ||
| 6773 | } | ||
| 6774 | |||
| 6775 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6776 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6777 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6778 | |||
| 6779 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u64.c' | ||
| 6780 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2010-07-29 15:38:15 +0000 | ||
| 6781 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2010-08-20 13:27:11 +0000 | ||
| 6782 | @@ -15,5 +15,5 @@ | ||
| 6783 | out_uint64x1x3_t = vld3_u64 (0); | ||
| 6784 | } | ||
| 6785 | |||
| 6786 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6787 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6788 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6789 | |||
| 6790 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u8.c' | ||
| 6791 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2010-07-29 15:38:15 +0000 | ||
| 6792 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2010-08-20 13:27:11 +0000 | ||
| 6793 | @@ -15,5 +15,5 @@ | ||
| 6794 | out_uint8x8x3_t = vld3_u8 (0); | ||
| 6795 | } | ||
| 6796 | |||
| 6797 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6798 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6799 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6800 | |||
| 6801 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c' | ||
| 6802 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 6803 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 6804 | @@ -16,5 +16,5 @@ | ||
| 6805 | out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1); | ||
| 6806 | } | ||
| 6807 | |||
| 6808 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6809 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6810 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6811 | |||
| 6812 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c' | ||
| 6813 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 6814 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 6815 | @@ -16,5 +16,5 @@ | ||
| 6816 | out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1); | ||
| 6817 | } | ||
| 6818 | |||
| 6819 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6820 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6821 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6822 | |||
| 6823 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c' | ||
| 6824 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 6825 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 6826 | @@ -16,5 +16,5 @@ | ||
| 6827 | out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1); | ||
| 6828 | } | ||
| 6829 | |||
| 6830 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6831 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6832 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6833 | |||
| 6834 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c' | ||
| 6835 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 6836 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 6837 | @@ -16,5 +16,5 @@ | ||
| 6838 | out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1); | ||
| 6839 | } | ||
| 6840 | |||
| 6841 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6842 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6843 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6844 | |||
| 6845 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c' | ||
| 6846 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 6847 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 6848 | @@ -16,5 +16,5 @@ | ||
| 6849 | out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1); | ||
| 6850 | } | ||
| 6851 | |||
| 6852 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6853 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6854 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6855 | |||
| 6856 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c' | ||
| 6857 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 6858 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 6859 | @@ -16,5 +16,5 @@ | ||
| 6860 | out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1); | ||
| 6861 | } | ||
| 6862 | |||
| 6863 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6864 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6865 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6866 | |||
| 6867 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c' | ||
| 6868 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2010-07-29 15:38:15 +0000 | ||
| 6869 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 6870 | @@ -15,6 +15,6 @@ | ||
| 6871 | out_float32x4x4_t = vld4q_f32 (0); | ||
| 6872 | } | ||
| 6873 | |||
| 6874 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6875 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6876 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6877 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6878 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6879 | |||
| 6880 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c' | ||
| 6881 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2010-07-29 15:38:15 +0000 | ||
| 6882 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 6883 | @@ -15,6 +15,6 @@ | ||
| 6884 | out_poly16x8x4_t = vld4q_p16 (0); | ||
| 6885 | } | ||
| 6886 | |||
| 6887 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6888 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6889 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6890 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6891 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6892 | |||
| 6893 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c' | ||
| 6894 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2010-07-29 15:38:15 +0000 | ||
| 6895 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 6896 | @@ -15,6 +15,6 @@ | ||
| 6897 | out_poly8x16x4_t = vld4q_p8 (0); | ||
| 6898 | } | ||
| 6899 | |||
| 6900 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6901 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6902 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6903 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6904 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6905 | |||
| 6906 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c' | ||
| 6907 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2010-07-29 15:38:15 +0000 | ||
| 6908 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 6909 | @@ -15,6 +15,6 @@ | ||
| 6910 | out_int16x8x4_t = vld4q_s16 (0); | ||
| 6911 | } | ||
| 6912 | |||
| 6913 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6914 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6915 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6916 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6917 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6918 | |||
| 6919 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c' | ||
| 6920 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2010-07-29 15:38:15 +0000 | ||
| 6921 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 6922 | @@ -15,6 +15,6 @@ | ||
| 6923 | out_int32x4x4_t = vld4q_s32 (0); | ||
| 6924 | } | ||
| 6925 | |||
| 6926 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6927 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6928 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6929 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6930 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6931 | |||
| 6932 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c' | ||
| 6933 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2010-07-29 15:38:15 +0000 | ||
| 6934 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 6935 | @@ -15,6 +15,6 @@ | ||
| 6936 | out_int8x16x4_t = vld4q_s8 (0); | ||
| 6937 | } | ||
| 6938 | |||
| 6939 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6940 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6941 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6942 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6943 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6944 | |||
| 6945 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c' | ||
| 6946 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2010-07-29 15:38:15 +0000 | ||
| 6947 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 6948 | @@ -15,6 +15,6 @@ | ||
| 6949 | out_uint16x8x4_t = vld4q_u16 (0); | ||
| 6950 | } | ||
| 6951 | |||
| 6952 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6953 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6954 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6955 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6956 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6957 | |||
| 6958 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c' | ||
| 6959 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2010-07-29 15:38:15 +0000 | ||
| 6960 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 6961 | @@ -15,6 +15,6 @@ | ||
| 6962 | out_uint32x4x4_t = vld4q_u32 (0); | ||
| 6963 | } | ||
| 6964 | |||
| 6965 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6966 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6967 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6968 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6969 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6970 | |||
| 6971 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c' | ||
| 6972 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2010-07-29 15:38:15 +0000 | ||
| 6973 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 6974 | @@ -15,6 +15,6 @@ | ||
| 6975 | out_uint8x16x4_t = vld4q_u8 (0); | ||
| 6976 | } | ||
| 6977 | |||
| 6978 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6979 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6980 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6981 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6982 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6983 | |||
| 6984 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c' | ||
| 6985 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2010-07-29 15:38:15 +0000 | ||
| 6986 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2010-08-20 13:27:11 +0000 | ||
| 6987 | @@ -15,5 +15,5 @@ | ||
| 6988 | out_float32x2x4_t = vld4_dup_f32 (0); | ||
| 6989 | } | ||
| 6990 | |||
| 6991 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 6992 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6993 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6994 | |||
| 6995 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c' | ||
| 6996 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2010-07-29 15:38:15 +0000 | ||
| 6997 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2010-08-20 13:27:11 +0000 | ||
| 6998 | @@ -15,5 +15,5 @@ | ||
| 6999 | out_poly16x4x4_t = vld4_dup_p16 (0); | ||
| 7000 | } | ||
| 7001 | |||
| 7002 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7003 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7004 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7005 | |||
| 7006 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c' | ||
| 7007 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2010-07-29 15:38:15 +0000 | ||
| 7008 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2010-08-20 13:27:11 +0000 | ||
| 7009 | @@ -15,5 +15,5 @@ | ||
| 7010 | out_poly8x8x4_t = vld4_dup_p8 (0); | ||
| 7011 | } | ||
| 7012 | |||
| 7013 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7014 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7015 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7016 | |||
| 7017 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c' | ||
| 7018 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2010-07-29 15:38:15 +0000 | ||
| 7019 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2010-08-20 13:27:11 +0000 | ||
| 7020 | @@ -15,5 +15,5 @@ | ||
| 7021 | out_int16x4x4_t = vld4_dup_s16 (0); | ||
| 7022 | } | ||
| 7023 | |||
| 7024 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7025 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7026 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7027 | |||
| 7028 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c' | ||
| 7029 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2010-07-29 15:38:15 +0000 | ||
| 7030 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2010-08-20 13:27:11 +0000 | ||
| 7031 | @@ -15,5 +15,5 @@ | ||
| 7032 | out_int32x2x4_t = vld4_dup_s32 (0); | ||
| 7033 | } | ||
| 7034 | |||
| 7035 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7036 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7037 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7038 | |||
| 7039 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c' | ||
| 7040 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2010-07-29 15:38:15 +0000 | ||
| 7041 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2010-08-20 13:27:11 +0000 | ||
| 7042 | @@ -15,5 +15,5 @@ | ||
| 7043 | out_int64x1x4_t = vld4_dup_s64 (0); | ||
| 7044 | } | ||
| 7045 | |||
| 7046 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7047 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7048 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7049 | |||
| 7050 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c' | ||
| 7051 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2010-07-29 15:38:15 +0000 | ||
| 7052 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2010-08-20 13:27:11 +0000 | ||
| 7053 | @@ -15,5 +15,5 @@ | ||
| 7054 | out_int8x8x4_t = vld4_dup_s8 (0); | ||
| 7055 | } | ||
| 7056 | |||
| 7057 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7058 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7059 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7060 | |||
| 7061 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c' | ||
| 7062 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2010-07-29 15:38:15 +0000 | ||
| 7063 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2010-08-20 13:27:11 +0000 | ||
| 7064 | @@ -15,5 +15,5 @@ | ||
| 7065 | out_uint16x4x4_t = vld4_dup_u16 (0); | ||
| 7066 | } | ||
| 7067 | |||
| 7068 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7069 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7070 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7071 | |||
| 7072 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c' | ||
| 7073 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2010-07-29 15:38:15 +0000 | ||
| 7074 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2010-08-20 13:27:11 +0000 | ||
| 7075 | @@ -15,5 +15,5 @@ | ||
| 7076 | out_uint32x2x4_t = vld4_dup_u32 (0); | ||
| 7077 | } | ||
| 7078 | |||
| 7079 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7080 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7081 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7082 | |||
| 7083 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c' | ||
| 7084 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2010-07-29 15:38:15 +0000 | ||
| 7085 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2010-08-20 13:27:11 +0000 | ||
| 7086 | @@ -15,5 +15,5 @@ | ||
| 7087 | out_uint64x1x4_t = vld4_dup_u64 (0); | ||
| 7088 | } | ||
| 7089 | |||
| 7090 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7091 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7092 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7093 | |||
| 7094 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c' | ||
| 7095 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2010-07-29 15:38:15 +0000 | ||
| 7096 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2010-08-20 13:27:11 +0000 | ||
| 7097 | @@ -15,5 +15,5 @@ | ||
| 7098 | out_uint8x8x4_t = vld4_dup_u8 (0); | ||
| 7099 | } | ||
| 7100 | |||
| 7101 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7102 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7103 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7104 | |||
| 7105 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c' | ||
| 7106 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 7107 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 7108 | @@ -16,5 +16,5 @@ | ||
| 7109 | out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1); | ||
| 7110 | } | ||
| 7111 | |||
| 7112 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7113 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7114 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7115 | |||
| 7116 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c' | ||
| 7117 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 7118 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 7119 | @@ -16,5 +16,5 @@ | ||
| 7120 | out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1); | ||
| 7121 | } | ||
| 7122 | |||
| 7123 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7124 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7125 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7126 | |||
| 7127 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c' | ||
| 7128 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 7129 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 7130 | @@ -16,5 +16,5 @@ | ||
| 7131 | out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1); | ||
| 7132 | } | ||
| 7133 | |||
| 7134 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7135 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7136 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7137 | |||
| 7138 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c' | ||
| 7139 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 7140 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 7141 | @@ -16,5 +16,5 @@ | ||
| 7142 | out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1); | ||
| 7143 | } | ||
| 7144 | |||
| 7145 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7146 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7147 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7148 | |||
| 7149 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c' | ||
| 7150 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 7151 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 7152 | @@ -16,5 +16,5 @@ | ||
| 7153 | out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1); | ||
| 7154 | } | ||
| 7155 | |||
| 7156 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7157 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7158 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7159 | |||
| 7160 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c' | ||
| 7161 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 7162 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 7163 | @@ -16,5 +16,5 @@ | ||
| 7164 | out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1); | ||
| 7165 | } | ||
| 7166 | |||
| 7167 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7168 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7169 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7170 | |||
| 7171 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c' | ||
| 7172 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 7173 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 7174 | @@ -16,5 +16,5 @@ | ||
| 7175 | out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1); | ||
| 7176 | } | ||
| 7177 | |||
| 7178 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7179 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7180 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7181 | |||
| 7182 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c' | ||
| 7183 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 7184 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 7185 | @@ -16,5 +16,5 @@ | ||
| 7186 | out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1); | ||
| 7187 | } | ||
| 7188 | |||
| 7189 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7190 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7191 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7192 | |||
| 7193 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c' | ||
| 7194 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 7195 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 7196 | @@ -16,5 +16,5 @@ | ||
| 7197 | out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1); | ||
| 7198 | } | ||
| 7199 | |||
| 7200 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7201 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7202 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7203 | |||
| 7204 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4f32.c' | ||
| 7205 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2010-07-29 15:38:15 +0000 | ||
| 7206 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2010-08-20 13:27:11 +0000 | ||
| 7207 | @@ -15,5 +15,5 @@ | ||
| 7208 | out_float32x2x4_t = vld4_f32 (0); | ||
| 7209 | } | ||
| 7210 | |||
| 7211 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7212 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7213 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7214 | |||
| 7215 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p16.c' | ||
| 7216 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2010-07-29 15:38:15 +0000 | ||
| 7217 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2010-08-20 13:27:11 +0000 | ||
| 7218 | @@ -15,5 +15,5 @@ | ||
| 7219 | out_poly16x4x4_t = vld4_p16 (0); | ||
| 7220 | } | ||
| 7221 | |||
| 7222 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7223 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7224 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7225 | |||
| 7226 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p8.c' | ||
| 7227 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2010-07-29 15:38:15 +0000 | ||
| 7228 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2010-08-20 13:27:11 +0000 | ||
| 7229 | @@ -15,5 +15,5 @@ | ||
| 7230 | out_poly8x8x4_t = vld4_p8 (0); | ||
| 7231 | } | ||
| 7232 | |||
| 7233 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7234 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7235 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7236 | |||
| 7237 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s16.c' | ||
| 7238 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2010-07-29 15:38:15 +0000 | ||
| 7239 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2010-08-20 13:27:11 +0000 | ||
| 7240 | @@ -15,5 +15,5 @@ | ||
| 7241 | out_int16x4x4_t = vld4_s16 (0); | ||
| 7242 | } | ||
| 7243 | |||
| 7244 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7245 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7246 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7247 | |||
| 7248 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s32.c' | ||
| 7249 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2010-07-29 15:38:15 +0000 | ||
| 7250 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2010-08-20 13:27:11 +0000 | ||
| 7251 | @@ -15,5 +15,5 @@ | ||
| 7252 | out_int32x2x4_t = vld4_s32 (0); | ||
| 7253 | } | ||
| 7254 | |||
| 7255 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7256 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7257 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7258 | |||
| 7259 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s64.c' | ||
| 7260 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2010-07-29 15:38:15 +0000 | ||
| 7261 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2010-08-20 13:27:11 +0000 | ||
| 7262 | @@ -15,5 +15,5 @@ | ||
| 7263 | out_int64x1x4_t = vld4_s64 (0); | ||
| 7264 | } | ||
| 7265 | |||
| 7266 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7267 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7268 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7269 | |||
| 7270 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s8.c' | ||
| 7271 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2010-07-29 15:38:15 +0000 | ||
| 7272 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2010-08-20 13:27:11 +0000 | ||
| 7273 | @@ -15,5 +15,5 @@ | ||
| 7274 | out_int8x8x4_t = vld4_s8 (0); | ||
| 7275 | } | ||
| 7276 | |||
| 7277 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7278 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7279 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7280 | |||
| 7281 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u16.c' | ||
| 7282 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2010-07-29 15:38:15 +0000 | ||
| 7283 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2010-08-20 13:27:11 +0000 | ||
| 7284 | @@ -15,5 +15,5 @@ | ||
| 7285 | out_uint16x4x4_t = vld4_u16 (0); | ||
| 7286 | } | ||
| 7287 | |||
| 7288 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7289 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7290 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7291 | |||
| 7292 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u32.c' | ||
| 7293 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2010-07-29 15:38:15 +0000 | ||
| 7294 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2010-08-20 13:27:11 +0000 | ||
| 7295 | @@ -15,5 +15,5 @@ | ||
| 7296 | out_uint32x2x4_t = vld4_u32 (0); | ||
| 7297 | } | ||
| 7298 | |||
| 7299 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7300 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7301 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7302 | |||
| 7303 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u64.c' | ||
| 7304 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2010-07-29 15:38:15 +0000 | ||
| 7305 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2010-08-20 13:27:11 +0000 | ||
| 7306 | @@ -15,5 +15,5 @@ | ||
| 7307 | out_uint64x1x4_t = vld4_u64 (0); | ||
| 7308 | } | ||
| 7309 | |||
| 7310 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7311 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7312 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7313 | |||
| 7314 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u8.c' | ||
| 7315 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2010-07-29 15:38:15 +0000 | ||
| 7316 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2010-08-20 13:27:11 +0000 | ||
| 7317 | @@ -15,5 +15,5 @@ | ||
| 7318 | out_uint8x8x4_t = vld4_u8 (0); | ||
| 7319 | } | ||
| 7320 | |||
| 7321 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7322 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7323 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7324 | |||
| 7325 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c' | ||
| 7326 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c 2010-07-29 15:38:15 +0000 | ||
| 7327 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c 2010-08-20 13:27:11 +0000 | ||
| 7328 | @@ -17,5 +17,5 @@ | ||
| 7329 | out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 7330 | } | ||
| 7331 | |||
| 7332 | -/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7333 | +/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7334 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7335 | |||
| 7336 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c' | ||
| 7337 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c 2010-07-29 15:38:15 +0000 | ||
| 7338 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c 2010-08-20 13:27:11 +0000 | ||
| 7339 | @@ -17,5 +17,5 @@ | ||
| 7340 | out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 7341 | } | ||
| 7342 | |||
| 7343 | -/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7344 | +/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7345 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7346 | |||
| 7347 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c' | ||
| 7348 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c 2010-07-29 15:38:15 +0000 | ||
| 7349 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c 2010-08-20 13:27:11 +0000 | ||
| 7350 | @@ -17,5 +17,5 @@ | ||
| 7351 | out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 7352 | } | ||
| 7353 | |||
| 7354 | -/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7355 | +/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7356 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7357 | |||
| 7358 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c' | ||
| 7359 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c 2010-07-29 15:38:15 +0000 | ||
| 7360 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c 2010-08-20 13:27:11 +0000 | ||
| 7361 | @@ -17,5 +17,5 @@ | ||
| 7362 | out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 7363 | } | ||
| 7364 | |||
| 7365 | -/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7366 | +/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7367 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7368 | |||
| 7369 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c' | ||
| 7370 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c 2010-07-29 15:38:15 +0000 | ||
| 7371 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c 2010-08-20 13:27:11 +0000 | ||
| 7372 | @@ -17,5 +17,5 @@ | ||
| 7373 | out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 7374 | } | ||
| 7375 | |||
| 7376 | -/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7377 | +/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7378 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7379 | |||
| 7380 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c' | ||
| 7381 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c 2010-07-29 15:38:15 +0000 | ||
| 7382 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c 2010-08-20 13:27:11 +0000 | ||
| 7383 | @@ -17,5 +17,5 @@ | ||
| 7384 | out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 7385 | } | ||
| 7386 | |||
| 7387 | -/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7388 | +/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7389 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7390 | |||
| 7391 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c' | ||
| 7392 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c 2010-07-29 15:38:15 +0000 | ||
| 7393 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c 2010-08-20 13:27:11 +0000 | ||
| 7394 | @@ -17,5 +17,5 @@ | ||
| 7395 | out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 7396 | } | ||
| 7397 | |||
| 7398 | -/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7399 | +/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7400 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7401 | |||
| 7402 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxf32.c' | ||
| 7403 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c 2010-07-29 15:38:15 +0000 | ||
| 7404 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c 2010-08-20 13:27:11 +0000 | ||
| 7405 | @@ -17,5 +17,5 @@ | ||
| 7406 | out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 7407 | } | ||
| 7408 | |||
| 7409 | -/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7410 | +/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7411 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7412 | |||
| 7413 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxs16.c' | ||
| 7414 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c 2010-07-29 15:38:15 +0000 | ||
| 7415 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c 2010-08-20 13:27:11 +0000 | ||
| 7416 | @@ -17,5 +17,5 @@ | ||
| 7417 | out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 7418 | } | ||
| 7419 | |||
| 7420 | -/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7421 | +/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7422 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7423 | |||
| 7424 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxs32.c' | ||
| 7425 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c 2010-07-29 15:38:15 +0000 | ||
| 7426 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c 2010-08-20 13:27:11 +0000 | ||
| 7427 | @@ -17,5 +17,5 @@ | ||
| 7428 | out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 7429 | } | ||
| 7430 | |||
| 7431 | -/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7432 | +/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7433 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7434 | |||
| 7435 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxs8.c' | ||
| 7436 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c 2010-07-29 15:38:15 +0000 | ||
| 7437 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c 2010-08-20 13:27:11 +0000 | ||
| 7438 | @@ -17,5 +17,5 @@ | ||
| 7439 | out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 7440 | } | ||
| 7441 | |||
| 7442 | -/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7443 | +/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7444 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7445 | |||
| 7446 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxu16.c' | ||
| 7447 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c 2010-07-29 15:38:15 +0000 | ||
| 7448 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c 2010-08-20 13:27:11 +0000 | ||
| 7449 | @@ -17,5 +17,5 @@ | ||
| 7450 | out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 7451 | } | ||
| 7452 | |||
| 7453 | -/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7454 | +/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7455 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7456 | |||
| 7457 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxu32.c' | ||
| 7458 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c 2010-07-29 15:38:15 +0000 | ||
| 7459 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c 2010-08-20 13:27:11 +0000 | ||
| 7460 | @@ -17,5 +17,5 @@ | ||
| 7461 | out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 7462 | } | ||
| 7463 | |||
| 7464 | -/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7465 | +/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7466 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7467 | |||
| 7468 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmaxu8.c' | ||
| 7469 | --- old/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c 2010-07-29 15:38:15 +0000 | ||
| 7470 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c 2010-08-20 13:27:11 +0000 | ||
| 7471 | @@ -17,5 +17,5 @@ | ||
| 7472 | out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 7473 | } | ||
| 7474 | |||
| 7475 | -/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7476 | +/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7477 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7478 | |||
| 7479 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vminQf32.c' | ||
| 7480 | --- old/gcc/testsuite/gcc.target/arm/neon/vminQf32.c 2010-07-29 15:38:15 +0000 | ||
| 7481 | +++ new/gcc/testsuite/gcc.target/arm/neon/vminQf32.c 2010-08-20 13:27:11 +0000 | ||
| 7482 | @@ -17,5 +17,5 @@ | ||
| 7483 | out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 7484 | } | ||
| 7485 | |||
| 7486 | -/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7487 | +/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7488 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7489 | |||
| 7490 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vminQs16.c' | ||
| 7491 | --- old/gcc/testsuite/gcc.target/arm/neon/vminQs16.c 2010-07-29 15:38:15 +0000 | ||
| 7492 | +++ new/gcc/testsuite/gcc.target/arm/neon/vminQs16.c 2010-08-20 13:27:11 +0000 | ||
| 7493 | @@ -17,5 +17,5 @@ | ||
| 7494 | out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 7495 | } | ||
| 7496 | |||
| 7497 | -/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7498 | +/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7499 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7500 | |||
| 7501 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vminQs32.c' | ||
| 7502 | --- old/gcc/testsuite/gcc.target/arm/neon/vminQs32.c 2010-07-29 15:38:15 +0000 | ||
| 7503 | +++ new/gcc/testsuite/gcc.target/arm/neon/vminQs32.c 2010-08-20 13:27:11 +0000 | ||
| 7504 | @@ -17,5 +17,5 @@ | ||
| 7505 | out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 7506 | } | ||
| 7507 | |||
| 7508 | -/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7509 | +/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7510 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7511 | |||
| 7512 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vminQs8.c' | ||
| 7513 | --- old/gcc/testsuite/gcc.target/arm/neon/vminQs8.c 2010-07-29 15:38:15 +0000 | ||
| 7514 | +++ new/gcc/testsuite/gcc.target/arm/neon/vminQs8.c 2010-08-20 13:27:11 +0000 | ||
| 7515 | @@ -17,5 +17,5 @@ | ||
| 7516 | out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 7517 | } | ||
| 7518 | |||
| 7519 | -/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7520 | +/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7521 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7522 | |||
| 7523 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vminQu16.c' | ||
| 7524 | --- old/gcc/testsuite/gcc.target/arm/neon/vminQu16.c 2010-07-29 15:38:15 +0000 | ||
| 7525 | +++ new/gcc/testsuite/gcc.target/arm/neon/vminQu16.c 2010-08-20 13:27:11 +0000 | ||
| 7526 | @@ -17,5 +17,5 @@ | ||
| 7527 | out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 7528 | } | ||
| 7529 | |||
| 7530 | -/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7531 | +/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7532 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7533 | |||
| 7534 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vminQu32.c' | ||
| 7535 | --- old/gcc/testsuite/gcc.target/arm/neon/vminQu32.c 2010-07-29 15:38:15 +0000 | ||
| 7536 | +++ new/gcc/testsuite/gcc.target/arm/neon/vminQu32.c 2010-08-20 13:27:11 +0000 | ||
| 7537 | @@ -17,5 +17,5 @@ | ||
| 7538 | out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 7539 | } | ||
| 7540 | |||
| 7541 | -/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7542 | +/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7543 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7544 | |||
| 7545 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vminQu8.c' | ||
| 7546 | --- old/gcc/testsuite/gcc.target/arm/neon/vminQu8.c 2010-07-29 15:38:15 +0000 | ||
| 7547 | +++ new/gcc/testsuite/gcc.target/arm/neon/vminQu8.c 2010-08-20 13:27:11 +0000 | ||
| 7548 | @@ -17,5 +17,5 @@ | ||
| 7549 | out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 7550 | } | ||
| 7551 | |||
| 7552 | -/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7553 | +/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7554 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7555 | |||
| 7556 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vminf32.c' | ||
| 7557 | --- old/gcc/testsuite/gcc.target/arm/neon/vminf32.c 2010-07-29 15:38:15 +0000 | ||
| 7558 | +++ new/gcc/testsuite/gcc.target/arm/neon/vminf32.c 2010-08-20 13:27:11 +0000 | ||
| 7559 | @@ -17,5 +17,5 @@ | ||
| 7560 | out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 7561 | } | ||
| 7562 | |||
| 7563 | -/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7564 | +/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7565 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7566 | |||
| 7567 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmins16.c' | ||
| 7568 | --- old/gcc/testsuite/gcc.target/arm/neon/vmins16.c 2010-07-29 15:38:15 +0000 | ||
| 7569 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmins16.c 2010-08-20 13:27:11 +0000 | ||
| 7570 | @@ -17,5 +17,5 @@ | ||
| 7571 | out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 7572 | } | ||
| 7573 | |||
| 7574 | -/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7575 | +/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7576 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7577 | |||
| 7578 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmins32.c' | ||
| 7579 | --- old/gcc/testsuite/gcc.target/arm/neon/vmins32.c 2010-07-29 15:38:15 +0000 | ||
| 7580 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmins32.c 2010-08-20 13:27:11 +0000 | ||
| 7581 | @@ -17,5 +17,5 @@ | ||
| 7582 | out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 7583 | } | ||
| 7584 | |||
| 7585 | -/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7586 | +/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7587 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7588 | |||
| 7589 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmins8.c' | ||
| 7590 | --- old/gcc/testsuite/gcc.target/arm/neon/vmins8.c 2010-07-29 15:38:15 +0000 | ||
| 7591 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmins8.c 2010-08-20 13:27:11 +0000 | ||
| 7592 | @@ -17,5 +17,5 @@ | ||
| 7593 | out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 7594 | } | ||
| 7595 | |||
| 7596 | -/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7597 | +/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7598 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7599 | |||
| 7600 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vminu16.c' | ||
| 7601 | --- old/gcc/testsuite/gcc.target/arm/neon/vminu16.c 2010-07-29 15:38:15 +0000 | ||
| 7602 | +++ new/gcc/testsuite/gcc.target/arm/neon/vminu16.c 2010-08-20 13:27:11 +0000 | ||
| 7603 | @@ -17,5 +17,5 @@ | ||
| 7604 | out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 7605 | } | ||
| 7606 | |||
| 7607 | -/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7608 | +/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7609 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7610 | |||
| 7611 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vminu32.c' | ||
| 7612 | --- old/gcc/testsuite/gcc.target/arm/neon/vminu32.c 2010-07-29 15:38:15 +0000 | ||
| 7613 | +++ new/gcc/testsuite/gcc.target/arm/neon/vminu32.c 2010-08-20 13:27:11 +0000 | ||
| 7614 | @@ -17,5 +17,5 @@ | ||
| 7615 | out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 7616 | } | ||
| 7617 | |||
| 7618 | -/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7619 | +/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7620 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7621 | |||
| 7622 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vminu8.c' | ||
| 7623 | --- old/gcc/testsuite/gcc.target/arm/neon/vminu8.c 2010-07-29 15:38:15 +0000 | ||
| 7624 | +++ new/gcc/testsuite/gcc.target/arm/neon/vminu8.c 2010-08-20 13:27:11 +0000 | ||
| 7625 | @@ -17,5 +17,5 @@ | ||
| 7626 | out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 7627 | } | ||
| 7628 | |||
| 7629 | -/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7630 | +/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7631 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7632 | |||
| 7633 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c' | ||
| 7634 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 7635 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 7636 | @@ -18,5 +18,5 @@ | ||
| 7637 | out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1); | ||
| 7638 | } | ||
| 7639 | |||
| 7640 | -/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7641 | +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7642 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7643 | |||
| 7644 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c' | ||
| 7645 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 7646 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 7647 | @@ -18,5 +18,5 @@ | ||
| 7648 | out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1); | ||
| 7649 | } | ||
| 7650 | |||
| 7651 | -/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7652 | +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7653 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7654 | |||
| 7655 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c' | ||
| 7656 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 7657 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 7658 | @@ -18,5 +18,5 @@ | ||
| 7659 | out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1); | ||
| 7660 | } | ||
| 7661 | |||
| 7662 | -/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7663 | +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7664 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7665 | |||
| 7666 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c' | ||
| 7667 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 7668 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 7669 | @@ -18,5 +18,5 @@ | ||
| 7670 | out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1); | ||
| 7671 | } | ||
| 7672 | |||
| 7673 | -/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7674 | +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7675 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7676 | |||
| 7677 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c' | ||
| 7678 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 7679 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 7680 | @@ -18,5 +18,5 @@ | ||
| 7681 | out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1); | ||
| 7682 | } | ||
| 7683 | |||
| 7684 | -/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7685 | +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7686 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7687 | |||
| 7688 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c' | ||
| 7689 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c 2010-07-29 15:38:15 +0000 | ||
| 7690 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c 2010-08-20 13:27:11 +0000 | ||
| 7691 | @@ -18,5 +18,5 @@ | ||
| 7692 | out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t); | ||
| 7693 | } | ||
| 7694 | |||
| 7695 | -/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7696 | +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7697 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7698 | |||
| 7699 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c' | ||
| 7700 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 7701 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 7702 | @@ -18,5 +18,5 @@ | ||
| 7703 | out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t); | ||
| 7704 | } | ||
| 7705 | |||
| 7706 | -/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7707 | +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7708 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7709 | |||
| 7710 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c' | ||
| 7711 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 7712 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 7713 | @@ -18,5 +18,5 @@ | ||
| 7714 | out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t); | ||
| 7715 | } | ||
| 7716 | |||
| 7717 | -/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7718 | +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7719 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7720 | |||
| 7721 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c' | ||
| 7722 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 7723 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 7724 | @@ -18,5 +18,5 @@ | ||
| 7725 | out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t); | ||
| 7726 | } | ||
| 7727 | |||
| 7728 | -/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7729 | +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7730 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7731 | |||
| 7732 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c' | ||
| 7733 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 7734 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 7735 | @@ -18,5 +18,5 @@ | ||
| 7736 | out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t); | ||
| 7737 | } | ||
| 7738 | |||
| 7739 | -/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7740 | +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7741 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7742 | |||
| 7743 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c' | ||
| 7744 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c 2010-07-29 15:38:15 +0000 | ||
| 7745 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c 2010-08-20 13:27:11 +0000 | ||
| 7746 | @@ -18,5 +18,5 @@ | ||
| 7747 | out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); | ||
| 7748 | } | ||
| 7749 | |||
| 7750 | -/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7751 | +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7752 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7753 | |||
| 7754 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c' | ||
| 7755 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c 2010-07-29 15:38:15 +0000 | ||
| 7756 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c 2010-08-20 13:27:11 +0000 | ||
| 7757 | @@ -18,5 +18,5 @@ | ||
| 7758 | out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); | ||
| 7759 | } | ||
| 7760 | |||
| 7761 | -/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7762 | +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7763 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7764 | |||
| 7765 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c' | ||
| 7766 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c 2010-07-29 15:38:15 +0000 | ||
| 7767 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c 2010-08-20 13:27:11 +0000 | ||
| 7768 | @@ -18,5 +18,5 @@ | ||
| 7769 | out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); | ||
| 7770 | } | ||
| 7771 | |||
| 7772 | -/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7773 | +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7774 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7775 | |||
| 7776 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c' | ||
| 7777 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c 2010-07-29 15:38:15 +0000 | ||
| 7778 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c 2010-08-20 13:27:11 +0000 | ||
| 7779 | @@ -18,5 +18,5 @@ | ||
| 7780 | out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); | ||
| 7781 | } | ||
| 7782 | |||
| 7783 | -/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7784 | +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7785 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7786 | |||
| 7787 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c' | ||
| 7788 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c 2010-07-29 15:38:15 +0000 | ||
| 7789 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c 2010-08-20 13:27:11 +0000 | ||
| 7790 | @@ -18,5 +18,5 @@ | ||
| 7791 | out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); | ||
| 7792 | } | ||
| 7793 | |||
| 7794 | -/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7795 | +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7796 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7797 | |||
| 7798 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c' | ||
| 7799 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c 2010-07-29 15:38:15 +0000 | ||
| 7800 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c 2010-08-20 13:27:11 +0000 | ||
| 7801 | @@ -18,5 +18,5 @@ | ||
| 7802 | out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); | ||
| 7803 | } | ||
| 7804 | |||
| 7805 | -/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7806 | +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7807 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7808 | |||
| 7809 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c' | ||
| 7810 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c 2010-07-29 15:38:15 +0000 | ||
| 7811 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c 2010-08-20 13:27:11 +0000 | ||
| 7812 | @@ -18,5 +18,5 @@ | ||
| 7813 | out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); | ||
| 7814 | } | ||
| 7815 | |||
| 7816 | -/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7817 | +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7818 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7819 | |||
| 7820 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c' | ||
| 7821 | --- old/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 7822 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 7823 | @@ -18,5 +18,5 @@ | ||
| 7824 | out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1); | ||
| 7825 | } | ||
| 7826 | |||
| 7827 | -/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7828 | +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7829 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7830 | |||
| 7831 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c' | ||
| 7832 | --- old/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 7833 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 7834 | @@ -18,5 +18,5 @@ | ||
| 7835 | out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); | ||
| 7836 | } | ||
| 7837 | |||
| 7838 | -/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7839 | +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7840 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7841 | |||
| 7842 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c' | ||
| 7843 | --- old/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 7844 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 7845 | @@ -18,5 +18,5 @@ | ||
| 7846 | out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); | ||
| 7847 | } | ||
| 7848 | |||
| 7849 | -/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7850 | +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7851 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7852 | |||
| 7853 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c' | ||
| 7854 | --- old/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 7855 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 7856 | @@ -18,5 +18,5 @@ | ||
| 7857 | out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); | ||
| 7858 | } | ||
| 7859 | |||
| 7860 | -/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7861 | +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7862 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7863 | |||
| 7864 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c' | ||
| 7865 | --- old/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 7866 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 7867 | @@ -18,5 +18,5 @@ | ||
| 7868 | out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); | ||
| 7869 | } | ||
| 7870 | |||
| 7871 | -/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7872 | +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7873 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7874 | |||
| 7875 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c' | ||
| 7876 | --- old/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c 2010-07-29 15:38:15 +0000 | ||
| 7877 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c 2010-08-20 13:27:11 +0000 | ||
| 7878 | @@ -18,5 +18,5 @@ | ||
| 7879 | out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t); | ||
| 7880 | } | ||
| 7881 | |||
| 7882 | -/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7883 | +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7884 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7885 | |||
| 7886 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c' | ||
| 7887 | --- old/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 7888 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 7889 | @@ -18,5 +18,5 @@ | ||
| 7890 | out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t); | ||
| 7891 | } | ||
| 7892 | |||
| 7893 | -/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7894 | +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7895 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7896 | |||
| 7897 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c' | ||
| 7898 | --- old/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 7899 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 7900 | @@ -18,5 +18,5 @@ | ||
| 7901 | out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t); | ||
| 7902 | } | ||
| 7903 | |||
| 7904 | -/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7905 | +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7906 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7907 | |||
| 7908 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c' | ||
| 7909 | --- old/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 7910 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 7911 | @@ -18,5 +18,5 @@ | ||
| 7912 | out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t); | ||
| 7913 | } | ||
| 7914 | |||
| 7915 | -/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7916 | +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7917 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7918 | |||
| 7919 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c' | ||
| 7920 | --- old/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 7921 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 7922 | @@ -18,5 +18,5 @@ | ||
| 7923 | out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t); | ||
| 7924 | } | ||
| 7925 | |||
| 7926 | -/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7927 | +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7928 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7929 | |||
| 7930 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlaf32.c' | ||
| 7931 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c 2010-07-29 15:38:15 +0000 | ||
| 7932 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c 2010-08-20 13:27:11 +0000 | ||
| 7933 | @@ -18,5 +18,5 @@ | ||
| 7934 | out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); | ||
| 7935 | } | ||
| 7936 | |||
| 7937 | -/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7938 | +/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7939 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7940 | |||
| 7941 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c' | ||
| 7942 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 7943 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 7944 | @@ -18,5 +18,5 @@ | ||
| 7945 | out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); | ||
| 7946 | } | ||
| 7947 | |||
| 7948 | -/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7949 | +/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7950 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7951 | |||
| 7952 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c' | ||
| 7953 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 7954 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 7955 | @@ -18,5 +18,5 @@ | ||
| 7956 | out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); | ||
| 7957 | } | ||
| 7958 | |||
| 7959 | -/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7960 | +/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7961 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7962 | |||
| 7963 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c' | ||
| 7964 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 7965 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 7966 | @@ -18,5 +18,5 @@ | ||
| 7967 | out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); | ||
| 7968 | } | ||
| 7969 | |||
| 7970 | -/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7971 | +/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7972 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7973 | |||
| 7974 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c' | ||
| 7975 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 7976 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 7977 | @@ -18,5 +18,5 @@ | ||
| 7978 | out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); | ||
| 7979 | } | ||
| 7980 | |||
| 7981 | -/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7982 | +/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7983 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7984 | |||
| 7985 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c' | ||
| 7986 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 7987 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 7988 | @@ -18,5 +18,5 @@ | ||
| 7989 | out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); | ||
| 7990 | } | ||
| 7991 | |||
| 7992 | -/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 7993 | +/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 7994 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 7995 | |||
| 7996 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c' | ||
| 7997 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 7998 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 7999 | @@ -18,5 +18,5 @@ | ||
| 8000 | out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); | ||
| 8001 | } | ||
| 8002 | |||
| 8003 | -/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8004 | +/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8005 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8006 | |||
| 8007 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c' | ||
| 8008 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 8009 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 8010 | @@ -18,5 +18,5 @@ | ||
| 8011 | out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t); | ||
| 8012 | } | ||
| 8013 | |||
| 8014 | -/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8015 | +/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8016 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8017 | |||
| 8018 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c' | ||
| 8019 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 8020 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 8021 | @@ -18,5 +18,5 @@ | ||
| 8022 | out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t); | ||
| 8023 | } | ||
| 8024 | |||
| 8025 | -/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8026 | +/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8027 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8028 | |||
| 8029 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlals16.c' | ||
| 8030 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlals16.c 2010-07-29 15:38:15 +0000 | ||
| 8031 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlals16.c 2010-08-20 13:27:11 +0000 | ||
| 8032 | @@ -18,5 +18,5 @@ | ||
| 8033 | out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); | ||
| 8034 | } | ||
| 8035 | |||
| 8036 | -/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8037 | +/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8038 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8039 | |||
| 8040 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlals32.c' | ||
| 8041 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlals32.c 2010-07-29 15:38:15 +0000 | ||
| 8042 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlals32.c 2010-08-20 13:27:11 +0000 | ||
| 8043 | @@ -18,5 +18,5 @@ | ||
| 8044 | out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); | ||
| 8045 | } | ||
| 8046 | |||
| 8047 | -/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8048 | +/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8049 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8050 | |||
| 8051 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlals8.c' | ||
| 8052 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlals8.c 2010-07-29 15:38:15 +0000 | ||
| 8053 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlals8.c 2010-08-20 13:27:11 +0000 | ||
| 8054 | @@ -18,5 +18,5 @@ | ||
| 8055 | out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); | ||
| 8056 | } | ||
| 8057 | |||
| 8058 | -/* { dg-final { scan-assembler "vmlal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8059 | +/* { dg-final { scan-assembler "vmlal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8060 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8061 | |||
| 8062 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlalu16.c' | ||
| 8063 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c 2010-07-29 15:38:15 +0000 | ||
| 8064 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c 2010-08-20 13:27:11 +0000 | ||
| 8065 | @@ -18,5 +18,5 @@ | ||
| 8066 | out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); | ||
| 8067 | } | ||
| 8068 | |||
| 8069 | -/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8070 | +/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8071 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8072 | |||
| 8073 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlalu32.c' | ||
| 8074 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c 2010-07-29 15:38:15 +0000 | ||
| 8075 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c 2010-08-20 13:27:11 +0000 | ||
| 8076 | @@ -18,5 +18,5 @@ | ||
| 8077 | out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); | ||
| 8078 | } | ||
| 8079 | |||
| 8080 | -/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8081 | +/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8082 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8083 | |||
| 8084 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlalu8.c' | ||
| 8085 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c 2010-07-29 15:38:15 +0000 | ||
| 8086 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c 2010-08-20 13:27:11 +0000 | ||
| 8087 | @@ -18,5 +18,5 @@ | ||
| 8088 | out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); | ||
| 8089 | } | ||
| 8090 | |||
| 8091 | -/* { dg-final { scan-assembler "vmlal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8092 | +/* { dg-final { scan-assembler "vmlal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8093 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8094 | |||
| 8095 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlas16.c' | ||
| 8096 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlas16.c 2010-07-29 15:38:15 +0000 | ||
| 8097 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlas16.c 2010-08-20 13:27:11 +0000 | ||
| 8098 | @@ -18,5 +18,5 @@ | ||
| 8099 | out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); | ||
| 8100 | } | ||
| 8101 | |||
| 8102 | -/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8103 | +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8104 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8105 | |||
| 8106 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlas32.c' | ||
| 8107 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlas32.c 2010-07-29 15:38:15 +0000 | ||
| 8108 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlas32.c 2010-08-20 13:27:11 +0000 | ||
| 8109 | @@ -18,5 +18,5 @@ | ||
| 8110 | out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); | ||
| 8111 | } | ||
| 8112 | |||
| 8113 | -/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8114 | +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8115 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8116 | |||
| 8117 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlas8.c' | ||
| 8118 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlas8.c 2010-07-29 15:38:15 +0000 | ||
| 8119 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlas8.c 2010-08-20 13:27:11 +0000 | ||
| 8120 | @@ -18,5 +18,5 @@ | ||
| 8121 | out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); | ||
| 8122 | } | ||
| 8123 | |||
| 8124 | -/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8125 | +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8126 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8127 | |||
| 8128 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlau16.c' | ||
| 8129 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlau16.c 2010-07-29 15:38:15 +0000 | ||
| 8130 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlau16.c 2010-08-20 13:27:11 +0000 | ||
| 8131 | @@ -18,5 +18,5 @@ | ||
| 8132 | out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); | ||
| 8133 | } | ||
| 8134 | |||
| 8135 | -/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8136 | +/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8137 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8138 | |||
| 8139 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlau32.c' | ||
| 8140 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlau32.c 2010-07-29 15:38:15 +0000 | ||
| 8141 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlau32.c 2010-08-20 13:27:11 +0000 | ||
| 8142 | @@ -18,5 +18,5 @@ | ||
| 8143 | out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); | ||
| 8144 | } | ||
| 8145 | |||
| 8146 | -/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8147 | +/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8148 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8149 | |||
| 8150 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlau8.c' | ||
| 8151 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlau8.c 2010-07-29 15:38:15 +0000 | ||
| 8152 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlau8.c 2010-08-20 13:27:11 +0000 | ||
| 8153 | @@ -18,5 +18,5 @@ | ||
| 8154 | out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); | ||
| 8155 | } | ||
| 8156 | |||
| 8157 | -/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8158 | +/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8159 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8160 | |||
| 8161 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c' | ||
| 8162 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 8163 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 8164 | @@ -18,5 +18,5 @@ | ||
| 8165 | out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1); | ||
| 8166 | } | ||
| 8167 | |||
| 8168 | -/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8169 | +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8170 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8171 | |||
| 8172 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c' | ||
| 8173 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 8174 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 8175 | @@ -18,5 +18,5 @@ | ||
| 8176 | out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1); | ||
| 8177 | } | ||
| 8178 | |||
| 8179 | -/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8180 | +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8181 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8182 | |||
| 8183 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c' | ||
| 8184 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 8185 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 8186 | @@ -18,5 +18,5 @@ | ||
| 8187 | out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1); | ||
| 8188 | } | ||
| 8189 | |||
| 8190 | -/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8191 | +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8192 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8193 | |||
| 8194 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c' | ||
| 8195 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 8196 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 8197 | @@ -18,5 +18,5 @@ | ||
| 8198 | out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1); | ||
| 8199 | } | ||
| 8200 | |||
| 8201 | -/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8202 | +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8203 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8204 | |||
| 8205 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c' | ||
| 8206 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 8207 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 8208 | @@ -18,5 +18,5 @@ | ||
| 8209 | out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1); | ||
| 8210 | } | ||
| 8211 | |||
| 8212 | -/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8213 | +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8214 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8215 | |||
| 8216 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c' | ||
| 8217 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c 2010-07-29 15:38:15 +0000 | ||
| 8218 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c 2010-08-20 13:27:11 +0000 | ||
| 8219 | @@ -18,5 +18,5 @@ | ||
| 8220 | out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t); | ||
| 8221 | } | ||
| 8222 | |||
| 8223 | -/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8224 | +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8225 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8226 | |||
| 8227 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c' | ||
| 8228 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 8229 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 8230 | @@ -18,5 +18,5 @@ | ||
| 8231 | out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t); | ||
| 8232 | } | ||
| 8233 | |||
| 8234 | -/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8235 | +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8236 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8237 | |||
| 8238 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c' | ||
| 8239 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 8240 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 8241 | @@ -18,5 +18,5 @@ | ||
| 8242 | out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t); | ||
| 8243 | } | ||
| 8244 | |||
| 8245 | -/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8246 | +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8247 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8248 | |||
| 8249 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c' | ||
| 8250 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 8251 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 8252 | @@ -18,5 +18,5 @@ | ||
| 8253 | out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t); | ||
| 8254 | } | ||
| 8255 | |||
| 8256 | -/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8257 | +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8258 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8259 | |||
| 8260 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c' | ||
| 8261 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 8262 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 8263 | @@ -18,5 +18,5 @@ | ||
| 8264 | out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t); | ||
| 8265 | } | ||
| 8266 | |||
| 8267 | -/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8268 | +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8269 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8270 | |||
| 8271 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c' | ||
| 8272 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c 2010-07-29 15:38:15 +0000 | ||
| 8273 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c 2010-08-20 13:27:11 +0000 | ||
| 8274 | @@ -18,5 +18,5 @@ | ||
| 8275 | out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t); | ||
| 8276 | } | ||
| 8277 | |||
| 8278 | -/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8279 | +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8280 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8281 | |||
| 8282 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c' | ||
| 8283 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c 2010-07-29 15:38:15 +0000 | ||
| 8284 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c 2010-08-20 13:27:11 +0000 | ||
| 8285 | @@ -18,5 +18,5 @@ | ||
| 8286 | out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t); | ||
| 8287 | } | ||
| 8288 | |||
| 8289 | -/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8290 | +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8291 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8292 | |||
| 8293 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c' | ||
| 8294 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c 2010-07-29 15:38:15 +0000 | ||
| 8295 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c 2010-08-20 13:27:11 +0000 | ||
| 8296 | @@ -18,5 +18,5 @@ | ||
| 8297 | out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t); | ||
| 8298 | } | ||
| 8299 | |||
| 8300 | -/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8301 | +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8302 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8303 | |||
| 8304 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c' | ||
| 8305 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c 2010-07-29 15:38:15 +0000 | ||
| 8306 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c 2010-08-20 13:27:11 +0000 | ||
| 8307 | @@ -18,5 +18,5 @@ | ||
| 8308 | out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t); | ||
| 8309 | } | ||
| 8310 | |||
| 8311 | -/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8312 | +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8313 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8314 | |||
| 8315 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c' | ||
| 8316 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c 2010-07-29 15:38:15 +0000 | ||
| 8317 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c 2010-08-20 13:27:11 +0000 | ||
| 8318 | @@ -18,5 +18,5 @@ | ||
| 8319 | out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t); | ||
| 8320 | } | ||
| 8321 | |||
| 8322 | -/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8323 | +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8324 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8325 | |||
| 8326 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c' | ||
| 8327 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c 2010-07-29 15:38:15 +0000 | ||
| 8328 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c 2010-08-20 13:27:11 +0000 | ||
| 8329 | @@ -18,5 +18,5 @@ | ||
| 8330 | out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t); | ||
| 8331 | } | ||
| 8332 | |||
| 8333 | -/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8334 | +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8335 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8336 | |||
| 8337 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c' | ||
| 8338 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c 2010-07-29 15:38:15 +0000 | ||
| 8339 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c 2010-08-20 13:27:11 +0000 | ||
| 8340 | @@ -18,5 +18,5 @@ | ||
| 8341 | out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t); | ||
| 8342 | } | ||
| 8343 | |||
| 8344 | -/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8345 | +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8346 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8347 | |||
| 8348 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c' | ||
| 8349 | --- old/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 8350 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 8351 | @@ -18,5 +18,5 @@ | ||
| 8352 | out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1); | ||
| 8353 | } | ||
| 8354 | |||
| 8355 | -/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8356 | +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8357 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8358 | |||
| 8359 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c' | ||
| 8360 | --- old/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 8361 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 8362 | @@ -18,5 +18,5 @@ | ||
| 8363 | out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); | ||
| 8364 | } | ||
| 8365 | |||
| 8366 | -/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8367 | +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8368 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8369 | |||
| 8370 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c' | ||
| 8371 | --- old/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 8372 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 8373 | @@ -18,5 +18,5 @@ | ||
| 8374 | out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); | ||
| 8375 | } | ||
| 8376 | |||
| 8377 | -/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8378 | +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8379 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8380 | |||
| 8381 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c' | ||
| 8382 | --- old/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 8383 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 8384 | @@ -18,5 +18,5 @@ | ||
| 8385 | out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); | ||
| 8386 | } | ||
| 8387 | |||
| 8388 | -/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8389 | +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8390 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8391 | |||
| 8392 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c' | ||
| 8393 | --- old/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 8394 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 8395 | @@ -18,5 +18,5 @@ | ||
| 8396 | out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); | ||
| 8397 | } | ||
| 8398 | |||
| 8399 | -/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8400 | +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8401 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8402 | |||
| 8403 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c' | ||
| 8404 | --- old/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c 2010-07-29 15:38:15 +0000 | ||
| 8405 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c 2010-08-20 13:27:11 +0000 | ||
| 8406 | @@ -18,5 +18,5 @@ | ||
| 8407 | out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t); | ||
| 8408 | } | ||
| 8409 | |||
| 8410 | -/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8411 | +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8412 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8413 | |||
| 8414 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c' | ||
| 8415 | --- old/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 8416 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 8417 | @@ -18,5 +18,5 @@ | ||
| 8418 | out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t); | ||
| 8419 | } | ||
| 8420 | |||
| 8421 | -/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8422 | +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8423 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8424 | |||
| 8425 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c' | ||
| 8426 | --- old/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 8427 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 8428 | @@ -18,5 +18,5 @@ | ||
| 8429 | out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t); | ||
| 8430 | } | ||
| 8431 | |||
| 8432 | -/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8433 | +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8434 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8435 | |||
| 8436 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c' | ||
| 8437 | --- old/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 8438 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 8439 | @@ -18,5 +18,5 @@ | ||
| 8440 | out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t); | ||
| 8441 | } | ||
| 8442 | |||
| 8443 | -/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8444 | +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8445 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8446 | |||
| 8447 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c' | ||
| 8448 | --- old/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 8449 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 8450 | @@ -18,5 +18,5 @@ | ||
| 8451 | out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t); | ||
| 8452 | } | ||
| 8453 | |||
| 8454 | -/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8455 | +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8456 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8457 | |||
| 8458 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsf32.c' | ||
| 8459 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c 2010-07-29 15:38:15 +0000 | ||
| 8460 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c 2010-08-20 13:27:11 +0000 | ||
| 8461 | @@ -18,5 +18,5 @@ | ||
| 8462 | out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t); | ||
| 8463 | } | ||
| 8464 | |||
| 8465 | -/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8466 | +/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8467 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8468 | |||
| 8469 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c' | ||
| 8470 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 8471 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 8472 | @@ -18,5 +18,5 @@ | ||
| 8473 | out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); | ||
| 8474 | } | ||
| 8475 | |||
| 8476 | -/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8477 | +/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8478 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8479 | |||
| 8480 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c' | ||
| 8481 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 8482 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 8483 | @@ -18,5 +18,5 @@ | ||
| 8484 | out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); | ||
| 8485 | } | ||
| 8486 | |||
| 8487 | -/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8488 | +/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8489 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8490 | |||
| 8491 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c' | ||
| 8492 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 8493 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 8494 | @@ -18,5 +18,5 @@ | ||
| 8495 | out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1); | ||
| 8496 | } | ||
| 8497 | |||
| 8498 | -/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8499 | +/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8500 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8501 | |||
| 8502 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c' | ||
| 8503 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 8504 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 8505 | @@ -18,5 +18,5 @@ | ||
| 8506 | out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1); | ||
| 8507 | } | ||
| 8508 | |||
| 8509 | -/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8510 | +/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8511 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8512 | |||
| 8513 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c' | ||
| 8514 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 8515 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 8516 | @@ -18,5 +18,5 @@ | ||
| 8517 | out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); | ||
| 8518 | } | ||
| 8519 | |||
| 8520 | -/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8521 | +/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8522 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8523 | |||
| 8524 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c' | ||
| 8525 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 8526 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 8527 | @@ -18,5 +18,5 @@ | ||
| 8528 | out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); | ||
| 8529 | } | ||
| 8530 | |||
| 8531 | -/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8532 | +/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8533 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8534 | |||
| 8535 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c' | ||
| 8536 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 8537 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 8538 | @@ -18,5 +18,5 @@ | ||
| 8539 | out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t); | ||
| 8540 | } | ||
| 8541 | |||
| 8542 | -/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8543 | +/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8544 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8545 | |||
| 8546 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c' | ||
| 8547 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 8548 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 8549 | @@ -18,5 +18,5 @@ | ||
| 8550 | out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t); | ||
| 8551 | } | ||
| 8552 | |||
| 8553 | -/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8554 | +/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8555 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8556 | |||
| 8557 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsls16.c' | ||
| 8558 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c 2010-07-29 15:38:15 +0000 | ||
| 8559 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c 2010-08-20 13:27:11 +0000 | ||
| 8560 | @@ -18,5 +18,5 @@ | ||
| 8561 | out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); | ||
| 8562 | } | ||
| 8563 | |||
| 8564 | -/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8565 | +/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8566 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8567 | |||
| 8568 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsls32.c' | ||
| 8569 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c 2010-07-29 15:38:15 +0000 | ||
| 8570 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c 2010-08-20 13:27:11 +0000 | ||
| 8571 | @@ -18,5 +18,5 @@ | ||
| 8572 | out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); | ||
| 8573 | } | ||
| 8574 | |||
| 8575 | -/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8576 | +/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8577 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8578 | |||
| 8579 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsls8.c' | ||
| 8580 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c 2010-07-29 15:38:15 +0000 | ||
| 8581 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c 2010-08-20 13:27:11 +0000 | ||
| 8582 | @@ -18,5 +18,5 @@ | ||
| 8583 | out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t); | ||
| 8584 | } | ||
| 8585 | |||
| 8586 | -/* { dg-final { scan-assembler "vmlsl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8587 | +/* { dg-final { scan-assembler "vmlsl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8588 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8589 | |||
| 8590 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlslu16.c' | ||
| 8591 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c 2010-07-29 15:38:15 +0000 | ||
| 8592 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c 2010-08-20 13:27:11 +0000 | ||
| 8593 | @@ -18,5 +18,5 @@ | ||
| 8594 | out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t); | ||
| 8595 | } | ||
| 8596 | |||
| 8597 | -/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8598 | +/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8599 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8600 | |||
| 8601 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlslu32.c' | ||
| 8602 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c 2010-07-29 15:38:15 +0000 | ||
| 8603 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c 2010-08-20 13:27:11 +0000 | ||
| 8604 | @@ -18,5 +18,5 @@ | ||
| 8605 | out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t); | ||
| 8606 | } | ||
| 8607 | |||
| 8608 | -/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8609 | +/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8610 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8611 | |||
| 8612 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlslu8.c' | ||
| 8613 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c 2010-07-29 15:38:15 +0000 | ||
| 8614 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c 2010-08-20 13:27:11 +0000 | ||
| 8615 | @@ -18,5 +18,5 @@ | ||
| 8616 | out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t); | ||
| 8617 | } | ||
| 8618 | |||
| 8619 | -/* { dg-final { scan-assembler "vmlsl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8620 | +/* { dg-final { scan-assembler "vmlsl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8621 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8622 | |||
| 8623 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlss16.c' | ||
| 8624 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlss16.c 2010-07-29 15:38:15 +0000 | ||
| 8625 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlss16.c 2010-08-20 13:27:11 +0000 | ||
| 8626 | @@ -18,5 +18,5 @@ | ||
| 8627 | out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t); | ||
| 8628 | } | ||
| 8629 | |||
| 8630 | -/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8631 | +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8632 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8633 | |||
| 8634 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlss32.c' | ||
| 8635 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlss32.c 2010-07-29 15:38:15 +0000 | ||
| 8636 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlss32.c 2010-08-20 13:27:11 +0000 | ||
| 8637 | @@ -18,5 +18,5 @@ | ||
| 8638 | out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t); | ||
| 8639 | } | ||
| 8640 | |||
| 8641 | -/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8642 | +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8643 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8644 | |||
| 8645 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlss8.c' | ||
| 8646 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlss8.c 2010-07-29 15:38:15 +0000 | ||
| 8647 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlss8.c 2010-08-20 13:27:11 +0000 | ||
| 8648 | @@ -18,5 +18,5 @@ | ||
| 8649 | out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); | ||
| 8650 | } | ||
| 8651 | |||
| 8652 | -/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8653 | +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8654 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8655 | |||
| 8656 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsu16.c' | ||
| 8657 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c 2010-07-29 15:38:15 +0000 | ||
| 8658 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c 2010-08-20 13:27:11 +0000 | ||
| 8659 | @@ -18,5 +18,5 @@ | ||
| 8660 | out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t); | ||
| 8661 | } | ||
| 8662 | |||
| 8663 | -/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8664 | +/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8665 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8666 | |||
| 8667 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsu32.c' | ||
| 8668 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c 2010-07-29 15:38:15 +0000 | ||
| 8669 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c 2010-08-20 13:27:11 +0000 | ||
| 8670 | @@ -18,5 +18,5 @@ | ||
| 8671 | out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t); | ||
| 8672 | } | ||
| 8673 | |||
| 8674 | -/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8675 | +/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8676 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8677 | |||
| 8678 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmlsu8.c' | ||
| 8679 | --- old/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c 2010-07-29 15:38:15 +0000 | ||
| 8680 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c 2010-08-20 13:27:11 +0000 | ||
| 8681 | @@ -18,5 +18,5 @@ | ||
| 8682 | out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); | ||
| 8683 | } | ||
| 8684 | |||
| 8685 | -/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8686 | +/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8687 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8688 | |||
| 8689 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c' | ||
| 8690 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c 2010-07-29 15:38:15 +0000 | ||
| 8691 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c 2010-08-20 13:27:11 +0000 | ||
| 8692 | @@ -16,5 +16,5 @@ | ||
| 8693 | out_float32x4_t = vmovq_n_f32 (arg0_float32_t); | ||
| 8694 | } | ||
| 8695 | |||
| 8696 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8697 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8698 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8699 | |||
| 8700 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c' | ||
| 8701 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c 2010-07-29 15:38:15 +0000 | ||
| 8702 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c 2010-08-20 13:27:11 +0000 | ||
| 8703 | @@ -16,5 +16,5 @@ | ||
| 8704 | out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t); | ||
| 8705 | } | ||
| 8706 | |||
| 8707 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8708 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8709 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8710 | |||
| 8711 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c' | ||
| 8712 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c 2010-07-29 15:38:15 +0000 | ||
| 8713 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c 2010-08-20 13:27:11 +0000 | ||
| 8714 | @@ -16,5 +16,5 @@ | ||
| 8715 | out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t); | ||
| 8716 | } | ||
| 8717 | |||
| 8718 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8719 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8720 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8721 | |||
| 8722 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c' | ||
| 8723 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 8724 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 8725 | @@ -16,5 +16,5 @@ | ||
| 8726 | out_int16x8_t = vmovq_n_s16 (arg0_int16_t); | ||
| 8727 | } | ||
| 8728 | |||
| 8729 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8730 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8731 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8732 | |||
| 8733 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c' | ||
| 8734 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 8735 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 8736 | @@ -16,5 +16,5 @@ | ||
| 8737 | out_int32x4_t = vmovq_n_s32 (arg0_int32_t); | ||
| 8738 | } | ||
| 8739 | |||
| 8740 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8741 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8742 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8743 | |||
| 8744 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c' | ||
| 8745 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 8746 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 8747 | @@ -16,5 +16,5 @@ | ||
| 8748 | out_int8x16_t = vmovq_n_s8 (arg0_int8_t); | ||
| 8749 | } | ||
| 8750 | |||
| 8751 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8752 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8753 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8754 | |||
| 8755 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c' | ||
| 8756 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 8757 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 8758 | @@ -16,5 +16,5 @@ | ||
| 8759 | out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t); | ||
| 8760 | } | ||
| 8761 | |||
| 8762 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8763 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8764 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8765 | |||
| 8766 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c' | ||
| 8767 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 8768 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 8769 | @@ -16,5 +16,5 @@ | ||
| 8770 | out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t); | ||
| 8771 | } | ||
| 8772 | |||
| 8773 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8774 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8775 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8776 | |||
| 8777 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c' | ||
| 8778 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 8779 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 8780 | @@ -16,5 +16,5 @@ | ||
| 8781 | out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t); | ||
| 8782 | } | ||
| 8783 | |||
| 8784 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8785 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8786 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8787 | |||
| 8788 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c' | ||
| 8789 | --- old/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c 2010-07-29 15:38:15 +0000 | ||
| 8790 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c 2010-08-20 13:27:11 +0000 | ||
| 8791 | @@ -16,5 +16,5 @@ | ||
| 8792 | out_float32x2_t = vmov_n_f32 (arg0_float32_t); | ||
| 8793 | } | ||
| 8794 | |||
| 8795 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8796 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8797 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8798 | |||
| 8799 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_np16.c' | ||
| 8800 | --- old/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c 2010-07-29 15:38:15 +0000 | ||
| 8801 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c 2010-08-20 13:27:11 +0000 | ||
| 8802 | @@ -16,5 +16,5 @@ | ||
| 8803 | out_poly16x4_t = vmov_n_p16 (arg0_poly16_t); | ||
| 8804 | } | ||
| 8805 | |||
| 8806 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8807 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8808 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8809 | |||
| 8810 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_np8.c' | ||
| 8811 | --- old/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c 2010-07-29 15:38:15 +0000 | ||
| 8812 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c 2010-08-20 13:27:11 +0000 | ||
| 8813 | @@ -16,5 +16,5 @@ | ||
| 8814 | out_poly8x8_t = vmov_n_p8 (arg0_poly8_t); | ||
| 8815 | } | ||
| 8816 | |||
| 8817 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8818 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8819 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8820 | |||
| 8821 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c' | ||
| 8822 | --- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 8823 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 8824 | @@ -16,5 +16,5 @@ | ||
| 8825 | out_int16x4_t = vmov_n_s16 (arg0_int16_t); | ||
| 8826 | } | ||
| 8827 | |||
| 8828 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8829 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8830 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8831 | |||
| 8832 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c' | ||
| 8833 | --- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 8834 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 8835 | @@ -16,5 +16,5 @@ | ||
| 8836 | out_int32x2_t = vmov_n_s32 (arg0_int32_t); | ||
| 8837 | } | ||
| 8838 | |||
| 8839 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8840 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8841 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8842 | |||
| 8843 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c' | ||
| 8844 | --- old/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 8845 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 8846 | @@ -16,5 +16,5 @@ | ||
| 8847 | out_int8x8_t = vmov_n_s8 (arg0_int8_t); | ||
| 8848 | } | ||
| 8849 | |||
| 8850 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8851 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8852 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8853 | |||
| 8854 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c' | ||
| 8855 | --- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 8856 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 8857 | @@ -16,5 +16,5 @@ | ||
| 8858 | out_uint16x4_t = vmov_n_u16 (arg0_uint16_t); | ||
| 8859 | } | ||
| 8860 | |||
| 8861 | -/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8862 | +/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8863 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8864 | |||
| 8865 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c' | ||
| 8866 | --- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 8867 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 8868 | @@ -16,5 +16,5 @@ | ||
| 8869 | out_uint32x2_t = vmov_n_u32 (arg0_uint32_t); | ||
| 8870 | } | ||
| 8871 | |||
| 8872 | -/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8873 | +/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8874 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8875 | |||
| 8876 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c' | ||
| 8877 | --- old/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 8878 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 8879 | @@ -16,5 +16,5 @@ | ||
| 8880 | out_uint8x8_t = vmov_n_u8 (arg0_uint8_t); | ||
| 8881 | } | ||
| 8882 | |||
| 8883 | -/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8884 | +/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8885 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8886 | |||
| 8887 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovls16.c' | ||
| 8888 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovls16.c 2010-07-29 15:38:15 +0000 | ||
| 8889 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovls16.c 2010-08-20 13:27:11 +0000 | ||
| 8890 | @@ -16,5 +16,5 @@ | ||
| 8891 | out_int32x4_t = vmovl_s16 (arg0_int16x4_t); | ||
| 8892 | } | ||
| 8893 | |||
| 8894 | -/* { dg-final { scan-assembler "vmovl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8895 | +/* { dg-final { scan-assembler "vmovl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8896 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8897 | |||
| 8898 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovls32.c' | ||
| 8899 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovls32.c 2010-07-29 15:38:15 +0000 | ||
| 8900 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovls32.c 2010-08-20 13:27:11 +0000 | ||
| 8901 | @@ -16,5 +16,5 @@ | ||
| 8902 | out_int64x2_t = vmovl_s32 (arg0_int32x2_t); | ||
| 8903 | } | ||
| 8904 | |||
| 8905 | -/* { dg-final { scan-assembler "vmovl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8906 | +/* { dg-final { scan-assembler "vmovl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8907 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8908 | |||
| 8909 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovls8.c' | ||
| 8910 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovls8.c 2010-07-29 15:38:15 +0000 | ||
| 8911 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovls8.c 2010-08-20 13:27:11 +0000 | ||
| 8912 | @@ -16,5 +16,5 @@ | ||
| 8913 | out_int16x8_t = vmovl_s8 (arg0_int8x8_t); | ||
| 8914 | } | ||
| 8915 | |||
| 8916 | -/* { dg-final { scan-assembler "vmovl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8917 | +/* { dg-final { scan-assembler "vmovl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8918 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8919 | |||
| 8920 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovlu16.c' | ||
| 8921 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c 2010-07-29 15:38:15 +0000 | ||
| 8922 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c 2010-08-20 13:27:11 +0000 | ||
| 8923 | @@ -16,5 +16,5 @@ | ||
| 8924 | out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t); | ||
| 8925 | } | ||
| 8926 | |||
| 8927 | -/* { dg-final { scan-assembler "vmovl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8928 | +/* { dg-final { scan-assembler "vmovl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8929 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8930 | |||
| 8931 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovlu32.c' | ||
| 8932 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c 2010-07-29 15:38:15 +0000 | ||
| 8933 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c 2010-08-20 13:27:11 +0000 | ||
| 8934 | @@ -16,5 +16,5 @@ | ||
| 8935 | out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t); | ||
| 8936 | } | ||
| 8937 | |||
| 8938 | -/* { dg-final { scan-assembler "vmovl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8939 | +/* { dg-final { scan-assembler "vmovl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8940 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8941 | |||
| 8942 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovlu8.c' | ||
| 8943 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c 2010-07-29 15:38:15 +0000 | ||
| 8944 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c 2010-08-20 13:27:11 +0000 | ||
| 8945 | @@ -16,5 +16,5 @@ | ||
| 8946 | out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t); | ||
| 8947 | } | ||
| 8948 | |||
| 8949 | -/* { dg-final { scan-assembler "vmovl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8950 | +/* { dg-final { scan-assembler "vmovl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8951 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8952 | |||
| 8953 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovns16.c' | ||
| 8954 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovns16.c 2010-07-29 15:38:15 +0000 | ||
| 8955 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovns16.c 2010-08-20 13:27:11 +0000 | ||
| 8956 | @@ -16,5 +16,5 @@ | ||
| 8957 | out_int8x8_t = vmovn_s16 (arg0_int16x8_t); | ||
| 8958 | } | ||
| 8959 | |||
| 8960 | -/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8961 | +/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8962 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8963 | |||
| 8964 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovns32.c' | ||
| 8965 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovns32.c 2010-07-29 15:38:15 +0000 | ||
| 8966 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovns32.c 2010-08-20 13:27:11 +0000 | ||
| 8967 | @@ -16,5 +16,5 @@ | ||
| 8968 | out_int16x4_t = vmovn_s32 (arg0_int32x4_t); | ||
| 8969 | } | ||
| 8970 | |||
| 8971 | -/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8972 | +/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8973 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8974 | |||
| 8975 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovns64.c' | ||
| 8976 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovns64.c 2010-07-29 15:38:15 +0000 | ||
| 8977 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovns64.c 2010-08-20 13:27:11 +0000 | ||
| 8978 | @@ -16,5 +16,5 @@ | ||
| 8979 | out_int32x2_t = vmovn_s64 (arg0_int64x2_t); | ||
| 8980 | } | ||
| 8981 | |||
| 8982 | -/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8983 | +/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8984 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8985 | |||
| 8986 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovnu16.c' | ||
| 8987 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c 2010-07-29 15:38:15 +0000 | ||
| 8988 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c 2010-08-20 13:27:11 +0000 | ||
| 8989 | @@ -16,5 +16,5 @@ | ||
| 8990 | out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t); | ||
| 8991 | } | ||
| 8992 | |||
| 8993 | -/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 8994 | +/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 8995 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 8996 | |||
| 8997 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovnu32.c' | ||
| 8998 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c 2010-07-29 15:38:15 +0000 | ||
| 8999 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c 2010-08-20 13:27:11 +0000 | ||
| 9000 | @@ -16,5 +16,5 @@ | ||
| 9001 | out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t); | ||
| 9002 | } | ||
| 9003 | |||
| 9004 | -/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9005 | +/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9006 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9007 | |||
| 9008 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmovnu64.c' | ||
| 9009 | --- old/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c 2010-07-29 15:38:15 +0000 | ||
| 9010 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c 2010-08-20 13:27:11 +0000 | ||
| 9011 | @@ -16,5 +16,5 @@ | ||
| 9012 | out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t); | ||
| 9013 | } | ||
| 9014 | |||
| 9015 | -/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9016 | +/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9017 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9018 | |||
| 9019 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c' | ||
| 9020 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 9021 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 9022 | @@ -17,5 +17,5 @@ | ||
| 9023 | out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1); | ||
| 9024 | } | ||
| 9025 | |||
| 9026 | -/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9027 | +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9028 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9029 | |||
| 9030 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c' | ||
| 9031 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 9032 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 9033 | @@ -17,5 +17,5 @@ | ||
| 9034 | out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); | ||
| 9035 | } | ||
| 9036 | |||
| 9037 | -/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9038 | +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9039 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9040 | |||
| 9041 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c' | ||
| 9042 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 9043 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 9044 | @@ -17,5 +17,5 @@ | ||
| 9045 | out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); | ||
| 9046 | } | ||
| 9047 | |||
| 9048 | -/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9049 | +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9050 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9051 | |||
| 9052 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c' | ||
| 9053 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 9054 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 9055 | @@ -17,5 +17,5 @@ | ||
| 9056 | out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1); | ||
| 9057 | } | ||
| 9058 | |||
| 9059 | -/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9060 | +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9061 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9062 | |||
| 9063 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c' | ||
| 9064 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 9065 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 9066 | @@ -17,5 +17,5 @@ | ||
| 9067 | out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1); | ||
| 9068 | } | ||
| 9069 | |||
| 9070 | -/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9071 | +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9072 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9073 | |||
| 9074 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c' | ||
| 9075 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c 2010-07-29 15:38:15 +0000 | ||
| 9076 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c 2010-08-20 13:27:11 +0000 | ||
| 9077 | @@ -17,5 +17,5 @@ | ||
| 9078 | out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t); | ||
| 9079 | } | ||
| 9080 | |||
| 9081 | -/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9082 | +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9083 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9084 | |||
| 9085 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c' | ||
| 9086 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 9087 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 9088 | @@ -17,5 +17,5 @@ | ||
| 9089 | out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t); | ||
| 9090 | } | ||
| 9091 | |||
| 9092 | -/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9093 | +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9094 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9095 | |||
| 9096 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c' | ||
| 9097 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 9098 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 9099 | @@ -17,5 +17,5 @@ | ||
| 9100 | out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t); | ||
| 9101 | } | ||
| 9102 | |||
| 9103 | -/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9104 | +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9105 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9106 | |||
| 9107 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c' | ||
| 9108 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 9109 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 9110 | @@ -17,5 +17,5 @@ | ||
| 9111 | out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t); | ||
| 9112 | } | ||
| 9113 | |||
| 9114 | -/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9115 | +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9116 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9117 | |||
| 9118 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c' | ||
| 9119 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 9120 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 9121 | @@ -17,5 +17,5 @@ | ||
| 9122 | out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t); | ||
| 9123 | } | ||
| 9124 | |||
| 9125 | -/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9126 | +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9127 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9128 | |||
| 9129 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQf32.c' | ||
| 9130 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c 2010-07-29 15:38:15 +0000 | ||
| 9131 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c 2010-08-20 13:27:11 +0000 | ||
| 9132 | @@ -17,5 +17,5 @@ | ||
| 9133 | out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 9134 | } | ||
| 9135 | |||
| 9136 | -/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9137 | +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9138 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9139 | |||
| 9140 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQp8.c' | ||
| 9141 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c 2010-07-29 15:38:15 +0000 | ||
| 9142 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c 2010-08-20 13:27:11 +0000 | ||
| 9143 | @@ -17,5 +17,5 @@ | ||
| 9144 | out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); | ||
| 9145 | } | ||
| 9146 | |||
| 9147 | -/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9148 | +/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9149 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9150 | |||
| 9151 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQs16.c' | ||
| 9152 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c 2010-07-29 15:38:15 +0000 | ||
| 9153 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c 2010-08-20 13:27:11 +0000 | ||
| 9154 | @@ -17,5 +17,5 @@ | ||
| 9155 | out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 9156 | } | ||
| 9157 | |||
| 9158 | -/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9159 | +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9160 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9161 | |||
| 9162 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQs32.c' | ||
| 9163 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c 2010-07-29 15:38:15 +0000 | ||
| 9164 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c 2010-08-20 13:27:11 +0000 | ||
| 9165 | @@ -17,5 +17,5 @@ | ||
| 9166 | out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 9167 | } | ||
| 9168 | |||
| 9169 | -/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9170 | +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9171 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9172 | |||
| 9173 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQs8.c' | ||
| 9174 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c 2010-07-29 15:38:15 +0000 | ||
| 9175 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c 2010-08-20 13:27:11 +0000 | ||
| 9176 | @@ -17,5 +17,5 @@ | ||
| 9177 | out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 9178 | } | ||
| 9179 | |||
| 9180 | -/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9181 | +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9182 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9183 | |||
| 9184 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQu16.c' | ||
| 9185 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c 2010-07-29 15:38:15 +0000 | ||
| 9186 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c 2010-08-20 13:27:11 +0000 | ||
| 9187 | @@ -17,5 +17,5 @@ | ||
| 9188 | out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 9189 | } | ||
| 9190 | |||
| 9191 | -/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9192 | +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9193 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9194 | |||
| 9195 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQu32.c' | ||
| 9196 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c 2010-07-29 15:38:15 +0000 | ||
| 9197 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c 2010-08-20 13:27:11 +0000 | ||
| 9198 | @@ -17,5 +17,5 @@ | ||
| 9199 | out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 9200 | } | ||
| 9201 | |||
| 9202 | -/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9203 | +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9204 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9205 | |||
| 9206 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulQu8.c' | ||
| 9207 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c 2010-07-29 15:38:15 +0000 | ||
| 9208 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c 2010-08-20 13:27:11 +0000 | ||
| 9209 | @@ -17,5 +17,5 @@ | ||
| 9210 | out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 9211 | } | ||
| 9212 | |||
| 9213 | -/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9214 | +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9215 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9216 | |||
| 9217 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c' | ||
| 9218 | --- old/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 9219 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 9220 | @@ -17,5 +17,5 @@ | ||
| 9221 | out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1); | ||
| 9222 | } | ||
| 9223 | |||
| 9224 | -/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9225 | +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9226 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9227 | |||
| 9228 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c' | ||
| 9229 | --- old/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 9230 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 9231 | @@ -17,5 +17,5 @@ | ||
| 9232 | out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); | ||
| 9233 | } | ||
| 9234 | |||
| 9235 | -/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9236 | +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9237 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9238 | |||
| 9239 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c' | ||
| 9240 | --- old/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 9241 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 9242 | @@ -17,5 +17,5 @@ | ||
| 9243 | out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); | ||
| 9244 | } | ||
| 9245 | |||
| 9246 | -/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9247 | +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9248 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9249 | |||
| 9250 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c' | ||
| 9251 | --- old/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 9252 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 9253 | @@ -17,5 +17,5 @@ | ||
| 9254 | out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); | ||
| 9255 | } | ||
| 9256 | |||
| 9257 | -/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9258 | +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9259 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9260 | |||
| 9261 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c' | ||
| 9262 | --- old/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 9263 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 9264 | @@ -17,5 +17,5 @@ | ||
| 9265 | out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); | ||
| 9266 | } | ||
| 9267 | |||
| 9268 | -/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9269 | +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9270 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9271 | |||
| 9272 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c' | ||
| 9273 | --- old/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c 2010-07-29 15:38:15 +0000 | ||
| 9274 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c 2010-08-20 13:27:11 +0000 | ||
| 9275 | @@ -17,5 +17,5 @@ | ||
| 9276 | out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t); | ||
| 9277 | } | ||
| 9278 | |||
| 9279 | -/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9280 | +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9281 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9282 | |||
| 9283 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c' | ||
| 9284 | --- old/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 9285 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 9286 | @@ -17,5 +17,5 @@ | ||
| 9287 | out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t); | ||
| 9288 | } | ||
| 9289 | |||
| 9290 | -/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9291 | +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9292 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9293 | |||
| 9294 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c' | ||
| 9295 | --- old/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 9296 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 9297 | @@ -17,5 +17,5 @@ | ||
| 9298 | out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t); | ||
| 9299 | } | ||
| 9300 | |||
| 9301 | -/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9302 | +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9303 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9304 | |||
| 9305 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c' | ||
| 9306 | --- old/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 9307 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 9308 | @@ -17,5 +17,5 @@ | ||
| 9309 | out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t); | ||
| 9310 | } | ||
| 9311 | |||
| 9312 | -/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9313 | +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9314 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9315 | |||
| 9316 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c' | ||
| 9317 | --- old/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 9318 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 9319 | @@ -17,5 +17,5 @@ | ||
| 9320 | out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t); | ||
| 9321 | } | ||
| 9322 | |||
| 9323 | -/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9324 | +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9325 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9326 | |||
| 9327 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulf32.c' | ||
| 9328 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulf32.c 2010-07-29 15:38:15 +0000 | ||
| 9329 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulf32.c 2010-08-20 13:27:11 +0000 | ||
| 9330 | @@ -17,5 +17,5 @@ | ||
| 9331 | out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 9332 | } | ||
| 9333 | |||
| 9334 | -/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9335 | +/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9336 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9337 | |||
| 9338 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c' | ||
| 9339 | --- old/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 9340 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 9341 | @@ -17,5 +17,5 @@ | ||
| 9342 | out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); | ||
| 9343 | } | ||
| 9344 | |||
| 9345 | -/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9346 | +/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9347 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9348 | |||
| 9349 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c' | ||
| 9350 | --- old/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 9351 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 9352 | @@ -17,5 +17,5 @@ | ||
| 9353 | out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); | ||
| 9354 | } | ||
| 9355 | |||
| 9356 | -/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9357 | +/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9358 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9359 | |||
| 9360 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c' | ||
| 9361 | --- old/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 9362 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 9363 | @@ -17,5 +17,5 @@ | ||
| 9364 | out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); | ||
| 9365 | } | ||
| 9366 | |||
| 9367 | -/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9368 | +/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9369 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9370 | |||
| 9371 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c' | ||
| 9372 | --- old/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 9373 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 9374 | @@ -17,5 +17,5 @@ | ||
| 9375 | out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); | ||
| 9376 | } | ||
| 9377 | |||
| 9378 | -/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9379 | +/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9380 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9381 | |||
| 9382 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c' | ||
| 9383 | --- old/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 9384 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 9385 | @@ -17,5 +17,5 @@ | ||
| 9386 | out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t); | ||
| 9387 | } | ||
| 9388 | |||
| 9389 | -/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9390 | +/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9391 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9392 | |||
| 9393 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c' | ||
| 9394 | --- old/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 9395 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 9396 | @@ -17,5 +17,5 @@ | ||
| 9397 | out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t); | ||
| 9398 | } | ||
| 9399 | |||
| 9400 | -/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9401 | +/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9402 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9403 | |||
| 9404 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c' | ||
| 9405 | --- old/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 9406 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 9407 | @@ -17,5 +17,5 @@ | ||
| 9408 | out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t); | ||
| 9409 | } | ||
| 9410 | |||
| 9411 | -/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9412 | +/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9413 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9414 | |||
| 9415 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c' | ||
| 9416 | --- old/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 9417 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 9418 | @@ -17,5 +17,5 @@ | ||
| 9419 | out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t); | ||
| 9420 | } | ||
| 9421 | |||
| 9422 | -/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9423 | +/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9424 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9425 | |||
| 9426 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmullp8.c' | ||
| 9427 | --- old/gcc/testsuite/gcc.target/arm/neon/vmullp8.c 2010-07-29 15:38:15 +0000 | ||
| 9428 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmullp8.c 2010-08-20 13:27:11 +0000 | ||
| 9429 | @@ -17,5 +17,5 @@ | ||
| 9430 | out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t); | ||
| 9431 | } | ||
| 9432 | |||
| 9433 | -/* { dg-final { scan-assembler "vmull\.p8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9434 | +/* { dg-final { scan-assembler "vmull\.p8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9435 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9436 | |||
| 9437 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulls16.c' | ||
| 9438 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulls16.c 2010-07-29 15:38:15 +0000 | ||
| 9439 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulls16.c 2010-08-20 13:27:11 +0000 | ||
| 9440 | @@ -17,5 +17,5 @@ | ||
| 9441 | out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 9442 | } | ||
| 9443 | |||
| 9444 | -/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9445 | +/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9446 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9447 | |||
| 9448 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulls32.c' | ||
| 9449 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulls32.c 2010-07-29 15:38:15 +0000 | ||
| 9450 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulls32.c 2010-08-20 13:27:11 +0000 | ||
| 9451 | @@ -17,5 +17,5 @@ | ||
| 9452 | out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 9453 | } | ||
| 9454 | |||
| 9455 | -/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9456 | +/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9457 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9458 | |||
| 9459 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulls8.c' | ||
| 9460 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulls8.c 2010-07-29 15:38:15 +0000 | ||
| 9461 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulls8.c 2010-08-20 13:27:11 +0000 | ||
| 9462 | @@ -17,5 +17,5 @@ | ||
| 9463 | out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 9464 | } | ||
| 9465 | |||
| 9466 | -/* { dg-final { scan-assembler "vmull\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9467 | +/* { dg-final { scan-assembler "vmull\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9468 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9469 | |||
| 9470 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmullu16.c' | ||
| 9471 | --- old/gcc/testsuite/gcc.target/arm/neon/vmullu16.c 2010-07-29 15:38:15 +0000 | ||
| 9472 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmullu16.c 2010-08-20 13:27:11 +0000 | ||
| 9473 | @@ -17,5 +17,5 @@ | ||
| 9474 | out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 9475 | } | ||
| 9476 | |||
| 9477 | -/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9478 | +/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9479 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9480 | |||
| 9481 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmullu32.c' | ||
| 9482 | --- old/gcc/testsuite/gcc.target/arm/neon/vmullu32.c 2010-07-29 15:38:15 +0000 | ||
| 9483 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmullu32.c 2010-08-20 13:27:11 +0000 | ||
| 9484 | @@ -17,5 +17,5 @@ | ||
| 9485 | out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 9486 | } | ||
| 9487 | |||
| 9488 | -/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9489 | +/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9490 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9491 | |||
| 9492 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmullu8.c' | ||
| 9493 | --- old/gcc/testsuite/gcc.target/arm/neon/vmullu8.c 2010-07-29 15:38:15 +0000 | ||
| 9494 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmullu8.c 2010-08-20 13:27:11 +0000 | ||
| 9495 | @@ -17,5 +17,5 @@ | ||
| 9496 | out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 9497 | } | ||
| 9498 | |||
| 9499 | -/* { dg-final { scan-assembler "vmull\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9500 | +/* { dg-final { scan-assembler "vmull\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9501 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9502 | |||
| 9503 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulp8.c' | ||
| 9504 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulp8.c 2010-07-29 15:38:15 +0000 | ||
| 9505 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulp8.c 2010-08-20 13:27:11 +0000 | ||
| 9506 | @@ -17,5 +17,5 @@ | ||
| 9507 | out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t); | ||
| 9508 | } | ||
| 9509 | |||
| 9510 | -/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9511 | +/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9512 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9513 | |||
| 9514 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmuls16.c' | ||
| 9515 | --- old/gcc/testsuite/gcc.target/arm/neon/vmuls16.c 2010-07-29 15:38:15 +0000 | ||
| 9516 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmuls16.c 2010-08-20 13:27:11 +0000 | ||
| 9517 | @@ -17,5 +17,5 @@ | ||
| 9518 | out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 9519 | } | ||
| 9520 | |||
| 9521 | -/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9522 | +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9523 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9524 | |||
| 9525 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmuls32.c' | ||
| 9526 | --- old/gcc/testsuite/gcc.target/arm/neon/vmuls32.c 2010-07-29 15:38:15 +0000 | ||
| 9527 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmuls32.c 2010-08-20 13:27:11 +0000 | ||
| 9528 | @@ -17,5 +17,5 @@ | ||
| 9529 | out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 9530 | } | ||
| 9531 | |||
| 9532 | -/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9533 | +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9534 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9535 | |||
| 9536 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmuls8.c' | ||
| 9537 | --- old/gcc/testsuite/gcc.target/arm/neon/vmuls8.c 2010-07-29 15:38:15 +0000 | ||
| 9538 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmuls8.c 2010-08-20 13:27:11 +0000 | ||
| 9539 | @@ -17,5 +17,5 @@ | ||
| 9540 | out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 9541 | } | ||
| 9542 | |||
| 9543 | -/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9544 | +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9545 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9546 | |||
| 9547 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulu16.c' | ||
| 9548 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulu16.c 2010-07-29 15:38:15 +0000 | ||
| 9549 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulu16.c 2010-08-20 13:27:11 +0000 | ||
| 9550 | @@ -17,5 +17,5 @@ | ||
| 9551 | out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 9552 | } | ||
| 9553 | |||
| 9554 | -/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9555 | +/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9556 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9557 | |||
| 9558 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulu32.c' | ||
| 9559 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulu32.c 2010-07-29 15:38:15 +0000 | ||
| 9560 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulu32.c 2010-08-20 13:27:11 +0000 | ||
| 9561 | @@ -17,5 +17,5 @@ | ||
| 9562 | out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 9563 | } | ||
| 9564 | |||
| 9565 | -/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9566 | +/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9567 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9568 | |||
| 9569 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmulu8.c' | ||
| 9570 | --- old/gcc/testsuite/gcc.target/arm/neon/vmulu8.c 2010-07-29 15:38:15 +0000 | ||
| 9571 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmulu8.c 2010-08-20 13:27:11 +0000 | ||
| 9572 | @@ -17,5 +17,5 @@ | ||
| 9573 | out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 9574 | } | ||
| 9575 | |||
| 9576 | -/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9577 | +/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9578 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9579 | |||
| 9580 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c' | ||
| 9581 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c 2010-07-29 15:38:15 +0000 | ||
| 9582 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c 2010-08-20 13:27:11 +0000 | ||
| 9583 | @@ -16,5 +16,5 @@ | ||
| 9584 | out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t); | ||
| 9585 | } | ||
| 9586 | |||
| 9587 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9588 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9589 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9590 | |||
| 9591 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c' | ||
| 9592 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c 2010-07-29 15:38:15 +0000 | ||
| 9593 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c 2010-08-20 13:27:11 +0000 | ||
| 9594 | @@ -16,5 +16,5 @@ | ||
| 9595 | out_int16x8_t = vmvnq_s16 (arg0_int16x8_t); | ||
| 9596 | } | ||
| 9597 | |||
| 9598 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9599 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9600 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9601 | |||
| 9602 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c' | ||
| 9603 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c 2010-07-29 15:38:15 +0000 | ||
| 9604 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c 2010-08-20 13:27:11 +0000 | ||
| 9605 | @@ -16,5 +16,5 @@ | ||
| 9606 | out_int32x4_t = vmvnq_s32 (arg0_int32x4_t); | ||
| 9607 | } | ||
| 9608 | |||
| 9609 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9610 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9611 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9612 | |||
| 9613 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c' | ||
| 9614 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c 2010-07-29 15:38:15 +0000 | ||
| 9615 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c 2010-08-20 13:27:11 +0000 | ||
| 9616 | @@ -16,5 +16,5 @@ | ||
| 9617 | out_int8x16_t = vmvnq_s8 (arg0_int8x16_t); | ||
| 9618 | } | ||
| 9619 | |||
| 9620 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9621 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9622 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9623 | |||
| 9624 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c' | ||
| 9625 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c 2010-07-29 15:38:15 +0000 | ||
| 9626 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c 2010-08-20 13:27:11 +0000 | ||
| 9627 | @@ -16,5 +16,5 @@ | ||
| 9628 | out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t); | ||
| 9629 | } | ||
| 9630 | |||
| 9631 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9632 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9633 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9634 | |||
| 9635 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c' | ||
| 9636 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c 2010-07-29 15:38:15 +0000 | ||
| 9637 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c 2010-08-20 13:27:11 +0000 | ||
| 9638 | @@ -16,5 +16,5 @@ | ||
| 9639 | out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t); | ||
| 9640 | } | ||
| 9641 | |||
| 9642 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9643 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9644 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9645 | |||
| 9646 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c' | ||
| 9647 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c 2010-07-29 15:38:15 +0000 | ||
| 9648 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c 2010-08-20 13:27:11 +0000 | ||
| 9649 | @@ -16,5 +16,5 @@ | ||
| 9650 | out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t); | ||
| 9651 | } | ||
| 9652 | |||
| 9653 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9654 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9655 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9656 | |||
| 9657 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnp8.c' | ||
| 9658 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c 2010-07-29 15:38:15 +0000 | ||
| 9659 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c 2010-08-20 13:27:11 +0000 | ||
| 9660 | @@ -16,5 +16,5 @@ | ||
| 9661 | out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t); | ||
| 9662 | } | ||
| 9663 | |||
| 9664 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9665 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9666 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9667 | |||
| 9668 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvns16.c' | ||
| 9669 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvns16.c 2010-07-29 15:38:15 +0000 | ||
| 9670 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvns16.c 2010-08-20 13:27:11 +0000 | ||
| 9671 | @@ -16,5 +16,5 @@ | ||
| 9672 | out_int16x4_t = vmvn_s16 (arg0_int16x4_t); | ||
| 9673 | } | ||
| 9674 | |||
| 9675 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9676 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9677 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9678 | |||
| 9679 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvns32.c' | ||
| 9680 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvns32.c 2010-07-29 15:38:15 +0000 | ||
| 9681 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvns32.c 2010-08-20 13:27:11 +0000 | ||
| 9682 | @@ -16,5 +16,5 @@ | ||
| 9683 | out_int32x2_t = vmvn_s32 (arg0_int32x2_t); | ||
| 9684 | } | ||
| 9685 | |||
| 9686 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9687 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9688 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9689 | |||
| 9690 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvns8.c' | ||
| 9691 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvns8.c 2010-07-29 15:38:15 +0000 | ||
| 9692 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvns8.c 2010-08-20 13:27:11 +0000 | ||
| 9693 | @@ -16,5 +16,5 @@ | ||
| 9694 | out_int8x8_t = vmvn_s8 (arg0_int8x8_t); | ||
| 9695 | } | ||
| 9696 | |||
| 9697 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9698 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9699 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9700 | |||
| 9701 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnu16.c' | ||
| 9702 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c 2010-07-29 15:38:15 +0000 | ||
| 9703 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c 2010-08-20 13:27:11 +0000 | ||
| 9704 | @@ -16,5 +16,5 @@ | ||
| 9705 | out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t); | ||
| 9706 | } | ||
| 9707 | |||
| 9708 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9709 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9710 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9711 | |||
| 9712 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnu32.c' | ||
| 9713 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c 2010-07-29 15:38:15 +0000 | ||
| 9714 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c 2010-08-20 13:27:11 +0000 | ||
| 9715 | @@ -16,5 +16,5 @@ | ||
| 9716 | out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t); | ||
| 9717 | } | ||
| 9718 | |||
| 9719 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9720 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9721 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9722 | |||
| 9723 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vmvnu8.c' | ||
| 9724 | --- old/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c 2010-07-29 15:38:15 +0000 | ||
| 9725 | +++ new/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c 2010-08-20 13:27:11 +0000 | ||
| 9726 | @@ -16,5 +16,5 @@ | ||
| 9727 | out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t); | ||
| 9728 | } | ||
| 9729 | |||
| 9730 | -/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9731 | +/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9732 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9733 | |||
| 9734 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQf32.c' | ||
| 9735 | --- old/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c 2010-07-29 15:38:15 +0000 | ||
| 9736 | +++ new/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c 2010-08-20 13:27:11 +0000 | ||
| 9737 | @@ -16,5 +16,5 @@ | ||
| 9738 | out_float32x4_t = vnegq_f32 (arg0_float32x4_t); | ||
| 9739 | } | ||
| 9740 | |||
| 9741 | -/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9742 | +/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9743 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9744 | |||
| 9745 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQs16.c' | ||
| 9746 | --- old/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c 2010-07-29 15:38:15 +0000 | ||
| 9747 | +++ new/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c 2010-08-20 13:27:11 +0000 | ||
| 9748 | @@ -16,5 +16,5 @@ | ||
| 9749 | out_int16x8_t = vnegq_s16 (arg0_int16x8_t); | ||
| 9750 | } | ||
| 9751 | |||
| 9752 | -/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9753 | +/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9754 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9755 | |||
| 9756 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQs32.c' | ||
| 9757 | --- old/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c 2010-07-29 15:38:15 +0000 | ||
| 9758 | +++ new/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c 2010-08-20 13:27:11 +0000 | ||
| 9759 | @@ -16,5 +16,5 @@ | ||
| 9760 | out_int32x4_t = vnegq_s32 (arg0_int32x4_t); | ||
| 9761 | } | ||
| 9762 | |||
| 9763 | -/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9764 | +/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9765 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9766 | |||
| 9767 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vnegQs8.c' | ||
| 9768 | --- old/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c 2010-07-29 15:38:15 +0000 | ||
| 9769 | +++ new/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c 2010-08-20 13:27:11 +0000 | ||
| 9770 | @@ -16,5 +16,5 @@ | ||
| 9771 | out_int8x16_t = vnegq_s8 (arg0_int8x16_t); | ||
| 9772 | } | ||
| 9773 | |||
| 9774 | -/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9775 | +/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9776 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9777 | |||
| 9778 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vnegf32.c' | ||
| 9779 | --- old/gcc/testsuite/gcc.target/arm/neon/vnegf32.c 2010-07-29 15:38:15 +0000 | ||
| 9780 | +++ new/gcc/testsuite/gcc.target/arm/neon/vnegf32.c 2010-08-20 13:27:11 +0000 | ||
| 9781 | @@ -16,5 +16,5 @@ | ||
| 9782 | out_float32x2_t = vneg_f32 (arg0_float32x2_t); | ||
| 9783 | } | ||
| 9784 | |||
| 9785 | -/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9786 | +/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9787 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9788 | |||
| 9789 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vnegs16.c' | ||
| 9790 | --- old/gcc/testsuite/gcc.target/arm/neon/vnegs16.c 2010-07-29 15:38:15 +0000 | ||
| 9791 | +++ new/gcc/testsuite/gcc.target/arm/neon/vnegs16.c 2010-08-20 13:27:11 +0000 | ||
| 9792 | @@ -16,5 +16,5 @@ | ||
| 9793 | out_int16x4_t = vneg_s16 (arg0_int16x4_t); | ||
| 9794 | } | ||
| 9795 | |||
| 9796 | -/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9797 | +/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9798 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9799 | |||
| 9800 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vnegs32.c' | ||
| 9801 | --- old/gcc/testsuite/gcc.target/arm/neon/vnegs32.c 2010-07-29 15:38:15 +0000 | ||
| 9802 | +++ new/gcc/testsuite/gcc.target/arm/neon/vnegs32.c 2010-08-20 13:27:11 +0000 | ||
| 9803 | @@ -16,5 +16,5 @@ | ||
| 9804 | out_int32x2_t = vneg_s32 (arg0_int32x2_t); | ||
| 9805 | } | ||
| 9806 | |||
| 9807 | -/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9808 | +/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9809 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9810 | |||
| 9811 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vnegs8.c' | ||
| 9812 | --- old/gcc/testsuite/gcc.target/arm/neon/vnegs8.c 2010-07-29 15:38:15 +0000 | ||
| 9813 | +++ new/gcc/testsuite/gcc.target/arm/neon/vnegs8.c 2010-08-20 13:27:11 +0000 | ||
| 9814 | @@ -16,5 +16,5 @@ | ||
| 9815 | out_int8x8_t = vneg_s8 (arg0_int8x8_t); | ||
| 9816 | } | ||
| 9817 | |||
| 9818 | -/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9819 | +/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9820 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9821 | |||
| 9822 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs16.c' | ||
| 9823 | --- old/gcc/testsuite/gcc.target/arm/neon/vornQs16.c 2010-07-29 15:38:15 +0000 | ||
| 9824 | +++ new/gcc/testsuite/gcc.target/arm/neon/vornQs16.c 2010-08-20 13:27:11 +0000 | ||
| 9825 | @@ -17,5 +17,5 @@ | ||
| 9826 | out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 9827 | } | ||
| 9828 | |||
| 9829 | -/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9830 | +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9831 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9832 | |||
| 9833 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs32.c' | ||
| 9834 | --- old/gcc/testsuite/gcc.target/arm/neon/vornQs32.c 2010-07-29 15:38:15 +0000 | ||
| 9835 | +++ new/gcc/testsuite/gcc.target/arm/neon/vornQs32.c 2010-08-20 13:27:11 +0000 | ||
| 9836 | @@ -17,5 +17,5 @@ | ||
| 9837 | out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 9838 | } | ||
| 9839 | |||
| 9840 | -/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9841 | +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9842 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9843 | |||
| 9844 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs64.c' | ||
| 9845 | --- old/gcc/testsuite/gcc.target/arm/neon/vornQs64.c 2010-07-29 15:38:15 +0000 | ||
| 9846 | +++ new/gcc/testsuite/gcc.target/arm/neon/vornQs64.c 2010-08-20 13:27:11 +0000 | ||
| 9847 | @@ -17,5 +17,5 @@ | ||
| 9848 | out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 9849 | } | ||
| 9850 | |||
| 9851 | -/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9852 | +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9853 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9854 | |||
| 9855 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vornQs8.c' | ||
| 9856 | --- old/gcc/testsuite/gcc.target/arm/neon/vornQs8.c 2010-07-29 15:38:15 +0000 | ||
| 9857 | +++ new/gcc/testsuite/gcc.target/arm/neon/vornQs8.c 2010-08-20 13:27:11 +0000 | ||
| 9858 | @@ -17,5 +17,5 @@ | ||
| 9859 | out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 9860 | } | ||
| 9861 | |||
| 9862 | -/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9863 | +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9864 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9865 | |||
| 9866 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu16.c' | ||
| 9867 | --- old/gcc/testsuite/gcc.target/arm/neon/vornQu16.c 2010-07-29 15:38:15 +0000 | ||
| 9868 | +++ new/gcc/testsuite/gcc.target/arm/neon/vornQu16.c 2010-08-20 13:27:11 +0000 | ||
| 9869 | @@ -17,5 +17,5 @@ | ||
| 9870 | out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 9871 | } | ||
| 9872 | |||
| 9873 | -/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9874 | +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9875 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9876 | |||
| 9877 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu32.c' | ||
| 9878 | --- old/gcc/testsuite/gcc.target/arm/neon/vornQu32.c 2010-07-29 15:38:15 +0000 | ||
| 9879 | +++ new/gcc/testsuite/gcc.target/arm/neon/vornQu32.c 2010-08-20 13:27:11 +0000 | ||
| 9880 | @@ -17,5 +17,5 @@ | ||
| 9881 | out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 9882 | } | ||
| 9883 | |||
| 9884 | -/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9885 | +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9886 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9887 | |||
| 9888 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu64.c' | ||
| 9889 | --- old/gcc/testsuite/gcc.target/arm/neon/vornQu64.c 2010-07-29 15:38:15 +0000 | ||
| 9890 | +++ new/gcc/testsuite/gcc.target/arm/neon/vornQu64.c 2010-08-20 13:27:11 +0000 | ||
| 9891 | @@ -17,5 +17,5 @@ | ||
| 9892 | out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 9893 | } | ||
| 9894 | |||
| 9895 | -/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9896 | +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9897 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9898 | |||
| 9899 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vornQu8.c' | ||
| 9900 | --- old/gcc/testsuite/gcc.target/arm/neon/vornQu8.c 2010-07-29 15:38:15 +0000 | ||
| 9901 | +++ new/gcc/testsuite/gcc.target/arm/neon/vornQu8.c 2010-08-20 13:27:11 +0000 | ||
| 9902 | @@ -17,5 +17,5 @@ | ||
| 9903 | out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 9904 | } | ||
| 9905 | |||
| 9906 | -/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9907 | +/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9908 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9909 | |||
| 9910 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorns16.c' | ||
| 9911 | --- old/gcc/testsuite/gcc.target/arm/neon/vorns16.c 2010-07-29 15:38:15 +0000 | ||
| 9912 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorns16.c 2010-08-20 13:27:11 +0000 | ||
| 9913 | @@ -17,5 +17,5 @@ | ||
| 9914 | out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 9915 | } | ||
| 9916 | |||
| 9917 | -/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9918 | +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9919 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9920 | |||
| 9921 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorns32.c' | ||
| 9922 | --- old/gcc/testsuite/gcc.target/arm/neon/vorns32.c 2010-07-29 15:38:15 +0000 | ||
| 9923 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorns32.c 2010-08-20 13:27:11 +0000 | ||
| 9924 | @@ -17,5 +17,5 @@ | ||
| 9925 | out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 9926 | } | ||
| 9927 | |||
| 9928 | -/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9929 | +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9930 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9931 | |||
| 9932 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorns8.c' | ||
| 9933 | --- old/gcc/testsuite/gcc.target/arm/neon/vorns8.c 2010-07-29 15:38:15 +0000 | ||
| 9934 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorns8.c 2010-08-20 13:27:11 +0000 | ||
| 9935 | @@ -17,5 +17,5 @@ | ||
| 9936 | out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 9937 | } | ||
| 9938 | |||
| 9939 | -/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9940 | +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9941 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9942 | |||
| 9943 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vornu16.c' | ||
| 9944 | --- old/gcc/testsuite/gcc.target/arm/neon/vornu16.c 2010-07-29 15:38:15 +0000 | ||
| 9945 | +++ new/gcc/testsuite/gcc.target/arm/neon/vornu16.c 2010-08-20 13:27:11 +0000 | ||
| 9946 | @@ -17,5 +17,5 @@ | ||
| 9947 | out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 9948 | } | ||
| 9949 | |||
| 9950 | -/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9951 | +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9952 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9953 | |||
| 9954 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vornu32.c' | ||
| 9955 | --- old/gcc/testsuite/gcc.target/arm/neon/vornu32.c 2010-07-29 15:38:15 +0000 | ||
| 9956 | +++ new/gcc/testsuite/gcc.target/arm/neon/vornu32.c 2010-08-20 13:27:11 +0000 | ||
| 9957 | @@ -17,5 +17,5 @@ | ||
| 9958 | out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 9959 | } | ||
| 9960 | |||
| 9961 | -/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9962 | +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9963 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9964 | |||
| 9965 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vornu8.c' | ||
| 9966 | --- old/gcc/testsuite/gcc.target/arm/neon/vornu8.c 2010-07-29 15:38:15 +0000 | ||
| 9967 | +++ new/gcc/testsuite/gcc.target/arm/neon/vornu8.c 2010-08-20 13:27:11 +0000 | ||
| 9968 | @@ -17,5 +17,5 @@ | ||
| 9969 | out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 9970 | } | ||
| 9971 | |||
| 9972 | -/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9973 | +/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9974 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9975 | |||
| 9976 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs16.c' | ||
| 9977 | --- old/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c 2010-07-29 15:38:15 +0000 | ||
| 9978 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c 2010-08-20 13:27:11 +0000 | ||
| 9979 | @@ -17,5 +17,5 @@ | ||
| 9980 | out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 9981 | } | ||
| 9982 | |||
| 9983 | -/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9984 | +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9985 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9986 | |||
| 9987 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs32.c' | ||
| 9988 | --- old/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c 2010-07-29 15:38:15 +0000 | ||
| 9989 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c 2010-08-20 13:27:11 +0000 | ||
| 9990 | @@ -17,5 +17,5 @@ | ||
| 9991 | out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 9992 | } | ||
| 9993 | |||
| 9994 | -/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 9995 | +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 9996 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 9997 | |||
| 9998 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs64.c' | ||
| 9999 | --- old/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c 2010-07-29 15:38:15 +0000 | ||
| 10000 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c 2010-08-20 13:27:11 +0000 | ||
| 10001 | @@ -17,5 +17,5 @@ | ||
| 10002 | out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 10003 | } | ||
| 10004 | |||
| 10005 | -/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10006 | +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10007 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10008 | |||
| 10009 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQs8.c' | ||
| 10010 | --- old/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c 2010-07-29 15:38:15 +0000 | ||
| 10011 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c 2010-08-20 13:27:11 +0000 | ||
| 10012 | @@ -17,5 +17,5 @@ | ||
| 10013 | out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 10014 | } | ||
| 10015 | |||
| 10016 | -/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10017 | +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10018 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10019 | |||
| 10020 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu16.c' | ||
| 10021 | --- old/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c 2010-07-29 15:38:15 +0000 | ||
| 10022 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c 2010-08-20 13:27:11 +0000 | ||
| 10023 | @@ -17,5 +17,5 @@ | ||
| 10024 | out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 10025 | } | ||
| 10026 | |||
| 10027 | -/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10028 | +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10029 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10030 | |||
| 10031 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu32.c' | ||
| 10032 | --- old/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c 2010-07-29 15:38:15 +0000 | ||
| 10033 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c 2010-08-20 13:27:11 +0000 | ||
| 10034 | @@ -17,5 +17,5 @@ | ||
| 10035 | out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 10036 | } | ||
| 10037 | |||
| 10038 | -/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10039 | +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10040 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10041 | |||
| 10042 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu64.c' | ||
| 10043 | --- old/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c 2010-07-29 15:38:15 +0000 | ||
| 10044 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c 2010-08-20 13:27:11 +0000 | ||
| 10045 | @@ -17,5 +17,5 @@ | ||
| 10046 | out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 10047 | } | ||
| 10048 | |||
| 10049 | -/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10050 | +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10051 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10052 | |||
| 10053 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorrQu8.c' | ||
| 10054 | --- old/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c 2010-07-29 15:38:15 +0000 | ||
| 10055 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c 2010-08-20 13:27:11 +0000 | ||
| 10056 | @@ -17,5 +17,5 @@ | ||
| 10057 | out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 10058 | } | ||
| 10059 | |||
| 10060 | -/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10061 | +/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10062 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10063 | |||
| 10064 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs16.c' | ||
| 10065 | --- old/gcc/testsuite/gcc.target/arm/neon/vorrs16.c 2010-07-29 15:38:15 +0000 | ||
| 10066 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorrs16.c 2010-08-20 13:27:11 +0000 | ||
| 10067 | @@ -17,5 +17,5 @@ | ||
| 10068 | out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 10069 | } | ||
| 10070 | |||
| 10071 | -/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10072 | +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10073 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10074 | |||
| 10075 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs32.c' | ||
| 10076 | --- old/gcc/testsuite/gcc.target/arm/neon/vorrs32.c 2010-07-29 15:38:15 +0000 | ||
| 10077 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorrs32.c 2010-08-20 13:27:11 +0000 | ||
| 10078 | @@ -17,5 +17,5 @@ | ||
| 10079 | out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 10080 | } | ||
| 10081 | |||
| 10082 | -/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10083 | +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10084 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10085 | |||
| 10086 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorrs8.c' | ||
| 10087 | --- old/gcc/testsuite/gcc.target/arm/neon/vorrs8.c 2010-07-29 15:38:15 +0000 | ||
| 10088 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorrs8.c 2010-08-20 13:27:11 +0000 | ||
| 10089 | @@ -17,5 +17,5 @@ | ||
| 10090 | out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 10091 | } | ||
| 10092 | |||
| 10093 | -/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10094 | +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10095 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10096 | |||
| 10097 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorru16.c' | ||
| 10098 | --- old/gcc/testsuite/gcc.target/arm/neon/vorru16.c 2010-07-29 15:38:15 +0000 | ||
| 10099 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorru16.c 2010-08-20 13:27:11 +0000 | ||
| 10100 | @@ -17,5 +17,5 @@ | ||
| 10101 | out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 10102 | } | ||
| 10103 | |||
| 10104 | -/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10105 | +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10106 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10107 | |||
| 10108 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorru32.c' | ||
| 10109 | --- old/gcc/testsuite/gcc.target/arm/neon/vorru32.c 2010-07-29 15:38:15 +0000 | ||
| 10110 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorru32.c 2010-08-20 13:27:11 +0000 | ||
| 10111 | @@ -17,5 +17,5 @@ | ||
| 10112 | out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 10113 | } | ||
| 10114 | |||
| 10115 | -/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10116 | +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10117 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10118 | |||
| 10119 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vorru8.c' | ||
| 10120 | --- old/gcc/testsuite/gcc.target/arm/neon/vorru8.c 2010-07-29 15:38:15 +0000 | ||
| 10121 | +++ new/gcc/testsuite/gcc.target/arm/neon/vorru8.c 2010-08-20 13:27:11 +0000 | ||
| 10122 | @@ -17,5 +17,5 @@ | ||
| 10123 | out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 10124 | } | ||
| 10125 | |||
| 10126 | -/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10127 | +/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10128 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10129 | |||
| 10130 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c' | ||
| 10131 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c 2010-07-29 15:38:15 +0000 | ||
| 10132 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c 2010-08-20 13:27:11 +0000 | ||
| 10133 | @@ -17,5 +17,5 @@ | ||
| 10134 | out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t); | ||
| 10135 | } | ||
| 10136 | |||
| 10137 | -/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10138 | +/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10139 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10140 | |||
| 10141 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c' | ||
| 10142 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c 2010-07-29 15:38:15 +0000 | ||
| 10143 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c 2010-08-20 13:27:11 +0000 | ||
| 10144 | @@ -17,5 +17,5 @@ | ||
| 10145 | out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t); | ||
| 10146 | } | ||
| 10147 | |||
| 10148 | -/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10149 | +/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10150 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10151 | |||
| 10152 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c' | ||
| 10153 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c 2010-07-29 15:38:15 +0000 | ||
| 10154 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c 2010-08-20 13:27:11 +0000 | ||
| 10155 | @@ -17,5 +17,5 @@ | ||
| 10156 | out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t); | ||
| 10157 | } | ||
| 10158 | |||
| 10159 | -/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10160 | +/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10161 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10162 | |||
| 10163 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c' | ||
| 10164 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c 2010-07-29 15:38:15 +0000 | ||
| 10165 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c 2010-08-20 13:27:11 +0000 | ||
| 10166 | @@ -17,5 +17,5 @@ | ||
| 10167 | out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t); | ||
| 10168 | } | ||
| 10169 | |||
| 10170 | -/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10171 | +/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10172 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10173 | |||
| 10174 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c' | ||
| 10175 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c 2010-07-29 15:38:15 +0000 | ||
| 10176 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c 2010-08-20 13:27:11 +0000 | ||
| 10177 | @@ -17,5 +17,5 @@ | ||
| 10178 | out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t); | ||
| 10179 | } | ||
| 10180 | |||
| 10181 | -/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10182 | +/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10183 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10184 | |||
| 10185 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c' | ||
| 10186 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c 2010-07-29 15:38:15 +0000 | ||
| 10187 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c 2010-08-20 13:27:11 +0000 | ||
| 10188 | @@ -17,5 +17,5 @@ | ||
| 10189 | out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t); | ||
| 10190 | } | ||
| 10191 | |||
| 10192 | -/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10193 | +/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10194 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10195 | |||
| 10196 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadals16.c' | ||
| 10197 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadals16.c 2010-07-29 15:38:15 +0000 | ||
| 10198 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadals16.c 2010-08-20 13:27:11 +0000 | ||
| 10199 | @@ -17,5 +17,5 @@ | ||
| 10200 | out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t); | ||
| 10201 | } | ||
| 10202 | |||
| 10203 | -/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10204 | +/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10205 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10206 | |||
| 10207 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadals32.c' | ||
| 10208 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadals32.c 2010-07-29 15:38:15 +0000 | ||
| 10209 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadals32.c 2010-08-20 13:27:11 +0000 | ||
| 10210 | @@ -17,5 +17,5 @@ | ||
| 10211 | out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t); | ||
| 10212 | } | ||
| 10213 | |||
| 10214 | -/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10215 | +/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10216 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10217 | |||
| 10218 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadals8.c' | ||
| 10219 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadals8.c 2010-07-29 15:38:15 +0000 | ||
| 10220 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadals8.c 2010-08-20 13:27:11 +0000 | ||
| 10221 | @@ -17,5 +17,5 @@ | ||
| 10222 | out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t); | ||
| 10223 | } | ||
| 10224 | |||
| 10225 | -/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10226 | +/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10227 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10228 | |||
| 10229 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalu16.c' | ||
| 10230 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c 2010-07-29 15:38:15 +0000 | ||
| 10231 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c 2010-08-20 13:27:11 +0000 | ||
| 10232 | @@ -17,5 +17,5 @@ | ||
| 10233 | out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t); | ||
| 10234 | } | ||
| 10235 | |||
| 10236 | -/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10237 | +/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10238 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10239 | |||
| 10240 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalu32.c' | ||
| 10241 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c 2010-07-29 15:38:15 +0000 | ||
| 10242 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c 2010-08-20 13:27:11 +0000 | ||
| 10243 | @@ -17,5 +17,5 @@ | ||
| 10244 | out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t); | ||
| 10245 | } | ||
| 10246 | |||
| 10247 | -/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10248 | +/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10249 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10250 | |||
| 10251 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadalu8.c' | ||
| 10252 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c 2010-07-29 15:38:15 +0000 | ||
| 10253 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c 2010-08-20 13:27:11 +0000 | ||
| 10254 | @@ -17,5 +17,5 @@ | ||
| 10255 | out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t); | ||
| 10256 | } | ||
| 10257 | |||
| 10258 | -/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10259 | +/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10260 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10261 | |||
| 10262 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddf32.c' | ||
| 10263 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c 2010-07-29 15:38:15 +0000 | ||
| 10264 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c 2010-08-20 13:27:11 +0000 | ||
| 10265 | @@ -17,5 +17,5 @@ | ||
| 10266 | out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 10267 | } | ||
| 10268 | |||
| 10269 | -/* { dg-final { scan-assembler "vpadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10270 | +/* { dg-final { scan-assembler "vpadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10271 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10272 | |||
| 10273 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c' | ||
| 10274 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c 2010-07-29 15:38:15 +0000 | ||
| 10275 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c 2010-08-20 13:27:11 +0000 | ||
| 10276 | @@ -16,5 +16,5 @@ | ||
| 10277 | out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t); | ||
| 10278 | } | ||
| 10279 | |||
| 10280 | -/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10281 | +/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10282 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10283 | |||
| 10284 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c' | ||
| 10285 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c 2010-07-29 15:38:15 +0000 | ||
| 10286 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c 2010-08-20 13:27:11 +0000 | ||
| 10287 | @@ -16,5 +16,5 @@ | ||
| 10288 | out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t); | ||
| 10289 | } | ||
| 10290 | |||
| 10291 | -/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10292 | +/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10293 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10294 | |||
| 10295 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c' | ||
| 10296 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c 2010-07-29 15:38:15 +0000 | ||
| 10297 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c 2010-08-20 13:27:11 +0000 | ||
| 10298 | @@ -16,5 +16,5 @@ | ||
| 10299 | out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t); | ||
| 10300 | } | ||
| 10301 | |||
| 10302 | -/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10303 | +/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10304 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10305 | |||
| 10306 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c' | ||
| 10307 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c 2010-07-29 15:38:15 +0000 | ||
| 10308 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c 2010-08-20 13:27:11 +0000 | ||
| 10309 | @@ -16,5 +16,5 @@ | ||
| 10310 | out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t); | ||
| 10311 | } | ||
| 10312 | |||
| 10313 | -/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10314 | +/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10315 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10316 | |||
| 10317 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c' | ||
| 10318 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c 2010-07-29 15:38:15 +0000 | ||
| 10319 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c 2010-08-20 13:27:11 +0000 | ||
| 10320 | @@ -16,5 +16,5 @@ | ||
| 10321 | out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t); | ||
| 10322 | } | ||
| 10323 | |||
| 10324 | -/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10325 | +/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10326 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10327 | |||
| 10328 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c' | ||
| 10329 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c 2010-07-29 15:38:15 +0000 | ||
| 10330 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c 2010-08-20 13:27:11 +0000 | ||
| 10331 | @@ -16,5 +16,5 @@ | ||
| 10332 | out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t); | ||
| 10333 | } | ||
| 10334 | |||
| 10335 | -/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10336 | +/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10337 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10338 | |||
| 10339 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddls16.c' | ||
| 10340 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c 2010-07-29 15:38:15 +0000 | ||
| 10341 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c 2010-08-20 13:27:11 +0000 | ||
| 10342 | @@ -16,5 +16,5 @@ | ||
| 10343 | out_int32x2_t = vpaddl_s16 (arg0_int16x4_t); | ||
| 10344 | } | ||
| 10345 | |||
| 10346 | -/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10347 | +/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10348 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10349 | |||
| 10350 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddls32.c' | ||
| 10351 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c 2010-07-29 15:38:15 +0000 | ||
| 10352 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c 2010-08-20 13:27:11 +0000 | ||
| 10353 | @@ -16,5 +16,5 @@ | ||
| 10354 | out_int64x1_t = vpaddl_s32 (arg0_int32x2_t); | ||
| 10355 | } | ||
| 10356 | |||
| 10357 | -/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10358 | +/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10359 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10360 | |||
| 10361 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddls8.c' | ||
| 10362 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c 2010-07-29 15:38:15 +0000 | ||
| 10363 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c 2010-08-20 13:27:11 +0000 | ||
| 10364 | @@ -16,5 +16,5 @@ | ||
| 10365 | out_int16x4_t = vpaddl_s8 (arg0_int8x8_t); | ||
| 10366 | } | ||
| 10367 | |||
| 10368 | -/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10369 | +/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10370 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10371 | |||
| 10372 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c' | ||
| 10373 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c 2010-07-29 15:38:15 +0000 | ||
| 10374 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c 2010-08-20 13:27:11 +0000 | ||
| 10375 | @@ -16,5 +16,5 @@ | ||
| 10376 | out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t); | ||
| 10377 | } | ||
| 10378 | |||
| 10379 | -/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10380 | +/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10381 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10382 | |||
| 10383 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c' | ||
| 10384 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c 2010-07-29 15:38:15 +0000 | ||
| 10385 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c 2010-08-20 13:27:11 +0000 | ||
| 10386 | @@ -16,5 +16,5 @@ | ||
| 10387 | out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t); | ||
| 10388 | } | ||
| 10389 | |||
| 10390 | -/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10391 | +/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10392 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10393 | |||
| 10394 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c' | ||
| 10395 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c 2010-07-29 15:38:15 +0000 | ||
| 10396 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c 2010-08-20 13:27:11 +0000 | ||
| 10397 | @@ -16,5 +16,5 @@ | ||
| 10398 | out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t); | ||
| 10399 | } | ||
| 10400 | |||
| 10401 | -/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10402 | +/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10403 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10404 | |||
| 10405 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadds16.c' | ||
| 10406 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadds16.c 2010-07-29 15:38:15 +0000 | ||
| 10407 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadds16.c 2010-08-20 13:27:11 +0000 | ||
| 10408 | @@ -17,5 +17,5 @@ | ||
| 10409 | out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 10410 | } | ||
| 10411 | |||
| 10412 | -/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10413 | +/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10414 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10415 | |||
| 10416 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadds32.c' | ||
| 10417 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadds32.c 2010-07-29 15:38:15 +0000 | ||
| 10418 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadds32.c 2010-08-20 13:27:11 +0000 | ||
| 10419 | @@ -17,5 +17,5 @@ | ||
| 10420 | out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 10421 | } | ||
| 10422 | |||
| 10423 | -/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10424 | +/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10425 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10426 | |||
| 10427 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpadds8.c' | ||
| 10428 | --- old/gcc/testsuite/gcc.target/arm/neon/vpadds8.c 2010-07-29 15:38:15 +0000 | ||
| 10429 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpadds8.c 2010-08-20 13:27:11 +0000 | ||
| 10430 | @@ -17,5 +17,5 @@ | ||
| 10431 | out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 10432 | } | ||
| 10433 | |||
| 10434 | -/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10435 | +/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10436 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10437 | |||
| 10438 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddu16.c' | ||
| 10439 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c 2010-07-29 15:38:15 +0000 | ||
| 10440 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c 2010-08-20 13:27:11 +0000 | ||
| 10441 | @@ -17,5 +17,5 @@ | ||
| 10442 | out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 10443 | } | ||
| 10444 | |||
| 10445 | -/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10446 | +/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10447 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10448 | |||
| 10449 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddu32.c' | ||
| 10450 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c 2010-07-29 15:38:15 +0000 | ||
| 10451 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c 2010-08-20 13:27:11 +0000 | ||
| 10452 | @@ -17,5 +17,5 @@ | ||
| 10453 | out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 10454 | } | ||
| 10455 | |||
| 10456 | -/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10457 | +/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10458 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10459 | |||
| 10460 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpaddu8.c' | ||
| 10461 | --- old/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c 2010-07-29 15:38:15 +0000 | ||
| 10462 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c 2010-08-20 13:27:11 +0000 | ||
| 10463 | @@ -17,5 +17,5 @@ | ||
| 10464 | out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 10465 | } | ||
| 10466 | |||
| 10467 | -/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10468 | +/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10469 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10470 | |||
| 10471 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c' | ||
| 10472 | --- old/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c 2010-07-29 15:38:15 +0000 | ||
| 10473 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c 2010-08-20 13:27:11 +0000 | ||
| 10474 | @@ -17,5 +17,5 @@ | ||
| 10475 | out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 10476 | } | ||
| 10477 | |||
| 10478 | -/* { dg-final { scan-assembler "vpmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10479 | +/* { dg-final { scan-assembler "vpmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10480 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10481 | |||
| 10482 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c' | ||
| 10483 | --- old/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c 2010-07-29 15:38:15 +0000 | ||
| 10484 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c 2010-08-20 13:27:11 +0000 | ||
| 10485 | @@ -17,5 +17,5 @@ | ||
| 10486 | out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 10487 | } | ||
| 10488 | |||
| 10489 | -/* { dg-final { scan-assembler "vpmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10490 | +/* { dg-final { scan-assembler "vpmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10491 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10492 | |||
| 10493 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c' | ||
| 10494 | --- old/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c 2010-07-29 15:38:15 +0000 | ||
| 10495 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c 2010-08-20 13:27:11 +0000 | ||
| 10496 | @@ -17,5 +17,5 @@ | ||
| 10497 | out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 10498 | } | ||
| 10499 | |||
| 10500 | -/* { dg-final { scan-assembler "vpmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10501 | +/* { dg-final { scan-assembler "vpmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10502 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10503 | |||
| 10504 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c' | ||
| 10505 | --- old/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c 2010-07-29 15:38:15 +0000 | ||
| 10506 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c 2010-08-20 13:27:11 +0000 | ||
| 10507 | @@ -17,5 +17,5 @@ | ||
| 10508 | out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 10509 | } | ||
| 10510 | |||
| 10511 | -/* { dg-final { scan-assembler "vpmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10512 | +/* { dg-final { scan-assembler "vpmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10513 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10514 | |||
| 10515 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c' | ||
| 10516 | --- old/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c 2010-07-29 15:38:15 +0000 | ||
| 10517 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c 2010-08-20 13:27:11 +0000 | ||
| 10518 | @@ -17,5 +17,5 @@ | ||
| 10519 | out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 10520 | } | ||
| 10521 | |||
| 10522 | -/* { dg-final { scan-assembler "vpmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10523 | +/* { dg-final { scan-assembler "vpmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10524 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10525 | |||
| 10526 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c' | ||
| 10527 | --- old/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c 2010-07-29 15:38:15 +0000 | ||
| 10528 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c 2010-08-20 13:27:11 +0000 | ||
| 10529 | @@ -17,5 +17,5 @@ | ||
| 10530 | out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 10531 | } | ||
| 10532 | |||
| 10533 | -/* { dg-final { scan-assembler "vpmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10534 | +/* { dg-final { scan-assembler "vpmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10535 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10536 | |||
| 10537 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c' | ||
| 10538 | --- old/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c 2010-07-29 15:38:15 +0000 | ||
| 10539 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c 2010-08-20 13:27:11 +0000 | ||
| 10540 | @@ -17,5 +17,5 @@ | ||
| 10541 | out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 10542 | } | ||
| 10543 | |||
| 10544 | -/* { dg-final { scan-assembler "vpmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10545 | +/* { dg-final { scan-assembler "vpmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10546 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10547 | |||
| 10548 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpminf32.c' | ||
| 10549 | --- old/gcc/testsuite/gcc.target/arm/neon/vpminf32.c 2010-07-29 15:38:15 +0000 | ||
| 10550 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpminf32.c 2010-08-20 13:27:11 +0000 | ||
| 10551 | @@ -17,5 +17,5 @@ | ||
| 10552 | out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 10553 | } | ||
| 10554 | |||
| 10555 | -/* { dg-final { scan-assembler "vpmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10556 | +/* { dg-final { scan-assembler "vpmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10557 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10558 | |||
| 10559 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpmins16.c' | ||
| 10560 | --- old/gcc/testsuite/gcc.target/arm/neon/vpmins16.c 2010-07-29 15:38:15 +0000 | ||
| 10561 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpmins16.c 2010-08-20 13:27:11 +0000 | ||
| 10562 | @@ -17,5 +17,5 @@ | ||
| 10563 | out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 10564 | } | ||
| 10565 | |||
| 10566 | -/* { dg-final { scan-assembler "vpmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10567 | +/* { dg-final { scan-assembler "vpmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10568 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10569 | |||
| 10570 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpmins32.c' | ||
| 10571 | --- old/gcc/testsuite/gcc.target/arm/neon/vpmins32.c 2010-07-29 15:38:15 +0000 | ||
| 10572 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpmins32.c 2010-08-20 13:27:11 +0000 | ||
| 10573 | @@ -17,5 +17,5 @@ | ||
| 10574 | out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 10575 | } | ||
| 10576 | |||
| 10577 | -/* { dg-final { scan-assembler "vpmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10578 | +/* { dg-final { scan-assembler "vpmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10579 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10580 | |||
| 10581 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpmins8.c' | ||
| 10582 | --- old/gcc/testsuite/gcc.target/arm/neon/vpmins8.c 2010-07-29 15:38:15 +0000 | ||
| 10583 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpmins8.c 2010-08-20 13:27:11 +0000 | ||
| 10584 | @@ -17,5 +17,5 @@ | ||
| 10585 | out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 10586 | } | ||
| 10587 | |||
| 10588 | -/* { dg-final { scan-assembler "vpmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10589 | +/* { dg-final { scan-assembler "vpmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10590 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10591 | |||
| 10592 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpminu16.c' | ||
| 10593 | --- old/gcc/testsuite/gcc.target/arm/neon/vpminu16.c 2010-07-29 15:38:15 +0000 | ||
| 10594 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpminu16.c 2010-08-20 13:27:11 +0000 | ||
| 10595 | @@ -17,5 +17,5 @@ | ||
| 10596 | out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 10597 | } | ||
| 10598 | |||
| 10599 | -/* { dg-final { scan-assembler "vpmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10600 | +/* { dg-final { scan-assembler "vpmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10601 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10602 | |||
| 10603 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpminu32.c' | ||
| 10604 | --- old/gcc/testsuite/gcc.target/arm/neon/vpminu32.c 2010-07-29 15:38:15 +0000 | ||
| 10605 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpminu32.c 2010-08-20 13:27:11 +0000 | ||
| 10606 | @@ -17,5 +17,5 @@ | ||
| 10607 | out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 10608 | } | ||
| 10609 | |||
| 10610 | -/* { dg-final { scan-assembler "vpmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10611 | +/* { dg-final { scan-assembler "vpmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10612 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10613 | |||
| 10614 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vpminu8.c' | ||
| 10615 | --- old/gcc/testsuite/gcc.target/arm/neon/vpminu8.c 2010-07-29 15:38:15 +0000 | ||
| 10616 | +++ new/gcc/testsuite/gcc.target/arm/neon/vpminu8.c 2010-08-20 13:27:11 +0000 | ||
| 10617 | @@ -17,5 +17,5 @@ | ||
| 10618 | out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 10619 | } | ||
| 10620 | |||
| 10621 | -/* { dg-final { scan-assembler "vpmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10622 | +/* { dg-final { scan-assembler "vpmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10623 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10624 | |||
| 10625 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c' | ||
| 10626 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 10627 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 10628 | @@ -17,5 +17,5 @@ | ||
| 10629 | out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); | ||
| 10630 | } | ||
| 10631 | |||
| 10632 | -/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10633 | +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10634 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10635 | |||
| 10636 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c' | ||
| 10637 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 10638 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 10639 | @@ -17,5 +17,5 @@ | ||
| 10640 | out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); | ||
| 10641 | } | ||
| 10642 | |||
| 10643 | -/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10644 | +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10645 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10646 | |||
| 10647 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c' | ||
| 10648 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 10649 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 10650 | @@ -17,5 +17,5 @@ | ||
| 10651 | out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t); | ||
| 10652 | } | ||
| 10653 | |||
| 10654 | -/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10655 | +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10656 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10657 | |||
| 10658 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c' | ||
| 10659 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 10660 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 10661 | @@ -17,5 +17,5 @@ | ||
| 10662 | out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t); | ||
| 10663 | } | ||
| 10664 | |||
| 10665 | -/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10666 | +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10667 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10668 | |||
| 10669 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c' | ||
| 10670 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c 2010-07-29 15:38:15 +0000 | ||
| 10671 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c 2010-08-20 13:27:11 +0000 | ||
| 10672 | @@ -17,5 +17,5 @@ | ||
| 10673 | out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 10674 | } | ||
| 10675 | |||
| 10676 | -/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10677 | +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10678 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10679 | |||
| 10680 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c' | ||
| 10681 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c 2010-07-29 15:38:15 +0000 | ||
| 10682 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c 2010-08-20 13:27:11 +0000 | ||
| 10683 | @@ -17,5 +17,5 @@ | ||
| 10684 | out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 10685 | } | ||
| 10686 | |||
| 10687 | -/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10688 | +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10689 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10690 | |||
| 10691 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c' | ||
| 10692 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 10693 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 10694 | @@ -17,5 +17,5 @@ | ||
| 10695 | out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); | ||
| 10696 | } | ||
| 10697 | |||
| 10698 | -/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10699 | +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10700 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10701 | |||
| 10702 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c' | ||
| 10703 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 10704 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 10705 | @@ -17,5 +17,5 @@ | ||
| 10706 | out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); | ||
| 10707 | } | ||
| 10708 | |||
| 10709 | -/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10710 | +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10711 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10712 | |||
| 10713 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c' | ||
| 10714 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 10715 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 10716 | @@ -17,5 +17,5 @@ | ||
| 10717 | out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t); | ||
| 10718 | } | ||
| 10719 | |||
| 10720 | -/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10721 | +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10722 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10723 | |||
| 10724 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c' | ||
| 10725 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 10726 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 10727 | @@ -17,5 +17,5 @@ | ||
| 10728 | out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t); | ||
| 10729 | } | ||
| 10730 | |||
| 10731 | -/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10732 | +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10733 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10734 | |||
| 10735 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c' | ||
| 10736 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c 2010-07-29 15:38:15 +0000 | ||
| 10737 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c 2010-08-20 13:27:11 +0000 | ||
| 10738 | @@ -17,5 +17,5 @@ | ||
| 10739 | out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 10740 | } | ||
| 10741 | |||
| 10742 | -/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10743 | +/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10744 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10745 | |||
| 10746 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c' | ||
| 10747 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c 2010-07-29 15:38:15 +0000 | ||
| 10748 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c 2010-08-20 13:27:11 +0000 | ||
| 10749 | @@ -17,5 +17,5 @@ | ||
| 10750 | out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 10751 | } | ||
| 10752 | |||
| 10753 | -/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10754 | +/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10755 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10756 | |||
| 10757 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c' | ||
| 10758 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c 2010-07-29 15:38:15 +0000 | ||
| 10759 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c 2010-08-20 13:27:11 +0000 | ||
| 10760 | @@ -17,5 +17,5 @@ | ||
| 10761 | out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 10762 | } | ||
| 10763 | |||
| 10764 | -/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10765 | +/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10766 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10767 | |||
| 10768 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c' | ||
| 10769 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c 2010-07-29 15:38:15 +0000 | ||
| 10770 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c 2010-08-20 13:27:11 +0000 | ||
| 10771 | @@ -17,5 +17,5 @@ | ||
| 10772 | out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 10773 | } | ||
| 10774 | |||
| 10775 | -/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10776 | +/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10777 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10778 | |||
| 10779 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c' | ||
| 10780 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c 2010-07-29 15:38:15 +0000 | ||
| 10781 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c 2010-08-20 13:27:11 +0000 | ||
| 10782 | @@ -17,5 +17,5 @@ | ||
| 10783 | out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 10784 | } | ||
| 10785 | |||
| 10786 | -/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10787 | +/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10788 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10789 | |||
| 10790 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c' | ||
| 10791 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c 2010-07-29 15:38:15 +0000 | ||
| 10792 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c 2010-08-20 13:27:11 +0000 | ||
| 10793 | @@ -17,5 +17,5 @@ | ||
| 10794 | out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 10795 | } | ||
| 10796 | |||
| 10797 | -/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10798 | +/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10799 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10800 | |||
| 10801 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c' | ||
| 10802 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c 2010-07-29 15:38:15 +0000 | ||
| 10803 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c 2010-08-20 13:27:11 +0000 | ||
| 10804 | @@ -17,5 +17,5 @@ | ||
| 10805 | out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); | ||
| 10806 | } | ||
| 10807 | |||
| 10808 | -/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10809 | +/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10810 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10811 | |||
| 10812 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c' | ||
| 10813 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c 2010-07-29 15:38:15 +0000 | ||
| 10814 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c 2010-08-20 13:27:11 +0000 | ||
| 10815 | @@ -17,5 +17,5 @@ | ||
| 10816 | out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); | ||
| 10817 | } | ||
| 10818 | |||
| 10819 | -/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10820 | +/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10821 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10822 | |||
| 10823 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c' | ||
| 10824 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c 2010-07-29 15:38:15 +0000 | ||
| 10825 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c 2010-08-20 13:27:11 +0000 | ||
| 10826 | @@ -17,5 +17,5 @@ | ||
| 10827 | out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); | ||
| 10828 | } | ||
| 10829 | |||
| 10830 | -/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10831 | +/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10832 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10833 | |||
| 10834 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c' | ||
| 10835 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c 2010-07-29 15:38:15 +0000 | ||
| 10836 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c 2010-08-20 13:27:11 +0000 | ||
| 10837 | @@ -17,5 +17,5 @@ | ||
| 10838 | out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); | ||
| 10839 | } | ||
| 10840 | |||
| 10841 | -/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10842 | +/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10843 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10844 | |||
| 10845 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls16.c' | ||
| 10846 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c 2010-07-29 15:38:15 +0000 | ||
| 10847 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c 2010-08-20 13:27:11 +0000 | ||
| 10848 | @@ -17,5 +17,5 @@ | ||
| 10849 | out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 10850 | } | ||
| 10851 | |||
| 10852 | -/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10853 | +/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10854 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10855 | |||
| 10856 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls32.c' | ||
| 10857 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c 2010-07-29 15:38:15 +0000 | ||
| 10858 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c 2010-08-20 13:27:11 +0000 | ||
| 10859 | @@ -17,5 +17,5 @@ | ||
| 10860 | out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 10861 | } | ||
| 10862 | |||
| 10863 | -/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10864 | +/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10865 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10866 | |||
| 10867 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls64.c' | ||
| 10868 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c 2010-07-29 15:38:15 +0000 | ||
| 10869 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c 2010-08-20 13:27:11 +0000 | ||
| 10870 | @@ -17,5 +17,5 @@ | ||
| 10871 | out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 10872 | } | ||
| 10873 | |||
| 10874 | -/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10875 | +/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10876 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10877 | |||
| 10878 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshls8.c' | ||
| 10879 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c 2010-07-29 15:38:15 +0000 | ||
| 10880 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c 2010-08-20 13:27:11 +0000 | ||
| 10881 | @@ -17,5 +17,5 @@ | ||
| 10882 | out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 10883 | } | ||
| 10884 | |||
| 10885 | -/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10886 | +/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10887 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10888 | |||
| 10889 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c' | ||
| 10890 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c 2010-07-29 15:38:15 +0000 | ||
| 10891 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c 2010-08-20 13:27:11 +0000 | ||
| 10892 | @@ -17,5 +17,5 @@ | ||
| 10893 | out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); | ||
| 10894 | } | ||
| 10895 | |||
| 10896 | -/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10897 | +/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10898 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10899 | |||
| 10900 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c' | ||
| 10901 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c 2010-07-29 15:38:15 +0000 | ||
| 10902 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c 2010-08-20 13:27:11 +0000 | ||
| 10903 | @@ -17,5 +17,5 @@ | ||
| 10904 | out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); | ||
| 10905 | } | ||
| 10906 | |||
| 10907 | -/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10908 | +/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10909 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10910 | |||
| 10911 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c' | ||
| 10912 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c 2010-07-29 15:38:15 +0000 | ||
| 10913 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c 2010-08-20 13:27:11 +0000 | ||
| 10914 | @@ -17,5 +17,5 @@ | ||
| 10915 | out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); | ||
| 10916 | } | ||
| 10917 | |||
| 10918 | -/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10919 | +/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10920 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10921 | |||
| 10922 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c' | ||
| 10923 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c 2010-07-29 15:38:15 +0000 | ||
| 10924 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c 2010-08-20 13:27:11 +0000 | ||
| 10925 | @@ -17,5 +17,5 @@ | ||
| 10926 | out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); | ||
| 10927 | } | ||
| 10928 | |||
| 10929 | -/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10930 | +/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10931 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10932 | |||
| 10933 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c' | ||
| 10934 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 10935 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 10936 | @@ -16,5 +16,5 @@ | ||
| 10937 | out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1); | ||
| 10938 | } | ||
| 10939 | |||
| 10940 | -/* { dg-final { scan-assembler "vqrshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10941 | +/* { dg-final { scan-assembler "vqrshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10942 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10943 | |||
| 10944 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c' | ||
| 10945 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 10946 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 10947 | @@ -16,5 +16,5 @@ | ||
| 10948 | out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1); | ||
| 10949 | } | ||
| 10950 | |||
| 10951 | -/* { dg-final { scan-assembler "vqrshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10952 | +/* { dg-final { scan-assembler "vqrshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10953 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10954 | |||
| 10955 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c' | ||
| 10956 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 10957 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 10958 | @@ -16,5 +16,5 @@ | ||
| 10959 | out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1); | ||
| 10960 | } | ||
| 10961 | |||
| 10962 | -/* { dg-final { scan-assembler "vqrshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10963 | +/* { dg-final { scan-assembler "vqrshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10964 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10965 | |||
| 10966 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c' | ||
| 10967 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 10968 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 10969 | @@ -16,5 +16,5 @@ | ||
| 10970 | out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1); | ||
| 10971 | } | ||
| 10972 | |||
| 10973 | -/* { dg-final { scan-assembler "vqrshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10974 | +/* { dg-final { scan-assembler "vqrshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10975 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10976 | |||
| 10977 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c' | ||
| 10978 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 10979 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 10980 | @@ -16,5 +16,5 @@ | ||
| 10981 | out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1); | ||
| 10982 | } | ||
| 10983 | |||
| 10984 | -/* { dg-final { scan-assembler "vqrshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10985 | +/* { dg-final { scan-assembler "vqrshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10986 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10987 | |||
| 10988 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c' | ||
| 10989 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 10990 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 10991 | @@ -16,5 +16,5 @@ | ||
| 10992 | out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1); | ||
| 10993 | } | ||
| 10994 | |||
| 10995 | -/* { dg-final { scan-assembler "vqrshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 10996 | +/* { dg-final { scan-assembler "vqrshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 10997 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 10998 | |||
| 10999 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c' | ||
| 11000 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 11001 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 11002 | @@ -16,5 +16,5 @@ | ||
| 11003 | out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1); | ||
| 11004 | } | ||
| 11005 | |||
| 11006 | -/* { dg-final { scan-assembler "vqrshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11007 | +/* { dg-final { scan-assembler "vqrshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11008 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11009 | |||
| 11010 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c' | ||
| 11011 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 11012 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 11013 | @@ -16,5 +16,5 @@ | ||
| 11014 | out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1); | ||
| 11015 | } | ||
| 11016 | |||
| 11017 | -/* { dg-final { scan-assembler "vqrshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11018 | +/* { dg-final { scan-assembler "vqrshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11019 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11020 | |||
| 11021 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c' | ||
| 11022 | --- old/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 11023 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 11024 | @@ -16,5 +16,5 @@ | ||
| 11025 | out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1); | ||
| 11026 | } | ||
| 11027 | |||
| 11028 | -/* { dg-final { scan-assembler "vqrshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11029 | +/* { dg-final { scan-assembler "vqrshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11030 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11031 | |||
| 11032 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c' | ||
| 11033 | --- old/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c 2010-07-29 15:38:15 +0000 | ||
| 11034 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c 2010-08-20 13:27:11 +0000 | ||
| 11035 | @@ -16,5 +16,5 @@ | ||
| 11036 | out_int16x8_t = vqabsq_s16 (arg0_int16x8_t); | ||
| 11037 | } | ||
| 11038 | |||
| 11039 | -/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11040 | +/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11041 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11042 | |||
| 11043 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c' | ||
| 11044 | --- old/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c 2010-07-29 15:38:15 +0000 | ||
| 11045 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c 2010-08-20 13:27:11 +0000 | ||
| 11046 | @@ -16,5 +16,5 @@ | ||
| 11047 | out_int32x4_t = vqabsq_s32 (arg0_int32x4_t); | ||
| 11048 | } | ||
| 11049 | |||
| 11050 | -/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11051 | +/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11052 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11053 | |||
| 11054 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c' | ||
| 11055 | --- old/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c 2010-07-29 15:38:15 +0000 | ||
| 11056 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c 2010-08-20 13:27:11 +0000 | ||
| 11057 | @@ -16,5 +16,5 @@ | ||
| 11058 | out_int8x16_t = vqabsq_s8 (arg0_int8x16_t); | ||
| 11059 | } | ||
| 11060 | |||
| 11061 | -/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11062 | +/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11063 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11064 | |||
| 11065 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqabss16.c' | ||
| 11066 | --- old/gcc/testsuite/gcc.target/arm/neon/vqabss16.c 2010-07-29 15:38:15 +0000 | ||
| 11067 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqabss16.c 2010-08-20 13:27:11 +0000 | ||
| 11068 | @@ -16,5 +16,5 @@ | ||
| 11069 | out_int16x4_t = vqabs_s16 (arg0_int16x4_t); | ||
| 11070 | } | ||
| 11071 | |||
| 11072 | -/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11073 | +/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11074 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11075 | |||
| 11076 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqabss32.c' | ||
| 11077 | --- old/gcc/testsuite/gcc.target/arm/neon/vqabss32.c 2010-07-29 15:38:15 +0000 | ||
| 11078 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqabss32.c 2010-08-20 13:27:11 +0000 | ||
| 11079 | @@ -16,5 +16,5 @@ | ||
| 11080 | out_int32x2_t = vqabs_s32 (arg0_int32x2_t); | ||
| 11081 | } | ||
| 11082 | |||
| 11083 | -/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11084 | +/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11085 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11086 | |||
| 11087 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqabss8.c' | ||
| 11088 | --- old/gcc/testsuite/gcc.target/arm/neon/vqabss8.c 2010-07-29 15:38:15 +0000 | ||
| 11089 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqabss8.c 2010-08-20 13:27:11 +0000 | ||
| 11090 | @@ -16,5 +16,5 @@ | ||
| 11091 | out_int8x8_t = vqabs_s8 (arg0_int8x8_t); | ||
| 11092 | } | ||
| 11093 | |||
| 11094 | -/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11095 | +/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11096 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11097 | |||
| 11098 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c' | ||
| 11099 | --- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c 2010-07-29 15:38:15 +0000 | ||
| 11100 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c 2010-08-20 13:27:11 +0000 | ||
| 11101 | @@ -17,5 +17,5 @@ | ||
| 11102 | out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 11103 | } | ||
| 11104 | |||
| 11105 | -/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11106 | +/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11107 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11108 | |||
| 11109 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c' | ||
| 11110 | --- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c 2010-07-29 15:38:15 +0000 | ||
| 11111 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c 2010-08-20 13:27:11 +0000 | ||
| 11112 | @@ -17,5 +17,5 @@ | ||
| 11113 | out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 11114 | } | ||
| 11115 | |||
| 11116 | -/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11117 | +/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11118 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11119 | |||
| 11120 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c' | ||
| 11121 | --- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c 2010-07-29 15:38:15 +0000 | ||
| 11122 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c 2010-08-20 13:27:11 +0000 | ||
| 11123 | @@ -17,5 +17,5 @@ | ||
| 11124 | out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 11125 | } | ||
| 11126 | |||
| 11127 | -/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11128 | +/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11129 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11130 | |||
| 11131 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c' | ||
| 11132 | --- old/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c 2010-07-29 15:38:15 +0000 | ||
| 11133 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c 2010-08-20 13:27:11 +0000 | ||
| 11134 | @@ -17,5 +17,5 @@ | ||
| 11135 | out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 11136 | } | ||
| 11137 | |||
| 11138 | -/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11139 | +/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11140 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11141 | |||
| 11142 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c' | ||
| 11143 | --- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c 2010-07-29 15:38:15 +0000 | ||
| 11144 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c 2010-08-20 13:27:11 +0000 | ||
| 11145 | @@ -17,5 +17,5 @@ | ||
| 11146 | out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 11147 | } | ||
| 11148 | |||
| 11149 | -/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11150 | +/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11151 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11152 | |||
| 11153 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c' | ||
| 11154 | --- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c 2010-07-29 15:38:15 +0000 | ||
| 11155 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c 2010-08-20 13:27:11 +0000 | ||
| 11156 | @@ -17,5 +17,5 @@ | ||
| 11157 | out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 11158 | } | ||
| 11159 | |||
| 11160 | -/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11161 | +/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11162 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11163 | |||
| 11164 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c' | ||
| 11165 | --- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c 2010-07-29 15:38:15 +0000 | ||
| 11166 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c 2010-08-20 13:27:11 +0000 | ||
| 11167 | @@ -17,5 +17,5 @@ | ||
| 11168 | out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 11169 | } | ||
| 11170 | |||
| 11171 | -/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11172 | +/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11173 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11174 | |||
| 11175 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c' | ||
| 11176 | --- old/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c 2010-07-29 15:38:15 +0000 | ||
| 11177 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c 2010-08-20 13:27:11 +0000 | ||
| 11178 | @@ -17,5 +17,5 @@ | ||
| 11179 | out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 11180 | } | ||
| 11181 | |||
| 11182 | -/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11183 | +/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11184 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11185 | |||
| 11186 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds16.c' | ||
| 11187 | --- old/gcc/testsuite/gcc.target/arm/neon/vqadds16.c 2010-07-29 15:38:15 +0000 | ||
| 11188 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqadds16.c 2010-08-20 13:27:11 +0000 | ||
| 11189 | @@ -17,5 +17,5 @@ | ||
| 11190 | out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 11191 | } | ||
| 11192 | |||
| 11193 | -/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11194 | +/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11195 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11196 | |||
| 11197 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds32.c' | ||
| 11198 | --- old/gcc/testsuite/gcc.target/arm/neon/vqadds32.c 2010-07-29 15:38:15 +0000 | ||
| 11199 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqadds32.c 2010-08-20 13:27:11 +0000 | ||
| 11200 | @@ -17,5 +17,5 @@ | ||
| 11201 | out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 11202 | } | ||
| 11203 | |||
| 11204 | -/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11205 | +/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11206 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11207 | |||
| 11208 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds64.c' | ||
| 11209 | --- old/gcc/testsuite/gcc.target/arm/neon/vqadds64.c 2010-07-29 15:38:15 +0000 | ||
| 11210 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqadds64.c 2010-08-20 13:27:11 +0000 | ||
| 11211 | @@ -17,5 +17,5 @@ | ||
| 11212 | out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 11213 | } | ||
| 11214 | |||
| 11215 | -/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11216 | +/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11217 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11218 | |||
| 11219 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqadds8.c' | ||
| 11220 | --- old/gcc/testsuite/gcc.target/arm/neon/vqadds8.c 2010-07-29 15:38:15 +0000 | ||
| 11221 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqadds8.c 2010-08-20 13:27:11 +0000 | ||
| 11222 | @@ -17,5 +17,5 @@ | ||
| 11223 | out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 11224 | } | ||
| 11225 | |||
| 11226 | -/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11227 | +/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11228 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11229 | |||
| 11230 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu16.c' | ||
| 11231 | --- old/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c 2010-07-29 15:38:15 +0000 | ||
| 11232 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c 2010-08-20 13:27:11 +0000 | ||
| 11233 | @@ -17,5 +17,5 @@ | ||
| 11234 | out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 11235 | } | ||
| 11236 | |||
| 11237 | -/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11238 | +/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11239 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11240 | |||
| 11241 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu32.c' | ||
| 11242 | --- old/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c 2010-07-29 15:38:15 +0000 | ||
| 11243 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c 2010-08-20 13:27:11 +0000 | ||
| 11244 | @@ -17,5 +17,5 @@ | ||
| 11245 | out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 11246 | } | ||
| 11247 | |||
| 11248 | -/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11249 | +/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11250 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11251 | |||
| 11252 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu64.c' | ||
| 11253 | --- old/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c 2010-07-29 15:38:15 +0000 | ||
| 11254 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c 2010-08-20 13:27:11 +0000 | ||
| 11255 | @@ -17,5 +17,5 @@ | ||
| 11256 | out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 11257 | } | ||
| 11258 | |||
| 11259 | -/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11260 | +/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11261 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11262 | |||
| 11263 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqaddu8.c' | ||
| 11264 | --- old/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c 2010-07-29 15:38:15 +0000 | ||
| 11265 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c 2010-08-20 13:27:11 +0000 | ||
| 11266 | @@ -17,5 +17,5 @@ | ||
| 11267 | out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 11268 | } | ||
| 11269 | |||
| 11270 | -/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11271 | +/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11272 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11273 | |||
| 11274 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c' | ||
| 11275 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 11276 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 11277 | @@ -18,5 +18,5 @@ | ||
| 11278 | out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); | ||
| 11279 | } | ||
| 11280 | |||
| 11281 | -/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11282 | +/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11283 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11284 | |||
| 11285 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c' | ||
| 11286 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 11287 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 11288 | @@ -18,5 +18,5 @@ | ||
| 11289 | out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); | ||
| 11290 | } | ||
| 11291 | |||
| 11292 | -/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11293 | +/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11294 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11295 | |||
| 11296 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c' | ||
| 11297 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 11298 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 11299 | @@ -18,5 +18,5 @@ | ||
| 11300 | out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); | ||
| 11301 | } | ||
| 11302 | |||
| 11303 | -/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11304 | +/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11305 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11306 | |||
| 11307 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c' | ||
| 11308 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 11309 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 11310 | @@ -18,5 +18,5 @@ | ||
| 11311 | out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); | ||
| 11312 | } | ||
| 11313 | |||
| 11314 | -/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11315 | +/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11316 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11317 | |||
| 11318 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c' | ||
| 11319 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c 2010-07-29 15:38:15 +0000 | ||
| 11320 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c 2010-08-20 13:27:11 +0000 | ||
| 11321 | @@ -18,5 +18,5 @@ | ||
| 11322 | out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); | ||
| 11323 | } | ||
| 11324 | |||
| 11325 | -/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11326 | +/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11327 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11328 | |||
| 11329 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c' | ||
| 11330 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c 2010-07-29 15:38:15 +0000 | ||
| 11331 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c 2010-08-20 13:27:11 +0000 | ||
| 11332 | @@ -18,5 +18,5 @@ | ||
| 11333 | out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); | ||
| 11334 | } | ||
| 11335 | |||
| 11336 | -/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11337 | +/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11338 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11339 | |||
| 11340 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c' | ||
| 11341 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 11342 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 11343 | @@ -18,5 +18,5 @@ | ||
| 11344 | out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1); | ||
| 11345 | } | ||
| 11346 | |||
| 11347 | -/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11348 | +/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11349 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11350 | |||
| 11351 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c' | ||
| 11352 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 11353 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 11354 | @@ -18,5 +18,5 @@ | ||
| 11355 | out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1); | ||
| 11356 | } | ||
| 11357 | |||
| 11358 | -/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11359 | +/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11360 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11361 | |||
| 11362 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c' | ||
| 11363 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 11364 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 11365 | @@ -18,5 +18,5 @@ | ||
| 11366 | out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t); | ||
| 11367 | } | ||
| 11368 | |||
| 11369 | -/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11370 | +/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11371 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11372 | |||
| 11373 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c' | ||
| 11374 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 11375 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 11376 | @@ -18,5 +18,5 @@ | ||
| 11377 | out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t); | ||
| 11378 | } | ||
| 11379 | |||
| 11380 | -/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11381 | +/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11382 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11383 | |||
| 11384 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c' | ||
| 11385 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c 2010-07-29 15:38:15 +0000 | ||
| 11386 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c 2010-08-20 13:27:11 +0000 | ||
| 11387 | @@ -18,5 +18,5 @@ | ||
| 11388 | out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t); | ||
| 11389 | } | ||
| 11390 | |||
| 11391 | -/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11392 | +/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11393 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11394 | |||
| 11395 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c' | ||
| 11396 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c 2010-07-29 15:38:15 +0000 | ||
| 11397 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c 2010-08-20 13:27:11 +0000 | ||
| 11398 | @@ -18,5 +18,5 @@ | ||
| 11399 | out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t); | ||
| 11400 | } | ||
| 11401 | |||
| 11402 | -/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11403 | +/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11404 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11405 | |||
| 11406 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c' | ||
| 11407 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 11408 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 11409 | @@ -17,5 +17,5 @@ | ||
| 11410 | out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1); | ||
| 11411 | } | ||
| 11412 | |||
| 11413 | -/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11414 | +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11415 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11416 | |||
| 11417 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c' | ||
| 11418 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 11419 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 11420 | @@ -17,5 +17,5 @@ | ||
| 11421 | out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1); | ||
| 11422 | } | ||
| 11423 | |||
| 11424 | -/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11425 | +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11426 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11427 | |||
| 11428 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c' | ||
| 11429 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 11430 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 11431 | @@ -17,5 +17,5 @@ | ||
| 11432 | out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t); | ||
| 11433 | } | ||
| 11434 | |||
| 11435 | -/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11436 | +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11437 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11438 | |||
| 11439 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c' | ||
| 11440 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 11441 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 11442 | @@ -17,5 +17,5 @@ | ||
| 11443 | out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t); | ||
| 11444 | } | ||
| 11445 | |||
| 11446 | -/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11447 | +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11448 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11449 | |||
| 11450 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c' | ||
| 11451 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c 2010-07-29 15:38:15 +0000 | ||
| 11452 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c 2010-08-20 13:27:11 +0000 | ||
| 11453 | @@ -17,5 +17,5 @@ | ||
| 11454 | out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 11455 | } | ||
| 11456 | |||
| 11457 | -/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11458 | +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11459 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11460 | |||
| 11461 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c' | ||
| 11462 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c 2010-07-29 15:38:15 +0000 | ||
| 11463 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c 2010-08-20 13:27:11 +0000 | ||
| 11464 | @@ -17,5 +17,5 @@ | ||
| 11465 | out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 11466 | } | ||
| 11467 | |||
| 11468 | -/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11469 | +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11470 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11471 | |||
| 11472 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c' | ||
| 11473 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 11474 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 11475 | @@ -17,5 +17,5 @@ | ||
| 11476 | out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); | ||
| 11477 | } | ||
| 11478 | |||
| 11479 | -/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11480 | +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11481 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11482 | |||
| 11483 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c' | ||
| 11484 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 11485 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 11486 | @@ -17,5 +17,5 @@ | ||
| 11487 | out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); | ||
| 11488 | } | ||
| 11489 | |||
| 11490 | -/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11491 | +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11492 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11493 | |||
| 11494 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c' | ||
| 11495 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 11496 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 11497 | @@ -17,5 +17,5 @@ | ||
| 11498 | out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t); | ||
| 11499 | } | ||
| 11500 | |||
| 11501 | -/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11502 | +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11503 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11504 | |||
| 11505 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c' | ||
| 11506 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 11507 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 11508 | @@ -17,5 +17,5 @@ | ||
| 11509 | out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t); | ||
| 11510 | } | ||
| 11511 | |||
| 11512 | -/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11513 | +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11514 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11515 | |||
| 11516 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c' | ||
| 11517 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c 2010-07-29 15:38:15 +0000 | ||
| 11518 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c 2010-08-20 13:27:11 +0000 | ||
| 11519 | @@ -17,5 +17,5 @@ | ||
| 11520 | out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 11521 | } | ||
| 11522 | |||
| 11523 | -/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11524 | +/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11525 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11526 | |||
| 11527 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c' | ||
| 11528 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c 2010-07-29 15:38:15 +0000 | ||
| 11529 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c 2010-08-20 13:27:11 +0000 | ||
| 11530 | @@ -17,5 +17,5 @@ | ||
| 11531 | out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 11532 | } | ||
| 11533 | |||
| 11534 | -/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11535 | +/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11536 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11537 | |||
| 11538 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c' | ||
| 11539 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 11540 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 11541 | @@ -17,5 +17,5 @@ | ||
| 11542 | out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); | ||
| 11543 | } | ||
| 11544 | |||
| 11545 | -/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11546 | +/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11547 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11548 | |||
| 11549 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c' | ||
| 11550 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 11551 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 11552 | @@ -17,5 +17,5 @@ | ||
| 11553 | out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); | ||
| 11554 | } | ||
| 11555 | |||
| 11556 | -/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11557 | +/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11558 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11559 | |||
| 11560 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c' | ||
| 11561 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 11562 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 11563 | @@ -17,5 +17,5 @@ | ||
| 11564 | out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t); | ||
| 11565 | } | ||
| 11566 | |||
| 11567 | -/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11568 | +/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11569 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11570 | |||
| 11571 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c' | ||
| 11572 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 11573 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 11574 | @@ -17,5 +17,5 @@ | ||
| 11575 | out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t); | ||
| 11576 | } | ||
| 11577 | |||
| 11578 | -/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11579 | +/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11580 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11581 | |||
| 11582 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c' | ||
| 11583 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c 2010-07-29 15:38:15 +0000 | ||
| 11584 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c 2010-08-20 13:27:11 +0000 | ||
| 11585 | @@ -17,5 +17,5 @@ | ||
| 11586 | out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 11587 | } | ||
| 11588 | |||
| 11589 | -/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11590 | +/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11591 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11592 | |||
| 11593 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c' | ||
| 11594 | --- old/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c 2010-07-29 15:38:15 +0000 | ||
| 11595 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c 2010-08-20 13:27:11 +0000 | ||
| 11596 | @@ -17,5 +17,5 @@ | ||
| 11597 | out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 11598 | } | ||
| 11599 | |||
| 11600 | -/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11601 | +/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11602 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11603 | |||
| 11604 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovns16.c' | ||
| 11605 | --- old/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c 2010-07-29 15:38:15 +0000 | ||
| 11606 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c 2010-08-20 13:27:11 +0000 | ||
| 11607 | @@ -16,5 +16,5 @@ | ||
| 11608 | out_int8x8_t = vqmovn_s16 (arg0_int16x8_t); | ||
| 11609 | } | ||
| 11610 | |||
| 11611 | -/* { dg-final { scan-assembler "vqmovn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11612 | +/* { dg-final { scan-assembler "vqmovn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11613 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11614 | |||
| 11615 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovns32.c' | ||
| 11616 | --- old/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c 2010-07-29 15:38:15 +0000 | ||
| 11617 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c 2010-08-20 13:27:11 +0000 | ||
| 11618 | @@ -16,5 +16,5 @@ | ||
| 11619 | out_int16x4_t = vqmovn_s32 (arg0_int32x4_t); | ||
| 11620 | } | ||
| 11621 | |||
| 11622 | -/* { dg-final { scan-assembler "vqmovn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11623 | +/* { dg-final { scan-assembler "vqmovn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11624 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11625 | |||
| 11626 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovns64.c' | ||
| 11627 | --- old/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c 2010-07-29 15:38:15 +0000 | ||
| 11628 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c 2010-08-20 13:27:11 +0000 | ||
| 11629 | @@ -16,5 +16,5 @@ | ||
| 11630 | out_int32x2_t = vqmovn_s64 (arg0_int64x2_t); | ||
| 11631 | } | ||
| 11632 | |||
| 11633 | -/* { dg-final { scan-assembler "vqmovn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11634 | +/* { dg-final { scan-assembler "vqmovn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11635 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11636 | |||
| 11637 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c' | ||
| 11638 | --- old/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c 2010-07-29 15:38:15 +0000 | ||
| 11639 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c 2010-08-20 13:27:11 +0000 | ||
| 11640 | @@ -16,5 +16,5 @@ | ||
| 11641 | out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t); | ||
| 11642 | } | ||
| 11643 | |||
| 11644 | -/* { dg-final { scan-assembler "vqmovn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11645 | +/* { dg-final { scan-assembler "vqmovn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11646 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11647 | |||
| 11648 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c' | ||
| 11649 | --- old/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c 2010-07-29 15:38:15 +0000 | ||
| 11650 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c 2010-08-20 13:27:11 +0000 | ||
| 11651 | @@ -16,5 +16,5 @@ | ||
| 11652 | out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t); | ||
| 11653 | } | ||
| 11654 | |||
| 11655 | -/* { dg-final { scan-assembler "vqmovn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11656 | +/* { dg-final { scan-assembler "vqmovn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11657 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11658 | |||
| 11659 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c' | ||
| 11660 | --- old/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c 2010-07-29 15:38:15 +0000 | ||
| 11661 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c 2010-08-20 13:27:11 +0000 | ||
| 11662 | @@ -16,5 +16,5 @@ | ||
| 11663 | out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t); | ||
| 11664 | } | ||
| 11665 | |||
| 11666 | -/* { dg-final { scan-assembler "vqmovn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11667 | +/* { dg-final { scan-assembler "vqmovn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11668 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11669 | |||
| 11670 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c' | ||
| 11671 | --- old/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c 2010-07-29 15:38:15 +0000 | ||
| 11672 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c 2010-08-20 13:27:11 +0000 | ||
| 11673 | @@ -16,5 +16,5 @@ | ||
| 11674 | out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t); | ||
| 11675 | } | ||
| 11676 | |||
| 11677 | -/* { dg-final { scan-assembler "vqmovun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11678 | +/* { dg-final { scan-assembler "vqmovun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11679 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11680 | |||
| 11681 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c' | ||
| 11682 | --- old/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c 2010-07-29 15:38:15 +0000 | ||
| 11683 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c 2010-08-20 13:27:11 +0000 | ||
| 11684 | @@ -16,5 +16,5 @@ | ||
| 11685 | out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t); | ||
| 11686 | } | ||
| 11687 | |||
| 11688 | -/* { dg-final { scan-assembler "vqmovun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11689 | +/* { dg-final { scan-assembler "vqmovun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11690 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11691 | |||
| 11692 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c' | ||
| 11693 | --- old/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c 2010-07-29 15:38:15 +0000 | ||
| 11694 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c 2010-08-20 13:27:11 +0000 | ||
| 11695 | @@ -16,5 +16,5 @@ | ||
| 11696 | out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t); | ||
| 11697 | } | ||
| 11698 | |||
| 11699 | -/* { dg-final { scan-assembler "vqmovun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11700 | +/* { dg-final { scan-assembler "vqmovun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11701 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11702 | |||
| 11703 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c' | ||
| 11704 | --- old/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c 2010-07-29 15:38:15 +0000 | ||
| 11705 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c 2010-08-20 13:27:11 +0000 | ||
| 11706 | @@ -16,5 +16,5 @@ | ||
| 11707 | out_int16x8_t = vqnegq_s16 (arg0_int16x8_t); | ||
| 11708 | } | ||
| 11709 | |||
| 11710 | -/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11711 | +/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11712 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11713 | |||
| 11714 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c' | ||
| 11715 | --- old/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c 2010-07-29 15:38:15 +0000 | ||
| 11716 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c 2010-08-20 13:27:11 +0000 | ||
| 11717 | @@ -16,5 +16,5 @@ | ||
| 11718 | out_int32x4_t = vqnegq_s32 (arg0_int32x4_t); | ||
| 11719 | } | ||
| 11720 | |||
| 11721 | -/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11722 | +/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11723 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11724 | |||
| 11725 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c' | ||
| 11726 | --- old/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c 2010-07-29 15:38:15 +0000 | ||
| 11727 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c 2010-08-20 13:27:11 +0000 | ||
| 11728 | @@ -16,5 +16,5 @@ | ||
| 11729 | out_int8x16_t = vqnegq_s8 (arg0_int8x16_t); | ||
| 11730 | } | ||
| 11731 | |||
| 11732 | -/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11733 | +/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11734 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11735 | |||
| 11736 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegs16.c' | ||
| 11737 | --- old/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c 2010-07-29 15:38:15 +0000 | ||
| 11738 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c 2010-08-20 13:27:11 +0000 | ||
| 11739 | @@ -16,5 +16,5 @@ | ||
| 11740 | out_int16x4_t = vqneg_s16 (arg0_int16x4_t); | ||
| 11741 | } | ||
| 11742 | |||
| 11743 | -/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11744 | +/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11745 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11746 | |||
| 11747 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegs32.c' | ||
| 11748 | --- old/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c 2010-07-29 15:38:15 +0000 | ||
| 11749 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c 2010-08-20 13:27:11 +0000 | ||
| 11750 | @@ -16,5 +16,5 @@ | ||
| 11751 | out_int32x2_t = vqneg_s32 (arg0_int32x2_t); | ||
| 11752 | } | ||
| 11753 | |||
| 11754 | -/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11755 | +/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11756 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11757 | |||
| 11758 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqnegs8.c' | ||
| 11759 | --- old/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c 2010-07-29 15:38:15 +0000 | ||
| 11760 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c 2010-08-20 13:27:11 +0000 | ||
| 11761 | @@ -16,5 +16,5 @@ | ||
| 11762 | out_int8x8_t = vqneg_s8 (arg0_int8x8_t); | ||
| 11763 | } | ||
| 11764 | |||
| 11765 | -/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11766 | +/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11767 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11768 | |||
| 11769 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c' | ||
| 11770 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 11771 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 11772 | @@ -16,5 +16,5 @@ | ||
| 11773 | out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1); | ||
| 11774 | } | ||
| 11775 | |||
| 11776 | -/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11777 | +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11778 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11779 | |||
| 11780 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c' | ||
| 11781 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 11782 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 11783 | @@ -16,5 +16,5 @@ | ||
| 11784 | out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1); | ||
| 11785 | } | ||
| 11786 | |||
| 11787 | -/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11788 | +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11789 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11790 | |||
| 11791 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c' | ||
| 11792 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 11793 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 11794 | @@ -16,5 +16,5 @@ | ||
| 11795 | out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1); | ||
| 11796 | } | ||
| 11797 | |||
| 11798 | -/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11799 | +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11800 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11801 | |||
| 11802 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c' | ||
| 11803 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 11804 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 11805 | @@ -16,5 +16,5 @@ | ||
| 11806 | out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1); | ||
| 11807 | } | ||
| 11808 | |||
| 11809 | -/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11810 | +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11811 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11812 | |||
| 11813 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c' | ||
| 11814 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 11815 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 11816 | @@ -16,5 +16,5 @@ | ||
| 11817 | out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1); | ||
| 11818 | } | ||
| 11819 | |||
| 11820 | -/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11821 | +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11822 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11823 | |||
| 11824 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c' | ||
| 11825 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 11826 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 11827 | @@ -16,5 +16,5 @@ | ||
| 11828 | out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1); | ||
| 11829 | } | ||
| 11830 | |||
| 11831 | -/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11832 | +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11833 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11834 | |||
| 11835 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c' | ||
| 11836 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 11837 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 11838 | @@ -16,5 +16,5 @@ | ||
| 11839 | out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1); | ||
| 11840 | } | ||
| 11841 | |||
| 11842 | -/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11843 | +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11844 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11845 | |||
| 11846 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c' | ||
| 11847 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 11848 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 11849 | @@ -16,5 +16,5 @@ | ||
| 11850 | out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1); | ||
| 11851 | } | ||
| 11852 | |||
| 11853 | -/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11854 | +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11855 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11856 | |||
| 11857 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c' | ||
| 11858 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c 2010-07-29 15:38:15 +0000 | ||
| 11859 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c 2010-08-20 13:27:11 +0000 | ||
| 11860 | @@ -17,5 +17,5 @@ | ||
| 11861 | out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 11862 | } | ||
| 11863 | |||
| 11864 | -/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11865 | +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11866 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11867 | |||
| 11868 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c' | ||
| 11869 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c 2010-07-29 15:38:15 +0000 | ||
| 11870 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c 2010-08-20 13:27:11 +0000 | ||
| 11871 | @@ -17,5 +17,5 @@ | ||
| 11872 | out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 11873 | } | ||
| 11874 | |||
| 11875 | -/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11876 | +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11877 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11878 | |||
| 11879 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c' | ||
| 11880 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c 2010-07-29 15:38:15 +0000 | ||
| 11881 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c 2010-08-20 13:27:11 +0000 | ||
| 11882 | @@ -17,5 +17,5 @@ | ||
| 11883 | out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 11884 | } | ||
| 11885 | |||
| 11886 | -/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11887 | +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11888 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11889 | |||
| 11890 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c' | ||
| 11891 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c 2010-07-29 15:38:15 +0000 | ||
| 11892 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c 2010-08-20 13:27:11 +0000 | ||
| 11893 | @@ -17,5 +17,5 @@ | ||
| 11894 | out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 11895 | } | ||
| 11896 | |||
| 11897 | -/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11898 | +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11899 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11900 | |||
| 11901 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c' | ||
| 11902 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c 2010-07-29 15:38:15 +0000 | ||
| 11903 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c 2010-08-20 13:27:11 +0000 | ||
| 11904 | @@ -17,5 +17,5 @@ | ||
| 11905 | out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); | ||
| 11906 | } | ||
| 11907 | |||
| 11908 | -/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11909 | +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11910 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11911 | |||
| 11912 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c' | ||
| 11913 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c 2010-07-29 15:38:15 +0000 | ||
| 11914 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c 2010-08-20 13:27:11 +0000 | ||
| 11915 | @@ -17,5 +17,5 @@ | ||
| 11916 | out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); | ||
| 11917 | } | ||
| 11918 | |||
| 11919 | -/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11920 | +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11921 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11922 | |||
| 11923 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c' | ||
| 11924 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c 2010-07-29 15:38:15 +0000 | ||
| 11925 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c 2010-08-20 13:27:11 +0000 | ||
| 11926 | @@ -17,5 +17,5 @@ | ||
| 11927 | out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); | ||
| 11928 | } | ||
| 11929 | |||
| 11930 | -/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11931 | +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11932 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11933 | |||
| 11934 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c' | ||
| 11935 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c 2010-07-29 15:38:15 +0000 | ||
| 11936 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c 2010-08-20 13:27:11 +0000 | ||
| 11937 | @@ -17,5 +17,5 @@ | ||
| 11938 | out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); | ||
| 11939 | } | ||
| 11940 | |||
| 11941 | -/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11942 | +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11943 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11944 | |||
| 11945 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c' | ||
| 11946 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 11947 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 11948 | @@ -16,5 +16,5 @@ | ||
| 11949 | out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1); | ||
| 11950 | } | ||
| 11951 | |||
| 11952 | -/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11953 | +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11954 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11955 | |||
| 11956 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c' | ||
| 11957 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 11958 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 11959 | @@ -16,5 +16,5 @@ | ||
| 11960 | out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1); | ||
| 11961 | } | ||
| 11962 | |||
| 11963 | -/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11964 | +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11965 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11966 | |||
| 11967 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c' | ||
| 11968 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 11969 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 11970 | @@ -16,5 +16,5 @@ | ||
| 11971 | out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1); | ||
| 11972 | } | ||
| 11973 | |||
| 11974 | -/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11975 | +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11976 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11977 | |||
| 11978 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c' | ||
| 11979 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 11980 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 11981 | @@ -16,5 +16,5 @@ | ||
| 11982 | out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1); | ||
| 11983 | } | ||
| 11984 | |||
| 11985 | -/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11986 | +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11987 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11988 | |||
| 11989 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c' | ||
| 11990 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 11991 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 11992 | @@ -16,5 +16,5 @@ | ||
| 11993 | out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1); | ||
| 11994 | } | ||
| 11995 | |||
| 11996 | -/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 11997 | +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 11998 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 11999 | |||
| 12000 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c' | ||
| 12001 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 12002 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 12003 | @@ -16,5 +16,5 @@ | ||
| 12004 | out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1); | ||
| 12005 | } | ||
| 12006 | |||
| 12007 | -/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12008 | +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12009 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12010 | |||
| 12011 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c' | ||
| 12012 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 12013 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 12014 | @@ -16,5 +16,5 @@ | ||
| 12015 | out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1); | ||
| 12016 | } | ||
| 12017 | |||
| 12018 | -/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12019 | +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12020 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12021 | |||
| 12022 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c' | ||
| 12023 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 12024 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 12025 | @@ -16,5 +16,5 @@ | ||
| 12026 | out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1); | ||
| 12027 | } | ||
| 12028 | |||
| 12029 | -/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12030 | +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12031 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12032 | |||
| 12033 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls16.c' | ||
| 12034 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshls16.c 2010-07-29 15:38:15 +0000 | ||
| 12035 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshls16.c 2010-08-20 13:27:11 +0000 | ||
| 12036 | @@ -17,5 +17,5 @@ | ||
| 12037 | out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 12038 | } | ||
| 12039 | |||
| 12040 | -/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12041 | +/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12042 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12043 | |||
| 12044 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls32.c' | ||
| 12045 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshls32.c 2010-07-29 15:38:15 +0000 | ||
| 12046 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshls32.c 2010-08-20 13:27:11 +0000 | ||
| 12047 | @@ -17,5 +17,5 @@ | ||
| 12048 | out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 12049 | } | ||
| 12050 | |||
| 12051 | -/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12052 | +/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12053 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12054 | |||
| 12055 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls64.c' | ||
| 12056 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshls64.c 2010-07-29 15:38:15 +0000 | ||
| 12057 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshls64.c 2010-08-20 13:27:11 +0000 | ||
| 12058 | @@ -17,5 +17,5 @@ | ||
| 12059 | out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 12060 | } | ||
| 12061 | |||
| 12062 | -/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12063 | +/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12064 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12065 | |||
| 12066 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshls8.c' | ||
| 12067 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshls8.c 2010-07-29 15:38:15 +0000 | ||
| 12068 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshls8.c 2010-08-20 13:27:11 +0000 | ||
| 12069 | @@ -17,5 +17,5 @@ | ||
| 12070 | out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 12071 | } | ||
| 12072 | |||
| 12073 | -/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12074 | +/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12075 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12076 | |||
| 12077 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu16.c' | ||
| 12078 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c 2010-07-29 15:38:15 +0000 | ||
| 12079 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c 2010-08-20 13:27:11 +0000 | ||
| 12080 | @@ -17,5 +17,5 @@ | ||
| 12081 | out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); | ||
| 12082 | } | ||
| 12083 | |||
| 12084 | -/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12085 | +/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12086 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12087 | |||
| 12088 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu32.c' | ||
| 12089 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c 2010-07-29 15:38:15 +0000 | ||
| 12090 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c 2010-08-20 13:27:11 +0000 | ||
| 12091 | @@ -17,5 +17,5 @@ | ||
| 12092 | out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); | ||
| 12093 | } | ||
| 12094 | |||
| 12095 | -/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12096 | +/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12097 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12098 | |||
| 12099 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu64.c' | ||
| 12100 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c 2010-07-29 15:38:15 +0000 | ||
| 12101 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c 2010-08-20 13:27:11 +0000 | ||
| 12102 | @@ -17,5 +17,5 @@ | ||
| 12103 | out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); | ||
| 12104 | } | ||
| 12105 | |||
| 12106 | -/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12107 | +/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12108 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12109 | |||
| 12110 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu8.c' | ||
| 12111 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c 2010-07-29 15:38:15 +0000 | ||
| 12112 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c 2010-08-20 13:27:11 +0000 | ||
| 12113 | @@ -17,5 +17,5 @@ | ||
| 12114 | out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); | ||
| 12115 | } | ||
| 12116 | |||
| 12117 | -/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12118 | +/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12119 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12120 | |||
| 12121 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c' | ||
| 12122 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 12123 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 12124 | @@ -16,5 +16,5 @@ | ||
| 12125 | out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1); | ||
| 12126 | } | ||
| 12127 | |||
| 12128 | -/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12129 | +/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12130 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12131 | |||
| 12132 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c' | ||
| 12133 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 12134 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 12135 | @@ -16,5 +16,5 @@ | ||
| 12136 | out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1); | ||
| 12137 | } | ||
| 12138 | |||
| 12139 | -/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12140 | +/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12141 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12142 | |||
| 12143 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c' | ||
| 12144 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 12145 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 12146 | @@ -16,5 +16,5 @@ | ||
| 12147 | out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1); | ||
| 12148 | } | ||
| 12149 | |||
| 12150 | -/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12151 | +/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12152 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12153 | |||
| 12154 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c' | ||
| 12155 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 12156 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 12157 | @@ -16,5 +16,5 @@ | ||
| 12158 | out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1); | ||
| 12159 | } | ||
| 12160 | |||
| 12161 | -/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12162 | +/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12163 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12164 | |||
| 12165 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c' | ||
| 12166 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 12167 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 12168 | @@ -16,5 +16,5 @@ | ||
| 12169 | out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1); | ||
| 12170 | } | ||
| 12171 | |||
| 12172 | -/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12173 | +/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12174 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12175 | |||
| 12176 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c' | ||
| 12177 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 12178 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 12179 | @@ -16,5 +16,5 @@ | ||
| 12180 | out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1); | ||
| 12181 | } | ||
| 12182 | |||
| 12183 | -/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12184 | +/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12185 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12186 | |||
| 12187 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c' | ||
| 12188 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 12189 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 12190 | @@ -16,5 +16,5 @@ | ||
| 12191 | out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1); | ||
| 12192 | } | ||
| 12193 | |||
| 12194 | -/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12195 | +/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12196 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12197 | |||
| 12198 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c' | ||
| 12199 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 12200 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 12201 | @@ -16,5 +16,5 @@ | ||
| 12202 | out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1); | ||
| 12203 | } | ||
| 12204 | |||
| 12205 | -/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12206 | +/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12207 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12208 | |||
| 12209 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c' | ||
| 12210 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 12211 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 12212 | @@ -16,5 +16,5 @@ | ||
| 12213 | out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1); | ||
| 12214 | } | ||
| 12215 | |||
| 12216 | -/* { dg-final { scan-assembler "vqshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12217 | +/* { dg-final { scan-assembler "vqshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12218 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12219 | |||
| 12220 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c' | ||
| 12221 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 12222 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 12223 | @@ -16,5 +16,5 @@ | ||
| 12224 | out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1); | ||
| 12225 | } | ||
| 12226 | |||
| 12227 | -/* { dg-final { scan-assembler "vqshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12228 | +/* { dg-final { scan-assembler "vqshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12229 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12230 | |||
| 12231 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c' | ||
| 12232 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 12233 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 12234 | @@ -16,5 +16,5 @@ | ||
| 12235 | out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1); | ||
| 12236 | } | ||
| 12237 | |||
| 12238 | -/* { dg-final { scan-assembler "vqshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12239 | +/* { dg-final { scan-assembler "vqshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12240 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12241 | |||
| 12242 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c' | ||
| 12243 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 12244 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 12245 | @@ -16,5 +16,5 @@ | ||
| 12246 | out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1); | ||
| 12247 | } | ||
| 12248 | |||
| 12249 | -/* { dg-final { scan-assembler "vqshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12250 | +/* { dg-final { scan-assembler "vqshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12251 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12252 | |||
| 12253 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c' | ||
| 12254 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 12255 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 12256 | @@ -16,5 +16,5 @@ | ||
| 12257 | out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1); | ||
| 12258 | } | ||
| 12259 | |||
| 12260 | -/* { dg-final { scan-assembler "vqshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12261 | +/* { dg-final { scan-assembler "vqshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12262 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12263 | |||
| 12264 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c' | ||
| 12265 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 12266 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 12267 | @@ -16,5 +16,5 @@ | ||
| 12268 | out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1); | ||
| 12269 | } | ||
| 12270 | |||
| 12271 | -/* { dg-final { scan-assembler "vqshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12272 | +/* { dg-final { scan-assembler "vqshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12273 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12274 | |||
| 12275 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c' | ||
| 12276 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 12277 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 12278 | @@ -16,5 +16,5 @@ | ||
| 12279 | out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1); | ||
| 12280 | } | ||
| 12281 | |||
| 12282 | -/* { dg-final { scan-assembler "vqshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12283 | +/* { dg-final { scan-assembler "vqshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12284 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12285 | |||
| 12286 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c' | ||
| 12287 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 12288 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 12289 | @@ -16,5 +16,5 @@ | ||
| 12290 | out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1); | ||
| 12291 | } | ||
| 12292 | |||
| 12293 | -/* { dg-final { scan-assembler "vqshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12294 | +/* { dg-final { scan-assembler "vqshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12295 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12296 | |||
| 12297 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c' | ||
| 12298 | --- old/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 12299 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 12300 | @@ -16,5 +16,5 @@ | ||
| 12301 | out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1); | ||
| 12302 | } | ||
| 12303 | |||
| 12304 | -/* { dg-final { scan-assembler "vqshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12305 | +/* { dg-final { scan-assembler "vqshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12306 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12307 | |||
| 12308 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c' | ||
| 12309 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c 2010-07-29 15:38:15 +0000 | ||
| 12310 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c 2010-08-20 13:27:11 +0000 | ||
| 12311 | @@ -17,5 +17,5 @@ | ||
| 12312 | out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 12313 | } | ||
| 12314 | |||
| 12315 | -/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12316 | +/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12317 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12318 | |||
| 12319 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c' | ||
| 12320 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c 2010-07-29 15:38:15 +0000 | ||
| 12321 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c 2010-08-20 13:27:11 +0000 | ||
| 12322 | @@ -17,5 +17,5 @@ | ||
| 12323 | out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 12324 | } | ||
| 12325 | |||
| 12326 | -/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12327 | +/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12328 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12329 | |||
| 12330 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c' | ||
| 12331 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c 2010-07-29 15:38:15 +0000 | ||
| 12332 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c 2010-08-20 13:27:11 +0000 | ||
| 12333 | @@ -17,5 +17,5 @@ | ||
| 12334 | out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 12335 | } | ||
| 12336 | |||
| 12337 | -/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12338 | +/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12339 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12340 | |||
| 12341 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c' | ||
| 12342 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c 2010-07-29 15:38:15 +0000 | ||
| 12343 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c 2010-08-20 13:27:11 +0000 | ||
| 12344 | @@ -17,5 +17,5 @@ | ||
| 12345 | out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 12346 | } | ||
| 12347 | |||
| 12348 | -/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12349 | +/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12350 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12351 | |||
| 12352 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c' | ||
| 12353 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c 2010-07-29 15:38:15 +0000 | ||
| 12354 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c 2010-08-20 13:27:11 +0000 | ||
| 12355 | @@ -17,5 +17,5 @@ | ||
| 12356 | out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 12357 | } | ||
| 12358 | |||
| 12359 | -/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12360 | +/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12361 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12362 | |||
| 12363 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c' | ||
| 12364 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c 2010-07-29 15:38:15 +0000 | ||
| 12365 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c 2010-08-20 13:27:11 +0000 | ||
| 12366 | @@ -17,5 +17,5 @@ | ||
| 12367 | out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 12368 | } | ||
| 12369 | |||
| 12370 | -/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12371 | +/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12372 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12373 | |||
| 12374 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c' | ||
| 12375 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c 2010-07-29 15:38:15 +0000 | ||
| 12376 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c 2010-08-20 13:27:11 +0000 | ||
| 12377 | @@ -17,5 +17,5 @@ | ||
| 12378 | out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 12379 | } | ||
| 12380 | |||
| 12381 | -/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12382 | +/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12383 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12384 | |||
| 12385 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c' | ||
| 12386 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c 2010-07-29 15:38:15 +0000 | ||
| 12387 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c 2010-08-20 13:27:11 +0000 | ||
| 12388 | @@ -17,5 +17,5 @@ | ||
| 12389 | out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 12390 | } | ||
| 12391 | |||
| 12392 | -/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12393 | +/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12394 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12395 | |||
| 12396 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs16.c' | ||
| 12397 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c 2010-07-29 15:38:15 +0000 | ||
| 12398 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c 2010-08-20 13:27:11 +0000 | ||
| 12399 | @@ -17,5 +17,5 @@ | ||
| 12400 | out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 12401 | } | ||
| 12402 | |||
| 12403 | -/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12404 | +/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12405 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12406 | |||
| 12407 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs32.c' | ||
| 12408 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c 2010-07-29 15:38:15 +0000 | ||
| 12409 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c 2010-08-20 13:27:11 +0000 | ||
| 12410 | @@ -17,5 +17,5 @@ | ||
| 12411 | out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 12412 | } | ||
| 12413 | |||
| 12414 | -/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12415 | +/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12416 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12417 | |||
| 12418 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs64.c' | ||
| 12419 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c 2010-07-29 15:38:15 +0000 | ||
| 12420 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c 2010-08-20 13:27:11 +0000 | ||
| 12421 | @@ -17,5 +17,5 @@ | ||
| 12422 | out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 12423 | } | ||
| 12424 | |||
| 12425 | -/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12426 | +/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12427 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12428 | |||
| 12429 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubs8.c' | ||
| 12430 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c 2010-07-29 15:38:15 +0000 | ||
| 12431 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c 2010-08-20 13:27:11 +0000 | ||
| 12432 | @@ -17,5 +17,5 @@ | ||
| 12433 | out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 12434 | } | ||
| 12435 | |||
| 12436 | -/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12437 | +/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12438 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12439 | |||
| 12440 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu16.c' | ||
| 12441 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c 2010-07-29 15:38:15 +0000 | ||
| 12442 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c 2010-08-20 13:27:11 +0000 | ||
| 12443 | @@ -17,5 +17,5 @@ | ||
| 12444 | out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 12445 | } | ||
| 12446 | |||
| 12447 | -/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12448 | +/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12449 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12450 | |||
| 12451 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu32.c' | ||
| 12452 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c 2010-07-29 15:38:15 +0000 | ||
| 12453 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c 2010-08-20 13:27:11 +0000 | ||
| 12454 | @@ -17,5 +17,5 @@ | ||
| 12455 | out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 12456 | } | ||
| 12457 | |||
| 12458 | -/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12459 | +/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12460 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12461 | |||
| 12462 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu64.c' | ||
| 12463 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c 2010-07-29 15:38:15 +0000 | ||
| 12464 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c 2010-08-20 13:27:11 +0000 | ||
| 12465 | @@ -17,5 +17,5 @@ | ||
| 12466 | out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t); | ||
| 12467 | } | ||
| 12468 | |||
| 12469 | -/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12470 | +/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12471 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12472 | |||
| 12473 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vqsubu8.c' | ||
| 12474 | --- old/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c 2010-07-29 15:38:15 +0000 | ||
| 12475 | +++ new/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c 2010-08-20 13:27:11 +0000 | ||
| 12476 | @@ -17,5 +17,5 @@ | ||
| 12477 | out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 12478 | } | ||
| 12479 | |||
| 12480 | -/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12481 | +/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12482 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12483 | |||
| 12484 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c' | ||
| 12485 | --- old/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c 2010-07-29 15:38:15 +0000 | ||
| 12486 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c 2010-08-20 13:27:11 +0000 | ||
| 12487 | @@ -16,5 +16,5 @@ | ||
| 12488 | out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t); | ||
| 12489 | } | ||
| 12490 | |||
| 12491 | -/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12492 | +/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12493 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12494 | |||
| 12495 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c' | ||
| 12496 | --- old/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c 2010-07-29 15:38:15 +0000 | ||
| 12497 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c 2010-08-20 13:27:11 +0000 | ||
| 12498 | @@ -16,5 +16,5 @@ | ||
| 12499 | out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t); | ||
| 12500 | } | ||
| 12501 | |||
| 12502 | -/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12503 | +/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12504 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12505 | |||
| 12506 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpef32.c' | ||
| 12507 | --- old/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c 2010-07-29 15:38:15 +0000 | ||
| 12508 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c 2010-08-20 13:27:11 +0000 | ||
| 12509 | @@ -16,5 +16,5 @@ | ||
| 12510 | out_float32x2_t = vrecpe_f32 (arg0_float32x2_t); | ||
| 12511 | } | ||
| 12512 | |||
| 12513 | -/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12514 | +/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12515 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12516 | |||
| 12517 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c' | ||
| 12518 | --- old/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c 2010-07-29 15:38:15 +0000 | ||
| 12519 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c 2010-08-20 13:27:11 +0000 | ||
| 12520 | @@ -16,5 +16,5 @@ | ||
| 12521 | out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t); | ||
| 12522 | } | ||
| 12523 | |||
| 12524 | -/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12525 | +/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12526 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12527 | |||
| 12528 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c' | ||
| 12529 | --- old/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c 2010-07-29 15:38:15 +0000 | ||
| 12530 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c 2010-08-20 13:27:11 +0000 | ||
| 12531 | @@ -17,5 +17,5 @@ | ||
| 12532 | out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 12533 | } | ||
| 12534 | |||
| 12535 | -/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12536 | +/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12537 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12538 | |||
| 12539 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c' | ||
| 12540 | --- old/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c 2010-07-29 15:38:15 +0000 | ||
| 12541 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c 2010-08-20 13:27:11 +0000 | ||
| 12542 | @@ -17,5 +17,5 @@ | ||
| 12543 | out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 12544 | } | ||
| 12545 | |||
| 12546 | -/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12547 | +/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12548 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12549 | |||
| 12550 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c' | ||
| 12551 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c 2010-07-29 15:38:15 +0000 | ||
| 12552 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 12553 | @@ -16,5 +16,5 @@ | ||
| 12554 | out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t); | ||
| 12555 | } | ||
| 12556 | |||
| 12557 | -/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12558 | +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12559 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12560 | |||
| 12561 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c' | ||
| 12562 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c 2010-07-29 15:38:15 +0000 | ||
| 12563 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 12564 | @@ -16,5 +16,5 @@ | ||
| 12565 | out_int8x16_t = vrev16q_s8 (arg0_int8x16_t); | ||
| 12566 | } | ||
| 12567 | |||
| 12568 | -/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12569 | +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12570 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12571 | |||
| 12572 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c' | ||
| 12573 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c 2010-07-29 15:38:15 +0000 | ||
| 12574 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 12575 | @@ -16,5 +16,5 @@ | ||
| 12576 | out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t); | ||
| 12577 | } | ||
| 12578 | |||
| 12579 | -/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12580 | +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12581 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12582 | |||
| 12583 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16p8.c' | ||
| 12584 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c 2010-07-29 15:38:15 +0000 | ||
| 12585 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c 2010-08-20 13:27:11 +0000 | ||
| 12586 | @@ -16,5 +16,5 @@ | ||
| 12587 | out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t); | ||
| 12588 | } | ||
| 12589 | |||
| 12590 | -/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12591 | +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12592 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12593 | |||
| 12594 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16s8.c' | ||
| 12595 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c 2010-07-29 15:38:15 +0000 | ||
| 12596 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c 2010-08-20 13:27:11 +0000 | ||
| 12597 | @@ -16,5 +16,5 @@ | ||
| 12598 | out_int8x8_t = vrev16_s8 (arg0_int8x8_t); | ||
| 12599 | } | ||
| 12600 | |||
| 12601 | -/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12602 | +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12603 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12604 | |||
| 12605 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev16u8.c' | ||
| 12606 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c 2010-07-29 15:38:15 +0000 | ||
| 12607 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c 2010-08-20 13:27:11 +0000 | ||
| 12608 | @@ -16,5 +16,5 @@ | ||
| 12609 | out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t); | ||
| 12610 | } | ||
| 12611 | |||
| 12612 | -/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12613 | +/* { dg-final { scan-assembler "vrev16\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12614 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12615 | |||
| 12616 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c' | ||
| 12617 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c 2010-07-29 15:38:15 +0000 | ||
| 12618 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 12619 | @@ -16,5 +16,5 @@ | ||
| 12620 | out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t); | ||
| 12621 | } | ||
| 12622 | |||
| 12623 | -/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12624 | +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12625 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12626 | |||
| 12627 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c' | ||
| 12628 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c 2010-07-29 15:38:15 +0000 | ||
| 12629 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 12630 | @@ -16,5 +16,5 @@ | ||
| 12631 | out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t); | ||
| 12632 | } | ||
| 12633 | |||
| 12634 | -/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12635 | +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12636 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12637 | |||
| 12638 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c' | ||
| 12639 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c 2010-07-29 15:38:15 +0000 | ||
| 12640 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 12641 | @@ -16,5 +16,5 @@ | ||
| 12642 | out_int16x8_t = vrev32q_s16 (arg0_int16x8_t); | ||
| 12643 | } | ||
| 12644 | |||
| 12645 | -/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12646 | +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12647 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12648 | |||
| 12649 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c' | ||
| 12650 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c 2010-07-29 15:38:15 +0000 | ||
| 12651 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 12652 | @@ -16,5 +16,5 @@ | ||
| 12653 | out_int8x16_t = vrev32q_s8 (arg0_int8x16_t); | ||
| 12654 | } | ||
| 12655 | |||
| 12656 | -/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12657 | +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12658 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12659 | |||
| 12660 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c' | ||
| 12661 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c 2010-07-29 15:38:15 +0000 | ||
| 12662 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 12663 | @@ -16,5 +16,5 @@ | ||
| 12664 | out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t); | ||
| 12665 | } | ||
| 12666 | |||
| 12667 | -/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12668 | +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12669 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12670 | |||
| 12671 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c' | ||
| 12672 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c 2010-07-29 15:38:15 +0000 | ||
| 12673 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 12674 | @@ -16,5 +16,5 @@ | ||
| 12675 | out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t); | ||
| 12676 | } | ||
| 12677 | |||
| 12678 | -/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12679 | +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12680 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12681 | |||
| 12682 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32p16.c' | ||
| 12683 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c 2010-07-29 15:38:15 +0000 | ||
| 12684 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c 2010-08-20 13:27:11 +0000 | ||
| 12685 | @@ -16,5 +16,5 @@ | ||
| 12686 | out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t); | ||
| 12687 | } | ||
| 12688 | |||
| 12689 | -/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12690 | +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12691 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12692 | |||
| 12693 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32p8.c' | ||
| 12694 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c 2010-07-29 15:38:15 +0000 | ||
| 12695 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c 2010-08-20 13:27:11 +0000 | ||
| 12696 | @@ -16,5 +16,5 @@ | ||
| 12697 | out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t); | ||
| 12698 | } | ||
| 12699 | |||
| 12700 | -/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12701 | +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12702 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12703 | |||
| 12704 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32s16.c' | ||
| 12705 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c 2010-07-29 15:38:15 +0000 | ||
| 12706 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c 2010-08-20 13:27:11 +0000 | ||
| 12707 | @@ -16,5 +16,5 @@ | ||
| 12708 | out_int16x4_t = vrev32_s16 (arg0_int16x4_t); | ||
| 12709 | } | ||
| 12710 | |||
| 12711 | -/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12712 | +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12713 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12714 | |||
| 12715 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32s8.c' | ||
| 12716 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c 2010-07-29 15:38:15 +0000 | ||
| 12717 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c 2010-08-20 13:27:11 +0000 | ||
| 12718 | @@ -16,5 +16,5 @@ | ||
| 12719 | out_int8x8_t = vrev32_s8 (arg0_int8x8_t); | ||
| 12720 | } | ||
| 12721 | |||
| 12722 | -/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12723 | +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12724 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12725 | |||
| 12726 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32u16.c' | ||
| 12727 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c 2010-07-29 15:38:15 +0000 | ||
| 12728 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c 2010-08-20 13:27:11 +0000 | ||
| 12729 | @@ -16,5 +16,5 @@ | ||
| 12730 | out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t); | ||
| 12731 | } | ||
| 12732 | |||
| 12733 | -/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12734 | +/* { dg-final { scan-assembler "vrev32\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12735 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12736 | |||
| 12737 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev32u8.c' | ||
| 12738 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c 2010-07-29 15:38:15 +0000 | ||
| 12739 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c 2010-08-20 13:27:11 +0000 | ||
| 12740 | @@ -16,5 +16,5 @@ | ||
| 12741 | out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t); | ||
| 12742 | } | ||
| 12743 | |||
| 12744 | -/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12745 | +/* { dg-final { scan-assembler "vrev32\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12746 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12747 | |||
| 12748 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c' | ||
| 12749 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c 2010-07-29 15:38:15 +0000 | ||
| 12750 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 12751 | @@ -16,5 +16,5 @@ | ||
| 12752 | out_float32x4_t = vrev64q_f32 (arg0_float32x4_t); | ||
| 12753 | } | ||
| 12754 | |||
| 12755 | -/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12756 | +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12757 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12758 | |||
| 12759 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c' | ||
| 12760 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c 2010-07-29 15:38:15 +0000 | ||
| 12761 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 12762 | @@ -16,5 +16,5 @@ | ||
| 12763 | out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t); | ||
| 12764 | } | ||
| 12765 | |||
| 12766 | -/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12767 | +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12768 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12769 | |||
| 12770 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c' | ||
| 12771 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c 2010-07-29 15:38:15 +0000 | ||
| 12772 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 12773 | @@ -16,5 +16,5 @@ | ||
| 12774 | out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t); | ||
| 12775 | } | ||
| 12776 | |||
| 12777 | -/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12778 | +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12779 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12780 | |||
| 12781 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c' | ||
| 12782 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c 2010-07-29 15:38:15 +0000 | ||
| 12783 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 12784 | @@ -16,5 +16,5 @@ | ||
| 12785 | out_int16x8_t = vrev64q_s16 (arg0_int16x8_t); | ||
| 12786 | } | ||
| 12787 | |||
| 12788 | -/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12789 | +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12790 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12791 | |||
| 12792 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c' | ||
| 12793 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c 2010-07-29 15:38:15 +0000 | ||
| 12794 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 12795 | @@ -16,5 +16,5 @@ | ||
| 12796 | out_int32x4_t = vrev64q_s32 (arg0_int32x4_t); | ||
| 12797 | } | ||
| 12798 | |||
| 12799 | -/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12800 | +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12801 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12802 | |||
| 12803 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c' | ||
| 12804 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c 2010-07-29 15:38:15 +0000 | ||
| 12805 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 12806 | @@ -16,5 +16,5 @@ | ||
| 12807 | out_int8x16_t = vrev64q_s8 (arg0_int8x16_t); | ||
| 12808 | } | ||
| 12809 | |||
| 12810 | -/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12811 | +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12812 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12813 | |||
| 12814 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c' | ||
| 12815 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c 2010-07-29 15:38:15 +0000 | ||
| 12816 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 12817 | @@ -16,5 +16,5 @@ | ||
| 12818 | out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t); | ||
| 12819 | } | ||
| 12820 | |||
| 12821 | -/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12822 | +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12823 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12824 | |||
| 12825 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c' | ||
| 12826 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c 2010-07-29 15:38:15 +0000 | ||
| 12827 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 12828 | @@ -16,5 +16,5 @@ | ||
| 12829 | out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t); | ||
| 12830 | } | ||
| 12831 | |||
| 12832 | -/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12833 | +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12834 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12835 | |||
| 12836 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c' | ||
| 12837 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c 2010-07-29 15:38:15 +0000 | ||
| 12838 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 12839 | @@ -16,5 +16,5 @@ | ||
| 12840 | out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t); | ||
| 12841 | } | ||
| 12842 | |||
| 12843 | -/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12844 | +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12845 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12846 | |||
| 12847 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64f32.c' | ||
| 12848 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c 2010-07-29 15:38:15 +0000 | ||
| 12849 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c 2010-08-20 13:27:11 +0000 | ||
| 12850 | @@ -16,5 +16,5 @@ | ||
| 12851 | out_float32x2_t = vrev64_f32 (arg0_float32x2_t); | ||
| 12852 | } | ||
| 12853 | |||
| 12854 | -/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12855 | +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12856 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12857 | |||
| 12858 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64p16.c' | ||
| 12859 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c 2010-07-29 15:38:15 +0000 | ||
| 12860 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c 2010-08-20 13:27:11 +0000 | ||
| 12861 | @@ -16,5 +16,5 @@ | ||
| 12862 | out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t); | ||
| 12863 | } | ||
| 12864 | |||
| 12865 | -/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12866 | +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12867 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12868 | |||
| 12869 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64p8.c' | ||
| 12870 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c 2010-07-29 15:38:15 +0000 | ||
| 12871 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c 2010-08-20 13:27:11 +0000 | ||
| 12872 | @@ -16,5 +16,5 @@ | ||
| 12873 | out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t); | ||
| 12874 | } | ||
| 12875 | |||
| 12876 | -/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12877 | +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12878 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12879 | |||
| 12880 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64s16.c' | ||
| 12881 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c 2010-07-29 15:38:15 +0000 | ||
| 12882 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c 2010-08-20 13:27:11 +0000 | ||
| 12883 | @@ -16,5 +16,5 @@ | ||
| 12884 | out_int16x4_t = vrev64_s16 (arg0_int16x4_t); | ||
| 12885 | } | ||
| 12886 | |||
| 12887 | -/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12888 | +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12889 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12890 | |||
| 12891 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64s32.c' | ||
| 12892 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c 2010-07-29 15:38:15 +0000 | ||
| 12893 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c 2010-08-20 13:27:11 +0000 | ||
| 12894 | @@ -16,5 +16,5 @@ | ||
| 12895 | out_int32x2_t = vrev64_s32 (arg0_int32x2_t); | ||
| 12896 | } | ||
| 12897 | |||
| 12898 | -/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12899 | +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12900 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12901 | |||
| 12902 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64s8.c' | ||
| 12903 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c 2010-07-29 15:38:15 +0000 | ||
| 12904 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c 2010-08-20 13:27:11 +0000 | ||
| 12905 | @@ -16,5 +16,5 @@ | ||
| 12906 | out_int8x8_t = vrev64_s8 (arg0_int8x8_t); | ||
| 12907 | } | ||
| 12908 | |||
| 12909 | -/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12910 | +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12911 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12912 | |||
| 12913 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64u16.c' | ||
| 12914 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c 2010-07-29 15:38:15 +0000 | ||
| 12915 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c 2010-08-20 13:27:11 +0000 | ||
| 12916 | @@ -16,5 +16,5 @@ | ||
| 12917 | out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t); | ||
| 12918 | } | ||
| 12919 | |||
| 12920 | -/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12921 | +/* { dg-final { scan-assembler "vrev64\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12922 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12923 | |||
| 12924 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64u32.c' | ||
| 12925 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c 2010-07-29 15:38:15 +0000 | ||
| 12926 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c 2010-08-20 13:27:11 +0000 | ||
| 12927 | @@ -16,5 +16,5 @@ | ||
| 12928 | out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t); | ||
| 12929 | } | ||
| 12930 | |||
| 12931 | -/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12932 | +/* { dg-final { scan-assembler "vrev64\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12933 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12934 | |||
| 12935 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrev64u8.c' | ||
| 12936 | --- old/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c 2010-07-29 15:38:15 +0000 | ||
| 12937 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c 2010-08-20 13:27:11 +0000 | ||
| 12938 | @@ -16,5 +16,5 @@ | ||
| 12939 | out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t); | ||
| 12940 | } | ||
| 12941 | |||
| 12942 | -/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12943 | +/* { dg-final { scan-assembler "vrev64\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12944 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12945 | |||
| 12946 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c' | ||
| 12947 | --- old/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c 2010-07-29 15:38:15 +0000 | ||
| 12948 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c 2010-08-20 13:27:11 +0000 | ||
| 12949 | @@ -16,5 +16,5 @@ | ||
| 12950 | out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t); | ||
| 12951 | } | ||
| 12952 | |||
| 12953 | -/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12954 | +/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12955 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12956 | |||
| 12957 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c' | ||
| 12958 | --- old/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c 2010-07-29 15:38:15 +0000 | ||
| 12959 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c 2010-08-20 13:27:11 +0000 | ||
| 12960 | @@ -16,5 +16,5 @@ | ||
| 12961 | out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t); | ||
| 12962 | } | ||
| 12963 | |||
| 12964 | -/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12965 | +/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12966 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12967 | |||
| 12968 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c' | ||
| 12969 | --- old/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c 2010-07-29 15:38:15 +0000 | ||
| 12970 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c 2010-08-20 13:27:11 +0000 | ||
| 12971 | @@ -16,5 +16,5 @@ | ||
| 12972 | out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t); | ||
| 12973 | } | ||
| 12974 | |||
| 12975 | -/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12976 | +/* { dg-final { scan-assembler "vrsqrte\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12977 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12978 | |||
| 12979 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c' | ||
| 12980 | --- old/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c 2010-07-29 15:38:15 +0000 | ||
| 12981 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c 2010-08-20 13:27:11 +0000 | ||
| 12982 | @@ -16,5 +16,5 @@ | ||
| 12983 | out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t); | ||
| 12984 | } | ||
| 12985 | |||
| 12986 | -/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12987 | +/* { dg-final { scan-assembler "vrsqrte\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12988 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 12989 | |||
| 12990 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c' | ||
| 12991 | --- old/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c 2010-07-29 15:38:15 +0000 | ||
| 12992 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c 2010-08-20 13:27:11 +0000 | ||
| 12993 | @@ -17,5 +17,5 @@ | ||
| 12994 | out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 12995 | } | ||
| 12996 | |||
| 12997 | -/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 12998 | +/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 12999 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13000 | |||
| 13001 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c' | ||
| 13002 | --- old/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c 2010-07-29 15:38:15 +0000 | ||
| 13003 | +++ new/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c 2010-08-20 13:27:11 +0000 | ||
| 13004 | @@ -17,5 +17,5 @@ | ||
| 13005 | out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 13006 | } | ||
| 13007 | |||
| 13008 | -/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13009 | +/* { dg-final { scan-assembler "vrsqrts\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13010 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13011 | |||
| 13012 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c' | ||
| 13013 | --- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 13014 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 13015 | @@ -17,5 +17,5 @@ | ||
| 13016 | out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); | ||
| 13017 | } | ||
| 13018 | |||
| 13019 | -/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13020 | +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13021 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13022 | |||
| 13023 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c' | ||
| 13024 | --- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 13025 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 13026 | @@ -17,5 +17,5 @@ | ||
| 13027 | out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); | ||
| 13028 | } | ||
| 13029 | |||
| 13030 | -/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13031 | +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13032 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13033 | |||
| 13034 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c' | ||
| 13035 | --- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 13036 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 13037 | @@ -17,5 +17,5 @@ | ||
| 13038 | out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); | ||
| 13039 | } | ||
| 13040 | |||
| 13041 | -/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13042 | +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13043 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13044 | |||
| 13045 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c' | ||
| 13046 | --- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 13047 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 13048 | @@ -17,5 +17,5 @@ | ||
| 13049 | out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); | ||
| 13050 | } | ||
| 13051 | |||
| 13052 | -/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13053 | +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13054 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13055 | |||
| 13056 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c' | ||
| 13057 | --- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 13058 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 13059 | @@ -17,5 +17,5 @@ | ||
| 13060 | out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); | ||
| 13061 | } | ||
| 13062 | |||
| 13063 | -/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13064 | +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13065 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13066 | |||
| 13067 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c' | ||
| 13068 | --- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c 2010-07-29 15:38:15 +0000 | ||
| 13069 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c 2010-08-20 13:27:11 +0000 | ||
| 13070 | @@ -17,5 +17,5 @@ | ||
| 13071 | out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0); | ||
| 13072 | } | ||
| 13073 | |||
| 13074 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13075 | +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13076 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13077 | |||
| 13078 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c' | ||
| 13079 | --- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 13080 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 13081 | @@ -17,5 +17,5 @@ | ||
| 13082 | out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); | ||
| 13083 | } | ||
| 13084 | |||
| 13085 | -/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13086 | +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13087 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13088 | |||
| 13089 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c' | ||
| 13090 | --- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 13091 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 13092 | @@ -17,5 +17,5 @@ | ||
| 13093 | out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); | ||
| 13094 | } | ||
| 13095 | |||
| 13096 | -/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13097 | +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13098 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13099 | |||
| 13100 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c' | ||
| 13101 | --- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 13102 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 13103 | @@ -17,5 +17,5 @@ | ||
| 13104 | out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); | ||
| 13105 | } | ||
| 13106 | |||
| 13107 | -/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13108 | +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13109 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13110 | |||
| 13111 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c' | ||
| 13112 | --- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c 2010-07-29 15:38:15 +0000 | ||
| 13113 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c 2010-08-20 13:27:11 +0000 | ||
| 13114 | @@ -17,5 +17,5 @@ | ||
| 13115 | out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0); | ||
| 13116 | } | ||
| 13117 | |||
| 13118 | -/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13119 | +/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13120 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13121 | |||
| 13122 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c' | ||
| 13123 | --- old/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 13124 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 13125 | @@ -17,5 +17,5 @@ | ||
| 13126 | out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); | ||
| 13127 | } | ||
| 13128 | |||
| 13129 | -/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13130 | +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13131 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13132 | |||
| 13133 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c' | ||
| 13134 | --- old/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 13135 | +++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 13136 | @@ -17,5 +17,5 @@ | ||
| 13137 | out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); | ||
| 13138 | } | ||
| 13139 | |||
| 13140 | -/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13141 | +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13142 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13143 | |||
| 13144 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c' | ||
| 13145 | --- old/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 13146 | +++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 13147 | @@ -17,5 +17,5 @@ | ||
| 13148 | out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); | ||
| 13149 | } | ||
| 13150 | |||
| 13151 | -/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13152 | +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13153 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13154 | |||
| 13155 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c' | ||
| 13156 | --- old/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 13157 | +++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 13158 | @@ -17,5 +17,5 @@ | ||
| 13159 | out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); | ||
| 13160 | } | ||
| 13161 | |||
| 13162 | -/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13163 | +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13164 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13165 | |||
| 13166 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c' | ||
| 13167 | --- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 13168 | +++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 13169 | @@ -17,5 +17,5 @@ | ||
| 13170 | out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); | ||
| 13171 | } | ||
| 13172 | |||
| 13173 | -/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13174 | +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13175 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13176 | |||
| 13177 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c' | ||
| 13178 | --- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 13179 | +++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 13180 | @@ -17,5 +17,5 @@ | ||
| 13181 | out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); | ||
| 13182 | } | ||
| 13183 | |||
| 13184 | -/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13185 | +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13186 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13187 | |||
| 13188 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c' | ||
| 13189 | --- old/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 13190 | +++ new/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 13191 | @@ -17,5 +17,5 @@ | ||
| 13192 | out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); | ||
| 13193 | } | ||
| 13194 | |||
| 13195 | -/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13196 | +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13197 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13198 | |||
| 13199 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c' | ||
| 13200 | --- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 13201 | +++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 13202 | @@ -17,5 +17,5 @@ | ||
| 13203 | out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); | ||
| 13204 | } | ||
| 13205 | |||
| 13206 | -/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13207 | +/* { dg-final { scan-assembler "vmov\.16\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13208 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13209 | |||
| 13210 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c' | ||
| 13211 | --- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 13212 | +++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 13213 | @@ -17,5 +17,5 @@ | ||
| 13214 | out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); | ||
| 13215 | } | ||
| 13216 | |||
| 13217 | -/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13218 | +/* { dg-final { scan-assembler "vmov\.32\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13219 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13220 | |||
| 13221 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c' | ||
| 13222 | --- old/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 13223 | +++ new/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 13224 | @@ -17,5 +17,5 @@ | ||
| 13225 | out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); | ||
| 13226 | } | ||
| 13227 | |||
| 13228 | -/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13229 | +/* { dg-final { scan-assembler "vmov\.8\[ \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13230 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13231 | |||
| 13232 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c' | ||
| 13233 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 13234 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 13235 | @@ -16,5 +16,5 @@ | ||
| 13236 | out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1); | ||
| 13237 | } | ||
| 13238 | |||
| 13239 | -/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13240 | +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13241 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13242 | |||
| 13243 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c' | ||
| 13244 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 13245 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 13246 | @@ -16,5 +16,5 @@ | ||
| 13247 | out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1); | ||
| 13248 | } | ||
| 13249 | |||
| 13250 | -/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13251 | +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13252 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13253 | |||
| 13254 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c' | ||
| 13255 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 13256 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 13257 | @@ -16,5 +16,5 @@ | ||
| 13258 | out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1); | ||
| 13259 | } | ||
| 13260 | |||
| 13261 | -/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13262 | +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13263 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13264 | |||
| 13265 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c' | ||
| 13266 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 13267 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 13268 | @@ -16,5 +16,5 @@ | ||
| 13269 | out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1); | ||
| 13270 | } | ||
| 13271 | |||
| 13272 | -/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13273 | +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13274 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13275 | |||
| 13276 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c' | ||
| 13277 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 13278 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 13279 | @@ -16,5 +16,5 @@ | ||
| 13280 | out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1); | ||
| 13281 | } | ||
| 13282 | |||
| 13283 | -/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13284 | +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13285 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13286 | |||
| 13287 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c' | ||
| 13288 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 13289 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 13290 | @@ -16,5 +16,5 @@ | ||
| 13291 | out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1); | ||
| 13292 | } | ||
| 13293 | |||
| 13294 | -/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13295 | +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13296 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13297 | |||
| 13298 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c' | ||
| 13299 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 13300 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 13301 | @@ -16,5 +16,5 @@ | ||
| 13302 | out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1); | ||
| 13303 | } | ||
| 13304 | |||
| 13305 | -/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13306 | +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13307 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13308 | |||
| 13309 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c' | ||
| 13310 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 13311 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 13312 | @@ -16,5 +16,5 @@ | ||
| 13313 | out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1); | ||
| 13314 | } | ||
| 13315 | |||
| 13316 | -/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13317 | +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13318 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13319 | |||
| 13320 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs16.c' | ||
| 13321 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c 2010-07-29 15:38:15 +0000 | ||
| 13322 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c 2010-08-20 13:27:11 +0000 | ||
| 13323 | @@ -17,5 +17,5 @@ | ||
| 13324 | out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 13325 | } | ||
| 13326 | |||
| 13327 | -/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13328 | +/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13329 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13330 | |||
| 13331 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs32.c' | ||
| 13332 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c 2010-07-29 15:38:15 +0000 | ||
| 13333 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c 2010-08-20 13:27:11 +0000 | ||
| 13334 | @@ -17,5 +17,5 @@ | ||
| 13335 | out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 13336 | } | ||
| 13337 | |||
| 13338 | -/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13339 | +/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13340 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13341 | |||
| 13342 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs64.c' | ||
| 13343 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c 2010-07-29 15:38:15 +0000 | ||
| 13344 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c 2010-08-20 13:27:11 +0000 | ||
| 13345 | @@ -17,5 +17,5 @@ | ||
| 13346 | out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 13347 | } | ||
| 13348 | |||
| 13349 | -/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13350 | +/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13351 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13352 | |||
| 13353 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQs8.c' | ||
| 13354 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c 2010-07-29 15:38:15 +0000 | ||
| 13355 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c 2010-08-20 13:27:11 +0000 | ||
| 13356 | @@ -17,5 +17,5 @@ | ||
| 13357 | out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 13358 | } | ||
| 13359 | |||
| 13360 | -/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13361 | +/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13362 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13363 | |||
| 13364 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu16.c' | ||
| 13365 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c 2010-07-29 15:38:15 +0000 | ||
| 13366 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c 2010-08-20 13:27:11 +0000 | ||
| 13367 | @@ -17,5 +17,5 @@ | ||
| 13368 | out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t); | ||
| 13369 | } | ||
| 13370 | |||
| 13371 | -/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13372 | +/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13373 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13374 | |||
| 13375 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu32.c' | ||
| 13376 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c 2010-07-29 15:38:15 +0000 | ||
| 13377 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c 2010-08-20 13:27:11 +0000 | ||
| 13378 | @@ -17,5 +17,5 @@ | ||
| 13379 | out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t); | ||
| 13380 | } | ||
| 13381 | |||
| 13382 | -/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13383 | +/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13384 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13385 | |||
| 13386 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu64.c' | ||
| 13387 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c 2010-07-29 15:38:15 +0000 | ||
| 13388 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c 2010-08-20 13:27:11 +0000 | ||
| 13389 | @@ -17,5 +17,5 @@ | ||
| 13390 | out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t); | ||
| 13391 | } | ||
| 13392 | |||
| 13393 | -/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13394 | +/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13395 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13396 | |||
| 13397 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlQu8.c' | ||
| 13398 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c 2010-07-29 15:38:15 +0000 | ||
| 13399 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c 2010-08-20 13:27:11 +0000 | ||
| 13400 | @@ -17,5 +17,5 @@ | ||
| 13401 | out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t); | ||
| 13402 | } | ||
| 13403 | |||
| 13404 | -/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13405 | +/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13406 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13407 | |||
| 13408 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c' | ||
| 13409 | --- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 13410 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 13411 | @@ -16,5 +16,5 @@ | ||
| 13412 | out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1); | ||
| 13413 | } | ||
| 13414 | |||
| 13415 | -/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13416 | +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13417 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13418 | |||
| 13419 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c' | ||
| 13420 | --- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 13421 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 13422 | @@ -16,5 +16,5 @@ | ||
| 13423 | out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1); | ||
| 13424 | } | ||
| 13425 | |||
| 13426 | -/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13427 | +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13428 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13429 | |||
| 13430 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c' | ||
| 13431 | --- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 13432 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 13433 | @@ -16,5 +16,5 @@ | ||
| 13434 | out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1); | ||
| 13435 | } | ||
| 13436 | |||
| 13437 | -/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13438 | +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13439 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13440 | |||
| 13441 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c' | ||
| 13442 | --- old/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 13443 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 13444 | @@ -16,5 +16,5 @@ | ||
| 13445 | out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1); | ||
| 13446 | } | ||
| 13447 | |||
| 13448 | -/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13449 | +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13450 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13451 | |||
| 13452 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c' | ||
| 13453 | --- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 13454 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 13455 | @@ -16,5 +16,5 @@ | ||
| 13456 | out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1); | ||
| 13457 | } | ||
| 13458 | |||
| 13459 | -/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13460 | +/* { dg-final { scan-assembler "vshl\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13461 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13462 | |||
| 13463 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c' | ||
| 13464 | --- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 13465 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 13466 | @@ -16,5 +16,5 @@ | ||
| 13467 | out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1); | ||
| 13468 | } | ||
| 13469 | |||
| 13470 | -/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13471 | +/* { dg-final { scan-assembler "vshl\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13472 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13473 | |||
| 13474 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c' | ||
| 13475 | --- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 13476 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 13477 | @@ -16,5 +16,5 @@ | ||
| 13478 | out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1); | ||
| 13479 | } | ||
| 13480 | |||
| 13481 | -/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13482 | +/* { dg-final { scan-assembler "vshl\.i64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13483 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13484 | |||
| 13485 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c' | ||
| 13486 | --- old/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 13487 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 13488 | @@ -16,5 +16,5 @@ | ||
| 13489 | out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1); | ||
| 13490 | } | ||
| 13491 | |||
| 13492 | -/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13493 | +/* { dg-final { scan-assembler "vshl\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13494 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13495 | |||
| 13496 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c' | ||
| 13497 | --- old/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 13498 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 13499 | @@ -16,5 +16,5 @@ | ||
| 13500 | out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1); | ||
| 13501 | } | ||
| 13502 | |||
| 13503 | -/* { dg-final { scan-assembler "vshll\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13504 | +/* { dg-final { scan-assembler "vshll\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13505 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13506 | |||
| 13507 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c' | ||
| 13508 | --- old/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 13509 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 13510 | @@ -16,5 +16,5 @@ | ||
| 13511 | out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1); | ||
| 13512 | } | ||
| 13513 | |||
| 13514 | -/* { dg-final { scan-assembler "vshll\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13515 | +/* { dg-final { scan-assembler "vshll\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13516 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13517 | |||
| 13518 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c' | ||
| 13519 | --- old/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 13520 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 13521 | @@ -16,5 +16,5 @@ | ||
| 13522 | out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1); | ||
| 13523 | } | ||
| 13524 | |||
| 13525 | -/* { dg-final { scan-assembler "vshll\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13526 | +/* { dg-final { scan-assembler "vshll\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13527 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13528 | |||
| 13529 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c' | ||
| 13530 | --- old/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 13531 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 13532 | @@ -16,5 +16,5 @@ | ||
| 13533 | out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1); | ||
| 13534 | } | ||
| 13535 | |||
| 13536 | -/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13537 | +/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13538 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13539 | |||
| 13540 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c' | ||
| 13541 | --- old/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 13542 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 13543 | @@ -16,5 +16,5 @@ | ||
| 13544 | out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1); | ||
| 13545 | } | ||
| 13546 | |||
| 13547 | -/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13548 | +/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13549 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13550 | |||
| 13551 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c' | ||
| 13552 | --- old/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 13553 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 13554 | @@ -16,5 +16,5 @@ | ||
| 13555 | out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1); | ||
| 13556 | } | ||
| 13557 | |||
| 13558 | -/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13559 | +/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13560 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13561 | |||
| 13562 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshls16.c' | ||
| 13563 | --- old/gcc/testsuite/gcc.target/arm/neon/vshls16.c 2010-07-29 15:38:15 +0000 | ||
| 13564 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshls16.c 2010-08-20 13:27:11 +0000 | ||
| 13565 | @@ -17,5 +17,5 @@ | ||
| 13566 | out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 13567 | } | ||
| 13568 | |||
| 13569 | -/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13570 | +/* { dg-final { scan-assembler "vshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13571 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13572 | |||
| 13573 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshls32.c' | ||
| 13574 | --- old/gcc/testsuite/gcc.target/arm/neon/vshls32.c 2010-07-29 15:38:15 +0000 | ||
| 13575 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshls32.c 2010-08-20 13:27:11 +0000 | ||
| 13576 | @@ -17,5 +17,5 @@ | ||
| 13577 | out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 13578 | } | ||
| 13579 | |||
| 13580 | -/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13581 | +/* { dg-final { scan-assembler "vshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13582 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13583 | |||
| 13584 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshls64.c' | ||
| 13585 | --- old/gcc/testsuite/gcc.target/arm/neon/vshls64.c 2010-07-29 15:38:15 +0000 | ||
| 13586 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshls64.c 2010-08-20 13:27:11 +0000 | ||
| 13587 | @@ -17,5 +17,5 @@ | ||
| 13588 | out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t); | ||
| 13589 | } | ||
| 13590 | |||
| 13591 | -/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13592 | +/* { dg-final { scan-assembler "vshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13593 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13594 | |||
| 13595 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshls8.c' | ||
| 13596 | --- old/gcc/testsuite/gcc.target/arm/neon/vshls8.c 2010-07-29 15:38:15 +0000 | ||
| 13597 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshls8.c 2010-08-20 13:27:11 +0000 | ||
| 13598 | @@ -17,5 +17,5 @@ | ||
| 13599 | out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 13600 | } | ||
| 13601 | |||
| 13602 | -/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13603 | +/* { dg-final { scan-assembler "vshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13604 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13605 | |||
| 13606 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu16.c' | ||
| 13607 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlu16.c 2010-07-29 15:38:15 +0000 | ||
| 13608 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlu16.c 2010-08-20 13:27:11 +0000 | ||
| 13609 | @@ -17,5 +17,5 @@ | ||
| 13610 | out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t); | ||
| 13611 | } | ||
| 13612 | |||
| 13613 | -/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13614 | +/* { dg-final { scan-assembler "vshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13615 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13616 | |||
| 13617 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu32.c' | ||
| 13618 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlu32.c 2010-07-29 15:38:15 +0000 | ||
| 13619 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlu32.c 2010-08-20 13:27:11 +0000 | ||
| 13620 | @@ -17,5 +17,5 @@ | ||
| 13621 | out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t); | ||
| 13622 | } | ||
| 13623 | |||
| 13624 | -/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13625 | +/* { dg-final { scan-assembler "vshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13626 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13627 | |||
| 13628 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu64.c' | ||
| 13629 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlu64.c 2010-07-29 15:38:15 +0000 | ||
| 13630 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlu64.c 2010-08-20 13:27:11 +0000 | ||
| 13631 | @@ -17,5 +17,5 @@ | ||
| 13632 | out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t); | ||
| 13633 | } | ||
| 13634 | |||
| 13635 | -/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13636 | +/* { dg-final { scan-assembler "vshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13637 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13638 | |||
| 13639 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshlu8.c' | ||
| 13640 | --- old/gcc/testsuite/gcc.target/arm/neon/vshlu8.c 2010-07-29 15:38:15 +0000 | ||
| 13641 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshlu8.c 2010-08-20 13:27:11 +0000 | ||
| 13642 | @@ -17,5 +17,5 @@ | ||
| 13643 | out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t); | ||
| 13644 | } | ||
| 13645 | |||
| 13646 | -/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13647 | +/* { dg-final { scan-assembler "vshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13648 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13649 | |||
| 13650 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c' | ||
| 13651 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 13652 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 13653 | @@ -16,5 +16,5 @@ | ||
| 13654 | out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1); | ||
| 13655 | } | ||
| 13656 | |||
| 13657 | -/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13658 | +/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13659 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13660 | |||
| 13661 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c' | ||
| 13662 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 13663 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 13664 | @@ -16,5 +16,5 @@ | ||
| 13665 | out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1); | ||
| 13666 | } | ||
| 13667 | |||
| 13668 | -/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13669 | +/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13670 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13671 | |||
| 13672 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c' | ||
| 13673 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 13674 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 13675 | @@ -16,5 +16,5 @@ | ||
| 13676 | out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1); | ||
| 13677 | } | ||
| 13678 | |||
| 13679 | -/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13680 | +/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13681 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13682 | |||
| 13683 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c' | ||
| 13684 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 13685 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 13686 | @@ -16,5 +16,5 @@ | ||
| 13687 | out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1); | ||
| 13688 | } | ||
| 13689 | |||
| 13690 | -/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13691 | +/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13692 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13693 | |||
| 13694 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c' | ||
| 13695 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 13696 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 13697 | @@ -16,5 +16,5 @@ | ||
| 13698 | out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1); | ||
| 13699 | } | ||
| 13700 | |||
| 13701 | -/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13702 | +/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13703 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13704 | |||
| 13705 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c' | ||
| 13706 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 13707 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 13708 | @@ -16,5 +16,5 @@ | ||
| 13709 | out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1); | ||
| 13710 | } | ||
| 13711 | |||
| 13712 | -/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13713 | +/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13714 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13715 | |||
| 13716 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c' | ||
| 13717 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 13718 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 13719 | @@ -16,5 +16,5 @@ | ||
| 13720 | out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1); | ||
| 13721 | } | ||
| 13722 | |||
| 13723 | -/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13724 | +/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13725 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13726 | |||
| 13727 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c' | ||
| 13728 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 13729 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 13730 | @@ -16,5 +16,5 @@ | ||
| 13731 | out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1); | ||
| 13732 | } | ||
| 13733 | |||
| 13734 | -/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13735 | +/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13736 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13737 | |||
| 13738 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c' | ||
| 13739 | --- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 13740 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 13741 | @@ -16,5 +16,5 @@ | ||
| 13742 | out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1); | ||
| 13743 | } | ||
| 13744 | |||
| 13745 | -/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13746 | +/* { dg-final { scan-assembler "vshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13747 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13748 | |||
| 13749 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c' | ||
| 13750 | --- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 13751 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 13752 | @@ -16,5 +16,5 @@ | ||
| 13753 | out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1); | ||
| 13754 | } | ||
| 13755 | |||
| 13756 | -/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13757 | +/* { dg-final { scan-assembler "vshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13758 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13759 | |||
| 13760 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c' | ||
| 13761 | --- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 13762 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 13763 | @@ -16,5 +16,5 @@ | ||
| 13764 | out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1); | ||
| 13765 | } | ||
| 13766 | |||
| 13767 | -/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13768 | +/* { dg-final { scan-assembler "vshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13769 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13770 | |||
| 13771 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c' | ||
| 13772 | --- old/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 13773 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 13774 | @@ -16,5 +16,5 @@ | ||
| 13775 | out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1); | ||
| 13776 | } | ||
| 13777 | |||
| 13778 | -/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13779 | +/* { dg-final { scan-assembler "vshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13780 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13781 | |||
| 13782 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c' | ||
| 13783 | --- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 13784 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 13785 | @@ -16,5 +16,5 @@ | ||
| 13786 | out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1); | ||
| 13787 | } | ||
| 13788 | |||
| 13789 | -/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13790 | +/* { dg-final { scan-assembler "vshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13791 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13792 | |||
| 13793 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c' | ||
| 13794 | --- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 13795 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 13796 | @@ -16,5 +16,5 @@ | ||
| 13797 | out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1); | ||
| 13798 | } | ||
| 13799 | |||
| 13800 | -/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13801 | +/* { dg-final { scan-assembler "vshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13802 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13803 | |||
| 13804 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c' | ||
| 13805 | --- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 13806 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 13807 | @@ -16,5 +16,5 @@ | ||
| 13808 | out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1); | ||
| 13809 | } | ||
| 13810 | |||
| 13811 | -/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13812 | +/* { dg-final { scan-assembler "vshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13813 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13814 | |||
| 13815 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c' | ||
| 13816 | --- old/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 13817 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 13818 | @@ -16,5 +16,5 @@ | ||
| 13819 | out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1); | ||
| 13820 | } | ||
| 13821 | |||
| 13822 | -/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13823 | +/* { dg-final { scan-assembler "vshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13824 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13825 | |||
| 13826 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c' | ||
| 13827 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 13828 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 13829 | @@ -16,5 +16,5 @@ | ||
| 13830 | out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1); | ||
| 13831 | } | ||
| 13832 | |||
| 13833 | -/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13834 | +/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13835 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13836 | |||
| 13837 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c' | ||
| 13838 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 13839 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 13840 | @@ -16,5 +16,5 @@ | ||
| 13841 | out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1); | ||
| 13842 | } | ||
| 13843 | |||
| 13844 | -/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13845 | +/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13846 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13847 | |||
| 13848 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c' | ||
| 13849 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 13850 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 13851 | @@ -16,5 +16,5 @@ | ||
| 13852 | out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1); | ||
| 13853 | } | ||
| 13854 | |||
| 13855 | -/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13856 | +/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13857 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13858 | |||
| 13859 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c' | ||
| 13860 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 13861 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 13862 | @@ -16,5 +16,5 @@ | ||
| 13863 | out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1); | ||
| 13864 | } | ||
| 13865 | |||
| 13866 | -/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13867 | +/* { dg-final { scan-assembler "vshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13868 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13869 | |||
| 13870 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c' | ||
| 13871 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 13872 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 13873 | @@ -16,5 +16,5 @@ | ||
| 13874 | out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1); | ||
| 13875 | } | ||
| 13876 | |||
| 13877 | -/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13878 | +/* { dg-final { scan-assembler "vshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13879 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13880 | |||
| 13881 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c' | ||
| 13882 | --- old/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 13883 | +++ new/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 13884 | @@ -16,5 +16,5 @@ | ||
| 13885 | out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1); | ||
| 13886 | } | ||
| 13887 | |||
| 13888 | -/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13889 | +/* { dg-final { scan-assembler "vshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13890 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13891 | |||
| 13892 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c' | ||
| 13893 | --- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c 2010-07-29 15:38:15 +0000 | ||
| 13894 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c 2010-08-20 13:27:11 +0000 | ||
| 13895 | @@ -17,5 +17,5 @@ | ||
| 13896 | out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1); | ||
| 13897 | } | ||
| 13898 | |||
| 13899 | -/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13900 | +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13901 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13902 | |||
| 13903 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c' | ||
| 13904 | --- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c 2010-07-29 15:38:15 +0000 | ||
| 13905 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c 2010-08-20 13:27:11 +0000 | ||
| 13906 | @@ -17,5 +17,5 @@ | ||
| 13907 | out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1); | ||
| 13908 | } | ||
| 13909 | |||
| 13910 | -/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13911 | +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13912 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13913 | |||
| 13914 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c' | ||
| 13915 | --- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 13916 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 13917 | @@ -17,5 +17,5 @@ | ||
| 13918 | out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); | ||
| 13919 | } | ||
| 13920 | |||
| 13921 | -/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13922 | +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13923 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13924 | |||
| 13925 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c' | ||
| 13926 | --- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 13927 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 13928 | @@ -17,5 +17,5 @@ | ||
| 13929 | out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); | ||
| 13930 | } | ||
| 13931 | |||
| 13932 | -/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13933 | +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13934 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13935 | |||
| 13936 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c' | ||
| 13937 | --- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 13938 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 13939 | @@ -17,5 +17,5 @@ | ||
| 13940 | out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); | ||
| 13941 | } | ||
| 13942 | |||
| 13943 | -/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13944 | +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13945 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13946 | |||
| 13947 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c' | ||
| 13948 | --- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 13949 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 13950 | @@ -17,5 +17,5 @@ | ||
| 13951 | out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); | ||
| 13952 | } | ||
| 13953 | |||
| 13954 | -/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13955 | +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13956 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13957 | |||
| 13958 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c' | ||
| 13959 | --- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 13960 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 13961 | @@ -17,5 +17,5 @@ | ||
| 13962 | out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); | ||
| 13963 | } | ||
| 13964 | |||
| 13965 | -/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13966 | +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13967 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13968 | |||
| 13969 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c' | ||
| 13970 | --- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 13971 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 13972 | @@ -17,5 +17,5 @@ | ||
| 13973 | out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); | ||
| 13974 | } | ||
| 13975 | |||
| 13976 | -/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13977 | +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13978 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13979 | |||
| 13980 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c' | ||
| 13981 | --- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 13982 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 13983 | @@ -17,5 +17,5 @@ | ||
| 13984 | out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); | ||
| 13985 | } | ||
| 13986 | |||
| 13987 | -/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13988 | +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 13989 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 13990 | |||
| 13991 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c' | ||
| 13992 | --- old/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 13993 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 13994 | @@ -17,5 +17,5 @@ | ||
| 13995 | out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); | ||
| 13996 | } | ||
| 13997 | |||
| 13998 | -/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 13999 | +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14000 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14001 | |||
| 14002 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_np16.c' | ||
| 14003 | --- old/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c 2010-07-29 15:38:15 +0000 | ||
| 14004 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c 2010-08-20 13:27:11 +0000 | ||
| 14005 | @@ -17,5 +17,5 @@ | ||
| 14006 | out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1); | ||
| 14007 | } | ||
| 14008 | |||
| 14009 | -/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14010 | +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14011 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14012 | |||
| 14013 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_np8.c' | ||
| 14014 | --- old/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c 2010-07-29 15:38:15 +0000 | ||
| 14015 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c 2010-08-20 13:27:11 +0000 | ||
| 14016 | @@ -17,5 +17,5 @@ | ||
| 14017 | out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1); | ||
| 14018 | } | ||
| 14019 | |||
| 14020 | -/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14021 | +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14022 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14023 | |||
| 14024 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c' | ||
| 14025 | --- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 14026 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 14027 | @@ -17,5 +17,5 @@ | ||
| 14028 | out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); | ||
| 14029 | } | ||
| 14030 | |||
| 14031 | -/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14032 | +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14033 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14034 | |||
| 14035 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c' | ||
| 14036 | --- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 14037 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 14038 | @@ -17,5 +17,5 @@ | ||
| 14039 | out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); | ||
| 14040 | } | ||
| 14041 | |||
| 14042 | -/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14043 | +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14044 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14045 | |||
| 14046 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c' | ||
| 14047 | --- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 14048 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 14049 | @@ -17,5 +17,5 @@ | ||
| 14050 | out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); | ||
| 14051 | } | ||
| 14052 | |||
| 14053 | -/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14054 | +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14055 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14056 | |||
| 14057 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c' | ||
| 14058 | --- old/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 14059 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 14060 | @@ -17,5 +17,5 @@ | ||
| 14061 | out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); | ||
| 14062 | } | ||
| 14063 | |||
| 14064 | -/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14065 | +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14066 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14067 | |||
| 14068 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c' | ||
| 14069 | --- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 14070 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 14071 | @@ -17,5 +17,5 @@ | ||
| 14072 | out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); | ||
| 14073 | } | ||
| 14074 | |||
| 14075 | -/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14076 | +/* { dg-final { scan-assembler "vsli\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14077 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14078 | |||
| 14079 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c' | ||
| 14080 | --- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 14081 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 14082 | @@ -17,5 +17,5 @@ | ||
| 14083 | out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); | ||
| 14084 | } | ||
| 14085 | |||
| 14086 | -/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14087 | +/* { dg-final { scan-assembler "vsli\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14088 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14089 | |||
| 14090 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c' | ||
| 14091 | --- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 14092 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 14093 | @@ -17,5 +17,5 @@ | ||
| 14094 | out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); | ||
| 14095 | } | ||
| 14096 | |||
| 14097 | -/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14098 | +/* { dg-final { scan-assembler "vsli\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14099 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14100 | |||
| 14101 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c' | ||
| 14102 | --- old/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 14103 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 14104 | @@ -17,5 +17,5 @@ | ||
| 14105 | out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); | ||
| 14106 | } | ||
| 14107 | |||
| 14108 | -/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14109 | +/* { dg-final { scan-assembler "vsli\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14110 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14111 | |||
| 14112 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c' | ||
| 14113 | --- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 14114 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 14115 | @@ -17,5 +17,5 @@ | ||
| 14116 | out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); | ||
| 14117 | } | ||
| 14118 | |||
| 14119 | -/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14120 | +/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14121 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14122 | |||
| 14123 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c' | ||
| 14124 | --- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 14125 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 14126 | @@ -17,5 +17,5 @@ | ||
| 14127 | out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); | ||
| 14128 | } | ||
| 14129 | |||
| 14130 | -/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14131 | +/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14132 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14133 | |||
| 14134 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c' | ||
| 14135 | --- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 14136 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 14137 | @@ -17,5 +17,5 @@ | ||
| 14138 | out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); | ||
| 14139 | } | ||
| 14140 | |||
| 14141 | -/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14142 | +/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14143 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14144 | |||
| 14145 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c' | ||
| 14146 | --- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 14147 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 14148 | @@ -17,5 +17,5 @@ | ||
| 14149 | out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); | ||
| 14150 | } | ||
| 14151 | |||
| 14152 | -/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14153 | +/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14154 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14155 | |||
| 14156 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c' | ||
| 14157 | --- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 14158 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 14159 | @@ -17,5 +17,5 @@ | ||
| 14160 | out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); | ||
| 14161 | } | ||
| 14162 | |||
| 14163 | -/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14164 | +/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14165 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14166 | |||
| 14167 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c' | ||
| 14168 | --- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 14169 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 14170 | @@ -17,5 +17,5 @@ | ||
| 14171 | out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); | ||
| 14172 | } | ||
| 14173 | |||
| 14174 | -/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14175 | +/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14176 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14177 | |||
| 14178 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c' | ||
| 14179 | --- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 14180 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 14181 | @@ -17,5 +17,5 @@ | ||
| 14182 | out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); | ||
| 14183 | } | ||
| 14184 | |||
| 14185 | -/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14186 | +/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14187 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14188 | |||
| 14189 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c' | ||
| 14190 | --- old/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 14191 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 14192 | @@ -17,5 +17,5 @@ | ||
| 14193 | out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); | ||
| 14194 | } | ||
| 14195 | |||
| 14196 | -/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14197 | +/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14198 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14199 | |||
| 14200 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c' | ||
| 14201 | --- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 14202 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 14203 | @@ -17,5 +17,5 @@ | ||
| 14204 | out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); | ||
| 14205 | } | ||
| 14206 | |||
| 14207 | -/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14208 | +/* { dg-final { scan-assembler "vsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14209 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14210 | |||
| 14211 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c' | ||
| 14212 | --- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 14213 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 14214 | @@ -17,5 +17,5 @@ | ||
| 14215 | out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); | ||
| 14216 | } | ||
| 14217 | |||
| 14218 | -/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14219 | +/* { dg-final { scan-assembler "vsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14220 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14221 | |||
| 14222 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c' | ||
| 14223 | --- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 14224 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 14225 | @@ -17,5 +17,5 @@ | ||
| 14226 | out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); | ||
| 14227 | } | ||
| 14228 | |||
| 14229 | -/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14230 | +/* { dg-final { scan-assembler "vsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14231 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14232 | |||
| 14233 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c' | ||
| 14234 | --- old/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 14235 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 14236 | @@ -17,5 +17,5 @@ | ||
| 14237 | out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); | ||
| 14238 | } | ||
| 14239 | |||
| 14240 | -/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14241 | +/* { dg-final { scan-assembler "vsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14242 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14243 | |||
| 14244 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c' | ||
| 14245 | --- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 14246 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 14247 | @@ -17,5 +17,5 @@ | ||
| 14248 | out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); | ||
| 14249 | } | ||
| 14250 | |||
| 14251 | -/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14252 | +/* { dg-final { scan-assembler "vsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14253 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14254 | |||
| 14255 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c' | ||
| 14256 | --- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 14257 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 14258 | @@ -17,5 +17,5 @@ | ||
| 14259 | out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); | ||
| 14260 | } | ||
| 14261 | |||
| 14262 | -/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14263 | +/* { dg-final { scan-assembler "vsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14264 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14265 | |||
| 14266 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c' | ||
| 14267 | --- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 14268 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 14269 | @@ -17,5 +17,5 @@ | ||
| 14270 | out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); | ||
| 14271 | } | ||
| 14272 | |||
| 14273 | -/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14274 | +/* { dg-final { scan-assembler "vsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14275 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14276 | |||
| 14277 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c' | ||
| 14278 | --- old/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 14279 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 14280 | @@ -17,5 +17,5 @@ | ||
| 14281 | out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); | ||
| 14282 | } | ||
| 14283 | |||
| 14284 | -/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14285 | +/* { dg-final { scan-assembler "vsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14286 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14287 | |||
| 14288 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c' | ||
| 14289 | --- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c 2010-07-29 15:38:15 +0000 | ||
| 14290 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c 2010-08-20 13:27:11 +0000 | ||
| 14291 | @@ -17,5 +17,5 @@ | ||
| 14292 | out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1); | ||
| 14293 | } | ||
| 14294 | |||
| 14295 | -/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14296 | +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14297 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14298 | |||
| 14299 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c' | ||
| 14300 | --- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c 2010-07-29 15:38:15 +0000 | ||
| 14301 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c 2010-08-20 13:27:11 +0000 | ||
| 14302 | @@ -17,5 +17,5 @@ | ||
| 14303 | out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1); | ||
| 14304 | } | ||
| 14305 | |||
| 14306 | -/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14307 | +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14308 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14309 | |||
| 14310 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c' | ||
| 14311 | --- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 14312 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 14313 | @@ -17,5 +17,5 @@ | ||
| 14314 | out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1); | ||
| 14315 | } | ||
| 14316 | |||
| 14317 | -/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14318 | +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14319 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14320 | |||
| 14321 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c' | ||
| 14322 | --- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 14323 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 14324 | @@ -17,5 +17,5 @@ | ||
| 14325 | out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1); | ||
| 14326 | } | ||
| 14327 | |||
| 14328 | -/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14329 | +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14330 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14331 | |||
| 14332 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c' | ||
| 14333 | --- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 14334 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 14335 | @@ -17,5 +17,5 @@ | ||
| 14336 | out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1); | ||
| 14337 | } | ||
| 14338 | |||
| 14339 | -/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14340 | +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14341 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14342 | |||
| 14343 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c' | ||
| 14344 | --- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 14345 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 14346 | @@ -17,5 +17,5 @@ | ||
| 14347 | out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1); | ||
| 14348 | } | ||
| 14349 | |||
| 14350 | -/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14351 | +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14352 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14353 | |||
| 14354 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c' | ||
| 14355 | --- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 14356 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 14357 | @@ -17,5 +17,5 @@ | ||
| 14358 | out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1); | ||
| 14359 | } | ||
| 14360 | |||
| 14361 | -/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14362 | +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14363 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14364 | |||
| 14365 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c' | ||
| 14366 | --- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 14367 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 14368 | @@ -17,5 +17,5 @@ | ||
| 14369 | out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1); | ||
| 14370 | } | ||
| 14371 | |||
| 14372 | -/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14373 | +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14374 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14375 | |||
| 14376 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c' | ||
| 14377 | --- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 14378 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 14379 | @@ -17,5 +17,5 @@ | ||
| 14380 | out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1); | ||
| 14381 | } | ||
| 14382 | |||
| 14383 | -/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14384 | +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14385 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14386 | |||
| 14387 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c' | ||
| 14388 | --- old/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 14389 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 14390 | @@ -17,5 +17,5 @@ | ||
| 14391 | out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1); | ||
| 14392 | } | ||
| 14393 | |||
| 14394 | -/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14395 | +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14396 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14397 | |||
| 14398 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_np16.c' | ||
| 14399 | --- old/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c 2010-07-29 15:38:15 +0000 | ||
| 14400 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c 2010-08-20 13:27:11 +0000 | ||
| 14401 | @@ -17,5 +17,5 @@ | ||
| 14402 | out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1); | ||
| 14403 | } | ||
| 14404 | |||
| 14405 | -/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14406 | +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14407 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14408 | |||
| 14409 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_np8.c' | ||
| 14410 | --- old/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c 2010-07-29 15:38:15 +0000 | ||
| 14411 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c 2010-08-20 13:27:11 +0000 | ||
| 14412 | @@ -17,5 +17,5 @@ | ||
| 14413 | out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1); | ||
| 14414 | } | ||
| 14415 | |||
| 14416 | -/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14417 | +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14418 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14419 | |||
| 14420 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c' | ||
| 14421 | --- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c 2010-07-29 15:38:15 +0000 | ||
| 14422 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c 2010-08-20 13:27:11 +0000 | ||
| 14423 | @@ -17,5 +17,5 @@ | ||
| 14424 | out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1); | ||
| 14425 | } | ||
| 14426 | |||
| 14427 | -/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14428 | +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14429 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14430 | |||
| 14431 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c' | ||
| 14432 | --- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c 2010-07-29 15:38:15 +0000 | ||
| 14433 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c 2010-08-20 13:27:11 +0000 | ||
| 14434 | @@ -17,5 +17,5 @@ | ||
| 14435 | out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1); | ||
| 14436 | } | ||
| 14437 | |||
| 14438 | -/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14439 | +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14440 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14441 | |||
| 14442 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c' | ||
| 14443 | --- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c 2010-07-29 15:38:15 +0000 | ||
| 14444 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c 2010-08-20 13:27:11 +0000 | ||
| 14445 | @@ -17,5 +17,5 @@ | ||
| 14446 | out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1); | ||
| 14447 | } | ||
| 14448 | |||
| 14449 | -/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14450 | +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14451 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14452 | |||
| 14453 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c' | ||
| 14454 | --- old/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c 2010-07-29 15:38:15 +0000 | ||
| 14455 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c 2010-08-20 13:27:11 +0000 | ||
| 14456 | @@ -17,5 +17,5 @@ | ||
| 14457 | out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1); | ||
| 14458 | } | ||
| 14459 | |||
| 14460 | -/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14461 | +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14462 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14463 | |||
| 14464 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c' | ||
| 14465 | --- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c 2010-07-29 15:38:15 +0000 | ||
| 14466 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c 2010-08-20 13:27:11 +0000 | ||
| 14467 | @@ -17,5 +17,5 @@ | ||
| 14468 | out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1); | ||
| 14469 | } | ||
| 14470 | |||
| 14471 | -/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14472 | +/* { dg-final { scan-assembler "vsri\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14473 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14474 | |||
| 14475 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c' | ||
| 14476 | --- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c 2010-07-29 15:38:15 +0000 | ||
| 14477 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c 2010-08-20 13:27:11 +0000 | ||
| 14478 | @@ -17,5 +17,5 @@ | ||
| 14479 | out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1); | ||
| 14480 | } | ||
| 14481 | |||
| 14482 | -/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14483 | +/* { dg-final { scan-assembler "vsri\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14484 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14485 | |||
| 14486 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c' | ||
| 14487 | --- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c 2010-07-29 15:38:15 +0000 | ||
| 14488 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c 2010-08-20 13:27:11 +0000 | ||
| 14489 | @@ -17,5 +17,5 @@ | ||
| 14490 | out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1); | ||
| 14491 | } | ||
| 14492 | |||
| 14493 | -/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14494 | +/* { dg-final { scan-assembler "vsri\.64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14495 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14496 | |||
| 14497 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c' | ||
| 14498 | --- old/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c 2010-07-29 15:38:15 +0000 | ||
| 14499 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c 2010-08-20 13:27:11 +0000 | ||
| 14500 | @@ -17,5 +17,5 @@ | ||
| 14501 | out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1); | ||
| 14502 | } | ||
| 14503 | |||
| 14504 | -/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14505 | +/* { dg-final { scan-assembler "vsri\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14506 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14507 | |||
| 14508 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c' | ||
| 14509 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 14510 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 14511 | @@ -16,5 +16,5 @@ | ||
| 14512 | vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); | ||
| 14513 | } | ||
| 14514 | |||
| 14515 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14516 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14517 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14518 | |||
| 14519 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c' | ||
| 14520 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 14521 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 14522 | @@ -16,5 +16,5 @@ | ||
| 14523 | vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); | ||
| 14524 | } | ||
| 14525 | |||
| 14526 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14527 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14528 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14529 | |||
| 14530 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c' | ||
| 14531 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 14532 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 14533 | @@ -16,5 +16,5 @@ | ||
| 14534 | vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); | ||
| 14535 | } | ||
| 14536 | |||
| 14537 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14538 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14539 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14540 | |||
| 14541 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c' | ||
| 14542 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 14543 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 14544 | @@ -16,5 +16,5 @@ | ||
| 14545 | vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); | ||
| 14546 | } | ||
| 14547 | |||
| 14548 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14549 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14550 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14551 | |||
| 14552 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c' | ||
| 14553 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 14554 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 14555 | @@ -16,5 +16,5 @@ | ||
| 14556 | vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); | ||
| 14557 | } | ||
| 14558 | |||
| 14559 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14560 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14561 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14562 | |||
| 14563 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c' | ||
| 14564 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2010-07-29 15:38:15 +0000 | ||
| 14565 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2010-08-20 13:27:11 +0000 | ||
| 14566 | @@ -16,5 +16,5 @@ | ||
| 14567 | vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1); | ||
| 14568 | } | ||
| 14569 | |||
| 14570 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14571 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14572 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14573 | |||
| 14574 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c' | ||
| 14575 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 14576 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 14577 | @@ -16,5 +16,5 @@ | ||
| 14578 | vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); | ||
| 14579 | } | ||
| 14580 | |||
| 14581 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14582 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14583 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14584 | |||
| 14585 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c' | ||
| 14586 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 14587 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 14588 | @@ -16,5 +16,5 @@ | ||
| 14589 | vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); | ||
| 14590 | } | ||
| 14591 | |||
| 14592 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14593 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14594 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14595 | |||
| 14596 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c' | ||
| 14597 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 14598 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 14599 | @@ -16,5 +16,5 @@ | ||
| 14600 | vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); | ||
| 14601 | } | ||
| 14602 | |||
| 14603 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14604 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14605 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14606 | |||
| 14607 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c' | ||
| 14608 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2010-07-29 15:38:15 +0000 | ||
| 14609 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2010-08-20 13:27:11 +0000 | ||
| 14610 | @@ -16,5 +16,5 @@ | ||
| 14611 | vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1); | ||
| 14612 | } | ||
| 14613 | |||
| 14614 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14615 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14616 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14617 | |||
| 14618 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c' | ||
| 14619 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 14620 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 14621 | @@ -16,5 +16,5 @@ | ||
| 14622 | vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); | ||
| 14623 | } | ||
| 14624 | |||
| 14625 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14626 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14627 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14628 | |||
| 14629 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c' | ||
| 14630 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2010-07-29 15:38:15 +0000 | ||
| 14631 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 14632 | @@ -16,5 +16,5 @@ | ||
| 14633 | vst1q_f32 (arg0_float32_t, arg1_float32x4_t); | ||
| 14634 | } | ||
| 14635 | |||
| 14636 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14637 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14638 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14639 | |||
| 14640 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c' | ||
| 14641 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2010-07-29 15:38:15 +0000 | ||
| 14642 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 14643 | @@ -16,5 +16,5 @@ | ||
| 14644 | vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t); | ||
| 14645 | } | ||
| 14646 | |||
| 14647 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14648 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14649 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14650 | |||
| 14651 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c' | ||
| 14652 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2010-07-29 15:38:15 +0000 | ||
| 14653 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 14654 | @@ -16,5 +16,5 @@ | ||
| 14655 | vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t); | ||
| 14656 | } | ||
| 14657 | |||
| 14658 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14659 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14660 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14661 | |||
| 14662 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c' | ||
| 14663 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2010-07-29 15:38:15 +0000 | ||
| 14664 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 14665 | @@ -16,5 +16,5 @@ | ||
| 14666 | vst1q_s16 (arg0_int16_t, arg1_int16x8_t); | ||
| 14667 | } | ||
| 14668 | |||
| 14669 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14670 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14671 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14672 | |||
| 14673 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c' | ||
| 14674 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2010-07-29 15:38:15 +0000 | ||
| 14675 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 14676 | @@ -16,5 +16,5 @@ | ||
| 14677 | vst1q_s32 (arg0_int32_t, arg1_int32x4_t); | ||
| 14678 | } | ||
| 14679 | |||
| 14680 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14681 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14682 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14683 | |||
| 14684 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c' | ||
| 14685 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2010-07-29 15:38:15 +0000 | ||
| 14686 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2010-08-20 13:27:11 +0000 | ||
| 14687 | @@ -16,5 +16,5 @@ | ||
| 14688 | vst1q_s64 (arg0_int64_t, arg1_int64x2_t); | ||
| 14689 | } | ||
| 14690 | |||
| 14691 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14692 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14693 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14694 | |||
| 14695 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c' | ||
| 14696 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2010-07-29 15:38:15 +0000 | ||
| 14697 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 14698 | @@ -16,5 +16,5 @@ | ||
| 14699 | vst1q_s8 (arg0_int8_t, arg1_int8x16_t); | ||
| 14700 | } | ||
| 14701 | |||
| 14702 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14703 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14704 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14705 | |||
| 14706 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c' | ||
| 14707 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2010-07-29 15:38:15 +0000 | ||
| 14708 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 14709 | @@ -16,5 +16,5 @@ | ||
| 14710 | vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t); | ||
| 14711 | } | ||
| 14712 | |||
| 14713 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14714 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14715 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14716 | |||
| 14717 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c' | ||
| 14718 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2010-07-29 15:38:15 +0000 | ||
| 14719 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 14720 | @@ -16,5 +16,5 @@ | ||
| 14721 | vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t); | ||
| 14722 | } | ||
| 14723 | |||
| 14724 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14725 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14726 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14727 | |||
| 14728 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c' | ||
| 14729 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2010-07-29 15:38:15 +0000 | ||
| 14730 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2010-08-20 13:27:11 +0000 | ||
| 14731 | @@ -16,5 +16,5 @@ | ||
| 14732 | vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t); | ||
| 14733 | } | ||
| 14734 | |||
| 14735 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14736 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14737 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14738 | |||
| 14739 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c' | ||
| 14740 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2010-07-29 15:38:15 +0000 | ||
| 14741 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 14742 | @@ -16,5 +16,5 @@ | ||
| 14743 | vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t); | ||
| 14744 | } | ||
| 14745 | |||
| 14746 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14747 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14748 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14749 | |||
| 14750 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c' | ||
| 14751 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 14752 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 14753 | @@ -16,5 +16,5 @@ | ||
| 14754 | vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); | ||
| 14755 | } | ||
| 14756 | |||
| 14757 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14758 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14759 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14760 | |||
| 14761 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c' | ||
| 14762 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 14763 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 14764 | @@ -16,5 +16,5 @@ | ||
| 14765 | vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); | ||
| 14766 | } | ||
| 14767 | |||
| 14768 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14769 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14770 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14771 | |||
| 14772 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c' | ||
| 14773 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 14774 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 14775 | @@ -16,5 +16,5 @@ | ||
| 14776 | vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); | ||
| 14777 | } | ||
| 14778 | |||
| 14779 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14780 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14781 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14782 | |||
| 14783 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c' | ||
| 14784 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 14785 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 14786 | @@ -16,5 +16,5 @@ | ||
| 14787 | vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); | ||
| 14788 | } | ||
| 14789 | |||
| 14790 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14791 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14792 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14793 | |||
| 14794 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c' | ||
| 14795 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 14796 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 14797 | @@ -16,5 +16,5 @@ | ||
| 14798 | vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); | ||
| 14799 | } | ||
| 14800 | |||
| 14801 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14802 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14803 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14804 | |||
| 14805 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c' | ||
| 14806 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2010-07-29 15:38:15 +0000 | ||
| 14807 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2010-08-20 13:27:11 +0000 | ||
| 14808 | @@ -16,5 +16,5 @@ | ||
| 14809 | vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); | ||
| 14810 | } | ||
| 14811 | |||
| 14812 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14813 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14814 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14815 | |||
| 14816 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c' | ||
| 14817 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 14818 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 14819 | @@ -16,5 +16,5 @@ | ||
| 14820 | vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); | ||
| 14821 | } | ||
| 14822 | |||
| 14823 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14824 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14825 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14826 | |||
| 14827 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c' | ||
| 14828 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 14829 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 14830 | @@ -16,5 +16,5 @@ | ||
| 14831 | vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); | ||
| 14832 | } | ||
| 14833 | |||
| 14834 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14835 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14836 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14837 | |||
| 14838 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c' | ||
| 14839 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 14840 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 14841 | @@ -16,5 +16,5 @@ | ||
| 14842 | vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); | ||
| 14843 | } | ||
| 14844 | |||
| 14845 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14846 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14847 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14848 | |||
| 14849 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c' | ||
| 14850 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2010-07-29 15:38:15 +0000 | ||
| 14851 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2010-08-20 13:27:11 +0000 | ||
| 14852 | @@ -16,5 +16,5 @@ | ||
| 14853 | vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); | ||
| 14854 | } | ||
| 14855 | |||
| 14856 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14857 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14858 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14859 | |||
| 14860 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c' | ||
| 14861 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 14862 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 14863 | @@ -16,5 +16,5 @@ | ||
| 14864 | vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); | ||
| 14865 | } | ||
| 14866 | |||
| 14867 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14868 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14869 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14870 | |||
| 14871 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1f32.c' | ||
| 14872 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2010-07-29 15:38:15 +0000 | ||
| 14873 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2010-08-20 13:27:11 +0000 | ||
| 14874 | @@ -16,5 +16,5 @@ | ||
| 14875 | vst1_f32 (arg0_float32_t, arg1_float32x2_t); | ||
| 14876 | } | ||
| 14877 | |||
| 14878 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14879 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14880 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14881 | |||
| 14882 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p16.c' | ||
| 14883 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2010-07-29 15:38:15 +0000 | ||
| 14884 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2010-08-20 13:27:11 +0000 | ||
| 14885 | @@ -16,5 +16,5 @@ | ||
| 14886 | vst1_p16 (arg0_poly16_t, arg1_poly16x4_t); | ||
| 14887 | } | ||
| 14888 | |||
| 14889 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14890 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14891 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14892 | |||
| 14893 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p8.c' | ||
| 14894 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2010-07-29 15:38:15 +0000 | ||
| 14895 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2010-08-20 13:27:11 +0000 | ||
| 14896 | @@ -16,5 +16,5 @@ | ||
| 14897 | vst1_p8 (arg0_poly8_t, arg1_poly8x8_t); | ||
| 14898 | } | ||
| 14899 | |||
| 14900 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14901 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14902 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14903 | |||
| 14904 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s16.c' | ||
| 14905 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2010-07-29 15:38:15 +0000 | ||
| 14906 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2010-08-20 13:27:11 +0000 | ||
| 14907 | @@ -16,5 +16,5 @@ | ||
| 14908 | vst1_s16 (arg0_int16_t, arg1_int16x4_t); | ||
| 14909 | } | ||
| 14910 | |||
| 14911 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14912 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14913 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14914 | |||
| 14915 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s32.c' | ||
| 14916 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2010-07-29 15:38:15 +0000 | ||
| 14917 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2010-08-20 13:27:11 +0000 | ||
| 14918 | @@ -16,5 +16,5 @@ | ||
| 14919 | vst1_s32 (arg0_int32_t, arg1_int32x2_t); | ||
| 14920 | } | ||
| 14921 | |||
| 14922 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14923 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14924 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14925 | |||
| 14926 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s64.c' | ||
| 14927 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2010-07-29 15:38:15 +0000 | ||
| 14928 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2010-08-20 13:27:11 +0000 | ||
| 14929 | @@ -16,5 +16,5 @@ | ||
| 14930 | vst1_s64 (arg0_int64_t, arg1_int64x1_t); | ||
| 14931 | } | ||
| 14932 | |||
| 14933 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14934 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14935 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14936 | |||
| 14937 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s8.c' | ||
| 14938 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2010-07-29 15:38:15 +0000 | ||
| 14939 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2010-08-20 13:27:11 +0000 | ||
| 14940 | @@ -16,5 +16,5 @@ | ||
| 14941 | vst1_s8 (arg0_int8_t, arg1_int8x8_t); | ||
| 14942 | } | ||
| 14943 | |||
| 14944 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14945 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14946 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14947 | |||
| 14948 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u16.c' | ||
| 14949 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2010-07-29 15:38:15 +0000 | ||
| 14950 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2010-08-20 13:27:11 +0000 | ||
| 14951 | @@ -16,5 +16,5 @@ | ||
| 14952 | vst1_u16 (arg0_uint16_t, arg1_uint16x4_t); | ||
| 14953 | } | ||
| 14954 | |||
| 14955 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14956 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14957 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14958 | |||
| 14959 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u32.c' | ||
| 14960 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2010-07-29 15:38:15 +0000 | ||
| 14961 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2010-08-20 13:27:11 +0000 | ||
| 14962 | @@ -16,5 +16,5 @@ | ||
| 14963 | vst1_u32 (arg0_uint32_t, arg1_uint32x2_t); | ||
| 14964 | } | ||
| 14965 | |||
| 14966 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14967 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14968 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14969 | |||
| 14970 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u64.c' | ||
| 14971 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2010-07-29 15:38:15 +0000 | ||
| 14972 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2010-08-20 13:27:11 +0000 | ||
| 14973 | @@ -16,5 +16,5 @@ | ||
| 14974 | vst1_u64 (arg0_uint64_t, arg1_uint64x1_t); | ||
| 14975 | } | ||
| 14976 | |||
| 14977 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14978 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14979 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14980 | |||
| 14981 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u8.c' | ||
| 14982 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2010-07-29 15:38:15 +0000 | ||
| 14983 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2010-08-20 13:27:11 +0000 | ||
| 14984 | @@ -16,5 +16,5 @@ | ||
| 14985 | vst1_u8 (arg0_uint8_t, arg1_uint8x8_t); | ||
| 14986 | } | ||
| 14987 | |||
| 14988 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 14989 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 14990 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 14991 | |||
| 14992 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c' | ||
| 14993 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 14994 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 14995 | @@ -16,5 +16,5 @@ | ||
| 14996 | vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1); | ||
| 14997 | } | ||
| 14998 | |||
| 14999 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15000 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15001 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15002 | |||
| 15003 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c' | ||
| 15004 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 15005 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 15006 | @@ -16,5 +16,5 @@ | ||
| 15007 | vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1); | ||
| 15008 | } | ||
| 15009 | |||
| 15010 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15011 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15012 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15013 | |||
| 15014 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c' | ||
| 15015 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 15016 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 15017 | @@ -16,5 +16,5 @@ | ||
| 15018 | vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1); | ||
| 15019 | } | ||
| 15020 | |||
| 15021 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15022 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15023 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15024 | |||
| 15025 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c' | ||
| 15026 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 15027 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 15028 | @@ -16,5 +16,5 @@ | ||
| 15029 | vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1); | ||
| 15030 | } | ||
| 15031 | |||
| 15032 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15033 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15034 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15035 | |||
| 15036 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c' | ||
| 15037 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 15038 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 15039 | @@ -16,5 +16,5 @@ | ||
| 15040 | vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1); | ||
| 15041 | } | ||
| 15042 | |||
| 15043 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15044 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15045 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15046 | |||
| 15047 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c' | ||
| 15048 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 15049 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 15050 | @@ -16,5 +16,5 @@ | ||
| 15051 | vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1); | ||
| 15052 | } | ||
| 15053 | |||
| 15054 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15055 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15056 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15057 | |||
| 15058 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c' | ||
| 15059 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2010-07-29 15:38:15 +0000 | ||
| 15060 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 15061 | @@ -16,6 +16,6 @@ | ||
| 15062 | vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t); | ||
| 15063 | } | ||
| 15064 | |||
| 15065 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15066 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15067 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15068 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15069 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15070 | |||
| 15071 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c' | ||
| 15072 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2010-07-29 15:38:15 +0000 | ||
| 15073 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 15074 | @@ -16,6 +16,6 @@ | ||
| 15075 | vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t); | ||
| 15076 | } | ||
| 15077 | |||
| 15078 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15079 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15080 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15081 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15082 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15083 | |||
| 15084 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c' | ||
| 15085 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2010-07-29 15:38:15 +0000 | ||
| 15086 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 15087 | @@ -16,6 +16,6 @@ | ||
| 15088 | vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t); | ||
| 15089 | } | ||
| 15090 | |||
| 15091 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15092 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15093 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15094 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15095 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15096 | |||
| 15097 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c' | ||
| 15098 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2010-07-29 15:38:15 +0000 | ||
| 15099 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 15100 | @@ -16,6 +16,6 @@ | ||
| 15101 | vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t); | ||
| 15102 | } | ||
| 15103 | |||
| 15104 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15105 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15106 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15107 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15108 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15109 | |||
| 15110 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c' | ||
| 15111 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2010-07-29 15:38:15 +0000 | ||
| 15112 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 15113 | @@ -16,6 +16,6 @@ | ||
| 15114 | vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t); | ||
| 15115 | } | ||
| 15116 | |||
| 15117 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15118 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15119 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15120 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15121 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15122 | |||
| 15123 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c' | ||
| 15124 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2010-07-29 15:38:15 +0000 | ||
| 15125 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 15126 | @@ -16,6 +16,6 @@ | ||
| 15127 | vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t); | ||
| 15128 | } | ||
| 15129 | |||
| 15130 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15131 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15132 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15133 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15134 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15135 | |||
| 15136 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c' | ||
| 15137 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2010-07-29 15:38:15 +0000 | ||
| 15138 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 15139 | @@ -16,6 +16,6 @@ | ||
| 15140 | vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t); | ||
| 15141 | } | ||
| 15142 | |||
| 15143 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15144 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15145 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15146 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15147 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15148 | |||
| 15149 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c' | ||
| 15150 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2010-07-29 15:38:15 +0000 | ||
| 15151 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 15152 | @@ -16,6 +16,6 @@ | ||
| 15153 | vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t); | ||
| 15154 | } | ||
| 15155 | |||
| 15156 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15157 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15158 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15159 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15160 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15161 | |||
| 15162 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c' | ||
| 15163 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2010-07-29 15:38:15 +0000 | ||
| 15164 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 15165 | @@ -16,6 +16,6 @@ | ||
| 15166 | vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t); | ||
| 15167 | } | ||
| 15168 | |||
| 15169 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15170 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15171 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15172 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15173 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15174 | |||
| 15175 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c' | ||
| 15176 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 15177 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 15178 | @@ -16,5 +16,5 @@ | ||
| 15179 | vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1); | ||
| 15180 | } | ||
| 15181 | |||
| 15182 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15183 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15184 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15185 | |||
| 15186 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c' | ||
| 15187 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 15188 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 15189 | @@ -16,5 +16,5 @@ | ||
| 15190 | vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1); | ||
| 15191 | } | ||
| 15192 | |||
| 15193 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15194 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15195 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15196 | |||
| 15197 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c' | ||
| 15198 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 15199 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 15200 | @@ -16,5 +16,5 @@ | ||
| 15201 | vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1); | ||
| 15202 | } | ||
| 15203 | |||
| 15204 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15205 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15206 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15207 | |||
| 15208 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c' | ||
| 15209 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 15210 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 15211 | @@ -16,5 +16,5 @@ | ||
| 15212 | vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1); | ||
| 15213 | } | ||
| 15214 | |||
| 15215 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15216 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15217 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15218 | |||
| 15219 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c' | ||
| 15220 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 15221 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 15222 | @@ -16,5 +16,5 @@ | ||
| 15223 | vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1); | ||
| 15224 | } | ||
| 15225 | |||
| 15226 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15227 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15228 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15229 | |||
| 15230 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c' | ||
| 15231 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 15232 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 15233 | @@ -16,5 +16,5 @@ | ||
| 15234 | vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1); | ||
| 15235 | } | ||
| 15236 | |||
| 15237 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15238 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15239 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15240 | |||
| 15241 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c' | ||
| 15242 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 15243 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 15244 | @@ -16,5 +16,5 @@ | ||
| 15245 | vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1); | ||
| 15246 | } | ||
| 15247 | |||
| 15248 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15249 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15250 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15251 | |||
| 15252 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c' | ||
| 15253 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 15254 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 15255 | @@ -16,5 +16,5 @@ | ||
| 15256 | vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1); | ||
| 15257 | } | ||
| 15258 | |||
| 15259 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15260 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15261 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15262 | |||
| 15263 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c' | ||
| 15264 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 15265 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 15266 | @@ -16,5 +16,5 @@ | ||
| 15267 | vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1); | ||
| 15268 | } | ||
| 15269 | |||
| 15270 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15271 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15272 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15273 | |||
| 15274 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2f32.c' | ||
| 15275 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2010-07-29 15:38:15 +0000 | ||
| 15276 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2010-08-20 13:27:11 +0000 | ||
| 15277 | @@ -16,5 +16,5 @@ | ||
| 15278 | vst2_f32 (arg0_float32_t, arg1_float32x2x2_t); | ||
| 15279 | } | ||
| 15280 | |||
| 15281 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15282 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15283 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15284 | |||
| 15285 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p16.c' | ||
| 15286 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2010-07-29 15:38:15 +0000 | ||
| 15287 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2010-08-20 13:27:11 +0000 | ||
| 15288 | @@ -16,5 +16,5 @@ | ||
| 15289 | vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t); | ||
| 15290 | } | ||
| 15291 | |||
| 15292 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15293 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15294 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15295 | |||
| 15296 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p8.c' | ||
| 15297 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2010-07-29 15:38:15 +0000 | ||
| 15298 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2010-08-20 13:27:11 +0000 | ||
| 15299 | @@ -16,5 +16,5 @@ | ||
| 15300 | vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t); | ||
| 15301 | } | ||
| 15302 | |||
| 15303 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15304 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15305 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15306 | |||
| 15307 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s16.c' | ||
| 15308 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2010-07-29 15:38:15 +0000 | ||
| 15309 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2010-08-20 13:27:11 +0000 | ||
| 15310 | @@ -16,5 +16,5 @@ | ||
| 15311 | vst2_s16 (arg0_int16_t, arg1_int16x4x2_t); | ||
| 15312 | } | ||
| 15313 | |||
| 15314 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15315 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15316 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15317 | |||
| 15318 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s32.c' | ||
| 15319 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2010-07-29 15:38:15 +0000 | ||
| 15320 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2010-08-20 13:27:11 +0000 | ||
| 15321 | @@ -16,5 +16,5 @@ | ||
| 15322 | vst2_s32 (arg0_int32_t, arg1_int32x2x2_t); | ||
| 15323 | } | ||
| 15324 | |||
| 15325 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15326 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15327 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15328 | |||
| 15329 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s64.c' | ||
| 15330 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2010-07-29 15:38:15 +0000 | ||
| 15331 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2010-08-20 13:27:11 +0000 | ||
| 15332 | @@ -16,5 +16,5 @@ | ||
| 15333 | vst2_s64 (arg0_int64_t, arg1_int64x1x2_t); | ||
| 15334 | } | ||
| 15335 | |||
| 15336 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15337 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15338 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15339 | |||
| 15340 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s8.c' | ||
| 15341 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2010-07-29 15:38:15 +0000 | ||
| 15342 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2010-08-20 13:27:11 +0000 | ||
| 15343 | @@ -16,5 +16,5 @@ | ||
| 15344 | vst2_s8 (arg0_int8_t, arg1_int8x8x2_t); | ||
| 15345 | } | ||
| 15346 | |||
| 15347 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15348 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15349 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15350 | |||
| 15351 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u16.c' | ||
| 15352 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2010-07-29 15:38:15 +0000 | ||
| 15353 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2010-08-20 13:27:11 +0000 | ||
| 15354 | @@ -16,5 +16,5 @@ | ||
| 15355 | vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t); | ||
| 15356 | } | ||
| 15357 | |||
| 15358 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15359 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15360 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15361 | |||
| 15362 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u32.c' | ||
| 15363 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2010-07-29 15:38:15 +0000 | ||
| 15364 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2010-08-20 13:27:11 +0000 | ||
| 15365 | @@ -16,5 +16,5 @@ | ||
| 15366 | vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t); | ||
| 15367 | } | ||
| 15368 | |||
| 15369 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15370 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15371 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15372 | |||
| 15373 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u64.c' | ||
| 15374 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2010-07-29 15:38:15 +0000 | ||
| 15375 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2010-08-20 13:27:11 +0000 | ||
| 15376 | @@ -16,5 +16,5 @@ | ||
| 15377 | vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t); | ||
| 15378 | } | ||
| 15379 | |||
| 15380 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15381 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15382 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15383 | |||
| 15384 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u8.c' | ||
| 15385 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2010-07-29 15:38:15 +0000 | ||
| 15386 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2010-08-20 13:27:11 +0000 | ||
| 15387 | @@ -16,5 +16,5 @@ | ||
| 15388 | vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t); | ||
| 15389 | } | ||
| 15390 | |||
| 15391 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15392 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15393 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15394 | |||
| 15395 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c' | ||
| 15396 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 15397 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 15398 | @@ -16,5 +16,5 @@ | ||
| 15399 | vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1); | ||
| 15400 | } | ||
| 15401 | |||
| 15402 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15403 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15404 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15405 | |||
| 15406 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c' | ||
| 15407 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 15408 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 15409 | @@ -16,5 +16,5 @@ | ||
| 15410 | vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1); | ||
| 15411 | } | ||
| 15412 | |||
| 15413 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15414 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15415 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15416 | |||
| 15417 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c' | ||
| 15418 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 15419 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 15420 | @@ -16,5 +16,5 @@ | ||
| 15421 | vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1); | ||
| 15422 | } | ||
| 15423 | |||
| 15424 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15425 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15426 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15427 | |||
| 15428 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c' | ||
| 15429 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 15430 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 15431 | @@ -16,5 +16,5 @@ | ||
| 15432 | vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1); | ||
| 15433 | } | ||
| 15434 | |||
| 15435 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15436 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15437 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15438 | |||
| 15439 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c' | ||
| 15440 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 15441 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 15442 | @@ -16,5 +16,5 @@ | ||
| 15443 | vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1); | ||
| 15444 | } | ||
| 15445 | |||
| 15446 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15447 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15448 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15449 | |||
| 15450 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c' | ||
| 15451 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 15452 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 15453 | @@ -16,5 +16,5 @@ | ||
| 15454 | vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1); | ||
| 15455 | } | ||
| 15456 | |||
| 15457 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15458 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15459 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15460 | |||
| 15461 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c' | ||
| 15462 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2010-07-29 15:38:15 +0000 | ||
| 15463 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 15464 | @@ -16,6 +16,6 @@ | ||
| 15465 | vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t); | ||
| 15466 | } | ||
| 15467 | |||
| 15468 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15469 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15470 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15471 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15472 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15473 | |||
| 15474 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c' | ||
| 15475 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2010-07-29 15:38:15 +0000 | ||
| 15476 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 15477 | @@ -16,6 +16,6 @@ | ||
| 15478 | vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t); | ||
| 15479 | } | ||
| 15480 | |||
| 15481 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15482 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15483 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15484 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15485 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15486 | |||
| 15487 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c' | ||
| 15488 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2010-07-29 15:38:15 +0000 | ||
| 15489 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 15490 | @@ -16,6 +16,6 @@ | ||
| 15491 | vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t); | ||
| 15492 | } | ||
| 15493 | |||
| 15494 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15495 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15496 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15497 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15498 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15499 | |||
| 15500 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c' | ||
| 15501 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2010-07-29 15:38:15 +0000 | ||
| 15502 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 15503 | @@ -16,6 +16,6 @@ | ||
| 15504 | vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t); | ||
| 15505 | } | ||
| 15506 | |||
| 15507 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15508 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15509 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15510 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15511 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15512 | |||
| 15513 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c' | ||
| 15514 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2010-07-29 15:38:15 +0000 | ||
| 15515 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 15516 | @@ -16,6 +16,6 @@ | ||
| 15517 | vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t); | ||
| 15518 | } | ||
| 15519 | |||
| 15520 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15521 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15522 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15523 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15524 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15525 | |||
| 15526 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c' | ||
| 15527 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2010-07-29 15:38:15 +0000 | ||
| 15528 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 15529 | @@ -16,6 +16,6 @@ | ||
| 15530 | vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t); | ||
| 15531 | } | ||
| 15532 | |||
| 15533 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15534 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15535 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15536 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15537 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15538 | |||
| 15539 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c' | ||
| 15540 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2010-07-29 15:38:15 +0000 | ||
| 15541 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 15542 | @@ -16,6 +16,6 @@ | ||
| 15543 | vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t); | ||
| 15544 | } | ||
| 15545 | |||
| 15546 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15547 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15548 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15549 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15550 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15551 | |||
| 15552 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c' | ||
| 15553 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2010-07-29 15:38:15 +0000 | ||
| 15554 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 15555 | @@ -16,6 +16,6 @@ | ||
| 15556 | vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t); | ||
| 15557 | } | ||
| 15558 | |||
| 15559 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15560 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15561 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15562 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15563 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15564 | |||
| 15565 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c' | ||
| 15566 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2010-07-29 15:38:15 +0000 | ||
| 15567 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 15568 | @@ -16,6 +16,6 @@ | ||
| 15569 | vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t); | ||
| 15570 | } | ||
| 15571 | |||
| 15572 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15573 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15574 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15575 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15576 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15577 | |||
| 15578 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c' | ||
| 15579 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 15580 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 15581 | @@ -16,5 +16,5 @@ | ||
| 15582 | vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1); | ||
| 15583 | } | ||
| 15584 | |||
| 15585 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15586 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15587 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15588 | |||
| 15589 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c' | ||
| 15590 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 15591 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 15592 | @@ -16,5 +16,5 @@ | ||
| 15593 | vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1); | ||
| 15594 | } | ||
| 15595 | |||
| 15596 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15597 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15598 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15599 | |||
| 15600 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c' | ||
| 15601 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 15602 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 15603 | @@ -16,5 +16,5 @@ | ||
| 15604 | vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1); | ||
| 15605 | } | ||
| 15606 | |||
| 15607 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15608 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15609 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15610 | |||
| 15611 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c' | ||
| 15612 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 15613 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 15614 | @@ -16,5 +16,5 @@ | ||
| 15615 | vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1); | ||
| 15616 | } | ||
| 15617 | |||
| 15618 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15619 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15620 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15621 | |||
| 15622 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c' | ||
| 15623 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 15624 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 15625 | @@ -16,5 +16,5 @@ | ||
| 15626 | vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1); | ||
| 15627 | } | ||
| 15628 | |||
| 15629 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15630 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15631 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15632 | |||
| 15633 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c' | ||
| 15634 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 15635 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 15636 | @@ -16,5 +16,5 @@ | ||
| 15637 | vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1); | ||
| 15638 | } | ||
| 15639 | |||
| 15640 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15641 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15642 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15643 | |||
| 15644 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c' | ||
| 15645 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 15646 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 15647 | @@ -16,5 +16,5 @@ | ||
| 15648 | vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1); | ||
| 15649 | } | ||
| 15650 | |||
| 15651 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15652 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15653 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15654 | |||
| 15655 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c' | ||
| 15656 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 15657 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 15658 | @@ -16,5 +16,5 @@ | ||
| 15659 | vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1); | ||
| 15660 | } | ||
| 15661 | |||
| 15662 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15663 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15664 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15665 | |||
| 15666 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c' | ||
| 15667 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 15668 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 15669 | @@ -16,5 +16,5 @@ | ||
| 15670 | vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1); | ||
| 15671 | } | ||
| 15672 | |||
| 15673 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15674 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15675 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15676 | |||
| 15677 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3f32.c' | ||
| 15678 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2010-07-29 15:38:15 +0000 | ||
| 15679 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2010-08-20 13:27:11 +0000 | ||
| 15680 | @@ -16,5 +16,5 @@ | ||
| 15681 | vst3_f32 (arg0_float32_t, arg1_float32x2x3_t); | ||
| 15682 | } | ||
| 15683 | |||
| 15684 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15685 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15686 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15687 | |||
| 15688 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p16.c' | ||
| 15689 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2010-07-29 15:38:15 +0000 | ||
| 15690 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2010-08-20 13:27:11 +0000 | ||
| 15691 | @@ -16,5 +16,5 @@ | ||
| 15692 | vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t); | ||
| 15693 | } | ||
| 15694 | |||
| 15695 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15696 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15697 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15698 | |||
| 15699 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p8.c' | ||
| 15700 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2010-07-29 15:38:15 +0000 | ||
| 15701 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2010-08-20 13:27:11 +0000 | ||
| 15702 | @@ -16,5 +16,5 @@ | ||
| 15703 | vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t); | ||
| 15704 | } | ||
| 15705 | |||
| 15706 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15707 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15708 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15709 | |||
| 15710 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s16.c' | ||
| 15711 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2010-07-29 15:38:15 +0000 | ||
| 15712 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2010-08-20 13:27:11 +0000 | ||
| 15713 | @@ -16,5 +16,5 @@ | ||
| 15714 | vst3_s16 (arg0_int16_t, arg1_int16x4x3_t); | ||
| 15715 | } | ||
| 15716 | |||
| 15717 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15718 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15719 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15720 | |||
| 15721 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s32.c' | ||
| 15722 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2010-07-29 15:38:15 +0000 | ||
| 15723 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2010-08-20 13:27:11 +0000 | ||
| 15724 | @@ -16,5 +16,5 @@ | ||
| 15725 | vst3_s32 (arg0_int32_t, arg1_int32x2x3_t); | ||
| 15726 | } | ||
| 15727 | |||
| 15728 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15729 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15730 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15731 | |||
| 15732 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s64.c' | ||
| 15733 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2010-07-29 15:38:15 +0000 | ||
| 15734 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2010-08-20 13:27:11 +0000 | ||
| 15735 | @@ -16,5 +16,5 @@ | ||
| 15736 | vst3_s64 (arg0_int64_t, arg1_int64x1x3_t); | ||
| 15737 | } | ||
| 15738 | |||
| 15739 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15740 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15741 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15742 | |||
| 15743 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s8.c' | ||
| 15744 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2010-07-29 15:38:15 +0000 | ||
| 15745 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2010-08-20 13:27:11 +0000 | ||
| 15746 | @@ -16,5 +16,5 @@ | ||
| 15747 | vst3_s8 (arg0_int8_t, arg1_int8x8x3_t); | ||
| 15748 | } | ||
| 15749 | |||
| 15750 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15751 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15752 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15753 | |||
| 15754 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u16.c' | ||
| 15755 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2010-07-29 15:38:15 +0000 | ||
| 15756 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2010-08-20 13:27:11 +0000 | ||
| 15757 | @@ -16,5 +16,5 @@ | ||
| 15758 | vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t); | ||
| 15759 | } | ||
| 15760 | |||
| 15761 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15762 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15763 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15764 | |||
| 15765 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u32.c' | ||
| 15766 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2010-07-29 15:38:15 +0000 | ||
| 15767 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2010-08-20 13:27:11 +0000 | ||
| 15768 | @@ -16,5 +16,5 @@ | ||
| 15769 | vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t); | ||
| 15770 | } | ||
| 15771 | |||
| 15772 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15773 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15774 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15775 | |||
| 15776 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u64.c' | ||
| 15777 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2010-07-29 15:38:15 +0000 | ||
| 15778 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2010-08-20 13:27:11 +0000 | ||
| 15779 | @@ -16,5 +16,5 @@ | ||
| 15780 | vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t); | ||
| 15781 | } | ||
| 15782 | |||
| 15783 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15784 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15785 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15786 | |||
| 15787 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u8.c' | ||
| 15788 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2010-07-29 15:38:15 +0000 | ||
| 15789 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2010-08-20 13:27:11 +0000 | ||
| 15790 | @@ -16,5 +16,5 @@ | ||
| 15791 | vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t); | ||
| 15792 | } | ||
| 15793 | |||
| 15794 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15795 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15796 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15797 | |||
| 15798 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c' | ||
| 15799 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 15800 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 15801 | @@ -16,5 +16,5 @@ | ||
| 15802 | vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1); | ||
| 15803 | } | ||
| 15804 | |||
| 15805 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15806 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15807 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15808 | |||
| 15809 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c' | ||
| 15810 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 15811 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 15812 | @@ -16,5 +16,5 @@ | ||
| 15813 | vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1); | ||
| 15814 | } | ||
| 15815 | |||
| 15816 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15817 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15818 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15819 | |||
| 15820 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c' | ||
| 15821 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 15822 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 15823 | @@ -16,5 +16,5 @@ | ||
| 15824 | vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1); | ||
| 15825 | } | ||
| 15826 | |||
| 15827 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15828 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15829 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15830 | |||
| 15831 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c' | ||
| 15832 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 15833 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 15834 | @@ -16,5 +16,5 @@ | ||
| 15835 | vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1); | ||
| 15836 | } | ||
| 15837 | |||
| 15838 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15839 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15840 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15841 | |||
| 15842 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c' | ||
| 15843 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 15844 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 15845 | @@ -16,5 +16,5 @@ | ||
| 15846 | vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1); | ||
| 15847 | } | ||
| 15848 | |||
| 15849 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15850 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15851 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15852 | |||
| 15853 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c' | ||
| 15854 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 15855 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 15856 | @@ -16,5 +16,5 @@ | ||
| 15857 | vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1); | ||
| 15858 | } | ||
| 15859 | |||
| 15860 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15861 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15862 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15863 | |||
| 15864 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c' | ||
| 15865 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2010-07-29 15:38:15 +0000 | ||
| 15866 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 15867 | @@ -16,6 +16,6 @@ | ||
| 15868 | vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t); | ||
| 15869 | } | ||
| 15870 | |||
| 15871 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15872 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15873 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15874 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15875 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15876 | |||
| 15877 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c' | ||
| 15878 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2010-07-29 15:38:15 +0000 | ||
| 15879 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 15880 | @@ -16,6 +16,6 @@ | ||
| 15881 | vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t); | ||
| 15882 | } | ||
| 15883 | |||
| 15884 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15885 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15886 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15887 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15888 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15889 | |||
| 15890 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c' | ||
| 15891 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2010-07-29 15:38:15 +0000 | ||
| 15892 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 15893 | @@ -16,6 +16,6 @@ | ||
| 15894 | vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t); | ||
| 15895 | } | ||
| 15896 | |||
| 15897 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15898 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15899 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15900 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15901 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15902 | |||
| 15903 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c' | ||
| 15904 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2010-07-29 15:38:15 +0000 | ||
| 15905 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 15906 | @@ -16,6 +16,6 @@ | ||
| 15907 | vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t); | ||
| 15908 | } | ||
| 15909 | |||
| 15910 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15911 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15912 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15913 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15914 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15915 | |||
| 15916 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c' | ||
| 15917 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2010-07-29 15:38:15 +0000 | ||
| 15918 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 15919 | @@ -16,6 +16,6 @@ | ||
| 15920 | vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t); | ||
| 15921 | } | ||
| 15922 | |||
| 15923 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15924 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15925 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15926 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15927 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15928 | |||
| 15929 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c' | ||
| 15930 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2010-07-29 15:38:15 +0000 | ||
| 15931 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 15932 | @@ -16,6 +16,6 @@ | ||
| 15933 | vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t); | ||
| 15934 | } | ||
| 15935 | |||
| 15936 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15937 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15938 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15939 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15940 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15941 | |||
| 15942 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c' | ||
| 15943 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2010-07-29 15:38:15 +0000 | ||
| 15944 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 15945 | @@ -16,6 +16,6 @@ | ||
| 15946 | vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t); | ||
| 15947 | } | ||
| 15948 | |||
| 15949 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15950 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15951 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15952 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15953 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15954 | |||
| 15955 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c' | ||
| 15956 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2010-07-29 15:38:15 +0000 | ||
| 15957 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 15958 | @@ -16,6 +16,6 @@ | ||
| 15959 | vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t); | ||
| 15960 | } | ||
| 15961 | |||
| 15962 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15963 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15964 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15965 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15966 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15967 | |||
| 15968 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c' | ||
| 15969 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2010-07-29 15:38:15 +0000 | ||
| 15970 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 15971 | @@ -16,6 +16,6 @@ | ||
| 15972 | vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t); | ||
| 15973 | } | ||
| 15974 | |||
| 15975 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15976 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15977 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15978 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15979 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15980 | |||
| 15981 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c' | ||
| 15982 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2010-07-29 15:38:15 +0000 | ||
| 15983 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 15984 | @@ -16,5 +16,5 @@ | ||
| 15985 | vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1); | ||
| 15986 | } | ||
| 15987 | |||
| 15988 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 15989 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 15990 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 15991 | |||
| 15992 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c' | ||
| 15993 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2010-07-29 15:38:15 +0000 | ||
| 15994 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 15995 | @@ -16,5 +16,5 @@ | ||
| 15996 | vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1); | ||
| 15997 | } | ||
| 15998 | |||
| 15999 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16000 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16001 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16002 | |||
| 16003 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c' | ||
| 16004 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2010-07-29 15:38:15 +0000 | ||
| 16005 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 16006 | @@ -16,5 +16,5 @@ | ||
| 16007 | vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1); | ||
| 16008 | } | ||
| 16009 | |||
| 16010 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16011 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16012 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16013 | |||
| 16014 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c' | ||
| 16015 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2010-07-29 15:38:15 +0000 | ||
| 16016 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 16017 | @@ -16,5 +16,5 @@ | ||
| 16018 | vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1); | ||
| 16019 | } | ||
| 16020 | |||
| 16021 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16022 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16023 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16024 | |||
| 16025 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c' | ||
| 16026 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2010-07-29 15:38:15 +0000 | ||
| 16027 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 16028 | @@ -16,5 +16,5 @@ | ||
| 16029 | vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1); | ||
| 16030 | } | ||
| 16031 | |||
| 16032 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16033 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16034 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16035 | |||
| 16036 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c' | ||
| 16037 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2010-07-29 15:38:15 +0000 | ||
| 16038 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 16039 | @@ -16,5 +16,5 @@ | ||
| 16040 | vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1); | ||
| 16041 | } | ||
| 16042 | |||
| 16043 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16044 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16045 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16046 | |||
| 16047 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c' | ||
| 16048 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2010-07-29 15:38:15 +0000 | ||
| 16049 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 16050 | @@ -16,5 +16,5 @@ | ||
| 16051 | vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1); | ||
| 16052 | } | ||
| 16053 | |||
| 16054 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16055 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16056 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16057 | |||
| 16058 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c' | ||
| 16059 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2010-07-29 15:38:15 +0000 | ||
| 16060 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 16061 | @@ -16,5 +16,5 @@ | ||
| 16062 | vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1); | ||
| 16063 | } | ||
| 16064 | |||
| 16065 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16066 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16067 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16068 | |||
| 16069 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c' | ||
| 16070 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2010-07-29 15:38:15 +0000 | ||
| 16071 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 16072 | @@ -16,5 +16,5 @@ | ||
| 16073 | vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1); | ||
| 16074 | } | ||
| 16075 | |||
| 16076 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16077 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16078 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16079 | |||
| 16080 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4f32.c' | ||
| 16081 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2010-07-29 15:38:15 +0000 | ||
| 16082 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2010-08-20 13:27:11 +0000 | ||
| 16083 | @@ -16,5 +16,5 @@ | ||
| 16084 | vst4_f32 (arg0_float32_t, arg1_float32x2x4_t); | ||
| 16085 | } | ||
| 16086 | |||
| 16087 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16088 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16089 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16090 | |||
| 16091 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p16.c' | ||
| 16092 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2010-07-29 15:38:15 +0000 | ||
| 16093 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2010-08-20 13:27:11 +0000 | ||
| 16094 | @@ -16,5 +16,5 @@ | ||
| 16095 | vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t); | ||
| 16096 | } | ||
| 16097 | |||
| 16098 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16099 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16100 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16101 | |||
| 16102 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p8.c' | ||
| 16103 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2010-07-29 15:38:15 +0000 | ||
| 16104 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2010-08-20 13:27:11 +0000 | ||
| 16105 | @@ -16,5 +16,5 @@ | ||
| 16106 | vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t); | ||
| 16107 | } | ||
| 16108 | |||
| 16109 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16110 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16111 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16112 | |||
| 16113 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s16.c' | ||
| 16114 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2010-07-29 15:38:15 +0000 | ||
| 16115 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2010-08-20 13:27:11 +0000 | ||
| 16116 | @@ -16,5 +16,5 @@ | ||
| 16117 | vst4_s16 (arg0_int16_t, arg1_int16x4x4_t); | ||
| 16118 | } | ||
| 16119 | |||
| 16120 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16121 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16122 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16123 | |||
| 16124 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s32.c' | ||
| 16125 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2010-07-29 15:38:15 +0000 | ||
| 16126 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2010-08-20 13:27:11 +0000 | ||
| 16127 | @@ -16,5 +16,5 @@ | ||
| 16128 | vst4_s32 (arg0_int32_t, arg1_int32x2x4_t); | ||
| 16129 | } | ||
| 16130 | |||
| 16131 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16132 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16133 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16134 | |||
| 16135 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s64.c' | ||
| 16136 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2010-07-29 15:38:15 +0000 | ||
| 16137 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2010-08-20 13:27:11 +0000 | ||
| 16138 | @@ -16,5 +16,5 @@ | ||
| 16139 | vst4_s64 (arg0_int64_t, arg1_int64x1x4_t); | ||
| 16140 | } | ||
| 16141 | |||
| 16142 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16143 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16144 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16145 | |||
| 16146 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s8.c' | ||
| 16147 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2010-07-29 15:38:15 +0000 | ||
| 16148 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2010-08-20 13:27:11 +0000 | ||
| 16149 | @@ -16,5 +16,5 @@ | ||
| 16150 | vst4_s8 (arg0_int8_t, arg1_int8x8x4_t); | ||
| 16151 | } | ||
| 16152 | |||
| 16153 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16154 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16155 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16156 | |||
| 16157 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u16.c' | ||
| 16158 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2010-07-29 15:38:15 +0000 | ||
| 16159 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2010-08-20 13:27:11 +0000 | ||
| 16160 | @@ -16,5 +16,5 @@ | ||
| 16161 | vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t); | ||
| 16162 | } | ||
| 16163 | |||
| 16164 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16165 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16166 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16167 | |||
| 16168 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u32.c' | ||
| 16169 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2010-07-29 15:38:15 +0000 | ||
| 16170 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2010-08-20 13:27:11 +0000 | ||
| 16171 | @@ -16,5 +16,5 @@ | ||
| 16172 | vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t); | ||
| 16173 | } | ||
| 16174 | |||
| 16175 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16176 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16177 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16178 | |||
| 16179 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u64.c' | ||
| 16180 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2010-07-29 15:38:15 +0000 | ||
| 16181 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2010-08-20 13:27:11 +0000 | ||
| 16182 | @@ -16,5 +16,5 @@ | ||
| 16183 | vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t); | ||
| 16184 | } | ||
| 16185 | |||
| 16186 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16187 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16188 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16189 | |||
| 16190 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u8.c' | ||
| 16191 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2010-07-29 15:38:15 +0000 | ||
| 16192 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2010-08-20 13:27:11 +0000 | ||
| 16193 | @@ -16,5 +16,5 @@ | ||
| 16194 | vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t); | ||
| 16195 | } | ||
| 16196 | |||
| 16197 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16198 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16199 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16200 | |||
| 16201 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQf32.c' | ||
| 16202 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c 2010-07-29 15:38:15 +0000 | ||
| 16203 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c 2010-08-20 13:27:11 +0000 | ||
| 16204 | @@ -17,5 +17,5 @@ | ||
| 16205 | out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 16206 | } | ||
| 16207 | |||
| 16208 | -/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16209 | +/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16210 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16211 | |||
| 16212 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs16.c' | ||
| 16213 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c 2010-07-29 15:38:15 +0000 | ||
| 16214 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c 2010-08-20 13:27:11 +0000 | ||
| 16215 | @@ -17,5 +17,5 @@ | ||
| 16216 | out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 16217 | } | ||
| 16218 | |||
| 16219 | -/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16220 | +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16221 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16222 | |||
| 16223 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs32.c' | ||
| 16224 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c 2010-07-29 15:38:15 +0000 | ||
| 16225 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c 2010-08-20 13:27:11 +0000 | ||
| 16226 | @@ -17,5 +17,5 @@ | ||
| 16227 | out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 16228 | } | ||
| 16229 | |||
| 16230 | -/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16231 | +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16232 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16233 | |||
| 16234 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs64.c' | ||
| 16235 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c 2010-07-29 15:38:15 +0000 | ||
| 16236 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c 2010-08-20 13:27:11 +0000 | ||
| 16237 | @@ -17,5 +17,5 @@ | ||
| 16238 | out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 16239 | } | ||
| 16240 | |||
| 16241 | -/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16242 | +/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16243 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16244 | |||
| 16245 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQs8.c' | ||
| 16246 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c 2010-07-29 15:38:15 +0000 | ||
| 16247 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c 2010-08-20 13:27:11 +0000 | ||
| 16248 | @@ -17,5 +17,5 @@ | ||
| 16249 | out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 16250 | } | ||
| 16251 | |||
| 16252 | -/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16253 | +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16254 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16255 | |||
| 16256 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu16.c' | ||
| 16257 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c 2010-07-29 15:38:15 +0000 | ||
| 16258 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c 2010-08-20 13:27:11 +0000 | ||
| 16259 | @@ -17,5 +17,5 @@ | ||
| 16260 | out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 16261 | } | ||
| 16262 | |||
| 16263 | -/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16264 | +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16265 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16266 | |||
| 16267 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu32.c' | ||
| 16268 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c 2010-07-29 15:38:15 +0000 | ||
| 16269 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c 2010-08-20 13:27:11 +0000 | ||
| 16270 | @@ -17,5 +17,5 @@ | ||
| 16271 | out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 16272 | } | ||
| 16273 | |||
| 16274 | -/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16275 | +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16276 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16277 | |||
| 16278 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu64.c' | ||
| 16279 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c 2010-07-29 15:38:15 +0000 | ||
| 16280 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c 2010-08-20 13:27:11 +0000 | ||
| 16281 | @@ -17,5 +17,5 @@ | ||
| 16282 | out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 16283 | } | ||
| 16284 | |||
| 16285 | -/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16286 | +/* { dg-final { scan-assembler "vsub\.i64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16287 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16288 | |||
| 16289 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubQu8.c' | ||
| 16290 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c 2010-07-29 15:38:15 +0000 | ||
| 16291 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c 2010-08-20 13:27:11 +0000 | ||
| 16292 | @@ -17,5 +17,5 @@ | ||
| 16293 | out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 16294 | } | ||
| 16295 | |||
| 16296 | -/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16297 | +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16298 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16299 | |||
| 16300 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubf32.c' | ||
| 16301 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubf32.c 2010-07-29 15:38:15 +0000 | ||
| 16302 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubf32.c 2010-08-20 13:27:11 +0000 | ||
| 16303 | @@ -17,5 +17,5 @@ | ||
| 16304 | out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 16305 | } | ||
| 16306 | |||
| 16307 | -/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16308 | +/* { dg-final { scan-assembler "vsub\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16309 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16310 | |||
| 16311 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhns16.c' | ||
| 16312 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c 2010-07-29 15:38:15 +0000 | ||
| 16313 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c 2010-08-20 13:27:11 +0000 | ||
| 16314 | @@ -17,5 +17,5 @@ | ||
| 16315 | out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 16316 | } | ||
| 16317 | |||
| 16318 | -/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16319 | +/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16320 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16321 | |||
| 16322 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhns32.c' | ||
| 16323 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c 2010-07-29 15:38:15 +0000 | ||
| 16324 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c 2010-08-20 13:27:11 +0000 | ||
| 16325 | @@ -17,5 +17,5 @@ | ||
| 16326 | out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 16327 | } | ||
| 16328 | |||
| 16329 | -/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16330 | +/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16331 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16332 | |||
| 16333 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhns64.c' | ||
| 16334 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c 2010-07-29 15:38:15 +0000 | ||
| 16335 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c 2010-08-20 13:27:11 +0000 | ||
| 16336 | @@ -17,5 +17,5 @@ | ||
| 16337 | out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t); | ||
| 16338 | } | ||
| 16339 | |||
| 16340 | -/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16341 | +/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16342 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16343 | |||
| 16344 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c' | ||
| 16345 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c 2010-07-29 15:38:15 +0000 | ||
| 16346 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c 2010-08-20 13:27:11 +0000 | ||
| 16347 | @@ -17,5 +17,5 @@ | ||
| 16348 | out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 16349 | } | ||
| 16350 | |||
| 16351 | -/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16352 | +/* { dg-final { scan-assembler "vsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16353 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16354 | |||
| 16355 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c' | ||
| 16356 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c 2010-07-29 15:38:15 +0000 | ||
| 16357 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c 2010-08-20 13:27:11 +0000 | ||
| 16358 | @@ -17,5 +17,5 @@ | ||
| 16359 | out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 16360 | } | ||
| 16361 | |||
| 16362 | -/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16363 | +/* { dg-final { scan-assembler "vsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16364 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16365 | |||
| 16366 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c' | ||
| 16367 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c 2010-07-29 15:38:15 +0000 | ||
| 16368 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c 2010-08-20 13:27:11 +0000 | ||
| 16369 | @@ -17,5 +17,5 @@ | ||
| 16370 | out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t); | ||
| 16371 | } | ||
| 16372 | |||
| 16373 | -/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16374 | +/* { dg-final { scan-assembler "vsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16375 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16376 | |||
| 16377 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubls16.c' | ||
| 16378 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubls16.c 2010-07-29 15:38:15 +0000 | ||
| 16379 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubls16.c 2010-08-20 13:27:11 +0000 | ||
| 16380 | @@ -17,5 +17,5 @@ | ||
| 16381 | out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 16382 | } | ||
| 16383 | |||
| 16384 | -/* { dg-final { scan-assembler "vsubl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16385 | +/* { dg-final { scan-assembler "vsubl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16386 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16387 | |||
| 16388 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubls32.c' | ||
| 16389 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubls32.c 2010-07-29 15:38:15 +0000 | ||
| 16390 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubls32.c 2010-08-20 13:27:11 +0000 | ||
| 16391 | @@ -17,5 +17,5 @@ | ||
| 16392 | out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 16393 | } | ||
| 16394 | |||
| 16395 | -/* { dg-final { scan-assembler "vsubl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16396 | +/* { dg-final { scan-assembler "vsubl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16397 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16398 | |||
| 16399 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubls8.c' | ||
| 16400 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubls8.c 2010-07-29 15:38:15 +0000 | ||
| 16401 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubls8.c 2010-08-20 13:27:11 +0000 | ||
| 16402 | @@ -17,5 +17,5 @@ | ||
| 16403 | out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 16404 | } | ||
| 16405 | |||
| 16406 | -/* { dg-final { scan-assembler "vsubl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16407 | +/* { dg-final { scan-assembler "vsubl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16408 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16409 | |||
| 16410 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsublu16.c' | ||
| 16411 | --- old/gcc/testsuite/gcc.target/arm/neon/vsublu16.c 2010-07-29 15:38:15 +0000 | ||
| 16412 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsublu16.c 2010-08-20 13:27:11 +0000 | ||
| 16413 | @@ -17,5 +17,5 @@ | ||
| 16414 | out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 16415 | } | ||
| 16416 | |||
| 16417 | -/* { dg-final { scan-assembler "vsubl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16418 | +/* { dg-final { scan-assembler "vsubl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16419 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16420 | |||
| 16421 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsublu32.c' | ||
| 16422 | --- old/gcc/testsuite/gcc.target/arm/neon/vsublu32.c 2010-07-29 15:38:15 +0000 | ||
| 16423 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsublu32.c 2010-08-20 13:27:11 +0000 | ||
| 16424 | @@ -17,5 +17,5 @@ | ||
| 16425 | out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 16426 | } | ||
| 16427 | |||
| 16428 | -/* { dg-final { scan-assembler "vsubl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16429 | +/* { dg-final { scan-assembler "vsubl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16430 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16431 | |||
| 16432 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsublu8.c' | ||
| 16433 | --- old/gcc/testsuite/gcc.target/arm/neon/vsublu8.c 2010-07-29 15:38:15 +0000 | ||
| 16434 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsublu8.c 2010-08-20 13:27:11 +0000 | ||
| 16435 | @@ -17,5 +17,5 @@ | ||
| 16436 | out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 16437 | } | ||
| 16438 | |||
| 16439 | -/* { dg-final { scan-assembler "vsubl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16440 | +/* { dg-final { scan-assembler "vsubl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16441 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16442 | |||
| 16443 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs16.c' | ||
| 16444 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubs16.c 2010-07-29 15:38:15 +0000 | ||
| 16445 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubs16.c 2010-08-20 13:27:11 +0000 | ||
| 16446 | @@ -17,5 +17,5 @@ | ||
| 16447 | out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 16448 | } | ||
| 16449 | |||
| 16450 | -/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16451 | +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16452 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16453 | |||
| 16454 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs32.c' | ||
| 16455 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubs32.c 2010-07-29 15:38:15 +0000 | ||
| 16456 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubs32.c 2010-08-20 13:27:11 +0000 | ||
| 16457 | @@ -17,5 +17,5 @@ | ||
| 16458 | out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 16459 | } | ||
| 16460 | |||
| 16461 | -/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16462 | +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16463 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16464 | |||
| 16465 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubs8.c' | ||
| 16466 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubs8.c 2010-07-29 15:38:15 +0000 | ||
| 16467 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubs8.c 2010-08-20 13:27:11 +0000 | ||
| 16468 | @@ -17,5 +17,5 @@ | ||
| 16469 | out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 16470 | } | ||
| 16471 | |||
| 16472 | -/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16473 | +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16474 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16475 | |||
| 16476 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu16.c' | ||
| 16477 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubu16.c 2010-07-29 15:38:15 +0000 | ||
| 16478 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubu16.c 2010-08-20 13:27:11 +0000 | ||
| 16479 | @@ -17,5 +17,5 @@ | ||
| 16480 | out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 16481 | } | ||
| 16482 | |||
| 16483 | -/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16484 | +/* { dg-final { scan-assembler "vsub\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16485 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16486 | |||
| 16487 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu32.c' | ||
| 16488 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubu32.c 2010-07-29 15:38:15 +0000 | ||
| 16489 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubu32.c 2010-08-20 13:27:11 +0000 | ||
| 16490 | @@ -17,5 +17,5 @@ | ||
| 16491 | out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 16492 | } | ||
| 16493 | |||
| 16494 | -/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16495 | +/* { dg-final { scan-assembler "vsub\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16496 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16497 | |||
| 16498 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubu8.c' | ||
| 16499 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubu8.c 2010-07-29 15:38:15 +0000 | ||
| 16500 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubu8.c 2010-08-20 13:27:11 +0000 | ||
| 16501 | @@ -17,5 +17,5 @@ | ||
| 16502 | out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 16503 | } | ||
| 16504 | |||
| 16505 | -/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16506 | +/* { dg-final { scan-assembler "vsub\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16507 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16508 | |||
| 16509 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubws16.c' | ||
| 16510 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubws16.c 2010-07-29 15:38:15 +0000 | ||
| 16511 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubws16.c 2010-08-20 13:27:11 +0000 | ||
| 16512 | @@ -17,5 +17,5 @@ | ||
| 16513 | out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t); | ||
| 16514 | } | ||
| 16515 | |||
| 16516 | -/* { dg-final { scan-assembler "vsubw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16517 | +/* { dg-final { scan-assembler "vsubw\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16518 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16519 | |||
| 16520 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubws32.c' | ||
| 16521 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubws32.c 2010-07-29 15:38:15 +0000 | ||
| 16522 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubws32.c 2010-08-20 13:27:11 +0000 | ||
| 16523 | @@ -17,5 +17,5 @@ | ||
| 16524 | out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t); | ||
| 16525 | } | ||
| 16526 | |||
| 16527 | -/* { dg-final { scan-assembler "vsubw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16528 | +/* { dg-final { scan-assembler "vsubw\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16529 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16530 | |||
| 16531 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubws8.c' | ||
| 16532 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubws8.c 2010-07-29 15:38:15 +0000 | ||
| 16533 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubws8.c 2010-08-20 13:27:11 +0000 | ||
| 16534 | @@ -17,5 +17,5 @@ | ||
| 16535 | out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t); | ||
| 16536 | } | ||
| 16537 | |||
| 16538 | -/* { dg-final { scan-assembler "vsubw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16539 | +/* { dg-final { scan-assembler "vsubw\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16540 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16541 | |||
| 16542 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubwu16.c' | ||
| 16543 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c 2010-07-29 15:38:15 +0000 | ||
| 16544 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c 2010-08-20 13:27:11 +0000 | ||
| 16545 | @@ -17,5 +17,5 @@ | ||
| 16546 | out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t); | ||
| 16547 | } | ||
| 16548 | |||
| 16549 | -/* { dg-final { scan-assembler "vsubw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16550 | +/* { dg-final { scan-assembler "vsubw\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16551 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16552 | |||
| 16553 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubwu32.c' | ||
| 16554 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c 2010-07-29 15:38:15 +0000 | ||
| 16555 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c 2010-08-20 13:27:11 +0000 | ||
| 16556 | @@ -17,5 +17,5 @@ | ||
| 16557 | out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t); | ||
| 16558 | } | ||
| 16559 | |||
| 16560 | -/* { dg-final { scan-assembler "vsubw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16561 | +/* { dg-final { scan-assembler "vsubw\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16562 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16563 | |||
| 16564 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vsubwu8.c' | ||
| 16565 | --- old/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c 2010-07-29 15:38:15 +0000 | ||
| 16566 | +++ new/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c 2010-08-20 13:27:11 +0000 | ||
| 16567 | @@ -17,5 +17,5 @@ | ||
| 16568 | out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t); | ||
| 16569 | } | ||
| 16570 | |||
| 16571 | -/* { dg-final { scan-assembler "vsubw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16572 | +/* { dg-final { scan-assembler "vsubw\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16573 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16574 | |||
| 16575 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c' | ||
| 16576 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c 2010-07-29 15:38:15 +0000 | ||
| 16577 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c 2010-08-20 13:27:11 +0000 | ||
| 16578 | @@ -17,5 +17,5 @@ | ||
| 16579 | out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t); | ||
| 16580 | } | ||
| 16581 | |||
| 16582 | -/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16583 | +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16584 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16585 | |||
| 16586 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c' | ||
| 16587 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c 2010-07-29 15:38:15 +0000 | ||
| 16588 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c 2010-08-20 13:27:11 +0000 | ||
| 16589 | @@ -17,5 +17,5 @@ | ||
| 16590 | out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 16591 | } | ||
| 16592 | |||
| 16593 | -/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16594 | +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16595 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16596 | |||
| 16597 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c' | ||
| 16598 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c 2010-07-29 15:38:15 +0000 | ||
| 16599 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c 2010-08-20 13:27:11 +0000 | ||
| 16600 | @@ -17,5 +17,5 @@ | ||
| 16601 | out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 16602 | } | ||
| 16603 | |||
| 16604 | -/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16605 | +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16606 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16607 | |||
| 16608 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c' | ||
| 16609 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c 2010-07-29 15:38:15 +0000 | ||
| 16610 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c 2010-08-20 13:27:11 +0000 | ||
| 16611 | @@ -17,5 +17,5 @@ | ||
| 16612 | out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t); | ||
| 16613 | } | ||
| 16614 | |||
| 16615 | -/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16616 | +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16617 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16618 | |||
| 16619 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c' | ||
| 16620 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c 2010-07-29 15:38:15 +0000 | ||
| 16621 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c 2010-08-20 13:27:11 +0000 | ||
| 16622 | @@ -17,5 +17,5 @@ | ||
| 16623 | out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t); | ||
| 16624 | } | ||
| 16625 | |||
| 16626 | -/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16627 | +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16628 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16629 | |||
| 16630 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c' | ||
| 16631 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c 2010-07-29 15:38:15 +0000 | ||
| 16632 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c 2010-08-20 13:27:11 +0000 | ||
| 16633 | @@ -17,5 +17,5 @@ | ||
| 16634 | out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t); | ||
| 16635 | } | ||
| 16636 | |||
| 16637 | -/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16638 | +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16639 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16640 | |||
| 16641 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c' | ||
| 16642 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c 2010-07-29 15:38:15 +0000 | ||
| 16643 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c 2010-08-20 13:27:11 +0000 | ||
| 16644 | @@ -17,5 +17,5 @@ | ||
| 16645 | out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t); | ||
| 16646 | } | ||
| 16647 | |||
| 16648 | -/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16649 | +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16650 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16651 | |||
| 16652 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c' | ||
| 16653 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c 2010-07-29 15:38:15 +0000 | ||
| 16654 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c 2010-08-20 13:27:11 +0000 | ||
| 16655 | @@ -17,5 +17,5 @@ | ||
| 16656 | out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t); | ||
| 16657 | } | ||
| 16658 | |||
| 16659 | -/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16660 | +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16661 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16662 | |||
| 16663 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c' | ||
| 16664 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c 2010-07-29 15:38:15 +0000 | ||
| 16665 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c 2010-08-20 13:27:11 +0000 | ||
| 16666 | @@ -17,5 +17,5 @@ | ||
| 16667 | out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t); | ||
| 16668 | } | ||
| 16669 | |||
| 16670 | -/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16671 | +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16672 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16673 | |||
| 16674 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c' | ||
| 16675 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c 2010-07-29 15:38:15 +0000 | ||
| 16676 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c 2010-08-20 13:27:11 +0000 | ||
| 16677 | @@ -17,5 +17,5 @@ | ||
| 16678 | out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t); | ||
| 16679 | } | ||
| 16680 | |||
| 16681 | -/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16682 | +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16683 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16684 | |||
| 16685 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c' | ||
| 16686 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c 2010-07-29 15:38:15 +0000 | ||
| 16687 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c 2010-08-20 13:27:11 +0000 | ||
| 16688 | @@ -17,5 +17,5 @@ | ||
| 16689 | out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t); | ||
| 16690 | } | ||
| 16691 | |||
| 16692 | -/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16693 | +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16694 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16695 | |||
| 16696 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c' | ||
| 16697 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c 2010-07-29 15:38:15 +0000 | ||
| 16698 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c 2010-08-20 13:27:11 +0000 | ||
| 16699 | @@ -17,5 +17,5 @@ | ||
| 16700 | out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t); | ||
| 16701 | } | ||
| 16702 | |||
| 16703 | -/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16704 | +/* { dg-final { scan-assembler "vtbl\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16705 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16706 | |||
| 16707 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c' | ||
| 16708 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c 2010-07-29 15:38:15 +0000 | ||
| 16709 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c 2010-08-20 13:27:11 +0000 | ||
| 16710 | @@ -18,5 +18,5 @@ | ||
| 16711 | out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t); | ||
| 16712 | } | ||
| 16713 | |||
| 16714 | -/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16715 | +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16716 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16717 | |||
| 16718 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c' | ||
| 16719 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c 2010-07-29 15:38:15 +0000 | ||
| 16720 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c 2010-08-20 13:27:11 +0000 | ||
| 16721 | @@ -18,5 +18,5 @@ | ||
| 16722 | out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t); | ||
| 16723 | } | ||
| 16724 | |||
| 16725 | -/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16726 | +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16727 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16728 | |||
| 16729 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c' | ||
| 16730 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c 2010-07-29 15:38:15 +0000 | ||
| 16731 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c 2010-08-20 13:27:11 +0000 | ||
| 16732 | @@ -18,5 +18,5 @@ | ||
| 16733 | out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t); | ||
| 16734 | } | ||
| 16735 | |||
| 16736 | -/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16737 | +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16738 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16739 | |||
| 16740 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c' | ||
| 16741 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c 2010-07-29 15:38:15 +0000 | ||
| 16742 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c 2010-08-20 13:27:11 +0000 | ||
| 16743 | @@ -18,5 +18,5 @@ | ||
| 16744 | out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t); | ||
| 16745 | } | ||
| 16746 | |||
| 16747 | -/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16748 | +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16749 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16750 | |||
| 16751 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c' | ||
| 16752 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c 2010-07-29 15:38:15 +0000 | ||
| 16753 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c 2010-08-20 13:27:11 +0000 | ||
| 16754 | @@ -18,5 +18,5 @@ | ||
| 16755 | out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t); | ||
| 16756 | } | ||
| 16757 | |||
| 16758 | -/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16759 | +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16760 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16761 | |||
| 16762 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c' | ||
| 16763 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c 2010-07-29 15:38:15 +0000 | ||
| 16764 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c 2010-08-20 13:27:11 +0000 | ||
| 16765 | @@ -18,5 +18,5 @@ | ||
| 16766 | out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t); | ||
| 16767 | } | ||
| 16768 | |||
| 16769 | -/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16770 | +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16771 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16772 | |||
| 16773 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c' | ||
| 16774 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c 2010-07-29 15:38:15 +0000 | ||
| 16775 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c 2010-08-20 13:27:11 +0000 | ||
| 16776 | @@ -18,5 +18,5 @@ | ||
| 16777 | out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t); | ||
| 16778 | } | ||
| 16779 | |||
| 16780 | -/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16781 | +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16782 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16783 | |||
| 16784 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c' | ||
| 16785 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c 2010-07-29 15:38:15 +0000 | ||
| 16786 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c 2010-08-20 13:27:11 +0000 | ||
| 16787 | @@ -18,5 +18,5 @@ | ||
| 16788 | out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t); | ||
| 16789 | } | ||
| 16790 | |||
| 16791 | -/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16792 | +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16793 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16794 | |||
| 16795 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c' | ||
| 16796 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c 2010-07-29 15:38:15 +0000 | ||
| 16797 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c 2010-08-20 13:27:11 +0000 | ||
| 16798 | @@ -18,5 +18,5 @@ | ||
| 16799 | out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t); | ||
| 16800 | } | ||
| 16801 | |||
| 16802 | -/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16803 | +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16804 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16805 | |||
| 16806 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c' | ||
| 16807 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c 2010-07-29 15:38:15 +0000 | ||
| 16808 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c 2010-08-20 13:27:11 +0000 | ||
| 16809 | @@ -18,5 +18,5 @@ | ||
| 16810 | out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t); | ||
| 16811 | } | ||
| 16812 | |||
| 16813 | -/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16814 | +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16815 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16816 | |||
| 16817 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c' | ||
| 16818 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c 2010-07-29 15:38:15 +0000 | ||
| 16819 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c 2010-08-20 13:27:11 +0000 | ||
| 16820 | @@ -18,5 +18,5 @@ | ||
| 16821 | out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t); | ||
| 16822 | } | ||
| 16823 | |||
| 16824 | -/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16825 | +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16826 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16827 | |||
| 16828 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c' | ||
| 16829 | --- old/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c 2010-07-29 15:38:15 +0000 | ||
| 16830 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c 2010-08-20 13:27:11 +0000 | ||
| 16831 | @@ -18,5 +18,5 @@ | ||
| 16832 | out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t); | ||
| 16833 | } | ||
| 16834 | |||
| 16835 | -/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16836 | +/* { dg-final { scan-assembler "vtbx\.8\[ \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16837 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16838 | |||
| 16839 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c' | ||
| 16840 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c 2010-07-29 15:38:15 +0000 | ||
| 16841 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c 2010-08-20 13:27:11 +0000 | ||
| 16842 | @@ -17,5 +17,5 @@ | ||
| 16843 | out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 16844 | } | ||
| 16845 | |||
| 16846 | -/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16847 | +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16848 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16849 | |||
| 16850 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c' | ||
| 16851 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c 2010-07-29 15:38:15 +0000 | ||
| 16852 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c 2010-08-20 13:27:11 +0000 | ||
| 16853 | @@ -17,5 +17,5 @@ | ||
| 16854 | out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); | ||
| 16855 | } | ||
| 16856 | |||
| 16857 | -/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16858 | +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16859 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16860 | |||
| 16861 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c' | ||
| 16862 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c 2010-07-29 15:38:15 +0000 | ||
| 16863 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c 2010-08-20 13:27:11 +0000 | ||
| 16864 | @@ -17,5 +17,5 @@ | ||
| 16865 | out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); | ||
| 16866 | } | ||
| 16867 | |||
| 16868 | -/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16869 | +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16870 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16871 | |||
| 16872 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c' | ||
| 16873 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c 2010-07-29 15:38:15 +0000 | ||
| 16874 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c 2010-08-20 13:27:11 +0000 | ||
| 16875 | @@ -17,5 +17,5 @@ | ||
| 16876 | out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 16877 | } | ||
| 16878 | |||
| 16879 | -/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16880 | +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16881 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16882 | |||
| 16883 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c' | ||
| 16884 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c 2010-07-29 15:38:15 +0000 | ||
| 16885 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c 2010-08-20 13:27:11 +0000 | ||
| 16886 | @@ -17,5 +17,5 @@ | ||
| 16887 | out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 16888 | } | ||
| 16889 | |||
| 16890 | -/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16891 | +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16892 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16893 | |||
| 16894 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c' | ||
| 16895 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c 2010-07-29 15:38:15 +0000 | ||
| 16896 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c 2010-08-20 13:27:11 +0000 | ||
| 16897 | @@ -17,5 +17,5 @@ | ||
| 16898 | out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 16899 | } | ||
| 16900 | |||
| 16901 | -/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16902 | +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16903 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16904 | |||
| 16905 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c' | ||
| 16906 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c 2010-07-29 15:38:15 +0000 | ||
| 16907 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c 2010-08-20 13:27:11 +0000 | ||
| 16908 | @@ -17,5 +17,5 @@ | ||
| 16909 | out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 16910 | } | ||
| 16911 | |||
| 16912 | -/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16913 | +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16914 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16915 | |||
| 16916 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c' | ||
| 16917 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c 2010-07-29 15:38:15 +0000 | ||
| 16918 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c 2010-08-20 13:27:11 +0000 | ||
| 16919 | @@ -17,5 +17,5 @@ | ||
| 16920 | out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 16921 | } | ||
| 16922 | |||
| 16923 | -/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16924 | +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16925 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16926 | |||
| 16927 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c' | ||
| 16928 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c 2010-07-29 15:38:15 +0000 | ||
| 16929 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c 2010-08-20 13:27:11 +0000 | ||
| 16930 | @@ -17,5 +17,5 @@ | ||
| 16931 | out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 16932 | } | ||
| 16933 | |||
| 16934 | -/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16935 | +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16936 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16937 | |||
| 16938 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnf32.c' | ||
| 16939 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c 2010-07-29 15:38:15 +0000 | ||
| 16940 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c 2010-08-20 13:27:11 +0000 | ||
| 16941 | @@ -17,5 +17,5 @@ | ||
| 16942 | out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 16943 | } | ||
| 16944 | |||
| 16945 | -/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16946 | +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16947 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16948 | |||
| 16949 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnp16.c' | ||
| 16950 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c 2010-07-29 15:38:15 +0000 | ||
| 16951 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c 2010-08-20 13:27:11 +0000 | ||
| 16952 | @@ -17,5 +17,5 @@ | ||
| 16953 | out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t); | ||
| 16954 | } | ||
| 16955 | |||
| 16956 | -/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16957 | +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16958 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16959 | |||
| 16960 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnp8.c' | ||
| 16961 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c 2010-07-29 15:38:15 +0000 | ||
| 16962 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c 2010-08-20 13:27:11 +0000 | ||
| 16963 | @@ -17,5 +17,5 @@ | ||
| 16964 | out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t); | ||
| 16965 | } | ||
| 16966 | |||
| 16967 | -/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16968 | +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16969 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16970 | |||
| 16971 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrns16.c' | ||
| 16972 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrns16.c 2010-07-29 15:38:15 +0000 | ||
| 16973 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrns16.c 2010-08-20 13:27:11 +0000 | ||
| 16974 | @@ -17,5 +17,5 @@ | ||
| 16975 | out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 16976 | } | ||
| 16977 | |||
| 16978 | -/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16979 | +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16980 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16981 | |||
| 16982 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrns32.c' | ||
| 16983 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrns32.c 2010-07-29 15:38:15 +0000 | ||
| 16984 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrns32.c 2010-08-20 13:27:11 +0000 | ||
| 16985 | @@ -17,5 +17,5 @@ | ||
| 16986 | out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 16987 | } | ||
| 16988 | |||
| 16989 | -/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 16990 | +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 16991 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 16992 | |||
| 16993 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrns8.c' | ||
| 16994 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrns8.c 2010-07-29 15:38:15 +0000 | ||
| 16995 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrns8.c 2010-08-20 13:27:11 +0000 | ||
| 16996 | @@ -17,5 +17,5 @@ | ||
| 16997 | out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 16998 | } | ||
| 16999 | |||
| 17000 | -/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17001 | +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17002 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17003 | |||
| 17004 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnu16.c' | ||
| 17005 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c 2010-07-29 15:38:15 +0000 | ||
| 17006 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c 2010-08-20 13:27:11 +0000 | ||
| 17007 | @@ -17,5 +17,5 @@ | ||
| 17008 | out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 17009 | } | ||
| 17010 | |||
| 17011 | -/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17012 | +/* { dg-final { scan-assembler "vtrn\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17013 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17014 | |||
| 17015 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnu32.c' | ||
| 17016 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c 2010-07-29 15:38:15 +0000 | ||
| 17017 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c 2010-08-20 13:27:11 +0000 | ||
| 17018 | @@ -17,5 +17,5 @@ | ||
| 17019 | out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 17020 | } | ||
| 17021 | |||
| 17022 | -/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17023 | +/* { dg-final { scan-assembler "vtrn\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17024 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17025 | |||
| 17026 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtrnu8.c' | ||
| 17027 | --- old/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c 2010-07-29 15:38:15 +0000 | ||
| 17028 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c 2010-08-20 13:27:11 +0000 | ||
| 17029 | @@ -17,5 +17,5 @@ | ||
| 17030 | out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 17031 | } | ||
| 17032 | |||
| 17033 | -/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17034 | +/* { dg-final { scan-assembler "vtrn\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17035 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17036 | |||
| 17037 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQp8.c' | ||
| 17038 | --- old/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c 2010-07-29 15:38:15 +0000 | ||
| 17039 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c 2010-08-20 13:27:11 +0000 | ||
| 17040 | @@ -17,5 +17,5 @@ | ||
| 17041 | out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); | ||
| 17042 | } | ||
| 17043 | |||
| 17044 | -/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17045 | +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17046 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17047 | |||
| 17048 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQs16.c' | ||
| 17049 | --- old/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c 2010-07-29 15:38:15 +0000 | ||
| 17050 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c 2010-08-20 13:27:11 +0000 | ||
| 17051 | @@ -17,5 +17,5 @@ | ||
| 17052 | out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 17053 | } | ||
| 17054 | |||
| 17055 | -/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17056 | +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17057 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17058 | |||
| 17059 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQs32.c' | ||
| 17060 | --- old/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c 2010-07-29 15:38:15 +0000 | ||
| 17061 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c 2010-08-20 13:27:11 +0000 | ||
| 17062 | @@ -17,5 +17,5 @@ | ||
| 17063 | out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 17064 | } | ||
| 17065 | |||
| 17066 | -/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17067 | +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17068 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17069 | |||
| 17070 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQs8.c' | ||
| 17071 | --- old/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c 2010-07-29 15:38:15 +0000 | ||
| 17072 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c 2010-08-20 13:27:11 +0000 | ||
| 17073 | @@ -17,5 +17,5 @@ | ||
| 17074 | out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 17075 | } | ||
| 17076 | |||
| 17077 | -/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17078 | +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17079 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17080 | |||
| 17081 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQu16.c' | ||
| 17082 | --- old/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c 2010-07-29 15:38:15 +0000 | ||
| 17083 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c 2010-08-20 13:27:11 +0000 | ||
| 17084 | @@ -17,5 +17,5 @@ | ||
| 17085 | out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 17086 | } | ||
| 17087 | |||
| 17088 | -/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17089 | +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17090 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17091 | |||
| 17092 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQu32.c' | ||
| 17093 | --- old/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c 2010-07-29 15:38:15 +0000 | ||
| 17094 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c 2010-08-20 13:27:11 +0000 | ||
| 17095 | @@ -17,5 +17,5 @@ | ||
| 17096 | out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 17097 | } | ||
| 17098 | |||
| 17099 | -/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17100 | +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17101 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17102 | |||
| 17103 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtstQu8.c' | ||
| 17104 | --- old/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c 2010-07-29 15:38:15 +0000 | ||
| 17105 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c 2010-08-20 13:27:11 +0000 | ||
| 17106 | @@ -17,5 +17,5 @@ | ||
| 17107 | out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 17108 | } | ||
| 17109 | |||
| 17110 | -/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17111 | +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17112 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17113 | |||
| 17114 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtstp8.c' | ||
| 17115 | --- old/gcc/testsuite/gcc.target/arm/neon/vtstp8.c 2010-07-29 15:38:15 +0000 | ||
| 17116 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtstp8.c 2010-08-20 13:27:11 +0000 | ||
| 17117 | @@ -17,5 +17,5 @@ | ||
| 17118 | out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t); | ||
| 17119 | } | ||
| 17120 | |||
| 17121 | -/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17122 | +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17123 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17124 | |||
| 17125 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtsts16.c' | ||
| 17126 | --- old/gcc/testsuite/gcc.target/arm/neon/vtsts16.c 2010-07-29 15:38:15 +0000 | ||
| 17127 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtsts16.c 2010-08-20 13:27:11 +0000 | ||
| 17128 | @@ -17,5 +17,5 @@ | ||
| 17129 | out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 17130 | } | ||
| 17131 | |||
| 17132 | -/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17133 | +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17134 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17135 | |||
| 17136 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtsts32.c' | ||
| 17137 | --- old/gcc/testsuite/gcc.target/arm/neon/vtsts32.c 2010-07-29 15:38:15 +0000 | ||
| 17138 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtsts32.c 2010-08-20 13:27:11 +0000 | ||
| 17139 | @@ -17,5 +17,5 @@ | ||
| 17140 | out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 17141 | } | ||
| 17142 | |||
| 17143 | -/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17144 | +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17145 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17146 | |||
| 17147 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtsts8.c' | ||
| 17148 | --- old/gcc/testsuite/gcc.target/arm/neon/vtsts8.c 2010-07-29 15:38:15 +0000 | ||
| 17149 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtsts8.c 2010-08-20 13:27:11 +0000 | ||
| 17150 | @@ -17,5 +17,5 @@ | ||
| 17151 | out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 17152 | } | ||
| 17153 | |||
| 17154 | -/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17155 | +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17156 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17157 | |||
| 17158 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtstu16.c' | ||
| 17159 | --- old/gcc/testsuite/gcc.target/arm/neon/vtstu16.c 2010-07-29 15:38:15 +0000 | ||
| 17160 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtstu16.c 2010-08-20 13:27:11 +0000 | ||
| 17161 | @@ -17,5 +17,5 @@ | ||
| 17162 | out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 17163 | } | ||
| 17164 | |||
| 17165 | -/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17166 | +/* { dg-final { scan-assembler "vtst\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17167 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17168 | |||
| 17169 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtstu32.c' | ||
| 17170 | --- old/gcc/testsuite/gcc.target/arm/neon/vtstu32.c 2010-07-29 15:38:15 +0000 | ||
| 17171 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtstu32.c 2010-08-20 13:27:11 +0000 | ||
| 17172 | @@ -17,5 +17,5 @@ | ||
| 17173 | out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 17174 | } | ||
| 17175 | |||
| 17176 | -/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17177 | +/* { dg-final { scan-assembler "vtst\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17178 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17179 | |||
| 17180 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vtstu8.c' | ||
| 17181 | --- old/gcc/testsuite/gcc.target/arm/neon/vtstu8.c 2010-07-29 15:38:15 +0000 | ||
| 17182 | +++ new/gcc/testsuite/gcc.target/arm/neon/vtstu8.c 2010-08-20 13:27:11 +0000 | ||
| 17183 | @@ -17,5 +17,5 @@ | ||
| 17184 | out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 17185 | } | ||
| 17186 | |||
| 17187 | -/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17188 | +/* { dg-final { scan-assembler "vtst\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17189 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17190 | |||
| 17191 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c' | ||
| 17192 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c 2010-07-29 15:38:15 +0000 | ||
| 17193 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c 2010-08-20 13:27:11 +0000 | ||
| 17194 | @@ -17,5 +17,5 @@ | ||
| 17195 | out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 17196 | } | ||
| 17197 | |||
| 17198 | -/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17199 | +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17200 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17201 | |||
| 17202 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c' | ||
| 17203 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c 2010-07-29 15:38:15 +0000 | ||
| 17204 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c 2010-08-20 13:27:11 +0000 | ||
| 17205 | @@ -17,5 +17,5 @@ | ||
| 17206 | out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); | ||
| 17207 | } | ||
| 17208 | |||
| 17209 | -/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17210 | +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17211 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17212 | |||
| 17213 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c' | ||
| 17214 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c 2010-07-29 15:38:15 +0000 | ||
| 17215 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c 2010-08-20 13:27:11 +0000 | ||
| 17216 | @@ -17,5 +17,5 @@ | ||
| 17217 | out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); | ||
| 17218 | } | ||
| 17219 | |||
| 17220 | -/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17221 | +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17222 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17223 | |||
| 17224 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c' | ||
| 17225 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c 2010-07-29 15:38:15 +0000 | ||
| 17226 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c 2010-08-20 13:27:11 +0000 | ||
| 17227 | @@ -17,5 +17,5 @@ | ||
| 17228 | out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 17229 | } | ||
| 17230 | |||
| 17231 | -/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17232 | +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17233 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17234 | |||
| 17235 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c' | ||
| 17236 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c 2010-07-29 15:38:15 +0000 | ||
| 17237 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c 2010-08-20 13:27:11 +0000 | ||
| 17238 | @@ -17,5 +17,5 @@ | ||
| 17239 | out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 17240 | } | ||
| 17241 | |||
| 17242 | -/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17243 | +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17244 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17245 | |||
| 17246 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c' | ||
| 17247 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c 2010-07-29 15:38:15 +0000 | ||
| 17248 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c 2010-08-20 13:27:11 +0000 | ||
| 17249 | @@ -17,5 +17,5 @@ | ||
| 17250 | out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 17251 | } | ||
| 17252 | |||
| 17253 | -/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17254 | +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17255 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17256 | |||
| 17257 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c' | ||
| 17258 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c 2010-07-29 15:38:15 +0000 | ||
| 17259 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c 2010-08-20 13:27:11 +0000 | ||
| 17260 | @@ -17,5 +17,5 @@ | ||
| 17261 | out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 17262 | } | ||
| 17263 | |||
| 17264 | -/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17265 | +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17266 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17267 | |||
| 17268 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c' | ||
| 17269 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c 2010-07-29 15:38:15 +0000 | ||
| 17270 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c 2010-08-20 13:27:11 +0000 | ||
| 17271 | @@ -17,5 +17,5 @@ | ||
| 17272 | out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 17273 | } | ||
| 17274 | |||
| 17275 | -/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17276 | +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17277 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17278 | |||
| 17279 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c' | ||
| 17280 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c 2010-07-29 15:38:15 +0000 | ||
| 17281 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c 2010-08-20 13:27:11 +0000 | ||
| 17282 | @@ -17,5 +17,5 @@ | ||
| 17283 | out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 17284 | } | ||
| 17285 | |||
| 17286 | -/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17287 | +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17288 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17289 | |||
| 17290 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpf32.c' | ||
| 17291 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c 2010-07-29 15:38:15 +0000 | ||
| 17292 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c 2010-08-20 13:27:11 +0000 | ||
| 17293 | @@ -17,5 +17,5 @@ | ||
| 17294 | out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 17295 | } | ||
| 17296 | |||
| 17297 | -/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17298 | +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17299 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17300 | |||
| 17301 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpp16.c' | ||
| 17302 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c 2010-07-29 15:38:15 +0000 | ||
| 17303 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c 2010-08-20 13:27:11 +0000 | ||
| 17304 | @@ -17,5 +17,5 @@ | ||
| 17305 | out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t); | ||
| 17306 | } | ||
| 17307 | |||
| 17308 | -/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17309 | +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17310 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17311 | |||
| 17312 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpp8.c' | ||
| 17313 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c 2010-07-29 15:38:15 +0000 | ||
| 17314 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c 2010-08-20 13:27:11 +0000 | ||
| 17315 | @@ -17,5 +17,5 @@ | ||
| 17316 | out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t); | ||
| 17317 | } | ||
| 17318 | |||
| 17319 | -/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17320 | +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17321 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17322 | |||
| 17323 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzps16.c' | ||
| 17324 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzps16.c 2010-07-29 15:38:15 +0000 | ||
| 17325 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzps16.c 2010-08-20 13:27:11 +0000 | ||
| 17326 | @@ -17,5 +17,5 @@ | ||
| 17327 | out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 17328 | } | ||
| 17329 | |||
| 17330 | -/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17331 | +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17332 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17333 | |||
| 17334 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzps32.c' | ||
| 17335 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzps32.c 2010-07-29 15:38:15 +0000 | ||
| 17336 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzps32.c 2010-08-20 13:27:11 +0000 | ||
| 17337 | @@ -17,5 +17,5 @@ | ||
| 17338 | out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 17339 | } | ||
| 17340 | |||
| 17341 | -/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17342 | +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17343 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17344 | |||
| 17345 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzps8.c' | ||
| 17346 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzps8.c 2010-07-29 15:38:15 +0000 | ||
| 17347 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzps8.c 2010-08-20 13:27:11 +0000 | ||
| 17348 | @@ -17,5 +17,5 @@ | ||
| 17349 | out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 17350 | } | ||
| 17351 | |||
| 17352 | -/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17353 | +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17354 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17355 | |||
| 17356 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpu16.c' | ||
| 17357 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c 2010-07-29 15:38:15 +0000 | ||
| 17358 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c 2010-08-20 13:27:11 +0000 | ||
| 17359 | @@ -17,5 +17,5 @@ | ||
| 17360 | out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 17361 | } | ||
| 17362 | |||
| 17363 | -/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17364 | +/* { dg-final { scan-assembler "vuzp\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17365 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17366 | |||
| 17367 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpu32.c' | ||
| 17368 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c 2010-07-29 15:38:15 +0000 | ||
| 17369 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c 2010-08-20 13:27:11 +0000 | ||
| 17370 | @@ -17,5 +17,5 @@ | ||
| 17371 | out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 17372 | } | ||
| 17373 | |||
| 17374 | -/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17375 | +/* { dg-final { scan-assembler "vuzp\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17376 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17377 | |||
| 17378 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vuzpu8.c' | ||
| 17379 | --- old/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c 2010-07-29 15:38:15 +0000 | ||
| 17380 | +++ new/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c 2010-08-20 13:27:11 +0000 | ||
| 17381 | @@ -17,5 +17,5 @@ | ||
| 17382 | out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 17383 | } | ||
| 17384 | |||
| 17385 | -/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17386 | +/* { dg-final { scan-assembler "vuzp\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17387 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17388 | |||
| 17389 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQf32.c' | ||
| 17390 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c 2010-07-29 15:38:15 +0000 | ||
| 17391 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c 2010-08-20 13:27:11 +0000 | ||
| 17392 | @@ -17,5 +17,5 @@ | ||
| 17393 | out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t); | ||
| 17394 | } | ||
| 17395 | |||
| 17396 | -/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17397 | +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17398 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17399 | |||
| 17400 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQp16.c' | ||
| 17401 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c 2010-07-29 15:38:15 +0000 | ||
| 17402 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c 2010-08-20 13:27:11 +0000 | ||
| 17403 | @@ -17,5 +17,5 @@ | ||
| 17404 | out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t); | ||
| 17405 | } | ||
| 17406 | |||
| 17407 | -/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17408 | +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17409 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17410 | |||
| 17411 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQp8.c' | ||
| 17412 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c 2010-07-29 15:38:15 +0000 | ||
| 17413 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c 2010-08-20 13:27:11 +0000 | ||
| 17414 | @@ -17,5 +17,5 @@ | ||
| 17415 | out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t); | ||
| 17416 | } | ||
| 17417 | |||
| 17418 | -/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17419 | +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17420 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17421 | |||
| 17422 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQs16.c' | ||
| 17423 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c 2010-07-29 15:38:15 +0000 | ||
| 17424 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c 2010-08-20 13:27:11 +0000 | ||
| 17425 | @@ -17,5 +17,5 @@ | ||
| 17426 | out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t); | ||
| 17427 | } | ||
| 17428 | |||
| 17429 | -/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17430 | +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17431 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17432 | |||
| 17433 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQs32.c' | ||
| 17434 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c 2010-07-29 15:38:15 +0000 | ||
| 17435 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c 2010-08-20 13:27:11 +0000 | ||
| 17436 | @@ -17,5 +17,5 @@ | ||
| 17437 | out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t); | ||
| 17438 | } | ||
| 17439 | |||
| 17440 | -/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17441 | +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17442 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17443 | |||
| 17444 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQs8.c' | ||
| 17445 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c 2010-07-29 15:38:15 +0000 | ||
| 17446 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c 2010-08-20 13:27:11 +0000 | ||
| 17447 | @@ -17,5 +17,5 @@ | ||
| 17448 | out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t); | ||
| 17449 | } | ||
| 17450 | |||
| 17451 | -/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17452 | +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17453 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17454 | |||
| 17455 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQu16.c' | ||
| 17456 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c 2010-07-29 15:38:15 +0000 | ||
| 17457 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c 2010-08-20 13:27:11 +0000 | ||
| 17458 | @@ -17,5 +17,5 @@ | ||
| 17459 | out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); | ||
| 17460 | } | ||
| 17461 | |||
| 17462 | -/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17463 | +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17464 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17465 | |||
| 17466 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQu32.c' | ||
| 17467 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c 2010-07-29 15:38:15 +0000 | ||
| 17468 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c 2010-08-20 13:27:11 +0000 | ||
| 17469 | @@ -17,5 +17,5 @@ | ||
| 17470 | out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); | ||
| 17471 | } | ||
| 17472 | |||
| 17473 | -/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17474 | +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17475 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17476 | |||
| 17477 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipQu8.c' | ||
| 17478 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c 2010-07-29 15:38:15 +0000 | ||
| 17479 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c 2010-08-20 13:27:11 +0000 | ||
| 17480 | @@ -17,5 +17,5 @@ | ||
| 17481 | out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); | ||
| 17482 | } | ||
| 17483 | |||
| 17484 | -/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17485 | +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17486 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17487 | |||
| 17488 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipf32.c' | ||
| 17489 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipf32.c 2010-07-29 15:38:15 +0000 | ||
| 17490 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipf32.c 2010-08-20 13:27:11 +0000 | ||
| 17491 | @@ -17,5 +17,5 @@ | ||
| 17492 | out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t); | ||
| 17493 | } | ||
| 17494 | |||
| 17495 | -/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17496 | +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17497 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17498 | |||
| 17499 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipp16.c' | ||
| 17500 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipp16.c 2010-07-29 15:38:15 +0000 | ||
| 17501 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipp16.c 2010-08-20 13:27:11 +0000 | ||
| 17502 | @@ -17,5 +17,5 @@ | ||
| 17503 | out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t); | ||
| 17504 | } | ||
| 17505 | |||
| 17506 | -/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17507 | +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17508 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17509 | |||
| 17510 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipp8.c' | ||
| 17511 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipp8.c 2010-07-29 15:38:15 +0000 | ||
| 17512 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipp8.c 2010-08-20 13:27:11 +0000 | ||
| 17513 | @@ -17,5 +17,5 @@ | ||
| 17514 | out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t); | ||
| 17515 | } | ||
| 17516 | |||
| 17517 | -/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17518 | +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17519 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17520 | |||
| 17521 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzips16.c' | ||
| 17522 | --- old/gcc/testsuite/gcc.target/arm/neon/vzips16.c 2010-07-29 15:38:15 +0000 | ||
| 17523 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzips16.c 2010-08-20 13:27:11 +0000 | ||
| 17524 | @@ -17,5 +17,5 @@ | ||
| 17525 | out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t); | ||
| 17526 | } | ||
| 17527 | |||
| 17528 | -/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17529 | +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17530 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17531 | |||
| 17532 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzips32.c' | ||
| 17533 | --- old/gcc/testsuite/gcc.target/arm/neon/vzips32.c 2010-07-29 15:38:15 +0000 | ||
| 17534 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzips32.c 2010-08-20 13:27:11 +0000 | ||
| 17535 | @@ -17,5 +17,5 @@ | ||
| 17536 | out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t); | ||
| 17537 | } | ||
| 17538 | |||
| 17539 | -/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17540 | +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17541 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17542 | |||
| 17543 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzips8.c' | ||
| 17544 | --- old/gcc/testsuite/gcc.target/arm/neon/vzips8.c 2010-07-29 15:38:15 +0000 | ||
| 17545 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzips8.c 2010-08-20 13:27:11 +0000 | ||
| 17546 | @@ -17,5 +17,5 @@ | ||
| 17547 | out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t); | ||
| 17548 | } | ||
| 17549 | |||
| 17550 | -/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17551 | +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17552 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17553 | |||
| 17554 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipu16.c' | ||
| 17555 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipu16.c 2010-07-29 15:38:15 +0000 | ||
| 17556 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipu16.c 2010-08-20 13:27:11 +0000 | ||
| 17557 | @@ -17,5 +17,5 @@ | ||
| 17558 | out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t); | ||
| 17559 | } | ||
| 17560 | |||
| 17561 | -/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17562 | +/* { dg-final { scan-assembler "vzip\.16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17563 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17564 | |||
| 17565 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipu32.c' | ||
| 17566 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipu32.c 2010-07-29 15:38:15 +0000 | ||
| 17567 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipu32.c 2010-08-20 13:27:11 +0000 | ||
| 17568 | @@ -17,5 +17,5 @@ | ||
| 17569 | out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t); | ||
| 17570 | } | ||
| 17571 | |||
| 17572 | -/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17573 | +/* { dg-final { scan-assembler "vzip\.32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17574 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17575 | |||
| 17576 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vzipu8.c' | ||
| 17577 | --- old/gcc/testsuite/gcc.target/arm/neon/vzipu8.c 2010-07-29 15:38:15 +0000 | ||
| 17578 | +++ new/gcc/testsuite/gcc.target/arm/neon/vzipu8.c 2010-08-20 13:27:11 +0000 | ||
| 17579 | @@ -17,5 +17,5 @@ | ||
| 17580 | out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t); | ||
| 17581 | } | ||
| 17582 | |||
| 17583 | -/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ | ||
| 17584 | +/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@.*\)?\n" } } */ | ||
| 17585 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 17586 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99363.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99363.patch deleted file mode 100644 index 7003cf837..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99363.patch +++ /dev/null | |||
| @@ -1,95 +0,0 @@ | |||
| 1 | 2010-08-05 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #7257 | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | 2010-08-05 Jie Zhang <jie@codesourcery.com> | ||
| 9 | PR tree-optimization/45144 | ||
| 10 | * tree-sra.c (type_consists_of_records_p): Return false | ||
| 11 | if the record contains bit-field. | ||
| 12 | |||
| 13 | gcc/testsuite/ | ||
| 14 | 2010-08-05 Jie Zhang <jie@codesourcery.com> | ||
| 15 | PR tree-optimization/45144 | ||
| 16 | * gcc.dg/tree-ssa/pr45144.c: New test. | ||
| 17 | |||
| 18 | 2010-08-04 Mark Mitchell <mark@codesourcery.com> | ||
| 19 | |||
| 20 | Backport from mainline: | ||
| 21 | |||
| 22 | === added file 'gcc/testsuite/gcc.dg/tree-ssa/pr45144.c' | ||
| 23 | --- old/gcc/testsuite/gcc.dg/tree-ssa/pr45144.c 1970-01-01 00:00:00 +0000 | ||
| 24 | +++ new/gcc/testsuite/gcc.dg/tree-ssa/pr45144.c 2010-08-20 16:04:44 +0000 | ||
| 25 | @@ -0,0 +1,46 @@ | ||
| 26 | +/* { dg-do compile } */ | ||
| 27 | +/* { dg-options "-O2 -fdump-tree-optimized" } */ | ||
| 28 | + | ||
| 29 | +void baz (unsigned); | ||
| 30 | + | ||
| 31 | +extern unsigned buf[]; | ||
| 32 | + | ||
| 33 | +struct A | ||
| 34 | +{ | ||
| 35 | + unsigned a1:10; | ||
| 36 | + unsigned a2:3; | ||
| 37 | + unsigned:19; | ||
| 38 | +}; | ||
| 39 | + | ||
| 40 | +union TMP | ||
| 41 | +{ | ||
| 42 | + struct A a; | ||
| 43 | + unsigned int b; | ||
| 44 | +}; | ||
| 45 | + | ||
| 46 | +static unsigned | ||
| 47 | +foo (struct A *p) | ||
| 48 | +{ | ||
| 49 | + union TMP t; | ||
| 50 | + struct A x; | ||
| 51 | + | ||
| 52 | + x = *p; | ||
| 53 | + t.a = x; | ||
| 54 | + return t.b; | ||
| 55 | +} | ||
| 56 | + | ||
| 57 | +void | ||
| 58 | +bar (unsigned orig, unsigned *new) | ||
| 59 | +{ | ||
| 60 | + struct A a; | ||
| 61 | + union TMP s; | ||
| 62 | + | ||
| 63 | + s.b = orig; | ||
| 64 | + a = s.a; | ||
| 65 | + if (a.a1) | ||
| 66 | + baz (a.a2); | ||
| 67 | + *new = foo (&a); | ||
| 68 | +} | ||
| 69 | + | ||
| 70 | +/* { dg-final { scan-tree-dump "x = a;" "optimized"} } */ | ||
| 71 | +/* { dg-final { cleanup-tree-dump "optimized" } } */ | ||
| 72 | |||
| 73 | === modified file 'gcc/tree-sra.c' | ||
| 74 | --- old/gcc/tree-sra.c 2010-08-10 13:31:21 +0000 | ||
| 75 | +++ new/gcc/tree-sra.c 2010-08-20 16:04:44 +0000 | ||
| 76 | @@ -805,7 +805,7 @@ | ||
| 77 | /* Return true iff TYPE is a RECORD_TYPE with fields that are either of gimple | ||
| 78 | register types or (recursively) records with only these two kinds of fields. | ||
| 79 | It also returns false if any of these records has a zero-size field as its | ||
| 80 | - last field. */ | ||
| 81 | + last field or has a bit-field. */ | ||
| 82 | |||
| 83 | static bool | ||
| 84 | type_consists_of_records_p (tree type) | ||
| 85 | @@ -821,6 +821,9 @@ | ||
| 86 | { | ||
| 87 | tree ft = TREE_TYPE (fld); | ||
| 88 | |||
| 89 | + if (DECL_BIT_FIELD (fld)) | ||
| 90 | + return false; | ||
| 91 | + | ||
| 92 | if (!is_gimple_reg_type (ft) | ||
| 93 | && !type_consists_of_records_p (ft)) | ||
| 94 | return false; | ||
| 95 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99364.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99364.patch deleted file mode 100644 index 8ae781eca..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99364.patch +++ /dev/null | |||
| @@ -1,511 +0,0 @@ | |||
| 1 | 2010-08-05 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline (candidate patch): | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * expr.c (expand_assignment): Add assertion to prevent emitting null | ||
| 7 | rtx for movmisalign pattern. | ||
| 8 | (expand_expr_real_1): Likewise. | ||
| 9 | * config/arm/arm.c (arm_builtin_support_vector_misalignment): New. | ||
| 10 | (TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): New. Use above. | ||
| 11 | (arm_vector_alignment_reachable): New. | ||
| 12 | (TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE): New. Use above. | ||
| 13 | (neon_vector_mem_operand): Disallow PRE_DEC for misaligned loads. | ||
| 14 | (arm_print_operand): Include alignment qualifier in %A. | ||
| 15 | * config/arm/neon.md (UNSPEC_MISALIGNED_ACCESS): New constant. | ||
| 16 | (movmisalign<mode>): New expander. | ||
| 17 | (movmisalign<mode>_neon_store, movmisalign<mode>_neon_load): New | ||
| 18 | insn patterns. | ||
| 19 | |||
| 20 | gcc/testsuite/ | ||
| 21 | * gcc.dg/vect/vect-42.c: Use vect_element_align instead of | ||
| 22 | vect_hw_misalign. | ||
| 23 | * gcc.dg/vect/vect-60.c: Likewise. | ||
| 24 | * gcc.dg/vect/vect-56.c: Likewise. | ||
| 25 | * gcc.dg/vect/vect-93.c: Likewise. | ||
| 26 | * gcc.dg/vect/no-scevccp-outer-8.c: Likewise. | ||
| 27 | * gcc.dg/vect/vect-95.c: Likewise. | ||
| 28 | * gcc.dg/vect/vect-96.c: Likewise. | ||
| 29 | * gcc.dg/vect/vect-outer-5.c: Use quad-word vectors when available. | ||
| 30 | * gcc.dg/vect/slp-25.c: Likewise. | ||
| 31 | * gcc.dg/vect/slp-3.c: Likewise. | ||
| 32 | * gcc.dg/vect/vect-multitypes-1.c: Likewise. | ||
| 33 | * gcc.dg/vect/no-vfa-pr29145.c: Likewise. | ||
| 34 | * gcc.dg/vect/vect-multitypes-4.c: Likewise. Use vect_element_align. | ||
| 35 | * gcc.dg/vect/vect-109.c: Likewise. | ||
| 36 | * gcc.dg/vect/vect-peel-1.c: Likewise. | ||
| 37 | * gcc.dg/vect/vect-peel-2.c: Likewise. | ||
| 38 | * lib/target-supports.exp | ||
| 39 | (check_effective_target_arm_vect_no_misalign): New. | ||
| 40 | (check_effective_target_vect_no_align): Use above. | ||
| 41 | (check_effective_target_vect_element_align): New. | ||
| 42 | (add_options_for_quad_vectors): New. | ||
| 43 | |||
| 44 | 2010-08-05 Jie Zhang <jie@codesourcery.com> | ||
| 45 | |||
| 46 | Issue #7257 | ||
| 47 | |||
| 48 | === modified file 'gcc/config/arm/arm.c' | ||
| 49 | --- old/gcc/config/arm/arm.c 2010-08-16 09:41:58 +0000 | ||
| 50 | +++ new/gcc/config/arm/arm.c 2010-08-20 16:21:01 +0000 | ||
| 51 | @@ -228,6 +228,11 @@ | ||
| 52 | static void arm_trampoline_init (rtx, tree, rtx); | ||
| 53 | static rtx arm_trampoline_adjust_address (rtx); | ||
| 54 | static rtx arm_pic_static_addr (rtx orig, rtx reg); | ||
| 55 | +static bool arm_vector_alignment_reachable (const_tree type, bool is_packed); | ||
| 56 | +static bool arm_builtin_support_vector_misalignment (enum machine_mode mode, | ||
| 57 | + const_tree type, | ||
| 58 | + int misalignment, | ||
| 59 | + bool is_packed); | ||
| 60 | |||
| 61 | |||
| 62 | /* Table of machine attributes. */ | ||
| 63 | @@ -514,6 +519,14 @@ | ||
| 64 | #undef TARGET_CAN_ELIMINATE | ||
| 65 | #define TARGET_CAN_ELIMINATE arm_can_eliminate | ||
| 66 | |||
| 67 | +#undef TARGET_VECTOR_ALIGNMENT_REACHABLE | ||
| 68 | +#define TARGET_VECTOR_ALIGNMENT_REACHABLE \ | ||
| 69 | + arm_vector_alignment_reachable | ||
| 70 | + | ||
| 71 | +#undef TARGET_SUPPORT_VECTOR_MISALIGNMENT | ||
| 72 | +#define TARGET_SUPPORT_VECTOR_MISALIGNMENT \ | ||
| 73 | + arm_builtin_support_vector_misalignment | ||
| 74 | + | ||
| 75 | struct gcc_target targetm = TARGET_INITIALIZER; | ||
| 76 | |||
| 77 | /* Obstack for minipool constant handling. */ | ||
| 78 | @@ -9084,7 +9097,8 @@ | ||
| 79 | return arm_address_register_rtx_p (ind, 0); | ||
| 80 | |||
| 81 | /* Allow post-increment with Neon registers. */ | ||
| 82 | - if (type != 1 && (GET_CODE (ind) == POST_INC || GET_CODE (ind) == PRE_DEC)) | ||
| 83 | + if ((type != 1 && GET_CODE (ind) == POST_INC) | ||
| 84 | + || (type == 0 && GET_CODE (ind) == PRE_DEC)) | ||
| 85 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); | ||
| 86 | |||
| 87 | /* FIXME: vld1 allows register post-modify. */ | ||
| 88 | @@ -16365,6 +16379,8 @@ | ||
| 89 | { | ||
| 90 | rtx addr; | ||
| 91 | bool postinc = FALSE; | ||
| 92 | + unsigned align, modesize, align_bits; | ||
| 93 | + | ||
| 94 | gcc_assert (GET_CODE (x) == MEM); | ||
| 95 | addr = XEXP (x, 0); | ||
| 96 | if (GET_CODE (addr) == POST_INC) | ||
| 97 | @@ -16372,7 +16388,29 @@ | ||
| 98 | postinc = 1; | ||
| 99 | addr = XEXP (addr, 0); | ||
| 100 | } | ||
| 101 | - asm_fprintf (stream, "[%r]", REGNO (addr)); | ||
| 102 | + asm_fprintf (stream, "[%r", REGNO (addr)); | ||
| 103 | + | ||
| 104 | + /* We know the alignment of this access, so we can emit a hint in the | ||
| 105 | + instruction (for some alignments) as an aid to the memory subsystem | ||
| 106 | + of the target. */ | ||
| 107 | + align = MEM_ALIGN (x) >> 3; | ||
| 108 | + modesize = GET_MODE_SIZE (GET_MODE (x)); | ||
| 109 | + | ||
| 110 | + /* Only certain alignment specifiers are supported by the hardware. */ | ||
| 111 | + if (modesize == 16 && (align % 32) == 0) | ||
| 112 | + align_bits = 256; | ||
| 113 | + else if ((modesize == 8 || modesize == 16) && (align % 16) == 0) | ||
| 114 | + align_bits = 128; | ||
| 115 | + else if ((align % 8) == 0) | ||
| 116 | + align_bits = 64; | ||
| 117 | + else | ||
| 118 | + align_bits = 0; | ||
| 119 | + | ||
| 120 | + if (align_bits != 0) | ||
| 121 | + asm_fprintf (stream, ", :%d", align_bits); | ||
| 122 | + | ||
| 123 | + asm_fprintf (stream, "]"); | ||
| 124 | + | ||
| 125 | if (postinc) | ||
| 126 | fputs("!", stream); | ||
| 127 | } | ||
| 128 | @@ -22450,4 +22488,43 @@ | ||
| 129 | return !TARGET_THUMB1; | ||
| 130 | } | ||
| 131 | |||
| 132 | +static bool | ||
| 133 | +arm_vector_alignment_reachable (const_tree type, bool is_packed) | ||
| 134 | +{ | ||
| 135 | + /* Vectors which aren't in packed structures will not be less aligned than | ||
| 136 | + the natural alignment of their element type, so this is safe. */ | ||
| 137 | + if (TARGET_NEON && !BYTES_BIG_ENDIAN) | ||
| 138 | + return !is_packed; | ||
| 139 | + | ||
| 140 | + return default_builtin_vector_alignment_reachable (type, is_packed); | ||
| 141 | +} | ||
| 142 | + | ||
| 143 | +static bool | ||
| 144 | +arm_builtin_support_vector_misalignment (enum machine_mode mode, | ||
| 145 | + const_tree type, int misalignment, | ||
| 146 | + bool is_packed) | ||
| 147 | +{ | ||
| 148 | + if (TARGET_NEON && !BYTES_BIG_ENDIAN) | ||
| 149 | + { | ||
| 150 | + HOST_WIDE_INT align = TYPE_ALIGN_UNIT (type); | ||
| 151 | + | ||
| 152 | + if (is_packed) | ||
| 153 | + return align == 1; | ||
| 154 | + | ||
| 155 | + /* If the misalignment is unknown, we should be able to handle the access | ||
| 156 | + so long as it is not to a member of a packed data structure. */ | ||
| 157 | + if (misalignment == -1) | ||
| 158 | + return true; | ||
| 159 | + | ||
| 160 | + /* Return true if the misalignment is a multiple of the natural alignment | ||
| 161 | + of the vector's element type. This is probably always going to be | ||
| 162 | + true in practice, since we've already established that this isn't a | ||
| 163 | + packed access. */ | ||
| 164 | + return ((misalignment % align) == 0); | ||
| 165 | + } | ||
| 166 | + | ||
| 167 | + return default_builtin_support_vector_misalignment (mode, type, misalignment, | ||
| 168 | + is_packed); | ||
| 169 | +} | ||
| 170 | + | ||
| 171 | #include "gt-arm.h" | ||
| 172 | |||
| 173 | === modified file 'gcc/config/arm/neon.md' | ||
| 174 | --- old/gcc/config/arm/neon.md 2010-08-13 11:40:17 +0000 | ||
| 175 | +++ new/gcc/config/arm/neon.md 2010-08-20 16:21:01 +0000 | ||
| 176 | @@ -140,7 +140,8 @@ | ||
| 177 | (UNSPEC_VUZP1 201) | ||
| 178 | (UNSPEC_VUZP2 202) | ||
| 179 | (UNSPEC_VZIP1 203) | ||
| 180 | - (UNSPEC_VZIP2 204)]) | ||
| 181 | + (UNSPEC_VZIP2 204) | ||
| 182 | + (UNSPEC_MISALIGNED_ACCESS 205)]) | ||
| 183 | |||
| 184 | ;; Double-width vector modes. | ||
| 185 | (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) | ||
| 186 | @@ -660,6 +661,52 @@ | ||
| 187 | neon_disambiguate_copy (operands, dest, src, 4); | ||
| 188 | }) | ||
| 189 | |||
| 190 | +(define_expand "movmisalign<mode>" | ||
| 191 | + [(set (match_operand:VDQX 0 "nonimmediate_operand" "") | ||
| 192 | + (unspec:VDQX [(match_operand:VDQX 1 "general_operand" "")] | ||
| 193 | + UNSPEC_MISALIGNED_ACCESS))] | ||
| 194 | + "TARGET_NEON && !BYTES_BIG_ENDIAN" | ||
| 195 | +{ | ||
| 196 | + /* This pattern is not permitted to fail during expansion: if both arguments | ||
| 197 | + are non-registers (e.g. memory := constant, which can be created by the | ||
| 198 | + auto-vectorizer), force operand 1 into a register. */ | ||
| 199 | + if (!s_register_operand (operands[0], <MODE>mode) | ||
| 200 | + && !s_register_operand (operands[1], <MODE>mode)) | ||
| 201 | + operands[1] = force_reg (<MODE>mode, operands[1]); | ||
| 202 | +}) | ||
| 203 | + | ||
| 204 | +(define_insn "*movmisalign<mode>_neon_store" | ||
| 205 | + [(set (match_operand:VDX 0 "memory_operand" "=Um") | ||
| 206 | + (unspec:VDX [(match_operand:VDX 1 "s_register_operand" " w")] | ||
| 207 | + UNSPEC_MISALIGNED_ACCESS))] | ||
| 208 | + "TARGET_NEON && !BYTES_BIG_ENDIAN" | ||
| 209 | + "vst1.<V_sz_elem>\t{%P1}, %A0" | ||
| 210 | + [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) | ||
| 211 | + | ||
| 212 | +(define_insn "*movmisalign<mode>_neon_load" | ||
| 213 | + [(set (match_operand:VDX 0 "s_register_operand" "=w") | ||
| 214 | + (unspec:VDX [(match_operand:VDX 1 "memory_operand" " Um")] | ||
| 215 | + UNSPEC_MISALIGNED_ACCESS))] | ||
| 216 | + "TARGET_NEON && !BYTES_BIG_ENDIAN" | ||
| 217 | + "vld1.<V_sz_elem>\t{%P0}, %A1" | ||
| 218 | + [(set_attr "neon_type" "neon_vld1_1_2_regs")]) | ||
| 219 | + | ||
| 220 | +(define_insn "*movmisalign<mode>_neon_store" | ||
| 221 | + [(set (match_operand:VQX 0 "memory_operand" "=Um") | ||
| 222 | + (unspec:VQX [(match_operand:VQX 1 "s_register_operand" " w")] | ||
| 223 | + UNSPEC_MISALIGNED_ACCESS))] | ||
| 224 | + "TARGET_NEON && !BYTES_BIG_ENDIAN" | ||
| 225 | + "vst1.<V_sz_elem>\t{%q1}, %A0" | ||
| 226 | + [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) | ||
| 227 | + | ||
| 228 | +(define_insn "*movmisalign<mode>_neon_load" | ||
| 229 | + [(set (match_operand:VQX 0 "s_register_operand" "=w") | ||
| 230 | + (unspec:VQX [(match_operand:VQX 1 "memory_operand" " Um")] | ||
| 231 | + UNSPEC_MISALIGNED_ACCESS))] | ||
| 232 | + "TARGET_NEON && !BYTES_BIG_ENDIAN" | ||
| 233 | + "vld1.<V_sz_elem>\t{%q0}, %A1" | ||
| 234 | + [(set_attr "neon_type" "neon_vld1_1_2_regs")]) | ||
| 235 | + | ||
| 236 | (define_insn "vec_set<mode>_internal" | ||
| 237 | [(set (match_operand:VD 0 "s_register_operand" "=w") | ||
| 238 | (vec_merge:VD | ||
| 239 | |||
| 240 | === modified file 'gcc/expr.c' | ||
| 241 | --- old/gcc/expr.c 2010-08-12 13:51:16 +0000 | ||
| 242 | +++ new/gcc/expr.c 2010-08-20 16:21:01 +0000 | ||
| 243 | @@ -4362,7 +4362,10 @@ | ||
| 244 | && op_mode1 != VOIDmode) | ||
| 245 | reg = copy_to_mode_reg (op_mode1, reg); | ||
| 246 | |||
| 247 | - insn = GEN_FCN (icode) (mem, reg); | ||
| 248 | + insn = GEN_FCN (icode) (mem, reg); | ||
| 249 | + /* The movmisalign<mode> pattern cannot fail, else the assignment would | ||
| 250 | + silently be omitted. */ | ||
| 251 | + gcc_assert (insn != NULL_RTX); | ||
| 252 | emit_insn (insn); | ||
| 253 | return; | ||
| 254 | } | ||
| 255 | @@ -8742,6 +8745,7 @@ | ||
| 256 | |||
| 257 | /* Nor can the insn generator. */ | ||
| 258 | insn = GEN_FCN (icode) (reg, temp); | ||
| 259 | + gcc_assert (insn != NULL_RTX); | ||
| 260 | emit_insn (insn); | ||
| 261 | |||
| 262 | return reg; | ||
| 263 | |||
| 264 | === modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c' | ||
| 265 | --- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c 2009-06-05 14:28:50 +0000 | ||
| 266 | +++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-8.c 2010-08-20 16:21:01 +0000 | ||
| 267 | @@ -46,5 +46,5 @@ | ||
| 268 | return 0; | ||
| 269 | } | ||
| 270 | |||
| 271 | -/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { xfail { ! { vect_hw_misalign } } } } } */ | ||
| 272 | +/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { xfail { ! { vect_element_align } } } } } */ | ||
| 273 | /* { dg-final { cleanup-tree-dump "vect" } } */ | ||
| 274 | |||
| 275 | === modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c' | ||
| 276 | --- old/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c 2008-08-18 19:36:03 +0000 | ||
| 277 | +++ new/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c 2010-08-20 16:21:01 +0000 | ||
| 278 | @@ -1,4 +1,5 @@ | ||
| 279 | /* { dg-require-effective-target vect_int } */ | ||
| 280 | +/* { dg-add-options quad_vectors } */ | ||
| 281 | |||
| 282 | #include <stdarg.h> | ||
| 283 | #include "tree-vect.h" | ||
| 284 | |||
| 285 | === modified file 'gcc/testsuite/gcc.dg/vect/slp-25.c' | ||
| 286 | --- old/gcc/testsuite/gcc.dg/vect/slp-25.c 2009-10-27 11:46:07 +0000 | ||
| 287 | +++ new/gcc/testsuite/gcc.dg/vect/slp-25.c 2010-08-20 16:21:01 +0000 | ||
| 288 | @@ -1,4 +1,5 @@ | ||
| 289 | /* { dg-require-effective-target vect_int } */ | ||
| 290 | +/* { dg-add-options quad_vectors } */ | ||
| 291 | |||
| 292 | #include <stdarg.h> | ||
| 293 | #include "tree-vect.h" | ||
| 294 | |||
| 295 | === modified file 'gcc/testsuite/gcc.dg/vect/slp-3.c' | ||
| 296 | --- old/gcc/testsuite/gcc.dg/vect/slp-3.c 2009-05-12 13:05:28 +0000 | ||
| 297 | +++ new/gcc/testsuite/gcc.dg/vect/slp-3.c 2010-08-20 16:21:01 +0000 | ||
| 298 | @@ -1,4 +1,5 @@ | ||
| 299 | /* { dg-require-effective-target vect_int } */ | ||
| 300 | +/* { dg-add-options quad_vectors } */ | ||
| 301 | |||
| 302 | #include <stdarg.h> | ||
| 303 | #include <stdio.h> | ||
| 304 | |||
| 305 | === modified file 'gcc/testsuite/gcc.dg/vect/vect-109.c' | ||
| 306 | --- old/gcc/testsuite/gcc.dg/vect/vect-109.c 2010-07-10 20:38:32 +0000 | ||
| 307 | +++ new/gcc/testsuite/gcc.dg/vect/vect-109.c 2010-08-20 16:21:01 +0000 | ||
| 308 | @@ -1,4 +1,5 @@ | ||
| 309 | /* { dg-require-effective-target vect_int } */ | ||
| 310 | +/* { dg-add-options quad_vectors } */ | ||
| 311 | |||
| 312 | #include <stdarg.h> | ||
| 313 | #include "tree-vect.h" | ||
| 314 | @@ -72,8 +73,8 @@ | ||
| 315 | return 0; | ||
| 316 | } | ||
| 317 | |||
| 318 | -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_hw_misalign } } } */ | ||
| 319 | -/* { dg-final { scan-tree-dump-times "not vectorized: unsupported unaligned store" 2 "vect" { xfail vect_hw_misalign } } } */ | ||
| 320 | -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 10 "vect" { target vect_hw_misalign } } } */ | ||
| 321 | +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_element_align } } } */ | ||
| 322 | +/* { dg-final { scan-tree-dump-times "not vectorized: unsupported unaligned store" 2 "vect" { xfail vect_element_align } } } */ | ||
| 323 | +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 10 "vect" { target vect_element_align } } } */ | ||
| 324 | /* { dg-final { cleanup-tree-dump "vect" } } */ | ||
| 325 | |||
| 326 | |||
| 327 | === modified file 'gcc/testsuite/gcc.dg/vect/vect-42.c' | ||
| 328 | --- old/gcc/testsuite/gcc.dg/vect/vect-42.c 2009-11-04 10:22:22 +0000 | ||
| 329 | +++ new/gcc/testsuite/gcc.dg/vect/vect-42.c 2010-08-20 16:21:01 +0000 | ||
| 330 | @@ -64,7 +64,7 @@ | ||
| 331 | |||
| 332 | /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ | ||
| 333 | /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 3 "vect" { target vect_no_align } } } */ | ||
| 334 | -/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { { ! vector_alignment_reachable } && { ! vect_hw_misalign } } } } } */ | ||
| 335 | +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { { ! vector_alignment_reachable } && { ! vect_element_align } } } } } */ | ||
| 336 | /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || { ! vector_alignment_reachable } } } } } */ | ||
| 337 | /* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || { ! vector_alignment_reachable } } } } } */ | ||
| 338 | /* { dg-final { cleanup-tree-dump "vect" } } */ | ||
| 339 | |||
| 340 | === modified file 'gcc/testsuite/gcc.dg/vect/vect-95.c' | ||
| 341 | --- old/gcc/testsuite/gcc.dg/vect/vect-95.c 2009-10-27 11:46:07 +0000 | ||
| 342 | +++ new/gcc/testsuite/gcc.dg/vect/vect-95.c 2010-08-20 16:21:01 +0000 | ||
| 343 | @@ -56,14 +56,14 @@ | ||
| 344 | } | ||
| 345 | |||
| 346 | /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ | ||
| 347 | -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { xfail {vect_hw_misalign} } } } */ | ||
| 348 | +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { xfail {vect_element_align} } } } */ | ||
| 349 | |||
| 350 | /* For targets that support unaligned loads we version for the two unaligned | ||
| 351 | stores and generate misaligned accesses for the loads. For targets that | ||
| 352 | don't support unaligned loads we version for all four accesses. */ | ||
| 353 | |||
| 354 | -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_hw_misalign} } } } */ | ||
| 355 | -/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 2 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ | ||
| 356 | +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align} } } } */ | ||
| 357 | +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */ | ||
| 358 | /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target vect_no_align } } } */ | ||
| 359 | /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 4 "vect" { target vect_no_align } } } */ | ||
| 360 | /* { dg-final { cleanup-tree-dump "vect" } } */ | ||
| 361 | |||
| 362 | === modified file 'gcc/testsuite/gcc.dg/vect/vect-96.c' | ||
| 363 | --- old/gcc/testsuite/gcc.dg/vect/vect-96.c 2009-10-27 11:46:07 +0000 | ||
| 364 | +++ new/gcc/testsuite/gcc.dg/vect/vect-96.c 2010-08-20 16:21:01 +0000 | ||
| 365 | @@ -45,5 +45,5 @@ | ||
| 366 | /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ | ||
| 367 | /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { target { {! vect_no_align} && vector_alignment_reachable } } } } */ | ||
| 368 | /* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { { vect_no_align } || {! vector_alignment_reachable} } } } } */ | ||
| 369 | -/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 1 "vect" { target { vect_no_align || { {! vector_alignment_reachable} && {! vect_hw_misalign} } } } } } */ | ||
| 370 | +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 1 "vect" { target { vect_no_align || { {! vector_alignment_reachable} && {! vect_element_align} } } } } } */ | ||
| 371 | /* { dg-final { cleanup-tree-dump "vect" } } */ | ||
| 372 | |||
| 373 | === modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c' | ||
| 374 | --- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c 2009-10-27 11:46:07 +0000 | ||
| 375 | +++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c 2010-08-20 16:21:01 +0000 | ||
| 376 | @@ -1,4 +1,5 @@ | ||
| 377 | /* { dg-require-effective-target vect_int } */ | ||
| 378 | +/* { dg-add-options quad_vectors } */ | ||
| 379 | |||
| 380 | #include <stdarg.h> | ||
| 381 | #include "tree-vect.h" | ||
| 382 | @@ -78,11 +79,11 @@ | ||
| 383 | return 0; | ||
| 384 | } | ||
| 385 | |||
| 386 | -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_hw_misalign} } } } */ | ||
| 387 | -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ | ||
| 388 | -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_hw_misalign} } } } */ | ||
| 389 | -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ | ||
| 390 | +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_element_align} } } } */ | ||
| 391 | +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */ | ||
| 392 | +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_element_align} } } } */ | ||
| 393 | +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */ | ||
| 394 | /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail *-*-* } } } */ | ||
| 395 | -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ | ||
| 396 | +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */ | ||
| 397 | /* { dg-final { cleanup-tree-dump "vect" } } */ | ||
| 398 | |||
| 399 | |||
| 400 | === modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c' | ||
| 401 | --- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c 2009-10-27 11:46:07 +0000 | ||
| 402 | +++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c 2010-08-20 16:21:01 +0000 | ||
| 403 | @@ -1,4 +1,5 @@ | ||
| 404 | /* { dg-require-effective-target vect_int } */ | ||
| 405 | +/* { dg-add-options quad_vectors } */ | ||
| 406 | |||
| 407 | #include <stdarg.h> | ||
| 408 | #include "tree-vect.h" | ||
| 409 | @@ -85,11 +86,11 @@ | ||
| 410 | return 0; | ||
| 411 | } | ||
| 412 | |||
| 413 | -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_hw_misalign} } } } */ | ||
| 414 | -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ | ||
| 415 | -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_hw_misalign} } } } */ | ||
| 416 | -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ | ||
| 417 | +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail {! vect_element_align} } } } */ | ||
| 418 | +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */ | ||
| 419 | +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vect_element_align} } } } */ | ||
| 420 | +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */ | ||
| 421 | /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 8 "vect" { xfail *-*-* } } } */ | ||
| 422 | -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || vect_hw_misalign } } } } */ | ||
| 423 | +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || vect_element_align } } } } */ | ||
| 424 | /* { dg-final { cleanup-tree-dump "vect" } } */ | ||
| 425 | |||
| 426 | |||
| 427 | === modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-5.c' | ||
| 428 | --- old/gcc/testsuite/gcc.dg/vect/vect-outer-5.c 2009-05-08 12:39:01 +0000 | ||
| 429 | +++ new/gcc/testsuite/gcc.dg/vect/vect-outer-5.c 2010-08-20 16:21:01 +0000 | ||
| 430 | @@ -1,4 +1,5 @@ | ||
| 431 | /* { dg-require-effective-target vect_float } */ | ||
| 432 | +/* { dg-add-options quad_vectors } */ | ||
| 433 | |||
| 434 | #include <stdio.h> | ||
| 435 | #include <stdarg.h> | ||
| 436 | |||
| 437 | === modified file 'gcc/testsuite/lib/target-supports.exp' | ||
| 438 | --- old/gcc/testsuite/lib/target-supports.exp 2010-08-10 13:31:21 +0000 | ||
| 439 | +++ new/gcc/testsuite/lib/target-supports.exp 2010-08-20 16:21:01 +0000 | ||
| 440 | @@ -1642,6 +1642,18 @@ | ||
| 441 | }] | ||
| 442 | } | ||
| 443 | |||
| 444 | +# Return 1 if this is an ARM target that only supports aligned vector accesses | ||
| 445 | +proc check_effective_target_arm_vect_no_misalign { } { | ||
| 446 | + return [check_no_compiler_messages arm_vect_no_misalign assembly { | ||
| 447 | + #if !defined(__arm__) \ | ||
| 448 | + || (defined(__ARMEL__) \ | ||
| 449 | + && (!defined(__thumb__) || defined(__thumb2__))) | ||
| 450 | + #error FOO | ||
| 451 | + #endif | ||
| 452 | + }] | ||
| 453 | +} | ||
| 454 | + | ||
| 455 | + | ||
| 456 | # Return 1 if this is an ARM target supporting -mfpu=vfp | ||
| 457 | # -mfloat-abi=softfp. Some multilibs may be incompatible with these | ||
| 458 | # options. | ||
| 459 | @@ -2547,7 +2559,7 @@ | ||
| 460 | if { [istarget mipsisa64*-*-*] | ||
| 461 | || [istarget sparc*-*-*] | ||
| 462 | || [istarget ia64-*-*] | ||
| 463 | - || [check_effective_target_arm32] } { | ||
| 464 | + || [check_effective_target_arm_vect_no_misalign] } { | ||
| 465 | set et_vect_no_align_saved 1 | ||
| 466 | } | ||
| 467 | } | ||
| 468 | @@ -2682,6 +2694,25 @@ | ||
| 469 | return $et_vector_alignment_reachable_for_64bit_saved | ||
| 470 | } | ||
| 471 | |||
| 472 | +# Return 1 if the target only requires element alignment for vector accesses | ||
| 473 | + | ||
| 474 | +proc check_effective_target_vect_element_align { } { | ||
| 475 | + global et_vect_element_align | ||
| 476 | + | ||
| 477 | + if [info exists et_vect_element_align] { | ||
| 478 | + verbose "check_effective_target_vect_element_align: using cached result" 2 | ||
| 479 | + } else { | ||
| 480 | + set et_vect_element_align 0 | ||
| 481 | + if { [istarget arm*-*-*] | ||
| 482 | + || [check_effective_target_vect_hw_misalign] } { | ||
| 483 | + set et_vect_element_align 1 | ||
| 484 | + } | ||
| 485 | + } | ||
| 486 | + | ||
| 487 | + verbose "check_effective_target_vect_element_align: returning $et_vect_element_align" 2 | ||
| 488 | + return $et_vect_element_align | ||
| 489 | +} | ||
| 490 | + | ||
| 491 | # Return 1 if the target supports vector conditional operations, 0 otherwise. | ||
| 492 | |||
| 493 | proc check_effective_target_vect_condition { } { | ||
| 494 | @@ -3239,6 +3270,16 @@ | ||
| 495 | return $flags | ||
| 496 | } | ||
| 497 | |||
| 498 | +# Add to FLAGS the flags needed to enable 128-bit vectors. | ||
| 499 | + | ||
| 500 | +proc add_options_for_quad_vectors { flags } { | ||
| 501 | + if [is-effective-target arm_neon_ok] { | ||
| 502 | + return "$flags -mvectorize-with-neon-quad" | ||
| 503 | + } | ||
| 504 | + | ||
| 505 | + return $flags | ||
| 506 | +} | ||
| 507 | + | ||
| 508 | # Return 1 if the target provides a full C99 runtime. | ||
| 509 | |||
| 510 | proc check_effective_target_c99_runtime { } { | ||
| 511 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99365.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99365.patch deleted file mode 100644 index 36a942118..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99365.patch +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | 2010-08-12 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | gcc/testsuite/ | ||
| 6 | 2010-08-12 Jie Zhang <jie@codesourcery.com> | ||
| 7 | * gcc.dg/graphite/interchange-9.c (M): Define to be 111. | ||
| 8 | (N): Likewise. | ||
| 9 | (main): Adjust accordingly. | ||
| 10 | |||
| 11 | 2010-08-05 Julian Brown <julian@codesourcery.com> | ||
| 12 | |||
| 13 | Backport from mainline (candidate patch): | ||
| 14 | |||
| 15 | === modified file 'gcc/testsuite/gcc.dg/graphite/interchange-9.c' | ||
| 16 | --- old/gcc/testsuite/gcc.dg/graphite/interchange-9.c 2010-02-07 19:49:26 +0000 | ||
| 17 | +++ new/gcc/testsuite/gcc.dg/graphite/interchange-9.c 2010-08-20 16:32:45 +0000 | ||
| 18 | @@ -5,8 +5,8 @@ | ||
| 19 | #include <stdio.h> | ||
| 20 | #endif | ||
| 21 | |||
| 22 | -#define N 1111 | ||
| 23 | -#define M 1111 | ||
| 24 | +#define N 111 | ||
| 25 | +#define M 111 | ||
| 26 | |||
| 27 | static int __attribute__((noinline)) | ||
| 28 | foo (int *x) | ||
| 29 | @@ -38,7 +38,7 @@ | ||
| 30 | fprintf (stderr, "res = %d \n", res); | ||
| 31 | #endif | ||
| 32 | |||
| 33 | - if (res != 2468642) | ||
| 34 | + if (res != 24642) | ||
| 35 | abort (); | ||
| 36 | |||
| 37 | return 0; | ||
| 38 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99366.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99366.patch deleted file mode 100644 index 0998c812e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99366.patch +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | 2010-08-13 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | 2010-08-13 Jie Zhang <jie@codesourcery.com> | ||
| 7 | * config/arm/arm.md (cstoredf4): Only valid when | ||
| 8 | !TARGET_VFP_SINGLE. | ||
| 9 | |||
| 10 | 2010-08-12 Jie Zhang <jie@codesourcery.com> | ||
| 11 | |||
| 12 | Backport from mainline: | ||
| 13 | |||
| 14 | === modified file 'gcc/config/arm/arm.md' | ||
| 15 | --- old/gcc/config/arm/arm.md 2010-08-16 09:41:58 +0000 | ||
| 16 | +++ new/gcc/config/arm/arm.md 2010-08-20 16:41:37 +0000 | ||
| 17 | @@ -8344,7 +8344,7 @@ | ||
| 18 | (match_operator:SI 1 "arm_comparison_operator" | ||
| 19 | [(match_operand:DF 2 "s_register_operand" "") | ||
| 20 | (match_operand:DF 3 "arm_float_compare_operand" "")]))] | ||
| 21 | - "TARGET_32BIT && TARGET_HARD_FLOAT" | ||
| 22 | + "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" | ||
| 23 | "emit_insn (gen_cstore_cc (operands[0], operands[1], | ||
| 24 | operands[2], operands[3])); DONE;" | ||
| 25 | ) | ||
| 26 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99367.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99367.patch deleted file mode 100644 index 2d572b1bb..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99367.patch +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | 2010-08-18 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | gcc/testsuite/ | ||
| 6 | 2010-08-18 Jie Zhang <jie@codesourcery.com> | ||
| 7 | * gcc.dg/builtin-apply2.c (STACK_ARGUMENTS_SIZE): Define to | ||
| 8 | 20 if __ARM_PCS is defined otherwise 64. | ||
| 9 | (bar): Use STACK_ARGUMENTS_SIZE for the third argument | ||
| 10 | instead of hard coded 64. | ||
| 11 | |||
| 12 | 2010-08-13 Jie Zhang <jie@codesourcery.com> | ||
| 13 | |||
| 14 | Backport from mainline: | ||
| 15 | |||
| 16 | === modified file 'gcc/testsuite/gcc.dg/builtin-apply2.c' | ||
| 17 | --- old/gcc/testsuite/gcc.dg/builtin-apply2.c 2009-08-06 13:27:45 +0000 | ||
| 18 | +++ new/gcc/testsuite/gcc.dg/builtin-apply2.c 2010-08-23 13:59:02 +0000 | ||
| 19 | @@ -8,10 +8,19 @@ | ||
| 20 | /* Verify that __builtin_apply behaves correctly on targets | ||
| 21 | with pre-pushed arguments (e.g. SPARC). */ | ||
| 22 | |||
| 23 | - | ||
| 24 | + | ||
| 25 | |||
| 26 | #define INTEGER_ARG 5 | ||
| 27 | |||
| 28 | +#ifdef __ARM_PCS | ||
| 29 | +/* For Base AAPCS, NAME is passed in r0. D is passed in r2 and r3. | ||
| 30 | + E, F and G are passed on stack. So the size of the stack argument | ||
| 31 | + data is 20. */ | ||
| 32 | +#define STACK_ARGUMENTS_SIZE 20 | ||
| 33 | +#else | ||
| 34 | +#define STACK_ARGUMENTS_SIZE 64 | ||
| 35 | +#endif | ||
| 36 | + | ||
| 37 | extern void abort(void); | ||
| 38 | |||
| 39 | void foo(char *name, double d, double e, double f, int g) | ||
| 40 | @@ -22,7 +31,7 @@ | ||
| 41 | |||
| 42 | void bar(char *name, ...) | ||
| 43 | { | ||
| 44 | - __builtin_apply(foo, __builtin_apply_args(), 64); | ||
| 45 | + __builtin_apply(foo, __builtin_apply_args(), STACK_ARGUMENTS_SIZE); | ||
| 46 | } | ||
| 47 | |||
| 48 | int main(void) | ||
| 49 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch deleted file mode 100644 index 0705e4183..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99368.patch +++ /dev/null | |||
| @@ -1,342 +0,0 @@ | |||
| 1 | 2010-08-18 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #9222 | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * config/arm/neon.md (UNSPEC_VCLE, UNSPEC_VCLT): New constants for | ||
| 7 | unspecs. | ||
| 8 | (vcond<mode>, vcondu<mode>): New expanders. | ||
| 9 | (neon_vceq<mode>, neon_vcge<mode>, neon_vcgt<mode>): Support | ||
| 10 | comparisons with zero. | ||
| 11 | (neon_vcle<mode>, neon_vclt<mode>): New patterns. | ||
| 12 | * config/arm/constraints.md (Dz): New constraint. | ||
| 13 | |||
| 14 | 2010-08-18 Jie Zhang <jie@codesourcery.com> | ||
| 15 | |||
| 16 | Backport from mainline: | ||
| 17 | |||
| 18 | === modified file 'gcc/config/arm/constraints.md' | ||
| 19 | Index: gcc-4.5/gcc/config/arm/constraints.md | ||
| 20 | =================================================================== | ||
| 21 | --- gcc-4.5.orig/gcc/config/arm/constraints.md | ||
| 22 | +++ gcc-4.5/gcc/config/arm/constraints.md | ||
| 23 | @@ -29,7 +29,7 @@ | ||
| 24 | ;; in Thumb-1 state: I, J, K, L, M, N, O | ||
| 25 | |||
| 26 | ;; The following multi-letter normal constraints have been used: | ||
| 27 | -;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di | ||
| 28 | +;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz | ||
| 29 | ;; in Thumb-1 state: Pa, Pb | ||
| 30 | ;; in Thumb-2 state: Ps, Pt, Pv | ||
| 31 | |||
| 32 | @@ -173,6 +173,12 @@ | ||
| 33 | (and (match_code "const_double") | ||
| 34 | (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)"))) | ||
| 35 | |||
| 36 | +(define_constraint "Dz" | ||
| 37 | + "@internal | ||
| 38 | + In ARM/Thumb-2 state a vector of constant zeros." | ||
| 39 | + (and (match_code "const_vector") | ||
| 40 | + (match_test "TARGET_NEON && op == CONST0_RTX (mode)"))) | ||
| 41 | + | ||
| 42 | (define_constraint "Da" | ||
| 43 | "@internal | ||
| 44 | In ARM/Thumb-2 state a const_int, const_double or const_vector that can | ||
| 45 | Index: gcc-4.5/gcc/config/arm/neon.md | ||
| 46 | =================================================================== | ||
| 47 | --- gcc-4.5.orig/gcc/config/arm/neon.md | ||
| 48 | +++ gcc-4.5/gcc/config/arm/neon.md | ||
| 49 | @@ -141,7 +141,9 @@ | ||
| 50 | (UNSPEC_VUZP2 202) | ||
| 51 | (UNSPEC_VZIP1 203) | ||
| 52 | (UNSPEC_VZIP2 204) | ||
| 53 | - (UNSPEC_MISALIGNED_ACCESS 205)]) | ||
| 54 | + (UNSPEC_MISALIGNED_ACCESS 205) | ||
| 55 | + (UNSPEC_VCLE 206) | ||
| 56 | + (UNSPEC_VCLT 207)]) | ||
| 57 | |||
| 58 | ;; Double-width vector modes. | ||
| 59 | (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) | ||
| 60 | @@ -1804,6 +1806,169 @@ | ||
| 61 | [(set_attr "neon_type" "neon_int_5")] | ||
| 62 | ) | ||
| 63 | |||
| 64 | +;; Conditional instructions. These are comparisons with conditional moves for | ||
| 65 | +;; vectors. They perform the assignment: | ||
| 66 | +;; | ||
| 67 | +;; Vop0 = (Vop4 <op3> Vop5) ? Vop1 : Vop2; | ||
| 68 | +;; | ||
| 69 | +;; where op3 is <, <=, ==, !=, >= or >. Operations are performed | ||
| 70 | +;; element-wise. | ||
| 71 | + | ||
| 72 | +(define_expand "vcond<mode>" | ||
| 73 | + [(set (match_operand:VDQW 0 "s_register_operand" "") | ||
| 74 | + (if_then_else:VDQW | ||
| 75 | + (match_operator 3 "arm_comparison_operator" | ||
| 76 | + [(match_operand:VDQW 4 "s_register_operand" "") | ||
| 77 | + (match_operand:VDQW 5 "nonmemory_operand" "")]) | ||
| 78 | + (match_operand:VDQW 1 "s_register_operand" "") | ||
| 79 | + (match_operand:VDQW 2 "s_register_operand" "")))] | ||
| 80 | + "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" | ||
| 81 | +{ | ||
| 82 | + rtx mask; | ||
| 83 | + int inverse = 0, immediate_zero = 0; | ||
| 84 | + /* See the description of "magic" bits in the 'T' case of | ||
| 85 | + arm_print_operand. */ | ||
| 86 | + HOST_WIDE_INT magic_word = (<MODE>mode == V2SFmode || <MODE>mode == V4SFmode) | ||
| 87 | + ? 3 : 1; | ||
| 88 | + rtx magic_rtx = GEN_INT (magic_word); | ||
| 89 | + | ||
| 90 | + mask = gen_reg_rtx (<V_cmp_result>mode); | ||
| 91 | + | ||
| 92 | + if (operands[5] == CONST0_RTX (<MODE>mode)) | ||
| 93 | + immediate_zero = 1; | ||
| 94 | + else if (!REG_P (operands[5])) | ||
| 95 | + operands[5] = force_reg (<MODE>mode, operands[5]); | ||
| 96 | + | ||
| 97 | + switch (GET_CODE (operands[3])) | ||
| 98 | + { | ||
| 99 | + case GE: | ||
| 100 | + emit_insn (gen_neon_vcge<mode> (mask, operands[4], operands[5], | ||
| 101 | + magic_rtx)); | ||
| 102 | + break; | ||
| 103 | + | ||
| 104 | + case GT: | ||
| 105 | + emit_insn (gen_neon_vcgt<mode> (mask, operands[4], operands[5], | ||
| 106 | + magic_rtx)); | ||
| 107 | + break; | ||
| 108 | + | ||
| 109 | + case EQ: | ||
| 110 | + emit_insn (gen_neon_vceq<mode> (mask, operands[4], operands[5], | ||
| 111 | + magic_rtx)); | ||
| 112 | + break; | ||
| 113 | + | ||
| 114 | + case LE: | ||
| 115 | + if (immediate_zero) | ||
| 116 | + emit_insn (gen_neon_vcle<mode> (mask, operands[4], operands[5], | ||
| 117 | + magic_rtx)); | ||
| 118 | + else | ||
| 119 | + emit_insn (gen_neon_vcge<mode> (mask, operands[5], operands[4], | ||
| 120 | + magic_rtx)); | ||
| 121 | + break; | ||
| 122 | + | ||
| 123 | + case LT: | ||
| 124 | + if (immediate_zero) | ||
| 125 | + emit_insn (gen_neon_vclt<mode> (mask, operands[4], operands[5], | ||
| 126 | + magic_rtx)); | ||
| 127 | + else | ||
| 128 | + emit_insn (gen_neon_vcgt<mode> (mask, operands[5], operands[4], | ||
| 129 | + magic_rtx)); | ||
| 130 | + break; | ||
| 131 | + | ||
| 132 | + case NE: | ||
| 133 | + emit_insn (gen_neon_vceq<mode> (mask, operands[4], operands[5], | ||
| 134 | + magic_rtx)); | ||
| 135 | + inverse = 1; | ||
| 136 | + break; | ||
| 137 | + | ||
| 138 | + default: | ||
| 139 | + gcc_unreachable (); | ||
| 140 | + } | ||
| 141 | + | ||
| 142 | + if (inverse) | ||
| 143 | + emit_insn (gen_neon_vbsl<mode> (operands[0], mask, operands[2], | ||
| 144 | + operands[1])); | ||
| 145 | + else | ||
| 146 | + emit_insn (gen_neon_vbsl<mode> (operands[0], mask, operands[1], | ||
| 147 | + operands[2])); | ||
| 148 | + | ||
| 149 | + DONE; | ||
| 150 | +}) | ||
| 151 | + | ||
| 152 | +(define_expand "vcondu<mode>" | ||
| 153 | + [(set (match_operand:VDQIW 0 "s_register_operand" "") | ||
| 154 | + (if_then_else:VDQIW | ||
| 155 | + (match_operator 3 "arm_comparison_operator" | ||
| 156 | + [(match_operand:VDQIW 4 "s_register_operand" "") | ||
| 157 | + (match_operand:VDQIW 5 "s_register_operand" "")]) | ||
| 158 | + (match_operand:VDQIW 1 "s_register_operand" "") | ||
| 159 | + (match_operand:VDQIW 2 "s_register_operand" "")))] | ||
| 160 | + "TARGET_NEON" | ||
| 161 | +{ | ||
| 162 | + rtx mask; | ||
| 163 | + int inverse = 0, immediate_zero = 0; | ||
| 164 | + | ||
| 165 | + mask = gen_reg_rtx (<V_cmp_result>mode); | ||
| 166 | + | ||
| 167 | + if (operands[5] == CONST0_RTX (<MODE>mode)) | ||
| 168 | + immediate_zero = 1; | ||
| 169 | + else if (!REG_P (operands[5])) | ||
| 170 | + operands[5] = force_reg (<MODE>mode, operands[5]); | ||
| 171 | + | ||
| 172 | + switch (GET_CODE (operands[3])) | ||
| 173 | + { | ||
| 174 | + case GEU: | ||
| 175 | + emit_insn (gen_neon_vcge<mode> (mask, operands[4], operands[5], | ||
| 176 | + const0_rtx)); | ||
| 177 | + break; | ||
| 178 | + | ||
| 179 | + case GTU: | ||
| 180 | + emit_insn (gen_neon_vcgt<mode> (mask, operands[4], operands[5], | ||
| 181 | + const0_rtx)); | ||
| 182 | + break; | ||
| 183 | + | ||
| 184 | + case EQ: | ||
| 185 | + emit_insn (gen_neon_vceq<mode> (mask, operands[4], operands[5], | ||
| 186 | + const0_rtx)); | ||
| 187 | + break; | ||
| 188 | + | ||
| 189 | + case LEU: | ||
| 190 | + if (immediate_zero) | ||
| 191 | + emit_insn (gen_neon_vcle<mode> (mask, operands[4], operands[5], | ||
| 192 | + const0_rtx)); | ||
| 193 | + else | ||
| 194 | + emit_insn (gen_neon_vcge<mode> (mask, operands[5], operands[4], | ||
| 195 | + const0_rtx)); | ||
| 196 | + break; | ||
| 197 | + | ||
| 198 | + case LTU: | ||
| 199 | + if (immediate_zero) | ||
| 200 | + emit_insn (gen_neon_vclt<mode> (mask, operands[4], operands[5], | ||
| 201 | + const0_rtx)); | ||
| 202 | + else | ||
| 203 | + emit_insn (gen_neon_vcgt<mode> (mask, operands[5], operands[4], | ||
| 204 | + const0_rtx)); | ||
| 205 | + break; | ||
| 206 | + | ||
| 207 | + case NE: | ||
| 208 | + emit_insn (gen_neon_vceq<mode> (mask, operands[4], operands[5], | ||
| 209 | + const0_rtx)); | ||
| 210 | + inverse = 1; | ||
| 211 | + break; | ||
| 212 | + | ||
| 213 | + default: | ||
| 214 | + gcc_unreachable (); | ||
| 215 | + } | ||
| 216 | + | ||
| 217 | + if (inverse) | ||
| 218 | + emit_insn (gen_neon_vbsl<mode> (operands[0], mask, operands[2], | ||
| 219 | + operands[1])); | ||
| 220 | + else | ||
| 221 | + emit_insn (gen_neon_vbsl<mode> (operands[0], mask, operands[1], | ||
| 222 | + operands[2])); | ||
| 223 | + | ||
| 224 | + DONE; | ||
| 225 | +}) | ||
| 226 | + | ||
| 227 | ;; Patterns for builtins. | ||
| 228 | |||
| 229 | ; good for plain vadd, vaddq. | ||
| 230 | @@ -2215,13 +2380,16 @@ | ||
| 231 | ) | ||
| 232 | |||
| 233 | (define_insn "neon_vceq<mode>" | ||
| 234 | - [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w") | ||
| 235 | - (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w") | ||
| 236 | - (match_operand:VDQW 2 "s_register_operand" "w") | ||
| 237 | - (match_operand:SI 3 "immediate_operand" "i")] | ||
| 238 | - UNSPEC_VCEQ))] | ||
| 239 | + [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w") | ||
| 240 | + (unspec:<V_cmp_result> | ||
| 241 | + [(match_operand:VDQW 1 "s_register_operand" "w,w") | ||
| 242 | + (match_operand:VDQW 2 "nonmemory_operand" "w,Dz") | ||
| 243 | + (match_operand:SI 3 "immediate_operand" "i,i")] | ||
| 244 | + UNSPEC_VCEQ))] | ||
| 245 | "TARGET_NEON" | ||
| 246 | - "vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" | ||
| 247 | + "@ | ||
| 248 | + vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2 | ||
| 249 | + vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, #0" | ||
| 250 | [(set (attr "neon_type") | ||
| 251 | (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0)) | ||
| 252 | (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0)) | ||
| 253 | @@ -2231,13 +2399,16 @@ | ||
| 254 | ) | ||
| 255 | |||
| 256 | (define_insn "neon_vcge<mode>" | ||
| 257 | - [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w") | ||
| 258 | - (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w") | ||
| 259 | - (match_operand:VDQW 2 "s_register_operand" "w") | ||
| 260 | - (match_operand:SI 3 "immediate_operand" "i")] | ||
| 261 | - UNSPEC_VCGE))] | ||
| 262 | + [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w") | ||
| 263 | + (unspec:<V_cmp_result> | ||
| 264 | + [(match_operand:VDQW 1 "s_register_operand" "w,w") | ||
| 265 | + (match_operand:VDQW 2 "nonmemory_operand" "w,Dz") | ||
| 266 | + (match_operand:SI 3 "immediate_operand" "i,i")] | ||
| 267 | + UNSPEC_VCGE))] | ||
| 268 | "TARGET_NEON" | ||
| 269 | - "vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" | ||
| 270 | + "@ | ||
| 271 | + vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2 | ||
| 272 | + vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0" | ||
| 273 | [(set (attr "neon_type") | ||
| 274 | (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0)) | ||
| 275 | (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0)) | ||
| 276 | @@ -2247,13 +2418,16 @@ | ||
| 277 | ) | ||
| 278 | |||
| 279 | (define_insn "neon_vcgt<mode>" | ||
| 280 | - [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w") | ||
| 281 | - (unspec:<V_cmp_result> [(match_operand:VDQW 1 "s_register_operand" "w") | ||
| 282 | - (match_operand:VDQW 2 "s_register_operand" "w") | ||
| 283 | - (match_operand:SI 3 "immediate_operand" "i")] | ||
| 284 | - UNSPEC_VCGT))] | ||
| 285 | + [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w") | ||
| 286 | + (unspec:<V_cmp_result> | ||
| 287 | + [(match_operand:VDQW 1 "s_register_operand" "w,w") | ||
| 288 | + (match_operand:VDQW 2 "nonmemory_operand" "w,Dz") | ||
| 289 | + (match_operand:SI 3 "immediate_operand" "i,i")] | ||
| 290 | + UNSPEC_VCGT))] | ||
| 291 | "TARGET_NEON" | ||
| 292 | - "vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" | ||
| 293 | + "@ | ||
| 294 | + vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2 | ||
| 295 | + vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0" | ||
| 296 | [(set (attr "neon_type") | ||
| 297 | (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0)) | ||
| 298 | (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0)) | ||
| 299 | @@ -2262,6 +2436,43 @@ | ||
| 300 | (const_string "neon_int_5")))] | ||
| 301 | ) | ||
| 302 | |||
| 303 | +;; VCLE and VCLT only support comparisons with immediate zero (register | ||
| 304 | +;; variants are VCGE and VCGT with operands reversed). | ||
| 305 | + | ||
| 306 | +(define_insn "neon_vcle<mode>" | ||
| 307 | + [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w") | ||
| 308 | + (unspec:<V_cmp_result> | ||
| 309 | + [(match_operand:VDQW 1 "s_register_operand" "w") | ||
| 310 | + (match_operand:VDQW 2 "nonmemory_operand" "Dz") | ||
| 311 | + (match_operand:SI 3 "immediate_operand" "i")] | ||
| 312 | + UNSPEC_VCLE))] | ||
| 313 | + "TARGET_NEON" | ||
| 314 | + "vcle.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0" | ||
| 315 | + [(set (attr "neon_type") | ||
| 316 | + (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0)) | ||
| 317 | + (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0)) | ||
| 318 | + (const_string "neon_fp_vadd_ddd_vabs_dd") | ||
| 319 | + (const_string "neon_fp_vadd_qqq_vabs_qq")) | ||
| 320 | + (const_string "neon_int_5")))] | ||
| 321 | +) | ||
| 322 | + | ||
| 323 | +(define_insn "neon_vclt<mode>" | ||
| 324 | + [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w") | ||
| 325 | + (unspec:<V_cmp_result> | ||
| 326 | + [(match_operand:VDQW 1 "s_register_operand" "w") | ||
| 327 | + (match_operand:VDQW 2 "nonmemory_operand" "Dz") | ||
| 328 | + (match_operand:SI 3 "immediate_operand" "i")] | ||
| 329 | + UNSPEC_VCLT))] | ||
| 330 | + "TARGET_NEON" | ||
| 331 | + "vclt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0" | ||
| 332 | + [(set (attr "neon_type") | ||
| 333 | + (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0)) | ||
| 334 | + (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0)) | ||
| 335 | + (const_string "neon_fp_vadd_ddd_vabs_dd") | ||
| 336 | + (const_string "neon_fp_vadd_qqq_vabs_qq")) | ||
| 337 | + (const_string "neon_int_5")))] | ||
| 338 | +) | ||
| 339 | + | ||
| 340 | (define_insn "neon_vcage<mode>" | ||
| 341 | [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w") | ||
| 342 | (unspec:<V_cmp_result> [(match_operand:VCVTF 1 "s_register_operand" "w") | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99369.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99369.patch deleted file mode 100644 index 9bbc02062..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99369.patch +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | 2010-08-20 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Merged from Sourcery G++ 4.4: | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | 2009-05-29 Julian Brown <julian@codesourcery.com> | ||
| 7 | Merged from Sourcery G++ 4.3: | ||
| 8 | * config/arm/arm.md (movsi): Don't split symbol refs here. | ||
| 9 | (define_split): New. | ||
| 10 | |||
| 11 | 2010-08-18 Julian Brown <julian@codesourcery.com> | ||
| 12 | |||
| 13 | Issue #9222 | ||
| 14 | |||
| 15 | === modified file 'gcc/config/arm/arm.md' | ||
| 16 | --- old/gcc/config/arm/arm.md 2010-08-20 16:41:37 +0000 | ||
| 17 | +++ new/gcc/config/arm/arm.md 2010-08-23 14:39:12 +0000 | ||
| 18 | @@ -5150,14 +5150,6 @@ | ||
| 19 | optimize && can_create_pseudo_p ()); | ||
| 20 | DONE; | ||
| 21 | } | ||
| 22 | - | ||
| 23 | - if (TARGET_USE_MOVT && !target_word_relocations | ||
| 24 | - && GET_CODE (operands[1]) == SYMBOL_REF | ||
| 25 | - && !flag_pic && !arm_tls_referenced_p (operands[1])) | ||
| 26 | - { | ||
| 27 | - arm_emit_movpair (operands[0], operands[1]); | ||
| 28 | - DONE; | ||
| 29 | - } | ||
| 30 | } | ||
| 31 | else /* TARGET_THUMB1... */ | ||
| 32 | { | ||
| 33 | @@ -5265,6 +5257,19 @@ | ||
| 34 | " | ||
| 35 | ) | ||
| 36 | |||
| 37 | +(define_split | ||
| 38 | + [(set (match_operand:SI 0 "arm_general_register_operand" "") | ||
| 39 | + (match_operand:SI 1 "general_operand" ""))] | ||
| 40 | + "TARGET_32BIT | ||
| 41 | + && TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF | ||
| 42 | + && !flag_pic && !target_word_relocations | ||
| 43 | + && !arm_tls_referenced_p (operands[1])" | ||
| 44 | + [(clobber (const_int 0))] | ||
| 45 | +{ | ||
| 46 | + arm_emit_movpair (operands[0], operands[1]); | ||
| 47 | + DONE; | ||
| 48 | +}) | ||
| 49 | + | ||
| 50 | (define_insn "*thumb1_movsi_insn" | ||
| 51 | [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*lhk") | ||
| 52 | (match_operand:SI 1 "general_operand" "l, I,J,K,>,l,mi,l,*lhk"))] | ||
| 53 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99371.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99371.patch deleted file mode 100644 index be102160c..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99371.patch +++ /dev/null | |||
| @@ -1,663 +0,0 @@ | |||
| 1 | 2010-08-24 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from FSF: | ||
| 4 | |||
| 5 | 2010-08-07 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | ||
| 6 | |||
| 7 | * config/arm/cortex-a9.md: Rewrite VFP Pipeline description. | ||
| 8 | * config/arm/arm.c (arm_xscale_tune): Initialize sched_adjust_cost. | ||
| 9 | (arm_fastmul_tune,arm_slowmul_tune, arm_9e_tune): Likewise. | ||
| 10 | (arm_adjust_cost): Split into xscale_sched_adjust_cost and a | ||
| 11 | generic part. | ||
| 12 | (cortex_a9_sched_adjust_cost): New function. | ||
| 13 | (xscale_sched_adjust_cost): New function. | ||
| 14 | * config/arm/arm-protos.h (struct tune_params): New field | ||
| 15 | sched_adjust_cost. | ||
| 16 | * config/arm/arm-cores.def: Adjust costs for cortex-a9. | ||
| 17 | |||
| 18 | 2010-04-17 Richard Earnshaw <rearnsha@arm.com> | ||
| 19 | |||
| 20 | * arm-protos.h (tune_params): New structure. | ||
| 21 | * arm.c (current_tune): New variable. | ||
| 22 | (arm_constant_limit): Delete. | ||
| 23 | (struct processors): Add pointer to the tune parameters. | ||
| 24 | (arm_slowmul_tune): New tuning option. | ||
| 25 | (arm_fastmul_tune, arm_xscale_tune, arm_9e_tune): Likewise. | ||
| 26 | (all_cores): Adjust to pick up the tuning model. | ||
| 27 | (arm_constant_limit): New function. | ||
| 28 | (arm_override_options): Select the appropriate tuning model. Delete | ||
| 29 | initialization of arm_const_limit. | ||
| 30 | (arm_split_constant): Use the new constant-limit model. | ||
| 31 | (arm_rtx_costs): Pick up the current tuning model. | ||
| 32 | * arm.md (is_strongarm, is_xscale): Delete. | ||
| 33 | * arm-generic.md (load_ldsched_x, load_ldsched): Test explicitly | ||
| 34 | for Xscale variant architectures. | ||
| 35 | (mult_ldsched_strongarm, mult_ldsched): Similarly for StrongARM. | ||
| 36 | |||
| 37 | 2010-08-23 Andrew Stubbs <ams@codesourcery.com> | ||
| 38 | |||
| 39 | Backport from FSF: | ||
| 40 | |||
| 41 | === modified file 'gcc/config/arm/arm-cores.def' | ||
| 42 | --- old/gcc/config/arm/arm-cores.def 2010-07-29 15:53:39 +0000 | ||
| 43 | +++ new/gcc/config/arm/arm-cores.def 2010-08-24 13:15:54 +0000 | ||
| 44 | @@ -120,7 +120,7 @@ | ||
| 45 | ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, 9e) | ||
| 46 | ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, 9e) | ||
| 47 | ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e) | ||
| 48 | -ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, 9e) | ||
| 49 | +ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) | ||
| 50 | ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e) | ||
| 51 | ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e) | ||
| 52 | ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, 9e) | ||
| 53 | |||
| 54 | === modified file 'gcc/config/arm/arm-generic.md' | ||
| 55 | --- old/gcc/config/arm/arm-generic.md 2007-08-02 09:49:31 +0000 | ||
| 56 | +++ new/gcc/config/arm/arm-generic.md 2010-08-24 13:15:54 +0000 | ||
| 57 | @@ -104,14 +104,14 @@ | ||
| 58 | (and (eq_attr "generic_sched" "yes") | ||
| 59 | (and (eq_attr "ldsched" "yes") | ||
| 60 | (and (eq_attr "type" "load_byte,load1") | ||
| 61 | - (eq_attr "is_xscale" "yes")))) | ||
| 62 | + (eq_attr "tune" "xscale,iwmmxt,iwmmxt2")))) | ||
| 63 | "core") | ||
| 64 | |||
| 65 | (define_insn_reservation "load_ldsched" 2 | ||
| 66 | (and (eq_attr "generic_sched" "yes") | ||
| 67 | (and (eq_attr "ldsched" "yes") | ||
| 68 | (and (eq_attr "type" "load_byte,load1") | ||
| 69 | - (eq_attr "is_xscale" "no")))) | ||
| 70 | + (eq_attr "tune" "!xscale,iwmmxt,iwmmxt2")))) | ||
| 71 | "core") | ||
| 72 | |||
| 73 | (define_insn_reservation "load_or_store" 2 | ||
| 74 | @@ -128,14 +128,16 @@ | ||
| 75 | (define_insn_reservation "mult_ldsched_strongarm" 3 | ||
| 76 | (and (eq_attr "generic_sched" "yes") | ||
| 77 | (and (eq_attr "ldsched" "yes") | ||
| 78 | - (and (eq_attr "is_strongarm" "yes") | ||
| 79 | + (and (eq_attr "tune" | ||
| 80 | + "strongarm,strongarm110,strongarm1100,strongarm1110") | ||
| 81 | (eq_attr "type" "mult")))) | ||
| 82 | "core*2") | ||
| 83 | |||
| 84 | (define_insn_reservation "mult_ldsched" 4 | ||
| 85 | (and (eq_attr "generic_sched" "yes") | ||
| 86 | (and (eq_attr "ldsched" "yes") | ||
| 87 | - (and (eq_attr "is_strongarm" "no") | ||
| 88 | + (and (eq_attr "tune" | ||
| 89 | + "!strongarm,strongarm110,strongarm1100,strongarm1110") | ||
| 90 | (eq_attr "type" "mult")))) | ||
| 91 | "core*4") | ||
| 92 | |||
| 93 | |||
| 94 | === modified file 'gcc/config/arm/arm-protos.h' | ||
| 95 | --- old/gcc/config/arm/arm-protos.h 2010-08-10 13:31:21 +0000 | ||
| 96 | +++ new/gcc/config/arm/arm-protos.h 2010-08-24 13:15:54 +0000 | ||
| 97 | @@ -214,4 +214,17 @@ | ||
| 98 | |||
| 99 | extern void arm_order_regs_for_local_alloc (void); | ||
| 100 | |||
| 101 | +#ifdef RTX_CODE | ||
| 102 | +/* This needs to be here because we need RTX_CODE and similar. */ | ||
| 103 | + | ||
| 104 | +struct tune_params | ||
| 105 | +{ | ||
| 106 | + bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool); | ||
| 107 | + bool (*sched_adjust_cost) (rtx, rtx, rtx, int *); | ||
| 108 | + int constant_limit; | ||
| 109 | +}; | ||
| 110 | + | ||
| 111 | +extern const struct tune_params *current_tune; | ||
| 112 | +#endif /* RTX_CODE */ | ||
| 113 | + | ||
| 114 | #endif /* ! GCC_ARM_PROTOS_H */ | ||
| 115 | |||
| 116 | === modified file 'gcc/config/arm/arm.c' | ||
| 117 | --- old/gcc/config/arm/arm.c 2010-08-20 16:21:01 +0000 | ||
| 118 | +++ new/gcc/config/arm/arm.c 2010-08-24 13:15:54 +0000 | ||
| 119 | @@ -228,6 +228,8 @@ | ||
| 120 | static void arm_trampoline_init (rtx, tree, rtx); | ||
| 121 | static rtx arm_trampoline_adjust_address (rtx); | ||
| 122 | static rtx arm_pic_static_addr (rtx orig, rtx reg); | ||
| 123 | +static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *); | ||
| 124 | +static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *); | ||
| 125 | static bool arm_vector_alignment_reachable (const_tree type, bool is_packed); | ||
| 126 | static bool arm_builtin_support_vector_misalignment (enum machine_mode mode, | ||
| 127 | const_tree type, | ||
| 128 | @@ -545,6 +547,9 @@ | ||
| 129 | /* The processor for which instructions should be scheduled. */ | ||
| 130 | enum processor_type arm_tune = arm_none; | ||
| 131 | |||
| 132 | +/* The current tuning set. */ | ||
| 133 | +const struct tune_params *current_tune; | ||
| 134 | + | ||
| 135 | /* The default processor used if not overridden by commandline. */ | ||
| 136 | static enum processor_type arm_default_cpu = arm_none; | ||
| 137 | |||
| 138 | @@ -720,9 +725,6 @@ | ||
| 139 | the next function. */ | ||
| 140 | static int after_arm_reorg = 0; | ||
| 141 | |||
| 142 | -/* The maximum number of insns to be used when loading a constant. */ | ||
| 143 | -static int arm_constant_limit = 3; | ||
| 144 | - | ||
| 145 | enum arm_pcs arm_pcs_default; | ||
| 146 | |||
| 147 | /* For an explanation of these variables, see final_prescan_insn below. */ | ||
| 148 | @@ -761,8 +763,44 @@ | ||
| 149 | enum processor_type core; | ||
| 150 | const char *arch; | ||
| 151 | const unsigned long flags; | ||
| 152 | - bool (* rtx_costs) (rtx, enum rtx_code, enum rtx_code, int *, bool); | ||
| 153 | -}; | ||
| 154 | + const struct tune_params *const tune; | ||
| 155 | +}; | ||
| 156 | + | ||
| 157 | +const struct tune_params arm_slowmul_tune = | ||
| 158 | +{ | ||
| 159 | + arm_slowmul_rtx_costs, | ||
| 160 | + NULL, | ||
| 161 | + 3 | ||
| 162 | +}; | ||
| 163 | + | ||
| 164 | +const struct tune_params arm_fastmul_tune = | ||
| 165 | +{ | ||
| 166 | + arm_fastmul_rtx_costs, | ||
| 167 | + NULL, | ||
| 168 | + 1 | ||
| 169 | +}; | ||
| 170 | + | ||
| 171 | +const struct tune_params arm_xscale_tune = | ||
| 172 | +{ | ||
| 173 | + arm_xscale_rtx_costs, | ||
| 174 | + xscale_sched_adjust_cost, | ||
| 175 | + 2 | ||
| 176 | +}; | ||
| 177 | + | ||
| 178 | +const struct tune_params arm_9e_tune = | ||
| 179 | +{ | ||
| 180 | + arm_9e_rtx_costs, | ||
| 181 | + NULL, | ||
| 182 | + 1 | ||
| 183 | +}; | ||
| 184 | + | ||
| 185 | +const struct tune_params arm_cortex_a9_tune = | ||
| 186 | +{ | ||
| 187 | + arm_9e_rtx_costs, | ||
| 188 | + cortex_a9_sched_adjust_cost, | ||
| 189 | + 1 | ||
| 190 | +}; | ||
| 191 | + | ||
| 192 | |||
| 193 | /* Not all of these give usefully different compilation alternatives, | ||
| 194 | but there is no simple way of generalizing them. */ | ||
| 195 | @@ -770,7 +808,7 @@ | ||
| 196 | { | ||
| 197 | /* ARM Cores */ | ||
| 198 | #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ | ||
| 199 | - {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs}, | ||
| 200 | + {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune}, | ||
| 201 | #include "arm-cores.def" | ||
| 202 | #undef ARM_CORE | ||
| 203 | {NULL, arm_none, NULL, 0, NULL} | ||
| 204 | @@ -779,7 +817,7 @@ | ||
| 205 | static const struct processors all_architectures[] = | ||
| 206 | { | ||
| 207 | /* ARM Architectures */ | ||
| 208 | - /* We don't specify rtx_costs here as it will be figured out | ||
| 209 | + /* We don't specify tuning costs here as it will be figured out | ||
| 210 | from the core. */ | ||
| 211 | |||
| 212 | {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, | ||
| 213 | @@ -928,6 +966,13 @@ | ||
| 214 | TLS_LE32 | ||
| 215 | }; | ||
| 216 | |||
| 217 | +/* The maximum number of insns to be used when loading a constant. */ | ||
| 218 | +inline static int | ||
| 219 | +arm_constant_limit (bool size_p) | ||
| 220 | +{ | ||
| 221 | + return size_p ? 1 : current_tune->constant_limit; | ||
| 222 | +} | ||
| 223 | + | ||
| 224 | /* Emit an insn that's a simple single-set. Both the operands must be known | ||
| 225 | to be valid. */ | ||
| 226 | inline static rtx | ||
| 227 | @@ -1478,6 +1523,7 @@ | ||
| 228 | } | ||
| 229 | |||
| 230 | tune_flags = all_cores[(int)arm_tune].flags; | ||
| 231 | + current_tune = all_cores[(int)arm_tune].tune; | ||
| 232 | |||
| 233 | if (target_fp16_format_name) | ||
| 234 | { | ||
| 235 | @@ -1875,26 +1921,12 @@ | ||
| 236 | |||
| 237 | if (optimize_size) | ||
| 238 | { | ||
| 239 | - arm_constant_limit = 1; | ||
| 240 | - | ||
| 241 | /* If optimizing for size, bump the number of instructions that we | ||
| 242 | are prepared to conditionally execute (even on a StrongARM). */ | ||
| 243 | max_insns_skipped = 6; | ||
| 244 | } | ||
| 245 | else | ||
| 246 | { | ||
| 247 | - /* For processors with load scheduling, it never costs more than | ||
| 248 | - 2 cycles to load a constant, and the load scheduler may well | ||
| 249 | - reduce that to 1. */ | ||
| 250 | - if (arm_ld_sched) | ||
| 251 | - arm_constant_limit = 1; | ||
| 252 | - | ||
| 253 | - /* On XScale the longer latency of a load makes it more difficult | ||
| 254 | - to achieve a good schedule, so it's faster to synthesize | ||
| 255 | - constants that can be done in two insns. */ | ||
| 256 | - if (arm_tune_xscale) | ||
| 257 | - arm_constant_limit = 2; | ||
| 258 | - | ||
| 259 | /* StrongARM has early execution of branches, so a sequence | ||
| 260 | that is worth skipping is shorter. */ | ||
| 261 | if (arm_tune_strongarm) | ||
| 262 | @@ -2423,7 +2455,8 @@ | ||
| 263 | && !cond | ||
| 264 | && (arm_gen_constant (code, mode, NULL_RTX, val, target, source, | ||
| 265 | 1, 0) | ||
| 266 | - > arm_constant_limit + (code != SET))) | ||
| 267 | + > (arm_constant_limit (optimize_function_for_size_p (cfun)) | ||
| 268 | + + (code != SET)))) | ||
| 269 | { | ||
| 270 | if (code == SET) | ||
| 271 | { | ||
| 272 | @@ -7771,9 +7804,9 @@ | ||
| 273 | (enum rtx_code) outer_code, total); | ||
| 274 | } | ||
| 275 | else | ||
| 276 | - return all_cores[(int)arm_tune].rtx_costs (x, (enum rtx_code) code, | ||
| 277 | - (enum rtx_code) outer_code, | ||
| 278 | - total, speed); | ||
| 279 | + return current_tune->rtx_costs (x, (enum rtx_code) code, | ||
| 280 | + (enum rtx_code) outer_code, | ||
| 281 | + total, speed); | ||
| 282 | } | ||
| 283 | |||
| 284 | /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not | ||
| 285 | @@ -7918,7 +7951,8 @@ | ||
| 286 | so it can be ignored. */ | ||
| 287 | |||
| 288 | static bool | ||
| 289 | -arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, int *total, bool speed) | ||
| 290 | +arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, | ||
| 291 | + int *total, bool speed) | ||
| 292 | { | ||
| 293 | enum machine_mode mode = GET_MODE (x); | ||
| 294 | |||
| 295 | @@ -8119,15 +8153,15 @@ | ||
| 296 | return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x); | ||
| 297 | } | ||
| 298 | |||
| 299 | -static int | ||
| 300 | -arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) | ||
| 301 | +/* Adjust cost hook for XScale. */ | ||
| 302 | +static bool | ||
| 303 | +xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) | ||
| 304 | { | ||
| 305 | rtx i_pat, d_pat; | ||
| 306 | |||
| 307 | /* Some true dependencies can have a higher cost depending | ||
| 308 | on precisely how certain input operands are used. */ | ||
| 309 | - if (arm_tune_xscale | ||
| 310 | - && REG_NOTE_KIND (link) == 0 | ||
| 311 | + if (REG_NOTE_KIND (link) == 0 | ||
| 312 | && recog_memoized (insn) >= 0 | ||
| 313 | && recog_memoized (dep) >= 0) | ||
| 314 | { | ||
| 315 | @@ -8161,10 +8195,106 @@ | ||
| 316 | |||
| 317 | if (reg_overlap_mentioned_p (recog_data.operand[opno], | ||
| 318 | shifted_operand)) | ||
| 319 | - return 2; | ||
| 320 | + { | ||
| 321 | + *cost = 2; | ||
| 322 | + return false; | ||
| 323 | + } | ||
| 324 | } | ||
| 325 | } | ||
| 326 | } | ||
| 327 | + return true; | ||
| 328 | +} | ||
| 329 | + | ||
| 330 | +/* Adjust cost hook for Cortex A9. */ | ||
| 331 | +static bool | ||
| 332 | +cortex_a9_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) | ||
| 333 | +{ | ||
| 334 | + switch (REG_NOTE_KIND (link)) | ||
| 335 | + { | ||
| 336 | + case REG_DEP_ANTI: | ||
| 337 | + *cost = 0; | ||
| 338 | + return false; | ||
| 339 | + | ||
| 340 | + case REG_DEP_TRUE: | ||
| 341 | + case REG_DEP_OUTPUT: | ||
| 342 | + if (recog_memoized (insn) >= 0 | ||
| 343 | + && recog_memoized (dep) >= 0) | ||
| 344 | + { | ||
| 345 | + if (GET_CODE (PATTERN (insn)) == SET) | ||
| 346 | + { | ||
| 347 | + if (GET_MODE_CLASS | ||
| 348 | + (GET_MODE (SET_DEST (PATTERN (insn)))) == MODE_FLOAT | ||
| 349 | + || GET_MODE_CLASS | ||
| 350 | + (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT) | ||
| 351 | + { | ||
| 352 | + enum attr_type attr_type_insn = get_attr_type (insn); | ||
| 353 | + enum attr_type attr_type_dep = get_attr_type (dep); | ||
| 354 | + | ||
| 355 | + /* By default all dependencies of the form | ||
| 356 | + s0 = s0 <op> s1 | ||
| 357 | + s0 = s0 <op> s2 | ||
| 358 | + have an extra latency of 1 cycle because | ||
| 359 | + of the input and output dependency in this | ||
| 360 | + case. However this gets modeled as an true | ||
| 361 | + dependency and hence all these checks. */ | ||
| 362 | + if (REG_P (SET_DEST (PATTERN (insn))) | ||
| 363 | + && REG_P (SET_DEST (PATTERN (dep))) | ||
| 364 | + && reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)), | ||
| 365 | + SET_DEST (PATTERN (dep)))) | ||
| 366 | + { | ||
| 367 | + /* FMACS is a special case where the dependant | ||
| 368 | + instruction can be issued 3 cycles before | ||
| 369 | + the normal latency in case of an output | ||
| 370 | + dependency. */ | ||
| 371 | + if ((attr_type_insn == TYPE_FMACS | ||
| 372 | + || attr_type_insn == TYPE_FMACD) | ||
| 373 | + && (attr_type_dep == TYPE_FMACS | ||
| 374 | + || attr_type_dep == TYPE_FMACD)) | ||
| 375 | + { | ||
| 376 | + if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | ||
| 377 | + *cost = insn_default_latency (dep) - 3; | ||
| 378 | + else | ||
| 379 | + *cost = insn_default_latency (dep); | ||
| 380 | + return false; | ||
| 381 | + } | ||
| 382 | + else | ||
| 383 | + { | ||
| 384 | + if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | ||
| 385 | + *cost = insn_default_latency (dep) + 1; | ||
| 386 | + else | ||
| 387 | + *cost = insn_default_latency (dep); | ||
| 388 | + } | ||
| 389 | + return false; | ||
| 390 | + } | ||
| 391 | + } | ||
| 392 | + } | ||
| 393 | + } | ||
| 394 | + break; | ||
| 395 | + | ||
| 396 | + default: | ||
| 397 | + gcc_unreachable (); | ||
| 398 | + } | ||
| 399 | + | ||
| 400 | + return true; | ||
| 401 | +} | ||
| 402 | + | ||
| 403 | +/* This function implements the target macro TARGET_SCHED_ADJUST_COST. | ||
| 404 | + It corrects the value of COST based on the relationship between | ||
| 405 | + INSN and DEP through the dependence LINK. It returns the new | ||
| 406 | + value. There is a per-core adjust_cost hook to adjust scheduler costs | ||
| 407 | + and the per-core hook can choose to completely override the generic | ||
| 408 | + adjust_cost function. Only put bits of code into arm_adjust_cost that | ||
| 409 | + are common across all cores. */ | ||
| 410 | +static int | ||
| 411 | +arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) | ||
| 412 | +{ | ||
| 413 | + rtx i_pat, d_pat; | ||
| 414 | + | ||
| 415 | + if (current_tune->sched_adjust_cost != NULL) | ||
| 416 | + { | ||
| 417 | + if (!current_tune->sched_adjust_cost (insn, link, dep, &cost)) | ||
| 418 | + return cost; | ||
| 419 | + } | ||
| 420 | |||
| 421 | /* XXX This is not strictly true for the FPA. */ | ||
| 422 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI | ||
| 423 | @@ -8187,7 +8317,8 @@ | ||
| 424 | constant pool are cached, and that others will miss. This is a | ||
| 425 | hack. */ | ||
| 426 | |||
| 427 | - if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem)) | ||
| 428 | + if ((GET_CODE (src_mem) == SYMBOL_REF | ||
| 429 | + && CONSTANT_POOL_ADDRESS_P (src_mem)) | ||
| 430 | || reg_mentioned_p (stack_pointer_rtx, src_mem) | ||
| 431 | || reg_mentioned_p (frame_pointer_rtx, src_mem) | ||
| 432 | || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) | ||
| 433 | |||
| 434 | === modified file 'gcc/config/arm/arm.md' | ||
| 435 | --- old/gcc/config/arm/arm.md 2010-08-23 14:39:12 +0000 | ||
| 436 | +++ new/gcc/config/arm/arm.md 2010-08-24 13:15:54 +0000 | ||
| 437 | @@ -150,13 +150,6 @@ | ||
| 438 | ; patterns that share the same RTL in both ARM and Thumb code. | ||
| 439 | (define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code"))) | ||
| 440 | |||
| 441 | -; IS_STRONGARM is set to 'yes' when compiling for StrongARM, it affects | ||
| 442 | -; scheduling decisions for the load unit and the multiplier. | ||
| 443 | -(define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_tune_strongarm"))) | ||
| 444 | - | ||
| 445 | -; IS_XSCALE is set to 'yes' when compiling for XScale. | ||
| 446 | -(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale"))) | ||
| 447 | - | ||
| 448 | ;; Operand number of an input operand that is shifted. Zero if the | ||
| 449 | ;; given instruction does not shift one of its input operands. | ||
| 450 | (define_attr "shift" "" (const_int 0)) | ||
| 451 | |||
| 452 | === modified file 'gcc/config/arm/cortex-a9.md' | ||
| 453 | --- old/gcc/config/arm/cortex-a9.md 2009-10-31 16:40:03 +0000 | ||
| 454 | +++ new/gcc/config/arm/cortex-a9.md 2010-08-24 13:15:54 +0000 | ||
| 455 | @@ -2,8 +2,10 @@ | ||
| 456 | ;; Copyright (C) 2008, 2009 Free Software Foundation, Inc. | ||
| 457 | ;; Originally written by CodeSourcery for VFP. | ||
| 458 | ;; | ||
| 459 | -;; Integer core pipeline description contributed by ARM Ltd. | ||
| 460 | -;; | ||
| 461 | +;; Rewritten by Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | ||
| 462 | +;; Integer Pipeline description contributed by ARM Ltd. | ||
| 463 | +;; VFP Pipeline description rewritten and contributed by ARM Ltd. | ||
| 464 | + | ||
| 465 | ;; This file is part of GCC. | ||
| 466 | ;; | ||
| 467 | ;; GCC is free software; you can redistribute it and/or modify it | ||
| 468 | @@ -22,28 +24,27 @@ | ||
| 469 | |||
| 470 | (define_automaton "cortex_a9") | ||
| 471 | |||
| 472 | -;; The Cortex-A9 integer core is modelled as a dual issue pipeline that has | ||
| 473 | +;; The Cortex-A9 core is modelled as a dual issue pipeline that has | ||
| 474 | ;; the following components. | ||
| 475 | ;; 1. 1 Load Store Pipeline. | ||
| 476 | ;; 2. P0 / main pipeline for data processing instructions. | ||
| 477 | ;; 3. P1 / Dual pipeline for Data processing instructions. | ||
| 478 | ;; 4. MAC pipeline for multiply as well as multiply | ||
| 479 | ;; and accumulate instructions. | ||
| 480 | -;; 5. 1 VFP / Neon pipeline. | ||
| 481 | -;; The Load/Store and VFP/Neon pipeline are multiplexed. | ||
| 482 | +;; 5. 1 VFP and an optional Neon unit. | ||
| 483 | +;; The Load/Store, VFP and Neon issue pipeline are multiplexed. | ||
| 484 | ;; The P0 / main pipeline and M1 stage of the MAC pipeline are | ||
| 485 | ;; multiplexed. | ||
| 486 | ;; The P1 / dual pipeline and M2 stage of the MAC pipeline are | ||
| 487 | ;; multiplexed. | ||
| 488 | -;; There are only 4 register read ports and hence at any point of | ||
| 489 | +;; There are only 4 integer register read ports and hence at any point of | ||
| 490 | ;; time we can't have issue down the E1 and the E2 ports unless | ||
| 491 | ;; of course there are bypass paths that get exercised. | ||
| 492 | ;; Both P0 and P1 have 2 stages E1 and E2. | ||
| 493 | ;; Data processing instructions issue to E1 or E2 depending on | ||
| 494 | ;; whether they have an early shift or not. | ||
| 495 | |||
| 496 | - | ||
| 497 | -(define_cpu_unit "cortex_a9_vfp, cortex_a9_ls" "cortex_a9") | ||
| 498 | +(define_cpu_unit "ca9_issue_vfp_neon, cortex_a9_ls" "cortex_a9") | ||
| 499 | (define_cpu_unit "cortex_a9_p0_e1, cortex_a9_p0_e2" "cortex_a9") | ||
| 500 | (define_cpu_unit "cortex_a9_p1_e1, cortex_a9_p1_e2" "cortex_a9") | ||
| 501 | (define_cpu_unit "cortex_a9_p0_wb, cortex_a9_p1_wb" "cortex_a9") | ||
| 502 | @@ -71,11 +72,7 @@ | ||
| 503 | |||
| 504 | ;; Issue at the same time along the load store pipeline and | ||
| 505 | ;; the VFP / Neon pipeline is not possible. | ||
| 506 | -;; FIXME:: At some point we need to model the issue | ||
| 507 | -;; of the load store and the vfp being shared rather than anything else. | ||
| 508 | - | ||
| 509 | -(exclusion_set "cortex_a9_ls" "cortex_a9_vfp") | ||
| 510 | - | ||
| 511 | +(exclusion_set "cortex_a9_ls" "ca9_issue_vfp_neon") | ||
| 512 | |||
| 513 | ;; Default data processing instruction without any shift | ||
| 514 | ;; The only exception to this is the mov instruction | ||
| 515 | @@ -101,18 +98,13 @@ | ||
| 516 | |||
| 517 | (define_insn_reservation "cortex_a9_load1_2" 4 | ||
| 518 | (and (eq_attr "tune" "cortexa9") | ||
| 519 | - (eq_attr "type" "load1, load2, load_byte")) | ||
| 520 | + (eq_attr "type" "load1, load2, load_byte, f_loads, f_loadd")) | ||
| 521 | "cortex_a9_ls") | ||
| 522 | |||
| 523 | ;; Loads multiples and store multiples can't be issued for 2 cycles in a | ||
| 524 | ;; row. The description below assumes that addresses are 64 bit aligned. | ||
| 525 | ;; If not, there is an extra cycle latency which is not modelled. | ||
| 526 | |||
| 527 | -;; FIXME:: This bit might need to be reworked when we get to | ||
| 528 | -;; tuning for the VFP because strictly speaking the ldm | ||
| 529 | -;; is sent to the LSU unit as is and there is only an | ||
| 530 | -;; issue restriction between the LSU and the VFP/ Neon unit. | ||
| 531 | - | ||
| 532 | (define_insn_reservation "cortex_a9_load3_4" 5 | ||
| 533 | (and (eq_attr "tune" "cortexa9") | ||
| 534 | (eq_attr "type" "load3, load4")) | ||
| 535 | @@ -120,12 +112,13 @@ | ||
| 536 | |||
| 537 | (define_insn_reservation "cortex_a9_store1_2" 0 | ||
| 538 | (and (eq_attr "tune" "cortexa9") | ||
| 539 | - (eq_attr "type" "store1, store2")) | ||
| 540 | + (eq_attr "type" "store1, store2, f_stores, f_stored")) | ||
| 541 | "cortex_a9_ls") | ||
| 542 | |||
| 543 | ;; Almost all our store multiples use an auto-increment | ||
| 544 | ;; form. Don't issue back to back load and store multiples | ||
| 545 | ;; because the load store unit will stall. | ||
| 546 | + | ||
| 547 | (define_insn_reservation "cortex_a9_store3_4" 0 | ||
| 548 | (and (eq_attr "tune" "cortexa9") | ||
| 549 | (eq_attr "type" "store3, store4")) | ||
| 550 | @@ -193,47 +186,79 @@ | ||
| 551 | (define_insn_reservation "cortex_a9_call" 0 | ||
| 552 | (and (eq_attr "tune" "cortexa9") | ||
| 553 | (eq_attr "type" "call")) | ||
| 554 | - "cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + cortex_a9_vfp") | ||
| 555 | + "cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + ca9_issue_vfp_neon") | ||
| 556 | |||
| 557 | |||
| 558 | ;; Pipelining for VFP instructions. | ||
| 559 | - | ||
| 560 | -(define_insn_reservation "cortex_a9_ffarith" 1 | ||
| 561 | +;; Issue happens either along load store unit or the VFP / Neon unit. | ||
| 562 | +;; Pipeline Instruction Classification. | ||
| 563 | +;; FPS - fcpys, ffariths, ffarithd,r_2_f,f_2_r | ||
| 564 | +;; FP_ADD - fadds, faddd, fcmps (1) | ||
| 565 | +;; FPMUL - fmul{s,d}, fmac{s,d} | ||
| 566 | +;; FPDIV - fdiv{s,d} | ||
| 567 | +(define_cpu_unit "ca9fps" "cortex_a9") | ||
| 568 | +(define_cpu_unit "ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4" "cortex_a9") | ||
| 569 | +(define_cpu_unit "ca9fp_mul1, ca9fp_mul2 , ca9fp_mul3, ca9fp_mul4" "cortex_a9") | ||
| 570 | +(define_cpu_unit "ca9fp_ds1" "cortex_a9") | ||
| 571 | + | ||
| 572 | + | ||
| 573 | +;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle. | ||
| 574 | +(define_insn_reservation "cortex_a9_fps" 2 | ||
| 575 | (and (eq_attr "tune" "cortexa9") | ||
| 576 | - (eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd,fconsts,fconstd")) | ||
| 577 | - "cortex_a9_vfp") | ||
| 578 | + (eq_attr "type" "fcpys, fconsts, fconstd, ffariths, ffarithd, r_2_f, f_2_r, f_flag")) | ||
| 579 | + "ca9_issue_vfp_neon + ca9fps") | ||
| 580 | + | ||
| 581 | +(define_bypass 1 | ||
| 582 | + "cortex_a9_fps" | ||
| 583 | + "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply") | ||
| 584 | + | ||
| 585 | +;; Scheduling on the FP_ADD pipeline. | ||
| 586 | +(define_reservation "ca9fp_add" "ca9_issue_vfp_neon + ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4") | ||
| 587 | |||
| 588 | (define_insn_reservation "cortex_a9_fadd" 4 | ||
| 589 | - (and (eq_attr "tune" "cortexa9") | ||
| 590 | - (eq_attr "type" "fadds,faddd,f_cvt")) | ||
| 591 | - "cortex_a9_vfp") | ||
| 592 | - | ||
| 593 | -(define_insn_reservation "cortex_a9_fmuls" 5 | ||
| 594 | - (and (eq_attr "tune" "cortexa9") | ||
| 595 | - (eq_attr "type" "fmuls")) | ||
| 596 | - "cortex_a9_vfp") | ||
| 597 | - | ||
| 598 | -(define_insn_reservation "cortex_a9_fmuld" 6 | ||
| 599 | - (and (eq_attr "tune" "cortexa9") | ||
| 600 | - (eq_attr "type" "fmuld")) | ||
| 601 | - "cortex_a9_vfp*2") | ||
| 602 | + (and (eq_attr "tune" "cortexa9") | ||
| 603 | + (eq_attr "type" "fadds, faddd, f_cvt")) | ||
| 604 | + "ca9fp_add") | ||
| 605 | + | ||
| 606 | +(define_insn_reservation "cortex_a9_fcmp" 1 | ||
| 607 | + (and (eq_attr "tune" "cortexa9") | ||
| 608 | + (eq_attr "type" "fcmps, fcmpd")) | ||
| 609 | + "ca9_issue_vfp_neon + ca9fp_add1") | ||
| 610 | + | ||
| 611 | +;; Scheduling for the Multiply and MAC instructions. | ||
| 612 | +(define_reservation "ca9fmuls" | ||
| 613 | + "ca9fp_mul1 + ca9_issue_vfp_neon, ca9fp_mul2, ca9fp_mul3, ca9fp_mul4") | ||
| 614 | + | ||
| 615 | +(define_reservation "ca9fmuld" | ||
| 616 | + "ca9fp_mul1 + ca9_issue_vfp_neon, (ca9fp_mul1 + ca9fp_mul2), ca9fp_mul2, ca9fp_mul3, ca9fp_mul4") | ||
| 617 | + | ||
| 618 | +(define_insn_reservation "cortex_a9_fmuls" 4 | ||
| 619 | + (and (eq_attr "tune" "cortexa9") | ||
| 620 | + (eq_attr "type" "fmuls")) | ||
| 621 | + "ca9fmuls") | ||
| 622 | + | ||
| 623 | +(define_insn_reservation "cortex_a9_fmuld" 5 | ||
| 624 | + (and (eq_attr "tune" "cortexa9") | ||
| 625 | + (eq_attr "type" "fmuld")) | ||
| 626 | + "ca9fmuld") | ||
| 627 | |||
| 628 | (define_insn_reservation "cortex_a9_fmacs" 8 | ||
| 629 | - (and (eq_attr "tune" "cortexa9") | ||
| 630 | - (eq_attr "type" "fmacs")) | ||
| 631 | - "cortex_a9_vfp") | ||
| 632 | - | ||
| 633 | -(define_insn_reservation "cortex_a9_fmacd" 8 | ||
| 634 | - (and (eq_attr "tune" "cortexa9") | ||
| 635 | - (eq_attr "type" "fmacd")) | ||
| 636 | - "cortex_a9_vfp*2") | ||
| 637 | - | ||
| 638 | + (and (eq_attr "tune" "cortexa9") | ||
| 639 | + (eq_attr "type" "fmacs")) | ||
| 640 | + "ca9fmuls, ca9fp_add") | ||
| 641 | + | ||
| 642 | +(define_insn_reservation "cortex_a9_fmacd" 9 | ||
| 643 | + (and (eq_attr "tune" "cortexa9") | ||
| 644 | + (eq_attr "type" "fmacd")) | ||
| 645 | + "ca9fmuld, ca9fp_add") | ||
| 646 | + | ||
| 647 | +;; Division pipeline description. | ||
| 648 | (define_insn_reservation "cortex_a9_fdivs" 15 | ||
| 649 | - (and (eq_attr "tune" "cortexa9") | ||
| 650 | - (eq_attr "type" "fdivs")) | ||
| 651 | - "cortex_a9_vfp*10") | ||
| 652 | + (and (eq_attr "tune" "cortexa9") | ||
| 653 | + (eq_attr "type" "fdivs")) | ||
| 654 | + "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*14") | ||
| 655 | |||
| 656 | (define_insn_reservation "cortex_a9_fdivd" 25 | ||
| 657 | - (and (eq_attr "tune" "cortexa9") | ||
| 658 | - (eq_attr "type" "fdivd")) | ||
| 659 | - "cortex_a9_vfp*20") | ||
| 660 | + (and (eq_attr "tune" "cortexa9") | ||
| 661 | + (eq_attr "type" "fdivd")) | ||
| 662 | + "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24") | ||
| 663 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch deleted file mode 100644 index 03b478b79..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch +++ /dev/null | |||
| @@ -1,380 +0,0 @@ | |||
| 1 | 2010-08-25 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | |||
| 3 | Revert: | ||
| 4 | |||
| 5 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 6 | |||
| 7 | Merge from Sourcery G++ 4.4: | ||
| 8 | |||
| 9 | 2010-04-11 Julian Brown <julian@codesourcery.com> | ||
| 10 | |||
| 11 | Issue #7326 | ||
| 12 | |||
| 13 | gcc/ | ||
| 14 | * config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5. | ||
| 15 | * config/arm/arm.md (generic_sched): No for Cortex-A5. | ||
| 16 | (generic_vfp): Likewise. | ||
| 17 | (cortex-a5.md): Include. | ||
| 18 | * config/arm/cortex-a5.md: New. | ||
| 19 | |||
| 20 | 2010-08-24 Andrew Stubbs <ams@codesourcery.com> | ||
| 21 | |||
| 22 | Backport from FSF: | ||
| 23 | |||
| 24 | === modified file 'gcc/config/arm/arm.c' | ||
| 25 | --- old/gcc/config/arm/arm.c 2010-08-24 13:15:54 +0000 | ||
| 26 | +++ new/gcc/config/arm/arm.c 2010-08-25 16:20:13 +0000 | ||
| 27 | @@ -22472,7 +22472,6 @@ | ||
| 28 | { | ||
| 29 | case cortexr4: | ||
| 30 | case cortexr4f: | ||
| 31 | - case cortexa5: | ||
| 32 | case cortexa8: | ||
| 33 | case cortexa9: | ||
| 34 | return 2; | ||
| 35 | |||
| 36 | === modified file 'gcc/config/arm/arm.md' | ||
| 37 | --- old/gcc/config/arm/arm.md 2010-08-24 13:15:54 +0000 | ||
| 38 | +++ new/gcc/config/arm/arm.md 2010-08-25 16:20:13 +0000 | ||
| 39 | @@ -412,7 +412,7 @@ | ||
| 40 | |||
| 41 | (define_attr "generic_sched" "yes,no" | ||
| 42 | (const (if_then_else | ||
| 43 | - (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9") | ||
| 44 | + (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9") | ||
| 45 | (eq_attr "tune_cortexr4" "yes")) | ||
| 46 | (const_string "no") | ||
| 47 | (const_string "yes")))) | ||
| 48 | @@ -420,7 +420,7 @@ | ||
| 49 | (define_attr "generic_vfp" "yes,no" | ||
| 50 | (const (if_then_else | ||
| 51 | (and (eq_attr "fpu" "vfp") | ||
| 52 | - (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9") | ||
| 53 | + (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9") | ||
| 54 | (eq_attr "tune_cortexr4" "no")) | ||
| 55 | (const_string "yes") | ||
| 56 | (const_string "no")))) | ||
| 57 | @@ -444,7 +444,6 @@ | ||
| 58 | (include "arm1020e.md") | ||
| 59 | (include "arm1026ejs.md") | ||
| 60 | (include "arm1136jfs.md") | ||
| 61 | -(include "cortex-a5.md") | ||
| 62 | (include "cortex-a8.md") | ||
| 63 | (include "cortex-a9.md") | ||
| 64 | (include "cortex-r4.md") | ||
| 65 | |||
| 66 | === removed file 'gcc/config/arm/cortex-a5.md' | ||
| 67 | --- old/gcc/config/arm/cortex-a5.md 2010-08-13 15:15:12 +0000 | ||
| 68 | +++ new/gcc/config/arm/cortex-a5.md 1970-01-01 00:00:00 +0000 | ||
| 69 | @@ -1,310 +0,0 @@ | ||
| 70 | -;; ARM Cortex-A5 pipeline description | ||
| 71 | -;; Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 72 | -;; Contributed by CodeSourcery. | ||
| 73 | -;; | ||
| 74 | -;; This file is part of GCC. | ||
| 75 | -;; | ||
| 76 | -;; GCC is free software; you can redistribute it and/or modify it | ||
| 77 | -;; under the terms of the GNU General Public License as published by | ||
| 78 | -;; the Free Software Foundation; either version 3, or (at your option) | ||
| 79 | -;; any later version. | ||
| 80 | -;; | ||
| 81 | -;; GCC is distributed in the hope that it will be useful, but | ||
| 82 | -;; WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 83 | -;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 84 | -;; General Public License for more details. | ||
| 85 | -;; | ||
| 86 | -;; You should have received a copy of the GNU General Public License | ||
| 87 | -;; along with GCC; see the file COPYING3. If not see | ||
| 88 | -;; <http://www.gnu.org/licenses/>. | ||
| 89 | - | ||
| 90 | -(define_automaton "cortex_a5") | ||
| 91 | - | ||
| 92 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 93 | -;; Functional units. | ||
| 94 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 95 | - | ||
| 96 | -;; The integer (ALU) pipeline. There are five DPU pipeline stages. However the | ||
| 97 | -;; decode/issue stages operate the same for all instructions, so do not model | ||
| 98 | -;; them. We only need to model the first execute stage because instructions | ||
| 99 | -;; always advance one stage per cycle in order. Only branch instructions may | ||
| 100 | -;; dual-issue, so a single unit covers all of the LS, ALU, MAC and FPU | ||
| 101 | -;; pipelines. | ||
| 102 | - | ||
| 103 | -(define_cpu_unit "cortex_a5_ex1" "cortex_a5") | ||
| 104 | - | ||
| 105 | -;; The branch pipeline. Branches can dual-issue with other instructions | ||
| 106 | -;; (except when those instructions take multiple cycles to issue). | ||
| 107 | - | ||
| 108 | -(define_cpu_unit "cortex_a5_branch" "cortex_a5") | ||
| 109 | - | ||
| 110 | -;; Pseudo-unit for blocking the multiply pipeline when a double-precision | ||
| 111 | -;; multiply is in progress. | ||
| 112 | - | ||
| 113 | -(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5") | ||
| 114 | - | ||
| 115 | -;; The floating-point add pipeline (ex1/f1 stage), used to model the usage | ||
| 116 | -;; of the add pipeline by fmac instructions, etc. | ||
| 117 | - | ||
| 118 | -(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5") | ||
| 119 | - | ||
| 120 | -;; Floating-point div/sqrt (long latency, out-of-order completion). | ||
| 121 | - | ||
| 122 | -(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5") | ||
| 123 | - | ||
| 124 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 125 | -;; ALU instructions. | ||
| 126 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 127 | - | ||
| 128 | -(define_insn_reservation "cortex_a5_alu" 2 | ||
| 129 | - (and (eq_attr "tune" "cortexa5") | ||
| 130 | - (eq_attr "type" "alu")) | ||
| 131 | - "cortex_a5_ex1") | ||
| 132 | - | ||
| 133 | -(define_insn_reservation "cortex_a5_alu_shift" 2 | ||
| 134 | - (and (eq_attr "tune" "cortexa5") | ||
| 135 | - (eq_attr "type" "alu_shift,alu_shift_reg")) | ||
| 136 | - "cortex_a5_ex1") | ||
| 137 | - | ||
| 138 | -;; Forwarding path for unshifted operands. | ||
| 139 | - | ||
| 140 | -(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" | ||
| 141 | - "cortex_a5_alu") | ||
| 142 | - | ||
| 143 | -(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" | ||
| 144 | - "cortex_a5_alu_shift" | ||
| 145 | - "arm_no_early_alu_shift_dep") | ||
| 146 | - | ||
| 147 | -;; The multiplier pipeline can forward results from wr stage only (so I don't | ||
| 148 | -;; think there's any need to specify bypasses). | ||
| 149 | - | ||
| 150 | -(define_insn_reservation "cortex_a5_mul" 2 | ||
| 151 | - (and (eq_attr "tune" "cortexa5") | ||
| 152 | - (eq_attr "type" "mult")) | ||
| 153 | - "cortex_a5_ex1") | ||
| 154 | - | ||
| 155 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 156 | -;; Load/store instructions. | ||
| 157 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 158 | - | ||
| 159 | -;; Address-generation happens in the issue stage, which is one stage behind | ||
| 160 | -;; the ex1 stage (the first stage we care about for scheduling purposes). The | ||
| 161 | -;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr. | ||
| 162 | - | ||
| 163 | -;; FIXME: These might not be entirely accurate for load2, load3, load4. I think | ||
| 164 | -;; they make sense since there's a 32-bit interface between the DPU and the DCU, | ||
| 165 | -;; so we can't load more than that per cycle. The store2, store3, store4 | ||
| 166 | -;; reservations are similarly guessed. | ||
| 167 | - | ||
| 168 | -(define_insn_reservation "cortex_a5_load1" 2 | ||
| 169 | - (and (eq_attr "tune" "cortexa5") | ||
| 170 | - (eq_attr "type" "load_byte,load1")) | ||
| 171 | - "cortex_a5_ex1") | ||
| 172 | - | ||
| 173 | -(define_insn_reservation "cortex_a5_store1" 0 | ||
| 174 | - (and (eq_attr "tune" "cortexa5") | ||
| 175 | - (eq_attr "type" "store1")) | ||
| 176 | - "cortex_a5_ex1") | ||
| 177 | - | ||
| 178 | -(define_insn_reservation "cortex_a5_load2" 3 | ||
| 179 | - (and (eq_attr "tune" "cortexa5") | ||
| 180 | - (eq_attr "type" "load2")) | ||
| 181 | - "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 182 | - | ||
| 183 | -(define_insn_reservation "cortex_a5_store2" 0 | ||
| 184 | - (and (eq_attr "tune" "cortexa5") | ||
| 185 | - (eq_attr "type" "store2")) | ||
| 186 | - "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 187 | - | ||
| 188 | -(define_insn_reservation "cortex_a5_load3" 4 | ||
| 189 | - (and (eq_attr "tune" "cortexa5") | ||
| 190 | - (eq_attr "type" "load3")) | ||
| 191 | - "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ | ||
| 192 | - cortex_a5_ex1") | ||
| 193 | - | ||
| 194 | -(define_insn_reservation "cortex_a5_store3" 0 | ||
| 195 | - (and (eq_attr "tune" "cortexa5") | ||
| 196 | - (eq_attr "type" "store3")) | ||
| 197 | - "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ | ||
| 198 | - cortex_a5_ex1") | ||
| 199 | - | ||
| 200 | -(define_insn_reservation "cortex_a5_load4" 5 | ||
| 201 | - (and (eq_attr "tune" "cortexa5") | ||
| 202 | - (eq_attr "type" "load3")) | ||
| 203 | - "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ | ||
| 204 | - cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 205 | - | ||
| 206 | -(define_insn_reservation "cortex_a5_store4" 0 | ||
| 207 | - (and (eq_attr "tune" "cortexa5") | ||
| 208 | - (eq_attr "type" "store3")) | ||
| 209 | - "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ | ||
| 210 | - cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 211 | - | ||
| 212 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 213 | -;; Branches. | ||
| 214 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 215 | - | ||
| 216 | -;; Direct branches are the only instructions we can dual-issue (also IT and | ||
| 217 | -;; nop, but those aren't very interesting for scheduling). (The latency here | ||
| 218 | -;; is meant to represent when the branch actually takes place, but may not be | ||
| 219 | -;; entirely correct.) | ||
| 220 | - | ||
| 221 | -(define_insn_reservation "cortex_a5_branch" 3 | ||
| 222 | - (and (eq_attr "tune" "cortexa5") | ||
| 223 | - (eq_attr "type" "branch,call")) | ||
| 224 | - "cortex_a5_branch") | ||
| 225 | - | ||
| 226 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 227 | -;; Floating-point arithmetic. | ||
| 228 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 229 | - | ||
| 230 | -(define_insn_reservation "cortex_a5_fpalu" 4 | ||
| 231 | - (and (eq_attr "tune" "cortexa5") | ||
| 232 | - (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ | ||
| 233 | - fcmps, fcmpd")) | ||
| 234 | - "cortex_a5_ex1+cortex_a5_fpadd_pipe") | ||
| 235 | - | ||
| 236 | -;; For fconsts and fconstd, 8-bit immediate data is passed directly from | ||
| 237 | -;; f1 to f3 (which I think reduces the latency by one cycle). | ||
| 238 | - | ||
| 239 | -(define_insn_reservation "cortex_a5_fconst" 3 | ||
| 240 | - (and (eq_attr "tune" "cortexa5") | ||
| 241 | - (eq_attr "type" "fconsts,fconstd")) | ||
| 242 | - "cortex_a5_ex1+cortex_a5_fpadd_pipe") | ||
| 243 | - | ||
| 244 | -;; We should try not to attempt to issue a single-precision multiplication in | ||
| 245 | -;; the middle of a double-precision multiplication operation (the usage of | ||
| 246 | -;; cortex_a5_fpmul_pipe). | ||
| 247 | - | ||
| 248 | -(define_insn_reservation "cortex_a5_fpmuls" 4 | ||
| 249 | - (and (eq_attr "tune" "cortexa5") | ||
| 250 | - (eq_attr "type" "fmuls")) | ||
| 251 | - "cortex_a5_ex1+cortex_a5_fpmul_pipe") | ||
| 252 | - | ||
| 253 | -;; For single-precision multiply-accumulate, the add (accumulate) is issued | ||
| 254 | -;; whilst the multiply is in F4. The multiply result can then be forwarded | ||
| 255 | -;; from F5 to F1. The issue unit is only used once (when we first start | ||
| 256 | -;; processing the instruction), but the usage of the FP add pipeline could | ||
| 257 | -;; block other instructions attempting to use it simultaneously. We try to | ||
| 258 | -;; avoid that using cortex_a5_fpadd_pipe. | ||
| 259 | - | ||
| 260 | -(define_insn_reservation "cortex_a5_fpmacs" 8 | ||
| 261 | - (and (eq_attr "tune" "cortexa5") | ||
| 262 | - (eq_attr "type" "fmacs")) | ||
| 263 | - "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") | ||
| 264 | - | ||
| 265 | -;; Non-multiply instructions can issue in the middle two instructions of a | ||
| 266 | -;; double-precision multiply. Note that it isn't entirely clear when a branch | ||
| 267 | -;; can dual-issue when a multi-cycle multiplication is in progress; we ignore | ||
| 268 | -;; that for now though. | ||
| 269 | - | ||
| 270 | -(define_insn_reservation "cortex_a5_fpmuld" 7 | ||
| 271 | - (and (eq_attr "tune" "cortexa5") | ||
| 272 | - (eq_attr "type" "fmuld")) | ||
| 273 | - "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ | ||
| 274 | - cortex_a5_ex1+cortex_a5_fpmul_pipe") | ||
| 275 | - | ||
| 276 | -(define_insn_reservation "cortex_a5_fpmacd" 11 | ||
| 277 | - (and (eq_attr "tune" "cortexa5") | ||
| 278 | - (eq_attr "type" "fmacd")) | ||
| 279 | - "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ | ||
| 280 | - cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") | ||
| 281 | - | ||
| 282 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 283 | -;; Floating-point divide/square root instructions. | ||
| 284 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 285 | - | ||
| 286 | -;; ??? Not sure if the 14 cycles taken for single-precision divide to complete | ||
| 287 | -;; includes the time taken for the special instruction used to collect the | ||
| 288 | -;; result to travel down the multiply pipeline, or not. Assuming so. (If | ||
| 289 | -;; that's wrong, the latency should be increased by a few cycles.) | ||
| 290 | - | ||
| 291 | -;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the | ||
| 292 | -;; multiply pipeline to collect the divide/square-root result. | ||
| 293 | - | ||
| 294 | -(define_insn_reservation "cortex_a5_fdivs" 14 | ||
| 295 | - (and (eq_attr "tune" "cortexa5") | ||
| 296 | - (eq_attr "type" "fdivs")) | ||
| 297 | - "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13") | ||
| 298 | - | ||
| 299 | -;; ??? Similarly for fdivd. | ||
| 300 | - | ||
| 301 | -(define_insn_reservation "cortex_a5_fdivd" 29 | ||
| 302 | - (and (eq_attr "tune" "cortexa5") | ||
| 303 | - (eq_attr "type" "fdivd")) | ||
| 304 | - "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28") | ||
| 305 | - | ||
| 306 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 307 | -;; VFP to/from core transfers. | ||
| 308 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 309 | - | ||
| 310 | -;; FP loads take data from wr/rot/f3. Might need to define bypasses to model | ||
| 311 | -;; this? | ||
| 312 | - | ||
| 313 | -;; Core-to-VFP transfers use the multiply pipeline. | ||
| 314 | -;; Not sure about this at all... I think we need some bypasses too. | ||
| 315 | - | ||
| 316 | -(define_insn_reservation "cortex_a5_r2f" 4 | ||
| 317 | - (and (eq_attr "tune" "cortexa5") | ||
| 318 | - (eq_attr "type" "r_2_f")) | ||
| 319 | - "cortex_a5_ex1") | ||
| 320 | - | ||
| 321 | -;; Not sure about this either. 6.8.7 says "Additionally, the store pipe used | ||
| 322 | -;; for store and FP->core register transfers can forward into the F2 and F3 | ||
| 323 | -;; stages." | ||
| 324 | -;; This doesn't correspond to what we have though. | ||
| 325 | - | ||
| 326 | -(define_insn_reservation "cortex_a5_f2r" 2 | ||
| 327 | - (and (eq_attr "tune" "cortexa5") | ||
| 328 | - (eq_attr "type" "f_2_r")) | ||
| 329 | - "cortex_a5_ex1") | ||
| 330 | - | ||
| 331 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 332 | -;; VFP flag transfer. | ||
| 333 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 334 | - | ||
| 335 | -;; ??? The flag forwarding described in section 6.8.11 of the Cortex-A5 DPU | ||
| 336 | -;; specification (from fmstat to the ex2 stage of the second instruction) is | ||
| 337 | -;; not modeled at present. | ||
| 338 | - | ||
| 339 | -(define_insn_reservation "cortex_a5_f_flags" 4 | ||
| 340 | - (and (eq_attr "tune" "cortexa5") | ||
| 341 | - (eq_attr "type" "f_flag")) | ||
| 342 | - "cortex_a5_ex1") | ||
| 343 | - | ||
| 344 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 345 | -;; VFP load/store. | ||
| 346 | -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 347 | - | ||
| 348 | -(define_insn_reservation "cortex_a5_f_loads" 4 | ||
| 349 | - (and (eq_attr "tune" "cortexa5") | ||
| 350 | - (eq_attr "type" "f_loads")) | ||
| 351 | - "cortex_a5_ex1") | ||
| 352 | - | ||
| 353 | -(define_insn_reservation "cortex_a5_f_loadd" 5 | ||
| 354 | - (and (eq_attr "tune" "cortexa5") | ||
| 355 | - (eq_attr "type" "f_load,f_loadd")) | ||
| 356 | - "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 357 | - | ||
| 358 | -(define_insn_reservation "cortex_a5_f_stores" 0 | ||
| 359 | - (and (eq_attr "tune" "cortexa5") | ||
| 360 | - (eq_attr "type" "f_stores")) | ||
| 361 | - "cortex_a5_ex1") | ||
| 362 | - | ||
| 363 | -(define_insn_reservation "cortex_a5_f_stored" 0 | ||
| 364 | - (and (eq_attr "tune" "cortexa5") | ||
| 365 | - (eq_attr "type" "f_store,f_stored")) | ||
| 366 | - "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 367 | - | ||
| 368 | -;; Load-to-use for floating-point values has a penalty of one cycle, i.e. a | ||
| 369 | -;; latency of two (6.8.3). | ||
| 370 | - | ||
| 371 | -(define_bypass 2 "cortex_a5_f_loads" | ||
| 372 | - "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ | ||
| 373 | - cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ | ||
| 374 | - cortex_a5_f2r") | ||
| 375 | - | ||
| 376 | -(define_bypass 3 "cortex_a5_f_loadd" | ||
| 377 | - "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ | ||
| 378 | - cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ | ||
| 379 | - cortex_a5_f2r") | ||
| 380 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch deleted file mode 100644 index 60608e481..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch +++ /dev/null | |||
| @@ -1,360 +0,0 @@ | |||
| 1 | Backport from FSF: | ||
| 2 | |||
| 3 | 2010-08-25 Julian Brown <julian@codesourcery.com> | ||
| 4 | |||
| 5 | * config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5. | ||
| 6 | * config/arm/arm.md (generic_sched): No for Cortex-A5. | ||
| 7 | (generic_vfp): Likewise. | ||
| 8 | (cortex-a5.md): Include. | ||
| 9 | * config/arm/cortex-a5.md: New. | ||
| 10 | |||
| 11 | 2010-08-25 Andrew Stubbs <ams@codesourcery.com> | ||
| 12 | |||
| 13 | Revert: | ||
| 14 | |||
| 15 | 2010-07-26 Julian Brown <julian@codesourcery.com> | ||
| 16 | |||
| 17 | === modified file 'gcc/config/arm/arm.c' | ||
| 18 | --- old/gcc/config/arm/arm.c 2010-08-25 16:20:13 +0000 | ||
| 19 | +++ new/gcc/config/arm/arm.c 2010-08-25 16:22:17 +0000 | ||
| 20 | @@ -22472,6 +22472,7 @@ | ||
| 21 | { | ||
| 22 | case cortexr4: | ||
| 23 | case cortexr4f: | ||
| 24 | + case cortexa5: | ||
| 25 | case cortexa8: | ||
| 26 | case cortexa9: | ||
| 27 | return 2; | ||
| 28 | |||
| 29 | === modified file 'gcc/config/arm/arm.md' | ||
| 30 | --- old/gcc/config/arm/arm.md 2010-08-25 16:20:13 +0000 | ||
| 31 | +++ new/gcc/config/arm/arm.md 2010-08-25 16:22:17 +0000 | ||
| 32 | @@ -412,7 +412,7 @@ | ||
| 33 | |||
| 34 | (define_attr "generic_sched" "yes,no" | ||
| 35 | (const (if_then_else | ||
| 36 | - (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9") | ||
| 37 | + (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9") | ||
| 38 | (eq_attr "tune_cortexr4" "yes")) | ||
| 39 | (const_string "no") | ||
| 40 | (const_string "yes")))) | ||
| 41 | @@ -420,7 +420,7 @@ | ||
| 42 | (define_attr "generic_vfp" "yes,no" | ||
| 43 | (const (if_then_else | ||
| 44 | (and (eq_attr "fpu" "vfp") | ||
| 45 | - (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9") | ||
| 46 | + (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9") | ||
| 47 | (eq_attr "tune_cortexr4" "no")) | ||
| 48 | (const_string "yes") | ||
| 49 | (const_string "no")))) | ||
| 50 | @@ -444,6 +444,7 @@ | ||
| 51 | (include "arm1020e.md") | ||
| 52 | (include "arm1026ejs.md") | ||
| 53 | (include "arm1136jfs.md") | ||
| 54 | +(include "cortex-a5.md") | ||
| 55 | (include "cortex-a8.md") | ||
| 56 | (include "cortex-a9.md") | ||
| 57 | (include "cortex-r4.md") | ||
| 58 | |||
| 59 | === added file 'gcc/config/arm/cortex-a5.md' | ||
| 60 | --- old/gcc/config/arm/cortex-a5.md 1970-01-01 00:00:00 +0000 | ||
| 61 | +++ new/gcc/config/arm/cortex-a5.md 2010-08-25 16:22:17 +0000 | ||
| 62 | @@ -0,0 +1,297 @@ | ||
| 63 | +;; ARM Cortex-A5 pipeline description | ||
| 64 | +;; Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 65 | +;; Contributed by CodeSourcery. | ||
| 66 | +;; | ||
| 67 | +;; This file is part of GCC. | ||
| 68 | +;; | ||
| 69 | +;; GCC is free software; you can redistribute it and/or modify it | ||
| 70 | +;; under the terms of the GNU General Public License as published by | ||
| 71 | +;; the Free Software Foundation; either version 3, or (at your option) | ||
| 72 | +;; any later version. | ||
| 73 | +;; | ||
| 74 | +;; GCC is distributed in the hope that it will be useful, but | ||
| 75 | +;; WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 76 | +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 77 | +;; General Public License for more details. | ||
| 78 | +;; | ||
| 79 | +;; You should have received a copy of the GNU General Public License | ||
| 80 | +;; along with GCC; see the file COPYING3. If not see | ||
| 81 | +;; <http://www.gnu.org/licenses/>. | ||
| 82 | + | ||
| 83 | +(define_automaton "cortex_a5") | ||
| 84 | + | ||
| 85 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 86 | +;; Functional units. | ||
| 87 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 88 | + | ||
| 89 | +;; The integer (ALU) pipeline. There are five DPU pipeline | ||
| 90 | +;; stages. However the decode/issue stages operate the same for all | ||
| 91 | +;; instructions, so do not model them. We only need to model the | ||
| 92 | +;; first execute stage because instructions always advance one stage | ||
| 93 | +;; per cycle in order. Only branch instructions may dual-issue, so a | ||
| 94 | +;; single unit covers all of the LS, ALU, MAC and FPU pipelines. | ||
| 95 | + | ||
| 96 | +(define_cpu_unit "cortex_a5_ex1" "cortex_a5") | ||
| 97 | + | ||
| 98 | +;; The branch pipeline. Branches can dual-issue with other instructions | ||
| 99 | +;; (except when those instructions take multiple cycles to issue). | ||
| 100 | + | ||
| 101 | +(define_cpu_unit "cortex_a5_branch" "cortex_a5") | ||
| 102 | + | ||
| 103 | +;; Pseudo-unit for blocking the multiply pipeline when a double-precision | ||
| 104 | +;; multiply is in progress. | ||
| 105 | + | ||
| 106 | +(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5") | ||
| 107 | + | ||
| 108 | +;; The floating-point add pipeline (ex1/f1 stage), used to model the usage | ||
| 109 | +;; of the add pipeline by fmac instructions, etc. | ||
| 110 | + | ||
| 111 | +(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5") | ||
| 112 | + | ||
| 113 | +;; Floating-point div/sqrt (long latency, out-of-order completion). | ||
| 114 | + | ||
| 115 | +(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5") | ||
| 116 | + | ||
| 117 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 118 | +;; ALU instructions. | ||
| 119 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 120 | + | ||
| 121 | +(define_insn_reservation "cortex_a5_alu" 2 | ||
| 122 | + (and (eq_attr "tune" "cortexa5") | ||
| 123 | + (eq_attr "type" "alu")) | ||
| 124 | + "cortex_a5_ex1") | ||
| 125 | + | ||
| 126 | +(define_insn_reservation "cortex_a5_alu_shift" 2 | ||
| 127 | + (and (eq_attr "tune" "cortexa5") | ||
| 128 | + (eq_attr "type" "alu_shift,alu_shift_reg")) | ||
| 129 | + "cortex_a5_ex1") | ||
| 130 | + | ||
| 131 | +;; Forwarding path for unshifted operands. | ||
| 132 | + | ||
| 133 | +(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" | ||
| 134 | + "cortex_a5_alu") | ||
| 135 | + | ||
| 136 | +(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift" | ||
| 137 | + "cortex_a5_alu_shift" | ||
| 138 | + "arm_no_early_alu_shift_dep") | ||
| 139 | + | ||
| 140 | +;; The multiplier pipeline can forward results from wr stage only so | ||
| 141 | +;; there's no need to specify bypasses). | ||
| 142 | + | ||
| 143 | +(define_insn_reservation "cortex_a5_mul" 2 | ||
| 144 | + (and (eq_attr "tune" "cortexa5") | ||
| 145 | + (eq_attr "type" "mult")) | ||
| 146 | + "cortex_a5_ex1") | ||
| 147 | + | ||
| 148 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 149 | +;; Load/store instructions. | ||
| 150 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 151 | + | ||
| 152 | +;; Address-generation happens in the issue stage, which is one stage behind | ||
| 153 | +;; the ex1 stage (the first stage we care about for scheduling purposes). The | ||
| 154 | +;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr. | ||
| 155 | + | ||
| 156 | +(define_insn_reservation "cortex_a5_load1" 2 | ||
| 157 | + (and (eq_attr "tune" "cortexa5") | ||
| 158 | + (eq_attr "type" "load_byte,load1")) | ||
| 159 | + "cortex_a5_ex1") | ||
| 160 | + | ||
| 161 | +(define_insn_reservation "cortex_a5_store1" 0 | ||
| 162 | + (and (eq_attr "tune" "cortexa5") | ||
| 163 | + (eq_attr "type" "store1")) | ||
| 164 | + "cortex_a5_ex1") | ||
| 165 | + | ||
| 166 | +(define_insn_reservation "cortex_a5_load2" 3 | ||
| 167 | + (and (eq_attr "tune" "cortexa5") | ||
| 168 | + (eq_attr "type" "load2")) | ||
| 169 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 170 | + | ||
| 171 | +(define_insn_reservation "cortex_a5_store2" 0 | ||
| 172 | + (and (eq_attr "tune" "cortexa5") | ||
| 173 | + (eq_attr "type" "store2")) | ||
| 174 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 175 | + | ||
| 176 | +(define_insn_reservation "cortex_a5_load3" 4 | ||
| 177 | + (and (eq_attr "tune" "cortexa5") | ||
| 178 | + (eq_attr "type" "load3")) | ||
| 179 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ | ||
| 180 | + cortex_a5_ex1") | ||
| 181 | + | ||
| 182 | +(define_insn_reservation "cortex_a5_store3" 0 | ||
| 183 | + (and (eq_attr "tune" "cortexa5") | ||
| 184 | + (eq_attr "type" "store3")) | ||
| 185 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ | ||
| 186 | + cortex_a5_ex1") | ||
| 187 | + | ||
| 188 | +(define_insn_reservation "cortex_a5_load4" 5 | ||
| 189 | + (and (eq_attr "tune" "cortexa5") | ||
| 190 | + (eq_attr "type" "load3")) | ||
| 191 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ | ||
| 192 | + cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 193 | + | ||
| 194 | +(define_insn_reservation "cortex_a5_store4" 0 | ||
| 195 | + (and (eq_attr "tune" "cortexa5") | ||
| 196 | + (eq_attr "type" "store3")) | ||
| 197 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\ | ||
| 198 | + cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 199 | + | ||
| 200 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 201 | +;; Branches. | ||
| 202 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 203 | + | ||
| 204 | +;; Direct branches are the only instructions we can dual-issue (also IT and | ||
| 205 | +;; nop, but those aren't very interesting for scheduling). (The latency here | ||
| 206 | +;; is meant to represent when the branch actually takes place, but may not be | ||
| 207 | +;; entirely correct.) | ||
| 208 | + | ||
| 209 | +(define_insn_reservation "cortex_a5_branch" 3 | ||
| 210 | + (and (eq_attr "tune" "cortexa5") | ||
| 211 | + (eq_attr "type" "branch,call")) | ||
| 212 | + "cortex_a5_branch") | ||
| 213 | + | ||
| 214 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 215 | +;; Floating-point arithmetic. | ||
| 216 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 217 | + | ||
| 218 | +(define_insn_reservation "cortex_a5_fpalu" 4 | ||
| 219 | + (and (eq_attr "tune" "cortexa5") | ||
| 220 | + (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ | ||
| 221 | + fcmps, fcmpd")) | ||
| 222 | + "cortex_a5_ex1+cortex_a5_fpadd_pipe") | ||
| 223 | + | ||
| 224 | +;; For fconsts and fconstd, 8-bit immediate data is passed directly from | ||
| 225 | +;; f1 to f3 (which I think reduces the latency by one cycle). | ||
| 226 | + | ||
| 227 | +(define_insn_reservation "cortex_a5_fconst" 3 | ||
| 228 | + (and (eq_attr "tune" "cortexa5") | ||
| 229 | + (eq_attr "type" "fconsts,fconstd")) | ||
| 230 | + "cortex_a5_ex1+cortex_a5_fpadd_pipe") | ||
| 231 | + | ||
| 232 | +;; We should try not to attempt to issue a single-precision multiplication in | ||
| 233 | +;; the middle of a double-precision multiplication operation (the usage of | ||
| 234 | +;; cortex_a5_fpmul_pipe). | ||
| 235 | + | ||
| 236 | +(define_insn_reservation "cortex_a5_fpmuls" 4 | ||
| 237 | + (and (eq_attr "tune" "cortexa5") | ||
| 238 | + (eq_attr "type" "fmuls")) | ||
| 239 | + "cortex_a5_ex1+cortex_a5_fpmul_pipe") | ||
| 240 | + | ||
| 241 | +;; For single-precision multiply-accumulate, the add (accumulate) is issued | ||
| 242 | +;; whilst the multiply is in F4. The multiply result can then be forwarded | ||
| 243 | +;; from F5 to F1. The issue unit is only used once (when we first start | ||
| 244 | +;; processing the instruction), but the usage of the FP add pipeline could | ||
| 245 | +;; block other instructions attempting to use it simultaneously. We try to | ||
| 246 | +;; avoid that using cortex_a5_fpadd_pipe. | ||
| 247 | + | ||
| 248 | +(define_insn_reservation "cortex_a5_fpmacs" 8 | ||
| 249 | + (and (eq_attr "tune" "cortexa5") | ||
| 250 | + (eq_attr "type" "fmacs")) | ||
| 251 | + "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") | ||
| 252 | + | ||
| 253 | +;; Non-multiply instructions can issue in the middle two instructions of a | ||
| 254 | +;; double-precision multiply. Note that it isn't entirely clear when a branch | ||
| 255 | +;; can dual-issue when a multi-cycle multiplication is in progress; we ignore | ||
| 256 | +;; that for now though. | ||
| 257 | + | ||
| 258 | +(define_insn_reservation "cortex_a5_fpmuld" 7 | ||
| 259 | + (and (eq_attr "tune" "cortexa5") | ||
| 260 | + (eq_attr "type" "fmuld")) | ||
| 261 | + "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ | ||
| 262 | + cortex_a5_ex1+cortex_a5_fpmul_pipe") | ||
| 263 | + | ||
| 264 | +(define_insn_reservation "cortex_a5_fpmacd" 11 | ||
| 265 | + (and (eq_attr "tune" "cortexa5") | ||
| 266 | + (eq_attr "type" "fmacd")) | ||
| 267 | + "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\ | ||
| 268 | + cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe") | ||
| 269 | + | ||
| 270 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 271 | +;; Floating-point divide/square root instructions. | ||
| 272 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 273 | + | ||
| 274 | +;; ??? Not sure if the 14 cycles taken for single-precision divide to complete | ||
| 275 | +;; includes the time taken for the special instruction used to collect the | ||
| 276 | +;; result to travel down the multiply pipeline, or not. Assuming so. (If | ||
| 277 | +;; that's wrong, the latency should be increased by a few cycles.) | ||
| 278 | + | ||
| 279 | +;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the | ||
| 280 | +;; multiply pipeline to collect the divide/square-root result. | ||
| 281 | + | ||
| 282 | +(define_insn_reservation "cortex_a5_fdivs" 14 | ||
| 283 | + (and (eq_attr "tune" "cortexa5") | ||
| 284 | + (eq_attr "type" "fdivs")) | ||
| 285 | + "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13") | ||
| 286 | + | ||
| 287 | +;; ??? Similarly for fdivd. | ||
| 288 | + | ||
| 289 | +(define_insn_reservation "cortex_a5_fdivd" 29 | ||
| 290 | + (and (eq_attr "tune" "cortexa5") | ||
| 291 | + (eq_attr "type" "fdivd")) | ||
| 292 | + "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28") | ||
| 293 | + | ||
| 294 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 295 | +;; VFP to/from core transfers. | ||
| 296 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 297 | + | ||
| 298 | +;; FP loads take data from wr/rot/f3. | ||
| 299 | + | ||
| 300 | +;; Core-to-VFP transfers use the multiply pipeline. | ||
| 301 | + | ||
| 302 | +(define_insn_reservation "cortex_a5_r2f" 4 | ||
| 303 | + (and (eq_attr "tune" "cortexa5") | ||
| 304 | + (eq_attr "type" "r_2_f")) | ||
| 305 | + "cortex_a5_ex1") | ||
| 306 | + | ||
| 307 | +(define_insn_reservation "cortex_a5_f2r" 2 | ||
| 308 | + (and (eq_attr "tune" "cortexa5") | ||
| 309 | + (eq_attr "type" "f_2_r")) | ||
| 310 | + "cortex_a5_ex1") | ||
| 311 | + | ||
| 312 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 313 | +;; VFP flag transfer. | ||
| 314 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 315 | + | ||
| 316 | +;; ??? The flag forwarding from fmstat to the ex2 stage of the second | ||
| 317 | +;; instruction is not modeled at present. | ||
| 318 | + | ||
| 319 | +(define_insn_reservation "cortex_a5_f_flags" 4 | ||
| 320 | + (and (eq_attr "tune" "cortexa5") | ||
| 321 | + (eq_attr "type" "f_flag")) | ||
| 322 | + "cortex_a5_ex1") | ||
| 323 | + | ||
| 324 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 325 | +;; VFP load/store. | ||
| 326 | +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; | ||
| 327 | + | ||
| 328 | +(define_insn_reservation "cortex_a5_f_loads" 4 | ||
| 329 | + (and (eq_attr "tune" "cortexa5") | ||
| 330 | + (eq_attr "type" "f_loads")) | ||
| 331 | + "cortex_a5_ex1") | ||
| 332 | + | ||
| 333 | +(define_insn_reservation "cortex_a5_f_loadd" 5 | ||
| 334 | + (and (eq_attr "tune" "cortexa5") | ||
| 335 | + (eq_attr "type" "f_load,f_loadd")) | ||
| 336 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 337 | + | ||
| 338 | +(define_insn_reservation "cortex_a5_f_stores" 0 | ||
| 339 | + (and (eq_attr "tune" "cortexa5") | ||
| 340 | + (eq_attr "type" "f_stores")) | ||
| 341 | + "cortex_a5_ex1") | ||
| 342 | + | ||
| 343 | +(define_insn_reservation "cortex_a5_f_stored" 0 | ||
| 344 | + (and (eq_attr "tune" "cortexa5") | ||
| 345 | + (eq_attr "type" "f_store,f_stored")) | ||
| 346 | + "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1") | ||
| 347 | + | ||
| 348 | +;; Load-to-use for floating-point values has a penalty of one cycle, | ||
| 349 | +;; i.e. a latency of two. | ||
| 350 | + | ||
| 351 | +(define_bypass 2 "cortex_a5_f_loads" | ||
| 352 | + "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ | ||
| 353 | + cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ | ||
| 354 | + cortex_a5_f2r") | ||
| 355 | + | ||
| 356 | +(define_bypass 3 "cortex_a5_f_loadd" | ||
| 357 | + "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\ | ||
| 358 | + cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\ | ||
| 359 | + cortex_a5_f2r") | ||
| 360 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99374.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99374.patch deleted file mode 100644 index dfe193ff2..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99374.patch +++ /dev/null | |||
| @@ -1,72 +0,0 @@ | |||
| 1 | 2010-08-26 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Ubuntu GCC: | ||
| 4 | |||
| 5 | GCC bugzilla PR objc/41848. | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * objc/lang-specs.h: Work around ObjC and -fsection-anchors. | ||
| 9 | |||
| 10 | gcc/testsuite/ | ||
| 11 | * objc/execute/forward-1.x: Update for ARM. | ||
| 12 | |||
| 13 | 2010-08-25 Andrew Stubbs <ams@codesourcery.com> | ||
| 14 | |||
| 15 | Backport from FSF: | ||
| 16 | |||
| 17 | === modified file 'gcc/objc/lang-specs.h' | ||
| 18 | --- old/gcc/objc/lang-specs.h 2007-08-02 09:37:36 +0000 | ||
| 19 | +++ new/gcc/objc/lang-specs.h 2010-08-26 14:02:04 +0000 | ||
| 20 | @@ -26,29 +26,33 @@ | ||
| 21 | {"@objective-c", | ||
| 22 | "%{E|M|MM:cc1obj -E %{traditional|ftraditional|traditional-cpp:-traditional-cpp}\ | ||
| 23 | %(cpp_options) %(cpp_debug_options)}\ | ||
| 24 | + %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \ | ||
| 25 | %{!E:%{!M:%{!MM:\ | ||
| 26 | %{traditional|ftraditional|traditional-cpp:\ | ||
| 27 | %eGNU Objective C no longer supports traditional compilation}\ | ||
| 28 | %{save-temps|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps:%b.mi} %{!save-temps:%g.mi} \n\ | ||
| 29 | - cc1obj -fpreprocessed %{save-temps:%b.mi} %{!save-temps:%g.mi} %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}\ | ||
| 30 | + cc1obj -fpreprocessed -fno-section-anchors %{save-temps:%b.mi} %{!save-temps:%g.mi} %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}\ | ||
| 31 | %{!save-temps:%{!no-integrated-cpp:\ | ||
| 32 | - cc1obj %(cpp_unique_options) %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}}\ | ||
| 33 | + cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %{print-objc-runtime-info} %{gen-decls}}}\ | ||
| 34 | %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, | ||
| 35 | {".mi", "@objc-cpp-output", 0, 0, 0}, | ||
| 36 | {"@objc-cpp-output", | ||
| 37 | - "%{!M:%{!MM:%{!E:cc1obj -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ | ||
| 38 | - %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0}, | ||
| 39 | + "%{!M:%{!MM:%{!E:cc1obj -fno-section-anchors -fpreprocessed %i %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ | ||
| 40 | + %{!fsyntax-only:%(invoke_as)}}}} \ | ||
| 41 | + %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} ", 0, 0, 0}, | ||
| 42 | {"@objective-c-header", | ||
| 43 | "%{E|M|MM:cc1obj -E %{traditional|ftraditional|traditional-cpp:-traditional-cpp}\ | ||
| 44 | %(cpp_options) %(cpp_debug_options)}\ | ||
| 45 | + %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \ | ||
| 46 | %{!E:%{!M:%{!MM:\ | ||
| 47 | %{traditional|ftraditional|traditional-cpp:\ | ||
| 48 | %eGNU Objective C no longer supports traditional compilation}\ | ||
| 49 | %{save-temps|no-integrated-cpp:cc1obj -E %(cpp_options) -o %{save-temps:%b.mi} %{!save-temps:%g.mi} \n\ | ||
| 50 | - cc1obj -fpreprocessed %b.mi %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ | ||
| 51 | + cc1obj -fpreprocessed %b.mi %(cc1_options) -fno-section-anchors %{print-objc-runtime-info} %{gen-decls}\ | ||
| 52 | -o %g.s %{!o*:--output-pch=%i.gch}\ | ||
| 53 | %W{o*:--output-pch=%*}%V}\ | ||
| 54 | + %{fsection-anchors: %eGNU Objective C can't use -fsection-anchors} \ | ||
| 55 | %{!save-temps:%{!no-integrated-cpp:\ | ||
| 56 | - cc1obj %(cpp_unique_options) %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ | ||
| 57 | + cc1obj %(cpp_unique_options) -fno-section-anchors %(cc1_options) %{print-objc-runtime-info} %{gen-decls}\ | ||
| 58 | -o %g.s %{!o*:--output-pch=%i.gch}\ | ||
| 59 | %W{o*:--output-pch=%*}%V}}}}}", 0, 0, 0}, | ||
| 60 | |||
| 61 | === modified file 'gcc/testsuite/objc/execute/forward-1.x' | ||
| 62 | --- old/gcc/testsuite/objc/execute/forward-1.x 2010-03-25 22:25:05 +0000 | ||
| 63 | +++ new/gcc/testsuite/objc/execute/forward-1.x 2010-08-26 14:02:04 +0000 | ||
| 64 | @@ -4,6 +4,7 @@ | ||
| 65 | |||
| 66 | if { ([istarget x86_64-*-linux*] && [check_effective_target_lp64] ) | ||
| 67 | || [istarget powerpc*-*-linux*] | ||
| 68 | + || [istarget arm*] | ||
| 69 | || [istarget powerpc*-*-aix*] | ||
| 70 | || [istarget s390*-*-*-linux*] | ||
| 71 | || [istarget sh4-*-linux*] | ||
| 72 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99375.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99375.patch deleted file mode 100644 index fac64b964..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99375.patch +++ /dev/null | |||
| @@ -1,146 +0,0 @@ | |||
| 1 | 2010-08-26 Maciej Rozycki <macro@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ 4.4: | ||
| 4 | |||
| 5 | 2009-02-17 Andrew Jenner <andrew@codesourcery.com> | ||
| 6 | Maciej Rozycki <macro@codesourcery.com> | ||
| 7 | |||
| 8 | gcc/ | ||
| 9 | * unwind.inc (_Unwind_RaiseException): Use return value of | ||
| 10 | uw_init_context. | ||
| 11 | * unwind-dw2.c (uw_init_context): Make macro an expression instead of | ||
| 12 | a statement. | ||
| 13 | (uw_init_context_1): Add return value. | ||
| 14 | * unwind-sjlj.c (uw_init_context): Add return value. | ||
| 15 | |||
| 16 | 2010-08-26 Andrew Stubbs <ams@codesourcery.com> | ||
| 17 | |||
| 18 | Merge from Ubuntu GCC: | ||
| 19 | |||
| 20 | === modified file 'gcc/unwind-dw2.c' | ||
| 21 | --- old/gcc/unwind-dw2.c 2010-04-27 08:41:30 +0000 | ||
| 22 | +++ new/gcc/unwind-dw2.c 2010-08-26 15:38:19 +0000 | ||
| 23 | @@ -1414,16 +1414,12 @@ | ||
| 24 | /* Fill in CONTEXT for top-of-stack. The only valid registers at this | ||
| 25 | level will be the return address and the CFA. */ | ||
| 26 | |||
| 27 | -#define uw_init_context(CONTEXT) \ | ||
| 28 | - do \ | ||
| 29 | - { \ | ||
| 30 | - /* Do any necessary initialization to access arbitrary stack frames. \ | ||
| 31 | - On the SPARC, this means flushing the register windows. */ \ | ||
| 32 | - __builtin_unwind_init (); \ | ||
| 33 | - uw_init_context_1 (CONTEXT, __builtin_dwarf_cfa (), \ | ||
| 34 | - __builtin_return_address (0)); \ | ||
| 35 | - } \ | ||
| 36 | - while (0) | ||
| 37 | +#define uw_init_context(CONTEXT) \ | ||
| 38 | + /* Do any necessary initialization to access arbitrary stack frames. \ | ||
| 39 | + On the SPARC, this means flushing the register windows. */ \ | ||
| 40 | + (__builtin_unwind_init (), \ | ||
| 41 | + uw_init_context_1 ((CONTEXT), __builtin_dwarf_cfa (), \ | ||
| 42 | + __builtin_return_address (0))) | ||
| 43 | |||
| 44 | static inline void | ||
| 45 | init_dwarf_reg_size_table (void) | ||
| 46 | @@ -1431,7 +1427,7 @@ | ||
| 47 | __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table); | ||
| 48 | } | ||
| 49 | |||
| 50 | -static void __attribute__((noinline)) | ||
| 51 | +static _Unwind_Reason_Code __attribute__((noinline)) | ||
| 52 | uw_init_context_1 (struct _Unwind_Context *context, | ||
| 53 | void *outer_cfa, void *outer_ra) | ||
| 54 | { | ||
| 55 | @@ -1445,7 +1441,8 @@ | ||
| 56 | context->flags = EXTENDED_CONTEXT_BIT; | ||
| 57 | |||
| 58 | code = uw_frame_state_for (context, &fs); | ||
| 59 | - gcc_assert (code == _URC_NO_REASON); | ||
| 60 | + if (code != _URC_NO_REASON) | ||
| 61 | + return code; | ||
| 62 | |||
| 63 | #if __GTHREADS | ||
| 64 | { | ||
| 65 | @@ -1471,6 +1468,8 @@ | ||
| 66 | initialization context, then we can't see it in the given | ||
| 67 | call frame data. So have the initialization context tell us. */ | ||
| 68 | context->ra = __builtin_extract_return_addr (outer_ra); | ||
| 69 | + | ||
| 70 | + return _URC_NO_REASON; | ||
| 71 | } | ||
| 72 | |||
| 73 | static void _Unwind_DebugHook (void *, void *) | ||
| 74 | |||
| 75 | === modified file 'gcc/unwind-sjlj.c' | ||
| 76 | --- old/gcc/unwind-sjlj.c 2009-04-09 14:00:19 +0000 | ||
| 77 | +++ new/gcc/unwind-sjlj.c 2010-08-26 15:38:19 +0000 | ||
| 78 | @@ -292,10 +292,11 @@ | ||
| 79 | uw_update_context (context, fs); | ||
| 80 | } | ||
| 81 | |||
| 82 | -static inline void | ||
| 83 | +static inline _Unwind_Reason_Code | ||
| 84 | uw_init_context (struct _Unwind_Context *context) | ||
| 85 | { | ||
| 86 | context->fc = _Unwind_SjLj_GetContext (); | ||
| 87 | + return _URC_NO_REASON; | ||
| 88 | } | ||
| 89 | |||
| 90 | static void __attribute__((noreturn)) | ||
| 91 | |||
| 92 | === modified file 'gcc/unwind.inc' | ||
| 93 | --- old/gcc/unwind.inc 2009-04-09 14:00:19 +0000 | ||
| 94 | +++ new/gcc/unwind.inc 2010-08-26 15:38:19 +0000 | ||
| 95 | @@ -85,7 +85,8 @@ | ||
| 96 | _Unwind_Reason_Code code; | ||
| 97 | |||
| 98 | /* Set up this_context to describe the current stack frame. */ | ||
| 99 | - uw_init_context (&this_context); | ||
| 100 | + code = uw_init_context (&this_context); | ||
| 101 | + gcc_assert (code == _URC_NO_REASON); | ||
| 102 | cur_context = this_context; | ||
| 103 | |||
| 104 | /* Phase 1: Search. Unwind the stack, calling the personality routine | ||
| 105 | @@ -198,7 +199,8 @@ | ||
| 106 | struct _Unwind_Context this_context, cur_context; | ||
| 107 | _Unwind_Reason_Code code; | ||
| 108 | |||
| 109 | - uw_init_context (&this_context); | ||
| 110 | + code = uw_init_context (&this_context); | ||
| 111 | + gcc_assert (code == _URC_NO_REASON); | ||
| 112 | cur_context = this_context; | ||
| 113 | |||
| 114 | exc->private_1 = (_Unwind_Ptr) stop; | ||
| 115 | @@ -221,7 +223,8 @@ | ||
| 116 | struct _Unwind_Context this_context, cur_context; | ||
| 117 | _Unwind_Reason_Code code; | ||
| 118 | |||
| 119 | - uw_init_context (&this_context); | ||
| 120 | + code = uw_init_context (&this_context); | ||
| 121 | + gcc_assert (code == _URC_NO_REASON); | ||
| 122 | cur_context = this_context; | ||
| 123 | |||
| 124 | /* Choose between continuing to process _Unwind_RaiseException | ||
| 125 | @@ -251,7 +254,8 @@ | ||
| 126 | if (exc->private_1 == 0) | ||
| 127 | return _Unwind_RaiseException (exc); | ||
| 128 | |||
| 129 | - uw_init_context (&this_context); | ||
| 130 | + code = uw_init_context (&this_context); | ||
| 131 | + gcc_assert (code == _URC_NO_REASON); | ||
| 132 | cur_context = this_context; | ||
| 133 | |||
| 134 | code = _Unwind_ForcedUnwind_Phase2 (exc, &cur_context); | ||
| 135 | @@ -280,7 +284,9 @@ | ||
| 136 | struct _Unwind_Context context; | ||
| 137 | _Unwind_Reason_Code code; | ||
| 138 | |||
| 139 | - uw_init_context (&context); | ||
| 140 | + code = uw_init_context (&context); | ||
| 141 | + if (code != _URC_NO_REASON) | ||
| 142 | + return _URC_FATAL_PHASE1_ERROR; | ||
| 143 | |||
| 144 | while (1) | ||
| 145 | { | ||
| 146 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99376.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99376.patch deleted file mode 100644 index 5e402a753..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99376.patch +++ /dev/null | |||
| @@ -1,35 +0,0 @@ | |||
| 1 | 2010-08-26 Paul Brook <paul@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ 4.3/4.4: | ||
| 4 | 2007-03-30 Paul Brook <paul@codesourcery.com> | ||
| 5 | gcc/ | ||
| 6 | * calls.c (store_one_arg): Check alignment of mode used for save. | ||
| 7 | |||
| 8 | 2010-08-26 Maciej Rozycki <macro@codesourcery.com> | ||
| 9 | |||
| 10 | Merge from Sourcery G++ 4.4: | ||
| 11 | |||
| 12 | === modified file 'gcc/calls.c' | ||
| 13 | --- old/gcc/calls.c 2010-08-13 10:50:45 +0000 | ||
| 14 | +++ new/gcc/calls.c 2010-08-26 15:44:20 +0000 | ||
| 15 | @@ -4048,8 +4048,17 @@ | ||
| 16 | /* We need to make a save area. */ | ||
| 17 | unsigned int size = arg->locate.size.constant * BITS_PER_UNIT; | ||
| 18 | enum machine_mode save_mode = mode_for_size (size, MODE_INT, 1); | ||
| 19 | - rtx adr = memory_address (save_mode, XEXP (arg->stack_slot, 0)); | ||
| 20 | - rtx stack_area = gen_rtx_MEM (save_mode, adr); | ||
| 21 | + rtx adr; | ||
| 22 | + rtx stack_area; | ||
| 23 | + | ||
| 24 | + /* We can only use save_mode if the arg is sufficiently | ||
| 25 | + aligned. */ | ||
| 26 | + if (STRICT_ALIGNMENT | ||
| 27 | + && GET_MODE_ALIGNMENT (save_mode) > arg->locate.boundary) | ||
| 28 | + save_mode = BLKmode; | ||
| 29 | + | ||
| 30 | + adr = memory_address (save_mode, XEXP (arg->stack_slot, 0)); | ||
| 31 | + stack_area = gen_rtx_MEM (save_mode, adr); | ||
| 32 | |||
| 33 | if (save_mode == BLKmode) | ||
| 34 | { | ||
| 35 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99377.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99377.patch deleted file mode 100644 index d51f0874e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99377.patch +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | Issue #1510 | ||
| 2 | 2007-04-27 Paul Brook <paul@codesourcery.com> | ||
| 3 | gcc/ | ||
| 4 | * cse.c (cse_process_notes): Make sure PLUS are canonical. | ||
| 5 | |||
| 6 | 2010-08-26 Paul Brook <paul@codesourcery.com> | ||
| 7 | |||
| 8 | Merge from Sourcery G++ 4.3/4.4: | ||
| 9 | 2007-03-30 Paul Brook <paul@codesourcery.com> | ||
| 10 | gcc/ | ||
| 11 | * calls.c (store_one_arg): Check alignment of mode used for save. | ||
| 12 | |||
| 13 | === modified file 'gcc/cse.c' | ||
| 14 | --- old/gcc/cse.c 2010-01-12 20:25:10 +0000 | ||
| 15 | +++ new/gcc/cse.c 2010-08-26 15:53:20 +0000 | ||
| 16 | @@ -6061,6 +6061,11 @@ | ||
| 17 | validate_change (object, &XEXP (x, i), | ||
| 18 | cse_process_notes (XEXP (x, i), object, changed), 0); | ||
| 19 | |||
| 20 | + /* Rebuild a PLUS expression in canonical form if the first operand | ||
| 21 | + ends up as a constant. */ | ||
| 22 | + if (code == PLUS && GET_CODE (XEXP (x, 0)) == CONST_INT) | ||
| 23 | + return plus_constant (XEXP(x, 1), INTVAL (XEXP (x, 0))); | ||
| 24 | + | ||
| 25 | return x; | ||
| 26 | } | ||
| 27 | |||
| 28 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99378.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99378.patch deleted file mode 100644 index aacf19b7c..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99378.patch +++ /dev/null | |||
| @@ -1,159 +0,0 @@ | |||
| 1 | 2010-08-27 Paul Brook <paul@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * config/arm/thumb2.md (thumb_andsi_not_shiftsi_si, | ||
| 5 | thumb2_notsi_shiftsi, thumb2_notsi_shiftsi_compare0, | ||
| 6 | thumb2_not_shiftsi_compare0_scratch, thumb2_cmpsi_shiftsi, | ||
| 7 | thumb2_cmpsi_shiftsi_swp, thumb2_cmpsi_neg_shiftsi, | ||
| 8 | thumb2_arith_shiftsi, thumb2_arith_shiftsi_compare0, | ||
| 9 | thumb2_arith_shiftsi_compare0_scratch, thumb2_sub_shiftsi, | ||
| 10 | thumb2_sub_shiftsi_compare0, thumb2_sub_shiftsi_compare0_scratch): | ||
| 11 | Use const_shift_count predicate for "M" constraints. | ||
| 12 | * config/arm/predicates.md (const_shift_operand): Remove. | ||
| 13 | (const_shift_count): New. | ||
| 14 | |||
| 15 | gcc/testsuite/ | ||
| 16 | * gcc.dg/long-long-shift-1.c: New test. | ||
| 17 | |||
| 18 | 2010-08-26 Paul Brook <paul@codesourcery.com> | ||
| 19 | |||
| 20 | Merge from Sourcery G++ 4.3/4.4: | ||
| 21 | |||
| 22 | === modified file 'gcc/config/arm/predicates.md' | ||
| 23 | --- old/gcc/config/arm/predicates.md 2010-08-12 13:35:39 +0000 | ||
| 24 | +++ new/gcc/config/arm/predicates.md 2010-08-31 09:40:16 +0000 | ||
| 25 | @@ -318,10 +318,9 @@ | ||
| 26 | (and (match_code "reg,subreg,mem") | ||
| 27 | (match_operand 0 "nonimmediate_soft_df_operand")))) | ||
| 28 | |||
| 29 | -(define_predicate "const_shift_operand" | ||
| 30 | +(define_predicate "const_shift_count" | ||
| 31 | (and (match_code "const_int") | ||
| 32 | - (ior (match_operand 0 "power_of_two_operand") | ||
| 33 | - (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32")))) | ||
| 34 | + (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 32"))) | ||
| 35 | |||
| 36 | |||
| 37 | (define_special_predicate "load_multiple_operation" | ||
| 38 | |||
| 39 | === modified file 'gcc/config/arm/thumb2.md' | ||
| 40 | --- old/gcc/config/arm/thumb2.md 2010-08-13 16:00:58 +0000 | ||
| 41 | +++ new/gcc/config/arm/thumb2.md 2010-08-31 09:40:16 +0000 | ||
| 42 | @@ -55,7 +55,7 @@ | ||
| 43 | [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 44 | (and:SI (not:SI (match_operator:SI 4 "shift_operator" | ||
| 45 | [(match_operand:SI 2 "s_register_operand" "r") | ||
| 46 | - (match_operand:SI 3 "const_int_operand" "M")])) | ||
| 47 | + (match_operand:SI 3 "const_shift_count" "M")])) | ||
| 48 | (match_operand:SI 1 "s_register_operand" "r")))] | ||
| 49 | "TARGET_THUMB2" | ||
| 50 | "bic%?\\t%0, %1, %2%S4" | ||
| 51 | @@ -124,7 +124,7 @@ | ||
| 52 | [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 53 | (not:SI (match_operator:SI 3 "shift_operator" | ||
| 54 | [(match_operand:SI 1 "s_register_operand" "r") | ||
| 55 | - (match_operand:SI 2 "const_int_operand" "M")])))] | ||
| 56 | + (match_operand:SI 2 "const_shift_count" "M")])))] | ||
| 57 | "TARGET_THUMB2" | ||
| 58 | "mvn%?\\t%0, %1%S3" | ||
| 59 | [(set_attr "predicable" "yes") | ||
| 60 | @@ -136,7 +136,7 @@ | ||
| 61 | [(set (reg:CC_NOOV CC_REGNUM) | ||
| 62 | (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" | ||
| 63 | [(match_operand:SI 1 "s_register_operand" "r") | ||
| 64 | - (match_operand:SI 2 "const_int_operand" "M")])) | ||
| 65 | + (match_operand:SI 2 "const_shift_count" "M")])) | ||
| 66 | (const_int 0))) | ||
| 67 | (set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 68 | (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))] | ||
| 69 | @@ -151,7 +151,7 @@ | ||
| 70 | [(set (reg:CC_NOOV CC_REGNUM) | ||
| 71 | (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" | ||
| 72 | [(match_operand:SI 1 "s_register_operand" "r") | ||
| 73 | - (match_operand:SI 2 "const_int_operand" "M")])) | ||
| 74 | + (match_operand:SI 2 "const_shift_count" "M")])) | ||
| 75 | (const_int 0))) | ||
| 76 | (clobber (match_scratch:SI 0 "=r"))] | ||
| 77 | "TARGET_THUMB2" | ||
| 78 | @@ -328,7 +328,7 @@ | ||
| 79 | (compare:CC (match_operand:SI 0 "s_register_operand" "r") | ||
| 80 | (match_operator:SI 3 "shift_operator" | ||
| 81 | [(match_operand:SI 1 "s_register_operand" "r") | ||
| 82 | - (match_operand:SI 2 "const_int_operand" "M")])))] | ||
| 83 | + (match_operand:SI 2 "const_shift_count" "M")])))] | ||
| 84 | "TARGET_THUMB2" | ||
| 85 | "cmp%?\\t%0, %1%S3" | ||
| 86 | [(set_attr "conds" "set") | ||
| 87 | @@ -340,7 +340,7 @@ | ||
| 88 | [(set (reg:CC_SWP CC_REGNUM) | ||
| 89 | (compare:CC_SWP (match_operator:SI 3 "shift_operator" | ||
| 90 | [(match_operand:SI 1 "s_register_operand" "r") | ||
| 91 | - (match_operand:SI 2 "const_int_operand" "M")]) | ||
| 92 | + (match_operand:SI 2 "const_shift_count" "M")]) | ||
| 93 | (match_operand:SI 0 "s_register_operand" "r")))] | ||
| 94 | "TARGET_THUMB2" | ||
| 95 | "cmp%?\\t%0, %1%S3" | ||
| 96 | @@ -354,7 +354,7 @@ | ||
| 97 | (compare:CC (match_operand:SI 0 "s_register_operand" "r") | ||
| 98 | (neg:SI (match_operator:SI 3 "shift_operator" | ||
| 99 | [(match_operand:SI 1 "s_register_operand" "r") | ||
| 100 | - (match_operand:SI 2 "const_int_operand" "M")]))))] | ||
| 101 | + (match_operand:SI 2 "const_shift_count" "M")]))))] | ||
| 102 | "TARGET_THUMB2" | ||
| 103 | "cmn%?\\t%0, %1%S3" | ||
| 104 | [(set_attr "conds" "set") | ||
| 105 | @@ -466,7 +466,7 @@ | ||
| 106 | (match_operator:SI 1 "shiftable_operator" | ||
| 107 | [(match_operator:SI 3 "shift_operator" | ||
| 108 | [(match_operand:SI 4 "s_register_operand" "r") | ||
| 109 | - (match_operand:SI 5 "const_int_operand" "M")]) | ||
| 110 | + (match_operand:SI 5 "const_shift_count" "M")]) | ||
| 111 | (match_operand:SI 2 "s_register_operand" "r")]))] | ||
| 112 | "TARGET_THUMB2" | ||
| 113 | "%i1%?\\t%0, %2, %4%S3" | ||
| 114 | @@ -499,7 +499,7 @@ | ||
| 115 | (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator" | ||
| 116 | [(match_operator:SI 3 "shift_operator" | ||
| 117 | [(match_operand:SI 4 "s_register_operand" "r") | ||
| 118 | - (match_operand:SI 5 "const_int_operand" "M")]) | ||
| 119 | + (match_operand:SI 5 "const_shift_count" "M")]) | ||
| 120 | (match_operand:SI 2 "s_register_operand" "r")]) | ||
| 121 | (const_int 0))) | ||
| 122 | (set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 123 | @@ -517,7 +517,7 @@ | ||
| 124 | (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator" | ||
| 125 | [(match_operator:SI 3 "shift_operator" | ||
| 126 | [(match_operand:SI 4 "s_register_operand" "r") | ||
| 127 | - (match_operand:SI 5 "const_int_operand" "M")]) | ||
| 128 | + (match_operand:SI 5 "const_shift_count" "M")]) | ||
| 129 | (match_operand:SI 2 "s_register_operand" "r")]) | ||
| 130 | (const_int 0))) | ||
| 131 | (clobber (match_scratch:SI 0 "=r"))] | ||
| 132 | @@ -533,7 +533,7 @@ | ||
| 133 | (minus:SI (match_operand:SI 1 "s_register_operand" "r") | ||
| 134 | (match_operator:SI 2 "shift_operator" | ||
| 135 | [(match_operand:SI 3 "s_register_operand" "r") | ||
| 136 | - (match_operand:SI 4 "const_int_operand" "M")])))] | ||
| 137 | + (match_operand:SI 4 "const_shift_count" "M")])))] | ||
| 138 | "TARGET_THUMB2" | ||
| 139 | "sub%?\\t%0, %1, %3%S2" | ||
| 140 | [(set_attr "predicable" "yes") | ||
| 141 | @@ -547,7 +547,7 @@ | ||
| 142 | (minus:SI (match_operand:SI 1 "s_register_operand" "r") | ||
| 143 | (match_operator:SI 2 "shift_operator" | ||
| 144 | [(match_operand:SI 3 "s_register_operand" "r") | ||
| 145 | - (match_operand:SI 4 "const_int_operand" "M")])) | ||
| 146 | + (match_operand:SI 4 "const_shift_count" "M")])) | ||
| 147 | (const_int 0))) | ||
| 148 | (set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 149 | (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) | ||
| 150 | @@ -565,7 +565,7 @@ | ||
| 151 | (minus:SI (match_operand:SI 1 "s_register_operand" "r") | ||
| 152 | (match_operator:SI 2 "shift_operator" | ||
| 153 | [(match_operand:SI 3 "s_register_operand" "r") | ||
| 154 | - (match_operand:SI 4 "const_int_operand" "M")])) | ||
| 155 | + (match_operand:SI 4 "const_shift_count" "M")])) | ||
| 156 | (const_int 0))) | ||
| 157 | (clobber (match_scratch:SI 0 "=r"))] | ||
| 158 | "TARGET_THUMB2" | ||
| 159 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99379.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99379.patch deleted file mode 100644 index e1e89bf8a..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99379.patch +++ /dev/null | |||
| @@ -1,2011 +0,0 @@ | |||
| 1 | 2010-08-29 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-04-16 Bernd Schmidt <bernds@codesourcery.com> | ||
| 6 | |||
| 7 | PR target/41514 | ||
| 8 | gcc/ | ||
| 9 | * config/arm/arm.md (cbranchsi4_insn): Renamed from "*cbranchsi4_insn". | ||
| 10 | If the previous insn is a cbranchsi4_insn with the same arguments, | ||
| 11 | omit the compare instruction. | ||
| 12 | |||
| 13 | gcc/testsuite/ | ||
| 14 | * gcc.target/arm/thumb-comparisons.c: New test. | ||
| 15 | |||
| 16 | gcc/ | ||
| 17 | * config/arm/arm.md (addsi3_cbranch): If destination is a high | ||
| 18 | register, inputs must be low registers and we need a low register | ||
| 19 | scratch. Handle alternative 2 like alternative 3. | ||
| 20 | |||
| 21 | PR target/40603 | ||
| 22 | gcc/ | ||
| 23 | * config/arm/arm.md (cbranchqi4): New pattern. | ||
| 24 | * config/arm/predicates.md (const0_operand, | ||
| 25 | cbranchqi4_comparison_operator): New predicates. | ||
| 26 | |||
| 27 | gcc/testsuite/ | ||
| 28 | * gcc.target/arm/thumb-cbranchqi.c: New test. | ||
| 29 | |||
| 30 | 2010-04-27 Bernd Schmidt <bernds@codesourcery.com> | ||
| 31 | |||
| 32 | PR target/40657 | ||
| 33 | gcc/ | ||
| 34 | * config/arm/arm.c (thumb1_extra_regs_pushed): New function. | ||
| 35 | (thumb1_expand_prologue, thumb1_output_function_prologue): Call it | ||
| 36 | here to determine which regs to push and how much stack to reserve. | ||
| 37 | |||
| 38 | gcc/testsuite/ | ||
| 39 | * gcc.target/arm/thumb-stackframe.c: New test. | ||
| 40 | |||
| 41 | 2010-07-02 Bernd Schmidt <bernds@codesourcery.com> | ||
| 42 | |||
| 43 | PR target/42835 | ||
| 44 | gcc/ | ||
| 45 | * config/arm/arm-modes.def (CC_NOTB): New mode. | ||
| 46 | * config/arm/arm.c (get_arm_condition_code): Handle it. | ||
| 47 | * config/arm/thumb2.md (thumb2_compare_scc): Delete pattern. | ||
| 48 | * config/arm/arm.md (subsi3_compare0_c): New pattern. | ||
| 49 | (compare_scc): Now a define_and_split. Add a number of extra | ||
| 50 | splitters before it. | ||
| 51 | |||
| 52 | gcc/testsuite/ | ||
| 53 | * gcc.target/arm/pr42835.c: New test. | ||
| 54 | |||
| 55 | PR target/42172 | ||
| 56 | gcc/ | ||
| 57 | * config/arm/arm.c (thumb1_rtx_costs): Improve support for SIGN_EXTEND | ||
| 58 | and ZERO_EXTEND. | ||
| 59 | (arm_rtx_costs_1): Likewise. | ||
| 60 | (arm_size_rtx_costs): Use arm_rtx_costs_1 for these codes. | ||
| 61 | * config/arm/arm.md (is_arch6): New attribute. | ||
| 62 | (zero_extendhisi2, zero_extendqisi2, extendhisi2, | ||
| 63 | extendqisi2): Tighten the code somewhat, avoiding invalid | ||
| 64 | RTL to occur in the expander patterns. | ||
| 65 | (thumb1_zero_extendhisi2): Merge with thumb1_zero_extendhisi2_v6. | ||
| 66 | (thumb1_zero_extendhisi2_v6): Delete. | ||
| 67 | (thumb1_extendhisi2): Merge with thumb1_extendhisi2_v6. | ||
| 68 | (thumb1_extendhisi2_v6): Delete. | ||
| 69 | (thumb1_extendqisi2): Merge with thumb1_extendhisi2_v6. | ||
| 70 | (thumb1_extendqisi2_v6): Delete. | ||
| 71 | (zero_extendhisi2 for register input splitter): New. | ||
| 72 | (zero_extendqisi2 for register input splitter): New. | ||
| 73 | (thumb1_extendhisi2 for register input splitter): New. | ||
| 74 | (extendhisi2 for register input splitter): New. | ||
| 75 | (extendqisi2 for register input splitter): New. | ||
| 76 | (TARGET_THUMB1 extendqisi2 for memory input splitter): New. | ||
| 77 | (arm_zero_extendhisi2): Allow nonimmediate_operand for operand 1, | ||
| 78 | and add support for a register alternative requiring a split. | ||
| 79 | (thumb1_zero_extendqisi2): Likewise. | ||
| 80 | (arm_zero_extendqisi2): Likewise. | ||
| 81 | (arm_extendhisi2): Likewise. | ||
| 82 | (arm_extendqisi2): Likewise. | ||
| 83 | |||
| 84 | gcc/testsuite/ | ||
| 85 | * gcc.target/arm/pr42172-1.c: New test. | ||
| 86 | |||
| 87 | 2010-07-05 Bernd Schmidt <bernds@codesourcery.com> | ||
| 88 | |||
| 89 | * config/arm/arm.c (get_arm_condition_code): Remove CC_NOTBmode case. | ||
| 90 | * arm-modes.def (CC_NOTB): Don't define. | ||
| 91 | * config/arm/arm.md (arm_adddi3): Generate canonical RTL. | ||
| 92 | (adddi_sesidi_di, adddi_zesidi_di): Likewise. | ||
| 93 | (LTUGEU): New code_iterator. | ||
| 94 | (cnb, optab): New corresponding code_attrs. | ||
| 95 | (addsi3_carryin_<optab>): Renamed from addsi3_carryin. Change pattern | ||
| 96 | to canonical form. Operands 1 and 2 are commutative. Parametrize | ||
| 97 | using LTUGEU. | ||
| 98 | (addsi3_carryin_shift_<optab>): Likewise. | ||
| 99 | (addsi3_carryin_alt2_<optab>): Renamed from addsi3_carryin_alt2. | ||
| 100 | Operands 1 and 2 are commutative. Parametrize using LTUGEU. | ||
| 101 | (addsi3_carryin_alt1, addsi3_carryin_alt3): Remove. | ||
| 102 | (subsi3_compare): Renamed from subsi3_compare0_c. Change CC_NOTB to | ||
| 103 | CC. | ||
| 104 | (arm_subsi3_insn): Allow constants for operand 0. | ||
| 105 | (compare_scc peephole for eq case): New. | ||
| 106 | (compare_scc splitters): Change CC_NOTB to CC. | ||
| 107 | |||
| 108 | 2010-07-09 Bernd Schmidt <bernds@codesourcery.com> | ||
| 109 | |||
| 110 | PR target/40657 | ||
| 111 | gcc/ | ||
| 112 | * config/arm/arm.c (thumb1_extra_regs_pushed): New arg FOR_PROLOGUE. | ||
| 113 | All callers changed. | ||
| 114 | Handle the case when we're called for the epilogue. | ||
| 115 | (thumb_unexpanded_epilogue): Use it. | ||
| 116 | (thumb1_expand_epilogue): Likewise. | ||
| 117 | |||
| 118 | gcc/testsuite/ | ||
| 119 | * gcc.target/arm/pr40657-1.c: New test. | ||
| 120 | * gcc.target/arm/pr40657-2.c: New test. | ||
| 121 | * gcc.c-torture/execute/pr40657.c: New test. | ||
| 122 | |||
| 123 | gcc/ | ||
| 124 | * config/arm/arm.md (addsi3_cbranch): Switch alternatives 0 and 1. | ||
| 125 | |||
| 126 | * config/arm/arm.md (Thumb-1 ldrsb peephole): New. | ||
| 127 | |||
| 128 | * config/arm/arm.md (cbranchqi4): Fix array size. | ||
| 129 | (addsi3_cbranch): Also andle alternative 2 like alternative 3 when | ||
| 130 | calculating length. | ||
| 131 | |||
| 132 | 2010-08-27 Paul Brook <paul@codesourcery.com> | ||
| 133 | |||
| 134 | gcc/ | ||
| 135 | |||
| 136 | === modified file 'gcc/config/arm/arm-modes.def' | ||
| 137 | --- old/gcc/config/arm/arm-modes.def 2010-07-29 16:58:56 +0000 | ||
| 138 | +++ new/gcc/config/arm/arm-modes.def 2010-08-31 10:00:27 +0000 | ||
| 139 | @@ -34,6 +34,8 @@ | ||
| 140 | CCFPmode should be used with floating equalities. | ||
| 141 | CC_NOOVmode should be used with SImode integer equalities. | ||
| 142 | CC_Zmode should be used if only the Z flag is set correctly | ||
| 143 | + CC_Cmode should be used if only the C flag is set correctly, after an | ||
| 144 | + addition. | ||
| 145 | CC_Nmode should be used if only the N (sign) flag is set correctly | ||
| 146 | CC_CZmode should be used if only the C and Z flags are correct | ||
| 147 | (used for DImode unsigned comparisons). | ||
| 148 | |||
| 149 | === modified file 'gcc/config/arm/arm.c' | ||
| 150 | --- old/gcc/config/arm/arm.c 2010-08-25 16:22:17 +0000 | ||
| 151 | +++ new/gcc/config/arm/arm.c 2010-08-31 10:00:27 +0000 | ||
| 152 | @@ -6443,6 +6443,7 @@ | ||
| 153 | thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) | ||
| 154 | { | ||
| 155 | enum machine_mode mode = GET_MODE (x); | ||
| 156 | + int total; | ||
| 157 | |||
| 158 | switch (code) | ||
| 159 | { | ||
| 160 | @@ -6545,24 +6546,20 @@ | ||
| 161 | return 14; | ||
| 162 | return 2; | ||
| 163 | |||
| 164 | + case SIGN_EXTEND: | ||
| 165 | case ZERO_EXTEND: | ||
| 166 | - /* XXX still guessing. */ | ||
| 167 | - switch (GET_MODE (XEXP (x, 0))) | ||
| 168 | - { | ||
| 169 | - case QImode: | ||
| 170 | - return (1 + (mode == DImode ? 4 : 0) | ||
| 171 | - + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | ||
| 172 | - | ||
| 173 | - case HImode: | ||
| 174 | - return (4 + (mode == DImode ? 4 : 0) | ||
| 175 | - + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | ||
| 176 | - | ||
| 177 | - case SImode: | ||
| 178 | - return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | ||
| 179 | - | ||
| 180 | - default: | ||
| 181 | - return 99; | ||
| 182 | - } | ||
| 183 | + total = mode == DImode ? COSTS_N_INSNS (1) : 0; | ||
| 184 | + total += thumb1_rtx_costs (XEXP (x, 0), GET_CODE (XEXP (x, 0)), code); | ||
| 185 | + | ||
| 186 | + if (mode == SImode) | ||
| 187 | + return total; | ||
| 188 | + | ||
| 189 | + if (arm_arch6) | ||
| 190 | + return total + COSTS_N_INSNS (1); | ||
| 191 | + | ||
| 192 | + /* Assume a two-shift sequence. Increase the cost slightly so | ||
| 193 | + we prefer actual shifts over an extend operation. */ | ||
| 194 | + return total + 1 + COSTS_N_INSNS (2); | ||
| 195 | |||
| 196 | default: | ||
| 197 | return 99; | ||
| 198 | @@ -7046,44 +7043,39 @@ | ||
| 199 | return false; | ||
| 200 | |||
| 201 | case SIGN_EXTEND: | ||
| 202 | - if (GET_MODE_CLASS (mode) == MODE_INT) | ||
| 203 | - { | ||
| 204 | - *total = 0; | ||
| 205 | - if (mode == DImode) | ||
| 206 | - *total += COSTS_N_INSNS (1); | ||
| 207 | - | ||
| 208 | - if (GET_MODE (XEXP (x, 0)) != SImode) | ||
| 209 | - { | ||
| 210 | - if (arm_arch6) | ||
| 211 | - { | ||
| 212 | - if (GET_CODE (XEXP (x, 0)) != MEM) | ||
| 213 | - *total += COSTS_N_INSNS (1); | ||
| 214 | - } | ||
| 215 | - else if (!arm_arch4 || GET_CODE (XEXP (x, 0)) != MEM) | ||
| 216 | - *total += COSTS_N_INSNS (2); | ||
| 217 | - } | ||
| 218 | - | ||
| 219 | - return false; | ||
| 220 | - } | ||
| 221 | - | ||
| 222 | - /* Fall through */ | ||
| 223 | case ZERO_EXTEND: | ||
| 224 | *total = 0; | ||
| 225 | if (GET_MODE_CLASS (mode) == MODE_INT) | ||
| 226 | { | ||
| 227 | + rtx op = XEXP (x, 0); | ||
| 228 | + enum machine_mode opmode = GET_MODE (op); | ||
| 229 | + | ||
| 230 | if (mode == DImode) | ||
| 231 | *total += COSTS_N_INSNS (1); | ||
| 232 | |||
| 233 | - if (GET_MODE (XEXP (x, 0)) != SImode) | ||
| 234 | + if (opmode != SImode) | ||
| 235 | { | ||
| 236 | - if (arm_arch6) | ||
| 237 | + if (MEM_P (op)) | ||
| 238 | { | ||
| 239 | - if (GET_CODE (XEXP (x, 0)) != MEM) | ||
| 240 | - *total += COSTS_N_INSNS (1); | ||
| 241 | + /* If !arm_arch4, we use one of the extendhisi2_mem | ||
| 242 | + or movhi_bytes patterns for HImode. For a QImode | ||
| 243 | + sign extension, we first zero-extend from memory | ||
| 244 | + and then perform a shift sequence. */ | ||
| 245 | + if (!arm_arch4 && (opmode != QImode || code == SIGN_EXTEND)) | ||
| 246 | + *total += COSTS_N_INSNS (2); | ||
| 247 | } | ||
| 248 | - else if (!arm_arch4 || GET_CODE (XEXP (x, 0)) != MEM) | ||
| 249 | - *total += COSTS_N_INSNS (GET_MODE (XEXP (x, 0)) == QImode ? | ||
| 250 | - 1 : 2); | ||
| 251 | + else if (arm_arch6) | ||
| 252 | + *total += COSTS_N_INSNS (1); | ||
| 253 | + | ||
| 254 | + /* We don't have the necessary insn, so we need to perform some | ||
| 255 | + other operation. */ | ||
| 256 | + else if (TARGET_ARM && code == ZERO_EXTEND && mode == QImode) | ||
| 257 | + /* An and with constant 255. */ | ||
| 258 | + *total += COSTS_N_INSNS (1); | ||
| 259 | + else | ||
| 260 | + /* A shift sequence. Increase costs slightly to avoid | ||
| 261 | + combining two shifts into an extend operation. */ | ||
| 262 | + *total += COSTS_N_INSNS (2) + 1; | ||
| 263 | } | ||
| 264 | |||
| 265 | return false; | ||
| 266 | @@ -7333,41 +7325,8 @@ | ||
| 267 | return false; | ||
| 268 | |||
| 269 | case SIGN_EXTEND: | ||
| 270 | - *total = 0; | ||
| 271 | - if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4) | ||
| 272 | - { | ||
| 273 | - if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) | ||
| 274 | - *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); | ||
| 275 | - } | ||
| 276 | - if (mode == DImode) | ||
| 277 | - *total += COSTS_N_INSNS (1); | ||
| 278 | - return false; | ||
| 279 | - | ||
| 280 | case ZERO_EXTEND: | ||
| 281 | - *total = 0; | ||
| 282 | - if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) | ||
| 283 | - { | ||
| 284 | - switch (GET_MODE (XEXP (x, 0))) | ||
| 285 | - { | ||
| 286 | - case QImode: | ||
| 287 | - *total += COSTS_N_INSNS (1); | ||
| 288 | - break; | ||
| 289 | - | ||
| 290 | - case HImode: | ||
| 291 | - *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); | ||
| 292 | - | ||
| 293 | - case SImode: | ||
| 294 | - break; | ||
| 295 | - | ||
| 296 | - default: | ||
| 297 | - *total += COSTS_N_INSNS (2); | ||
| 298 | - } | ||
| 299 | - } | ||
| 300 | - | ||
| 301 | - if (mode == DImode) | ||
| 302 | - *total += COSTS_N_INSNS (1); | ||
| 303 | - | ||
| 304 | - return false; | ||
| 305 | + return arm_rtx_costs_1 (x, outer_code, total, 0); | ||
| 306 | |||
| 307 | case CONST_INT: | ||
| 308 | if (const_ok_for_arm (INTVAL (x))) | ||
| 309 | @@ -16898,11 +16857,11 @@ | ||
| 310 | |||
| 311 | case CC_Cmode: | ||
| 312 | switch (comp_code) | ||
| 313 | - { | ||
| 314 | - case LTU: return ARM_CS; | ||
| 315 | - case GEU: return ARM_CC; | ||
| 316 | - default: gcc_unreachable (); | ||
| 317 | - } | ||
| 318 | + { | ||
| 319 | + case LTU: return ARM_CS; | ||
| 320 | + case GEU: return ARM_CC; | ||
| 321 | + default: gcc_unreachable (); | ||
| 322 | + } | ||
| 323 | |||
| 324 | case CC_CZmode: | ||
| 325 | switch (comp_code) | ||
| 326 | @@ -20127,6 +20086,81 @@ | ||
| 327 | #endif | ||
| 328 | } | ||
| 329 | |||
| 330 | +/* Given the stack offsets and register mask in OFFSETS, decide how | ||
| 331 | + many additional registers to push instead of subtracting a constant | ||
| 332 | + from SP. For epilogues the principle is the same except we use pop. | ||
| 333 | + FOR_PROLOGUE indicates which we're generating. */ | ||
| 334 | +static int | ||
| 335 | +thumb1_extra_regs_pushed (arm_stack_offsets *offsets, bool for_prologue) | ||
| 336 | +{ | ||
| 337 | + HOST_WIDE_INT amount; | ||
| 338 | + unsigned long live_regs_mask = offsets->saved_regs_mask; | ||
| 339 | + /* Extract a mask of the ones we can give to the Thumb's push/pop | ||
| 340 | + instruction. */ | ||
| 341 | + unsigned long l_mask = live_regs_mask & (for_prologue ? 0x40ff : 0xff); | ||
| 342 | + /* Then count how many other high registers will need to be pushed. */ | ||
| 343 | + unsigned long high_regs_pushed = bit_count (live_regs_mask & 0x0f00); | ||
| 344 | + int n_free, reg_base; | ||
| 345 | + | ||
| 346 | + if (!for_prologue && frame_pointer_needed) | ||
| 347 | + amount = offsets->locals_base - offsets->saved_regs; | ||
| 348 | + else | ||
| 349 | + amount = offsets->outgoing_args - offsets->saved_regs; | ||
| 350 | + | ||
| 351 | + /* If the stack frame size is 512 exactly, we can save one load | ||
| 352 | + instruction, which should make this a win even when optimizing | ||
| 353 | + for speed. */ | ||
| 354 | + if (!optimize_size && amount != 512) | ||
| 355 | + return 0; | ||
| 356 | + | ||
| 357 | + /* Can't do this if there are high registers to push. */ | ||
| 358 | + if (high_regs_pushed != 0) | ||
| 359 | + return 0; | ||
| 360 | + | ||
| 361 | + /* Shouldn't do it in the prologue if no registers would normally | ||
| 362 | + be pushed at all. In the epilogue, also allow it if we'll have | ||
| 363 | + a pop insn for the PC. */ | ||
| 364 | + if (l_mask == 0 | ||
| 365 | + && (for_prologue | ||
| 366 | + || TARGET_BACKTRACE | ||
| 367 | + || (live_regs_mask & 1 << LR_REGNUM) == 0 | ||
| 368 | + || TARGET_INTERWORK | ||
| 369 | + || crtl->args.pretend_args_size != 0)) | ||
| 370 | + return 0; | ||
| 371 | + | ||
| 372 | + /* Don't do this if thumb_expand_prologue wants to emit instructions | ||
| 373 | + between the push and the stack frame allocation. */ | ||
| 374 | + if (for_prologue | ||
| 375 | + && ((flag_pic && arm_pic_register != INVALID_REGNUM) | ||
| 376 | + || (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0))) | ||
| 377 | + return 0; | ||
| 378 | + | ||
| 379 | + reg_base = 0; | ||
| 380 | + n_free = 0; | ||
| 381 | + if (!for_prologue) | ||
| 382 | + { | ||
| 383 | + reg_base = arm_size_return_regs () / UNITS_PER_WORD; | ||
| 384 | + live_regs_mask >>= reg_base; | ||
| 385 | + } | ||
| 386 | + | ||
| 387 | + while (reg_base + n_free < 8 && !(live_regs_mask & 1) | ||
| 388 | + && (for_prologue || call_used_regs[reg_base + n_free])) | ||
| 389 | + { | ||
| 390 | + live_regs_mask >>= 1; | ||
| 391 | + n_free++; | ||
| 392 | + } | ||
| 393 | + | ||
| 394 | + if (n_free == 0) | ||
| 395 | + return 0; | ||
| 396 | + gcc_assert (amount / 4 * 4 == amount); | ||
| 397 | + | ||
| 398 | + if (amount >= 512 && (amount - n_free * 4) < 512) | ||
| 399 | + return (amount - 508) / 4; | ||
| 400 | + if (amount <= n_free * 4) | ||
| 401 | + return amount / 4; | ||
| 402 | + return 0; | ||
| 403 | +} | ||
| 404 | + | ||
| 405 | /* The bits which aren't usefully expanded as rtl. */ | ||
| 406 | const char * | ||
| 407 | thumb_unexpanded_epilogue (void) | ||
| 408 | @@ -20135,6 +20169,7 @@ | ||
| 409 | int regno; | ||
| 410 | unsigned long live_regs_mask = 0; | ||
| 411 | int high_regs_pushed = 0; | ||
| 412 | + int extra_pop; | ||
| 413 | int had_to_push_lr; | ||
| 414 | int size; | ||
| 415 | |||
| 416 | @@ -20154,6 +20189,13 @@ | ||
| 417 | the register is used to hold a return value. */ | ||
| 418 | size = arm_size_return_regs (); | ||
| 419 | |||
| 420 | + extra_pop = thumb1_extra_regs_pushed (offsets, false); | ||
| 421 | + if (extra_pop > 0) | ||
| 422 | + { | ||
| 423 | + unsigned long extra_mask = (1 << extra_pop) - 1; | ||
| 424 | + live_regs_mask |= extra_mask << (size / UNITS_PER_WORD); | ||
| 425 | + } | ||
| 426 | + | ||
| 427 | /* The prolog may have pushed some high registers to use as | ||
| 428 | work registers. e.g. the testsuite file: | ||
| 429 | gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c | ||
| 430 | @@ -20237,7 +20279,9 @@ | ||
| 431 | live_regs_mask); | ||
| 432 | |||
| 433 | /* We have either just popped the return address into the | ||
| 434 | - PC or it is was kept in LR for the entire function. */ | ||
| 435 | + PC or it is was kept in LR for the entire function. | ||
| 436 | + Note that thumb_pushpop has already called thumb_exit if the | ||
| 437 | + PC was in the list. */ | ||
| 438 | if (!had_to_push_lr) | ||
| 439 | thumb_exit (asm_out_file, LR_REGNUM); | ||
| 440 | } | ||
| 441 | @@ -20419,6 +20463,7 @@ | ||
| 442 | stack_pointer_rtx); | ||
| 443 | |||
| 444 | amount = offsets->outgoing_args - offsets->saved_regs; | ||
| 445 | + amount -= 4 * thumb1_extra_regs_pushed (offsets, true); | ||
| 446 | if (amount) | ||
| 447 | { | ||
| 448 | if (amount < 512) | ||
| 449 | @@ -20503,6 +20548,7 @@ | ||
| 450 | emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); | ||
| 451 | amount = offsets->locals_base - offsets->saved_regs; | ||
| 452 | } | ||
| 453 | + amount -= 4 * thumb1_extra_regs_pushed (offsets, false); | ||
| 454 | |||
| 455 | gcc_assert (amount >= 0); | ||
| 456 | if (amount) | ||
| 457 | @@ -20723,7 +20769,11 @@ | ||
| 458 | register. */ | ||
| 459 | else if ((l_mask & 0xff) != 0 | ||
| 460 | || (high_regs_pushed == 0 && l_mask)) | ||
| 461 | - thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); | ||
| 462 | + { | ||
| 463 | + unsigned long mask = l_mask; | ||
| 464 | + mask |= (1 << thumb1_extra_regs_pushed (offsets, true)) - 1; | ||
| 465 | + thumb_pushpop (f, mask, 1, &cfa_offset, mask); | ||
| 466 | + } | ||
| 467 | |||
| 468 | if (high_regs_pushed) | ||
| 469 | { | ||
| 470 | |||
| 471 | === modified file 'gcc/config/arm/arm.md' | ||
| 472 | --- old/gcc/config/arm/arm.md 2010-08-25 16:22:17 +0000 | ||
| 473 | +++ new/gcc/config/arm/arm.md 2010-08-31 10:00:27 +0000 | ||
| 474 | @@ -150,6 +150,9 @@ | ||
| 475 | ; patterns that share the same RTL in both ARM and Thumb code. | ||
| 476 | (define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code"))) | ||
| 477 | |||
| 478 | +; IS_ARCH6 is set to 'yes' when we are generating code form ARMv6. | ||
| 479 | +(define_attr "is_arch6" "no,yes" (const (symbol_ref "arm_arch6"))) | ||
| 480 | + | ||
| 481 | ;; Operand number of an input operand that is shifted. Zero if the | ||
| 482 | ;; given instruction does not shift one of its input operands. | ||
| 483 | (define_attr "shift" "" (const_int 0)) | ||
| 484 | @@ -515,8 +518,8 @@ | ||
| 485 | (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) | ||
| 486 | (match_dup 1))) | ||
| 487 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) | ||
| 488 | - (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) | ||
| 489 | - (plus:SI (match_dup 4) (match_dup 5))))] | ||
| 490 | + (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) | ||
| 491 | + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] | ||
| 492 | " | ||
| 493 | { | ||
| 494 | operands[3] = gen_highpart (SImode, operands[0]); | ||
| 495 | @@ -543,10 +546,10 @@ | ||
| 496 | (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) | ||
| 497 | (match_dup 1))) | ||
| 498 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) | ||
| 499 | - (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) | ||
| 500 | - (plus:SI (ashiftrt:SI (match_dup 2) | ||
| 501 | + (set (match_dup 3) (plus:SI (plus:SI (ashiftrt:SI (match_dup 2) | ||
| 502 | (const_int 31)) | ||
| 503 | - (match_dup 4))))] | ||
| 504 | + (match_dup 4)) | ||
| 505 | + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] | ||
| 506 | " | ||
| 507 | { | ||
| 508 | operands[3] = gen_highpart (SImode, operands[0]); | ||
| 509 | @@ -572,8 +575,8 @@ | ||
| 510 | (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) | ||
| 511 | (match_dup 1))) | ||
| 512 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) | ||
| 513 | - (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) | ||
| 514 | - (plus:SI (match_dup 4) (const_int 0))))] | ||
| 515 | + (set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (const_int 0)) | ||
| 516 | + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] | ||
| 517 | " | ||
| 518 | { | ||
| 519 | operands[3] = gen_highpart (SImode, operands[0]); | ||
| 520 | @@ -861,24 +864,38 @@ | ||
| 521 | [(set_attr "conds" "set")] | ||
| 522 | ) | ||
| 523 | |||
| 524 | -(define_insn "*addsi3_carryin" | ||
| 525 | - [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 526 | - (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) | ||
| 527 | - (plus:SI (match_operand:SI 1 "s_register_operand" "r") | ||
| 528 | - (match_operand:SI 2 "arm_rhs_operand" "rI"))))] | ||
| 529 | - "TARGET_32BIT" | ||
| 530 | - "adc%?\\t%0, %1, %2" | ||
| 531 | - [(set_attr "conds" "use")] | ||
| 532 | -) | ||
| 533 | - | ||
| 534 | -(define_insn "*addsi3_carryin_shift" | ||
| 535 | - [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 536 | - (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) | ||
| 537 | - (plus:SI | ||
| 538 | - (match_operator:SI 2 "shift_operator" | ||
| 539 | - [(match_operand:SI 3 "s_register_operand" "r") | ||
| 540 | - (match_operand:SI 4 "reg_or_int_operand" "rM")]) | ||
| 541 | - (match_operand:SI 1 "s_register_operand" "r"))))] | ||
| 542 | +(define_code_iterator LTUGEU [ltu geu]) | ||
| 543 | +(define_code_attr cnb [(ltu "CC_C") (geu "CC")]) | ||
| 544 | +(define_code_attr optab [(ltu "ltu") (geu "geu")]) | ||
| 545 | + | ||
| 546 | +(define_insn "*addsi3_carryin_<optab>" | ||
| 547 | + [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 548 | + (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r") | ||
| 549 | + (match_operand:SI 2 "arm_rhs_operand" "rI")) | ||
| 550 | + (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))] | ||
| 551 | + "TARGET_32BIT" | ||
| 552 | + "adc%?\\t%0, %1, %2" | ||
| 553 | + [(set_attr "conds" "use")] | ||
| 554 | +) | ||
| 555 | + | ||
| 556 | +(define_insn "*addsi3_carryin_alt2_<optab>" | ||
| 557 | + [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 558 | + (plus:SI (plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0)) | ||
| 559 | + (match_operand:SI 1 "s_register_operand" "%r")) | ||
| 560 | + (match_operand:SI 2 "arm_rhs_operand" "rI")))] | ||
| 561 | + "TARGET_32BIT" | ||
| 562 | + "adc%?\\t%0, %1, %2" | ||
| 563 | + [(set_attr "conds" "use")] | ||
| 564 | +) | ||
| 565 | + | ||
| 566 | +(define_insn "*addsi3_carryin_shift_<optab>" | ||
| 567 | + [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 568 | + (plus:SI (plus:SI | ||
| 569 | + (match_operator:SI 2 "shift_operator" | ||
| 570 | + [(match_operand:SI 3 "s_register_operand" "r") | ||
| 571 | + (match_operand:SI 4 "reg_or_int_operand" "rM")]) | ||
| 572 | + (match_operand:SI 1 "s_register_operand" "r")) | ||
| 573 | + (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))] | ||
| 574 | "TARGET_32BIT" | ||
| 575 | "adc%?\\t%0, %1, %3%S2" | ||
| 576 | [(set_attr "conds" "use") | ||
| 577 | @@ -887,36 +904,6 @@ | ||
| 578 | (const_string "alu_shift_reg")))] | ||
| 579 | ) | ||
| 580 | |||
| 581 | -(define_insn "*addsi3_carryin_alt1" | ||
| 582 | - [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 583 | - (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") | ||
| 584 | - (match_operand:SI 2 "arm_rhs_operand" "rI")) | ||
| 585 | - (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] | ||
| 586 | - "TARGET_32BIT" | ||
| 587 | - "adc%?\\t%0, %1, %2" | ||
| 588 | - [(set_attr "conds" "use")] | ||
| 589 | -) | ||
| 590 | - | ||
| 591 | -(define_insn "*addsi3_carryin_alt2" | ||
| 592 | - [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 593 | - (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) | ||
| 594 | - (match_operand:SI 1 "s_register_operand" "r")) | ||
| 595 | - (match_operand:SI 2 "arm_rhs_operand" "rI")))] | ||
| 596 | - "TARGET_32BIT" | ||
| 597 | - "adc%?\\t%0, %1, %2" | ||
| 598 | - [(set_attr "conds" "use")] | ||
| 599 | -) | ||
| 600 | - | ||
| 601 | -(define_insn "*addsi3_carryin_alt3" | ||
| 602 | - [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 603 | - (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) | ||
| 604 | - (match_operand:SI 2 "arm_rhs_operand" "rI")) | ||
| 605 | - (match_operand:SI 1 "s_register_operand" "r")))] | ||
| 606 | - "TARGET_32BIT" | ||
| 607 | - "adc%?\\t%0, %1, %2" | ||
| 608 | - [(set_attr "conds" "use")] | ||
| 609 | -) | ||
| 610 | - | ||
| 611 | (define_expand "incscc" | ||
| 612 | [(set (match_operand:SI 0 "s_register_operand" "=r,r") | ||
| 613 | (plus:SI (match_operator:SI 2 "arm_comparison_operator" | ||
| 614 | @@ -1116,24 +1103,27 @@ | ||
| 615 | |||
| 616 | ; ??? Check Thumb-2 split length | ||
| 617 | (define_insn_and_split "*arm_subsi3_insn" | ||
| 618 | - [(set (match_operand:SI 0 "s_register_operand" "=r,rk,r") | ||
| 619 | - (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,!k,?n") | ||
| 620 | - (match_operand:SI 2 "s_register_operand" "r, r, r")))] | ||
| 621 | + [(set (match_operand:SI 0 "s_register_operand" "=r,r,rk,r,r") | ||
| 622 | + (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,!k,?n,r") | ||
| 623 | + (match_operand:SI 2 "reg_or_int_operand" "r,rI, r, r,?n")))] | ||
| 624 | "TARGET_32BIT" | ||
| 625 | "@ | ||
| 626 | rsb%?\\t%0, %2, %1 | ||
| 627 | sub%?\\t%0, %1, %2 | ||
| 628 | + sub%?\\t%0, %1, %2 | ||
| 629 | + # | ||
| 630 | #" | ||
| 631 | - "TARGET_32BIT | ||
| 632 | - && GET_CODE (operands[1]) == CONST_INT | ||
| 633 | - && !const_ok_for_arm (INTVAL (operands[1]))" | ||
| 634 | + "&& ((GET_CODE (operands[1]) == CONST_INT | ||
| 635 | + && !const_ok_for_arm (INTVAL (operands[1]))) | ||
| 636 | + || (GET_CODE (operands[2]) == CONST_INT | ||
| 637 | + && !const_ok_for_arm (INTVAL (operands[2]))))" | ||
| 638 | [(clobber (const_int 0))] | ||
| 639 | " | ||
| 640 | arm_split_constant (MINUS, SImode, curr_insn, | ||
| 641 | INTVAL (operands[1]), operands[0], operands[2], 0); | ||
| 642 | DONE; | ||
| 643 | " | ||
| 644 | - [(set_attr "length" "4,4,16") | ||
| 645 | + [(set_attr "length" "4,4,4,16,16") | ||
| 646 | (set_attr "predicable" "yes")] | ||
| 647 | ) | ||
| 648 | |||
| 649 | @@ -1165,6 +1155,19 @@ | ||
| 650 | [(set_attr "conds" "set")] | ||
| 651 | ) | ||
| 652 | |||
| 653 | +(define_insn "*subsi3_compare" | ||
| 654 | + [(set (reg:CC CC_REGNUM) | ||
| 655 | + (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,I") | ||
| 656 | + (match_operand:SI 2 "arm_rhs_operand" "rI,r"))) | ||
| 657 | + (set (match_operand:SI 0 "s_register_operand" "=r,r") | ||
| 658 | + (minus:SI (match_dup 1) (match_dup 2)))] | ||
| 659 | + "TARGET_32BIT" | ||
| 660 | + "@ | ||
| 661 | + sub%.\\t%0, %1, %2 | ||
| 662 | + rsb%.\\t%0, %2, %1" | ||
| 663 | + [(set_attr "conds" "set")] | ||
| 664 | +) | ||
| 665 | + | ||
| 666 | (define_expand "decscc" | ||
| 667 | [(set (match_operand:SI 0 "s_register_operand" "=r,r") | ||
| 668 | (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") | ||
| 669 | @@ -4050,93 +4053,46 @@ | ||
| 670 | ) | ||
| 671 | |||
| 672 | (define_expand "zero_extendhisi2" | ||
| 673 | - [(set (match_dup 2) | ||
| 674 | - (ashift:SI (match_operand:HI 1 "nonimmediate_operand" "") | ||
| 675 | - (const_int 16))) | ||
| 676 | - (set (match_operand:SI 0 "s_register_operand" "") | ||
| 677 | - (lshiftrt:SI (match_dup 2) (const_int 16)))] | ||
| 678 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 679 | + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] | ||
| 680 | "TARGET_EITHER" | ||
| 681 | - " | ||
| 682 | - { | ||
| 683 | - if ((TARGET_THUMB1 || arm_arch4) && GET_CODE (operands[1]) == MEM) | ||
| 684 | - { | ||
| 685 | - emit_insn (gen_rtx_SET (VOIDmode, operands[0], | ||
| 686 | - gen_rtx_ZERO_EXTEND (SImode, operands[1]))); | ||
| 687 | - DONE; | ||
| 688 | - } | ||
| 689 | - | ||
| 690 | - if (TARGET_ARM && GET_CODE (operands[1]) == MEM) | ||
| 691 | - { | ||
| 692 | - emit_insn (gen_movhi_bytes (operands[0], operands[1])); | ||
| 693 | - DONE; | ||
| 694 | - } | ||
| 695 | - | ||
| 696 | - if (!s_register_operand (operands[1], HImode)) | ||
| 697 | - operands[1] = copy_to_mode_reg (HImode, operands[1]); | ||
| 698 | - | ||
| 699 | - if (arm_arch6) | ||
| 700 | - { | ||
| 701 | - emit_insn (gen_rtx_SET (VOIDmode, operands[0], | ||
| 702 | - gen_rtx_ZERO_EXTEND (SImode, operands[1]))); | ||
| 703 | - DONE; | ||
| 704 | - } | ||
| 705 | - | ||
| 706 | - operands[1] = gen_lowpart (SImode, operands[1]); | ||
| 707 | - operands[2] = gen_reg_rtx (SImode); | ||
| 708 | - }" | ||
| 709 | -) | ||
| 710 | +{ | ||
| 711 | + if (TARGET_ARM && !arm_arch4 && MEM_P (operands[1])) | ||
| 712 | + { | ||
| 713 | + emit_insn (gen_movhi_bytes (operands[0], operands[1])); | ||
| 714 | + DONE; | ||
| 715 | + } | ||
| 716 | + if (!arm_arch6 && !MEM_P (operands[1])) | ||
| 717 | + { | ||
| 718 | + rtx t = gen_lowpart (SImode, operands[1]); | ||
| 719 | + rtx tmp = gen_reg_rtx (SImode); | ||
| 720 | + emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16))); | ||
| 721 | + emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (16))); | ||
| 722 | + DONE; | ||
| 723 | + } | ||
| 724 | +}) | ||
| 725 | + | ||
| 726 | +(define_split | ||
| 727 | + [(set (match_operand:SI 0 "register_operand" "") | ||
| 728 | + (zero_extend:SI (match_operand:HI 1 "register_operand" "l,m")))] | ||
| 729 | + "!TARGET_THUMB2 && !arm_arch6" | ||
| 730 | + [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) | ||
| 731 | + (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))] | ||
| 732 | +{ | ||
| 733 | + operands[2] = gen_lowpart (SImode, operands[1]); | ||
| 734 | +}) | ||
| 735 | |||
| 736 | (define_insn "*thumb1_zero_extendhisi2" | ||
| 737 | - [(set (match_operand:SI 0 "register_operand" "=l") | ||
| 738 | - (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] | ||
| 739 | - "TARGET_THUMB1 && !arm_arch6" | ||
| 740 | - "* | ||
| 741 | - rtx mem = XEXP (operands[1], 0); | ||
| 742 | - | ||
| 743 | - if (GET_CODE (mem) == CONST) | ||
| 744 | - mem = XEXP (mem, 0); | ||
| 745 | - | ||
| 746 | - if (GET_CODE (mem) == LABEL_REF) | ||
| 747 | - return \"ldr\\t%0, %1\"; | ||
| 748 | - | ||
| 749 | - if (GET_CODE (mem) == PLUS) | ||
| 750 | - { | ||
| 751 | - rtx a = XEXP (mem, 0); | ||
| 752 | - rtx b = XEXP (mem, 1); | ||
| 753 | - | ||
| 754 | - /* This can happen due to bugs in reload. */ | ||
| 755 | - if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM) | ||
| 756 | - { | ||
| 757 | - rtx ops[2]; | ||
| 758 | - ops[0] = operands[0]; | ||
| 759 | - ops[1] = a; | ||
| 760 | - | ||
| 761 | - output_asm_insn (\"mov %0, %1\", ops); | ||
| 762 | - | ||
| 763 | - XEXP (mem, 0) = operands[0]; | ||
| 764 | - } | ||
| 765 | - | ||
| 766 | - else if ( GET_CODE (a) == LABEL_REF | ||
| 767 | - && GET_CODE (b) == CONST_INT) | ||
| 768 | - return \"ldr\\t%0, %1\"; | ||
| 769 | - } | ||
| 770 | - | ||
| 771 | - return \"ldrh\\t%0, %1\"; | ||
| 772 | - " | ||
| 773 | - [(set_attr "length" "4") | ||
| 774 | - (set_attr "type" "load_byte") | ||
| 775 | - (set_attr "pool_range" "60")] | ||
| 776 | -) | ||
| 777 | - | ||
| 778 | -(define_insn "*thumb1_zero_extendhisi2_v6" | ||
| 779 | [(set (match_operand:SI 0 "register_operand" "=l,l") | ||
| 780 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))] | ||
| 781 | - "TARGET_THUMB1 && arm_arch6" | ||
| 782 | + "TARGET_THUMB1" | ||
| 783 | "* | ||
| 784 | rtx mem; | ||
| 785 | |||
| 786 | - if (which_alternative == 0) | ||
| 787 | + if (which_alternative == 0 && arm_arch6) | ||
| 788 | return \"uxth\\t%0, %1\"; | ||
| 789 | + if (which_alternative == 0) | ||
| 790 | + return \"#\"; | ||
| 791 | |||
| 792 | mem = XEXP (operands[1], 0); | ||
| 793 | |||
| 794 | @@ -4170,20 +4126,25 @@ | ||
| 795 | |||
| 796 | return \"ldrh\\t%0, %1\"; | ||
| 797 | " | ||
| 798 | - [(set_attr "length" "2,4") | ||
| 799 | + [(set_attr_alternative "length" | ||
| 800 | + [(if_then_else (eq_attr "is_arch6" "yes") | ||
| 801 | + (const_int 2) (const_int 4)) | ||
| 802 | + (const_int 4)]) | ||
| 803 | (set_attr "type" "alu_shift,load_byte") | ||
| 804 | (set_attr "pool_range" "*,60")] | ||
| 805 | ) | ||
| 806 | |||
| 807 | (define_insn "*arm_zero_extendhisi2" | ||
| 808 | - [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 809 | - (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] | ||
| 810 | + [(set (match_operand:SI 0 "s_register_operand" "=r,r") | ||
| 811 | + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] | ||
| 812 | "TARGET_ARM && arm_arch4 && !arm_arch6" | ||
| 813 | - "ldr%(h%)\\t%0, %1" | ||
| 814 | - [(set_attr "type" "load_byte") | ||
| 815 | + "@ | ||
| 816 | + # | ||
| 817 | + ldr%(h%)\\t%0, %1" | ||
| 818 | + [(set_attr "type" "alu_shift,load_byte") | ||
| 819 | (set_attr "predicable" "yes") | ||
| 820 | - (set_attr "pool_range" "256") | ||
| 821 | - (set_attr "neg_pool_range" "244")] | ||
| 822 | + (set_attr "pool_range" "*,256") | ||
| 823 | + (set_attr "neg_pool_range" "*,244")] | ||
| 824 | ) | ||
| 825 | |||
| 826 | (define_insn "*arm_zero_extendhisi2_v6" | ||
| 827 | @@ -4213,50 +4174,49 @@ | ||
| 828 | [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 829 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] | ||
| 830 | "TARGET_EITHER" | ||
| 831 | - " | ||
| 832 | - if (!arm_arch6 && GET_CODE (operands[1]) != MEM) | ||
| 833 | - { | ||
| 834 | - if (TARGET_ARM) | ||
| 835 | - { | ||
| 836 | - emit_insn (gen_andsi3 (operands[0], | ||
| 837 | - gen_lowpart (SImode, operands[1]), | ||
| 838 | - GEN_INT (255))); | ||
| 839 | - } | ||
| 840 | - else /* TARGET_THUMB */ | ||
| 841 | - { | ||
| 842 | - rtx temp = gen_reg_rtx (SImode); | ||
| 843 | - rtx ops[3]; | ||
| 844 | - | ||
| 845 | - operands[1] = copy_to_mode_reg (QImode, operands[1]); | ||
| 846 | - operands[1] = gen_lowpart (SImode, operands[1]); | ||
| 847 | - | ||
| 848 | - ops[0] = temp; | ||
| 849 | - ops[1] = operands[1]; | ||
| 850 | - ops[2] = GEN_INT (24); | ||
| 851 | - | ||
| 852 | - emit_insn (gen_rtx_SET (VOIDmode, ops[0], | ||
| 853 | - gen_rtx_ASHIFT (SImode, ops[1], ops[2]))); | ||
| 854 | - | ||
| 855 | - ops[0] = operands[0]; | ||
| 856 | - ops[1] = temp; | ||
| 857 | - ops[2] = GEN_INT (24); | ||
| 858 | - | ||
| 859 | - emit_insn (gen_rtx_SET (VOIDmode, ops[0], | ||
| 860 | - gen_rtx_LSHIFTRT (SImode, ops[1], ops[2]))); | ||
| 861 | - } | ||
| 862 | - DONE; | ||
| 863 | - } | ||
| 864 | - " | ||
| 865 | -) | ||
| 866 | +{ | ||
| 867 | + if (TARGET_ARM && !arm_arch6 && GET_CODE (operands[1]) != MEM) | ||
| 868 | + { | ||
| 869 | + emit_insn (gen_andsi3 (operands[0], | ||
| 870 | + gen_lowpart (SImode, operands[1]), | ||
| 871 | + GEN_INT (255))); | ||
| 872 | + DONE; | ||
| 873 | + } | ||
| 874 | + if (!arm_arch6 && !MEM_P (operands[1])) | ||
| 875 | + { | ||
| 876 | + rtx t = gen_lowpart (SImode, operands[1]); | ||
| 877 | + rtx tmp = gen_reg_rtx (SImode); | ||
| 878 | + emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (24))); | ||
| 879 | + emit_insn (gen_lshrsi3 (operands[0], tmp, GEN_INT (24))); | ||
| 880 | + DONE; | ||
| 881 | + } | ||
| 882 | +}) | ||
| 883 | + | ||
| 884 | +(define_split | ||
| 885 | + [(set (match_operand:SI 0 "register_operand" "") | ||
| 886 | + (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] | ||
| 887 | + "!arm_arch6" | ||
| 888 | + [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24))) | ||
| 889 | + (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | ||
| 890 | +{ | ||
| 891 | + operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0); | ||
| 892 | + if (TARGET_ARM) | ||
| 893 | + { | ||
| 894 | + emit_insn (gen_andsi3 (operands[0], operands[2], GEN_INT (255))); | ||
| 895 | + DONE; | ||
| 896 | + } | ||
| 897 | +}) | ||
| 898 | |||
| 899 | (define_insn "*thumb1_zero_extendqisi2" | ||
| 900 | - [(set (match_operand:SI 0 "register_operand" "=l") | ||
| 901 | - (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | ||
| 902 | + [(set (match_operand:SI 0 "register_operand" "=l,l") | ||
| 903 | + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,m")))] | ||
| 904 | "TARGET_THUMB1 && !arm_arch6" | ||
| 905 | - "ldrb\\t%0, %1" | ||
| 906 | - [(set_attr "length" "2") | ||
| 907 | - (set_attr "type" "load_byte") | ||
| 908 | - (set_attr "pool_range" "32")] | ||
| 909 | + "@ | ||
| 910 | + # | ||
| 911 | + ldrb\\t%0, %1" | ||
| 912 | + [(set_attr "length" "4,2") | ||
| 913 | + (set_attr "type" "alu_shift,load_byte") | ||
| 914 | + (set_attr "pool_range" "*,32")] | ||
| 915 | ) | ||
| 916 | |||
| 917 | (define_insn "*thumb1_zero_extendqisi2_v6" | ||
| 918 | @@ -4272,14 +4232,17 @@ | ||
| 919 | ) | ||
| 920 | |||
| 921 | (define_insn "*arm_zero_extendqisi2" | ||
| 922 | - [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 923 | - (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | ||
| 924 | + [(set (match_operand:SI 0 "s_register_operand" "=r,r") | ||
| 925 | + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] | ||
| 926 | "TARGET_ARM && !arm_arch6" | ||
| 927 | - "ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" | ||
| 928 | - [(set_attr "type" "load_byte") | ||
| 929 | + "@ | ||
| 930 | + # | ||
| 931 | + ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" | ||
| 932 | + [(set_attr "length" "8,4") | ||
| 933 | + (set_attr "type" "alu_shift,load_byte") | ||
| 934 | (set_attr "predicable" "yes") | ||
| 935 | - (set_attr "pool_range" "4096") | ||
| 936 | - (set_attr "neg_pool_range" "4084")] | ||
| 937 | + (set_attr "pool_range" "*,4096") | ||
| 938 | + (set_attr "neg_pool_range" "*,4084")] | ||
| 939 | ) | ||
| 940 | |||
| 941 | (define_insn "*arm_zero_extendqisi2_v6" | ||
| 942 | @@ -4358,108 +4321,42 @@ | ||
| 943 | ) | ||
| 944 | |||
| 945 | (define_expand "extendhisi2" | ||
| 946 | - [(set (match_dup 2) | ||
| 947 | - (ashift:SI (match_operand:HI 1 "nonimmediate_operand" "") | ||
| 948 | - (const_int 16))) | ||
| 949 | - (set (match_operand:SI 0 "s_register_operand" "") | ||
| 950 | - (ashiftrt:SI (match_dup 2) | ||
| 951 | - (const_int 16)))] | ||
| 952 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 953 | + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] | ||
| 954 | "TARGET_EITHER" | ||
| 955 | - " | ||
| 956 | - { | ||
| 957 | - if (GET_CODE (operands[1]) == MEM) | ||
| 958 | - { | ||
| 959 | - if (TARGET_THUMB1) | ||
| 960 | - { | ||
| 961 | - emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1])); | ||
| 962 | - DONE; | ||
| 963 | - } | ||
| 964 | - else if (arm_arch4) | ||
| 965 | - { | ||
| 966 | - emit_insn (gen_rtx_SET (VOIDmode, operands[0], | ||
| 967 | - gen_rtx_SIGN_EXTEND (SImode, operands[1]))); | ||
| 968 | - DONE; | ||
| 969 | - } | ||
| 970 | - } | ||
| 971 | - | ||
| 972 | - if (TARGET_ARM && GET_CODE (operands[1]) == MEM) | ||
| 973 | - { | ||
| 974 | - emit_insn (gen_extendhisi2_mem (operands[0], operands[1])); | ||
| 975 | - DONE; | ||
| 976 | - } | ||
| 977 | - | ||
| 978 | - if (!s_register_operand (operands[1], HImode)) | ||
| 979 | - operands[1] = copy_to_mode_reg (HImode, operands[1]); | ||
| 980 | - | ||
| 981 | - if (arm_arch6) | ||
| 982 | - { | ||
| 983 | - if (TARGET_THUMB1) | ||
| 984 | - emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1])); | ||
| 985 | - else | ||
| 986 | - emit_insn (gen_rtx_SET (VOIDmode, operands[0], | ||
| 987 | - gen_rtx_SIGN_EXTEND (SImode, operands[1]))); | ||
| 988 | - | ||
| 989 | - DONE; | ||
| 990 | - } | ||
| 991 | - | ||
| 992 | - operands[1] = gen_lowpart (SImode, operands[1]); | ||
| 993 | - operands[2] = gen_reg_rtx (SImode); | ||
| 994 | - }" | ||
| 995 | -) | ||
| 996 | - | ||
| 997 | -(define_insn "thumb1_extendhisi2" | ||
| 998 | - [(set (match_operand:SI 0 "register_operand" "=l") | ||
| 999 | - (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))) | ||
| 1000 | - (clobber (match_scratch:SI 2 "=&l"))] | ||
| 1001 | - "TARGET_THUMB1 && !arm_arch6" | ||
| 1002 | - "* | ||
| 1003 | - { | ||
| 1004 | - rtx ops[4]; | ||
| 1005 | - rtx mem = XEXP (operands[1], 0); | ||
| 1006 | - | ||
| 1007 | - /* This code used to try to use 'V', and fix the address only if it was | ||
| 1008 | - offsettable, but this fails for e.g. REG+48 because 48 is outside the | ||
| 1009 | - range of QImode offsets, and offsettable_address_p does a QImode | ||
| 1010 | - address check. */ | ||
| 1011 | - | ||
| 1012 | - if (GET_CODE (mem) == CONST) | ||
| 1013 | - mem = XEXP (mem, 0); | ||
| 1014 | - | ||
| 1015 | - if (GET_CODE (mem) == LABEL_REF) | ||
| 1016 | - return \"ldr\\t%0, %1\"; | ||
| 1017 | - | ||
| 1018 | - if (GET_CODE (mem) == PLUS) | ||
| 1019 | - { | ||
| 1020 | - rtx a = XEXP (mem, 0); | ||
| 1021 | - rtx b = XEXP (mem, 1); | ||
| 1022 | - | ||
| 1023 | - if (GET_CODE (a) == LABEL_REF | ||
| 1024 | - && GET_CODE (b) == CONST_INT) | ||
| 1025 | - return \"ldr\\t%0, %1\"; | ||
| 1026 | - | ||
| 1027 | - if (GET_CODE (b) == REG) | ||
| 1028 | - return \"ldrsh\\t%0, %1\"; | ||
| 1029 | - | ||
| 1030 | - ops[1] = a; | ||
| 1031 | - ops[2] = b; | ||
| 1032 | - } | ||
| 1033 | - else | ||
| 1034 | - { | ||
| 1035 | - ops[1] = mem; | ||
| 1036 | - ops[2] = const0_rtx; | ||
| 1037 | - } | ||
| 1038 | - | ||
| 1039 | - gcc_assert (GET_CODE (ops[1]) == REG); | ||
| 1040 | - | ||
| 1041 | - ops[0] = operands[0]; | ||
| 1042 | - ops[3] = operands[2]; | ||
| 1043 | - output_asm_insn (\"mov\\t%3, %2\;ldrsh\\t%0, [%1, %3]\", ops); | ||
| 1044 | - return \"\"; | ||
| 1045 | - }" | ||
| 1046 | - [(set_attr "length" "4") | ||
| 1047 | - (set_attr "type" "load_byte") | ||
| 1048 | - (set_attr "pool_range" "1020")] | ||
| 1049 | -) | ||
| 1050 | +{ | ||
| 1051 | + if (TARGET_THUMB1) | ||
| 1052 | + { | ||
| 1053 | + emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1])); | ||
| 1054 | + DONE; | ||
| 1055 | + } | ||
| 1056 | + if (MEM_P (operands[1]) && TARGET_ARM && !arm_arch4) | ||
| 1057 | + { | ||
| 1058 | + emit_insn (gen_extendhisi2_mem (operands[0], operands[1])); | ||
| 1059 | + DONE; | ||
| 1060 | + } | ||
| 1061 | + | ||
| 1062 | + if (!arm_arch6 && !MEM_P (operands[1])) | ||
| 1063 | + { | ||
| 1064 | + rtx t = gen_lowpart (SImode, operands[1]); | ||
| 1065 | + rtx tmp = gen_reg_rtx (SImode); | ||
| 1066 | + emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (16))); | ||
| 1067 | + emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (16))); | ||
| 1068 | + DONE; | ||
| 1069 | + } | ||
| 1070 | +}) | ||
| 1071 | + | ||
| 1072 | +(define_split | ||
| 1073 | + [(parallel | ||
| 1074 | + [(set (match_operand:SI 0 "register_operand" "") | ||
| 1075 | + (sign_extend:SI (match_operand:HI 1 "register_operand" ""))) | ||
| 1076 | + (clobber (match_scratch:SI 2 ""))])] | ||
| 1077 | + "!arm_arch6" | ||
| 1078 | + [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) | ||
| 1079 | + (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))] | ||
| 1080 | +{ | ||
| 1081 | + operands[2] = simplify_gen_subreg (SImode, operands[1], HImode, 0); | ||
| 1082 | +}) | ||
| 1083 | |||
| 1084 | ;; We used to have an early-clobber on the scratch register here. | ||
| 1085 | ;; However, there's a bug somewhere in reload which means that this | ||
| 1086 | @@ -4468,16 +4365,18 @@ | ||
| 1087 | ;; we try to verify the operands. Fortunately, we don't really need | ||
| 1088 | ;; the early-clobber: we can always use operand 0 if operand 2 | ||
| 1089 | ;; overlaps the address. | ||
| 1090 | -(define_insn "*thumb1_extendhisi2_insn_v6" | ||
| 1091 | +(define_insn "thumb1_extendhisi2" | ||
| 1092 | [(set (match_operand:SI 0 "register_operand" "=l,l") | ||
| 1093 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m"))) | ||
| 1094 | (clobber (match_scratch:SI 2 "=X,l"))] | ||
| 1095 | - "TARGET_THUMB1 && arm_arch6" | ||
| 1096 | + "TARGET_THUMB1" | ||
| 1097 | "* | ||
| 1098 | { | ||
| 1099 | rtx ops[4]; | ||
| 1100 | rtx mem; | ||
| 1101 | |||
| 1102 | + if (which_alternative == 0 && !arm_arch6) | ||
| 1103 | + return \"#\"; | ||
| 1104 | if (which_alternative == 0) | ||
| 1105 | return \"sxth\\t%0, %1\"; | ||
| 1106 | |||
| 1107 | @@ -4525,7 +4424,10 @@ | ||
| 1108 | output_asm_insn (\"mov\\t%3, %2\;ldrsh\\t%0, [%1, %3]\", ops); | ||
| 1109 | return \"\"; | ||
| 1110 | }" | ||
| 1111 | - [(set_attr "length" "2,4") | ||
| 1112 | + [(set_attr_alternative "length" | ||
| 1113 | + [(if_then_else (eq_attr "is_arch6" "yes") | ||
| 1114 | + (const_int 2) (const_int 4)) | ||
| 1115 | + (const_int 4)]) | ||
| 1116 | (set_attr "type" "alu_shift,load_byte") | ||
| 1117 | (set_attr "pool_range" "*,1020")] | ||
| 1118 | ) | ||
| 1119 | @@ -4566,15 +4468,28 @@ | ||
| 1120 | }" | ||
| 1121 | ) | ||
| 1122 | |||
| 1123 | +(define_split | ||
| 1124 | + [(set (match_operand:SI 0 "register_operand" "") | ||
| 1125 | + (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] | ||
| 1126 | + "!arm_arch6" | ||
| 1127 | + [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) | ||
| 1128 | + (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))] | ||
| 1129 | +{ | ||
| 1130 | + operands[2] = simplify_gen_subreg (SImode, operands[1], HImode, 0); | ||
| 1131 | +}) | ||
| 1132 | + | ||
| 1133 | (define_insn "*arm_extendhisi2" | ||
| 1134 | - [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 1135 | - (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] | ||
| 1136 | + [(set (match_operand:SI 0 "s_register_operand" "=r,r") | ||
| 1137 | + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] | ||
| 1138 | "TARGET_ARM && arm_arch4 && !arm_arch6" | ||
| 1139 | - "ldr%(sh%)\\t%0, %1" | ||
| 1140 | - [(set_attr "type" "load_byte") | ||
| 1141 | + "@ | ||
| 1142 | + # | ||
| 1143 | + ldr%(sh%)\\t%0, %1" | ||
| 1144 | + [(set_attr "length" "8,4") | ||
| 1145 | + (set_attr "type" "alu_shift,load_byte") | ||
| 1146 | (set_attr "predicable" "yes") | ||
| 1147 | - (set_attr "pool_range" "256") | ||
| 1148 | - (set_attr "neg_pool_range" "244")] | ||
| 1149 | + (set_attr "pool_range" "*,256") | ||
| 1150 | + (set_attr "neg_pool_range" "*,244")] | ||
| 1151 | ) | ||
| 1152 | |||
| 1153 | ;; ??? Check Thumb-2 pool range | ||
| 1154 | @@ -4636,46 +4551,45 @@ | ||
| 1155 | ) | ||
| 1156 | |||
| 1157 | (define_expand "extendqisi2" | ||
| 1158 | - [(set (match_dup 2) | ||
| 1159 | - (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "") | ||
| 1160 | - (const_int 24))) | ||
| 1161 | - (set (match_operand:SI 0 "s_register_operand" "") | ||
| 1162 | - (ashiftrt:SI (match_dup 2) | ||
| 1163 | - (const_int 24)))] | ||
| 1164 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 1165 | + (sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")))] | ||
| 1166 | "TARGET_EITHER" | ||
| 1167 | - " | ||
| 1168 | - { | ||
| 1169 | - if ((TARGET_THUMB || arm_arch4) && GET_CODE (operands[1]) == MEM) | ||
| 1170 | - { | ||
| 1171 | - emit_insn (gen_rtx_SET (VOIDmode, operands[0], | ||
| 1172 | - gen_rtx_SIGN_EXTEND (SImode, operands[1]))); | ||
| 1173 | - DONE; | ||
| 1174 | - } | ||
| 1175 | - | ||
| 1176 | - if (!s_register_operand (operands[1], QImode)) | ||
| 1177 | - operands[1] = copy_to_mode_reg (QImode, operands[1]); | ||
| 1178 | - | ||
| 1179 | - if (arm_arch6) | ||
| 1180 | - { | ||
| 1181 | - emit_insn (gen_rtx_SET (VOIDmode, operands[0], | ||
| 1182 | - gen_rtx_SIGN_EXTEND (SImode, operands[1]))); | ||
| 1183 | - DONE; | ||
| 1184 | - } | ||
| 1185 | - | ||
| 1186 | - operands[1] = gen_lowpart (SImode, operands[1]); | ||
| 1187 | - operands[2] = gen_reg_rtx (SImode); | ||
| 1188 | - }" | ||
| 1189 | -) | ||
| 1190 | +{ | ||
| 1191 | + if (!arm_arch4 && MEM_P (operands[1])) | ||
| 1192 | + operands[1] = copy_to_mode_reg (QImode, operands[1]); | ||
| 1193 | + | ||
| 1194 | + if (!arm_arch6 && !MEM_P (operands[1])) | ||
| 1195 | + { | ||
| 1196 | + rtx t = gen_lowpart (SImode, operands[1]); | ||
| 1197 | + rtx tmp = gen_reg_rtx (SImode); | ||
| 1198 | + emit_insn (gen_ashlsi3 (tmp, t, GEN_INT (24))); | ||
| 1199 | + emit_insn (gen_ashrsi3 (operands[0], tmp, GEN_INT (24))); | ||
| 1200 | + DONE; | ||
| 1201 | + } | ||
| 1202 | +}) | ||
| 1203 | + | ||
| 1204 | +(define_split | ||
| 1205 | + [(set (match_operand:SI 0 "register_operand" "") | ||
| 1206 | + (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] | ||
| 1207 | + "!arm_arch6" | ||
| 1208 | + [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24))) | ||
| 1209 | + (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))] | ||
| 1210 | +{ | ||
| 1211 | + operands[2] = simplify_gen_subreg (SImode, operands[1], QImode, 0); | ||
| 1212 | +}) | ||
| 1213 | |||
| 1214 | (define_insn "*arm_extendqisi" | ||
| 1215 | - [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 1216 | - (sign_extend:SI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))] | ||
| 1217 | + [(set (match_operand:SI 0 "s_register_operand" "=r,r") | ||
| 1218 | + (sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))] | ||
| 1219 | "TARGET_ARM && arm_arch4 && !arm_arch6" | ||
| 1220 | - "ldr%(sb%)\\t%0, %1" | ||
| 1221 | - [(set_attr "type" "load_byte") | ||
| 1222 | + "@ | ||
| 1223 | + # | ||
| 1224 | + ldr%(sb%)\\t%0, %1" | ||
| 1225 | + [(set_attr "length" "8,4") | ||
| 1226 | + (set_attr "type" "alu_shift,load_byte") | ||
| 1227 | (set_attr "predicable" "yes") | ||
| 1228 | - (set_attr "pool_range" "256") | ||
| 1229 | - (set_attr "neg_pool_range" "244")] | ||
| 1230 | + (set_attr "pool_range" "*,256") | ||
| 1231 | + (set_attr "neg_pool_range" "*,244")] | ||
| 1232 | ) | ||
| 1233 | |||
| 1234 | (define_insn "*arm_extendqisi_v6" | ||
| 1235 | @@ -4703,162 +4617,103 @@ | ||
| 1236 | (set_attr "predicable" "yes")] | ||
| 1237 | ) | ||
| 1238 | |||
| 1239 | -(define_insn "*thumb1_extendqisi2" | ||
| 1240 | - [(set (match_operand:SI 0 "register_operand" "=l,l") | ||
| 1241 | - (sign_extend:SI (match_operand:QI 1 "memory_operand" "V,m")))] | ||
| 1242 | - "TARGET_THUMB1 && !arm_arch6" | ||
| 1243 | - "* | ||
| 1244 | - { | ||
| 1245 | - rtx ops[3]; | ||
| 1246 | - rtx mem = XEXP (operands[1], 0); | ||
| 1247 | - | ||
| 1248 | - if (GET_CODE (mem) == CONST) | ||
| 1249 | - mem = XEXP (mem, 0); | ||
| 1250 | - | ||
| 1251 | - if (GET_CODE (mem) == LABEL_REF) | ||
| 1252 | - return \"ldr\\t%0, %1\"; | ||
| 1253 | - | ||
| 1254 | - if (GET_CODE (mem) == PLUS | ||
| 1255 | - && GET_CODE (XEXP (mem, 0)) == LABEL_REF) | ||
| 1256 | - return \"ldr\\t%0, %1\"; | ||
| 1257 | - | ||
| 1258 | - if (which_alternative == 0) | ||
| 1259 | - return \"ldrsb\\t%0, %1\"; | ||
| 1260 | - | ||
| 1261 | - ops[0] = operands[0]; | ||
| 1262 | - | ||
| 1263 | - if (GET_CODE (mem) == PLUS) | ||
| 1264 | - { | ||
| 1265 | - rtx a = XEXP (mem, 0); | ||
| 1266 | - rtx b = XEXP (mem, 1); | ||
| 1267 | - | ||
| 1268 | - ops[1] = a; | ||
| 1269 | - ops[2] = b; | ||
| 1270 | - | ||
| 1271 | - if (GET_CODE (a) == REG) | ||
| 1272 | - { | ||
| 1273 | - if (GET_CODE (b) == REG) | ||
| 1274 | - output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops); | ||
| 1275 | - else if (REGNO (a) == REGNO (ops[0])) | ||
| 1276 | - { | ||
| 1277 | - output_asm_insn (\"ldrb\\t%0, [%1, %2]\", ops); | ||
| 1278 | - output_asm_insn (\"lsl\\t%0, %0, #24\", ops); | ||
| 1279 | - output_asm_insn (\"asr\\t%0, %0, #24\", ops); | ||
| 1280 | - } | ||
| 1281 | - else | ||
| 1282 | - output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); | ||
| 1283 | - } | ||
| 1284 | - else | ||
| 1285 | - { | ||
| 1286 | - gcc_assert (GET_CODE (b) == REG); | ||
| 1287 | - if (REGNO (b) == REGNO (ops[0])) | ||
| 1288 | - { | ||
| 1289 | - output_asm_insn (\"ldrb\\t%0, [%2, %1]\", ops); | ||
| 1290 | - output_asm_insn (\"lsl\\t%0, %0, #24\", ops); | ||
| 1291 | - output_asm_insn (\"asr\\t%0, %0, #24\", ops); | ||
| 1292 | - } | ||
| 1293 | - else | ||
| 1294 | - output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); | ||
| 1295 | - } | ||
| 1296 | - } | ||
| 1297 | - else if (GET_CODE (mem) == REG && REGNO (ops[0]) == REGNO (mem)) | ||
| 1298 | - { | ||
| 1299 | - output_asm_insn (\"ldrb\\t%0, [%0, #0]\", ops); | ||
| 1300 | - output_asm_insn (\"lsl\\t%0, %0, #24\", ops); | ||
| 1301 | - output_asm_insn (\"asr\\t%0, %0, #24\", ops); | ||
| 1302 | - } | ||
| 1303 | - else | ||
| 1304 | - { | ||
| 1305 | - ops[1] = mem; | ||
| 1306 | - ops[2] = const0_rtx; | ||
| 1307 | - | ||
| 1308 | - output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); | ||
| 1309 | - } | ||
| 1310 | - return \"\"; | ||
| 1311 | - }" | ||
| 1312 | - [(set_attr "length" "2,6") | ||
| 1313 | - (set_attr "type" "load_byte,load_byte") | ||
| 1314 | - (set_attr "pool_range" "32,32")] | ||
| 1315 | -) | ||
| 1316 | - | ||
| 1317 | -(define_insn "*thumb1_extendqisi2_v6" | ||
| 1318 | +(define_split | ||
| 1319 | + [(set (match_operand:SI 0 "register_operand" "") | ||
| 1320 | + (sign_extend:SI (match_operand:QI 1 "memory_operand" "")))] | ||
| 1321 | + "TARGET_THUMB1 && reload_completed" | ||
| 1322 | + [(set (match_dup 0) (match_dup 2)) | ||
| 1323 | + (set (match_dup 0) (sign_extend:SI (match_dup 3)))] | ||
| 1324 | +{ | ||
| 1325 | + rtx addr = XEXP (operands[1], 0); | ||
| 1326 | + | ||
| 1327 | + if (GET_CODE (addr) == CONST) | ||
| 1328 | + addr = XEXP (addr, 0); | ||
| 1329 | + | ||
| 1330 | + if (GET_CODE (addr) == PLUS | ||
| 1331 | + && REG_P (XEXP (addr, 0)) && REG_P (XEXP (addr, 1))) | ||
| 1332 | + /* No split necessary. */ | ||
| 1333 | + FAIL; | ||
| 1334 | + | ||
| 1335 | + if (GET_CODE (addr) == PLUS | ||
| 1336 | + && !REG_P (XEXP (addr, 0)) && !REG_P (XEXP (addr, 1))) | ||
| 1337 | + FAIL; | ||
| 1338 | + | ||
| 1339 | + if (reg_overlap_mentioned_p (operands[0], addr)) | ||
| 1340 | + { | ||
| 1341 | + rtx t = gen_lowpart (QImode, operands[0]); | ||
| 1342 | + emit_move_insn (t, operands[1]); | ||
| 1343 | + emit_insn (gen_thumb1_extendqisi2 (operands[0], t)); | ||
| 1344 | + DONE; | ||
| 1345 | + } | ||
| 1346 | + | ||
| 1347 | + if (REG_P (addr)) | ||
| 1348 | + { | ||
| 1349 | + addr = gen_rtx_PLUS (Pmode, addr, operands[0]); | ||
| 1350 | + operands[2] = const0_rtx; | ||
| 1351 | + } | ||
| 1352 | + else if (GET_CODE (addr) != PLUS) | ||
| 1353 | + FAIL; | ||
| 1354 | + else if (REG_P (XEXP (addr, 0))) | ||
| 1355 | + { | ||
| 1356 | + operands[2] = XEXP (addr, 1); | ||
| 1357 | + addr = gen_rtx_PLUS (Pmode, XEXP (addr, 0), operands[0]); | ||
| 1358 | + } | ||
| 1359 | + else | ||
| 1360 | + { | ||
| 1361 | + operands[2] = XEXP (addr, 0); | ||
| 1362 | + addr = gen_rtx_PLUS (Pmode, XEXP (addr, 1), operands[0]); | ||
| 1363 | + } | ||
| 1364 | + | ||
| 1365 | + operands[3] = change_address (operands[1], QImode, addr); | ||
| 1366 | +}) | ||
| 1367 | + | ||
| 1368 | +(define_peephole2 | ||
| 1369 | + [(set (match_operand:SI 0 "register_operand" "") | ||
| 1370 | + (plus:SI (match_dup 0) (match_operand 1 "const_int_operand"))) | ||
| 1371 | + (set (match_operand:SI 2 "register_operand" "") (const_int 0)) | ||
| 1372 | + (set (match_operand:SI 3 "register_operand" "") | ||
| 1373 | + (sign_extend:SI (match_operand:QI 4 "memory_operand" "")))] | ||
| 1374 | + "TARGET_THUMB1 | ||
| 1375 | + && GET_CODE (XEXP (operands[4], 0)) == PLUS | ||
| 1376 | + && rtx_equal_p (operands[0], XEXP (XEXP (operands[4], 0), 0)) | ||
| 1377 | + && rtx_equal_p (operands[2], XEXP (XEXP (operands[4], 0), 1)) | ||
| 1378 | + && (peep2_reg_dead_p (3, operands[0]) | ||
| 1379 | + || rtx_equal_p (operands[0], operands[3])) | ||
| 1380 | + && (peep2_reg_dead_p (3, operands[2]) | ||
| 1381 | + || rtx_equal_p (operands[2], operands[3]))" | ||
| 1382 | + [(set (match_dup 2) (match_dup 1)) | ||
| 1383 | + (set (match_dup 3) (sign_extend:SI (match_dup 4)))] | ||
| 1384 | +{ | ||
| 1385 | + rtx addr = gen_rtx_PLUS (Pmode, operands[0], operands[2]); | ||
| 1386 | + operands[4] = change_address (operands[4], QImode, addr); | ||
| 1387 | +}) | ||
| 1388 | + | ||
| 1389 | +(define_insn "thumb1_extendqisi2" | ||
| 1390 | [(set (match_operand:SI 0 "register_operand" "=l,l,l") | ||
| 1391 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,V,m")))] | ||
| 1392 | - "TARGET_THUMB1 && arm_arch6" | ||
| 1393 | - "* | ||
| 1394 | - { | ||
| 1395 | - rtx ops[3]; | ||
| 1396 | - rtx mem; | ||
| 1397 | - | ||
| 1398 | - if (which_alternative == 0) | ||
| 1399 | - return \"sxtb\\t%0, %1\"; | ||
| 1400 | - | ||
| 1401 | - mem = XEXP (operands[1], 0); | ||
| 1402 | - | ||
| 1403 | - if (GET_CODE (mem) == CONST) | ||
| 1404 | - mem = XEXP (mem, 0); | ||
| 1405 | - | ||
| 1406 | - if (GET_CODE (mem) == LABEL_REF) | ||
| 1407 | - return \"ldr\\t%0, %1\"; | ||
| 1408 | - | ||
| 1409 | - if (GET_CODE (mem) == PLUS | ||
| 1410 | - && GET_CODE (XEXP (mem, 0)) == LABEL_REF) | ||
| 1411 | - return \"ldr\\t%0, %1\"; | ||
| 1412 | - | ||
| 1413 | - if (which_alternative == 0) | ||
| 1414 | - return \"ldrsb\\t%0, %1\"; | ||
| 1415 | - | ||
| 1416 | - ops[0] = operands[0]; | ||
| 1417 | - | ||
| 1418 | - if (GET_CODE (mem) == PLUS) | ||
| 1419 | - { | ||
| 1420 | - rtx a = XEXP (mem, 0); | ||
| 1421 | - rtx b = XEXP (mem, 1); | ||
| 1422 | - | ||
| 1423 | - ops[1] = a; | ||
| 1424 | - ops[2] = b; | ||
| 1425 | - | ||
| 1426 | - if (GET_CODE (a) == REG) | ||
| 1427 | - { | ||
| 1428 | - if (GET_CODE (b) == REG) | ||
| 1429 | - output_asm_insn (\"ldrsb\\t%0, [%1, %2]\", ops); | ||
| 1430 | - else if (REGNO (a) == REGNO (ops[0])) | ||
| 1431 | - { | ||
| 1432 | - output_asm_insn (\"ldrb\\t%0, [%1, %2]\", ops); | ||
| 1433 | - output_asm_insn (\"sxtb\\t%0, %0\", ops); | ||
| 1434 | - } | ||
| 1435 | - else | ||
| 1436 | - output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); | ||
| 1437 | - } | ||
| 1438 | - else | ||
| 1439 | - { | ||
| 1440 | - gcc_assert (GET_CODE (b) == REG); | ||
| 1441 | - if (REGNO (b) == REGNO (ops[0])) | ||
| 1442 | - { | ||
| 1443 | - output_asm_insn (\"ldrb\\t%0, [%2, %1]\", ops); | ||
| 1444 | - output_asm_insn (\"sxtb\\t%0, %0\", ops); | ||
| 1445 | - } | ||
| 1446 | - else | ||
| 1447 | - output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); | ||
| 1448 | - } | ||
| 1449 | - } | ||
| 1450 | - else if (GET_CODE (mem) == REG && REGNO (ops[0]) == REGNO (mem)) | ||
| 1451 | - { | ||
| 1452 | - output_asm_insn (\"ldrb\\t%0, [%0, #0]\", ops); | ||
| 1453 | - output_asm_insn (\"sxtb\\t%0, %0\", ops); | ||
| 1454 | - } | ||
| 1455 | - else | ||
| 1456 | - { | ||
| 1457 | - ops[1] = mem; | ||
| 1458 | - ops[2] = const0_rtx; | ||
| 1459 | - | ||
| 1460 | - output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops); | ||
| 1461 | - } | ||
| 1462 | - return \"\"; | ||
| 1463 | - }" | ||
| 1464 | - [(set_attr "length" "2,2,4") | ||
| 1465 | - (set_attr "type" "alu_shift,load_byte,load_byte") | ||
| 1466 | - (set_attr "pool_range" "*,32,32")] | ||
| 1467 | + "TARGET_THUMB1" | ||
| 1468 | +{ | ||
| 1469 | + rtx addr; | ||
| 1470 | + | ||
| 1471 | + if (which_alternative == 0 && arm_arch6) | ||
| 1472 | + return "sxtb\\t%0, %1"; | ||
| 1473 | + if (which_alternative == 0) | ||
| 1474 | + return "#"; | ||
| 1475 | + | ||
| 1476 | + addr = XEXP (operands[1], 0); | ||
| 1477 | + if (GET_CODE (addr) == PLUS | ||
| 1478 | + && REG_P (XEXP (addr, 0)) && REG_P (XEXP (addr, 1))) | ||
| 1479 | + return "ldrsb\\t%0, %1"; | ||
| 1480 | + | ||
| 1481 | + return "#"; | ||
| 1482 | +} | ||
| 1483 | + [(set_attr_alternative "length" | ||
| 1484 | + [(if_then_else (eq_attr "is_arch6" "yes") | ||
| 1485 | + (const_int 2) (const_int 4)) | ||
| 1486 | + (const_int 2) | ||
| 1487 | + (if_then_else (eq_attr "is_arch6" "yes") | ||
| 1488 | + (const_int 4) (const_int 6))]) | ||
| 1489 | + (set_attr "type" "alu_shift,load_byte,load_byte")] | ||
| 1490 | ) | ||
| 1491 | |||
| 1492 | (define_expand "extendsfdf2" | ||
| 1493 | @@ -6784,6 +6639,30 @@ | ||
| 1494 | operands[2] = force_reg (SImode, operands[2]); | ||
| 1495 | ") | ||
| 1496 | |||
| 1497 | +;; A pattern to recognize a special situation and optimize for it. | ||
| 1498 | +;; On the thumb, zero-extension from memory is preferrable to sign-extension | ||
| 1499 | +;; due to the available addressing modes. Hence, convert a signed comparison | ||
| 1500 | +;; with zero into an unsigned comparison with 127 if possible. | ||
| 1501 | +(define_expand "cbranchqi4" | ||
| 1502 | + [(set (pc) (if_then_else | ||
| 1503 | + (match_operator 0 "lt_ge_comparison_operator" | ||
| 1504 | + [(match_operand:QI 1 "memory_operand" "") | ||
| 1505 | + (match_operand:QI 2 "const0_operand" "")]) | ||
| 1506 | + (label_ref (match_operand 3 "" "")) | ||
| 1507 | + (pc)))] | ||
| 1508 | + "TARGET_THUMB1" | ||
| 1509 | +{ | ||
| 1510 | + rtx xops[4]; | ||
| 1511 | + xops[1] = gen_reg_rtx (SImode); | ||
| 1512 | + emit_insn (gen_zero_extendqisi2 (xops[1], operands[1])); | ||
| 1513 | + xops[2] = GEN_INT (127); | ||
| 1514 | + xops[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]) == GE ? LEU : GTU, | ||
| 1515 | + VOIDmode, xops[1], xops[2]); | ||
| 1516 | + xops[3] = operands[3]; | ||
| 1517 | + emit_insn (gen_cbranchsi4 (xops[0], xops[1], xops[2], xops[3])); | ||
| 1518 | + DONE; | ||
| 1519 | +}) | ||
| 1520 | + | ||
| 1521 | (define_expand "cbranchsf4" | ||
| 1522 | [(set (pc) (if_then_else | ||
| 1523 | (match_operator 0 "arm_comparison_operator" | ||
| 1524 | @@ -6849,7 +6728,7 @@ | ||
| 1525 | }" | ||
| 1526 | ) | ||
| 1527 | |||
| 1528 | -(define_insn "*cbranchsi4_insn" | ||
| 1529 | +(define_insn "cbranchsi4_insn" | ||
| 1530 | [(set (pc) (if_then_else | ||
| 1531 | (match_operator 0 "arm_comparison_operator" | ||
| 1532 | [(match_operand:SI 1 "s_register_operand" "l,*h") | ||
| 1533 | @@ -6858,7 +6737,20 @@ | ||
| 1534 | (pc)))] | ||
| 1535 | "TARGET_THUMB1" | ||
| 1536 | "* | ||
| 1537 | - output_asm_insn (\"cmp\\t%1, %2\", operands); | ||
| 1538 | + rtx t = prev_nonnote_insn (insn); | ||
| 1539 | + if (t != NULL_RTX | ||
| 1540 | + && INSN_P (t) | ||
| 1541 | + && INSN_CODE (t) == CODE_FOR_cbranchsi4_insn) | ||
| 1542 | + { | ||
| 1543 | + t = XEXP (SET_SRC (PATTERN (t)), 0); | ||
| 1544 | + if (!rtx_equal_p (XEXP (t, 0), operands[1]) | ||
| 1545 | + || !rtx_equal_p (XEXP (t, 1), operands[2])) | ||
| 1546 | + t = NULL_RTX; | ||
| 1547 | + } | ||
| 1548 | + else | ||
| 1549 | + t = NULL_RTX; | ||
| 1550 | + if (t == NULL_RTX) | ||
| 1551 | + output_asm_insn (\"cmp\\t%1, %2\", operands); | ||
| 1552 | |||
| 1553 | switch (get_attr_length (insn)) | ||
| 1554 | { | ||
| 1555 | @@ -7674,15 +7566,15 @@ | ||
| 1556 | (if_then_else | ||
| 1557 | (match_operator 4 "arm_comparison_operator" | ||
| 1558 | [(plus:SI | ||
| 1559 | - (match_operand:SI 2 "s_register_operand" "%l,0,*0,1,1,1") | ||
| 1560 | - (match_operand:SI 3 "reg_or_int_operand" "lL,IJ,*r,lIJ,lIJ,lIJ")) | ||
| 1561 | + (match_operand:SI 2 "s_register_operand" "%0,l,*l,1,1,1") | ||
| 1562 | + (match_operand:SI 3 "reg_or_int_operand" "IJ,lL,*l,lIJ,lIJ,lIJ")) | ||
| 1563 | (const_int 0)]) | ||
| 1564 | (label_ref (match_operand 5 "" "")) | ||
| 1565 | (pc))) | ||
| 1566 | (set | ||
| 1567 | (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*!h,*?h,*?m,*?m") | ||
| 1568 | (plus:SI (match_dup 2) (match_dup 3))) | ||
| 1569 | - (clobber (match_scratch:SI 1 "=X,X,X,l,&l,&l"))] | ||
| 1570 | + (clobber (match_scratch:SI 1 "=X,X,l,l,&l,&l"))] | ||
| 1571 | "TARGET_THUMB1 | ||
| 1572 | && (GET_CODE (operands[4]) == EQ | ||
| 1573 | || GET_CODE (operands[4]) == NE | ||
| 1574 | @@ -7692,8 +7584,7 @@ | ||
| 1575 | { | ||
| 1576 | rtx cond[3]; | ||
| 1577 | |||
| 1578 | - | ||
| 1579 | - cond[0] = (which_alternative < 3) ? operands[0] : operands[1]; | ||
| 1580 | + cond[0] = (which_alternative < 2) ? operands[0] : operands[1]; | ||
| 1581 | cond[1] = operands[2]; | ||
| 1582 | cond[2] = operands[3]; | ||
| 1583 | |||
| 1584 | @@ -7702,13 +7593,13 @@ | ||
| 1585 | else | ||
| 1586 | output_asm_insn (\"add\\t%0, %1, %2\", cond); | ||
| 1587 | |||
| 1588 | - if (which_alternative >= 3 | ||
| 1589 | + if (which_alternative >= 2 | ||
| 1590 | && which_alternative < 4) | ||
| 1591 | output_asm_insn (\"mov\\t%0, %1\", operands); | ||
| 1592 | else if (which_alternative >= 4) | ||
| 1593 | output_asm_insn (\"str\\t%1, %0\", operands); | ||
| 1594 | |||
| 1595 | - switch (get_attr_length (insn) - ((which_alternative >= 3) ? 2 : 0)) | ||
| 1596 | + switch (get_attr_length (insn) - ((which_alternative >= 2) ? 2 : 0)) | ||
| 1597 | { | ||
| 1598 | case 4: | ||
| 1599 | return \"b%d4\\t%l5\"; | ||
| 1600 | @@ -7722,7 +7613,7 @@ | ||
| 1601 | [(set (attr "far_jump") | ||
| 1602 | (if_then_else | ||
| 1603 | (ior (and (lt (symbol_ref ("which_alternative")) | ||
| 1604 | - (const_int 3)) | ||
| 1605 | + (const_int 2)) | ||
| 1606 | (eq_attr "length" "8")) | ||
| 1607 | (eq_attr "length" "10")) | ||
| 1608 | (const_string "yes") | ||
| 1609 | @@ -7730,7 +7621,7 @@ | ||
| 1610 | (set (attr "length") | ||
| 1611 | (if_then_else | ||
| 1612 | (lt (symbol_ref ("which_alternative")) | ||
| 1613 | - (const_int 3)) | ||
| 1614 | + (const_int 2)) | ||
| 1615 | (if_then_else | ||
| 1616 | (and (ge (minus (match_dup 5) (pc)) (const_int -250)) | ||
| 1617 | (le (minus (match_dup 5) (pc)) (const_int 256))) | ||
| 1618 | @@ -9483,41 +9374,117 @@ | ||
| 1619 | (set_attr "length" "4,8")] | ||
| 1620 | ) | ||
| 1621 | |||
| 1622 | -(define_insn "*compare_scc" | ||
| 1623 | +; A series of splitters for the compare_scc pattern below. Note that | ||
| 1624 | +; order is important. | ||
| 1625 | +(define_split | ||
| 1626 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 1627 | + (lt:SI (match_operand:SI 1 "s_register_operand" "") | ||
| 1628 | + (const_int 0))) | ||
| 1629 | + (clobber (reg:CC CC_REGNUM))] | ||
| 1630 | + "TARGET_32BIT && reload_completed" | ||
| 1631 | + [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 31)))]) | ||
| 1632 | + | ||
| 1633 | +(define_split | ||
| 1634 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 1635 | + (ge:SI (match_operand:SI 1 "s_register_operand" "") | ||
| 1636 | + (const_int 0))) | ||
| 1637 | + (clobber (reg:CC CC_REGNUM))] | ||
| 1638 | + "TARGET_32BIT && reload_completed" | ||
| 1639 | + [(set (match_dup 0) (not:SI (match_dup 1))) | ||
| 1640 | + (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 31)))]) | ||
| 1641 | + | ||
| 1642 | +(define_split | ||
| 1643 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 1644 | + (eq:SI (match_operand:SI 1 "s_register_operand" "") | ||
| 1645 | + (const_int 0))) | ||
| 1646 | + (clobber (reg:CC CC_REGNUM))] | ||
| 1647 | + "TARGET_32BIT && reload_completed" | ||
| 1648 | + [(parallel | ||
| 1649 | + [(set (reg:CC CC_REGNUM) | ||
| 1650 | + (compare:CC (const_int 1) (match_dup 1))) | ||
| 1651 | + (set (match_dup 0) | ||
| 1652 | + (minus:SI (const_int 1) (match_dup 1)))]) | ||
| 1653 | + (cond_exec (ltu:CC (reg:CC CC_REGNUM) (const_int 0)) | ||
| 1654 | + (set (match_dup 0) (const_int 0)))]) | ||
| 1655 | + | ||
| 1656 | +(define_split | ||
| 1657 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 1658 | + (ne:SI (match_operand:SI 1 "s_register_operand" "") | ||
| 1659 | + (match_operand:SI 2 "const_int_operand" ""))) | ||
| 1660 | + (clobber (reg:CC CC_REGNUM))] | ||
| 1661 | + "TARGET_32BIT && reload_completed" | ||
| 1662 | + [(parallel | ||
| 1663 | + [(set (reg:CC CC_REGNUM) | ||
| 1664 | + (compare:CC (match_dup 1) (match_dup 2))) | ||
| 1665 | + (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))]) | ||
| 1666 | + (cond_exec (ne:CC (reg:CC CC_REGNUM) (const_int 0)) | ||
| 1667 | + (set (match_dup 0) (const_int 1)))] | ||
| 1668 | +{ | ||
| 1669 | + operands[3] = GEN_INT (-INTVAL (operands[2])); | ||
| 1670 | +}) | ||
| 1671 | + | ||
| 1672 | +(define_split | ||
| 1673 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 1674 | + (ne:SI (match_operand:SI 1 "s_register_operand" "") | ||
| 1675 | + (match_operand:SI 2 "arm_add_operand" ""))) | ||
| 1676 | + (clobber (reg:CC CC_REGNUM))] | ||
| 1677 | + "TARGET_32BIT && reload_completed" | ||
| 1678 | + [(parallel | ||
| 1679 | + [(set (reg:CC_NOOV CC_REGNUM) | ||
| 1680 | + (compare:CC_NOOV (minus:SI (match_dup 1) (match_dup 2)) | ||
| 1681 | + (const_int 0))) | ||
| 1682 | + (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) | ||
| 1683 | + (cond_exec (ne:CC_NOOV (reg:CC_NOOV CC_REGNUM) (const_int 0)) | ||
| 1684 | + (set (match_dup 0) (const_int 1)))]) | ||
| 1685 | + | ||
| 1686 | +(define_insn_and_split "*compare_scc" | ||
| 1687 | [(set (match_operand:SI 0 "s_register_operand" "=r,r") | ||
| 1688 | (match_operator:SI 1 "arm_comparison_operator" | ||
| 1689 | [(match_operand:SI 2 "s_register_operand" "r,r") | ||
| 1690 | (match_operand:SI 3 "arm_add_operand" "rI,L")])) | ||
| 1691 | (clobber (reg:CC CC_REGNUM))] | ||
| 1692 | - "TARGET_ARM" | ||
| 1693 | - "* | ||
| 1694 | - if (operands[3] == const0_rtx) | ||
| 1695 | - { | ||
| 1696 | - if (GET_CODE (operands[1]) == LT) | ||
| 1697 | - return \"mov\\t%0, %2, lsr #31\"; | ||
| 1698 | - | ||
| 1699 | - if (GET_CODE (operands[1]) == GE) | ||
| 1700 | - return \"mvn\\t%0, %2\;mov\\t%0, %0, lsr #31\"; | ||
| 1701 | - | ||
| 1702 | - if (GET_CODE (operands[1]) == EQ) | ||
| 1703 | - return \"rsbs\\t%0, %2, #1\;movcc\\t%0, #0\"; | ||
| 1704 | - } | ||
| 1705 | - | ||
| 1706 | - if (GET_CODE (operands[1]) == NE) | ||
| 1707 | - { | ||
| 1708 | - if (which_alternative == 1) | ||
| 1709 | - return \"adds\\t%0, %2, #%n3\;movne\\t%0, #1\"; | ||
| 1710 | - return \"subs\\t%0, %2, %3\;movne\\t%0, #1\"; | ||
| 1711 | - } | ||
| 1712 | - if (which_alternative == 1) | ||
| 1713 | - output_asm_insn (\"cmn\\t%2, #%n3\", operands); | ||
| 1714 | - else | ||
| 1715 | - output_asm_insn (\"cmp\\t%2, %3\", operands); | ||
| 1716 | - return \"mov%D1\\t%0, #0\;mov%d1\\t%0, #1\"; | ||
| 1717 | - " | ||
| 1718 | - [(set_attr "conds" "clob") | ||
| 1719 | - (set_attr "length" "12")] | ||
| 1720 | -) | ||
| 1721 | + "TARGET_32BIT" | ||
| 1722 | + "#" | ||
| 1723 | + "&& reload_completed" | ||
| 1724 | + [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 3))) | ||
| 1725 | + (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0))) | ||
| 1726 | + (cond_exec (match_dup 5) (set (match_dup 0) (const_int 1)))] | ||
| 1727 | +{ | ||
| 1728 | + rtx tmp1; | ||
| 1729 | + enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), | ||
| 1730 | + operands[2], operands[3]); | ||
| 1731 | + enum rtx_code rc = GET_CODE (operands[1]); | ||
| 1732 | + | ||
| 1733 | + tmp1 = gen_rtx_REG (mode, CC_REGNUM); | ||
| 1734 | + | ||
| 1735 | + operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx); | ||
| 1736 | + if (mode == CCFPmode || mode == CCFPEmode) | ||
| 1737 | + rc = reverse_condition_maybe_unordered (rc); | ||
| 1738 | + else | ||
| 1739 | + rc = reverse_condition (rc); | ||
| 1740 | + operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx); | ||
| 1741 | +}) | ||
| 1742 | + | ||
| 1743 | +;; Attempt to improve the sequence generated by the compare_scc splitters | ||
| 1744 | +;; not to use conditional execution. | ||
| 1745 | +(define_peephole2 | ||
| 1746 | + [(set (reg:CC CC_REGNUM) | ||
| 1747 | + (compare:CC (match_operand:SI 1 "register_operand" "") | ||
| 1748 | + (match_operand:SI 2 "arm_rhs_operand" ""))) | ||
| 1749 | + (cond_exec (ne (reg:CC CC_REGNUM) (const_int 0)) | ||
| 1750 | + (set (match_operand:SI 0 "register_operand" "") (const_int 0))) | ||
| 1751 | + (cond_exec (eq (reg:CC CC_REGNUM) (const_int 0)) | ||
| 1752 | + (set (match_dup 0) (const_int 1))) | ||
| 1753 | + (match_scratch:SI 3 "r")] | ||
| 1754 | + "TARGET_32BIT" | ||
| 1755 | + [(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | ||
| 1756 | + (parallel | ||
| 1757 | + [(set (reg:CC CC_REGNUM) | ||
| 1758 | + (compare:CC (const_int 0) (match_dup 3))) | ||
| 1759 | + (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))]) | ||
| 1760 | + (set (match_dup 0) | ||
| 1761 | + (plus:SI (plus:SI (match_dup 0) (match_dup 3)) | ||
| 1762 | + (geu:SI (reg:CC CC_REGNUM) (const_int 0))))]) | ||
| 1763 | |||
| 1764 | (define_insn "*cond_move" | ||
| 1765 | [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") | ||
| 1766 | |||
| 1767 | === modified file 'gcc/config/arm/predicates.md' | ||
| 1768 | --- old/gcc/config/arm/predicates.md 2010-08-31 09:40:16 +0000 | ||
| 1769 | +++ new/gcc/config/arm/predicates.md 2010-08-31 10:00:27 +0000 | ||
| 1770 | @@ -115,6 +115,10 @@ | ||
| 1771 | (and (match_code "const_int") | ||
| 1772 | (match_test "const_ok_for_arm (~INTVAL (op))"))) | ||
| 1773 | |||
| 1774 | +(define_predicate "const0_operand" | ||
| 1775 | + (and (match_code "const_int") | ||
| 1776 | + (match_test "INTVAL (op) == 0"))) | ||
| 1777 | + | ||
| 1778 | ;; Something valid on the RHS of an ARM data-processing instruction | ||
| 1779 | (define_predicate "arm_rhs_operand" | ||
| 1780 | (ior (match_operand 0 "s_register_operand") | ||
| 1781 | @@ -233,6 +237,9 @@ | ||
| 1782 | && (TARGET_FPA || TARGET_VFP)") | ||
| 1783 | (match_code "unordered,ordered,unlt,unle,unge,ungt")))) | ||
| 1784 | |||
| 1785 | +(define_special_predicate "lt_ge_comparison_operator" | ||
| 1786 | + (match_code "lt,ge")) | ||
| 1787 | + | ||
| 1788 | (define_special_predicate "minmax_operator" | ||
| 1789 | (and (match_code "smin,smax,umin,umax") | ||
| 1790 | (match_test "mode == GET_MODE (op)"))) | ||
| 1791 | |||
| 1792 | === modified file 'gcc/config/arm/thumb2.md' | ||
| 1793 | --- old/gcc/config/arm/thumb2.md 2010-08-31 09:40:16 +0000 | ||
| 1794 | +++ new/gcc/config/arm/thumb2.md 2010-08-31 10:00:27 +0000 | ||
| 1795 | @@ -599,42 +599,6 @@ | ||
| 1796 | (set_attr "length" "6,10")] | ||
| 1797 | ) | ||
| 1798 | |||
| 1799 | -(define_insn "*thumb2_compare_scc" | ||
| 1800 | - [(set (match_operand:SI 0 "s_register_operand" "=r,r") | ||
| 1801 | - (match_operator:SI 1 "arm_comparison_operator" | ||
| 1802 | - [(match_operand:SI 2 "s_register_operand" "r,r") | ||
| 1803 | - (match_operand:SI 3 "arm_add_operand" "rI,L")])) | ||
| 1804 | - (clobber (reg:CC CC_REGNUM))] | ||
| 1805 | - "TARGET_THUMB2" | ||
| 1806 | - "* | ||
| 1807 | - if (operands[3] == const0_rtx) | ||
| 1808 | - { | ||
| 1809 | - if (GET_CODE (operands[1]) == LT) | ||
| 1810 | - return \"lsr\\t%0, %2, #31\"; | ||
| 1811 | - | ||
| 1812 | - if (GET_CODE (operands[1]) == GE) | ||
| 1813 | - return \"mvn\\t%0, %2\;lsr\\t%0, %0, #31\"; | ||
| 1814 | - | ||
| 1815 | - if (GET_CODE (operands[1]) == EQ) | ||
| 1816 | - return \"rsbs\\t%0, %2, #1\;it\\tcc\;movcc\\t%0, #0\"; | ||
| 1817 | - } | ||
| 1818 | - | ||
| 1819 | - if (GET_CODE (operands[1]) == NE) | ||
| 1820 | - { | ||
| 1821 | - if (which_alternative == 1) | ||
| 1822 | - return \"adds\\t%0, %2, #%n3\;it\\tne\;movne\\t%0, #1\"; | ||
| 1823 | - return \"subs\\t%0, %2, %3\;it\\tne\;movne\\t%0, #1\"; | ||
| 1824 | - } | ||
| 1825 | - if (which_alternative == 1) | ||
| 1826 | - output_asm_insn (\"cmn\\t%2, #%n3\", operands); | ||
| 1827 | - else | ||
| 1828 | - output_asm_insn (\"cmp\\t%2, %3\", operands); | ||
| 1829 | - return \"ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1\"; | ||
| 1830 | - " | ||
| 1831 | - [(set_attr "conds" "clob") | ||
| 1832 | - (set_attr "length" "14")] | ||
| 1833 | -) | ||
| 1834 | - | ||
| 1835 | (define_insn "*thumb2_cond_move" | ||
| 1836 | [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") | ||
| 1837 | (if_then_else:SI (match_operator 3 "equality_operator" | ||
| 1838 | |||
| 1839 | === added file 'gcc/testsuite/gcc.c-torture/execute/pr40657.c' | ||
| 1840 | --- old/gcc/testsuite/gcc.c-torture/execute/pr40657.c 1970-01-01 00:00:00 +0000 | ||
| 1841 | +++ new/gcc/testsuite/gcc.c-torture/execute/pr40657.c 2010-08-31 10:00:27 +0000 | ||
| 1842 | @@ -0,0 +1,23 @@ | ||
| 1843 | +/* Verify that that Thumb-1 epilogue size optimization does not clobber the | ||
| 1844 | + return value. */ | ||
| 1845 | + | ||
| 1846 | +long long v = 0x123456789abc; | ||
| 1847 | + | ||
| 1848 | +__attribute__((noinline)) void bar (int *x) | ||
| 1849 | +{ | ||
| 1850 | + asm volatile ("" : "=m" (x) ::); | ||
| 1851 | +} | ||
| 1852 | + | ||
| 1853 | +__attribute__((noinline)) long long foo() | ||
| 1854 | +{ | ||
| 1855 | + int x; | ||
| 1856 | + bar(&x); | ||
| 1857 | + return v; | ||
| 1858 | +} | ||
| 1859 | + | ||
| 1860 | +int main () | ||
| 1861 | +{ | ||
| 1862 | + if (foo () != v) | ||
| 1863 | + abort (); | ||
| 1864 | + exit (0); | ||
| 1865 | +} | ||
| 1866 | |||
| 1867 | === added file 'gcc/testsuite/gcc.target/arm/pr40657-1.c' | ||
| 1868 | --- old/gcc/testsuite/gcc.target/arm/pr40657-1.c 1970-01-01 00:00:00 +0000 | ||
| 1869 | +++ new/gcc/testsuite/gcc.target/arm/pr40657-1.c 2010-08-31 10:00:27 +0000 | ||
| 1870 | @@ -0,0 +1,13 @@ | ||
| 1871 | +/* { dg-options "-Os -march=armv5te -mthumb" } */ | ||
| 1872 | +/* { dg-require-effective-target arm_thumb1_ok } */ | ||
| 1873 | +/* { dg-final { scan-assembler "pop.*r1.*pc" } } */ | ||
| 1874 | +/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */ | ||
| 1875 | +/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */ | ||
| 1876 | + | ||
| 1877 | +extern void bar(int*); | ||
| 1878 | +int foo() | ||
| 1879 | +{ | ||
| 1880 | + int x; | ||
| 1881 | + bar(&x); | ||
| 1882 | + return x; | ||
| 1883 | +} | ||
| 1884 | |||
| 1885 | === added file 'gcc/testsuite/gcc.target/arm/pr40657-2.c' | ||
| 1886 | --- old/gcc/testsuite/gcc.target/arm/pr40657-2.c 1970-01-01 00:00:00 +0000 | ||
| 1887 | +++ new/gcc/testsuite/gcc.target/arm/pr40657-2.c 2010-08-31 10:00:27 +0000 | ||
| 1888 | @@ -0,0 +1,20 @@ | ||
| 1889 | +/* { dg-options "-Os -march=armv4t -mthumb" } */ | ||
| 1890 | +/* { dg-require-effective-target arm_thumb1_ok } */ | ||
| 1891 | +/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */ | ||
| 1892 | +/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */ | ||
| 1893 | + | ||
| 1894 | +/* Here, we test that if there's a pop of r[4567] in the epilogue, | ||
| 1895 | + add sp,sp,#12 is removed and replaced by three additional pops | ||
| 1896 | + of lower-numbered regs. */ | ||
| 1897 | + | ||
| 1898 | +extern void bar(int*); | ||
| 1899 | + | ||
| 1900 | +int t1, t2, t3, t4, t5; | ||
| 1901 | +int foo() | ||
| 1902 | +{ | ||
| 1903 | + int i,j,k,x = 0; | ||
| 1904 | + for (i = 0; i < t1; i++) | ||
| 1905 | + for (j = 0; j < t2; j++) | ||
| 1906 | + bar(&x); | ||
| 1907 | + return x; | ||
| 1908 | +} | ||
| 1909 | |||
| 1910 | === added file 'gcc/testsuite/gcc.target/arm/pr42172-1.c' | ||
| 1911 | --- old/gcc/testsuite/gcc.target/arm/pr42172-1.c 1970-01-01 00:00:00 +0000 | ||
| 1912 | +++ new/gcc/testsuite/gcc.target/arm/pr42172-1.c 2010-08-31 10:00:27 +0000 | ||
| 1913 | @@ -0,0 +1,19 @@ | ||
| 1914 | +/* { dg-options "-O2" } */ | ||
| 1915 | + | ||
| 1916 | +struct A { | ||
| 1917 | + unsigned int f1 : 3; | ||
| 1918 | + unsigned int f2 : 3; | ||
| 1919 | + unsigned int f3 : 1; | ||
| 1920 | + unsigned int f4 : 1; | ||
| 1921 | + | ||
| 1922 | +}; | ||
| 1923 | + | ||
| 1924 | +void init_A (struct A *this) | ||
| 1925 | +{ | ||
| 1926 | + this->f1 = 0; | ||
| 1927 | + this->f2 = 1; | ||
| 1928 | + this->f3 = 0; | ||
| 1929 | + this->f4 = 0; | ||
| 1930 | +} | ||
| 1931 | + | ||
| 1932 | +/* { dg-final { scan-assembler-times "ldr" 1 } } */ | ||
| 1933 | |||
| 1934 | === added file 'gcc/testsuite/gcc.target/arm/pr42835.c' | ||
| 1935 | --- old/gcc/testsuite/gcc.target/arm/pr42835.c 1970-01-01 00:00:00 +0000 | ||
| 1936 | +++ new/gcc/testsuite/gcc.target/arm/pr42835.c 2010-08-31 10:00:27 +0000 | ||
| 1937 | @@ -0,0 +1,12 @@ | ||
| 1938 | +/* { dg-do compile } */ | ||
| 1939 | +/* { dg-options "-mthumb -Os" } */ | ||
| 1940 | +/* { dg-require-effective-target arm_thumb2_ok } */ | ||
| 1941 | + | ||
| 1942 | +int foo(int *p, int i) | ||
| 1943 | +{ | ||
| 1944 | + return( (i < 0 && *p == 1) | ||
| 1945 | + || (i > 0 && *p == 2) ); | ||
| 1946 | +} | ||
| 1947 | + | ||
| 1948 | +/* { dg-final { scan-assembler-times "movne\[\\t \]*r.,\[\\t \]*#" 1 } } */ | ||
| 1949 | +/* { dg-final { scan-assembler-times "moveq\[\\t \]*r.,\[\\t \]*#" 1 } } */ | ||
| 1950 | |||
| 1951 | === added file 'gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c' | ||
| 1952 | --- old/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c 1970-01-01 00:00:00 +0000 | ||
| 1953 | +++ new/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c 2010-08-31 10:00:27 +0000 | ||
| 1954 | @@ -0,0 +1,15 @@ | ||
| 1955 | +/* { dg-do compile } */ | ||
| 1956 | +/* { dg-options "-mthumb -Os" } */ | ||
| 1957 | +/* { dg-require-effective-target arm_thumb1_ok } */ | ||
| 1958 | + | ||
| 1959 | +int ldrb(unsigned char* p) | ||
| 1960 | +{ | ||
| 1961 | + if (p[8] <= 0x7F) | ||
| 1962 | + return 2; | ||
| 1963 | + else | ||
| 1964 | + return 5; | ||
| 1965 | +} | ||
| 1966 | + | ||
| 1967 | + | ||
| 1968 | +/* { dg-final { scan-assembler "127" } } */ | ||
| 1969 | +/* { dg-final { scan-assembler "bhi" } } */ | ||
| 1970 | |||
| 1971 | === added file 'gcc/testsuite/gcc.target/arm/thumb-comparisons.c' | ||
| 1972 | --- old/gcc/testsuite/gcc.target/arm/thumb-comparisons.c 1970-01-01 00:00:00 +0000 | ||
| 1973 | +++ new/gcc/testsuite/gcc.target/arm/thumb-comparisons.c 2010-08-31 10:00:27 +0000 | ||
| 1974 | @@ -0,0 +1,18 @@ | ||
| 1975 | +/* { dg-do compile } */ | ||
| 1976 | +/* { dg-options "-mthumb -Os" } */ | ||
| 1977 | +/* { dg-require-effective-target arm_thumb1_ok } */ | ||
| 1978 | + | ||
| 1979 | +int foo(char ch) | ||
| 1980 | +{ | ||
| 1981 | + switch (ch) { | ||
| 1982 | + case '-': | ||
| 1983 | + case '?': | ||
| 1984 | + case '/': | ||
| 1985 | + case 99: | ||
| 1986 | + return 1; | ||
| 1987 | + default: | ||
| 1988 | + return 0; | ||
| 1989 | + } | ||
| 1990 | +} | ||
| 1991 | + | ||
| 1992 | +/* { dg-final { scan-assembler-times "cmp\[\\t \]*r.,\[\\t \]*#63" 1 } } */ | ||
| 1993 | |||
| 1994 | === added file 'gcc/testsuite/gcc.target/arm/thumb-stackframe.c' | ||
| 1995 | --- old/gcc/testsuite/gcc.target/arm/thumb-stackframe.c 1970-01-01 00:00:00 +0000 | ||
| 1996 | +++ new/gcc/testsuite/gcc.target/arm/thumb-stackframe.c 2010-08-31 10:00:27 +0000 | ||
| 1997 | @@ -0,0 +1,13 @@ | ||
| 1998 | +/* { dg-do compile } */ | ||
| 1999 | +/* { dg-options "-mthumb -Os" } */ | ||
| 2000 | +/* { dg-require-effective-target arm_thumb1_ok } */ | ||
| 2001 | + | ||
| 2002 | +extern void bar(int*); | ||
| 2003 | +int foo() | ||
| 2004 | +{ | ||
| 2005 | + int x; | ||
| 2006 | + bar(&x); | ||
| 2007 | + return x; | ||
| 2008 | +} | ||
| 2009 | + | ||
| 2010 | +/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp," } } */ | ||
| 2011 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch deleted file mode 100644 index b7b6d88a0..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch +++ /dev/null | |||
| @@ -1,2985 +0,0 @@ | |||
| 1 | 2010-08-31 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-04-14 Bernd Schmidt <bernds@codesourcery.com> | ||
| 6 | |||
| 7 | PR target/21803 | ||
| 8 | gcc/ | ||
| 9 | * ifcvt.c (cond_exec_process_if_block): Look for identical sequences | ||
| 10 | at the start and end of the then/else blocks, and omit them from the | ||
| 11 | conversion. | ||
| 12 | * cfgcleanup.c (flow_find_cross_jump): No longer static. Remove MODE | ||
| 13 | argument; all callers changed. Pass zero to old_insns_match_p instead. | ||
| 14 | (flow_find_head_matching_sequence): New function. | ||
| 15 | (old_insns_match_p): Check REG_EH_REGION notes for calls. | ||
| 16 | * basic-block.h (flow_find_cross_jump, | ||
| 17 | flow_find_head_matching_sequence): Declare functions. | ||
| 18 | |||
| 19 | gcc/testsuite/ | ||
| 20 | * gcc.target/arm/pr42496.c: New test. | ||
| 21 | |||
| 22 | 2010-04-22 Bernd Schmidt <bernds@codesourcery.com> | ||
| 23 | |||
| 24 | PR middle-end/29274 | ||
| 25 | gcc/ | ||
| 26 | * tree-pass.h (pass_optimize_widening_mul): Declare. | ||
| 27 | * tree-ssa-math-opts.c (execute_optimize_widening_mul, | ||
| 28 | gate_optimize_widening_mul): New static functions. | ||
| 29 | (pass_optimize_widening_mul): New. | ||
| 30 | * expr.c (expand_expr_real_2) <case WIDEN_MULT_EXPR>: New case. | ||
| 31 | <case MULT_EXPR>: Remove support for widening multiplies. | ||
| 32 | * tree.def (WIDEN_MULT_EXPR): Tweak comment. | ||
| 33 | * cfgexpand.c (expand_debug_expr) <case WIDEN_MULT_EXPR>: Use | ||
| 34 | simplify_gen_unary rather than directly building extensions. | ||
| 35 | * tree-cfg.c (verify_gimple_assign_binary): Add tests for | ||
| 36 | WIDEN_MULT_EXPR. | ||
| 37 | * expmed.c (expand_widening_mult): New function. | ||
| 38 | * passes.c (init_optimization_passes): Add pass_optimize_widening_mul. | ||
| 39 | * optabs.h (expand_widening_mult): Declare. | ||
| 40 | |||
| 41 | gcc/testsuite/ | ||
| 42 | * gcc.target/i386/wmul-1.c: New test. | ||
| 43 | * gcc.target/i386/wmul-2.c: New test. | ||
| 44 | * gcc.target/bfin/wmul-1.c: New test. | ||
| 45 | * gcc.target/bfin/wmul-2.c: New test. | ||
| 46 | * gcc.target/arm/wmul-1.c: New test. | ||
| 47 | * gcc.target/arm/wmul-2.c: New test. | ||
| 48 | |||
| 49 | 2010-04-24 Bernd Schmidt <bernds@codesourcery.com> | ||
| 50 | |||
| 51 | PR tree-optimization/41442 | ||
| 52 | gcc/ | ||
| 53 | * fold-const.c (merge_truthop_with_opposite_arm): New function. | ||
| 54 | (fold_binary_loc): Call it. | ||
| 55 | |||
| 56 | gcc/testsuite/ | ||
| 57 | * gcc.target/i386/pr41442.c: New test. | ||
| 58 | |||
| 59 | 2010-04-29 Bernd Schmidt <bernds@codesourcery.com> | ||
| 60 | |||
| 61 | PR target/42895 | ||
| 62 | gcc/ | ||
| 63 | * doc/tm.texi (ADJUST_REG_ALLOC_ORDER): Renamed from | ||
| 64 | ORDER_REGS_FOR_LOCAL_ALLOC. All instances of this macro changed. | ||
| 65 | (HONOR_REG_ALLOC_ORDER): Describe new macro. | ||
| 66 | * ira.c (setup_alloc_regs): Use ADJUST_REG_ALLOC_ORDER if defined. | ||
| 67 | * ira-color.c (assign_hard_reg): Take prologue/epilogue costs into | ||
| 68 | account only if HONOR_REG_ALLOC_ORDER is not defined. | ||
| 69 | * config/arm/arm.h (HONOR_REG_ALLOC_ORDER): Define. | ||
| 70 | * system.h (ORDER_REGS_FOR_LOCAL_ALLOC): Poison. | ||
| 71 | |||
| 72 | 2010-05-04 Mikael Pettersson <mikpe@it.uu.se> | ||
| 73 | |||
| 74 | PR bootstrap/43964 | ||
| 75 | gcc/ | ||
| 76 | * ira-color.c (assign_hard_reg): Declare rclass and add_cost | ||
| 77 | only if HONOR_REG_ALLOC_ORDER is not defined. | ||
| 78 | |||
| 79 | 2010-06-04 Bernd Schmidt <bernds@codesourcery.com> | ||
| 80 | |||
| 81 | PR rtl-optimization/39871 | ||
| 82 | PR rtl-optimization/40615 | ||
| 83 | PR rtl-optimization/42500 | ||
| 84 | PR rtl-optimization/42502 | ||
| 85 | gcc/ | ||
| 86 | * ira.c (init_reg_equiv_memory_loc: New function. | ||
| 87 | (ira): Call it twice. | ||
| 88 | * reload.h (calculate_elim_costs_all_insns): Declare. | ||
| 89 | * ira-costs.c: Include "reload.h". | ||
| 90 | (regno_equiv_gains): New static variable. | ||
| 91 | (init_costs): Allocate it. | ||
| 92 | (finish_costs): Free it. | ||
| 93 | (ira_costs): Call calculate_elim_costs_all_insns. | ||
| 94 | (find_costs_and_classes): Take estimated elimination costs | ||
| 95 | into account. | ||
| 96 | (ira_adjust_equiv_reg_cost): New function. | ||
| 97 | * ira.h (ira_adjust_equiv_reg_cost): Declare it. | ||
| 98 | * reload1.c (init_eliminable_invariants, free_reg_equiv, | ||
| 99 | elimination_costs_in_insn, note_reg_elim_costly): New static functions. | ||
| 100 | (elim_bb): New static variable. | ||
| 101 | (reload): Move code out of here into init_eliminable_invariants and | ||
| 102 | free_reg_equiv. Call them. | ||
| 103 | (calculate_elim_costs_all_insns): New function. | ||
| 104 | (eliminate_regs_1): Declare. Add extra arg FOR_COSTS; | ||
| 105 | all callers changed. If FOR_COSTS is true, don't call alter_reg, | ||
| 106 | but call note_reg_elim_costly if we turned a valid memory address | ||
| 107 | into an invalid one. | ||
| 108 | * Makefile.in (ira-costs.o): Depend on reload.h. | ||
| 109 | |||
| 110 | gcc/testsuite/ | ||
| 111 | * gcc.target/arm/eliminate.c: New test. | ||
| 112 | |||
| 113 | 2010-06-09 Bernd Schmidt <bernds@codesourcery.com> | ||
| 114 | |||
| 115 | gcc/ | ||
| 116 | * config/arm/arm.c (thumb2_reorg): New function. | ||
| 117 | (arm_reorg): Call it. | ||
| 118 | * config/arm/thumb2.md (define_peephole2 for flag clobbering | ||
| 119 | arithmetic operations): Delete. | ||
| 120 | |||
| 121 | 2010-06-12 Bernd Schmidt <bernds@codesourcery.com> | ||
| 122 | |||
| 123 | gcc/ | ||
| 124 | * config/arm/arm.c (thumb2_reorg): Fix errors in previous change. | ||
| 125 | |||
| 126 | 2010-06-17 Bernd Schmidt <bernds@codesourcery.com> | ||
| 127 | |||
| 128 | PR rtl-optimization/39871 | ||
| 129 | gcc/ | ||
| 130 | * reload1.c (init_eliminable_invariants): For flag_pic, disable | ||
| 131 | equivalences only for constants that aren't LEGITIMATE_PIC_OPERAND_P. | ||
| 132 | (function_invariant_p): Rule out a plus of frame or arg pointer with | ||
| 133 | a SYMBOL_REF. | ||
| 134 | * ira.c (find_reg_equiv_invariant_const): Likewise. | ||
| 135 | |||
| 136 | 2010-06-18 Eric Botcazou <ebotcazou@adacore.com> | ||
| 137 | |||
| 138 | PR rtl-optimization/40900 | ||
| 139 | gcc/ | ||
| 140 | * expr.c (expand_expr_real_1) <SSA_NAME>: Fix long line. Save the | ||
| 141 | original expression for later reuse. | ||
| 142 | <expand_decl_rtl>: Use promote_function_mode to compute the signedness | ||
| 143 | of the promoted RTL for a SSA_NAME on the LHS of a call statement. | ||
| 144 | |||
| 145 | 2010-06-18 Bernd Schmidt <bernds@codesourcery.com> | ||
| 146 | gcc/testsuite/ | ||
| 147 | * gcc.target/arm/pr40900.c: New test. | ||
| 148 | |||
| 149 | 2010-06-30 Bernd Schmidt <bernds@codesourcery.com> | ||
| 150 | |||
| 151 | PR tree-optimization/39799 | ||
| 152 | gcc/ | ||
| 153 | * tree-inline.c (remap_ssa_name): Initialize variable only if | ||
| 154 | SSA_NAME_OCCURS_IN_ABNORMAL_PHI. | ||
| 155 | * tree-ssa.c (warn_uninit): Avoid emitting an unnecessary message. | ||
| 156 | |||
| 157 | gcc/testsuite/ | ||
| 158 | * c-c++-common/uninit-17.c: New test. | ||
| 159 | |||
| 160 | 2010-07-25 Eric Botcazou <ebotcazou@adacore.com> | ||
| 161 | |||
| 162 | PR target/44484 | ||
| 163 | gcc/ | ||
| 164 | * config/sparc/predicates.md (memory_reg_operand): Delete. | ||
| 165 | * config/sparc/sync.md (sync_compare_and_swap): Minor tweaks. | ||
| 166 | (*sync_compare_and_swap): Encode the address form in the pattern. | ||
| 167 | (*sync_compare_and_swapdi_v8plus): Likewise. | ||
| 168 | |||
| 169 | 2010-08-29 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 170 | |||
| 171 | Backport from mainline: | ||
| 172 | |||
| 173 | === modified file 'gcc/Makefile.in' | ||
| 174 | Index: gcc-4_5-branch/gcc/Makefile.in | ||
| 175 | =================================================================== | ||
| 176 | --- gcc-4_5-branch.orig/gcc/Makefile.in 2012-03-06 12:11:29.000000000 -0800 | ||
| 177 | +++ gcc-4_5-branch/gcc/Makefile.in 2012-03-06 12:14:01.024439210 -0800 | ||
| 178 | @@ -3197,7 +3197,7 @@ | ||
| 179 | ira-costs.o: ira-costs.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ | ||
| 180 | hard-reg-set.h $(RTL_H) $(EXPR_H) $(TM_P_H) $(FLAGS_H) $(BASIC_BLOCK_H) \ | ||
| 181 | $(REGS_H) addresses.h insn-config.h $(RECOG_H) $(TOPLEV_H) $(TARGET_H) \ | ||
| 182 | - $(PARAMS_H) $(IRA_INT_H) | ||
| 183 | + $(PARAMS_H) $(IRA_INT_H) reload.h | ||
| 184 | ira-conflicts.o: ira-conflicts.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ | ||
| 185 | $(TARGET_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) \ | ||
| 186 | insn-config.h $(RECOG_H) $(BASIC_BLOCK_H) $(TOPLEV_H) $(TM_P_H) $(PARAMS_H) \ | ||
| 187 | Index: gcc-4_5-branch/gcc/basic-block.h | ||
| 188 | =================================================================== | ||
| 189 | --- gcc-4_5-branch.orig/gcc/basic-block.h 2012-03-06 12:11:33.000000000 -0800 | ||
| 190 | +++ gcc-4_5-branch/gcc/basic-block.h 2012-03-06 12:14:01.024439210 -0800 | ||
| 191 | @@ -894,6 +894,10 @@ | ||
| 192 | |||
| 193 | /* In cfgcleanup.c. */ | ||
| 194 | extern bool cleanup_cfg (int); | ||
| 195 | +extern int flow_find_cross_jump (basic_block, basic_block, rtx *, rtx *); | ||
| 196 | +extern int flow_find_head_matching_sequence (basic_block, basic_block, | ||
| 197 | + rtx *, rtx *, int); | ||
| 198 | + | ||
| 199 | extern bool delete_unreachable_blocks (void); | ||
| 200 | |||
| 201 | extern bool mark_dfs_back_edges (void); | ||
| 202 | Index: gcc-4_5-branch/gcc/cfgcleanup.c | ||
| 203 | =================================================================== | ||
| 204 | --- gcc-4_5-branch.orig/gcc/cfgcleanup.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 205 | +++ gcc-4_5-branch/gcc/cfgcleanup.c 2012-03-06 12:14:01.028439167 -0800 | ||
| 206 | @@ -68,7 +68,6 @@ | ||
| 207 | static bool try_crossjump_to_edge (int, edge, edge); | ||
| 208 | static bool try_crossjump_bb (int, basic_block); | ||
| 209 | static bool outgoing_edges_match (int, basic_block, basic_block); | ||
| 210 | -static int flow_find_cross_jump (int, basic_block, basic_block, rtx *, rtx *); | ||
| 211 | static bool old_insns_match_p (int, rtx, rtx); | ||
| 212 | |||
| 213 | static void merge_blocks_move_predecessor_nojumps (basic_block, basic_block); | ||
| 214 | @@ -977,13 +976,27 @@ | ||
| 215 | be filled that clobbers a parameter expected by the subroutine. | ||
| 216 | |||
| 217 | ??? We take the simple route for now and assume that if they're | ||
| 218 | - equal, they were constructed identically. */ | ||
| 219 | + equal, they were constructed identically. | ||
| 220 | |||
| 221 | - if (CALL_P (i1) | ||
| 222 | - && (!rtx_equal_p (CALL_INSN_FUNCTION_USAGE (i1), | ||
| 223 | + Also check for identical exception regions. */ | ||
| 224 | + | ||
| 225 | + if (CALL_P (i1)) | ||
| 226 | + { | ||
| 227 | + /* Ensure the same EH region. */ | ||
| 228 | + rtx n1 = find_reg_note (i1, REG_EH_REGION, 0); | ||
| 229 | + rtx n2 = find_reg_note (i2, REG_EH_REGION, 0); | ||
| 230 | + | ||
| 231 | + if (!n1 && n2) | ||
| 232 | + return false; | ||
| 233 | + | ||
| 234 | + if (n1 && (!n2 || XEXP (n1, 0) != XEXP (n2, 0))) | ||
| 235 | + return false; | ||
| 236 | + | ||
| 237 | + if (!rtx_equal_p (CALL_INSN_FUNCTION_USAGE (i1), | ||
| 238 | CALL_INSN_FUNCTION_USAGE (i2)) | ||
| 239 | - || SIBLING_CALL_P (i1) != SIBLING_CALL_P (i2))) | ||
| 240 | - return false; | ||
| 241 | + || SIBLING_CALL_P (i1) != SIBLING_CALL_P (i2)) | ||
| 242 | + return false; | ||
| 243 | + } | ||
| 244 | |||
| 245 | #ifdef STACK_REGS | ||
| 246 | /* If cross_jump_death_matters is not 0, the insn's mode | ||
| 247 | @@ -1022,6 +1035,29 @@ | ||
| 248 | return false; | ||
| 249 | } | ||
| 250 | |||
| 251 | +/* When comparing insns I1 and I2 in flow_find_cross_jump or | ||
| 252 | + flow_find_head_matching_sequence, ensure the notes match. */ | ||
| 253 | + | ||
| 254 | +static void | ||
| 255 | +merge_notes (rtx i1, rtx i2) | ||
| 256 | +{ | ||
| 257 | + /* If the merged insns have different REG_EQUAL notes, then | ||
| 258 | + remove them. */ | ||
| 259 | + rtx equiv1 = find_reg_equal_equiv_note (i1); | ||
| 260 | + rtx equiv2 = find_reg_equal_equiv_note (i2); | ||
| 261 | + | ||
| 262 | + if (equiv1 && !equiv2) | ||
| 263 | + remove_note (i1, equiv1); | ||
| 264 | + else if (!equiv1 && equiv2) | ||
| 265 | + remove_note (i2, equiv2); | ||
| 266 | + else if (equiv1 && equiv2 | ||
| 267 | + && !rtx_equal_p (XEXP (equiv1, 0), XEXP (equiv2, 0))) | ||
| 268 | + { | ||
| 269 | + remove_note (i1, equiv1); | ||
| 270 | + remove_note (i2, equiv2); | ||
| 271 | + } | ||
| 272 | +} | ||
| 273 | + | ||
| 274 | /* Look through the insns at the end of BB1 and BB2 and find the longest | ||
| 275 | sequence that are equivalent. Store the first insns for that sequence | ||
| 276 | in *F1 and *F2 and return the sequence length. | ||
| 277 | @@ -1029,9 +1065,8 @@ | ||
| 278 | To simplify callers of this function, if the blocks match exactly, | ||
| 279 | store the head of the blocks in *F1 and *F2. */ | ||
| 280 | |||
| 281 | -static int | ||
| 282 | -flow_find_cross_jump (int mode ATTRIBUTE_UNUSED, basic_block bb1, | ||
| 283 | - basic_block bb2, rtx *f1, rtx *f2) | ||
| 284 | +int | ||
| 285 | +flow_find_cross_jump (basic_block bb1, basic_block bb2, rtx *f1, rtx *f2) | ||
| 286 | { | ||
| 287 | rtx i1, i2, last1, last2, afterlast1, afterlast2; | ||
| 288 | int ninsns = 0; | ||
| 289 | @@ -1071,7 +1106,7 @@ | ||
| 290 | if (i1 == BB_HEAD (bb1) || i2 == BB_HEAD (bb2)) | ||
| 291 | break; | ||
| 292 | |||
| 293 | - if (!old_insns_match_p (mode, i1, i2)) | ||
| 294 | + if (!old_insns_match_p (0, i1, i2)) | ||
| 295 | break; | ||
| 296 | |||
| 297 | merge_memattrs (i1, i2); | ||
| 298 | @@ -1079,21 +1114,7 @@ | ||
| 299 | /* Don't begin a cross-jump with a NOTE insn. */ | ||
| 300 | if (INSN_P (i1)) | ||
| 301 | { | ||
| 302 | - /* If the merged insns have different REG_EQUAL notes, then | ||
| 303 | - remove them. */ | ||
| 304 | - rtx equiv1 = find_reg_equal_equiv_note (i1); | ||
| 305 | - rtx equiv2 = find_reg_equal_equiv_note (i2); | ||
| 306 | - | ||
| 307 | - if (equiv1 && !equiv2) | ||
| 308 | - remove_note (i1, equiv1); | ||
| 309 | - else if (!equiv1 && equiv2) | ||
| 310 | - remove_note (i2, equiv2); | ||
| 311 | - else if (equiv1 && equiv2 | ||
| 312 | - && !rtx_equal_p (XEXP (equiv1, 0), XEXP (equiv2, 0))) | ||
| 313 | - { | ||
| 314 | - remove_note (i1, equiv1); | ||
| 315 | - remove_note (i2, equiv2); | ||
| 316 | - } | ||
| 317 | + merge_notes (i1, i2); | ||
| 318 | |||
| 319 | afterlast1 = last1, afterlast2 = last2; | ||
| 320 | last1 = i1, last2 = i2; | ||
| 321 | @@ -1135,6 +1156,97 @@ | ||
| 322 | return ninsns; | ||
| 323 | } | ||
| 324 | |||
| 325 | +/* Like flow_find_cross_jump, except start looking for a matching sequence from | ||
| 326 | + the head of the two blocks. Do not include jumps at the end. | ||
| 327 | + If STOP_AFTER is nonzero, stop after finding that many matching | ||
| 328 | + instructions. */ | ||
| 329 | + | ||
| 330 | +int | ||
| 331 | +flow_find_head_matching_sequence (basic_block bb1, basic_block bb2, rtx *f1, | ||
| 332 | + rtx *f2, int stop_after) | ||
| 333 | +{ | ||
| 334 | + rtx i1, i2, last1, last2, beforelast1, beforelast2; | ||
| 335 | + int ninsns = 0; | ||
| 336 | + edge e; | ||
| 337 | + edge_iterator ei; | ||
| 338 | + int nehedges1 = 0, nehedges2 = 0; | ||
| 339 | + | ||
| 340 | + FOR_EACH_EDGE (e, ei, bb1->succs) | ||
| 341 | + if (e->flags & EDGE_EH) | ||
| 342 | + nehedges1++; | ||
| 343 | + FOR_EACH_EDGE (e, ei, bb2->succs) | ||
| 344 | + if (e->flags & EDGE_EH) | ||
| 345 | + nehedges2++; | ||
| 346 | + | ||
| 347 | + i1 = BB_HEAD (bb1); | ||
| 348 | + i2 = BB_HEAD (bb2); | ||
| 349 | + last1 = beforelast1 = last2 = beforelast2 = NULL_RTX; | ||
| 350 | + | ||
| 351 | + while (true) | ||
| 352 | + { | ||
| 353 | + | ||
| 354 | + /* Ignore notes. */ | ||
| 355 | + while (!NONDEBUG_INSN_P (i1) && i1 != BB_END (bb1)) | ||
| 356 | + i1 = NEXT_INSN (i1); | ||
| 357 | + | ||
| 358 | + while (!NONDEBUG_INSN_P (i2) && i2 != BB_END (bb2)) | ||
| 359 | + i2 = NEXT_INSN (i2); | ||
| 360 | + | ||
| 361 | + if (NOTE_P (i1) || NOTE_P (i2) | ||
| 362 | + || JUMP_P (i1) || JUMP_P (i2)) | ||
| 363 | + break; | ||
| 364 | + | ||
| 365 | + /* A sanity check to make sure we're not merging insns with different | ||
| 366 | + effects on EH. If only one of them ends a basic block, it shouldn't | ||
| 367 | + have an EH edge; if both end a basic block, there should be the same | ||
| 368 | + number of EH edges. */ | ||
| 369 | + if ((i1 == BB_END (bb1) && i2 != BB_END (bb2) | ||
| 370 | + && nehedges1 > 0) | ||
| 371 | + || (i2 == BB_END (bb2) && i1 != BB_END (bb1) | ||
| 372 | + && nehedges2 > 0) | ||
| 373 | + || (i1 == BB_END (bb1) && i2 == BB_END (bb2) | ||
| 374 | + && nehedges1 != nehedges2)) | ||
| 375 | + break; | ||
| 376 | + | ||
| 377 | + if (!old_insns_match_p (0, i1, i2)) | ||
| 378 | + break; | ||
| 379 | + | ||
| 380 | + merge_memattrs (i1, i2); | ||
| 381 | + | ||
| 382 | + /* Don't begin a cross-jump with a NOTE insn. */ | ||
| 383 | + if (INSN_P (i1)) | ||
| 384 | + { | ||
| 385 | + merge_notes (i1, i2); | ||
| 386 | + | ||
| 387 | + beforelast1 = last1, beforelast2 = last2; | ||
| 388 | + last1 = i1, last2 = i2; | ||
| 389 | + ninsns++; | ||
| 390 | + } | ||
| 391 | + | ||
| 392 | + if (i1 == BB_END (bb1) || i2 == BB_END (bb2) | ||
| 393 | + || (stop_after > 0 && ninsns == stop_after)) | ||
| 394 | + break; | ||
| 395 | + | ||
| 396 | + i1 = NEXT_INSN (i1); | ||
| 397 | + i2 = NEXT_INSN (i2); | ||
| 398 | + } | ||
| 399 | + | ||
| 400 | +#ifdef HAVE_cc0 | ||
| 401 | + /* Don't allow a compare to be shared by cross-jumping unless the insn | ||
| 402 | + after the compare is also shared. */ | ||
| 403 | + if (ninsns && reg_mentioned_p (cc0_rtx, last1) && sets_cc0_p (last1)) | ||
| 404 | + last1 = beforelast1, last2 = beforelast2, ninsns--; | ||
| 405 | +#endif | ||
| 406 | + | ||
| 407 | + if (ninsns) | ||
| 408 | + { | ||
| 409 | + *f1 = last1; | ||
| 410 | + *f2 = last2; | ||
| 411 | + } | ||
| 412 | + | ||
| 413 | + return ninsns; | ||
| 414 | +} | ||
| 415 | + | ||
| 416 | /* Return true iff outgoing edges of BB1 and BB2 match, together with | ||
| 417 | the branch instruction. This means that if we commonize the control | ||
| 418 | flow before end of the basic block, the semantic remains unchanged. | ||
| 419 | @@ -1503,7 +1615,7 @@ | ||
| 420 | return false; | ||
| 421 | |||
| 422 | /* ... and part the second. */ | ||
| 423 | - nmatch = flow_find_cross_jump (mode, src1, src2, &newpos1, &newpos2); | ||
| 424 | + nmatch = flow_find_cross_jump (src1, src2, &newpos1, &newpos2); | ||
| 425 | |||
| 426 | /* Don't proceed with the crossjump unless we found a sufficient number | ||
| 427 | of matching instructions or the 'from' block was totally matched | ||
| 428 | Index: gcc-4_5-branch/gcc/cfgexpand.c | ||
| 429 | =================================================================== | ||
| 430 | --- gcc-4_5-branch.orig/gcc/cfgexpand.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 431 | +++ gcc-4_5-branch/gcc/cfgexpand.c 2012-03-06 12:14:01.028439167 -0800 | ||
| 432 | @@ -3033,14 +3033,15 @@ | ||
| 433 | if (SCALAR_INT_MODE_P (GET_MODE (op0)) | ||
| 434 | && SCALAR_INT_MODE_P (mode)) | ||
| 435 | { | ||
| 436 | + enum machine_mode inner_mode = GET_MODE (op0); | ||
| 437 | if (TYPE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 0)))) | ||
| 438 | - op0 = gen_rtx_ZERO_EXTEND (mode, op0); | ||
| 439 | + op0 = simplify_gen_unary (ZERO_EXTEND, mode, op0, inner_mode); | ||
| 440 | else | ||
| 441 | - op0 = gen_rtx_SIGN_EXTEND (mode, op0); | ||
| 442 | + op0 = simplify_gen_unary (SIGN_EXTEND, mode, op0, inner_mode); | ||
| 443 | if (TYPE_UNSIGNED (TREE_TYPE (TREE_OPERAND (exp, 1)))) | ||
| 444 | - op1 = gen_rtx_ZERO_EXTEND (mode, op1); | ||
| 445 | + op1 = simplify_gen_unary (ZERO_EXTEND, mode, op1, inner_mode); | ||
| 446 | else | ||
| 447 | - op1 = gen_rtx_SIGN_EXTEND (mode, op1); | ||
| 448 | + op1 = simplify_gen_unary (SIGN_EXTEND, mode, op1, inner_mode); | ||
| 449 | return gen_rtx_MULT (mode, op0, op1); | ||
| 450 | } | ||
| 451 | return NULL; | ||
| 452 | Index: gcc-4_5-branch/gcc/config/arm/arm.c | ||
| 453 | =================================================================== | ||
| 454 | --- gcc-4_5-branch.orig/gcc/config/arm/arm.c 2012-03-06 12:11:35.000000000 -0800 | ||
| 455 | +++ gcc-4_5-branch/gcc/config/arm/arm.c 2012-03-06 12:14:01.032439183 -0800 | ||
| 456 | @@ -8096,8 +8096,6 @@ | ||
| 457 | static bool | ||
| 458 | xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) | ||
| 459 | { | ||
| 460 | - rtx i_pat, d_pat; | ||
| 461 | - | ||
| 462 | /* Some true dependencies can have a higher cost depending | ||
| 463 | on precisely how certain input operands are used. */ | ||
| 464 | if (REG_NOTE_KIND (link) == 0 | ||
| 465 | @@ -12146,6 +12144,60 @@ | ||
| 466 | return result; | ||
| 467 | } | ||
| 468 | |||
| 469 | +/* Convert instructions to their cc-clobbering variant if possible, since | ||
| 470 | + that allows us to use smaller encodings. */ | ||
| 471 | + | ||
| 472 | +static void | ||
| 473 | +thumb2_reorg (void) | ||
| 474 | +{ | ||
| 475 | + basic_block bb; | ||
| 476 | + regset_head live; | ||
| 477 | + | ||
| 478 | + INIT_REG_SET (&live); | ||
| 479 | + | ||
| 480 | + /* We are freeing block_for_insn in the toplev to keep compatibility | ||
| 481 | + with old MDEP_REORGS that are not CFG based. Recompute it now. */ | ||
| 482 | + compute_bb_for_insn (); | ||
| 483 | + df_analyze (); | ||
| 484 | + | ||
| 485 | + FOR_EACH_BB (bb) | ||
| 486 | + { | ||
| 487 | + rtx insn; | ||
| 488 | + COPY_REG_SET (&live, DF_LR_OUT (bb)); | ||
| 489 | + df_simulate_initialize_backwards (bb, &live); | ||
| 490 | + FOR_BB_INSNS_REVERSE (bb, insn) | ||
| 491 | + { | ||
| 492 | + if (NONJUMP_INSN_P (insn) | ||
| 493 | + && !REGNO_REG_SET_P (&live, CC_REGNUM)) | ||
| 494 | + { | ||
| 495 | + rtx pat = PATTERN (insn); | ||
| 496 | + if (GET_CODE (pat) == SET | ||
| 497 | + && low_register_operand (XEXP (pat, 0), SImode) | ||
| 498 | + && thumb_16bit_operator (XEXP (pat, 1), SImode) | ||
| 499 | + && low_register_operand (XEXP (XEXP (pat, 1), 0), SImode) | ||
| 500 | + && low_register_operand (XEXP (XEXP (pat, 1), 1), SImode)) | ||
| 501 | + { | ||
| 502 | + rtx dst = XEXP (pat, 0); | ||
| 503 | + rtx src = XEXP (pat, 1); | ||
| 504 | + rtx op0 = XEXP (src, 0); | ||
| 505 | + if (rtx_equal_p (dst, op0) | ||
| 506 | + || GET_CODE (src) == PLUS || GET_CODE (src) == MINUS) | ||
| 507 | + { | ||
| 508 | + rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM); | ||
| 509 | + rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg); | ||
| 510 | + rtvec vec = gen_rtvec (2, pat, clobber); | ||
| 511 | + PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); | ||
| 512 | + INSN_CODE (insn) = -1; | ||
| 513 | + } | ||
| 514 | + } | ||
| 515 | + } | ||
| 516 | + if (NONDEBUG_INSN_P (insn)) | ||
| 517 | + df_simulate_one_insn_backwards (bb, insn, &live); | ||
| 518 | + } | ||
| 519 | + } | ||
| 520 | + CLEAR_REG_SET (&live); | ||
| 521 | +} | ||
| 522 | + | ||
| 523 | /* Gcc puts the pool in the wrong place for ARM, since we can only | ||
| 524 | load addresses a limited distance around the pc. We do some | ||
| 525 | special munging to move the constant pool values to the correct | ||
| 526 | @@ -12157,6 +12209,9 @@ | ||
| 527 | HOST_WIDE_INT address = 0; | ||
| 528 | Mfix * fix; | ||
| 529 | |||
| 530 | + if (TARGET_THUMB2) | ||
| 531 | + thumb2_reorg (); | ||
| 532 | + | ||
| 533 | minipool_fix_head = minipool_fix_tail = NULL; | ||
| 534 | |||
| 535 | /* The first insn must always be a note, or the code below won't | ||
| 536 | Index: gcc-4_5-branch/gcc/config/arm/arm.h | ||
| 537 | =================================================================== | ||
| 538 | --- gcc-4_5-branch.orig/gcc/config/arm/arm.h 2012-03-06 12:11:33.000000000 -0800 | ||
| 539 | +++ gcc-4_5-branch/gcc/config/arm/arm.h 2012-03-06 12:14:01.032439183 -0800 | ||
| 540 | @@ -1133,7 +1133,11 @@ | ||
| 541 | } | ||
| 542 | |||
| 543 | /* Use different register alloc ordering for Thumb. */ | ||
| 544 | -#define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc () | ||
| 545 | +#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () | ||
| 546 | + | ||
| 547 | +/* Tell IRA to use the order we define rather than messing it up with its | ||
| 548 | + own cost calculations. */ | ||
| 549 | +#define HONOR_REG_ALLOC_ORDER | ||
| 550 | |||
| 551 | /* Interrupt functions can only use registers that have already been | ||
| 552 | saved by the prologue, even if they would normally be | ||
| 553 | Index: gcc-4_5-branch/gcc/config/arm/arm.md | ||
| 554 | =================================================================== | ||
| 555 | --- gcc-4_5-branch.orig/gcc/config/arm/arm.md 2012-03-06 12:11:35.000000000 -0800 | ||
| 556 | +++ gcc-4_5-branch/gcc/config/arm/arm.md 2012-03-06 12:14:01.036439231 -0800 | ||
| 557 | @@ -4074,7 +4074,7 @@ | ||
| 558 | |||
| 559 | (define_split | ||
| 560 | [(set (match_operand:SI 0 "register_operand" "") | ||
| 561 | - (zero_extend:SI (match_operand:HI 1 "register_operand" "l,m")))] | ||
| 562 | + (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] | ||
| 563 | "!TARGET_THUMB2 && !arm_arch6" | ||
| 564 | [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) | ||
| 565 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))] | ||
| 566 | Index: gcc-4_5-branch/gcc/config/arm/thumb2.md | ||
| 567 | =================================================================== | ||
| 568 | --- gcc-4_5-branch.orig/gcc/config/arm/thumb2.md 2012-03-06 12:11:35.000000000 -0800 | ||
| 569 | +++ gcc-4_5-branch/gcc/config/arm/thumb2.md 2012-03-06 12:14:01.036439231 -0800 | ||
| 570 | @@ -1046,29 +1046,6 @@ | ||
| 571 | }" | ||
| 572 | ) | ||
| 573 | |||
| 574 | -;; Peepholes and insns for 16-bit flag clobbering instructions. | ||
| 575 | -;; The conditional forms of these instructions do not clobber CC. | ||
| 576 | -;; However by the time peepholes are run it is probably too late to do | ||
| 577 | -;; anything useful with this information. | ||
| 578 | -(define_peephole2 | ||
| 579 | - [(set (match_operand:SI 0 "low_register_operand" "") | ||
| 580 | - (match_operator:SI 3 "thumb_16bit_operator" | ||
| 581 | - [(match_operand:SI 1 "low_register_operand" "") | ||
| 582 | - (match_operand:SI 2 "low_register_operand" "")]))] | ||
| 583 | - "TARGET_THUMB2 | ||
| 584 | - && (rtx_equal_p(operands[0], operands[1]) | ||
| 585 | - || GET_CODE(operands[3]) == PLUS | ||
| 586 | - || GET_CODE(operands[3]) == MINUS) | ||
| 587 | - && peep2_regno_dead_p(0, CC_REGNUM)" | ||
| 588 | - [(parallel | ||
| 589 | - [(set (match_dup 0) | ||
| 590 | - (match_op_dup 3 | ||
| 591 | - [(match_dup 1) | ||
| 592 | - (match_dup 2)])) | ||
| 593 | - (clobber (reg:CC CC_REGNUM))])] | ||
| 594 | - "" | ||
| 595 | -) | ||
| 596 | - | ||
| 597 | (define_insn "*thumb2_alusi3_short" | ||
| 598 | [(set (match_operand:SI 0 "s_register_operand" "=l") | ||
| 599 | (match_operator:SI 3 "thumb_16bit_operator" | ||
| 600 | Index: gcc-4_5-branch/gcc/config/avr/avr.h | ||
| 601 | =================================================================== | ||
| 602 | --- gcc-4_5-branch.orig/gcc/config/avr/avr.h 2012-03-06 11:53:21.000000000 -0800 | ||
| 603 | +++ gcc-4_5-branch/gcc/config/avr/avr.h 2012-03-06 12:14:01.036439231 -0800 | ||
| 604 | @@ -232,7 +232,7 @@ | ||
| 605 | 32,33,34,35 \ | ||
| 606 | } | ||
| 607 | |||
| 608 | -#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | ||
| 609 | +#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () | ||
| 610 | |||
| 611 | |||
| 612 | #define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | ||
| 613 | Index: gcc-4_5-branch/gcc/config/i386/i386.h | ||
| 614 | =================================================================== | ||
| 615 | --- gcc-4_5-branch.orig/gcc/config/i386/i386.h 2012-03-06 11:53:19.000000000 -0800 | ||
| 616 | +++ gcc-4_5-branch/gcc/config/i386/i386.h 2012-03-06 12:14:01.036439231 -0800 | ||
| 617 | @@ -955,7 +955,7 @@ | ||
| 618 | registers listed in CALL_USED_REGISTERS, keeping the others | ||
| 619 | available for storage of persistent values. | ||
| 620 | |||
| 621 | - The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, | ||
| 622 | + The ADJUST_REG_ALLOC_ORDER actually overwrite the order, | ||
| 623 | so this is just empty initializer for array. */ | ||
| 624 | |||
| 625 | #define REG_ALLOC_ORDER \ | ||
| 626 | @@ -964,11 +964,11 @@ | ||
| 627 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | ||
| 628 | 48, 49, 50, 51, 52 } | ||
| 629 | |||
| 630 | -/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order | ||
| 631 | +/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order | ||
| 632 | to be rearranged based on a particular function. When using sse math, | ||
| 633 | we want to allocate SSE before x87 registers and vice versa. */ | ||
| 634 | |||
| 635 | -#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () | ||
| 636 | +#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () | ||
| 637 | |||
| 638 | |||
| 639 | #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) | ||
| 640 | Index: gcc-4_5-branch/gcc/config/mips/mips.h | ||
| 641 | =================================================================== | ||
| 642 | --- gcc-4_5-branch.orig/gcc/config/mips/mips.h 2012-03-06 11:53:28.000000000 -0800 | ||
| 643 | +++ gcc-4_5-branch/gcc/config/mips/mips.h 2012-03-06 12:14:01.040439261 -0800 | ||
| 644 | @@ -2059,12 +2059,12 @@ | ||
| 645 | 182,183,184,185,186,187 \ | ||
| 646 | } | ||
| 647 | |||
| 648 | -/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order | ||
| 649 | +/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order | ||
| 650 | to be rearranged based on a particular function. On the mips16, we | ||
| 651 | want to allocate $24 (T_REG) before other registers for | ||
| 652 | instructions for which it is possible. */ | ||
| 653 | |||
| 654 | -#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc () | ||
| 655 | +#define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc () | ||
| 656 | |||
| 657 | /* True if VALUE is an unsigned 6-bit number. */ | ||
| 658 | |||
| 659 | Index: gcc-4_5-branch/gcc/config/picochip/picochip.h | ||
| 660 | =================================================================== | ||
| 661 | --- gcc-4_5-branch.orig/gcc/config/picochip/picochip.h 2012-03-06 11:53:26.000000000 -0800 | ||
| 662 | +++ gcc-4_5-branch/gcc/config/picochip/picochip.h 2012-03-06 12:14:01.040439261 -0800 | ||
| 663 | @@ -261,7 +261,7 @@ | ||
| 664 | /* We can dynamically change the REG_ALLOC_ORDER using the following hook. | ||
| 665 | It would be desirable to change it for leaf functions so we can put | ||
| 666 | r12 at the end of this list.*/ | ||
| 667 | -#define ORDER_REGS_FOR_LOCAL_ALLOC picochip_order_regs_for_local_alloc () | ||
| 668 | +#define ADJUST_REG_ALLOC_ORDER picochip_order_regs_for_local_alloc () | ||
| 669 | |||
| 670 | /* How Values Fit in Registers */ | ||
| 671 | |||
| 672 | Index: gcc-4_5-branch/gcc/config/sparc/predicates.md | ||
| 673 | =================================================================== | ||
| 674 | --- gcc-4_5-branch.orig/gcc/config/sparc/predicates.md 2012-03-06 11:53:17.000000000 -0800 | ||
| 675 | +++ gcc-4_5-branch/gcc/config/sparc/predicates.md 2012-03-06 12:14:01.040439261 -0800 | ||
| 676 | @@ -1,5 +1,5 @@ | ||
| 677 | ;; Predicate definitions for SPARC. | ||
| 678 | -;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc. | ||
| 679 | +;; Copyright (C) 2005, 2007, 2008, 2010 Free Software Foundation, Inc. | ||
| 680 | ;; | ||
| 681 | ;; This file is part of GCC. | ||
| 682 | ;; | ||
| 683 | @@ -473,9 +473,3 @@ | ||
| 684 | ;; and (xor ... (not ...)) to (not (xor ...)). */ | ||
| 685 | (define_predicate "cc_arith_not_operator" | ||
| 686 | (match_code "and,ior")) | ||
| 687 | - | ||
| 688 | -;; Return true if OP is memory operand with just [%reg] addressing mode. | ||
| 689 | -(define_predicate "memory_reg_operand" | ||
| 690 | - (and (match_code "mem") | ||
| 691 | - (and (match_operand 0 "memory_operand") | ||
| 692 | - (match_test "REG_P (XEXP (op, 0))")))) | ||
| 693 | Index: gcc-4_5-branch/gcc/config/sparc/sparc.h | ||
| 694 | =================================================================== | ||
| 695 | --- gcc-4_5-branch.orig/gcc/config/sparc/sparc.h 2012-03-06 11:53:17.000000000 -0800 | ||
| 696 | +++ gcc-4_5-branch/gcc/config/sparc/sparc.h 2012-03-06 12:14:01.040439261 -0800 | ||
| 697 | @@ -1188,7 +1188,7 @@ | ||
| 698 | 96, 97, 98, 99, /* %fcc0-3 */ \ | ||
| 699 | 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ | ||
| 700 | |||
| 701 | -#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | ||
| 702 | +#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () | ||
| 703 | |||
| 704 | extern char sparc_leaf_regs[]; | ||
| 705 | #define LEAF_REGISTERS sparc_leaf_regs | ||
| 706 | Index: gcc-4_5-branch/gcc/config/sparc/sync.md | ||
| 707 | =================================================================== | ||
| 708 | --- gcc-4_5-branch.orig/gcc/config/sparc/sync.md 2012-03-06 11:53:17.000000000 -0800 | ||
| 709 | +++ gcc-4_5-branch/gcc/config/sparc/sync.md 2012-03-06 12:14:01.040439261 -0800 | ||
| 710 | @@ -1,5 +1,5 @@ | ||
| 711 | ;; GCC machine description for SPARC synchronization instructions. | ||
| 712 | -;; Copyright (C) 2005, 2007, 2009 | ||
| 713 | +;; Copyright (C) 2005, 2007, 2009, 2010 | ||
| 714 | ;; Free Software Foundation, Inc. | ||
| 715 | ;; | ||
| 716 | ;; This file is part of GCC. | ||
| 717 | @@ -62,7 +62,7 @@ | ||
| 718 | |||
| 719 | (define_expand "sync_compare_and_swap<mode>" | ||
| 720 | [(parallel | ||
| 721 | - [(set (match_operand:I48MODE 0 "register_operand" "=r") | ||
| 722 | + [(set (match_operand:I48MODE 0 "register_operand" "") | ||
| 723 | (match_operand:I48MODE 1 "memory_operand" "")) | ||
| 724 | (set (match_dup 1) | ||
| 725 | (unspec_volatile:I48MODE | ||
| 726 | @@ -71,7 +71,7 @@ | ||
| 727 | UNSPECV_CAS))])] | ||
| 728 | "TARGET_V9" | ||
| 729 | { | ||
| 730 | - if (! REG_P (XEXP (operands[1], 0))) | ||
| 731 | + if (!REG_P (XEXP (operands[1], 0))) | ||
| 732 | { | ||
| 733 | rtx addr = force_reg (Pmode, XEXP (operands[1], 0)); | ||
| 734 | operands[1] = replace_equiv_address (operands[1], addr); | ||
| 735 | @@ -81,20 +81,20 @@ | ||
| 736 | |||
| 737 | (define_insn "*sync_compare_and_swap<mode>" | ||
| 738 | [(set (match_operand:I48MODE 0 "register_operand" "=r") | ||
| 739 | - (match_operand:I48MODE 1 "memory_reg_operand" "+m")) | ||
| 740 | - (set (match_dup 1) | ||
| 741 | + (mem:I48MODE (match_operand 1 "register_operand" "r"))) | ||
| 742 | + (set (mem:I48MODE (match_dup 1)) | ||
| 743 | (unspec_volatile:I48MODE | ||
| 744 | [(match_operand:I48MODE 2 "register_operand" "r") | ||
| 745 | (match_operand:I48MODE 3 "register_operand" "0")] | ||
| 746 | UNSPECV_CAS))] | ||
| 747 | "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)" | ||
| 748 | - "cas<modesuffix>\t%1, %2, %0" | ||
| 749 | + "cas<modesuffix>\t[%1], %2, %0" | ||
| 750 | [(set_attr "type" "multi")]) | ||
| 751 | |||
| 752 | (define_insn "*sync_compare_and_swapdi_v8plus" | ||
| 753 | [(set (match_operand:DI 0 "register_operand" "=h") | ||
| 754 | - (match_operand:DI 1 "memory_reg_operand" "+m")) | ||
| 755 | - (set (match_dup 1) | ||
| 756 | + (mem:DI (match_operand 1 "register_operand" "r"))) | ||
| 757 | + (set (mem:DI (match_dup 1)) | ||
| 758 | (unspec_volatile:DI | ||
| 759 | [(match_operand:DI 2 "register_operand" "h") | ||
| 760 | (match_operand:DI 3 "register_operand" "0")] | ||
| 761 | @@ -109,7 +109,7 @@ | ||
| 762 | output_asm_insn ("srl\t%L2, 0, %L2", operands); | ||
| 763 | output_asm_insn ("sllx\t%H2, 32, %H3", operands); | ||
| 764 | output_asm_insn ("or\t%L2, %H3, %H3", operands); | ||
| 765 | - output_asm_insn ("casx\t%1, %H3, %L3", operands); | ||
| 766 | + output_asm_insn ("casx\t[%1], %H3, %L3", operands); | ||
| 767 | return "srlx\t%L3, 32, %H3"; | ||
| 768 | } | ||
| 769 | [(set_attr "type" "multi") | ||
| 770 | Index: gcc-4_5-branch/gcc/config/xtensa/xtensa.h | ||
| 771 | =================================================================== | ||
| 772 | --- gcc-4_5-branch.orig/gcc/config/xtensa/xtensa.h 2012-03-06 11:53:21.000000000 -0800 | ||
| 773 | +++ gcc-4_5-branch/gcc/config/xtensa/xtensa.h 2012-03-06 12:14:01.040439261 -0800 | ||
| 774 | @@ -286,7 +286,7 @@ | ||
| 775 | incoming argument in a2 is live throughout the function and | ||
| 776 | local-alloc decides to use a2, then the incoming argument must | ||
| 777 | either be spilled or copied to another register. To get around | ||
| 778 | - this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine | ||
| 779 | + this, we define ADJUST_REG_ALLOC_ORDER to redefine | ||
| 780 | reg_alloc_order for leaf functions such that lowest numbered | ||
| 781 | registers are used first with the exception that the incoming | ||
| 782 | argument registers are not used until after other register choices | ||
| 783 | @@ -300,7 +300,7 @@ | ||
| 784 | 35, \ | ||
| 785 | } | ||
| 786 | |||
| 787 | -#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | ||
| 788 | +#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () | ||
| 789 | |||
| 790 | /* For Xtensa, the only point of this is to prevent GCC from otherwise | ||
| 791 | giving preference to call-used registers. To minimize window | ||
| 792 | Index: gcc-4_5-branch/gcc/doc/tm.texi | ||
| 793 | =================================================================== | ||
| 794 | --- gcc-4_5-branch.orig/gcc/doc/tm.texi 2012-03-06 12:11:33.000000000 -0800 | ||
| 795 | +++ gcc-4_5-branch/gcc/doc/tm.texi 2012-03-06 12:14:01.044439265 -0800 | ||
| 796 | @@ -2093,7 +2093,7 @@ | ||
| 797 | the highest numbered allocable register first. | ||
| 798 | @end defmac | ||
| 799 | |||
| 800 | -@defmac ORDER_REGS_FOR_LOCAL_ALLOC | ||
| 801 | +@defmac ADJUST_REG_ALLOC_ORDER | ||
| 802 | A C statement (sans semicolon) to choose the order in which to allocate | ||
| 803 | hard registers for pseudo-registers local to a basic block. | ||
| 804 | |||
| 805 | @@ -2107,6 +2107,15 @@ | ||
| 806 | On most machines, it is not necessary to define this macro. | ||
| 807 | @end defmac | ||
| 808 | |||
| 809 | +@defmac HONOR_REG_ALLOC_ORDER | ||
| 810 | +Normally, IRA tries to estimate the costs for saving a register in the | ||
| 811 | +prologue and restoring it in the epilogue. This discourages it from | ||
| 812 | +using call-saved registers. If a machine wants to ensure that IRA | ||
| 813 | +allocates registers in the order given by REG_ALLOC_ORDER even if some | ||
| 814 | +call-saved registers appear earlier than call-used ones, this macro | ||
| 815 | +should be defined. | ||
| 816 | +@end defmac | ||
| 817 | + | ||
| 818 | @defmac IRA_HARD_REGNO_ADD_COST_MULTIPLIER (@var{regno}) | ||
| 819 | In some case register allocation order is not enough for the | ||
| 820 | Integrated Register Allocator (@acronym{IRA}) to generate a good code. | ||
| 821 | Index: gcc-4_5-branch/gcc/expmed.c | ||
| 822 | =================================================================== | ||
| 823 | --- gcc-4_5-branch.orig/gcc/expmed.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 824 | +++ gcc-4_5-branch/gcc/expmed.c 2012-03-06 12:14:01.044439265 -0800 | ||
| 825 | @@ -3255,6 +3255,55 @@ | ||
| 826 | gcc_assert (op0); | ||
| 827 | return op0; | ||
| 828 | } | ||
| 829 | + | ||
| 830 | +/* Perform a widening multiplication and return an rtx for the result. | ||
| 831 | + MODE is mode of value; OP0 and OP1 are what to multiply (rtx's); | ||
| 832 | + TARGET is a suggestion for where to store the result (an rtx). | ||
| 833 | + THIS_OPTAB is the optab we should use, it must be either umul_widen_optab | ||
| 834 | + or smul_widen_optab. | ||
| 835 | + | ||
| 836 | + We check specially for a constant integer as OP1, comparing the | ||
| 837 | + cost of a widening multiply against the cost of a sequence of shifts | ||
| 838 | + and adds. */ | ||
| 839 | + | ||
| 840 | +rtx | ||
| 841 | +expand_widening_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, | ||
| 842 | + int unsignedp, optab this_optab) | ||
| 843 | +{ | ||
| 844 | + bool speed = optimize_insn_for_speed_p (); | ||
| 845 | + | ||
| 846 | + if (CONST_INT_P (op1) | ||
| 847 | + && (INTVAL (op1) >= 0 | ||
| 848 | + || GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)) | ||
| 849 | + { | ||
| 850 | + HOST_WIDE_INT coeff = INTVAL (op1); | ||
| 851 | + int max_cost; | ||
| 852 | + enum mult_variant variant; | ||
| 853 | + struct algorithm algorithm; | ||
| 854 | + | ||
| 855 | + /* Special case powers of two. */ | ||
| 856 | + if (EXACT_POWER_OF_2_OR_ZERO_P (coeff)) | ||
| 857 | + { | ||
| 858 | + op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab); | ||
| 859 | + return expand_shift (LSHIFT_EXPR, mode, op0, | ||
| 860 | + build_int_cst (NULL_TREE, floor_log2 (coeff)), | ||
| 861 | + target, unsignedp); | ||
| 862 | + } | ||
| 863 | + | ||
| 864 | + /* Exclude cost of op0 from max_cost to match the cost | ||
| 865 | + calculation of the synth_mult. */ | ||
| 866 | + max_cost = mul_widen_cost[speed][mode]; | ||
| 867 | + if (choose_mult_variant (mode, coeff, &algorithm, &variant, | ||
| 868 | + max_cost)) | ||
| 869 | + { | ||
| 870 | + op0 = convert_to_mode (mode, op0, this_optab == umul_widen_optab); | ||
| 871 | + return expand_mult_const (mode, op0, coeff, target, | ||
| 872 | + &algorithm, variant); | ||
| 873 | + } | ||
| 874 | + } | ||
| 875 | + return expand_binop (mode, this_optab, op0, op1, target, | ||
| 876 | + unsignedp, OPTAB_LIB_WIDEN); | ||
| 877 | +} | ||
| 878 | |||
| 879 | /* Return the smallest n such that 2**n >= X. */ | ||
| 880 | |||
| 881 | Index: gcc-4_5-branch/gcc/expr.c | ||
| 882 | =================================================================== | ||
| 883 | --- gcc-4_5-branch.orig/gcc/expr.c 2012-03-06 12:11:34.000000000 -0800 | ||
| 884 | +++ gcc-4_5-branch/gcc/expr.c 2012-03-06 12:46:21.548533151 -0800 | ||
| 885 | @@ -7345,7 +7345,6 @@ | ||
| 886 | optab this_optab; | ||
| 887 | rtx subtarget, original_target; | ||
| 888 | int ignore; | ||
| 889 | - tree subexp0, subexp1; | ||
| 890 | bool reduce_bit_field; | ||
| 891 | gimple subexp0_def, subexp1_def; | ||
| 892 | tree top0, top1; | ||
| 893 | @@ -7800,13 +7799,7 @@ | ||
| 894 | |||
| 895 | goto binop2; | ||
| 896 | |||
| 897 | - case MULT_EXPR: | ||
| 898 | - /* If this is a fixed-point operation, then we cannot use the code | ||
| 899 | - below because "expand_mult" doesn't support sat/no-sat fixed-point | ||
| 900 | - multiplications. */ | ||
| 901 | - if (ALL_FIXED_POINT_MODE_P (mode)) | ||
| 902 | - goto binop; | ||
| 903 | - | ||
| 904 | + case WIDEN_MULT_EXPR: | ||
| 905 | /* If first operand is constant, swap them. | ||
| 906 | Thus the following special case checks need only | ||
| 907 | check the second operand. */ | ||
| 908 | @@ -7817,96 +7810,35 @@ | ||
| 909 | treeop1 = t1; | ||
| 910 | } | ||
| 911 | |||
| 912 | - /* Attempt to return something suitable for generating an | ||
| 913 | - indexed address, for machines that support that. */ | ||
| 914 | - | ||
| 915 | - if (modifier == EXPAND_SUM && mode == ptr_mode | ||
| 916 | - && host_integerp (treeop1, 0)) | ||
| 917 | - { | ||
| 918 | - tree exp1 = treeop1; | ||
| 919 | - | ||
| 920 | - op0 = expand_expr (treeop0, subtarget, VOIDmode, | ||
| 921 | - EXPAND_SUM); | ||
| 922 | - | ||
| 923 | - if (!REG_P (op0)) | ||
| 924 | - op0 = force_operand (op0, NULL_RTX); | ||
| 925 | - if (!REG_P (op0)) | ||
| 926 | - op0 = copy_to_mode_reg (mode, op0); | ||
| 927 | - | ||
| 928 | - return REDUCE_BIT_FIELD (gen_rtx_MULT (mode, op0, | ||
| 929 | - gen_int_mode (tree_low_cst (exp1, 0), | ||
| 930 | - TYPE_MODE (TREE_TYPE (exp1))))); | ||
| 931 | - } | ||
| 932 | - | ||
| 933 | - if (modifier == EXPAND_STACK_PARM) | ||
| 934 | - target = 0; | ||
| 935 | - | ||
| 936 | - /* Check for multiplying things that have been extended | ||
| 937 | - from a narrower type. If this machine supports multiplying | ||
| 938 | - in that narrower type with a result in the desired type, | ||
| 939 | - do it that way, and avoid the explicit type-conversion. */ | ||
| 940 | - | ||
| 941 | - subexp0 = treeop0; | ||
| 942 | - subexp1 = treeop1; | ||
| 943 | - subexp0_def = get_def_for_expr (subexp0, NOP_EXPR); | ||
| 944 | - subexp1_def = get_def_for_expr (subexp1, NOP_EXPR); | ||
| 945 | - top0 = top1 = NULL_TREE; | ||
| 946 | - | ||
| 947 | /* First, check if we have a multiplication of one signed and one | ||
| 948 | unsigned operand. */ | ||
| 949 | - if (subexp0_def | ||
| 950 | - && (top0 = gimple_assign_rhs1 (subexp0_def)) | ||
| 951 | - && subexp1_def | ||
| 952 | - && (top1 = gimple_assign_rhs1 (subexp1_def)) | ||
| 953 | - && TREE_CODE (type) == INTEGER_TYPE | ||
| 954 | - && (TYPE_PRECISION (TREE_TYPE (top0)) | ||
| 955 | - < TYPE_PRECISION (TREE_TYPE (subexp0))) | ||
| 956 | - && (TYPE_PRECISION (TREE_TYPE (top0)) | ||
| 957 | - == TYPE_PRECISION (TREE_TYPE (top1))) | ||
| 958 | - && (TYPE_UNSIGNED (TREE_TYPE (top0)) | ||
| 959 | - != TYPE_UNSIGNED (TREE_TYPE (top1)))) | ||
| 960 | + if (TREE_CODE (treeop1) != INTEGER_CST | ||
| 961 | + && (TYPE_UNSIGNED (TREE_TYPE (treeop0)) | ||
| 962 | + != TYPE_UNSIGNED (TREE_TYPE (treeop1)))) | ||
| 963 | { | ||
| 964 | - enum machine_mode innermode | ||
| 965 | - = TYPE_MODE (TREE_TYPE (top0)); | ||
| 966 | + enum machine_mode innermode = TYPE_MODE (TREE_TYPE (treeop0)); | ||
| 967 | this_optab = usmul_widen_optab; | ||
| 968 | - if (mode == GET_MODE_WIDER_MODE (innermode)) | ||
| 969 | + if (mode == GET_MODE_2XWIDER_MODE (innermode)) | ||
| 970 | { | ||
| 971 | if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing) | ||
| 972 | { | ||
| 973 | - if (TYPE_UNSIGNED (TREE_TYPE (top0))) | ||
| 974 | - expand_operands (top0, top1, NULL_RTX, &op0, &op1, | ||
| 975 | + if (TYPE_UNSIGNED (TREE_TYPE (treeop0))) | ||
| 976 | + expand_operands (treeop0, treeop1, subtarget, &op0, &op1, | ||
| 977 | EXPAND_NORMAL); | ||
| 978 | else | ||
| 979 | - expand_operands (top0, top1, NULL_RTX, &op1, &op0, | ||
| 980 | + expand_operands (treeop0, treeop1, subtarget, &op1, &op0, | ||
| 981 | EXPAND_NORMAL); | ||
| 982 | - | ||
| 983 | goto binop3; | ||
| 984 | } | ||
| 985 | } | ||
| 986 | } | ||
| 987 | - /* Check for a multiplication with matching signedness. If | ||
| 988 | - valid, TOP0 and TOP1 were set in the previous if | ||
| 989 | - condition. */ | ||
| 990 | - else if (top0 | ||
| 991 | - && TREE_CODE (type) == INTEGER_TYPE | ||
| 992 | - && (TYPE_PRECISION (TREE_TYPE (top0)) | ||
| 993 | - < TYPE_PRECISION (TREE_TYPE (subexp0))) | ||
| 994 | - && ((TREE_CODE (subexp1) == INTEGER_CST | ||
| 995 | - && int_fits_type_p (subexp1, TREE_TYPE (top0)) | ||
| 996 | - /* Don't use a widening multiply if a shift will do. */ | ||
| 997 | - && ((GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (subexp1))) | ||
| 998 | - > HOST_BITS_PER_WIDE_INT) | ||
| 999 | - || exact_log2 (TREE_INT_CST_LOW (subexp1)) < 0)) | ||
| 1000 | - || | ||
| 1001 | - (top1 | ||
| 1002 | - && (TYPE_PRECISION (TREE_TYPE (top1)) | ||
| 1003 | - == TYPE_PRECISION (TREE_TYPE (top0)) | ||
| 1004 | - /* If both operands are extended, they must either both | ||
| 1005 | - be zero-extended or both be sign-extended. */ | ||
| 1006 | - && (TYPE_UNSIGNED (TREE_TYPE (top1)) | ||
| 1007 | - == TYPE_UNSIGNED (TREE_TYPE (top0))))))) | ||
| 1008 | + /* Check for a multiplication with matching signedness. */ | ||
| 1009 | + else if ((TREE_CODE (treeop1) == INTEGER_CST | ||
| 1010 | + && int_fits_type_p (treeop1, TREE_TYPE (treeop0))) | ||
| 1011 | + || (TYPE_UNSIGNED (TREE_TYPE (treeop1)) | ||
| 1012 | + == TYPE_UNSIGNED (TREE_TYPE (treeop0)))) | ||
| 1013 | { | ||
| 1014 | - tree op0type = TREE_TYPE (top0); | ||
| 1015 | + tree op0type = TREE_TYPE (treeop0); | ||
| 1016 | enum machine_mode innermode = TYPE_MODE (op0type); | ||
| 1017 | bool zextend_p = TYPE_UNSIGNED (op0type); | ||
| 1018 | optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab; | ||
| 1019 | @@ -7916,24 +7848,22 @@ | ||
| 1020 | { | ||
| 1021 | if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing) | ||
| 1022 | { | ||
| 1023 | - if (TREE_CODE (subexp1) == INTEGER_CST) | ||
| 1024 | - expand_operands (top0, subexp1, NULL_RTX, &op0, &op1, | ||
| 1025 | - EXPAND_NORMAL); | ||
| 1026 | - else | ||
| 1027 | - expand_operands (top0, top1, NULL_RTX, &op0, &op1, | ||
| 1028 | - EXPAND_NORMAL); | ||
| 1029 | - goto binop3; | ||
| 1030 | + expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, | ||
| 1031 | + EXPAND_NORMAL); | ||
| 1032 | + temp = expand_widening_mult (mode, op0, op1, target, | ||
| 1033 | + unsignedp, this_optab); | ||
| 1034 | + return REDUCE_BIT_FIELD (temp); | ||
| 1035 | } | ||
| 1036 | - else if (optab_handler (other_optab, mode)->insn_code != CODE_FOR_nothing | ||
| 1037 | - && innermode == word_mode) | ||
| 1038 | + if (optab_handler (other_optab, mode)->insn_code != CODE_FOR_nothing | ||
| 1039 | + && innermode == word_mode) | ||
| 1040 | { | ||
| 1041 | rtx htem, hipart; | ||
| 1042 | - op0 = expand_normal (top0); | ||
| 1043 | - if (TREE_CODE (subexp1) == INTEGER_CST) | ||
| 1044 | + op0 = expand_normal (treeop0); | ||
| 1045 | + if (TREE_CODE (treeop1) == INTEGER_CST) | ||
| 1046 | op1 = convert_modes (innermode, mode, | ||
| 1047 | - expand_normal (subexp1), unsignedp); | ||
| 1048 | + expand_normal (treeop1), unsignedp); | ||
| 1049 | else | ||
| 1050 | - op1 = expand_normal (top1); | ||
| 1051 | + op1 = expand_normal (treeop1); | ||
| 1052 | temp = expand_binop (mode, other_optab, op0, op1, target, | ||
| 1053 | unsignedp, OPTAB_LIB_WIDEN); | ||
| 1054 | hipart = gen_highpart (innermode, temp); | ||
| 1055 | @@ -7946,7 +7876,53 @@ | ||
| 1056 | } | ||
| 1057 | } | ||
| 1058 | } | ||
| 1059 | - expand_operands (subexp0, subexp1, subtarget, &op0, &op1, EXPAND_NORMAL); | ||
| 1060 | + treeop0 = fold_build1 (CONVERT_EXPR, type, treeop0); | ||
| 1061 | + treeop1 = fold_build1 (CONVERT_EXPR, type, treeop1); | ||
| 1062 | + expand_operands (treeop0, treeop1, subtarget, &op0, &op1, EXPAND_NORMAL); | ||
| 1063 | + return REDUCE_BIT_FIELD (expand_mult (mode, op0, op1, target, unsignedp)); | ||
| 1064 | + | ||
| 1065 | + case MULT_EXPR: | ||
| 1066 | + /* If this is a fixed-point operation, then we cannot use the code | ||
| 1067 | + below because "expand_mult" doesn't support sat/no-sat fixed-point | ||
| 1068 | + multiplications. */ | ||
| 1069 | + if (ALL_FIXED_POINT_MODE_P (mode)) | ||
| 1070 | + goto binop; | ||
| 1071 | + | ||
| 1072 | + /* If first operand is constant, swap them. | ||
| 1073 | + Thus the following special case checks need only | ||
| 1074 | + check the second operand. */ | ||
| 1075 | + if (TREE_CODE (treeop0) == INTEGER_CST) | ||
| 1076 | + { | ||
| 1077 | + tree t1 = treeop0; | ||
| 1078 | + treeop0 = treeop1; | ||
| 1079 | + treeop1 = t1; | ||
| 1080 | + } | ||
| 1081 | + | ||
| 1082 | + /* Attempt to return something suitable for generating an | ||
| 1083 | + indexed address, for machines that support that. */ | ||
| 1084 | + | ||
| 1085 | + if (modifier == EXPAND_SUM && mode == ptr_mode | ||
| 1086 | + && host_integerp (treeop1, 0)) | ||
| 1087 | + { | ||
| 1088 | + tree exp1 = treeop1; | ||
| 1089 | + | ||
| 1090 | + op0 = expand_expr (treeop0, subtarget, VOIDmode, | ||
| 1091 | + EXPAND_SUM); | ||
| 1092 | + | ||
| 1093 | + if (!REG_P (op0)) | ||
| 1094 | + op0 = force_operand (op0, NULL_RTX); | ||
| 1095 | + if (!REG_P (op0)) | ||
| 1096 | + op0 = copy_to_mode_reg (mode, op0); | ||
| 1097 | + | ||
| 1098 | + return REDUCE_BIT_FIELD (gen_rtx_MULT (mode, op0, | ||
| 1099 | + gen_int_mode (tree_low_cst (exp1, 0), | ||
| 1100 | + TYPE_MODE (TREE_TYPE (exp1))))); | ||
| 1101 | + } | ||
| 1102 | + | ||
| 1103 | + if (modifier == EXPAND_STACK_PARM) | ||
| 1104 | + target = 0; | ||
| 1105 | + | ||
| 1106 | + expand_operands (treeop0, treeop1, subtarget, &op0, &op1, EXPAND_NORMAL); | ||
| 1107 | return REDUCE_BIT_FIELD (expand_mult (mode, op0, op1, target, unsignedp)); | ||
| 1108 | |||
| 1109 | case TRUNC_DIV_EXPR: | ||
| 1110 | @@ -8435,6 +8411,8 @@ | ||
| 1111 | location_t loc = EXPR_LOCATION (exp); | ||
| 1112 | struct separate_ops ops; | ||
| 1113 | tree treeop0, treeop1, treeop2; | ||
| 1114 | + tree ssa_name = NULL_TREE; | ||
| 1115 | + gimple g; | ||
| 1116 | |||
| 1117 | type = TREE_TYPE (exp); | ||
| 1118 | mode = TYPE_MODE (type); | ||
| 1119 | @@ -8547,15 +8525,17 @@ | ||
| 1120 | base variable. This unnecessarily allocates a pseudo, see how we can | ||
| 1121 | reuse it, if partition base vars have it set already. */ | ||
| 1122 | if (!currently_expanding_to_rtl) | ||
| 1123 | - return expand_expr_real_1 (SSA_NAME_VAR (exp), target, tmode, modifier, NULL); | ||
| 1124 | - { | ||
| 1125 | - gimple g = get_gimple_for_ssa_name (exp); | ||
| 1126 | - if (g) | ||
| 1127 | - return expand_expr_real (gimple_assign_rhs_to_tree (g), target, | ||
| 1128 | - tmode, modifier, NULL); | ||
| 1129 | - } | ||
| 1130 | - decl_rtl = get_rtx_for_ssa_name (exp); | ||
| 1131 | - exp = SSA_NAME_VAR (exp); | ||
| 1132 | + return expand_expr_real_1 (SSA_NAME_VAR (exp), target, tmode, modifier, | ||
| 1133 | + NULL); | ||
| 1134 | + | ||
| 1135 | + g = get_gimple_for_ssa_name (exp); | ||
| 1136 | + if (g) | ||
| 1137 | + return expand_expr_real (gimple_assign_rhs_to_tree (g), target, tmode, | ||
| 1138 | + modifier, NULL); | ||
| 1139 | + | ||
| 1140 | + ssa_name = exp; | ||
| 1141 | + decl_rtl = get_rtx_for_ssa_name (ssa_name); | ||
| 1142 | + exp = SSA_NAME_VAR (ssa_name); | ||
| 1143 | goto expand_decl_rtl; | ||
| 1144 | |||
| 1145 | case PARM_DECL: | ||
| 1146 | @@ -8669,7 +8649,15 @@ | ||
| 1147 | |||
| 1148 | /* Get the signedness used for this variable. Ensure we get the | ||
| 1149 | same mode we got when the variable was declared. */ | ||
| 1150 | - pmode = promote_decl_mode (exp, &unsignedp); | ||
| 1151 | + if (code == SSA_NAME | ||
| 1152 | + && (g = SSA_NAME_DEF_STMT (ssa_name)) | ||
| 1153 | + && gimple_code (g) == GIMPLE_CALL) | ||
| 1154 | + pmode = promote_function_mode (type, mode, &unsignedp, | ||
| 1155 | + TREE_TYPE | ||
| 1156 | + (TREE_TYPE (gimple_call_fn (g))), | ||
| 1157 | + 2); | ||
| 1158 | + else | ||
| 1159 | + pmode = promote_decl_mode (exp, &unsignedp); | ||
| 1160 | gcc_assert (GET_MODE (decl_rtl) == pmode); | ||
| 1161 | |||
| 1162 | temp = gen_lowpart_SUBREG (mode, decl_rtl); | ||
| 1163 | Index: gcc-4_5-branch/gcc/fold-const.c | ||
| 1164 | =================================================================== | ||
| 1165 | --- gcc-4_5-branch.orig/gcc/fold-const.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 1166 | +++ gcc-4_5-branch/gcc/fold-const.c 2012-03-06 12:14:01.052439240 -0800 | ||
| 1167 | @@ -5749,6 +5749,76 @@ | ||
| 1168 | const_binop (BIT_XOR_EXPR, c, temp, 0)); | ||
| 1169 | } | ||
| 1170 | |||
| 1171 | +/* For an expression that has the form | ||
| 1172 | + (A && B) || ~B | ||
| 1173 | + or | ||
| 1174 | + (A || B) && ~B, | ||
| 1175 | + we can drop one of the inner expressions and simplify to | ||
| 1176 | + A || ~B | ||
| 1177 | + or | ||
| 1178 | + A && ~B | ||
| 1179 | + LOC is the location of the resulting expression. OP is the inner | ||
| 1180 | + logical operation; the left-hand side in the examples above, while CMPOP | ||
| 1181 | + is the right-hand side. RHS_ONLY is used to prevent us from accidentally | ||
| 1182 | + removing a condition that guards another, as in | ||
| 1183 | + (A != NULL && A->...) || A == NULL | ||
| 1184 | + which we must not transform. If RHS_ONLY is true, only eliminate the | ||
| 1185 | + right-most operand of the inner logical operation. */ | ||
| 1186 | + | ||
| 1187 | +static tree | ||
| 1188 | +merge_truthop_with_opposite_arm (location_t loc, tree op, tree cmpop, | ||
| 1189 | + bool rhs_only) | ||
| 1190 | +{ | ||
| 1191 | + tree type = TREE_TYPE (cmpop); | ||
| 1192 | + enum tree_code code = TREE_CODE (cmpop); | ||
| 1193 | + enum tree_code truthop_code = TREE_CODE (op); | ||
| 1194 | + tree lhs = TREE_OPERAND (op, 0); | ||
| 1195 | + tree rhs = TREE_OPERAND (op, 1); | ||
| 1196 | + tree orig_lhs = lhs, orig_rhs = rhs; | ||
| 1197 | + enum tree_code rhs_code = TREE_CODE (rhs); | ||
| 1198 | + enum tree_code lhs_code = TREE_CODE (lhs); | ||
| 1199 | + enum tree_code inv_code; | ||
| 1200 | + | ||
| 1201 | + if (TREE_SIDE_EFFECTS (op) || TREE_SIDE_EFFECTS (cmpop)) | ||
| 1202 | + return NULL_TREE; | ||
| 1203 | + | ||
| 1204 | + if (TREE_CODE_CLASS (code) != tcc_comparison) | ||
| 1205 | + return NULL_TREE; | ||
| 1206 | + | ||
| 1207 | + if (rhs_code == truthop_code) | ||
| 1208 | + { | ||
| 1209 | + tree newrhs = merge_truthop_with_opposite_arm (loc, rhs, cmpop, rhs_only); | ||
| 1210 | + if (newrhs != NULL_TREE) | ||
| 1211 | + { | ||
| 1212 | + rhs = newrhs; | ||
| 1213 | + rhs_code = TREE_CODE (rhs); | ||
| 1214 | + } | ||
| 1215 | + } | ||
| 1216 | + if (lhs_code == truthop_code && !rhs_only) | ||
| 1217 | + { | ||
| 1218 | + tree newlhs = merge_truthop_with_opposite_arm (loc, lhs, cmpop, false); | ||
| 1219 | + if (newlhs != NULL_TREE) | ||
| 1220 | + { | ||
| 1221 | + lhs = newlhs; | ||
| 1222 | + lhs_code = TREE_CODE (lhs); | ||
| 1223 | + } | ||
| 1224 | + } | ||
| 1225 | + | ||
| 1226 | + inv_code = invert_tree_comparison (code, HONOR_NANS (TYPE_MODE (type))); | ||
| 1227 | + if (inv_code == rhs_code | ||
| 1228 | + && operand_equal_p (TREE_OPERAND (rhs, 0), TREE_OPERAND (cmpop, 0), 0) | ||
| 1229 | + && operand_equal_p (TREE_OPERAND (rhs, 1), TREE_OPERAND (cmpop, 1), 0)) | ||
| 1230 | + return lhs; | ||
| 1231 | + if (!rhs_only && inv_code == lhs_code | ||
| 1232 | + && operand_equal_p (TREE_OPERAND (lhs, 0), TREE_OPERAND (cmpop, 0), 0) | ||
| 1233 | + && operand_equal_p (TREE_OPERAND (lhs, 1), TREE_OPERAND (cmpop, 1), 0)) | ||
| 1234 | + return rhs; | ||
| 1235 | + if (rhs != orig_rhs || lhs != orig_lhs) | ||
| 1236 | + return fold_build2_loc (loc, truthop_code, TREE_TYPE (cmpop), | ||
| 1237 | + lhs, rhs); | ||
| 1238 | + return NULL_TREE; | ||
| 1239 | +} | ||
| 1240 | + | ||
| 1241 | /* Find ways of folding logical expressions of LHS and RHS: | ||
| 1242 | Try to merge two comparisons to the same innermost item. | ||
| 1243 | Look for range tests like "ch >= '0' && ch <= '9'". | ||
| 1244 | @@ -12553,6 +12623,22 @@ | ||
| 1245 | if (0 != (tem = fold_range_test (loc, code, type, op0, op1))) | ||
| 1246 | return tem; | ||
| 1247 | |||
| 1248 | + if ((code == TRUTH_ANDIF_EXPR && TREE_CODE (arg0) == TRUTH_ORIF_EXPR) | ||
| 1249 | + || (code == TRUTH_ORIF_EXPR && TREE_CODE (arg0) == TRUTH_ANDIF_EXPR)) | ||
| 1250 | + { | ||
| 1251 | + tem = merge_truthop_with_opposite_arm (loc, arg0, arg1, true); | ||
| 1252 | + if (tem) | ||
| 1253 | + return fold_build2_loc (loc, code, type, tem, arg1); | ||
| 1254 | + } | ||
| 1255 | + | ||
| 1256 | + if ((code == TRUTH_ANDIF_EXPR && TREE_CODE (arg1) == TRUTH_ORIF_EXPR) | ||
| 1257 | + || (code == TRUTH_ORIF_EXPR && TREE_CODE (arg1) == TRUTH_ANDIF_EXPR)) | ||
| 1258 | + { | ||
| 1259 | + tem = merge_truthop_with_opposite_arm (loc, arg1, arg0, false); | ||
| 1260 | + if (tem) | ||
| 1261 | + return fold_build2_loc (loc, code, type, arg0, tem); | ||
| 1262 | + } | ||
| 1263 | + | ||
| 1264 | /* Check for the possibility of merging component references. If our | ||
| 1265 | lhs is another similar operation, try to merge its rhs with our | ||
| 1266 | rhs. Then try to merge our lhs and rhs. */ | ||
| 1267 | Index: gcc-4_5-branch/gcc/ifcvt.c | ||
| 1268 | =================================================================== | ||
| 1269 | --- gcc-4_5-branch.orig/gcc/ifcvt.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 1270 | +++ gcc-4_5-branch/gcc/ifcvt.c 2012-03-06 12:14:01.052439240 -0800 | ||
| 1271 | @@ -385,7 +385,11 @@ | ||
| 1272 | rtx false_expr; /* test for then block insns */ | ||
| 1273 | rtx true_prob_val; /* probability of else block */ | ||
| 1274 | rtx false_prob_val; /* probability of then block */ | ||
| 1275 | - int n_insns; | ||
| 1276 | + rtx then_last_head = NULL_RTX; /* Last match at the head of THEN */ | ||
| 1277 | + rtx else_last_head = NULL_RTX; /* Last match at the head of ELSE */ | ||
| 1278 | + rtx then_first_tail = NULL_RTX; /* First match at the tail of THEN */ | ||
| 1279 | + rtx else_first_tail = NULL_RTX; /* First match at the tail of ELSE */ | ||
| 1280 | + int then_n_insns, else_n_insns, n_insns; | ||
| 1281 | enum rtx_code false_code; | ||
| 1282 | |||
| 1283 | /* If test is comprised of && or || elements, and we've failed at handling | ||
| 1284 | @@ -418,15 +422,78 @@ | ||
| 1285 | number of insns and see if it is small enough to convert. */ | ||
| 1286 | then_start = first_active_insn (then_bb); | ||
| 1287 | then_end = last_active_insn (then_bb, TRUE); | ||
| 1288 | - n_insns = ce_info->num_then_insns = count_bb_insns (then_bb); | ||
| 1289 | + then_n_insns = ce_info->num_then_insns = count_bb_insns (then_bb); | ||
| 1290 | + n_insns = then_n_insns; | ||
| 1291 | max = MAX_CONDITIONAL_EXECUTE; | ||
| 1292 | |||
| 1293 | if (else_bb) | ||
| 1294 | { | ||
| 1295 | + int n_matching; | ||
| 1296 | + | ||
| 1297 | max *= 2; | ||
| 1298 | else_start = first_active_insn (else_bb); | ||
| 1299 | else_end = last_active_insn (else_bb, TRUE); | ||
| 1300 | - n_insns += ce_info->num_else_insns = count_bb_insns (else_bb); | ||
| 1301 | + else_n_insns = ce_info->num_else_insns = count_bb_insns (else_bb); | ||
| 1302 | + n_insns += else_n_insns; | ||
| 1303 | + | ||
| 1304 | + /* Look for matching sequences at the head and tail of the two blocks, | ||
| 1305 | + and limit the range of insns to be converted if possible. */ | ||
| 1306 | + n_matching = flow_find_cross_jump (then_bb, else_bb, | ||
| 1307 | + &then_first_tail, &else_first_tail); | ||
| 1308 | + if (then_first_tail == BB_HEAD (then_bb)) | ||
| 1309 | + then_start = then_end = NULL_RTX; | ||
| 1310 | + if (else_first_tail == BB_HEAD (else_bb)) | ||
| 1311 | + else_start = else_end = NULL_RTX; | ||
| 1312 | + | ||
| 1313 | + if (n_matching > 0) | ||
| 1314 | + { | ||
| 1315 | + if (then_end) | ||
| 1316 | + then_end = prev_active_insn (then_first_tail); | ||
| 1317 | + if (else_end) | ||
| 1318 | + else_end = prev_active_insn (else_first_tail); | ||
| 1319 | + n_insns -= 2 * n_matching; | ||
| 1320 | + } | ||
| 1321 | + | ||
| 1322 | + if (then_start && else_start) | ||
| 1323 | + { | ||
| 1324 | + int longest_match = MIN (then_n_insns - n_matching, | ||
| 1325 | + else_n_insns - n_matching); | ||
| 1326 | + n_matching | ||
| 1327 | + = flow_find_head_matching_sequence (then_bb, else_bb, | ||
| 1328 | + &then_last_head, | ||
| 1329 | + &else_last_head, | ||
| 1330 | + longest_match); | ||
| 1331 | + | ||
| 1332 | + if (n_matching > 0) | ||
| 1333 | + { | ||
| 1334 | + rtx insn; | ||
| 1335 | + | ||
| 1336 | + /* We won't pass the insns in the head sequence to | ||
| 1337 | + cond_exec_process_insns, so we need to test them here | ||
| 1338 | + to make sure that they don't clobber the condition. */ | ||
| 1339 | + for (insn = BB_HEAD (then_bb); | ||
| 1340 | + insn != NEXT_INSN (then_last_head); | ||
| 1341 | + insn = NEXT_INSN (insn)) | ||
| 1342 | + if (!LABEL_P (insn) && !NOTE_P (insn) | ||
| 1343 | + && !DEBUG_INSN_P (insn) | ||
| 1344 | + && modified_in_p (test_expr, insn)) | ||
| 1345 | + return FALSE; | ||
| 1346 | + } | ||
| 1347 | + | ||
| 1348 | + if (then_last_head == then_end) | ||
| 1349 | + then_start = then_end = NULL_RTX; | ||
| 1350 | + if (else_last_head == else_end) | ||
| 1351 | + else_start = else_end = NULL_RTX; | ||
| 1352 | + | ||
| 1353 | + if (n_matching > 0) | ||
| 1354 | + { | ||
| 1355 | + if (then_start) | ||
| 1356 | + then_start = next_active_insn (then_last_head); | ||
| 1357 | + if (else_start) | ||
| 1358 | + else_start = next_active_insn (else_last_head); | ||
| 1359 | + n_insns -= 2 * n_matching; | ||
| 1360 | + } | ||
| 1361 | + } | ||
| 1362 | } | ||
| 1363 | |||
| 1364 | if (n_insns > max) | ||
| 1365 | @@ -570,7 +637,21 @@ | ||
| 1366 | fprintf (dump_file, "%d insn%s converted to conditional execution.\n", | ||
| 1367 | n_insns, (n_insns == 1) ? " was" : "s were"); | ||
| 1368 | |||
| 1369 | - /* Merge the blocks! */ | ||
| 1370 | + /* Merge the blocks! If we had matching sequences, make sure to delete one | ||
| 1371 | + copy at the appropriate location first: delete the copy in the THEN branch | ||
| 1372 | + for a tail sequence so that the remaining one is executed last for both | ||
| 1373 | + branches, and delete the copy in the ELSE branch for a head sequence so | ||
| 1374 | + that the remaining one is executed first for both branches. */ | ||
| 1375 | + if (then_first_tail) | ||
| 1376 | + { | ||
| 1377 | + rtx from = then_first_tail; | ||
| 1378 | + if (!INSN_P (from)) | ||
| 1379 | + from = next_active_insn (from); | ||
| 1380 | + delete_insn_chain (from, BB_END (then_bb), false); | ||
| 1381 | + } | ||
| 1382 | + if (else_last_head) | ||
| 1383 | + delete_insn_chain (first_active_insn (else_bb), else_last_head, false); | ||
| 1384 | + | ||
| 1385 | merge_if_block (ce_info); | ||
| 1386 | cond_exec_changed_p = TRUE; | ||
| 1387 | return TRUE; | ||
| 1388 | Index: gcc-4_5-branch/gcc/ira-color.c | ||
| 1389 | =================================================================== | ||
| 1390 | --- gcc-4_5-branch.orig/gcc/ira-color.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 1391 | +++ gcc-4_5-branch/gcc/ira-color.c 2012-03-06 12:14:01.056439222 -0800 | ||
| 1392 | @@ -447,14 +447,18 @@ | ||
| 1393 | { | ||
| 1394 | HARD_REG_SET conflicting_regs; | ||
| 1395 | int i, j, k, hard_regno, best_hard_regno, class_size; | ||
| 1396 | - int cost, mem_cost, min_cost, full_cost, min_full_cost, add_cost; | ||
| 1397 | + int cost, mem_cost, min_cost, full_cost, min_full_cost; | ||
| 1398 | int *a_costs; | ||
| 1399 | int *conflict_costs; | ||
| 1400 | - enum reg_class cover_class, rclass, conflict_cover_class; | ||
| 1401 | + enum reg_class cover_class, conflict_cover_class; | ||
| 1402 | enum machine_mode mode; | ||
| 1403 | ira_allocno_t a, conflict_allocno; | ||
| 1404 | ira_allocno_conflict_iterator aci; | ||
| 1405 | static int costs[FIRST_PSEUDO_REGISTER], full_costs[FIRST_PSEUDO_REGISTER]; | ||
| 1406 | +#ifndef HONOR_REG_ALLOC_ORDER | ||
| 1407 | + enum reg_class rclass; | ||
| 1408 | + int add_cost; | ||
| 1409 | +#endif | ||
| 1410 | #ifdef STACK_REGS | ||
| 1411 | bool no_stack_reg_p; | ||
| 1412 | #endif | ||
| 1413 | @@ -592,6 +596,7 @@ | ||
| 1414 | continue; | ||
| 1415 | cost = costs[i]; | ||
| 1416 | full_cost = full_costs[i]; | ||
| 1417 | +#ifndef HONOR_REG_ALLOC_ORDER | ||
| 1418 | if (! allocated_hardreg_p[hard_regno] | ||
| 1419 | && ira_hard_reg_not_in_set_p (hard_regno, mode, call_used_reg_set)) | ||
| 1420 | /* We need to save/restore the hard register in | ||
| 1421 | @@ -604,6 +609,7 @@ | ||
| 1422 | cost += add_cost; | ||
| 1423 | full_cost += add_cost; | ||
| 1424 | } | ||
| 1425 | +#endif | ||
| 1426 | if (min_cost > cost) | ||
| 1427 | min_cost = cost; | ||
| 1428 | if (min_full_cost > full_cost) | ||
| 1429 | Index: gcc-4_5-branch/gcc/ira-costs.c | ||
| 1430 | =================================================================== | ||
| 1431 | --- gcc-4_5-branch.orig/gcc/ira-costs.c 2012-03-06 12:11:33.000000000 -0800 | ||
| 1432 | +++ gcc-4_5-branch/gcc/ira-costs.c 2012-03-06 12:14:01.056439222 -0800 | ||
| 1433 | @@ -33,6 +33,7 @@ | ||
| 1434 | #include "addresses.h" | ||
| 1435 | #include "insn-config.h" | ||
| 1436 | #include "recog.h" | ||
| 1437 | +#include "reload.h" | ||
| 1438 | #include "toplev.h" | ||
| 1439 | #include "target.h" | ||
| 1440 | #include "params.h" | ||
| 1441 | @@ -123,6 +124,10 @@ | ||
| 1442 | /* Record cover register class of each allocno with the same regno. */ | ||
| 1443 | static enum reg_class *regno_cover_class; | ||
| 1444 | |||
| 1445 | +/* Record cost gains for not allocating a register with an invariant | ||
| 1446 | + equivalence. */ | ||
| 1447 | +static int *regno_equiv_gains; | ||
| 1448 | + | ||
| 1449 | /* Execution frequency of the current insn. */ | ||
| 1450 | static int frequency; | ||
| 1451 | |||
| 1452 | @@ -1263,6 +1268,7 @@ | ||
| 1453 | #ifdef FORBIDDEN_INC_DEC_CLASSES | ||
| 1454 | int inc_dec_p = false; | ||
| 1455 | #endif | ||
| 1456 | + int equiv_savings = regno_equiv_gains[i]; | ||
| 1457 | |||
| 1458 | if (! allocno_p) | ||
| 1459 | { | ||
| 1460 | @@ -1311,6 +1317,15 @@ | ||
| 1461 | #endif | ||
| 1462 | } | ||
| 1463 | } | ||
| 1464 | + if (equiv_savings < 0) | ||
| 1465 | + temp_costs->mem_cost = -equiv_savings; | ||
| 1466 | + else if (equiv_savings > 0) | ||
| 1467 | + { | ||
| 1468 | + temp_costs->mem_cost = 0; | ||
| 1469 | + for (k = 0; k < cost_classes_num; k++) | ||
| 1470 | + temp_costs->cost[k] += equiv_savings; | ||
| 1471 | + } | ||
| 1472 | + | ||
| 1473 | best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; | ||
| 1474 | best = ALL_REGS; | ||
| 1475 | alt_class = NO_REGS; | ||
| 1476 | @@ -1680,6 +1695,8 @@ | ||
| 1477 | regno_cover_class | ||
| 1478 | = (enum reg_class *) ira_allocate (sizeof (enum reg_class) | ||
| 1479 | * max_reg_num ()); | ||
| 1480 | + regno_equiv_gains = (int *) ira_allocate (sizeof (int) * max_reg_num ()); | ||
| 1481 | + memset (regno_equiv_gains, 0, sizeof (int) * max_reg_num ()); | ||
| 1482 | } | ||
| 1483 | |||
| 1484 | /* Common finalization function for ira_costs and | ||
| 1485 | @@ -1687,6 +1704,7 @@ | ||
| 1486 | static void | ||
| 1487 | finish_costs (void) | ||
| 1488 | { | ||
| 1489 | + ira_free (regno_equiv_gains); | ||
| 1490 | ira_free (regno_cover_class); | ||
| 1491 | ira_free (pref_buffer); | ||
| 1492 | ira_free (costs); | ||
| 1493 | @@ -1702,6 +1720,7 @@ | ||
| 1494 | init_costs (); | ||
| 1495 | total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size | ||
| 1496 | * ira_allocnos_num); | ||
| 1497 | + calculate_elim_costs_all_insns (); | ||
| 1498 | find_costs_and_classes (ira_dump_file); | ||
| 1499 | setup_allocno_cover_class_and_costs (); | ||
| 1500 | finish_costs (); | ||
| 1501 | @@ -1775,3 +1794,16 @@ | ||
| 1502 | ALLOCNO_COVER_CLASS_COST (a) = min_cost; | ||
| 1503 | } | ||
| 1504 | } | ||
| 1505 | + | ||
| 1506 | +/* Add COST to the estimated gain for eliminating REGNO with its | ||
| 1507 | + equivalence. If COST is zero, record that no such elimination is | ||
| 1508 | + possible. */ | ||
| 1509 | + | ||
| 1510 | +void | ||
| 1511 | +ira_adjust_equiv_reg_cost (unsigned regno, int cost) | ||
| 1512 | +{ | ||
| 1513 | + if (cost == 0) | ||
| 1514 | + regno_equiv_gains[regno] = 0; | ||
| 1515 | + else | ||
| 1516 | + regno_equiv_gains[regno] += cost; | ||
| 1517 | +} | ||
| 1518 | Index: gcc-4_5-branch/gcc/ira.c | ||
| 1519 | =================================================================== | ||
| 1520 | --- gcc-4_5-branch.orig/gcc/ira.c 2012-03-06 12:11:32.000000000 -0800 | ||
| 1521 | +++ gcc-4_5-branch/gcc/ira.c 2012-03-06 12:14:01.056439222 -0800 | ||
| 1522 | @@ -431,9 +431,6 @@ | ||
| 1523 | HARD_REG_SET processed_hard_reg_set; | ||
| 1524 | |||
| 1525 | ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); | ||
| 1526 | - /* We could call ORDER_REGS_FOR_LOCAL_ALLOC here (it is usually | ||
| 1527 | - putting hard callee-used hard registers first). But our | ||
| 1528 | - heuristics work better. */ | ||
| 1529 | for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) | ||
| 1530 | { | ||
| 1531 | COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); | ||
| 1532 | @@ -490,6 +487,9 @@ | ||
| 1533 | static void | ||
| 1534 | setup_alloc_regs (bool use_hard_frame_p) | ||
| 1535 | { | ||
| 1536 | +#ifdef ADJUST_REG_ALLOC_ORDER | ||
| 1537 | + ADJUST_REG_ALLOC_ORDER; | ||
| 1538 | +#endif | ||
| 1539 | COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); | ||
| 1540 | if (! use_hard_frame_p) | ||
| 1541 | SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); | ||
| 1542 | @@ -1533,12 +1533,8 @@ | ||
| 1543 | |||
| 1544 | x = XEXP (note, 0); | ||
| 1545 | |||
| 1546 | - if (! function_invariant_p (x) | ||
| 1547 | - || ! flag_pic | ||
| 1548 | - /* A function invariant is often CONSTANT_P but may | ||
| 1549 | - include a register. We promise to only pass CONSTANT_P | ||
| 1550 | - objects to LEGITIMATE_PIC_OPERAND_P. */ | ||
| 1551 | - || (CONSTANT_P (x) && LEGITIMATE_PIC_OPERAND_P (x))) | ||
| 1552 | + if (! CONSTANT_P (x) | ||
| 1553 | + || ! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)) | ||
| 1554 | { | ||
| 1555 | /* It can happen that a REG_EQUIV note contains a MEM | ||
| 1556 | that is not a legitimate memory operand. As later | ||
| 1557 | @@ -3096,8 +3092,19 @@ | ||
| 1558 | if (dump_file) | ||
| 1559 | print_insn_chains (dump_file); | ||
| 1560 | } | ||
| 1561 | - | ||
| 1562 | |||
| 1563 | +/* Allocate memory for reg_equiv_memory_loc. */ | ||
| 1564 | +static void | ||
| 1565 | +init_reg_equiv_memory_loc (void) | ||
| 1566 | +{ | ||
| 1567 | + max_regno = max_reg_num (); | ||
| 1568 | + | ||
| 1569 | + /* And the reg_equiv_memory_loc array. */ | ||
| 1570 | + VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno); | ||
| 1571 | + memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0, | ||
| 1572 | + sizeof (rtx) * max_regno); | ||
| 1573 | + reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec); | ||
| 1574 | +} | ||
| 1575 | |||
| 1576 | /* All natural loops. */ | ||
| 1577 | struct loops ira_loops; | ||
| 1578 | @@ -3202,6 +3209,8 @@ | ||
| 1579 | record_loop_exits (); | ||
| 1580 | current_loops = &ira_loops; | ||
| 1581 | |||
| 1582 | + init_reg_equiv_memory_loc (); | ||
| 1583 | + | ||
| 1584 | if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) | ||
| 1585 | fprintf (ira_dump_file, "Building IRA IR\n"); | ||
| 1586 | loops_p = ira_build (optimize | ||
| 1587 | @@ -3265,13 +3274,8 @@ | ||
| 1588 | #endif | ||
| 1589 | |||
| 1590 | delete_trivially_dead_insns (get_insns (), max_reg_num ()); | ||
| 1591 | - max_regno = max_reg_num (); | ||
| 1592 | |||
| 1593 | - /* And the reg_equiv_memory_loc array. */ | ||
| 1594 | - VEC_safe_grow (rtx, gc, reg_equiv_memory_loc_vec, max_regno); | ||
| 1595 | - memset (VEC_address (rtx, reg_equiv_memory_loc_vec), 0, | ||
| 1596 | - sizeof (rtx) * max_regno); | ||
| 1597 | - reg_equiv_memory_loc = VEC_address (rtx, reg_equiv_memory_loc_vec); | ||
| 1598 | + init_reg_equiv_memory_loc (); | ||
| 1599 | |||
| 1600 | if (max_regno != max_regno_before_ira) | ||
| 1601 | { | ||
| 1602 | Index: gcc-4_5-branch/gcc/ira.h | ||
| 1603 | =================================================================== | ||
| 1604 | --- gcc-4_5-branch.orig/gcc/ira.h 2012-03-06 11:53:32.000000000 -0800 | ||
| 1605 | +++ gcc-4_5-branch/gcc/ira.h 2012-03-06 12:14:01.056439222 -0800 | ||
| 1606 | @@ -87,3 +87,4 @@ | ||
| 1607 | extern void ira_mark_new_stack_slot (rtx, int, unsigned int); | ||
| 1608 | extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx); | ||
| 1609 | |||
| 1610 | +extern void ira_adjust_equiv_reg_cost (unsigned, int); | ||
| 1611 | Index: gcc-4_5-branch/gcc/optabs.h | ||
| 1612 | =================================================================== | ||
| 1613 | --- gcc-4_5-branch.orig/gcc/optabs.h 2012-03-06 11:53:32.000000000 -0800 | ||
| 1614 | +++ gcc-4_5-branch/gcc/optabs.h 2012-03-06 12:14:01.056439222 -0800 | ||
| 1615 | @@ -771,6 +771,9 @@ | ||
| 1616 | /* Generate code for float to integral conversion. */ | ||
| 1617 | extern bool expand_sfix_optab (rtx, rtx, convert_optab); | ||
| 1618 | |||
| 1619 | +/* Generate code for a widening multiply. */ | ||
| 1620 | +extern rtx expand_widening_mult (enum machine_mode, rtx, rtx, rtx, int, optab); | ||
| 1621 | + | ||
| 1622 | /* Return tree if target supports vector operations for COND_EXPR. */ | ||
| 1623 | bool expand_vec_cond_expr_p (tree, enum machine_mode); | ||
| 1624 | |||
| 1625 | Index: gcc-4_5-branch/gcc/passes.c | ||
| 1626 | =================================================================== | ||
| 1627 | --- gcc-4_5-branch.orig/gcc/passes.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 1628 | +++ gcc-4_5-branch/gcc/passes.c 2012-03-06 12:14:01.056439222 -0800 | ||
| 1629 | @@ -944,6 +944,7 @@ | ||
| 1630 | NEXT_PASS (pass_forwprop); | ||
| 1631 | NEXT_PASS (pass_phiopt); | ||
| 1632 | NEXT_PASS (pass_fold_builtins); | ||
| 1633 | + NEXT_PASS (pass_optimize_widening_mul); | ||
| 1634 | NEXT_PASS (pass_tail_calls); | ||
| 1635 | NEXT_PASS (pass_rename_ssa_copies); | ||
| 1636 | NEXT_PASS (pass_uncprop); | ||
| 1637 | Index: gcc-4_5-branch/gcc/reload.h | ||
| 1638 | =================================================================== | ||
| 1639 | --- gcc-4_5-branch.orig/gcc/reload.h 2012-03-06 11:53:32.000000000 -0800 | ||
| 1640 | +++ gcc-4_5-branch/gcc/reload.h 2012-03-06 12:14:01.056439222 -0800 | ||
| 1641 | @@ -347,6 +347,10 @@ | ||
| 1642 | extern rtx eliminate_regs (rtx, enum machine_mode, rtx); | ||
| 1643 | extern bool elimination_target_reg_p (rtx); | ||
| 1644 | |||
| 1645 | +/* Called from the register allocator to estimate costs of eliminating | ||
| 1646 | + invariant registers. */ | ||
| 1647 | +extern void calculate_elim_costs_all_insns (void); | ||
| 1648 | + | ||
| 1649 | /* Deallocate the reload register used by reload number R. */ | ||
| 1650 | extern void deallocate_reload_reg (int r); | ||
| 1651 | |||
| 1652 | Index: gcc-4_5-branch/gcc/reload1.c | ||
| 1653 | =================================================================== | ||
| 1654 | --- gcc-4_5-branch.orig/gcc/reload1.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 1655 | +++ gcc-4_5-branch/gcc/reload1.c 2012-03-06 12:14:01.060439213 -0800 | ||
| 1656 | @@ -413,6 +413,7 @@ | ||
| 1657 | static void set_label_offsets (rtx, rtx, int); | ||
| 1658 | static void check_eliminable_occurrences (rtx); | ||
| 1659 | static void elimination_effects (rtx, enum machine_mode); | ||
| 1660 | +static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool); | ||
| 1661 | static int eliminate_regs_in_insn (rtx, int); | ||
| 1662 | static void update_eliminable_offsets (void); | ||
| 1663 | static void mark_not_eliminable (rtx, const_rtx, void *); | ||
| 1664 | @@ -420,8 +421,11 @@ | ||
| 1665 | static bool verify_initial_elim_offsets (void); | ||
| 1666 | static void set_initial_label_offsets (void); | ||
| 1667 | static void set_offsets_for_label (rtx); | ||
| 1668 | +static void init_eliminable_invariants (rtx, bool); | ||
| 1669 | static void init_elim_table (void); | ||
| 1670 | +static void free_reg_equiv (void); | ||
| 1671 | static void update_eliminables (HARD_REG_SET *); | ||
| 1672 | +static void elimination_costs_in_insn (rtx); | ||
| 1673 | static void spill_hard_reg (unsigned int, int); | ||
| 1674 | static int finish_spills (int); | ||
| 1675 | static void scan_paradoxical_subregs (rtx); | ||
| 1676 | @@ -697,6 +701,9 @@ | ||
| 1677 | |||
| 1678 | /* Global variables used by reload and its subroutines. */ | ||
| 1679 | |||
| 1680 | +/* The current basic block while in calculate_elim_costs_all_insns. */ | ||
| 1681 | +static basic_block elim_bb; | ||
| 1682 | + | ||
| 1683 | /* Set during calculate_needs if an insn needs register elimination. */ | ||
| 1684 | static int something_needs_elimination; | ||
| 1685 | /* Set during calculate_needs if an insn needs an operand changed. */ | ||
| 1686 | @@ -775,22 +782,6 @@ | ||
| 1687 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) | ||
| 1688 | df_set_regs_ever_live (i, true); | ||
| 1689 | |||
| 1690 | - /* Find all the pseudo registers that didn't get hard regs | ||
| 1691 | - but do have known equivalent constants or memory slots. | ||
| 1692 | - These include parameters (known equivalent to parameter slots) | ||
| 1693 | - and cse'd or loop-moved constant memory addresses. | ||
| 1694 | - | ||
| 1695 | - Record constant equivalents in reg_equiv_constant | ||
| 1696 | - so they will be substituted by find_reloads. | ||
| 1697 | - Record memory equivalents in reg_mem_equiv so they can | ||
| 1698 | - be substituted eventually by altering the REG-rtx's. */ | ||
| 1699 | - | ||
| 1700 | - reg_equiv_constant = XCNEWVEC (rtx, max_regno); | ||
| 1701 | - reg_equiv_invariant = XCNEWVEC (rtx, max_regno); | ||
| 1702 | - reg_equiv_mem = XCNEWVEC (rtx, max_regno); | ||
| 1703 | - reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno); | ||
| 1704 | - reg_equiv_address = XCNEWVEC (rtx, max_regno); | ||
| 1705 | - reg_max_ref_width = XCNEWVEC (unsigned int, max_regno); | ||
| 1706 | reg_old_renumber = XCNEWVEC (short, max_regno); | ||
| 1707 | memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); | ||
| 1708 | pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno); | ||
| 1709 | @@ -798,115 +789,9 @@ | ||
| 1710 | |||
| 1711 | CLEAR_HARD_REG_SET (bad_spill_regs_global); | ||
| 1712 | |||
| 1713 | - /* Look for REG_EQUIV notes; record what each pseudo is equivalent | ||
| 1714 | - to. Also find all paradoxical subregs and find largest such for | ||
| 1715 | - each pseudo. */ | ||
| 1716 | - | ||
| 1717 | - num_eliminable_invariants = 0; | ||
| 1718 | - for (insn = first; insn; insn = NEXT_INSN (insn)) | ||
| 1719 | - { | ||
| 1720 | - rtx set = single_set (insn); | ||
| 1721 | - | ||
| 1722 | - /* We may introduce USEs that we want to remove at the end, so | ||
| 1723 | - we'll mark them with QImode. Make sure there are no | ||
| 1724 | - previously-marked insns left by say regmove. */ | ||
| 1725 | - if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE | ||
| 1726 | - && GET_MODE (insn) != VOIDmode) | ||
| 1727 | - PUT_MODE (insn, VOIDmode); | ||
| 1728 | - | ||
| 1729 | - if (NONDEBUG_INSN_P (insn)) | ||
| 1730 | - scan_paradoxical_subregs (PATTERN (insn)); | ||
| 1731 | - | ||
| 1732 | - if (set != 0 && REG_P (SET_DEST (set))) | ||
| 1733 | - { | ||
| 1734 | - rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | ||
| 1735 | - rtx x; | ||
| 1736 | - | ||
| 1737 | - if (! note) | ||
| 1738 | - continue; | ||
| 1739 | - | ||
| 1740 | - i = REGNO (SET_DEST (set)); | ||
| 1741 | - x = XEXP (note, 0); | ||
| 1742 | - | ||
| 1743 | - if (i <= LAST_VIRTUAL_REGISTER) | ||
| 1744 | - continue; | ||
| 1745 | - | ||
| 1746 | - if (! function_invariant_p (x) | ||
| 1747 | - || ! flag_pic | ||
| 1748 | - /* A function invariant is often CONSTANT_P but may | ||
| 1749 | - include a register. We promise to only pass | ||
| 1750 | - CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | ||
| 1751 | - || (CONSTANT_P (x) | ||
| 1752 | - && LEGITIMATE_PIC_OPERAND_P (x))) | ||
| 1753 | - { | ||
| 1754 | - /* It can happen that a REG_EQUIV note contains a MEM | ||
| 1755 | - that is not a legitimate memory operand. As later | ||
| 1756 | - stages of reload assume that all addresses found | ||
| 1757 | - in the reg_equiv_* arrays were originally legitimate, | ||
| 1758 | - we ignore such REG_EQUIV notes. */ | ||
| 1759 | - if (memory_operand (x, VOIDmode)) | ||
| 1760 | - { | ||
| 1761 | - /* Always unshare the equivalence, so we can | ||
| 1762 | - substitute into this insn without touching the | ||
| 1763 | - equivalence. */ | ||
| 1764 | - reg_equiv_memory_loc[i] = copy_rtx (x); | ||
| 1765 | - } | ||
| 1766 | - else if (function_invariant_p (x)) | ||
| 1767 | - { | ||
| 1768 | - if (GET_CODE (x) == PLUS) | ||
| 1769 | - { | ||
| 1770 | - /* This is PLUS of frame pointer and a constant, | ||
| 1771 | - and might be shared. Unshare it. */ | ||
| 1772 | - reg_equiv_invariant[i] = copy_rtx (x); | ||
| 1773 | - num_eliminable_invariants++; | ||
| 1774 | - } | ||
| 1775 | - else if (x == frame_pointer_rtx || x == arg_pointer_rtx) | ||
| 1776 | - { | ||
| 1777 | - reg_equiv_invariant[i] = x; | ||
| 1778 | - num_eliminable_invariants++; | ||
| 1779 | - } | ||
| 1780 | - else if (LEGITIMATE_CONSTANT_P (x)) | ||
| 1781 | - reg_equiv_constant[i] = x; | ||
| 1782 | - else | ||
| 1783 | - { | ||
| 1784 | - reg_equiv_memory_loc[i] | ||
| 1785 | - = force_const_mem (GET_MODE (SET_DEST (set)), x); | ||
| 1786 | - if (! reg_equiv_memory_loc[i]) | ||
| 1787 | - reg_equiv_init[i] = NULL_RTX; | ||
| 1788 | - } | ||
| 1789 | - } | ||
| 1790 | - else | ||
| 1791 | - { | ||
| 1792 | - reg_equiv_init[i] = NULL_RTX; | ||
| 1793 | - continue; | ||
| 1794 | - } | ||
| 1795 | - } | ||
| 1796 | - else | ||
| 1797 | - reg_equiv_init[i] = NULL_RTX; | ||
| 1798 | - } | ||
| 1799 | - } | ||
| 1800 | - | ||
| 1801 | - if (dump_file) | ||
| 1802 | - for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | ||
| 1803 | - if (reg_equiv_init[i]) | ||
| 1804 | - { | ||
| 1805 | - fprintf (dump_file, "init_insns for %u: ", i); | ||
| 1806 | - print_inline_rtx (dump_file, reg_equiv_init[i], 20); | ||
| 1807 | - fprintf (dump_file, "\n"); | ||
| 1808 | - } | ||
| 1809 | - | ||
| 1810 | + init_eliminable_invariants (first, true); | ||
| 1811 | init_elim_table (); | ||
| 1812 | |||
| 1813 | - first_label_num = get_first_label_num (); | ||
| 1814 | - num_labels = max_label_num () - first_label_num; | ||
| 1815 | - | ||
| 1816 | - /* Allocate the tables used to store offset information at labels. */ | ||
| 1817 | - /* We used to use alloca here, but the size of what it would try to | ||
| 1818 | - allocate would occasionally cause it to exceed the stack limit and | ||
| 1819 | - cause a core dump. */ | ||
| 1820 | - offsets_known_at = XNEWVEC (char, num_labels); | ||
| 1821 | - offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT)); | ||
| 1822 | - | ||
| 1823 | /* Alter each pseudo-reg rtx to contain its hard reg number. Assign | ||
| 1824 | stack slots to the pseudos that lack hard regs or equivalents. | ||
| 1825 | Do not touch virtual registers. */ | ||
| 1826 | @@ -1410,31 +1295,11 @@ | ||
| 1827 | } | ||
| 1828 | } | ||
| 1829 | |||
| 1830 | - /* Indicate that we no longer have known memory locations or constants. */ | ||
| 1831 | - if (reg_equiv_constant) | ||
| 1832 | - free (reg_equiv_constant); | ||
| 1833 | - if (reg_equiv_invariant) | ||
| 1834 | - free (reg_equiv_invariant); | ||
| 1835 | - reg_equiv_constant = 0; | ||
| 1836 | - reg_equiv_invariant = 0; | ||
| 1837 | - VEC_free (rtx, gc, reg_equiv_memory_loc_vec); | ||
| 1838 | - reg_equiv_memory_loc = 0; | ||
| 1839 | - | ||
| 1840 | free (temp_pseudo_reg_arr); | ||
| 1841 | |||
| 1842 | - if (offsets_known_at) | ||
| 1843 | - free (offsets_known_at); | ||
| 1844 | - if (offsets_at) | ||
| 1845 | - free (offsets_at); | ||
| 1846 | - | ||
| 1847 | - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 1848 | - if (reg_equiv_alt_mem_list[i]) | ||
| 1849 | - free_EXPR_LIST_list (®_equiv_alt_mem_list[i]); | ||
| 1850 | - free (reg_equiv_alt_mem_list); | ||
| 1851 | - | ||
| 1852 | - free (reg_equiv_mem); | ||
| 1853 | + /* Indicate that we no longer have known memory locations or constants. */ | ||
| 1854 | + free_reg_equiv (); | ||
| 1855 | reg_equiv_init = 0; | ||
| 1856 | - free (reg_equiv_address); | ||
| 1857 | free (reg_max_ref_width); | ||
| 1858 | free (reg_old_renumber); | ||
| 1859 | free (pseudo_previous_regs); | ||
| 1860 | @@ -1727,6 +1592,100 @@ | ||
| 1861 | *pprev_reload = 0; | ||
| 1862 | } | ||
| 1863 | |||
| 1864 | +/* This function is called from the register allocator to set up estimates | ||
| 1865 | + for the cost of eliminating pseudos which have REG_EQUIV equivalences to | ||
| 1866 | + an invariant. The structure is similar to calculate_needs_all_insns. */ | ||
| 1867 | + | ||
| 1868 | +void | ||
| 1869 | +calculate_elim_costs_all_insns (void) | ||
| 1870 | +{ | ||
| 1871 | + int *reg_equiv_init_cost; | ||
| 1872 | + basic_block bb; | ||
| 1873 | + int i; | ||
| 1874 | + | ||
| 1875 | + reg_equiv_init_cost = XCNEWVEC (int, max_regno); | ||
| 1876 | + init_elim_table (); | ||
| 1877 | + init_eliminable_invariants (get_insns (), false); | ||
| 1878 | + | ||
| 1879 | + set_initial_elim_offsets (); | ||
| 1880 | + set_initial_label_offsets (); | ||
| 1881 | + | ||
| 1882 | + FOR_EACH_BB (bb) | ||
| 1883 | + { | ||
| 1884 | + rtx insn; | ||
| 1885 | + elim_bb = bb; | ||
| 1886 | + | ||
| 1887 | + FOR_BB_INSNS (bb, insn) | ||
| 1888 | + { | ||
| 1889 | + /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might | ||
| 1890 | + include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see | ||
| 1891 | + what effects this has on the known offsets at labels. */ | ||
| 1892 | + | ||
| 1893 | + if (LABEL_P (insn) || JUMP_P (insn) | ||
| 1894 | + || (INSN_P (insn) && REG_NOTES (insn) != 0)) | ||
| 1895 | + set_label_offsets (insn, insn, 0); | ||
| 1896 | + | ||
| 1897 | + if (INSN_P (insn)) | ||
| 1898 | + { | ||
| 1899 | + rtx set = single_set (insn); | ||
| 1900 | + | ||
| 1901 | + /* Skip insns that only set an equivalence. */ | ||
| 1902 | + if (set && REG_P (SET_DEST (set)) | ||
| 1903 | + && reg_renumber[REGNO (SET_DEST (set))] < 0 | ||
| 1904 | + && (reg_equiv_constant[REGNO (SET_DEST (set))] | ||
| 1905 | + || (reg_equiv_invariant[REGNO (SET_DEST (set))]))) | ||
| 1906 | + { | ||
| 1907 | + unsigned regno = REGNO (SET_DEST (set)); | ||
| 1908 | + rtx init = reg_equiv_init[regno]; | ||
| 1909 | + if (init) | ||
| 1910 | + { | ||
| 1911 | + rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn, | ||
| 1912 | + false, true); | ||
| 1913 | + int cost = rtx_cost (t, SET, | ||
| 1914 | + optimize_bb_for_speed_p (bb)); | ||
| 1915 | + int freq = REG_FREQ_FROM_BB (bb); | ||
| 1916 | + | ||
| 1917 | + reg_equiv_init_cost[regno] = cost * freq; | ||
| 1918 | + continue; | ||
| 1919 | + } | ||
| 1920 | + } | ||
| 1921 | + /* If needed, eliminate any eliminable registers. */ | ||
| 1922 | + if (num_eliminable || num_eliminable_invariants) | ||
| 1923 | + elimination_costs_in_insn (insn); | ||
| 1924 | + | ||
| 1925 | + if (num_eliminable) | ||
| 1926 | + update_eliminable_offsets (); | ||
| 1927 | + } | ||
| 1928 | + } | ||
| 1929 | + } | ||
| 1930 | + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | ||
| 1931 | + { | ||
| 1932 | + if (reg_equiv_invariant[i]) | ||
| 1933 | + { | ||
| 1934 | + if (reg_equiv_init[i]) | ||
| 1935 | + { | ||
| 1936 | + int cost = reg_equiv_init_cost[i]; | ||
| 1937 | + if (dump_file) | ||
| 1938 | + fprintf (dump_file, | ||
| 1939 | + "Reg %d has equivalence, initial gains %d\n", i, cost); | ||
| 1940 | + if (cost != 0) | ||
| 1941 | + ira_adjust_equiv_reg_cost (i, cost); | ||
| 1942 | + } | ||
| 1943 | + else | ||
| 1944 | + { | ||
| 1945 | + if (dump_file) | ||
| 1946 | + fprintf (dump_file, | ||
| 1947 | + "Reg %d had equivalence, but can't be eliminated\n", | ||
| 1948 | + i); | ||
| 1949 | + ira_adjust_equiv_reg_cost (i, 0); | ||
| 1950 | + } | ||
| 1951 | + } | ||
| 1952 | + } | ||
| 1953 | + | ||
| 1954 | + free_reg_equiv (); | ||
| 1955 | + free (reg_equiv_init_cost); | ||
| 1956 | +} | ||
| 1957 | + | ||
| 1958 | /* Comparison function for qsort to decide which of two reloads | ||
| 1959 | should be handled first. *P1 and *P2 are the reload numbers. */ | ||
| 1960 | |||
| 1961 | @@ -2513,6 +2472,36 @@ | ||
| 1962 | } | ||
| 1963 | } | ||
| 1964 | |||
| 1965 | +/* Called through for_each_rtx, this function examines every reg that occurs | ||
| 1966 | + in PX and adjusts the costs for its elimination which are gathered by IRA. | ||
| 1967 | + DATA is the insn in which PX occurs. We do not recurse into MEM | ||
| 1968 | + expressions. */ | ||
| 1969 | + | ||
| 1970 | +static int | ||
| 1971 | +note_reg_elim_costly (rtx *px, void *data) | ||
| 1972 | +{ | ||
| 1973 | + rtx insn = (rtx)data; | ||
| 1974 | + rtx x = *px; | ||
| 1975 | + | ||
| 1976 | + if (MEM_P (x)) | ||
| 1977 | + return -1; | ||
| 1978 | + | ||
| 1979 | + if (REG_P (x) | ||
| 1980 | + && REGNO (x) >= FIRST_PSEUDO_REGISTER | ||
| 1981 | + && reg_equiv_init[REGNO (x)] | ||
| 1982 | + && reg_equiv_invariant[REGNO (x)]) | ||
| 1983 | + { | ||
| 1984 | + rtx t = reg_equiv_invariant[REGNO (x)]; | ||
| 1985 | + rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true); | ||
| 1986 | + int cost = rtx_cost (new_rtx, SET, optimize_bb_for_speed_p (elim_bb)); | ||
| 1987 | + int freq = REG_FREQ_FROM_BB (elim_bb); | ||
| 1988 | + | ||
| 1989 | + if (cost != 0) | ||
| 1990 | + ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq); | ||
| 1991 | + } | ||
| 1992 | + return 0; | ||
| 1993 | +} | ||
| 1994 | + | ||
| 1995 | /* Scan X and replace any eliminable registers (such as fp) with a | ||
| 1996 | replacement (such as sp), plus an offset. | ||
| 1997 | |||
| 1998 | @@ -2532,6 +2521,9 @@ | ||
| 1999 | This means, do not set ref_outside_mem even if the reference | ||
| 2000 | is outside of MEMs. | ||
| 2001 | |||
| 2002 | + If FOR_COSTS is true, we are being called before reload in order to | ||
| 2003 | + estimate the costs of keeping registers with an equivalence unallocated. | ||
| 2004 | + | ||
| 2005 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had | ||
| 2006 | replacements done assuming all offsets are at their initial values. If | ||
| 2007 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | ||
| 2008 | @@ -2540,7 +2532,7 @@ | ||
| 2009 | |||
| 2010 | static rtx | ||
| 2011 | eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn, | ||
| 2012 | - bool may_use_invariant) | ||
| 2013 | + bool may_use_invariant, bool for_costs) | ||
| 2014 | { | ||
| 2015 | enum rtx_code code = GET_CODE (x); | ||
| 2016 | struct elim_table *ep; | ||
| 2017 | @@ -2588,11 +2580,12 @@ | ||
| 2018 | { | ||
| 2019 | if (may_use_invariant || (insn && DEBUG_INSN_P (insn))) | ||
| 2020 | return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]), | ||
| 2021 | - mem_mode, insn, true); | ||
| 2022 | + mem_mode, insn, true, for_costs); | ||
| 2023 | /* There exists at least one use of REGNO that cannot be | ||
| 2024 | eliminated. Prevent the defining insn from being deleted. */ | ||
| 2025 | reg_equiv_init[regno] = NULL_RTX; | ||
| 2026 | - alter_reg (regno, -1, true); | ||
| 2027 | + if (!for_costs) | ||
| 2028 | + alter_reg (regno, -1, true); | ||
| 2029 | } | ||
| 2030 | return x; | ||
| 2031 | |||
| 2032 | @@ -2653,8 +2646,10 @@ | ||
| 2033 | operand of a load-address insn. */ | ||
| 2034 | |||
| 2035 | { | ||
| 2036 | - rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); | ||
| 2037 | - rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); | ||
| 2038 | + rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true, | ||
| 2039 | + for_costs); | ||
| 2040 | + rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true, | ||
| 2041 | + for_costs); | ||
| 2042 | |||
| 2043 | if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) | ||
| 2044 | { | ||
| 2045 | @@ -2728,9 +2723,11 @@ | ||
| 2046 | case GE: case GT: case GEU: case GTU: | ||
| 2047 | case LE: case LT: case LEU: case LTU: | ||
| 2048 | { | ||
| 2049 | - rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); | ||
| 2050 | + rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false, | ||
| 2051 | + for_costs); | ||
| 2052 | rtx new1 = XEXP (x, 1) | ||
| 2053 | - ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0; | ||
| 2054 | + ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false, | ||
| 2055 | + for_costs) : 0; | ||
| 2056 | |||
| 2057 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | ||
| 2058 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); | ||
| 2059 | @@ -2741,7 +2738,8 @@ | ||
| 2060 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | ||
| 2061 | if (XEXP (x, 0)) | ||
| 2062 | { | ||
| 2063 | - new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); | ||
| 2064 | + new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true, | ||
| 2065 | + for_costs); | ||
| 2066 | if (new_rtx != XEXP (x, 0)) | ||
| 2067 | { | ||
| 2068 | /* If this is a REG_DEAD note, it is not valid anymore. | ||
| 2069 | @@ -2749,7 +2747,8 @@ | ||
| 2070 | REG_DEAD note for the stack or frame pointer. */ | ||
| 2071 | if (REG_NOTE_KIND (x) == REG_DEAD) | ||
| 2072 | return (XEXP (x, 1) | ||
| 2073 | - ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true) | ||
| 2074 | + ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true, | ||
| 2075 | + for_costs) | ||
| 2076 | : NULL_RTX); | ||
| 2077 | |||
| 2078 | x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1)); | ||
| 2079 | @@ -2764,7 +2763,8 @@ | ||
| 2080 | strictly needed, but it simplifies the code. */ | ||
| 2081 | if (XEXP (x, 1)) | ||
| 2082 | { | ||
| 2083 | - new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); | ||
| 2084 | + new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true, | ||
| 2085 | + for_costs); | ||
| 2086 | if (new_rtx != XEXP (x, 1)) | ||
| 2087 | return | ||
| 2088 | gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx); | ||
| 2089 | @@ -2790,7 +2790,7 @@ | ||
| 2090 | && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) | ||
| 2091 | { | ||
| 2092 | rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode, | ||
| 2093 | - insn, true); | ||
| 2094 | + insn, true, for_costs); | ||
| 2095 | |||
| 2096 | if (new_rtx != XEXP (XEXP (x, 1), 1)) | ||
| 2097 | return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0), | ||
| 2098 | @@ -2813,7 +2813,8 @@ | ||
| 2099 | case POPCOUNT: | ||
| 2100 | case PARITY: | ||
| 2101 | case BSWAP: | ||
| 2102 | - new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); | ||
| 2103 | + new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false, | ||
| 2104 | + for_costs); | ||
| 2105 | if (new_rtx != XEXP (x, 0)) | ||
| 2106 | return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx); | ||
| 2107 | return x; | ||
| 2108 | @@ -2834,7 +2835,8 @@ | ||
| 2109 | new_rtx = SUBREG_REG (x); | ||
| 2110 | } | ||
| 2111 | else | ||
| 2112 | - new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false); | ||
| 2113 | + new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, | ||
| 2114 | + for_costs); | ||
| 2115 | |||
| 2116 | if (new_rtx != SUBREG_REG (x)) | ||
| 2117 | { | ||
| 2118 | @@ -2868,14 +2870,20 @@ | ||
| 2119 | /* Our only special processing is to pass the mode of the MEM to our | ||
| 2120 | recursive call and copy the flags. While we are here, handle this | ||
| 2121 | case more efficiently. */ | ||
| 2122 | - return | ||
| 2123 | - replace_equiv_address_nv (x, | ||
| 2124 | - eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), | ||
| 2125 | - insn, true)); | ||
| 2126 | + | ||
| 2127 | + new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true, | ||
| 2128 | + for_costs); | ||
| 2129 | + if (for_costs | ||
| 2130 | + && memory_address_p (GET_MODE (x), XEXP (x, 0)) | ||
| 2131 | + && !memory_address_p (GET_MODE (x), new_rtx)) | ||
| 2132 | + for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn); | ||
| 2133 | + | ||
| 2134 | + return replace_equiv_address_nv (x, new_rtx); | ||
| 2135 | |||
| 2136 | case USE: | ||
| 2137 | /* Handle insn_list USE that a call to a pure function may generate. */ | ||
| 2138 | - new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false); | ||
| 2139 | + new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false, | ||
| 2140 | + for_costs); | ||
| 2141 | if (new_rtx != XEXP (x, 0)) | ||
| 2142 | return gen_rtx_USE (GET_MODE (x), new_rtx); | ||
| 2143 | return x; | ||
| 2144 | @@ -2899,7 +2907,8 @@ | ||
| 2145 | { | ||
| 2146 | if (*fmt == 'e') | ||
| 2147 | { | ||
| 2148 | - new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false); | ||
| 2149 | + new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false, | ||
| 2150 | + for_costs); | ||
| 2151 | if (new_rtx != XEXP (x, i) && ! copied) | ||
| 2152 | { | ||
| 2153 | x = shallow_copy_rtx (x); | ||
| 2154 | @@ -2912,7 +2921,8 @@ | ||
| 2155 | int copied_vec = 0; | ||
| 2156 | for (j = 0; j < XVECLEN (x, i); j++) | ||
| 2157 | { | ||
| 2158 | - new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false); | ||
| 2159 | + new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false, | ||
| 2160 | + for_costs); | ||
| 2161 | if (new_rtx != XVECEXP (x, i, j) && ! copied_vec) | ||
| 2162 | { | ||
| 2163 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), | ||
| 2164 | @@ -2936,7 +2946,7 @@ | ||
| 2165 | rtx | ||
| 2166 | eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn) | ||
| 2167 | { | ||
| 2168 | - return eliminate_regs_1 (x, mem_mode, insn, false); | ||
| 2169 | + return eliminate_regs_1 (x, mem_mode, insn, false, false); | ||
| 2170 | } | ||
| 2171 | |||
| 2172 | /* Scan rtx X for modifications of elimination target registers. Update | ||
| 2173 | @@ -3454,7 +3464,8 @@ | ||
| 2174 | /* Companion to the above plus substitution, we can allow | ||
| 2175 | invariants as the source of a plain move. */ | ||
| 2176 | is_set_src = false; | ||
| 2177 | - if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set)) | ||
| 2178 | + if (old_set | ||
| 2179 | + && recog_data.operand_loc[i] == &SET_SRC (old_set)) | ||
| 2180 | is_set_src = true; | ||
| 2181 | in_plus = false; | ||
| 2182 | if (plus_src | ||
| 2183 | @@ -3465,7 +3476,7 @@ | ||
| 2184 | substed_operand[i] | ||
| 2185 | = eliminate_regs_1 (recog_data.operand[i], VOIDmode, | ||
| 2186 | replace ? insn : NULL_RTX, | ||
| 2187 | - is_set_src || in_plus); | ||
| 2188 | + is_set_src || in_plus, false); | ||
| 2189 | if (substed_operand[i] != orig_operand[i]) | ||
| 2190 | val = 1; | ||
| 2191 | /* Terminate the search in check_eliminable_occurrences at | ||
| 2192 | @@ -3593,11 +3604,167 @@ | ||
| 2193 | the pre-passes. */ | ||
| 2194 | if (val && REG_NOTES (insn) != 0) | ||
| 2195 | REG_NOTES (insn) | ||
| 2196 | - = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true); | ||
| 2197 | + = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true, | ||
| 2198 | + false); | ||
| 2199 | |||
| 2200 | return val; | ||
| 2201 | } | ||
| 2202 | |||
| 2203 | +/* Like eliminate_regs_in_insn, but only estimate costs for the use of the | ||
| 2204 | + register allocator. INSN is the instruction we need to examine, we perform | ||
| 2205 | + eliminations in its operands and record cases where eliminating a reg with | ||
| 2206 | + an invariant equivalence would add extra cost. */ | ||
| 2207 | + | ||
| 2208 | +static void | ||
| 2209 | +elimination_costs_in_insn (rtx insn) | ||
| 2210 | +{ | ||
| 2211 | + int icode = recog_memoized (insn); | ||
| 2212 | + rtx old_body = PATTERN (insn); | ||
| 2213 | + int insn_is_asm = asm_noperands (old_body) >= 0; | ||
| 2214 | + rtx old_set = single_set (insn); | ||
| 2215 | + int i; | ||
| 2216 | + rtx orig_operand[MAX_RECOG_OPERANDS]; | ||
| 2217 | + rtx orig_dup[MAX_RECOG_OPERANDS]; | ||
| 2218 | + struct elim_table *ep; | ||
| 2219 | + rtx plus_src, plus_cst_src; | ||
| 2220 | + bool sets_reg_p; | ||
| 2221 | + | ||
| 2222 | + if (! insn_is_asm && icode < 0) | ||
| 2223 | + { | ||
| 2224 | + gcc_assert (GET_CODE (PATTERN (insn)) == USE | ||
| 2225 | + || GET_CODE (PATTERN (insn)) == CLOBBER | ||
| 2226 | + || GET_CODE (PATTERN (insn)) == ADDR_VEC | ||
| 2227 | + || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | ||
| 2228 | + || GET_CODE (PATTERN (insn)) == ASM_INPUT | ||
| 2229 | + || DEBUG_INSN_P (insn)); | ||
| 2230 | + return; | ||
| 2231 | + } | ||
| 2232 | + | ||
| 2233 | + if (old_set != 0 && REG_P (SET_DEST (old_set)) | ||
| 2234 | + && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) | ||
| 2235 | + { | ||
| 2236 | + /* Check for setting an eliminable register. */ | ||
| 2237 | + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | ||
| 2238 | + if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) | ||
| 2239 | + return; | ||
| 2240 | + } | ||
| 2241 | + | ||
| 2242 | + /* We allow one special case which happens to work on all machines we | ||
| 2243 | + currently support: a single set with the source or a REG_EQUAL | ||
| 2244 | + note being a PLUS of an eliminable register and a constant. */ | ||
| 2245 | + plus_src = plus_cst_src = 0; | ||
| 2246 | + sets_reg_p = false; | ||
| 2247 | + if (old_set && REG_P (SET_DEST (old_set))) | ||
| 2248 | + { | ||
| 2249 | + sets_reg_p = true; | ||
| 2250 | + if (GET_CODE (SET_SRC (old_set)) == PLUS) | ||
| 2251 | + plus_src = SET_SRC (old_set); | ||
| 2252 | + /* First see if the source is of the form (plus (...) CST). */ | ||
| 2253 | + if (plus_src | ||
| 2254 | + && CONST_INT_P (XEXP (plus_src, 1))) | ||
| 2255 | + plus_cst_src = plus_src; | ||
| 2256 | + else if (REG_P (SET_SRC (old_set)) | ||
| 2257 | + || plus_src) | ||
| 2258 | + { | ||
| 2259 | + /* Otherwise, see if we have a REG_EQUAL note of the form | ||
| 2260 | + (plus (...) CST). */ | ||
| 2261 | + rtx links; | ||
| 2262 | + for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) | ||
| 2263 | + { | ||
| 2264 | + if ((REG_NOTE_KIND (links) == REG_EQUAL | ||
| 2265 | + || REG_NOTE_KIND (links) == REG_EQUIV) | ||
| 2266 | + && GET_CODE (XEXP (links, 0)) == PLUS | ||
| 2267 | + && CONST_INT_P (XEXP (XEXP (links, 0), 1))) | ||
| 2268 | + { | ||
| 2269 | + plus_cst_src = XEXP (links, 0); | ||
| 2270 | + break; | ||
| 2271 | + } | ||
| 2272 | + } | ||
| 2273 | + } | ||
| 2274 | + } | ||
| 2275 | + | ||
| 2276 | + /* Determine the effects of this insn on elimination offsets. */ | ||
| 2277 | + elimination_effects (old_body, VOIDmode); | ||
| 2278 | + | ||
| 2279 | + /* Eliminate all eliminable registers occurring in operands that | ||
| 2280 | + can be handled by reload. */ | ||
| 2281 | + extract_insn (insn); | ||
| 2282 | + for (i = 0; i < recog_data.n_dups; i++) | ||
| 2283 | + orig_dup[i] = *recog_data.dup_loc[i]; | ||
| 2284 | + | ||
| 2285 | + for (i = 0; i < recog_data.n_operands; i++) | ||
| 2286 | + { | ||
| 2287 | + orig_operand[i] = recog_data.operand[i]; | ||
| 2288 | + | ||
| 2289 | + /* For an asm statement, every operand is eliminable. */ | ||
| 2290 | + if (insn_is_asm || insn_data[icode].operand[i].eliminable) | ||
| 2291 | + { | ||
| 2292 | + bool is_set_src, in_plus; | ||
| 2293 | + | ||
| 2294 | + /* Check for setting a register that we know about. */ | ||
| 2295 | + if (recog_data.operand_type[i] != OP_IN | ||
| 2296 | + && REG_P (orig_operand[i])) | ||
| 2297 | + { | ||
| 2298 | + /* If we are assigning to a register that can be eliminated, it | ||
| 2299 | + must be as part of a PARALLEL, since the code above handles | ||
| 2300 | + single SETs. We must indicate that we can no longer | ||
| 2301 | + eliminate this reg. */ | ||
| 2302 | + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | ||
| 2303 | + ep++) | ||
| 2304 | + if (ep->from_rtx == orig_operand[i]) | ||
| 2305 | + ep->can_eliminate = 0; | ||
| 2306 | + } | ||
| 2307 | + | ||
| 2308 | + /* Companion to the above plus substitution, we can allow | ||
| 2309 | + invariants as the source of a plain move. */ | ||
| 2310 | + is_set_src = false; | ||
| 2311 | + if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set)) | ||
| 2312 | + is_set_src = true; | ||
| 2313 | + if (is_set_src && !sets_reg_p) | ||
| 2314 | + note_reg_elim_costly (&SET_SRC (old_set), insn); | ||
| 2315 | + in_plus = false; | ||
| 2316 | + if (plus_src && sets_reg_p | ||
| 2317 | + && (recog_data.operand_loc[i] == &XEXP (plus_src, 0) | ||
| 2318 | + || recog_data.operand_loc[i] == &XEXP (plus_src, 1))) | ||
| 2319 | + in_plus = true; | ||
| 2320 | + | ||
| 2321 | + eliminate_regs_1 (recog_data.operand[i], VOIDmode, | ||
| 2322 | + NULL_RTX, | ||
| 2323 | + is_set_src || in_plus, true); | ||
| 2324 | + /* Terminate the search in check_eliminable_occurrences at | ||
| 2325 | + this point. */ | ||
| 2326 | + *recog_data.operand_loc[i] = 0; | ||
| 2327 | + } | ||
| 2328 | + } | ||
| 2329 | + | ||
| 2330 | + for (i = 0; i < recog_data.n_dups; i++) | ||
| 2331 | + *recog_data.dup_loc[i] | ||
| 2332 | + = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; | ||
| 2333 | + | ||
| 2334 | + /* If any eliminable remain, they aren't eliminable anymore. */ | ||
| 2335 | + check_eliminable_occurrences (old_body); | ||
| 2336 | + | ||
| 2337 | + /* Restore the old body. */ | ||
| 2338 | + for (i = 0; i < recog_data.n_operands; i++) | ||
| 2339 | + *recog_data.operand_loc[i] = orig_operand[i]; | ||
| 2340 | + for (i = 0; i < recog_data.n_dups; i++) | ||
| 2341 | + *recog_data.dup_loc[i] = orig_dup[i]; | ||
| 2342 | + | ||
| 2343 | + /* Update all elimination pairs to reflect the status after the current | ||
| 2344 | + insn. The changes we make were determined by the earlier call to | ||
| 2345 | + elimination_effects. */ | ||
| 2346 | + | ||
| 2347 | + for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | ||
| 2348 | + { | ||
| 2349 | + if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | ||
| 2350 | + ep->can_eliminate = 0; | ||
| 2351 | + | ||
| 2352 | + ep->ref_outside_mem = 0; | ||
| 2353 | + } | ||
| 2354 | + | ||
| 2355 | + return; | ||
| 2356 | +} | ||
| 2357 | + | ||
| 2358 | /* Loop through all elimination pairs. | ||
| 2359 | Recalculate the number not at initial offset. | ||
| 2360 | |||
| 2361 | @@ -3907,6 +4074,168 @@ | ||
| 2362 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | ||
| 2363 | } | ||
| 2364 | } | ||
| 2365 | + | ||
| 2366 | +/* Find all the pseudo registers that didn't get hard regs | ||
| 2367 | + but do have known equivalent constants or memory slots. | ||
| 2368 | + These include parameters (known equivalent to parameter slots) | ||
| 2369 | + and cse'd or loop-moved constant memory addresses. | ||
| 2370 | + | ||
| 2371 | + Record constant equivalents in reg_equiv_constant | ||
| 2372 | + so they will be substituted by find_reloads. | ||
| 2373 | + Record memory equivalents in reg_mem_equiv so they can | ||
| 2374 | + be substituted eventually by altering the REG-rtx's. */ | ||
| 2375 | + | ||
| 2376 | +static void | ||
| 2377 | +init_eliminable_invariants (rtx first, bool do_subregs) | ||
| 2378 | +{ | ||
| 2379 | + int i; | ||
| 2380 | + rtx insn; | ||
| 2381 | + | ||
| 2382 | + reg_equiv_constant = XCNEWVEC (rtx, max_regno); | ||
| 2383 | + reg_equiv_invariant = XCNEWVEC (rtx, max_regno); | ||
| 2384 | + reg_equiv_mem = XCNEWVEC (rtx, max_regno); | ||
| 2385 | + reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno); | ||
| 2386 | + reg_equiv_address = XCNEWVEC (rtx, max_regno); | ||
| 2387 | + if (do_subregs) | ||
| 2388 | + reg_max_ref_width = XCNEWVEC (unsigned int, max_regno); | ||
| 2389 | + else | ||
| 2390 | + reg_max_ref_width = NULL; | ||
| 2391 | + | ||
| 2392 | + num_eliminable_invariants = 0; | ||
| 2393 | + | ||
| 2394 | + first_label_num = get_first_label_num (); | ||
| 2395 | + num_labels = max_label_num () - first_label_num; | ||
| 2396 | + | ||
| 2397 | + /* Allocate the tables used to store offset information at labels. */ | ||
| 2398 | + offsets_known_at = XNEWVEC (char, num_labels); | ||
| 2399 | + offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT)); | ||
| 2400 | + | ||
| 2401 | +/* Look for REG_EQUIV notes; record what each pseudo is equivalent | ||
| 2402 | + to. If DO_SUBREGS is true, also find all paradoxical subregs and | ||
| 2403 | + find largest such for each pseudo. FIRST is the head of the insn | ||
| 2404 | + list. */ | ||
| 2405 | + | ||
| 2406 | + for (insn = first; insn; insn = NEXT_INSN (insn)) | ||
| 2407 | + { | ||
| 2408 | + rtx set = single_set (insn); | ||
| 2409 | + | ||
| 2410 | + /* We may introduce USEs that we want to remove at the end, so | ||
| 2411 | + we'll mark them with QImode. Make sure there are no | ||
| 2412 | + previously-marked insns left by say regmove. */ | ||
| 2413 | + if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE | ||
| 2414 | + && GET_MODE (insn) != VOIDmode) | ||
| 2415 | + PUT_MODE (insn, VOIDmode); | ||
| 2416 | + | ||
| 2417 | + if (do_subregs && NONDEBUG_INSN_P (insn)) | ||
| 2418 | + scan_paradoxical_subregs (PATTERN (insn)); | ||
| 2419 | + | ||
| 2420 | + if (set != 0 && REG_P (SET_DEST (set))) | ||
| 2421 | + { | ||
| 2422 | + rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); | ||
| 2423 | + rtx x; | ||
| 2424 | + | ||
| 2425 | + if (! note) | ||
| 2426 | + continue; | ||
| 2427 | + | ||
| 2428 | + i = REGNO (SET_DEST (set)); | ||
| 2429 | + x = XEXP (note, 0); | ||
| 2430 | + | ||
| 2431 | + if (i <= LAST_VIRTUAL_REGISTER) | ||
| 2432 | + continue; | ||
| 2433 | + | ||
| 2434 | + /* If flag_pic and we have constant, verify it's legitimate. */ | ||
| 2435 | + if (!CONSTANT_P (x) | ||
| 2436 | + || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x)) | ||
| 2437 | + { | ||
| 2438 | + /* It can happen that a REG_EQUIV note contains a MEM | ||
| 2439 | + that is not a legitimate memory operand. As later | ||
| 2440 | + stages of reload assume that all addresses found | ||
| 2441 | + in the reg_equiv_* arrays were originally legitimate, | ||
| 2442 | + we ignore such REG_EQUIV notes. */ | ||
| 2443 | + if (memory_operand (x, VOIDmode)) | ||
| 2444 | + { | ||
| 2445 | + /* Always unshare the equivalence, so we can | ||
| 2446 | + substitute into this insn without touching the | ||
| 2447 | + equivalence. */ | ||
| 2448 | + reg_equiv_memory_loc[i] = copy_rtx (x); | ||
| 2449 | + } | ||
| 2450 | + else if (function_invariant_p (x)) | ||
| 2451 | + { | ||
| 2452 | + if (GET_CODE (x) == PLUS) | ||
| 2453 | + { | ||
| 2454 | + /* This is PLUS of frame pointer and a constant, | ||
| 2455 | + and might be shared. Unshare it. */ | ||
| 2456 | + reg_equiv_invariant[i] = copy_rtx (x); | ||
| 2457 | + num_eliminable_invariants++; | ||
| 2458 | + } | ||
| 2459 | + else if (x == frame_pointer_rtx || x == arg_pointer_rtx) | ||
| 2460 | + { | ||
| 2461 | + reg_equiv_invariant[i] = x; | ||
| 2462 | + num_eliminable_invariants++; | ||
| 2463 | + } | ||
| 2464 | + else if (LEGITIMATE_CONSTANT_P (x)) | ||
| 2465 | + reg_equiv_constant[i] = x; | ||
| 2466 | + else | ||
| 2467 | + { | ||
| 2468 | + reg_equiv_memory_loc[i] | ||
| 2469 | + = force_const_mem (GET_MODE (SET_DEST (set)), x); | ||
| 2470 | + if (! reg_equiv_memory_loc[i]) | ||
| 2471 | + reg_equiv_init[i] = NULL_RTX; | ||
| 2472 | + } | ||
| 2473 | + } | ||
| 2474 | + else | ||
| 2475 | + { | ||
| 2476 | + reg_equiv_init[i] = NULL_RTX; | ||
| 2477 | + continue; | ||
| 2478 | + } | ||
| 2479 | + } | ||
| 2480 | + else | ||
| 2481 | + reg_equiv_init[i] = NULL_RTX; | ||
| 2482 | + } | ||
| 2483 | + } | ||
| 2484 | + | ||
| 2485 | + if (dump_file) | ||
| 2486 | + for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | ||
| 2487 | + if (reg_equiv_init[i]) | ||
| 2488 | + { | ||
| 2489 | + fprintf (dump_file, "init_insns for %u: ", i); | ||
| 2490 | + print_inline_rtx (dump_file, reg_equiv_init[i], 20); | ||
| 2491 | + fprintf (dump_file, "\n"); | ||
| 2492 | + } | ||
| 2493 | +} | ||
| 2494 | + | ||
| 2495 | +/* Indicate that we no longer have known memory locations or constants. | ||
| 2496 | + Free all data involved in tracking these. */ | ||
| 2497 | + | ||
| 2498 | +static void | ||
| 2499 | +free_reg_equiv (void) | ||
| 2500 | +{ | ||
| 2501 | + int i; | ||
| 2502 | + | ||
| 2503 | + if (reg_equiv_constant) | ||
| 2504 | + free (reg_equiv_constant); | ||
| 2505 | + if (reg_equiv_invariant) | ||
| 2506 | + free (reg_equiv_invariant); | ||
| 2507 | + reg_equiv_constant = 0; | ||
| 2508 | + reg_equiv_invariant = 0; | ||
| 2509 | + VEC_free (rtx, gc, reg_equiv_memory_loc_vec); | ||
| 2510 | + reg_equiv_memory_loc = 0; | ||
| 2511 | + | ||
| 2512 | + if (offsets_known_at) | ||
| 2513 | + free (offsets_known_at); | ||
| 2514 | + if (offsets_at) | ||
| 2515 | + free (offsets_at); | ||
| 2516 | + offsets_at = 0; | ||
| 2517 | + offsets_known_at = 0; | ||
| 2518 | + | ||
| 2519 | + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 2520 | + if (reg_equiv_alt_mem_list[i]) | ||
| 2521 | + free_EXPR_LIST_list (®_equiv_alt_mem_list[i]); | ||
| 2522 | + free (reg_equiv_alt_mem_list); | ||
| 2523 | + | ||
| 2524 | + free (reg_equiv_mem); | ||
| 2525 | + free (reg_equiv_address); | ||
| 2526 | +} | ||
| 2527 | |||
| 2528 | /* Kick all pseudos out of hard register REGNO. | ||
| 2529 | |||
| 2530 | @@ -5664,7 +5993,7 @@ | ||
| 2531 | return 1; | ||
| 2532 | if (GET_CODE (x) == PLUS | ||
| 2533 | && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) | ||
| 2534 | - && CONSTANT_P (XEXP (x, 1))) | ||
| 2535 | + && GET_CODE (XEXP (x, 1)) == CONST_INT) | ||
| 2536 | return 1; | ||
| 2537 | return 0; | ||
| 2538 | } | ||
| 2539 | Index: gcc-4_5-branch/gcc/system.h | ||
| 2540 | =================================================================== | ||
| 2541 | --- gcc-4_5-branch.orig/gcc/system.h 2012-03-06 11:53:32.000000000 -0800 | ||
| 2542 | +++ gcc-4_5-branch/gcc/system.h 2012-03-06 12:14:01.060439213 -0800 | ||
| 2543 | @@ -761,7 +761,8 @@ | ||
| 2544 | TARGET_ASM_EXCEPTION_SECTION TARGET_ASM_EH_FRAME_SECTION \ | ||
| 2545 | SMALL_ARG_MAX ASM_OUTPUT_SHARED_BSS ASM_OUTPUT_SHARED_COMMON \ | ||
| 2546 | ASM_OUTPUT_SHARED_LOCAL ASM_MAKE_LABEL_LINKONCE \ | ||
| 2547 | - STACK_CHECK_PROBE_INTERVAL STACK_CHECK_PROBE_LOAD | ||
| 2548 | + STACK_CHECK_PROBE_INTERVAL STACK_CHECK_PROBE_LOAD \ | ||
| 2549 | + ORDER_REGS_FOR_LOCAL_ALLOC | ||
| 2550 | |||
| 2551 | /* Hooks that are no longer used. */ | ||
| 2552 | #pragma GCC poison LANG_HOOKS_FUNCTION_MARK LANG_HOOKS_FUNCTION_FREE \ | ||
| 2553 | Index: gcc-4_5-branch/gcc/testsuite/c-c++-common/uninit-17.c | ||
| 2554 | =================================================================== | ||
| 2555 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 2556 | +++ gcc-4_5-branch/gcc/testsuite/c-c++-common/uninit-17.c 2012-03-06 12:14:01.060439213 -0800 | ||
| 2557 | @@ -0,0 +1,25 @@ | ||
| 2558 | +/* { dg-do compile } */ | ||
| 2559 | +/* { dg-options "-O2 -Wuninitialized" } */ | ||
| 2560 | + | ||
| 2561 | +inline int foo(int x) | ||
| 2562 | +{ | ||
| 2563 | + return x; | ||
| 2564 | +} | ||
| 2565 | +static void bar(int a, int *ptr) | ||
| 2566 | +{ | ||
| 2567 | + do | ||
| 2568 | + { | ||
| 2569 | + int b; /* { dg-warning "is used uninitialized" } */ | ||
| 2570 | + if (b < 40) { | ||
| 2571 | + ptr[0] = b; | ||
| 2572 | + } | ||
| 2573 | + b += 1; | ||
| 2574 | + ptr++; | ||
| 2575 | + } | ||
| 2576 | + while (--a != 0); | ||
| 2577 | +} | ||
| 2578 | +void foobar(int a, int *ptr) | ||
| 2579 | +{ | ||
| 2580 | + bar(foo(a), ptr); | ||
| 2581 | +} | ||
| 2582 | + | ||
| 2583 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/eliminate.c | ||
| 2584 | =================================================================== | ||
| 2585 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 2586 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/eliminate.c 2012-03-06 12:14:01.060439213 -0800 | ||
| 2587 | @@ -0,0 +1,19 @@ | ||
| 2588 | +/* { dg-do compile } */ | ||
| 2589 | +/* { dg-options "-O2" } */ | ||
| 2590 | + | ||
| 2591 | +struct X | ||
| 2592 | +{ | ||
| 2593 | + int c; | ||
| 2594 | +}; | ||
| 2595 | + | ||
| 2596 | +extern void bar(struct X *); | ||
| 2597 | + | ||
| 2598 | +void foo () | ||
| 2599 | +{ | ||
| 2600 | + struct X x; | ||
| 2601 | + bar (&x); | ||
| 2602 | + bar (&x); | ||
| 2603 | + bar (&x); | ||
| 2604 | +} | ||
| 2605 | + | ||
| 2606 | +/* { dg-final { scan-assembler-times "r0,\[\\t \]*sp" 3 } } */ | ||
| 2607 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/pr40900.c | ||
| 2608 | =================================================================== | ||
| 2609 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 2610 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/pr40900.c 2012-03-06 12:14:01.060439213 -0800 | ||
| 2611 | @@ -0,0 +1,12 @@ | ||
| 2612 | +/* { dg-do compile } */ | ||
| 2613 | +/* { dg-options "-O2 -fno-optimize-sibling-calls" } */ | ||
| 2614 | + | ||
| 2615 | +extern short shortv2(); | ||
| 2616 | +short shortv1() | ||
| 2617 | +{ | ||
| 2618 | + return shortv2(); | ||
| 2619 | +} | ||
| 2620 | + | ||
| 2621 | +/* { dg-final { scan-assembler-not "lsl" } } */ | ||
| 2622 | +/* { dg-final { scan-assembler-not "asr" } } */ | ||
| 2623 | +/* { dg-final { scan-assembler-not "sxth" } } */ | ||
| 2624 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/pr42496.c | ||
| 2625 | =================================================================== | ||
| 2626 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 2627 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/pr42496.c 2012-03-06 12:14:01.060439213 -0800 | ||
| 2628 | @@ -0,0 +1,16 @@ | ||
| 2629 | +/* { dg-options "-O2" } */ | ||
| 2630 | + | ||
| 2631 | +void foo(int i) | ||
| 2632 | +{ | ||
| 2633 | + extern int j; | ||
| 2634 | + | ||
| 2635 | + if (i) { | ||
| 2636 | + j = 10; | ||
| 2637 | + } | ||
| 2638 | + else { | ||
| 2639 | + j = 20; | ||
| 2640 | + } | ||
| 2641 | +} | ||
| 2642 | + | ||
| 2643 | +/* { dg-final { scan-assembler-not "strne" } } */ | ||
| 2644 | +/* { dg-final { scan-assembler-not "streq" } } */ | ||
| 2645 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-1.c | ||
| 2646 | =================================================================== | ||
| 2647 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 2648 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-1.c 2012-03-06 12:14:01.060439213 -0800 | ||
| 2649 | @@ -0,0 +1,18 @@ | ||
| 2650 | +/* { dg-do compile } */ | ||
| 2651 | +/* { dg-options "-O2 -march=armv6t2 -fno-unroll-loops" } */ | ||
| 2652 | + | ||
| 2653 | +int mac(const short *a, const short *b, int sqr, int *sum) | ||
| 2654 | +{ | ||
| 2655 | + int i; | ||
| 2656 | + int dotp = *sum; | ||
| 2657 | + | ||
| 2658 | + for (i = 0; i < 150; i++) { | ||
| 2659 | + dotp += b[i] * a[i]; | ||
| 2660 | + sqr += b[i] * b[i]; | ||
| 2661 | + } | ||
| 2662 | + | ||
| 2663 | + *sum = dotp; | ||
| 2664 | + return sqr; | ||
| 2665 | +} | ||
| 2666 | + | ||
| 2667 | +/* { dg-final { scan-assembler-times "smulbb" 2 } } */ | ||
| 2668 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-2.c | ||
| 2669 | =================================================================== | ||
| 2670 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 2671 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-2.c 2012-03-06 12:14:01.064439219 -0800 | ||
| 2672 | @@ -0,0 +1,12 @@ | ||
| 2673 | +/* { dg-do compile } */ | ||
| 2674 | +/* { dg-options "-O2 -march=armv6t2 -fno-unroll-loops" } */ | ||
| 2675 | + | ||
| 2676 | +void vec_mpy(int y[], const short x[], short scaler) | ||
| 2677 | +{ | ||
| 2678 | + int i; | ||
| 2679 | + | ||
| 2680 | + for (i = 0; i < 150; i++) | ||
| 2681 | + y[i] += ((scaler * x[i]) >> 31); | ||
| 2682 | +} | ||
| 2683 | + | ||
| 2684 | +/* { dg-final { scan-assembler-times "smulbb" 1 } } */ | ||
| 2685 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/bfin/wmul-1.c | ||
| 2686 | =================================================================== | ||
| 2687 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 2688 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/bfin/wmul-1.c 2012-03-06 12:14:01.064439219 -0800 | ||
| 2689 | @@ -0,0 +1,18 @@ | ||
| 2690 | +/* { dg-do compile } */ | ||
| 2691 | +/* { dg-options "-O2" } */ | ||
| 2692 | + | ||
| 2693 | +int mac(const short *a, const short *b, int sqr, int *sum) | ||
| 2694 | +{ | ||
| 2695 | + int i; | ||
| 2696 | + int dotp = *sum; | ||
| 2697 | + | ||
| 2698 | + for (i = 0; i < 150; i++) { | ||
| 2699 | + dotp += b[i] * a[i]; | ||
| 2700 | + sqr += b[i] * b[i]; | ||
| 2701 | + } | ||
| 2702 | + | ||
| 2703 | + *sum = dotp; | ||
| 2704 | + return sqr; | ||
| 2705 | +} | ||
| 2706 | + | ||
| 2707 | +/* { dg-final { scan-assembler-times "\\(IS\\)" 2 } } */ | ||
| 2708 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/bfin/wmul-2.c | ||
| 2709 | =================================================================== | ||
| 2710 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 2711 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/bfin/wmul-2.c 2012-03-06 12:14:01.064439219 -0800 | ||
| 2712 | @@ -0,0 +1,12 @@ | ||
| 2713 | +/* { dg-do compile } */ | ||
| 2714 | +/* { dg-options "-O2" } */ | ||
| 2715 | + | ||
| 2716 | +void vec_mpy(int y[], const short x[], short scaler) | ||
| 2717 | +{ | ||
| 2718 | + int i; | ||
| 2719 | + | ||
| 2720 | + for (i = 0; i < 150; i++) | ||
| 2721 | + y[i] += ((scaler * x[i]) >> 31); | ||
| 2722 | +} | ||
| 2723 | + | ||
| 2724 | +/* { dg-final { scan-assembler-times "\\(IS\\)" 1 } } */ | ||
| 2725 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/pr41442.c | ||
| 2726 | =================================================================== | ||
| 2727 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 2728 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/pr41442.c 2012-03-06 12:14:01.064439219 -0800 | ||
| 2729 | @@ -0,0 +1,18 @@ | ||
| 2730 | +/* { dg-do compile } */ | ||
| 2731 | +/* { dg-options "-O2" } */ | ||
| 2732 | + | ||
| 2733 | +typedef struct LINK link; | ||
| 2734 | +struct LINK | ||
| 2735 | +{ | ||
| 2736 | + link* next; | ||
| 2737 | +}; | ||
| 2738 | + | ||
| 2739 | +int haha(link* p1, link* p2) | ||
| 2740 | +{ | ||
| 2741 | + if ((p1->next && !p2->next) || p2->next) | ||
| 2742 | + return 0; | ||
| 2743 | + | ||
| 2744 | + return 1; | ||
| 2745 | +} | ||
| 2746 | + | ||
| 2747 | +/* { dg-final { scan-assembler-times "test|cmp" 2 } } */ | ||
| 2748 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/wmul-1.c | ||
| 2749 | =================================================================== | ||
| 2750 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 2751 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/wmul-1.c 2012-03-06 12:14:01.064439219 -0800 | ||
| 2752 | @@ -0,0 +1,18 @@ | ||
| 2753 | +/* { dg-do compile } */ | ||
| 2754 | +/* { dg-options "-O2" } */ | ||
| 2755 | + | ||
| 2756 | +long long mac(const int *a, const int *b, long long sqr, long long *sum) | ||
| 2757 | +{ | ||
| 2758 | + int i; | ||
| 2759 | + long long dotp = *sum; | ||
| 2760 | + | ||
| 2761 | + for (i = 0; i < 150; i++) { | ||
| 2762 | + dotp += (long long)b[i] * a[i]; | ||
| 2763 | + sqr += (long long)b[i] * b[i]; | ||
| 2764 | + } | ||
| 2765 | + | ||
| 2766 | + *sum = dotp; | ||
| 2767 | + return sqr; | ||
| 2768 | +} | ||
| 2769 | + | ||
| 2770 | +/* { dg-final { scan-assembler-times "imull" 2 } } */ | ||
| 2771 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/wmul-2.c | ||
| 2772 | =================================================================== | ||
| 2773 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 2774 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/wmul-2.c 2012-03-06 12:14:01.064439219 -0800 | ||
| 2775 | @@ -0,0 +1,12 @@ | ||
| 2776 | +/* { dg-do compile } */ | ||
| 2777 | +/* { dg-options "-O2" } */ | ||
| 2778 | + | ||
| 2779 | +void vec_mpy(int y[], const int x[], int scaler) | ||
| 2780 | +{ | ||
| 2781 | + int i; | ||
| 2782 | + | ||
| 2783 | + for (i = 0; i < 150; i++) | ||
| 2784 | + y[i] += (((long long)scaler * x[i]) >> 31); | ||
| 2785 | +} | ||
| 2786 | + | ||
| 2787 | +/* { dg-final { scan-assembler-times "imull" 1 } } */ | ||
| 2788 | Index: gcc-4_5-branch/gcc/tree-cfg.c | ||
| 2789 | =================================================================== | ||
| 2790 | --- gcc-4_5-branch.orig/gcc/tree-cfg.c 2012-03-06 12:11:30.000000000 -0800 | ||
| 2791 | +++ gcc-4_5-branch/gcc/tree-cfg.c 2012-03-06 12:14:01.064439219 -0800 | ||
| 2792 | @@ -3429,8 +3429,13 @@ | ||
| 2793 | connected to the operand types. */ | ||
| 2794 | return verify_gimple_comparison (lhs_type, rhs1, rhs2); | ||
| 2795 | |||
| 2796 | - case WIDEN_SUM_EXPR: | ||
| 2797 | case WIDEN_MULT_EXPR: | ||
| 2798 | + if (TREE_CODE (lhs_type) != INTEGER_TYPE) | ||
| 2799 | + return true; | ||
| 2800 | + return ((2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type)) | ||
| 2801 | + || (TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type))); | ||
| 2802 | + | ||
| 2803 | + case WIDEN_SUM_EXPR: | ||
| 2804 | case VEC_WIDEN_MULT_HI_EXPR: | ||
| 2805 | case VEC_WIDEN_MULT_LO_EXPR: | ||
| 2806 | case VEC_PACK_TRUNC_EXPR: | ||
| 2807 | Index: gcc-4_5-branch/gcc/tree-inline.c | ||
| 2808 | =================================================================== | ||
| 2809 | --- gcc-4_5-branch.orig/gcc/tree-inline.c 2012-03-06 12:11:30.000000000 -0800 | ||
| 2810 | +++ gcc-4_5-branch/gcc/tree-inline.c 2012-03-06 12:14:01.064439219 -0800 | ||
| 2811 | @@ -229,6 +229,7 @@ | ||
| 2812 | regions of the CFG, but this is expensive to test. */ | ||
| 2813 | if (id->entry_bb | ||
| 2814 | && is_gimple_reg (SSA_NAME_VAR (name)) | ||
| 2815 | + && SSA_NAME_OCCURS_IN_ABNORMAL_PHI (name) | ||
| 2816 | && TREE_CODE (SSA_NAME_VAR (name)) != PARM_DECL | ||
| 2817 | && (id->entry_bb != EDGE_SUCC (ENTRY_BLOCK_PTR, 0)->dest | ||
| 2818 | || EDGE_COUNT (id->entry_bb->preds) != 1)) | ||
| 2819 | Index: gcc-4_5-branch/gcc/tree-pass.h | ||
| 2820 | =================================================================== | ||
| 2821 | --- gcc-4_5-branch.orig/gcc/tree-pass.h 2012-03-06 11:53:32.000000000 -0800 | ||
| 2822 | +++ gcc-4_5-branch/gcc/tree-pass.h 2012-03-06 12:14:01.068439233 -0800 | ||
| 2823 | @@ -407,6 +407,7 @@ | ||
| 2824 | extern struct gimple_opt_pass pass_cse_reciprocals; | ||
| 2825 | extern struct gimple_opt_pass pass_cse_sincos; | ||
| 2826 | extern struct gimple_opt_pass pass_optimize_bswap; | ||
| 2827 | +extern struct gimple_opt_pass pass_optimize_widening_mul; | ||
| 2828 | extern struct gimple_opt_pass pass_warn_function_return; | ||
| 2829 | extern struct gimple_opt_pass pass_warn_function_noreturn; | ||
| 2830 | extern struct gimple_opt_pass pass_cselim; | ||
| 2831 | Index: gcc-4_5-branch/gcc/tree-ssa-math-opts.c | ||
| 2832 | =================================================================== | ||
| 2833 | --- gcc-4_5-branch.orig/gcc/tree-ssa-math-opts.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 2834 | +++ gcc-4_5-branch/gcc/tree-ssa-math-opts.c 2012-03-06 12:14:01.068439233 -0800 | ||
| 2835 | @@ -1269,3 +1269,137 @@ | ||
| 2836 | 0 /* todo_flags_finish */ | ||
| 2837 | } | ||
| 2838 | }; | ||
| 2839 | + | ||
| 2840 | +/* Find integer multiplications where the operands are extended from | ||
| 2841 | + smaller types, and replace the MULT_EXPR with a WIDEN_MULT_EXPR | ||
| 2842 | + where appropriate. */ | ||
| 2843 | + | ||
| 2844 | +static unsigned int | ||
| 2845 | +execute_optimize_widening_mul (void) | ||
| 2846 | +{ | ||
| 2847 | + bool changed = false; | ||
| 2848 | + basic_block bb; | ||
| 2849 | + | ||
| 2850 | + FOR_EACH_BB (bb) | ||
| 2851 | + { | ||
| 2852 | + gimple_stmt_iterator gsi; | ||
| 2853 | + | ||
| 2854 | + for (gsi = gsi_after_labels (bb); !gsi_end_p (gsi); gsi_next (&gsi)) | ||
| 2855 | + { | ||
| 2856 | + gimple stmt = gsi_stmt (gsi); | ||
| 2857 | + gimple rhs1_stmt = NULL, rhs2_stmt = NULL; | ||
| 2858 | + tree type, type1 = NULL, type2 = NULL; | ||
| 2859 | + tree rhs1, rhs2, rhs1_convop = NULL, rhs2_convop = NULL; | ||
| 2860 | + enum tree_code rhs1_code, rhs2_code; | ||
| 2861 | + | ||
| 2862 | + if (!is_gimple_assign (stmt) | ||
| 2863 | + || gimple_assign_rhs_code (stmt) != MULT_EXPR) | ||
| 2864 | + continue; | ||
| 2865 | + | ||
| 2866 | + type = TREE_TYPE (gimple_assign_lhs (stmt)); | ||
| 2867 | + | ||
| 2868 | + if (TREE_CODE (type) != INTEGER_TYPE) | ||
| 2869 | + continue; | ||
| 2870 | + | ||
| 2871 | + rhs1 = gimple_assign_rhs1 (stmt); | ||
| 2872 | + rhs2 = gimple_assign_rhs2 (stmt); | ||
| 2873 | + | ||
| 2874 | + if (TREE_CODE (rhs1) == SSA_NAME) | ||
| 2875 | + { | ||
| 2876 | + rhs1_stmt = SSA_NAME_DEF_STMT (rhs1); | ||
| 2877 | + if (!is_gimple_assign (rhs1_stmt)) | ||
| 2878 | + continue; | ||
| 2879 | + rhs1_code = gimple_assign_rhs_code (rhs1_stmt); | ||
| 2880 | + if (!CONVERT_EXPR_CODE_P (rhs1_code)) | ||
| 2881 | + continue; | ||
| 2882 | + rhs1_convop = gimple_assign_rhs1 (rhs1_stmt); | ||
| 2883 | + type1 = TREE_TYPE (rhs1_convop); | ||
| 2884 | + if (TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type)) | ||
| 2885 | + continue; | ||
| 2886 | + } | ||
| 2887 | + else if (TREE_CODE (rhs1) != INTEGER_CST) | ||
| 2888 | + continue; | ||
| 2889 | + | ||
| 2890 | + if (TREE_CODE (rhs2) == SSA_NAME) | ||
| 2891 | + { | ||
| 2892 | + rhs2_stmt = SSA_NAME_DEF_STMT (rhs2); | ||
| 2893 | + if (!is_gimple_assign (rhs2_stmt)) | ||
| 2894 | + continue; | ||
| 2895 | + rhs2_code = gimple_assign_rhs_code (rhs2_stmt); | ||
| 2896 | + if (!CONVERT_EXPR_CODE_P (rhs2_code)) | ||
| 2897 | + continue; | ||
| 2898 | + rhs2_convop = gimple_assign_rhs1 (rhs2_stmt); | ||
| 2899 | + type2 = TREE_TYPE (rhs2_convop); | ||
| 2900 | + if (TYPE_PRECISION (type2) * 2 != TYPE_PRECISION (type)) | ||
| 2901 | + continue; | ||
| 2902 | + } | ||
| 2903 | + else if (TREE_CODE (rhs2) != INTEGER_CST) | ||
| 2904 | + continue; | ||
| 2905 | + | ||
| 2906 | + if (rhs1_stmt == NULL && rhs2_stmt == NULL) | ||
| 2907 | + continue; | ||
| 2908 | + | ||
| 2909 | + /* Verify that the machine can perform a widening multiply in this | ||
| 2910 | + mode/signedness combination, otherwise this transformation is | ||
| 2911 | + likely to pessimize code. */ | ||
| 2912 | + if ((rhs1_stmt == NULL || TYPE_UNSIGNED (type1)) | ||
| 2913 | + && (rhs2_stmt == NULL || TYPE_UNSIGNED (type2)) | ||
| 2914 | + && (optab_handler (umul_widen_optab, TYPE_MODE (type)) | ||
| 2915 | + ->insn_code == CODE_FOR_nothing)) | ||
| 2916 | + continue; | ||
| 2917 | + else if ((rhs1_stmt == NULL || !TYPE_UNSIGNED (type1)) | ||
| 2918 | + && (rhs2_stmt == NULL || !TYPE_UNSIGNED (type2)) | ||
| 2919 | + && (optab_handler (smul_widen_optab, TYPE_MODE (type)) | ||
| 2920 | + ->insn_code == CODE_FOR_nothing)) | ||
| 2921 | + continue; | ||
| 2922 | + else if (rhs1_stmt != NULL && rhs2_stmt != 0 | ||
| 2923 | + && (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2)) | ||
| 2924 | + && (optab_handler (usmul_widen_optab, TYPE_MODE (type)) | ||
| 2925 | + ->insn_code == CODE_FOR_nothing)) | ||
| 2926 | + continue; | ||
| 2927 | + | ||
| 2928 | + if ((rhs1_stmt == NULL && !int_fits_type_p (rhs1, type2)) | ||
| 2929 | + || (rhs2_stmt == NULL && !int_fits_type_p (rhs2, type1))) | ||
| 2930 | + continue; | ||
| 2931 | + | ||
| 2932 | + if (rhs1_stmt == NULL) | ||
| 2933 | + gimple_assign_set_rhs1 (stmt, fold_convert (type2, rhs1)); | ||
| 2934 | + else | ||
| 2935 | + gimple_assign_set_rhs1 (stmt, rhs1_convop); | ||
| 2936 | + if (rhs2_stmt == NULL) | ||
| 2937 | + gimple_assign_set_rhs2 (stmt, fold_convert (type1, rhs2)); | ||
| 2938 | + else | ||
| 2939 | + gimple_assign_set_rhs2 (stmt, rhs2_convop); | ||
| 2940 | + gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR); | ||
| 2941 | + update_stmt (stmt); | ||
| 2942 | + changed = true; | ||
| 2943 | + } | ||
| 2944 | + } | ||
| 2945 | + return (changed ? TODO_dump_func | TODO_update_ssa | TODO_verify_ssa | ||
| 2946 | + | TODO_verify_stmts : 0); | ||
| 2947 | +} | ||
| 2948 | + | ||
| 2949 | +static bool | ||
| 2950 | +gate_optimize_widening_mul (void) | ||
| 2951 | +{ | ||
| 2952 | + return flag_expensive_optimizations && optimize; | ||
| 2953 | +} | ||
| 2954 | + | ||
| 2955 | +struct gimple_opt_pass pass_optimize_widening_mul = | ||
| 2956 | +{ | ||
| 2957 | + { | ||
| 2958 | + GIMPLE_PASS, | ||
| 2959 | + "widening_mul", /* name */ | ||
| 2960 | + gate_optimize_widening_mul, /* gate */ | ||
| 2961 | + execute_optimize_widening_mul, /* execute */ | ||
| 2962 | + NULL, /* sub */ | ||
| 2963 | + NULL, /* next */ | ||
| 2964 | + 0, /* static_pass_number */ | ||
| 2965 | + TV_NONE, /* tv_id */ | ||
| 2966 | + PROP_ssa, /* properties_required */ | ||
| 2967 | + 0, /* properties_provided */ | ||
| 2968 | + 0, /* properties_destroyed */ | ||
| 2969 | + 0, /* todo_flags_start */ | ||
| 2970 | + 0 /* todo_flags_finish */ | ||
| 2971 | + } | ||
| 2972 | +}; | ||
| 2973 | Index: gcc-4_5-branch/gcc/tree-ssa.c | ||
| 2974 | =================================================================== | ||
| 2975 | --- gcc-4_5-branch.orig/gcc/tree-ssa.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 2976 | +++ gcc-4_5-branch/gcc/tree-ssa.c 2012-03-06 12:14:01.068439233 -0800 | ||
| 2977 | @@ -1671,6 +1671,8 @@ | ||
| 2978 | { | ||
| 2979 | TREE_NO_WARNING (var) = 1; | ||
| 2980 | |||
| 2981 | + if (location == DECL_SOURCE_LOCATION (var)) | ||
| 2982 | + return; | ||
| 2983 | if (xloc.file != floc.file | ||
| 2984 | || xloc.line < floc.line | ||
| 2985 | || xloc.line > LOCATION_LINE (cfun->function_end_locus)) | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99381.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99381.patch deleted file mode 100644 index c504f44fb..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99381.patch +++ /dev/null | |||
| @@ -1,512 +0,0 @@ | |||
| 1 | 2010-09-06 Mark Mitchell <mark@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #9022 | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | 2010-09-05 Mark Mitchell <mark@codesourcery.com> | ||
| 7 | * doc/invoke.texi: Document -Wdouble-promotion. | ||
| 8 | * c-typeck.c (convert_arguments): Check for implicit conversions | ||
| 9 | from float to double. | ||
| 10 | (do_warn_double_promotion): New function. | ||
| 11 | (build_conditional_expr): Use it. | ||
| 12 | (build_binary_op): Likewise. | ||
| 13 | * c.opt (Wdouble-promotion): New. | ||
| 14 | 2010-09-05 Mark Mitchell <mark@codesourcery.com> | ||
| 15 | * gcc.dg/Wdouble-promotion.c: New. | ||
| 16 | 2010-09-06 Mark Mitchell <mark@codesourcery.com> | ||
| 17 | gcc/ | ||
| 18 | * c-common.h (do_warn_double_promotion): Declare. | ||
| 19 | * c-common.c (do_warn_double_promotion): Define. | ||
| 20 | * c-typeck.c (do_warn_double_promotion): Remove. | ||
| 21 | * doc/invoke.texi (-Wdouble-promotion): Note available for C++ and | ||
| 22 | Objective-C++ too. | ||
| 23 | gcc/cp/ | ||
| 24 | * typeck.c (cp_build_binary_op): Call do_warn_double_promotion. | ||
| 25 | * call.c (build_conditional_expr): Likewise. | ||
| 26 | (convert_arg_to_ellipsis): Likewise. | ||
| 27 | gcc/testsuite/ | ||
| 28 | * g++.dg/warn/Wdouble-promotion.C: New. | ||
| 29 | |||
| 30 | 2010-08-31 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 31 | |||
| 32 | Backport from mainline: | ||
| 33 | |||
| 34 | === modified file 'gcc/c-common.c' | ||
| 35 | --- old/gcc/c-common.c 2010-06-25 09:35:40 +0000 | ||
| 36 | +++ new/gcc/c-common.c 2010-09-07 15:47:57 +0000 | ||
| 37 | @@ -9172,6 +9172,40 @@ | ||
| 38 | } | ||
| 39 | } | ||
| 40 | |||
| 41 | +/* RESULT_TYPE is the result of converting TYPE1 and TYPE2 to a common | ||
| 42 | + type via c_common_type. If -Wdouble-promotion is in use, and the | ||
| 43 | + conditions for warning have been met, issue a warning. GMSGID is | ||
| 44 | + the warning message. It must have two %T specifiers for the type | ||
| 45 | + that was converted (generally "float") and the type to which it was | ||
| 46 | + converted (generally "double), respectively. LOC is the location | ||
| 47 | + to which the awrning should refer. */ | ||
| 48 | + | ||
| 49 | +void | ||
| 50 | +do_warn_double_promotion (tree result_type, tree type1, tree type2, | ||
| 51 | + const char *gmsgid, location_t loc) | ||
| 52 | +{ | ||
| 53 | + tree source_type; | ||
| 54 | + | ||
| 55 | + if (!warn_double_promotion) | ||
| 56 | + return; | ||
| 57 | + /* If the conversion will not occur at run-time, there is no need to | ||
| 58 | + warn about it. */ | ||
| 59 | + if (c_inhibit_evaluation_warnings) | ||
| 60 | + return; | ||
| 61 | + if (TYPE_MAIN_VARIANT (result_type) != double_type_node | ||
| 62 | + && TYPE_MAIN_VARIANT (result_type) != complex_double_type_node) | ||
| 63 | + return; | ||
| 64 | + if (TYPE_MAIN_VARIANT (type1) == float_type_node | ||
| 65 | + || TYPE_MAIN_VARIANT (type1) == complex_float_type_node) | ||
| 66 | + source_type = type1; | ||
| 67 | + else if (TYPE_MAIN_VARIANT (type2) == float_type_node | ||
| 68 | + || TYPE_MAIN_VARIANT (type2) == complex_float_type_node) | ||
| 69 | + source_type = type2; | ||
| 70 | + else | ||
| 71 | + return; | ||
| 72 | + warning_at (loc, OPT_Wdouble_promotion, gmsgid, source_type, result_type); | ||
| 73 | +} | ||
| 74 | + | ||
| 75 | /* Setup a TYPE_DECL node as a typedef representation. | ||
| 76 | |||
| 77 | X is a TYPE_DECL for a typedef statement. Create a brand new | ||
| 78 | |||
| 79 | === modified file 'gcc/c-common.h' | ||
| 80 | --- old/gcc/c-common.h 2009-12-17 03:22:22 +0000 | ||
| 81 | +++ new/gcc/c-common.h 2010-09-07 15:47:57 +0000 | ||
| 82 | @@ -1056,6 +1056,8 @@ | ||
| 83 | tree op0, tree op1, | ||
| 84 | tree result_type, | ||
| 85 | enum tree_code resultcode); | ||
| 86 | +extern void do_warn_double_promotion (tree, tree, tree, const char *, | ||
| 87 | + location_t); | ||
| 88 | extern void set_underlying_type (tree x); | ||
| 89 | extern bool is_typedef_decl (tree x); | ||
| 90 | extern VEC(tree,gc) *make_tree_vector (void); | ||
| 91 | |||
| 92 | === modified file 'gcc/c-typeck.c' | ||
| 93 | --- old/gcc/c-typeck.c 2010-04-02 18:54:46 +0000 | ||
| 94 | +++ new/gcc/c-typeck.c 2010-09-07 15:47:57 +0000 | ||
| 95 | @@ -3012,8 +3012,15 @@ | ||
| 96 | if (type_generic) | ||
| 97 | parmval = val; | ||
| 98 | else | ||
| 99 | - /* Convert `float' to `double'. */ | ||
| 100 | - parmval = convert (double_type_node, val); | ||
| 101 | + { | ||
| 102 | + /* Convert `float' to `double'. */ | ||
| 103 | + if (warn_double_promotion && !c_inhibit_evaluation_warnings) | ||
| 104 | + warning (OPT_Wdouble_promotion, | ||
| 105 | + "implicit conversion from %qT to %qT when passing " | ||
| 106 | + "argument to function", | ||
| 107 | + valtype, double_type_node); | ||
| 108 | + parmval = convert (double_type_node, val); | ||
| 109 | + } | ||
| 110 | } | ||
| 111 | else if (excess_precision && !type_generic) | ||
| 112 | /* A "double" argument with excess precision being passed | ||
| 113 | @@ -4036,6 +4043,10 @@ | ||
| 114 | || code2 == COMPLEX_TYPE)) | ||
| 115 | { | ||
| 116 | result_type = c_common_type (type1, type2); | ||
| 117 | + do_warn_double_promotion (result_type, type1, type2, | ||
| 118 | + "implicit conversion from %qT to %qT to " | ||
| 119 | + "match other result of conditional", | ||
| 120 | + colon_loc); | ||
| 121 | |||
| 122 | /* If -Wsign-compare, warn here if type1 and type2 have | ||
| 123 | different signedness. We'll promote the signed to unsigned | ||
| 124 | @@ -9607,6 +9618,11 @@ | ||
| 125 | if (shorten || common || short_compare) | ||
| 126 | { | ||
| 127 | result_type = c_common_type (type0, type1); | ||
| 128 | + do_warn_double_promotion (result_type, type0, type1, | ||
| 129 | + "implicit conversion from %qT to %qT " | ||
| 130 | + "to match other operand of binary " | ||
| 131 | + "expression", | ||
| 132 | + location); | ||
| 133 | if (result_type == error_mark_node) | ||
| 134 | return error_mark_node; | ||
| 135 | } | ||
| 136 | |||
| 137 | === modified file 'gcc/c.opt' | ||
| 138 | --- old/gcc/c.opt 2010-04-02 18:54:46 +0000 | ||
| 139 | +++ new/gcc/c.opt 2010-09-07 15:47:57 +0000 | ||
| 140 | @@ -265,6 +265,10 @@ | ||
| 141 | Wimplicit | ||
| 142 | C ObjC C++ ObjC++ Warning | ||
| 143 | |||
| 144 | +Wdouble-promotion | ||
| 145 | +C ObjC C++ ObjC++ Var(warn_double_promotion) Warning | ||
| 146 | +Warn about implicit conversions from \"float\" to \"double\" | ||
| 147 | + | ||
| 148 | Wimplicit-function-declaration | ||
| 149 | C ObjC Var(warn_implicit_function_declaration) Init(-1) Warning | ||
| 150 | Warn about implicit function declarations | ||
| 151 | |||
| 152 | === modified file 'gcc/cp/call.c' | ||
| 153 | --- old/gcc/cp/call.c 2010-07-08 13:08:36 +0000 | ||
| 154 | +++ new/gcc/cp/call.c 2010-09-07 15:47:57 +0000 | ||
| 155 | @@ -3946,6 +3946,10 @@ | ||
| 156 | /* In this case, there is always a common type. */ | ||
| 157 | result_type = type_after_usual_arithmetic_conversions (arg2_type, | ||
| 158 | arg3_type); | ||
| 159 | + do_warn_double_promotion (result_type, arg2_type, arg3_type, | ||
| 160 | + "implicit conversion from %qT to %qT to " | ||
| 161 | + "match other result of conditional", | ||
| 162 | + input_location); | ||
| 163 | |||
| 164 | if (TREE_CODE (arg2_type) == ENUMERAL_TYPE | ||
| 165 | && TREE_CODE (arg3_type) == ENUMERAL_TYPE) | ||
| 166 | @@ -5179,11 +5183,14 @@ | ||
| 167 | tree | ||
| 168 | convert_arg_to_ellipsis (tree arg) | ||
| 169 | { | ||
| 170 | + tree arg_type; | ||
| 171 | + | ||
| 172 | /* [expr.call] | ||
| 173 | |||
| 174 | The lvalue-to-rvalue, array-to-pointer, and function-to-pointer | ||
| 175 | standard conversions are performed. */ | ||
| 176 | arg = decay_conversion (arg); | ||
| 177 | + arg_type = TREE_TYPE (arg); | ||
| 178 | /* [expr.call] | ||
| 179 | |||
| 180 | If the argument has integral or enumeration type that is subject | ||
| 181 | @@ -5191,19 +5198,27 @@ | ||
| 182 | type that is subject to the floating point promotion | ||
| 183 | (_conv.fpprom_), the value of the argument is converted to the | ||
| 184 | promoted type before the call. */ | ||
| 185 | - if (TREE_CODE (TREE_TYPE (arg)) == REAL_TYPE | ||
| 186 | - && (TYPE_PRECISION (TREE_TYPE (arg)) | ||
| 187 | + if (TREE_CODE (arg_type) == REAL_TYPE | ||
| 188 | + && (TYPE_PRECISION (arg_type) | ||
| 189 | < TYPE_PRECISION (double_type_node)) | ||
| 190 | - && !DECIMAL_FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (arg)))) | ||
| 191 | - arg = convert_to_real (double_type_node, arg); | ||
| 192 | - else if (INTEGRAL_OR_ENUMERATION_TYPE_P (TREE_TYPE (arg))) | ||
| 193 | + && !DECIMAL_FLOAT_MODE_P (TYPE_MODE (arg_type))) | ||
| 194 | + { | ||
| 195 | + if (warn_double_promotion && !c_inhibit_evaluation_warnings) | ||
| 196 | + warning (OPT_Wdouble_promotion, | ||
| 197 | + "implicit conversion from %qT to %qT when passing " | ||
| 198 | + "argument to function", | ||
| 199 | + arg_type, double_type_node); | ||
| 200 | + arg = convert_to_real (double_type_node, arg); | ||
| 201 | + } | ||
| 202 | + else if (INTEGRAL_OR_ENUMERATION_TYPE_P (arg_type)) | ||
| 203 | arg = perform_integral_promotions (arg); | ||
| 204 | |||
| 205 | arg = require_complete_type (arg); | ||
| 206 | + arg_type = TREE_TYPE (arg); | ||
| 207 | |||
| 208 | if (arg != error_mark_node | ||
| 209 | - && (type_has_nontrivial_copy_init (TREE_TYPE (arg)) | ||
| 210 | - || TYPE_HAS_NONTRIVIAL_DESTRUCTOR (TREE_TYPE (arg)))) | ||
| 211 | + && (type_has_nontrivial_copy_init (arg_type) | ||
| 212 | + || TYPE_HAS_NONTRIVIAL_DESTRUCTOR (arg_type))) | ||
| 213 | { | ||
| 214 | /* [expr.call] 5.2.2/7: | ||
| 215 | Passing a potentially-evaluated argument of class type (Clause 9) | ||
| 216 | @@ -5218,7 +5233,7 @@ | ||
| 217 | it is not potentially-evaluated. */ | ||
| 218 | if (cp_unevaluated_operand == 0) | ||
| 219 | error ("cannot pass objects of non-trivially-copyable " | ||
| 220 | - "type %q#T through %<...%>", TREE_TYPE (arg)); | ||
| 221 | + "type %q#T through %<...%>", arg_type); | ||
| 222 | } | ||
| 223 | |||
| 224 | return arg; | ||
| 225 | |||
| 226 | === modified file 'gcc/cp/typeck.c' | ||
| 227 | --- old/gcc/cp/typeck.c 2010-06-30 21:06:28 +0000 | ||
| 228 | +++ new/gcc/cp/typeck.c 2010-09-07 15:47:57 +0000 | ||
| 229 | @@ -260,6 +260,7 @@ | ||
| 230 | enum tree_code code2 = TREE_CODE (t2); | ||
| 231 | tree attributes; | ||
| 232 | |||
| 233 | + | ||
| 234 | /* In what follows, we slightly generalize the rules given in [expr] so | ||
| 235 | as to deal with `long long' and `complex'. First, merge the | ||
| 236 | attributes. */ | ||
| 237 | @@ -4226,7 +4227,14 @@ | ||
| 238 | if (!result_type | ||
| 239 | && arithmetic_types_p | ||
| 240 | && (shorten || common || short_compare)) | ||
| 241 | - result_type = cp_common_type (type0, type1); | ||
| 242 | + { | ||
| 243 | + result_type = cp_common_type (type0, type1); | ||
| 244 | + do_warn_double_promotion (result_type, type0, type1, | ||
| 245 | + "implicit conversion from %qT to %qT " | ||
| 246 | + "to match other operand of binary " | ||
| 247 | + "expression", | ||
| 248 | + location); | ||
| 249 | + } | ||
| 250 | |||
| 251 | if (!result_type) | ||
| 252 | { | ||
| 253 | |||
| 254 | === modified file 'gcc/doc/invoke.texi' | ||
| 255 | --- old/gcc/doc/invoke.texi 2010-08-16 09:41:58 +0000 | ||
| 256 | +++ new/gcc/doc/invoke.texi 2010-09-07 15:47:57 +0000 | ||
| 257 | @@ -234,8 +234,8 @@ | ||
| 258 | -Wchar-subscripts -Wclobbered -Wcomment @gol | ||
| 259 | -Wconversion -Wcoverage-mismatch -Wno-deprecated @gol | ||
| 260 | -Wno-deprecated-declarations -Wdisabled-optimization @gol | ||
| 261 | --Wno-div-by-zero -Wempty-body -Wenum-compare -Wno-endif-labels @gol | ||
| 262 | --Werror -Werror=* @gol | ||
| 263 | +-Wno-div-by-zero -Wdouble-promotion -Wempty-body -Wenum-compare @gol | ||
| 264 | +-Wno-endif-labels -Werror -Werror=* @gol | ||
| 265 | -Wfatal-errors -Wfloat-equal -Wformat -Wformat=2 @gol | ||
| 266 | -Wno-format-contains-nul -Wno-format-extra-args -Wformat-nonliteral @gol | ||
| 267 | -Wformat-security -Wformat-y2k @gol | ||
| 268 | @@ -2976,6 +2976,30 @@ | ||
| 269 | comment, or whenever a Backslash-Newline appears in a @samp{//} comment. | ||
| 270 | This warning is enabled by @option{-Wall}. | ||
| 271 | |||
| 272 | +@item -Wdouble-promotion @r{(C, C++, Objective-C and Objective-C++ only)} | ||
| 273 | +@opindex Wdouble-promotion | ||
| 274 | +@opindex Wno-double-promotion | ||
| 275 | +Give a warning when a value of type @code{float} is implicitly | ||
| 276 | +promoted to @code{double}. CPUs with a 32-bit ``single-precision'' | ||
| 277 | +floating-point unit implement @code{float} in hardware, but emulate | ||
| 278 | +@code{double} in software. On such a machine, doing computations | ||
| 279 | +using @code{double} values is much more expensive because of the | ||
| 280 | +overhead required for software emulation. | ||
| 281 | + | ||
| 282 | +It is easy to accidentally do computations with @code{double} because | ||
| 283 | +floating-point literals are implicitly of type @code{double}. For | ||
| 284 | +example, in: | ||
| 285 | +@smallexample | ||
| 286 | +@group | ||
| 287 | +float area(float radius) | ||
| 288 | +@{ | ||
| 289 | + return 3.14159 * radius * radius; | ||
| 290 | +@} | ||
| 291 | +@end group | ||
| 292 | +@end smallexample | ||
| 293 | +the compiler will perform the entire computation with @code{double} | ||
| 294 | +because the floating-point literal is a @code{double}. | ||
| 295 | + | ||
| 296 | @item -Wformat | ||
| 297 | @opindex Wformat | ||
| 298 | @opindex Wno-format | ||
| 299 | |||
| 300 | === added file 'gcc/testsuite/g++.dg/warn/Wdouble-promotion.C' | ||
| 301 | --- old/gcc/testsuite/g++.dg/warn/Wdouble-promotion.C 1970-01-01 00:00:00 +0000 | ||
| 302 | +++ new/gcc/testsuite/g++.dg/warn/Wdouble-promotion.C 2010-09-07 15:47:57 +0000 | ||
| 303 | @@ -0,0 +1,99 @@ | ||
| 304 | +/* { dg-do compile } */ | ||
| 305 | +/* { dg-options "-Wdouble-promotion" } */ | ||
| 306 | + | ||
| 307 | +#include <stddef.h> | ||
| 308 | + | ||
| 309 | +/* Some targets do not provide <complex.h> so we define I ourselves. */ | ||
| 310 | +#define I 1.0iF | ||
| 311 | +#define ID ((_Complex double)I) | ||
| 312 | + | ||
| 313 | +float f; | ||
| 314 | +double d; | ||
| 315 | +int i; | ||
| 316 | +long double ld; | ||
| 317 | +_Complex float cf; | ||
| 318 | +_Complex double cd; | ||
| 319 | +_Complex long double cld; | ||
| 320 | +size_t s; | ||
| 321 | + | ||
| 322 | +extern void varargs_fn (int, ...); | ||
| 323 | +extern void double_fn (double); | ||
| 324 | +extern float float_fn (void); | ||
| 325 | + | ||
| 326 | +void | ||
| 327 | +usual_arithmetic_conversions(void) | ||
| 328 | +{ | ||
| 329 | + float local_f; | ||
| 330 | + _Complex float local_cf; | ||
| 331 | + | ||
| 332 | + /* Values of type "float" are implicitly converted to "double" or | ||
| 333 | + "long double" due to use in arithmetic with "double" or "long | ||
| 334 | + double" operands. */ | ||
| 335 | + local_f = f + 1.0; /* { dg-warning "implicit" } */ | ||
| 336 | + local_f = f - d; /* { dg-warning "implicit" } */ | ||
| 337 | + local_f = 1.0f * 1.0; /* { dg-warning "implicit" } */ | ||
| 338 | + local_f = 1.0f / d; /* { dg-warning "implicit" } */ | ||
| 339 | + | ||
| 340 | + local_cf = cf + 1.0; /* { dg-warning "implicit" } */ | ||
| 341 | + local_cf = cf - d; /* { dg-warning "implicit" } */ | ||
| 342 | + local_cf = cf + 1.0 * ID; /* { dg-warning "implicit" } */ | ||
| 343 | + local_cf = cf - cd; /* { dg-warning "implicit" } */ | ||
| 344 | + | ||
| 345 | + local_f = i ? f : d; /* { dg-warning "implicit" } */ | ||
| 346 | + i = f == d; /* { dg-warning "implicit" } */ | ||
| 347 | + i = d != f; /* { dg-warning "implicit" } */ | ||
| 348 | +} | ||
| 349 | + | ||
| 350 | +void | ||
| 351 | +default_argument_promotion (void) | ||
| 352 | +{ | ||
| 353 | + /* Because "f" is part of the variable argument list, it is promoted | ||
| 354 | + to "double". */ | ||
| 355 | + varargs_fn (1, f); /* { dg-warning "implicit" } */ | ||
| 356 | +} | ||
| 357 | + | ||
| 358 | +/* There is no warning when an explicit cast is used to perform the | ||
| 359 | + conversion. */ | ||
| 360 | + | ||
| 361 | +void | ||
| 362 | +casts (void) | ||
| 363 | +{ | ||
| 364 | + float local_f; | ||
| 365 | + _Complex float local_cf; | ||
| 366 | + | ||
| 367 | + local_f = (double)f + 1.0; /* { dg-bogus "implicit" } */ | ||
| 368 | + local_f = (double)f - d; /* { dg-bogus "implicit" } */ | ||
| 369 | + local_f = (double)1.0f + 1.0; /* { dg-bogus "implicit" } */ | ||
| 370 | + local_f = (double)1.0f - d; /* { dg-bogus "implicit" } */ | ||
| 371 | + | ||
| 372 | + local_cf = (_Complex double)cf + 1.0; /* { dg-bogus "implicit" } */ | ||
| 373 | + local_cf = (_Complex double)cf - d; /* { dg-bogus "implicit" } */ | ||
| 374 | + local_cf = (_Complex double)cf + 1.0 * ID; /* { dg-bogus "implicit" } */ | ||
| 375 | + local_cf = (_Complex double)cf - cd; /* { dg-bogus "implicit" } */ | ||
| 376 | + | ||
| 377 | + local_f = i ? (double)f : d; /* { dg-bogus "implicit" } */ | ||
| 378 | + i = (double)f == d; /* { dg-bogus "implicit" } */ | ||
| 379 | + i = d != (double)f; /* { dg-bogus "implicit" } */ | ||
| 380 | +} | ||
| 381 | + | ||
| 382 | +/* There is no warning on conversions that occur in assignment (and | ||
| 383 | + assignment-like) contexts. */ | ||
| 384 | + | ||
| 385 | +void | ||
| 386 | +assignments (void) | ||
| 387 | +{ | ||
| 388 | + d = f; /* { dg-bogus "implicit" } */ | ||
| 389 | + double_fn (f); /* { dg-bogus "implicit" } */ | ||
| 390 | + d = float_fn (); /* { dg-bogus "implicit" } */ | ||
| 391 | +} | ||
| 392 | + | ||
| 393 | +/* There is no warning in non-evaluated contexts. */ | ||
| 394 | + | ||
| 395 | +void | ||
| 396 | +non_evaluated (void) | ||
| 397 | +{ | ||
| 398 | + s = sizeof (f + 1.0); /* { dg-bogus "implicit" } */ | ||
| 399 | + s = __alignof__ (f + 1.0); /* { dg-bogus "implicit" } */ | ||
| 400 | + d = (__typeof__(f + 1.0))f; /* { dg-bogus "implicit" } */ | ||
| 401 | + s = sizeof (i ? f : d); /* { dg-bogus "implicit" } */ | ||
| 402 | +} | ||
| 403 | |||
| 404 | === added file 'gcc/testsuite/gcc.dg/Wdouble-promotion.c' | ||
| 405 | --- old/gcc/testsuite/gcc.dg/Wdouble-promotion.c 1970-01-01 00:00:00 +0000 | ||
| 406 | +++ new/gcc/testsuite/gcc.dg/Wdouble-promotion.c 2010-09-07 15:47:57 +0000 | ||
| 407 | @@ -0,0 +1,104 @@ | ||
| 408 | +/* { dg-do compile } */ | ||
| 409 | +/* { dg-options "-Wdouble-promotion" } */ | ||
| 410 | + | ||
| 411 | +#include <stddef.h> | ||
| 412 | + | ||
| 413 | +/* Some targets do not provide <complex.h> so we define I ourselves. */ | ||
| 414 | +#define I 1.0iF | ||
| 415 | +#define ID ((_Complex double)I) | ||
| 416 | + | ||
| 417 | +float f; | ||
| 418 | +double d; | ||
| 419 | +int i; | ||
| 420 | +long double ld; | ||
| 421 | +_Complex float cf; | ||
| 422 | +_Complex double cd; | ||
| 423 | +_Complex long double cld; | ||
| 424 | +size_t s; | ||
| 425 | + | ||
| 426 | +extern void unprototyped_fn (); | ||
| 427 | +extern void varargs_fn (int, ...); | ||
| 428 | +extern void double_fn (double); | ||
| 429 | +extern float float_fn (void); | ||
| 430 | + | ||
| 431 | +void | ||
| 432 | +usual_arithmetic_conversions(void) | ||
| 433 | +{ | ||
| 434 | + float local_f; | ||
| 435 | + _Complex float local_cf; | ||
| 436 | + | ||
| 437 | + /* Values of type "float" are implicitly converted to "double" or | ||
| 438 | + "long double" due to use in arithmetic with "double" or "long | ||
| 439 | + double" operands. */ | ||
| 440 | + local_f = f + 1.0; /* { dg-warning "implicit" } */ | ||
| 441 | + local_f = f - d; /* { dg-warning "implicit" } */ | ||
| 442 | + local_f = 1.0f * 1.0; /* { dg-warning "implicit" } */ | ||
| 443 | + local_f = 1.0f / d; /* { dg-warning "implicit" } */ | ||
| 444 | + | ||
| 445 | + local_cf = cf + 1.0; /* { dg-warning "implicit" } */ | ||
| 446 | + local_cf = cf - d; /* { dg-warning "implicit" } */ | ||
| 447 | + local_cf = cf + 1.0 * ID; /* { dg-warning "implicit" } */ | ||
| 448 | + local_cf = cf - cd; /* { dg-warning "implicit" } */ | ||
| 449 | + | ||
| 450 | + local_f = i ? f : d; /* { dg-warning "implicit" } */ | ||
| 451 | + i = f == d; /* { dg-warning "implicit" } */ | ||
| 452 | + i = d != f; /* { dg-warning "implicit" } */ | ||
| 453 | +} | ||
| 454 | + | ||
| 455 | +void | ||
| 456 | +default_argument_promotion (void) | ||
| 457 | +{ | ||
| 458 | + /* Because there is no prototype, "f" is promoted to "double". */ | ||
| 459 | + unprototyped_fn (f); /* { dg-warning "implicit" } */ | ||
| 460 | + undeclared_fn (f); /* { dg-warning "implicit" } */ | ||
| 461 | + /* Because "f" is part of the variable argument list, it is promoted | ||
| 462 | + to "double". */ | ||
| 463 | + varargs_fn (1, f); /* { dg-warning "implicit" } */ | ||
| 464 | +} | ||
| 465 | + | ||
| 466 | +/* There is no warning when an explicit cast is used to perform the | ||
| 467 | + conversion. */ | ||
| 468 | + | ||
| 469 | +void | ||
| 470 | +casts (void) | ||
| 471 | +{ | ||
| 472 | + float local_f; | ||
| 473 | + _Complex float local_cf; | ||
| 474 | + | ||
| 475 | + local_f = (double)f + 1.0; /* { dg-bogus "implicit" } */ | ||
| 476 | + local_f = (double)f - d; /* { dg-bogus "implicit" } */ | ||
| 477 | + local_f = (double)1.0f + 1.0; /* { dg-bogus "implicit" } */ | ||
| 478 | + local_f = (double)1.0f - d; /* { dg-bogus "implicit" } */ | ||
| 479 | + | ||
| 480 | + local_cf = (_Complex double)cf + 1.0; /* { dg-bogus "implicit" } */ | ||
| 481 | + local_cf = (_Complex double)cf - d; /* { dg-bogus "implicit" } */ | ||
| 482 | + local_cf = (_Complex double)cf + 1.0 * ID; /* { dg-bogus "implicit" } */ | ||
| 483 | + local_cf = (_Complex double)cf - cd; /* { dg-bogus "implicit" } */ | ||
| 484 | + | ||
| 485 | + local_f = i ? (double)f : d; /* { dg-bogus "implicit" } */ | ||
| 486 | + i = (double)f == d; /* { dg-bogus "implicit" } */ | ||
| 487 | + i = d != (double)f; /* { dg-bogus "implicit" } */ | ||
| 488 | +} | ||
| 489 | + | ||
| 490 | +/* There is no warning on conversions that occur in assignment (and | ||
| 491 | + assignment-like) contexts. */ | ||
| 492 | + | ||
| 493 | +void | ||
| 494 | +assignments (void) | ||
| 495 | +{ | ||
| 496 | + d = f; /* { dg-bogus "implicit" } */ | ||
| 497 | + double_fn (f); /* { dg-bogus "implicit" } */ | ||
| 498 | + d = float_fn (); /* { dg-bogus "implicit" } */ | ||
| 499 | +} | ||
| 500 | + | ||
| 501 | +/* There is no warning in non-evaluated contexts. */ | ||
| 502 | + | ||
| 503 | +void | ||
| 504 | +non_evaluated (void) | ||
| 505 | +{ | ||
| 506 | + s = sizeof (f + 1.0); /* { dg-bogus "implicit" } */ | ||
| 507 | + s = __alignof__ (f + 1.0); /* { dg-bogus "implicit" } */ | ||
| 508 | + d = (__typeof__(f + 1.0))f; /* { dg-bogus "implicit" } */ | ||
| 509 | + s = sizeof (i ? f : d); /* { dg-bogus "implicit" } */ | ||
| 510 | + s = sizeof (unprototyped_fn (f)); /* { dg-bogus "implicit" } */ | ||
| 511 | +} | ||
| 512 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch deleted file mode 100644 index 82a9e93e4..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99383.patch +++ /dev/null | |||
| @@ -1,369 +0,0 @@ | |||
| 1 | 2010-09-09 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-08-25 Tejas Belagod <tejas.belagod@arm.com> | ||
| 6 | * config/arm/iterators.md (VU, SE, V_widen_l): New. | ||
| 7 | (V_unpack, US): New. | ||
| 8 | * config/arm/neon.md (vec_unpack<US>_hi_<mode>): Expansion for | ||
| 9 | vmovl. | ||
| 10 | (vec_unpack<US>_lo_<mode>): Likewise. | ||
| 11 | (neon_vec_unpack<US>_hi_<mode>): Instruction pattern for vmovl. | ||
| 12 | (neon_vec_unpack<US>_lo_<mode>): Likewise. | ||
| 13 | (vec_widen_<US>mult_lo_<mode>): Expansion for vmull. | ||
| 14 | (vec_widen_<US>mult_hi_<mode>): Likewise. | ||
| 15 | (neon_vec_<US>mult_lo_<mode>"): Instruction pattern for vmull. | ||
| 16 | (neon_vec_<US>mult_hi_<mode>"): Likewise. | ||
| 17 | (neon_unpack<US>_<mode>): Widening move intermediate step for | ||
| 18 | vectorizing without -mvectorize-with-neon-quad. | ||
| 19 | (neon_vec_<US>mult_<mode>): Widening multiply intermediate step | ||
| 20 | for vectorizing without -mvectorize-with-neon-quad. | ||
| 21 | * config/arm/predicates.md (vect_par_constant_high): Check for | ||
| 22 | high-half lanes of a vector. | ||
| 23 | (vect_par_constant_low): Check for low-half lanes of a vector. | ||
| 24 | |||
| 25 | 2010-08-25 Tejas Belagod <tejas.belagod@arm.com> | ||
| 26 | * lib/target-supports.exp (check_effective_target_vect_unpack): | ||
| 27 | Set vect_unpack supported flag to true for neon. | ||
| 28 | |||
| 29 | 2010-09-07 Andrew Stubbs <ams@codesourcery.com> | ||
| 30 | |||
| 31 | Backport from gcc-patches: | ||
| 32 | |||
| 33 | === modified file 'gcc/config/arm/arm.md' | ||
| 34 | --- old/gcc/config/arm/arm.md 2010-09-01 13:29:58 +0000 | ||
| 35 | +++ new/gcc/config/arm/arm.md 2010-09-09 14:11:34 +0000 | ||
| 36 | @@ -868,6 +868,9 @@ | ||
| 37 | (define_code_attr cnb [(ltu "CC_C") (geu "CC")]) | ||
| 38 | (define_code_attr optab [(ltu "ltu") (geu "geu")]) | ||
| 39 | |||
| 40 | +;; Assembler mnemonics for signedness of widening operations. | ||
| 41 | +(define_code_attr US [(sign_extend "s") (zero_extend "u")]) | ||
| 42 | + | ||
| 43 | (define_insn "*addsi3_carryin_<optab>" | ||
| 44 | [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 45 | (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r") | ||
| 46 | |||
| 47 | === modified file 'gcc/config/arm/neon.md' | ||
| 48 | --- old/gcc/config/arm/neon.md 2010-08-23 14:29:45 +0000 | ||
| 49 | +++ new/gcc/config/arm/neon.md 2010-09-09 14:11:34 +0000 | ||
| 50 | @@ -235,6 +235,9 @@ | ||
| 51 | ;; Modes with 32-bit elements only. | ||
| 52 | (define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) | ||
| 53 | |||
| 54 | +;; Modes with 8-bit, 16-bit and 32-bit elements. | ||
| 55 | +(define_mode_iterator VU [V16QI V8HI V4SI]) | ||
| 56 | + | ||
| 57 | ;; (Opposite) mode to convert to/from for above conversions. | ||
| 58 | (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") | ||
| 59 | (V4SI "V4SF") (V4SF "V4SI")]) | ||
| 60 | @@ -388,6 +391,9 @@ | ||
| 61 | ;; Same, without unsigned variants (for use with *SFmode pattern). | ||
| 62 | (define_code_iterator vqhs_ops [plus smin smax]) | ||
| 63 | |||
| 64 | +;; A list of widening operators | ||
| 65 | +(define_code_iterator SE [sign_extend zero_extend]) | ||
| 66 | + | ||
| 67 | ;; Assembler mnemonics for above codes. | ||
| 68 | (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") | ||
| 69 | (umin "vmin") (umax "vmax")]) | ||
| 70 | @@ -443,6 +449,12 @@ | ||
| 71 | (V2SF "2") (V4SF "4") | ||
| 72 | (DI "1") (V2DI "2")]) | ||
| 73 | |||
| 74 | +;; Same as V_widen, but lower-case. | ||
| 75 | +(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) | ||
| 76 | + | ||
| 77 | +;; Widen. Result is half the number of elements, but widened to double-width. | ||
| 78 | +(define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) | ||
| 79 | + | ||
| 80 | (define_insn "*neon_mov<mode>" | ||
| 81 | [(set (match_operand:VD 0 "nonimmediate_operand" | ||
| 82 | "=w,Uv,w, w, ?r,?w,?r,?r, ?Us") | ||
| 83 | @@ -5540,3 +5552,205 @@ | ||
| 84 | emit_insn (gen_orn<mode>3_neon (operands[0], operands[1], operands[2])); | ||
| 85 | DONE; | ||
| 86 | }) | ||
| 87 | + | ||
| 88 | +(define_insn "neon_vec_unpack<US>_lo_<mode>" | ||
| 89 | + [(set (match_operand:<V_unpack> 0 "register_operand" "=w") | ||
| 90 | + (SE:<V_unpack> (vec_select:<V_HALF> | ||
| 91 | + (match_operand:VU 1 "register_operand" "w") | ||
| 92 | + (match_operand:VU 2 "vect_par_constant_low" ""))))] | ||
| 93 | + "TARGET_NEON" | ||
| 94 | + "vmovl.<US><V_sz_elem> %q0, %e1" | ||
| 95 | + [(set_attr "neon_type" "neon_shift_1")] | ||
| 96 | +) | ||
| 97 | + | ||
| 98 | +(define_insn "neon_vec_unpack<US>_hi_<mode>" | ||
| 99 | + [(set (match_operand:<V_unpack> 0 "register_operand" "=w") | ||
| 100 | + (SE:<V_unpack> (vec_select:<V_HALF> | ||
| 101 | + (match_operand:VU 1 "register_operand" "w") | ||
| 102 | + (match_operand:VU 2 "vect_par_constant_high" ""))))] | ||
| 103 | + "TARGET_NEON" | ||
| 104 | + "vmovl.<US><V_sz_elem> %q0, %f1" | ||
| 105 | + [(set_attr "neon_type" "neon_shift_1")] | ||
| 106 | +) | ||
| 107 | + | ||
| 108 | +(define_expand "vec_unpack<US>_hi_<mode>" | ||
| 109 | + [(match_operand:<V_unpack> 0 "register_operand" "") | ||
| 110 | + (SE:<V_unpack> (match_operand:VU 1 "register_operand"))] | ||
| 111 | + "TARGET_NEON" | ||
| 112 | + { | ||
| 113 | + rtvec v = rtvec_alloc (<V_mode_nunits>/2) ; | ||
| 114 | + rtx t1; | ||
| 115 | + int i; | ||
| 116 | + for (i = 0; i < (<V_mode_nunits>/2); i++) | ||
| 117 | + RTVEC_ELT (v, i) = GEN_INT ((<V_mode_nunits>/2) + i); | ||
| 118 | + | ||
| 119 | + t1 = gen_rtx_PARALLEL (<MODE>mode, v); | ||
| 120 | + emit_insn (gen_neon_vec_unpack<US>_hi_<mode> (operands[0], | ||
| 121 | + operands[1], | ||
| 122 | + t1)); | ||
| 123 | + DONE; | ||
| 124 | + } | ||
| 125 | +) | ||
| 126 | + | ||
| 127 | +(define_expand "vec_unpack<US>_lo_<mode>" | ||
| 128 | + [(match_operand:<V_unpack> 0 "register_operand" "") | ||
| 129 | + (SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))] | ||
| 130 | + "TARGET_NEON" | ||
| 131 | + { | ||
| 132 | + rtvec v = rtvec_alloc (<V_mode_nunits>/2) ; | ||
| 133 | + rtx t1; | ||
| 134 | + int i; | ||
| 135 | + for (i = 0; i < (<V_mode_nunits>/2) ; i++) | ||
| 136 | + RTVEC_ELT (v, i) = GEN_INT (i); | ||
| 137 | + t1 = gen_rtx_PARALLEL (<MODE>mode, v); | ||
| 138 | + emit_insn (gen_neon_vec_unpack<US>_lo_<mode> (operands[0], | ||
| 139 | + operands[1], | ||
| 140 | + t1)); | ||
| 141 | + DONE; | ||
| 142 | + } | ||
| 143 | +) | ||
| 144 | + | ||
| 145 | +(define_insn "neon_vec_<US>mult_lo_<mode>" | ||
| 146 | + [(set (match_operand:<V_unpack> 0 "register_operand" "=w") | ||
| 147 | + (mult:<V_unpack> (SE:<V_unpack> (vec_select:<V_HALF> | ||
| 148 | + (match_operand:VU 1 "register_operand" "w") | ||
| 149 | + (match_operand:VU 2 "vect_par_constant_low" ""))) | ||
| 150 | + (SE:<V_unpack> (vec_select:<V_HALF> | ||
| 151 | + (match_operand:VU 3 "register_operand" "w") | ||
| 152 | + (match_dup 2)))))] | ||
| 153 | + "TARGET_NEON" | ||
| 154 | + "vmull.<US><V_sz_elem> %q0, %e1, %e3" | ||
| 155 | + [(set_attr "neon_type" "neon_shift_1")] | ||
| 156 | +) | ||
| 157 | + | ||
| 158 | +(define_expand "vec_widen_<US>mult_lo_<mode>" | ||
| 159 | + [(match_operand:<V_unpack> 0 "register_operand" "") | ||
| 160 | + (SE:<V_unpack> (match_operand:VU 1 "register_operand" "")) | ||
| 161 | + (SE:<V_unpack> (match_operand:VU 2 "register_operand" ""))] | ||
| 162 | + "TARGET_NEON" | ||
| 163 | + { | ||
| 164 | + rtvec v = rtvec_alloc (<V_mode_nunits>/2) ; | ||
| 165 | + rtx t1; | ||
| 166 | + int i; | ||
| 167 | + for (i = 0; i < (<V_mode_nunits>/2) ; i++) | ||
| 168 | + RTVEC_ELT (v, i) = GEN_INT (i); | ||
| 169 | + t1 = gen_rtx_PARALLEL (<MODE>mode, v); | ||
| 170 | + | ||
| 171 | + emit_insn (gen_neon_vec_<US>mult_lo_<mode> (operands[0], | ||
| 172 | + operands[1], | ||
| 173 | + t1, | ||
| 174 | + operands[2])); | ||
| 175 | + DONE; | ||
| 176 | + } | ||
| 177 | +) | ||
| 178 | + | ||
| 179 | +(define_insn "neon_vec_<US>mult_hi_<mode>" | ||
| 180 | + [(set (match_operand:<V_unpack> 0 "register_operand" "=w") | ||
| 181 | + (mult:<V_unpack> (SE:<V_unpack> (vec_select:<V_HALF> | ||
| 182 | + (match_operand:VU 1 "register_operand" "w") | ||
| 183 | + (match_operand:VU 2 "vect_par_constant_high" ""))) | ||
| 184 | + (SE:<V_unpack> (vec_select:<V_HALF> | ||
| 185 | + (match_operand:VU 3 "register_operand" "w") | ||
| 186 | + (match_dup 2)))))] | ||
| 187 | + "TARGET_NEON" | ||
| 188 | + "vmull.<US><V_sz_elem> %q0, %f1, %f3" | ||
| 189 | + [(set_attr "neon_type" "neon_shift_1")] | ||
| 190 | +) | ||
| 191 | + | ||
| 192 | +(define_expand "vec_widen_<US>mult_hi_<mode>" | ||
| 193 | + [(match_operand:<V_unpack> 0 "register_operand" "") | ||
| 194 | + (SE:<V_unpack> (match_operand:VU 1 "register_operand" "")) | ||
| 195 | + (SE:<V_unpack> (match_operand:VU 2 "register_operand" ""))] | ||
| 196 | + "TARGET_NEON" | ||
| 197 | + { | ||
| 198 | + rtvec v = rtvec_alloc (<V_mode_nunits>/2) ; | ||
| 199 | + rtx t1; | ||
| 200 | + int i; | ||
| 201 | + for (i = 0; i < (<V_mode_nunits>/2) ; i++) | ||
| 202 | + RTVEC_ELT (v, i) = GEN_INT (<V_mode_nunits>/2 + i); | ||
| 203 | + t1 = gen_rtx_PARALLEL (<MODE>mode, v); | ||
| 204 | + | ||
| 205 | + emit_insn (gen_neon_vec_<US>mult_hi_<mode> (operands[0], | ||
| 206 | + operands[1], | ||
| 207 | + t1, | ||
| 208 | + operands[2])); | ||
| 209 | + DONE; | ||
| 210 | + | ||
| 211 | + } | ||
| 212 | +) | ||
| 213 | + | ||
| 214 | +;; Vectorize for non-neon-quad case | ||
| 215 | +(define_insn "neon_unpack<US>_<mode>" | ||
| 216 | + [(set (match_operand:<V_widen> 0 "register_operand" "=w") | ||
| 217 | + (SE:<V_widen> (match_operand:VDI 1 "register_operand" "")))] | ||
| 218 | + "TARGET_NEON" | ||
| 219 | + "vmovl.<US><V_sz_elem> %q0, %1" | ||
| 220 | + [(set_attr "neon_type" "neon_shift_1")] | ||
| 221 | +) | ||
| 222 | + | ||
| 223 | +(define_expand "vec_unpack<US>_lo_<mode>" | ||
| 224 | + [(match_operand:<V_double_width> 0 "register_operand" "") | ||
| 225 | + (SE:<V_double_width>(match_operand:VDI 1 "register_operand"))] | ||
| 226 | + "TARGET_NEON" | ||
| 227 | +{ | ||
| 228 | + rtx tmpreg = gen_reg_rtx (<V_widen>mode); | ||
| 229 | + emit_insn (gen_neon_unpack<US>_<mode> (tmpreg, operands[1])); | ||
| 230 | + emit_insn (gen_neon_vget_low<V_widen_l> (operands[0], tmpreg)); | ||
| 231 | + | ||
| 232 | + DONE; | ||
| 233 | +} | ||
| 234 | +) | ||
| 235 | + | ||
| 236 | +(define_expand "vec_unpack<US>_hi_<mode>" | ||
| 237 | + [(match_operand:<V_double_width> 0 "register_operand" "") | ||
| 238 | + (SE:<V_double_width>(match_operand:VDI 1 "register_operand"))] | ||
| 239 | + "TARGET_NEON" | ||
| 240 | +{ | ||
| 241 | + rtx tmpreg = gen_reg_rtx (<V_widen>mode); | ||
| 242 | + emit_insn (gen_neon_unpack<US>_<mode> (tmpreg, operands[1])); | ||
| 243 | + emit_insn (gen_neon_vget_high<V_widen_l> (operands[0], tmpreg)); | ||
| 244 | + | ||
| 245 | + DONE; | ||
| 246 | +} | ||
| 247 | +) | ||
| 248 | + | ||
| 249 | +(define_insn "neon_vec_<US>mult_<mode>" | ||
| 250 | + [(set (match_operand:<V_widen> 0 "register_operand" "=w") | ||
| 251 | + (mult:<V_widen> (SE:<V_widen> | ||
| 252 | + (match_operand:VDI 1 "register_operand" "w")) | ||
| 253 | + (SE:<V_widen> | ||
| 254 | + (match_operand:VDI 2 "register_operand" "w"))))] | ||
| 255 | + "TARGET_NEON" | ||
| 256 | + "vmull.<US><V_sz_elem> %q0, %1, %2" | ||
| 257 | + [(set_attr "neon_type" "neon_shift_1")] | ||
| 258 | +) | ||
| 259 | + | ||
| 260 | +(define_expand "vec_widen_<US>mult_hi_<mode>" | ||
| 261 | + [(match_operand:<V_double_width> 0 "register_operand" "") | ||
| 262 | + (SE:<V_double_width> (match_operand:VDI 1 "register_operand" "")) | ||
| 263 | + (SE:<V_double_width> (match_operand:VDI 2 "register_operand" ""))] | ||
| 264 | + "TARGET_NEON" | ||
| 265 | + { | ||
| 266 | + rtx tmpreg = gen_reg_rtx (<V_widen>mode); | ||
| 267 | + emit_insn (gen_neon_vec_<US>mult_<mode> (tmpreg, operands[1], operands[2])); | ||
| 268 | + emit_insn (gen_neon_vget_high<V_widen_l> (operands[0], tmpreg)); | ||
| 269 | + | ||
| 270 | + DONE; | ||
| 271 | + | ||
| 272 | + } | ||
| 273 | +) | ||
| 274 | + | ||
| 275 | +(define_expand "vec_widen_<US>mult_lo_<mode>" | ||
| 276 | + [(match_operand:<V_double_width> 0 "register_operand" "") | ||
| 277 | + (SE:<V_double_width> (match_operand:VDI 1 "register_operand" "")) | ||
| 278 | + (SE:<V_double_width> (match_operand:VDI 2 "register_operand" ""))] | ||
| 279 | + "TARGET_NEON" | ||
| 280 | + { | ||
| 281 | + rtx tmpreg = gen_reg_rtx (<V_widen>mode); | ||
| 282 | + emit_insn (gen_neon_vec_<US>mult_<mode> (tmpreg, operands[1], operands[2])); | ||
| 283 | + emit_insn (gen_neon_vget_low<V_widen_l> (operands[0], tmpreg)); | ||
| 284 | + | ||
| 285 | + DONE; | ||
| 286 | + | ||
| 287 | + } | ||
| 288 | +) | ||
| 289 | |||
| 290 | === modified file 'gcc/config/arm/predicates.md' | ||
| 291 | --- old/gcc/config/arm/predicates.md 2010-08-31 10:00:27 +0000 | ||
| 292 | +++ new/gcc/config/arm/predicates.md 2010-09-09 14:11:34 +0000 | ||
| 293 | @@ -573,3 +573,61 @@ | ||
| 294 | (and (match_test "TARGET_32BIT") | ||
| 295 | (match_operand 0 "arm_di_operand")))) | ||
| 296 | |||
| 297 | +;; Predicates for parallel expanders based on mode. | ||
| 298 | +(define_special_predicate "vect_par_constant_high" | ||
| 299 | + (match_code "parallel") | ||
| 300 | +{ | ||
| 301 | + HOST_WIDE_INT count = XVECLEN (op, 0); | ||
| 302 | + int i; | ||
| 303 | + int base = GET_MODE_NUNITS (mode); | ||
| 304 | + | ||
| 305 | + if ((count < 1) | ||
| 306 | + || (count != base/2)) | ||
| 307 | + return false; | ||
| 308 | + | ||
| 309 | + if (!VECTOR_MODE_P (mode)) | ||
| 310 | + return false; | ||
| 311 | + | ||
| 312 | + for (i = 0; i < count; i++) | ||
| 313 | + { | ||
| 314 | + rtx elt = XVECEXP (op, 0, i); | ||
| 315 | + int val; | ||
| 316 | + | ||
| 317 | + if (GET_CODE (elt) != CONST_INT) | ||
| 318 | + return false; | ||
| 319 | + | ||
| 320 | + val = INTVAL (elt); | ||
| 321 | + if (val != (base/2) + i) | ||
| 322 | + return false; | ||
| 323 | + } | ||
| 324 | + return true; | ||
| 325 | +}) | ||
| 326 | + | ||
| 327 | +(define_special_predicate "vect_par_constant_low" | ||
| 328 | + (match_code "parallel") | ||
| 329 | +{ | ||
| 330 | + HOST_WIDE_INT count = XVECLEN (op, 0); | ||
| 331 | + int i; | ||
| 332 | + int base = GET_MODE_NUNITS (mode); | ||
| 333 | + | ||
| 334 | + if ((count < 1) | ||
| 335 | + || (count != base/2)) | ||
| 336 | + return false; | ||
| 337 | + | ||
| 338 | + if (!VECTOR_MODE_P (mode)) | ||
| 339 | + return false; | ||
| 340 | + | ||
| 341 | + for (i = 0; i < count; i++) | ||
| 342 | + { | ||
| 343 | + rtx elt = XVECEXP (op, 0, i); | ||
| 344 | + int val; | ||
| 345 | + | ||
| 346 | + if (GET_CODE (elt) != CONST_INT) | ||
| 347 | + return false; | ||
| 348 | + | ||
| 349 | + val = INTVAL (elt); | ||
| 350 | + if (val != i) | ||
| 351 | + return false; | ||
| 352 | + } | ||
| 353 | + return true; | ||
| 354 | +}) | ||
| 355 | |||
| 356 | === modified file 'gcc/testsuite/lib/target-supports.exp' | ||
| 357 | --- old/gcc/testsuite/lib/target-supports.exp 2010-08-24 13:00:03 +0000 | ||
| 358 | +++ new/gcc/testsuite/lib/target-supports.exp 2010-09-09 14:11:34 +0000 | ||
| 359 | @@ -2519,7 +2519,8 @@ | ||
| 360 | if { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*]) | ||
| 361 | || [istarget i?86-*-*] | ||
| 362 | || [istarget x86_64-*-*] | ||
| 363 | - || [istarget spu-*-*] } { | ||
| 364 | + || [istarget spu-*-*] | ||
| 365 | + || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } { | ||
| 366 | set et_vect_unpack_saved 1 | ||
| 367 | } | ||
| 368 | } | ||
| 369 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99384.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99384.patch deleted file mode 100644 index 89c04a894..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99384.patch +++ /dev/null | |||
| @@ -1,1202 +0,0 @@ | |||
| 1 | 2010-08-18 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 2 | * config/arm/arm-protos.h (arm_expand_sync): New. | ||
| 3 | (arm_output_memory_barrier, arm_output_sync_insn): New. | ||
| 4 | (arm_sync_loop_insns): New. | ||
| 5 | * config/arm/arm.c (FL_ARCH7): New. | ||
| 6 | (FL_FOR_ARCH7): Include FL_ARCH7. | ||
| 7 | (arm_arch7): New. | ||
| 8 | (arm_print_operand): Support %C markup. | ||
| 9 | (arm_legitimize_sync_memory): New. | ||
| 10 | (arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New. | ||
| 11 | (arm_process_output_memory_barrier, arm_output_memory_barrier): New. | ||
| 12 | (arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New. | ||
| 13 | (arm_output_op2, arm_output_op3, arm_output_sync_loop): New. | ||
| 14 | (arm_get_sync_operand, FETCH_SYNC_OPERAND): New. | ||
| 15 | (arm_process_output_sync_insn, arm_output_sync_insn): New. | ||
| 16 | (arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New. | ||
| 17 | * config/arm/arm.h (struct arm_sync_generator): New. | ||
| 18 | (TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New. | ||
| 19 | (TARGET_HAVE_MEMORY_BARRIER): New. | ||
| 20 | (TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New. | ||
| 21 | * config/arm/arm.md: Include sync.md. | ||
| 22 | (UNSPEC_MEMORY_BARRIER): New. | ||
| 23 | (VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New. | ||
| 24 | (VUNSPEC_SYNC_OP):New. | ||
| 25 | (VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New. | ||
| 26 | (sync_result, sync_memory, sync_required_value): New attributes. | ||
| 27 | (sync_new_value, sync_t1, sync_t2): Likewise. | ||
| 28 | (sync_release_barrier, sync_op): Likewise. | ||
| 29 | (length): Add logic to length attribute defintion to call | ||
| 30 | arm_sync_loop_insns when appropriate. | ||
| 31 | * config/arm/sync.md: New file. | ||
| 32 | |||
| 33 | 2010-09-09 Andrew Stubbs <ams@codesourcery.com> | ||
| 34 | |||
| 35 | Backport from mainline: | ||
| 36 | |||
| 37 | 2010-08-25 Tejas Belagod <tejas.belagod@arm.com> | ||
| 38 | * config/arm/iterators.md (VU, SE, V_widen_l): New. | ||
| 39 | (V_unpack, US): New. | ||
| 40 | |||
| 41 | === modified file 'gcc/config/arm/arm-protos.h' | ||
| 42 | --- old/gcc/config/arm/arm-protos.h 2010-08-24 13:15:54 +0000 | ||
| 43 | +++ new/gcc/config/arm/arm-protos.h 2010-09-09 15:03:00 +0000 | ||
| 44 | @@ -148,6 +148,11 @@ | ||
| 45 | extern void arm_set_return_address (rtx, rtx); | ||
| 46 | extern int arm_eliminable_register (rtx); | ||
| 47 | extern const char *arm_output_shift(rtx *, int); | ||
| 48 | +extern void arm_expand_sync (enum machine_mode, struct arm_sync_generator *, | ||
| 49 | + rtx, rtx, rtx, rtx); | ||
| 50 | +extern const char *arm_output_memory_barrier (rtx *); | ||
| 51 | +extern const char *arm_output_sync_insn (rtx, rtx *); | ||
| 52 | +extern unsigned int arm_sync_loop_insns (rtx , rtx *); | ||
| 53 | |||
| 54 | extern bool arm_output_addr_const_extra (FILE *, rtx); | ||
| 55 | |||
| 56 | |||
| 57 | === modified file 'gcc/config/arm/arm.c' | ||
| 58 | --- old/gcc/config/arm/arm.c 2010-09-01 13:29:58 +0000 | ||
| 59 | +++ new/gcc/config/arm/arm.c 2010-09-09 15:03:00 +0000 | ||
| 60 | @@ -605,6 +605,7 @@ | ||
| 61 | #define FL_NEON (1 << 20) /* Neon instructions. */ | ||
| 62 | #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M | ||
| 63 | architecture. */ | ||
| 64 | +#define FL_ARCH7 (1 << 22) /* Architecture 7. */ | ||
| 65 | |||
| 66 | #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ | ||
| 67 | |||
| 68 | @@ -625,7 +626,7 @@ | ||
| 69 | #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K | ||
| 70 | #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) | ||
| 71 | #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) | ||
| 72 | -#define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM) | ||
| 73 | +#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) | ||
| 74 | #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) | ||
| 75 | #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) | ||
| 76 | #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) | ||
| 77 | @@ -663,6 +664,9 @@ | ||
| 78 | /* Nonzero if this chip supports the ARM 6K extensions. */ | ||
| 79 | int arm_arch6k = 0; | ||
| 80 | |||
| 81 | +/* Nonzero if this chip supports the ARM 7 extensions. */ | ||
| 82 | +int arm_arch7 = 0; | ||
| 83 | + | ||
| 84 | /* Nonzero if instructions not present in the 'M' profile can be used. */ | ||
| 85 | int arm_arch_notm = 0; | ||
| 86 | |||
| 87 | @@ -1634,6 +1638,7 @@ | ||
| 88 | arm_arch6 = (insn_flags & FL_ARCH6) != 0; | ||
| 89 | arm_arch6k = (insn_flags & FL_ARCH6K) != 0; | ||
| 90 | arm_arch_notm = (insn_flags & FL_NOTM) != 0; | ||
| 91 | + arm_arch7 = (insn_flags & FL_ARCH7) != 0; | ||
| 92 | arm_arch7em = (insn_flags & FL_ARCH7EM) != 0; | ||
| 93 | arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; | ||
| 94 | arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; | ||
| 95 | @@ -16561,6 +16566,17 @@ | ||
| 96 | } | ||
| 97 | return; | ||
| 98 | |||
| 99 | + case 'C': | ||
| 100 | + { | ||
| 101 | + rtx addr; | ||
| 102 | + | ||
| 103 | + gcc_assert (GET_CODE (x) == MEM); | ||
| 104 | + addr = XEXP (x, 0); | ||
| 105 | + gcc_assert (GET_CODE (addr) == REG); | ||
| 106 | + asm_fprintf (stream, "[%r]", REGNO (addr)); | ||
| 107 | + } | ||
| 108 | + return; | ||
| 109 | + | ||
| 110 | /* Translate an S register number into a D register number and element index. */ | ||
| 111 | case 'y': | ||
| 112 | { | ||
| 113 | @@ -22763,4 +22779,372 @@ | ||
| 114 | is_packed); | ||
| 115 | } | ||
| 116 | |||
| 117 | +/* Legitimize a memory reference for sync primitive implemented using | ||
| 118 | + ldrex / strex. We currently force the form of the reference to be | ||
| 119 | + indirect without offset. We do not yet support the indirect offset | ||
| 120 | + addressing supported by some ARM targets for these | ||
| 121 | + instructions. */ | ||
| 122 | +static rtx | ||
| 123 | +arm_legitimize_sync_memory (rtx memory) | ||
| 124 | +{ | ||
| 125 | + rtx addr = force_reg (Pmode, XEXP (memory, 0)); | ||
| 126 | + rtx legitimate_memory = gen_rtx_MEM (GET_MODE (memory), addr); | ||
| 127 | + | ||
| 128 | + set_mem_alias_set (legitimate_memory, ALIAS_SET_MEMORY_BARRIER); | ||
| 129 | + MEM_VOLATILE_P (legitimate_memory) = MEM_VOLATILE_P (memory); | ||
| 130 | + return legitimate_memory; | ||
| 131 | +} | ||
| 132 | + | ||
| 133 | +/* An instruction emitter. */ | ||
| 134 | +typedef void (* emit_f) (int label, const char *, rtx *); | ||
| 135 | + | ||
| 136 | +/* An instruction emitter that emits via the conventional | ||
| 137 | + output_asm_insn. */ | ||
| 138 | +static void | ||
| 139 | +arm_emit (int label ATTRIBUTE_UNUSED, const char *pattern, rtx *operands) | ||
| 140 | +{ | ||
| 141 | + output_asm_insn (pattern, operands); | ||
| 142 | +} | ||
| 143 | + | ||
| 144 | +/* Count the number of emitted synchronization instructions. */ | ||
| 145 | +static unsigned arm_insn_count; | ||
| 146 | + | ||
| 147 | +/* An emitter that counts emitted instructions but does not actually | ||
| 148 | + emit instruction into the the instruction stream. */ | ||
| 149 | +static void | ||
| 150 | +arm_count (int label, | ||
| 151 | + const char *pattern ATTRIBUTE_UNUSED, | ||
| 152 | + rtx *operands ATTRIBUTE_UNUSED) | ||
| 153 | +{ | ||
| 154 | + if (! label) | ||
| 155 | + ++ arm_insn_count; | ||
| 156 | +} | ||
| 157 | + | ||
| 158 | +/* Construct a pattern using conventional output formatting and feed | ||
| 159 | + it to output_asm_insn. Provides a mechanism to construct the | ||
| 160 | + output pattern on the fly. Note the hard limit on the pattern | ||
| 161 | + buffer size. */ | ||
| 162 | +static void | ||
| 163 | +arm_output_asm_insn (emit_f emit, int label, rtx *operands, | ||
| 164 | + const char *pattern, ...) | ||
| 165 | +{ | ||
| 166 | + va_list ap; | ||
| 167 | + char buffer[256]; | ||
| 168 | + | ||
| 169 | + va_start (ap, pattern); | ||
| 170 | + vsprintf (buffer, pattern, ap); | ||
| 171 | + va_end (ap); | ||
| 172 | + emit (label, buffer, operands); | ||
| 173 | +} | ||
| 174 | + | ||
| 175 | +/* Emit the memory barrier instruction, if any, provided by this | ||
| 176 | + target to a specified emitter. */ | ||
| 177 | +static void | ||
| 178 | +arm_process_output_memory_barrier (emit_f emit, rtx *operands) | ||
| 179 | +{ | ||
| 180 | + if (TARGET_HAVE_DMB) | ||
| 181 | + { | ||
| 182 | + /* Note we issue a system level barrier. We should consider | ||
| 183 | + issuing a inner shareabilty zone barrier here instead, ie. | ||
| 184 | + "DMB ISH". */ | ||
| 185 | + emit (0, "dmb\tsy", operands); | ||
| 186 | + return; | ||
| 187 | + } | ||
| 188 | + | ||
| 189 | + if (TARGET_HAVE_DMB_MCR) | ||
| 190 | + { | ||
| 191 | + emit (0, "mcr\tp15, 0, r0, c7, c10, 5", operands); | ||
| 192 | + return; | ||
| 193 | + } | ||
| 194 | + | ||
| 195 | + gcc_unreachable (); | ||
| 196 | +} | ||
| 197 | + | ||
| 198 | +/* Emit the memory barrier instruction, if any, provided by this | ||
| 199 | + target. */ | ||
| 200 | +const char * | ||
| 201 | +arm_output_memory_barrier (rtx *operands) | ||
| 202 | +{ | ||
| 203 | + arm_process_output_memory_barrier (arm_emit, operands); | ||
| 204 | + return ""; | ||
| 205 | +} | ||
| 206 | + | ||
| 207 | +/* Helper to figure out the instruction suffix required on ldrex/strex | ||
| 208 | + for operations on an object of the specified mode. */ | ||
| 209 | +static const char * | ||
| 210 | +arm_ldrex_suffix (enum machine_mode mode) | ||
| 211 | +{ | ||
| 212 | + switch (mode) | ||
| 213 | + { | ||
| 214 | + case QImode: return "b"; | ||
| 215 | + case HImode: return "h"; | ||
| 216 | + case SImode: return ""; | ||
| 217 | + case DImode: return "d"; | ||
| 218 | + default: | ||
| 219 | + gcc_unreachable (); | ||
| 220 | + } | ||
| 221 | + return ""; | ||
| 222 | +} | ||
| 223 | + | ||
| 224 | +/* Emit an ldrex{b,h,d, } instruction appropriate for the specified | ||
| 225 | + mode. */ | ||
| 226 | +static void | ||
| 227 | +arm_output_ldrex (emit_f emit, | ||
| 228 | + enum machine_mode mode, | ||
| 229 | + rtx target, | ||
| 230 | + rtx memory) | ||
| 231 | +{ | ||
| 232 | + const char *suffix = arm_ldrex_suffix (mode); | ||
| 233 | + rtx operands[2]; | ||
| 234 | + | ||
| 235 | + operands[0] = target; | ||
| 236 | + operands[1] = memory; | ||
| 237 | + arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix); | ||
| 238 | +} | ||
| 239 | + | ||
| 240 | +/* Emit a strex{b,h,d, } instruction appropriate for the specified | ||
| 241 | + mode. */ | ||
| 242 | +static void | ||
| 243 | +arm_output_strex (emit_f emit, | ||
| 244 | + enum machine_mode mode, | ||
| 245 | + const char *cc, | ||
| 246 | + rtx result, | ||
| 247 | + rtx value, | ||
| 248 | + rtx memory) | ||
| 249 | +{ | ||
| 250 | + const char *suffix = arm_ldrex_suffix (mode); | ||
| 251 | + rtx operands[3]; | ||
| 252 | + | ||
| 253 | + operands[0] = result; | ||
| 254 | + operands[1] = value; | ||
| 255 | + operands[2] = memory; | ||
| 256 | + arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2", suffix, | ||
| 257 | + cc); | ||
| 258 | +} | ||
| 259 | + | ||
| 260 | +/* Helper to emit a two operand instruction. */ | ||
| 261 | +static void | ||
| 262 | +arm_output_op2 (emit_f emit, const char *mnemonic, rtx d, rtx s) | ||
| 263 | +{ | ||
| 264 | + rtx operands[2]; | ||
| 265 | + | ||
| 266 | + operands[0] = d; | ||
| 267 | + operands[1] = s; | ||
| 268 | + arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1", mnemonic); | ||
| 269 | +} | ||
| 270 | + | ||
| 271 | +/* Helper to emit a three operand instruction. */ | ||
| 272 | +static void | ||
| 273 | +arm_output_op3 (emit_f emit, const char *mnemonic, rtx d, rtx a, rtx b) | ||
| 274 | +{ | ||
| 275 | + rtx operands[3]; | ||
| 276 | + | ||
| 277 | + operands[0] = d; | ||
| 278 | + operands[1] = a; | ||
| 279 | + operands[2] = b; | ||
| 280 | + arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1, %%2", mnemonic); | ||
| 281 | +} | ||
| 282 | + | ||
| 283 | +/* Emit a load store exclusive synchronization loop. | ||
| 284 | + | ||
| 285 | + do | ||
| 286 | + old_value = [mem] | ||
| 287 | + if old_value != required_value | ||
| 288 | + break; | ||
| 289 | + t1 = sync_op (old_value, new_value) | ||
| 290 | + [mem] = t1, t2 = [0|1] | ||
| 291 | + while ! t2 | ||
| 292 | + | ||
| 293 | + Note: | ||
| 294 | + t1 == t2 is not permitted | ||
| 295 | + t1 == old_value is permitted | ||
| 296 | + | ||
| 297 | + required_value: | ||
| 298 | + | ||
| 299 | + RTX register or const_int representing the required old_value for | ||
| 300 | + the modify to continue, if NULL no comparsion is performed. */ | ||
| 301 | +static void | ||
| 302 | +arm_output_sync_loop (emit_f emit, | ||
| 303 | + enum machine_mode mode, | ||
| 304 | + rtx old_value, | ||
| 305 | + rtx memory, | ||
| 306 | + rtx required_value, | ||
| 307 | + rtx new_value, | ||
| 308 | + rtx t1, | ||
| 309 | + rtx t2, | ||
| 310 | + enum attr_sync_op sync_op, | ||
| 311 | + int early_barrier_required) | ||
| 312 | +{ | ||
| 313 | + rtx operands[1]; | ||
| 314 | + | ||
| 315 | + gcc_assert (t1 != t2); | ||
| 316 | + | ||
| 317 | + if (early_barrier_required) | ||
| 318 | + arm_process_output_memory_barrier (emit, NULL); | ||
| 319 | + | ||
| 320 | + arm_output_asm_insn (emit, 1, operands, "%sLSYT%%=:", LOCAL_LABEL_PREFIX); | ||
| 321 | + | ||
| 322 | + arm_output_ldrex (emit, mode, old_value, memory); | ||
| 323 | + | ||
| 324 | + if (required_value) | ||
| 325 | + { | ||
| 326 | + rtx operands[2]; | ||
| 327 | + | ||
| 328 | + operands[0] = old_value; | ||
| 329 | + operands[1] = required_value; | ||
| 330 | + arm_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1"); | ||
| 331 | + arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX); | ||
| 332 | + } | ||
| 333 | + | ||
| 334 | + switch (sync_op) | ||
| 335 | + { | ||
| 336 | + case SYNC_OP_ADD: | ||
| 337 | + arm_output_op3 (emit, "add", t1, old_value, new_value); | ||
| 338 | + break; | ||
| 339 | + | ||
| 340 | + case SYNC_OP_SUB: | ||
| 341 | + arm_output_op3 (emit, "sub", t1, old_value, new_value); | ||
| 342 | + break; | ||
| 343 | + | ||
| 344 | + case SYNC_OP_IOR: | ||
| 345 | + arm_output_op3 (emit, "orr", t1, old_value, new_value); | ||
| 346 | + break; | ||
| 347 | + | ||
| 348 | + case SYNC_OP_XOR: | ||
| 349 | + arm_output_op3 (emit, "eor", t1, old_value, new_value); | ||
| 350 | + break; | ||
| 351 | + | ||
| 352 | + case SYNC_OP_AND: | ||
| 353 | + arm_output_op3 (emit,"and", t1, old_value, new_value); | ||
| 354 | + break; | ||
| 355 | + | ||
| 356 | + case SYNC_OP_NAND: | ||
| 357 | + arm_output_op3 (emit, "and", t1, old_value, new_value); | ||
| 358 | + arm_output_op2 (emit, "mvn", t1, t1); | ||
| 359 | + break; | ||
| 360 | + | ||
| 361 | + case SYNC_OP_NONE: | ||
| 362 | + t1 = new_value; | ||
| 363 | + break; | ||
| 364 | + } | ||
| 365 | + | ||
| 366 | + arm_output_strex (emit, mode, "", t2, t1, memory); | ||
| 367 | + operands[0] = t2; | ||
| 368 | + arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0"); | ||
| 369 | + arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", LOCAL_LABEL_PREFIX); | ||
| 370 | + | ||
| 371 | + arm_process_output_memory_barrier (emit, NULL); | ||
| 372 | + arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX); | ||
| 373 | +} | ||
| 374 | + | ||
| 375 | +static rtx | ||
| 376 | +arm_get_sync_operand (rtx *operands, int index, rtx default_value) | ||
| 377 | +{ | ||
| 378 | + if (index > 0) | ||
| 379 | + default_value = operands[index - 1]; | ||
| 380 | + | ||
| 381 | + return default_value; | ||
| 382 | +} | ||
| 383 | + | ||
| 384 | +#define FETCH_SYNC_OPERAND(NAME, DEFAULT) \ | ||
| 385 | + arm_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), DEFAULT); | ||
| 386 | + | ||
| 387 | +/* Extract the operands for a synchroniztion instruction from the | ||
| 388 | + instructions attributes and emit the instruction. */ | ||
| 389 | +static void | ||
| 390 | +arm_process_output_sync_insn (emit_f emit, rtx insn, rtx *operands) | ||
| 391 | +{ | ||
| 392 | + rtx result, memory, required_value, new_value, t1, t2; | ||
| 393 | + int early_barrier; | ||
| 394 | + enum machine_mode mode; | ||
| 395 | + enum attr_sync_op sync_op; | ||
| 396 | + | ||
| 397 | + result = FETCH_SYNC_OPERAND(result, 0); | ||
| 398 | + memory = FETCH_SYNC_OPERAND(memory, 0); | ||
| 399 | + required_value = FETCH_SYNC_OPERAND(required_value, 0); | ||
| 400 | + new_value = FETCH_SYNC_OPERAND(new_value, 0); | ||
| 401 | + t1 = FETCH_SYNC_OPERAND(t1, 0); | ||
| 402 | + t2 = FETCH_SYNC_OPERAND(t2, 0); | ||
| 403 | + early_barrier = | ||
| 404 | + get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES; | ||
| 405 | + sync_op = get_attr_sync_op (insn); | ||
| 406 | + mode = GET_MODE (memory); | ||
| 407 | + | ||
| 408 | + arm_output_sync_loop (emit, mode, result, memory, required_value, | ||
| 409 | + new_value, t1, t2, sync_op, early_barrier); | ||
| 410 | +} | ||
| 411 | + | ||
| 412 | +/* Emit a synchronization instruction loop. */ | ||
| 413 | +const char * | ||
| 414 | +arm_output_sync_insn (rtx insn, rtx *operands) | ||
| 415 | +{ | ||
| 416 | + arm_process_output_sync_insn (arm_emit, insn, operands); | ||
| 417 | + return ""; | ||
| 418 | +} | ||
| 419 | + | ||
| 420 | +/* Count the number of machine instruction that will be emitted for a | ||
| 421 | + synchronization instruction. Note that the emitter used does not | ||
| 422 | + emit instructions, it just counts instructions being carefull not | ||
| 423 | + to count labels. */ | ||
| 424 | +unsigned int | ||
| 425 | +arm_sync_loop_insns (rtx insn, rtx *operands) | ||
| 426 | +{ | ||
| 427 | + arm_insn_count = 0; | ||
| 428 | + arm_process_output_sync_insn (arm_count, insn, operands); | ||
| 429 | + return arm_insn_count; | ||
| 430 | +} | ||
| 431 | + | ||
| 432 | +/* Helper to call a target sync instruction generator, dealing with | ||
| 433 | + the variation in operands required by the different generators. */ | ||
| 434 | +static rtx | ||
| 435 | +arm_call_generator (struct arm_sync_generator *generator, rtx old_value, | ||
| 436 | + rtx memory, rtx required_value, rtx new_value) | ||
| 437 | +{ | ||
| 438 | + switch (generator->op) | ||
| 439 | + { | ||
| 440 | + case arm_sync_generator_omn: | ||
| 441 | + gcc_assert (! required_value); | ||
| 442 | + return generator->u.omn (old_value, memory, new_value); | ||
| 443 | + | ||
| 444 | + case arm_sync_generator_omrn: | ||
| 445 | + gcc_assert (required_value); | ||
| 446 | + return generator->u.omrn (old_value, memory, required_value, new_value); | ||
| 447 | + } | ||
| 448 | + | ||
| 449 | + return NULL; | ||
| 450 | +} | ||
| 451 | + | ||
| 452 | +/* Expand a synchronization loop. The synchronization loop is expanded | ||
| 453 | + as an opaque block of instructions in order to ensure that we do | ||
| 454 | + not subsequently get extraneous memory accesses inserted within the | ||
| 455 | + critical region. The exclusive access property of ldrex/strex is | ||
| 456 | + only guaranteed in there are no intervening memory accesses. */ | ||
| 457 | +void | ||
| 458 | +arm_expand_sync (enum machine_mode mode, | ||
| 459 | + struct arm_sync_generator *generator, | ||
| 460 | + rtx target, rtx memory, rtx required_value, rtx new_value) | ||
| 461 | +{ | ||
| 462 | + if (target == NULL) | ||
| 463 | + target = gen_reg_rtx (mode); | ||
| 464 | + | ||
| 465 | + memory = arm_legitimize_sync_memory (memory); | ||
| 466 | + if (mode != SImode) | ||
| 467 | + { | ||
| 468 | + rtx load_temp = gen_reg_rtx (SImode); | ||
| 469 | + | ||
| 470 | + if (required_value) | ||
| 471 | + required_value = convert_modes (SImode, mode, required_value, true); | ||
| 472 | + | ||
| 473 | + new_value = convert_modes (SImode, mode, new_value, true); | ||
| 474 | + emit_insn (arm_call_generator (generator, load_temp, memory, | ||
| 475 | + required_value, new_value)); | ||
| 476 | + emit_move_insn (target, gen_lowpart (mode, load_temp)); | ||
| 477 | + } | ||
| 478 | + else | ||
| 479 | + { | ||
| 480 | + emit_insn (arm_call_generator (generator, target, memory, required_value, | ||
| 481 | + new_value)); | ||
| 482 | + } | ||
| 483 | +} | ||
| 484 | + | ||
| 485 | #include "gt-arm.h" | ||
| 486 | |||
| 487 | === modified file 'gcc/config/arm/arm.h' | ||
| 488 | --- old/gcc/config/arm/arm.h 2010-09-01 13:29:58 +0000 | ||
| 489 | +++ new/gcc/config/arm/arm.h 2010-09-09 15:03:00 +0000 | ||
| 490 | @@ -128,6 +128,24 @@ | ||
| 491 | /* The processor for which instructions should be scheduled. */ | ||
| 492 | extern enum processor_type arm_tune; | ||
| 493 | |||
| 494 | +enum arm_sync_generator_tag | ||
| 495 | + { | ||
| 496 | + arm_sync_generator_omn, | ||
| 497 | + arm_sync_generator_omrn | ||
| 498 | + }; | ||
| 499 | + | ||
| 500 | +/* Wrapper to pass around a polymorphic pointer to a sync instruction | ||
| 501 | + generator and. */ | ||
| 502 | +struct arm_sync_generator | ||
| 503 | +{ | ||
| 504 | + enum arm_sync_generator_tag op; | ||
| 505 | + union | ||
| 506 | + { | ||
| 507 | + rtx (* omn) (rtx, rtx, rtx); | ||
| 508 | + rtx (* omrn) (rtx, rtx, rtx, rtx); | ||
| 509 | + } u; | ||
| 510 | +}; | ||
| 511 | + | ||
| 512 | typedef enum arm_cond_code | ||
| 513 | { | ||
| 514 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | ||
| 515 | @@ -272,6 +290,20 @@ | ||
| 516 | for Thumb-2. */ | ||
| 517 | #define TARGET_UNIFIED_ASM TARGET_THUMB2 | ||
| 518 | |||
| 519 | +/* Nonzero if this chip provides the DMB instruction. */ | ||
| 520 | +#define TARGET_HAVE_DMB (arm_arch7) | ||
| 521 | + | ||
| 522 | +/* Nonzero if this chip implements a memory barrier via CP15. */ | ||
| 523 | +#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB) | ||
| 524 | + | ||
| 525 | +/* Nonzero if this chip implements a memory barrier instruction. */ | ||
| 526 | +#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) | ||
| 527 | + | ||
| 528 | +/* Nonzero if this chip supports ldrex and strex */ | ||
| 529 | +#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) | ||
| 530 | + | ||
| 531 | +/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */ | ||
| 532 | +#define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7) | ||
| 533 | |||
| 534 | /* True iff the full BPABI is being used. If TARGET_BPABI is true, | ||
| 535 | then TARGET_AAPCS_BASED must be true -- but the converse does not | ||
| 536 | @@ -405,6 +437,12 @@ | ||
| 537 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ | ||
| 538 | extern int arm_arch6; | ||
| 539 | |||
| 540 | +/* Nonzero if this chip supports the ARM Architecture 6k extensions. */ | ||
| 541 | +extern int arm_arch6k; | ||
| 542 | + | ||
| 543 | +/* Nonzero if this chip supports the ARM Architecture 7 extensions. */ | ||
| 544 | +extern int arm_arch7; | ||
| 545 | + | ||
| 546 | /* Nonzero if instructions not present in the 'M' profile can be used. */ | ||
| 547 | extern int arm_arch_notm; | ||
| 548 | |||
| 549 | |||
| 550 | === modified file 'gcc/config/arm/arm.md' | ||
| 551 | --- old/gcc/config/arm/arm.md 2010-09-09 14:11:34 +0000 | ||
| 552 | +++ new/gcc/config/arm/arm.md 2010-09-09 15:03:00 +0000 | ||
| 553 | @@ -103,6 +103,7 @@ | ||
| 554 | (UNSPEC_RBIT 26) ; rbit operation. | ||
| 555 | (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from | ||
| 556 | ; another symbolic address. | ||
| 557 | + (UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier. | ||
| 558 | ] | ||
| 559 | ) | ||
| 560 | |||
| 561 | @@ -139,6 +140,11 @@ | ||
| 562 | (VUNSPEC_ALIGN32 16) ; Used to force 32-byte alignment. | ||
| 563 | (VUNSPEC_EH_RETURN 20); Use to override the return address for exception | ||
| 564 | ; handling. | ||
| 565 | + (VUNSPEC_SYNC_COMPARE_AND_SWAP 21) ; Represent an atomic compare swap. | ||
| 566 | + (VUNSPEC_SYNC_LOCK 22) ; Represent a sync_lock_test_and_set. | ||
| 567 | + (VUNSPEC_SYNC_OP 23) ; Represent a sync_<op> | ||
| 568 | + (VUNSPEC_SYNC_NEW_OP 24) ; Represent a sync_new_<op> | ||
| 569 | + (VUNSPEC_SYNC_OLD_OP 25) ; Represent a sync_old_<op> | ||
| 570 | ] | ||
| 571 | ) | ||
| 572 | |||
| 573 | @@ -163,8 +169,21 @@ | ||
| 574 | (define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp" | ||
| 575 | (const (symbol_ref "arm_fpu_attr"))) | ||
| 576 | |||
| 577 | +(define_attr "sync_result" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 578 | +(define_attr "sync_memory" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 579 | +(define_attr "sync_required_value" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 580 | +(define_attr "sync_new_value" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 581 | +(define_attr "sync_t1" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 582 | +(define_attr "sync_t2" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 583 | +(define_attr "sync_release_barrier" "yes,no" (const_string "yes")) | ||
| 584 | +(define_attr "sync_op" "none,add,sub,ior,xor,and,nand" | ||
| 585 | + (const_string "none")) | ||
| 586 | + | ||
| 587 | ; LENGTH of an instruction (in bytes) | ||
| 588 | -(define_attr "length" "" (const_int 4)) | ||
| 589 | +(define_attr "length" "" | ||
| 590 | + (cond [(not (eq_attr "sync_memory" "none")) | ||
| 591 | + (symbol_ref "arm_sync_loop_insns (insn, operands) * 4") | ||
| 592 | + ] (const_int 4))) | ||
| 593 | |||
| 594 | ; POOL_RANGE is how far away from a constant pool entry that this insn | ||
| 595 | ; can be placed. If the distance is zero, then this insn will never | ||
| 596 | @@ -11530,4 +11549,5 @@ | ||
| 597 | (include "thumb2.md") | ||
| 598 | ;; Neon patterns | ||
| 599 | (include "neon.md") | ||
| 600 | - | ||
| 601 | +;; Synchronization Primitives | ||
| 602 | +(include "sync.md") | ||
| 603 | |||
| 604 | === added file 'gcc/config/arm/sync.md' | ||
| 605 | --- old/gcc/config/arm/sync.md 1970-01-01 00:00:00 +0000 | ||
| 606 | +++ new/gcc/config/arm/sync.md 2010-09-09 15:03:00 +0000 | ||
| 607 | @@ -0,0 +1,594 @@ | ||
| 608 | +;; Machine description for ARM processor synchronization primitives. | ||
| 609 | +;; Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 610 | +;; Written by Marcus Shawcroft (marcus.shawcroft@arm.com) | ||
| 611 | +;; | ||
| 612 | +;; This file is part of GCC. | ||
| 613 | +;; | ||
| 614 | +;; GCC is free software; you can redistribute it and/or modify it | ||
| 615 | +;; under the terms of the GNU General Public License as published by | ||
| 616 | +;; the Free Software Foundation; either version 3, or (at your option) | ||
| 617 | +;; any later version. | ||
| 618 | +;; | ||
| 619 | +;; GCC is distributed in the hope that it will be useful, but | ||
| 620 | +;; WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 621 | +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 622 | +;; General Public License for more details. | ||
| 623 | +;; | ||
| 624 | +;; You should have received a copy of the GNU General Public License | ||
| 625 | +;; along with GCC; see the file COPYING3. If not see | ||
| 626 | +;; <http://www.gnu.org/licenses/>. */ | ||
| 627 | + | ||
| 628 | +;; ARMV6 introduced ldrex and strex instruction. These instruction | ||
| 629 | +;; access SI width data. In order to implement synchronization | ||
| 630 | +;; primitives for the narrower QI and HI modes we insert appropriate | ||
| 631 | +;; AND/OR sequences into the synchronization loop to mask out the | ||
| 632 | +;; relevant component of an SI access. | ||
| 633 | + | ||
| 634 | +(define_expand "memory_barrier" | ||
| 635 | + [(set (match_dup 0) | ||
| 636 | + (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))] | ||
| 637 | + "TARGET_HAVE_MEMORY_BARRIER" | ||
| 638 | +{ | ||
| 639 | + operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | ||
| 640 | + MEM_VOLATILE_P (operands[0]) = 1; | ||
| 641 | +}) | ||
| 642 | + | ||
| 643 | +(define_expand "sync_compare_and_swapsi" | ||
| 644 | + [(set (match_operand:SI 0 "s_register_operand") | ||
| 645 | + (unspec_volatile:SI [(match_operand:SI 1 "memory_operand") | ||
| 646 | + (match_operand:SI 2 "s_register_operand") | ||
| 647 | + (match_operand:SI 3 "s_register_operand")] | ||
| 648 | + VUNSPEC_SYNC_COMPARE_AND_SWAP))] | ||
| 649 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 650 | + { | ||
| 651 | + struct arm_sync_generator generator; | ||
| 652 | + generator.op = arm_sync_generator_omrn; | ||
| 653 | + generator.u.omrn = gen_arm_sync_compare_and_swapsi; | ||
| 654 | + arm_expand_sync (SImode, &generator, operands[0], operands[1], operands[2], | ||
| 655 | + operands[3]); | ||
| 656 | + DONE; | ||
| 657 | + }) | ||
| 658 | + | ||
| 659 | +(define_mode_iterator NARROW [QI HI]) | ||
| 660 | + | ||
| 661 | +(define_expand "sync_compare_and_swap<mode>" | ||
| 662 | + [(set (match_operand:NARROW 0 "s_register_operand") | ||
| 663 | + (unspec_volatile:NARROW [(match_operand:NARROW 1 "memory_operand") | ||
| 664 | + (match_operand:NARROW 2 "s_register_operand") | ||
| 665 | + (match_operand:NARROW 3 "s_register_operand")] | ||
| 666 | + VUNSPEC_SYNC_COMPARE_AND_SWAP))] | ||
| 667 | + "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 668 | + { | ||
| 669 | + struct arm_sync_generator generator; | ||
| 670 | + generator.op = arm_sync_generator_omrn; | ||
| 671 | + generator.u.omrn = gen_arm_sync_compare_and_swap<mode>; | ||
| 672 | + arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1], | ||
| 673 | + operands[2], operands[3]); | ||
| 674 | + DONE; | ||
| 675 | + }) | ||
| 676 | + | ||
| 677 | +(define_expand "sync_lock_test_and_setsi" | ||
| 678 | + [(match_operand:SI 0 "s_register_operand") | ||
| 679 | + (match_operand:SI 1 "memory_operand") | ||
| 680 | + (match_operand:SI 2 "s_register_operand")] | ||
| 681 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 682 | + { | ||
| 683 | + struct arm_sync_generator generator; | ||
| 684 | + generator.op = arm_sync_generator_omn; | ||
| 685 | + generator.u.omn = gen_arm_sync_lock_test_and_setsi; | ||
| 686 | + arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, | ||
| 687 | + operands[2]); | ||
| 688 | + DONE; | ||
| 689 | + }) | ||
| 690 | + | ||
| 691 | +(define_expand "sync_lock_test_and_set<mode>" | ||
| 692 | + [(match_operand:NARROW 0 "s_register_operand") | ||
| 693 | + (match_operand:NARROW 1 "memory_operand") | ||
| 694 | + (match_operand:NARROW 2 "s_register_operand")] | ||
| 695 | + "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 696 | + { | ||
| 697 | + struct arm_sync_generator generator; | ||
| 698 | + generator.op = arm_sync_generator_omn; | ||
| 699 | + generator.u.omn = gen_arm_sync_lock_test_and_set<mode>; | ||
| 700 | + arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1], NULL, | ||
| 701 | + operands[2]); | ||
| 702 | + DONE; | ||
| 703 | + }) | ||
| 704 | + | ||
| 705 | +(define_code_iterator syncop [plus minus ior xor and]) | ||
| 706 | + | ||
| 707 | +(define_code_attr sync_optab [(ior "ior") | ||
| 708 | + (xor "xor") | ||
| 709 | + (and "and") | ||
| 710 | + (plus "add") | ||
| 711 | + (minus "sub")]) | ||
| 712 | + | ||
| 713 | +(define_expand "sync_<sync_optab>si" | ||
| 714 | + [(match_operand:SI 0 "memory_operand") | ||
| 715 | + (match_operand:SI 1 "s_register_operand") | ||
| 716 | + (syncop:SI (match_dup 0) (match_dup 1))] | ||
| 717 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 718 | + { | ||
| 719 | + struct arm_sync_generator generator; | ||
| 720 | + generator.op = arm_sync_generator_omn; | ||
| 721 | + generator.u.omn = gen_arm_sync_new_<sync_optab>si; | ||
| 722 | + arm_expand_sync (SImode, &generator, NULL, operands[0], NULL, operands[1]); | ||
| 723 | + DONE; | ||
| 724 | + }) | ||
| 725 | + | ||
| 726 | +(define_expand "sync_nandsi" | ||
| 727 | + [(match_operand:SI 0 "memory_operand") | ||
| 728 | + (match_operand:SI 1 "s_register_operand") | ||
| 729 | + (not:SI (and:SI (match_dup 0) (match_dup 1)))] | ||
| 730 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 731 | + { | ||
| 732 | + struct arm_sync_generator generator; | ||
| 733 | + generator.op = arm_sync_generator_omn; | ||
| 734 | + generator.u.omn = gen_arm_sync_new_nandsi; | ||
| 735 | + arm_expand_sync (SImode, &generator, NULL, operands[0], NULL, operands[1]); | ||
| 736 | + DONE; | ||
| 737 | + }) | ||
| 738 | + | ||
| 739 | +(define_expand "sync_<sync_optab><mode>" | ||
| 740 | + [(match_operand:NARROW 0 "memory_operand") | ||
| 741 | + (match_operand:NARROW 1 "s_register_operand") | ||
| 742 | + (syncop:NARROW (match_dup 0) (match_dup 1))] | ||
| 743 | + "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 744 | + { | ||
| 745 | + struct arm_sync_generator generator; | ||
| 746 | + generator.op = arm_sync_generator_omn; | ||
| 747 | + generator.u.omn = gen_arm_sync_new_<sync_optab><mode>; | ||
| 748 | + arm_expand_sync (<MODE>mode, &generator, NULL, operands[0], NULL, | ||
| 749 | + operands[1]); | ||
| 750 | + DONE; | ||
| 751 | + }) | ||
| 752 | + | ||
| 753 | +(define_expand "sync_nand<mode>" | ||
| 754 | + [(match_operand:NARROW 0 "memory_operand") | ||
| 755 | + (match_operand:NARROW 1 "s_register_operand") | ||
| 756 | + (not:NARROW (and:NARROW (match_dup 0) (match_dup 1)))] | ||
| 757 | + "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 758 | + { | ||
| 759 | + struct arm_sync_generator generator; | ||
| 760 | + generator.op = arm_sync_generator_omn; | ||
| 761 | + generator.u.omn = gen_arm_sync_new_nand<mode>; | ||
| 762 | + arm_expand_sync (<MODE>mode, &generator, NULL, operands[0], NULL, | ||
| 763 | + operands[1]); | ||
| 764 | + DONE; | ||
| 765 | + }) | ||
| 766 | + | ||
| 767 | +(define_expand "sync_new_<sync_optab>si" | ||
| 768 | + [(match_operand:SI 0 "s_register_operand") | ||
| 769 | + (match_operand:SI 1 "memory_operand") | ||
| 770 | + (match_operand:SI 2 "s_register_operand") | ||
| 771 | + (syncop:SI (match_dup 1) (match_dup 2))] | ||
| 772 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 773 | + { | ||
| 774 | + struct arm_sync_generator generator; | ||
| 775 | + generator.op = arm_sync_generator_omn; | ||
| 776 | + generator.u.omn = gen_arm_sync_new_<sync_optab>si; | ||
| 777 | + arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, | ||
| 778 | + operands[2]); | ||
| 779 | + DONE; | ||
| 780 | + }) | ||
| 781 | + | ||
| 782 | +(define_expand "sync_new_nandsi" | ||
| 783 | + [(match_operand:SI 0 "s_register_operand") | ||
| 784 | + (match_operand:SI 1 "memory_operand") | ||
| 785 | + (match_operand:SI 2 "s_register_operand") | ||
| 786 | + (not:SI (and:SI (match_dup 1) (match_dup 2)))] | ||
| 787 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 788 | + { | ||
| 789 | + struct arm_sync_generator generator; | ||
| 790 | + generator.op = arm_sync_generator_omn; | ||
| 791 | + generator.u.omn = gen_arm_sync_new_nandsi; | ||
| 792 | + arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, | ||
| 793 | + operands[2]); | ||
| 794 | + DONE; | ||
| 795 | + }) | ||
| 796 | + | ||
| 797 | +(define_expand "sync_new_<sync_optab><mode>" | ||
| 798 | + [(match_operand:NARROW 0 "s_register_operand") | ||
| 799 | + (match_operand:NARROW 1 "memory_operand") | ||
| 800 | + (match_operand:NARROW 2 "s_register_operand") | ||
| 801 | + (syncop:NARROW (match_dup 1) (match_dup 2))] | ||
| 802 | + "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 803 | + { | ||
| 804 | + struct arm_sync_generator generator; | ||
| 805 | + generator.op = arm_sync_generator_omn; | ||
| 806 | + generator.u.omn = gen_arm_sync_new_<sync_optab><mode>; | ||
| 807 | + arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1], | ||
| 808 | + NULL, operands[2]); | ||
| 809 | + DONE; | ||
| 810 | + }) | ||
| 811 | + | ||
| 812 | +(define_expand "sync_new_nand<mode>" | ||
| 813 | + [(match_operand:NARROW 0 "s_register_operand") | ||
| 814 | + (match_operand:NARROW 1 "memory_operand") | ||
| 815 | + (match_operand:NARROW 2 "s_register_operand") | ||
| 816 | + (not:NARROW (and:NARROW (match_dup 1) (match_dup 2)))] | ||
| 817 | + "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 818 | + { | ||
| 819 | + struct arm_sync_generator generator; | ||
| 820 | + generator.op = arm_sync_generator_omn; | ||
| 821 | + generator.u.omn = gen_arm_sync_new_nand<mode>; | ||
| 822 | + arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1], | ||
| 823 | + NULL, operands[2]); | ||
| 824 | + DONE; | ||
| 825 | + }); | ||
| 826 | + | ||
| 827 | +(define_expand "sync_old_<sync_optab>si" | ||
| 828 | + [(match_operand:SI 0 "s_register_operand") | ||
| 829 | + (match_operand:SI 1 "memory_operand") | ||
| 830 | + (match_operand:SI 2 "s_register_operand") | ||
| 831 | + (syncop:SI (match_dup 1) (match_dup 2))] | ||
| 832 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 833 | + { | ||
| 834 | + struct arm_sync_generator generator; | ||
| 835 | + generator.op = arm_sync_generator_omn; | ||
| 836 | + generator.u.omn = gen_arm_sync_old_<sync_optab>si; | ||
| 837 | + arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, | ||
| 838 | + operands[2]); | ||
| 839 | + DONE; | ||
| 840 | + }) | ||
| 841 | + | ||
| 842 | +(define_expand "sync_old_nandsi" | ||
| 843 | + [(match_operand:SI 0 "s_register_operand") | ||
| 844 | + (match_operand:SI 1 "memory_operand") | ||
| 845 | + (match_operand:SI 2 "s_register_operand") | ||
| 846 | + (not:SI (and:SI (match_dup 1) (match_dup 2)))] | ||
| 847 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 848 | + { | ||
| 849 | + struct arm_sync_generator generator; | ||
| 850 | + generator.op = arm_sync_generator_omn; | ||
| 851 | + generator.u.omn = gen_arm_sync_old_nandsi; | ||
| 852 | + arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL, | ||
| 853 | + operands[2]); | ||
| 854 | + DONE; | ||
| 855 | + }) | ||
| 856 | + | ||
| 857 | +(define_expand "sync_old_<sync_optab><mode>" | ||
| 858 | + [(match_operand:NARROW 0 "s_register_operand") | ||
| 859 | + (match_operand:NARROW 1 "memory_operand") | ||
| 860 | + (match_operand:NARROW 2 "s_register_operand") | ||
| 861 | + (syncop:NARROW (match_dup 1) (match_dup 2))] | ||
| 862 | + "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 863 | + { | ||
| 864 | + struct arm_sync_generator generator; | ||
| 865 | + generator.op = arm_sync_generator_omn; | ||
| 866 | + generator.u.omn = gen_arm_sync_old_<sync_optab><mode>; | ||
| 867 | + arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1], | ||
| 868 | + NULL, operands[2]); | ||
| 869 | + DONE; | ||
| 870 | + }) | ||
| 871 | + | ||
| 872 | +(define_expand "sync_old_nand<mode>" | ||
| 873 | + [(match_operand:NARROW 0 "s_register_operand") | ||
| 874 | + (match_operand:NARROW 1 "memory_operand") | ||
| 875 | + (match_operand:NARROW 2 "s_register_operand") | ||
| 876 | + (not:NARROW (and:NARROW (match_dup 1) (match_dup 2)))] | ||
| 877 | + "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 878 | + { | ||
| 879 | + struct arm_sync_generator generator; | ||
| 880 | + generator.op = arm_sync_generator_omn; | ||
| 881 | + generator.u.omn = gen_arm_sync_old_nand<mode>; | ||
| 882 | + arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1], | ||
| 883 | + NULL, operands[2]); | ||
| 884 | + DONE; | ||
| 885 | + }) | ||
| 886 | + | ||
| 887 | +(define_insn "arm_sync_compare_and_swapsi" | ||
| 888 | + [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 889 | + (unspec_volatile:SI | ||
| 890 | + [(match_operand:SI 1 "memory_operand" "+m") | ||
| 891 | + (match_operand:SI 2 "s_register_operand" "r") | ||
| 892 | + (match_operand:SI 3 "s_register_operand" "r")] | ||
| 893 | + VUNSPEC_SYNC_COMPARE_AND_SWAP)) | ||
| 894 | + (set (match_dup 1) (unspec_volatile:SI [(match_dup 2)] | ||
| 895 | + VUNSPEC_SYNC_COMPARE_AND_SWAP)) | ||
| 896 | + (clobber:SI (match_scratch:SI 4 "=&r")) | ||
| 897 | + (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)] | ||
| 898 | + VUNSPEC_SYNC_COMPARE_AND_SWAP)) | ||
| 899 | + ] | ||
| 900 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 901 | + { | ||
| 902 | + return arm_output_sync_insn (insn, operands); | ||
| 903 | + } | ||
| 904 | + [(set_attr "sync_result" "0") | ||
| 905 | + (set_attr "sync_memory" "1") | ||
| 906 | + (set_attr "sync_required_value" "2") | ||
| 907 | + (set_attr "sync_new_value" "3") | ||
| 908 | + (set_attr "sync_t1" "0") | ||
| 909 | + (set_attr "sync_t2" "4") | ||
| 910 | + (set_attr "conds" "nocond") | ||
| 911 | + (set_attr "predicable" "no")]) | ||
| 912 | + | ||
| 913 | +(define_insn "arm_sync_compare_and_swap<mode>" | ||
| 914 | + [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 915 | + (zero_extend:SI | ||
| 916 | + (unspec_volatile:NARROW | ||
| 917 | + [(match_operand:NARROW 1 "memory_operand" "+m") | ||
| 918 | + (match_operand:SI 2 "s_register_operand" "r") | ||
| 919 | + (match_operand:SI 3 "s_register_operand" "r")] | ||
| 920 | + VUNSPEC_SYNC_COMPARE_AND_SWAP))) | ||
| 921 | + (set (match_dup 1) (unspec_volatile:NARROW [(match_dup 2)] | ||
| 922 | + VUNSPEC_SYNC_COMPARE_AND_SWAP)) | ||
| 923 | + (clobber:SI (match_scratch:SI 4 "=&r")) | ||
| 924 | + (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)] | ||
| 925 | + VUNSPEC_SYNC_COMPARE_AND_SWAP)) | ||
| 926 | + ] | ||
| 927 | + "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 928 | + { | ||
| 929 | + return arm_output_sync_insn (insn, operands); | ||
| 930 | + } | ||
| 931 | + [(set_attr "sync_result" "0") | ||
| 932 | + (set_attr "sync_memory" "1") | ||
| 933 | + (set_attr "sync_required_value" "2") | ||
| 934 | + (set_attr "sync_new_value" "3") | ||
| 935 | + (set_attr "sync_t1" "0") | ||
| 936 | + (set_attr "sync_t2" "4") | ||
| 937 | + (set_attr "conds" "nocond") | ||
| 938 | + (set_attr "predicable" "no")]) | ||
| 939 | + | ||
| 940 | +(define_insn "arm_sync_lock_test_and_setsi" | ||
| 941 | + [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 942 | + (match_operand:SI 1 "memory_operand" "+m")) | ||
| 943 | + (set (match_dup 1) | ||
| 944 | + (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")] | ||
| 945 | + VUNSPEC_SYNC_LOCK)) | ||
| 946 | + (clobber (reg:CC CC_REGNUM)) | ||
| 947 | + (clobber (match_scratch:SI 3 "=&r"))] | ||
| 948 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 949 | + { | ||
| 950 | + return arm_output_sync_insn (insn, operands); | ||
| 951 | + } | ||
| 952 | + [(set_attr "sync_release_barrier" "no") | ||
| 953 | + (set_attr "sync_result" "0") | ||
| 954 | + (set_attr "sync_memory" "1") | ||
| 955 | + (set_attr "sync_new_value" "2") | ||
| 956 | + (set_attr "sync_t1" "0") | ||
| 957 | + (set_attr "sync_t2" "3") | ||
| 958 | + (set_attr "conds" "nocond") | ||
| 959 | + (set_attr "predicable" "no")]) | ||
| 960 | + | ||
| 961 | +(define_insn "arm_sync_lock_test_and_set<mode>" | ||
| 962 | + [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 963 | + (zero_extend:SI (match_operand:NARROW 1 "memory_operand" "+m"))) | ||
| 964 | + (set (match_dup 1) | ||
| 965 | + (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")] | ||
| 966 | + VUNSPEC_SYNC_LOCK)) | ||
| 967 | + (clobber (reg:CC CC_REGNUM)) | ||
| 968 | + (clobber (match_scratch:SI 3 "=&r"))] | ||
| 969 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 970 | + { | ||
| 971 | + return arm_output_sync_insn (insn, operands); | ||
| 972 | + } | ||
| 973 | + [(set_attr "sync_release_barrier" "no") | ||
| 974 | + (set_attr "sync_result" "0") | ||
| 975 | + (set_attr "sync_memory" "1") | ||
| 976 | + (set_attr "sync_new_value" "2") | ||
| 977 | + (set_attr "sync_t1" "0") | ||
| 978 | + (set_attr "sync_t2" "3") | ||
| 979 | + (set_attr "conds" "nocond") | ||
| 980 | + (set_attr "predicable" "no")]) | ||
| 981 | + | ||
| 982 | +(define_insn "arm_sync_new_<sync_optab>si" | ||
| 983 | + [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 984 | + (unspec_volatile:SI [(syncop:SI | ||
| 985 | + (match_operand:SI 1 "memory_operand" "+m") | ||
| 986 | + (match_operand:SI 2 "s_register_operand" "r")) | ||
| 987 | + ] | ||
| 988 | + VUNSPEC_SYNC_NEW_OP)) | ||
| 989 | + (set (match_dup 1) | ||
| 990 | + (unspec_volatile:SI [(match_dup 1) (match_dup 2)] | ||
| 991 | + VUNSPEC_SYNC_NEW_OP)) | ||
| 992 | + (clobber (reg:CC CC_REGNUM)) | ||
| 993 | + (clobber (match_scratch:SI 3 "=&r"))] | ||
| 994 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 995 | + { | ||
| 996 | + return arm_output_sync_insn (insn, operands); | ||
| 997 | + } | ||
| 998 | + [(set_attr "sync_result" "0") | ||
| 999 | + (set_attr "sync_memory" "1") | ||
| 1000 | + (set_attr "sync_new_value" "2") | ||
| 1001 | + (set_attr "sync_t1" "0") | ||
| 1002 | + (set_attr "sync_t2" "3") | ||
| 1003 | + (set_attr "sync_op" "<sync_optab>") | ||
| 1004 | + (set_attr "conds" "nocond") | ||
| 1005 | + (set_attr "predicable" "no")]) | ||
| 1006 | + | ||
| 1007 | +(define_insn "arm_sync_new_nandsi" | ||
| 1008 | + [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 1009 | + (unspec_volatile:SI [(not:SI (and:SI | ||
| 1010 | + (match_operand:SI 1 "memory_operand" "+m") | ||
| 1011 | + (match_operand:SI 2 "s_register_operand" "r"))) | ||
| 1012 | + ] | ||
| 1013 | + VUNSPEC_SYNC_NEW_OP)) | ||
| 1014 | + (set (match_dup 1) | ||
| 1015 | + (unspec_volatile:SI [(match_dup 1) (match_dup 2)] | ||
| 1016 | + VUNSPEC_SYNC_NEW_OP)) | ||
| 1017 | + (clobber (reg:CC CC_REGNUM)) | ||
| 1018 | + (clobber (match_scratch:SI 3 "=&r"))] | ||
| 1019 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 1020 | + { | ||
| 1021 | + return arm_output_sync_insn (insn, operands); | ||
| 1022 | + } | ||
| 1023 | + [(set_attr "sync_result" "0") | ||
| 1024 | + (set_attr "sync_memory" "1") | ||
| 1025 | + (set_attr "sync_new_value" "2") | ||
| 1026 | + (set_attr "sync_t1" "0") | ||
| 1027 | + (set_attr "sync_t2" "3") | ||
| 1028 | + (set_attr "sync_op" "nand") | ||
| 1029 | + (set_attr "conds" "nocond") | ||
| 1030 | + (set_attr "predicable" "no")]) | ||
| 1031 | + | ||
| 1032 | +(define_insn "arm_sync_new_<sync_optab><mode>" | ||
| 1033 | + [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 1034 | + (unspec_volatile:SI [(syncop:SI | ||
| 1035 | + (zero_extend:SI | ||
| 1036 | + (match_operand:NARROW 1 "memory_operand" "+m")) | ||
| 1037 | + (match_operand:SI 2 "s_register_operand" "r")) | ||
| 1038 | + ] | ||
| 1039 | + VUNSPEC_SYNC_NEW_OP)) | ||
| 1040 | + (set (match_dup 1) | ||
| 1041 | + (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)] | ||
| 1042 | + VUNSPEC_SYNC_NEW_OP)) | ||
| 1043 | + (clobber (reg:CC CC_REGNUM)) | ||
| 1044 | + (clobber (match_scratch:SI 3 "=&r"))] | ||
| 1045 | + "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 1046 | + { | ||
| 1047 | + return arm_output_sync_insn (insn, operands); | ||
| 1048 | + } | ||
| 1049 | + [(set_attr "sync_result" "0") | ||
| 1050 | + (set_attr "sync_memory" "1") | ||
| 1051 | + (set_attr "sync_new_value" "2") | ||
| 1052 | + (set_attr "sync_t1" "0") | ||
| 1053 | + (set_attr "sync_t2" "3") | ||
| 1054 | + (set_attr "sync_op" "<sync_optab>") | ||
| 1055 | + (set_attr "conds" "nocond") | ||
| 1056 | + (set_attr "predicable" "no")]) | ||
| 1057 | + | ||
| 1058 | +(define_insn "arm_sync_new_nand<mode>" | ||
| 1059 | + [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 1060 | + (unspec_volatile:SI | ||
| 1061 | + [(not:SI | ||
| 1062 | + (and:SI | ||
| 1063 | + (zero_extend:SI | ||
| 1064 | + (match_operand:NARROW 1 "memory_operand" "+m")) | ||
| 1065 | + (match_operand:SI 2 "s_register_operand" "r"))) | ||
| 1066 | + ] VUNSPEC_SYNC_NEW_OP)) | ||
| 1067 | + (set (match_dup 1) | ||
| 1068 | + (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)] | ||
| 1069 | + VUNSPEC_SYNC_NEW_OP)) | ||
| 1070 | + (clobber (reg:CC CC_REGNUM)) | ||
| 1071 | + (clobber (match_scratch:SI 3 "=&r"))] | ||
| 1072 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 1073 | + { | ||
| 1074 | + return arm_output_sync_insn (insn, operands); | ||
| 1075 | + } | ||
| 1076 | + [(set_attr "sync_result" "0") | ||
| 1077 | + (set_attr "sync_memory" "1") | ||
| 1078 | + (set_attr "sync_new_value" "2") | ||
| 1079 | + (set_attr "sync_t1" "0") | ||
| 1080 | + (set_attr "sync_t2" "3") | ||
| 1081 | + (set_attr "sync_op" "nand") | ||
| 1082 | + (set_attr "conds" "nocond") | ||
| 1083 | + (set_attr "predicable" "no")]) | ||
| 1084 | + | ||
| 1085 | +(define_insn "arm_sync_old_<sync_optab>si" | ||
| 1086 | + [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 1087 | + (unspec_volatile:SI [(syncop:SI | ||
| 1088 | + (match_operand:SI 1 "memory_operand" "+m") | ||
| 1089 | + (match_operand:SI 2 "s_register_operand" "r")) | ||
| 1090 | + ] | ||
| 1091 | + VUNSPEC_SYNC_OLD_OP)) | ||
| 1092 | + (set (match_dup 1) | ||
| 1093 | + (unspec_volatile:SI [(match_dup 1) (match_dup 2)] | ||
| 1094 | + VUNSPEC_SYNC_OLD_OP)) | ||
| 1095 | + (clobber (reg:CC CC_REGNUM)) | ||
| 1096 | + (clobber (match_scratch:SI 3 "=&r")) | ||
| 1097 | + (clobber (match_scratch:SI 4 "=&r"))] | ||
| 1098 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 1099 | + { | ||
| 1100 | + return arm_output_sync_insn (insn, operands); | ||
| 1101 | + } | ||
| 1102 | + [(set_attr "sync_result" "0") | ||
| 1103 | + (set_attr "sync_memory" "1") | ||
| 1104 | + (set_attr "sync_new_value" "2") | ||
| 1105 | + (set_attr "sync_t1" "3") | ||
| 1106 | + (set_attr "sync_t2" "4") | ||
| 1107 | + (set_attr "sync_op" "<sync_optab>") | ||
| 1108 | + (set_attr "conds" "nocond") | ||
| 1109 | + (set_attr "predicable" "no")]) | ||
| 1110 | + | ||
| 1111 | +(define_insn "arm_sync_old_nandsi" | ||
| 1112 | + [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 1113 | + (unspec_volatile:SI [(not:SI (and:SI | ||
| 1114 | + (match_operand:SI 1 "memory_operand" "+m") | ||
| 1115 | + (match_operand:SI 2 "s_register_operand" "r"))) | ||
| 1116 | + ] | ||
| 1117 | + VUNSPEC_SYNC_OLD_OP)) | ||
| 1118 | + (set (match_dup 1) | ||
| 1119 | + (unspec_volatile:SI [(match_dup 1) (match_dup 2)] | ||
| 1120 | + VUNSPEC_SYNC_OLD_OP)) | ||
| 1121 | + (clobber (reg:CC CC_REGNUM)) | ||
| 1122 | + (clobber (match_scratch:SI 3 "=&r")) | ||
| 1123 | + (clobber (match_scratch:SI 4 "=&r"))] | ||
| 1124 | + "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 1125 | + { | ||
| 1126 | + return arm_output_sync_insn (insn, operands); | ||
| 1127 | + } | ||
| 1128 | + [(set_attr "sync_result" "0") | ||
| 1129 | + (set_attr "sync_memory" "1") | ||
| 1130 | + (set_attr "sync_new_value" "2") | ||
| 1131 | + (set_attr "sync_t1" "3") | ||
| 1132 | + (set_attr "sync_t2" "4") | ||
| 1133 | + (set_attr "sync_op" "nand") | ||
| 1134 | + (set_attr "conds" "nocond") | ||
| 1135 | + (set_attr "predicable" "no")]) | ||
| 1136 | + | ||
| 1137 | +(define_insn "arm_sync_old_<sync_optab><mode>" | ||
| 1138 | + [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 1139 | + (unspec_volatile:SI [(syncop:SI | ||
| 1140 | + (zero_extend:SI | ||
| 1141 | + (match_operand:NARROW 1 "memory_operand" "+m")) | ||
| 1142 | + (match_operand:SI 2 "s_register_operand" "r")) | ||
| 1143 | + ] | ||
| 1144 | + VUNSPEC_SYNC_OLD_OP)) | ||
| 1145 | + (set (match_dup 1) | ||
| 1146 | + (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)] | ||
| 1147 | + VUNSPEC_SYNC_OLD_OP)) | ||
| 1148 | + (clobber (reg:CC CC_REGNUM)) | ||
| 1149 | + (clobber (match_scratch:SI 3 "=&r")) | ||
| 1150 | + (clobber (match_scratch:SI 4 "=&r"))] | ||
| 1151 | + "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 1152 | + { | ||
| 1153 | + return arm_output_sync_insn (insn, operands); | ||
| 1154 | + } | ||
| 1155 | + [(set_attr "sync_result" "0") | ||
| 1156 | + (set_attr "sync_memory" "1") | ||
| 1157 | + (set_attr "sync_new_value" "2") | ||
| 1158 | + (set_attr "sync_t1" "3") | ||
| 1159 | + (set_attr "sync_t2" "4") | ||
| 1160 | + (set_attr "sync_op" "<sync_optab>") | ||
| 1161 | + (set_attr "conds" "nocond") | ||
| 1162 | + (set_attr "predicable" "no")]) | ||
| 1163 | + | ||
| 1164 | +(define_insn "arm_sync_old_nand<mode>" | ||
| 1165 | + [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 1166 | + (unspec_volatile:SI [(not:SI (and:SI | ||
| 1167 | + (zero_extend:SI | ||
| 1168 | + (match_operand:NARROW 1 "memory_operand" "+m")) | ||
| 1169 | + (match_operand:SI 2 "s_register_operand" "r"))) | ||
| 1170 | + ] | ||
| 1171 | + VUNSPEC_SYNC_OLD_OP)) | ||
| 1172 | + (set (match_dup 1) | ||
| 1173 | + (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)] | ||
| 1174 | + VUNSPEC_SYNC_OLD_OP)) | ||
| 1175 | + (clobber (reg:CC CC_REGNUM)) | ||
| 1176 | + (clobber (match_scratch:SI 3 "=&r")) | ||
| 1177 | + (clobber (match_scratch:SI 4 "=&r"))] | ||
| 1178 | + "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 1179 | + { | ||
| 1180 | + return arm_output_sync_insn (insn, operands); | ||
| 1181 | + } | ||
| 1182 | + [(set_attr "sync_result" "0") | ||
| 1183 | + (set_attr "sync_memory" "1") | ||
| 1184 | + (set_attr "sync_new_value" "2") | ||
| 1185 | + (set_attr "sync_t1" "3") | ||
| 1186 | + (set_attr "sync_t2" "4") | ||
| 1187 | + (set_attr "sync_op" "nand") | ||
| 1188 | + (set_attr "conds" "nocond") | ||
| 1189 | + (set_attr "predicable" "no")]) | ||
| 1190 | + | ||
| 1191 | +(define_insn "*memory_barrier" | ||
| 1192 | + [(set (match_operand:BLK 0 "" "") | ||
| 1193 | + (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))] | ||
| 1194 | + "TARGET_HAVE_MEMORY_BARRIER" | ||
| 1195 | + { | ||
| 1196 | + return arm_output_memory_barrier (operands); | ||
| 1197 | + } | ||
| 1198 | + [(set_attr "length" "4") | ||
| 1199 | + (set_attr "conds" "unconditional") | ||
| 1200 | + (set_attr "predicable" "no")]) | ||
| 1201 | + | ||
| 1202 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch deleted file mode 100644 index d10cf3465..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99385.patch +++ /dev/null | |||
| @@ -1,151 +0,0 @@ | |||
| 1 | 2010-09-02 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 2 | * config/arm/predicates.md (arm_sync_memory_operand): New. | ||
| 3 | * config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate | ||
| 4 | to arm_sync_memory_operand and constraint to Q. | ||
| 5 | (arm_sync_compare_and_swap<mode>): Likewise. | ||
| 6 | (arm_sync_compare_and_swap<mode>): Likewise. | ||
| 7 | (arm_sync_lock_test_and_setsi): Likewise. | ||
| 8 | (arm_sync_lock_test_and_set<mode>): Likewise. | ||
| 9 | (arm_sync_new_<sync_optab>si): Likewise. | ||
| 10 | (arm_sync_new_nandsi): Likewise. | ||
| 11 | (arm_sync_new_<sync_optab><mode>): Likewise. | ||
| 12 | (arm_sync_new_nand<mode>): Likewise. | ||
| 13 | (arm_sync_old_<sync_optab>si): Likewise. | ||
| 14 | (arm_sync_old_nandsi): Likewise. | ||
| 15 | (arm_sync_old_<sync_optab><mode>): Likewise. | ||
| 16 | (arm_sync_old_nand<mode>): Likewise. | ||
| 17 | |||
| 18 | 2010-09-09 Andrew Stubbs <ams@codesourcery.com> | ||
| 19 | |||
| 20 | Backport from mainline: | ||
| 21 | |||
| 22 | 2010-08-18 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 23 | |||
| 24 | === modified file 'gcc/config/arm/predicates.md' | ||
| 25 | --- old/gcc/config/arm/predicates.md 2010-09-09 14:11:34 +0000 | ||
| 26 | +++ new/gcc/config/arm/predicates.md 2010-09-09 15:18:16 +0000 | ||
| 27 | @@ -573,6 +573,11 @@ | ||
| 28 | (and (match_test "TARGET_32BIT") | ||
| 29 | (match_operand 0 "arm_di_operand")))) | ||
| 30 | |||
| 31 | +;; True if the operand is memory reference suitable for a ldrex/strex. | ||
| 32 | +(define_predicate "arm_sync_memory_operand" | ||
| 33 | + (and (match_operand 0 "memory_operand") | ||
| 34 | + (match_code "reg" "0"))) | ||
| 35 | + | ||
| 36 | ;; Predicates for parallel expanders based on mode. | ||
| 37 | (define_special_predicate "vect_par_constant_high" | ||
| 38 | (match_code "parallel") | ||
| 39 | |||
| 40 | === modified file 'gcc/config/arm/sync.md' | ||
| 41 | --- old/gcc/config/arm/sync.md 2010-09-09 15:03:00 +0000 | ||
| 42 | +++ new/gcc/config/arm/sync.md 2010-09-09 15:18:16 +0000 | ||
| 43 | @@ -280,7 +280,7 @@ | ||
| 44 | (define_insn "arm_sync_compare_and_swapsi" | ||
| 45 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 46 | (unspec_volatile:SI | ||
| 47 | - [(match_operand:SI 1 "memory_operand" "+m") | ||
| 48 | + [(match_operand:SI 1 "arm_sync_memory_operand" "+Q") | ||
| 49 | (match_operand:SI 2 "s_register_operand" "r") | ||
| 50 | (match_operand:SI 3 "s_register_operand" "r")] | ||
| 51 | VUNSPEC_SYNC_COMPARE_AND_SWAP)) | ||
| 52 | @@ -307,7 +307,7 @@ | ||
| 53 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 54 | (zero_extend:SI | ||
| 55 | (unspec_volatile:NARROW | ||
| 56 | - [(match_operand:NARROW 1 "memory_operand" "+m") | ||
| 57 | + [(match_operand:NARROW 1 "arm_sync_memory_operand" "+Q") | ||
| 58 | (match_operand:SI 2 "s_register_operand" "r") | ||
| 59 | (match_operand:SI 3 "s_register_operand" "r")] | ||
| 60 | VUNSPEC_SYNC_COMPARE_AND_SWAP))) | ||
| 61 | @@ -332,7 +332,7 @@ | ||
| 62 | |||
| 63 | (define_insn "arm_sync_lock_test_and_setsi" | ||
| 64 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 65 | - (match_operand:SI 1 "memory_operand" "+m")) | ||
| 66 | + (match_operand:SI 1 "arm_sync_memory_operand" "+Q")) | ||
| 67 | (set (match_dup 1) | ||
| 68 | (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")] | ||
| 69 | VUNSPEC_SYNC_LOCK)) | ||
| 70 | @@ -353,7 +353,7 @@ | ||
| 71 | |||
| 72 | (define_insn "arm_sync_lock_test_and_set<mode>" | ||
| 73 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 74 | - (zero_extend:SI (match_operand:NARROW 1 "memory_operand" "+m"))) | ||
| 75 | + (zero_extend:SI (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))) | ||
| 76 | (set (match_dup 1) | ||
| 77 | (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")] | ||
| 78 | VUNSPEC_SYNC_LOCK)) | ||
| 79 | @@ -375,7 +375,7 @@ | ||
| 80 | (define_insn "arm_sync_new_<sync_optab>si" | ||
| 81 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 82 | (unspec_volatile:SI [(syncop:SI | ||
| 83 | - (match_operand:SI 1 "memory_operand" "+m") | ||
| 84 | + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") | ||
| 85 | (match_operand:SI 2 "s_register_operand" "r")) | ||
| 86 | ] | ||
| 87 | VUNSPEC_SYNC_NEW_OP)) | ||
| 88 | @@ -400,7 +400,7 @@ | ||
| 89 | (define_insn "arm_sync_new_nandsi" | ||
| 90 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 91 | (unspec_volatile:SI [(not:SI (and:SI | ||
| 92 | - (match_operand:SI 1 "memory_operand" "+m") | ||
| 93 | + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") | ||
| 94 | (match_operand:SI 2 "s_register_operand" "r"))) | ||
| 95 | ] | ||
| 96 | VUNSPEC_SYNC_NEW_OP)) | ||
| 97 | @@ -426,7 +426,7 @@ | ||
| 98 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 99 | (unspec_volatile:SI [(syncop:SI | ||
| 100 | (zero_extend:SI | ||
| 101 | - (match_operand:NARROW 1 "memory_operand" "+m")) | ||
| 102 | + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) | ||
| 103 | (match_operand:SI 2 "s_register_operand" "r")) | ||
| 104 | ] | ||
| 105 | VUNSPEC_SYNC_NEW_OP)) | ||
| 106 | @@ -454,7 +454,7 @@ | ||
| 107 | [(not:SI | ||
| 108 | (and:SI | ||
| 109 | (zero_extend:SI | ||
| 110 | - (match_operand:NARROW 1 "memory_operand" "+m")) | ||
| 111 | + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) | ||
| 112 | (match_operand:SI 2 "s_register_operand" "r"))) | ||
| 113 | ] VUNSPEC_SYNC_NEW_OP)) | ||
| 114 | (set (match_dup 1) | ||
| 115 | @@ -478,7 +478,7 @@ | ||
| 116 | (define_insn "arm_sync_old_<sync_optab>si" | ||
| 117 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 118 | (unspec_volatile:SI [(syncop:SI | ||
| 119 | - (match_operand:SI 1 "memory_operand" "+m") | ||
| 120 | + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") | ||
| 121 | (match_operand:SI 2 "s_register_operand" "r")) | ||
| 122 | ] | ||
| 123 | VUNSPEC_SYNC_OLD_OP)) | ||
| 124 | @@ -504,7 +504,7 @@ | ||
| 125 | (define_insn "arm_sync_old_nandsi" | ||
| 126 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 127 | (unspec_volatile:SI [(not:SI (and:SI | ||
| 128 | - (match_operand:SI 1 "memory_operand" "+m") | ||
| 129 | + (match_operand:SI 1 "arm_sync_memory_operand" "+Q") | ||
| 130 | (match_operand:SI 2 "s_register_operand" "r"))) | ||
| 131 | ] | ||
| 132 | VUNSPEC_SYNC_OLD_OP)) | ||
| 133 | @@ -531,7 +531,7 @@ | ||
| 134 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 135 | (unspec_volatile:SI [(syncop:SI | ||
| 136 | (zero_extend:SI | ||
| 137 | - (match_operand:NARROW 1 "memory_operand" "+m")) | ||
| 138 | + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) | ||
| 139 | (match_operand:SI 2 "s_register_operand" "r")) | ||
| 140 | ] | ||
| 141 | VUNSPEC_SYNC_OLD_OP)) | ||
| 142 | @@ -558,7 +558,7 @@ | ||
| 143 | [(set (match_operand:SI 0 "s_register_operand" "=&r") | ||
| 144 | (unspec_volatile:SI [(not:SI (and:SI | ||
| 145 | (zero_extend:SI | ||
| 146 | - (match_operand:NARROW 1 "memory_operand" "+m")) | ||
| 147 | + (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")) | ||
| 148 | (match_operand:SI 2 "s_register_operand" "r"))) | ||
| 149 | ] | ||
| 150 | VUNSPEC_SYNC_OLD_OP)) | ||
| 151 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99388.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99388.patch deleted file mode 100644 index f603fcadb..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99388.patch +++ /dev/null | |||
| @@ -1,191 +0,0 @@ | |||
| 1 | 2010-09-13 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from FSF: | ||
| 4 | |||
| 5 | 2010-09-13 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 6 | |||
| 7 | * config/arm/arm.md: (define_attr "conds"): Update comment. | ||
| 8 | * config/arm/sync.md (arm_sync_compare_and_swapsi): Change | ||
| 9 | conds attribute to clob. | ||
| 10 | (arm_sync_compare_and_swapsi): Likewise. | ||
| 11 | (arm_sync_compare_and_swap<mode>): Likewise. | ||
| 12 | (arm_sync_lock_test_and_setsi): Likewise. | ||
| 13 | (arm_sync_lock_test_and_set<mode>): Likewise. | ||
| 14 | (arm_sync_new_<sync_optab>si): Likewise. | ||
| 15 | (arm_sync_new_nandsi): Likewise. | ||
| 16 | (arm_sync_new_<sync_optab><mode>): Likewise. | ||
| 17 | (arm_sync_new_nand<mode>): Likewise. | ||
| 18 | (arm_sync_old_<sync_optab>si): Likewise. | ||
| 19 | (arm_sync_old_nandsi): Likewise. | ||
| 20 | (arm_sync_old_<sync_optab><mode>): Likewise. | ||
| 21 | (arm_sync_old_nand<mode>): Likewise. | ||
| 22 | |||
| 23 | 2010-09-13 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 24 | |||
| 25 | * gcc.target/arm/sync-1.c: New. | ||
| 26 | |||
| 27 | 2010-09-10 Andrew Stubbs <ams@codesourcery.com> | ||
| 28 | |||
| 29 | gcc/ | ||
| 30 | |||
| 31 | === modified file 'gcc/config/arm/arm.md' | ||
| 32 | --- old/gcc/config/arm/arm.md 2010-09-09 15:03:00 +0000 | ||
| 33 | +++ new/gcc/config/arm/arm.md 2010-09-13 15:39:11 +0000 | ||
| 34 | @@ -352,10 +352,11 @@ | ||
| 35 | ; CLOB means that the condition codes are altered in an undefined manner, if | ||
| 36 | ; they are altered at all | ||
| 37 | ; | ||
| 38 | -; UNCONDITIONAL means the instions can not be conditionally executed. | ||
| 39 | +; UNCONDITIONAL means the instruction can not be conditionally executed and | ||
| 40 | +; that the instruction does not use or alter the condition codes. | ||
| 41 | ; | ||
| 42 | -; NOCOND means that the condition codes are neither altered nor affect the | ||
| 43 | -; output of this insn | ||
| 44 | +; NOCOND means that the instruction does not use or alter the condition | ||
| 45 | +; codes but can be converted into a conditionally exectuted instruction. | ||
| 46 | |||
| 47 | (define_attr "conds" "use,set,clob,unconditional,nocond" | ||
| 48 | (if_then_else (eq_attr "type" "call") | ||
| 49 | |||
| 50 | === modified file 'gcc/config/arm/sync.md' | ||
| 51 | --- old/gcc/config/arm/sync.md 2010-09-09 15:18:16 +0000 | ||
| 52 | +++ new/gcc/config/arm/sync.md 2010-09-13 15:39:11 +0000 | ||
| 53 | @@ -300,7 +300,7 @@ | ||
| 54 | (set_attr "sync_new_value" "3") | ||
| 55 | (set_attr "sync_t1" "0") | ||
| 56 | (set_attr "sync_t2" "4") | ||
| 57 | - (set_attr "conds" "nocond") | ||
| 58 | + (set_attr "conds" "clob") | ||
| 59 | (set_attr "predicable" "no")]) | ||
| 60 | |||
| 61 | (define_insn "arm_sync_compare_and_swap<mode>" | ||
| 62 | @@ -327,7 +327,7 @@ | ||
| 63 | (set_attr "sync_new_value" "3") | ||
| 64 | (set_attr "sync_t1" "0") | ||
| 65 | (set_attr "sync_t2" "4") | ||
| 66 | - (set_attr "conds" "nocond") | ||
| 67 | + (set_attr "conds" "clob") | ||
| 68 | (set_attr "predicable" "no")]) | ||
| 69 | |||
| 70 | (define_insn "arm_sync_lock_test_and_setsi" | ||
| 71 | @@ -348,7 +348,7 @@ | ||
| 72 | (set_attr "sync_new_value" "2") | ||
| 73 | (set_attr "sync_t1" "0") | ||
| 74 | (set_attr "sync_t2" "3") | ||
| 75 | - (set_attr "conds" "nocond") | ||
| 76 | + (set_attr "conds" "clob") | ||
| 77 | (set_attr "predicable" "no")]) | ||
| 78 | |||
| 79 | (define_insn "arm_sync_lock_test_and_set<mode>" | ||
| 80 | @@ -369,7 +369,7 @@ | ||
| 81 | (set_attr "sync_new_value" "2") | ||
| 82 | (set_attr "sync_t1" "0") | ||
| 83 | (set_attr "sync_t2" "3") | ||
| 84 | - (set_attr "conds" "nocond") | ||
| 85 | + (set_attr "conds" "clob") | ||
| 86 | (set_attr "predicable" "no")]) | ||
| 87 | |||
| 88 | (define_insn "arm_sync_new_<sync_optab>si" | ||
| 89 | @@ -394,7 +394,7 @@ | ||
| 90 | (set_attr "sync_t1" "0") | ||
| 91 | (set_attr "sync_t2" "3") | ||
| 92 | (set_attr "sync_op" "<sync_optab>") | ||
| 93 | - (set_attr "conds" "nocond") | ||
| 94 | + (set_attr "conds" "clob") | ||
| 95 | (set_attr "predicable" "no")]) | ||
| 96 | |||
| 97 | (define_insn "arm_sync_new_nandsi" | ||
| 98 | @@ -419,7 +419,7 @@ | ||
| 99 | (set_attr "sync_t1" "0") | ||
| 100 | (set_attr "sync_t2" "3") | ||
| 101 | (set_attr "sync_op" "nand") | ||
| 102 | - (set_attr "conds" "nocond") | ||
| 103 | + (set_attr "conds" "clob") | ||
| 104 | (set_attr "predicable" "no")]) | ||
| 105 | |||
| 106 | (define_insn "arm_sync_new_<sync_optab><mode>" | ||
| 107 | @@ -445,7 +445,7 @@ | ||
| 108 | (set_attr "sync_t1" "0") | ||
| 109 | (set_attr "sync_t2" "3") | ||
| 110 | (set_attr "sync_op" "<sync_optab>") | ||
| 111 | - (set_attr "conds" "nocond") | ||
| 112 | + (set_attr "conds" "clob") | ||
| 113 | (set_attr "predicable" "no")]) | ||
| 114 | |||
| 115 | (define_insn "arm_sync_new_nand<mode>" | ||
| 116 | @@ -472,7 +472,7 @@ | ||
| 117 | (set_attr "sync_t1" "0") | ||
| 118 | (set_attr "sync_t2" "3") | ||
| 119 | (set_attr "sync_op" "nand") | ||
| 120 | - (set_attr "conds" "nocond") | ||
| 121 | + (set_attr "conds" "clob") | ||
| 122 | (set_attr "predicable" "no")]) | ||
| 123 | |||
| 124 | (define_insn "arm_sync_old_<sync_optab>si" | ||
| 125 | @@ -498,7 +498,7 @@ | ||
| 126 | (set_attr "sync_t1" "3") | ||
| 127 | (set_attr "sync_t2" "4") | ||
| 128 | (set_attr "sync_op" "<sync_optab>") | ||
| 129 | - (set_attr "conds" "nocond") | ||
| 130 | + (set_attr "conds" "clob") | ||
| 131 | (set_attr "predicable" "no")]) | ||
| 132 | |||
| 133 | (define_insn "arm_sync_old_nandsi" | ||
| 134 | @@ -524,7 +524,7 @@ | ||
| 135 | (set_attr "sync_t1" "3") | ||
| 136 | (set_attr "sync_t2" "4") | ||
| 137 | (set_attr "sync_op" "nand") | ||
| 138 | - (set_attr "conds" "nocond") | ||
| 139 | + (set_attr "conds" "clob") | ||
| 140 | (set_attr "predicable" "no")]) | ||
| 141 | |||
| 142 | (define_insn "arm_sync_old_<sync_optab><mode>" | ||
| 143 | @@ -551,7 +551,7 @@ | ||
| 144 | (set_attr "sync_t1" "3") | ||
| 145 | (set_attr "sync_t2" "4") | ||
| 146 | (set_attr "sync_op" "<sync_optab>") | ||
| 147 | - (set_attr "conds" "nocond") | ||
| 148 | + (set_attr "conds" "clob") | ||
| 149 | (set_attr "predicable" "no")]) | ||
| 150 | |||
| 151 | (define_insn "arm_sync_old_nand<mode>" | ||
| 152 | @@ -578,7 +578,7 @@ | ||
| 153 | (set_attr "sync_t1" "3") | ||
| 154 | (set_attr "sync_t2" "4") | ||
| 155 | (set_attr "sync_op" "nand") | ||
| 156 | - (set_attr "conds" "nocond") | ||
| 157 | + (set_attr "conds" "clob") | ||
| 158 | (set_attr "predicable" "no")]) | ||
| 159 | |||
| 160 | (define_insn "*memory_barrier" | ||
| 161 | |||
| 162 | === added file 'gcc/testsuite/gcc.target/arm/sync-1.c' | ||
| 163 | --- old/gcc/testsuite/gcc.target/arm/sync-1.c 1970-01-01 00:00:00 +0000 | ||
| 164 | +++ new/gcc/testsuite/gcc.target/arm/sync-1.c 2010-09-13 15:39:11 +0000 | ||
| 165 | @@ -0,0 +1,25 @@ | ||
| 166 | +/* { dg-do run } */ | ||
| 167 | +/* { dg-options "-O2 -march=armv7-a" } */ | ||
| 168 | + | ||
| 169 | +volatile int mem; | ||
| 170 | + | ||
| 171 | +int | ||
| 172 | +bar (int x, int y) | ||
| 173 | +{ | ||
| 174 | + if (x) | ||
| 175 | + __sync_fetch_and_add(&mem, y); | ||
| 176 | + return 0; | ||
| 177 | +} | ||
| 178 | + | ||
| 179 | +extern void abort (void); | ||
| 180 | + | ||
| 181 | +int | ||
| 182 | +main (int argc, char *argv[]) | ||
| 183 | +{ | ||
| 184 | + mem = 0; | ||
| 185 | + bar (0, 1); | ||
| 186 | + bar (1, 1); | ||
| 187 | + if (mem != 1) | ||
| 188 | + abort (); | ||
| 189 | + return 0; | ||
| 190 | +} | ||
| 191 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99391.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99391.patch deleted file mode 100644 index 31122e34b..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99391.patch +++ /dev/null | |||
| @@ -1,43 +0,0 @@ | |||
| 1 | 2010-09-08 Tom de Vries <tom@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * gcc/emit-rtl.c (set_mem_attributes_minus_bitpos): Set MEM_READONLY_P | ||
| 5 | for static const strings. | ||
| 6 | * gcc/testsuite/gcc.dg/memcpy-3.c: New test. | ||
| 7 | |||
| 8 | 2010-09-13 Andrew Stubbs <ams@codesourcery.com> | ||
| 9 | |||
| 10 | gcc/ | ||
| 11 | |||
| 12 | === modified file 'gcc/emit-rtl.c' | ||
| 13 | --- old/gcc/emit-rtl.c 2009-11-27 12:00:28 +0000 | ||
| 14 | +++ new/gcc/emit-rtl.c 2010-09-15 16:40:06 +0000 | ||
| 15 | @@ -1648,6 +1648,11 @@ | ||
| 16 | MEM_READONLY_P (ref) = 1; | ||
| 17 | } | ||
| 18 | |||
| 19 | + /* Mark static const strings readonly as well. */ | ||
| 20 | + if (base && TREE_CODE (base) == STRING_CST && TREE_READONLY (base) | ||
| 21 | + && TREE_STATIC (base)) | ||
| 22 | + MEM_READONLY_P (ref) = 1; | ||
| 23 | + | ||
| 24 | /* If this expression uses it's parent's alias set, mark it such | ||
| 25 | that we won't change it. */ | ||
| 26 | if (component_uses_parent_alias_set (t)) | ||
| 27 | |||
| 28 | === added file 'gcc/testsuite/gcc.dg/memcpy-3.c' | ||
| 29 | --- old/gcc/testsuite/gcc.dg/memcpy-3.c 1970-01-01 00:00:00 +0000 | ||
| 30 | +++ new/gcc/testsuite/gcc.dg/memcpy-3.c 2010-09-15 16:40:06 +0000 | ||
| 31 | @@ -0,0 +1,11 @@ | ||
| 32 | +/* { dg-do compile } */ | ||
| 33 | +/* { dg-options "-O2 -fdump-rtl-expand" } */ | ||
| 34 | + | ||
| 35 | +void | ||
| 36 | +f1 (char *p) | ||
| 37 | +{ | ||
| 38 | + __builtin_memcpy (p, "123", 3); | ||
| 39 | +} | ||
| 40 | + | ||
| 41 | +/* { dg-final { scan-rtl-dump-times "mem/s/u:" 3 "expand" { target mips*-*-* } } } */ | ||
| 42 | +/* { dg-final { cleanup-rtl-dump "expand" } } */ | ||
| 43 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99392.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99392.patch deleted file mode 100644 index 9a9d5940c..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99392.patch +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | 2010-09-10 Nathan Froyd <froydnj@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #9120 | ||
| 4 | |||
| 5 | * release-notes-csl.xml (Compiler optimization improvements): New | ||
| 6 | bullet. | ||
| 7 | |||
| 8 | gcc/ | ||
| 9 | * gimple.c (is_gimple_min_invariant): Check for constant INDIRECT_REFs. | ||
| 10 | |||
| 11 | 2010-09-08 Tom de Vries <tom@codesourcery.com> | ||
| 12 | |||
| 13 | gcc/ | ||
| 14 | |||
| 15 | === modified file 'gcc/gimple.c' | ||
| 16 | --- old/gcc/gimple.c 2010-06-22 17:23:11 +0000 | ||
| 17 | +++ new/gcc/gimple.c 2010-09-15 16:47:52 +0000 | ||
| 18 | @@ -2591,7 +2591,13 @@ | ||
| 19 | |||
| 20 | op = strip_invariant_refs (TREE_OPERAND (t, 0)); | ||
| 21 | |||
| 22 | - return op && (CONSTANT_CLASS_P (op) || decl_address_invariant_p (op)); | ||
| 23 | + if (!op) | ||
| 24 | + return false; | ||
| 25 | + | ||
| 26 | + if (TREE_CODE (op) == INDIRECT_REF) | ||
| 27 | + return CONSTANT_CLASS_P (TREE_OPERAND (op, 0)); | ||
| 28 | + else | ||
| 29 | + return CONSTANT_CLASS_P (op) || decl_address_invariant_p (op); | ||
| 30 | } | ||
| 31 | |||
| 32 | /* Return true if T is a gimple invariant address at IPA level | ||
| 33 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99393.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99393.patch deleted file mode 100644 index d8df57a44..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99393.patch +++ /dev/null | |||
| @@ -1,45 +0,0 @@ | |||
| 1 | 2010-09-13 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-09-12 Bernd Schmidt <bernds@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * config/arm/arm.md (arm_ashldi3_1bit, arm_ashrdi3_1bit, | ||
| 9 | arm_lshrdi3_1bit): Put earlyclobber on the right alternative. | ||
| 10 | |||
| 11 | 2010-09-10 Nathan Froyd <froydnj@codesourcery.com> | ||
| 12 | |||
| 13 | Issue #9120 | ||
| 14 | |||
| 15 | === modified file 'gcc/config/arm/arm.md' | ||
| 16 | --- old/gcc/config/arm/arm.md 2010-09-13 15:39:11 +0000 | ||
| 17 | +++ new/gcc/config/arm/arm.md 2010-09-15 16:55:55 +0000 | ||
| 18 | @@ -3295,7 +3295,7 @@ | ||
| 19 | ) | ||
| 20 | |||
| 21 | (define_insn "arm_ashldi3_1bit" | ||
| 22 | - [(set (match_operand:DI 0 "s_register_operand" "=&r,r") | ||
| 23 | + [(set (match_operand:DI 0 "s_register_operand" "=r,&r") | ||
| 24 | (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r") | ||
| 25 | (const_int 1))) | ||
| 26 | (clobber (reg:CC CC_REGNUM))] | ||
| 27 | @@ -3354,7 +3354,7 @@ | ||
| 28 | ) | ||
| 29 | |||
| 30 | (define_insn "arm_ashrdi3_1bit" | ||
| 31 | - [(set (match_operand:DI 0 "s_register_operand" "=&r,r") | ||
| 32 | + [(set (match_operand:DI 0 "s_register_operand" "=r,&r") | ||
| 33 | (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") | ||
| 34 | (const_int 1))) | ||
| 35 | (clobber (reg:CC CC_REGNUM))] | ||
| 36 | @@ -3410,7 +3410,7 @@ | ||
| 37 | ) | ||
| 38 | |||
| 39 | (define_insn "arm_lshrdi3_1bit" | ||
| 40 | - [(set (match_operand:DI 0 "s_register_operand" "=&r,r") | ||
| 41 | + [(set (match_operand:DI 0 "s_register_operand" "=r,&r") | ||
| 42 | (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") | ||
| 43 | (const_int 1))) | ||
| 44 | (clobber (reg:CC CC_REGNUM))] | ||
| 45 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99395.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99395.patch deleted file mode 100644 index 809a20aae..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99395.patch +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | 2010-09-15 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | 2010-09-15 Jie Zhang <jie@codesourcery.com> | ||
| 7 | * config/arm/vfp.md (cmpsf_trap_vfp): Change type from | ||
| 8 | fcmpd to fcmps. | ||
| 9 | |||
| 10 | 2010-09-13 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 11 | |||
| 12 | Backport from mainline: | ||
| 13 | |||
| 14 | === modified file 'gcc/config/arm/vfp.md' | ||
| 15 | --- old/gcc/config/arm/vfp.md 2010-08-13 15:28:31 +0000 | ||
| 16 | +++ new/gcc/config/arm/vfp.md 2010-09-16 08:57:30 +0000 | ||
| 17 | @@ -1159,7 +1159,7 @@ | ||
| 18 | fcmpes%?\\t%0, %1 | ||
| 19 | fcmpezs%?\\t%0" | ||
| 20 | [(set_attr "predicable" "yes") | ||
| 21 | - (set_attr "type" "fcmpd")] | ||
| 22 | + (set_attr "type" "fcmps")] | ||
| 23 | ) | ||
| 24 | |||
| 25 | (define_insn "*cmpdf_vfp" | ||
| 26 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99396.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99396.patch deleted file mode 100644 index b7eaa685a..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99396.patch +++ /dev/null | |||
| @@ -1,1721 +0,0 @@ | |||
| 1 | 2010-09-15 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #9441 | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | |||
| 7 | 2010-06-25 Bernd Schmidt <bernds@codesourcery.com> | ||
| 8 | |||
| 9 | With large parts from Jim Wilson: | ||
| 10 | PR target/43902 | ||
| 11 | |||
| 12 | gcc/ | ||
| 13 | * tree-pretty-print.c (dump_generic_node, op_code_prio): Add | ||
| 14 | WIDEN_MULT_PLUS_EXPR and WIDEN_MULT_MINUS_EXPR. | ||
| 15 | * optabs.c (optab_for_tree_code): Likewise. | ||
| 16 | (expand_widen_pattern_expr): Likewise. | ||
| 17 | * tree-ssa-math-opts.c (convert_mult_to_widen): New function, broken | ||
| 18 | out of execute_optimize_widening_mul. | ||
| 19 | (convert_plusminus_to_widen): New function. | ||
| 20 | (execute_optimize_widening_mul): Use the two new functions. | ||
| 21 | * expr.c (expand_expr_real_2): Add support for GIMPLE_TERNARY_RHS. | ||
| 22 | Remove code to generate widening multiply-accumulate. Add support | ||
| 23 | for WIDEN_MULT_PLUS_EXPR and WIDEN_MULT_MINUS_EXPR. | ||
| 24 | * gimple-pretty-print.c (dump_ternary_rhs): New function. | ||
| 25 | (dump_gimple_assign): Call it when appropriate. | ||
| 26 | * tree.def (WIDEN_MULT_PLUS_EXPR, WIDEN_MULT_MINUS_EXPR): New codes. | ||
| 27 | * cfgexpand.c (gimple_assign_rhs_to_tree): Likewise. | ||
| 28 | (expand_gimple_stmt_1): Likewise. | ||
| 29 | (expand_debug_expr): Support WIDEN_MULT_PLUS_EXPR and | ||
| 30 | WIDEN_MULT_MINUS_EXPR. | ||
| 31 | * tree-ssa-operands.c (get_expr_operands): Likewise. | ||
| 32 | * tree-inline.c (estimate_operator_cost): Likewise. | ||
| 33 | * gimple.c (extract_ops_from_tree_1): Renamed from | ||
| 34 | extract_ops_from_tree. Add new arg for a third operand; fill it. | ||
| 35 | (gimple_build_assign_stat): Support operations with three operands. | ||
| 36 | (gimple_build_assign_with_ops_stat): Likewise. | ||
| 37 | (gimple_assign_set_rhs_from_tree): Likewise. | ||
| 38 | (gimple_assign_set_rhs_with_ops_1): Renamed from | ||
| 39 | gimple_assign_set_rhs_with_ops. Add new arg for a third operand. | ||
| 40 | (get_gimple_rhs_num_ops): Support GIMPLE_TERNARY_RHS. | ||
| 41 | (get_gimple_rhs_num_ops): Handle WIDEN_MULT_PLUS_EXPR and | ||
| 42 | WIDEN_MULT_MINUS_EXPR. | ||
| 43 | * gimple.h (enum gimple_rhs_class): Add GIMPLE_TERNARY_RHS. | ||
| 44 | (extract_ops_from_tree_1): Adjust declaration. | ||
| 45 | (gimple_assign_set_rhs_with_ops_1): Likewise. | ||
| 46 | (gimple_build_assign_with_ops): Pass NULL for last operand. | ||
| 47 | (gimple_build_assign_with_ops3): New macro. | ||
| 48 | (gimple_assign_rhs3, gimple_assign_rhs3_ptr, gimple_assign_set_rhs3, | ||
| 49 | gimple_assign_set_rhs_with_ops, extract_ops_from_tree): New inline | ||
| 50 | functions. | ||
| 51 | * tree-cfg.c (verify_gimple_assign_ternary): New static function. | ||
| 52 | (verify_gimple_assign): Call it. | ||
| 53 | * doc/gimple.texi (Manipulating operands): Document GIMPLE_TERNARY_RHS. | ||
| 54 | (Tuple specific accessors, subsection GIMPLE_ASSIGN): Document new | ||
| 55 | functions for dealing with three-operand statements. | ||
| 56 | * tree.c (commutative_ternary_tree_code): New function. | ||
| 57 | * tree.h (commutative_ternary_tree_code): Declare it. | ||
| 58 | * tree-vrp.c (gimple_assign_nonnegative_warnv_p): Return false for | ||
| 59 | ternary statements. | ||
| 60 | (gimple_assign_nonzero_warnv_p): Likewise. | ||
| 61 | * tree-ssa-sccvn.c (stmt_has_constants): Handle GIMPLE_TERNARY_RHS. | ||
| 62 | * tree-ssa-ccp.c (get_rhs_assign_op_for_ccp): New static function. | ||
| 63 | (ccp_fold): Use it. Handle GIMPLE_TERNARY_RHS. | ||
| 64 | * tree-ssa-dom.c (enum expr_kind): Add EXPR_TERNARY. | ||
| 65 | (struct hashtable_expr): New member ternary in the union. | ||
| 66 | (initialize_hash_element): Handle GIMPLE_TERNARY_RHS. | ||
| 67 | (hashable_expr_equal_p): Fix indentation. Handle EXPR_TERNARY. | ||
| 68 | (iterative_hash_hashable_expr): Likewise. | ||
| 69 | (print_expr_hash_elt): Handle EXPR_TERNARY. | ||
| 70 | * gimple-fold.c (fold_gimple_assign): Handle GIMPLE_TERNARY_RHS. | ||
| 71 | * tree-ssa-threadedge.c (fold_assignment_stmt): Remove useless break | ||
| 72 | statements. Handle GIMPLE_TERNARY_RHS. | ||
| 73 | |||
| 74 | From Jim Wilson: | ||
| 75 | gcc/testsuite/ | ||
| 76 | * gcc.target/mips/madd-9.c: New test. | ||
| 77 | |||
| 78 | 2010-06-29 Bernd Schmidt <bernds@codesourcery.com> | ||
| 79 | |||
| 80 | PR target/43902 | ||
| 81 | gcc/ | ||
| 82 | * config/arm/arm.md (maddsidi4, umaddsidi4): New expanders. | ||
| 83 | (maddhisi4): Renamed from mulhisi3addsi. Operands renumbered. | ||
| 84 | (maddhidi4): Likewise. | ||
| 85 | |||
| 86 | gcc/testsuite/ | ||
| 87 | * gcc.target/arm/wmul-1.c: Test for smlabb instead of smulbb. | ||
| 88 | * gcc.target/arm/wmul-3.c: New test. | ||
| 89 | * gcc.target/arm/wmul-4.c: New test. | ||
| 90 | |||
| 91 | 2010-07-22 Richard Sandiford <rdsandiford@googlemail.com> | ||
| 92 | |||
| 93 | gcc/ | ||
| 94 | * tree-ssa-math-opts.c (is_widening_mult_rhs_p): New function. | ||
| 95 | (is_widening_mult_p): Likewise. | ||
| 96 | (convert_to_widen): Use them. | ||
| 97 | (convert_plusminus_to_widen): Likewise. Handle fixed-point types as | ||
| 98 | well as integer ones. | ||
| 99 | |||
| 100 | 2010-07-31 Richard Sandiford <rdsandiford@googlemail.com> | ||
| 101 | |||
| 102 | gcc/ | ||
| 103 | * tree-ssa-math-opts.c (convert_plusminus_to_widen): Fix type | ||
| 104 | used in the call to optab_for_tree_code. Fix the second | ||
| 105 | is_widening_mult_p call. Check that both unwidened operands | ||
| 106 | have the same sign. | ||
| 107 | |||
| 108 | 2010-09-15 Jie Zhang <jie@codesourcery.com> | ||
| 109 | |||
| 110 | Backport from mainline: | ||
| 111 | |||
| 112 | === modified file 'gcc/cfgexpand.c' | ||
| 113 | Index: gcc-4_5-branch/gcc/cfgexpand.c | ||
| 114 | =================================================================== | ||
| 115 | --- gcc-4_5-branch.orig/gcc/cfgexpand.c 2011-07-22 16:59:23.000000000 -0700 | ||
| 116 | +++ gcc-4_5-branch/gcc/cfgexpand.c 2011-07-22 16:59:28.581747691 -0700 | ||
| 117 | @@ -64,7 +64,13 @@ | ||
| 118 | |||
| 119 | grhs_class = get_gimple_rhs_class (gimple_expr_code (stmt)); | ||
| 120 | |||
| 121 | - if (grhs_class == GIMPLE_BINARY_RHS) | ||
| 122 | + if (grhs_class == GIMPLE_TERNARY_RHS) | ||
| 123 | + t = build3 (gimple_assign_rhs_code (stmt), | ||
| 124 | + TREE_TYPE (gimple_assign_lhs (stmt)), | ||
| 125 | + gimple_assign_rhs1 (stmt), | ||
| 126 | + gimple_assign_rhs2 (stmt), | ||
| 127 | + gimple_assign_rhs3 (stmt)); | ||
| 128 | + else if (grhs_class == GIMPLE_BINARY_RHS) | ||
| 129 | t = build2 (gimple_assign_rhs_code (stmt), | ||
| 130 | TREE_TYPE (gimple_assign_lhs (stmt)), | ||
| 131 | gimple_assign_rhs1 (stmt), | ||
| 132 | @@ -1893,6 +1899,9 @@ | ||
| 133 | ops.type = TREE_TYPE (lhs); | ||
| 134 | switch (get_gimple_rhs_class (gimple_expr_code (stmt))) | ||
| 135 | { | ||
| 136 | + case GIMPLE_TERNARY_RHS: | ||
| 137 | + ops.op2 = gimple_assign_rhs3 (stmt); | ||
| 138 | + /* Fallthru */ | ||
| 139 | case GIMPLE_BINARY_RHS: | ||
| 140 | ops.op1 = gimple_assign_rhs2 (stmt); | ||
| 141 | /* Fallthru */ | ||
| 142 | @@ -2243,6 +2252,8 @@ | ||
| 143 | { | ||
| 144 | case COND_EXPR: | ||
| 145 | case DOT_PROD_EXPR: | ||
| 146 | + case WIDEN_MULT_PLUS_EXPR: | ||
| 147 | + case WIDEN_MULT_MINUS_EXPR: | ||
| 148 | goto ternary; | ||
| 149 | |||
| 150 | case TRUTH_ANDIF_EXPR: | ||
| 151 | @@ -3030,6 +3041,8 @@ | ||
| 152 | return NULL; | ||
| 153 | |||
| 154 | case WIDEN_MULT_EXPR: | ||
| 155 | + case WIDEN_MULT_PLUS_EXPR: | ||
| 156 | + case WIDEN_MULT_MINUS_EXPR: | ||
| 157 | if (SCALAR_INT_MODE_P (GET_MODE (op0)) | ||
| 158 | && SCALAR_INT_MODE_P (mode)) | ||
| 159 | { | ||
| 160 | @@ -3042,7 +3055,13 @@ | ||
| 161 | op1 = simplify_gen_unary (ZERO_EXTEND, mode, op1, inner_mode); | ||
| 162 | else | ||
| 163 | op1 = simplify_gen_unary (SIGN_EXTEND, mode, op1, inner_mode); | ||
| 164 | - return gen_rtx_MULT (mode, op0, op1); | ||
| 165 | + op0 = gen_rtx_MULT (mode, op0, op1); | ||
| 166 | + if (TREE_CODE (exp) == WIDEN_MULT_EXPR) | ||
| 167 | + return op0; | ||
| 168 | + else if (TREE_CODE (exp) == WIDEN_MULT_PLUS_EXPR) | ||
| 169 | + return gen_rtx_PLUS (mode, op0, op2); | ||
| 170 | + else | ||
| 171 | + return gen_rtx_MINUS (mode, op2, op0); | ||
| 172 | } | ||
| 173 | return NULL; | ||
| 174 | |||
| 175 | Index: gcc-4_5-branch/gcc/config/arm/arm.md | ||
| 176 | =================================================================== | ||
| 177 | --- gcc-4_5-branch.orig/gcc/config/arm/arm.md 2011-07-22 16:59:25.000000000 -0700 | ||
| 178 | +++ gcc-4_5-branch/gcc/config/arm/arm.md 2011-07-22 16:59:28.581747691 -0700 | ||
| 179 | @@ -1507,7 +1507,15 @@ | ||
| 180 | (set_attr "predicable" "yes")] | ||
| 181 | ) | ||
| 182 | |||
| 183 | -;; Unnamed template to match long long multiply-accumulate (smlal) | ||
| 184 | +(define_expand "maddsidi4" | ||
| 185 | + [(set (match_operand:DI 0 "s_register_operand" "") | ||
| 186 | + (plus:DI | ||
| 187 | + (mult:DI | ||
| 188 | + (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")) | ||
| 189 | + (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))) | ||
| 190 | + (match_operand:DI 3 "s_register_operand" "")))] | ||
| 191 | + "TARGET_32BIT && arm_arch3m" | ||
| 192 | + "") | ||
| 193 | |||
| 194 | (define_insn "*mulsidi3adddi" | ||
| 195 | [(set (match_operand:DI 0 "s_register_operand" "=&r") | ||
| 196 | @@ -1603,7 +1611,15 @@ | ||
| 197 | (set_attr "predicable" "yes")] | ||
| 198 | ) | ||
| 199 | |||
| 200 | -;; Unnamed template to match long long unsigned multiply-accumulate (umlal) | ||
| 201 | +(define_expand "umaddsidi4" | ||
| 202 | + [(set (match_operand:DI 0 "s_register_operand" "") | ||
| 203 | + (plus:DI | ||
| 204 | + (mult:DI | ||
| 205 | + (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")) | ||
| 206 | + (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))) | ||
| 207 | + (match_operand:DI 3 "s_register_operand" "")))] | ||
| 208 | + "TARGET_32BIT && arm_arch3m" | ||
| 209 | + "") | ||
| 210 | |||
| 211 | (define_insn "*umulsidi3adddi" | ||
| 212 | [(set (match_operand:DI 0 "s_register_operand" "=&r") | ||
| 213 | @@ -1771,29 +1787,29 @@ | ||
| 214 | (set_attr "predicable" "yes")] | ||
| 215 | ) | ||
| 216 | |||
| 217 | -(define_insn "*mulhisi3addsi" | ||
| 218 | +(define_insn "maddhisi4" | ||
| 219 | [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 220 | - (plus:SI (match_operand:SI 1 "s_register_operand" "r") | ||
| 221 | + (plus:SI (match_operand:SI 3 "s_register_operand" "r") | ||
| 222 | (mult:SI (sign_extend:SI | ||
| 223 | - (match_operand:HI 2 "s_register_operand" "%r")) | ||
| 224 | + (match_operand:HI 1 "s_register_operand" "%r")) | ||
| 225 | (sign_extend:SI | ||
| 226 | - (match_operand:HI 3 "s_register_operand" "r")))))] | ||
| 227 | + (match_operand:HI 2 "s_register_operand" "r")))))] | ||
| 228 | "TARGET_DSP_MULTIPLY" | ||
| 229 | - "smlabb%?\\t%0, %2, %3, %1" | ||
| 230 | + "smlabb%?\\t%0, %1, %2, %3" | ||
| 231 | [(set_attr "insn" "smlaxy") | ||
| 232 | (set_attr "predicable" "yes")] | ||
| 233 | ) | ||
| 234 | |||
| 235 | -(define_insn "*mulhidi3adddi" | ||
| 236 | +(define_insn "*maddhidi4" | ||
| 237 | [(set (match_operand:DI 0 "s_register_operand" "=r") | ||
| 238 | (plus:DI | ||
| 239 | - (match_operand:DI 1 "s_register_operand" "0") | ||
| 240 | + (match_operand:DI 3 "s_register_operand" "0") | ||
| 241 | (mult:DI (sign_extend:DI | ||
| 242 | - (match_operand:HI 2 "s_register_operand" "%r")) | ||
| 243 | + (match_operand:HI 1 "s_register_operand" "%r")) | ||
| 244 | (sign_extend:DI | ||
| 245 | - (match_operand:HI 3 "s_register_operand" "r")))))] | ||
| 246 | + (match_operand:HI 2 "s_register_operand" "r")))))] | ||
| 247 | "TARGET_DSP_MULTIPLY" | ||
| 248 | - "smlalbb%?\\t%Q0, %R0, %2, %3" | ||
| 249 | + "smlalbb%?\\t%Q0, %R0, %1, %2" | ||
| 250 | [(set_attr "insn" "smlalxy") | ||
| 251 | (set_attr "predicable" "yes")]) | ||
| 252 | |||
| 253 | Index: gcc-4_5-branch/gcc/doc/gimple.texi | ||
| 254 | =================================================================== | ||
| 255 | --- gcc-4_5-branch.orig/gcc/doc/gimple.texi 2011-07-22 16:58:48.000000000 -0700 | ||
| 256 | +++ gcc-4_5-branch/gcc/doc/gimple.texi 2011-07-22 16:59:28.581747691 -0700 | ||
| 257 | @@ -554,6 +554,9 @@ | ||
| 258 | @item @code{GIMPLE_INVALID_RHS} | ||
| 259 | The tree cannot be used as a GIMPLE operand. | ||
| 260 | |||
| 261 | +@item @code{GIMPLE_TERNARY_RHS} | ||
| 262 | +The tree is a valid GIMPLE ternary operation. | ||
| 263 | + | ||
| 264 | @item @code{GIMPLE_BINARY_RHS} | ||
| 265 | The tree is a valid GIMPLE binary operation. | ||
| 266 | |||
| 267 | @@ -575,10 +578,11 @@ | ||
| 268 | expressions should be flattened into the operand vector. | ||
| 269 | @end itemize | ||
| 270 | |||
| 271 | -For tree nodes in the categories @code{GIMPLE_BINARY_RHS} and | ||
| 272 | -@code{GIMPLE_UNARY_RHS}, they cannot be stored inside tuples directly. | ||
| 273 | -They first need to be flattened and separated into individual | ||
| 274 | -components. For instance, given the GENERIC expression | ||
| 275 | +For tree nodes in the categories @code{GIMPLE_TERNARY_RHS}, | ||
| 276 | +@code{GIMPLE_BINARY_RHS} and @code{GIMPLE_UNARY_RHS}, they cannot be | ||
| 277 | +stored inside tuples directly. They first need to be flattened and | ||
| 278 | +separated into individual components. For instance, given the GENERIC | ||
| 279 | +expression | ||
| 280 | |||
| 281 | @smallexample | ||
| 282 | a = b + c | ||
| 283 | @@ -1082,7 +1086,16 @@ | ||
| 284 | Return the address of the second operand on the @code{RHS} of assignment | ||
| 285 | statement @code{G}. | ||
| 286 | @end deftypefn | ||
| 287 | + | ||
| 288 | +@deftypefn {GIMPLE function} tree gimple_assign_rhs3 (gimple g) | ||
| 289 | +Return the third operand on the @code{RHS} of assignment statement @code{G}. | ||
| 290 | +@end deftypefn | ||
| 291 | |||
| 292 | +@deftypefn {GIMPLE function} tree *gimple_assign_rhs3_ptr (gimple g) | ||
| 293 | +Return the address of the third operand on the @code{RHS} of assignment | ||
| 294 | +statement @code{G}. | ||
| 295 | +@end deftypefn | ||
| 296 | + | ||
| 297 | @deftypefn {GIMPLE function} void gimple_assign_set_lhs (gimple g, tree lhs) | ||
| 298 | Set @code{LHS} to be the @code{LHS} operand of assignment statement @code{G}. | ||
| 299 | @end deftypefn | ||
| 300 | @@ -1092,17 +1105,13 @@ | ||
| 301 | statement @code{G}. | ||
| 302 | @end deftypefn | ||
| 303 | |||
| 304 | -@deftypefn {GIMPLE function} tree gimple_assign_rhs2 (gimple g) | ||
| 305 | -Return the second operand on the @code{RHS} of assignment statement @code{G}. | ||
| 306 | -@end deftypefn | ||
| 307 | - | ||
| 308 | -@deftypefn {GIMPLE function} tree *gimple_assign_rhs2_ptr (gimple g) | ||
| 309 | -Return a pointer to the second operand on the @code{RHS} of assignment | ||
| 310 | +@deftypefn {GIMPLE function} void gimple_assign_set_rhs2 (gimple g, tree rhs) | ||
| 311 | +Set @code{RHS} to be the second operand on the @code{RHS} of assignment | ||
| 312 | statement @code{G}. | ||
| 313 | @end deftypefn | ||
| 314 | |||
| 315 | -@deftypefn {GIMPLE function} void gimple_assign_set_rhs2 (gimple g, tree rhs) | ||
| 316 | -Set @code{RHS} to be the second operand on the @code{RHS} of assignment | ||
| 317 | +@deftypefn {GIMPLE function} void gimple_assign_set_rhs3 (gimple g, tree rhs) | ||
| 318 | +Set @code{RHS} to be the third operand on the @code{RHS} of assignment | ||
| 319 | statement @code{G}. | ||
| 320 | @end deftypefn | ||
| 321 | |||
| 322 | Index: gcc-4_5-branch/gcc/expr.c | ||
| 323 | =================================================================== | ||
| 324 | --- gcc-4_5-branch.orig/gcc/expr.c 2011-07-22 16:59:23.000000000 -0700 | ||
| 325 | +++ gcc-4_5-branch/gcc/expr.c 2011-07-22 16:59:28.591747691 -0700 | ||
| 326 | @@ -7228,8 +7228,6 @@ | ||
| 327 | rtx subtarget, original_target; | ||
| 328 | int ignore; | ||
| 329 | bool reduce_bit_field; | ||
| 330 | - gimple subexp0_def, subexp1_def; | ||
| 331 | - tree top0, top1; | ||
| 332 | location_t loc = ops->location; | ||
| 333 | tree treeop0, treeop1; | ||
| 334 | #define REDUCE_BIT_FIELD(expr) (reduce_bit_field \ | ||
| 335 | @@ -7249,7 +7247,8 @@ | ||
| 336 | exactly those that are valid in gimple expressions that aren't | ||
| 337 | GIMPLE_SINGLE_RHS (or invalid). */ | ||
| 338 | gcc_assert (get_gimple_rhs_class (code) == GIMPLE_UNARY_RHS | ||
| 339 | - || get_gimple_rhs_class (code) == GIMPLE_BINARY_RHS); | ||
| 340 | + || get_gimple_rhs_class (code) == GIMPLE_BINARY_RHS | ||
| 341 | + || get_gimple_rhs_class (code) == GIMPLE_TERNARY_RHS); | ||
| 342 | |||
| 343 | ignore = (target == const0_rtx | ||
| 344 | || ((CONVERT_EXPR_CODE_P (code) | ||
| 345 | @@ -7424,58 +7423,6 @@ | ||
| 346 | fold_convert_loc (loc, ssizetype, | ||
| 347 | treeop1)); | ||
| 348 | case PLUS_EXPR: | ||
| 349 | - | ||
| 350 | - /* Check if this is a case for multiplication and addition. */ | ||
| 351 | - if ((TREE_CODE (type) == INTEGER_TYPE | ||
| 352 | - || TREE_CODE (type) == FIXED_POINT_TYPE) | ||
| 353 | - && (subexp0_def = get_def_for_expr (treeop0, | ||
| 354 | - MULT_EXPR))) | ||
| 355 | - { | ||
| 356 | - tree subsubexp0, subsubexp1; | ||
| 357 | - gimple subsubexp0_def, subsubexp1_def; | ||
| 358 | - enum tree_code this_code; | ||
| 359 | - | ||
| 360 | - this_code = TREE_CODE (type) == INTEGER_TYPE ? NOP_EXPR | ||
| 361 | - : FIXED_CONVERT_EXPR; | ||
| 362 | - subsubexp0 = gimple_assign_rhs1 (subexp0_def); | ||
| 363 | - subsubexp0_def = get_def_for_expr (subsubexp0, this_code); | ||
| 364 | - subsubexp1 = gimple_assign_rhs2 (subexp0_def); | ||
| 365 | - subsubexp1_def = get_def_for_expr (subsubexp1, this_code); | ||
| 366 | - if (subsubexp0_def && subsubexp1_def | ||
| 367 | - && (top0 = gimple_assign_rhs1 (subsubexp0_def)) | ||
| 368 | - && (top1 = gimple_assign_rhs1 (subsubexp1_def)) | ||
| 369 | - && (TYPE_PRECISION (TREE_TYPE (top0)) | ||
| 370 | - < TYPE_PRECISION (TREE_TYPE (subsubexp0))) | ||
| 371 | - && (TYPE_PRECISION (TREE_TYPE (top0)) | ||
| 372 | - == TYPE_PRECISION (TREE_TYPE (top1))) | ||
| 373 | - && (TYPE_UNSIGNED (TREE_TYPE (top0)) | ||
| 374 | - == TYPE_UNSIGNED (TREE_TYPE (top1)))) | ||
| 375 | - { | ||
| 376 | - tree op0type = TREE_TYPE (top0); | ||
| 377 | - enum machine_mode innermode = TYPE_MODE (op0type); | ||
| 378 | - bool zextend_p = TYPE_UNSIGNED (op0type); | ||
| 379 | - bool sat_p = TYPE_SATURATING (TREE_TYPE (subsubexp0)); | ||
| 380 | - if (sat_p == 0) | ||
| 381 | - this_optab = zextend_p ? umadd_widen_optab : smadd_widen_optab; | ||
| 382 | - else | ||
| 383 | - this_optab = zextend_p ? usmadd_widen_optab | ||
| 384 | - : ssmadd_widen_optab; | ||
| 385 | - if (mode == GET_MODE_2XWIDER_MODE (innermode) | ||
| 386 | - && (optab_handler (this_optab, mode)->insn_code | ||
| 387 | - != CODE_FOR_nothing)) | ||
| 388 | - { | ||
| 389 | - expand_operands (top0, top1, NULL_RTX, &op0, &op1, | ||
| 390 | - EXPAND_NORMAL); | ||
| 391 | - op2 = expand_expr (treeop1, subtarget, | ||
| 392 | - VOIDmode, EXPAND_NORMAL); | ||
| 393 | - temp = expand_ternary_op (mode, this_optab, op0, op1, op2, | ||
| 394 | - target, unsignedp); | ||
| 395 | - gcc_assert (temp); | ||
| 396 | - return REDUCE_BIT_FIELD (temp); | ||
| 397 | - } | ||
| 398 | - } | ||
| 399 | - } | ||
| 400 | - | ||
| 401 | /* If we are adding a constant, a VAR_DECL that is sp, fp, or ap, and | ||
| 402 | something else, make sure we add the register to the constant and | ||
| 403 | then to the other thing. This case can occur during strength | ||
| 404 | @@ -7590,57 +7537,6 @@ | ||
| 405 | return REDUCE_BIT_FIELD (simplify_gen_binary (PLUS, mode, op0, op1)); | ||
| 406 | |||
| 407 | case MINUS_EXPR: | ||
| 408 | - /* Check if this is a case for multiplication and subtraction. */ | ||
| 409 | - if ((TREE_CODE (type) == INTEGER_TYPE | ||
| 410 | - || TREE_CODE (type) == FIXED_POINT_TYPE) | ||
| 411 | - && (subexp1_def = get_def_for_expr (treeop1, | ||
| 412 | - MULT_EXPR))) | ||
| 413 | - { | ||
| 414 | - tree subsubexp0, subsubexp1; | ||
| 415 | - gimple subsubexp0_def, subsubexp1_def; | ||
| 416 | - enum tree_code this_code; | ||
| 417 | - | ||
| 418 | - this_code = TREE_CODE (type) == INTEGER_TYPE ? NOP_EXPR | ||
| 419 | - : FIXED_CONVERT_EXPR; | ||
| 420 | - subsubexp0 = gimple_assign_rhs1 (subexp1_def); | ||
| 421 | - subsubexp0_def = get_def_for_expr (subsubexp0, this_code); | ||
| 422 | - subsubexp1 = gimple_assign_rhs2 (subexp1_def); | ||
| 423 | - subsubexp1_def = get_def_for_expr (subsubexp1, this_code); | ||
| 424 | - if (subsubexp0_def && subsubexp1_def | ||
| 425 | - && (top0 = gimple_assign_rhs1 (subsubexp0_def)) | ||
| 426 | - && (top1 = gimple_assign_rhs1 (subsubexp1_def)) | ||
| 427 | - && (TYPE_PRECISION (TREE_TYPE (top0)) | ||
| 428 | - < TYPE_PRECISION (TREE_TYPE (subsubexp0))) | ||
| 429 | - && (TYPE_PRECISION (TREE_TYPE (top0)) | ||
| 430 | - == TYPE_PRECISION (TREE_TYPE (top1))) | ||
| 431 | - && (TYPE_UNSIGNED (TREE_TYPE (top0)) | ||
| 432 | - == TYPE_UNSIGNED (TREE_TYPE (top1)))) | ||
| 433 | - { | ||
| 434 | - tree op0type = TREE_TYPE (top0); | ||
| 435 | - enum machine_mode innermode = TYPE_MODE (op0type); | ||
| 436 | - bool zextend_p = TYPE_UNSIGNED (op0type); | ||
| 437 | - bool sat_p = TYPE_SATURATING (TREE_TYPE (subsubexp0)); | ||
| 438 | - if (sat_p == 0) | ||
| 439 | - this_optab = zextend_p ? umsub_widen_optab : smsub_widen_optab; | ||
| 440 | - else | ||
| 441 | - this_optab = zextend_p ? usmsub_widen_optab | ||
| 442 | - : ssmsub_widen_optab; | ||
| 443 | - if (mode == GET_MODE_2XWIDER_MODE (innermode) | ||
| 444 | - && (optab_handler (this_optab, mode)->insn_code | ||
| 445 | - != CODE_FOR_nothing)) | ||
| 446 | - { | ||
| 447 | - expand_operands (top0, top1, NULL_RTX, &op0, &op1, | ||
| 448 | - EXPAND_NORMAL); | ||
| 449 | - op2 = expand_expr (treeop0, subtarget, | ||
| 450 | - VOIDmode, EXPAND_NORMAL); | ||
| 451 | - temp = expand_ternary_op (mode, this_optab, op0, op1, op2, | ||
| 452 | - target, unsignedp); | ||
| 453 | - gcc_assert (temp); | ||
| 454 | - return REDUCE_BIT_FIELD (temp); | ||
| 455 | - } | ||
| 456 | - } | ||
| 457 | - } | ||
| 458 | - | ||
| 459 | /* For initializers, we are allowed to return a MINUS of two | ||
| 460 | symbolic constants. Here we handle all cases when both operands | ||
| 461 | are constant. */ | ||
| 462 | @@ -7681,6 +7577,14 @@ | ||
| 463 | |||
| 464 | goto binop2; | ||
| 465 | |||
| 466 | + case WIDEN_MULT_PLUS_EXPR: | ||
| 467 | + case WIDEN_MULT_MINUS_EXPR: | ||
| 468 | + expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, EXPAND_NORMAL); | ||
| 469 | + op2 = expand_normal (ops->op2); | ||
| 470 | + target = expand_widen_pattern_expr (ops, op0, op1, op2, | ||
| 471 | + target, unsignedp); | ||
| 472 | + return target; | ||
| 473 | + | ||
| 474 | case WIDEN_MULT_EXPR: | ||
| 475 | /* If first operand is constant, swap them. | ||
| 476 | Thus the following special case checks need only | ||
| 477 | Index: gcc-4_5-branch/gcc/gimple-pretty-print.c | ||
| 478 | =================================================================== | ||
| 479 | --- gcc-4_5-branch.orig/gcc/gimple-pretty-print.c 2011-07-22 16:58:48.000000000 -0700 | ||
| 480 | +++ gcc-4_5-branch/gcc/gimple-pretty-print.c 2011-07-22 16:59:28.591747691 -0700 | ||
| 481 | @@ -376,6 +376,34 @@ | ||
| 482 | } | ||
| 483 | } | ||
| 484 | |||
| 485 | +/* Helper for dump_gimple_assign. Print the ternary RHS of the | ||
| 486 | + assignment GS. BUFFER, SPC and FLAGS are as in dump_gimple_stmt. */ | ||
| 487 | + | ||
| 488 | +static void | ||
| 489 | +dump_ternary_rhs (pretty_printer *buffer, gimple gs, int spc, int flags) | ||
| 490 | +{ | ||
| 491 | + const char *p; | ||
| 492 | + enum tree_code code = gimple_assign_rhs_code (gs); | ||
| 493 | + switch (code) | ||
| 494 | + { | ||
| 495 | + case WIDEN_MULT_PLUS_EXPR: | ||
| 496 | + case WIDEN_MULT_MINUS_EXPR: | ||
| 497 | + for (p = tree_code_name [(int) code]; *p; p++) | ||
| 498 | + pp_character (buffer, TOUPPER (*p)); | ||
| 499 | + pp_string (buffer, " <"); | ||
| 500 | + dump_generic_node (buffer, gimple_assign_rhs1 (gs), spc, flags, false); | ||
| 501 | + pp_string (buffer, ", "); | ||
| 502 | + dump_generic_node (buffer, gimple_assign_rhs2 (gs), spc, flags, false); | ||
| 503 | + pp_string (buffer, ", "); | ||
| 504 | + dump_generic_node (buffer, gimple_assign_rhs3 (gs), spc, flags, false); | ||
| 505 | + pp_character (buffer, '>'); | ||
| 506 | + break; | ||
| 507 | + | ||
| 508 | + default: | ||
| 509 | + gcc_unreachable (); | ||
| 510 | + } | ||
| 511 | +} | ||
| 512 | + | ||
| 513 | |||
| 514 | /* Dump the gimple assignment GS. BUFFER, SPC and FLAGS are as in | ||
| 515 | dump_gimple_stmt. */ | ||
| 516 | @@ -418,6 +446,8 @@ | ||
| 517 | dump_unary_rhs (buffer, gs, spc, flags); | ||
| 518 | else if (gimple_num_ops (gs) == 3) | ||
| 519 | dump_binary_rhs (buffer, gs, spc, flags); | ||
| 520 | + else if (gimple_num_ops (gs) == 4) | ||
| 521 | + dump_ternary_rhs (buffer, gs, spc, flags); | ||
| 522 | else | ||
| 523 | gcc_unreachable (); | ||
| 524 | if (!(flags & TDF_RHS_ONLY)) | ||
| 525 | Index: gcc-4_5-branch/gcc/gimple.c | ||
| 526 | =================================================================== | ||
| 527 | --- gcc-4_5-branch.orig/gcc/gimple.c 2011-07-22 16:59:25.000000000 -0700 | ||
| 528 | +++ gcc-4_5-branch/gcc/gimple.c 2011-07-22 16:59:28.591747691 -0700 | ||
| 529 | @@ -289,31 +289,40 @@ | ||
| 530 | |||
| 531 | |||
| 532 | /* Extract the operands and code for expression EXPR into *SUBCODE_P, | ||
| 533 | - *OP1_P and *OP2_P respectively. */ | ||
| 534 | + *OP1_P, *OP2_P and *OP3_P respectively. */ | ||
| 535 | |||
| 536 | void | ||
| 537 | -extract_ops_from_tree (tree expr, enum tree_code *subcode_p, tree *op1_p, | ||
| 538 | - tree *op2_p) | ||
| 539 | +extract_ops_from_tree_1 (tree expr, enum tree_code *subcode_p, tree *op1_p, | ||
| 540 | + tree *op2_p, tree *op3_p) | ||
| 541 | { | ||
| 542 | enum gimple_rhs_class grhs_class; | ||
| 543 | |||
| 544 | *subcode_p = TREE_CODE (expr); | ||
| 545 | grhs_class = get_gimple_rhs_class (*subcode_p); | ||
| 546 | |||
| 547 | - if (grhs_class == GIMPLE_BINARY_RHS) | ||
| 548 | + if (grhs_class == GIMPLE_TERNARY_RHS) | ||
| 549 | { | ||
| 550 | *op1_p = TREE_OPERAND (expr, 0); | ||
| 551 | *op2_p = TREE_OPERAND (expr, 1); | ||
| 552 | + *op3_p = TREE_OPERAND (expr, 2); | ||
| 553 | + } | ||
| 554 | + else if (grhs_class == GIMPLE_BINARY_RHS) | ||
| 555 | + { | ||
| 556 | + *op1_p = TREE_OPERAND (expr, 0); | ||
| 557 | + *op2_p = TREE_OPERAND (expr, 1); | ||
| 558 | + *op3_p = NULL_TREE; | ||
| 559 | } | ||
| 560 | else if (grhs_class == GIMPLE_UNARY_RHS) | ||
| 561 | { | ||
| 562 | *op1_p = TREE_OPERAND (expr, 0); | ||
| 563 | *op2_p = NULL_TREE; | ||
| 564 | + *op3_p = NULL_TREE; | ||
| 565 | } | ||
| 566 | else if (grhs_class == GIMPLE_SINGLE_RHS) | ||
| 567 | { | ||
| 568 | *op1_p = expr; | ||
| 569 | *op2_p = NULL_TREE; | ||
| 570 | + *op3_p = NULL_TREE; | ||
| 571 | } | ||
| 572 | else | ||
| 573 | gcc_unreachable (); | ||
| 574 | @@ -329,10 +338,10 @@ | ||
| 575 | gimple_build_assign_stat (tree lhs, tree rhs MEM_STAT_DECL) | ||
| 576 | { | ||
| 577 | enum tree_code subcode; | ||
| 578 | - tree op1, op2; | ||
| 579 | + tree op1, op2, op3; | ||
| 580 | |||
| 581 | - extract_ops_from_tree (rhs, &subcode, &op1, &op2); | ||
| 582 | - return gimple_build_assign_with_ops_stat (subcode, lhs, op1, op2 | ||
| 583 | + extract_ops_from_tree_1 (rhs, &subcode, &op1, &op2, &op3); | ||
| 584 | + return gimple_build_assign_with_ops_stat (subcode, lhs, op1, op2, op3 | ||
| 585 | PASS_MEM_STAT); | ||
| 586 | } | ||
| 587 | |||
| 588 | @@ -343,7 +352,7 @@ | ||
| 589 | |||
| 590 | gimple | ||
| 591 | gimple_build_assign_with_ops_stat (enum tree_code subcode, tree lhs, tree op1, | ||
| 592 | - tree op2 MEM_STAT_DECL) | ||
| 593 | + tree op2, tree op3 MEM_STAT_DECL) | ||
| 594 | { | ||
| 595 | unsigned num_ops; | ||
| 596 | gimple p; | ||
| 597 | @@ -362,6 +371,12 @@ | ||
| 598 | gimple_assign_set_rhs2 (p, op2); | ||
| 599 | } | ||
| 600 | |||
| 601 | + if (op3) | ||
| 602 | + { | ||
| 603 | + gcc_assert (num_ops > 3); | ||
| 604 | + gimple_assign_set_rhs3 (p, op3); | ||
| 605 | + } | ||
| 606 | + | ||
| 607 | return p; | ||
| 608 | } | ||
| 609 | |||
| 610 | @@ -1860,22 +1875,22 @@ | ||
| 611 | gimple_assign_set_rhs_from_tree (gimple_stmt_iterator *gsi, tree expr) | ||
| 612 | { | ||
| 613 | enum tree_code subcode; | ||
| 614 | - tree op1, op2; | ||
| 615 | + tree op1, op2, op3; | ||
| 616 | |||
| 617 | - extract_ops_from_tree (expr, &subcode, &op1, &op2); | ||
| 618 | - gimple_assign_set_rhs_with_ops (gsi, subcode, op1, op2); | ||
| 619 | + extract_ops_from_tree_1 (expr, &subcode, &op1, &op2, &op3); | ||
| 620 | + gimple_assign_set_rhs_with_ops_1 (gsi, subcode, op1, op2, op3); | ||
| 621 | } | ||
| 622 | |||
| 623 | |||
| 624 | /* Set the RHS of assignment statement pointed-to by GSI to CODE with | ||
| 625 | - operands OP1 and OP2. | ||
| 626 | + operands OP1, OP2 and OP3. | ||
| 627 | |||
| 628 | NOTE: The statement pointed-to by GSI may be reallocated if it | ||
| 629 | did not have enough operand slots. */ | ||
| 630 | |||
| 631 | void | ||
| 632 | -gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *gsi, enum tree_code code, | ||
| 633 | - tree op1, tree op2) | ||
| 634 | +gimple_assign_set_rhs_with_ops_1 (gimple_stmt_iterator *gsi, enum tree_code code, | ||
| 635 | + tree op1, tree op2, tree op3) | ||
| 636 | { | ||
| 637 | unsigned new_rhs_ops = get_gimple_rhs_num_ops (code); | ||
| 638 | gimple stmt = gsi_stmt (*gsi); | ||
| 639 | @@ -1899,6 +1914,8 @@ | ||
| 640 | gimple_assign_set_rhs1 (stmt, op1); | ||
| 641 | if (new_rhs_ops > 1) | ||
| 642 | gimple_assign_set_rhs2 (stmt, op2); | ||
| 643 | + if (new_rhs_ops > 2) | ||
| 644 | + gimple_assign_set_rhs3 (stmt, op3); | ||
| 645 | } | ||
| 646 | |||
| 647 | |||
| 648 | @@ -2378,6 +2395,8 @@ | ||
| 649 | return 1; | ||
| 650 | else if (rhs_class == GIMPLE_BINARY_RHS) | ||
| 651 | return 2; | ||
| 652 | + else if (rhs_class == GIMPLE_TERNARY_RHS) | ||
| 653 | + return 3; | ||
| 654 | else | ||
| 655 | gcc_unreachable (); | ||
| 656 | } | ||
| 657 | @@ -2394,6 +2413,8 @@ | ||
| 658 | || (SYM) == TRUTH_OR_EXPR \ | ||
| 659 | || (SYM) == TRUTH_XOR_EXPR) ? GIMPLE_BINARY_RHS \ | ||
| 660 | : (SYM) == TRUTH_NOT_EXPR ? GIMPLE_UNARY_RHS \ | ||
| 661 | + : ((SYM) == WIDEN_MULT_PLUS_EXPR \ | ||
| 662 | + || (SYM) == WIDEN_MULT_MINUS_EXPR) ? GIMPLE_TERNARY_RHS \ | ||
| 663 | : ((SYM) == COND_EXPR \ | ||
| 664 | || (SYM) == CONSTRUCTOR \ | ||
| 665 | || (SYM) == OBJ_TYPE_REF \ | ||
| 666 | Index: gcc-4_5-branch/gcc/gimple.h | ||
| 667 | =================================================================== | ||
| 668 | --- gcc-4_5-branch.orig/gcc/gimple.h 2011-07-22 16:59:12.000000000 -0700 | ||
| 669 | +++ gcc-4_5-branch/gcc/gimple.h 2011-07-22 16:59:28.591747691 -0700 | ||
| 670 | @@ -80,6 +80,7 @@ | ||
| 671 | enum gimple_rhs_class | ||
| 672 | { | ||
| 673 | GIMPLE_INVALID_RHS, /* The expression cannot be used on the RHS. */ | ||
| 674 | + GIMPLE_TERNARY_RHS, /* The expression is a ternary operation. */ | ||
| 675 | GIMPLE_BINARY_RHS, /* The expression is a binary operation. */ | ||
| 676 | GIMPLE_UNARY_RHS, /* The expression is a unary operation. */ | ||
| 677 | GIMPLE_SINGLE_RHS /* The expression is a single object (an SSA | ||
| 678 | @@ -786,12 +787,14 @@ | ||
| 679 | gimple gimple_build_assign_stat (tree, tree MEM_STAT_DECL); | ||
| 680 | #define gimple_build_assign(l,r) gimple_build_assign_stat (l, r MEM_STAT_INFO) | ||
| 681 | |||
| 682 | -void extract_ops_from_tree (tree, enum tree_code *, tree *, tree *); | ||
| 683 | +void extract_ops_from_tree_1 (tree, enum tree_code *, tree *, tree *, tree *); | ||
| 684 | |||
| 685 | gimple gimple_build_assign_with_ops_stat (enum tree_code, tree, tree, | ||
| 686 | - tree MEM_STAT_DECL); | ||
| 687 | -#define gimple_build_assign_with_ops(c,o1,o2,o3) \ | ||
| 688 | - gimple_build_assign_with_ops_stat (c, o1, o2, o3 MEM_STAT_INFO) | ||
| 689 | + tree, tree MEM_STAT_DECL); | ||
| 690 | +#define gimple_build_assign_with_ops(c,o1,o2,o3) \ | ||
| 691 | + gimple_build_assign_with_ops_stat (c, o1, o2, o3, NULL_TREE MEM_STAT_INFO) | ||
| 692 | +#define gimple_build_assign_with_ops3(c,o1,o2,o3,o4) \ | ||
| 693 | + gimple_build_assign_with_ops_stat (c, o1, o2, o3, o4 MEM_STAT_INFO) | ||
| 694 | |||
| 695 | gimple gimple_build_debug_bind_stat (tree, tree, gimple MEM_STAT_DECL); | ||
| 696 | #define gimple_build_debug_bind(var,val,stmt) \ | ||
| 697 | @@ -850,8 +853,8 @@ | ||
| 698 | bool gimple_assign_unary_nop_p (gimple); | ||
| 699 | void gimple_set_bb (gimple, struct basic_block_def *); | ||
| 700 | void gimple_assign_set_rhs_from_tree (gimple_stmt_iterator *, tree); | ||
| 701 | -void gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *, enum tree_code, | ||
| 702 | - tree, tree); | ||
| 703 | +void gimple_assign_set_rhs_with_ops_1 (gimple_stmt_iterator *, enum tree_code, | ||
| 704 | + tree, tree, tree); | ||
| 705 | tree gimple_get_lhs (const_gimple); | ||
| 706 | void gimple_set_lhs (gimple, tree); | ||
| 707 | void gimple_replace_lhs (gimple, tree); | ||
| 708 | @@ -1793,6 +1796,63 @@ | ||
| 709 | gimple_set_op (gs, 2, rhs); | ||
| 710 | } | ||
| 711 | |||
| 712 | +/* Return the third operand on the RHS of assignment statement GS. | ||
| 713 | + If GS does not have two operands, NULL is returned instead. */ | ||
| 714 | + | ||
| 715 | +static inline tree | ||
| 716 | +gimple_assign_rhs3 (const_gimple gs) | ||
| 717 | +{ | ||
| 718 | + GIMPLE_CHECK (gs, GIMPLE_ASSIGN); | ||
| 719 | + | ||
| 720 | + if (gimple_num_ops (gs) >= 4) | ||
| 721 | + return gimple_op (gs, 3); | ||
| 722 | + else | ||
| 723 | + return NULL_TREE; | ||
| 724 | +} | ||
| 725 | + | ||
| 726 | +/* Return a pointer to the third operand on the RHS of assignment | ||
| 727 | + statement GS. */ | ||
| 728 | + | ||
| 729 | +static inline tree * | ||
| 730 | +gimple_assign_rhs3_ptr (const_gimple gs) | ||
| 731 | +{ | ||
| 732 | + GIMPLE_CHECK (gs, GIMPLE_ASSIGN); | ||
| 733 | + return gimple_op_ptr (gs, 3); | ||
| 734 | +} | ||
| 735 | + | ||
| 736 | + | ||
| 737 | +/* Set RHS to be the third operand on the RHS of assignment statement GS. */ | ||
| 738 | + | ||
| 739 | +static inline void | ||
| 740 | +gimple_assign_set_rhs3 (gimple gs, tree rhs) | ||
| 741 | +{ | ||
| 742 | + GIMPLE_CHECK (gs, GIMPLE_ASSIGN); | ||
| 743 | + | ||
| 744 | + gimple_set_op (gs, 3, rhs); | ||
| 745 | +} | ||
| 746 | + | ||
| 747 | +/* A wrapper around gimple_assign_set_rhs_with_ops_1, for callers which expect | ||
| 748 | + to see only a maximum of two operands. */ | ||
| 749 | + | ||
| 750 | +static inline void | ||
| 751 | +gimple_assign_set_rhs_with_ops (gimple_stmt_iterator *gsi, enum tree_code code, | ||
| 752 | + tree op1, tree op2) | ||
| 753 | +{ | ||
| 754 | + gimple_assign_set_rhs_with_ops_1 (gsi, code, op1, op2, NULL); | ||
| 755 | +} | ||
| 756 | + | ||
| 757 | +/* A wrapper around extract_ops_from_tree_1, for callers which expect | ||
| 758 | + to see only a maximum of two operands. */ | ||
| 759 | + | ||
| 760 | +static inline void | ||
| 761 | +extract_ops_from_tree (tree expr, enum tree_code *code, tree *op0, | ||
| 762 | + tree *op1) | ||
| 763 | +{ | ||
| 764 | + tree op2; | ||
| 765 | + extract_ops_from_tree_1 (expr, code, op0, op1, &op2); | ||
| 766 | + gcc_assert (op2 == NULL_TREE); | ||
| 767 | +} | ||
| 768 | + | ||
| 769 | /* Returns true if GS is a nontemporal move. */ | ||
| 770 | |||
| 771 | static inline bool | ||
| 772 | Index: gcc-4_5-branch/gcc/optabs.c | ||
| 773 | =================================================================== | ||
| 774 | --- gcc-4_5-branch.orig/gcc/optabs.c 2011-07-22 16:58:48.000000000 -0700 | ||
| 775 | +++ gcc-4_5-branch/gcc/optabs.c 2011-07-22 16:59:28.601747691 -0700 | ||
| 776 | @@ -408,6 +408,20 @@ | ||
| 777 | case DOT_PROD_EXPR: | ||
| 778 | return TYPE_UNSIGNED (type) ? udot_prod_optab : sdot_prod_optab; | ||
| 779 | |||
| 780 | + case WIDEN_MULT_PLUS_EXPR: | ||
| 781 | + return (TYPE_UNSIGNED (type) | ||
| 782 | + ? (TYPE_SATURATING (type) | ||
| 783 | + ? usmadd_widen_optab : umadd_widen_optab) | ||
| 784 | + : (TYPE_SATURATING (type) | ||
| 785 | + ? ssmadd_widen_optab : smadd_widen_optab)); | ||
| 786 | + | ||
| 787 | + case WIDEN_MULT_MINUS_EXPR: | ||
| 788 | + return (TYPE_UNSIGNED (type) | ||
| 789 | + ? (TYPE_SATURATING (type) | ||
| 790 | + ? usmsub_widen_optab : umsub_widen_optab) | ||
| 791 | + : (TYPE_SATURATING (type) | ||
| 792 | + ? ssmsub_widen_optab : smsub_widen_optab)); | ||
| 793 | + | ||
| 794 | case REDUC_MAX_EXPR: | ||
| 795 | return TYPE_UNSIGNED (type) ? reduc_umax_optab : reduc_smax_optab; | ||
| 796 | |||
| 797 | @@ -547,7 +561,12 @@ | ||
| 798 | tmode0 = TYPE_MODE (TREE_TYPE (oprnd0)); | ||
| 799 | widen_pattern_optab = | ||
| 800 | optab_for_tree_code (ops->code, TREE_TYPE (oprnd0), optab_default); | ||
| 801 | - icode = (int) optab_handler (widen_pattern_optab, tmode0)->insn_code; | ||
| 802 | + if (ops->code == WIDEN_MULT_PLUS_EXPR | ||
| 803 | + || ops->code == WIDEN_MULT_MINUS_EXPR) | ||
| 804 | + icode = (int) optab_handler (widen_pattern_optab, | ||
| 805 | + TYPE_MODE (TREE_TYPE (ops->op2)))->insn_code; | ||
| 806 | + else | ||
| 807 | + icode = (int) optab_handler (widen_pattern_optab, tmode0)->insn_code; | ||
| 808 | gcc_assert (icode != CODE_FOR_nothing); | ||
| 809 | xmode0 = insn_data[icode].operand[1].mode; | ||
| 810 | |||
| 811 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-1.c | ||
| 812 | =================================================================== | ||
| 813 | --- gcc-4_5-branch.orig/gcc/testsuite/gcc.target/arm/wmul-1.c 2011-07-22 16:59:24.000000000 -0700 | ||
| 814 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-1.c 2011-07-22 16:59:28.601747691 -0700 | ||
| 815 | @@ -15,4 +15,4 @@ | ||
| 816 | return sqr; | ||
| 817 | } | ||
| 818 | |||
| 819 | -/* { dg-final { scan-assembler-times "smulbb" 2 } } */ | ||
| 820 | +/* { dg-final { scan-assembler-times "smlabb" 2 } } */ | ||
| 821 | Index: gcc-4_5-branch/gcc/tree-cfg.c | ||
| 822 | =================================================================== | ||
| 823 | --- gcc-4_5-branch.orig/gcc/tree-cfg.c 2011-07-22 16:59:24.000000000 -0700 | ||
| 824 | +++ gcc-4_5-branch/gcc/tree-cfg.c 2011-07-22 16:59:28.601747691 -0700 | ||
| 825 | @@ -3484,6 +3484,65 @@ | ||
| 826 | return false; | ||
| 827 | } | ||
| 828 | |||
| 829 | +/* Verify a gimple assignment statement STMT with a ternary rhs. | ||
| 830 | + Returns true if anything is wrong. */ | ||
| 831 | + | ||
| 832 | +static bool | ||
| 833 | +verify_gimple_assign_ternary (gimple stmt) | ||
| 834 | +{ | ||
| 835 | + enum tree_code rhs_code = gimple_assign_rhs_code (stmt); | ||
| 836 | + tree lhs = gimple_assign_lhs (stmt); | ||
| 837 | + tree lhs_type = TREE_TYPE (lhs); | ||
| 838 | + tree rhs1 = gimple_assign_rhs1 (stmt); | ||
| 839 | + tree rhs1_type = TREE_TYPE (rhs1); | ||
| 840 | + tree rhs2 = gimple_assign_rhs2 (stmt); | ||
| 841 | + tree rhs2_type = TREE_TYPE (rhs2); | ||
| 842 | + tree rhs3 = gimple_assign_rhs3 (stmt); | ||
| 843 | + tree rhs3_type = TREE_TYPE (rhs3); | ||
| 844 | + | ||
| 845 | + if (!is_gimple_reg (lhs) | ||
| 846 | + && !(optimize == 0 | ||
| 847 | + && TREE_CODE (lhs_type) == COMPLEX_TYPE)) | ||
| 848 | + { | ||
| 849 | + error ("non-register as LHS of ternary operation"); | ||
| 850 | + return true; | ||
| 851 | + } | ||
| 852 | + | ||
| 853 | + if (!is_gimple_val (rhs1) | ||
| 854 | + || !is_gimple_val (rhs2) | ||
| 855 | + || !is_gimple_val (rhs3)) | ||
| 856 | + { | ||
| 857 | + error ("invalid operands in ternary operation"); | ||
| 858 | + return true; | ||
| 859 | + } | ||
| 860 | + | ||
| 861 | + /* First handle operations that involve different types. */ | ||
| 862 | + switch (rhs_code) | ||
| 863 | + { | ||
| 864 | + case WIDEN_MULT_PLUS_EXPR: | ||
| 865 | + case WIDEN_MULT_MINUS_EXPR: | ||
| 866 | + if ((!INTEGRAL_TYPE_P (rhs1_type) | ||
| 867 | + && !FIXED_POINT_TYPE_P (rhs1_type)) | ||
| 868 | + || !useless_type_conversion_p (rhs1_type, rhs2_type) | ||
| 869 | + || !useless_type_conversion_p (lhs_type, rhs3_type) | ||
| 870 | + || 2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type) | ||
| 871 | + || TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type)) | ||
| 872 | + { | ||
| 873 | + error ("type mismatch in widening multiply-accumulate expression"); | ||
| 874 | + debug_generic_expr (lhs_type); | ||
| 875 | + debug_generic_expr (rhs1_type); | ||
| 876 | + debug_generic_expr (rhs2_type); | ||
| 877 | + debug_generic_expr (rhs3_type); | ||
| 878 | + return true; | ||
| 879 | + } | ||
| 880 | + break; | ||
| 881 | + | ||
| 882 | + default: | ||
| 883 | + gcc_unreachable (); | ||
| 884 | + } | ||
| 885 | + return false; | ||
| 886 | +} | ||
| 887 | + | ||
| 888 | /* Verify a gimple assignment statement STMT with a single rhs. | ||
| 889 | Returns true if anything is wrong. */ | ||
| 890 | |||
| 891 | @@ -3616,6 +3675,9 @@ | ||
| 892 | case GIMPLE_BINARY_RHS: | ||
| 893 | return verify_gimple_assign_binary (stmt); | ||
| 894 | |||
| 895 | + case GIMPLE_TERNARY_RHS: | ||
| 896 | + return verify_gimple_assign_ternary (stmt); | ||
| 897 | + | ||
| 898 | default: | ||
| 899 | gcc_unreachable (); | ||
| 900 | } | ||
| 901 | Index: gcc-4_5-branch/gcc/tree-inline.c | ||
| 902 | =================================================================== | ||
| 903 | --- gcc-4_5-branch.orig/gcc/tree-inline.c 2011-07-22 16:59:24.000000000 -0700 | ||
| 904 | +++ gcc-4_5-branch/gcc/tree-inline.c 2011-07-22 16:59:28.601747691 -0700 | ||
| 905 | @@ -3207,6 +3207,8 @@ | ||
| 906 | case WIDEN_SUM_EXPR: | ||
| 907 | case WIDEN_MULT_EXPR: | ||
| 908 | case DOT_PROD_EXPR: | ||
| 909 | + case WIDEN_MULT_PLUS_EXPR: | ||
| 910 | + case WIDEN_MULT_MINUS_EXPR: | ||
| 911 | |||
| 912 | case VEC_WIDEN_MULT_HI_EXPR: | ||
| 913 | case VEC_WIDEN_MULT_LO_EXPR: | ||
| 914 | Index: gcc-4_5-branch/gcc/tree-pretty-print.c | ||
| 915 | =================================================================== | ||
| 916 | --- gcc-4_5-branch.orig/gcc/tree-pretty-print.c 2011-07-22 16:58:48.000000000 -0700 | ||
| 917 | +++ gcc-4_5-branch/gcc/tree-pretty-print.c 2011-07-22 16:59:28.611747691 -0700 | ||
| 918 | @@ -1939,6 +1939,26 @@ | ||
| 919 | pp_string (buffer, " > "); | ||
| 920 | break; | ||
| 921 | |||
| 922 | + case WIDEN_MULT_PLUS_EXPR: | ||
| 923 | + pp_string (buffer, " WIDEN_MULT_PLUS_EXPR < "); | ||
| 924 | + dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false); | ||
| 925 | + pp_string (buffer, ", "); | ||
| 926 | + dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false); | ||
| 927 | + pp_string (buffer, ", "); | ||
| 928 | + dump_generic_node (buffer, TREE_OPERAND (node, 2), spc, flags, false); | ||
| 929 | + pp_string (buffer, " > "); | ||
| 930 | + break; | ||
| 931 | + | ||
| 932 | + case WIDEN_MULT_MINUS_EXPR: | ||
| 933 | + pp_string (buffer, " WIDEN_MULT_MINUS_EXPR < "); | ||
| 934 | + dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false); | ||
| 935 | + pp_string (buffer, ", "); | ||
| 936 | + dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false); | ||
| 937 | + pp_string (buffer, ", "); | ||
| 938 | + dump_generic_node (buffer, TREE_OPERAND (node, 2), spc, flags, false); | ||
| 939 | + pp_string (buffer, " > "); | ||
| 940 | + break; | ||
| 941 | + | ||
| 942 | case OMP_PARALLEL: | ||
| 943 | pp_string (buffer, "#pragma omp parallel"); | ||
| 944 | dump_omp_clauses (buffer, OMP_PARALLEL_CLAUSES (node), spc, flags); | ||
| 945 | @@ -2432,6 +2452,8 @@ | ||
| 946 | case VEC_WIDEN_MULT_LO_EXPR: | ||
| 947 | case WIDEN_MULT_EXPR: | ||
| 948 | case DOT_PROD_EXPR: | ||
| 949 | + case WIDEN_MULT_PLUS_EXPR: | ||
| 950 | + case WIDEN_MULT_MINUS_EXPR: | ||
| 951 | case MULT_EXPR: | ||
| 952 | case TRUNC_DIV_EXPR: | ||
| 953 | case CEIL_DIV_EXPR: | ||
| 954 | Index: gcc-4_5-branch/gcc/tree-ssa-ccp.c | ||
| 955 | =================================================================== | ||
| 956 | --- gcc-4_5-branch.orig/gcc/tree-ssa-ccp.c 2011-07-22 16:59:12.000000000 -0700 | ||
| 957 | +++ gcc-4_5-branch/gcc/tree-ssa-ccp.c 2011-07-22 16:59:28.611747691 -0700 | ||
| 958 | @@ -915,6 +915,23 @@ | ||
| 959 | TREE_TYPE (TREE_OPERAND (addr, 0)))); | ||
| 960 | } | ||
| 961 | |||
| 962 | +/* Get operand number OPNR from the rhs of STMT. Before returning it, | ||
| 963 | + simplify it to a constant if possible. */ | ||
| 964 | + | ||
| 965 | +static tree | ||
| 966 | +get_rhs_assign_op_for_ccp (gimple stmt, int opnr) | ||
| 967 | +{ | ||
| 968 | + tree op = gimple_op (stmt, opnr); | ||
| 969 | + | ||
| 970 | + if (TREE_CODE (op) == SSA_NAME) | ||
| 971 | + { | ||
| 972 | + prop_value_t *val = get_value (op); | ||
| 973 | + if (val->lattice_val == CONSTANT) | ||
| 974 | + op = get_value (op)->value; | ||
| 975 | + } | ||
| 976 | + return op; | ||
| 977 | +} | ||
| 978 | + | ||
| 979 | /* CCP specific front-end to the non-destructive constant folding | ||
| 980 | routines. | ||
| 981 | |||
| 982 | @@ -1037,15 +1054,7 @@ | ||
| 983 | Note that we know the single operand must be a constant, | ||
| 984 | so this should almost always return a simplified RHS. */ | ||
| 985 | tree lhs = gimple_assign_lhs (stmt); | ||
| 986 | - tree op0 = gimple_assign_rhs1 (stmt); | ||
| 987 | - | ||
| 988 | - /* Simplify the operand down to a constant. */ | ||
| 989 | - if (TREE_CODE (op0) == SSA_NAME) | ||
| 990 | - { | ||
| 991 | - prop_value_t *val = get_value (op0); | ||
| 992 | - if (val->lattice_val == CONSTANT) | ||
| 993 | - op0 = get_value (op0)->value; | ||
| 994 | - } | ||
| 995 | + tree op0 = get_rhs_assign_op_for_ccp (stmt, 1); | ||
| 996 | |||
| 997 | /* Conversions are useless for CCP purposes if they are | ||
| 998 | value-preserving. Thus the restrictions that | ||
| 999 | @@ -1082,23 +1091,8 @@ | ||
| 1000 | case GIMPLE_BINARY_RHS: | ||
| 1001 | { | ||
| 1002 | /* Handle binary operators that can appear in GIMPLE form. */ | ||
| 1003 | - tree op0 = gimple_assign_rhs1 (stmt); | ||
| 1004 | - tree op1 = gimple_assign_rhs2 (stmt); | ||
| 1005 | - | ||
| 1006 | - /* Simplify the operands down to constants when appropriate. */ | ||
| 1007 | - if (TREE_CODE (op0) == SSA_NAME) | ||
| 1008 | - { | ||
| 1009 | - prop_value_t *val = get_value (op0); | ||
| 1010 | - if (val->lattice_val == CONSTANT) | ||
| 1011 | - op0 = val->value; | ||
| 1012 | - } | ||
| 1013 | - | ||
| 1014 | - if (TREE_CODE (op1) == SSA_NAME) | ||
| 1015 | - { | ||
| 1016 | - prop_value_t *val = get_value (op1); | ||
| 1017 | - if (val->lattice_val == CONSTANT) | ||
| 1018 | - op1 = val->value; | ||
| 1019 | - } | ||
| 1020 | + tree op0 = get_rhs_assign_op_for_ccp (stmt, 1); | ||
| 1021 | + tree op1 = get_rhs_assign_op_for_ccp (stmt, 2); | ||
| 1022 | |||
| 1023 | /* Fold &foo + CST into an invariant reference if possible. */ | ||
| 1024 | if (gimple_assign_rhs_code (stmt) == POINTER_PLUS_EXPR | ||
| 1025 | @@ -1115,6 +1109,17 @@ | ||
| 1026 | gimple_expr_type (stmt), op0, op1); | ||
| 1027 | } | ||
| 1028 | |||
| 1029 | + case GIMPLE_TERNARY_RHS: | ||
| 1030 | + { | ||
| 1031 | + /* Handle binary operators that can appear in GIMPLE form. */ | ||
| 1032 | + tree op0 = get_rhs_assign_op_for_ccp (stmt, 1); | ||
| 1033 | + tree op1 = get_rhs_assign_op_for_ccp (stmt, 2); | ||
| 1034 | + tree op2 = get_rhs_assign_op_for_ccp (stmt, 3); | ||
| 1035 | + | ||
| 1036 | + return fold_ternary_loc (loc, subcode, | ||
| 1037 | + gimple_expr_type (stmt), op0, op1, op2); | ||
| 1038 | + } | ||
| 1039 | + | ||
| 1040 | default: | ||
| 1041 | gcc_unreachable (); | ||
| 1042 | } | ||
| 1043 | @@ -2959,6 +2964,33 @@ | ||
| 1044 | } | ||
| 1045 | break; | ||
| 1046 | |||
| 1047 | + case GIMPLE_TERNARY_RHS: | ||
| 1048 | + result = fold_ternary_loc (loc, subcode, | ||
| 1049 | + TREE_TYPE (gimple_assign_lhs (stmt)), | ||
| 1050 | + gimple_assign_rhs1 (stmt), | ||
| 1051 | + gimple_assign_rhs2 (stmt), | ||
| 1052 | + gimple_assign_rhs3 (stmt)); | ||
| 1053 | + | ||
| 1054 | + if (result) | ||
| 1055 | + { | ||
| 1056 | + STRIP_USELESS_TYPE_CONVERSION (result); | ||
| 1057 | + if (valid_gimple_rhs_p (result)) | ||
| 1058 | + return result; | ||
| 1059 | + | ||
| 1060 | + /* Fold might have produced non-GIMPLE, so if we trust it blindly | ||
| 1061 | + we lose canonicalization opportunities. Do not go again | ||
| 1062 | + through fold here though, or the same non-GIMPLE will be | ||
| 1063 | + produced. */ | ||
| 1064 | + if (commutative_ternary_tree_code (subcode) | ||
| 1065 | + && tree_swap_operands_p (gimple_assign_rhs1 (stmt), | ||
| 1066 | + gimple_assign_rhs2 (stmt), false)) | ||
| 1067 | + return build3 (subcode, TREE_TYPE (gimple_assign_lhs (stmt)), | ||
| 1068 | + gimple_assign_rhs2 (stmt), | ||
| 1069 | + gimple_assign_rhs1 (stmt), | ||
| 1070 | + gimple_assign_rhs3 (stmt)); | ||
| 1071 | + } | ||
| 1072 | + break; | ||
| 1073 | + | ||
| 1074 | case GIMPLE_INVALID_RHS: | ||
| 1075 | gcc_unreachable (); | ||
| 1076 | } | ||
| 1077 | Index: gcc-4_5-branch/gcc/tree-ssa-dom.c | ||
| 1078 | =================================================================== | ||
| 1079 | --- gcc-4_5-branch.orig/gcc/tree-ssa-dom.c 2011-07-22 16:58:48.000000000 -0700 | ||
| 1080 | +++ gcc-4_5-branch/gcc/tree-ssa-dom.c 2011-07-22 17:23:51.501747355 -0700 | ||
| 1081 | @@ -54,6 +54,7 @@ | ||
| 1082 | EXPR_SINGLE, | ||
| 1083 | EXPR_UNARY, | ||
| 1084 | EXPR_BINARY, | ||
| 1085 | + EXPR_TERNARY, | ||
| 1086 | EXPR_CALL | ||
| 1087 | }; | ||
| 1088 | |||
| 1089 | @@ -64,7 +65,8 @@ | ||
| 1090 | union { | ||
| 1091 | struct { tree rhs; } single; | ||
| 1092 | struct { enum tree_code op; tree opnd; } unary; | ||
| 1093 | - struct { enum tree_code op; tree opnd0; tree opnd1; } binary; | ||
| 1094 | + struct { enum tree_code op; tree opnd0, opnd1; } binary; | ||
| 1095 | + struct { enum tree_code op; tree opnd0, opnd1, opnd2; } ternary; | ||
| 1096 | struct { tree fn; bool pure; size_t nargs; tree *args; } call; | ||
| 1097 | } ops; | ||
| 1098 | }; | ||
| 1099 | @@ -229,6 +231,14 @@ | ||
| 1100 | expr->ops.binary.opnd0 = gimple_assign_rhs1 (stmt); | ||
| 1101 | expr->ops.binary.opnd1 = gimple_assign_rhs2 (stmt); | ||
| 1102 | break; | ||
| 1103 | + case GIMPLE_TERNARY_RHS: | ||
| 1104 | + expr->kind = EXPR_TERNARY; | ||
| 1105 | + expr->type = TREE_TYPE (gimple_assign_lhs (stmt)); | ||
| 1106 | + expr->ops.ternary.op = subcode; | ||
| 1107 | + expr->ops.ternary.opnd0 = gimple_assign_rhs1 (stmt); | ||
| 1108 | + expr->ops.ternary.opnd1 = gimple_assign_rhs2 (stmt); | ||
| 1109 | + expr->ops.ternary.opnd2 = gimple_assign_rhs3 (stmt); | ||
| 1110 | + break; | ||
| 1111 | default: | ||
| 1112 | gcc_unreachable (); | ||
| 1113 | } | ||
| 1114 | @@ -373,23 +383,40 @@ | ||
| 1115 | expr1->ops.unary.opnd, 0); | ||
| 1116 | |||
| 1117 | case EXPR_BINARY: | ||
| 1118 | - { | ||
| 1119 | - if (expr0->ops.binary.op != expr1->ops.binary.op) | ||
| 1120 | - return false; | ||
| 1121 | + if (expr0->ops.binary.op != expr1->ops.binary.op) | ||
| 1122 | + return false; | ||
| 1123 | |||
| 1124 | - if (operand_equal_p (expr0->ops.binary.opnd0, | ||
| 1125 | - expr1->ops.binary.opnd0, 0) | ||
| 1126 | - && operand_equal_p (expr0->ops.binary.opnd1, | ||
| 1127 | - expr1->ops.binary.opnd1, 0)) | ||
| 1128 | - return true; | ||
| 1129 | - | ||
| 1130 | - /* For commutative ops, allow the other order. */ | ||
| 1131 | - return (commutative_tree_code (expr0->ops.binary.op) | ||
| 1132 | - && operand_equal_p (expr0->ops.binary.opnd0, | ||
| 1133 | - expr1->ops.binary.opnd1, 0) | ||
| 1134 | - && operand_equal_p (expr0->ops.binary.opnd1, | ||
| 1135 | - expr1->ops.binary.opnd0, 0)); | ||
| 1136 | - } | ||
| 1137 | + if (operand_equal_p (expr0->ops.binary.opnd0, | ||
| 1138 | + expr1->ops.binary.opnd0, 0) | ||
| 1139 | + && operand_equal_p (expr0->ops.binary.opnd1, | ||
| 1140 | + expr1->ops.binary.opnd1, 0)) | ||
| 1141 | + return true; | ||
| 1142 | + | ||
| 1143 | + /* For commutative ops, allow the other order. */ | ||
| 1144 | + return (commutative_tree_code (expr0->ops.binary.op) | ||
| 1145 | + && operand_equal_p (expr0->ops.binary.opnd0, | ||
| 1146 | + expr1->ops.binary.opnd1, 0) | ||
| 1147 | + && operand_equal_p (expr0->ops.binary.opnd1, | ||
| 1148 | + expr1->ops.binary.opnd0, 0)); | ||
| 1149 | + | ||
| 1150 | + case EXPR_TERNARY: | ||
| 1151 | + if (expr0->ops.ternary.op != expr1->ops.ternary.op | ||
| 1152 | + || !operand_equal_p (expr0->ops.ternary.opnd2, | ||
| 1153 | + expr1->ops.ternary.opnd2, 0)) | ||
| 1154 | + return false; | ||
| 1155 | + | ||
| 1156 | + if (operand_equal_p (expr0->ops.ternary.opnd0, | ||
| 1157 | + expr1->ops.ternary.opnd0, 0) | ||
| 1158 | + && operand_equal_p (expr0->ops.ternary.opnd1, | ||
| 1159 | + expr1->ops.ternary.opnd1, 0)) | ||
| 1160 | + return true; | ||
| 1161 | + | ||
| 1162 | + /* For commutative ops, allow the other order. */ | ||
| 1163 | + return (commutative_ternary_tree_code (expr0->ops.ternary.op) | ||
| 1164 | + && operand_equal_p (expr0->ops.ternary.opnd0, | ||
| 1165 | + expr1->ops.ternary.opnd1, 0) | ||
| 1166 | + && operand_equal_p (expr0->ops.ternary.opnd1, | ||
| 1167 | + expr1->ops.ternary.opnd0, 0)); | ||
| 1168 | |||
| 1169 | case EXPR_CALL: | ||
| 1170 | { | ||
| 1171 | @@ -452,8 +479,8 @@ | ||
| 1172 | case EXPR_BINARY: | ||
| 1173 | val = iterative_hash_object (expr->ops.binary.op, val); | ||
| 1174 | if (commutative_tree_code (expr->ops.binary.op)) | ||
| 1175 | - val = iterative_hash_exprs_commutative (expr->ops.binary.opnd0, | ||
| 1176 | - expr->ops.binary.opnd1, val); | ||
| 1177 | + val = iterative_hash_exprs_commutative (expr->ops.binary.opnd0, | ||
| 1178 | + expr->ops.binary.opnd1, val); | ||
| 1179 | else | ||
| 1180 | { | ||
| 1181 | val = iterative_hash_expr (expr->ops.binary.opnd0, val); | ||
| 1182 | @@ -461,6 +488,19 @@ | ||
| 1183 | } | ||
| 1184 | break; | ||
| 1185 | |||
| 1186 | + case EXPR_TERNARY: | ||
| 1187 | + val = iterative_hash_object (expr->ops.ternary.op, val); | ||
| 1188 | + if (commutative_ternary_tree_code (expr->ops.ternary.op)) | ||
| 1189 | + val = iterative_hash_exprs_commutative (expr->ops.ternary.opnd0, | ||
| 1190 | + expr->ops.ternary.opnd1, val); | ||
| 1191 | + else | ||
| 1192 | + { | ||
| 1193 | + val = iterative_hash_expr (expr->ops.ternary.opnd0, val); | ||
| 1194 | + val = iterative_hash_expr (expr->ops.ternary.opnd1, val); | ||
| 1195 | + } | ||
| 1196 | + val = iterative_hash_expr (expr->ops.ternary.opnd2, val); | ||
| 1197 | + break; | ||
| 1198 | + | ||
| 1199 | case EXPR_CALL: | ||
| 1200 | { | ||
| 1201 | size_t i; | ||
| 1202 | @@ -513,6 +553,16 @@ | ||
| 1203 | print_generic_expr (stream, element->expr.ops.binary.opnd1, 0); | ||
| 1204 | break; | ||
| 1205 | |||
| 1206 | + case EXPR_TERNARY: | ||
| 1207 | + fprintf (stream, " %s <", tree_code_name[element->expr.ops.ternary.op]); | ||
| 1208 | + print_generic_expr (stream, element->expr.ops.ternary.opnd0, 0); | ||
| 1209 | + fputs (", ", stream); | ||
| 1210 | + print_generic_expr (stream, element->expr.ops.ternary.opnd1, 0); | ||
| 1211 | + fputs (", ", stream); | ||
| 1212 | + print_generic_expr (stream, element->expr.ops.ternary.opnd2, 0); | ||
| 1213 | + fputs (">", stream); | ||
| 1214 | + break; | ||
| 1215 | + | ||
| 1216 | case EXPR_CALL: | ||
| 1217 | { | ||
| 1218 | size_t i; | ||
| 1219 | Index: gcc-4_5-branch/gcc/tree-ssa-math-opts.c | ||
| 1220 | =================================================================== | ||
| 1221 | --- gcc-4_5-branch.orig/gcc/tree-ssa-math-opts.c 2011-07-22 16:59:24.000000000 -0700 | ||
| 1222 | +++ gcc-4_5-branch/gcc/tree-ssa-math-opts.c 2011-07-22 16:59:28.611747691 -0700 | ||
| 1223 | @@ -1270,6 +1270,235 @@ | ||
| 1224 | } | ||
| 1225 | }; | ||
| 1226 | |||
| 1227 | +/* Return true if RHS is a suitable operand for a widening multiplication. | ||
| 1228 | + There are two cases: | ||
| 1229 | + | ||
| 1230 | + - RHS makes some value twice as wide. Store that value in *NEW_RHS_OUT | ||
| 1231 | + if so, and store its type in *TYPE_OUT. | ||
| 1232 | + | ||
| 1233 | + - RHS is an integer constant. Store that value in *NEW_RHS_OUT if so, | ||
| 1234 | + but leave *TYPE_OUT untouched. */ | ||
| 1235 | + | ||
| 1236 | +static bool | ||
| 1237 | +is_widening_mult_rhs_p (tree rhs, tree *type_out, tree *new_rhs_out) | ||
| 1238 | +{ | ||
| 1239 | + gimple stmt; | ||
| 1240 | + tree type, type1, rhs1; | ||
| 1241 | + enum tree_code rhs_code; | ||
| 1242 | + | ||
| 1243 | + if (TREE_CODE (rhs) == SSA_NAME) | ||
| 1244 | + { | ||
| 1245 | + type = TREE_TYPE (rhs); | ||
| 1246 | + stmt = SSA_NAME_DEF_STMT (rhs); | ||
| 1247 | + if (!is_gimple_assign (stmt)) | ||
| 1248 | + return false; | ||
| 1249 | + | ||
| 1250 | + rhs_code = gimple_assign_rhs_code (stmt); | ||
| 1251 | + if (TREE_CODE (type) == INTEGER_TYPE | ||
| 1252 | + ? !CONVERT_EXPR_CODE_P (rhs_code) | ||
| 1253 | + : rhs_code != FIXED_CONVERT_EXPR) | ||
| 1254 | + return false; | ||
| 1255 | + | ||
| 1256 | + rhs1 = gimple_assign_rhs1 (stmt); | ||
| 1257 | + type1 = TREE_TYPE (rhs1); | ||
| 1258 | + if (TREE_CODE (type1) != TREE_CODE (type) | ||
| 1259 | + || TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type)) | ||
| 1260 | + return false; | ||
| 1261 | + | ||
| 1262 | + *new_rhs_out = rhs1; | ||
| 1263 | + *type_out = type1; | ||
| 1264 | + return true; | ||
| 1265 | + } | ||
| 1266 | + | ||
| 1267 | + if (TREE_CODE (rhs) == INTEGER_CST) | ||
| 1268 | + { | ||
| 1269 | + *new_rhs_out = rhs; | ||
| 1270 | + *type_out = NULL; | ||
| 1271 | + return true; | ||
| 1272 | + } | ||
| 1273 | + | ||
| 1274 | + return false; | ||
| 1275 | +} | ||
| 1276 | + | ||
| 1277 | +/* Return true if STMT performs a widening multiplication. If so, | ||
| 1278 | + store the unwidened types of the operands in *TYPE1_OUT and *TYPE2_OUT | ||
| 1279 | + respectively. Also fill *RHS1_OUT and *RHS2_OUT such that converting | ||
| 1280 | + those operands to types *TYPE1_OUT and *TYPE2_OUT would give the | ||
| 1281 | + operands of the multiplication. */ | ||
| 1282 | + | ||
| 1283 | +static bool | ||
| 1284 | +is_widening_mult_p (gimple stmt, | ||
| 1285 | + tree *type1_out, tree *rhs1_out, | ||
| 1286 | + tree *type2_out, tree *rhs2_out) | ||
| 1287 | +{ | ||
| 1288 | + tree type; | ||
| 1289 | + | ||
| 1290 | + type = TREE_TYPE (gimple_assign_lhs (stmt)); | ||
| 1291 | + if (TREE_CODE (type) != INTEGER_TYPE | ||
| 1292 | + && TREE_CODE (type) != FIXED_POINT_TYPE) | ||
| 1293 | + return false; | ||
| 1294 | + | ||
| 1295 | + if (!is_widening_mult_rhs_p (gimple_assign_rhs1 (stmt), type1_out, rhs1_out)) | ||
| 1296 | + return false; | ||
| 1297 | + | ||
| 1298 | + if (!is_widening_mult_rhs_p (gimple_assign_rhs2 (stmt), type2_out, rhs2_out)) | ||
| 1299 | + return false; | ||
| 1300 | + | ||
| 1301 | + if (*type1_out == NULL) | ||
| 1302 | + { | ||
| 1303 | + if (*type2_out == NULL || !int_fits_type_p (*rhs1_out, *type2_out)) | ||
| 1304 | + return false; | ||
| 1305 | + *type1_out = *type2_out; | ||
| 1306 | + } | ||
| 1307 | + | ||
| 1308 | + if (*type2_out == NULL) | ||
| 1309 | + { | ||
| 1310 | + if (!int_fits_type_p (*rhs2_out, *type1_out)) | ||
| 1311 | + return false; | ||
| 1312 | + *type2_out = *type1_out; | ||
| 1313 | + } | ||
| 1314 | + | ||
| 1315 | + return true; | ||
| 1316 | +} | ||
| 1317 | + | ||
| 1318 | +/* Process a single gimple statement STMT, which has a MULT_EXPR as | ||
| 1319 | + its rhs, and try to convert it into a WIDEN_MULT_EXPR. The return | ||
| 1320 | + value is true iff we converted the statement. */ | ||
| 1321 | + | ||
| 1322 | +static bool | ||
| 1323 | +convert_mult_to_widen (gimple stmt) | ||
| 1324 | +{ | ||
| 1325 | + tree lhs, rhs1, rhs2, type, type1, type2; | ||
| 1326 | + enum insn_code handler; | ||
| 1327 | + | ||
| 1328 | + lhs = gimple_assign_lhs (stmt); | ||
| 1329 | + type = TREE_TYPE (lhs); | ||
| 1330 | + if (TREE_CODE (type) != INTEGER_TYPE) | ||
| 1331 | + return false; | ||
| 1332 | + | ||
| 1333 | + if (!is_widening_mult_p (stmt, &type1, &rhs1, &type2, &rhs2)) | ||
| 1334 | + return false; | ||
| 1335 | + | ||
| 1336 | + if (TYPE_UNSIGNED (type1) && TYPE_UNSIGNED (type2)) | ||
| 1337 | + handler = optab_handler (umul_widen_optab, TYPE_MODE (type))->insn_code; | ||
| 1338 | + else if (!TYPE_UNSIGNED (type1) && !TYPE_UNSIGNED (type2)) | ||
| 1339 | + handler = optab_handler (smul_widen_optab, TYPE_MODE (type))->insn_code; | ||
| 1340 | + else | ||
| 1341 | + handler = optab_handler (usmul_widen_optab, TYPE_MODE (type))->insn_code; | ||
| 1342 | + | ||
| 1343 | + if (handler == CODE_FOR_nothing) | ||
| 1344 | + return false; | ||
| 1345 | + | ||
| 1346 | + gimple_assign_set_rhs1 (stmt, fold_convert (type1, rhs1)); | ||
| 1347 | + gimple_assign_set_rhs2 (stmt, fold_convert (type2, rhs2)); | ||
| 1348 | + gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR); | ||
| 1349 | + update_stmt (stmt); | ||
| 1350 | + return true; | ||
| 1351 | +} | ||
| 1352 | + | ||
| 1353 | +/* Process a single gimple statement STMT, which is found at the | ||
| 1354 | + iterator GSI and has a either a PLUS_EXPR or a MINUS_EXPR as its | ||
| 1355 | + rhs (given by CODE), and try to convert it into a | ||
| 1356 | + WIDEN_MULT_PLUS_EXPR or a WIDEN_MULT_MINUS_EXPR. The return value | ||
| 1357 | + is true iff we converted the statement. */ | ||
| 1358 | + | ||
| 1359 | +static bool | ||
| 1360 | +convert_plusminus_to_widen (gimple_stmt_iterator *gsi, gimple stmt, | ||
| 1361 | + enum tree_code code) | ||
| 1362 | +{ | ||
| 1363 | + gimple rhs1_stmt = NULL, rhs2_stmt = NULL; | ||
| 1364 | + tree type, type1, type2; | ||
| 1365 | + tree lhs, rhs1, rhs2, mult_rhs1, mult_rhs2, add_rhs; | ||
| 1366 | + enum tree_code rhs1_code = ERROR_MARK, rhs2_code = ERROR_MARK; | ||
| 1367 | + optab this_optab; | ||
| 1368 | + enum tree_code wmult_code; | ||
| 1369 | + | ||
| 1370 | + lhs = gimple_assign_lhs (stmt); | ||
| 1371 | + type = TREE_TYPE (lhs); | ||
| 1372 | + if (TREE_CODE (type) != INTEGER_TYPE | ||
| 1373 | + && TREE_CODE (type) != FIXED_POINT_TYPE) | ||
| 1374 | + return false; | ||
| 1375 | + | ||
| 1376 | + if (code == MINUS_EXPR) | ||
| 1377 | + wmult_code = WIDEN_MULT_MINUS_EXPR; | ||
| 1378 | + else | ||
| 1379 | + wmult_code = WIDEN_MULT_PLUS_EXPR; | ||
| 1380 | + | ||
| 1381 | + rhs1 = gimple_assign_rhs1 (stmt); | ||
| 1382 | + rhs2 = gimple_assign_rhs2 (stmt); | ||
| 1383 | + | ||
| 1384 | + if (TREE_CODE (rhs1) == SSA_NAME) | ||
| 1385 | + { | ||
| 1386 | + rhs1_stmt = SSA_NAME_DEF_STMT (rhs1); | ||
| 1387 | + if (is_gimple_assign (rhs1_stmt)) | ||
| 1388 | + rhs1_code = gimple_assign_rhs_code (rhs1_stmt); | ||
| 1389 | + } | ||
| 1390 | + else | ||
| 1391 | + return false; | ||
| 1392 | + | ||
| 1393 | + if (TREE_CODE (rhs2) == SSA_NAME) | ||
| 1394 | + { | ||
| 1395 | + rhs2_stmt = SSA_NAME_DEF_STMT (rhs2); | ||
| 1396 | + if (is_gimple_assign (rhs2_stmt)) | ||
| 1397 | + rhs2_code = gimple_assign_rhs_code (rhs2_stmt); | ||
| 1398 | + } | ||
| 1399 | + else | ||
| 1400 | + return false; | ||
| 1401 | + | ||
| 1402 | + if (code == PLUS_EXPR && rhs1_code == MULT_EXPR) | ||
| 1403 | + { | ||
| 1404 | + if (!is_widening_mult_p (rhs1_stmt, &type1, &mult_rhs1, | ||
| 1405 | + &type2, &mult_rhs2)) | ||
| 1406 | + return false; | ||
| 1407 | + add_rhs = rhs2; | ||
| 1408 | + } | ||
| 1409 | + else if (rhs2_code == MULT_EXPR) | ||
| 1410 | + { | ||
| 1411 | + if (!is_widening_mult_p (rhs2_stmt, &type1, &mult_rhs1, | ||
| 1412 | + &type2, &mult_rhs2)) | ||
| 1413 | + return false; | ||
| 1414 | + add_rhs = rhs1; | ||
| 1415 | + } | ||
| 1416 | + else if (code == PLUS_EXPR && rhs1_code == WIDEN_MULT_EXPR) | ||
| 1417 | + { | ||
| 1418 | + mult_rhs1 = gimple_assign_rhs1 (rhs1_stmt); | ||
| 1419 | + mult_rhs2 = gimple_assign_rhs2 (rhs1_stmt); | ||
| 1420 | + type1 = TREE_TYPE (mult_rhs1); | ||
| 1421 | + type2 = TREE_TYPE (mult_rhs2); | ||
| 1422 | + add_rhs = rhs2; | ||
| 1423 | + } | ||
| 1424 | + else if (rhs2_code == WIDEN_MULT_EXPR) | ||
| 1425 | + { | ||
| 1426 | + mult_rhs1 = gimple_assign_rhs1 (rhs2_stmt); | ||
| 1427 | + mult_rhs2 = gimple_assign_rhs2 (rhs2_stmt); | ||
| 1428 | + type1 = TREE_TYPE (mult_rhs1); | ||
| 1429 | + type2 = TREE_TYPE (mult_rhs2); | ||
| 1430 | + add_rhs = rhs1; | ||
| 1431 | + } | ||
| 1432 | + else | ||
| 1433 | + return false; | ||
| 1434 | + | ||
| 1435 | + if (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2)) | ||
| 1436 | + return false; | ||
| 1437 | + | ||
| 1438 | + /* Verify that the machine can perform a widening multiply | ||
| 1439 | + accumulate in this mode/signedness combination, otherwise | ||
| 1440 | + this transformation is likely to pessimize code. */ | ||
| 1441 | + this_optab = optab_for_tree_code (wmult_code, type1, optab_default); | ||
| 1442 | + if (optab_handler (this_optab, TYPE_MODE (type))->insn_code | ||
| 1443 | + == CODE_FOR_nothing) | ||
| 1444 | + return false; | ||
| 1445 | + | ||
| 1446 | + /* ??? May need some type verification here? */ | ||
| 1447 | + | ||
| 1448 | + gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code, | ||
| 1449 | + fold_convert (type1, mult_rhs1), | ||
| 1450 | + fold_convert (type2, mult_rhs2), | ||
| 1451 | + add_rhs); | ||
| 1452 | + update_stmt (gsi_stmt (*gsi)); | ||
| 1453 | + return true; | ||
| 1454 | +} | ||
| 1455 | + | ||
| 1456 | /* Find integer multiplications where the operands are extended from | ||
| 1457 | smaller types, and replace the MULT_EXPR with a WIDEN_MULT_EXPR | ||
| 1458 | where appropriate. */ | ||
| 1459 | @@ -1287,94 +1516,19 @@ | ||
| 1460 | for (gsi = gsi_after_labels (bb); !gsi_end_p (gsi); gsi_next (&gsi)) | ||
| 1461 | { | ||
| 1462 | gimple stmt = gsi_stmt (gsi); | ||
| 1463 | - gimple rhs1_stmt = NULL, rhs2_stmt = NULL; | ||
| 1464 | - tree type, type1 = NULL, type2 = NULL; | ||
| 1465 | - tree rhs1, rhs2, rhs1_convop = NULL, rhs2_convop = NULL; | ||
| 1466 | - enum tree_code rhs1_code, rhs2_code; | ||
| 1467 | + enum tree_code code; | ||
| 1468 | |||
| 1469 | - if (!is_gimple_assign (stmt) | ||
| 1470 | - || gimple_assign_rhs_code (stmt) != MULT_EXPR) | ||
| 1471 | + if (!is_gimple_assign (stmt)) | ||
| 1472 | continue; | ||
| 1473 | |||
| 1474 | - type = TREE_TYPE (gimple_assign_lhs (stmt)); | ||
| 1475 | - | ||
| 1476 | - if (TREE_CODE (type) != INTEGER_TYPE) | ||
| 1477 | - continue; | ||
| 1478 | - | ||
| 1479 | - rhs1 = gimple_assign_rhs1 (stmt); | ||
| 1480 | - rhs2 = gimple_assign_rhs2 (stmt); | ||
| 1481 | - | ||
| 1482 | - if (TREE_CODE (rhs1) == SSA_NAME) | ||
| 1483 | - { | ||
| 1484 | - rhs1_stmt = SSA_NAME_DEF_STMT (rhs1); | ||
| 1485 | - if (!is_gimple_assign (rhs1_stmt)) | ||
| 1486 | - continue; | ||
| 1487 | - rhs1_code = gimple_assign_rhs_code (rhs1_stmt); | ||
| 1488 | - if (!CONVERT_EXPR_CODE_P (rhs1_code)) | ||
| 1489 | - continue; | ||
| 1490 | - rhs1_convop = gimple_assign_rhs1 (rhs1_stmt); | ||
| 1491 | - type1 = TREE_TYPE (rhs1_convop); | ||
| 1492 | - if (TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type)) | ||
| 1493 | - continue; | ||
| 1494 | - } | ||
| 1495 | - else if (TREE_CODE (rhs1) != INTEGER_CST) | ||
| 1496 | - continue; | ||
| 1497 | - | ||
| 1498 | - if (TREE_CODE (rhs2) == SSA_NAME) | ||
| 1499 | - { | ||
| 1500 | - rhs2_stmt = SSA_NAME_DEF_STMT (rhs2); | ||
| 1501 | - if (!is_gimple_assign (rhs2_stmt)) | ||
| 1502 | - continue; | ||
| 1503 | - rhs2_code = gimple_assign_rhs_code (rhs2_stmt); | ||
| 1504 | - if (!CONVERT_EXPR_CODE_P (rhs2_code)) | ||
| 1505 | - continue; | ||
| 1506 | - rhs2_convop = gimple_assign_rhs1 (rhs2_stmt); | ||
| 1507 | - type2 = TREE_TYPE (rhs2_convop); | ||
| 1508 | - if (TYPE_PRECISION (type2) * 2 != TYPE_PRECISION (type)) | ||
| 1509 | - continue; | ||
| 1510 | - } | ||
| 1511 | - else if (TREE_CODE (rhs2) != INTEGER_CST) | ||
| 1512 | - continue; | ||
| 1513 | - | ||
| 1514 | - if (rhs1_stmt == NULL && rhs2_stmt == NULL) | ||
| 1515 | - continue; | ||
| 1516 | - | ||
| 1517 | - /* Verify that the machine can perform a widening multiply in this | ||
| 1518 | - mode/signedness combination, otherwise this transformation is | ||
| 1519 | - likely to pessimize code. */ | ||
| 1520 | - if ((rhs1_stmt == NULL || TYPE_UNSIGNED (type1)) | ||
| 1521 | - && (rhs2_stmt == NULL || TYPE_UNSIGNED (type2)) | ||
| 1522 | - && (optab_handler (umul_widen_optab, TYPE_MODE (type)) | ||
| 1523 | - ->insn_code == CODE_FOR_nothing)) | ||
| 1524 | - continue; | ||
| 1525 | - else if ((rhs1_stmt == NULL || !TYPE_UNSIGNED (type1)) | ||
| 1526 | - && (rhs2_stmt == NULL || !TYPE_UNSIGNED (type2)) | ||
| 1527 | - && (optab_handler (smul_widen_optab, TYPE_MODE (type)) | ||
| 1528 | - ->insn_code == CODE_FOR_nothing)) | ||
| 1529 | - continue; | ||
| 1530 | - else if (rhs1_stmt != NULL && rhs2_stmt != 0 | ||
| 1531 | - && (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2)) | ||
| 1532 | - && (optab_handler (usmul_widen_optab, TYPE_MODE (type)) | ||
| 1533 | - ->insn_code == CODE_FOR_nothing)) | ||
| 1534 | - continue; | ||
| 1535 | - | ||
| 1536 | - if ((rhs1_stmt == NULL && !int_fits_type_p (rhs1, type2)) | ||
| 1537 | - || (rhs2_stmt == NULL && !int_fits_type_p (rhs2, type1))) | ||
| 1538 | - continue; | ||
| 1539 | - | ||
| 1540 | - if (rhs1_stmt == NULL) | ||
| 1541 | - gimple_assign_set_rhs1 (stmt, fold_convert (type2, rhs1)); | ||
| 1542 | - else | ||
| 1543 | - gimple_assign_set_rhs1 (stmt, rhs1_convop); | ||
| 1544 | - if (rhs2_stmt == NULL) | ||
| 1545 | - gimple_assign_set_rhs2 (stmt, fold_convert (type1, rhs2)); | ||
| 1546 | - else | ||
| 1547 | - gimple_assign_set_rhs2 (stmt, rhs2_convop); | ||
| 1548 | - gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR); | ||
| 1549 | - update_stmt (stmt); | ||
| 1550 | - changed = true; | ||
| 1551 | + code = gimple_assign_rhs_code (stmt); | ||
| 1552 | + if (code == MULT_EXPR) | ||
| 1553 | + changed |= convert_mult_to_widen (stmt); | ||
| 1554 | + else if (code == PLUS_EXPR || code == MINUS_EXPR) | ||
| 1555 | + changed |= convert_plusminus_to_widen (&gsi, stmt, code); | ||
| 1556 | } | ||
| 1557 | } | ||
| 1558 | + | ||
| 1559 | return (changed ? TODO_dump_func | TODO_update_ssa | TODO_verify_ssa | ||
| 1560 | | TODO_verify_stmts : 0); | ||
| 1561 | } | ||
| 1562 | Index: gcc-4_5-branch/gcc/tree-ssa-operands.c | ||
| 1563 | =================================================================== | ||
| 1564 | --- gcc-4_5-branch.orig/gcc/tree-ssa-operands.c 2011-07-22 16:58:48.000000000 -0700 | ||
| 1565 | +++ gcc-4_5-branch/gcc/tree-ssa-operands.c 2011-07-22 16:59:28.611747691 -0700 | ||
| 1566 | @@ -994,11 +994,13 @@ | ||
| 1567 | |||
| 1568 | case DOT_PROD_EXPR: | ||
| 1569 | case REALIGN_LOAD_EXPR: | ||
| 1570 | + case WIDEN_MULT_PLUS_EXPR: | ||
| 1571 | + case WIDEN_MULT_MINUS_EXPR: | ||
| 1572 | { | ||
| 1573 | get_expr_operands (stmt, &TREE_OPERAND (expr, 0), flags); | ||
| 1574 | - get_expr_operands (stmt, &TREE_OPERAND (expr, 1), flags); | ||
| 1575 | - get_expr_operands (stmt, &TREE_OPERAND (expr, 2), flags); | ||
| 1576 | - return; | ||
| 1577 | + get_expr_operands (stmt, &TREE_OPERAND (expr, 1), flags); | ||
| 1578 | + get_expr_operands (stmt, &TREE_OPERAND (expr, 2), flags); | ||
| 1579 | + return; | ||
| 1580 | } | ||
| 1581 | |||
| 1582 | case FUNCTION_DECL: | ||
| 1583 | Index: gcc-4_5-branch/gcc/tree-ssa-sccvn.c | ||
| 1584 | =================================================================== | ||
| 1585 | --- gcc-4_5-branch.orig/gcc/tree-ssa-sccvn.c 2011-07-22 16:58:48.000000000 -0700 | ||
| 1586 | +++ gcc-4_5-branch/gcc/tree-ssa-sccvn.c 2011-07-22 16:59:28.611747691 -0700 | ||
| 1587 | @@ -2298,6 +2298,10 @@ | ||
| 1588 | case GIMPLE_BINARY_RHS: | ||
| 1589 | return (is_gimple_min_invariant (gimple_assign_rhs1 (stmt)) | ||
| 1590 | || is_gimple_min_invariant (gimple_assign_rhs2 (stmt))); | ||
| 1591 | + case GIMPLE_TERNARY_RHS: | ||
| 1592 | + return (is_gimple_min_invariant (gimple_assign_rhs1 (stmt)) | ||
| 1593 | + || is_gimple_min_invariant (gimple_assign_rhs2 (stmt)) | ||
| 1594 | + || is_gimple_min_invariant (gimple_assign_rhs3 (stmt))); | ||
| 1595 | case GIMPLE_SINGLE_RHS: | ||
| 1596 | /* Constants inside reference ops are rarely interesting, but | ||
| 1597 | it can take a lot of looking to find them. */ | ||
| 1598 | Index: gcc-4_5-branch/gcc/tree-ssa-threadedge.c | ||
| 1599 | =================================================================== | ||
| 1600 | --- gcc-4_5-branch.orig/gcc/tree-ssa-threadedge.c 2011-07-22 16:58:48.000000000 -0700 | ||
| 1601 | +++ gcc-4_5-branch/gcc/tree-ssa-threadedge.c 2011-07-22 16:59:28.611747691 -0700 | ||
| 1602 | @@ -247,14 +247,14 @@ | ||
| 1603 | |||
| 1604 | return fold (rhs); | ||
| 1605 | } | ||
| 1606 | - break; | ||
| 1607 | + | ||
| 1608 | case GIMPLE_UNARY_RHS: | ||
| 1609 | { | ||
| 1610 | tree lhs = gimple_assign_lhs (stmt); | ||
| 1611 | tree op0 = gimple_assign_rhs1 (stmt); | ||
| 1612 | return fold_unary (subcode, TREE_TYPE (lhs), op0); | ||
| 1613 | } | ||
| 1614 | - break; | ||
| 1615 | + | ||
| 1616 | case GIMPLE_BINARY_RHS: | ||
| 1617 | { | ||
| 1618 | tree lhs = gimple_assign_lhs (stmt); | ||
| 1619 | @@ -262,7 +262,16 @@ | ||
| 1620 | tree op1 = gimple_assign_rhs2 (stmt); | ||
| 1621 | return fold_binary (subcode, TREE_TYPE (lhs), op0, op1); | ||
| 1622 | } | ||
| 1623 | - break; | ||
| 1624 | + | ||
| 1625 | + case GIMPLE_TERNARY_RHS: | ||
| 1626 | + { | ||
| 1627 | + tree lhs = gimple_assign_lhs (stmt); | ||
| 1628 | + tree op0 = gimple_assign_rhs1 (stmt); | ||
| 1629 | + tree op1 = gimple_assign_rhs2 (stmt); | ||
| 1630 | + tree op2 = gimple_assign_rhs3 (stmt); | ||
| 1631 | + return fold_ternary (subcode, TREE_TYPE (lhs), op0, op1, op2); | ||
| 1632 | + } | ||
| 1633 | + | ||
| 1634 | default: | ||
| 1635 | gcc_unreachable (); | ||
| 1636 | } | ||
| 1637 | Index: gcc-4_5-branch/gcc/tree-vrp.c | ||
| 1638 | =================================================================== | ||
| 1639 | --- gcc-4_5-branch.orig/gcc/tree-vrp.c 2011-07-22 16:58:48.000000000 -0700 | ||
| 1640 | +++ gcc-4_5-branch/gcc/tree-vrp.c 2011-07-22 16:59:28.621747691 -0700 | ||
| 1641 | @@ -864,6 +864,8 @@ | ||
| 1642 | gimple_assign_rhs1 (stmt), | ||
| 1643 | gimple_assign_rhs2 (stmt), | ||
| 1644 | strict_overflow_p); | ||
| 1645 | + case GIMPLE_TERNARY_RHS: | ||
| 1646 | + return false; | ||
| 1647 | case GIMPLE_SINGLE_RHS: | ||
| 1648 | return tree_single_nonnegative_warnv_p (gimple_assign_rhs1 (stmt), | ||
| 1649 | strict_overflow_p); | ||
| 1650 | @@ -935,6 +937,8 @@ | ||
| 1651 | gimple_assign_rhs1 (stmt), | ||
| 1652 | gimple_assign_rhs2 (stmt), | ||
| 1653 | strict_overflow_p); | ||
| 1654 | + case GIMPLE_TERNARY_RHS: | ||
| 1655 | + return false; | ||
| 1656 | case GIMPLE_SINGLE_RHS: | ||
| 1657 | return tree_single_nonzero_warnv_p (gimple_assign_rhs1 (stmt), | ||
| 1658 | strict_overflow_p); | ||
| 1659 | Index: gcc-4_5-branch/gcc/tree.c | ||
| 1660 | =================================================================== | ||
| 1661 | --- gcc-4_5-branch.orig/gcc/tree.c 2011-07-22 16:59:13.000000000 -0700 | ||
| 1662 | +++ gcc-4_5-branch/gcc/tree.c 2011-07-22 16:59:28.621747691 -0700 | ||
| 1663 | @@ -6548,6 +6548,23 @@ | ||
| 1664 | return false; | ||
| 1665 | } | ||
| 1666 | |||
| 1667 | +/* Return true if CODE represents a ternary tree code for which the | ||
| 1668 | + first two operands are commutative. Otherwise return false. */ | ||
| 1669 | +bool | ||
| 1670 | +commutative_ternary_tree_code (enum tree_code code) | ||
| 1671 | +{ | ||
| 1672 | + switch (code) | ||
| 1673 | + { | ||
| 1674 | + case WIDEN_MULT_PLUS_EXPR: | ||
| 1675 | + case WIDEN_MULT_MINUS_EXPR: | ||
| 1676 | + return true; | ||
| 1677 | + | ||
| 1678 | + default: | ||
| 1679 | + break; | ||
| 1680 | + } | ||
| 1681 | + return false; | ||
| 1682 | +} | ||
| 1683 | + | ||
| 1684 | /* Generate a hash value for an expression. This can be used iteratively | ||
| 1685 | by passing a previous result as the VAL argument. | ||
| 1686 | |||
| 1687 | Index: gcc-4_5-branch/gcc/tree.def | ||
| 1688 | =================================================================== | ||
| 1689 | --- gcc-4_5-branch.orig/gcc/tree.def 2011-07-22 16:58:48.000000000 -0700 | ||
| 1690 | +++ gcc-4_5-branch/gcc/tree.def 2011-07-22 16:59:28.631747691 -0700 | ||
| 1691 | @@ -1083,6 +1083,18 @@ | ||
| 1692 | the arguments from type t1 to type t2, and then multiplying them. */ | ||
| 1693 | DEFTREECODE (WIDEN_MULT_EXPR, "widen_mult_expr", tcc_binary, 2) | ||
| 1694 | |||
| 1695 | +/* Widening multiply-accumulate. | ||
| 1696 | + The first two arguments are of type t1. | ||
| 1697 | + The third argument and the result are of type t2, such as t2 is at least | ||
| 1698 | + twice the size of t1. t1 and t2 must be integral or fixed-point types. | ||
| 1699 | + The expression is equivalent to a WIDEN_MULT_EXPR operation | ||
| 1700 | + of the first two operands followed by an add or subtract of the third | ||
| 1701 | + operand. */ | ||
| 1702 | +DEFTREECODE (WIDEN_MULT_PLUS_EXPR, "widen_mult_plus_expr", tcc_expression, 3) | ||
| 1703 | +/* This is like the above, except in the final expression the multiply result | ||
| 1704 | + is subtracted from t3. */ | ||
| 1705 | +DEFTREECODE (WIDEN_MULT_MINUS_EXPR, "widen_mult_plus_expr", tcc_expression, 3) | ||
| 1706 | + | ||
| 1707 | /* Whole vector left/right shift in bits. | ||
| 1708 | Operand 0 is a vector to be shifted. | ||
| 1709 | Operand 1 is an integer shift amount in bits. */ | ||
| 1710 | Index: gcc-4_5-branch/gcc/tree.h | ||
| 1711 | =================================================================== | ||
| 1712 | --- gcc-4_5-branch.orig/gcc/tree.h 2011-07-22 16:59:13.000000000 -0700 | ||
| 1713 | +++ gcc-4_5-branch/gcc/tree.h 2011-07-22 16:59:28.631747691 -0700 | ||
| 1714 | @@ -4687,6 +4687,7 @@ | ||
| 1715 | extern int type_num_arguments (const_tree); | ||
| 1716 | extern bool associative_tree_code (enum tree_code); | ||
| 1717 | extern bool commutative_tree_code (enum tree_code); | ||
| 1718 | +extern bool commutative_ternary_tree_code (enum tree_code); | ||
| 1719 | extern tree upper_bound_in_type (tree, tree); | ||
| 1720 | extern tree lower_bound_in_type (tree, tree); | ||
| 1721 | extern int operand_equal_for_phi_arg_p (const_tree, const_tree); | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch deleted file mode 100644 index e795d54e0..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99397.patch +++ /dev/null | |||
| @@ -1,3565 +0,0 @@ | |||
| 1 | 2010-09-16 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from FSF: | ||
| 4 | |||
| 5 | 2010-09-01 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | ||
| 6 | |||
| 7 | * config/arm/neon-schedgen.ml (core): New type. | ||
| 8 | (allCores): List of supported cores. | ||
| 9 | (availability_table): Add supported cores. | ||
| 10 | (collate_bypasses): Accept core as a parameter. | ||
| 11 | (worst_case_latencies_and_bypasses): Accept core as a | ||
| 12 | parameter. | ||
| 13 | (emit_insn_reservations): Accept core as a parameter. | ||
| 14 | Use tuneStr and coreStr to get tune attribute and prefix | ||
| 15 | for functional units. | ||
| 16 | (emit_bypasses): Accept core name and use it. | ||
| 17 | (calculate_per_core_availability_table): New. | ||
| 18 | (filter_core): New. | ||
| 19 | (calculate_core_availability_table): New. | ||
| 20 | (main): Use calculate_core_availablity_table. | ||
| 21 | * config/arm/cortex-a8-neon.md: Update copyright year. | ||
| 22 | Regenerated from ml file and merged in. | ||
| 23 | (neon_mrrc, neon_mrc): Rename to cortex_a8_neon_mrrc and | ||
| 24 | cortex_a8_neon_mrc. | ||
| 25 | |||
| 26 | 2010-09-10 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | ||
| 27 | |||
| 28 | * config/arm/neon-schedgen.ml (allCores): Add support for | ||
| 29 | Cortex-A9. | ||
| 30 | * config/arm/cortex-a9-neon.md: New and partially generated. | ||
| 31 | * config/arm/cortex-a9.md (cortex_a9_dp): Adjust for Neon. | ||
| 32 | |||
| 33 | 2010-09-15 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 34 | |||
| 35 | Issue #9441 | ||
| 36 | |||
| 37 | === modified file 'gcc/config/arm/cortex-a8-neon.md' | ||
| 38 | --- old/gcc/config/arm/cortex-a8-neon.md 2009-02-20 15:20:38 +0000 | ||
| 39 | +++ new/gcc/config/arm/cortex-a8-neon.md 2010-09-16 09:47:44 +0000 | ||
| 40 | @@ -182,12 +182,12 @@ | ||
| 41 | |||
| 42 | ;; NEON -> core transfers. | ||
| 43 | |||
| 44 | -(define_insn_reservation "neon_mrc" 20 | ||
| 45 | +(define_insn_reservation "cortex_a8_neon_mrc" 20 | ||
| 46 | (and (eq_attr "tune" "cortexa8") | ||
| 47 | (eq_attr "neon_type" "neon_mrc")) | ||
| 48 | "cortex_a8_neon_ls") | ||
| 49 | |||
| 50 | -(define_insn_reservation "neon_mrrc" 21 | ||
| 51 | +(define_insn_reservation "cortex_a8_neon_mrrc" 21 | ||
| 52 | (and (eq_attr "tune" "cortexa8") | ||
| 53 | (eq_attr "neon_type" "neon_mrrc")) | ||
| 54 | "cortex_a8_neon_ls_2") | ||
| 55 | @@ -196,48 +196,48 @@ | ||
| 56 | |||
| 57 | ;; Instructions using this reservation read their source operands at N2, and | ||
| 58 | ;; produce a result at N3. | ||
| 59 | -(define_insn_reservation "neon_int_1" 3 | ||
| 60 | +(define_insn_reservation "cortex_a8_neon_int_1" 3 | ||
| 61 | (and (eq_attr "tune" "cortexa8") | ||
| 62 | (eq_attr "neon_type" "neon_int_1")) | ||
| 63 | "cortex_a8_neon_dp") | ||
| 64 | |||
| 65 | ;; Instructions using this reservation read their (D|Q)m operands at N1, | ||
| 66 | ;; their (D|Q)n operands at N2, and produce a result at N3. | ||
| 67 | -(define_insn_reservation "neon_int_2" 3 | ||
| 68 | +(define_insn_reservation "cortex_a8_neon_int_2" 3 | ||
| 69 | (and (eq_attr "tune" "cortexa8") | ||
| 70 | (eq_attr "neon_type" "neon_int_2")) | ||
| 71 | "cortex_a8_neon_dp") | ||
| 72 | |||
| 73 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 74 | ;; produce a result at N3. | ||
| 75 | -(define_insn_reservation "neon_int_3" 3 | ||
| 76 | +(define_insn_reservation "cortex_a8_neon_int_3" 3 | ||
| 77 | (and (eq_attr "tune" "cortexa8") | ||
| 78 | (eq_attr "neon_type" "neon_int_3")) | ||
| 79 | "cortex_a8_neon_dp") | ||
| 80 | |||
| 81 | ;; Instructions using this reservation read their source operands at N2, and | ||
| 82 | ;; produce a result at N4. | ||
| 83 | -(define_insn_reservation "neon_int_4" 4 | ||
| 84 | +(define_insn_reservation "cortex_a8_neon_int_4" 4 | ||
| 85 | (and (eq_attr "tune" "cortexa8") | ||
| 86 | (eq_attr "neon_type" "neon_int_4")) | ||
| 87 | "cortex_a8_neon_dp") | ||
| 88 | |||
| 89 | ;; Instructions using this reservation read their (D|Q)m operands at N1, | ||
| 90 | ;; their (D|Q)n operands at N2, and produce a result at N4. | ||
| 91 | -(define_insn_reservation "neon_int_5" 4 | ||
| 92 | +(define_insn_reservation "cortex_a8_neon_int_5" 4 | ||
| 93 | (and (eq_attr "tune" "cortexa8") | ||
| 94 | (eq_attr "neon_type" "neon_int_5")) | ||
| 95 | "cortex_a8_neon_dp") | ||
| 96 | |||
| 97 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 98 | ;; produce a result at N4. | ||
| 99 | -(define_insn_reservation "neon_vqneg_vqabs" 4 | ||
| 100 | +(define_insn_reservation "cortex_a8_neon_vqneg_vqabs" 4 | ||
| 101 | (and (eq_attr "tune" "cortexa8") | ||
| 102 | (eq_attr "neon_type" "neon_vqneg_vqabs")) | ||
| 103 | "cortex_a8_neon_dp") | ||
| 104 | |||
| 105 | ;; Instructions using this reservation produce a result at N3. | ||
| 106 | -(define_insn_reservation "neon_vmov" 3 | ||
| 107 | +(define_insn_reservation "cortex_a8_neon_vmov" 3 | ||
| 108 | (and (eq_attr "tune" "cortexa8") | ||
| 109 | (eq_attr "neon_type" "neon_vmov")) | ||
| 110 | "cortex_a8_neon_dp") | ||
| 111 | @@ -245,7 +245,7 @@ | ||
| 112 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 113 | ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 114 | ;; produce a result at N6. | ||
| 115 | -(define_insn_reservation "neon_vaba" 6 | ||
| 116 | +(define_insn_reservation "cortex_a8_neon_vaba" 6 | ||
| 117 | (and (eq_attr "tune" "cortexa8") | ||
| 118 | (eq_attr "neon_type" "neon_vaba")) | ||
| 119 | "cortex_a8_neon_dp") | ||
| 120 | @@ -253,35 +253,35 @@ | ||
| 121 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 122 | ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 123 | ;; produce a result at N6 on cycle 2. | ||
| 124 | -(define_insn_reservation "neon_vaba_qqq" 7 | ||
| 125 | +(define_insn_reservation "cortex_a8_neon_vaba_qqq" 7 | ||
| 126 | (and (eq_attr "tune" "cortexa8") | ||
| 127 | (eq_attr "neon_type" "neon_vaba_qqq")) | ||
| 128 | "cortex_a8_neon_dp_2") | ||
| 129 | |||
| 130 | ;; Instructions using this reservation read their (D|Q)m operands at N1, | ||
| 131 | ;; their (D|Q)d operands at N3, and produce a result at N6. | ||
| 132 | -(define_insn_reservation "neon_vsma" 6 | ||
| 133 | +(define_insn_reservation "cortex_a8_neon_vsma" 6 | ||
| 134 | (and (eq_attr "tune" "cortexa8") | ||
| 135 | (eq_attr "neon_type" "neon_vsma")) | ||
| 136 | "cortex_a8_neon_dp") | ||
| 137 | |||
| 138 | ;; Instructions using this reservation read their source operands at N2, and | ||
| 139 | ;; produce a result at N6. | ||
| 140 | -(define_insn_reservation "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 | ||
| 141 | +(define_insn_reservation "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 | ||
| 142 | (and (eq_attr "tune" "cortexa8") | ||
| 143 | (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) | ||
| 144 | "cortex_a8_neon_dp") | ||
| 145 | |||
| 146 | ;; Instructions using this reservation read their source operands at N2, and | ||
| 147 | ;; produce a result at N6 on cycle 2. | ||
| 148 | -(define_insn_reservation "neon_mul_qqq_8_16_32_ddd_32" 7 | ||
| 149 | +(define_insn_reservation "cortex_a8_neon_mul_qqq_8_16_32_ddd_32" 7 | ||
| 150 | (and (eq_attr "tune" "cortexa8") | ||
| 151 | (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32")) | ||
| 152 | "cortex_a8_neon_dp_2") | ||
| 153 | |||
| 154 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 155 | ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2. | ||
| 156 | -(define_insn_reservation "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 | ||
| 157 | +(define_insn_reservation "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 | ||
| 158 | (and (eq_attr "tune" "cortexa8") | ||
| 159 | (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) | ||
| 160 | "cortex_a8_neon_dp_2") | ||
| 161 | @@ -289,7 +289,7 @@ | ||
| 162 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 163 | ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and | ||
| 164 | ;; produce a result at N6. | ||
| 165 | -(define_insn_reservation "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 | ||
| 166 | +(define_insn_reservation "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 | ||
| 167 | (and (eq_attr "tune" "cortexa8") | ||
| 168 | (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) | ||
| 169 | "cortex_a8_neon_dp") | ||
| 170 | @@ -297,7 +297,7 @@ | ||
| 171 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 172 | ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and | ||
| 173 | ;; produce a result at N6 on cycle 2. | ||
| 174 | -(define_insn_reservation "neon_mla_qqq_8_16" 7 | ||
| 175 | +(define_insn_reservation "cortex_a8_neon_mla_qqq_8_16" 7 | ||
| 176 | (and (eq_attr "tune" "cortexa8") | ||
| 177 | (eq_attr "neon_type" "neon_mla_qqq_8_16")) | ||
| 178 | "cortex_a8_neon_dp_2") | ||
| 179 | @@ -305,7 +305,7 @@ | ||
| 180 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 181 | ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 182 | ;; produce a result at N6 on cycle 2. | ||
| 183 | -(define_insn_reservation "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 | ||
| 184 | +(define_insn_reservation "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 | ||
| 185 | (and (eq_attr "tune" "cortexa8") | ||
| 186 | (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) | ||
| 187 | "cortex_a8_neon_dp_2") | ||
| 188 | @@ -313,21 +313,21 @@ | ||
| 189 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 190 | ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 191 | ;; produce a result at N6 on cycle 4. | ||
| 192 | -(define_insn_reservation "neon_mla_qqq_32_qqd_32_scalar" 9 | ||
| 193 | +(define_insn_reservation "cortex_a8_neon_mla_qqq_32_qqd_32_scalar" 9 | ||
| 194 | (and (eq_attr "tune" "cortexa8") | ||
| 195 | (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar")) | ||
| 196 | "cortex_a8_neon_dp_4") | ||
| 197 | |||
| 198 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 199 | ;; their (D|Q)m operands at N1, and produce a result at N6. | ||
| 200 | -(define_insn_reservation "neon_mul_ddd_16_scalar_32_16_long_scalar" 6 | ||
| 201 | +(define_insn_reservation "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar" 6 | ||
| 202 | (and (eq_attr "tune" "cortexa8") | ||
| 203 | (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) | ||
| 204 | "cortex_a8_neon_dp") | ||
| 205 | |||
| 206 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 207 | ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4. | ||
| 208 | -(define_insn_reservation "neon_mul_qqd_32_scalar" 9 | ||
| 209 | +(define_insn_reservation "cortex_a8_neon_mul_qqd_32_scalar" 9 | ||
| 210 | (and (eq_attr "tune" "cortexa8") | ||
| 211 | (eq_attr "neon_type" "neon_mul_qqd_32_scalar")) | ||
| 212 | "cortex_a8_neon_dp_4") | ||
| 213 | @@ -335,84 +335,84 @@ | ||
| 214 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 215 | ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 216 | ;; produce a result at N6. | ||
| 217 | -(define_insn_reservation "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 | ||
| 218 | +(define_insn_reservation "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 | ||
| 219 | (and (eq_attr "tune" "cortexa8") | ||
| 220 | (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) | ||
| 221 | "cortex_a8_neon_dp") | ||
| 222 | |||
| 223 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 224 | ;; produce a result at N3. | ||
| 225 | -(define_insn_reservation "neon_shift_1" 3 | ||
| 226 | +(define_insn_reservation "cortex_a8_neon_shift_1" 3 | ||
| 227 | (and (eq_attr "tune" "cortexa8") | ||
| 228 | (eq_attr "neon_type" "neon_shift_1")) | ||
| 229 | "cortex_a8_neon_dp") | ||
| 230 | |||
| 231 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 232 | ;; produce a result at N4. | ||
| 233 | -(define_insn_reservation "neon_shift_2" 4 | ||
| 234 | +(define_insn_reservation "cortex_a8_neon_shift_2" 4 | ||
| 235 | (and (eq_attr "tune" "cortexa8") | ||
| 236 | (eq_attr "neon_type" "neon_shift_2")) | ||
| 237 | "cortex_a8_neon_dp") | ||
| 238 | |||
| 239 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 240 | ;; produce a result at N3 on cycle 2. | ||
| 241 | -(define_insn_reservation "neon_shift_3" 4 | ||
| 242 | +(define_insn_reservation "cortex_a8_neon_shift_3" 4 | ||
| 243 | (and (eq_attr "tune" "cortexa8") | ||
| 244 | (eq_attr "neon_type" "neon_shift_3")) | ||
| 245 | "cortex_a8_neon_dp_2") | ||
| 246 | |||
| 247 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 248 | ;; produce a result at N1. | ||
| 249 | -(define_insn_reservation "neon_vshl_ddd" 1 | ||
| 250 | +(define_insn_reservation "cortex_a8_neon_vshl_ddd" 1 | ||
| 251 | (and (eq_attr "tune" "cortexa8") | ||
| 252 | (eq_attr "neon_type" "neon_vshl_ddd")) | ||
| 253 | "cortex_a8_neon_dp") | ||
| 254 | |||
| 255 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 256 | ;; produce a result at N4 on cycle 2. | ||
| 257 | -(define_insn_reservation "neon_vqshl_vrshl_vqrshl_qqq" 5 | ||
| 258 | +(define_insn_reservation "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq" 5 | ||
| 259 | (and (eq_attr "tune" "cortexa8") | ||
| 260 | (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq")) | ||
| 261 | "cortex_a8_neon_dp_2") | ||
| 262 | |||
| 263 | ;; Instructions using this reservation read their (D|Q)m operands at N1, | ||
| 264 | ;; their (D|Q)d operands at N3, and produce a result at N6. | ||
| 265 | -(define_insn_reservation "neon_vsra_vrsra" 6 | ||
| 266 | +(define_insn_reservation "cortex_a8_neon_vsra_vrsra" 6 | ||
| 267 | (and (eq_attr "tune" "cortexa8") | ||
| 268 | (eq_attr "neon_type" "neon_vsra_vrsra")) | ||
| 269 | "cortex_a8_neon_dp") | ||
| 270 | |||
| 271 | ;; Instructions using this reservation read their source operands at N2, and | ||
| 272 | ;; produce a result at N5. | ||
| 273 | -(define_insn_reservation "neon_fp_vadd_ddd_vabs_dd" 5 | ||
| 274 | +(define_insn_reservation "cortex_a8_neon_fp_vadd_ddd_vabs_dd" 5 | ||
| 275 | (and (eq_attr "tune" "cortexa8") | ||
| 276 | (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")) | ||
| 277 | "cortex_a8_neon_fadd") | ||
| 278 | |||
| 279 | ;; Instructions using this reservation read their source operands at N2, and | ||
| 280 | ;; produce a result at N5 on cycle 2. | ||
| 281 | -(define_insn_reservation "neon_fp_vadd_qqq_vabs_qq" 6 | ||
| 282 | +(define_insn_reservation "cortex_a8_neon_fp_vadd_qqq_vabs_qq" 6 | ||
| 283 | (and (eq_attr "tune" "cortexa8") | ||
| 284 | (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq")) | ||
| 285 | "cortex_a8_neon_fadd_2") | ||
| 286 | |||
| 287 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 288 | ;; produce a result at N5. | ||
| 289 | -(define_insn_reservation "neon_fp_vsum" 5 | ||
| 290 | +(define_insn_reservation "cortex_a8_neon_fp_vsum" 5 | ||
| 291 | (and (eq_attr "tune" "cortexa8") | ||
| 292 | (eq_attr "neon_type" "neon_fp_vsum")) | ||
| 293 | "cortex_a8_neon_fadd") | ||
| 294 | |||
| 295 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 296 | ;; their (D|Q)m operands at N1, and produce a result at N5. | ||
| 297 | -(define_insn_reservation "neon_fp_vmul_ddd" 5 | ||
| 298 | +(define_insn_reservation "cortex_a8_neon_fp_vmul_ddd" 5 | ||
| 299 | (and (eq_attr "tune" "cortexa8") | ||
| 300 | (eq_attr "neon_type" "neon_fp_vmul_ddd")) | ||
| 301 | "cortex_a8_neon_dp") | ||
| 302 | |||
| 303 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 304 | ;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2. | ||
| 305 | -(define_insn_reservation "neon_fp_vmul_qqd" 6 | ||
| 306 | +(define_insn_reservation "cortex_a8_neon_fp_vmul_qqd" 6 | ||
| 307 | (and (eq_attr "tune" "cortexa8") | ||
| 308 | (eq_attr "neon_type" "neon_fp_vmul_qqd")) | ||
| 309 | "cortex_a8_neon_dp_2") | ||
| 310 | @@ -420,7 +420,7 @@ | ||
| 311 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 312 | ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and | ||
| 313 | ;; produce a result at N9. | ||
| 314 | -(define_insn_reservation "neon_fp_vmla_ddd" 9 | ||
| 315 | +(define_insn_reservation "cortex_a8_neon_fp_vmla_ddd" 9 | ||
| 316 | (and (eq_attr "tune" "cortexa8") | ||
| 317 | (eq_attr "neon_type" "neon_fp_vmla_ddd")) | ||
| 318 | "cortex_a8_neon_fmul_then_fadd") | ||
| 319 | @@ -428,7 +428,7 @@ | ||
| 320 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 321 | ;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and | ||
| 322 | ;; produce a result at N9 on cycle 2. | ||
| 323 | -(define_insn_reservation "neon_fp_vmla_qqq" 10 | ||
| 324 | +(define_insn_reservation "cortex_a8_neon_fp_vmla_qqq" 10 | ||
| 325 | (and (eq_attr "tune" "cortexa8") | ||
| 326 | (eq_attr "neon_type" "neon_fp_vmla_qqq")) | ||
| 327 | "cortex_a8_neon_fmul_then_fadd_2") | ||
| 328 | @@ -436,7 +436,7 @@ | ||
| 329 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 330 | ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 331 | ;; produce a result at N9. | ||
| 332 | -(define_insn_reservation "neon_fp_vmla_ddd_scalar" 9 | ||
| 333 | +(define_insn_reservation "cortex_a8_neon_fp_vmla_ddd_scalar" 9 | ||
| 334 | (and (eq_attr "tune" "cortexa8") | ||
| 335 | (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar")) | ||
| 336 | "cortex_a8_neon_fmul_then_fadd") | ||
| 337 | @@ -444,869 +444,869 @@ | ||
| 338 | ;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 339 | ;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 340 | ;; produce a result at N9 on cycle 2. | ||
| 341 | -(define_insn_reservation "neon_fp_vmla_qqq_scalar" 10 | ||
| 342 | +(define_insn_reservation "cortex_a8_neon_fp_vmla_qqq_scalar" 10 | ||
| 343 | (and (eq_attr "tune" "cortexa8") | ||
| 344 | (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar")) | ||
| 345 | "cortex_a8_neon_fmul_then_fadd_2") | ||
| 346 | |||
| 347 | ;; Instructions using this reservation read their source operands at N2, and | ||
| 348 | ;; produce a result at N9. | ||
| 349 | -(define_insn_reservation "neon_fp_vrecps_vrsqrts_ddd" 9 | ||
| 350 | +(define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_ddd" 9 | ||
| 351 | (and (eq_attr "tune" "cortexa8") | ||
| 352 | (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd")) | ||
| 353 | "cortex_a8_neon_fmul_then_fadd") | ||
| 354 | |||
| 355 | ;; Instructions using this reservation read their source operands at N2, and | ||
| 356 | ;; produce a result at N9 on cycle 2. | ||
| 357 | -(define_insn_reservation "neon_fp_vrecps_vrsqrts_qqq" 10 | ||
| 358 | +(define_insn_reservation "cortex_a8_neon_fp_vrecps_vrsqrts_qqq" 10 | ||
| 359 | (and (eq_attr "tune" "cortexa8") | ||
| 360 | (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq")) | ||
| 361 | "cortex_a8_neon_fmul_then_fadd_2") | ||
| 362 | |||
| 363 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 364 | ;; produce a result at N2. | ||
| 365 | -(define_insn_reservation "neon_bp_simple" 2 | ||
| 366 | +(define_insn_reservation "cortex_a8_neon_bp_simple" 2 | ||
| 367 | (and (eq_attr "tune" "cortexa8") | ||
| 368 | (eq_attr "neon_type" "neon_bp_simple")) | ||
| 369 | "cortex_a8_neon_perm") | ||
| 370 | |||
| 371 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 372 | ;; produce a result at N2 on cycle 2. | ||
| 373 | -(define_insn_reservation "neon_bp_2cycle" 3 | ||
| 374 | +(define_insn_reservation "cortex_a8_neon_bp_2cycle" 3 | ||
| 375 | (and (eq_attr "tune" "cortexa8") | ||
| 376 | (eq_attr "neon_type" "neon_bp_2cycle")) | ||
| 377 | "cortex_a8_neon_perm_2") | ||
| 378 | |||
| 379 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 380 | ;; produce a result at N2 on cycle 3. | ||
| 381 | -(define_insn_reservation "neon_bp_3cycle" 4 | ||
| 382 | +(define_insn_reservation "cortex_a8_neon_bp_3cycle" 4 | ||
| 383 | (and (eq_attr "tune" "cortexa8") | ||
| 384 | (eq_attr "neon_type" "neon_bp_3cycle")) | ||
| 385 | "cortex_a8_neon_perm_3") | ||
| 386 | |||
| 387 | ;; Instructions using this reservation produce a result at N1. | ||
| 388 | -(define_insn_reservation "neon_ldr" 1 | ||
| 389 | +(define_insn_reservation "cortex_a8_neon_ldr" 1 | ||
| 390 | (and (eq_attr "tune" "cortexa8") | ||
| 391 | (eq_attr "neon_type" "neon_ldr")) | ||
| 392 | "cortex_a8_neon_ls") | ||
| 393 | |||
| 394 | ;; Instructions using this reservation read their source operands at N1. | ||
| 395 | -(define_insn_reservation "neon_str" 0 | ||
| 396 | +(define_insn_reservation "cortex_a8_neon_str" 0 | ||
| 397 | (and (eq_attr "tune" "cortexa8") | ||
| 398 | (eq_attr "neon_type" "neon_str")) | ||
| 399 | "cortex_a8_neon_ls") | ||
| 400 | |||
| 401 | ;; Instructions using this reservation produce a result at N1 on cycle 2. | ||
| 402 | -(define_insn_reservation "neon_vld1_1_2_regs" 2 | ||
| 403 | +(define_insn_reservation "cortex_a8_neon_vld1_1_2_regs" 2 | ||
| 404 | (and (eq_attr "tune" "cortexa8") | ||
| 405 | (eq_attr "neon_type" "neon_vld1_1_2_regs")) | ||
| 406 | "cortex_a8_neon_ls_2") | ||
| 407 | |||
| 408 | ;; Instructions using this reservation produce a result at N1 on cycle 3. | ||
| 409 | -(define_insn_reservation "neon_vld1_3_4_regs" 3 | ||
| 410 | +(define_insn_reservation "cortex_a8_neon_vld1_3_4_regs" 3 | ||
| 411 | (and (eq_attr "tune" "cortexa8") | ||
| 412 | (eq_attr "neon_type" "neon_vld1_3_4_regs")) | ||
| 413 | "cortex_a8_neon_ls_3") | ||
| 414 | |||
| 415 | ;; Instructions using this reservation produce a result at N2 on cycle 2. | ||
| 416 | -(define_insn_reservation "neon_vld2_2_regs_vld1_vld2_all_lanes" 3 | ||
| 417 | +(define_insn_reservation "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes" 3 | ||
| 418 | (and (eq_attr "tune" "cortexa8") | ||
| 419 | (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) | ||
| 420 | "cortex_a8_neon_ls_2") | ||
| 421 | |||
| 422 | ;; Instructions using this reservation produce a result at N2 on cycle 3. | ||
| 423 | -(define_insn_reservation "neon_vld2_4_regs" 4 | ||
| 424 | +(define_insn_reservation "cortex_a8_neon_vld2_4_regs" 4 | ||
| 425 | (and (eq_attr "tune" "cortexa8") | ||
| 426 | (eq_attr "neon_type" "neon_vld2_4_regs")) | ||
| 427 | "cortex_a8_neon_ls_3") | ||
| 428 | |||
| 429 | ;; Instructions using this reservation produce a result at N2 on cycle 4. | ||
| 430 | -(define_insn_reservation "neon_vld3_vld4" 5 | ||
| 431 | +(define_insn_reservation "cortex_a8_neon_vld3_vld4" 5 | ||
| 432 | (and (eq_attr "tune" "cortexa8") | ||
| 433 | (eq_attr "neon_type" "neon_vld3_vld4")) | ||
| 434 | "cortex_a8_neon_ls_4") | ||
| 435 | |||
| 436 | ;; Instructions using this reservation read their source operands at N1. | ||
| 437 | -(define_insn_reservation "neon_vst1_1_2_regs_vst2_2_regs" 0 | ||
| 438 | +(define_insn_reservation "cortex_a8_neon_vst1_1_2_regs_vst2_2_regs" 0 | ||
| 439 | (and (eq_attr "tune" "cortexa8") | ||
| 440 | (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")) | ||
| 441 | "cortex_a8_neon_ls_2") | ||
| 442 | |||
| 443 | ;; Instructions using this reservation read their source operands at N1. | ||
| 444 | -(define_insn_reservation "neon_vst1_3_4_regs" 0 | ||
| 445 | +(define_insn_reservation "cortex_a8_neon_vst1_3_4_regs" 0 | ||
| 446 | (and (eq_attr "tune" "cortexa8") | ||
| 447 | (eq_attr "neon_type" "neon_vst1_3_4_regs")) | ||
| 448 | "cortex_a8_neon_ls_3") | ||
| 449 | |||
| 450 | ;; Instructions using this reservation read their source operands at N1. | ||
| 451 | -(define_insn_reservation "neon_vst2_4_regs_vst3_vst4" 0 | ||
| 452 | +(define_insn_reservation "cortex_a8_neon_vst2_4_regs_vst3_vst4" 0 | ||
| 453 | (and (eq_attr "tune" "cortexa8") | ||
| 454 | (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")) | ||
| 455 | "cortex_a8_neon_ls_4") | ||
| 456 | |||
| 457 | ;; Instructions using this reservation read their source operands at N1. | ||
| 458 | -(define_insn_reservation "neon_vst3_vst4" 0 | ||
| 459 | +(define_insn_reservation "cortex_a8_neon_vst3_vst4" 0 | ||
| 460 | (and (eq_attr "tune" "cortexa8") | ||
| 461 | (eq_attr "neon_type" "neon_vst3_vst4")) | ||
| 462 | "cortex_a8_neon_ls_4") | ||
| 463 | |||
| 464 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 465 | ;; produce a result at N2 on cycle 3. | ||
| 466 | -(define_insn_reservation "neon_vld1_vld2_lane" 4 | ||
| 467 | +(define_insn_reservation "cortex_a8_neon_vld1_vld2_lane" 4 | ||
| 468 | (and (eq_attr "tune" "cortexa8") | ||
| 469 | (eq_attr "neon_type" "neon_vld1_vld2_lane")) | ||
| 470 | "cortex_a8_neon_ls_3") | ||
| 471 | |||
| 472 | ;; Instructions using this reservation read their source operands at N1, and | ||
| 473 | ;; produce a result at N2 on cycle 5. | ||
| 474 | -(define_insn_reservation "neon_vld3_vld4_lane" 6 | ||
| 475 | +(define_insn_reservation "cortex_a8_neon_vld3_vld4_lane" 6 | ||
| 476 | (and (eq_attr "tune" "cortexa8") | ||
| 477 | (eq_attr "neon_type" "neon_vld3_vld4_lane")) | ||
| 478 | "cortex_a8_neon_ls_5") | ||
| 479 | |||
| 480 | ;; Instructions using this reservation read their source operands at N1. | ||
| 481 | -(define_insn_reservation "neon_vst1_vst2_lane" 0 | ||
| 482 | +(define_insn_reservation "cortex_a8_neon_vst1_vst2_lane" 0 | ||
| 483 | (and (eq_attr "tune" "cortexa8") | ||
| 484 | (eq_attr "neon_type" "neon_vst1_vst2_lane")) | ||
| 485 | "cortex_a8_neon_ls_2") | ||
| 486 | |||
| 487 | ;; Instructions using this reservation read their source operands at N1. | ||
| 488 | -(define_insn_reservation "neon_vst3_vst4_lane" 0 | ||
| 489 | +(define_insn_reservation "cortex_a8_neon_vst3_vst4_lane" 0 | ||
| 490 | (and (eq_attr "tune" "cortexa8") | ||
| 491 | (eq_attr "neon_type" "neon_vst3_vst4_lane")) | ||
| 492 | "cortex_a8_neon_ls_3") | ||
| 493 | |||
| 494 | ;; Instructions using this reservation produce a result at N2 on cycle 2. | ||
| 495 | -(define_insn_reservation "neon_vld3_vld4_all_lanes" 3 | ||
| 496 | +(define_insn_reservation "cortex_a8_neon_vld3_vld4_all_lanes" 3 | ||
| 497 | (and (eq_attr "tune" "cortexa8") | ||
| 498 | (eq_attr "neon_type" "neon_vld3_vld4_all_lanes")) | ||
| 499 | "cortex_a8_neon_ls_3") | ||
| 500 | |||
| 501 | ;; Instructions using this reservation produce a result at N2. | ||
| 502 | -(define_insn_reservation "neon_mcr" 2 | ||
| 503 | +(define_insn_reservation "cortex_a8_neon_mcr" 2 | ||
| 504 | (and (eq_attr "tune" "cortexa8") | ||
| 505 | (eq_attr "neon_type" "neon_mcr")) | ||
| 506 | "cortex_a8_neon_perm") | ||
| 507 | |||
| 508 | ;; Instructions using this reservation produce a result at N2. | ||
| 509 | -(define_insn_reservation "neon_mcr_2_mcrr" 2 | ||
| 510 | +(define_insn_reservation "cortex_a8_neon_mcr_2_mcrr" 2 | ||
| 511 | (and (eq_attr "tune" "cortexa8") | ||
| 512 | (eq_attr "neon_type" "neon_mcr_2_mcrr")) | ||
| 513 | "cortex_a8_neon_perm_2") | ||
| 514 | |||
| 515 | ;; Exceptions to the default latencies. | ||
| 516 | |||
| 517 | -(define_bypass 1 "neon_mcr_2_mcrr" | ||
| 518 | - "neon_int_1,\ | ||
| 519 | - neon_int_4,\ | ||
| 520 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 521 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 522 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 523 | - neon_mla_qqq_8_16,\ | ||
| 524 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 525 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 526 | - neon_fp_vmla_ddd,\ | ||
| 527 | - neon_fp_vmla_qqq,\ | ||
| 528 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 529 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 530 | - | ||
| 531 | -(define_bypass 1 "neon_mcr" | ||
| 532 | - "neon_int_1,\ | ||
| 533 | - neon_int_4,\ | ||
| 534 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 535 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 536 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 537 | - neon_mla_qqq_8_16,\ | ||
| 538 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 539 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 540 | - neon_fp_vmla_ddd,\ | ||
| 541 | - neon_fp_vmla_qqq,\ | ||
| 542 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 543 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 544 | - | ||
| 545 | -(define_bypass 2 "neon_vld3_vld4_all_lanes" | ||
| 546 | - "neon_int_1,\ | ||
| 547 | - neon_int_4,\ | ||
| 548 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 549 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 550 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 551 | - neon_mla_qqq_8_16,\ | ||
| 552 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 553 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 554 | - neon_fp_vmla_ddd,\ | ||
| 555 | - neon_fp_vmla_qqq,\ | ||
| 556 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 557 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 558 | - | ||
| 559 | -(define_bypass 5 "neon_vld3_vld4_lane" | ||
| 560 | - "neon_int_1,\ | ||
| 561 | - neon_int_4,\ | ||
| 562 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 563 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 564 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 565 | - neon_mla_qqq_8_16,\ | ||
| 566 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 567 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 568 | - neon_fp_vmla_ddd,\ | ||
| 569 | - neon_fp_vmla_qqq,\ | ||
| 570 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 571 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 572 | - | ||
| 573 | -(define_bypass 3 "neon_vld1_vld2_lane" | ||
| 574 | - "neon_int_1,\ | ||
| 575 | - neon_int_4,\ | ||
| 576 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 577 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 578 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 579 | - neon_mla_qqq_8_16,\ | ||
| 580 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 581 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 582 | - neon_fp_vmla_ddd,\ | ||
| 583 | - neon_fp_vmla_qqq,\ | ||
| 584 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 585 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 586 | - | ||
| 587 | -(define_bypass 4 "neon_vld3_vld4" | ||
| 588 | - "neon_int_1,\ | ||
| 589 | - neon_int_4,\ | ||
| 590 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 591 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 592 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 593 | - neon_mla_qqq_8_16,\ | ||
| 594 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 595 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 596 | - neon_fp_vmla_ddd,\ | ||
| 597 | - neon_fp_vmla_qqq,\ | ||
| 598 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 599 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 600 | - | ||
| 601 | -(define_bypass 3 "neon_vld2_4_regs" | ||
| 602 | - "neon_int_1,\ | ||
| 603 | - neon_int_4,\ | ||
| 604 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 605 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 606 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 607 | - neon_mla_qqq_8_16,\ | ||
| 608 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 609 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 610 | - neon_fp_vmla_ddd,\ | ||
| 611 | - neon_fp_vmla_qqq,\ | ||
| 612 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 613 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 614 | - | ||
| 615 | -(define_bypass 2 "neon_vld2_2_regs_vld1_vld2_all_lanes" | ||
| 616 | - "neon_int_1,\ | ||
| 617 | - neon_int_4,\ | ||
| 618 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 619 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 620 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 621 | - neon_mla_qqq_8_16,\ | ||
| 622 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 623 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 624 | - neon_fp_vmla_ddd,\ | ||
| 625 | - neon_fp_vmla_qqq,\ | ||
| 626 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 627 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 628 | - | ||
| 629 | -(define_bypass 2 "neon_vld1_3_4_regs" | ||
| 630 | - "neon_int_1,\ | ||
| 631 | - neon_int_4,\ | ||
| 632 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 633 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 634 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 635 | - neon_mla_qqq_8_16,\ | ||
| 636 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 637 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 638 | - neon_fp_vmla_ddd,\ | ||
| 639 | - neon_fp_vmla_qqq,\ | ||
| 640 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 641 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 642 | - | ||
| 643 | -(define_bypass 1 "neon_vld1_1_2_regs" | ||
| 644 | - "neon_int_1,\ | ||
| 645 | - neon_int_4,\ | ||
| 646 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 647 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 648 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 649 | - neon_mla_qqq_8_16,\ | ||
| 650 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 651 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 652 | - neon_fp_vmla_ddd,\ | ||
| 653 | - neon_fp_vmla_qqq,\ | ||
| 654 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 655 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 656 | - | ||
| 657 | -(define_bypass 0 "neon_ldr" | ||
| 658 | - "neon_int_1,\ | ||
| 659 | - neon_int_4,\ | ||
| 660 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 661 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 662 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 663 | - neon_mla_qqq_8_16,\ | ||
| 664 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 665 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 666 | - neon_fp_vmla_ddd,\ | ||
| 667 | - neon_fp_vmla_qqq,\ | ||
| 668 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 669 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 670 | - | ||
| 671 | -(define_bypass 3 "neon_bp_3cycle" | ||
| 672 | - "neon_int_1,\ | ||
| 673 | - neon_int_4,\ | ||
| 674 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 675 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 676 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 677 | - neon_mla_qqq_8_16,\ | ||
| 678 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 679 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 680 | - neon_fp_vmla_ddd,\ | ||
| 681 | - neon_fp_vmla_qqq,\ | ||
| 682 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 683 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 684 | - | ||
| 685 | -(define_bypass 2 "neon_bp_2cycle" | ||
| 686 | - "neon_int_1,\ | ||
| 687 | - neon_int_4,\ | ||
| 688 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 689 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 690 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 691 | - neon_mla_qqq_8_16,\ | ||
| 692 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 693 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 694 | - neon_fp_vmla_ddd,\ | ||
| 695 | - neon_fp_vmla_qqq,\ | ||
| 696 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 697 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 698 | - | ||
| 699 | -(define_bypass 1 "neon_bp_simple" | ||
| 700 | - "neon_int_1,\ | ||
| 701 | - neon_int_4,\ | ||
| 702 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 703 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 704 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 705 | - neon_mla_qqq_8_16,\ | ||
| 706 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 707 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 708 | - neon_fp_vmla_ddd,\ | ||
| 709 | - neon_fp_vmla_qqq,\ | ||
| 710 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 711 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 712 | - | ||
| 713 | -(define_bypass 9 "neon_fp_vrecps_vrsqrts_qqq" | ||
| 714 | - "neon_int_1,\ | ||
| 715 | - neon_int_4,\ | ||
| 716 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 717 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 718 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 719 | - neon_mla_qqq_8_16,\ | ||
| 720 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 721 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 722 | - neon_fp_vmla_ddd,\ | ||
| 723 | - neon_fp_vmla_qqq,\ | ||
| 724 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 725 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 726 | - | ||
| 727 | -(define_bypass 8 "neon_fp_vrecps_vrsqrts_ddd" | ||
| 728 | - "neon_int_1,\ | ||
| 729 | - neon_int_4,\ | ||
| 730 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 731 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 732 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 733 | - neon_mla_qqq_8_16,\ | ||
| 734 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 735 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 736 | - neon_fp_vmla_ddd,\ | ||
| 737 | - neon_fp_vmla_qqq,\ | ||
| 738 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 739 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 740 | - | ||
| 741 | -(define_bypass 9 "neon_fp_vmla_qqq_scalar" | ||
| 742 | - "neon_int_1,\ | ||
| 743 | - neon_int_4,\ | ||
| 744 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 745 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 746 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 747 | - neon_mla_qqq_8_16,\ | ||
| 748 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 749 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 750 | - neon_fp_vmla_ddd,\ | ||
| 751 | - neon_fp_vmla_qqq,\ | ||
| 752 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 753 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 754 | - | ||
| 755 | -(define_bypass 8 "neon_fp_vmla_ddd_scalar" | ||
| 756 | - "neon_int_1,\ | ||
| 757 | - neon_int_4,\ | ||
| 758 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 759 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 760 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 761 | - neon_mla_qqq_8_16,\ | ||
| 762 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 763 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 764 | - neon_fp_vmla_ddd,\ | ||
| 765 | - neon_fp_vmla_qqq,\ | ||
| 766 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 767 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 768 | - | ||
| 769 | -(define_bypass 9 "neon_fp_vmla_qqq" | ||
| 770 | - "neon_int_1,\ | ||
| 771 | - neon_int_4,\ | ||
| 772 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 773 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 774 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 775 | - neon_mla_qqq_8_16,\ | ||
| 776 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 777 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 778 | - neon_fp_vmla_ddd,\ | ||
| 779 | - neon_fp_vmla_qqq,\ | ||
| 780 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 781 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 782 | - | ||
| 783 | -(define_bypass 8 "neon_fp_vmla_ddd" | ||
| 784 | - "neon_int_1,\ | ||
| 785 | - neon_int_4,\ | ||
| 786 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 787 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 788 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 789 | - neon_mla_qqq_8_16,\ | ||
| 790 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 791 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 792 | - neon_fp_vmla_ddd,\ | ||
| 793 | - neon_fp_vmla_qqq,\ | ||
| 794 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 795 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 796 | - | ||
| 797 | -(define_bypass 5 "neon_fp_vmul_qqd" | ||
| 798 | - "neon_int_1,\ | ||
| 799 | - neon_int_4,\ | ||
| 800 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 801 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 802 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 803 | - neon_mla_qqq_8_16,\ | ||
| 804 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 805 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 806 | - neon_fp_vmla_ddd,\ | ||
| 807 | - neon_fp_vmla_qqq,\ | ||
| 808 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 809 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 810 | - | ||
| 811 | -(define_bypass 4 "neon_fp_vmul_ddd" | ||
| 812 | - "neon_int_1,\ | ||
| 813 | - neon_int_4,\ | ||
| 814 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 815 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 816 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 817 | - neon_mla_qqq_8_16,\ | ||
| 818 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 819 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 820 | - neon_fp_vmla_ddd,\ | ||
| 821 | - neon_fp_vmla_qqq,\ | ||
| 822 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 823 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 824 | - | ||
| 825 | -(define_bypass 4 "neon_fp_vsum" | ||
| 826 | - "neon_int_1,\ | ||
| 827 | - neon_int_4,\ | ||
| 828 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 829 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 830 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 831 | - neon_mla_qqq_8_16,\ | ||
| 832 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 833 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 834 | - neon_fp_vmla_ddd,\ | ||
| 835 | - neon_fp_vmla_qqq,\ | ||
| 836 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 837 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 838 | - | ||
| 839 | -(define_bypass 5 "neon_fp_vadd_qqq_vabs_qq" | ||
| 840 | - "neon_int_1,\ | ||
| 841 | - neon_int_4,\ | ||
| 842 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 843 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 844 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 845 | - neon_mla_qqq_8_16,\ | ||
| 846 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 847 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 848 | - neon_fp_vmla_ddd,\ | ||
| 849 | - neon_fp_vmla_qqq,\ | ||
| 850 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 851 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 852 | - | ||
| 853 | -(define_bypass 4 "neon_fp_vadd_ddd_vabs_dd" | ||
| 854 | - "neon_int_1,\ | ||
| 855 | - neon_int_4,\ | ||
| 856 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 857 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 858 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 859 | - neon_mla_qqq_8_16,\ | ||
| 860 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 861 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 862 | - neon_fp_vmla_ddd,\ | ||
| 863 | - neon_fp_vmla_qqq,\ | ||
| 864 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 865 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 866 | - | ||
| 867 | -(define_bypass 5 "neon_vsra_vrsra" | ||
| 868 | - "neon_int_1,\ | ||
| 869 | - neon_int_4,\ | ||
| 870 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 871 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 872 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 873 | - neon_mla_qqq_8_16,\ | ||
| 874 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 875 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 876 | - neon_fp_vmla_ddd,\ | ||
| 877 | - neon_fp_vmla_qqq,\ | ||
| 878 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 879 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 880 | - | ||
| 881 | -(define_bypass 4 "neon_vqshl_vrshl_vqrshl_qqq" | ||
| 882 | - "neon_int_1,\ | ||
| 883 | - neon_int_4,\ | ||
| 884 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 885 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 886 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 887 | - neon_mla_qqq_8_16,\ | ||
| 888 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 889 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 890 | - neon_fp_vmla_ddd,\ | ||
| 891 | - neon_fp_vmla_qqq,\ | ||
| 892 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 893 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 894 | - | ||
| 895 | -(define_bypass 0 "neon_vshl_ddd" | ||
| 896 | - "neon_int_1,\ | ||
| 897 | - neon_int_4,\ | ||
| 898 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 899 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 900 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 901 | - neon_mla_qqq_8_16,\ | ||
| 902 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 903 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 904 | - neon_fp_vmla_ddd,\ | ||
| 905 | - neon_fp_vmla_qqq,\ | ||
| 906 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 907 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 908 | - | ||
| 909 | -(define_bypass 3 "neon_shift_3" | ||
| 910 | - "neon_int_1,\ | ||
| 911 | - neon_int_4,\ | ||
| 912 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 913 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 914 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 915 | - neon_mla_qqq_8_16,\ | ||
| 916 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 917 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 918 | - neon_fp_vmla_ddd,\ | ||
| 919 | - neon_fp_vmla_qqq,\ | ||
| 920 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 921 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 922 | - | ||
| 923 | -(define_bypass 3 "neon_shift_2" | ||
| 924 | - "neon_int_1,\ | ||
| 925 | - neon_int_4,\ | ||
| 926 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 927 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 928 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 929 | - neon_mla_qqq_8_16,\ | ||
| 930 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 931 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 932 | - neon_fp_vmla_ddd,\ | ||
| 933 | - neon_fp_vmla_qqq,\ | ||
| 934 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 935 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 936 | - | ||
| 937 | -(define_bypass 2 "neon_shift_1" | ||
| 938 | - "neon_int_1,\ | ||
| 939 | - neon_int_4,\ | ||
| 940 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 941 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 942 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 943 | - neon_mla_qqq_8_16,\ | ||
| 944 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 945 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 946 | - neon_fp_vmla_ddd,\ | ||
| 947 | - neon_fp_vmla_qqq,\ | ||
| 948 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 949 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 950 | - | ||
| 951 | -(define_bypass 5 "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" | ||
| 952 | - "neon_int_1,\ | ||
| 953 | - neon_int_4,\ | ||
| 954 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 955 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 956 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 957 | - neon_mla_qqq_8_16,\ | ||
| 958 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 959 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 960 | - neon_fp_vmla_ddd,\ | ||
| 961 | - neon_fp_vmla_qqq,\ | ||
| 962 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 963 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 964 | - | ||
| 965 | -(define_bypass 8 "neon_mul_qqd_32_scalar" | ||
| 966 | - "neon_int_1,\ | ||
| 967 | - neon_int_4,\ | ||
| 968 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 969 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 970 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 971 | - neon_mla_qqq_8_16,\ | ||
| 972 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 973 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 974 | - neon_fp_vmla_ddd,\ | ||
| 975 | - neon_fp_vmla_qqq,\ | ||
| 976 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 977 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 978 | - | ||
| 979 | -(define_bypass 5 "neon_mul_ddd_16_scalar_32_16_long_scalar" | ||
| 980 | - "neon_int_1,\ | ||
| 981 | - neon_int_4,\ | ||
| 982 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 983 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 984 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 985 | - neon_mla_qqq_8_16,\ | ||
| 986 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 987 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 988 | - neon_fp_vmla_ddd,\ | ||
| 989 | - neon_fp_vmla_qqq,\ | ||
| 990 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 991 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 992 | - | ||
| 993 | -(define_bypass 8 "neon_mla_qqq_32_qqd_32_scalar" | ||
| 994 | - "neon_int_1,\ | ||
| 995 | - neon_int_4,\ | ||
| 996 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 997 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 998 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 999 | - neon_mla_qqq_8_16,\ | ||
| 1000 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1001 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1002 | - neon_fp_vmla_ddd,\ | ||
| 1003 | - neon_fp_vmla_qqq,\ | ||
| 1004 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1005 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1006 | - | ||
| 1007 | -(define_bypass 6 "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" | ||
| 1008 | - "neon_int_1,\ | ||
| 1009 | - neon_int_4,\ | ||
| 1010 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1011 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1012 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1013 | - neon_mla_qqq_8_16,\ | ||
| 1014 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1015 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1016 | - neon_fp_vmla_ddd,\ | ||
| 1017 | - neon_fp_vmla_qqq,\ | ||
| 1018 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1019 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1020 | - | ||
| 1021 | -(define_bypass 6 "neon_mla_qqq_8_16" | ||
| 1022 | - "neon_int_1,\ | ||
| 1023 | - neon_int_4,\ | ||
| 1024 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1025 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1026 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1027 | - neon_mla_qqq_8_16,\ | ||
| 1028 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1029 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1030 | - neon_fp_vmla_ddd,\ | ||
| 1031 | - neon_fp_vmla_qqq,\ | ||
| 1032 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1033 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1034 | - | ||
| 1035 | -(define_bypass 5 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" | ||
| 1036 | - "neon_int_1,\ | ||
| 1037 | - neon_int_4,\ | ||
| 1038 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1039 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1040 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1041 | - neon_mla_qqq_8_16,\ | ||
| 1042 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1043 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1044 | - neon_fp_vmla_ddd,\ | ||
| 1045 | - neon_fp_vmla_qqq,\ | ||
| 1046 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1047 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1048 | - | ||
| 1049 | -(define_bypass 6 "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" | ||
| 1050 | - "neon_int_1,\ | ||
| 1051 | - neon_int_4,\ | ||
| 1052 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1053 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1054 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1055 | - neon_mla_qqq_8_16,\ | ||
| 1056 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1057 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1058 | - neon_fp_vmla_ddd,\ | ||
| 1059 | - neon_fp_vmla_qqq,\ | ||
| 1060 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1061 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1062 | - | ||
| 1063 | -(define_bypass 6 "neon_mul_qqq_8_16_32_ddd_32" | ||
| 1064 | - "neon_int_1,\ | ||
| 1065 | - neon_int_4,\ | ||
| 1066 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1067 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1068 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1069 | - neon_mla_qqq_8_16,\ | ||
| 1070 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1071 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1072 | - neon_fp_vmla_ddd,\ | ||
| 1073 | - neon_fp_vmla_qqq,\ | ||
| 1074 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1075 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1076 | - | ||
| 1077 | -(define_bypass 5 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" | ||
| 1078 | - "neon_int_1,\ | ||
| 1079 | - neon_int_4,\ | ||
| 1080 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1081 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1082 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1083 | - neon_mla_qqq_8_16,\ | ||
| 1084 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1085 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1086 | - neon_fp_vmla_ddd,\ | ||
| 1087 | - neon_fp_vmla_qqq,\ | ||
| 1088 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1089 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1090 | - | ||
| 1091 | -(define_bypass 5 "neon_vsma" | ||
| 1092 | - "neon_int_1,\ | ||
| 1093 | - neon_int_4,\ | ||
| 1094 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1095 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1096 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1097 | - neon_mla_qqq_8_16,\ | ||
| 1098 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1099 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1100 | - neon_fp_vmla_ddd,\ | ||
| 1101 | - neon_fp_vmla_qqq,\ | ||
| 1102 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1103 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1104 | - | ||
| 1105 | -(define_bypass 6 "neon_vaba_qqq" | ||
| 1106 | - "neon_int_1,\ | ||
| 1107 | - neon_int_4,\ | ||
| 1108 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1109 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1110 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1111 | - neon_mla_qqq_8_16,\ | ||
| 1112 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1113 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1114 | - neon_fp_vmla_ddd,\ | ||
| 1115 | - neon_fp_vmla_qqq,\ | ||
| 1116 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1117 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1118 | - | ||
| 1119 | -(define_bypass 5 "neon_vaba" | ||
| 1120 | - "neon_int_1,\ | ||
| 1121 | - neon_int_4,\ | ||
| 1122 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1123 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1124 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1125 | - neon_mla_qqq_8_16,\ | ||
| 1126 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1127 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1128 | - neon_fp_vmla_ddd,\ | ||
| 1129 | - neon_fp_vmla_qqq,\ | ||
| 1130 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1131 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1132 | - | ||
| 1133 | -(define_bypass 2 "neon_vmov" | ||
| 1134 | - "neon_int_1,\ | ||
| 1135 | - neon_int_4,\ | ||
| 1136 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1137 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1138 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1139 | - neon_mla_qqq_8_16,\ | ||
| 1140 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1141 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1142 | - neon_fp_vmla_ddd,\ | ||
| 1143 | - neon_fp_vmla_qqq,\ | ||
| 1144 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1145 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1146 | - | ||
| 1147 | -(define_bypass 3 "neon_vqneg_vqabs" | ||
| 1148 | - "neon_int_1,\ | ||
| 1149 | - neon_int_4,\ | ||
| 1150 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1151 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1152 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1153 | - neon_mla_qqq_8_16,\ | ||
| 1154 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1155 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1156 | - neon_fp_vmla_ddd,\ | ||
| 1157 | - neon_fp_vmla_qqq,\ | ||
| 1158 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1159 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1160 | - | ||
| 1161 | -(define_bypass 3 "neon_int_5" | ||
| 1162 | - "neon_int_1,\ | ||
| 1163 | - neon_int_4,\ | ||
| 1164 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1165 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1166 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1167 | - neon_mla_qqq_8_16,\ | ||
| 1168 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1169 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1170 | - neon_fp_vmla_ddd,\ | ||
| 1171 | - neon_fp_vmla_qqq,\ | ||
| 1172 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1173 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1174 | - | ||
| 1175 | -(define_bypass 3 "neon_int_4" | ||
| 1176 | - "neon_int_1,\ | ||
| 1177 | - neon_int_4,\ | ||
| 1178 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1179 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1180 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1181 | - neon_mla_qqq_8_16,\ | ||
| 1182 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1183 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1184 | - neon_fp_vmla_ddd,\ | ||
| 1185 | - neon_fp_vmla_qqq,\ | ||
| 1186 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1187 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1188 | - | ||
| 1189 | -(define_bypass 2 "neon_int_3" | ||
| 1190 | - "neon_int_1,\ | ||
| 1191 | - neon_int_4,\ | ||
| 1192 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1193 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1194 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1195 | - neon_mla_qqq_8_16,\ | ||
| 1196 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1197 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1198 | - neon_fp_vmla_ddd,\ | ||
| 1199 | - neon_fp_vmla_qqq,\ | ||
| 1200 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1201 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1202 | - | ||
| 1203 | -(define_bypass 2 "neon_int_2" | ||
| 1204 | - "neon_int_1,\ | ||
| 1205 | - neon_int_4,\ | ||
| 1206 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1207 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1208 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1209 | - neon_mla_qqq_8_16,\ | ||
| 1210 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1211 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1212 | - neon_fp_vmla_ddd,\ | ||
| 1213 | - neon_fp_vmla_qqq,\ | ||
| 1214 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1215 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1216 | - | ||
| 1217 | -(define_bypass 2 "neon_int_1" | ||
| 1218 | - "neon_int_1,\ | ||
| 1219 | - neon_int_4,\ | ||
| 1220 | - neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1221 | - neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1222 | - neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1223 | - neon_mla_qqq_8_16,\ | ||
| 1224 | - neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1225 | - neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1226 | - neon_fp_vmla_ddd,\ | ||
| 1227 | - neon_fp_vmla_qqq,\ | ||
| 1228 | - neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1229 | - neon_fp_vrecps_vrsqrts_qqq") | ||
| 1230 | +(define_bypass 1 "cortex_a8_neon_mcr_2_mcrr" | ||
| 1231 | + "cortex_a8_neon_int_1,\ | ||
| 1232 | + cortex_a8_neon_int_4,\ | ||
| 1233 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1234 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1235 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1236 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1237 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1238 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1239 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1240 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1241 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1242 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1243 | + | ||
| 1244 | +(define_bypass 1 "cortex_a8_neon_mcr" | ||
| 1245 | + "cortex_a8_neon_int_1,\ | ||
| 1246 | + cortex_a8_neon_int_4,\ | ||
| 1247 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1248 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1249 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1250 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1251 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1252 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1253 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1254 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1255 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1256 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1257 | + | ||
| 1258 | +(define_bypass 2 "cortex_a8_neon_vld3_vld4_all_lanes" | ||
| 1259 | + "cortex_a8_neon_int_1,\ | ||
| 1260 | + cortex_a8_neon_int_4,\ | ||
| 1261 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1262 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1263 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1264 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1265 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1266 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1267 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1268 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1269 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1270 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1271 | + | ||
| 1272 | +(define_bypass 5 "cortex_a8_neon_vld3_vld4_lane" | ||
| 1273 | + "cortex_a8_neon_int_1,\ | ||
| 1274 | + cortex_a8_neon_int_4,\ | ||
| 1275 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1276 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1277 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1278 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1279 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1280 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1281 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1282 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1283 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1284 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1285 | + | ||
| 1286 | +(define_bypass 3 "cortex_a8_neon_vld1_vld2_lane" | ||
| 1287 | + "cortex_a8_neon_int_1,\ | ||
| 1288 | + cortex_a8_neon_int_4,\ | ||
| 1289 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1290 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1291 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1292 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1293 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1294 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1295 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1296 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1297 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1298 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1299 | + | ||
| 1300 | +(define_bypass 4 "cortex_a8_neon_vld3_vld4" | ||
| 1301 | + "cortex_a8_neon_int_1,\ | ||
| 1302 | + cortex_a8_neon_int_4,\ | ||
| 1303 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1304 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1305 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1306 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1307 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1308 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1309 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1310 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1311 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1312 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1313 | + | ||
| 1314 | +(define_bypass 3 "cortex_a8_neon_vld2_4_regs" | ||
| 1315 | + "cortex_a8_neon_int_1,\ | ||
| 1316 | + cortex_a8_neon_int_4,\ | ||
| 1317 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1318 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1319 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1320 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1321 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1322 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1323 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1324 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1325 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1326 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1327 | + | ||
| 1328 | +(define_bypass 2 "cortex_a8_neon_vld2_2_regs_vld1_vld2_all_lanes" | ||
| 1329 | + "cortex_a8_neon_int_1,\ | ||
| 1330 | + cortex_a8_neon_int_4,\ | ||
| 1331 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1332 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1333 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1334 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1335 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1336 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1337 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1338 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1339 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1340 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1341 | + | ||
| 1342 | +(define_bypass 2 "cortex_a8_neon_vld1_3_4_regs" | ||
| 1343 | + "cortex_a8_neon_int_1,\ | ||
| 1344 | + cortex_a8_neon_int_4,\ | ||
| 1345 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1346 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1347 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1348 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1349 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1350 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1351 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1352 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1353 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1354 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1355 | + | ||
| 1356 | +(define_bypass 1 "cortex_a8_neon_vld1_1_2_regs" | ||
| 1357 | + "cortex_a8_neon_int_1,\ | ||
| 1358 | + cortex_a8_neon_int_4,\ | ||
| 1359 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1360 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1361 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1362 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1363 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1364 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1365 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1366 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1367 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1368 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1369 | + | ||
| 1370 | +(define_bypass 0 "cortex_a8_neon_ldr" | ||
| 1371 | + "cortex_a8_neon_int_1,\ | ||
| 1372 | + cortex_a8_neon_int_4,\ | ||
| 1373 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1374 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1375 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1376 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1377 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1378 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1379 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1380 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1381 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1382 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1383 | + | ||
| 1384 | +(define_bypass 3 "cortex_a8_neon_bp_3cycle" | ||
| 1385 | + "cortex_a8_neon_int_1,\ | ||
| 1386 | + cortex_a8_neon_int_4,\ | ||
| 1387 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1388 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1389 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1390 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1391 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1392 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1393 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1394 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1395 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1396 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1397 | + | ||
| 1398 | +(define_bypass 2 "cortex_a8_neon_bp_2cycle" | ||
| 1399 | + "cortex_a8_neon_int_1,\ | ||
| 1400 | + cortex_a8_neon_int_4,\ | ||
| 1401 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1402 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1403 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1404 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1405 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1406 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1407 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1408 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1409 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1410 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1411 | + | ||
| 1412 | +(define_bypass 1 "cortex_a8_neon_bp_simple" | ||
| 1413 | + "cortex_a8_neon_int_1,\ | ||
| 1414 | + cortex_a8_neon_int_4,\ | ||
| 1415 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1416 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1417 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1418 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1419 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1420 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1421 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1422 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1423 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1424 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1425 | + | ||
| 1426 | +(define_bypass 9 "cortex_a8_neon_fp_vrecps_vrsqrts_qqq" | ||
| 1427 | + "cortex_a8_neon_int_1,\ | ||
| 1428 | + cortex_a8_neon_int_4,\ | ||
| 1429 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1430 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1431 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1432 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1433 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1434 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1435 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1436 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1437 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1438 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1439 | + | ||
| 1440 | +(define_bypass 8 "cortex_a8_neon_fp_vrecps_vrsqrts_ddd" | ||
| 1441 | + "cortex_a8_neon_int_1,\ | ||
| 1442 | + cortex_a8_neon_int_4,\ | ||
| 1443 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1444 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1445 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1446 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1447 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1448 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1449 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1450 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1451 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1452 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1453 | + | ||
| 1454 | +(define_bypass 9 "cortex_a8_neon_fp_vmla_qqq_scalar" | ||
| 1455 | + "cortex_a8_neon_int_1,\ | ||
| 1456 | + cortex_a8_neon_int_4,\ | ||
| 1457 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1458 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1459 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1460 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1461 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1462 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1463 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1464 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1465 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1466 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1467 | + | ||
| 1468 | +(define_bypass 8 "cortex_a8_neon_fp_vmla_ddd_scalar" | ||
| 1469 | + "cortex_a8_neon_int_1,\ | ||
| 1470 | + cortex_a8_neon_int_4,\ | ||
| 1471 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1472 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1473 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1474 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1475 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1476 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1477 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1478 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1479 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1480 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1481 | + | ||
| 1482 | +(define_bypass 9 "cortex_a8_neon_fp_vmla_qqq" | ||
| 1483 | + "cortex_a8_neon_int_1,\ | ||
| 1484 | + cortex_a8_neon_int_4,\ | ||
| 1485 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1486 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1487 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1488 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1489 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1490 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1491 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1492 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1493 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1494 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1495 | + | ||
| 1496 | +(define_bypass 8 "cortex_a8_neon_fp_vmla_ddd" | ||
| 1497 | + "cortex_a8_neon_int_1,\ | ||
| 1498 | + cortex_a8_neon_int_4,\ | ||
| 1499 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1500 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1501 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1502 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1503 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1504 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1505 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1506 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1507 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1508 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1509 | + | ||
| 1510 | +(define_bypass 5 "cortex_a8_neon_fp_vmul_qqd" | ||
| 1511 | + "cortex_a8_neon_int_1,\ | ||
| 1512 | + cortex_a8_neon_int_4,\ | ||
| 1513 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1514 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1515 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1516 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1517 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1518 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1519 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1520 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1521 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1522 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1523 | + | ||
| 1524 | +(define_bypass 4 "cortex_a8_neon_fp_vmul_ddd" | ||
| 1525 | + "cortex_a8_neon_int_1,\ | ||
| 1526 | + cortex_a8_neon_int_4,\ | ||
| 1527 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1528 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1529 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1530 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1531 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1532 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1533 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1534 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1535 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1536 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1537 | + | ||
| 1538 | +(define_bypass 4 "cortex_a8_neon_fp_vsum" | ||
| 1539 | + "cortex_a8_neon_int_1,\ | ||
| 1540 | + cortex_a8_neon_int_4,\ | ||
| 1541 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1542 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1543 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1544 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1545 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1546 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1547 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1548 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1549 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1550 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1551 | + | ||
| 1552 | +(define_bypass 5 "cortex_a8_neon_fp_vadd_qqq_vabs_qq" | ||
| 1553 | + "cortex_a8_neon_int_1,\ | ||
| 1554 | + cortex_a8_neon_int_4,\ | ||
| 1555 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1556 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1557 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1558 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1559 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1560 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1561 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1562 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1563 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1564 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1565 | + | ||
| 1566 | +(define_bypass 4 "cortex_a8_neon_fp_vadd_ddd_vabs_dd" | ||
| 1567 | + "cortex_a8_neon_int_1,\ | ||
| 1568 | + cortex_a8_neon_int_4,\ | ||
| 1569 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1570 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1571 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1572 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1573 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1574 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1575 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1576 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1577 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1578 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1579 | + | ||
| 1580 | +(define_bypass 5 "cortex_a8_neon_vsra_vrsra" | ||
| 1581 | + "cortex_a8_neon_int_1,\ | ||
| 1582 | + cortex_a8_neon_int_4,\ | ||
| 1583 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1584 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1585 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1586 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1587 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1588 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1589 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1590 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1591 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1592 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1593 | + | ||
| 1594 | +(define_bypass 4 "cortex_a8_neon_vqshl_vrshl_vqrshl_qqq" | ||
| 1595 | + "cortex_a8_neon_int_1,\ | ||
| 1596 | + cortex_a8_neon_int_4,\ | ||
| 1597 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1598 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1599 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1600 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1601 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1602 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1603 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1604 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1605 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1606 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1607 | + | ||
| 1608 | +(define_bypass 0 "cortex_a8_neon_vshl_ddd" | ||
| 1609 | + "cortex_a8_neon_int_1,\ | ||
| 1610 | + cortex_a8_neon_int_4,\ | ||
| 1611 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1612 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1613 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1614 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1615 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1616 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1617 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1618 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1619 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1620 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1621 | + | ||
| 1622 | +(define_bypass 3 "cortex_a8_neon_shift_3" | ||
| 1623 | + "cortex_a8_neon_int_1,\ | ||
| 1624 | + cortex_a8_neon_int_4,\ | ||
| 1625 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1626 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1627 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1628 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1629 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1630 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1631 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1632 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1633 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1634 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1635 | + | ||
| 1636 | +(define_bypass 3 "cortex_a8_neon_shift_2" | ||
| 1637 | + "cortex_a8_neon_int_1,\ | ||
| 1638 | + cortex_a8_neon_int_4,\ | ||
| 1639 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1640 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1641 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1642 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1643 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1644 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1645 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1646 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1647 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1648 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1649 | + | ||
| 1650 | +(define_bypass 2 "cortex_a8_neon_shift_1" | ||
| 1651 | + "cortex_a8_neon_int_1,\ | ||
| 1652 | + cortex_a8_neon_int_4,\ | ||
| 1653 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1654 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1655 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1656 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1657 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1658 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1659 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1660 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1661 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1662 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1663 | + | ||
| 1664 | +(define_bypass 5 "cortex_a8_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" | ||
| 1665 | + "cortex_a8_neon_int_1,\ | ||
| 1666 | + cortex_a8_neon_int_4,\ | ||
| 1667 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1668 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1669 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1670 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1671 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1672 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1673 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1674 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1675 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1676 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1677 | + | ||
| 1678 | +(define_bypass 8 "cortex_a8_neon_mul_qqd_32_scalar" | ||
| 1679 | + "cortex_a8_neon_int_1,\ | ||
| 1680 | + cortex_a8_neon_int_4,\ | ||
| 1681 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1682 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1683 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1684 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1685 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1686 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1687 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1688 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1689 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1690 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1691 | + | ||
| 1692 | +(define_bypass 5 "cortex_a8_neon_mul_ddd_16_scalar_32_16_long_scalar" | ||
| 1693 | + "cortex_a8_neon_int_1,\ | ||
| 1694 | + cortex_a8_neon_int_4,\ | ||
| 1695 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1696 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1697 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1698 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1699 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1700 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1701 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1702 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1703 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1704 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1705 | + | ||
| 1706 | +(define_bypass 8 "cortex_a8_neon_mla_qqq_32_qqd_32_scalar" | ||
| 1707 | + "cortex_a8_neon_int_1,\ | ||
| 1708 | + cortex_a8_neon_int_4,\ | ||
| 1709 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1710 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1711 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1712 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1713 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1714 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1715 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1716 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1717 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1718 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1719 | + | ||
| 1720 | +(define_bypass 6 "cortex_a8_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" | ||
| 1721 | + "cortex_a8_neon_int_1,\ | ||
| 1722 | + cortex_a8_neon_int_4,\ | ||
| 1723 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1724 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1725 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1726 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1727 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1728 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1729 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1730 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1731 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1732 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1733 | + | ||
| 1734 | +(define_bypass 6 "cortex_a8_neon_mla_qqq_8_16" | ||
| 1735 | + "cortex_a8_neon_int_1,\ | ||
| 1736 | + cortex_a8_neon_int_4,\ | ||
| 1737 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1738 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1739 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1740 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1741 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1742 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1743 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1744 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1745 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1746 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1747 | + | ||
| 1748 | +(define_bypass 5 "cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" | ||
| 1749 | + "cortex_a8_neon_int_1,\ | ||
| 1750 | + cortex_a8_neon_int_4,\ | ||
| 1751 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1752 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1753 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1754 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1755 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1756 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1757 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1758 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1759 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1760 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1761 | + | ||
| 1762 | +(define_bypass 6 "cortex_a8_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" | ||
| 1763 | + "cortex_a8_neon_int_1,\ | ||
| 1764 | + cortex_a8_neon_int_4,\ | ||
| 1765 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1766 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1767 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1768 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1769 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1770 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1771 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1772 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1773 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1774 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1775 | + | ||
| 1776 | +(define_bypass 6 "cortex_a8_neon_mul_qqq_8_16_32_ddd_32" | ||
| 1777 | + "cortex_a8_neon_int_1,\ | ||
| 1778 | + cortex_a8_neon_int_4,\ | ||
| 1779 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1780 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1781 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1782 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1783 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1784 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1785 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1786 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1787 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1788 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1789 | + | ||
| 1790 | +(define_bypass 5 "cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" | ||
| 1791 | + "cortex_a8_neon_int_1,\ | ||
| 1792 | + cortex_a8_neon_int_4,\ | ||
| 1793 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1794 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1795 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1796 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1797 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1798 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1799 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1800 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1801 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1802 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1803 | + | ||
| 1804 | +(define_bypass 5 "cortex_a8_neon_vsma" | ||
| 1805 | + "cortex_a8_neon_int_1,\ | ||
| 1806 | + cortex_a8_neon_int_4,\ | ||
| 1807 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1808 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1809 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1810 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1811 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1812 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1813 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1814 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1815 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1816 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1817 | + | ||
| 1818 | +(define_bypass 6 "cortex_a8_neon_vaba_qqq" | ||
| 1819 | + "cortex_a8_neon_int_1,\ | ||
| 1820 | + cortex_a8_neon_int_4,\ | ||
| 1821 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1822 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1823 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1824 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1825 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1826 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1827 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1828 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1829 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1830 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1831 | + | ||
| 1832 | +(define_bypass 5 "cortex_a8_neon_vaba" | ||
| 1833 | + "cortex_a8_neon_int_1,\ | ||
| 1834 | + cortex_a8_neon_int_4,\ | ||
| 1835 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1836 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1837 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1838 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1839 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1840 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1841 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1842 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1843 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1844 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1845 | + | ||
| 1846 | +(define_bypass 2 "cortex_a8_neon_vmov" | ||
| 1847 | + "cortex_a8_neon_int_1,\ | ||
| 1848 | + cortex_a8_neon_int_4,\ | ||
| 1849 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1850 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1851 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1852 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1853 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1854 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1855 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1856 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1857 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1858 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1859 | + | ||
| 1860 | +(define_bypass 3 "cortex_a8_neon_vqneg_vqabs" | ||
| 1861 | + "cortex_a8_neon_int_1,\ | ||
| 1862 | + cortex_a8_neon_int_4,\ | ||
| 1863 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1864 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1865 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1866 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1867 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1868 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1869 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1870 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1871 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1872 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1873 | + | ||
| 1874 | +(define_bypass 3 "cortex_a8_neon_int_5" | ||
| 1875 | + "cortex_a8_neon_int_1,\ | ||
| 1876 | + cortex_a8_neon_int_4,\ | ||
| 1877 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1878 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1879 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1880 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1881 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1882 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1883 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1884 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1885 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1886 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1887 | + | ||
| 1888 | +(define_bypass 3 "cortex_a8_neon_int_4" | ||
| 1889 | + "cortex_a8_neon_int_1,\ | ||
| 1890 | + cortex_a8_neon_int_4,\ | ||
| 1891 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1892 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1893 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1894 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1895 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1896 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1897 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1898 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1899 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1900 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1901 | + | ||
| 1902 | +(define_bypass 2 "cortex_a8_neon_int_3" | ||
| 1903 | + "cortex_a8_neon_int_1,\ | ||
| 1904 | + cortex_a8_neon_int_4,\ | ||
| 1905 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1906 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1907 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1908 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1909 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1910 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1911 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1912 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1913 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1914 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1915 | + | ||
| 1916 | +(define_bypass 2 "cortex_a8_neon_int_2" | ||
| 1917 | + "cortex_a8_neon_int_1,\ | ||
| 1918 | + cortex_a8_neon_int_4,\ | ||
| 1919 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1920 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1921 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1922 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1923 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1924 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1925 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1926 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1927 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1928 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1929 | + | ||
| 1930 | +(define_bypass 2 "cortex_a8_neon_int_1" | ||
| 1931 | + "cortex_a8_neon_int_1,\ | ||
| 1932 | + cortex_a8_neon_int_4,\ | ||
| 1933 | + cortex_a8_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1934 | + cortex_a8_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 1935 | + cortex_a8_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 1936 | + cortex_a8_neon_mla_qqq_8_16,\ | ||
| 1937 | + cortex_a8_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 1938 | + cortex_a8_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 1939 | + cortex_a8_neon_fp_vmla_ddd,\ | ||
| 1940 | + cortex_a8_neon_fp_vmla_qqq,\ | ||
| 1941 | + cortex_a8_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 1942 | + cortex_a8_neon_fp_vrecps_vrsqrts_qqq") | ||
| 1943 | |||
| 1944 | |||
| 1945 | === added file 'gcc/config/arm/cortex-a9-neon.md' | ||
| 1946 | --- old/gcc/config/arm/cortex-a9-neon.md 1970-01-01 00:00:00 +0000 | ||
| 1947 | +++ new/gcc/config/arm/cortex-a9-neon.md 2010-09-16 09:47:44 +0000 | ||
| 1948 | @@ -0,0 +1,1237 @@ | ||
| 1949 | +;; ARM Cortex-A9 pipeline description | ||
| 1950 | +;; Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 1951 | +;; | ||
| 1952 | +;; Neon pipeline description contributed by ARM Ltd. | ||
| 1953 | +;; | ||
| 1954 | +;; This file is part of GCC. | ||
| 1955 | +;; | ||
| 1956 | +;; GCC is free software; you can redistribute it and/or modify it | ||
| 1957 | +;; under the terms of the GNU General Public License as published by | ||
| 1958 | +;; the Free Software Foundation; either version 3, or (at your option) | ||
| 1959 | +;; any later version. | ||
| 1960 | +;; | ||
| 1961 | +;; GCC is distributed in the hope that it will be useful, but | ||
| 1962 | +;; WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 1963 | +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 1964 | +;; General Public License for more details. | ||
| 1965 | +;; | ||
| 1966 | +;; You should have received a copy of the GNU General Public License | ||
| 1967 | +;; along with GCC; see the file COPYING3. If not see | ||
| 1968 | +;; <http://www.gnu.org/licenses/>. | ||
| 1969 | + | ||
| 1970 | + | ||
| 1971 | +(define_automaton "cortex_a9_neon") | ||
| 1972 | + | ||
| 1973 | +;; Only one instruction can be issued per cycle. | ||
| 1974 | +(define_cpu_unit "cortex_a9_neon_issue_perm" "cortex_a9_neon") | ||
| 1975 | + | ||
| 1976 | +;; Only one data-processing instruction can be issued per cycle. | ||
| 1977 | +(define_cpu_unit "cortex_a9_neon_issue_dp" "cortex_a9_neon") | ||
| 1978 | + | ||
| 1979 | +;; We need a special mutual exclusion (to be used in addition to | ||
| 1980 | +;; cortex_a9_neon_issue_dp) for the case when an instruction such as | ||
| 1981 | +;; vmla.f is forwarded from E5 of the floating-point multiply pipeline to | ||
| 1982 | +;; E2 of the floating-point add pipeline. On the cycle previous to that | ||
| 1983 | +;; forward we must prevent issue of any instruction to the floating-point | ||
| 1984 | +;; add pipeline, but still allow issue of a data-processing instruction | ||
| 1985 | +;; to any of the other pipelines. | ||
| 1986 | +(define_cpu_unit "cortex_a9_neon_issue_fadd" "cortex_a9_neon") | ||
| 1987 | +(define_cpu_unit "cortex_a9_neon_mcr" "cortex_a9_neon") | ||
| 1988 | + | ||
| 1989 | + | ||
| 1990 | +;; Patterns of reservation. | ||
| 1991 | +;; We model the NEON issue units as running in parallel with the core ones. | ||
| 1992 | +;; We assume that multi-cycle NEON instructions get decomposed into | ||
| 1993 | +;; micro-ops as they are issued into the NEON pipeline. | ||
| 1994 | + | ||
| 1995 | +(define_reservation "cortex_a9_neon_dp" | ||
| 1996 | + "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp") | ||
| 1997 | +(define_reservation "cortex_a9_neon_dp_2" | ||
| 1998 | + "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ | ||
| 1999 | + cortex_a9_neon_issue_dp") | ||
| 2000 | +(define_reservation "cortex_a9_neon_dp_4" | ||
| 2001 | + "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ | ||
| 2002 | + cortex_a9_neon_issue_dp + cortex_a9_neon_issue_perm,\ | ||
| 2003 | + cortex_a9_neon_issue_dp + cortex_a9_neon_issue_perm,\ | ||
| 2004 | + cortex_a9_neon_issue_dp") | ||
| 2005 | + | ||
| 2006 | +(define_reservation "cortex_a9_neon_fadd" | ||
| 2007 | + "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp + \ | ||
| 2008 | + cortex_a9_neon_issue_fadd") | ||
| 2009 | +(define_reservation "cortex_a9_neon_fadd_2" | ||
| 2010 | + "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ | ||
| 2011 | + cortex_a9_neon_issue_fadd,\ | ||
| 2012 | + cortex_a9_neon_issue_dp") | ||
| 2013 | + | ||
| 2014 | +(define_reservation "cortex_a9_neon_perm" | ||
| 2015 | + "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm") | ||
| 2016 | +(define_reservation "cortex_a9_neon_perm_2" | ||
| 2017 | + "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm, \ | ||
| 2018 | + cortex_a9_neon_issue_perm") | ||
| 2019 | +(define_reservation "cortex_a9_neon_perm_3" | ||
| 2020 | + "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\ | ||
| 2021 | + cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ | ||
| 2022 | + cortex_a9_neon_issue_perm") | ||
| 2023 | + | ||
| 2024 | +(define_reservation "cortex_a9_neon_ls" | ||
| 2025 | + "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm+cortex_a9_ls") | ||
| 2026 | +(define_reservation "cortex_a9_neon_ls_2" | ||
| 2027 | + "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\ | ||
| 2028 | + cortex_a9_neon_issue_perm") | ||
| 2029 | +(define_reservation "cortex_a9_neon_ls_3" | ||
| 2030 | + "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\ | ||
| 2031 | + cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ | ||
| 2032 | + cortex_a9_neon_issue_perm") | ||
| 2033 | +(define_reservation "cortex_a9_neon_ls_4" | ||
| 2034 | + "ca9_issue_vfp_neon+cortex_a9_neon_issue_perm,\ | ||
| 2035 | + cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ | ||
| 2036 | + cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ | ||
| 2037 | + cortex_a9_neon_issue_perm") | ||
| 2038 | +(define_reservation "cortex_a9_neon_ls_5" | ||
| 2039 | + "ca9_issue_vfp_neon + cortex_a9_neon_issue_perm,\ | ||
| 2040 | + cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ | ||
| 2041 | + cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ | ||
| 2042 | + cortex_a9_neon_issue_dp+cortex_a9_neon_issue_perm,\ | ||
| 2043 | + cortex_a9_neon_issue_perm") | ||
| 2044 | + | ||
| 2045 | +(define_reservation "cortex_a9_neon_fmul_then_fadd" | ||
| 2046 | + "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ | ||
| 2047 | + nothing*3,\ | ||
| 2048 | + cortex_a9_neon_issue_fadd") | ||
| 2049 | +(define_reservation "cortex_a9_neon_fmul_then_fadd_2" | ||
| 2050 | + "ca9_issue_vfp_neon + cortex_a9_neon_issue_dp,\ | ||
| 2051 | + cortex_a9_neon_issue_dp,\ | ||
| 2052 | + nothing*2,\ | ||
| 2053 | + cortex_a9_neon_issue_fadd,\ | ||
| 2054 | + cortex_a9_neon_issue_fadd") | ||
| 2055 | + | ||
| 2056 | + | ||
| 2057 | +;; NEON -> core transfers. | ||
| 2058 | +(define_insn_reservation "ca9_neon_mrc" 1 | ||
| 2059 | + (and (eq_attr "tune" "cortexa9") | ||
| 2060 | + (eq_attr "neon_type" "neon_mrc")) | ||
| 2061 | + "ca9_issue_vfp_neon + cortex_a9_neon_mcr") | ||
| 2062 | + | ||
| 2063 | +(define_insn_reservation "ca9_neon_mrrc" 1 | ||
| 2064 | + (and (eq_attr "tune" "cortexa9") | ||
| 2065 | + (eq_attr "neon_type" "neon_mrrc")) | ||
| 2066 | + "ca9_issue_vfp_neon + cortex_a9_neon_mcr") | ||
| 2067 | + | ||
| 2068 | +;; The remainder of this file is auto-generated by neon-schedgen. | ||
| 2069 | + | ||
| 2070 | +;; Instructions using this reservation read their source operands at N2, and | ||
| 2071 | +;; produce a result at N3. | ||
| 2072 | +(define_insn_reservation "cortex_a9_neon_int_1" 3 | ||
| 2073 | + (and (eq_attr "tune" "cortexa9") | ||
| 2074 | + (eq_attr "neon_type" "neon_int_1")) | ||
| 2075 | + "cortex_a9_neon_dp") | ||
| 2076 | + | ||
| 2077 | +;; Instructions using this reservation read their (D|Q)m operands at N1, | ||
| 2078 | +;; their (D|Q)n operands at N2, and produce a result at N3. | ||
| 2079 | +(define_insn_reservation "cortex_a9_neon_int_2" 3 | ||
| 2080 | + (and (eq_attr "tune" "cortexa9") | ||
| 2081 | + (eq_attr "neon_type" "neon_int_2")) | ||
| 2082 | + "cortex_a9_neon_dp") | ||
| 2083 | + | ||
| 2084 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2085 | +;; produce a result at N3. | ||
| 2086 | +(define_insn_reservation "cortex_a9_neon_int_3" 3 | ||
| 2087 | + (and (eq_attr "tune" "cortexa9") | ||
| 2088 | + (eq_attr "neon_type" "neon_int_3")) | ||
| 2089 | + "cortex_a9_neon_dp") | ||
| 2090 | + | ||
| 2091 | +;; Instructions using this reservation read their source operands at N2, and | ||
| 2092 | +;; produce a result at N4. | ||
| 2093 | +(define_insn_reservation "cortex_a9_neon_int_4" 4 | ||
| 2094 | + (and (eq_attr "tune" "cortexa9") | ||
| 2095 | + (eq_attr "neon_type" "neon_int_4")) | ||
| 2096 | + "cortex_a9_neon_dp") | ||
| 2097 | + | ||
| 2098 | +;; Instructions using this reservation read their (D|Q)m operands at N1, | ||
| 2099 | +;; their (D|Q)n operands at N2, and produce a result at N4. | ||
| 2100 | +(define_insn_reservation "cortex_a9_neon_int_5" 4 | ||
| 2101 | + (and (eq_attr "tune" "cortexa9") | ||
| 2102 | + (eq_attr "neon_type" "neon_int_5")) | ||
| 2103 | + "cortex_a9_neon_dp") | ||
| 2104 | + | ||
| 2105 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2106 | +;; produce a result at N4. | ||
| 2107 | +(define_insn_reservation "cortex_a9_neon_vqneg_vqabs" 4 | ||
| 2108 | + (and (eq_attr "tune" "cortexa9") | ||
| 2109 | + (eq_attr "neon_type" "neon_vqneg_vqabs")) | ||
| 2110 | + "cortex_a9_neon_dp") | ||
| 2111 | + | ||
| 2112 | +;; Instructions using this reservation produce a result at N3. | ||
| 2113 | +(define_insn_reservation "cortex_a9_neon_vmov" 3 | ||
| 2114 | + (and (eq_attr "tune" "cortexa9") | ||
| 2115 | + (eq_attr "neon_type" "neon_vmov")) | ||
| 2116 | + "cortex_a9_neon_dp") | ||
| 2117 | + | ||
| 2118 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2119 | +;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 2120 | +;; produce a result at N6. | ||
| 2121 | +(define_insn_reservation "cortex_a9_neon_vaba" 6 | ||
| 2122 | + (and (eq_attr "tune" "cortexa9") | ||
| 2123 | + (eq_attr "neon_type" "neon_vaba")) | ||
| 2124 | + "cortex_a9_neon_dp") | ||
| 2125 | + | ||
| 2126 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2127 | +;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 2128 | +;; produce a result at N6 on cycle 2. | ||
| 2129 | +(define_insn_reservation "cortex_a9_neon_vaba_qqq" 7 | ||
| 2130 | + (and (eq_attr "tune" "cortexa9") | ||
| 2131 | + (eq_attr "neon_type" "neon_vaba_qqq")) | ||
| 2132 | + "cortex_a9_neon_dp_2") | ||
| 2133 | + | ||
| 2134 | +;; Instructions using this reservation read their (D|Q)m operands at N1, | ||
| 2135 | +;; their (D|Q)d operands at N3, and produce a result at N6. | ||
| 2136 | +(define_insn_reservation "cortex_a9_neon_vsma" 6 | ||
| 2137 | + (and (eq_attr "tune" "cortexa9") | ||
| 2138 | + (eq_attr "neon_type" "neon_vsma")) | ||
| 2139 | + "cortex_a9_neon_dp") | ||
| 2140 | + | ||
| 2141 | +;; Instructions using this reservation read their source operands at N2, and | ||
| 2142 | +;; produce a result at N6. | ||
| 2143 | +(define_insn_reservation "cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" 6 | ||
| 2144 | + (and (eq_attr "tune" "cortexa9") | ||
| 2145 | + (eq_attr "neon_type" "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")) | ||
| 2146 | + "cortex_a9_neon_dp") | ||
| 2147 | + | ||
| 2148 | +;; Instructions using this reservation read their source operands at N2, and | ||
| 2149 | +;; produce a result at N6 on cycle 2. | ||
| 2150 | +(define_insn_reservation "cortex_a9_neon_mul_qqq_8_16_32_ddd_32" 7 | ||
| 2151 | + (and (eq_attr "tune" "cortexa9") | ||
| 2152 | + (eq_attr "neon_type" "neon_mul_qqq_8_16_32_ddd_32")) | ||
| 2153 | + "cortex_a9_neon_dp_2") | ||
| 2154 | + | ||
| 2155 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2156 | +;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2. | ||
| 2157 | +(define_insn_reservation "cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" 7 | ||
| 2158 | + (and (eq_attr "tune" "cortexa9") | ||
| 2159 | + (eq_attr "neon_type" "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")) | ||
| 2160 | + "cortex_a9_neon_dp_2") | ||
| 2161 | + | ||
| 2162 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2163 | +;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and | ||
| 2164 | +;; produce a result at N6. | ||
| 2165 | +(define_insn_reservation "cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" 6 | ||
| 2166 | + (and (eq_attr "tune" "cortexa9") | ||
| 2167 | + (eq_attr "neon_type" "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")) | ||
| 2168 | + "cortex_a9_neon_dp") | ||
| 2169 | + | ||
| 2170 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2171 | +;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and | ||
| 2172 | +;; produce a result at N6 on cycle 2. | ||
| 2173 | +(define_insn_reservation "cortex_a9_neon_mla_qqq_8_16" 7 | ||
| 2174 | + (and (eq_attr "tune" "cortexa9") | ||
| 2175 | + (eq_attr "neon_type" "neon_mla_qqq_8_16")) | ||
| 2176 | + "cortex_a9_neon_dp_2") | ||
| 2177 | + | ||
| 2178 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2179 | +;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 2180 | +;; produce a result at N6 on cycle 2. | ||
| 2181 | +(define_insn_reservation "cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" 7 | ||
| 2182 | + (and (eq_attr "tune" "cortexa9") | ||
| 2183 | + (eq_attr "neon_type" "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")) | ||
| 2184 | + "cortex_a9_neon_dp_2") | ||
| 2185 | + | ||
| 2186 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2187 | +;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 2188 | +;; produce a result at N6 on cycle 4. | ||
| 2189 | +(define_insn_reservation "cortex_a9_neon_mla_qqq_32_qqd_32_scalar" 9 | ||
| 2190 | + (and (eq_attr "tune" "cortexa9") | ||
| 2191 | + (eq_attr "neon_type" "neon_mla_qqq_32_qqd_32_scalar")) | ||
| 2192 | + "cortex_a9_neon_dp_4") | ||
| 2193 | + | ||
| 2194 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2195 | +;; their (D|Q)m operands at N1, and produce a result at N6. | ||
| 2196 | +(define_insn_reservation "cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar" 6 | ||
| 2197 | + (and (eq_attr "tune" "cortexa9") | ||
| 2198 | + (eq_attr "neon_type" "neon_mul_ddd_16_scalar_32_16_long_scalar")) | ||
| 2199 | + "cortex_a9_neon_dp") | ||
| 2200 | + | ||
| 2201 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2202 | +;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 4. | ||
| 2203 | +(define_insn_reservation "cortex_a9_neon_mul_qqd_32_scalar" 9 | ||
| 2204 | + (and (eq_attr "tune" "cortexa9") | ||
| 2205 | + (eq_attr "neon_type" "neon_mul_qqd_32_scalar")) | ||
| 2206 | + "cortex_a9_neon_dp_4") | ||
| 2207 | + | ||
| 2208 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2209 | +;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 2210 | +;; produce a result at N6. | ||
| 2211 | +(define_insn_reservation "cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" 6 | ||
| 2212 | + (and (eq_attr "tune" "cortexa9") | ||
| 2213 | + (eq_attr "neon_type" "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")) | ||
| 2214 | + "cortex_a9_neon_dp") | ||
| 2215 | + | ||
| 2216 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2217 | +;; produce a result at N3. | ||
| 2218 | +(define_insn_reservation "cortex_a9_neon_shift_1" 3 | ||
| 2219 | + (and (eq_attr "tune" "cortexa9") | ||
| 2220 | + (eq_attr "neon_type" "neon_shift_1")) | ||
| 2221 | + "cortex_a9_neon_dp") | ||
| 2222 | + | ||
| 2223 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2224 | +;; produce a result at N4. | ||
| 2225 | +(define_insn_reservation "cortex_a9_neon_shift_2" 4 | ||
| 2226 | + (and (eq_attr "tune" "cortexa9") | ||
| 2227 | + (eq_attr "neon_type" "neon_shift_2")) | ||
| 2228 | + "cortex_a9_neon_dp") | ||
| 2229 | + | ||
| 2230 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2231 | +;; produce a result at N3 on cycle 2. | ||
| 2232 | +(define_insn_reservation "cortex_a9_neon_shift_3" 4 | ||
| 2233 | + (and (eq_attr "tune" "cortexa9") | ||
| 2234 | + (eq_attr "neon_type" "neon_shift_3")) | ||
| 2235 | + "cortex_a9_neon_dp_2") | ||
| 2236 | + | ||
| 2237 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2238 | +;; produce a result at N1. | ||
| 2239 | +(define_insn_reservation "cortex_a9_neon_vshl_ddd" 1 | ||
| 2240 | + (and (eq_attr "tune" "cortexa9") | ||
| 2241 | + (eq_attr "neon_type" "neon_vshl_ddd")) | ||
| 2242 | + "cortex_a9_neon_dp") | ||
| 2243 | + | ||
| 2244 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2245 | +;; produce a result at N4 on cycle 2. | ||
| 2246 | +(define_insn_reservation "cortex_a9_neon_vqshl_vrshl_vqrshl_qqq" 5 | ||
| 2247 | + (and (eq_attr "tune" "cortexa9") | ||
| 2248 | + (eq_attr "neon_type" "neon_vqshl_vrshl_vqrshl_qqq")) | ||
| 2249 | + "cortex_a9_neon_dp_2") | ||
| 2250 | + | ||
| 2251 | +;; Instructions using this reservation read their (D|Q)m operands at N1, | ||
| 2252 | +;; their (D|Q)d operands at N3, and produce a result at N6. | ||
| 2253 | +(define_insn_reservation "cortex_a9_neon_vsra_vrsra" 6 | ||
| 2254 | + (and (eq_attr "tune" "cortexa9") | ||
| 2255 | + (eq_attr "neon_type" "neon_vsra_vrsra")) | ||
| 2256 | + "cortex_a9_neon_dp") | ||
| 2257 | + | ||
| 2258 | +;; Instructions using this reservation read their source operands at N2, and | ||
| 2259 | +;; produce a result at N5. | ||
| 2260 | +(define_insn_reservation "cortex_a9_neon_fp_vadd_ddd_vabs_dd" 5 | ||
| 2261 | + (and (eq_attr "tune" "cortexa9") | ||
| 2262 | + (eq_attr "neon_type" "neon_fp_vadd_ddd_vabs_dd")) | ||
| 2263 | + "cortex_a9_neon_fadd") | ||
| 2264 | + | ||
| 2265 | +;; Instructions using this reservation read their source operands at N2, and | ||
| 2266 | +;; produce a result at N5 on cycle 2. | ||
| 2267 | +(define_insn_reservation "cortex_a9_neon_fp_vadd_qqq_vabs_qq" 6 | ||
| 2268 | + (and (eq_attr "tune" "cortexa9") | ||
| 2269 | + (eq_attr "neon_type" "neon_fp_vadd_qqq_vabs_qq")) | ||
| 2270 | + "cortex_a9_neon_fadd_2") | ||
| 2271 | + | ||
| 2272 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2273 | +;; produce a result at N5. | ||
| 2274 | +(define_insn_reservation "cortex_a9_neon_fp_vsum" 5 | ||
| 2275 | + (and (eq_attr "tune" "cortexa9") | ||
| 2276 | + (eq_attr "neon_type" "neon_fp_vsum")) | ||
| 2277 | + "cortex_a9_neon_fadd") | ||
| 2278 | + | ||
| 2279 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2280 | +;; their (D|Q)m operands at N1, and produce a result at N5. | ||
| 2281 | +(define_insn_reservation "cortex_a9_neon_fp_vmul_ddd" 5 | ||
| 2282 | + (and (eq_attr "tune" "cortexa9") | ||
| 2283 | + (eq_attr "neon_type" "neon_fp_vmul_ddd")) | ||
| 2284 | + "cortex_a9_neon_dp") | ||
| 2285 | + | ||
| 2286 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2287 | +;; their (D|Q)m operands at N1, and produce a result at N5 on cycle 2. | ||
| 2288 | +(define_insn_reservation "cortex_a9_neon_fp_vmul_qqd" 6 | ||
| 2289 | + (and (eq_attr "tune" "cortexa9") | ||
| 2290 | + (eq_attr "neon_type" "neon_fp_vmul_qqd")) | ||
| 2291 | + "cortex_a9_neon_dp_2") | ||
| 2292 | + | ||
| 2293 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2294 | +;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and | ||
| 2295 | +;; produce a result at N9. | ||
| 2296 | +(define_insn_reservation "cortex_a9_neon_fp_vmla_ddd" 9 | ||
| 2297 | + (and (eq_attr "tune" "cortexa9") | ||
| 2298 | + (eq_attr "neon_type" "neon_fp_vmla_ddd")) | ||
| 2299 | + "cortex_a9_neon_fmul_then_fadd") | ||
| 2300 | + | ||
| 2301 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2302 | +;; their (D|Q)m operands at N2, their (D|Q)d operands at N3, and | ||
| 2303 | +;; produce a result at N9 on cycle 2. | ||
| 2304 | +(define_insn_reservation "cortex_a9_neon_fp_vmla_qqq" 10 | ||
| 2305 | + (and (eq_attr "tune" "cortexa9") | ||
| 2306 | + (eq_attr "neon_type" "neon_fp_vmla_qqq")) | ||
| 2307 | + "cortex_a9_neon_fmul_then_fadd_2") | ||
| 2308 | + | ||
| 2309 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2310 | +;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 2311 | +;; produce a result at N9. | ||
| 2312 | +(define_insn_reservation "cortex_a9_neon_fp_vmla_ddd_scalar" 9 | ||
| 2313 | + (and (eq_attr "tune" "cortexa9") | ||
| 2314 | + (eq_attr "neon_type" "neon_fp_vmla_ddd_scalar")) | ||
| 2315 | + "cortex_a9_neon_fmul_then_fadd") | ||
| 2316 | + | ||
| 2317 | +;; Instructions using this reservation read their (D|Q)n operands at N2, | ||
| 2318 | +;; their (D|Q)m operands at N1, their (D|Q)d operands at N3, and | ||
| 2319 | +;; produce a result at N9 on cycle 2. | ||
| 2320 | +(define_insn_reservation "cortex_a9_neon_fp_vmla_qqq_scalar" 10 | ||
| 2321 | + (and (eq_attr "tune" "cortexa9") | ||
| 2322 | + (eq_attr "neon_type" "neon_fp_vmla_qqq_scalar")) | ||
| 2323 | + "cortex_a9_neon_fmul_then_fadd_2") | ||
| 2324 | + | ||
| 2325 | +;; Instructions using this reservation read their source operands at N2, and | ||
| 2326 | +;; produce a result at N9. | ||
| 2327 | +(define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_ddd" 9 | ||
| 2328 | + (and (eq_attr "tune" "cortexa9") | ||
| 2329 | + (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_ddd")) | ||
| 2330 | + "cortex_a9_neon_fmul_then_fadd") | ||
| 2331 | + | ||
| 2332 | +;; Instructions using this reservation read their source operands at N2, and | ||
| 2333 | +;; produce a result at N9 on cycle 2. | ||
| 2334 | +(define_insn_reservation "cortex_a9_neon_fp_vrecps_vrsqrts_qqq" 10 | ||
| 2335 | + (and (eq_attr "tune" "cortexa9") | ||
| 2336 | + (eq_attr "neon_type" "neon_fp_vrecps_vrsqrts_qqq")) | ||
| 2337 | + "cortex_a9_neon_fmul_then_fadd_2") | ||
| 2338 | + | ||
| 2339 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2340 | +;; produce a result at N2. | ||
| 2341 | +(define_insn_reservation "cortex_a9_neon_bp_simple" 2 | ||
| 2342 | + (and (eq_attr "tune" "cortexa9") | ||
| 2343 | + (eq_attr "neon_type" "neon_bp_simple")) | ||
| 2344 | + "cortex_a9_neon_perm") | ||
| 2345 | + | ||
| 2346 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2347 | +;; produce a result at N2 on cycle 2. | ||
| 2348 | +(define_insn_reservation "cortex_a9_neon_bp_2cycle" 3 | ||
| 2349 | + (and (eq_attr "tune" "cortexa9") | ||
| 2350 | + (eq_attr "neon_type" "neon_bp_2cycle")) | ||
| 2351 | + "cortex_a9_neon_perm_2") | ||
| 2352 | + | ||
| 2353 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2354 | +;; produce a result at N2 on cycle 3. | ||
| 2355 | +(define_insn_reservation "cortex_a9_neon_bp_3cycle" 4 | ||
| 2356 | + (and (eq_attr "tune" "cortexa9") | ||
| 2357 | + (eq_attr "neon_type" "neon_bp_3cycle")) | ||
| 2358 | + "cortex_a9_neon_perm_3") | ||
| 2359 | + | ||
| 2360 | +;; Instructions using this reservation produce a result at N1. | ||
| 2361 | +(define_insn_reservation "cortex_a9_neon_ldr" 1 | ||
| 2362 | + (and (eq_attr "tune" "cortexa9") | ||
| 2363 | + (eq_attr "neon_type" "neon_ldr")) | ||
| 2364 | + "cortex_a9_neon_ls") | ||
| 2365 | + | ||
| 2366 | +;; Instructions using this reservation read their source operands at N1. | ||
| 2367 | +(define_insn_reservation "cortex_a9_neon_str" 0 | ||
| 2368 | + (and (eq_attr "tune" "cortexa9") | ||
| 2369 | + (eq_attr "neon_type" "neon_str")) | ||
| 2370 | + "cortex_a9_neon_ls") | ||
| 2371 | + | ||
| 2372 | +;; Instructions using this reservation produce a result at N1 on cycle 2. | ||
| 2373 | +(define_insn_reservation "cortex_a9_neon_vld1_1_2_regs" 2 | ||
| 2374 | + (and (eq_attr "tune" "cortexa9") | ||
| 2375 | + (eq_attr "neon_type" "neon_vld1_1_2_regs")) | ||
| 2376 | + "cortex_a9_neon_ls_2") | ||
| 2377 | + | ||
| 2378 | +;; Instructions using this reservation produce a result at N1 on cycle 3. | ||
| 2379 | +(define_insn_reservation "cortex_a9_neon_vld1_3_4_regs" 3 | ||
| 2380 | + (and (eq_attr "tune" "cortexa9") | ||
| 2381 | + (eq_attr "neon_type" "neon_vld1_3_4_regs")) | ||
| 2382 | + "cortex_a9_neon_ls_3") | ||
| 2383 | + | ||
| 2384 | +;; Instructions using this reservation produce a result at N2 on cycle 2. | ||
| 2385 | +(define_insn_reservation "cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes" 3 | ||
| 2386 | + (and (eq_attr "tune" "cortexa9") | ||
| 2387 | + (eq_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")) | ||
| 2388 | + "cortex_a9_neon_ls_2") | ||
| 2389 | + | ||
| 2390 | +;; Instructions using this reservation produce a result at N2 on cycle 3. | ||
| 2391 | +(define_insn_reservation "cortex_a9_neon_vld2_4_regs" 4 | ||
| 2392 | + (and (eq_attr "tune" "cortexa9") | ||
| 2393 | + (eq_attr "neon_type" "neon_vld2_4_regs")) | ||
| 2394 | + "cortex_a9_neon_ls_3") | ||
| 2395 | + | ||
| 2396 | +;; Instructions using this reservation produce a result at N2 on cycle 4. | ||
| 2397 | +(define_insn_reservation "cortex_a9_neon_vld3_vld4" 5 | ||
| 2398 | + (and (eq_attr "tune" "cortexa9") | ||
| 2399 | + (eq_attr "neon_type" "neon_vld3_vld4")) | ||
| 2400 | + "cortex_a9_neon_ls_4") | ||
| 2401 | + | ||
| 2402 | +;; Instructions using this reservation read their source operands at N1. | ||
| 2403 | +(define_insn_reservation "cortex_a9_neon_vst1_1_2_regs_vst2_2_regs" 0 | ||
| 2404 | + (and (eq_attr "tune" "cortexa9") | ||
| 2405 | + (eq_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")) | ||
| 2406 | + "cortex_a9_neon_ls_2") | ||
| 2407 | + | ||
| 2408 | +;; Instructions using this reservation read their source operands at N1. | ||
| 2409 | +(define_insn_reservation "cortex_a9_neon_vst1_3_4_regs" 0 | ||
| 2410 | + (and (eq_attr "tune" "cortexa9") | ||
| 2411 | + (eq_attr "neon_type" "neon_vst1_3_4_regs")) | ||
| 2412 | + "cortex_a9_neon_ls_3") | ||
| 2413 | + | ||
| 2414 | +;; Instructions using this reservation read their source operands at N1. | ||
| 2415 | +(define_insn_reservation "cortex_a9_neon_vst2_4_regs_vst3_vst4" 0 | ||
| 2416 | + (and (eq_attr "tune" "cortexa9") | ||
| 2417 | + (eq_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")) | ||
| 2418 | + "cortex_a9_neon_ls_4") | ||
| 2419 | + | ||
| 2420 | +;; Instructions using this reservation read their source operands at N1. | ||
| 2421 | +(define_insn_reservation "cortex_a9_neon_vst3_vst4" 0 | ||
| 2422 | + (and (eq_attr "tune" "cortexa9") | ||
| 2423 | + (eq_attr "neon_type" "neon_vst3_vst4")) | ||
| 2424 | + "cortex_a9_neon_ls_4") | ||
| 2425 | + | ||
| 2426 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2427 | +;; produce a result at N2 on cycle 3. | ||
| 2428 | +(define_insn_reservation "cortex_a9_neon_vld1_vld2_lane" 4 | ||
| 2429 | + (and (eq_attr "tune" "cortexa9") | ||
| 2430 | + (eq_attr "neon_type" "neon_vld1_vld2_lane")) | ||
| 2431 | + "cortex_a9_neon_ls_3") | ||
| 2432 | + | ||
| 2433 | +;; Instructions using this reservation read their source operands at N1, and | ||
| 2434 | +;; produce a result at N2 on cycle 5. | ||
| 2435 | +(define_insn_reservation "cortex_a9_neon_vld3_vld4_lane" 6 | ||
| 2436 | + (and (eq_attr "tune" "cortexa9") | ||
| 2437 | + (eq_attr "neon_type" "neon_vld3_vld4_lane")) | ||
| 2438 | + "cortex_a9_neon_ls_5") | ||
| 2439 | + | ||
| 2440 | +;; Instructions using this reservation read their source operands at N1. | ||
| 2441 | +(define_insn_reservation "cortex_a9_neon_vst1_vst2_lane" 0 | ||
| 2442 | + (and (eq_attr "tune" "cortexa9") | ||
| 2443 | + (eq_attr "neon_type" "neon_vst1_vst2_lane")) | ||
| 2444 | + "cortex_a9_neon_ls_2") | ||
| 2445 | + | ||
| 2446 | +;; Instructions using this reservation read their source operands at N1. | ||
| 2447 | +(define_insn_reservation "cortex_a9_neon_vst3_vst4_lane" 0 | ||
| 2448 | + (and (eq_attr "tune" "cortexa9") | ||
| 2449 | + (eq_attr "neon_type" "neon_vst3_vst4_lane")) | ||
| 2450 | + "cortex_a9_neon_ls_3") | ||
| 2451 | + | ||
| 2452 | +;; Instructions using this reservation produce a result at N2 on cycle 2. | ||
| 2453 | +(define_insn_reservation "cortex_a9_neon_vld3_vld4_all_lanes" 3 | ||
| 2454 | + (and (eq_attr "tune" "cortexa9") | ||
| 2455 | + (eq_attr "neon_type" "neon_vld3_vld4_all_lanes")) | ||
| 2456 | + "cortex_a9_neon_ls_3") | ||
| 2457 | + | ||
| 2458 | +;; Instructions using this reservation produce a result at N2. | ||
| 2459 | +(define_insn_reservation "cortex_a9_neon_mcr" 2 | ||
| 2460 | + (and (eq_attr "tune" "cortexa9") | ||
| 2461 | + (eq_attr "neon_type" "neon_mcr")) | ||
| 2462 | + "cortex_a9_neon_perm") | ||
| 2463 | + | ||
| 2464 | +;; Instructions using this reservation produce a result at N2. | ||
| 2465 | +(define_insn_reservation "cortex_a9_neon_mcr_2_mcrr" 2 | ||
| 2466 | + (and (eq_attr "tune" "cortexa9") | ||
| 2467 | + (eq_attr "neon_type" "neon_mcr_2_mcrr")) | ||
| 2468 | + "cortex_a9_neon_perm_2") | ||
| 2469 | + | ||
| 2470 | +;; Exceptions to the default latencies. | ||
| 2471 | + | ||
| 2472 | +(define_bypass 1 "cortex_a9_neon_mcr_2_mcrr" | ||
| 2473 | + "cortex_a9_neon_int_1,\ | ||
| 2474 | + cortex_a9_neon_int_4,\ | ||
| 2475 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2476 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2477 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2478 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2479 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2480 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2481 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2482 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2483 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2484 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2485 | + | ||
| 2486 | +(define_bypass 1 "cortex_a9_neon_mcr" | ||
| 2487 | + "cortex_a9_neon_int_1,\ | ||
| 2488 | + cortex_a9_neon_int_4,\ | ||
| 2489 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2490 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2491 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2492 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2493 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2494 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2495 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2496 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2497 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2498 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2499 | + | ||
| 2500 | +(define_bypass 2 "cortex_a9_neon_vld3_vld4_all_lanes" | ||
| 2501 | + "cortex_a9_neon_int_1,\ | ||
| 2502 | + cortex_a9_neon_int_4,\ | ||
| 2503 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2504 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2505 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2506 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2507 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2508 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2509 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2510 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2511 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2512 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2513 | + | ||
| 2514 | +(define_bypass 5 "cortex_a9_neon_vld3_vld4_lane" | ||
| 2515 | + "cortex_a9_neon_int_1,\ | ||
| 2516 | + cortex_a9_neon_int_4,\ | ||
| 2517 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2518 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2519 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2520 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2521 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2522 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2523 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2524 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2525 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2526 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2527 | + | ||
| 2528 | +(define_bypass 3 "cortex_a9_neon_vld1_vld2_lane" | ||
| 2529 | + "cortex_a9_neon_int_1,\ | ||
| 2530 | + cortex_a9_neon_int_4,\ | ||
| 2531 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2532 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2533 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2534 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2535 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2536 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2537 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2538 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2539 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2540 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2541 | + | ||
| 2542 | +(define_bypass 4 "cortex_a9_neon_vld3_vld4" | ||
| 2543 | + "cortex_a9_neon_int_1,\ | ||
| 2544 | + cortex_a9_neon_int_4,\ | ||
| 2545 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2546 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2547 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2548 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2549 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2550 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2551 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2552 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2553 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2554 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2555 | + | ||
| 2556 | +(define_bypass 3 "cortex_a9_neon_vld2_4_regs" | ||
| 2557 | + "cortex_a9_neon_int_1,\ | ||
| 2558 | + cortex_a9_neon_int_4,\ | ||
| 2559 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2560 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2561 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2562 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2563 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2564 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2565 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2566 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2567 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2568 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2569 | + | ||
| 2570 | +(define_bypass 2 "cortex_a9_neon_vld2_2_regs_vld1_vld2_all_lanes" | ||
| 2571 | + "cortex_a9_neon_int_1,\ | ||
| 2572 | + cortex_a9_neon_int_4,\ | ||
| 2573 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2574 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2575 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2576 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2577 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2578 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2579 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2580 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2581 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2582 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2583 | + | ||
| 2584 | +(define_bypass 2 "cortex_a9_neon_vld1_3_4_regs" | ||
| 2585 | + "cortex_a9_neon_int_1,\ | ||
| 2586 | + cortex_a9_neon_int_4,\ | ||
| 2587 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2588 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2589 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2590 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2591 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2592 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2593 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2594 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2595 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2596 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2597 | + | ||
| 2598 | +(define_bypass 1 "cortex_a9_neon_vld1_1_2_regs" | ||
| 2599 | + "cortex_a9_neon_int_1,\ | ||
| 2600 | + cortex_a9_neon_int_4,\ | ||
| 2601 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2602 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2603 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2604 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2605 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2606 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2607 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2608 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2609 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2610 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2611 | + | ||
| 2612 | +(define_bypass 0 "cortex_a9_neon_ldr" | ||
| 2613 | + "cortex_a9_neon_int_1,\ | ||
| 2614 | + cortex_a9_neon_int_4,\ | ||
| 2615 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2616 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2617 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2618 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2619 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2620 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2621 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2622 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2623 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2624 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2625 | + | ||
| 2626 | +(define_bypass 3 "cortex_a9_neon_bp_3cycle" | ||
| 2627 | + "cortex_a9_neon_int_1,\ | ||
| 2628 | + cortex_a9_neon_int_4,\ | ||
| 2629 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2630 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2631 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2632 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2633 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2634 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2635 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2636 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2637 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2638 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2639 | + | ||
| 2640 | +(define_bypass 2 "cortex_a9_neon_bp_2cycle" | ||
| 2641 | + "cortex_a9_neon_int_1,\ | ||
| 2642 | + cortex_a9_neon_int_4,\ | ||
| 2643 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2644 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2645 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2646 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2647 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2648 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2649 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2650 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2651 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2652 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2653 | + | ||
| 2654 | +(define_bypass 1 "cortex_a9_neon_bp_simple" | ||
| 2655 | + "cortex_a9_neon_int_1,\ | ||
| 2656 | + cortex_a9_neon_int_4,\ | ||
| 2657 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2658 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2659 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2660 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2661 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2662 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2663 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2664 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2665 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2666 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2667 | + | ||
| 2668 | +(define_bypass 9 "cortex_a9_neon_fp_vrecps_vrsqrts_qqq" | ||
| 2669 | + "cortex_a9_neon_int_1,\ | ||
| 2670 | + cortex_a9_neon_int_4,\ | ||
| 2671 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2672 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2673 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2674 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2675 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2676 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2677 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2678 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2679 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2680 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2681 | + | ||
| 2682 | +(define_bypass 8 "cortex_a9_neon_fp_vrecps_vrsqrts_ddd" | ||
| 2683 | + "cortex_a9_neon_int_1,\ | ||
| 2684 | + cortex_a9_neon_int_4,\ | ||
| 2685 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2686 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2687 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2688 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2689 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2690 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2691 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2692 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2693 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2694 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2695 | + | ||
| 2696 | +(define_bypass 9 "cortex_a9_neon_fp_vmla_qqq_scalar" | ||
| 2697 | + "cortex_a9_neon_int_1,\ | ||
| 2698 | + cortex_a9_neon_int_4,\ | ||
| 2699 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2700 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2701 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2702 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2703 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2704 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2705 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2706 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2707 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2708 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2709 | + | ||
| 2710 | +(define_bypass 8 "cortex_a9_neon_fp_vmla_ddd_scalar" | ||
| 2711 | + "cortex_a9_neon_int_1,\ | ||
| 2712 | + cortex_a9_neon_int_4,\ | ||
| 2713 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2714 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2715 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2716 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2717 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2718 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2719 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2720 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2721 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2722 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2723 | + | ||
| 2724 | +(define_bypass 9 "cortex_a9_neon_fp_vmla_qqq" | ||
| 2725 | + "cortex_a9_neon_int_1,\ | ||
| 2726 | + cortex_a9_neon_int_4,\ | ||
| 2727 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2728 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2729 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2730 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2731 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2732 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2733 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2734 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2735 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2736 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2737 | + | ||
| 2738 | +(define_bypass 8 "cortex_a9_neon_fp_vmla_ddd" | ||
| 2739 | + "cortex_a9_neon_int_1,\ | ||
| 2740 | + cortex_a9_neon_int_4,\ | ||
| 2741 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2742 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2743 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2744 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2745 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2746 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2747 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2748 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2749 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2750 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2751 | + | ||
| 2752 | +(define_bypass 5 "cortex_a9_neon_fp_vmul_qqd" | ||
| 2753 | + "cortex_a9_neon_int_1,\ | ||
| 2754 | + cortex_a9_neon_int_4,\ | ||
| 2755 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2756 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2757 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2758 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2759 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2760 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2761 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2762 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2763 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2764 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2765 | + | ||
| 2766 | +(define_bypass 4 "cortex_a9_neon_fp_vmul_ddd" | ||
| 2767 | + "cortex_a9_neon_int_1,\ | ||
| 2768 | + cortex_a9_neon_int_4,\ | ||
| 2769 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2770 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2771 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2772 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2773 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2774 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2775 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2776 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2777 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2778 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2779 | + | ||
| 2780 | +(define_bypass 4 "cortex_a9_neon_fp_vsum" | ||
| 2781 | + "cortex_a9_neon_int_1,\ | ||
| 2782 | + cortex_a9_neon_int_4,\ | ||
| 2783 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2784 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2785 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2786 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2787 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2788 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2789 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2790 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2791 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2792 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2793 | + | ||
| 2794 | +(define_bypass 5 "cortex_a9_neon_fp_vadd_qqq_vabs_qq" | ||
| 2795 | + "cortex_a9_neon_int_1,\ | ||
| 2796 | + cortex_a9_neon_int_4,\ | ||
| 2797 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2798 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2799 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2800 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2801 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2802 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2803 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2804 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2805 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2806 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2807 | + | ||
| 2808 | +(define_bypass 4 "cortex_a9_neon_fp_vadd_ddd_vabs_dd" | ||
| 2809 | + "cortex_a9_neon_int_1,\ | ||
| 2810 | + cortex_a9_neon_int_4,\ | ||
| 2811 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2812 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2813 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2814 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2815 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2816 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2817 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2818 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2819 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2820 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2821 | + | ||
| 2822 | +(define_bypass 5 "cortex_a9_neon_vsra_vrsra" | ||
| 2823 | + "cortex_a9_neon_int_1,\ | ||
| 2824 | + cortex_a9_neon_int_4,\ | ||
| 2825 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2826 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2827 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2828 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2829 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2830 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2831 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2832 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2833 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2834 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2835 | + | ||
| 2836 | +(define_bypass 4 "cortex_a9_neon_vqshl_vrshl_vqrshl_qqq" | ||
| 2837 | + "cortex_a9_neon_int_1,\ | ||
| 2838 | + cortex_a9_neon_int_4,\ | ||
| 2839 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2840 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2841 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2842 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2843 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2844 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2845 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2846 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2847 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2848 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2849 | + | ||
| 2850 | +(define_bypass 0 "cortex_a9_neon_vshl_ddd" | ||
| 2851 | + "cortex_a9_neon_int_1,\ | ||
| 2852 | + cortex_a9_neon_int_4,\ | ||
| 2853 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2854 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2855 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2856 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2857 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2858 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2859 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2860 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2861 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2862 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2863 | + | ||
| 2864 | +(define_bypass 3 "cortex_a9_neon_shift_3" | ||
| 2865 | + "cortex_a9_neon_int_1,\ | ||
| 2866 | + cortex_a9_neon_int_4,\ | ||
| 2867 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2868 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2869 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2870 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2871 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2872 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2873 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2874 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2875 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2876 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2877 | + | ||
| 2878 | +(define_bypass 3 "cortex_a9_neon_shift_2" | ||
| 2879 | + "cortex_a9_neon_int_1,\ | ||
| 2880 | + cortex_a9_neon_int_4,\ | ||
| 2881 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2882 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2883 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2884 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2885 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2886 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2887 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2888 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2889 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2890 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2891 | + | ||
| 2892 | +(define_bypass 2 "cortex_a9_neon_shift_1" | ||
| 2893 | + "cortex_a9_neon_int_1,\ | ||
| 2894 | + cortex_a9_neon_int_4,\ | ||
| 2895 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2896 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2897 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2898 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2899 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2900 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2901 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2902 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2903 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2904 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2905 | + | ||
| 2906 | +(define_bypass 5 "cortex_a9_neon_mla_ddd_16_scalar_qdd_32_16_long_scalar" | ||
| 2907 | + "cortex_a9_neon_int_1,\ | ||
| 2908 | + cortex_a9_neon_int_4,\ | ||
| 2909 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2910 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2911 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2912 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2913 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2914 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2915 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2916 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2917 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2918 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2919 | + | ||
| 2920 | +(define_bypass 8 "cortex_a9_neon_mul_qqd_32_scalar" | ||
| 2921 | + "cortex_a9_neon_int_1,\ | ||
| 2922 | + cortex_a9_neon_int_4,\ | ||
| 2923 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2924 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2925 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2926 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2927 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2928 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2929 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2930 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2931 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2932 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2933 | + | ||
| 2934 | +(define_bypass 5 "cortex_a9_neon_mul_ddd_16_scalar_32_16_long_scalar" | ||
| 2935 | + "cortex_a9_neon_int_1,\ | ||
| 2936 | + cortex_a9_neon_int_4,\ | ||
| 2937 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2938 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2939 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2940 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2941 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2942 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2943 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2944 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2945 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2946 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2947 | + | ||
| 2948 | +(define_bypass 8 "cortex_a9_neon_mla_qqq_32_qqd_32_scalar" | ||
| 2949 | + "cortex_a9_neon_int_1,\ | ||
| 2950 | + cortex_a9_neon_int_4,\ | ||
| 2951 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2952 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2953 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2954 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2955 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2956 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2957 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2958 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2959 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2960 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2961 | + | ||
| 2962 | +(define_bypass 6 "cortex_a9_neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long" | ||
| 2963 | + "cortex_a9_neon_int_1,\ | ||
| 2964 | + cortex_a9_neon_int_4,\ | ||
| 2965 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2966 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2967 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2968 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2969 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2970 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2971 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2972 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2973 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2974 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2975 | + | ||
| 2976 | +(define_bypass 6 "cortex_a9_neon_mla_qqq_8_16" | ||
| 2977 | + "cortex_a9_neon_int_1,\ | ||
| 2978 | + cortex_a9_neon_int_4,\ | ||
| 2979 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2980 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2981 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2982 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2983 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2984 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2985 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 2986 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 2987 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 2988 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 2989 | + | ||
| 2990 | +(define_bypass 5 "cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long" | ||
| 2991 | + "cortex_a9_neon_int_1,\ | ||
| 2992 | + cortex_a9_neon_int_4,\ | ||
| 2993 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2994 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 2995 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 2996 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 2997 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 2998 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 2999 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3000 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3001 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3002 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3003 | + | ||
| 3004 | +(define_bypass 6 "cortex_a9_neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar" | ||
| 3005 | + "cortex_a9_neon_int_1,\ | ||
| 3006 | + cortex_a9_neon_int_4,\ | ||
| 3007 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3008 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3009 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3010 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3011 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3012 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3013 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3014 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3015 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3016 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3017 | + | ||
| 3018 | +(define_bypass 6 "cortex_a9_neon_mul_qqq_8_16_32_ddd_32" | ||
| 3019 | + "cortex_a9_neon_int_1,\ | ||
| 3020 | + cortex_a9_neon_int_4,\ | ||
| 3021 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3022 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3023 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3024 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3025 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3026 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3027 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3028 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3029 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3030 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3031 | + | ||
| 3032 | +(define_bypass 5 "cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long" | ||
| 3033 | + "cortex_a9_neon_int_1,\ | ||
| 3034 | + cortex_a9_neon_int_4,\ | ||
| 3035 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3036 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3037 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3038 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3039 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3040 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3041 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3042 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3043 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3044 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3045 | + | ||
| 3046 | +(define_bypass 5 "cortex_a9_neon_vsma" | ||
| 3047 | + "cortex_a9_neon_int_1,\ | ||
| 3048 | + cortex_a9_neon_int_4,\ | ||
| 3049 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3050 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3051 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3052 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3053 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3054 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3055 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3056 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3057 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3058 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3059 | + | ||
| 3060 | +(define_bypass 6 "cortex_a9_neon_vaba_qqq" | ||
| 3061 | + "cortex_a9_neon_int_1,\ | ||
| 3062 | + cortex_a9_neon_int_4,\ | ||
| 3063 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3064 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3065 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3066 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3067 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3068 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3069 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3070 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3071 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3072 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3073 | + | ||
| 3074 | +(define_bypass 5 "cortex_a9_neon_vaba" | ||
| 3075 | + "cortex_a9_neon_int_1,\ | ||
| 3076 | + cortex_a9_neon_int_4,\ | ||
| 3077 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3078 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3079 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3080 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3081 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3082 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3083 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3084 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3085 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3086 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3087 | + | ||
| 3088 | +(define_bypass 2 "cortex_a9_neon_vmov" | ||
| 3089 | + "cortex_a9_neon_int_1,\ | ||
| 3090 | + cortex_a9_neon_int_4,\ | ||
| 3091 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3092 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3093 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3094 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3095 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3096 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3097 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3098 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3099 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3100 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3101 | + | ||
| 3102 | +(define_bypass 3 "cortex_a9_neon_vqneg_vqabs" | ||
| 3103 | + "cortex_a9_neon_int_1,\ | ||
| 3104 | + cortex_a9_neon_int_4,\ | ||
| 3105 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3106 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3107 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3108 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3109 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3110 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3111 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3112 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3113 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3114 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3115 | + | ||
| 3116 | +(define_bypass 3 "cortex_a9_neon_int_5" | ||
| 3117 | + "cortex_a9_neon_int_1,\ | ||
| 3118 | + cortex_a9_neon_int_4,\ | ||
| 3119 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3120 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3121 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3122 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3123 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3124 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3125 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3126 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3127 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3128 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3129 | + | ||
| 3130 | +(define_bypass 3 "cortex_a9_neon_int_4" | ||
| 3131 | + "cortex_a9_neon_int_1,\ | ||
| 3132 | + cortex_a9_neon_int_4,\ | ||
| 3133 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3134 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3135 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3136 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3137 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3138 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3139 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3140 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3141 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3142 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3143 | + | ||
| 3144 | +(define_bypass 2 "cortex_a9_neon_int_3" | ||
| 3145 | + "cortex_a9_neon_int_1,\ | ||
| 3146 | + cortex_a9_neon_int_4,\ | ||
| 3147 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3148 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3149 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3150 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3151 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3152 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3153 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3154 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3155 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3156 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3157 | + | ||
| 3158 | +(define_bypass 2 "cortex_a9_neon_int_2" | ||
| 3159 | + "cortex_a9_neon_int_1,\ | ||
| 3160 | + cortex_a9_neon_int_4,\ | ||
| 3161 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3162 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3163 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3164 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3165 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3166 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3167 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3168 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3169 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3170 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3171 | + | ||
| 3172 | +(define_bypass 2 "cortex_a9_neon_int_1" | ||
| 3173 | + "cortex_a9_neon_int_1,\ | ||
| 3174 | + cortex_a9_neon_int_4,\ | ||
| 3175 | + cortex_a9_neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3176 | + cortex_a9_neon_mul_qqq_8_16_32_ddd_32,\ | ||
| 3177 | + cortex_a9_neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\ | ||
| 3178 | + cortex_a9_neon_mla_qqq_8_16,\ | ||
| 3179 | + cortex_a9_neon_fp_vadd_ddd_vabs_dd,\ | ||
| 3180 | + cortex_a9_neon_fp_vadd_qqq_vabs_qq,\ | ||
| 3181 | + cortex_a9_neon_fp_vmla_ddd,\ | ||
| 3182 | + cortex_a9_neon_fp_vmla_qqq,\ | ||
| 3183 | + cortex_a9_neon_fp_vrecps_vrsqrts_ddd,\ | ||
| 3184 | + cortex_a9_neon_fp_vrecps_vrsqrts_qqq") | ||
| 3185 | + | ||
| 3186 | |||
| 3187 | === modified file 'gcc/config/arm/cortex-a9.md' | ||
| 3188 | --- old/gcc/config/arm/cortex-a9.md 2010-08-24 13:15:54 +0000 | ||
| 3189 | +++ new/gcc/config/arm/cortex-a9.md 2010-09-16 09:47:44 +0000 | ||
| 3190 | @@ -80,8 +80,9 @@ | ||
| 3191 | (define_insn_reservation "cortex_a9_dp" 2 | ||
| 3192 | (and (eq_attr "tune" "cortexa9") | ||
| 3193 | (ior (eq_attr "type" "alu") | ||
| 3194 | - (and (eq_attr "type" "alu_shift_reg, alu_shift") | ||
| 3195 | - (eq_attr "insn" "mov")))) | ||
| 3196 | + (ior (and (eq_attr "type" "alu_shift_reg, alu_shift") | ||
| 3197 | + (eq_attr "insn" "mov")) | ||
| 3198 | + (eq_attr "neon_type" "none")))) | ||
| 3199 | "cortex_a9_p0_default|cortex_a9_p1_default") | ||
| 3200 | |||
| 3201 | ;; An instruction using the shifter will go down E1. | ||
| 3202 | |||
| 3203 | === modified file 'gcc/config/arm/neon-schedgen.ml' | ||
| 3204 | --- old/gcc/config/arm/neon-schedgen.ml 2010-04-02 18:54:46 +0000 | ||
| 3205 | +++ new/gcc/config/arm/neon-schedgen.ml 2010-09-16 09:47:44 +0000 | ||
| 3206 | @@ -1,7 +1,6 @@ | ||
| 3207 | (* Emission of the core of the Cortex-A8 NEON scheduling description. | ||
| 3208 | Copyright (C) 2007, 2010 Free Software Foundation, Inc. | ||
| 3209 | Contributed by CodeSourcery. | ||
| 3210 | - | ||
| 3211 | This file is part of GCC. | ||
| 3212 | |||
| 3213 | GCC is free software; you can redistribute it and/or modify it under | ||
| 3214 | @@ -21,7 +20,14 @@ | ||
| 3215 | |||
| 3216 | (* This scheduling description generator works as follows. | ||
| 3217 | - Each group of instructions has source and destination requirements | ||
| 3218 | - specified. The source requirements may be specified using | ||
| 3219 | + specified and a list of cores supported. This is then filtered | ||
| 3220 | + and per core scheduler descriptions are generated out. | ||
| 3221 | + The reservations generated are prefixed by the name of the | ||
| 3222 | + core and the check is performed on the basis of what the tuning | ||
| 3223 | + string is. Running this will generate Neon scheduler descriptions | ||
| 3224 | + for all cores supported. | ||
| 3225 | + | ||
| 3226 | + The source requirements may be specified using | ||
| 3227 | Source (the stage at which all source operands not otherwise | ||
| 3228 | described are read), Source_m (the stage at which Rm operands are | ||
| 3229 | read), Source_n (likewise for Rn) and Source_d (likewise for Rd). | ||
| 3230 | @@ -83,6 +89,17 @@ | ||
| 3231 | | Ls of int | ||
| 3232 | | Fmul_then_fadd | Fmul_then_fadd_2 | ||
| 3233 | |||
| 3234 | +type core = CortexA8 | CortexA9 | ||
| 3235 | +let allCores = [CortexA8; CortexA9] | ||
| 3236 | +let coreStr = function | ||
| 3237 | + CortexA8 -> "cortex_a8" | ||
| 3238 | + | CortexA9 -> "cortex_a9" | ||
| 3239 | + | ||
| 3240 | +let tuneStr = function | ||
| 3241 | + CortexA8 -> "cortexa8" | ||
| 3242 | + | CortexA9 -> "cortexa9" | ||
| 3243 | + | ||
| 3244 | + | ||
| 3245 | (* This table must be kept as short as possible by conflating | ||
| 3246 | entries with the same availability behavior. | ||
| 3247 | |||
| 3248 | @@ -90,129 +107,136 @@ | ||
| 3249 | Second components: availability requirements, in the order in which | ||
| 3250 | they should appear in the comments in the .md file. | ||
| 3251 | Third components: reservation info | ||
| 3252 | + Fourth components: List of supported cores. | ||
| 3253 | *) | ||
| 3254 | let availability_table = [ | ||
| 3255 | (* NEON integer ALU instructions. *) | ||
| 3256 | (* vbit vbif vbsl vorr vbic vnot vcls vclz vcnt vadd vand vorr | ||
| 3257 | veor vbic vorn ddd qqq *) | ||
| 3258 | - "neon_int_1", [Source n2; Dest n3], ALU; | ||
| 3259 | + "neon_int_1", [Source n2; Dest n3], ALU, allCores; | ||
| 3260 | (* vadd vsub qqd vsub ddd qqq *) | ||
| 3261 | - "neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU; | ||
| 3262 | + "neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU, allCores; | ||
| 3263 | (* vsum vneg dd qq vadd vsub qdd *) | ||
| 3264 | - "neon_int_3", [Source n1; Dest n3], ALU; | ||
| 3265 | + "neon_int_3", [Source n1; Dest n3], ALU, allCores; | ||
| 3266 | (* vabs vceqz vcgez vcbtz vclez vcltz vadh vradh vsbh vrsbh dqq *) | ||
| 3267 | (* vhadd vrhadd vqadd vtst ddd qqq *) | ||
| 3268 | - "neon_int_4", [Source n2; Dest n4], ALU; | ||
| 3269 | + "neon_int_4", [Source n2; Dest n4], ALU, allCores; | ||
| 3270 | (* vabd qdd vhsub vqsub vabd vceq vcge vcgt vmax vmin vfmx vfmn ddd ddd *) | ||
| 3271 | - "neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU; | ||
| 3272 | + "neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU, allCores; | ||
| 3273 | (* vqneg vqabs dd qq *) | ||
| 3274 | - "neon_vqneg_vqabs", [Source n1; Dest n4], ALU; | ||
| 3275 | + "neon_vqneg_vqabs", [Source n1; Dest n4], ALU, allCores; | ||
| 3276 | (* vmov vmvn *) | ||
| 3277 | - "neon_vmov", [Dest n3], ALU; | ||
| 3278 | + "neon_vmov", [Dest n3], ALU, allCores; | ||
| 3279 | (* vaba *) | ||
| 3280 | - "neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU; | ||
| 3281 | + "neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU, allCores; | ||
| 3282 | "neon_vaba_qqq", | ||
| 3283 | - [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], ALU_2cycle; | ||
| 3284 | + [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], | ||
| 3285 | + ALU_2cycle, allCores; | ||
| 3286 | (* vsma *) | ||
| 3287 | - "neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU; | ||
| 3288 | + "neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU, allCores; | ||
| 3289 | |||
| 3290 | (* NEON integer multiply instructions. *) | ||
| 3291 | (* vmul, vqdmlh, vqrdmlh *) | ||
| 3292 | (* vmul, vqdmul, qdd 16/8 long 32/16 long *) | ||
| 3293 | - "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6], Mul; | ||
| 3294 | - "neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)], Mul_2cycle; | ||
| 3295 | + "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6], | ||
| 3296 | + Mul, allCores; | ||
| 3297 | + "neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)], | ||
| 3298 | + Mul_2cycle, allCores; | ||
| 3299 | (* vmul, vqdmul again *) | ||
| 3300 | "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar", | ||
| 3301 | - [Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle; | ||
| 3302 | + [Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle, allCores; | ||
| 3303 | (* vmla, vmls *) | ||
| 3304 | "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long", | ||
| 3305 | - [Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul; | ||
| 3306 | + [Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul, allCores; | ||
| 3307 | "neon_mla_qqq_8_16", | ||
| 3308 | - [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle; | ||
| 3309 | + [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)], | ||
| 3310 | + Mul_2cycle, allCores; | ||
| 3311 | "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long", | ||
| 3312 | - [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle; | ||
| 3313 | + [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], | ||
| 3314 | + Mul_2cycle, allCores; | ||
| 3315 | "neon_mla_qqq_32_qqd_32_scalar", | ||
| 3316 | - [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)], Mul_4cycle; | ||
| 3317 | + [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)], | ||
| 3318 | + Mul_4cycle, allCores; | ||
| 3319 | (* vmul, vqdmulh, vqrdmulh *) | ||
| 3320 | (* vmul, vqdmul *) | ||
| 3321 | "neon_mul_ddd_16_scalar_32_16_long_scalar", | ||
| 3322 | - [Source_n n2; Source_m n1; Dest n6], Mul; | ||
| 3323 | + [Source_n n2; Source_m n1; Dest n6], Mul, allCores; | ||
| 3324 | "neon_mul_qqd_32_scalar", | ||
| 3325 | - [Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle; | ||
| 3326 | + [Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle, allCores; | ||
| 3327 | (* vmla, vmls *) | ||
| 3328 | (* vmla, vmla, vqdmla, vqdmls *) | ||
| 3329 | "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar", | ||
| 3330 | - [Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul; | ||
| 3331 | + [Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul, allCores; | ||
| 3332 | |||
| 3333 | (* NEON integer shift instructions. *) | ||
| 3334 | (* vshr/vshl immediate, vshr_narrow, vshl_vmvh, vsli_vsri_ddd *) | ||
| 3335 | - "neon_shift_1", [Source n1; Dest n3], Shift; | ||
| 3336 | - (* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow; | ||
| 3337 | + "neon_shift_1", [Source n1; Dest n3], Shift, allCores; | ||
| 3338 | + (* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow, allCores; | ||
| 3339 | vqshl_vrshl_vqrshl_ddd *) | ||
| 3340 | - "neon_shift_2", [Source n1; Dest n4], Shift; | ||
| 3341 | + "neon_shift_2", [Source n1; Dest n4], Shift, allCores; | ||
| 3342 | (* vsli, vsri and vshl for qqq *) | ||
| 3343 | - "neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle; | ||
| 3344 | - "neon_vshl_ddd", [Source n1; Dest n1], Shift; | ||
| 3345 | + "neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle, allCores; | ||
| 3346 | + "neon_vshl_ddd", [Source n1; Dest n1], Shift, allCores; | ||
| 3347 | "neon_vqshl_vrshl_vqrshl_qqq", [Source n1; Dest_n_after (1, n4)], | ||
| 3348 | - Shift_2cycle; | ||
| 3349 | - "neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift; | ||
| 3350 | + Shift_2cycle, allCores; | ||
| 3351 | + "neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift, allCores; | ||
| 3352 | |||
| 3353 | (* NEON floating-point instructions. *) | ||
| 3354 | (* vadd, vsub, vabd, vmul, vceq, vcge, vcgt, vcage, vcagt, vmax, vmin *) | ||
| 3355 | (* vabs, vneg, vceqz, vcgez, vcgtz, vclez, vcltz, vrecpe, vrsqrte, vcvt *) | ||
| 3356 | - "neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd; | ||
| 3357 | + "neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd, allCores; | ||
| 3358 | "neon_fp_vadd_qqq_vabs_qq", [Source n2; Dest_n_after (1, n5)], | ||
| 3359 | - Fadd_2cycle; | ||
| 3360 | + Fadd_2cycle, allCores; | ||
| 3361 | (* vsum, fvmx, vfmn *) | ||
| 3362 | - "neon_fp_vsum", [Source n1; Dest n5], Fadd; | ||
| 3363 | - "neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul; | ||
| 3364 | + "neon_fp_vsum", [Source n1; Dest n5], Fadd, allCores; | ||
| 3365 | + "neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul, allCores; | ||
| 3366 | "neon_fp_vmul_qqd", [Source_n n2; Source_m n1; Dest_n_after (1, n5)], | ||
| 3367 | - Fmul_2cycle; | ||
| 3368 | + Fmul_2cycle, allCores; | ||
| 3369 | (* vmla, vmls *) | ||
| 3370 | "neon_fp_vmla_ddd", | ||
| 3371 | - [Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd; | ||
| 3372 | + [Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd, allCores; | ||
| 3373 | "neon_fp_vmla_qqq", | ||
| 3374 | [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n9)], | ||
| 3375 | - Fmul_then_fadd_2; | ||
| 3376 | + Fmul_then_fadd_2, allCores; | ||
| 3377 | "neon_fp_vmla_ddd_scalar", | ||
| 3378 | - [Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd; | ||
| 3379 | + [Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd, allCores; | ||
| 3380 | "neon_fp_vmla_qqq_scalar", | ||
| 3381 | [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n9)], | ||
| 3382 | - Fmul_then_fadd_2; | ||
| 3383 | - "neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd; | ||
| 3384 | + Fmul_then_fadd_2, allCores; | ||
| 3385 | + "neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd, allCores; | ||
| 3386 | "neon_fp_vrecps_vrsqrts_qqq", [Source n2; Dest_n_after (1, n9)], | ||
| 3387 | - Fmul_then_fadd_2; | ||
| 3388 | + Fmul_then_fadd_2, allCores; | ||
| 3389 | |||
| 3390 | (* NEON byte permute instructions. *) | ||
| 3391 | (* vmov; vtrn and vswp for dd; vzip for dd; vuzp for dd; vrev; vext for dd *) | ||
| 3392 | - "neon_bp_simple", [Source n1; Dest n2], Permute 1; | ||
| 3393 | - (* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1}; | ||
| 3394 | + "neon_bp_simple", [Source n1; Dest n2], Permute 1, allCores; | ||
| 3395 | + (* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1}, allCores; | ||
| 3396 | similarly for vtbx *) | ||
| 3397 | - "neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2; | ||
| 3398 | + "neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2, allCores; | ||
| 3399 | (* all the rest *) | ||
| 3400 | - "neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3; | ||
| 3401 | + "neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3, allCores; | ||
| 3402 | |||
| 3403 | (* NEON load/store instructions. *) | ||
| 3404 | - "neon_ldr", [Dest n1], Ls 1; | ||
| 3405 | - "neon_str", [Source n1], Ls 1; | ||
| 3406 | - "neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2; | ||
| 3407 | - "neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3; | ||
| 3408 | - "neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2; | ||
| 3409 | - "neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3; | ||
| 3410 | - "neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4; | ||
| 3411 | - "neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2; | ||
| 3412 | - "neon_vst1_3_4_regs", [Source n1], Ls 3; | ||
| 3413 | - "neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4; | ||
| 3414 | - "neon_vst3_vst4", [Source n1], Ls 4; | ||
| 3415 | - "neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3; | ||
| 3416 | - "neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5; | ||
| 3417 | - "neon_vst1_vst2_lane", [Source n1], Ls 2; | ||
| 3418 | - "neon_vst3_vst4_lane", [Source n1], Ls 3; | ||
| 3419 | - "neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3; | ||
| 3420 | + "neon_ldr", [Dest n1], Ls 1, allCores; | ||
| 3421 | + "neon_str", [Source n1], Ls 1, allCores; | ||
| 3422 | + "neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2, allCores; | ||
| 3423 | + "neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3, allCores; | ||
| 3424 | + "neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2, allCores; | ||
| 3425 | + "neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3, allCores; | ||
| 3426 | + "neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4, allCores; | ||
| 3427 | + "neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2, allCores; | ||
| 3428 | + "neon_vst1_3_4_regs", [Source n1], Ls 3, allCores; | ||
| 3429 | + "neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4, allCores; | ||
| 3430 | + "neon_vst3_vst4", [Source n1], Ls 4, allCores; | ||
| 3431 | + "neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3, allCores; | ||
| 3432 | + "neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5, allCores; | ||
| 3433 | + "neon_vst1_vst2_lane", [Source n1], Ls 2, allCores; | ||
| 3434 | + "neon_vst3_vst4_lane", [Source n1], Ls 3, allCores; | ||
| 3435 | + "neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3, allCores; | ||
| 3436 | |||
| 3437 | (* NEON register transfer instructions. *) | ||
| 3438 | - "neon_mcr", [Dest n2], Permute 1; | ||
| 3439 | - "neon_mcr_2_mcrr", [Dest n2], Permute 2; | ||
| 3440 | + "neon_mcr", [Dest n2], Permute 1, allCores; | ||
| 3441 | + "neon_mcr_2_mcrr", [Dest n2], Permute 2, allCores; | ||
| 3442 | (* MRC instructions are in the .tpl file. *) | ||
| 3443 | ] | ||
| 3444 | |||
| 3445 | @@ -221,7 +245,7 @@ | ||
| 3446 | required. (It is also possible that an entry in the table has no | ||
| 3447 | source requirements.) *) | ||
| 3448 | let calculate_sources = | ||
| 3449 | - List.map (fun (name, avail, res) -> | ||
| 3450 | + List.map (fun (name, avail, res, cores) -> | ||
| 3451 | let earliest_stage = | ||
| 3452 | List.fold_left | ||
| 3453 | (fun cur -> fun info -> | ||
| 3454 | @@ -331,7 +355,7 @@ | ||
| 3455 | of one bypass from this producer to any particular consumer listed | ||
| 3456 | in LATENCIES.) Use a hash table to collate bypasses with the | ||
| 3457 | same latency and guard. *) | ||
| 3458 | -let collate_bypasses (producer_name, _, _, _) largest latencies = | ||
| 3459 | +let collate_bypasses (producer_name, _, _, _) largest latencies core = | ||
| 3460 | let ht = Hashtbl.create 42 in | ||
| 3461 | let keys = ref [] in | ||
| 3462 | List.iter ( | ||
| 3463 | @@ -350,7 +374,7 @@ | ||
| 3464 | (if (try ignore (Hashtbl.find ht (guard, latency)); false | ||
| 3465 | with Not_found -> true) then | ||
| 3466 | keys := (guard, latency) :: !keys); | ||
| 3467 | - Hashtbl.add ht (guard, latency) consumer | ||
| 3468 | + Hashtbl.add ht (guard, latency) ((coreStr core) ^ "_" ^ consumer) | ||
| 3469 | end | ||
| 3470 | ) latencies; | ||
| 3471 | (* The hash table now has bypasses collated so that ones with the | ||
| 3472 | @@ -372,7 +396,7 @@ | ||
| 3473 | the output in such a way that all bypasses with the same producer | ||
| 3474 | and latency are together, and so that bypasses with the worst-case | ||
| 3475 | latency are ignored. *) | ||
| 3476 | -let worst_case_latencies_and_bypasses = | ||
| 3477 | +let worst_case_latencies_and_bypasses core = | ||
| 3478 | let rec f (worst_acc, bypasses_acc) prev xs = | ||
| 3479 | match xs with | ||
| 3480 | [] -> (worst_acc, bypasses_acc) | ||
| 3481 | @@ -400,7 +424,7 @@ | ||
| 3482 | (* Having got the largest latency, collect all bypasses for | ||
| 3483 | this producer and filter out those with that larger | ||
| 3484 | latency. Record the others for later emission. *) | ||
| 3485 | - let bypasses = collate_bypasses producer largest latencies in | ||
| 3486 | + let bypasses = collate_bypasses producer largest latencies core in | ||
| 3487 | (* Go on to process remaining producers, having noted | ||
| 3488 | the result for this one. *) | ||
| 3489 | f ((producer_name, producer_avail, largest, | ||
| 3490 | @@ -444,14 +468,18 @@ | ||
| 3491 | in | ||
| 3492 | f avail 0 | ||
| 3493 | |||
| 3494 | + | ||
| 3495 | (* Emit a define_insn_reservation for each producer. The latency | ||
| 3496 | written in will be its worst-case latency. *) | ||
| 3497 | -let emit_insn_reservations = | ||
| 3498 | - List.iter ( | ||
| 3499 | +let emit_insn_reservations core = | ||
| 3500 | + let corestring = coreStr core in | ||
| 3501 | + let tunestring = tuneStr core | ||
| 3502 | + in List.iter ( | ||
| 3503 | fun (producer, avail, latency, reservation) -> | ||
| 3504 | write_comment producer avail; | ||
| 3505 | - Printf.printf "(define_insn_reservation \"%s\" %d\n" producer latency; | ||
| 3506 | - Printf.printf " (and (eq_attr \"tune\" \"cortexa8\")\n"; | ||
| 3507 | + Printf.printf "(define_insn_reservation \"%s_%s\" %d\n" | ||
| 3508 | + corestring producer latency; | ||
| 3509 | + Printf.printf " (and (eq_attr \"tune\" \"%s\")\n" tunestring; | ||
| 3510 | Printf.printf " (eq_attr \"neon_type\" \"%s\"))\n" producer; | ||
| 3511 | let str = | ||
| 3512 | match reservation with | ||
| 3513 | @@ -467,7 +495,7 @@ | ||
| 3514 | | Fmul_then_fadd -> "fmul_then_fadd" | ||
| 3515 | | Fmul_then_fadd_2 -> "fmul_then_fadd_2" | ||
| 3516 | in | ||
| 3517 | - Printf.printf " \"cortex_a8_neon_%s\")\n\n" str | ||
| 3518 | + Printf.printf " \"%s_neon_%s\")\n\n" corestring str | ||
| 3519 | ) | ||
| 3520 | |||
| 3521 | (* Given a guard description, return the name of the C function to | ||
| 3522 | @@ -480,10 +508,12 @@ | ||
| 3523 | | Guard_none -> assert false | ||
| 3524 | |||
| 3525 | (* Emit a define_bypass for each bypass. *) | ||
| 3526 | -let emit_bypasses = | ||
| 3527 | +let emit_bypasses core = | ||
| 3528 | List.iter ( | ||
| 3529 | fun (producer, consumers, latency, guard) -> | ||
| 3530 | - Printf.printf "(define_bypass %d \"%s\"\n" latency producer; | ||
| 3531 | + Printf.printf "(define_bypass %d \"%s_%s\"\n" | ||
| 3532 | + latency (coreStr core) producer; | ||
| 3533 | + | ||
| 3534 | if guard = Guard_none then | ||
| 3535 | Printf.printf " \"%s\")\n\n" consumers | ||
| 3536 | else | ||
| 3537 | @@ -493,11 +523,21 @@ | ||
| 3538 | end | ||
| 3539 | ) | ||
| 3540 | |||
| 3541 | + | ||
| 3542 | +let calculate_per_core_availability_table core availability_table = | ||
| 3543 | + let table = calculate_sources availability_table in | ||
| 3544 | + let worst_cases, bypasses = worst_case_latencies_and_bypasses core table in | ||
| 3545 | + emit_insn_reservations core (List.rev worst_cases); | ||
| 3546 | + Printf.printf ";; Exceptions to the default latencies.\n\n"; | ||
| 3547 | + emit_bypasses core bypasses | ||
| 3548 | + | ||
| 3549 | +let calculate_core_availability_table core availability_table = | ||
| 3550 | +let filter_core = List.filter (fun (_, _, _, cores) | ||
| 3551 | + -> List.exists ((=) core) cores) | ||
| 3552 | +in calculate_per_core_availability_table core (filter_core availability_table) | ||
| 3553 | + | ||
| 3554 | + | ||
| 3555 | (* Program entry point. *) | ||
| 3556 | let main = | ||
| 3557 | - let table = calculate_sources availability_table in | ||
| 3558 | - let worst_cases, bypasses = worst_case_latencies_and_bypasses table in | ||
| 3559 | - emit_insn_reservations (List.rev worst_cases); | ||
| 3560 | - Printf.printf ";; Exceptions to the default latencies.\n\n"; | ||
| 3561 | - emit_bypasses bypasses | ||
| 3562 | - | ||
| 3563 | + List.map (fun core -> calculate_core_availability_table | ||
| 3564 | + core availability_table) allCores | ||
| 3565 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99398.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99398.patch deleted file mode 100644 index c332d50fa..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99398.patch +++ /dev/null | |||
| @@ -1,76 +0,0 @@ | |||
| 1 | 2010-09-21 Yao Qi <yao@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from FSF to fix ICE found in LP:635409: | ||
| 4 | |||
| 5 | 2010-07-07 Bernd Schmidt <bernds@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | PR rtl-optimization/44787 | ||
| 9 | * config/arm/arm.md (arith_shiftsi): Allow stack pointer in operand 2. | ||
| 10 | * config/arm/thumb2.md (thumb2_arith_shiftsi): Likewise. | ||
| 11 | |||
| 12 | gcc/testsuite/ | ||
| 13 | PR rtl-optimization/44787 | ||
| 14 | * gcc.c-torture/compile/pr44788.c: New test. | ||
| 15 | * gcc.target/arm/pr44788.c: New test. | ||
| 16 | |||
| 17 | 2010-09-16 Andrew Stubbs <ams@codesourcery.com> | ||
| 18 | |||
| 19 | Backport from FSF: | ||
| 20 | |||
| 21 | === modified file 'gcc/config/arm/arm.md' | ||
| 22 | --- old/gcc/config/arm/arm.md 2010-09-16 09:15:46 +0000 | ||
| 23 | +++ new/gcc/config/arm/arm.md 2010-09-22 05:54:42 +0000 | ||
| 24 | @@ -9268,7 +9268,7 @@ | ||
| 25 | [(match_operator:SI 3 "shift_operator" | ||
| 26 | [(match_operand:SI 4 "s_register_operand" "r") | ||
| 27 | (match_operand:SI 5 "reg_or_int_operand" "rI")]) | ||
| 28 | - (match_operand:SI 2 "s_register_operand" "r")]))] | ||
| 29 | + (match_operand:SI 2 "s_register_operand" "rk")]))] | ||
| 30 | "TARGET_ARM" | ||
| 31 | "%i1%?\\t%0, %2, %4%S3" | ||
| 32 | [(set_attr "predicable" "yes") | ||
| 33 | |||
| 34 | === modified file 'gcc/config/arm/thumb2.md' | ||
| 35 | --- old/gcc/config/arm/thumb2.md 2010-09-01 13:29:58 +0000 | ||
| 36 | +++ new/gcc/config/arm/thumb2.md 2010-09-22 05:54:42 +0000 | ||
| 37 | @@ -467,7 +467,7 @@ | ||
| 38 | [(match_operator:SI 3 "shift_operator" | ||
| 39 | [(match_operand:SI 4 "s_register_operand" "r") | ||
| 40 | (match_operand:SI 5 "const_shift_count" "M")]) | ||
| 41 | - (match_operand:SI 2 "s_register_operand" "r")]))] | ||
| 42 | + (match_operand:SI 2 "s_register_operand" "rk")]))] | ||
| 43 | "TARGET_THUMB2" | ||
| 44 | "%i1%?\\t%0, %2, %4%S3" | ||
| 45 | [(set_attr "predicable" "yes") | ||
| 46 | |||
| 47 | === added file 'gcc/testsuite/gcc.c-torture/compile/pr44788.c' | ||
| 48 | --- old/gcc/testsuite/gcc.c-torture/compile/pr44788.c 1970-01-01 00:00:00 +0000 | ||
| 49 | +++ new/gcc/testsuite/gcc.c-torture/compile/pr44788.c 2010-09-22 05:54:42 +0000 | ||
| 50 | @@ -0,0 +1,8 @@ | ||
| 51 | +void joint_decode(float* mlt_buffer1, int t) { | ||
| 52 | + int i; | ||
| 53 | + float decode_buffer[1060]; | ||
| 54 | + foo(decode_buffer); | ||
| 55 | + for (i=0; i<10 ; i++) { | ||
| 56 | + mlt_buffer1[i] = i * decode_buffer[t]; | ||
| 57 | + } | ||
| 58 | +} | ||
| 59 | |||
| 60 | === added file 'gcc/testsuite/gcc.target/arm/pr44788.c' | ||
| 61 | --- old/gcc/testsuite/gcc.target/arm/pr44788.c 1970-01-01 00:00:00 +0000 | ||
| 62 | +++ new/gcc/testsuite/gcc.target/arm/pr44788.c 2010-09-22 05:54:42 +0000 | ||
| 63 | @@ -0,0 +1,12 @@ | ||
| 64 | +/* { dg-do compile } */ | ||
| 65 | +/* { dg-require-effective-target arm_thumb2_ok } */ | ||
| 66 | +/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */ | ||
| 67 | + | ||
| 68 | +void joint_decode(float* mlt_buffer1, int t) { | ||
| 69 | + int i; | ||
| 70 | + float decode_buffer[1060]; | ||
| 71 | + foo(decode_buffer); | ||
| 72 | + for (i=0; i<10 ; i++) { | ||
| 73 | + mlt_buffer1[i] = i * decode_buffer[t]; | ||
| 74 | + } | ||
| 75 | +} | ||
| 76 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99402.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99402.patch deleted file mode 100644 index 6627a11d4..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99402.patch +++ /dev/null | |||
| @@ -1,1268 +0,0 @@ | |||
| 1 | 2010-09-17 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-07-15 Bernd Schmidt <bernds@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * postreload.c (last_label_ruid, first_index_reg, last_index_reg): | ||
| 9 | New static variables. | ||
| 10 | (reload_combine_recognize_pattern): New static function, broken out | ||
| 11 | of reload_combine. | ||
| 12 | (reload_combine): Use it. Only initialize first_index_reg and | ||
| 13 | last_index_reg once. | ||
| 14 | |||
| 15 | 2010-07-17 Bernd Schmidt <bernds@codesourcery.com> | ||
| 16 | |||
| 17 | PR target/42235 | ||
| 18 | gcc/ | ||
| 19 | * postreload.c (reload_cse_move2add): Return bool, true if anything. | ||
| 20 | changed. All callers changed. | ||
| 21 | (move2add_use_add2_insn): Likewise. | ||
| 22 | (move2add_use_add3_insn): Likewise. | ||
| 23 | (reload_cse_regs): If reload_cse_move2add changed anything, rerun | ||
| 24 | reload_combine. | ||
| 25 | (RELOAD_COMBINE_MAX_USES): Bump to 16. | ||
| 26 | (last_jump_ruid): New static variable. | ||
| 27 | (struct reg_use): New members CONTAINING_MEM and RUID. | ||
| 28 | (reg_state): New members ALL_OFFSETS_MATCH and REAL_STORE_RUID. | ||
| 29 | (reload_combine_split_one_ruid, reload_combine_split_ruids, | ||
| 30 | reload_combine_purge_insn_uses, reload_combine_closest_single_use | ||
| 31 | reload_combine_purge_reg_uses_after_ruid, | ||
| 32 | reload_combine_recognize_const_pattern): New static functions. | ||
| 33 | (reload_combine_recognize_pattern): Verify that ALL_OFFSETS_MATCH | ||
| 34 | is true for our reg and that we have available index regs. | ||
| 35 | (reload_combine_note_use): New args RUID and CONTAINING_MEM. All | ||
| 36 | callers changed. Use them to initialize fields in struct reg_use. | ||
| 37 | (reload_combine): Initialize last_jump_ruid. Be careful when to | ||
| 38 | take PREV_INSN of the scanned insn. Update REAL_STORE_RUID fields. | ||
| 39 | Call reload_combine_recognize_const_pattern. | ||
| 40 | (reload_combine_note_store): Update REAL_STORE_RUID field. | ||
| 41 | |||
| 42 | gcc/testsuite/ | ||
| 43 | * gcc.target/arm/pr42235.c: New test. | ||
| 44 | |||
| 45 | 2010-07-19 Bernd Schmidt <bernds@codesourcery.com> | ||
| 46 | |||
| 47 | gcc/ | ||
| 48 | * postreload.c (reload_combine_closest_single_use): Ignore the | ||
| 49 | number of uses for DEBUG_INSNs. | ||
| 50 | (fixup_debug_insns): New static function. | ||
| 51 | (reload_combine_recognize_const_pattern): Use it. Don't let the | ||
| 52 | main loop be affected by DEBUG_INSNs. | ||
| 53 | Really disallow moving adds past a jump insn. | ||
| 54 | (reload_combine_recognize_pattern): Don't update use_ruid here. | ||
| 55 | (reload_combine_note_use): Do it here. | ||
| 56 | (reload_combine): Use control_flow_insn_p rather than JUMP_P. | ||
| 57 | |||
| 58 | 2010-07-20 Bernd Schmidt <bernds@codesourcery.com> | ||
| 59 | |||
| 60 | gcc/ | ||
| 61 | * postreload.c (fixup_debug_insns): Remove arg REGNO. New args | ||
| 62 | FROM and TO. All callers changed. Don't look for tracked uses, | ||
| 63 | just scan the RTL for DEBUG_INSNs and substitute. | ||
| 64 | (reload_combine_recognize_pattern): Call fixup_debug_insns. | ||
| 65 | (reload_combine): Ignore DEBUG_INSNs. | ||
| 66 | |||
| 67 | 2010-07-22 Bernd Schmidt <bernds@codesourcery.com> | ||
| 68 | |||
| 69 | PR bootstrap/44970 | ||
| 70 | PR middle-end/45009 | ||
| 71 | gcc/ | ||
| 72 | * postreload.c: Include "target.h". | ||
| 73 | (reload_combine_closest_single_use): Don't take DEBUG_INSNs | ||
| 74 | into account. | ||
| 75 | (fixup_debug_insns): Don't copy the rtx. | ||
| 76 | (reload_combine_recognize_const_pattern): DEBUG_INSNs can't have uses. | ||
| 77 | Don't copy when replacing. Call fixup_debug_insns in the case where | ||
| 78 | we merged one add with another. | ||
| 79 | (reload_combine_recognize_pattern): Fail if there aren't any uses. | ||
| 80 | Try harder to determine whether we're picking a valid index register. | ||
| 81 | Don't set store_ruid for an insn we're going to scan in the | ||
| 82 | next iteration. | ||
| 83 | (reload_combine): Remove unused code. | ||
| 84 | (reload_combine_note_use): When updating use information for | ||
| 85 | an old insn, ignore a use that occurs after store_ruid. | ||
| 86 | * Makefile.in (postreload.o): Update dependencies. | ||
| 87 | |||
| 88 | 2010-07-27 Bernd Schmidt <bernds@codesourcery.com> | ||
| 89 | |||
| 90 | gcc/ | ||
| 91 | * postreload.c (reload_combine_recognize_const_pattern): Move test | ||
| 92 | for limiting the insn movement to the right scope. | ||
| 93 | |||
| 94 | 2010-07-27 Bernd Schmidt <bernds@codesourcery.com> | ||
| 95 | |||
| 96 | gcc/ | ||
| 97 | * postreload.c (try_replace_in_use): New static function. | ||
| 98 | (reload_combine_recognize_const_pattern): Use it here. Allow | ||
| 99 | substituting into a final add insn, and substituting into a memory | ||
| 100 | reference in an insn that sets the reg. | ||
| 101 | |||
| 102 | === modified file 'gcc/Makefile.in' | ||
| 103 | Index: gcc-4.5/gcc/Makefile.in | ||
| 104 | =================================================================== | ||
| 105 | --- gcc-4.5.orig/gcc/Makefile.in | ||
| 106 | +++ gcc-4.5/gcc/Makefile.in | ||
| 107 | @@ -3159,7 +3159,7 @@ postreload.o : postreload.c $(CONFIG_H) | ||
| 108 | $(RTL_H) $(REAL_H) $(FLAGS_H) $(EXPR_H) $(OPTABS_H) reload.h $(REGS_H) \ | ||
| 109 | hard-reg-set.h insn-config.h $(BASIC_BLOCK_H) $(RECOG_H) output.h \ | ||
| 110 | $(FUNCTION_H) $(TOPLEV_H) cselib.h $(TM_P_H) $(EXCEPT_H) $(TREE_H) $(MACHMODE_H) \ | ||
| 111 | - $(OBSTACK_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H) | ||
| 112 | + $(OBSTACK_H) $(TARGET_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H) | ||
| 113 | postreload-gcse.o : postreload-gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ | ||
| 114 | $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) insn-config.h \ | ||
| 115 | $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \ | ||
| 116 | Index: gcc-4.5/gcc/postreload.c | ||
| 117 | =================================================================== | ||
| 118 | --- gcc-4.5.orig/gcc/postreload.c | ||
| 119 | +++ gcc-4.5/gcc/postreload.c | ||
| 120 | @@ -44,6 +44,7 @@ along with GCC; see the file COPYING3. | ||
| 121 | #include "toplev.h" | ||
| 122 | #include "except.h" | ||
| 123 | #include "tree.h" | ||
| 124 | +#include "target.h" | ||
| 125 | #include "timevar.h" | ||
| 126 | #include "tree-pass.h" | ||
| 127 | #include "df.h" | ||
| 128 | @@ -56,10 +57,10 @@ static int reload_cse_simplify_set (rtx, | ||
| 129 | static int reload_cse_simplify_operands (rtx, rtx); | ||
| 130 | |||
| 131 | static void reload_combine (void); | ||
| 132 | -static void reload_combine_note_use (rtx *, rtx); | ||
| 133 | +static void reload_combine_note_use (rtx *, rtx, int, rtx); | ||
| 134 | static void reload_combine_note_store (rtx, const_rtx, void *); | ||
| 135 | |||
| 136 | -static void reload_cse_move2add (rtx); | ||
| 137 | +static bool reload_cse_move2add (rtx); | ||
| 138 | static void move2add_note_store (rtx, const_rtx, void *); | ||
| 139 | |||
| 140 | /* Call cse / combine like post-reload optimization phases. | ||
| 141 | @@ -67,11 +68,16 @@ static void move2add_note_store (rtx, co | ||
| 142 | void | ||
| 143 | reload_cse_regs (rtx first ATTRIBUTE_UNUSED) | ||
| 144 | { | ||
| 145 | + bool moves_converted; | ||
| 146 | reload_cse_regs_1 (first); | ||
| 147 | reload_combine (); | ||
| 148 | - reload_cse_move2add (first); | ||
| 149 | + moves_converted = reload_cse_move2add (first); | ||
| 150 | if (flag_expensive_optimizations) | ||
| 151 | - reload_cse_regs_1 (first); | ||
| 152 | + { | ||
| 153 | + if (moves_converted) | ||
| 154 | + reload_combine (); | ||
| 155 | + reload_cse_regs_1 (first); | ||
| 156 | + } | ||
| 157 | } | ||
| 158 | |||
| 159 | /* See whether a single set SET is a noop. */ | ||
| 160 | @@ -660,30 +666,43 @@ reload_cse_simplify_operands (rtx insn, | ||
| 161 | |||
| 162 | /* The maximum number of uses of a register we can keep track of to | ||
| 163 | replace them with reg+reg addressing. */ | ||
| 164 | -#define RELOAD_COMBINE_MAX_USES 6 | ||
| 165 | +#define RELOAD_COMBINE_MAX_USES 16 | ||
| 166 | |||
| 167 | -/* INSN is the insn where a register has been used, and USEP points to the | ||
| 168 | - location of the register within the rtl. */ | ||
| 169 | -struct reg_use { rtx insn, *usep; }; | ||
| 170 | +/* Describes a recorded use of a register. */ | ||
| 171 | +struct reg_use | ||
| 172 | +{ | ||
| 173 | + /* The insn where a register has been used. */ | ||
| 174 | + rtx insn; | ||
| 175 | + /* Points to the memory reference enclosing the use, if any, NULL_RTX | ||
| 176 | + otherwise. */ | ||
| 177 | + rtx containing_mem; | ||
| 178 | + /* Location of the register withing INSN. */ | ||
| 179 | + rtx *usep; | ||
| 180 | + /* The reverse uid of the insn. */ | ||
| 181 | + int ruid; | ||
| 182 | +}; | ||
| 183 | |||
| 184 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | ||
| 185 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | ||
| 186 | - indicates where it becomes live again. | ||
| 187 | + indicates where it is first set or clobbered. | ||
| 188 | Otherwise, USE_INDEX is the index of the last encountered use of the | ||
| 189 | - register (which is first among these we have seen since we scan backwards), | ||
| 190 | - OFFSET contains the constant offset that is added to the register in | ||
| 191 | - all encountered uses, and USE_RUID indicates the first encountered, i.e. | ||
| 192 | - last, of these uses. | ||
| 193 | + register (which is first among these we have seen since we scan backwards). | ||
| 194 | + USE_RUID indicates the first encountered, i.e. last, of these uses. | ||
| 195 | + If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS | ||
| 196 | + with a constant offset; OFFSET contains this constant in that case. | ||
| 197 | STORE_RUID is always meaningful if we only want to use a value in a | ||
| 198 | register in a different place: it denotes the next insn in the insn | ||
| 199 | - stream (i.e. the last encountered) that sets or clobbers the register. */ | ||
| 200 | + stream (i.e. the last encountered) that sets or clobbers the register. | ||
| 201 | + REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */ | ||
| 202 | static struct | ||
| 203 | { | ||
| 204 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | ||
| 205 | - int use_index; | ||
| 206 | rtx offset; | ||
| 207 | + int use_index; | ||
| 208 | int store_ruid; | ||
| 209 | + int real_store_ruid; | ||
| 210 | int use_ruid; | ||
| 211 | + bool all_offsets_match; | ||
| 212 | } reg_state[FIRST_PSEUDO_REGISTER]; | ||
| 213 | |||
| 214 | /* Reverse linear uid. This is increased in reload_combine while scanning | ||
| 215 | @@ -691,42 +710,548 @@ static struct | ||
| 216 | and the store_ruid / use_ruid fields in reg_state. */ | ||
| 217 | static int reload_combine_ruid; | ||
| 218 | |||
| 219 | +/* The RUID of the last label we encountered in reload_combine. */ | ||
| 220 | +static int last_label_ruid; | ||
| 221 | + | ||
| 222 | +/* The RUID of the last jump we encountered in reload_combine. */ | ||
| 223 | +static int last_jump_ruid; | ||
| 224 | + | ||
| 225 | +/* The register numbers of the first and last index register. A value of | ||
| 226 | + -1 in LAST_INDEX_REG indicates that we've previously computed these | ||
| 227 | + values and found no suitable index registers. */ | ||
| 228 | +static int first_index_reg = -1; | ||
| 229 | +static int last_index_reg; | ||
| 230 | + | ||
| 231 | #define LABEL_LIVE(LABEL) \ | ||
| 232 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | ||
| 233 | |||
| 234 | +/* Subroutine of reload_combine_split_ruids, called to fix up a single | ||
| 235 | + ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */ | ||
| 236 | + | ||
| 237 | +static inline void | ||
| 238 | +reload_combine_split_one_ruid (int *pruid, int split_ruid) | ||
| 239 | +{ | ||
| 240 | + if (*pruid > split_ruid) | ||
| 241 | + (*pruid)++; | ||
| 242 | +} | ||
| 243 | + | ||
| 244 | +/* Called when we insert a new insn in a position we've already passed in | ||
| 245 | + the scan. Examine all our state, increasing all ruids that are higher | ||
| 246 | + than SPLIT_RUID by one in order to make room for a new insn. */ | ||
| 247 | + | ||
| 248 | +static void | ||
| 249 | +reload_combine_split_ruids (int split_ruid) | ||
| 250 | +{ | ||
| 251 | + unsigned i; | ||
| 252 | + | ||
| 253 | + reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid); | ||
| 254 | + reload_combine_split_one_ruid (&last_label_ruid, split_ruid); | ||
| 255 | + reload_combine_split_one_ruid (&last_jump_ruid, split_ruid); | ||
| 256 | + | ||
| 257 | + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 258 | + { | ||
| 259 | + int j, idx = reg_state[i].use_index; | ||
| 260 | + reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid); | ||
| 261 | + reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid); | ||
| 262 | + reload_combine_split_one_ruid (®_state[i].real_store_ruid, | ||
| 263 | + split_ruid); | ||
| 264 | + if (idx < 0) | ||
| 265 | + continue; | ||
| 266 | + for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++) | ||
| 267 | + { | ||
| 268 | + reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid, | ||
| 269 | + split_ruid); | ||
| 270 | + } | ||
| 271 | + } | ||
| 272 | +} | ||
| 273 | + | ||
| 274 | +/* Called when we are about to rescan a previously encountered insn with | ||
| 275 | + reload_combine_note_use after modifying some part of it. This clears all | ||
| 276 | + information about uses in that particular insn. */ | ||
| 277 | + | ||
| 278 | +static void | ||
| 279 | +reload_combine_purge_insn_uses (rtx insn) | ||
| 280 | +{ | ||
| 281 | + unsigned i; | ||
| 282 | + | ||
| 283 | + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 284 | + { | ||
| 285 | + int j, k, idx = reg_state[i].use_index; | ||
| 286 | + if (idx < 0) | ||
| 287 | + continue; | ||
| 288 | + j = k = RELOAD_COMBINE_MAX_USES; | ||
| 289 | + while (j-- > idx) | ||
| 290 | + { | ||
| 291 | + if (reg_state[i].reg_use[j].insn != insn) | ||
| 292 | + { | ||
| 293 | + k--; | ||
| 294 | + if (k != j) | ||
| 295 | + reg_state[i].reg_use[k] = reg_state[i].reg_use[j]; | ||
| 296 | + } | ||
| 297 | + } | ||
| 298 | + reg_state[i].use_index = k; | ||
| 299 | + } | ||
| 300 | +} | ||
| 301 | + | ||
| 302 | +/* Called when we need to forget about all uses of REGNO after an insn | ||
| 303 | + which is identified by RUID. */ | ||
| 304 | + | ||
| 305 | +static void | ||
| 306 | +reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid) | ||
| 307 | +{ | ||
| 308 | + int j, k, idx = reg_state[regno].use_index; | ||
| 309 | + if (idx < 0) | ||
| 310 | + return; | ||
| 311 | + j = k = RELOAD_COMBINE_MAX_USES; | ||
| 312 | + while (j-- > idx) | ||
| 313 | + { | ||
| 314 | + if (reg_state[regno].reg_use[j].ruid >= ruid) | ||
| 315 | + { | ||
| 316 | + k--; | ||
| 317 | + if (k != j) | ||
| 318 | + reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j]; | ||
| 319 | + } | ||
| 320 | + } | ||
| 321 | + reg_state[regno].use_index = k; | ||
| 322 | +} | ||
| 323 | + | ||
| 324 | +/* Find the use of REGNO with the ruid that is highest among those | ||
| 325 | + lower than RUID_LIMIT, and return it if it is the only use of this | ||
| 326 | + reg in the insn. Return NULL otherwise. */ | ||
| 327 | + | ||
| 328 | +static struct reg_use * | ||
| 329 | +reload_combine_closest_single_use (unsigned regno, int ruid_limit) | ||
| 330 | +{ | ||
| 331 | + int i, best_ruid = 0; | ||
| 332 | + int use_idx = reg_state[regno].use_index; | ||
| 333 | + struct reg_use *retval; | ||
| 334 | + | ||
| 335 | + if (use_idx < 0) | ||
| 336 | + return NULL; | ||
| 337 | + retval = NULL; | ||
| 338 | + for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 339 | + { | ||
| 340 | + struct reg_use *use = reg_state[regno].reg_use + i; | ||
| 341 | + int this_ruid = use->ruid; | ||
| 342 | + if (this_ruid >= ruid_limit) | ||
| 343 | + continue; | ||
| 344 | + if (this_ruid > best_ruid) | ||
| 345 | + { | ||
| 346 | + best_ruid = this_ruid; | ||
| 347 | + retval = use; | ||
| 348 | + } | ||
| 349 | + else if (this_ruid == best_ruid) | ||
| 350 | + retval = NULL; | ||
| 351 | + } | ||
| 352 | + if (last_label_ruid >= best_ruid) | ||
| 353 | + return NULL; | ||
| 354 | + return retval; | ||
| 355 | +} | ||
| 356 | + | ||
| 357 | +/* After we've moved an add insn, fix up any debug insns that occur | ||
| 358 | + between the old location of the add and the new location. REG is | ||
| 359 | + the destination register of the add insn; REPLACEMENT is the | ||
| 360 | + SET_SRC of the add. FROM and TO specify the range in which we | ||
| 361 | + should make this change on debug insns. */ | ||
| 362 | + | ||
| 363 | +static void | ||
| 364 | +fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to) | ||
| 365 | +{ | ||
| 366 | + rtx insn; | ||
| 367 | + for (insn = from; insn != to; insn = NEXT_INSN (insn)) | ||
| 368 | + { | ||
| 369 | + rtx t; | ||
| 370 | + | ||
| 371 | + if (!DEBUG_INSN_P (insn)) | ||
| 372 | + continue; | ||
| 373 | + | ||
| 374 | + t = INSN_VAR_LOCATION_LOC (insn); | ||
| 375 | + t = simplify_replace_rtx (t, reg, replacement); | ||
| 376 | + validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0); | ||
| 377 | + } | ||
| 378 | +} | ||
| 379 | + | ||
| 380 | +/* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG | ||
| 381 | + with SRC in the insn described by USE, taking costs into account. Return | ||
| 382 | + true if we made the replacement. */ | ||
| 383 | + | ||
| 384 | +static bool | ||
| 385 | +try_replace_in_use (struct reg_use *use, rtx reg, rtx src) | ||
| 386 | +{ | ||
| 387 | + rtx use_insn = use->insn; | ||
| 388 | + rtx mem = use->containing_mem; | ||
| 389 | + bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); | ||
| 390 | + | ||
| 391 | + if (mem != NULL_RTX) | ||
| 392 | + { | ||
| 393 | + addr_space_t as = MEM_ADDR_SPACE (mem); | ||
| 394 | + rtx oldaddr = XEXP (mem, 0); | ||
| 395 | + rtx newaddr = NULL_RTX; | ||
| 396 | + int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed); | ||
| 397 | + int new_cost; | ||
| 398 | + | ||
| 399 | + newaddr = simplify_replace_rtx (oldaddr, reg, src); | ||
| 400 | + if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as)) | ||
| 401 | + { | ||
| 402 | + XEXP (mem, 0) = newaddr; | ||
| 403 | + new_cost = address_cost (newaddr, GET_MODE (mem), as, speed); | ||
| 404 | + XEXP (mem, 0) = oldaddr; | ||
| 405 | + if (new_cost <= old_cost | ||
| 406 | + && validate_change (use_insn, | ||
| 407 | + &XEXP (mem, 0), newaddr, 0)) | ||
| 408 | + return true; | ||
| 409 | + } | ||
| 410 | + } | ||
| 411 | + else | ||
| 412 | + { | ||
| 413 | + rtx new_set = single_set (use_insn); | ||
| 414 | + if (new_set | ||
| 415 | + && REG_P (SET_DEST (new_set)) | ||
| 416 | + && GET_CODE (SET_SRC (new_set)) == PLUS | ||
| 417 | + && REG_P (XEXP (SET_SRC (new_set), 0)) | ||
| 418 | + && CONSTANT_P (XEXP (SET_SRC (new_set), 1))) | ||
| 419 | + { | ||
| 420 | + rtx new_src; | ||
| 421 | + int old_cost = rtx_cost (SET_SRC (new_set), SET, speed); | ||
| 422 | + | ||
| 423 | + gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg)); | ||
| 424 | + new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src); | ||
| 425 | + | ||
| 426 | + if (rtx_cost (new_src, SET, speed) <= old_cost | ||
| 427 | + && validate_change (use_insn, &SET_SRC (new_set), | ||
| 428 | + new_src, 0)) | ||
| 429 | + return true; | ||
| 430 | + } | ||
| 431 | + } | ||
| 432 | + return false; | ||
| 433 | +} | ||
| 434 | + | ||
| 435 | +/* Called by reload_combine when scanning INSN. This function tries to detect | ||
| 436 | + patterns where a constant is added to a register, and the result is used | ||
| 437 | + in an address. | ||
| 438 | + Return true if no further processing is needed on INSN; false if it wasn't | ||
| 439 | + recognized and should be handled normally. */ | ||
| 440 | + | ||
| 441 | +static bool | ||
| 442 | +reload_combine_recognize_const_pattern (rtx insn) | ||
| 443 | +{ | ||
| 444 | + int from_ruid = reload_combine_ruid; | ||
| 445 | + rtx set, pat, reg, src, addreg; | ||
| 446 | + unsigned int regno; | ||
| 447 | + struct reg_use *use; | ||
| 448 | + bool must_move_add; | ||
| 449 | + rtx add_moved_after_insn = NULL_RTX; | ||
| 450 | + int add_moved_after_ruid = 0; | ||
| 451 | + int clobbered_regno = -1; | ||
| 452 | + | ||
| 453 | + set = single_set (insn); | ||
| 454 | + if (set == NULL_RTX) | ||
| 455 | + return false; | ||
| 456 | + | ||
| 457 | + reg = SET_DEST (set); | ||
| 458 | + src = SET_SRC (set); | ||
| 459 | + if (!REG_P (reg) | ||
| 460 | + || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1 | ||
| 461 | + || GET_MODE (reg) != Pmode | ||
| 462 | + || reg == stack_pointer_rtx) | ||
| 463 | + return false; | ||
| 464 | + | ||
| 465 | + regno = REGNO (reg); | ||
| 466 | + | ||
| 467 | + /* We look for a REG1 = REG2 + CONSTANT insn, followed by either | ||
| 468 | + uses of REG1 inside an address, or inside another add insn. If | ||
| 469 | + possible and profitable, merge the addition into subsequent | ||
| 470 | + uses. */ | ||
| 471 | + if (GET_CODE (src) != PLUS | ||
| 472 | + || !REG_P (XEXP (src, 0)) | ||
| 473 | + || !CONSTANT_P (XEXP (src, 1))) | ||
| 474 | + return false; | ||
| 475 | + | ||
| 476 | + addreg = XEXP (src, 0); | ||
| 477 | + must_move_add = rtx_equal_p (reg, addreg); | ||
| 478 | + | ||
| 479 | + pat = PATTERN (insn); | ||
| 480 | + if (must_move_add && set != pat) | ||
| 481 | + { | ||
| 482 | + /* We have to be careful when moving the add; apart from the | ||
| 483 | + single_set there may also be clobbers. Recognize one special | ||
| 484 | + case, that of one clobber alongside the set (likely a clobber | ||
| 485 | + of the CC register). */ | ||
| 486 | + gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL); | ||
| 487 | + if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set | ||
| 488 | + || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER | ||
| 489 | + || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))) | ||
| 490 | + return false; | ||
| 491 | + clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0)); | ||
| 492 | + } | ||
| 493 | + | ||
| 494 | + do | ||
| 495 | + { | ||
| 496 | + use = reload_combine_closest_single_use (regno, from_ruid); | ||
| 497 | + | ||
| 498 | + if (use) | ||
| 499 | + /* Start the search for the next use from here. */ | ||
| 500 | + from_ruid = use->ruid; | ||
| 501 | + | ||
| 502 | + if (use && GET_MODE (*use->usep) == Pmode) | ||
| 503 | + { | ||
| 504 | + bool delete_add = false; | ||
| 505 | + rtx use_insn = use->insn; | ||
| 506 | + int use_ruid = use->ruid; | ||
| 507 | + | ||
| 508 | + /* Avoid moving the add insn past a jump. */ | ||
| 509 | + if (must_move_add && use_ruid <= last_jump_ruid) | ||
| 510 | + break; | ||
| 511 | + | ||
| 512 | + /* If the add clobbers another hard reg in parallel, don't move | ||
| 513 | + it past a real set of this hard reg. */ | ||
| 514 | + if (must_move_add && clobbered_regno >= 0 | ||
| 515 | + && reg_state[clobbered_regno].real_store_ruid >= use_ruid) | ||
| 516 | + break; | ||
| 517 | + | ||
| 518 | + gcc_assert (reg_state[regno].store_ruid <= use_ruid); | ||
| 519 | + /* Avoid moving a use of ADDREG past a point where it is stored. */ | ||
| 520 | + if (reg_state[REGNO (addreg)].store_ruid > use_ruid) | ||
| 521 | + break; | ||
| 522 | + | ||
| 523 | + /* We also must not move the addition past an insn that sets | ||
| 524 | + the same register, unless we can combine two add insns. */ | ||
| 525 | + if (must_move_add && reg_state[regno].store_ruid == use_ruid) | ||
| 526 | + { | ||
| 527 | + if (use->containing_mem == NULL_RTX) | ||
| 528 | + delete_add = true; | ||
| 529 | + else | ||
| 530 | + break; | ||
| 531 | + } | ||
| 532 | + | ||
| 533 | + if (try_replace_in_use (use, reg, src)) | ||
| 534 | + { | ||
| 535 | + reload_combine_purge_insn_uses (use_insn); | ||
| 536 | + reload_combine_note_use (&PATTERN (use_insn), use_insn, | ||
| 537 | + use_ruid, NULL_RTX); | ||
| 538 | + | ||
| 539 | + if (delete_add) | ||
| 540 | + { | ||
| 541 | + fixup_debug_insns (reg, src, insn, use_insn); | ||
| 542 | + delete_insn (insn); | ||
| 543 | + return true; | ||
| 544 | + } | ||
| 545 | + if (must_move_add) | ||
| 546 | + { | ||
| 547 | + add_moved_after_insn = use_insn; | ||
| 548 | + add_moved_after_ruid = use_ruid; | ||
| 549 | + } | ||
| 550 | + continue; | ||
| 551 | + } | ||
| 552 | + } | ||
| 553 | + /* If we get here, we couldn't handle this use. */ | ||
| 554 | + if (must_move_add) | ||
| 555 | + break; | ||
| 556 | + } | ||
| 557 | + while (use); | ||
| 558 | + | ||
| 559 | + if (!must_move_add || add_moved_after_insn == NULL_RTX) | ||
| 560 | + /* Process the add normally. */ | ||
| 561 | + return false; | ||
| 562 | + | ||
| 563 | + fixup_debug_insns (reg, src, insn, add_moved_after_insn); | ||
| 564 | + | ||
| 565 | + reorder_insns (insn, insn, add_moved_after_insn); | ||
| 566 | + reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid); | ||
| 567 | + reload_combine_split_ruids (add_moved_after_ruid - 1); | ||
| 568 | + reload_combine_note_use (&PATTERN (insn), insn, | ||
| 569 | + add_moved_after_ruid, NULL_RTX); | ||
| 570 | + reg_state[regno].store_ruid = add_moved_after_ruid; | ||
| 571 | + | ||
| 572 | + return true; | ||
| 573 | +} | ||
| 574 | + | ||
| 575 | +/* Called by reload_combine when scanning INSN. Try to detect a pattern we | ||
| 576 | + can handle and improve. Return true if no further processing is needed on | ||
| 577 | + INSN; false if it wasn't recognized and should be handled normally. */ | ||
| 578 | + | ||
| 579 | +static bool | ||
| 580 | +reload_combine_recognize_pattern (rtx insn) | ||
| 581 | +{ | ||
| 582 | + rtx set, reg, src; | ||
| 583 | + unsigned int regno; | ||
| 584 | + | ||
| 585 | + set = single_set (insn); | ||
| 586 | + if (set == NULL_RTX) | ||
| 587 | + return false; | ||
| 588 | + | ||
| 589 | + reg = SET_DEST (set); | ||
| 590 | + src = SET_SRC (set); | ||
| 591 | + if (!REG_P (reg) | ||
| 592 | + || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1) | ||
| 593 | + return false; | ||
| 594 | + | ||
| 595 | + regno = REGNO (reg); | ||
| 596 | + | ||
| 597 | + /* Look for (set (REGX) (CONST_INT)) | ||
| 598 | + (set (REGX) (PLUS (REGX) (REGY))) | ||
| 599 | + ... | ||
| 600 | + ... (MEM (REGX)) ... | ||
| 601 | + and convert it to | ||
| 602 | + (set (REGZ) (CONST_INT)) | ||
| 603 | + ... | ||
| 604 | + ... (MEM (PLUS (REGZ) (REGY)))... . | ||
| 605 | + | ||
| 606 | + First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | ||
| 607 | + and that we know all uses of REGX before it dies. | ||
| 608 | + Also, explicitly check that REGX != REGY; our life information | ||
| 609 | + does not yet show whether REGY changes in this insn. */ | ||
| 610 | + | ||
| 611 | + if (GET_CODE (src) == PLUS | ||
| 612 | + && reg_state[regno].all_offsets_match | ||
| 613 | + && last_index_reg != -1 | ||
| 614 | + && REG_P (XEXP (src, 1)) | ||
| 615 | + && rtx_equal_p (XEXP (src, 0), reg) | ||
| 616 | + && !rtx_equal_p (XEXP (src, 1), reg) | ||
| 617 | + && reg_state[regno].use_index >= 0 | ||
| 618 | + && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES | ||
| 619 | + && last_label_ruid < reg_state[regno].use_ruid) | ||
| 620 | + { | ||
| 621 | + rtx base = XEXP (src, 1); | ||
| 622 | + rtx prev = prev_nonnote_insn (insn); | ||
| 623 | + rtx prev_set = prev ? single_set (prev) : NULL_RTX; | ||
| 624 | + rtx index_reg = NULL_RTX; | ||
| 625 | + rtx reg_sum = NULL_RTX; | ||
| 626 | + int i; | ||
| 627 | + | ||
| 628 | + /* Now we need to set INDEX_REG to an index register (denoted as | ||
| 629 | + REGZ in the illustration above) and REG_SUM to the expression | ||
| 630 | + register+register that we want to use to substitute uses of REG | ||
| 631 | + (typically in MEMs) with. First check REG and BASE for being | ||
| 632 | + index registers; we can use them even if they are not dead. */ | ||
| 633 | + if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | ||
| 634 | + || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | ||
| 635 | + REGNO (base))) | ||
| 636 | + { | ||
| 637 | + index_reg = reg; | ||
| 638 | + reg_sum = src; | ||
| 639 | + } | ||
| 640 | + else | ||
| 641 | + { | ||
| 642 | + /* Otherwise, look for a free index register. Since we have | ||
| 643 | + checked above that neither REG nor BASE are index registers, | ||
| 644 | + if we find anything at all, it will be different from these | ||
| 645 | + two registers. */ | ||
| 646 | + for (i = first_index_reg; i <= last_index_reg; i++) | ||
| 647 | + { | ||
| 648 | + if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) | ||
| 649 | + && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | ||
| 650 | + && reg_state[i].store_ruid <= reg_state[regno].use_ruid | ||
| 651 | + && (call_used_regs[i] || df_regs_ever_live_p (i)) | ||
| 652 | + && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM) | ||
| 653 | + && !fixed_regs[i] && !global_regs[i] | ||
| 654 | + && hard_regno_nregs[i][GET_MODE (reg)] == 1 | ||
| 655 | + && targetm.hard_regno_scratch_ok (i)) | ||
| 656 | + { | ||
| 657 | + index_reg = gen_rtx_REG (GET_MODE (reg), i); | ||
| 658 | + reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | ||
| 659 | + break; | ||
| 660 | + } | ||
| 661 | + } | ||
| 662 | + } | ||
| 663 | + | ||
| 664 | + /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that | ||
| 665 | + (REGY), i.e. BASE, is not clobbered before the last use we'll | ||
| 666 | + create. */ | ||
| 667 | + if (reg_sum | ||
| 668 | + && prev_set | ||
| 669 | + && CONST_INT_P (SET_SRC (prev_set)) | ||
| 670 | + && rtx_equal_p (SET_DEST (prev_set), reg) | ||
| 671 | + && (reg_state[REGNO (base)].store_ruid | ||
| 672 | + <= reg_state[regno].use_ruid)) | ||
| 673 | + { | ||
| 674 | + /* Change destination register and, if necessary, the constant | ||
| 675 | + value in PREV, the constant loading instruction. */ | ||
| 676 | + validate_change (prev, &SET_DEST (prev_set), index_reg, 1); | ||
| 677 | + if (reg_state[regno].offset != const0_rtx) | ||
| 678 | + validate_change (prev, | ||
| 679 | + &SET_SRC (prev_set), | ||
| 680 | + GEN_INT (INTVAL (SET_SRC (prev_set)) | ||
| 681 | + + INTVAL (reg_state[regno].offset)), | ||
| 682 | + 1); | ||
| 683 | + | ||
| 684 | + /* Now for every use of REG that we have recorded, replace REG | ||
| 685 | + with REG_SUM. */ | ||
| 686 | + for (i = reg_state[regno].use_index; | ||
| 687 | + i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 688 | + validate_unshare_change (reg_state[regno].reg_use[i].insn, | ||
| 689 | + reg_state[regno].reg_use[i].usep, | ||
| 690 | + /* Each change must have its own | ||
| 691 | + replacement. */ | ||
| 692 | + reg_sum, 1); | ||
| 693 | + | ||
| 694 | + if (apply_change_group ()) | ||
| 695 | + { | ||
| 696 | + struct reg_use *lowest_ruid = NULL; | ||
| 697 | + | ||
| 698 | + /* For every new use of REG_SUM, we have to record the use | ||
| 699 | + of BASE therein, i.e. operand 1. */ | ||
| 700 | + for (i = reg_state[regno].use_index; | ||
| 701 | + i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 702 | + { | ||
| 703 | + struct reg_use *use = reg_state[regno].reg_use + i; | ||
| 704 | + reload_combine_note_use (&XEXP (*use->usep, 1), use->insn, | ||
| 705 | + use->ruid, use->containing_mem); | ||
| 706 | + if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid) | ||
| 707 | + lowest_ruid = use; | ||
| 708 | + } | ||
| 709 | + | ||
| 710 | + fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn); | ||
| 711 | + | ||
| 712 | + /* Delete the reg-reg addition. */ | ||
| 713 | + delete_insn (insn); | ||
| 714 | + | ||
| 715 | + if (reg_state[regno].offset != const0_rtx) | ||
| 716 | + /* Previous REG_EQUIV / REG_EQUAL notes for PREV | ||
| 717 | + are now invalid. */ | ||
| 718 | + remove_reg_equal_equiv_notes (prev); | ||
| 719 | + | ||
| 720 | + reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 721 | + return true; | ||
| 722 | + } | ||
| 723 | + } | ||
| 724 | + } | ||
| 725 | + return false; | ||
| 726 | +} | ||
| 727 | + | ||
| 728 | static void | ||
| 729 | reload_combine (void) | ||
| 730 | { | ||
| 731 | - rtx insn, set; | ||
| 732 | - int first_index_reg = -1; | ||
| 733 | - int last_index_reg = 0; | ||
| 734 | + rtx insn, prev; | ||
| 735 | int i; | ||
| 736 | basic_block bb; | ||
| 737 | unsigned int r; | ||
| 738 | - int last_label_ruid; | ||
| 739 | int min_labelno, n_labels; | ||
| 740 | HARD_REG_SET ever_live_at_start, *label_live; | ||
| 741 | |||
| 742 | - /* If reg+reg can be used in offsetable memory addresses, the main chunk of | ||
| 743 | - reload has already used it where appropriate, so there is no use in | ||
| 744 | - trying to generate it now. */ | ||
| 745 | - if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS) | ||
| 746 | - return; | ||
| 747 | - | ||
| 748 | /* To avoid wasting too much time later searching for an index register, | ||
| 749 | determine the minimum and maximum index register numbers. */ | ||
| 750 | - for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | ||
| 751 | - if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | ||
| 752 | - { | ||
| 753 | - if (first_index_reg == -1) | ||
| 754 | - first_index_reg = r; | ||
| 755 | + if (INDEX_REG_CLASS == NO_REGS) | ||
| 756 | + last_index_reg = -1; | ||
| 757 | + else if (first_index_reg == -1 && last_index_reg == 0) | ||
| 758 | + { | ||
| 759 | + for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | ||
| 760 | + if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | ||
| 761 | + { | ||
| 762 | + if (first_index_reg == -1) | ||
| 763 | + first_index_reg = r; | ||
| 764 | |||
| 765 | - last_index_reg = r; | ||
| 766 | - } | ||
| 767 | + last_index_reg = r; | ||
| 768 | + } | ||
| 769 | |||
| 770 | - /* If no index register is available, we can quit now. */ | ||
| 771 | - if (first_index_reg == -1) | ||
| 772 | - return; | ||
| 773 | + /* If no index register is available, we can quit now. Set LAST_INDEX_REG | ||
| 774 | + to -1 so we'll know to quit early the next time we get here. */ | ||
| 775 | + if (first_index_reg == -1) | ||
| 776 | + { | ||
| 777 | + last_index_reg = -1; | ||
| 778 | + return; | ||
| 779 | + } | ||
| 780 | + } | ||
| 781 | |||
| 782 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime | ||
| 783 | information is a bit fuzzy immediately after reload, but it's | ||
| 784 | @@ -753,20 +1278,23 @@ reload_combine (void) | ||
| 785 | } | ||
| 786 | |||
| 787 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ | ||
| 788 | - last_label_ruid = reload_combine_ruid = 0; | ||
| 789 | + last_label_ruid = last_jump_ruid = reload_combine_ruid = 0; | ||
| 790 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | ||
| 791 | { | ||
| 792 | - reg_state[r].store_ruid = reload_combine_ruid; | ||
| 793 | + reg_state[r].store_ruid = 0; | ||
| 794 | + reg_state[r].real_store_ruid = 0; | ||
| 795 | if (fixed_regs[r]) | ||
| 796 | reg_state[r].use_index = -1; | ||
| 797 | else | ||
| 798 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 799 | } | ||
| 800 | |||
| 801 | - for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | ||
| 802 | + for (insn = get_last_insn (); insn; insn = prev) | ||
| 803 | { | ||
| 804 | rtx note; | ||
| 805 | |||
| 806 | + prev = PREV_INSN (insn); | ||
| 807 | + | ||
| 808 | /* We cannot do our optimization across labels. Invalidating all the use | ||
| 809 | information we have would be costly, so we just note where the label | ||
| 810 | is and then later disable any optimization that would cross it. */ | ||
| 811 | @@ -777,141 +1305,17 @@ reload_combine (void) | ||
| 812 | if (! fixed_regs[r]) | ||
| 813 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 814 | |||
| 815 | - if (! INSN_P (insn)) | ||
| 816 | + if (! NONDEBUG_INSN_P (insn)) | ||
| 817 | continue; | ||
| 818 | |||
| 819 | reload_combine_ruid++; | ||
| 820 | |||
| 821 | - /* Look for (set (REGX) (CONST_INT)) | ||
| 822 | - (set (REGX) (PLUS (REGX) (REGY))) | ||
| 823 | - ... | ||
| 824 | - ... (MEM (REGX)) ... | ||
| 825 | - and convert it to | ||
| 826 | - (set (REGZ) (CONST_INT)) | ||
| 827 | - ... | ||
| 828 | - ... (MEM (PLUS (REGZ) (REGY)))... . | ||
| 829 | - | ||
| 830 | - First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | ||
| 831 | - and that we know all uses of REGX before it dies. | ||
| 832 | - Also, explicitly check that REGX != REGY; our life information | ||
| 833 | - does not yet show whether REGY changes in this insn. */ | ||
| 834 | - set = single_set (insn); | ||
| 835 | - if (set != NULL_RTX | ||
| 836 | - && REG_P (SET_DEST (set)) | ||
| 837 | - && (hard_regno_nregs[REGNO (SET_DEST (set))] | ||
| 838 | - [GET_MODE (SET_DEST (set))] | ||
| 839 | - == 1) | ||
| 840 | - && GET_CODE (SET_SRC (set)) == PLUS | ||
| 841 | - && REG_P (XEXP (SET_SRC (set), 1)) | ||
| 842 | - && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set)) | ||
| 843 | - && !rtx_equal_p (XEXP (SET_SRC (set), 1), SET_DEST (set)) | ||
| 844 | - && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid) | ||
| 845 | - { | ||
| 846 | - rtx reg = SET_DEST (set); | ||
| 847 | - rtx plus = SET_SRC (set); | ||
| 848 | - rtx base = XEXP (plus, 1); | ||
| 849 | - rtx prev = prev_nonnote_nondebug_insn (insn); | ||
| 850 | - rtx prev_set = prev ? single_set (prev) : NULL_RTX; | ||
| 851 | - unsigned int regno = REGNO (reg); | ||
| 852 | - rtx index_reg = NULL_RTX; | ||
| 853 | - rtx reg_sum = NULL_RTX; | ||
| 854 | - | ||
| 855 | - /* Now we need to set INDEX_REG to an index register (denoted as | ||
| 856 | - REGZ in the illustration above) and REG_SUM to the expression | ||
| 857 | - register+register that we want to use to substitute uses of REG | ||
| 858 | - (typically in MEMs) with. First check REG and BASE for being | ||
| 859 | - index registers; we can use them even if they are not dead. */ | ||
| 860 | - if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | ||
| 861 | - || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | ||
| 862 | - REGNO (base))) | ||
| 863 | - { | ||
| 864 | - index_reg = reg; | ||
| 865 | - reg_sum = plus; | ||
| 866 | - } | ||
| 867 | - else | ||
| 868 | - { | ||
| 869 | - /* Otherwise, look for a free index register. Since we have | ||
| 870 | - checked above that neither REG nor BASE are index registers, | ||
| 871 | - if we find anything at all, it will be different from these | ||
| 872 | - two registers. */ | ||
| 873 | - for (i = first_index_reg; i <= last_index_reg; i++) | ||
| 874 | - { | ||
| 875 | - if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | ||
| 876 | - i) | ||
| 877 | - && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | ||
| 878 | - && reg_state[i].store_ruid <= reg_state[regno].use_ruid | ||
| 879 | - && hard_regno_nregs[i][GET_MODE (reg)] == 1) | ||
| 880 | - { | ||
| 881 | - index_reg = gen_rtx_REG (GET_MODE (reg), i); | ||
| 882 | - reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | ||
| 883 | - break; | ||
| 884 | - } | ||
| 885 | - } | ||
| 886 | - } | ||
| 887 | - | ||
| 888 | - /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that | ||
| 889 | - (REGY), i.e. BASE, is not clobbered before the last use we'll | ||
| 890 | - create. */ | ||
| 891 | - if (reg_sum | ||
| 892 | - && prev_set | ||
| 893 | - && CONST_INT_P (SET_SRC (prev_set)) | ||
| 894 | - && rtx_equal_p (SET_DEST (prev_set), reg) | ||
| 895 | - && reg_state[regno].use_index >= 0 | ||
| 896 | - && (reg_state[REGNO (base)].store_ruid | ||
| 897 | - <= reg_state[regno].use_ruid)) | ||
| 898 | - { | ||
| 899 | - int i; | ||
| 900 | - | ||
| 901 | - /* Change destination register and, if necessary, the constant | ||
| 902 | - value in PREV, the constant loading instruction. */ | ||
| 903 | - validate_change (prev, &SET_DEST (prev_set), index_reg, 1); | ||
| 904 | - if (reg_state[regno].offset != const0_rtx) | ||
| 905 | - validate_change (prev, | ||
| 906 | - &SET_SRC (prev_set), | ||
| 907 | - GEN_INT (INTVAL (SET_SRC (prev_set)) | ||
| 908 | - + INTVAL (reg_state[regno].offset)), | ||
| 909 | - 1); | ||
| 910 | + if (control_flow_insn_p (insn)) | ||
| 911 | + last_jump_ruid = reload_combine_ruid; | ||
| 912 | |||
| 913 | - /* Now for every use of REG that we have recorded, replace REG | ||
| 914 | - with REG_SUM. */ | ||
| 915 | - for (i = reg_state[regno].use_index; | ||
| 916 | - i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 917 | - validate_unshare_change (reg_state[regno].reg_use[i].insn, | ||
| 918 | - reg_state[regno].reg_use[i].usep, | ||
| 919 | - /* Each change must have its own | ||
| 920 | - replacement. */ | ||
| 921 | - reg_sum, 1); | ||
| 922 | - | ||
| 923 | - if (apply_change_group ()) | ||
| 924 | - { | ||
| 925 | - /* For every new use of REG_SUM, we have to record the use | ||
| 926 | - of BASE therein, i.e. operand 1. */ | ||
| 927 | - for (i = reg_state[regno].use_index; | ||
| 928 | - i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 929 | - reload_combine_note_use | ||
| 930 | - (&XEXP (*reg_state[regno].reg_use[i].usep, 1), | ||
| 931 | - reg_state[regno].reg_use[i].insn); | ||
| 932 | - | ||
| 933 | - if (reg_state[REGNO (base)].use_ruid | ||
| 934 | - > reg_state[regno].use_ruid) | ||
| 935 | - reg_state[REGNO (base)].use_ruid | ||
| 936 | - = reg_state[regno].use_ruid; | ||
| 937 | - | ||
| 938 | - /* Delete the reg-reg addition. */ | ||
| 939 | - delete_insn (insn); | ||
| 940 | - | ||
| 941 | - if (reg_state[regno].offset != const0_rtx) | ||
| 942 | - /* Previous REG_EQUIV / REG_EQUAL notes for PREV | ||
| 943 | - are now invalid. */ | ||
| 944 | - remove_reg_equal_equiv_notes (prev); | ||
| 945 | - | ||
| 946 | - reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 947 | - reg_state[REGNO (index_reg)].store_ruid | ||
| 948 | - = reload_combine_ruid; | ||
| 949 | - continue; | ||
| 950 | - } | ||
| 951 | - } | ||
| 952 | - } | ||
| 953 | + if (reload_combine_recognize_const_pattern (insn) | ||
| 954 | + || reload_combine_recognize_pattern (insn)) | ||
| 955 | + continue; | ||
| 956 | |||
| 957 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); | ||
| 958 | |||
| 959 | @@ -967,7 +1371,8 @@ reload_combine (void) | ||
| 960 | reg_state[i].use_index = -1; | ||
| 961 | } | ||
| 962 | |||
| 963 | - reload_combine_note_use (&PATTERN (insn), insn); | ||
| 964 | + reload_combine_note_use (&PATTERN (insn), insn, | ||
| 965 | + reload_combine_ruid, NULL_RTX); | ||
| 966 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | ||
| 967 | { | ||
| 968 | if (REG_NOTE_KIND (note) == REG_INC | ||
| 969 | @@ -976,6 +1381,7 @@ reload_combine (void) | ||
| 970 | int regno = REGNO (XEXP (note, 0)); | ||
| 971 | |||
| 972 | reg_state[regno].store_ruid = reload_combine_ruid; | ||
| 973 | + reg_state[regno].real_store_ruid = reload_combine_ruid; | ||
| 974 | reg_state[regno].use_index = -1; | ||
| 975 | } | ||
| 976 | } | ||
| 977 | @@ -985,8 +1391,8 @@ reload_combine (void) | ||
| 978 | } | ||
| 979 | |||
| 980 | /* Check if DST is a register or a subreg of a register; if it is, | ||
| 981 | - update reg_state[regno].store_ruid and reg_state[regno].use_index | ||
| 982 | - accordingly. Called via note_stores from reload_combine. */ | ||
| 983 | + update store_ruid, real_store_ruid and use_index in the reg_state | ||
| 984 | + structure accordingly. Called via note_stores from reload_combine. */ | ||
| 985 | |||
| 986 | static void | ||
| 987 | reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) | ||
| 988 | @@ -1010,14 +1416,14 @@ reload_combine_note_store (rtx dst, cons | ||
| 989 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be | ||
| 990 | careful with registers / register parts that are not full words. | ||
| 991 | Similarly for ZERO_EXTRACT. */ | ||
| 992 | - if (GET_CODE (set) != SET | ||
| 993 | - || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT | ||
| 994 | + if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT | ||
| 995 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) | ||
| 996 | { | ||
| 997 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) | ||
| 998 | { | ||
| 999 | reg_state[i].use_index = -1; | ||
| 1000 | reg_state[i].store_ruid = reload_combine_ruid; | ||
| 1001 | + reg_state[i].real_store_ruid = reload_combine_ruid; | ||
| 1002 | } | ||
| 1003 | } | ||
| 1004 | else | ||
| 1005 | @@ -1025,6 +1431,8 @@ reload_combine_note_store (rtx dst, cons | ||
| 1006 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) | ||
| 1007 | { | ||
| 1008 | reg_state[i].store_ruid = reload_combine_ruid; | ||
| 1009 | + if (GET_CODE (set) == SET) | ||
| 1010 | + reg_state[i].real_store_ruid = reload_combine_ruid; | ||
| 1011 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 1012 | } | ||
| 1013 | } | ||
| 1014 | @@ -1035,7 +1443,7 @@ reload_combine_note_store (rtx dst, cons | ||
| 1015 | *XP is the pattern of INSN, or a part of it. | ||
| 1016 | Called from reload_combine, and recursively by itself. */ | ||
| 1017 | static void | ||
| 1018 | -reload_combine_note_use (rtx *xp, rtx insn) | ||
| 1019 | +reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem) | ||
| 1020 | { | ||
| 1021 | rtx x = *xp; | ||
| 1022 | enum rtx_code code = x->code; | ||
| 1023 | @@ -1048,7 +1456,7 @@ reload_combine_note_use (rtx *xp, rtx in | ||
| 1024 | case SET: | ||
| 1025 | if (REG_P (SET_DEST (x))) | ||
| 1026 | { | ||
| 1027 | - reload_combine_note_use (&SET_SRC (x), insn); | ||
| 1028 | + reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX); | ||
| 1029 | return; | ||
| 1030 | } | ||
| 1031 | break; | ||
| 1032 | @@ -1104,6 +1512,11 @@ reload_combine_note_use (rtx *xp, rtx in | ||
| 1033 | return; | ||
| 1034 | } | ||
| 1035 | |||
| 1036 | + /* We may be called to update uses in previously seen insns. | ||
| 1037 | + Don't add uses beyond the last store we saw. */ | ||
| 1038 | + if (ruid < reg_state[regno].store_ruid) | ||
| 1039 | + return; | ||
| 1040 | + | ||
| 1041 | /* If this register is already used in some unknown fashion, we | ||
| 1042 | can't do anything. | ||
| 1043 | If we decrement the index from zero to -1, we can't store more | ||
| 1044 | @@ -1112,29 +1525,34 @@ reload_combine_note_use (rtx *xp, rtx in | ||
| 1045 | if (use_index < 0) | ||
| 1046 | return; | ||
| 1047 | |||
| 1048 | - if (use_index != RELOAD_COMBINE_MAX_USES - 1) | ||
| 1049 | - { | ||
| 1050 | - /* We have found another use for a register that is already | ||
| 1051 | - used later. Check if the offsets match; if not, mark the | ||
| 1052 | - register as used in an unknown fashion. */ | ||
| 1053 | - if (! rtx_equal_p (offset, reg_state[regno].offset)) | ||
| 1054 | - { | ||
| 1055 | - reg_state[regno].use_index = -1; | ||
| 1056 | - return; | ||
| 1057 | - } | ||
| 1058 | - } | ||
| 1059 | - else | ||
| 1060 | + if (use_index == RELOAD_COMBINE_MAX_USES - 1) | ||
| 1061 | { | ||
| 1062 | /* This is the first use of this register we have seen since we | ||
| 1063 | marked it as dead. */ | ||
| 1064 | reg_state[regno].offset = offset; | ||
| 1065 | - reg_state[regno].use_ruid = reload_combine_ruid; | ||
| 1066 | + reg_state[regno].all_offsets_match = true; | ||
| 1067 | + reg_state[regno].use_ruid = ruid; | ||
| 1068 | + } | ||
| 1069 | + else | ||
| 1070 | + { | ||
| 1071 | + if (reg_state[regno].use_ruid > ruid) | ||
| 1072 | + reg_state[regno].use_ruid = ruid; | ||
| 1073 | + | ||
| 1074 | + if (! rtx_equal_p (offset, reg_state[regno].offset)) | ||
| 1075 | + reg_state[regno].all_offsets_match = false; | ||
| 1076 | } | ||
| 1077 | + | ||
| 1078 | reg_state[regno].reg_use[use_index].insn = insn; | ||
| 1079 | + reg_state[regno].reg_use[use_index].ruid = ruid; | ||
| 1080 | + reg_state[regno].reg_use[use_index].containing_mem = containing_mem; | ||
| 1081 | reg_state[regno].reg_use[use_index].usep = xp; | ||
| 1082 | return; | ||
| 1083 | } | ||
| 1084 | |||
| 1085 | + case MEM: | ||
| 1086 | + containing_mem = x; | ||
| 1087 | + break; | ||
| 1088 | + | ||
| 1089 | default: | ||
| 1090 | break; | ||
| 1091 | } | ||
| 1092 | @@ -1144,11 +1562,12 @@ reload_combine_note_use (rtx *xp, rtx in | ||
| 1093 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | ||
| 1094 | { | ||
| 1095 | if (fmt[i] == 'e') | ||
| 1096 | - reload_combine_note_use (&XEXP (x, i), insn); | ||
| 1097 | + reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem); | ||
| 1098 | else if (fmt[i] == 'E') | ||
| 1099 | { | ||
| 1100 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | ||
| 1101 | - reload_combine_note_use (&XVECEXP (x, i, j), insn); | ||
| 1102 | + reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid, | ||
| 1103 | + containing_mem); | ||
| 1104 | } | ||
| 1105 | } | ||
| 1106 | } | ||
| 1107 | @@ -1196,9 +1615,10 @@ static int move2add_last_label_luid; | ||
| 1108 | while REG is known to already have value (SYM + offset). | ||
| 1109 | This function tries to change INSN into an add instruction | ||
| 1110 | (set (REG) (plus (REG) (OFF - offset))) using the known value. | ||
| 1111 | - It also updates the information about REG's known value. */ | ||
| 1112 | + It also updates the information about REG's known value. | ||
| 1113 | + Return true if we made a change. */ | ||
| 1114 | |||
| 1115 | -static void | ||
| 1116 | +static bool | ||
| 1117 | move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn) | ||
| 1118 | { | ||
| 1119 | rtx pat = PATTERN (insn); | ||
| 1120 | @@ -1207,6 +1627,7 @@ move2add_use_add2_insn (rtx reg, rtx sym | ||
| 1121 | rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno], | ||
| 1122 | GET_MODE (reg)); | ||
| 1123 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | ||
| 1124 | + bool changed = false; | ||
| 1125 | |||
| 1126 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | ||
| 1127 | use (set (reg) (reg)) instead. | ||
| 1128 | @@ -1221,13 +1642,13 @@ move2add_use_add2_insn (rtx reg, rtx sym | ||
| 1129 | (reg)), would be discarded. Maybe we should | ||
| 1130 | try a truncMN pattern? */ | ||
| 1131 | if (INTVAL (off) == reg_offset [regno]) | ||
| 1132 | - validate_change (insn, &SET_SRC (pat), reg, 0); | ||
| 1133 | + changed = validate_change (insn, &SET_SRC (pat), reg, 0); | ||
| 1134 | } | ||
| 1135 | else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed) | ||
| 1136 | && have_add2_insn (reg, new_src)) | ||
| 1137 | { | ||
| 1138 | rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); | ||
| 1139 | - validate_change (insn, &SET_SRC (pat), tem, 0); | ||
| 1140 | + changed = validate_change (insn, &SET_SRC (pat), tem, 0); | ||
| 1141 | } | ||
| 1142 | else if (sym == NULL_RTX && GET_MODE (reg) != BImode) | ||
| 1143 | { | ||
| 1144 | @@ -1252,8 +1673,9 @@ move2add_use_add2_insn (rtx reg, rtx sym | ||
| 1145 | gen_rtx_STRICT_LOW_PART (VOIDmode, | ||
| 1146 | narrow_reg), | ||
| 1147 | narrow_src); | ||
| 1148 | - if (validate_change (insn, &PATTERN (insn), | ||
| 1149 | - new_set, 0)) | ||
| 1150 | + changed = validate_change (insn, &PATTERN (insn), | ||
| 1151 | + new_set, 0); | ||
| 1152 | + if (changed) | ||
| 1153 | break; | ||
| 1154 | } | ||
| 1155 | } | ||
| 1156 | @@ -1263,6 +1685,7 @@ move2add_use_add2_insn (rtx reg, rtx sym | ||
| 1157 | reg_mode[regno] = GET_MODE (reg); | ||
| 1158 | reg_symbol_ref[regno] = sym; | ||
| 1159 | reg_offset[regno] = INTVAL (off); | ||
| 1160 | + return changed; | ||
| 1161 | } | ||
| 1162 | |||
| 1163 | |||
| 1164 | @@ -1272,9 +1695,10 @@ move2add_use_add2_insn (rtx reg, rtx sym | ||
| 1165 | value (SYM + offset) and change INSN into an add instruction | ||
| 1166 | (set (REG) (plus (the found register) (OFF - offset))) if such | ||
| 1167 | a register is found. It also updates the information about | ||
| 1168 | - REG's known value. */ | ||
| 1169 | + REG's known value. | ||
| 1170 | + Return true iff we made a change. */ | ||
| 1171 | |||
| 1172 | -static void | ||
| 1173 | +static bool | ||
| 1174 | move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn) | ||
| 1175 | { | ||
| 1176 | rtx pat = PATTERN (insn); | ||
| 1177 | @@ -1284,6 +1708,7 @@ move2add_use_add3_insn (rtx reg, rtx sym | ||
| 1178 | int min_regno; | ||
| 1179 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | ||
| 1180 | int i; | ||
| 1181 | + bool changed = false; | ||
| 1182 | |||
| 1183 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 1184 | if (reg_set_luid[i] > move2add_last_label_luid | ||
| 1185 | @@ -1328,20 +1753,25 @@ move2add_use_add3_insn (rtx reg, rtx sym | ||
| 1186 | GET_MODE (reg)); | ||
| 1187 | tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); | ||
| 1188 | } | ||
| 1189 | - validate_change (insn, &SET_SRC (pat), tem, 0); | ||
| 1190 | + if (validate_change (insn, &SET_SRC (pat), tem, 0)) | ||
| 1191 | + changed = true; | ||
| 1192 | } | ||
| 1193 | reg_set_luid[regno] = move2add_luid; | ||
| 1194 | reg_base_reg[regno] = -1; | ||
| 1195 | reg_mode[regno] = GET_MODE (reg); | ||
| 1196 | reg_symbol_ref[regno] = sym; | ||
| 1197 | reg_offset[regno] = INTVAL (off); | ||
| 1198 | + return changed; | ||
| 1199 | } | ||
| 1200 | |||
| 1201 | -static void | ||
| 1202 | +/* Convert move insns with constant inputs to additions if they are cheaper. | ||
| 1203 | + Return true if any changes were made. */ | ||
| 1204 | +static bool | ||
| 1205 | reload_cse_move2add (rtx first) | ||
| 1206 | { | ||
| 1207 | int i; | ||
| 1208 | rtx insn; | ||
| 1209 | + bool changed = false; | ||
| 1210 | |||
| 1211 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | ||
| 1212 | { | ||
| 1213 | @@ -1402,7 +1832,7 @@ reload_cse_move2add (rtx first) | ||
| 1214 | && reg_base_reg[regno] < 0 | ||
| 1215 | && reg_symbol_ref[regno] == NULL_RTX) | ||
| 1216 | { | ||
| 1217 | - move2add_use_add2_insn (reg, NULL_RTX, src, insn); | ||
| 1218 | + changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn); | ||
| 1219 | continue; | ||
| 1220 | } | ||
| 1221 | |||
| 1222 | @@ -1463,6 +1893,7 @@ reload_cse_move2add (rtx first) | ||
| 1223 | } | ||
| 1224 | if (success) | ||
| 1225 | delete_insn (insn); | ||
| 1226 | + changed |= success; | ||
| 1227 | insn = next; | ||
| 1228 | reg_mode[regno] = GET_MODE (reg); | ||
| 1229 | reg_offset[regno] = | ||
| 1230 | @@ -1508,12 +1939,12 @@ reload_cse_move2add (rtx first) | ||
| 1231 | && reg_base_reg[regno] < 0 | ||
| 1232 | && reg_symbol_ref[regno] != NULL_RTX | ||
| 1233 | && rtx_equal_p (sym, reg_symbol_ref[regno])) | ||
| 1234 | - move2add_use_add2_insn (reg, sym, off, insn); | ||
| 1235 | + changed |= move2add_use_add2_insn (reg, sym, off, insn); | ||
| 1236 | |||
| 1237 | /* Otherwise, we have to find a register whose value is sum | ||
| 1238 | of sym and some constant value. */ | ||
| 1239 | else | ||
| 1240 | - move2add_use_add3_insn (reg, sym, off, insn); | ||
| 1241 | + changed |= move2add_use_add3_insn (reg, sym, off, insn); | ||
| 1242 | |||
| 1243 | continue; | ||
| 1244 | } | ||
| 1245 | @@ -1568,6 +1999,7 @@ reload_cse_move2add (rtx first) | ||
| 1246 | } | ||
| 1247 | } | ||
| 1248 | } | ||
| 1249 | + return changed; | ||
| 1250 | } | ||
| 1251 | |||
| 1252 | /* SET is a SET or CLOBBER that sets DST. DATA is the insn which | ||
| 1253 | Index: gcc-4.5/testsuite/gcc.target/arm/pr42235.c | ||
| 1254 | =================================================================== | ||
| 1255 | --- /dev/null | ||
| 1256 | +++ gcc-4.5/testsuite/gcc.target/arm/pr42235.c | ||
| 1257 | @@ -0,0 +1,11 @@ | ||
| 1258 | +/* { dg-options "-mthumb -O2 -march=armv5te" } */ | ||
| 1259 | +/* { dg-require-effective-target arm_thumb1_ok } */ | ||
| 1260 | +/* { dg-final { scan-assembler-not "add\[\\t \]*r.,\[\\t \]*r.,\[\\t \]*\#1" } } */ | ||
| 1261 | +/* { dg-final { scan-assembler-not "add\[\\t \]*r.,\[\\t \]*\#1" } } */ | ||
| 1262 | + | ||
| 1263 | +#include <string.h> | ||
| 1264 | + | ||
| 1265 | +int foo (char *x) | ||
| 1266 | +{ | ||
| 1267 | + memset (x, 0, 6); | ||
| 1268 | +} | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99403.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99403.patch deleted file mode 100644 index 093dd1c57..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99403.patch +++ /dev/null | |||
| @@ -1,176 +0,0 @@ | |||
| 1 | 2010-09-20 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #5256 | ||
| 4 | |||
| 5 | libstdc++-v3/ | ||
| 6 | |||
| 7 | Backport from mainline: | ||
| 8 | |||
| 9 | 2010-05-21 Joseph Myers <joseph@codesourcery.com> | ||
| 10 | * acinclude.m4 (GLIBCXX_ENABLE_CLOCALE): Use GNU locale model for | ||
| 11 | glibc 2.3 and later, but not uClibc, without an execution test. | ||
| 12 | * configure: Regenerate. | ||
| 13 | * doc/xml/manual/configure.xml, doc/xml/manual/prerequisites.xml, | ||
| 14 | doc/xml/faq.xml: Update. | ||
| 15 | |||
| 16 | === modified file 'libstdc++-v3/acinclude.m4' | ||
| 17 | Index: gcc-4.5/libstdc++-v3/acinclude.m4 | ||
| 18 | =================================================================== | ||
| 19 | --- gcc-4.5.orig/libstdc++-v3/acinclude.m4 | ||
| 20 | +++ gcc-4.5/libstdc++-v3/acinclude.m4 | ||
| 21 | @@ -1740,41 +1740,11 @@ AC_DEFUN([GLIBCXX_ENABLE_CLOCALE], [ | ||
| 22 | if test $enable_clocale_flag = gnu; then | ||
| 23 | AC_EGREP_CPP([_GLIBCXX_ok], [ | ||
| 24 | #include <features.h> | ||
| 25 | - #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 2) | ||
| 26 | + #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(__UCLIBC__) | ||
| 27 | _GLIBCXX_ok | ||
| 28 | #endif | ||
| 29 | ], enable_clocale_flag=gnu, enable_clocale_flag=generic) | ||
| 30 | |||
| 31 | - if test $enable_clocale = auto; then | ||
| 32 | - # Test for bugs early in glibc-2.2.x series | ||
| 33 | - AC_TRY_RUN([ | ||
| 34 | - #define _GNU_SOURCE 1 | ||
| 35 | - #include <locale.h> | ||
| 36 | - #include <string.h> | ||
| 37 | - #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 2) | ||
| 38 | - extern __typeof(newlocale) __newlocale; | ||
| 39 | - extern __typeof(duplocale) __duplocale; | ||
| 40 | - extern __typeof(strcoll_l) __strcoll_l; | ||
| 41 | - #endif | ||
| 42 | - int main() | ||
| 43 | - { | ||
| 44 | - const char __one[] = "Äuglein Augmen"; | ||
| 45 | - const char __two[] = "Äuglein"; | ||
| 46 | - int i; | ||
| 47 | - int j; | ||
| 48 | - __locale_t loc; | ||
| 49 | - __locale_t loc_dup; | ||
| 50 | - loc = __newlocale(1 << LC_ALL, "de_DE", 0); | ||
| 51 | - loc_dup = __duplocale(loc); | ||
| 52 | - i = __strcoll_l(__one, __two, loc); | ||
| 53 | - j = __strcoll_l(__one, __two, loc_dup); | ||
| 54 | - return 0; | ||
| 55 | - } | ||
| 56 | - ], | ||
| 57 | - [enable_clocale_flag=gnu],[enable_clocale_flag=generic], | ||
| 58 | - [enable_clocale_flag=generic]) | ||
| 59 | - fi | ||
| 60 | - | ||
| 61 | # Set it to scream when it hurts. | ||
| 62 | ac_save_CFLAGS="$CFLAGS" | ||
| 63 | CFLAGS="-Wimplicit-function-declaration -Werror" | ||
| 64 | Index: gcc-4.5/libstdc++-v3/configure | ||
| 65 | =================================================================== | ||
| 66 | --- gcc-4.5.orig/libstdc++-v3/configure | ||
| 67 | +++ gcc-4.5/libstdc++-v3/configure | ||
| 68 | @@ -15627,7 +15627,7 @@ fi | ||
| 69 | /* end confdefs.h. */ | ||
| 70 | |||
| 71 | #include <features.h> | ||
| 72 | - #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 2) | ||
| 73 | + #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(__UCLIBC__) | ||
| 74 | _GLIBCXX_ok | ||
| 75 | #endif | ||
| 76 | |||
| 77 | @@ -15641,49 +15641,6 @@ fi | ||
| 78 | rm -f conftest* | ||
| 79 | |||
| 80 | |||
| 81 | - if test $enable_clocale = auto; then | ||
| 82 | - # Test for bugs early in glibc-2.2.x series | ||
| 83 | - if test "$cross_compiling" = yes; then : | ||
| 84 | - enable_clocale_flag=generic | ||
| 85 | -else | ||
| 86 | - cat confdefs.h - <<_ACEOF >conftest.$ac_ext | ||
| 87 | -/* end confdefs.h. */ | ||
| 88 | - | ||
| 89 | - #define _GNU_SOURCE 1 | ||
| 90 | - #include <locale.h> | ||
| 91 | - #include <string.h> | ||
| 92 | - #if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 2) | ||
| 93 | - extern __typeof(newlocale) __newlocale; | ||
| 94 | - extern __typeof(duplocale) __duplocale; | ||
| 95 | - extern __typeof(strcoll_l) __strcoll_l; | ||
| 96 | - #endif | ||
| 97 | - int main() | ||
| 98 | - { | ||
| 99 | - const char __one[] = "Äuglein Augmen"; | ||
| 100 | - const char __two[] = "Äuglein"; | ||
| 101 | - int i; | ||
| 102 | - int j; | ||
| 103 | - __locale_t loc; | ||
| 104 | - __locale_t loc_dup; | ||
| 105 | - loc = __newlocale(1 << LC_ALL, "de_DE", 0); | ||
| 106 | - loc_dup = __duplocale(loc); | ||
| 107 | - i = __strcoll_l(__one, __two, loc); | ||
| 108 | - j = __strcoll_l(__one, __two, loc_dup); | ||
| 109 | - return 0; | ||
| 110 | - } | ||
| 111 | - | ||
| 112 | -_ACEOF | ||
| 113 | -if ac_fn_c_try_run "$LINENO"; then : | ||
| 114 | - enable_clocale_flag=gnu | ||
| 115 | -else | ||
| 116 | - enable_clocale_flag=generic | ||
| 117 | -fi | ||
| 118 | -rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ | ||
| 119 | - conftest.$ac_objext conftest.beam conftest.$ac_ext | ||
| 120 | -fi | ||
| 121 | - | ||
| 122 | - fi | ||
| 123 | - | ||
| 124 | # Set it to scream when it hurts. | ||
| 125 | ac_save_CFLAGS="$CFLAGS" | ||
| 126 | CFLAGS="-Wimplicit-function-declaration -Werror" | ||
| 127 | Index: gcc-4.5/libstdc++-v3/doc/xml/faq.xml | ||
| 128 | =================================================================== | ||
| 129 | --- gcc-4.5.orig/libstdc++-v3/doc/xml/faq.xml | ||
| 130 | +++ gcc-4.5/libstdc++-v3/doc/xml/faq.xml | ||
| 131 | @@ -636,6 +636,8 @@ | ||
| 132 | C library (glibc) version 2.2.5. That version of glibc is over a | ||
| 133 | year old and contains necessary bugfixes. Many GNU/Linux distros make | ||
| 134 | glibc version 2.3.x available now. | ||
| 135 | + libstdc++ 4.6.0 and later require glibc 2.3 or later for this | ||
| 136 | + localization and formatting code. | ||
| 137 | </para> | ||
| 138 | <para>The guideline is simple: the more recent the C++ library, the | ||
| 139 | more recent the C library. (This is also documented in the main | ||
| 140 | Index: gcc-4.5/libstdc++-v3/doc/xml/manual/configure.xml | ||
| 141 | =================================================================== | ||
| 142 | --- gcc-4.5.orig/libstdc++-v3/doc/xml/manual/configure.xml | ||
| 143 | +++ gcc-4.5/libstdc++-v3/doc/xml/manual/configure.xml | ||
| 144 | @@ -113,8 +113,7 @@ | ||
| 145 | <para>If not explicitly specified, the configure proccess tries | ||
| 146 | to guess the most suitable package from the choices above. The | ||
| 147 | default is 'generic'. On glibc-based systems of sufficient | ||
| 148 | - vintage (2.2.5 and newer) and capability (with installed DE and | ||
| 149 | - FR locale data), 'gnu' is automatically selected. This option | ||
| 150 | + vintage (2.3 and newer), 'gnu' is automatically selected. This option | ||
| 151 | can change the library ABI. | ||
| 152 | </para> | ||
| 153 | </listitem></varlistentry> | ||
| 154 | Index: gcc-4.5/libstdc++-v3/doc/xml/manual/prerequisites.xml | ||
| 155 | =================================================================== | ||
| 156 | --- gcc-4.5.orig/libstdc++-v3/doc/xml/manual/prerequisites.xml | ||
| 157 | +++ gcc-4.5/libstdc++-v3/doc/xml/manual/prerequisites.xml | ||
| 158 | @@ -52,16 +52,8 @@ | ||
| 159 | <para> | ||
| 160 | If gcc 3.1.0 or later on is being used on linux, an attempt | ||
| 161 | will be made to use "C" library functionality necessary for | ||
| 162 | - C++ named locale support. For gcc 3.2.1 and later, this | ||
| 163 | - means that glibc 2.2.5 or later is required and the "C" | ||
| 164 | - library de_DE locale information must be installed. | ||
| 165 | - </para> | ||
| 166 | - | ||
| 167 | - <para> | ||
| 168 | - Note however that the sanity checks involving the de_DE | ||
| 169 | - locale are skipped when an explicit --enable-clocale=gnu | ||
| 170 | - configure option is used: only the basic checks are carried | ||
| 171 | - out, defending against misconfigurations. | ||
| 172 | + C++ named locale support. For gcc 4.6.0 and later, this | ||
| 173 | + means that glibc 2.3 or later is required. | ||
| 174 | </para> | ||
| 175 | |||
| 176 | <para> | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99404.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99404.patch deleted file mode 100644 index 275330092..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99404.patch +++ /dev/null | |||
| @@ -1,386 +0,0 @@ | |||
| 1 | 2010-09-20 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #9019 | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | 2010-09-20 Jie Zhang <jie@codesourcery.com> | ||
| 9 | * config/arm/arm.c (arm_address_offset_is_imm): New. | ||
| 10 | (arm_early_store_addr_dep): New. | ||
| 11 | (arm_early_load_addr_dep): New. | ||
| 12 | * config/arm/arm-protos.h (arm_early_store_addr_dep): Declare. | ||
| 13 | (arm_early_load_addr_dep): Declare. | ||
| 14 | (arm_address_offset_is_imm): Declare. | ||
| 15 | * config/arm/cortex-m4.md: New file. | ||
| 16 | * config/arm/cortex-m4-fpu.md: New file. | ||
| 17 | * config/arm/arm.md: Include cortex-m4.md and cortex-m4-fpu.md. | ||
| 18 | (attr generic_sched): Exclude cortexm4. | ||
| 19 | (attr generic_vfp): Exclude cortexm4. | ||
| 20 | |||
| 21 | === modified file 'gcc/config/arm/arm-protos.h' | ||
| 22 | Index: gcc-4.5/gcc/config/arm/arm-protos.h | ||
| 23 | =================================================================== | ||
| 24 | --- gcc-4.5.orig/gcc/config/arm/arm-protos.h | ||
| 25 | +++ gcc-4.5/gcc/config/arm/arm-protos.h | ||
| 26 | @@ -87,6 +87,8 @@ extern int arm_coproc_mem_operand (rtx, | ||
| 27 | extern int neon_vector_mem_operand (rtx, int); | ||
| 28 | extern int neon_struct_mem_operand (rtx); | ||
| 29 | extern int arm_no_early_store_addr_dep (rtx, rtx); | ||
| 30 | +extern int arm_early_store_addr_dep (rtx, rtx); | ||
| 31 | +extern int arm_early_load_addr_dep (rtx, rtx); | ||
| 32 | extern int arm_no_early_alu_shift_dep (rtx, rtx); | ||
| 33 | extern int arm_no_early_alu_shift_value_dep (rtx, rtx); | ||
| 34 | extern int arm_no_early_mul_dep (rtx, rtx); | ||
| 35 | @@ -131,6 +133,7 @@ extern const char *output_move_quad (rtx | ||
| 36 | extern const char *output_move_vfp (rtx *operands); | ||
| 37 | extern const char *output_move_neon (rtx *operands); | ||
| 38 | extern int arm_attr_length_move_neon (rtx); | ||
| 39 | +extern int arm_address_offset_is_imm (rtx); | ||
| 40 | extern const char *output_add_immediate (rtx *); | ||
| 41 | extern const char *arithmetic_instr (rtx, int); | ||
| 42 | extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int); | ||
| 43 | Index: gcc-4.5/gcc/config/arm/arm.c | ||
| 44 | =================================================================== | ||
| 45 | --- gcc-4.5.orig/gcc/config/arm/arm.c | ||
| 46 | +++ gcc-4.5/gcc/config/arm/arm.c | ||
| 47 | @@ -13542,6 +13542,34 @@ arm_attr_length_move_neon (rtx insn) | ||
| 48 | return 4; | ||
| 49 | } | ||
| 50 | |||
| 51 | +/* Return nonzero if the offset in the address is an immediate. Otherwise, | ||
| 52 | + return zero. */ | ||
| 53 | + | ||
| 54 | +int | ||
| 55 | +arm_address_offset_is_imm (rtx insn) | ||
| 56 | +{ | ||
| 57 | + rtx mem, addr; | ||
| 58 | + | ||
| 59 | + extract_insn_cached (insn); | ||
| 60 | + | ||
| 61 | + if (REG_P (recog_data.operand[0])) | ||
| 62 | + return 0; | ||
| 63 | + | ||
| 64 | + mem = recog_data.operand[0]; | ||
| 65 | + | ||
| 66 | + gcc_assert (MEM_P (mem)); | ||
| 67 | + | ||
| 68 | + addr = XEXP (mem, 0); | ||
| 69 | + | ||
| 70 | + if (GET_CODE (addr) == REG | ||
| 71 | + || (GET_CODE (addr) == PLUS | ||
| 72 | + && GET_CODE (XEXP (addr, 0)) == REG | ||
| 73 | + && GET_CODE (XEXP (addr, 1)) == CONST_INT)) | ||
| 74 | + return 1; | ||
| 75 | + else | ||
| 76 | + return 0; | ||
| 77 | +} | ||
| 78 | + | ||
| 79 | /* Output an ADD r, s, #n where n may be too big for one instruction. | ||
| 80 | If adding zero to one register, output nothing. */ | ||
| 81 | const char * | ||
| 82 | @@ -21620,6 +21648,38 @@ arm_no_early_store_addr_dep (rtx produce | ||
| 83 | return !reg_overlap_mentioned_p (value, addr); | ||
| 84 | } | ||
| 85 | |||
| 86 | +/* Return nonzero if the CONSUMER instruction (a store) does need | ||
| 87 | + PRODUCER's value to calculate the address. */ | ||
| 88 | + | ||
| 89 | +int | ||
| 90 | +arm_early_store_addr_dep (rtx producer, rtx consumer) | ||
| 91 | +{ | ||
| 92 | + return !arm_no_early_store_addr_dep (producer, consumer); | ||
| 93 | +} | ||
| 94 | + | ||
| 95 | +/* Return nonzero if the CONSUMER instruction (a load) does need | ||
| 96 | + PRODUCER's value to calculate the address. */ | ||
| 97 | + | ||
| 98 | +int | ||
| 99 | +arm_early_load_addr_dep (rtx producer, rtx consumer) | ||
| 100 | +{ | ||
| 101 | + rtx value = PATTERN (producer); | ||
| 102 | + rtx addr = PATTERN (consumer); | ||
| 103 | + | ||
| 104 | + if (GET_CODE (value) == COND_EXEC) | ||
| 105 | + value = COND_EXEC_CODE (value); | ||
| 106 | + if (GET_CODE (value) == PARALLEL) | ||
| 107 | + value = XVECEXP (value, 0, 0); | ||
| 108 | + value = XEXP (value, 0); | ||
| 109 | + if (GET_CODE (addr) == COND_EXEC) | ||
| 110 | + addr = COND_EXEC_CODE (addr); | ||
| 111 | + if (GET_CODE (addr) == PARALLEL) | ||
| 112 | + addr = XVECEXP (addr, 0, 0); | ||
| 113 | + addr = XEXP (addr, 1); | ||
| 114 | + | ||
| 115 | + return reg_overlap_mentioned_p (value, addr); | ||
| 116 | +} | ||
| 117 | + | ||
| 118 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not | ||
| 119 | have an early register shift value or amount dependency on the | ||
| 120 | result of PRODUCER. */ | ||
| 121 | Index: gcc-4.5/gcc/config/arm/arm.md | ||
| 122 | =================================================================== | ||
| 123 | --- gcc-4.5.orig/gcc/config/arm/arm.md | ||
| 124 | +++ gcc-4.5/gcc/config/arm/arm.md | ||
| 125 | @@ -434,16 +434,16 @@ | ||
| 126 | ;; True if the generic scheduling description should be used. | ||
| 127 | |||
| 128 | (define_attr "generic_sched" "yes,no" | ||
| 129 | - (const (if_then_else | ||
| 130 | - (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9") | ||
| 131 | - (eq_attr "tune_cortexr4" "yes")) | ||
| 132 | + (const (if_then_else | ||
| 133 | + (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4") | ||
| 134 | + (eq_attr "tune_cortexr4" "yes")) | ||
| 135 | (const_string "no") | ||
| 136 | (const_string "yes")))) | ||
| 137 | |||
| 138 | (define_attr "generic_vfp" "yes,no" | ||
| 139 | (const (if_then_else | ||
| 140 | (and (eq_attr "fpu" "vfp") | ||
| 141 | - (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9") | ||
| 142 | + (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9,cortexm4") | ||
| 143 | (eq_attr "tune_cortexr4" "no")) | ||
| 144 | (const_string "yes") | ||
| 145 | (const_string "no")))) | ||
| 146 | @@ -472,6 +472,8 @@ | ||
| 147 | (include "cortex-a9.md") | ||
| 148 | (include "cortex-r4.md") | ||
| 149 | (include "cortex-r4f.md") | ||
| 150 | +(include "cortex-m4.md") | ||
| 151 | +(include "cortex-m4-fpu.md") | ||
| 152 | (include "vfp11.md") | ||
| 153 | |||
| 154 | |||
| 155 | Index: gcc-4.5/gcc/config/arm/cortex-m4-fpu.md | ||
| 156 | =================================================================== | ||
| 157 | --- /dev/null | ||
| 158 | +++ gcc-4.5/gcc/config/arm/cortex-m4-fpu.md | ||
| 159 | @@ -0,0 +1,111 @@ | ||
| 160 | +;; ARM Cortex-M4 FPU pipeline description | ||
| 161 | +;; Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 162 | +;; Contributed by CodeSourcery. | ||
| 163 | +;; | ||
| 164 | +;; This file is part of GCC. | ||
| 165 | +;; | ||
| 166 | +;; GCC is free software; you can redistribute it and/or modify it | ||
| 167 | +;; under the terms of the GNU General Public License as published by | ||
| 168 | +;; the Free Software Foundation; either version 3, or (at your option) | ||
| 169 | +;; any later version. | ||
| 170 | +;; | ||
| 171 | +;; GCC is distributed in the hope that it will be useful, but | ||
| 172 | +;; WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 173 | +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 174 | +;; General Public License for more details. | ||
| 175 | +;; | ||
| 176 | +;; You should have received a copy of the GNU General Public License | ||
| 177 | +;; along with GCC; see the file COPYING3. If not see | ||
| 178 | +;; <http://www.gnu.org/licenses/>. | ||
| 179 | + | ||
| 180 | +;; Use an artifial unit to model FPU. | ||
| 181 | +(define_cpu_unit "cortex_m4_v" "cortex_m4") | ||
| 182 | + | ||
| 183 | +(define_reservation "cortex_m4_ex_v" "cortex_m4_ex+cortex_m4_v") | ||
| 184 | + | ||
| 185 | +;; Integer instructions following VDIV or VSQRT complete out-of-order. | ||
| 186 | +(define_insn_reservation "cortex_m4_fdivs" 15 | ||
| 187 | + (and (eq_attr "tune" "cortexm4") | ||
| 188 | + (eq_attr "type" "fdivs")) | ||
| 189 | + "cortex_m4_ex_v,cortex_m4_v*13") | ||
| 190 | + | ||
| 191 | +(define_insn_reservation "cortex_m4_vmov_1" 1 | ||
| 192 | + (and (eq_attr "tune" "cortexm4") | ||
| 193 | + (eq_attr "type" "fcpys,fconsts")) | ||
| 194 | + "cortex_m4_ex_v") | ||
| 195 | + | ||
| 196 | +(define_insn_reservation "cortex_m4_vmov_2" 2 | ||
| 197 | + (and (eq_attr "tune" "cortexm4") | ||
| 198 | + (eq_attr "type" "f_2_r,r_2_f")) | ||
| 199 | + "cortex_m4_ex_v*2") | ||
| 200 | + | ||
| 201 | +(define_insn_reservation "cortex_m4_fmuls" 2 | ||
| 202 | + (and (eq_attr "tune" "cortexm4") | ||
| 203 | + (eq_attr "type" "fmuls")) | ||
| 204 | + "cortex_m4_ex_v") | ||
| 205 | + | ||
| 206 | +(define_insn_reservation "cortex_m4_fmacs" 4 | ||
| 207 | + (and (eq_attr "tune" "cortexm4") | ||
| 208 | + (eq_attr "type" "fmacs")) | ||
| 209 | + "cortex_m4_ex_v*3") | ||
| 210 | + | ||
| 211 | +(define_insn_reservation "cortex_m4_ffariths" 1 | ||
| 212 | + (and (eq_attr "tune" "cortexm4") | ||
| 213 | + (eq_attr "type" "ffariths")) | ||
| 214 | + "cortex_m4_ex_v") | ||
| 215 | + | ||
| 216 | +(define_insn_reservation "cortex_m4_fadds" 2 | ||
| 217 | + (and (eq_attr "tune" "cortexm4") | ||
| 218 | + (eq_attr "type" "fadds")) | ||
| 219 | + "cortex_m4_ex_v") | ||
| 220 | + | ||
| 221 | +(define_insn_reservation "cortex_m4_fcmps" 1 | ||
| 222 | + (and (eq_attr "tune" "cortexm4") | ||
| 223 | + (eq_attr "type" "fcmps")) | ||
| 224 | + "cortex_m4_ex_v") | ||
| 225 | + | ||
| 226 | +(define_insn_reservation "cortex_m4_f_flag" 1 | ||
| 227 | + (and (eq_attr "tune" "cortexm4") | ||
| 228 | + (eq_attr "type" "f_flag")) | ||
| 229 | + "cortex_m4_ex_v") | ||
| 230 | + | ||
| 231 | +(define_insn_reservation "cortex_m4_f_cvt" 2 | ||
| 232 | + (and (eq_attr "tune" "cortexm4") | ||
| 233 | + (eq_attr "type" "f_cvt")) | ||
| 234 | + "cortex_m4_ex_v") | ||
| 235 | + | ||
| 236 | +(define_insn_reservation "cortex_m4_f_load" 2 | ||
| 237 | + (and (eq_attr "tune" "cortexm4") | ||
| 238 | + (eq_attr "type" "f_load")) | ||
| 239 | + "cortex_m4_ex_v*2") | ||
| 240 | + | ||
| 241 | +(define_insn_reservation "cortex_m4_f_store" 2 | ||
| 242 | + (and (eq_attr "tune" "cortexm4") | ||
| 243 | + (eq_attr "type" "f_store")) | ||
| 244 | + "cortex_m4_ex_v*2") | ||
| 245 | + | ||
| 246 | +(define_insn_reservation "cortex_m4_f_loadd" 3 | ||
| 247 | + (and (eq_attr "tune" "cortexm4") | ||
| 248 | + (eq_attr "type" "f_loadd")) | ||
| 249 | + "cortex_m4_ex_v*3") | ||
| 250 | + | ||
| 251 | +(define_insn_reservation "cortex_m4_f_stored" 3 | ||
| 252 | + (and (eq_attr "tune" "cortexm4") | ||
| 253 | + (eq_attr "type" "f_stored")) | ||
| 254 | + "cortex_m4_ex_v*3") | ||
| 255 | + | ||
| 256 | +;; MAC instructions consume their addend one cycle later. If the result | ||
| 257 | +;; of an arithmetic instruction is consumed as the addend of the following | ||
| 258 | +;; MAC instruction, the latency can be decreased by one. | ||
| 259 | + | ||
| 260 | +(define_bypass 1 "cortex_m4_fadds,cortex_m4_fmuls,cortex_m4_f_cvt" | ||
| 261 | + "cortex_m4_fmacs" | ||
| 262 | + "arm_no_early_mul_dep") | ||
| 263 | + | ||
| 264 | +(define_bypass 3 "cortex_m4_fmacs" | ||
| 265 | + "cortex_m4_fmacs" | ||
| 266 | + "arm_no_early_mul_dep") | ||
| 267 | + | ||
| 268 | +(define_bypass 14 "cortex_m4_fdivs" | ||
| 269 | + "cortex_m4_fmacs" | ||
| 270 | + "arm_no_early_mul_dep") | ||
| 271 | Index: gcc-4.5/gcc/config/arm/cortex-m4.md | ||
| 272 | =================================================================== | ||
| 273 | --- /dev/null | ||
| 274 | +++ gcc-4.5/gcc/config/arm/cortex-m4.md | ||
| 275 | @@ -0,0 +1,111 @@ | ||
| 276 | +;; ARM Cortex-M4 pipeline description | ||
| 277 | +;; Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 278 | +;; Contributed by CodeSourcery. | ||
| 279 | +;; | ||
| 280 | +;; This file is part of GCC. | ||
| 281 | +;; | ||
| 282 | +;; GCC is free software; you can redistribute it and/or modify it | ||
| 283 | +;; under the terms of the GNU General Public License as published by | ||
| 284 | +;; the Free Software Foundation; either version 3, or (at your option) | ||
| 285 | +;; any later version. | ||
| 286 | +;; | ||
| 287 | +;; GCC is distributed in the hope that it will be useful, but | ||
| 288 | +;; WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 289 | +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 290 | +;; General Public License for more details. | ||
| 291 | +;; | ||
| 292 | +;; You should have received a copy of the GNU General Public License | ||
| 293 | +;; along with GCC; see the file COPYING3. If not see | ||
| 294 | +;; <http://www.gnu.org/licenses/>. | ||
| 295 | + | ||
| 296 | +(define_automaton "cortex_m4") | ||
| 297 | + | ||
| 298 | +;; We model the pipelining of LDR instructions by using two artificial units. | ||
| 299 | + | ||
| 300 | +(define_cpu_unit "cortex_m4_a" "cortex_m4") | ||
| 301 | + | ||
| 302 | +(define_cpu_unit "cortex_m4_b" "cortex_m4") | ||
| 303 | + | ||
| 304 | +(define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b") | ||
| 305 | + | ||
| 306 | +;; ALU and multiply is one cycle. | ||
| 307 | +(define_insn_reservation "cortex_m4_alu" 1 | ||
| 308 | + (and (eq_attr "tune" "cortexm4") | ||
| 309 | + (eq_attr "type" "alu,alu_shift,alu_shift_reg,mult")) | ||
| 310 | + "cortex_m4_ex") | ||
| 311 | + | ||
| 312 | +;; Byte, half-word and word load is two cycles. | ||
| 313 | +(define_insn_reservation "cortex_m4_load1" 2 | ||
| 314 | + (and (eq_attr "tune" "cortexm4") | ||
| 315 | + (eq_attr "type" "load_byte,load1")) | ||
| 316 | + "cortex_m4_a, cortex_m4_b") | ||
| 317 | + | ||
| 318 | +;; str rx, [ry, #imm] is always one cycle. | ||
| 319 | +(define_insn_reservation "cortex_m4_store1_1" 1 | ||
| 320 | + (and (and (eq_attr "tune" "cortexm4") | ||
| 321 | + (eq_attr "type" "store1")) | ||
| 322 | + (ne (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0))) | ||
| 323 | + "cortex_m4_a") | ||
| 324 | + | ||
| 325 | +;; Other byte, half-word and word load is two cycles. | ||
| 326 | +(define_insn_reservation "cortex_m4_store1_2" 2 | ||
| 327 | + (and (and (eq_attr "tune" "cortexm4") | ||
| 328 | + (eq_attr "type" "store1")) | ||
| 329 | + (eq (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0))) | ||
| 330 | + "cortex_m4_a*2") | ||
| 331 | + | ||
| 332 | +(define_insn_reservation "cortex_m4_load2" 3 | ||
| 333 | + (and (eq_attr "tune" "cortexm4") | ||
| 334 | + (eq_attr "type" "load2")) | ||
| 335 | + "cortex_m4_ex*3") | ||
| 336 | + | ||
| 337 | +(define_insn_reservation "cortex_m4_store2" 3 | ||
| 338 | + (and (eq_attr "tune" "cortexm4") | ||
| 339 | + (eq_attr "type" "store2")) | ||
| 340 | + "cortex_m4_ex*3") | ||
| 341 | + | ||
| 342 | +(define_insn_reservation "cortex_m4_load3" 4 | ||
| 343 | + (and (eq_attr "tune" "cortexm4") | ||
| 344 | + (eq_attr "type" "load3")) | ||
| 345 | + "cortex_m4_ex*4") | ||
| 346 | + | ||
| 347 | +(define_insn_reservation "cortex_m4_store3" 4 | ||
| 348 | + (and (eq_attr "tune" "cortexm4") | ||
| 349 | + (eq_attr "type" "store3")) | ||
| 350 | + "cortex_m4_ex*4") | ||
| 351 | + | ||
| 352 | +(define_insn_reservation "cortex_m4_load4" 5 | ||
| 353 | + (and (eq_attr "tune" "cortexm4") | ||
| 354 | + (eq_attr "type" "load4")) | ||
| 355 | + "cortex_m4_ex*5") | ||
| 356 | + | ||
| 357 | +(define_insn_reservation "cortex_m4_store4" 5 | ||
| 358 | + (and (eq_attr "tune" "cortexm4") | ||
| 359 | + (eq_attr "type" "store4")) | ||
| 360 | + "cortex_m4_ex*5") | ||
| 361 | + | ||
| 362 | +;; If the address of load or store depends on the result of the preceding | ||
| 363 | +;; instruction, the latency is increased by one. | ||
| 364 | + | ||
| 365 | +(define_bypass 2 "cortex_m4_alu" | ||
| 366 | + "cortex_m4_load1" | ||
| 367 | + "arm_early_load_addr_dep") | ||
| 368 | + | ||
| 369 | +(define_bypass 2 "cortex_m4_alu" | ||
| 370 | + "cortex_m4_store1_1,cortex_m4_store1_2" | ||
| 371 | + "arm_early_store_addr_dep") | ||
| 372 | + | ||
| 373 | +(define_insn_reservation "cortex_m4_branch" 3 | ||
| 374 | + (and (eq_attr "tune" "cortexm4") | ||
| 375 | + (eq_attr "type" "branch")) | ||
| 376 | + "cortex_m4_ex*3") | ||
| 377 | + | ||
| 378 | +(define_insn_reservation "cortex_m4_call" 3 | ||
| 379 | + (and (eq_attr "tune" "cortexm4") | ||
| 380 | + (eq_attr "type" "call")) | ||
| 381 | + "cortex_m4_ex*3") | ||
| 382 | + | ||
| 383 | +(define_insn_reservation "cortex_m4_block" 1 | ||
| 384 | + (and (eq_attr "tune" "cortexm4") | ||
| 385 | + (eq_attr "type" "block")) | ||
| 386 | + "cortex_m4_ex") | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99405.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99405.patch deleted file mode 100644 index 7fc943f4b..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99405.patch +++ /dev/null | |||
| @@ -1,36 +0,0 @@ | |||
| 1 | 2010-09-22 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-09-22 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * postreload.c (move2add_note_store): Add reg_symbol_ref[] checks | ||
| 9 | to update conditions. Fix reg_mode[] check. | ||
| 10 | |||
| 11 | === modified file 'gcc/postreload.c' | ||
| 12 | Index: gcc-4.5/gcc/postreload.c | ||
| 13 | =================================================================== | ||
| 14 | --- gcc-4.5.orig/gcc/postreload.c | ||
| 15 | +++ gcc-4.5/gcc/postreload.c | ||
| 16 | @@ -2103,15 +2103,17 @@ move2add_note_store (rtx dst, const_rtx | ||
| 17 | && (MODES_OK_FOR_MOVE2ADD | ||
| 18 | (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))) | ||
| 19 | { | ||
| 20 | - if (reg_base_reg[REGNO (XEXP (src, 1))] < 0) | ||
| 21 | + if (reg_base_reg[REGNO (XEXP (src, 1))] < 0 | ||
| 22 | + && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX) | ||
| 23 | offset = reg_offset[REGNO (XEXP (src, 1))]; | ||
| 24 | /* Maybe the first register is known to be a | ||
| 25 | constant. */ | ||
| 26 | else if (reg_set_luid[REGNO (base_reg)] | ||
| 27 | > move2add_last_label_luid | ||
| 28 | && (MODES_OK_FOR_MOVE2ADD | ||
| 29 | - (dst_mode, reg_mode[REGNO (XEXP (src, 1))])) | ||
| 30 | - && reg_base_reg[REGNO (base_reg)] < 0) | ||
| 31 | + (dst_mode, reg_mode[REGNO (base_reg)])) | ||
| 32 | + && reg_base_reg[REGNO (base_reg)] < 0 | ||
| 33 | + && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX) | ||
| 34 | { | ||
| 35 | offset = reg_offset[REGNO (base_reg)]; | ||
| 36 | base_reg = XEXP (src, 1); | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99406.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99406.patch deleted file mode 100644 index 54473fa23..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99406.patch +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | 2010-09-28 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | gcc/testsuite/ | ||
| 6 | 2010-09-28 Jie Zhang <jie@codesourcery.com> | ||
| 7 | * gcc.dg/Wcxx-compat-12.c: Add -fno-short-enums. | ||
| 8 | |||
| 9 | === modified file 'gcc/testsuite/gcc.dg/Wcxx-compat-12.c' | ||
| 10 | Index: gcc-4.5/gcc/testsuite/gcc.dg/Wcxx-compat-12.c | ||
| 11 | =================================================================== | ||
| 12 | --- gcc-4.5.orig/gcc/testsuite/gcc.dg/Wcxx-compat-12.c | ||
| 13 | +++ gcc-4.5/gcc/testsuite/gcc.dg/Wcxx-compat-12.c | ||
| 14 | @@ -1,5 +1,5 @@ | ||
| 15 | /* { dg-do compile } */ | ||
| 16 | -/* { dg-options "-Wc++-compat" } */ | ||
| 17 | +/* { dg-options "-fno-short-enums -Wc++-compat" } */ | ||
| 18 | |||
| 19 | enum E { A }; | ||
| 20 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99407.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99407.patch deleted file mode 100644 index 80f4246ed..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99407.patch +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | 2010-09-30 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/testsuite/ | ||
| 4 | |||
| 5 | * c-c++-common/uninit-17.c: Adjust warning message. | ||
| 6 | |||
| 7 | Backport from mainline: | ||
| 8 | |||
| 9 | 2010-07-30 Xinliang David Li <davidxl@google.com> | ||
| 10 | PR tree-optimization/45121 | ||
| 11 | * c-c++-common/uninit-17.c: Add -fno-ivops option. | ||
| 12 | |||
| 13 | === modified file 'gcc/testsuite/c-c++-common/uninit-17.c' | ||
| 14 | Index: gcc-4.5/gcc/testsuite/c-c++-common/uninit-17.c | ||
| 15 | =================================================================== | ||
| 16 | --- gcc-4.5.orig/gcc/testsuite/c-c++-common/uninit-17.c | ||
| 17 | +++ gcc-4.5/gcc/testsuite/c-c++-common/uninit-17.c | ||
| 18 | @@ -1,5 +1,5 @@ | ||
| 19 | /* { dg-do compile } */ | ||
| 20 | -/* { dg-options "-O2 -Wuninitialized" } */ | ||
| 21 | +/* { dg-options "-O2 -Wuninitialized -fno-ivopts" } */ | ||
| 22 | |||
| 23 | inline int foo(int x) | ||
| 24 | { | ||
| 25 | @@ -9,7 +9,7 @@ static void bar(int a, int *ptr) | ||
| 26 | { | ||
| 27 | do | ||
| 28 | { | ||
| 29 | - int b; /* { dg-warning "is used uninitialized" } */ | ||
| 30 | + int b; /* { dg-warning "may be used uninitialized" } */ | ||
| 31 | if (b < 40) { | ||
| 32 | ptr[0] = b; | ||
| 33 | } | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99408.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99408.patch deleted file mode 100644 index 1d873ba65..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99408.patch +++ /dev/null | |||
| @@ -1,603 +0,0 @@ | |||
| 1 | 2010-10-01 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | Revert: | ||
| 4 | |||
| 5 | Backport from FSF: | ||
| 6 | |||
| 7 | 2010-08-07 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 8 | |||
| 9 | gcc/ | ||
| 10 | * config/arm/linux-atomic.c (SUBWORD_VAL_CAS): Instantiate with | ||
| 11 | 'unsigned short' and 'unsigned char' instead of 'short' and | ||
| 12 | 'char'. (SUBWORD_BOOL_CAS): Likewise. | ||
| 13 | (SUBWORD_SYNC_OP): Likewise. | ||
| 14 | (SUBWORD_TEST_AND_SET): Likewise. | ||
| 15 | (FETCH_AND_OP_WORD): Parenthesise INF_OP | ||
| 16 | (SUBWORD_SYNC_OP): Likewise. | ||
| 17 | (OP_AND_FETCH_WORD): Likewise. | ||
| 18 | |||
| 19 | gcc/testsuite/ | ||
| 20 | * lib/target-supports.exp: (check_effective_target_sync_int_long): | ||
| 21 | Add arm*-*-linux-gnueabi. | ||
| 22 | (check_effective_target_sync_char_short): Likewise. | ||
| 23 | |||
| 24 | === modified file 'gcc/config/arm/arm-protos.h' | ||
| 25 | Index: gcc-4.5/gcc/config/arm/arm-protos.h | ||
| 26 | =================================================================== | ||
| 27 | --- gcc-4.5.orig/gcc/config/arm/arm-protos.h | ||
| 28 | +++ gcc-4.5/gcc/config/arm/arm-protos.h | ||
| 29 | @@ -151,11 +151,6 @@ extern const char *vfp_output_fstmd (rtx | ||
| 30 | extern void arm_set_return_address (rtx, rtx); | ||
| 31 | extern int arm_eliminable_register (rtx); | ||
| 32 | extern const char *arm_output_shift(rtx *, int); | ||
| 33 | -extern void arm_expand_sync (enum machine_mode, struct arm_sync_generator *, | ||
| 34 | - rtx, rtx, rtx, rtx); | ||
| 35 | -extern const char *arm_output_memory_barrier (rtx *); | ||
| 36 | -extern const char *arm_output_sync_insn (rtx, rtx *); | ||
| 37 | -extern unsigned int arm_sync_loop_insns (rtx , rtx *); | ||
| 38 | |||
| 39 | extern bool arm_output_addr_const_extra (FILE *, rtx); | ||
| 40 | |||
| 41 | Index: gcc-4.5/gcc/config/arm/arm.c | ||
| 42 | =================================================================== | ||
| 43 | --- gcc-4.5.orig/gcc/config/arm/arm.c | ||
| 44 | +++ gcc-4.5/gcc/config/arm/arm.c | ||
| 45 | @@ -605,7 +605,6 @@ static int thumb_call_reg_needed; | ||
| 46 | #define FL_NEON (1 << 20) /* Neon instructions. */ | ||
| 47 | #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M | ||
| 48 | architecture. */ | ||
| 49 | -#define FL_ARCH7 (1 << 22) /* Architecture 7. */ | ||
| 50 | |||
| 51 | #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ | ||
| 52 | |||
| 53 | @@ -626,7 +625,7 @@ static int thumb_call_reg_needed; | ||
| 54 | #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K | ||
| 55 | #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) | ||
| 56 | #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) | ||
| 57 | -#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) | ||
| 58 | +#define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM) | ||
| 59 | #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) | ||
| 60 | #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) | ||
| 61 | #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) | ||
| 62 | @@ -664,9 +663,6 @@ int arm_arch6 = 0; | ||
| 63 | /* Nonzero if this chip supports the ARM 6K extensions. */ | ||
| 64 | int arm_arch6k = 0; | ||
| 65 | |||
| 66 | -/* Nonzero if this chip supports the ARM 7 extensions. */ | ||
| 67 | -int arm_arch7 = 0; | ||
| 68 | - | ||
| 69 | /* Nonzero if instructions not present in the 'M' profile can be used. */ | ||
| 70 | int arm_arch_notm = 0; | ||
| 71 | |||
| 72 | @@ -1638,7 +1634,6 @@ arm_override_options (void) | ||
| 73 | arm_arch6 = (insn_flags & FL_ARCH6) != 0; | ||
| 74 | arm_arch6k = (insn_flags & FL_ARCH6K) != 0; | ||
| 75 | arm_arch_notm = (insn_flags & FL_NOTM) != 0; | ||
| 76 | - arm_arch7 = (insn_flags & FL_ARCH7) != 0; | ||
| 77 | arm_arch7em = (insn_flags & FL_ARCH7EM) != 0; | ||
| 78 | arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; | ||
| 79 | arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; | ||
| 80 | @@ -16595,17 +16590,6 @@ arm_print_operand (FILE *stream, rtx x, | ||
| 81 | } | ||
| 82 | return; | ||
| 83 | |||
| 84 | - case 'C': | ||
| 85 | - { | ||
| 86 | - rtx addr; | ||
| 87 | - | ||
| 88 | - gcc_assert (GET_CODE (x) == MEM); | ||
| 89 | - addr = XEXP (x, 0); | ||
| 90 | - gcc_assert (GET_CODE (addr) == REG); | ||
| 91 | - asm_fprintf (stream, "[%r]", REGNO (addr)); | ||
| 92 | - } | ||
| 93 | - return; | ||
| 94 | - | ||
| 95 | /* Translate an S register number into a D register number and element index. */ | ||
| 96 | case 'y': | ||
| 97 | { | ||
| 98 | @@ -22840,372 +22824,4 @@ arm_builtin_support_vector_misalignment | ||
| 99 | is_packed); | ||
| 100 | } | ||
| 101 | |||
| 102 | -/* Legitimize a memory reference for sync primitive implemented using | ||
| 103 | - ldrex / strex. We currently force the form of the reference to be | ||
| 104 | - indirect without offset. We do not yet support the indirect offset | ||
| 105 | - addressing supported by some ARM targets for these | ||
| 106 | - instructions. */ | ||
| 107 | -static rtx | ||
| 108 | -arm_legitimize_sync_memory (rtx memory) | ||
| 109 | -{ | ||
| 110 | - rtx addr = force_reg (Pmode, XEXP (memory, 0)); | ||
| 111 | - rtx legitimate_memory = gen_rtx_MEM (GET_MODE (memory), addr); | ||
| 112 | - | ||
| 113 | - set_mem_alias_set (legitimate_memory, ALIAS_SET_MEMORY_BARRIER); | ||
| 114 | - MEM_VOLATILE_P (legitimate_memory) = MEM_VOLATILE_P (memory); | ||
| 115 | - return legitimate_memory; | ||
| 116 | -} | ||
| 117 | - | ||
| 118 | -/* An instruction emitter. */ | ||
| 119 | -typedef void (* emit_f) (int label, const char *, rtx *); | ||
| 120 | - | ||
| 121 | -/* An instruction emitter that emits via the conventional | ||
| 122 | - output_asm_insn. */ | ||
| 123 | -static void | ||
| 124 | -arm_emit (int label ATTRIBUTE_UNUSED, const char *pattern, rtx *operands) | ||
| 125 | -{ | ||
| 126 | - output_asm_insn (pattern, operands); | ||
| 127 | -} | ||
| 128 | - | ||
| 129 | -/* Count the number of emitted synchronization instructions. */ | ||
| 130 | -static unsigned arm_insn_count; | ||
| 131 | - | ||
| 132 | -/* An emitter that counts emitted instructions but does not actually | ||
| 133 | - emit instruction into the the instruction stream. */ | ||
| 134 | -static void | ||
| 135 | -arm_count (int label, | ||
| 136 | - const char *pattern ATTRIBUTE_UNUSED, | ||
| 137 | - rtx *operands ATTRIBUTE_UNUSED) | ||
| 138 | -{ | ||
| 139 | - if (! label) | ||
| 140 | - ++ arm_insn_count; | ||
| 141 | -} | ||
| 142 | - | ||
| 143 | -/* Construct a pattern using conventional output formatting and feed | ||
| 144 | - it to output_asm_insn. Provides a mechanism to construct the | ||
| 145 | - output pattern on the fly. Note the hard limit on the pattern | ||
| 146 | - buffer size. */ | ||
| 147 | -static void | ||
| 148 | -arm_output_asm_insn (emit_f emit, int label, rtx *operands, | ||
| 149 | - const char *pattern, ...) | ||
| 150 | -{ | ||
| 151 | - va_list ap; | ||
| 152 | - char buffer[256]; | ||
| 153 | - | ||
| 154 | - va_start (ap, pattern); | ||
| 155 | - vsprintf (buffer, pattern, ap); | ||
| 156 | - va_end (ap); | ||
| 157 | - emit (label, buffer, operands); | ||
| 158 | -} | ||
| 159 | - | ||
| 160 | -/* Emit the memory barrier instruction, if any, provided by this | ||
| 161 | - target to a specified emitter. */ | ||
| 162 | -static void | ||
| 163 | -arm_process_output_memory_barrier (emit_f emit, rtx *operands) | ||
| 164 | -{ | ||
| 165 | - if (TARGET_HAVE_DMB) | ||
| 166 | - { | ||
| 167 | - /* Note we issue a system level barrier. We should consider | ||
| 168 | - issuing a inner shareabilty zone barrier here instead, ie. | ||
| 169 | - "DMB ISH". */ | ||
| 170 | - emit (0, "dmb\tsy", operands); | ||
| 171 | - return; | ||
| 172 | - } | ||
| 173 | - | ||
| 174 | - if (TARGET_HAVE_DMB_MCR) | ||
| 175 | - { | ||
| 176 | - emit (0, "mcr\tp15, 0, r0, c7, c10, 5", operands); | ||
| 177 | - return; | ||
| 178 | - } | ||
| 179 | - | ||
| 180 | - gcc_unreachable (); | ||
| 181 | -} | ||
| 182 | - | ||
| 183 | -/* Emit the memory barrier instruction, if any, provided by this | ||
| 184 | - target. */ | ||
| 185 | -const char * | ||
| 186 | -arm_output_memory_barrier (rtx *operands) | ||
| 187 | -{ | ||
| 188 | - arm_process_output_memory_barrier (arm_emit, operands); | ||
| 189 | - return ""; | ||
| 190 | -} | ||
| 191 | - | ||
| 192 | -/* Helper to figure out the instruction suffix required on ldrex/strex | ||
| 193 | - for operations on an object of the specified mode. */ | ||
| 194 | -static const char * | ||
| 195 | -arm_ldrex_suffix (enum machine_mode mode) | ||
| 196 | -{ | ||
| 197 | - switch (mode) | ||
| 198 | - { | ||
| 199 | - case QImode: return "b"; | ||
| 200 | - case HImode: return "h"; | ||
| 201 | - case SImode: return ""; | ||
| 202 | - case DImode: return "d"; | ||
| 203 | - default: | ||
| 204 | - gcc_unreachable (); | ||
| 205 | - } | ||
| 206 | - return ""; | ||
| 207 | -} | ||
| 208 | - | ||
| 209 | -/* Emit an ldrex{b,h,d, } instruction appropriate for the specified | ||
| 210 | - mode. */ | ||
| 211 | -static void | ||
| 212 | -arm_output_ldrex (emit_f emit, | ||
| 213 | - enum machine_mode mode, | ||
| 214 | - rtx target, | ||
| 215 | - rtx memory) | ||
| 216 | -{ | ||
| 217 | - const char *suffix = arm_ldrex_suffix (mode); | ||
| 218 | - rtx operands[2]; | ||
| 219 | - | ||
| 220 | - operands[0] = target; | ||
| 221 | - operands[1] = memory; | ||
| 222 | - arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix); | ||
| 223 | -} | ||
| 224 | - | ||
| 225 | -/* Emit a strex{b,h,d, } instruction appropriate for the specified | ||
| 226 | - mode. */ | ||
| 227 | -static void | ||
| 228 | -arm_output_strex (emit_f emit, | ||
| 229 | - enum machine_mode mode, | ||
| 230 | - const char *cc, | ||
| 231 | - rtx result, | ||
| 232 | - rtx value, | ||
| 233 | - rtx memory) | ||
| 234 | -{ | ||
| 235 | - const char *suffix = arm_ldrex_suffix (mode); | ||
| 236 | - rtx operands[3]; | ||
| 237 | - | ||
| 238 | - operands[0] = result; | ||
| 239 | - operands[1] = value; | ||
| 240 | - operands[2] = memory; | ||
| 241 | - arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2", suffix, | ||
| 242 | - cc); | ||
| 243 | -} | ||
| 244 | - | ||
| 245 | -/* Helper to emit a two operand instruction. */ | ||
| 246 | -static void | ||
| 247 | -arm_output_op2 (emit_f emit, const char *mnemonic, rtx d, rtx s) | ||
| 248 | -{ | ||
| 249 | - rtx operands[2]; | ||
| 250 | - | ||
| 251 | - operands[0] = d; | ||
| 252 | - operands[1] = s; | ||
| 253 | - arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1", mnemonic); | ||
| 254 | -} | ||
| 255 | - | ||
| 256 | -/* Helper to emit a three operand instruction. */ | ||
| 257 | -static void | ||
| 258 | -arm_output_op3 (emit_f emit, const char *mnemonic, rtx d, rtx a, rtx b) | ||
| 259 | -{ | ||
| 260 | - rtx operands[3]; | ||
| 261 | - | ||
| 262 | - operands[0] = d; | ||
| 263 | - operands[1] = a; | ||
| 264 | - operands[2] = b; | ||
| 265 | - arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1, %%2", mnemonic); | ||
| 266 | -} | ||
| 267 | - | ||
| 268 | -/* Emit a load store exclusive synchronization loop. | ||
| 269 | - | ||
| 270 | - do | ||
| 271 | - old_value = [mem] | ||
| 272 | - if old_value != required_value | ||
| 273 | - break; | ||
| 274 | - t1 = sync_op (old_value, new_value) | ||
| 275 | - [mem] = t1, t2 = [0|1] | ||
| 276 | - while ! t2 | ||
| 277 | - | ||
| 278 | - Note: | ||
| 279 | - t1 == t2 is not permitted | ||
| 280 | - t1 == old_value is permitted | ||
| 281 | - | ||
| 282 | - required_value: | ||
| 283 | - | ||
| 284 | - RTX register or const_int representing the required old_value for | ||
| 285 | - the modify to continue, if NULL no comparsion is performed. */ | ||
| 286 | -static void | ||
| 287 | -arm_output_sync_loop (emit_f emit, | ||
| 288 | - enum machine_mode mode, | ||
| 289 | - rtx old_value, | ||
| 290 | - rtx memory, | ||
| 291 | - rtx required_value, | ||
| 292 | - rtx new_value, | ||
| 293 | - rtx t1, | ||
| 294 | - rtx t2, | ||
| 295 | - enum attr_sync_op sync_op, | ||
| 296 | - int early_barrier_required) | ||
| 297 | -{ | ||
| 298 | - rtx operands[1]; | ||
| 299 | - | ||
| 300 | - gcc_assert (t1 != t2); | ||
| 301 | - | ||
| 302 | - if (early_barrier_required) | ||
| 303 | - arm_process_output_memory_barrier (emit, NULL); | ||
| 304 | - | ||
| 305 | - arm_output_asm_insn (emit, 1, operands, "%sLSYT%%=:", LOCAL_LABEL_PREFIX); | ||
| 306 | - | ||
| 307 | - arm_output_ldrex (emit, mode, old_value, memory); | ||
| 308 | - | ||
| 309 | - if (required_value) | ||
| 310 | - { | ||
| 311 | - rtx operands[2]; | ||
| 312 | - | ||
| 313 | - operands[0] = old_value; | ||
| 314 | - operands[1] = required_value; | ||
| 315 | - arm_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1"); | ||
| 316 | - arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX); | ||
| 317 | - } | ||
| 318 | - | ||
| 319 | - switch (sync_op) | ||
| 320 | - { | ||
| 321 | - case SYNC_OP_ADD: | ||
| 322 | - arm_output_op3 (emit, "add", t1, old_value, new_value); | ||
| 323 | - break; | ||
| 324 | - | ||
| 325 | - case SYNC_OP_SUB: | ||
| 326 | - arm_output_op3 (emit, "sub", t1, old_value, new_value); | ||
| 327 | - break; | ||
| 328 | - | ||
| 329 | - case SYNC_OP_IOR: | ||
| 330 | - arm_output_op3 (emit, "orr", t1, old_value, new_value); | ||
| 331 | - break; | ||
| 332 | - | ||
| 333 | - case SYNC_OP_XOR: | ||
| 334 | - arm_output_op3 (emit, "eor", t1, old_value, new_value); | ||
| 335 | - break; | ||
| 336 | - | ||
| 337 | - case SYNC_OP_AND: | ||
| 338 | - arm_output_op3 (emit,"and", t1, old_value, new_value); | ||
| 339 | - break; | ||
| 340 | - | ||
| 341 | - case SYNC_OP_NAND: | ||
| 342 | - arm_output_op3 (emit, "and", t1, old_value, new_value); | ||
| 343 | - arm_output_op2 (emit, "mvn", t1, t1); | ||
| 344 | - break; | ||
| 345 | - | ||
| 346 | - case SYNC_OP_NONE: | ||
| 347 | - t1 = new_value; | ||
| 348 | - break; | ||
| 349 | - } | ||
| 350 | - | ||
| 351 | - arm_output_strex (emit, mode, "", t2, t1, memory); | ||
| 352 | - operands[0] = t2; | ||
| 353 | - arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0"); | ||
| 354 | - arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", LOCAL_LABEL_PREFIX); | ||
| 355 | - | ||
| 356 | - arm_process_output_memory_barrier (emit, NULL); | ||
| 357 | - arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX); | ||
| 358 | -} | ||
| 359 | - | ||
| 360 | -static rtx | ||
| 361 | -arm_get_sync_operand (rtx *operands, int index, rtx default_value) | ||
| 362 | -{ | ||
| 363 | - if (index > 0) | ||
| 364 | - default_value = operands[index - 1]; | ||
| 365 | - | ||
| 366 | - return default_value; | ||
| 367 | -} | ||
| 368 | - | ||
| 369 | -#define FETCH_SYNC_OPERAND(NAME, DEFAULT) \ | ||
| 370 | - arm_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), DEFAULT); | ||
| 371 | - | ||
| 372 | -/* Extract the operands for a synchroniztion instruction from the | ||
| 373 | - instructions attributes and emit the instruction. */ | ||
| 374 | -static void | ||
| 375 | -arm_process_output_sync_insn (emit_f emit, rtx insn, rtx *operands) | ||
| 376 | -{ | ||
| 377 | - rtx result, memory, required_value, new_value, t1, t2; | ||
| 378 | - int early_barrier; | ||
| 379 | - enum machine_mode mode; | ||
| 380 | - enum attr_sync_op sync_op; | ||
| 381 | - | ||
| 382 | - result = FETCH_SYNC_OPERAND(result, 0); | ||
| 383 | - memory = FETCH_SYNC_OPERAND(memory, 0); | ||
| 384 | - required_value = FETCH_SYNC_OPERAND(required_value, 0); | ||
| 385 | - new_value = FETCH_SYNC_OPERAND(new_value, 0); | ||
| 386 | - t1 = FETCH_SYNC_OPERAND(t1, 0); | ||
| 387 | - t2 = FETCH_SYNC_OPERAND(t2, 0); | ||
| 388 | - early_barrier = | ||
| 389 | - get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES; | ||
| 390 | - sync_op = get_attr_sync_op (insn); | ||
| 391 | - mode = GET_MODE (memory); | ||
| 392 | - | ||
| 393 | - arm_output_sync_loop (emit, mode, result, memory, required_value, | ||
| 394 | - new_value, t1, t2, sync_op, early_barrier); | ||
| 395 | -} | ||
| 396 | - | ||
| 397 | -/* Emit a synchronization instruction loop. */ | ||
| 398 | -const char * | ||
| 399 | -arm_output_sync_insn (rtx insn, rtx *operands) | ||
| 400 | -{ | ||
| 401 | - arm_process_output_sync_insn (arm_emit, insn, operands); | ||
| 402 | - return ""; | ||
| 403 | -} | ||
| 404 | - | ||
| 405 | -/* Count the number of machine instruction that will be emitted for a | ||
| 406 | - synchronization instruction. Note that the emitter used does not | ||
| 407 | - emit instructions, it just counts instructions being carefull not | ||
| 408 | - to count labels. */ | ||
| 409 | -unsigned int | ||
| 410 | -arm_sync_loop_insns (rtx insn, rtx *operands) | ||
| 411 | -{ | ||
| 412 | - arm_insn_count = 0; | ||
| 413 | - arm_process_output_sync_insn (arm_count, insn, operands); | ||
| 414 | - return arm_insn_count; | ||
| 415 | -} | ||
| 416 | - | ||
| 417 | -/* Helper to call a target sync instruction generator, dealing with | ||
| 418 | - the variation in operands required by the different generators. */ | ||
| 419 | -static rtx | ||
| 420 | -arm_call_generator (struct arm_sync_generator *generator, rtx old_value, | ||
| 421 | - rtx memory, rtx required_value, rtx new_value) | ||
| 422 | -{ | ||
| 423 | - switch (generator->op) | ||
| 424 | - { | ||
| 425 | - case arm_sync_generator_omn: | ||
| 426 | - gcc_assert (! required_value); | ||
| 427 | - return generator->u.omn (old_value, memory, new_value); | ||
| 428 | - | ||
| 429 | - case arm_sync_generator_omrn: | ||
| 430 | - gcc_assert (required_value); | ||
| 431 | - return generator->u.omrn (old_value, memory, required_value, new_value); | ||
| 432 | - } | ||
| 433 | - | ||
| 434 | - return NULL; | ||
| 435 | -} | ||
| 436 | - | ||
| 437 | -/* Expand a synchronization loop. The synchronization loop is expanded | ||
| 438 | - as an opaque block of instructions in order to ensure that we do | ||
| 439 | - not subsequently get extraneous memory accesses inserted within the | ||
| 440 | - critical region. The exclusive access property of ldrex/strex is | ||
| 441 | - only guaranteed in there are no intervening memory accesses. */ | ||
| 442 | -void | ||
| 443 | -arm_expand_sync (enum machine_mode mode, | ||
| 444 | - struct arm_sync_generator *generator, | ||
| 445 | - rtx target, rtx memory, rtx required_value, rtx new_value) | ||
| 446 | -{ | ||
| 447 | - if (target == NULL) | ||
| 448 | - target = gen_reg_rtx (mode); | ||
| 449 | - | ||
| 450 | - memory = arm_legitimize_sync_memory (memory); | ||
| 451 | - if (mode != SImode) | ||
| 452 | - { | ||
| 453 | - rtx load_temp = gen_reg_rtx (SImode); | ||
| 454 | - | ||
| 455 | - if (required_value) | ||
| 456 | - required_value = convert_modes (SImode, mode, required_value, true); | ||
| 457 | - | ||
| 458 | - new_value = convert_modes (SImode, mode, new_value, true); | ||
| 459 | - emit_insn (arm_call_generator (generator, load_temp, memory, | ||
| 460 | - required_value, new_value)); | ||
| 461 | - emit_move_insn (target, gen_lowpart (mode, load_temp)); | ||
| 462 | - } | ||
| 463 | - else | ||
| 464 | - { | ||
| 465 | - emit_insn (arm_call_generator (generator, target, memory, required_value, | ||
| 466 | - new_value)); | ||
| 467 | - } | ||
| 468 | -} | ||
| 469 | - | ||
| 470 | #include "gt-arm.h" | ||
| 471 | Index: gcc-4.5/gcc/config/arm/arm.h | ||
| 472 | =================================================================== | ||
| 473 | --- gcc-4.5.orig/gcc/config/arm/arm.h | ||
| 474 | +++ gcc-4.5/gcc/config/arm/arm.h | ||
| 475 | @@ -128,24 +128,6 @@ enum target_cpus | ||
| 476 | /* The processor for which instructions should be scheduled. */ | ||
| 477 | extern enum processor_type arm_tune; | ||
| 478 | |||
| 479 | -enum arm_sync_generator_tag | ||
| 480 | - { | ||
| 481 | - arm_sync_generator_omn, | ||
| 482 | - arm_sync_generator_omrn | ||
| 483 | - }; | ||
| 484 | - | ||
| 485 | -/* Wrapper to pass around a polymorphic pointer to a sync instruction | ||
| 486 | - generator and. */ | ||
| 487 | -struct arm_sync_generator | ||
| 488 | -{ | ||
| 489 | - enum arm_sync_generator_tag op; | ||
| 490 | - union | ||
| 491 | - { | ||
| 492 | - rtx (* omn) (rtx, rtx, rtx); | ||
| 493 | - rtx (* omrn) (rtx, rtx, rtx, rtx); | ||
| 494 | - } u; | ||
| 495 | -}; | ||
| 496 | - | ||
| 497 | typedef enum arm_cond_code | ||
| 498 | { | ||
| 499 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | ||
| 500 | @@ -290,20 +272,6 @@ extern void (*arm_lang_output_object_att | ||
| 501 | for Thumb-2. */ | ||
| 502 | #define TARGET_UNIFIED_ASM TARGET_THUMB2 | ||
| 503 | |||
| 504 | -/* Nonzero if this chip provides the DMB instruction. */ | ||
| 505 | -#define TARGET_HAVE_DMB (arm_arch7) | ||
| 506 | - | ||
| 507 | -/* Nonzero if this chip implements a memory barrier via CP15. */ | ||
| 508 | -#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB) | ||
| 509 | - | ||
| 510 | -/* Nonzero if this chip implements a memory barrier instruction. */ | ||
| 511 | -#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) | ||
| 512 | - | ||
| 513 | -/* Nonzero if this chip supports ldrex and strex */ | ||
| 514 | -#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) | ||
| 515 | - | ||
| 516 | -/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */ | ||
| 517 | -#define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7) | ||
| 518 | |||
| 519 | /* True iff the full BPABI is being used. If TARGET_BPABI is true, | ||
| 520 | then TARGET_AAPCS_BASED must be true -- but the converse does not | ||
| 521 | @@ -437,12 +405,6 @@ extern int arm_arch5e; | ||
| 522 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ | ||
| 523 | extern int arm_arch6; | ||
| 524 | |||
| 525 | -/* Nonzero if this chip supports the ARM Architecture 6k extensions. */ | ||
| 526 | -extern int arm_arch6k; | ||
| 527 | - | ||
| 528 | -/* Nonzero if this chip supports the ARM Architecture 7 extensions. */ | ||
| 529 | -extern int arm_arch7; | ||
| 530 | - | ||
| 531 | /* Nonzero if instructions not present in the 'M' profile can be used. */ | ||
| 532 | extern int arm_arch_notm; | ||
| 533 | |||
| 534 | Index: gcc-4.5/gcc/config/arm/arm.md | ||
| 535 | =================================================================== | ||
| 536 | --- gcc-4.5.orig/gcc/config/arm/arm.md | ||
| 537 | +++ gcc-4.5/gcc/config/arm/arm.md | ||
| 538 | @@ -103,7 +103,6 @@ | ||
| 539 | (UNSPEC_RBIT 26) ; rbit operation. | ||
| 540 | (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from | ||
| 541 | ; another symbolic address. | ||
| 542 | - (UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier. | ||
| 543 | ] | ||
| 544 | ) | ||
| 545 | |||
| 546 | @@ -140,11 +139,6 @@ | ||
| 547 | (VUNSPEC_ALIGN32 16) ; Used to force 32-byte alignment. | ||
| 548 | (VUNSPEC_EH_RETURN 20); Use to override the return address for exception | ||
| 549 | ; handling. | ||
| 550 | - (VUNSPEC_SYNC_COMPARE_AND_SWAP 21) ; Represent an atomic compare swap. | ||
| 551 | - (VUNSPEC_SYNC_LOCK 22) ; Represent a sync_lock_test_and_set. | ||
| 552 | - (VUNSPEC_SYNC_OP 23) ; Represent a sync_<op> | ||
| 553 | - (VUNSPEC_SYNC_NEW_OP 24) ; Represent a sync_new_<op> | ||
| 554 | - (VUNSPEC_SYNC_OLD_OP 25) ; Represent a sync_old_<op> | ||
| 555 | ] | ||
| 556 | ) | ||
| 557 | |||
| 558 | @@ -169,21 +163,8 @@ | ||
| 559 | (define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp" | ||
| 560 | (const (symbol_ref "arm_fpu_attr"))) | ||
| 561 | |||
| 562 | -(define_attr "sync_result" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 563 | -(define_attr "sync_memory" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 564 | -(define_attr "sync_required_value" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 565 | -(define_attr "sync_new_value" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 566 | -(define_attr "sync_t1" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 567 | -(define_attr "sync_t2" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 568 | -(define_attr "sync_release_barrier" "yes,no" (const_string "yes")) | ||
| 569 | -(define_attr "sync_op" "none,add,sub,ior,xor,and,nand" | ||
| 570 | - (const_string "none")) | ||
| 571 | - | ||
| 572 | ; LENGTH of an instruction (in bytes) | ||
| 573 | -(define_attr "length" "" | ||
| 574 | - (cond [(not (eq_attr "sync_memory" "none")) | ||
| 575 | - (symbol_ref "arm_sync_loop_insns (insn, operands) * 4") | ||
| 576 | - ] (const_int 4))) | ||
| 577 | +(define_attr "length" "" (const_int 4)) | ||
| 578 | |||
| 579 | ; POOL_RANGE is how far away from a constant pool entry that this insn | ||
| 580 | ; can be placed. If the distance is zero, then this insn will never | ||
| 581 | @@ -11568,5 +11549,4 @@ | ||
| 582 | (include "thumb2.md") | ||
| 583 | ;; Neon patterns | ||
| 584 | (include "neon.md") | ||
| 585 | -;; Synchronization Primitives | ||
| 586 | -(include "sync.md") | ||
| 587 | + | ||
| 588 | Index: gcc-4.5/gcc/config/arm/predicates.md | ||
| 589 | =================================================================== | ||
| 590 | --- gcc-4.5.orig/gcc/config/arm/predicates.md | ||
| 591 | +++ gcc-4.5/gcc/config/arm/predicates.md | ||
| 592 | @@ -573,11 +573,6 @@ | ||
| 593 | (and (match_test "TARGET_32BIT") | ||
| 594 | (match_operand 0 "arm_di_operand")))) | ||
| 595 | |||
| 596 | -;; True if the operand is memory reference suitable for a ldrex/strex. | ||
| 597 | -(define_predicate "arm_sync_memory_operand" | ||
| 598 | - (and (match_operand 0 "memory_operand") | ||
| 599 | - (match_code "reg" "0"))) | ||
| 600 | - | ||
| 601 | ;; Predicates for parallel expanders based on mode. | ||
| 602 | (define_special_predicate "vect_par_constant_high" | ||
| 603 | (match_code "parallel") | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99409.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99409.patch deleted file mode 100644 index 39c3ab081..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99409.patch +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | 2010-09-30 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/testsuite/ | ||
| 4 | * gcc.target/arm/neon-thumb2-move.c: Add | ||
| 5 | dg-require-effective-target arm_thumb2_ok. | ||
| 6 | |||
| 7 | === modified file 'gcc/testsuite/gcc.target/arm/neon-thumb2-move.c' | ||
| 8 | Index: gcc-4.5/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c | ||
| 9 | =================================================================== | ||
| 10 | --- gcc-4.5.orig/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c | ||
| 11 | +++ gcc-4.5/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c | ||
| 12 | @@ -1,5 +1,6 @@ | ||
| 13 | /* { dg-do compile } */ | ||
| 14 | /* { dg-require-effective-target arm_neon_ok } */ | ||
| 15 | +/* { dg-require-effective-target arm_thumb2_ok } */ | ||
| 16 | /* { dg-options "-O2 -mthumb -march=armv7-a" } */ | ||
| 17 | /* { dg-add-options arm_neon } */ | ||
| 18 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99410.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99410.patch deleted file mode 100644 index f2a1c9562..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99410.patch +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | 2010-10-06 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/testsuite/ | ||
| 4 | * gcc.dg/Warray-bounds-3.c: Add -fno-unroll-loops for ARM. | ||
| 5 | * gcc.dg/vect/vect.exp: Likewise, for all vect tests. | ||
| 6 | |||
| 7 | |||
| 8 | === modified file 'gcc/testsuite/gcc.dg/Warray-bounds-3.c' | ||
| 9 | Index: gcc-4.5/gcc/testsuite/gcc.dg/Warray-bounds-3.c | ||
| 10 | =================================================================== | ||
| 11 | --- gcc-4.5.orig/gcc/testsuite/gcc.dg/Warray-bounds-3.c | ||
| 12 | +++ gcc-4.5/gcc/testsuite/gcc.dg/Warray-bounds-3.c | ||
| 13 | @@ -1,5 +1,7 @@ | ||
| 14 | /* { dg-do compile } */ | ||
| 15 | /* { dg-options "-O2 -Warray-bounds" } */ | ||
| 16 | +/* { dg-options "-O2 -Warray-bounds -fno-unroll-loops" { target arm*-*-* } } */ | ||
| 17 | + | ||
| 18 | /* based on PR 31227 */ | ||
| 19 | |||
| 20 | typedef __SIZE_TYPE__ size_t; | ||
| 21 | Index: gcc-4.5/gcc/testsuite/gcc.dg/vect/vect.exp | ||
| 22 | =================================================================== | ||
| 23 | --- gcc-4.5.orig/gcc/testsuite/gcc.dg/vect/vect.exp | ||
| 24 | +++ gcc-4.5/gcc/testsuite/gcc.dg/vect/vect.exp | ||
| 25 | @@ -109,6 +109,7 @@ if [istarget "powerpc-*paired*"] { | ||
| 26 | # default to avoid loss of precision. We must pass -ffast-math to test | ||
| 27 | # vectorization of float operations. | ||
| 28 | lappend DEFAULT_VECTCFLAGS "-ffast-math" | ||
| 29 | + lappend DEFAULT_VECTCFLAGS "-fno-unroll-loops" | ||
| 30 | if [is-effective-target arm_neon_hw] { | ||
| 31 | set dg-do-what-default run | ||
| 32 | } else { | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99411.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99411.patch deleted file mode 100644 index c9a931686..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99411.patch +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | 2010-10-08 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | * config/arm/arm.c (arm_override_options): Disable | ||
| 4 | -fsched-interblock for Cortex-M4. | ||
| 5 | |||
| 6 | === modified file 'gcc/config/arm/arm.c' | ||
| 7 | Index: gcc-4.5/gcc/config/arm/arm.c | ||
| 8 | =================================================================== | ||
| 9 | --- gcc-4.5.orig/gcc/config/arm/arm.c | ||
| 10 | +++ gcc-4.5/gcc/config/arm/arm.c | ||
| 11 | @@ -1913,6 +1913,10 @@ arm_override_options (void) | ||
| 12 | fix_cm3_ldrd = 0; | ||
| 13 | } | ||
| 14 | |||
| 15 | + /* Disable -fsched-interblock for Cortex-M4. */ | ||
| 16 | + if (arm_selected_tune->core == cortexm4) | ||
| 17 | + flag_schedule_interblock = 0; | ||
| 18 | + | ||
| 19 | if (TARGET_THUMB1 && flag_schedule_insns) | ||
| 20 | { | ||
| 21 | /* Don't warn since it's on by default in -O2. */ | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99412.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99412.patch deleted file mode 100644 index c0aabbeb5..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99412.patch +++ /dev/null | |||
| @@ -1,316 +0,0 @@ | |||
| 1 | 2010-10-09 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | 2010-06-03 Paul Brook <paul@codesourcery.com> | ||
| 7 | * config/arm/arm.c (FL_TUNE): Define. | ||
| 8 | (arm_default_cpu, arm_cpu_select): Remove. | ||
| 9 | (all_cores): Populate core field. | ||
| 10 | (arm_selected_arch, arm_selected_cpu, arm_selected_tune): New. | ||
| 11 | (arm_find_cpu): New function. | ||
| 12 | (arm_handle_option): Lookup cpu/architecture names. | ||
| 13 | (arm_override_options): Cleanup mcpu/march/mtune handling. | ||
| 14 | (arm_file_start): Ditto. | ||
| 15 | |||
| 16 | === modified file 'gcc/config/arm/arm.c' | ||
| 17 | Index: gcc-4.5/gcc/config/arm/arm.c | ||
| 18 | =================================================================== | ||
| 19 | --- gcc-4.5.orig/gcc/config/arm/arm.c | ||
| 20 | +++ gcc-4.5/gcc/config/arm/arm.c | ||
| 21 | @@ -550,9 +550,6 @@ enum processor_type arm_tune = arm_none; | ||
| 22 | /* The current tuning set. */ | ||
| 23 | const struct tune_params *current_tune; | ||
| 24 | |||
| 25 | -/* The default processor used if not overridden by commandline. */ | ||
| 26 | -static enum processor_type arm_default_cpu = arm_none; | ||
| 27 | - | ||
| 28 | /* Which floating point hardware to schedule for. */ | ||
| 29 | int arm_fpu_attr; | ||
| 30 | |||
| 31 | @@ -608,6 +605,10 @@ static int thumb_call_reg_needed; | ||
| 32 | |||
| 33 | #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ | ||
| 34 | |||
| 35 | +/* Flags that only effect tuning, not available instructions. */ | ||
| 36 | +#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ | ||
| 37 | + | FL_CO_PROC) | ||
| 38 | + | ||
| 39 | #define FL_FOR_ARCH2 FL_NOTM | ||
| 40 | #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) | ||
| 41 | #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) | ||
| 42 | @@ -808,7 +809,7 @@ static const struct processors all_cores | ||
| 43 | { | ||
| 44 | /* ARM Cores */ | ||
| 45 | #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ | ||
| 46 | - {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune}, | ||
| 47 | + {NAME, IDENT, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune}, | ||
| 48 | #include "arm-cores.def" | ||
| 49 | #undef ARM_CORE | ||
| 50 | {NULL, arm_none, NULL, 0, NULL} | ||
| 51 | @@ -850,29 +851,12 @@ static const struct processors all_archi | ||
| 52 | {NULL, arm_none, NULL, 0 , NULL} | ||
| 53 | }; | ||
| 54 | |||
| 55 | -struct arm_cpu_select | ||
| 56 | -{ | ||
| 57 | - const char * string; | ||
| 58 | - const char * name; | ||
| 59 | - const struct processors * processors; | ||
| 60 | -}; | ||
| 61 | - | ||
| 62 | -/* This is a magic structure. The 'string' field is magically filled in | ||
| 63 | - with a pointer to the value specified by the user on the command line | ||
| 64 | - assuming that the user has specified such a value. */ | ||
| 65 | - | ||
| 66 | -static struct arm_cpu_select arm_select[] = | ||
| 67 | -{ | ||
| 68 | - /* string name processors */ | ||
| 69 | - { NULL, "-mcpu=", all_cores }, | ||
| 70 | - { NULL, "-march=", all_architectures }, | ||
| 71 | - { NULL, "-mtune=", all_cores } | ||
| 72 | -}; | ||
| 73 | |||
| 74 | -/* Defines representing the indexes into the above table. */ | ||
| 75 | -#define ARM_OPT_SET_CPU 0 | ||
| 76 | -#define ARM_OPT_SET_ARCH 1 | ||
| 77 | -#define ARM_OPT_SET_TUNE 2 | ||
| 78 | +/* These are populated as commandline arguments are processed, or NULL | ||
| 79 | + if not specified. */ | ||
| 80 | +static const struct processors *arm_selected_arch; | ||
| 81 | +static const struct processors *arm_selected_cpu; | ||
| 82 | +static const struct processors *arm_selected_tune; | ||
| 83 | |||
| 84 | /* The name of the preprocessor macro to define for this architecture. */ | ||
| 85 | |||
| 86 | @@ -1234,6 +1218,24 @@ arm_gimplify_va_arg_expr (tree valist, t | ||
| 87 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); | ||
| 88 | } | ||
| 89 | |||
| 90 | +/* Lookup NAME in SEL. */ | ||
| 91 | + | ||
| 92 | +static const struct processors * | ||
| 93 | +arm_find_cpu (const char *name, const struct processors *sel, const char *desc) | ||
| 94 | +{ | ||
| 95 | + if (!(name && *name)) | ||
| 96 | + return NULL; | ||
| 97 | + | ||
| 98 | + for (; sel->name != NULL; sel++) | ||
| 99 | + { | ||
| 100 | + if (streq (name, sel->name)) | ||
| 101 | + return sel; | ||
| 102 | + } | ||
| 103 | + | ||
| 104 | + error ("bad value (%s) for %s switch", name, desc); | ||
| 105 | + return NULL; | ||
| 106 | +} | ||
| 107 | + | ||
| 108 | /* Implement TARGET_HANDLE_OPTION. */ | ||
| 109 | |||
| 110 | static bool | ||
| 111 | @@ -1242,11 +1244,11 @@ arm_handle_option (size_t code, const ch | ||
| 112 | switch (code) | ||
| 113 | { | ||
| 114 | case OPT_march_: | ||
| 115 | - arm_select[1].string = arg; | ||
| 116 | + arm_selected_arch = arm_find_cpu(arg, all_architectures, "-march"); | ||
| 117 | return true; | ||
| 118 | |||
| 119 | case OPT_mcpu_: | ||
| 120 | - arm_select[0].string = arg; | ||
| 121 | + arm_selected_cpu = arm_find_cpu(arg, all_cores, "-mcpu"); | ||
| 122 | return true; | ||
| 123 | |||
| 124 | case OPT_mhard_float: | ||
| 125 | @@ -1258,7 +1260,7 @@ arm_handle_option (size_t code, const ch | ||
| 126 | return true; | ||
| 127 | |||
| 128 | case OPT_mtune_: | ||
| 129 | - arm_select[2].string = arg; | ||
| 130 | + arm_selected_tune = arm_find_cpu(arg, all_cores, "-mtune"); | ||
| 131 | return true; | ||
| 132 | |||
| 133 | default: | ||
| 134 | @@ -1358,88 +1360,52 @@ void | ||
| 135 | arm_override_options (void) | ||
| 136 | { | ||
| 137 | unsigned i; | ||
| 138 | - enum processor_type target_arch_cpu = arm_none; | ||
| 139 | - enum processor_type selected_cpu = arm_none; | ||
| 140 | |||
| 141 | - /* Set up the flags based on the cpu/architecture selected by the user. */ | ||
| 142 | - for (i = ARRAY_SIZE (arm_select); i--;) | ||
| 143 | + if (arm_selected_arch) | ||
| 144 | { | ||
| 145 | - struct arm_cpu_select * ptr = arm_select + i; | ||
| 146 | - | ||
| 147 | - if (ptr->string != NULL && ptr->string[0] != '\0') | ||
| 148 | - { | ||
| 149 | - const struct processors * sel; | ||
| 150 | - | ||
| 151 | - for (sel = ptr->processors; sel->name != NULL; sel++) | ||
| 152 | - if (streq (ptr->string, sel->name)) | ||
| 153 | - { | ||
| 154 | - /* Set the architecture define. */ | ||
| 155 | - if (i != ARM_OPT_SET_TUNE) | ||
| 156 | - sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); | ||
| 157 | - | ||
| 158 | - /* Determine the processor core for which we should | ||
| 159 | - tune code-generation. */ | ||
| 160 | - if (/* -mcpu= is a sensible default. */ | ||
| 161 | - i == ARM_OPT_SET_CPU | ||
| 162 | - /* -mtune= overrides -mcpu= and -march=. */ | ||
| 163 | - || i == ARM_OPT_SET_TUNE) | ||
| 164 | - arm_tune = (enum processor_type) (sel - ptr->processors); | ||
| 165 | - | ||
| 166 | - /* Remember the CPU associated with this architecture. | ||
| 167 | - If no other option is used to set the CPU type, | ||
| 168 | - we'll use this to guess the most suitable tuning | ||
| 169 | - options. */ | ||
| 170 | - if (i == ARM_OPT_SET_ARCH) | ||
| 171 | - target_arch_cpu = sel->core; | ||
| 172 | - | ||
| 173 | - if (i == ARM_OPT_SET_CPU) | ||
| 174 | - selected_cpu = (enum processor_type) (sel - ptr->processors); | ||
| 175 | - | ||
| 176 | - if (i != ARM_OPT_SET_TUNE) | ||
| 177 | - { | ||
| 178 | - /* If we have been given an architecture and a processor | ||
| 179 | - make sure that they are compatible. We only generate | ||
| 180 | - a warning though, and we prefer the CPU over the | ||
| 181 | - architecture. */ | ||
| 182 | - if (insn_flags != 0 && (insn_flags ^ sel->flags)) | ||
| 183 | - warning (0, "switch -mcpu=%s conflicts with -march= switch", | ||
| 184 | - ptr->string); | ||
| 185 | - | ||
| 186 | - insn_flags = sel->flags; | ||
| 187 | - } | ||
| 188 | - | ||
| 189 | - break; | ||
| 190 | - } | ||
| 191 | + if (arm_selected_cpu) | ||
| 192 | + { | ||
| 193 | + /* Check for conflict between mcpu and march */ | ||
| 194 | + if ((arm_selected_cpu->flags ^ arm_selected_arch->flags) & ~FL_TUNE) | ||
| 195 | + { | ||
| 196 | + warning (0, "switch -mcpu=%s conflicts with -march=%s switch", | ||
| 197 | + arm_selected_cpu->name, arm_selected_arch->name); | ||
| 198 | + /* -march wins for code generation. | ||
| 199 | + -mcpu wins for default tuning. */ | ||
| 200 | + if (!arm_selected_tune) | ||
| 201 | + arm_selected_tune = arm_selected_cpu; | ||
| 202 | |||
| 203 | - if (sel->name == NULL) | ||
| 204 | - error ("bad value (%s) for %s switch", ptr->string, ptr->name); | ||
| 205 | - } | ||
| 206 | + arm_selected_cpu = arm_selected_arch; | ||
| 207 | + } | ||
| 208 | + else | ||
| 209 | + /* -mcpu wins. */ | ||
| 210 | + arm_selected_arch = NULL; | ||
| 211 | + } | ||
| 212 | + else | ||
| 213 | + /* Pick a CPU based on the architecture. */ | ||
| 214 | + arm_selected_cpu = arm_selected_arch; | ||
| 215 | } | ||
| 216 | |||
| 217 | - /* Guess the tuning options from the architecture if necessary. */ | ||
| 218 | - if (arm_tune == arm_none) | ||
| 219 | - arm_tune = target_arch_cpu; | ||
| 220 | - | ||
| 221 | /* If the user did not specify a processor, choose one for them. */ | ||
| 222 | - if (insn_flags == 0) | ||
| 223 | + if (!arm_selected_cpu) | ||
| 224 | { | ||
| 225 | const struct processors * sel; | ||
| 226 | unsigned int sought; | ||
| 227 | |||
| 228 | - selected_cpu = (enum processor_type) TARGET_CPU_DEFAULT; | ||
| 229 | - if (selected_cpu == arm_none) | ||
| 230 | + arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT]; | ||
| 231 | + if (!arm_selected_cpu->name) | ||
| 232 | { | ||
| 233 | #ifdef SUBTARGET_CPU_DEFAULT | ||
| 234 | /* Use the subtarget default CPU if none was specified by | ||
| 235 | configure. */ | ||
| 236 | - selected_cpu = (enum processor_type) SUBTARGET_CPU_DEFAULT; | ||
| 237 | + arm_selected_cpu = &all_cores[SUBTARGET_CPU_DEFAULT]; | ||
| 238 | #endif | ||
| 239 | /* Default to ARM6. */ | ||
| 240 | - if (selected_cpu == arm_none) | ||
| 241 | - selected_cpu = arm6; | ||
| 242 | + if (arm_selected_cpu->name) | ||
| 243 | + arm_selected_cpu = &all_cores[arm6]; | ||
| 244 | } | ||
| 245 | - sel = &all_cores[selected_cpu]; | ||
| 246 | |||
| 247 | + sel = arm_selected_cpu; | ||
| 248 | insn_flags = sel->flags; | ||
| 249 | |||
| 250 | /* Now check to see if the user has specified some command line | ||
| 251 | @@ -1500,17 +1466,21 @@ arm_override_options (void) | ||
| 252 | sel = best_fit; | ||
| 253 | } | ||
| 254 | |||
| 255 | - insn_flags = sel->flags; | ||
| 256 | + arm_selected_cpu = sel; | ||
| 257 | } | ||
| 258 | - sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); | ||
| 259 | - arm_default_cpu = (enum processor_type) (sel - all_cores); | ||
| 260 | - if (arm_tune == arm_none) | ||
| 261 | - arm_tune = arm_default_cpu; | ||
| 262 | } | ||
| 263 | |||
| 264 | - /* The processor for which we should tune should now have been | ||
| 265 | - chosen. */ | ||
| 266 | - gcc_assert (arm_tune != arm_none); | ||
| 267 | + gcc_assert (arm_selected_cpu); | ||
| 268 | + /* The selected cpu may be an architecture, so lookup tuning by core ID. */ | ||
| 269 | + if (!arm_selected_tune) | ||
| 270 | + arm_selected_tune = &all_cores[arm_selected_cpu->core]; | ||
| 271 | + | ||
| 272 | + sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_selected_cpu->arch); | ||
| 273 | + insn_flags = arm_selected_cpu->flags; | ||
| 274 | + | ||
| 275 | + arm_tune = arm_selected_tune->core; | ||
| 276 | + tune_flags = arm_selected_tune->flags; | ||
| 277 | + current_tune = arm_selected_tune->tune; | ||
| 278 | |||
| 279 | if (arm_tune == cortexa8 && optimize >= 3) | ||
| 280 | { | ||
| 281 | @@ -1522,9 +1492,6 @@ arm_override_options (void) | ||
| 282 | align_jumps = 16; | ||
| 283 | } | ||
| 284 | |||
| 285 | - tune_flags = all_cores[(int)arm_tune].flags; | ||
| 286 | - current_tune = all_cores[(int)arm_tune].tune; | ||
| 287 | - | ||
| 288 | if (target_fp16_format_name) | ||
| 289 | { | ||
| 290 | for (i = 0; i < ARRAY_SIZE (all_fp16_formats); i++) | ||
| 291 | @@ -1907,7 +1874,7 @@ arm_override_options (void) | ||
| 292 | /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */ | ||
| 293 | if (fix_cm3_ldrd == 2) | ||
| 294 | { | ||
| 295 | - if (selected_cpu == cortexm3) | ||
| 296 | + if (arm_selected_cpu->core == cortexm3) | ||
| 297 | fix_cm3_ldrd = 1; | ||
| 298 | else | ||
| 299 | fix_cm3_ldrd = 0; | ||
| 300 | @@ -21235,13 +21202,10 @@ arm_file_start (void) | ||
| 301 | if (TARGET_BPABI) | ||
| 302 | { | ||
| 303 | const char *fpu_name; | ||
| 304 | - if (arm_select[0].string) | ||
| 305 | - asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string); | ||
| 306 | - else if (arm_select[1].string) | ||
| 307 | - asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string); | ||
| 308 | + if (arm_selected_arch) | ||
| 309 | + asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name); | ||
| 310 | else | ||
| 311 | - asm_fprintf (asm_out_file, "\t.cpu %s\n", | ||
| 312 | - all_cores[arm_default_cpu].name); | ||
| 313 | + asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name); | ||
| 314 | |||
| 315 | if (TARGET_SOFT_FLOAT) | ||
| 316 | { | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99413.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99413.patch deleted file mode 100644 index 3f873e7fe..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99413.patch +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | 2010-10-13 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-04-20 James E. Wilson <wilson@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | PR rtl-optimization/43520 | ||
| 9 | * ira-lives.c (ira_implicitly_set_insn_hard_regs): Exclude classes with | ||
| 10 | zero available registers. | ||
| 11 | |||
| 12 | === modified file 'gcc/ira-lives.c' | ||
| 13 | Index: gcc-4.5/gcc/ira-lives.c | ||
| 14 | =================================================================== | ||
| 15 | --- gcc-4.5.orig/gcc/ira-lives.c | ||
| 16 | +++ gcc-4.5/gcc/ira-lives.c | ||
| 17 | @@ -805,6 +805,9 @@ ira_implicitly_set_insn_hard_regs (HARD_ | ||
| 18 | ? GENERAL_REGS | ||
| 19 | : REG_CLASS_FROM_CONSTRAINT (c, p)); | ||
| 20 | if (cl != NO_REGS | ||
| 21 | + /* There is no register pressure problem if all of the | ||
| 22 | + regs in this class are fixed. */ | ||
| 23 | + && ira_available_class_regs[cl] != 0 | ||
| 24 | && (ira_available_class_regs[cl] | ||
| 25 | <= ira_reg_class_nregs[cl][mode])) | ||
| 26 | IOR_HARD_REG_SET (*set, reg_class_contents[cl]); | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99415.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99415.patch deleted file mode 100644 index 3622ac423..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99415.patch +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | 2010-10-13 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #8615 | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | |||
| 7 | 2010-10-12 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 8 | |||
| 9 | gcc/ | ||
| 10 | * config/arm/arm.h (ARM_EXPAND_ALIGNMENT): Rename from | ||
| 11 | DATA_ALIGNMENT and add COND parameter. Update comments above. | ||
| 12 | (DATA_ALIGNMENT): Use ARM_EXPAND_ALIGNMENT, with !optimize_size. | ||
| 13 | (LOCAL_ALIGNMENT): Use ARM_EXPAND_ALIGNMENT, with | ||
| 14 | !flag_conserve_stack. | ||
| 15 | |||
| 16 | === modified file 'gcc/config/arm/arm.h' | ||
| 17 | Index: gcc-4.5/gcc/config/arm/arm.h | ||
| 18 | =================================================================== | ||
| 19 | --- gcc-4.5.orig/gcc/config/arm/arm.h | ||
| 20 | +++ gcc-4.5/gcc/config/arm/arm.h | ||
| 21 | @@ -596,15 +596,21 @@ extern int low_irq_latency; | ||
| 22 | /* Align definitions of arrays, unions and structures so that | ||
| 23 | initializations and copies can be made more efficient. This is not | ||
| 24 | ABI-changing, so it only affects places where we can see the | ||
| 25 | - definition. */ | ||
| 26 | -#define DATA_ALIGNMENT(EXP, ALIGN) \ | ||
| 27 | - ((((ALIGN) < BITS_PER_WORD) \ | ||
| 28 | + definition. Increasing the alignment tends to introduce padding, | ||
| 29 | + so don't do this when optimizing for size/conserving stack space. */ | ||
| 30 | +#define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ | ||
| 31 | + (((COND) && ((ALIGN) < BITS_PER_WORD) \ | ||
| 32 | && (TREE_CODE (EXP) == ARRAY_TYPE \ | ||
| 33 | || TREE_CODE (EXP) == UNION_TYPE \ | ||
| 34 | || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | ||
| 35 | |||
| 36 | +/* Align global data. */ | ||
| 37 | +#define DATA_ALIGNMENT(EXP, ALIGN) \ | ||
| 38 | + ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) | ||
| 39 | + | ||
| 40 | /* Similarly, make sure that objects on the stack are sensibly aligned. */ | ||
| 41 | -#define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) | ||
| 42 | +#define LOCAL_ALIGNMENT(EXP, ALIGN) \ | ||
| 43 | + ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) | ||
| 44 | |||
| 45 | /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the | ||
| 46 | value set in previous versions of this toolchain was 8, which produces more | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99416.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99416.patch deleted file mode 100644 index 72a221b1d..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99416.patch +++ /dev/null | |||
| @@ -1,130 +0,0 @@ | |||
| 1 | 2010-10-15 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-10-15 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * ifcvt.c (find_active_insn_before): New function. | ||
| 9 | (find_active_insn_after): New function. | ||
| 10 | (cond_exec_process_if_block): Use new functions to replace | ||
| 11 | prev_active_insn() and next_active_insn(). | ||
| 12 | |||
| 13 | gcc/testsuite/ | ||
| 14 | * gcc.dg/20101010-1.c: New testcase. | ||
| 15 | |||
| 16 | === modified file 'gcc/ifcvt.c' | ||
| 17 | Index: gcc-4.5/gcc/ifcvt.c | ||
| 18 | =================================================================== | ||
| 19 | --- gcc-4.5.orig/gcc/ifcvt.c | ||
| 20 | +++ gcc-4.5/gcc/ifcvt.c | ||
| 21 | @@ -88,6 +88,8 @@ static int count_bb_insns (const_basic_b | ||
| 22 | static bool cheap_bb_rtx_cost_p (const_basic_block, int); | ||
| 23 | static rtx first_active_insn (basic_block); | ||
| 24 | static rtx last_active_insn (basic_block, int); | ||
| 25 | +static rtx find_active_insn_before (basic_block, rtx); | ||
| 26 | +static rtx find_active_insn_after (basic_block, rtx); | ||
| 27 | static basic_block block_fallthru (basic_block); | ||
| 28 | static int cond_exec_process_insns (ce_if_block_t *, rtx, rtx, rtx, rtx, int); | ||
| 29 | static rtx cond_exec_get_condition (rtx); | ||
| 30 | @@ -230,6 +232,48 @@ last_active_insn (basic_block bb, int sk | ||
| 31 | return insn; | ||
| 32 | } | ||
| 33 | |||
| 34 | +/* Return the active insn before INSN inside basic block CURR_BB. */ | ||
| 35 | + | ||
| 36 | +static rtx | ||
| 37 | +find_active_insn_before (basic_block curr_bb, rtx insn) | ||
| 38 | +{ | ||
| 39 | + if (!insn || insn == BB_HEAD (curr_bb)) | ||
| 40 | + return NULL_RTX; | ||
| 41 | + | ||
| 42 | + while ((insn = PREV_INSN (insn)) != NULL_RTX) | ||
| 43 | + { | ||
| 44 | + if (NONJUMP_INSN_P (insn) || JUMP_P (insn) || CALL_P (insn)) | ||
| 45 | + break; | ||
| 46 | + | ||
| 47 | + /* No other active insn all the way to the start of the basic block. */ | ||
| 48 | + if (insn == BB_HEAD (curr_bb)) | ||
| 49 | + return NULL_RTX; | ||
| 50 | + } | ||
| 51 | + | ||
| 52 | + return insn; | ||
| 53 | +} | ||
| 54 | + | ||
| 55 | +/* Return the active insn after INSN inside basic block CURR_BB. */ | ||
| 56 | + | ||
| 57 | +static rtx | ||
| 58 | +find_active_insn_after (basic_block curr_bb, rtx insn) | ||
| 59 | +{ | ||
| 60 | + if (!insn || insn == BB_END (curr_bb)) | ||
| 61 | + return NULL_RTX; | ||
| 62 | + | ||
| 63 | + while ((insn = NEXT_INSN (insn)) != NULL_RTX) | ||
| 64 | + { | ||
| 65 | + if (NONJUMP_INSN_P (insn) || JUMP_P (insn) || CALL_P (insn)) | ||
| 66 | + break; | ||
| 67 | + | ||
| 68 | + /* No other active insn all the way to the end of the basic block. */ | ||
| 69 | + if (insn == BB_END (curr_bb)) | ||
| 70 | + return NULL_RTX; | ||
| 71 | + } | ||
| 72 | + | ||
| 73 | + return insn; | ||
| 74 | +} | ||
| 75 | + | ||
| 76 | /* Return the basic block reached by falling though the basic block BB. */ | ||
| 77 | |||
| 78 | static basic_block | ||
| 79 | @@ -448,9 +492,9 @@ cond_exec_process_if_block (ce_if_block_ | ||
| 80 | if (n_matching > 0) | ||
| 81 | { | ||
| 82 | if (then_end) | ||
| 83 | - then_end = prev_active_insn (then_first_tail); | ||
| 84 | + then_end = find_active_insn_before (then_bb, then_first_tail); | ||
| 85 | if (else_end) | ||
| 86 | - else_end = prev_active_insn (else_first_tail); | ||
| 87 | + else_end = find_active_insn_before (else_bb, else_first_tail); | ||
| 88 | n_insns -= 2 * n_matching; | ||
| 89 | } | ||
| 90 | |||
| 91 | @@ -488,9 +532,9 @@ cond_exec_process_if_block (ce_if_block_ | ||
| 92 | if (n_matching > 0) | ||
| 93 | { | ||
| 94 | if (then_start) | ||
| 95 | - then_start = next_active_insn (then_last_head); | ||
| 96 | + then_start = find_active_insn_after (then_bb, then_last_head); | ||
| 97 | if (else_start) | ||
| 98 | - else_start = next_active_insn (else_last_head); | ||
| 99 | + else_start = find_active_insn_after (else_bb, else_last_head); | ||
| 100 | n_insns -= 2 * n_matching; | ||
| 101 | } | ||
| 102 | } | ||
| 103 | @@ -646,7 +690,7 @@ cond_exec_process_if_block (ce_if_block_ | ||
| 104 | { | ||
| 105 | rtx from = then_first_tail; | ||
| 106 | if (!INSN_P (from)) | ||
| 107 | - from = next_active_insn (from); | ||
| 108 | + from = find_active_insn_after (then_bb, from); | ||
| 109 | delete_insn_chain (from, BB_END (then_bb), false); | ||
| 110 | } | ||
| 111 | if (else_last_head) | ||
| 112 | Index: gcc-4.5/gcc/testsuite/gcc.dg/20101010-1.c | ||
| 113 | =================================================================== | ||
| 114 | --- /dev/null | ||
| 115 | +++ gcc-4.5/gcc/testsuite/gcc.dg/20101010-1.c | ||
| 116 | @@ -0,0 +1,14 @@ | ||
| 117 | +/* { dg-do compile } */ | ||
| 118 | +/* { dg-options "-O2 -fno-crossjumping" } */ | ||
| 119 | + | ||
| 120 | +int foo (void) | ||
| 121 | +{ | ||
| 122 | + int len; | ||
| 123 | + if (bar1 (&len)) | ||
| 124 | + { | ||
| 125 | + char devpath [len]; | ||
| 126 | + if (bar2 (devpath) == len) | ||
| 127 | + return len; | ||
| 128 | + } | ||
| 129 | + return -1; | ||
| 130 | +} | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99417.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99417.patch deleted file mode 100644 index 2ad7e6968..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99417.patch +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | 2010-10-15 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | gcc/testsuite/ | ||
| 6 | 2010-10-15 Jie Zhang <jie@codesourcery.com> | ||
| 7 | |||
| 8 | * lib/lto.exp (lto-link-and-maybe-run): Use the default linker | ||
| 9 | script when relocatable linking. | ||
| 10 | |||
| 11 | === modified file 'gcc/testsuite/lib/lto.exp' | ||
| 12 | Index: gcc-4.5/gcc/testsuite/lib/lto.exp | ||
| 13 | =================================================================== | ||
| 14 | --- gcc-4.5.orig/gcc/testsuite/lib/lto.exp | ||
| 15 | +++ gcc-4.5/gcc/testsuite/lib/lto.exp | ||
| 16 | @@ -156,6 +156,7 @@ proc lto-link-and-maybe-run { testname o | ||
| 17 | global testcase | ||
| 18 | global tool | ||
| 19 | global compile_type | ||
| 20 | + global board_info | ||
| 21 | |||
| 22 | # Check that all of the objects were built successfully. | ||
| 23 | foreach obj [split $objlist] { | ||
| 24 | @@ -170,10 +171,29 @@ proc lto-link-and-maybe-run { testname o | ||
| 25 | set options "" | ||
| 26 | lappend options "additional_flags=$optall $optfile" | ||
| 27 | |||
| 28 | + set target_board [target_info name] | ||
| 29 | + set relocatable 0 | ||
| 30 | + | ||
| 31 | + # Some LTO tests do relocatable linking. Some target boards set | ||
| 32 | + # a linker script which can't be used for relocatable linking. | ||
| 33 | + # Use the default linker script instead. | ||
| 34 | + if { [lsearch -exact [split "$optall $optfile"] "-r"] >= 0 } { | ||
| 35 | + set relocatable 1 | ||
| 36 | + } | ||
| 37 | + | ||
| 38 | + if { $relocatable } { | ||
| 39 | + set saved_ldscript [board_info $target_board ldscript] | ||
| 40 | + set board_info($target_board,ldscript) "" | ||
| 41 | + } | ||
| 42 | + | ||
| 43 | # Link the objects into an executable. | ||
| 44 | set comp_output [${tool}_target_compile "$objlist" $dest executable \ | ||
| 45 | "$options"] | ||
| 46 | |||
| 47 | + if { $relocatable } { | ||
| 48 | + set board_info($target_board,ldscript) $saved_ldscript | ||
| 49 | + } | ||
| 50 | + | ||
| 51 | # Prune unimportant visibility warnings before checking output. | ||
| 52 | set comp_output [lto_prune_warns $comp_output] | ||
| 53 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99418.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99418.patch deleted file mode 100644 index 3ea7956f0..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99418.patch +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | 2010-10-20 Yao Qi <yao@codesourcery.com> | ||
| 2 | |||
| 3 | Merge from Sourcery G++ to fix LP:660021 | ||
| 4 | 2010-10-18 Paul Brook <paul@codesourcery.com> | ||
| 5 | |||
| 6 | * tree-vect-stmts.c (supportable_widening_operation): Check if wide | ||
| 7 | vector type exists. | ||
| 8 | |||
| 9 | === modified file 'gcc/tree-vect-stmts.c' | ||
| 10 | Index: gcc-4.5/gcc/tree-vect-stmts.c | ||
| 11 | =================================================================== | ||
| 12 | --- gcc-4.5.orig/gcc/tree-vect-stmts.c | ||
| 13 | +++ gcc-4.5/gcc/tree-vect-stmts.c | ||
| 14 | @@ -4867,6 +4867,11 @@ supportable_widening_operation (enum tre | ||
| 15 | tree wide_vectype = get_vectype_for_scalar_type (type); | ||
| 16 | enum tree_code c1, c2; | ||
| 17 | |||
| 18 | + /* Check we have a valid vector type for the result. */ | ||
| 19 | + if (!wide_vectype) | ||
| 20 | + return false; | ||
| 21 | + | ||
| 22 | + | ||
| 23 | /* The result of a vectorized widening operation usually requires two vectors | ||
| 24 | (because the widened results do not fit int one vector). The generated | ||
| 25 | vector results would normally be expected to be generated in the same | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99419.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99419.patch deleted file mode 100644 index cb434082b..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99419.patch +++ /dev/null | |||
| @@ -1,734 +0,0 @@ | |||
| 1 | 2010-10-22 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-10-18 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 6 | |||
| 7 | gcc/testsuite/ | ||
| 8 | * gcc.target/arm/synchronize.c: Permit dmb or mcr in assembler scan. | ||
| 9 | |||
| 10 | 2010-10-14 Julian Brown <julian@codesourcery.com> | ||
| 11 | |||
| 12 | Backport from mainline: | ||
| 13 | |||
| 14 | 2010-08-18 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 15 | |||
| 16 | gcc/ | ||
| 17 | * config/arm/arm-protos.h (arm_expand_sync): New. | ||
| 18 | (arm_output_memory_barrier, arm_output_sync_insn): New. | ||
| 19 | (arm_sync_loop_insns): New. | ||
| 20 | * config/arm/arm.c (FL_ARCH7): New. | ||
| 21 | (FL_FOR_ARCH7): Include FL_ARCH7. | ||
| 22 | (arm_arch7): New. | ||
| 23 | (arm_print_operand): Support %C markup. | ||
| 24 | (arm_legitimize_sync_memory): New. | ||
| 25 | (arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New. | ||
| 26 | (arm_process_output_memory_barrier, arm_output_memory_barrier): New. | ||
| 27 | (arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New. | ||
| 28 | (arm_output_op2, arm_output_op3, arm_output_sync_loop): New. | ||
| 29 | (arm_get_sync_operand, FETCH_SYNC_OPERAND): New. | ||
| 30 | (arm_process_output_sync_insn, arm_output_sync_insn): New. | ||
| 31 | (arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New. | ||
| 32 | * config/arm/arm.h (struct arm_sync_generator): New. | ||
| 33 | (TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New. | ||
| 34 | (TARGET_HAVE_MEMORY_BARRIER): New. | ||
| 35 | (TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New. | ||
| 36 | * config/arm/arm.md: Include sync.md. | ||
| 37 | (UNSPEC_MEMORY_BARRIER): New. | ||
| 38 | (VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New. | ||
| 39 | (VUNSPEC_SYNC_OP):New. | ||
| 40 | (VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New. | ||
| 41 | (sync_result, sync_memory, sync_required_value): New attributes. | ||
| 42 | (sync_new_value, sync_t1, sync_t2): Likewise. | ||
| 43 | (sync_release_barrier, sync_op): Likewise. | ||
| 44 | (length): Add logic to length attribute defintion to call | ||
| 45 | arm_sync_loop_insns when appropriate. | ||
| 46 | * config/arm/sync.md: New file. | ||
| 47 | |||
| 48 | 2010-09-02 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 49 | |||
| 50 | gcc/ | ||
| 51 | * config/arm/predicates.md (arm_sync_memory_operand): New. | ||
| 52 | * config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate | ||
| 53 | to arm_sync_memory_operand and constraint to Q. | ||
| 54 | (arm_sync_compare_and_swap<mode>): Likewise. | ||
| 55 | (arm_sync_compare_and_swap<mode>): Likewise. | ||
| 56 | (arm_sync_lock_test_and_setsi): Likewise. | ||
| 57 | (arm_sync_lock_test_and_set<mode>): Likewise. | ||
| 58 | (arm_sync_new_<sync_optab>si): Likewise. | ||
| 59 | (arm_sync_new_nandsi): Likewise. | ||
| 60 | (arm_sync_new_<sync_optab><mode>): Likewise. | ||
| 61 | (arm_sync_new_nand<mode>): Likewise. | ||
| 62 | (arm_sync_old_<sync_optab>si): Likewise. | ||
| 63 | (arm_sync_old_nandsi): Likewise. | ||
| 64 | (arm_sync_old_<sync_optab><mode>): Likewise. | ||
| 65 | (arm_sync_old_nand<mode>): Likewise. | ||
| 66 | |||
| 67 | 2010-09-13 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 68 | |||
| 69 | gcc/ | ||
| 70 | * config/arm/arm.md: (define_attr "conds"): Update comment. | ||
| 71 | * config/arm/sync.md (arm_sync_compare_and_swapsi): Change | ||
| 72 | conds attribute to clob. | ||
| 73 | (arm_sync_compare_and_swapsi): Likewise. | ||
| 74 | (arm_sync_compare_and_swap<mode>): Likewise. | ||
| 75 | (arm_sync_lock_test_and_setsi): Likewise. | ||
| 76 | (arm_sync_lock_test_and_set<mode>): Likewise. | ||
| 77 | (arm_sync_new_<sync_optab>si): Likewise. | ||
| 78 | (arm_sync_new_nandsi): Likewise. | ||
| 79 | (arm_sync_new_<sync_optab><mode>): Likewise. | ||
| 80 | (arm_sync_new_nand<mode>): Likewise. | ||
| 81 | (arm_sync_old_<sync_optab>si): Likewise. | ||
| 82 | (arm_sync_old_nandsi): Likewise. | ||
| 83 | (arm_sync_old_<sync_optab><mode>): Likewise. | ||
| 84 | (arm_sync_old_nand<mode>): Likewise. | ||
| 85 | |||
| 86 | 2010-09-13 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 87 | |||
| 88 | gcc/testsuite/ | ||
| 89 | * gcc.target/arm/sync-1.c: New. | ||
| 90 | |||
| 91 | |||
| 92 | Backport from FSF: | ||
| 93 | |||
| 94 | gcc/ | ||
| 95 | 2010-08-18 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 96 | * config/arm/arm-protos.h (arm_expand_sync): New. | ||
| 97 | (arm_output_memory_barrier, arm_output_sync_insn): New. | ||
| 98 | (arm_sync_loop_insns): New. | ||
| 99 | * config/arm/arm.c (FL_ARCH7): New. | ||
| 100 | (FL_FOR_ARCH7): Include FL_ARCH7. | ||
| 101 | (arm_arch7): New. | ||
| 102 | (arm_print_operand): Support %C markup. | ||
| 103 | (arm_legitimize_sync_memory): New. | ||
| 104 | (arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New. | ||
| 105 | (arm_process_output_memory_barrier, arm_output_memory_barrier): New. | ||
| 106 | (arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New. | ||
| 107 | (arm_output_op2, arm_output_op3, arm_output_sync_loop): New. | ||
| 108 | (arm_get_sync_operand, FETCH_SYNC_OPERAND): New. | ||
| 109 | (arm_process_output_sync_insn, arm_output_sync_insn): New. | ||
| 110 | (arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New. | ||
| 111 | * config/arm/arm.h (struct arm_sync_generator): New. | ||
| 112 | (TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New. | ||
| 113 | (TARGET_HAVE_MEMORY_BARRIER): New. | ||
| 114 | (TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New. | ||
| 115 | * config/arm/arm.md: Include sync.md. | ||
| 116 | (UNSPEC_MEMORY_BARRIER): New. | ||
| 117 | (VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New. | ||
| 118 | (VUNSPEC_SYNC_OP):New. | ||
| 119 | (VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New. | ||
| 120 | (sync_result, sync_memory, sync_required_value): New attributes. | ||
| 121 | (sync_new_value, sync_t1, sync_t2): Likewise. | ||
| 122 | (sync_release_barrier, sync_op): Likewise. | ||
| 123 | (length): Add logic to length attribute defintion to call | ||
| 124 | arm_sync_loop_insns when appropriate. | ||
| 125 | * config/arm/sync.md: New file. | ||
| 126 | |||
| 127 | gcc/ | ||
| 128 | 2010-09-02 Marcus Shawcroft <marcus.shawcroft@arm.com> | ||
| 129 | * config/arm/predicates.md (arm_sync_memory_operand): New. | ||
| 130 | * config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate | ||
| 131 | to arm_sync_memory_operand and constraint to Q. | ||
| 132 | (arm_sync_compare_and_swap<mode>): Likewise. | ||
| 133 | (arm_sync_compare_and_swap<mode>): Likewise. | ||
| 134 | (arm_sync_lock_test_and_setsi): Likewise. | ||
| 135 | (arm_sync_lock_test_and_set<mode>): Likewise. | ||
| 136 | (arm_sync_new_<sync_optab>si): Likewise. | ||
| 137 | (arm_sync_new_nandsi): Likewise. | ||
| 138 | (arm_sync_new_<sync_optab><mode>): Likewise. | ||
| 139 | (arm_sync_new_nand<mode>): Likewise. | ||
| 140 | (arm_sync_old_<sync_optab>si): Likewise. | ||
| 141 | (arm_sync_old_nandsi): Likewise. | ||
| 142 | (arm_sync_old_<sync_optab><mode>): Likewise. | ||
| 143 | (arm_sync_old_nand<mode>): Likewise. | ||
| 144 | |||
| 145 | === modified file 'gcc/config/arm/arm-protos.h' | ||
| 146 | Index: gcc-4.5/gcc/config/arm/arm-protos.h | ||
| 147 | =================================================================== | ||
| 148 | --- gcc-4.5.orig/gcc/config/arm/arm-protos.h | ||
| 149 | +++ gcc-4.5/gcc/config/arm/arm-protos.h | ||
| 150 | @@ -151,6 +151,11 @@ extern const char *vfp_output_fstmd (rtx | ||
| 151 | extern void arm_set_return_address (rtx, rtx); | ||
| 152 | extern int arm_eliminable_register (rtx); | ||
| 153 | extern const char *arm_output_shift(rtx *, int); | ||
| 154 | +extern void arm_expand_sync (enum machine_mode, struct arm_sync_generator *, | ||
| 155 | + rtx, rtx, rtx, rtx); | ||
| 156 | +extern const char *arm_output_memory_barrier (rtx *); | ||
| 157 | +extern const char *arm_output_sync_insn (rtx, rtx *); | ||
| 158 | +extern unsigned int arm_sync_loop_insns (rtx , rtx *); | ||
| 159 | |||
| 160 | extern bool arm_output_addr_const_extra (FILE *, rtx); | ||
| 161 | |||
| 162 | Index: gcc-4.5/gcc/config/arm/arm.c | ||
| 163 | =================================================================== | ||
| 164 | --- gcc-4.5.orig/gcc/config/arm/arm.c | ||
| 165 | +++ gcc-4.5/gcc/config/arm/arm.c | ||
| 166 | @@ -602,6 +602,7 @@ static int thumb_call_reg_needed; | ||
| 167 | #define FL_NEON (1 << 20) /* Neon instructions. */ | ||
| 168 | #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M | ||
| 169 | architecture. */ | ||
| 170 | +#define FL_ARCH7 (1 << 22) /* Architecture 7. */ | ||
| 171 | |||
| 172 | #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ | ||
| 173 | |||
| 174 | @@ -626,7 +627,7 @@ static int thumb_call_reg_needed; | ||
| 175 | #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K | ||
| 176 | #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) | ||
| 177 | #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) | ||
| 178 | -#define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM) | ||
| 179 | +#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) | ||
| 180 | #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) | ||
| 181 | #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) | ||
| 182 | #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) | ||
| 183 | @@ -664,6 +665,9 @@ int arm_arch6 = 0; | ||
| 184 | /* Nonzero if this chip supports the ARM 6K extensions. */ | ||
| 185 | int arm_arch6k = 0; | ||
| 186 | |||
| 187 | +/* Nonzero if this chip supports the ARM 7 extensions. */ | ||
| 188 | +int arm_arch7 = 0; | ||
| 189 | + | ||
| 190 | /* Nonzero if instructions not present in the 'M' profile can be used. */ | ||
| 191 | int arm_arch_notm = 0; | ||
| 192 | |||
| 193 | @@ -1602,6 +1606,7 @@ arm_override_options (void) | ||
| 194 | arm_arch6 = (insn_flags & FL_ARCH6) != 0; | ||
| 195 | arm_arch6k = (insn_flags & FL_ARCH6K) != 0; | ||
| 196 | arm_arch_notm = (insn_flags & FL_NOTM) != 0; | ||
| 197 | + arm_arch7 = (insn_flags & FL_ARCH7) != 0; | ||
| 198 | arm_arch7em = (insn_flags & FL_ARCH7EM) != 0; | ||
| 199 | arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; | ||
| 200 | arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; | ||
| 201 | @@ -16562,6 +16567,17 @@ arm_print_operand (FILE *stream, rtx x, | ||
| 202 | } | ||
| 203 | return; | ||
| 204 | |||
| 205 | + case 'C': | ||
| 206 | + { | ||
| 207 | + rtx addr; | ||
| 208 | + | ||
| 209 | + gcc_assert (GET_CODE (x) == MEM); | ||
| 210 | + addr = XEXP (x, 0); | ||
| 211 | + gcc_assert (GET_CODE (addr) == REG); | ||
| 212 | + asm_fprintf (stream, "[%r]", REGNO (addr)); | ||
| 213 | + } | ||
| 214 | + return; | ||
| 215 | + | ||
| 216 | /* Translate an S register number into a D register number and element index. */ | ||
| 217 | case 'y': | ||
| 218 | { | ||
| 219 | @@ -22793,4 +22809,372 @@ arm_builtin_support_vector_misalignment | ||
| 220 | is_packed); | ||
| 221 | } | ||
| 222 | |||
| 223 | +/* Legitimize a memory reference for sync primitive implemented using | ||
| 224 | + ldrex / strex. We currently force the form of the reference to be | ||
| 225 | + indirect without offset. We do not yet support the indirect offset | ||
| 226 | + addressing supported by some ARM targets for these | ||
| 227 | + instructions. */ | ||
| 228 | +static rtx | ||
| 229 | +arm_legitimize_sync_memory (rtx memory) | ||
| 230 | +{ | ||
| 231 | + rtx addr = force_reg (Pmode, XEXP (memory, 0)); | ||
| 232 | + rtx legitimate_memory = gen_rtx_MEM (GET_MODE (memory), addr); | ||
| 233 | + | ||
| 234 | + set_mem_alias_set (legitimate_memory, ALIAS_SET_MEMORY_BARRIER); | ||
| 235 | + MEM_VOLATILE_P (legitimate_memory) = MEM_VOLATILE_P (memory); | ||
| 236 | + return legitimate_memory; | ||
| 237 | +} | ||
| 238 | + | ||
| 239 | +/* An instruction emitter. */ | ||
| 240 | +typedef void (* emit_f) (int label, const char *, rtx *); | ||
| 241 | + | ||
| 242 | +/* An instruction emitter that emits via the conventional | ||
| 243 | + output_asm_insn. */ | ||
| 244 | +static void | ||
| 245 | +arm_emit (int label ATTRIBUTE_UNUSED, const char *pattern, rtx *operands) | ||
| 246 | +{ | ||
| 247 | + output_asm_insn (pattern, operands); | ||
| 248 | +} | ||
| 249 | + | ||
| 250 | +/* Count the number of emitted synchronization instructions. */ | ||
| 251 | +static unsigned arm_insn_count; | ||
| 252 | + | ||
| 253 | +/* An emitter that counts emitted instructions but does not actually | ||
| 254 | + emit instruction into the the instruction stream. */ | ||
| 255 | +static void | ||
| 256 | +arm_count (int label, | ||
| 257 | + const char *pattern ATTRIBUTE_UNUSED, | ||
| 258 | + rtx *operands ATTRIBUTE_UNUSED) | ||
| 259 | +{ | ||
| 260 | + if (! label) | ||
| 261 | + ++ arm_insn_count; | ||
| 262 | +} | ||
| 263 | + | ||
| 264 | +/* Construct a pattern using conventional output formatting and feed | ||
| 265 | + it to output_asm_insn. Provides a mechanism to construct the | ||
| 266 | + output pattern on the fly. Note the hard limit on the pattern | ||
| 267 | + buffer size. */ | ||
| 268 | +static void | ||
| 269 | +arm_output_asm_insn (emit_f emit, int label, rtx *operands, | ||
| 270 | + const char *pattern, ...) | ||
| 271 | +{ | ||
| 272 | + va_list ap; | ||
| 273 | + char buffer[256]; | ||
| 274 | + | ||
| 275 | + va_start (ap, pattern); | ||
| 276 | + vsprintf (buffer, pattern, ap); | ||
| 277 | + va_end (ap); | ||
| 278 | + emit (label, buffer, operands); | ||
| 279 | +} | ||
| 280 | + | ||
| 281 | +/* Emit the memory barrier instruction, if any, provided by this | ||
| 282 | + target to a specified emitter. */ | ||
| 283 | +static void | ||
| 284 | +arm_process_output_memory_barrier (emit_f emit, rtx *operands) | ||
| 285 | +{ | ||
| 286 | + if (TARGET_HAVE_DMB) | ||
| 287 | + { | ||
| 288 | + /* Note we issue a system level barrier. We should consider | ||
| 289 | + issuing a inner shareabilty zone barrier here instead, ie. | ||
| 290 | + "DMB ISH". */ | ||
| 291 | + emit (0, "dmb\tsy", operands); | ||
| 292 | + return; | ||
| 293 | + } | ||
| 294 | + | ||
| 295 | + if (TARGET_HAVE_DMB_MCR) | ||
| 296 | + { | ||
| 297 | + emit (0, "mcr\tp15, 0, r0, c7, c10, 5", operands); | ||
| 298 | + return; | ||
| 299 | + } | ||
| 300 | + | ||
| 301 | + gcc_unreachable (); | ||
| 302 | +} | ||
| 303 | + | ||
| 304 | +/* Emit the memory barrier instruction, if any, provided by this | ||
| 305 | + target. */ | ||
| 306 | +const char * | ||
| 307 | +arm_output_memory_barrier (rtx *operands) | ||
| 308 | +{ | ||
| 309 | + arm_process_output_memory_barrier (arm_emit, operands); | ||
| 310 | + return ""; | ||
| 311 | +} | ||
| 312 | + | ||
| 313 | +/* Helper to figure out the instruction suffix required on ldrex/strex | ||
| 314 | + for operations on an object of the specified mode. */ | ||
| 315 | +static const char * | ||
| 316 | +arm_ldrex_suffix (enum machine_mode mode) | ||
| 317 | +{ | ||
| 318 | + switch (mode) | ||
| 319 | + { | ||
| 320 | + case QImode: return "b"; | ||
| 321 | + case HImode: return "h"; | ||
| 322 | + case SImode: return ""; | ||
| 323 | + case DImode: return "d"; | ||
| 324 | + default: | ||
| 325 | + gcc_unreachable (); | ||
| 326 | + } | ||
| 327 | + return ""; | ||
| 328 | +} | ||
| 329 | + | ||
| 330 | +/* Emit an ldrex{b,h,d, } instruction appropriate for the specified | ||
| 331 | + mode. */ | ||
| 332 | +static void | ||
| 333 | +arm_output_ldrex (emit_f emit, | ||
| 334 | + enum machine_mode mode, | ||
| 335 | + rtx target, | ||
| 336 | + rtx memory) | ||
| 337 | +{ | ||
| 338 | + const char *suffix = arm_ldrex_suffix (mode); | ||
| 339 | + rtx operands[2]; | ||
| 340 | + | ||
| 341 | + operands[0] = target; | ||
| 342 | + operands[1] = memory; | ||
| 343 | + arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix); | ||
| 344 | +} | ||
| 345 | + | ||
| 346 | +/* Emit a strex{b,h,d, } instruction appropriate for the specified | ||
| 347 | + mode. */ | ||
| 348 | +static void | ||
| 349 | +arm_output_strex (emit_f emit, | ||
| 350 | + enum machine_mode mode, | ||
| 351 | + const char *cc, | ||
| 352 | + rtx result, | ||
| 353 | + rtx value, | ||
| 354 | + rtx memory) | ||
| 355 | +{ | ||
| 356 | + const char *suffix = arm_ldrex_suffix (mode); | ||
| 357 | + rtx operands[3]; | ||
| 358 | + | ||
| 359 | + operands[0] = result; | ||
| 360 | + operands[1] = value; | ||
| 361 | + operands[2] = memory; | ||
| 362 | + arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2", suffix, | ||
| 363 | + cc); | ||
| 364 | +} | ||
| 365 | + | ||
| 366 | +/* Helper to emit a two operand instruction. */ | ||
| 367 | +static void | ||
| 368 | +arm_output_op2 (emit_f emit, const char *mnemonic, rtx d, rtx s) | ||
| 369 | +{ | ||
| 370 | + rtx operands[2]; | ||
| 371 | + | ||
| 372 | + operands[0] = d; | ||
| 373 | + operands[1] = s; | ||
| 374 | + arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1", mnemonic); | ||
| 375 | +} | ||
| 376 | + | ||
| 377 | +/* Helper to emit a three operand instruction. */ | ||
| 378 | +static void | ||
| 379 | +arm_output_op3 (emit_f emit, const char *mnemonic, rtx d, rtx a, rtx b) | ||
| 380 | +{ | ||
| 381 | + rtx operands[3]; | ||
| 382 | + | ||
| 383 | + operands[0] = d; | ||
| 384 | + operands[1] = a; | ||
| 385 | + operands[2] = b; | ||
| 386 | + arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1, %%2", mnemonic); | ||
| 387 | +} | ||
| 388 | + | ||
| 389 | +/* Emit a load store exclusive synchronization loop. | ||
| 390 | + | ||
| 391 | + do | ||
| 392 | + old_value = [mem] | ||
| 393 | + if old_value != required_value | ||
| 394 | + break; | ||
| 395 | + t1 = sync_op (old_value, new_value) | ||
| 396 | + [mem] = t1, t2 = [0|1] | ||
| 397 | + while ! t2 | ||
| 398 | + | ||
| 399 | + Note: | ||
| 400 | + t1 == t2 is not permitted | ||
| 401 | + t1 == old_value is permitted | ||
| 402 | + | ||
| 403 | + required_value: | ||
| 404 | + | ||
| 405 | + RTX register or const_int representing the required old_value for | ||
| 406 | + the modify to continue, if NULL no comparsion is performed. */ | ||
| 407 | +static void | ||
| 408 | +arm_output_sync_loop (emit_f emit, | ||
| 409 | + enum machine_mode mode, | ||
| 410 | + rtx old_value, | ||
| 411 | + rtx memory, | ||
| 412 | + rtx required_value, | ||
| 413 | + rtx new_value, | ||
| 414 | + rtx t1, | ||
| 415 | + rtx t2, | ||
| 416 | + enum attr_sync_op sync_op, | ||
| 417 | + int early_barrier_required) | ||
| 418 | +{ | ||
| 419 | + rtx operands[1]; | ||
| 420 | + | ||
| 421 | + gcc_assert (t1 != t2); | ||
| 422 | + | ||
| 423 | + if (early_barrier_required) | ||
| 424 | + arm_process_output_memory_barrier (emit, NULL); | ||
| 425 | + | ||
| 426 | + arm_output_asm_insn (emit, 1, operands, "%sLSYT%%=:", LOCAL_LABEL_PREFIX); | ||
| 427 | + | ||
| 428 | + arm_output_ldrex (emit, mode, old_value, memory); | ||
| 429 | + | ||
| 430 | + if (required_value) | ||
| 431 | + { | ||
| 432 | + rtx operands[2]; | ||
| 433 | + | ||
| 434 | + operands[0] = old_value; | ||
| 435 | + operands[1] = required_value; | ||
| 436 | + arm_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1"); | ||
| 437 | + arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX); | ||
| 438 | + } | ||
| 439 | + | ||
| 440 | + switch (sync_op) | ||
| 441 | + { | ||
| 442 | + case SYNC_OP_ADD: | ||
| 443 | + arm_output_op3 (emit, "add", t1, old_value, new_value); | ||
| 444 | + break; | ||
| 445 | + | ||
| 446 | + case SYNC_OP_SUB: | ||
| 447 | + arm_output_op3 (emit, "sub", t1, old_value, new_value); | ||
| 448 | + break; | ||
| 449 | + | ||
| 450 | + case SYNC_OP_IOR: | ||
| 451 | + arm_output_op3 (emit, "orr", t1, old_value, new_value); | ||
| 452 | + break; | ||
| 453 | + | ||
| 454 | + case SYNC_OP_XOR: | ||
| 455 | + arm_output_op3 (emit, "eor", t1, old_value, new_value); | ||
| 456 | + break; | ||
| 457 | + | ||
| 458 | + case SYNC_OP_AND: | ||
| 459 | + arm_output_op3 (emit,"and", t1, old_value, new_value); | ||
| 460 | + break; | ||
| 461 | + | ||
| 462 | + case SYNC_OP_NAND: | ||
| 463 | + arm_output_op3 (emit, "and", t1, old_value, new_value); | ||
| 464 | + arm_output_op2 (emit, "mvn", t1, t1); | ||
| 465 | + break; | ||
| 466 | + | ||
| 467 | + case SYNC_OP_NONE: | ||
| 468 | + t1 = new_value; | ||
| 469 | + break; | ||
| 470 | + } | ||
| 471 | + | ||
| 472 | + arm_output_strex (emit, mode, "", t2, t1, memory); | ||
| 473 | + operands[0] = t2; | ||
| 474 | + arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0"); | ||
| 475 | + arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", LOCAL_LABEL_PREFIX); | ||
| 476 | + | ||
| 477 | + arm_process_output_memory_barrier (emit, NULL); | ||
| 478 | + arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX); | ||
| 479 | +} | ||
| 480 | + | ||
| 481 | +static rtx | ||
| 482 | +arm_get_sync_operand (rtx *operands, int index, rtx default_value) | ||
| 483 | +{ | ||
| 484 | + if (index > 0) | ||
| 485 | + default_value = operands[index - 1]; | ||
| 486 | + | ||
| 487 | + return default_value; | ||
| 488 | +} | ||
| 489 | + | ||
| 490 | +#define FETCH_SYNC_OPERAND(NAME, DEFAULT) \ | ||
| 491 | + arm_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), DEFAULT); | ||
| 492 | + | ||
| 493 | +/* Extract the operands for a synchroniztion instruction from the | ||
| 494 | + instructions attributes and emit the instruction. */ | ||
| 495 | +static void | ||
| 496 | +arm_process_output_sync_insn (emit_f emit, rtx insn, rtx *operands) | ||
| 497 | +{ | ||
| 498 | + rtx result, memory, required_value, new_value, t1, t2; | ||
| 499 | + int early_barrier; | ||
| 500 | + enum machine_mode mode; | ||
| 501 | + enum attr_sync_op sync_op; | ||
| 502 | + | ||
| 503 | + result = FETCH_SYNC_OPERAND(result, 0); | ||
| 504 | + memory = FETCH_SYNC_OPERAND(memory, 0); | ||
| 505 | + required_value = FETCH_SYNC_OPERAND(required_value, 0); | ||
| 506 | + new_value = FETCH_SYNC_OPERAND(new_value, 0); | ||
| 507 | + t1 = FETCH_SYNC_OPERAND(t1, 0); | ||
| 508 | + t2 = FETCH_SYNC_OPERAND(t2, 0); | ||
| 509 | + early_barrier = | ||
| 510 | + get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES; | ||
| 511 | + sync_op = get_attr_sync_op (insn); | ||
| 512 | + mode = GET_MODE (memory); | ||
| 513 | + | ||
| 514 | + arm_output_sync_loop (emit, mode, result, memory, required_value, | ||
| 515 | + new_value, t1, t2, sync_op, early_barrier); | ||
| 516 | +} | ||
| 517 | + | ||
| 518 | +/* Emit a synchronization instruction loop. */ | ||
| 519 | +const char * | ||
| 520 | +arm_output_sync_insn (rtx insn, rtx *operands) | ||
| 521 | +{ | ||
| 522 | + arm_process_output_sync_insn (arm_emit, insn, operands); | ||
| 523 | + return ""; | ||
| 524 | +} | ||
| 525 | + | ||
| 526 | +/* Count the number of machine instruction that will be emitted for a | ||
| 527 | + synchronization instruction. Note that the emitter used does not | ||
| 528 | + emit instructions, it just counts instructions being carefull not | ||
| 529 | + to count labels. */ | ||
| 530 | +unsigned int | ||
| 531 | +arm_sync_loop_insns (rtx insn, rtx *operands) | ||
| 532 | +{ | ||
| 533 | + arm_insn_count = 0; | ||
| 534 | + arm_process_output_sync_insn (arm_count, insn, operands); | ||
| 535 | + return arm_insn_count; | ||
| 536 | +} | ||
| 537 | + | ||
| 538 | +/* Helper to call a target sync instruction generator, dealing with | ||
| 539 | + the variation in operands required by the different generators. */ | ||
| 540 | +static rtx | ||
| 541 | +arm_call_generator (struct arm_sync_generator *generator, rtx old_value, | ||
| 542 | + rtx memory, rtx required_value, rtx new_value) | ||
| 543 | +{ | ||
| 544 | + switch (generator->op) | ||
| 545 | + { | ||
| 546 | + case arm_sync_generator_omn: | ||
| 547 | + gcc_assert (! required_value); | ||
| 548 | + return generator->u.omn (old_value, memory, new_value); | ||
| 549 | + | ||
| 550 | + case arm_sync_generator_omrn: | ||
| 551 | + gcc_assert (required_value); | ||
| 552 | + return generator->u.omrn (old_value, memory, required_value, new_value); | ||
| 553 | + } | ||
| 554 | + | ||
| 555 | + return NULL; | ||
| 556 | +} | ||
| 557 | + | ||
| 558 | +/* Expand a synchronization loop. The synchronization loop is expanded | ||
| 559 | + as an opaque block of instructions in order to ensure that we do | ||
| 560 | + not subsequently get extraneous memory accesses inserted within the | ||
| 561 | + critical region. The exclusive access property of ldrex/strex is | ||
| 562 | + only guaranteed in there are no intervening memory accesses. */ | ||
| 563 | +void | ||
| 564 | +arm_expand_sync (enum machine_mode mode, | ||
| 565 | + struct arm_sync_generator *generator, | ||
| 566 | + rtx target, rtx memory, rtx required_value, rtx new_value) | ||
| 567 | +{ | ||
| 568 | + if (target == NULL) | ||
| 569 | + target = gen_reg_rtx (mode); | ||
| 570 | + | ||
| 571 | + memory = arm_legitimize_sync_memory (memory); | ||
| 572 | + if (mode != SImode) | ||
| 573 | + { | ||
| 574 | + rtx load_temp = gen_reg_rtx (SImode); | ||
| 575 | + | ||
| 576 | + if (required_value) | ||
| 577 | + required_value = convert_modes (SImode, mode, required_value, true); | ||
| 578 | + | ||
| 579 | + new_value = convert_modes (SImode, mode, new_value, true); | ||
| 580 | + emit_insn (arm_call_generator (generator, load_temp, memory, | ||
| 581 | + required_value, new_value)); | ||
| 582 | + emit_move_insn (target, gen_lowpart (mode, load_temp)); | ||
| 583 | + } | ||
| 584 | + else | ||
| 585 | + { | ||
| 586 | + emit_insn (arm_call_generator (generator, target, memory, required_value, | ||
| 587 | + new_value)); | ||
| 588 | + } | ||
| 589 | +} | ||
| 590 | + | ||
| 591 | #include "gt-arm.h" | ||
| 592 | Index: gcc-4.5/gcc/config/arm/arm.h | ||
| 593 | =================================================================== | ||
| 594 | --- gcc-4.5.orig/gcc/config/arm/arm.h | ||
| 595 | +++ gcc-4.5/gcc/config/arm/arm.h | ||
| 596 | @@ -128,6 +128,24 @@ enum target_cpus | ||
| 597 | /* The processor for which instructions should be scheduled. */ | ||
| 598 | extern enum processor_type arm_tune; | ||
| 599 | |||
| 600 | +enum arm_sync_generator_tag | ||
| 601 | + { | ||
| 602 | + arm_sync_generator_omn, | ||
| 603 | + arm_sync_generator_omrn | ||
| 604 | + }; | ||
| 605 | + | ||
| 606 | +/* Wrapper to pass around a polymorphic pointer to a sync instruction | ||
| 607 | + generator and. */ | ||
| 608 | +struct arm_sync_generator | ||
| 609 | +{ | ||
| 610 | + enum arm_sync_generator_tag op; | ||
| 611 | + union | ||
| 612 | + { | ||
| 613 | + rtx (* omn) (rtx, rtx, rtx); | ||
| 614 | + rtx (* omrn) (rtx, rtx, rtx, rtx); | ||
| 615 | + } u; | ||
| 616 | +}; | ||
| 617 | + | ||
| 618 | typedef enum arm_cond_code | ||
| 619 | { | ||
| 620 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | ||
| 621 | @@ -272,6 +290,20 @@ extern void (*arm_lang_output_object_att | ||
| 622 | for Thumb-2. */ | ||
| 623 | #define TARGET_UNIFIED_ASM TARGET_THUMB2 | ||
| 624 | |||
| 625 | +/* Nonzero if this chip provides the DMB instruction. */ | ||
| 626 | +#define TARGET_HAVE_DMB (arm_arch7) | ||
| 627 | + | ||
| 628 | +/* Nonzero if this chip implements a memory barrier via CP15. */ | ||
| 629 | +#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB) | ||
| 630 | + | ||
| 631 | +/* Nonzero if this chip implements a memory barrier instruction. */ | ||
| 632 | +#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) | ||
| 633 | + | ||
| 634 | +/* Nonzero if this chip supports ldrex and strex */ | ||
| 635 | +#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) | ||
| 636 | + | ||
| 637 | +/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */ | ||
| 638 | +#define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7) | ||
| 639 | |||
| 640 | /* True iff the full BPABI is being used. If TARGET_BPABI is true, | ||
| 641 | then TARGET_AAPCS_BASED must be true -- but the converse does not | ||
| 642 | @@ -405,6 +437,12 @@ extern int arm_arch5e; | ||
| 643 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ | ||
| 644 | extern int arm_arch6; | ||
| 645 | |||
| 646 | +/* Nonzero if this chip supports the ARM Architecture 6k extensions. */ | ||
| 647 | +extern int arm_arch6k; | ||
| 648 | + | ||
| 649 | +/* Nonzero if this chip supports the ARM Architecture 7 extensions. */ | ||
| 650 | +extern int arm_arch7; | ||
| 651 | + | ||
| 652 | /* Nonzero if instructions not present in the 'M' profile can be used. */ | ||
| 653 | extern int arm_arch_notm; | ||
| 654 | |||
| 655 | Index: gcc-4.5/gcc/config/arm/arm.md | ||
| 656 | =================================================================== | ||
| 657 | --- gcc-4.5.orig/gcc/config/arm/arm.md | ||
| 658 | +++ gcc-4.5/gcc/config/arm/arm.md | ||
| 659 | @@ -103,6 +103,7 @@ | ||
| 660 | (UNSPEC_RBIT 26) ; rbit operation. | ||
| 661 | (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from | ||
| 662 | ; another symbolic address. | ||
| 663 | + (UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier. | ||
| 664 | ] | ||
| 665 | ) | ||
| 666 | |||
| 667 | @@ -139,6 +140,11 @@ | ||
| 668 | (VUNSPEC_ALIGN32 16) ; Used to force 32-byte alignment. | ||
| 669 | (VUNSPEC_EH_RETURN 20); Use to override the return address for exception | ||
| 670 | ; handling. | ||
| 671 | + (VUNSPEC_SYNC_COMPARE_AND_SWAP 21) ; Represent an atomic compare swap. | ||
| 672 | + (VUNSPEC_SYNC_LOCK 22) ; Represent a sync_lock_test_and_set. | ||
| 673 | + (VUNSPEC_SYNC_OP 23) ; Represent a sync_<op> | ||
| 674 | + (VUNSPEC_SYNC_NEW_OP 24) ; Represent a sync_new_<op> | ||
| 675 | + (VUNSPEC_SYNC_OLD_OP 25) ; Represent a sync_old_<op> | ||
| 676 | ] | ||
| 677 | ) | ||
| 678 | |||
| 679 | @@ -163,8 +169,21 @@ | ||
| 680 | (define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp" | ||
| 681 | (const (symbol_ref "arm_fpu_attr"))) | ||
| 682 | |||
| 683 | +(define_attr "sync_result" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 684 | +(define_attr "sync_memory" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 685 | +(define_attr "sync_required_value" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 686 | +(define_attr "sync_new_value" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 687 | +(define_attr "sync_t1" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 688 | +(define_attr "sync_t2" "none,0,1,2,3,4,5" (const_string "none")) | ||
| 689 | +(define_attr "sync_release_barrier" "yes,no" (const_string "yes")) | ||
| 690 | +(define_attr "sync_op" "none,add,sub,ior,xor,and,nand" | ||
| 691 | + (const_string "none")) | ||
| 692 | + | ||
| 693 | ; LENGTH of an instruction (in bytes) | ||
| 694 | -(define_attr "length" "" (const_int 4)) | ||
| 695 | +(define_attr "length" "" | ||
| 696 | + (cond [(not (eq_attr "sync_memory" "none")) | ||
| 697 | + (symbol_ref "arm_sync_loop_insns (insn, operands) * 4") | ||
| 698 | + ] (const_int 4))) | ||
| 699 | |||
| 700 | ; POOL_RANGE is how far away from a constant pool entry that this insn | ||
| 701 | ; can be placed. If the distance is zero, then this insn will never | ||
| 702 | @@ -11549,4 +11568,5 @@ | ||
| 703 | (include "thumb2.md") | ||
| 704 | ;; Neon patterns | ||
| 705 | (include "neon.md") | ||
| 706 | - | ||
| 707 | +;; Synchronization Primitives | ||
| 708 | +(include "sync.md") | ||
| 709 | Index: gcc-4.5/gcc/config/arm/predicates.md | ||
| 710 | =================================================================== | ||
| 711 | --- gcc-4.5.orig/gcc/config/arm/predicates.md | ||
| 712 | +++ gcc-4.5/gcc/config/arm/predicates.md | ||
| 713 | @@ -573,6 +573,11 @@ | ||
| 714 | (and (match_test "TARGET_32BIT") | ||
| 715 | (match_operand 0 "arm_di_operand")))) | ||
| 716 | |||
| 717 | +;; True if the operand is memory reference suitable for a ldrex/strex. | ||
| 718 | +(define_predicate "arm_sync_memory_operand" | ||
| 719 | + (and (match_operand 0 "memory_operand") | ||
| 720 | + (match_code "reg" "0"))) | ||
| 721 | + | ||
| 722 | ;; Predicates for parallel expanders based on mode. | ||
| 723 | (define_special_predicate "vect_par_constant_high" | ||
| 724 | (match_code "parallel") | ||
| 725 | Index: gcc-4.5/gcc/testsuite/gcc.target/arm/synchronize.c | ||
| 726 | =================================================================== | ||
| 727 | --- gcc-4.5.orig/gcc/testsuite/gcc.target/arm/synchronize.c | ||
| 728 | +++ gcc-4.5/gcc/testsuite/gcc.target/arm/synchronize.c | ||
| 729 | @@ -1,4 +1,4 @@ | ||
| 730 | -/* { dg-final { scan-assembler "__sync_synchronize" { target arm*-*-linux-*eabi } } } */ | ||
| 731 | +/* { dg-final { scan-assembler "__sync_synchronize|dmb|mcr" { target arm*-*-linux-*eabi } } } */ | ||
| 732 | |||
| 733 | void *foo (void) | ||
| 734 | { | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99420.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99420.patch deleted file mode 100644 index 4e63a8189..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99420.patch +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | 2010-10-18 Kazu Hirata <kazu@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #9720 | ||
| 4 | Backport from mainline: | ||
| 5 | gcc/ | ||
| 6 | 2010-10-07 Tejas Belagod <tejas.belagod@arm.com> | ||
| 7 | * config/arm/neon.md (neon_unpack<US>_<mode>): Add 'w' to | ||
| 8 | constraint, add register specifier in instruction template. | ||
| 9 | (neon_vec_pack_trunc_<mode>): Likewise. | ||
| 10 | (neon_vec_<US>mult_<mode>): Add register specifier to | ||
| 11 | instruction template. | ||
| 12 | |||
| 13 | === modified file 'gcc/config/arm/neon.md' | ||
| 14 | Index: gcc-4.5/gcc/config/arm/neon.md | ||
| 15 | =================================================================== | ||
| 16 | --- gcc-4.5.orig/gcc/config/arm/neon.md | ||
| 17 | +++ gcc-4.5/gcc/config/arm/neon.md | ||
| 18 | @@ -5682,9 +5682,9 @@ | ||
| 19 | ;; Vectorize for non-neon-quad case | ||
| 20 | (define_insn "neon_unpack<US>_<mode>" | ||
| 21 | [(set (match_operand:<V_widen> 0 "register_operand" "=w") | ||
| 22 | - (SE:<V_widen> (match_operand:VDI 1 "register_operand" "")))] | ||
| 23 | + (SE:<V_widen> (match_operand:VDI 1 "register_operand" "w")))] | ||
| 24 | "TARGET_NEON" | ||
| 25 | - "vmovl.<US><V_sz_elem> %q0, %1" | ||
| 26 | + "vmovl.<US><V_sz_elem> %q0, %P1" | ||
| 27 | [(set_attr "neon_type" "neon_shift_1")] | ||
| 28 | ) | ||
| 29 | |||
| 30 | @@ -5721,7 +5721,7 @@ | ||
| 31 | (SE:<V_widen> | ||
| 32 | (match_operand:VDI 2 "register_operand" "w"))))] | ||
| 33 | "TARGET_NEON" | ||
| 34 | - "vmull.<US><V_sz_elem> %q0, %1, %2" | ||
| 35 | + "vmull.<US><V_sz_elem> %q0, %P1, %P2" | ||
| 36 | [(set_attr "neon_type" "neon_shift_1")] | ||
| 37 | ) | ||
| 38 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99421.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99421.patch deleted file mode 100644 index 3a45ee502..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99421.patch +++ /dev/null | |||
| @@ -1,94 +0,0 @@ | |||
| 1 | 2010-10-20 Nathan Froyd <froydnj@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #9781 | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | 2010-10-20 Nathan Froyd <froydnj@codesourcery.com> | ||
| 9 | |||
| 10 | * ifcvt.c (noce_emit_cmove): If both of the values are SUBREGs, try | ||
| 11 | emitting the conditional move in the inner mode of the SUBREG. | ||
| 12 | |||
| 13 | |||
| 14 | === modified file 'gcc/ifcvt.c' | ||
| 15 | --- old/gcc/ifcvt.c 2010-10-15 10:01:07 +0000 | ||
| 16 | +++ new/gcc/ifcvt.c 2010-11-04 12:11:15 +0000 | ||
| 17 | @@ -1338,6 +1338,9 @@ | ||
| 18 | noce_emit_cmove (struct noce_if_info *if_info, rtx x, enum rtx_code code, | ||
| 19 | rtx cmp_a, rtx cmp_b, rtx vfalse, rtx vtrue) | ||
| 20 | { | ||
| 21 | + rtx target; | ||
| 22 | + int unsignedp; | ||
| 23 | + | ||
| 24 | /* If earliest == jump, try to build the cmove insn directly. | ||
| 25 | This is helpful when combine has created some complex condition | ||
| 26 | (like for alpha's cmovlbs) that we can't hope to regenerate | ||
| 27 | @@ -1372,10 +1375,62 @@ | ||
| 28 | return NULL_RTX; | ||
| 29 | |||
| 30 | #if HAVE_conditional_move | ||
| 31 | - return emit_conditional_move (x, code, cmp_a, cmp_b, VOIDmode, | ||
| 32 | - vtrue, vfalse, GET_MODE (x), | ||
| 33 | - (code == LTU || code == GEU | ||
| 34 | - || code == LEU || code == GTU)); | ||
| 35 | + unsignedp = (code == LTU || code == GEU | ||
| 36 | + || code == LEU || code == GTU); | ||
| 37 | + | ||
| 38 | + target = emit_conditional_move (x, code, cmp_a, cmp_b, VOIDmode, | ||
| 39 | + vtrue, vfalse, GET_MODE (x), | ||
| 40 | + unsignedp); | ||
| 41 | + if (target) | ||
| 42 | + return target; | ||
| 43 | + | ||
| 44 | + /* We might be faced with a situation like: | ||
| 45 | + | ||
| 46 | + x = (reg:M TARGET) | ||
| 47 | + vtrue = (subreg:M (reg:N VTRUE) BYTE) | ||
| 48 | + vfalse = (subreg:M (reg:N VFALSE) BYTE) | ||
| 49 | + | ||
| 50 | + We can't do a conditional move in mode M, but it's possible that we | ||
| 51 | + could do a conditional move in mode N instead and take a subreg of | ||
| 52 | + the result. | ||
| 53 | + | ||
| 54 | + If we can't create new pseudos, though, don't bother. */ | ||
| 55 | + if (reload_completed) | ||
| 56 | + return NULL_RTX; | ||
| 57 | + | ||
| 58 | + if (GET_CODE (vtrue) == SUBREG && GET_CODE (vfalse) == SUBREG) | ||
| 59 | + { | ||
| 60 | + rtx reg_vtrue = SUBREG_REG (vtrue); | ||
| 61 | + rtx reg_vfalse = SUBREG_REG (vfalse); | ||
| 62 | + unsigned int byte_vtrue = SUBREG_BYTE (vtrue); | ||
| 63 | + unsigned int byte_vfalse = SUBREG_BYTE (vfalse); | ||
| 64 | + rtx promoted_target; | ||
| 65 | + | ||
| 66 | + if (GET_MODE (reg_vtrue) != GET_MODE (reg_vfalse) | ||
| 67 | + || byte_vtrue != byte_vfalse | ||
| 68 | + || (SUBREG_PROMOTED_VAR_P (vtrue) | ||
| 69 | + != SUBREG_PROMOTED_VAR_P (vfalse)) | ||
| 70 | + || (SUBREG_PROMOTED_UNSIGNED_P (vtrue) | ||
| 71 | + != SUBREG_PROMOTED_UNSIGNED_P (vfalse))) | ||
| 72 | + return NULL_RTX; | ||
| 73 | + | ||
| 74 | + promoted_target = gen_reg_rtx (GET_MODE (reg_vtrue)); | ||
| 75 | + | ||
| 76 | + target = emit_conditional_move (promoted_target, code, cmp_a, cmp_b, | ||
| 77 | + VOIDmode, reg_vtrue, reg_vfalse, | ||
| 78 | + GET_MODE (reg_vtrue), unsignedp); | ||
| 79 | + /* Nope, couldn't do it in that mode either. */ | ||
| 80 | + if (!target) | ||
| 81 | + return NULL_RTX; | ||
| 82 | + | ||
| 83 | + target = gen_rtx_SUBREG (GET_MODE (vtrue), promoted_target, byte_vtrue); | ||
| 84 | + SUBREG_PROMOTED_VAR_P (target) = SUBREG_PROMOTED_VAR_P (vtrue); | ||
| 85 | + SUBREG_PROMOTED_UNSIGNED_SET (target, SUBREG_PROMOTED_UNSIGNED_P (vtrue)); | ||
| 86 | + emit_move_insn (x, target); | ||
| 87 | + return x; | ||
| 88 | + } | ||
| 89 | + else | ||
| 90 | + return NULL_RTX; | ||
| 91 | #else | ||
| 92 | /* We'll never get here, as noce_process_if_block doesn't call the | ||
| 93 | functions involved. Ifdef code, however, should be discouraged | ||
| 94 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99423.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99423.patch deleted file mode 100644 index 80dbe3f71..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99423.patch +++ /dev/null | |||
| @@ -1,114 +0,0 @@ | |||
| 1 | 2010-10-25 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #9812 | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | 2010-10-25 Jie Zhang <jie@codesourcery.com> | ||
| 9 | * combine.c (try_combine): If insns need to be kept around, | ||
| 10 | check that they can be copied in the merged instruction. | ||
| 11 | |||
| 12 | gcc/testsuite/ | ||
| 13 | 2010-10-25 Jie Zhang <jie@codesourcery.com> | ||
| 14 | * g++.dg/opt/combine.c: New test. | ||
| 15 | |||
| 16 | === modified file 'gcc/combine.c' | ||
| 17 | --- old/gcc/combine.c 2010-09-20 22:37:32 +0000 | ||
| 18 | +++ new/gcc/combine.c 2010-11-04 12:39:28 +0000 | ||
| 19 | @@ -2809,6 +2809,17 @@ | ||
| 20 | = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) | ||
| 21 | : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); | ||
| 22 | |||
| 23 | + /* We are about to copy insns for the case where they need to be kept | ||
| 24 | + around. Check that they can be copied in the merged instruction. */ | ||
| 25 | + | ||
| 26 | + if (targetm.cannot_copy_insn_p | ||
| 27 | + && ((added_sets_2 && targetm.cannot_copy_insn_p (i2)) | ||
| 28 | + || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1)))) | ||
| 29 | + { | ||
| 30 | + undo_all (); | ||
| 31 | + return 0; | ||
| 32 | + } | ||
| 33 | + | ||
| 34 | /* If the set in I2 needs to be kept around, we must make a copy of | ||
| 35 | PATTERN (I2), so that when we substitute I1SRC for I1DEST in | ||
| 36 | PATTERN (I2), we are only substituting for the original I1DEST, not into | ||
| 37 | |||
| 38 | === added file 'gcc/testsuite/g++.dg/opt/combine.C' | ||
| 39 | --- old/gcc/testsuite/g++.dg/opt/combine.C 1970-01-01 00:00:00 +0000 | ||
| 40 | +++ new/gcc/testsuite/g++.dg/opt/combine.C 2010-11-04 12:39:28 +0000 | ||
| 41 | @@ -0,0 +1,72 @@ | ||
| 42 | +// { dg-do assemble { target fpic } } | ||
| 43 | +// { dg-options "-O2 -fweb -fPIC -fvisibility=hidden" } | ||
| 44 | + | ||
| 45 | +class QBasicAtomicInt | ||
| 46 | +{ | ||
| 47 | +public: | ||
| 48 | + volatile int _q_value; | ||
| 49 | + inline operator int () const {return _q_value;} | ||
| 50 | +}; | ||
| 51 | +class QVariant; | ||
| 52 | +class QScriptContext; | ||
| 53 | +class QScriptEngine; | ||
| 54 | +class QScriptValue | ||
| 55 | +{ | ||
| 56 | +public: | ||
| 57 | + QVariant toVariant () const; | ||
| 58 | +}; | ||
| 59 | +class QScriptDebuggerBackendPrivate | ||
| 60 | +{ | ||
| 61 | + static QScriptValue trace (QScriptContext *context); | ||
| 62 | +}; | ||
| 63 | +template <typename T> struct QMetaTypeId { }; | ||
| 64 | +template <typename T> struct QMetaTypeId2 | ||
| 65 | +{ | ||
| 66 | + static inline int qt_metatype_id () | ||
| 67 | + { | ||
| 68 | + return QMetaTypeId<T>::qt_metatype_id () ; | ||
| 69 | + } | ||
| 70 | +}; | ||
| 71 | +template <typename T> inline int qMetaTypeId (T * = 0) | ||
| 72 | +{ | ||
| 73 | + return QMetaTypeId2<T>::qt_metatype_id () ; | ||
| 74 | +} | ||
| 75 | +class QVariant { }; | ||
| 76 | +template<typename T> inline T qvariant_cast (const QVariant &v) | ||
| 77 | +{ | ||
| 78 | + const int vid = qMetaTypeId<T> ((0)) ; | ||
| 79 | +}; | ||
| 80 | +class QScriptContext | ||
| 81 | +{ | ||
| 82 | +public: | ||
| 83 | + QScriptValue callee () const; | ||
| 84 | +}; | ||
| 85 | +class QScriptEngine | ||
| 86 | +{ | ||
| 87 | +public: | ||
| 88 | + static bool convertV2 (const QScriptValue &value , int type , void *ptr) ; | ||
| 89 | +}; | ||
| 90 | +inline bool qscriptvalue_cast_helper (const QScriptValue &value , int type , void *ptr) | ||
| 91 | +{ | ||
| 92 | + return QScriptEngine::convertV2 (value, type, ptr) ; | ||
| 93 | +} | ||
| 94 | +template<typename T> T qscriptvalue_cast (const QScriptValue &value) | ||
| 95 | +{ | ||
| 96 | + T t; | ||
| 97 | + const int id = qMetaTypeId<T> () ; | ||
| 98 | + if ( qscriptvalue_cast_helper (value, id, &t)) | ||
| 99 | + return qvariant_cast<T> (value.toVariant ()) ; | ||
| 100 | +} | ||
| 101 | +template <> struct QMetaTypeId< QScriptDebuggerBackendPrivate* > | ||
| 102 | +{ | ||
| 103 | + static int qt_metatype_id () | ||
| 104 | + { | ||
| 105 | + static QBasicAtomicInt metatype_id = { (0) }; | ||
| 106 | + return metatype_id; | ||
| 107 | + } | ||
| 108 | +}; | ||
| 109 | +QScriptValue QScriptDebuggerBackendPrivate::trace (QScriptContext *context) | ||
| 110 | +{ | ||
| 111 | + QScriptValue data = context->callee () ; | ||
| 112 | + QScriptDebuggerBackendPrivate *self = qscriptvalue_cast<QScriptDebuggerBackendPrivate*> (data) ; | ||
| 113 | +} | ||
| 114 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99424.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99424.patch deleted file mode 100644 index ac3a1e224..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99424.patch +++ /dev/null | |||
| @@ -1,697 +0,0 @@ | |||
| 1 | Issue #1259 | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | 2010-10-22 Jie Zhang <jie@codesourcery.com> | ||
| 7 | |||
| 8 | * expr.c (emit_group_load_1): Update calls to extract_bit_field. | ||
| 9 | (copy_blkmode_from_reg): Likewise. | ||
| 10 | (read_complex_part): Likewise. | ||
| 11 | (expand_expr_real_1): Calculate packedp and pass it to | ||
| 12 | extract_bit_field. | ||
| 13 | * expr.h (extract_bit_field): Update declaration. | ||
| 14 | * calls.c (store_unaligned_arguments_into_pseudos): Update call | ||
| 15 | to extract_bit_field. | ||
| 16 | * expmed.c (extract_fixed_bit_field): Update calls to | ||
| 17 | extract_fixed_bit_field. | ||
| 18 | (store_split_bit_field): Likewise. | ||
| 19 | (extract_bit_field_1): Add new argument packedp. | ||
| 20 | (extract_bit_field): Add new argument packedp. | ||
| 21 | (extract_fixed_bit_field): Add new argument packedp and let | ||
| 22 | packed attribute override volatile. | ||
| 23 | * stmt.c (expand_return): Update call to extract_bit_field. | ||
| 24 | |||
| 25 | 2010-10-15 Jie Zhang <jie@codesourcery.com> | ||
| 26 | |||
| 27 | * doc/invoke.texi: Add -fstrict-volatile-bitfields to | ||
| 28 | Option Summary and Index. | ||
| 29 | |||
| 30 | 2010-07-13 DJ Delorie <dj@redhat.com> | ||
| 31 | |||
| 32 | * config/h8300/h8300.c (h8300_init_once): Default to | ||
| 33 | -fstrict_volatile_bitfields. | ||
| 34 | |||
| 35 | * config/sh/sh.c (sh_override_options): Default to | ||
| 36 | -fstrict_volatile_bitfields. | ||
| 37 | |||
| 38 | * config/rx/rx.c (rx_option_override): New. | ||
| 39 | |||
| 40 | * config/m32c/m32c.c (m32c_override_options): Default to | ||
| 41 | -fstrict_volatile_bitfields. | ||
| 42 | |||
| 43 | 2010-06-16 DJ Delorie <dj@redhat.com> | ||
| 44 | |||
| 45 | * common.opt (-fstrict-volatile-bitfields): new. | ||
| 46 | * doc/invoke.texi: Document it. | ||
| 47 | * fold-const.c (optimize_bit_field_compare): For volatile | ||
| 48 | bitfields, use the field's type to determine the mode, not the | ||
| 49 | field's size. | ||
| 50 | * expr.c (expand_assignment): Likewise. | ||
| 51 | (get_inner_reference): Likewise. | ||
| 52 | (expand_expr_real_1): Likewise. | ||
| 53 | * expmed.c (store_fixed_bit_field): Likewise. | ||
| 54 | (extract_bit_field_1): Likewise. | ||
| 55 | (extract_fixed_bit_field): Likewise. | ||
| 56 | |||
| 57 | gcc/testsuite/ | ||
| 58 | 2010-08-19 Uros Bizjak <ubizjak@gmail.com> | ||
| 59 | |||
| 60 | PR testsuite/45324 | ||
| 61 | * gcc.target/i386/volatile-bitfields-1.c: Also scan movb. | ||
| 62 | |||
| 63 | 2010-06-16 DJ Delorie <dj@redhat.com> | ||
| 64 | |||
| 65 | * gcc.target/i386/volatile-bitfields-1.c: New. | ||
| 66 | * gcc.target/i386/volatile-bitfields-2.c: New. | ||
| 67 | |||
| 68 | === modified file 'gcc/calls.c' | ||
| 69 | Index: gcc-4_5-branch/gcc/calls.c | ||
| 70 | =================================================================== | ||
| 71 | --- gcc-4_5-branch.orig/gcc/calls.c 2012-03-06 13:05:56.524590011 -0800 | ||
| 72 | +++ gcc-4_5-branch/gcc/calls.c 2012-03-06 13:36:10.276677792 -0800 | ||
| 73 | @@ -878,7 +878,7 @@ | ||
| 74 | int bitsize = MIN (bytes * BITS_PER_UNIT, BITS_PER_WORD); | ||
| 75 | |||
| 76 | args[i].aligned_regs[j] = reg; | ||
| 77 | - word = extract_bit_field (word, bitsize, 0, 1, NULL_RTX, | ||
| 78 | + word = extract_bit_field (word, bitsize, 0, 1, false, NULL_RTX, | ||
| 79 | word_mode, word_mode); | ||
| 80 | |||
| 81 | /* There is no need to restrict this code to loading items | ||
| 82 | Index: gcc-4_5-branch/gcc/common.opt | ||
| 83 | =================================================================== | ||
| 84 | --- gcc-4_5-branch.orig/gcc/common.opt 2012-03-06 13:05:48.400589618 -0800 | ||
| 85 | +++ gcc-4_5-branch/gcc/common.opt 2012-03-06 13:36:35.608679018 -0800 | ||
| 86 | @@ -613,6 +613,10 @@ | ||
| 87 | Common Report Var(flag_loop_block) Optimization | ||
| 88 | Enable Loop Blocking transformation | ||
| 89 | |||
| 90 | +fstrict-volatile-bitfields | ||
| 91 | +Common Report Var(flag_strict_volatile_bitfields) Init(-1) | ||
| 92 | +Force bitfield accesses to match their type width | ||
| 93 | + | ||
| 94 | fguess-branch-probability | ||
| 95 | Common Report Var(flag_guess_branch_prob) Optimization | ||
| 96 | Enable guessing of branch probabilities | ||
| 97 | Index: gcc-4_5-branch/gcc/config/h8300/h8300.c | ||
| 98 | =================================================================== | ||
| 99 | --- gcc-4_5-branch.orig/gcc/config/h8300/h8300.c 2012-03-06 11:53:30.000000000 -0800 | ||
| 100 | +++ gcc-4_5-branch/gcc/config/h8300/h8300.c 2012-03-06 13:36:35.528679014 -0800 | ||
| 101 | @@ -403,6 +403,10 @@ | ||
| 102 | restore er6 though, so bump up the cost. */ | ||
| 103 | h8300_move_ratio = 6; | ||
| 104 | } | ||
| 105 | + | ||
| 106 | + /* This target defaults to strict volatile bitfields. */ | ||
| 107 | + if (flag_strict_volatile_bitfields < 0) | ||
| 108 | + flag_strict_volatile_bitfields = 1; | ||
| 109 | } | ||
| 110 | |||
| 111 | /* Implement REG_CLASS_FROM_LETTER. | ||
| 112 | Index: gcc-4_5-branch/gcc/config/m32c/m32c.c | ||
| 113 | =================================================================== | ||
| 114 | --- gcc-4_5-branch.orig/gcc/config/m32c/m32c.c 2012-03-06 11:53:16.000000000 -0800 | ||
| 115 | +++ gcc-4_5-branch/gcc/config/m32c/m32c.c 2012-03-06 13:36:35.488679012 -0800 | ||
| 116 | @@ -428,6 +428,10 @@ | ||
| 117 | |||
| 118 | if (TARGET_A24) | ||
| 119 | flag_ivopts = 0; | ||
| 120 | + | ||
| 121 | + /* This target defaults to strict volatile bitfields. */ | ||
| 122 | + if (flag_strict_volatile_bitfields < 0) | ||
| 123 | + flag_strict_volatile_bitfields = 1; | ||
| 124 | } | ||
| 125 | |||
| 126 | /* Defining data structures for per-function information */ | ||
| 127 | Index: gcc-4_5-branch/gcc/config/rx/rx.c | ||
| 128 | =================================================================== | ||
| 129 | --- gcc-4_5-branch.orig/gcc/config/rx/rx.c 2012-03-06 11:53:17.000000000 -0800 | ||
| 130 | +++ gcc-4_5-branch/gcc/config/rx/rx.c 2012-03-06 13:36:35.508679013 -0800 | ||
| 131 | @@ -2417,6 +2417,14 @@ | ||
| 132 | return ! TYPE_PACKED (record_type); | ||
| 133 | } | ||
| 134 | |||
| 135 | +static void | ||
| 136 | +rx_option_override (void) | ||
| 137 | +{ | ||
| 138 | + /* This target defaults to strict volatile bitfields. */ | ||
| 139 | + if (flag_strict_volatile_bitfields < 0) | ||
| 140 | + flag_strict_volatile_bitfields = 1; | ||
| 141 | +} | ||
| 142 | + | ||
| 143 | |||
| 144 | /* Returns true if X a legitimate constant for an immediate | ||
| 145 | operand on the RX. X is already known to satisfy CONSTANT_P. */ | ||
| 146 | @@ -2794,6 +2802,9 @@ | ||
| 147 | #undef TARGET_PROMOTE_FUNCTION_MODE | ||
| 148 | #define TARGET_PROMOTE_FUNCTION_MODE rx_promote_function_mode | ||
| 149 | |||
| 150 | +#undef TARGET_OPTION_OVERRIDE | ||
| 151 | +#define TARGET_OPTION_OVERRIDE rx_option_override | ||
| 152 | + | ||
| 153 | struct gcc_target targetm = TARGET_INITIALIZER; | ||
| 154 | |||
| 155 | /* #include "gt-rx.h" */ | ||
| 156 | Index: gcc-4_5-branch/gcc/config/sh/sh.c | ||
| 157 | =================================================================== | ||
| 158 | --- gcc-4_5-branch.orig/gcc/config/sh/sh.c 2012-03-06 11:53:20.000000000 -0800 | ||
| 159 | +++ gcc-4_5-branch/gcc/config/sh/sh.c 2012-03-06 13:36:35.516679013 -0800 | ||
| 160 | @@ -950,6 +950,10 @@ | ||
| 161 | |||
| 162 | if (sh_fixed_range_str) | ||
| 163 | sh_fix_range (sh_fixed_range_str); | ||
| 164 | + | ||
| 165 | + /* This target defaults to strict volatile bitfields. */ | ||
| 166 | + if (flag_strict_volatile_bitfields < 0) | ||
| 167 | + flag_strict_volatile_bitfields = 1; | ||
| 168 | } | ||
| 169 | |||
| 170 | /* Print the operand address in x to the stream. */ | ||
| 171 | Index: gcc-4_5-branch/gcc/doc/invoke.texi | ||
| 172 | =================================================================== | ||
| 173 | --- gcc-4_5-branch.orig/gcc/doc/invoke.texi 2012-03-06 13:05:56.988590034 -0800 | ||
| 174 | +++ gcc-4_5-branch/gcc/doc/invoke.texi 2012-03-06 13:36:36.048679039 -0800 | ||
| 175 | @@ -922,7 +922,7 @@ | ||
| 176 | -fargument-noalias-global -fargument-noalias-anything @gol | ||
| 177 | -fleading-underscore -ftls-model=@var{model} @gol | ||
| 178 | -ftrapv -fwrapv -fbounds-check @gol | ||
| 179 | --fvisibility} | ||
| 180 | +-fvisibility -fstrict-volatile-bitfields} | ||
| 181 | @end table | ||
| 182 | |||
| 183 | @menu | ||
| 184 | @@ -17629,6 +17629,33 @@ | ||
| 185 | An overview of these techniques, their benefits and how to use them | ||
| 186 | is at @w{@uref{http://gcc.gnu.org/wiki/Visibility}}. | ||
| 187 | |||
| 188 | +@item -fstrict-volatile-bitfields | ||
| 189 | +@opindex fstrict-volatile-bitfields | ||
| 190 | +This option should be used if accesses to volatile bitfields (or other | ||
| 191 | +structure fields, although the compiler usually honors those types | ||
| 192 | +anyway) should use a single access in a mode of the same size as the | ||
| 193 | +container's type, aligned to a natural alignment if possible. For | ||
| 194 | +example, targets with memory-mapped peripheral registers might require | ||
| 195 | +all such accesses to be 16 bits wide; with this flag the user could | ||
| 196 | +declare all peripheral bitfields as ``unsigned short'' (assuming short | ||
| 197 | +is 16 bits on these targets) to force GCC to use 16 bit accesses | ||
| 198 | +instead of, perhaps, a more efficient 32 bit access. | ||
| 199 | + | ||
| 200 | +If this option is disabled, the compiler will use the most efficient | ||
| 201 | +instruction. In the previous example, that might be a 32-bit load | ||
| 202 | +instruction, even though that will access bytes that do not contain | ||
| 203 | +any portion of the bitfield, or memory-mapped registers unrelated to | ||
| 204 | +the one being updated. | ||
| 205 | + | ||
| 206 | +If the target requires strict alignment, and honoring the container | ||
| 207 | +type would require violating this alignment, a warning is issued. | ||
| 208 | +However, the access happens as the user requested, under the | ||
| 209 | +assumption that the user knows something about the target hardware | ||
| 210 | +that GCC is unaware of. | ||
| 211 | + | ||
| 212 | +The default value of this option is determined by the application binary | ||
| 213 | +interface for the target processor. | ||
| 214 | + | ||
| 215 | @end table | ||
| 216 | |||
| 217 | @c man end | ||
| 218 | Index: gcc-4_5-branch/gcc/expmed.c | ||
| 219 | =================================================================== | ||
| 220 | --- gcc-4_5-branch.orig/gcc/expmed.c 2012-03-06 13:05:56.876590028 -0800 | ||
| 221 | +++ gcc-4_5-branch/gcc/expmed.c 2012-03-06 13:36:35.104678993 -0800 | ||
| 222 | @@ -47,7 +47,7 @@ | ||
| 223 | static rtx extract_fixed_bit_field (enum machine_mode, rtx, | ||
| 224 | unsigned HOST_WIDE_INT, | ||
| 225 | unsigned HOST_WIDE_INT, | ||
| 226 | - unsigned HOST_WIDE_INT, rtx, int); | ||
| 227 | + unsigned HOST_WIDE_INT, rtx, int, bool); | ||
| 228 | static rtx mask_rtx (enum machine_mode, int, int, int); | ||
| 229 | static rtx lshift_value (enum machine_mode, rtx, int, int); | ||
| 230 | static rtx extract_split_bit_field (rtx, unsigned HOST_WIDE_INT, | ||
| 231 | @@ -904,8 +904,14 @@ | ||
| 232 | if (GET_MODE_BITSIZE (mode) == 0 | ||
| 233 | || GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (word_mode)) | ||
| 234 | mode = word_mode; | ||
| 235 | - mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, | ||
| 236 | - MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0)); | ||
| 237 | + | ||
| 238 | + if (MEM_VOLATILE_P (op0) | ||
| 239 | + && GET_MODE_BITSIZE (GET_MODE (op0)) > 0 | ||
| 240 | + && flag_strict_volatile_bitfields > 0) | ||
| 241 | + mode = GET_MODE (op0); | ||
| 242 | + else | ||
| 243 | + mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, | ||
| 244 | + MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0)); | ||
| 245 | |||
| 246 | if (mode == VOIDmode) | ||
| 247 | { | ||
| 248 | @@ -1099,7 +1105,7 @@ | ||
| 249 | endianness compensation) to fetch the piece we want. */ | ||
| 250 | part = extract_fixed_bit_field (word_mode, value, 0, thissize, | ||
| 251 | total_bits - bitsize + bitsdone, | ||
| 252 | - NULL_RTX, 1); | ||
| 253 | + NULL_RTX, 1, false); | ||
| 254 | } | ||
| 255 | else | ||
| 256 | { | ||
| 257 | @@ -1110,7 +1116,7 @@ | ||
| 258 | & (((HOST_WIDE_INT) 1 << thissize) - 1)); | ||
| 259 | else | ||
| 260 | part = extract_fixed_bit_field (word_mode, value, 0, thissize, | ||
| 261 | - bitsdone, NULL_RTX, 1); | ||
| 262 | + bitsdone, NULL_RTX, 1, false); | ||
| 263 | } | ||
| 264 | |||
| 265 | /* If OP0 is a register, then handle OFFSET here. | ||
| 266 | @@ -1176,7 +1182,8 @@ | ||
| 267 | |||
| 268 | static rtx | ||
| 269 | extract_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize, | ||
| 270 | - unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target, | ||
| 271 | + unsigned HOST_WIDE_INT bitnum, | ||
| 272 | + int unsignedp, bool packedp, rtx target, | ||
| 273 | enum machine_mode mode, enum machine_mode tmode, | ||
| 274 | bool fallback_p) | ||
| 275 | { | ||
| 276 | @@ -1378,6 +1385,14 @@ | ||
| 277 | ? mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) | ||
| 278 | : mode); | ||
| 279 | |||
| 280 | + /* If the bitfield is volatile, we need to make sure the access | ||
| 281 | + remains on a type-aligned boundary. */ | ||
| 282 | + if (GET_CODE (op0) == MEM | ||
| 283 | + && MEM_VOLATILE_P (op0) | ||
| 284 | + && GET_MODE_BITSIZE (GET_MODE (op0)) > 0 | ||
| 285 | + && flag_strict_volatile_bitfields > 0) | ||
| 286 | + goto no_subreg_mode_swap; | ||
| 287 | + | ||
| 288 | if (((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode) | ||
| 289 | && bitpos % BITS_PER_WORD == 0) | ||
| 290 | || (mode1 != BLKmode | ||
| 291 | @@ -1450,7 +1465,7 @@ | ||
| 292 | rtx result_part | ||
| 293 | = extract_bit_field (op0, MIN (BITS_PER_WORD, | ||
| 294 | bitsize - i * BITS_PER_WORD), | ||
| 295 | - bitnum + bit_offset, 1, target_part, mode, | ||
| 296 | + bitnum + bit_offset, 1, false, target_part, mode, | ||
| 297 | word_mode); | ||
| 298 | |||
| 299 | gcc_assert (target_part); | ||
| 300 | @@ -1649,7 +1664,7 @@ | ||
| 301 | xop0 = adjust_address (op0, bestmode, xoffset); | ||
| 302 | xop0 = force_reg (bestmode, xop0); | ||
| 303 | result = extract_bit_field_1 (xop0, bitsize, xbitpos, | ||
| 304 | - unsignedp, target, | ||
| 305 | + unsignedp, packedp, target, | ||
| 306 | mode, tmode, false); | ||
| 307 | if (result) | ||
| 308 | return result; | ||
| 309 | @@ -1663,7 +1678,7 @@ | ||
| 310 | return NULL; | ||
| 311 | |||
| 312 | target = extract_fixed_bit_field (int_mode, op0, offset, bitsize, | ||
| 313 | - bitpos, target, unsignedp); | ||
| 314 | + bitpos, target, unsignedp, packedp); | ||
| 315 | return convert_extracted_bit_field (target, mode, tmode, unsignedp); | ||
| 316 | } | ||
| 317 | |||
| 318 | @@ -1674,6 +1689,7 @@ | ||
| 319 | |||
| 320 | STR_RTX is the structure containing the byte (a REG or MEM). | ||
| 321 | UNSIGNEDP is nonzero if this is an unsigned bit field. | ||
| 322 | + PACKEDP is nonzero if the field has the packed attribute. | ||
| 323 | MODE is the natural mode of the field value once extracted. | ||
| 324 | TMODE is the mode the caller would like the value to have; | ||
| 325 | but the value may be returned with type MODE instead. | ||
| 326 | @@ -1685,10 +1701,10 @@ | ||
| 327 | |||
| 328 | rtx | ||
| 329 | extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize, | ||
| 330 | - unsigned HOST_WIDE_INT bitnum, int unsignedp, rtx target, | ||
| 331 | - enum machine_mode mode, enum machine_mode tmode) | ||
| 332 | + unsigned HOST_WIDE_INT bitnum, int unsignedp, bool packedp, | ||
| 333 | + rtx target, enum machine_mode mode, enum machine_mode tmode) | ||
| 334 | { | ||
| 335 | - return extract_bit_field_1 (str_rtx, bitsize, bitnum, unsignedp, | ||
| 336 | + return extract_bit_field_1 (str_rtx, bitsize, bitnum, unsignedp, packedp, | ||
| 337 | target, mode, tmode, true); | ||
| 338 | } | ||
| 339 | |||
| 340 | @@ -1704,6 +1720,8 @@ | ||
| 341 | which is significant on bigendian machines.) | ||
| 342 | |||
| 343 | UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value). | ||
| 344 | + PACKEDP is true if the field has the packed attribute. | ||
| 345 | + | ||
| 346 | If TARGET is nonzero, attempts to store the value there | ||
| 347 | and return TARGET, but this is not guaranteed. | ||
| 348 | If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */ | ||
| 349 | @@ -1713,7 +1731,7 @@ | ||
| 350 | unsigned HOST_WIDE_INT offset, | ||
| 351 | unsigned HOST_WIDE_INT bitsize, | ||
| 352 | unsigned HOST_WIDE_INT bitpos, rtx target, | ||
| 353 | - int unsignedp) | ||
| 354 | + int unsignedp, bool packedp) | ||
| 355 | { | ||
| 356 | unsigned int total_bits = BITS_PER_WORD; | ||
| 357 | enum machine_mode mode; | ||
| 358 | @@ -1730,8 +1748,19 @@ | ||
| 359 | includes the entire field. If such a mode would be larger than | ||
| 360 | a word, we won't be doing the extraction the normal way. */ | ||
| 361 | |||
| 362 | - mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, | ||
| 363 | - MEM_ALIGN (op0), word_mode, MEM_VOLATILE_P (op0)); | ||
| 364 | + if (MEM_VOLATILE_P (op0) | ||
| 365 | + && flag_strict_volatile_bitfields > 0) | ||
| 366 | + { | ||
| 367 | + if (GET_MODE_BITSIZE (GET_MODE (op0)) > 0) | ||
| 368 | + mode = GET_MODE (op0); | ||
| 369 | + else if (target && GET_MODE_BITSIZE (GET_MODE (target)) > 0) | ||
| 370 | + mode = GET_MODE (target); | ||
| 371 | + else | ||
| 372 | + mode = tmode; | ||
| 373 | + } | ||
| 374 | + else | ||
| 375 | + mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, | ||
| 376 | + MEM_ALIGN (op0), word_mode, MEM_VOLATILE_P (op0)); | ||
| 377 | |||
| 378 | if (mode == VOIDmode) | ||
| 379 | /* The only way this should occur is if the field spans word | ||
| 380 | @@ -1752,12 +1781,67 @@ | ||
| 381 | * BITS_PER_UNIT); | ||
| 382 | } | ||
| 383 | |||
| 384 | - /* Get ref to an aligned byte, halfword, or word containing the field. | ||
| 385 | - Adjust BITPOS to be position within a word, | ||
| 386 | - and OFFSET to be the offset of that word. | ||
| 387 | - Then alter OP0 to refer to that word. */ | ||
| 388 | - bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; | ||
| 389 | - offset -= (offset % (total_bits / BITS_PER_UNIT)); | ||
| 390 | + /* If we're accessing a volatile MEM, we can't do the next | ||
| 391 | + alignment step if it results in a multi-word access where we | ||
| 392 | + otherwise wouldn't have one. So, check for that case | ||
| 393 | + here. */ | ||
| 394 | + if (MEM_P (op0) | ||
| 395 | + && MEM_VOLATILE_P (op0) | ||
| 396 | + && flag_strict_volatile_bitfields > 0 | ||
| 397 | + && bitpos + bitsize <= total_bits | ||
| 398 | + && bitpos + bitsize + (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT > total_bits) | ||
| 399 | + { | ||
| 400 | + if (STRICT_ALIGNMENT) | ||
| 401 | + { | ||
| 402 | + static bool informed_about_misalignment = false; | ||
| 403 | + bool warned; | ||
| 404 | + | ||
| 405 | + if (packedp) | ||
| 406 | + { | ||
| 407 | + if (bitsize == total_bits) | ||
| 408 | + warned = warning_at (input_location, OPT_fstrict_volatile_bitfields, | ||
| 409 | + "multiple accesses to volatile structure member" | ||
| 410 | + " because of packed attribute"); | ||
| 411 | + else | ||
| 412 | + warned = warning_at (input_location, OPT_fstrict_volatile_bitfields, | ||
| 413 | + "multiple accesses to volatile structure bitfield" | ||
| 414 | + " because of packed attribute"); | ||
| 415 | + | ||
| 416 | + return extract_split_bit_field (op0, bitsize, | ||
| 417 | + bitpos + offset * BITS_PER_UNIT, | ||
| 418 | + unsignedp); | ||
| 419 | + } | ||
| 420 | + | ||
| 421 | + if (bitsize == total_bits) | ||
| 422 | + warned = warning_at (input_location, OPT_fstrict_volatile_bitfields, | ||
| 423 | + "mis-aligned access used for structure member"); | ||
| 424 | + else | ||
| 425 | + warned = warning_at (input_location, OPT_fstrict_volatile_bitfields, | ||
| 426 | + "mis-aligned access used for structure bitfield"); | ||
| 427 | + | ||
| 428 | + if (! informed_about_misalignment && warned) | ||
| 429 | + { | ||
| 430 | + informed_about_misalignment = true; | ||
| 431 | + inform (input_location, | ||
| 432 | + "When a volatile object spans multiple type-sized locations," | ||
| 433 | + " the compiler must choose between using a single mis-aligned access to" | ||
| 434 | + " preserve the volatility, or using multiple aligned accesses to avoid" | ||
| 435 | + " runtime faults. This code may fail at runtime if the hardware does" | ||
| 436 | + " not allow this access."); | ||
| 437 | + } | ||
| 438 | + } | ||
| 439 | + } | ||
| 440 | + else | ||
| 441 | + { | ||
| 442 | + | ||
| 443 | + /* Get ref to an aligned byte, halfword, or word containing the field. | ||
| 444 | + Adjust BITPOS to be position within a word, | ||
| 445 | + and OFFSET to be the offset of that word. | ||
| 446 | + Then alter OP0 to refer to that word. */ | ||
| 447 | + bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; | ||
| 448 | + offset -= (offset % (total_bits / BITS_PER_UNIT)); | ||
| 449 | + } | ||
| 450 | + | ||
| 451 | op0 = adjust_address (op0, mode, offset); | ||
| 452 | } | ||
| 453 | |||
| 454 | @@ -1966,7 +2050,7 @@ | ||
| 455 | extract_fixed_bit_field wants offset in bytes. */ | ||
| 456 | part = extract_fixed_bit_field (word_mode, word, | ||
| 457 | offset * unit / BITS_PER_UNIT, | ||
| 458 | - thissize, thispos, 0, 1); | ||
| 459 | + thissize, thispos, 0, 1, false); | ||
| 460 | bitsdone += thissize; | ||
| 461 | |||
| 462 | /* Shift this part into place for the result. */ | ||
| 463 | Index: gcc-4_5-branch/gcc/expr.c | ||
| 464 | =================================================================== | ||
| 465 | --- gcc-4_5-branch.orig/gcc/expr.c 2012-03-06 13:05:57.720590069 -0800 | ||
| 466 | +++ gcc-4_5-branch/gcc/expr.c 2012-03-06 13:40:14.504689612 -0800 | ||
| 467 | @@ -1749,7 +1749,7 @@ | ||
| 468 | && (!REG_P (tmps[i]) || GET_MODE (tmps[i]) != mode)) | ||
| 469 | tmps[i] = extract_bit_field (tmps[i], bytelen * BITS_PER_UNIT, | ||
| 470 | (bytepos % slen0) * BITS_PER_UNIT, | ||
| 471 | - 1, NULL_RTX, mode, mode); | ||
| 472 | + 1, false, NULL_RTX, mode, mode); | ||
| 473 | } | ||
| 474 | else | ||
| 475 | { | ||
| 476 | @@ -1759,7 +1759,7 @@ | ||
| 477 | mem = assign_stack_temp (GET_MODE (src), slen, 0); | ||
| 478 | emit_move_insn (mem, src); | ||
| 479 | tmps[i] = extract_bit_field (mem, bytelen * BITS_PER_UNIT, | ||
| 480 | - 0, 1, NULL_RTX, mode, mode); | ||
| 481 | + 0, 1, false, NULL_RTX, mode, mode); | ||
| 482 | } | ||
| 483 | } | ||
| 484 | /* FIXME: A SIMD parallel will eventually lead to a subreg of a | ||
| 485 | @@ -1800,7 +1800,7 @@ | ||
| 486 | tmps[i] = src; | ||
| 487 | else | ||
| 488 | tmps[i] = extract_bit_field (src, bytelen * BITS_PER_UNIT, | ||
| 489 | - bytepos * BITS_PER_UNIT, 1, NULL_RTX, | ||
| 490 | + bytepos * BITS_PER_UNIT, 1, false, NULL_RTX, | ||
| 491 | mode, mode); | ||
| 492 | |||
| 493 | if (shift) | ||
| 494 | @@ -2213,7 +2213,7 @@ | ||
| 495 | bitpos for the destination store (left justified). */ | ||
| 496 | store_bit_field (dst, bitsize, bitpos % BITS_PER_WORD, copy_mode, | ||
| 497 | extract_bit_field (src, bitsize, | ||
| 498 | - xbitpos % BITS_PER_WORD, 1, | ||
| 499 | + xbitpos % BITS_PER_WORD, 1, false, | ||
| 500 | NULL_RTX, copy_mode, copy_mode)); | ||
| 501 | } | ||
| 502 | |||
| 503 | @@ -2291,7 +2291,7 @@ | ||
| 504 | xbitpos for the destination store (right justified). */ | ||
| 505 | store_bit_field (dst_word, bitsize, xbitpos % BITS_PER_WORD, word_mode, | ||
| 506 | extract_bit_field (src_word, bitsize, | ||
| 507 | - bitpos % BITS_PER_WORD, 1, | ||
| 508 | + bitpos % BITS_PER_WORD, 1, false, | ||
| 509 | NULL_RTX, word_mode, word_mode)); | ||
| 510 | } | ||
| 511 | |||
| 512 | @@ -3075,7 +3075,7 @@ | ||
| 513 | } | ||
| 514 | |||
| 515 | return extract_bit_field (cplx, ibitsize, imag_p ? ibitsize : 0, | ||
| 516 | - true, NULL_RTX, imode, imode); | ||
| 517 | + true, false, NULL_RTX, imode, imode); | ||
| 518 | } | ||
| 519 | |||
| 520 | /* A subroutine of emit_move_insn_1. Yet another lowpart generator. | ||
| 521 | @@ -4338,6 +4338,13 @@ | ||
| 522 | |||
| 523 | to_rtx = expand_normal (tem); | ||
| 524 | |||
| 525 | + /* If the bitfield is volatile, we want to access it in the | ||
| 526 | + field's mode, not the computed mode. */ | ||
| 527 | + if (volatilep | ||
| 528 | + && GET_CODE (to_rtx) == MEM | ||
| 529 | + && flag_strict_volatile_bitfields > 0) | ||
| 530 | + to_rtx = adjust_address (to_rtx, mode1, 0); | ||
| 531 | + | ||
| 532 | if (offset != 0) | ||
| 533 | { | ||
| 534 | enum machine_mode address_mode; | ||
| 535 | @@ -6106,6 +6113,12 @@ | ||
| 536 | mode = DECL_MODE (field); | ||
| 537 | else if (DECL_MODE (field) == BLKmode) | ||
| 538 | blkmode_bitfield = true; | ||
| 539 | + else if (TREE_THIS_VOLATILE (exp) | ||
| 540 | + && flag_strict_volatile_bitfields > 0) | ||
| 541 | + /* Volatile bitfields should be accessed in the mode of the | ||
| 542 | + field's type, not the mode computed based on the bit | ||
| 543 | + size. */ | ||
| 544 | + mode = TYPE_MODE (DECL_BIT_FIELD_TYPE (field)); | ||
| 545 | |||
| 546 | *punsignedp = DECL_UNSIGNED (field); | ||
| 547 | } | ||
| 548 | @@ -8978,6 +8991,7 @@ | ||
| 549 | HOST_WIDE_INT bitsize, bitpos; | ||
| 550 | tree offset; | ||
| 551 | int volatilep = 0, must_force_mem; | ||
| 552 | + bool packedp = false; | ||
| 553 | tree tem = get_inner_reference (exp, &bitsize, &bitpos, &offset, | ||
| 554 | &mode1, &unsignedp, &volatilep, true); | ||
| 555 | rtx orig_op0, memloc; | ||
| 556 | @@ -8987,6 +9001,11 @@ | ||
| 557 | infinitely recurse. */ | ||
| 558 | gcc_assert (tem != exp); | ||
| 559 | |||
| 560 | + if (TYPE_PACKED (TREE_TYPE (TREE_OPERAND (exp, 0))) | ||
| 561 | + || (TREE_CODE (TREE_OPERAND (exp, 1)) == FIELD_DECL | ||
| 562 | + && DECL_PACKED (TREE_OPERAND (exp, 1)))) | ||
| 563 | + packedp = true; | ||
| 564 | + | ||
| 565 | /* If TEM's type is a union of variable size, pass TARGET to the inner | ||
| 566 | computation, since it will need a temporary and TARGET is known | ||
| 567 | to have to do. This occurs in unchecked conversion in Ada. */ | ||
| 568 | @@ -9003,6 +9022,14 @@ | ||
| 569 | || modifier == EXPAND_STACK_PARM) | ||
| 570 | ? modifier : EXPAND_NORMAL); | ||
| 571 | |||
| 572 | + | ||
| 573 | + /* If the bitfield is volatile, we want to access it in the | ||
| 574 | + field's mode, not the computed mode. */ | ||
| 575 | + if (volatilep | ||
| 576 | + && GET_CODE (op0) == MEM | ||
| 577 | + && flag_strict_volatile_bitfields > 0) | ||
| 578 | + op0 = adjust_address (op0, mode1, 0); | ||
| 579 | + | ||
| 580 | mode2 | ||
| 581 | = CONSTANT_P (op0) ? TYPE_MODE (TREE_TYPE (tem)) : GET_MODE (op0); | ||
| 582 | |||
| 583 | @@ -9128,6 +9155,9 @@ | ||
| 584 | && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT | ||
| 585 | && modifier != EXPAND_CONST_ADDRESS | ||
| 586 | && modifier != EXPAND_INITIALIZER) | ||
| 587 | + /* If the field is volatile, we always want an aligned | ||
| 588 | + access. */ | ||
| 589 | + || (volatilep && flag_strict_volatile_bitfields > 0) | ||
| 590 | /* If the field isn't aligned enough to fetch as a memref, | ||
| 591 | fetch it as a bit field. */ | ||
| 592 | || (mode1 != BLKmode | ||
| 593 | @@ -9188,7 +9218,7 @@ | ||
| 594 | if (MEM_P (op0) && REG_P (XEXP (op0, 0))) | ||
| 595 | mark_reg_pointer (XEXP (op0, 0), MEM_ALIGN (op0)); | ||
| 596 | |||
| 597 | - op0 = extract_bit_field (op0, bitsize, bitpos, unsignedp, | ||
| 598 | + op0 = extract_bit_field (op0, bitsize, bitpos, unsignedp, packedp, | ||
| 599 | (modifier == EXPAND_STACK_PARM | ||
| 600 | ? NULL_RTX : target), | ||
| 601 | ext_mode, ext_mode); | ||
| 602 | Index: gcc-4_5-branch/gcc/expr.h | ||
| 603 | =================================================================== | ||
| 604 | --- gcc-4_5-branch.orig/gcc/expr.h 2012-03-06 11:53:32.000000000 -0800 | ||
| 605 | +++ gcc-4_5-branch/gcc/expr.h 2012-03-06 13:05:59.668590163 -0800 | ||
| 606 | @@ -804,7 +804,7 @@ | ||
| 607 | extern void store_bit_field (rtx, unsigned HOST_WIDE_INT, | ||
| 608 | unsigned HOST_WIDE_INT, enum machine_mode, rtx); | ||
| 609 | extern rtx extract_bit_field (rtx, unsigned HOST_WIDE_INT, | ||
| 610 | - unsigned HOST_WIDE_INT, int, rtx, | ||
| 611 | + unsigned HOST_WIDE_INT, int, bool, rtx, | ||
| 612 | enum machine_mode, enum machine_mode); | ||
| 613 | extern rtx extract_low_bits (enum machine_mode, enum machine_mode, rtx); | ||
| 614 | extern rtx expand_mult (enum machine_mode, rtx, rtx, rtx, int); | ||
| 615 | Index: gcc-4_5-branch/gcc/fold-const.c | ||
| 616 | =================================================================== | ||
| 617 | --- gcc-4_5-branch.orig/gcc/fold-const.c 2012-03-06 13:05:56.880590028 -0800 | ||
| 618 | +++ gcc-4_5-branch/gcc/fold-const.c 2012-03-06 13:36:03.276677454 -0800 | ||
| 619 | @@ -4215,11 +4215,16 @@ | ||
| 620 | |||
| 621 | /* See if we can find a mode to refer to this field. We should be able to, | ||
| 622 | but fail if we can't. */ | ||
| 623 | - nmode = get_best_mode (lbitsize, lbitpos, | ||
| 624 | - const_p ? TYPE_ALIGN (TREE_TYPE (linner)) | ||
| 625 | - : MIN (TYPE_ALIGN (TREE_TYPE (linner)), | ||
| 626 | - TYPE_ALIGN (TREE_TYPE (rinner))), | ||
| 627 | - word_mode, lvolatilep || rvolatilep); | ||
| 628 | + if (lvolatilep | ||
| 629 | + && GET_MODE_BITSIZE (lmode) > 0 | ||
| 630 | + && flag_strict_volatile_bitfields > 0) | ||
| 631 | + nmode = lmode; | ||
| 632 | + else | ||
| 633 | + nmode = get_best_mode (lbitsize, lbitpos, | ||
| 634 | + const_p ? TYPE_ALIGN (TREE_TYPE (linner)) | ||
| 635 | + : MIN (TYPE_ALIGN (TREE_TYPE (linner)), | ||
| 636 | + TYPE_ALIGN (TREE_TYPE (rinner))), | ||
| 637 | + word_mode, lvolatilep || rvolatilep); | ||
| 638 | if (nmode == VOIDmode) | ||
| 639 | return 0; | ||
| 640 | |||
| 641 | Index: gcc-4_5-branch/gcc/stmt.c | ||
| 642 | =================================================================== | ||
| 643 | --- gcc-4_5-branch.orig/gcc/stmt.c 2012-03-06 13:05:54.568589917 -0800 | ||
| 644 | +++ gcc-4_5-branch/gcc/stmt.c 2012-03-06 13:36:34.948678986 -0800 | ||
| 645 | @@ -1754,7 +1754,7 @@ | ||
| 646 | xbitpos for the destination store (right justified). */ | ||
| 647 | store_bit_field (dst, bitsize, xbitpos % BITS_PER_WORD, word_mode, | ||
| 648 | extract_bit_field (src, bitsize, | ||
| 649 | - bitpos % BITS_PER_WORD, 1, | ||
| 650 | + bitpos % BITS_PER_WORD, 1, false, | ||
| 651 | NULL_RTX, word_mode, word_mode)); | ||
| 652 | } | ||
| 653 | |||
| 654 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c | ||
| 655 | =================================================================== | ||
| 656 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 657 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c 2012-03-06 13:05:59.672590164 -0800 | ||
| 658 | @@ -0,0 +1,17 @@ | ||
| 659 | +/* { dg-do compile } */ | ||
| 660 | +/* { dg-options "-O2 -fstrict-volatile-bitfields" } */ | ||
| 661 | + | ||
| 662 | +typedef struct { | ||
| 663 | + char a:1; | ||
| 664 | + char b:7; | ||
| 665 | + int c; | ||
| 666 | +} BitStruct; | ||
| 667 | + | ||
| 668 | +volatile BitStruct bits; | ||
| 669 | + | ||
| 670 | +int foo () | ||
| 671 | +{ | ||
| 672 | + return bits.b; | ||
| 673 | +} | ||
| 674 | + | ||
| 675 | +/* { dg-final { scan-assembler "mov(b|zbl).*bits" } } */ | ||
| 676 | Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c | ||
| 677 | =================================================================== | ||
| 678 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 679 | +++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c 2012-03-06 13:05:59.672590164 -0800 | ||
| 680 | @@ -0,0 +1,17 @@ | ||
| 681 | +/* { dg-do compile } */ | ||
| 682 | +/* { dg-options "-O2 -fno-strict-volatile-bitfields" } */ | ||
| 683 | + | ||
| 684 | +typedef struct { | ||
| 685 | + char a:1; | ||
| 686 | + char b:7; | ||
| 687 | + int c; | ||
| 688 | +} BitStruct; | ||
| 689 | + | ||
| 690 | +volatile BitStruct bits; | ||
| 691 | + | ||
| 692 | +int foo () | ||
| 693 | +{ | ||
| 694 | + return bits.b; | ||
| 695 | +} | ||
| 696 | + | ||
| 697 | +/* { dg-final { scan-assembler "movl.*bits" } } */ | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99425.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99425.patch deleted file mode 100644 index 17839c03d..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99425.patch +++ /dev/null | |||
| @@ -1,128 +0,0 @@ | |||
| 1 | 2010-10-26 Jie Zhang <jie@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #1259 | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | 2010-10-26 Jie Zhang <jie@codesourcery.com> | ||
| 9 | |||
| 10 | * stor-layout.c (layout_decl): Use the field's type to | ||
| 11 | determine the mode and keep DECL_BIT_FIELD for a volatile | ||
| 12 | bit-field. | ||
| 13 | * config/arm/arm.c (arm_override_options): Default to | ||
| 14 | -fstrict-volatile-bitfields. | ||
| 15 | |||
| 16 | gcc/testsuite/ | ||
| 17 | 2010-10-26 Jie Zhang <jie@codesourcery.com> | ||
| 18 | |||
| 19 | * gcc.target/arm/volatile-bitfields-1.c: New test. | ||
| 20 | * gcc.target/arm/volatile-bitfields-2.c: New test. | ||
| 21 | * gcc.target/arm/volatile-bitfields-3.c: New test. | ||
| 22 | |||
| 23 | === modified file 'gcc/config/arm/arm.c' | ||
| 24 | --- old/gcc/config/arm/arm.c 2010-11-04 10:45:05 +0000 | ||
| 25 | +++ new/gcc/config/arm/arm.c 2010-11-04 12:49:37 +0000 | ||
| 26 | @@ -1933,6 +1933,10 @@ | ||
| 27 | calculation, which is 2 instructions. */ | ||
| 28 | set_param_value ("gcse-unrestricted-cost", 2); | ||
| 29 | |||
| 30 | + /* ARM EABI defaults to strict volatile bitfields. */ | ||
| 31 | + if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0) | ||
| 32 | + flag_strict_volatile_bitfields = 1; | ||
| 33 | + | ||
| 34 | /* Register global variables with the garbage collector. */ | ||
| 35 | arm_add_gc_roots (); | ||
| 36 | |||
| 37 | |||
| 38 | === modified file 'gcc/stor-layout.c' | ||
| 39 | --- old/gcc/stor-layout.c 2010-04-02 18:54:46 +0000 | ||
| 40 | +++ new/gcc/stor-layout.c 2010-11-04 12:49:37 +0000 | ||
| 41 | @@ -593,11 +593,14 @@ | ||
| 42 | } | ||
| 43 | |||
| 44 | /* See if we can use an ordinary integer mode for a bit-field. | ||
| 45 | - Conditions are: a fixed size that is correct for another mode | ||
| 46 | - and occupying a complete byte or bytes on proper boundary. */ | ||
| 47 | + Conditions are: a fixed size that is correct for another mode, | ||
| 48 | + occupying a complete byte or bytes on proper boundary, | ||
| 49 | + and not volatile or not -fstrict-volatile-bitfields. */ | ||
| 50 | if (TYPE_SIZE (type) != 0 | ||
| 51 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | ||
| 52 | - && GET_MODE_CLASS (TYPE_MODE (type)) == MODE_INT) | ||
| 53 | + && GET_MODE_CLASS (TYPE_MODE (type)) == MODE_INT | ||
| 54 | + && !(TREE_THIS_VOLATILE (decl) | ||
| 55 | + && flag_strict_volatile_bitfields > 0)) | ||
| 56 | { | ||
| 57 | enum machine_mode xmode | ||
| 58 | = mode_for_size_tree (DECL_SIZE (decl), MODE_INT, 1); | ||
| 59 | |||
| 60 | === added file 'gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c' | ||
| 61 | --- old/gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c 1970-01-01 00:00:00 +0000 | ||
| 62 | +++ new/gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c 2010-11-04 12:49:37 +0000 | ||
| 63 | @@ -0,0 +1,18 @@ | ||
| 64 | +/* { dg-require-effective-target arm_eabi } */ | ||
| 65 | +/* { dg-do compile } */ | ||
| 66 | +/* { dg-options "-O2" } */ | ||
| 67 | + | ||
| 68 | +typedef struct { | ||
| 69 | + char a:1; | ||
| 70 | + char b:7; | ||
| 71 | + int c; | ||
| 72 | +} BitStruct; | ||
| 73 | + | ||
| 74 | +volatile BitStruct bits; | ||
| 75 | + | ||
| 76 | +int foo () | ||
| 77 | +{ | ||
| 78 | + return bits.b; | ||
| 79 | +} | ||
| 80 | + | ||
| 81 | +/* { dg-final { scan-assembler "ldrb\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */ | ||
| 82 | |||
| 83 | === added file 'gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c' | ||
| 84 | --- old/gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c 1970-01-01 00:00:00 +0000 | ||
| 85 | +++ new/gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c 2010-11-04 12:49:37 +0000 | ||
| 86 | @@ -0,0 +1,18 @@ | ||
| 87 | +/* { dg-require-effective-target arm_eabi } */ | ||
| 88 | +/* { dg-do compile } */ | ||
| 89 | +/* { dg-options "-O2" } */ | ||
| 90 | + | ||
| 91 | +typedef struct { | ||
| 92 | + volatile unsigned long a:8; | ||
| 93 | + volatile unsigned long b:8; | ||
| 94 | + volatile unsigned long c:16; | ||
| 95 | +} BitStruct; | ||
| 96 | + | ||
| 97 | +BitStruct bits; | ||
| 98 | + | ||
| 99 | +unsigned long foo () | ||
| 100 | +{ | ||
| 101 | + return bits.b; | ||
| 102 | +} | ||
| 103 | + | ||
| 104 | +/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */ | ||
| 105 | |||
| 106 | === added file 'gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c' | ||
| 107 | --- old/gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c 1970-01-01 00:00:00 +0000 | ||
| 108 | +++ new/gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c 2010-11-04 12:49:37 +0000 | ||
| 109 | @@ -0,0 +1,18 @@ | ||
| 110 | +/* { dg-require-effective-target arm_eabi } */ | ||
| 111 | +/* { dg-do compile } */ | ||
| 112 | +/* { dg-options "-O2" } */ | ||
| 113 | + | ||
| 114 | +typedef struct { | ||
| 115 | + volatile unsigned long a:8; | ||
| 116 | + volatile unsigned long b:8; | ||
| 117 | + volatile unsigned long c:16; | ||
| 118 | +} BitStruct; | ||
| 119 | + | ||
| 120 | +BitStruct bits; | ||
| 121 | + | ||
| 122 | +unsigned long foo () | ||
| 123 | +{ | ||
| 124 | + return bits.c; | ||
| 125 | +} | ||
| 126 | + | ||
| 127 | +/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */ | ||
| 128 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99426.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99426.patch deleted file mode 100644 index cf06e1ff7..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99426.patch +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | Backport from mainline: | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | 2010-10-26 Jie Zhang <jie@codesourcery.com> | ||
| 5 | |||
| 6 | * doc/invoke.texi: Improve documentation of | ||
| 7 | -fstrict-volatile-bitfields. | ||
| 8 | |||
| 9 | === modified file 'gcc/doc/invoke.texi' | ||
| 10 | --- old/gcc/doc/invoke.texi 2010-11-04 12:43:52 +0000 | ||
| 11 | +++ new/gcc/doc/invoke.texi 2010-11-04 14:29:09 +0000 | ||
| 12 | @@ -17633,8 +17633,8 @@ | ||
| 13 | @opindex fstrict-volatile-bitfields | ||
| 14 | This option should be used if accesses to volatile bitfields (or other | ||
| 15 | structure fields, although the compiler usually honors those types | ||
| 16 | -anyway) should use a single access in a mode of the same size as the | ||
| 17 | -container's type, aligned to a natural alignment if possible. For | ||
| 18 | +anyway) should use a single access of the width of the | ||
| 19 | +field's type, aligned to a natural alignment if possible. For | ||
| 20 | example, targets with memory-mapped peripheral registers might require | ||
| 21 | all such accesses to be 16 bits wide; with this flag the user could | ||
| 22 | declare all peripheral bitfields as ``unsigned short'' (assuming short | ||
| 23 | @@ -17647,11 +17647,13 @@ | ||
| 24 | any portion of the bitfield, or memory-mapped registers unrelated to | ||
| 25 | the one being updated. | ||
| 26 | |||
| 27 | -If the target requires strict alignment, and honoring the container | ||
| 28 | +If the target requires strict alignment, and honoring the field | ||
| 29 | type would require violating this alignment, a warning is issued. | ||
| 30 | -However, the access happens as the user requested, under the | ||
| 31 | -assumption that the user knows something about the target hardware | ||
| 32 | -that GCC is unaware of. | ||
| 33 | +If the field has @code{packed} attribute, the access is done without | ||
| 34 | +honoring the field type. If the field doesn't have @code{packed} | ||
| 35 | +attribute, the access is done honoring the field type. In both cases, | ||
| 36 | +GCC assumes that the user knows something about the target hardware | ||
| 37 | +that it is unaware of. | ||
| 38 | |||
| 39 | The default value of this option is determined by the application binary | ||
| 40 | interface for the target processor. | ||
| 41 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99429.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99429.patch deleted file mode 100644 index 63ba95e0e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99429.patch +++ /dev/null | |||
| @@ -1,1257 +0,0 @@ | |||
| 1 | 2010-11-09 Michael Hope <michael.hope@linaro.org> | ||
| 2 | |||
| 3 | Revert: | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | |||
| 7 | 2010-07-15 Bernd Schmidt <bernds@codesourcery.com> | ||
| 8 | |||
| 9 | gcc/ | ||
| 10 | * postreload.c (last_label_ruid, first_index_reg, last_index_reg): | ||
| 11 | New static variables. | ||
| 12 | (reload_combine_recognize_pattern): New static function, broken out | ||
| 13 | of reload_combine. | ||
| 14 | (reload_combine): Use it. Only initialize first_index_reg and | ||
| 15 | last_index_reg once. | ||
| 16 | |||
| 17 | 2010-07-17 Bernd Schmidt <bernds@codesourcery.com> | ||
| 18 | |||
| 19 | PR target/42235 | ||
| 20 | gcc/ | ||
| 21 | * postreload.c (reload_cse_move2add): Return bool, true if anything. | ||
| 22 | changed. All callers changed. | ||
| 23 | (move2add_use_add2_insn): Likewise. | ||
| 24 | (move2add_use_add3_insn): Likewise. | ||
| 25 | (reload_cse_regs): If reload_cse_move2add changed anything, rerun | ||
| 26 | reload_combine. | ||
| 27 | (RELOAD_COMBINE_MAX_USES): Bump to 16. | ||
| 28 | (last_jump_ruid): New static variable. | ||
| 29 | (struct reg_use): New members CONTAINING_MEM and RUID. | ||
| 30 | (reg_state): New members ALL_OFFSETS_MATCH and REAL_STORE_RUID. | ||
| 31 | (reload_combine_split_one_ruid, reload_combine_split_ruids, | ||
| 32 | reload_combine_purge_insn_uses, reload_combine_closest_single_use | ||
| 33 | reload_combine_purge_reg_uses_after_ruid, | ||
| 34 | reload_combine_recognize_const_pattern): New static functions. | ||
| 35 | (reload_combine_recognize_pattern): Verify that ALL_OFFSETS_MATCH | ||
| 36 | is true for our reg and that we have available index regs. | ||
| 37 | (reload_combine_note_use): New args RUID and CONTAINING_MEM. All | ||
| 38 | callers changed. Use them to initialize fields in struct reg_use. | ||
| 39 | (reload_combine): Initialize last_jump_ruid. Be careful when to | ||
| 40 | take PREV_INSN of the scanned insn. Update REAL_STORE_RUID fields. | ||
| 41 | Call reload_combine_recognize_const_pattern. | ||
| 42 | (reload_combine_note_store): Update REAL_STORE_RUID field. | ||
| 43 | |||
| 44 | gcc/testsuite/ | ||
| 45 | * gcc.target/arm/pr42235.c: New test. | ||
| 46 | |||
| 47 | 2010-07-19 Bernd Schmidt <bernds@codesourcery.com> | ||
| 48 | |||
| 49 | gcc/ | ||
| 50 | * postreload.c (reload_combine_closest_single_use): Ignore the | ||
| 51 | number of uses for DEBUG_INSNs. | ||
| 52 | (fixup_debug_insns): New static function. | ||
| 53 | (reload_combine_recognize_const_pattern): Use it. Don't let the | ||
| 54 | main loop be affected by DEBUG_INSNs. | ||
| 55 | Really disallow moving adds past a jump insn. | ||
| 56 | (reload_combine_recognize_pattern): Don't update use_ruid here. | ||
| 57 | (reload_combine_note_use): Do it here. | ||
| 58 | (reload_combine): Use control_flow_insn_p rather than JUMP_P. | ||
| 59 | |||
| 60 | 2010-07-20 Bernd Schmidt <bernds@codesourcery.com> | ||
| 61 | |||
| 62 | gcc/ | ||
| 63 | * postreload.c (fixup_debug_insns): Remove arg REGNO. New args | ||
| 64 | FROM and TO. All callers changed. Don't look for tracked uses, | ||
| 65 | just scan the RTL for DEBUG_INSNs and substitute. | ||
| 66 | (reload_combine_recognize_pattern): Call fixup_debug_insns. | ||
| 67 | (reload_combine): Ignore DEBUG_INSNs. | ||
| 68 | |||
| 69 | 2010-07-22 Bernd Schmidt <bernds@codesourcery.com> | ||
| 70 | |||
| 71 | PR bootstrap/44970 | ||
| 72 | PR middle-end/45009 | ||
| 73 | gcc/ | ||
| 74 | * postreload.c: Include "target.h". | ||
| 75 | (reload_combine_closest_single_use): Don't take DEBUG_INSNs | ||
| 76 | into account. | ||
| 77 | (fixup_debug_insns): Don't copy the rtx. | ||
| 78 | (reload_combine_recognize_const_pattern): DEBUG_INSNs can't have uses. | ||
| 79 | Don't copy when replacing. Call fixup_debug_insns in the case where | ||
| 80 | we merged one add with another. | ||
| 81 | (reload_combine_recognize_pattern): Fail if there aren't any uses. | ||
| 82 | Try harder to determine whether we're picking a valid index register. | ||
| 83 | Don't set store_ruid for an insn we're going to scan in the | ||
| 84 | next iteration. | ||
| 85 | (reload_combine): Remove unused code. | ||
| 86 | (reload_combine_note_use): When updating use information for | ||
| 87 | an old insn, ignore a use that occurs after store_ruid. | ||
| 88 | * Makefile.in (postreload.o): Update dependencies. | ||
| 89 | |||
| 90 | 2010-07-27 Bernd Schmidt <bernds@codesourcery.com> | ||
| 91 | |||
| 92 | gcc/ | ||
| 93 | * postreload.c (reload_combine_recognize_const_pattern): Move test | ||
| 94 | for limiting the insn movement to the right scope. | ||
| 95 | |||
| 96 | 2010-07-27 Bernd Schmidt <bernds@codesourcery.com> | ||
| 97 | |||
| 98 | gcc/ | ||
| 99 | * postreload.c (try_replace_in_use): New static function. | ||
| 100 | (reload_combine_recognize_const_pattern): Use it here. Allow | ||
| 101 | substituting into a final add insn, and substituting into a memory | ||
| 102 | reference in an insn that sets the reg. | ||
| 103 | |||
| 104 | === modified file 'gcc/Makefile.in' | ||
| 105 | --- old/gcc/Makefile.in 2010-10-14 11:25:44 +0000 | ||
| 106 | +++ new/gcc/Makefile.in 2010-11-08 22:08:43 +0000 | ||
| 107 | @@ -3155,7 +3155,7 @@ | ||
| 108 | $(RTL_H) $(REAL_H) $(FLAGS_H) $(EXPR_H) $(OPTABS_H) reload.h $(REGS_H) \ | ||
| 109 | hard-reg-set.h insn-config.h $(BASIC_BLOCK_H) $(RECOG_H) output.h \ | ||
| 110 | $(FUNCTION_H) $(TOPLEV_H) cselib.h $(TM_P_H) $(EXCEPT_H) $(TREE_H) $(MACHMODE_H) \ | ||
| 111 | - $(OBSTACK_H) $(TARGET_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H) | ||
| 112 | + $(OBSTACK_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H) | ||
| 113 | postreload-gcse.o : postreload-gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ | ||
| 114 | $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) insn-config.h \ | ||
| 115 | $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \ | ||
| 116 | |||
| 117 | === modified file 'gcc/postreload.c' | ||
| 118 | --- old/gcc/postreload.c 2010-10-14 11:32:02 +0000 | ||
| 119 | +++ new/gcc/postreload.c 2010-11-08 22:08:43 +0000 | ||
| 120 | @@ -44,7 +44,6 @@ | ||
| 121 | #include "toplev.h" | ||
| 122 | #include "except.h" | ||
| 123 | #include "tree.h" | ||
| 124 | -#include "target.h" | ||
| 125 | #include "timevar.h" | ||
| 126 | #include "tree-pass.h" | ||
| 127 | #include "df.h" | ||
| 128 | @@ -57,10 +56,10 @@ | ||
| 129 | static int reload_cse_simplify_operands (rtx, rtx); | ||
| 130 | |||
| 131 | static void reload_combine (void); | ||
| 132 | -static void reload_combine_note_use (rtx *, rtx, int, rtx); | ||
| 133 | +static void reload_combine_note_use (rtx *, rtx); | ||
| 134 | static void reload_combine_note_store (rtx, const_rtx, void *); | ||
| 135 | |||
| 136 | -static bool reload_cse_move2add (rtx); | ||
| 137 | +static void reload_cse_move2add (rtx); | ||
| 138 | static void move2add_note_store (rtx, const_rtx, void *); | ||
| 139 | |||
| 140 | /* Call cse / combine like post-reload optimization phases. | ||
| 141 | @@ -68,16 +67,11 @@ | ||
| 142 | void | ||
| 143 | reload_cse_regs (rtx first ATTRIBUTE_UNUSED) | ||
| 144 | { | ||
| 145 | - bool moves_converted; | ||
| 146 | reload_cse_regs_1 (first); | ||
| 147 | reload_combine (); | ||
| 148 | - moves_converted = reload_cse_move2add (first); | ||
| 149 | + reload_cse_move2add (first); | ||
| 150 | if (flag_expensive_optimizations) | ||
| 151 | - { | ||
| 152 | - if (moves_converted) | ||
| 153 | - reload_combine (); | ||
| 154 | - reload_cse_regs_1 (first); | ||
| 155 | - } | ||
| 156 | + reload_cse_regs_1 (first); | ||
| 157 | } | ||
| 158 | |||
| 159 | /* See whether a single set SET is a noop. */ | ||
| 160 | @@ -666,43 +660,30 @@ | ||
| 161 | |||
| 162 | /* The maximum number of uses of a register we can keep track of to | ||
| 163 | replace them with reg+reg addressing. */ | ||
| 164 | -#define RELOAD_COMBINE_MAX_USES 16 | ||
| 165 | +#define RELOAD_COMBINE_MAX_USES 6 | ||
| 166 | |||
| 167 | -/* Describes a recorded use of a register. */ | ||
| 168 | -struct reg_use | ||
| 169 | -{ | ||
| 170 | - /* The insn where a register has been used. */ | ||
| 171 | - rtx insn; | ||
| 172 | - /* Points to the memory reference enclosing the use, if any, NULL_RTX | ||
| 173 | - otherwise. */ | ||
| 174 | - rtx containing_mem; | ||
| 175 | - /* Location of the register withing INSN. */ | ||
| 176 | - rtx *usep; | ||
| 177 | - /* The reverse uid of the insn. */ | ||
| 178 | - int ruid; | ||
| 179 | -}; | ||
| 180 | +/* INSN is the insn where a register has been used, and USEP points to the | ||
| 181 | + location of the register within the rtl. */ | ||
| 182 | +struct reg_use { rtx insn, *usep; }; | ||
| 183 | |||
| 184 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | ||
| 185 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | ||
| 186 | - indicates where it is first set or clobbered. | ||
| 187 | + indicates where it becomes live again. | ||
| 188 | Otherwise, USE_INDEX is the index of the last encountered use of the | ||
| 189 | - register (which is first among these we have seen since we scan backwards). | ||
| 190 | - USE_RUID indicates the first encountered, i.e. last, of these uses. | ||
| 191 | - If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS | ||
| 192 | - with a constant offset; OFFSET contains this constant in that case. | ||
| 193 | + register (which is first among these we have seen since we scan backwards), | ||
| 194 | + OFFSET contains the constant offset that is added to the register in | ||
| 195 | + all encountered uses, and USE_RUID indicates the first encountered, i.e. | ||
| 196 | + last, of these uses. | ||
| 197 | STORE_RUID is always meaningful if we only want to use a value in a | ||
| 198 | register in a different place: it denotes the next insn in the insn | ||
| 199 | - stream (i.e. the last encountered) that sets or clobbers the register. | ||
| 200 | - REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */ | ||
| 201 | + stream (i.e. the last encountered) that sets or clobbers the register. */ | ||
| 202 | static struct | ||
| 203 | { | ||
| 204 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | ||
| 205 | + int use_index; | ||
| 206 | rtx offset; | ||
| 207 | - int use_index; | ||
| 208 | int store_ruid; | ||
| 209 | - int real_store_ruid; | ||
| 210 | int use_ruid; | ||
| 211 | - bool all_offsets_match; | ||
| 212 | } reg_state[FIRST_PSEUDO_REGISTER]; | ||
| 213 | |||
| 214 | /* Reverse linear uid. This is increased in reload_combine while scanning | ||
| 215 | @@ -710,548 +691,42 @@ | ||
| 216 | and the store_ruid / use_ruid fields in reg_state. */ | ||
| 217 | static int reload_combine_ruid; | ||
| 218 | |||
| 219 | -/* The RUID of the last label we encountered in reload_combine. */ | ||
| 220 | -static int last_label_ruid; | ||
| 221 | - | ||
| 222 | -/* The RUID of the last jump we encountered in reload_combine. */ | ||
| 223 | -static int last_jump_ruid; | ||
| 224 | - | ||
| 225 | -/* The register numbers of the first and last index register. A value of | ||
| 226 | - -1 in LAST_INDEX_REG indicates that we've previously computed these | ||
| 227 | - values and found no suitable index registers. */ | ||
| 228 | -static int first_index_reg = -1; | ||
| 229 | -static int last_index_reg; | ||
| 230 | - | ||
| 231 | #define LABEL_LIVE(LABEL) \ | ||
| 232 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | ||
| 233 | |||
| 234 | -/* Subroutine of reload_combine_split_ruids, called to fix up a single | ||
| 235 | - ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */ | ||
| 236 | - | ||
| 237 | -static inline void | ||
| 238 | -reload_combine_split_one_ruid (int *pruid, int split_ruid) | ||
| 239 | -{ | ||
| 240 | - if (*pruid > split_ruid) | ||
| 241 | - (*pruid)++; | ||
| 242 | -} | ||
| 243 | - | ||
| 244 | -/* Called when we insert a new insn in a position we've already passed in | ||
| 245 | - the scan. Examine all our state, increasing all ruids that are higher | ||
| 246 | - than SPLIT_RUID by one in order to make room for a new insn. */ | ||
| 247 | - | ||
| 248 | -static void | ||
| 249 | -reload_combine_split_ruids (int split_ruid) | ||
| 250 | -{ | ||
| 251 | - unsigned i; | ||
| 252 | - | ||
| 253 | - reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid); | ||
| 254 | - reload_combine_split_one_ruid (&last_label_ruid, split_ruid); | ||
| 255 | - reload_combine_split_one_ruid (&last_jump_ruid, split_ruid); | ||
| 256 | - | ||
| 257 | - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 258 | - { | ||
| 259 | - int j, idx = reg_state[i].use_index; | ||
| 260 | - reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid); | ||
| 261 | - reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid); | ||
| 262 | - reload_combine_split_one_ruid (®_state[i].real_store_ruid, | ||
| 263 | - split_ruid); | ||
| 264 | - if (idx < 0) | ||
| 265 | - continue; | ||
| 266 | - for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++) | ||
| 267 | - { | ||
| 268 | - reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid, | ||
| 269 | - split_ruid); | ||
| 270 | - } | ||
| 271 | - } | ||
| 272 | -} | ||
| 273 | - | ||
| 274 | -/* Called when we are about to rescan a previously encountered insn with | ||
| 275 | - reload_combine_note_use after modifying some part of it. This clears all | ||
| 276 | - information about uses in that particular insn. */ | ||
| 277 | - | ||
| 278 | -static void | ||
| 279 | -reload_combine_purge_insn_uses (rtx insn) | ||
| 280 | -{ | ||
| 281 | - unsigned i; | ||
| 282 | - | ||
| 283 | - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 284 | - { | ||
| 285 | - int j, k, idx = reg_state[i].use_index; | ||
| 286 | - if (idx < 0) | ||
| 287 | - continue; | ||
| 288 | - j = k = RELOAD_COMBINE_MAX_USES; | ||
| 289 | - while (j-- > idx) | ||
| 290 | - { | ||
| 291 | - if (reg_state[i].reg_use[j].insn != insn) | ||
| 292 | - { | ||
| 293 | - k--; | ||
| 294 | - if (k != j) | ||
| 295 | - reg_state[i].reg_use[k] = reg_state[i].reg_use[j]; | ||
| 296 | - } | ||
| 297 | - } | ||
| 298 | - reg_state[i].use_index = k; | ||
| 299 | - } | ||
| 300 | -} | ||
| 301 | - | ||
| 302 | -/* Called when we need to forget about all uses of REGNO after an insn | ||
| 303 | - which is identified by RUID. */ | ||
| 304 | - | ||
| 305 | -static void | ||
| 306 | -reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid) | ||
| 307 | -{ | ||
| 308 | - int j, k, idx = reg_state[regno].use_index; | ||
| 309 | - if (idx < 0) | ||
| 310 | - return; | ||
| 311 | - j = k = RELOAD_COMBINE_MAX_USES; | ||
| 312 | - while (j-- > idx) | ||
| 313 | - { | ||
| 314 | - if (reg_state[regno].reg_use[j].ruid >= ruid) | ||
| 315 | - { | ||
| 316 | - k--; | ||
| 317 | - if (k != j) | ||
| 318 | - reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j]; | ||
| 319 | - } | ||
| 320 | - } | ||
| 321 | - reg_state[regno].use_index = k; | ||
| 322 | -} | ||
| 323 | - | ||
| 324 | -/* Find the use of REGNO with the ruid that is highest among those | ||
| 325 | - lower than RUID_LIMIT, and return it if it is the only use of this | ||
| 326 | - reg in the insn. Return NULL otherwise. */ | ||
| 327 | - | ||
| 328 | -static struct reg_use * | ||
| 329 | -reload_combine_closest_single_use (unsigned regno, int ruid_limit) | ||
| 330 | -{ | ||
| 331 | - int i, best_ruid = 0; | ||
| 332 | - int use_idx = reg_state[regno].use_index; | ||
| 333 | - struct reg_use *retval; | ||
| 334 | - | ||
| 335 | - if (use_idx < 0) | ||
| 336 | - return NULL; | ||
| 337 | - retval = NULL; | ||
| 338 | - for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 339 | - { | ||
| 340 | - struct reg_use *use = reg_state[regno].reg_use + i; | ||
| 341 | - int this_ruid = use->ruid; | ||
| 342 | - if (this_ruid >= ruid_limit) | ||
| 343 | - continue; | ||
| 344 | - if (this_ruid > best_ruid) | ||
| 345 | - { | ||
| 346 | - best_ruid = this_ruid; | ||
| 347 | - retval = use; | ||
| 348 | - } | ||
| 349 | - else if (this_ruid == best_ruid) | ||
| 350 | - retval = NULL; | ||
| 351 | - } | ||
| 352 | - if (last_label_ruid >= best_ruid) | ||
| 353 | - return NULL; | ||
| 354 | - return retval; | ||
| 355 | -} | ||
| 356 | - | ||
| 357 | -/* After we've moved an add insn, fix up any debug insns that occur | ||
| 358 | - between the old location of the add and the new location. REG is | ||
| 359 | - the destination register of the add insn; REPLACEMENT is the | ||
| 360 | - SET_SRC of the add. FROM and TO specify the range in which we | ||
| 361 | - should make this change on debug insns. */ | ||
| 362 | - | ||
| 363 | -static void | ||
| 364 | -fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to) | ||
| 365 | -{ | ||
| 366 | - rtx insn; | ||
| 367 | - for (insn = from; insn != to; insn = NEXT_INSN (insn)) | ||
| 368 | - { | ||
| 369 | - rtx t; | ||
| 370 | - | ||
| 371 | - if (!DEBUG_INSN_P (insn)) | ||
| 372 | - continue; | ||
| 373 | - | ||
| 374 | - t = INSN_VAR_LOCATION_LOC (insn); | ||
| 375 | - t = simplify_replace_rtx (t, reg, replacement); | ||
| 376 | - validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0); | ||
| 377 | - } | ||
| 378 | -} | ||
| 379 | - | ||
| 380 | -/* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG | ||
| 381 | - with SRC in the insn described by USE, taking costs into account. Return | ||
| 382 | - true if we made the replacement. */ | ||
| 383 | - | ||
| 384 | -static bool | ||
| 385 | -try_replace_in_use (struct reg_use *use, rtx reg, rtx src) | ||
| 386 | -{ | ||
| 387 | - rtx use_insn = use->insn; | ||
| 388 | - rtx mem = use->containing_mem; | ||
| 389 | - bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); | ||
| 390 | - | ||
| 391 | - if (mem != NULL_RTX) | ||
| 392 | - { | ||
| 393 | - addr_space_t as = MEM_ADDR_SPACE (mem); | ||
| 394 | - rtx oldaddr = XEXP (mem, 0); | ||
| 395 | - rtx newaddr = NULL_RTX; | ||
| 396 | - int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed); | ||
| 397 | - int new_cost; | ||
| 398 | - | ||
| 399 | - newaddr = simplify_replace_rtx (oldaddr, reg, src); | ||
| 400 | - if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as)) | ||
| 401 | - { | ||
| 402 | - XEXP (mem, 0) = newaddr; | ||
| 403 | - new_cost = address_cost (newaddr, GET_MODE (mem), as, speed); | ||
| 404 | - XEXP (mem, 0) = oldaddr; | ||
| 405 | - if (new_cost <= old_cost | ||
| 406 | - && validate_change (use_insn, | ||
| 407 | - &XEXP (mem, 0), newaddr, 0)) | ||
| 408 | - return true; | ||
| 409 | - } | ||
| 410 | - } | ||
| 411 | - else | ||
| 412 | - { | ||
| 413 | - rtx new_set = single_set (use_insn); | ||
| 414 | - if (new_set | ||
| 415 | - && REG_P (SET_DEST (new_set)) | ||
| 416 | - && GET_CODE (SET_SRC (new_set)) == PLUS | ||
| 417 | - && REG_P (XEXP (SET_SRC (new_set), 0)) | ||
| 418 | - && CONSTANT_P (XEXP (SET_SRC (new_set), 1))) | ||
| 419 | - { | ||
| 420 | - rtx new_src; | ||
| 421 | - int old_cost = rtx_cost (SET_SRC (new_set), SET, speed); | ||
| 422 | - | ||
| 423 | - gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg)); | ||
| 424 | - new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src); | ||
| 425 | - | ||
| 426 | - if (rtx_cost (new_src, SET, speed) <= old_cost | ||
| 427 | - && validate_change (use_insn, &SET_SRC (new_set), | ||
| 428 | - new_src, 0)) | ||
| 429 | - return true; | ||
| 430 | - } | ||
| 431 | - } | ||
| 432 | - return false; | ||
| 433 | -} | ||
| 434 | - | ||
| 435 | -/* Called by reload_combine when scanning INSN. This function tries to detect | ||
| 436 | - patterns where a constant is added to a register, and the result is used | ||
| 437 | - in an address. | ||
| 438 | - Return true if no further processing is needed on INSN; false if it wasn't | ||
| 439 | - recognized and should be handled normally. */ | ||
| 440 | - | ||
| 441 | -static bool | ||
| 442 | -reload_combine_recognize_const_pattern (rtx insn) | ||
| 443 | -{ | ||
| 444 | - int from_ruid = reload_combine_ruid; | ||
| 445 | - rtx set, pat, reg, src, addreg; | ||
| 446 | - unsigned int regno; | ||
| 447 | - struct reg_use *use; | ||
| 448 | - bool must_move_add; | ||
| 449 | - rtx add_moved_after_insn = NULL_RTX; | ||
| 450 | - int add_moved_after_ruid = 0; | ||
| 451 | - int clobbered_regno = -1; | ||
| 452 | - | ||
| 453 | - set = single_set (insn); | ||
| 454 | - if (set == NULL_RTX) | ||
| 455 | - return false; | ||
| 456 | - | ||
| 457 | - reg = SET_DEST (set); | ||
| 458 | - src = SET_SRC (set); | ||
| 459 | - if (!REG_P (reg) | ||
| 460 | - || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1 | ||
| 461 | - || GET_MODE (reg) != Pmode | ||
| 462 | - || reg == stack_pointer_rtx) | ||
| 463 | - return false; | ||
| 464 | - | ||
| 465 | - regno = REGNO (reg); | ||
| 466 | - | ||
| 467 | - /* We look for a REG1 = REG2 + CONSTANT insn, followed by either | ||
| 468 | - uses of REG1 inside an address, or inside another add insn. If | ||
| 469 | - possible and profitable, merge the addition into subsequent | ||
| 470 | - uses. */ | ||
| 471 | - if (GET_CODE (src) != PLUS | ||
| 472 | - || !REG_P (XEXP (src, 0)) | ||
| 473 | - || !CONSTANT_P (XEXP (src, 1))) | ||
| 474 | - return false; | ||
| 475 | - | ||
| 476 | - addreg = XEXP (src, 0); | ||
| 477 | - must_move_add = rtx_equal_p (reg, addreg); | ||
| 478 | - | ||
| 479 | - pat = PATTERN (insn); | ||
| 480 | - if (must_move_add && set != pat) | ||
| 481 | - { | ||
| 482 | - /* We have to be careful when moving the add; apart from the | ||
| 483 | - single_set there may also be clobbers. Recognize one special | ||
| 484 | - case, that of one clobber alongside the set (likely a clobber | ||
| 485 | - of the CC register). */ | ||
| 486 | - gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL); | ||
| 487 | - if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set | ||
| 488 | - || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER | ||
| 489 | - || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))) | ||
| 490 | - return false; | ||
| 491 | - clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0)); | ||
| 492 | - } | ||
| 493 | - | ||
| 494 | - do | ||
| 495 | - { | ||
| 496 | - use = reload_combine_closest_single_use (regno, from_ruid); | ||
| 497 | - | ||
| 498 | - if (use) | ||
| 499 | - /* Start the search for the next use from here. */ | ||
| 500 | - from_ruid = use->ruid; | ||
| 501 | - | ||
| 502 | - if (use && GET_MODE (*use->usep) == Pmode) | ||
| 503 | - { | ||
| 504 | - bool delete_add = false; | ||
| 505 | - rtx use_insn = use->insn; | ||
| 506 | - int use_ruid = use->ruid; | ||
| 507 | - | ||
| 508 | - /* Avoid moving the add insn past a jump. */ | ||
| 509 | - if (must_move_add && use_ruid <= last_jump_ruid) | ||
| 510 | - break; | ||
| 511 | - | ||
| 512 | - /* If the add clobbers another hard reg in parallel, don't move | ||
| 513 | - it past a real set of this hard reg. */ | ||
| 514 | - if (must_move_add && clobbered_regno >= 0 | ||
| 515 | - && reg_state[clobbered_regno].real_store_ruid >= use_ruid) | ||
| 516 | - break; | ||
| 517 | - | ||
| 518 | - gcc_assert (reg_state[regno].store_ruid <= use_ruid); | ||
| 519 | - /* Avoid moving a use of ADDREG past a point where it is stored. */ | ||
| 520 | - if (reg_state[REGNO (addreg)].store_ruid > use_ruid) | ||
| 521 | - break; | ||
| 522 | - | ||
| 523 | - /* We also must not move the addition past an insn that sets | ||
| 524 | - the same register, unless we can combine two add insns. */ | ||
| 525 | - if (must_move_add && reg_state[regno].store_ruid == use_ruid) | ||
| 526 | - { | ||
| 527 | - if (use->containing_mem == NULL_RTX) | ||
| 528 | - delete_add = true; | ||
| 529 | - else | ||
| 530 | - break; | ||
| 531 | - } | ||
| 532 | - | ||
| 533 | - if (try_replace_in_use (use, reg, src)) | ||
| 534 | - { | ||
| 535 | - reload_combine_purge_insn_uses (use_insn); | ||
| 536 | - reload_combine_note_use (&PATTERN (use_insn), use_insn, | ||
| 537 | - use_ruid, NULL_RTX); | ||
| 538 | - | ||
| 539 | - if (delete_add) | ||
| 540 | - { | ||
| 541 | - fixup_debug_insns (reg, src, insn, use_insn); | ||
| 542 | - delete_insn (insn); | ||
| 543 | - return true; | ||
| 544 | - } | ||
| 545 | - if (must_move_add) | ||
| 546 | - { | ||
| 547 | - add_moved_after_insn = use_insn; | ||
| 548 | - add_moved_after_ruid = use_ruid; | ||
| 549 | - } | ||
| 550 | - continue; | ||
| 551 | - } | ||
| 552 | - } | ||
| 553 | - /* If we get here, we couldn't handle this use. */ | ||
| 554 | - if (must_move_add) | ||
| 555 | - break; | ||
| 556 | - } | ||
| 557 | - while (use); | ||
| 558 | - | ||
| 559 | - if (!must_move_add || add_moved_after_insn == NULL_RTX) | ||
| 560 | - /* Process the add normally. */ | ||
| 561 | - return false; | ||
| 562 | - | ||
| 563 | - fixup_debug_insns (reg, src, insn, add_moved_after_insn); | ||
| 564 | - | ||
| 565 | - reorder_insns (insn, insn, add_moved_after_insn); | ||
| 566 | - reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid); | ||
| 567 | - reload_combine_split_ruids (add_moved_after_ruid - 1); | ||
| 568 | - reload_combine_note_use (&PATTERN (insn), insn, | ||
| 569 | - add_moved_after_ruid, NULL_RTX); | ||
| 570 | - reg_state[regno].store_ruid = add_moved_after_ruid; | ||
| 571 | - | ||
| 572 | - return true; | ||
| 573 | -} | ||
| 574 | - | ||
| 575 | -/* Called by reload_combine when scanning INSN. Try to detect a pattern we | ||
| 576 | - can handle and improve. Return true if no further processing is needed on | ||
| 577 | - INSN; false if it wasn't recognized and should be handled normally. */ | ||
| 578 | - | ||
| 579 | -static bool | ||
| 580 | -reload_combine_recognize_pattern (rtx insn) | ||
| 581 | -{ | ||
| 582 | - rtx set, reg, src; | ||
| 583 | - unsigned int regno; | ||
| 584 | - | ||
| 585 | - set = single_set (insn); | ||
| 586 | - if (set == NULL_RTX) | ||
| 587 | - return false; | ||
| 588 | - | ||
| 589 | - reg = SET_DEST (set); | ||
| 590 | - src = SET_SRC (set); | ||
| 591 | - if (!REG_P (reg) | ||
| 592 | - || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1) | ||
| 593 | - return false; | ||
| 594 | - | ||
| 595 | - regno = REGNO (reg); | ||
| 596 | - | ||
| 597 | - /* Look for (set (REGX) (CONST_INT)) | ||
| 598 | - (set (REGX) (PLUS (REGX) (REGY))) | ||
| 599 | - ... | ||
| 600 | - ... (MEM (REGX)) ... | ||
| 601 | - and convert it to | ||
| 602 | - (set (REGZ) (CONST_INT)) | ||
| 603 | - ... | ||
| 604 | - ... (MEM (PLUS (REGZ) (REGY)))... . | ||
| 605 | - | ||
| 606 | - First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | ||
| 607 | - and that we know all uses of REGX before it dies. | ||
| 608 | - Also, explicitly check that REGX != REGY; our life information | ||
| 609 | - does not yet show whether REGY changes in this insn. */ | ||
| 610 | - | ||
| 611 | - if (GET_CODE (src) == PLUS | ||
| 612 | - && reg_state[regno].all_offsets_match | ||
| 613 | - && last_index_reg != -1 | ||
| 614 | - && REG_P (XEXP (src, 1)) | ||
| 615 | - && rtx_equal_p (XEXP (src, 0), reg) | ||
| 616 | - && !rtx_equal_p (XEXP (src, 1), reg) | ||
| 617 | - && reg_state[regno].use_index >= 0 | ||
| 618 | - && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES | ||
| 619 | - && last_label_ruid < reg_state[regno].use_ruid) | ||
| 620 | - { | ||
| 621 | - rtx base = XEXP (src, 1); | ||
| 622 | - rtx prev = prev_nonnote_insn (insn); | ||
| 623 | - rtx prev_set = prev ? single_set (prev) : NULL_RTX; | ||
| 624 | - rtx index_reg = NULL_RTX; | ||
| 625 | - rtx reg_sum = NULL_RTX; | ||
| 626 | - int i; | ||
| 627 | - | ||
| 628 | - /* Now we need to set INDEX_REG to an index register (denoted as | ||
| 629 | - REGZ in the illustration above) and REG_SUM to the expression | ||
| 630 | - register+register that we want to use to substitute uses of REG | ||
| 631 | - (typically in MEMs) with. First check REG and BASE for being | ||
| 632 | - index registers; we can use them even if they are not dead. */ | ||
| 633 | - if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | ||
| 634 | - || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | ||
| 635 | - REGNO (base))) | ||
| 636 | - { | ||
| 637 | - index_reg = reg; | ||
| 638 | - reg_sum = src; | ||
| 639 | - } | ||
| 640 | - else | ||
| 641 | - { | ||
| 642 | - /* Otherwise, look for a free index register. Since we have | ||
| 643 | - checked above that neither REG nor BASE are index registers, | ||
| 644 | - if we find anything at all, it will be different from these | ||
| 645 | - two registers. */ | ||
| 646 | - for (i = first_index_reg; i <= last_index_reg; i++) | ||
| 647 | - { | ||
| 648 | - if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) | ||
| 649 | - && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | ||
| 650 | - && reg_state[i].store_ruid <= reg_state[regno].use_ruid | ||
| 651 | - && (call_used_regs[i] || df_regs_ever_live_p (i)) | ||
| 652 | - && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM) | ||
| 653 | - && !fixed_regs[i] && !global_regs[i] | ||
| 654 | - && hard_regno_nregs[i][GET_MODE (reg)] == 1 | ||
| 655 | - && targetm.hard_regno_scratch_ok (i)) | ||
| 656 | - { | ||
| 657 | - index_reg = gen_rtx_REG (GET_MODE (reg), i); | ||
| 658 | - reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | ||
| 659 | - break; | ||
| 660 | - } | ||
| 661 | - } | ||
| 662 | - } | ||
| 663 | - | ||
| 664 | - /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that | ||
| 665 | - (REGY), i.e. BASE, is not clobbered before the last use we'll | ||
| 666 | - create. */ | ||
| 667 | - if (reg_sum | ||
| 668 | - && prev_set | ||
| 669 | - && CONST_INT_P (SET_SRC (prev_set)) | ||
| 670 | - && rtx_equal_p (SET_DEST (prev_set), reg) | ||
| 671 | - && (reg_state[REGNO (base)].store_ruid | ||
| 672 | - <= reg_state[regno].use_ruid)) | ||
| 673 | - { | ||
| 674 | - /* Change destination register and, if necessary, the constant | ||
| 675 | - value in PREV, the constant loading instruction. */ | ||
| 676 | - validate_change (prev, &SET_DEST (prev_set), index_reg, 1); | ||
| 677 | - if (reg_state[regno].offset != const0_rtx) | ||
| 678 | - validate_change (prev, | ||
| 679 | - &SET_SRC (prev_set), | ||
| 680 | - GEN_INT (INTVAL (SET_SRC (prev_set)) | ||
| 681 | - + INTVAL (reg_state[regno].offset)), | ||
| 682 | - 1); | ||
| 683 | - | ||
| 684 | - /* Now for every use of REG that we have recorded, replace REG | ||
| 685 | - with REG_SUM. */ | ||
| 686 | - for (i = reg_state[regno].use_index; | ||
| 687 | - i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 688 | - validate_unshare_change (reg_state[regno].reg_use[i].insn, | ||
| 689 | - reg_state[regno].reg_use[i].usep, | ||
| 690 | - /* Each change must have its own | ||
| 691 | - replacement. */ | ||
| 692 | - reg_sum, 1); | ||
| 693 | - | ||
| 694 | - if (apply_change_group ()) | ||
| 695 | - { | ||
| 696 | - struct reg_use *lowest_ruid = NULL; | ||
| 697 | - | ||
| 698 | - /* For every new use of REG_SUM, we have to record the use | ||
| 699 | - of BASE therein, i.e. operand 1. */ | ||
| 700 | - for (i = reg_state[regno].use_index; | ||
| 701 | - i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 702 | - { | ||
| 703 | - struct reg_use *use = reg_state[regno].reg_use + i; | ||
| 704 | - reload_combine_note_use (&XEXP (*use->usep, 1), use->insn, | ||
| 705 | - use->ruid, use->containing_mem); | ||
| 706 | - if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid) | ||
| 707 | - lowest_ruid = use; | ||
| 708 | - } | ||
| 709 | - | ||
| 710 | - fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn); | ||
| 711 | - | ||
| 712 | - /* Delete the reg-reg addition. */ | ||
| 713 | - delete_insn (insn); | ||
| 714 | - | ||
| 715 | - if (reg_state[regno].offset != const0_rtx) | ||
| 716 | - /* Previous REG_EQUIV / REG_EQUAL notes for PREV | ||
| 717 | - are now invalid. */ | ||
| 718 | - remove_reg_equal_equiv_notes (prev); | ||
| 719 | - | ||
| 720 | - reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 721 | - return true; | ||
| 722 | - } | ||
| 723 | - } | ||
| 724 | - } | ||
| 725 | - return false; | ||
| 726 | -} | ||
| 727 | - | ||
| 728 | static void | ||
| 729 | reload_combine (void) | ||
| 730 | { | ||
| 731 | - rtx insn, prev; | ||
| 732 | + rtx insn, set; | ||
| 733 | + int first_index_reg = -1; | ||
| 734 | + int last_index_reg = 0; | ||
| 735 | int i; | ||
| 736 | basic_block bb; | ||
| 737 | unsigned int r; | ||
| 738 | + int last_label_ruid; | ||
| 739 | int min_labelno, n_labels; | ||
| 740 | HARD_REG_SET ever_live_at_start, *label_live; | ||
| 741 | |||
| 742 | + /* If reg+reg can be used in offsetable memory addresses, the main chunk of | ||
| 743 | + reload has already used it where appropriate, so there is no use in | ||
| 744 | + trying to generate it now. */ | ||
| 745 | + if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS) | ||
| 746 | + return; | ||
| 747 | + | ||
| 748 | /* To avoid wasting too much time later searching for an index register, | ||
| 749 | determine the minimum and maximum index register numbers. */ | ||
| 750 | - if (INDEX_REG_CLASS == NO_REGS) | ||
| 751 | - last_index_reg = -1; | ||
| 752 | - else if (first_index_reg == -1 && last_index_reg == 0) | ||
| 753 | - { | ||
| 754 | - for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | ||
| 755 | - if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | ||
| 756 | - { | ||
| 757 | - if (first_index_reg == -1) | ||
| 758 | - first_index_reg = r; | ||
| 759 | - | ||
| 760 | - last_index_reg = r; | ||
| 761 | - } | ||
| 762 | - | ||
| 763 | - /* If no index register is available, we can quit now. Set LAST_INDEX_REG | ||
| 764 | - to -1 so we'll know to quit early the next time we get here. */ | ||
| 765 | - if (first_index_reg == -1) | ||
| 766 | - { | ||
| 767 | - last_index_reg = -1; | ||
| 768 | - return; | ||
| 769 | - } | ||
| 770 | - } | ||
| 771 | + for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | ||
| 772 | + if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | ||
| 773 | + { | ||
| 774 | + if (first_index_reg == -1) | ||
| 775 | + first_index_reg = r; | ||
| 776 | + | ||
| 777 | + last_index_reg = r; | ||
| 778 | + } | ||
| 779 | + | ||
| 780 | + /* If no index register is available, we can quit now. */ | ||
| 781 | + if (first_index_reg == -1) | ||
| 782 | + return; | ||
| 783 | |||
| 784 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime | ||
| 785 | information is a bit fuzzy immediately after reload, but it's | ||
| 786 | @@ -1278,23 +753,20 @@ | ||
| 787 | } | ||
| 788 | |||
| 789 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ | ||
| 790 | - last_label_ruid = last_jump_ruid = reload_combine_ruid = 0; | ||
| 791 | + last_label_ruid = reload_combine_ruid = 0; | ||
| 792 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | ||
| 793 | { | ||
| 794 | - reg_state[r].store_ruid = 0; | ||
| 795 | - reg_state[r].real_store_ruid = 0; | ||
| 796 | + reg_state[r].store_ruid = reload_combine_ruid; | ||
| 797 | if (fixed_regs[r]) | ||
| 798 | reg_state[r].use_index = -1; | ||
| 799 | else | ||
| 800 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 801 | } | ||
| 802 | |||
| 803 | - for (insn = get_last_insn (); insn; insn = prev) | ||
| 804 | + for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | ||
| 805 | { | ||
| 806 | rtx note; | ||
| 807 | |||
| 808 | - prev = PREV_INSN (insn); | ||
| 809 | - | ||
| 810 | /* We cannot do our optimization across labels. Invalidating all the use | ||
| 811 | information we have would be costly, so we just note where the label | ||
| 812 | is and then later disable any optimization that would cross it. */ | ||
| 813 | @@ -1305,17 +777,141 @@ | ||
| 814 | if (! fixed_regs[r]) | ||
| 815 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 816 | |||
| 817 | - if (! NONDEBUG_INSN_P (insn)) | ||
| 818 | + if (! INSN_P (insn)) | ||
| 819 | continue; | ||
| 820 | |||
| 821 | reload_combine_ruid++; | ||
| 822 | |||
| 823 | - if (control_flow_insn_p (insn)) | ||
| 824 | - last_jump_ruid = reload_combine_ruid; | ||
| 825 | - | ||
| 826 | - if (reload_combine_recognize_const_pattern (insn) | ||
| 827 | - || reload_combine_recognize_pattern (insn)) | ||
| 828 | - continue; | ||
| 829 | + /* Look for (set (REGX) (CONST_INT)) | ||
| 830 | + (set (REGX) (PLUS (REGX) (REGY))) | ||
| 831 | + ... | ||
| 832 | + ... (MEM (REGX)) ... | ||
| 833 | + and convert it to | ||
| 834 | + (set (REGZ) (CONST_INT)) | ||
| 835 | + ... | ||
| 836 | + ... (MEM (PLUS (REGZ) (REGY)))... . | ||
| 837 | + | ||
| 838 | + First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | ||
| 839 | + and that we know all uses of REGX before it dies. | ||
| 840 | + Also, explicitly check that REGX != REGY; our life information | ||
| 841 | + does not yet show whether REGY changes in this insn. */ | ||
| 842 | + set = single_set (insn); | ||
| 843 | + if (set != NULL_RTX | ||
| 844 | + && REG_P (SET_DEST (set)) | ||
| 845 | + && (hard_regno_nregs[REGNO (SET_DEST (set))] | ||
| 846 | + [GET_MODE (SET_DEST (set))] | ||
| 847 | + == 1) | ||
| 848 | + && GET_CODE (SET_SRC (set)) == PLUS | ||
| 849 | + && REG_P (XEXP (SET_SRC (set), 1)) | ||
| 850 | + && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set)) | ||
| 851 | + && !rtx_equal_p (XEXP (SET_SRC (set), 1), SET_DEST (set)) | ||
| 852 | + && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid) | ||
| 853 | + { | ||
| 854 | + rtx reg = SET_DEST (set); | ||
| 855 | + rtx plus = SET_SRC (set); | ||
| 856 | + rtx base = XEXP (plus, 1); | ||
| 857 | + rtx prev = prev_nonnote_nondebug_insn (insn); | ||
| 858 | + rtx prev_set = prev ? single_set (prev) : NULL_RTX; | ||
| 859 | + unsigned int regno = REGNO (reg); | ||
| 860 | + rtx index_reg = NULL_RTX; | ||
| 861 | + rtx reg_sum = NULL_RTX; | ||
| 862 | + | ||
| 863 | + /* Now we need to set INDEX_REG to an index register (denoted as | ||
| 864 | + REGZ in the illustration above) and REG_SUM to the expression | ||
| 865 | + register+register that we want to use to substitute uses of REG | ||
| 866 | + (typically in MEMs) with. First check REG and BASE for being | ||
| 867 | + index registers; we can use them even if they are not dead. */ | ||
| 868 | + if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | ||
| 869 | + || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | ||
| 870 | + REGNO (base))) | ||
| 871 | + { | ||
| 872 | + index_reg = reg; | ||
| 873 | + reg_sum = plus; | ||
| 874 | + } | ||
| 875 | + else | ||
| 876 | + { | ||
| 877 | + /* Otherwise, look for a free index register. Since we have | ||
| 878 | + checked above that neither REG nor BASE are index registers, | ||
| 879 | + if we find anything at all, it will be different from these | ||
| 880 | + two registers. */ | ||
| 881 | + for (i = first_index_reg; i <= last_index_reg; i++) | ||
| 882 | + { | ||
| 883 | + if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | ||
| 884 | + i) | ||
| 885 | + && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | ||
| 886 | + && reg_state[i].store_ruid <= reg_state[regno].use_ruid | ||
| 887 | + && hard_regno_nregs[i][GET_MODE (reg)] == 1) | ||
| 888 | + { | ||
| 889 | + index_reg = gen_rtx_REG (GET_MODE (reg), i); | ||
| 890 | + reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | ||
| 891 | + break; | ||
| 892 | + } | ||
| 893 | + } | ||
| 894 | + } | ||
| 895 | + | ||
| 896 | + /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that | ||
| 897 | + (REGY), i.e. BASE, is not clobbered before the last use we'll | ||
| 898 | + create. */ | ||
| 899 | + if (reg_sum | ||
| 900 | + && prev_set | ||
| 901 | + && CONST_INT_P (SET_SRC (prev_set)) | ||
| 902 | + && rtx_equal_p (SET_DEST (prev_set), reg) | ||
| 903 | + && reg_state[regno].use_index >= 0 | ||
| 904 | + && (reg_state[REGNO (base)].store_ruid | ||
| 905 | + <= reg_state[regno].use_ruid)) | ||
| 906 | + { | ||
| 907 | + int i; | ||
| 908 | + | ||
| 909 | + /* Change destination register and, if necessary, the constant | ||
| 910 | + value in PREV, the constant loading instruction. */ | ||
| 911 | + validate_change (prev, &SET_DEST (prev_set), index_reg, 1); | ||
| 912 | + if (reg_state[regno].offset != const0_rtx) | ||
| 913 | + validate_change (prev, | ||
| 914 | + &SET_SRC (prev_set), | ||
| 915 | + GEN_INT (INTVAL (SET_SRC (prev_set)) | ||
| 916 | + + INTVAL (reg_state[regno].offset)), | ||
| 917 | + 1); | ||
| 918 | + | ||
| 919 | + /* Now for every use of REG that we have recorded, replace REG | ||
| 920 | + with REG_SUM. */ | ||
| 921 | + for (i = reg_state[regno].use_index; | ||
| 922 | + i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 923 | + validate_unshare_change (reg_state[regno].reg_use[i].insn, | ||
| 924 | + reg_state[regno].reg_use[i].usep, | ||
| 925 | + /* Each change must have its own | ||
| 926 | + replacement. */ | ||
| 927 | + reg_sum, 1); | ||
| 928 | + | ||
| 929 | + if (apply_change_group ()) | ||
| 930 | + { | ||
| 931 | + /* For every new use of REG_SUM, we have to record the use | ||
| 932 | + of BASE therein, i.e. operand 1. */ | ||
| 933 | + for (i = reg_state[regno].use_index; | ||
| 934 | + i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 935 | + reload_combine_note_use | ||
| 936 | + (&XEXP (*reg_state[regno].reg_use[i].usep, 1), | ||
| 937 | + reg_state[regno].reg_use[i].insn); | ||
| 938 | + | ||
| 939 | + if (reg_state[REGNO (base)].use_ruid | ||
| 940 | + > reg_state[regno].use_ruid) | ||
| 941 | + reg_state[REGNO (base)].use_ruid | ||
| 942 | + = reg_state[regno].use_ruid; | ||
| 943 | + | ||
| 944 | + /* Delete the reg-reg addition. */ | ||
| 945 | + delete_insn (insn); | ||
| 946 | + | ||
| 947 | + if (reg_state[regno].offset != const0_rtx) | ||
| 948 | + /* Previous REG_EQUIV / REG_EQUAL notes for PREV | ||
| 949 | + are now invalid. */ | ||
| 950 | + remove_reg_equal_equiv_notes (prev); | ||
| 951 | + | ||
| 952 | + reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 953 | + reg_state[REGNO (index_reg)].store_ruid | ||
| 954 | + = reload_combine_ruid; | ||
| 955 | + continue; | ||
| 956 | + } | ||
| 957 | + } | ||
| 958 | + } | ||
| 959 | |||
| 960 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); | ||
| 961 | |||
| 962 | @@ -1371,8 +967,7 @@ | ||
| 963 | reg_state[i].use_index = -1; | ||
| 964 | } | ||
| 965 | |||
| 966 | - reload_combine_note_use (&PATTERN (insn), insn, | ||
| 967 | - reload_combine_ruid, NULL_RTX); | ||
| 968 | + reload_combine_note_use (&PATTERN (insn), insn); | ||
| 969 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | ||
| 970 | { | ||
| 971 | if (REG_NOTE_KIND (note) == REG_INC | ||
| 972 | @@ -1381,7 +976,6 @@ | ||
| 973 | int regno = REGNO (XEXP (note, 0)); | ||
| 974 | |||
| 975 | reg_state[regno].store_ruid = reload_combine_ruid; | ||
| 976 | - reg_state[regno].real_store_ruid = reload_combine_ruid; | ||
| 977 | reg_state[regno].use_index = -1; | ||
| 978 | } | ||
| 979 | } | ||
| 980 | @@ -1391,8 +985,8 @@ | ||
| 981 | } | ||
| 982 | |||
| 983 | /* Check if DST is a register or a subreg of a register; if it is, | ||
| 984 | - update store_ruid, real_store_ruid and use_index in the reg_state | ||
| 985 | - structure accordingly. Called via note_stores from reload_combine. */ | ||
| 986 | + update reg_state[regno].store_ruid and reg_state[regno].use_index | ||
| 987 | + accordingly. Called via note_stores from reload_combine. */ | ||
| 988 | |||
| 989 | static void | ||
| 990 | reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) | ||
| 991 | @@ -1416,14 +1010,14 @@ | ||
| 992 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be | ||
| 993 | careful with registers / register parts that are not full words. | ||
| 994 | Similarly for ZERO_EXTRACT. */ | ||
| 995 | - if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT | ||
| 996 | + if (GET_CODE (set) != SET | ||
| 997 | + || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT | ||
| 998 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) | ||
| 999 | { | ||
| 1000 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) | ||
| 1001 | { | ||
| 1002 | reg_state[i].use_index = -1; | ||
| 1003 | reg_state[i].store_ruid = reload_combine_ruid; | ||
| 1004 | - reg_state[i].real_store_ruid = reload_combine_ruid; | ||
| 1005 | } | ||
| 1006 | } | ||
| 1007 | else | ||
| 1008 | @@ -1431,8 +1025,6 @@ | ||
| 1009 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) | ||
| 1010 | { | ||
| 1011 | reg_state[i].store_ruid = reload_combine_ruid; | ||
| 1012 | - if (GET_CODE (set) == SET) | ||
| 1013 | - reg_state[i].real_store_ruid = reload_combine_ruid; | ||
| 1014 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 1015 | } | ||
| 1016 | } | ||
| 1017 | @@ -1443,7 +1035,7 @@ | ||
| 1018 | *XP is the pattern of INSN, or a part of it. | ||
| 1019 | Called from reload_combine, and recursively by itself. */ | ||
| 1020 | static void | ||
| 1021 | -reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem) | ||
| 1022 | +reload_combine_note_use (rtx *xp, rtx insn) | ||
| 1023 | { | ||
| 1024 | rtx x = *xp; | ||
| 1025 | enum rtx_code code = x->code; | ||
| 1026 | @@ -1456,7 +1048,7 @@ | ||
| 1027 | case SET: | ||
| 1028 | if (REG_P (SET_DEST (x))) | ||
| 1029 | { | ||
| 1030 | - reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX); | ||
| 1031 | + reload_combine_note_use (&SET_SRC (x), insn); | ||
| 1032 | return; | ||
| 1033 | } | ||
| 1034 | break; | ||
| 1035 | @@ -1512,11 +1104,6 @@ | ||
| 1036 | return; | ||
| 1037 | } | ||
| 1038 | |||
| 1039 | - /* We may be called to update uses in previously seen insns. | ||
| 1040 | - Don't add uses beyond the last store we saw. */ | ||
| 1041 | - if (ruid < reg_state[regno].store_ruid) | ||
| 1042 | - return; | ||
| 1043 | - | ||
| 1044 | /* If this register is already used in some unknown fashion, we | ||
| 1045 | can't do anything. | ||
| 1046 | If we decrement the index from zero to -1, we can't store more | ||
| 1047 | @@ -1525,34 +1112,29 @@ | ||
| 1048 | if (use_index < 0) | ||
| 1049 | return; | ||
| 1050 | |||
| 1051 | - if (use_index == RELOAD_COMBINE_MAX_USES - 1) | ||
| 1052 | + if (use_index != RELOAD_COMBINE_MAX_USES - 1) | ||
| 1053 | + { | ||
| 1054 | + /* We have found another use for a register that is already | ||
| 1055 | + used later. Check if the offsets match; if not, mark the | ||
| 1056 | + register as used in an unknown fashion. */ | ||
| 1057 | + if (! rtx_equal_p (offset, reg_state[regno].offset)) | ||
| 1058 | + { | ||
| 1059 | + reg_state[regno].use_index = -1; | ||
| 1060 | + return; | ||
| 1061 | + } | ||
| 1062 | + } | ||
| 1063 | + else | ||
| 1064 | { | ||
| 1065 | /* This is the first use of this register we have seen since we | ||
| 1066 | marked it as dead. */ | ||
| 1067 | reg_state[regno].offset = offset; | ||
| 1068 | - reg_state[regno].all_offsets_match = true; | ||
| 1069 | - reg_state[regno].use_ruid = ruid; | ||
| 1070 | - } | ||
| 1071 | - else | ||
| 1072 | - { | ||
| 1073 | - if (reg_state[regno].use_ruid > ruid) | ||
| 1074 | - reg_state[regno].use_ruid = ruid; | ||
| 1075 | - | ||
| 1076 | - if (! rtx_equal_p (offset, reg_state[regno].offset)) | ||
| 1077 | - reg_state[regno].all_offsets_match = false; | ||
| 1078 | - } | ||
| 1079 | - | ||
| 1080 | + reg_state[regno].use_ruid = reload_combine_ruid; | ||
| 1081 | + } | ||
| 1082 | reg_state[regno].reg_use[use_index].insn = insn; | ||
| 1083 | - reg_state[regno].reg_use[use_index].ruid = ruid; | ||
| 1084 | - reg_state[regno].reg_use[use_index].containing_mem = containing_mem; | ||
| 1085 | reg_state[regno].reg_use[use_index].usep = xp; | ||
| 1086 | return; | ||
| 1087 | } | ||
| 1088 | |||
| 1089 | - case MEM: | ||
| 1090 | - containing_mem = x; | ||
| 1091 | - break; | ||
| 1092 | - | ||
| 1093 | default: | ||
| 1094 | break; | ||
| 1095 | } | ||
| 1096 | @@ -1562,12 +1144,11 @@ | ||
| 1097 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | ||
| 1098 | { | ||
| 1099 | if (fmt[i] == 'e') | ||
| 1100 | - reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem); | ||
| 1101 | + reload_combine_note_use (&XEXP (x, i), insn); | ||
| 1102 | else if (fmt[i] == 'E') | ||
| 1103 | { | ||
| 1104 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | ||
| 1105 | - reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid, | ||
| 1106 | - containing_mem); | ||
| 1107 | + reload_combine_note_use (&XVECEXP (x, i, j), insn); | ||
| 1108 | } | ||
| 1109 | } | ||
| 1110 | } | ||
| 1111 | @@ -1615,10 +1196,9 @@ | ||
| 1112 | while REG is known to already have value (SYM + offset). | ||
| 1113 | This function tries to change INSN into an add instruction | ||
| 1114 | (set (REG) (plus (REG) (OFF - offset))) using the known value. | ||
| 1115 | - It also updates the information about REG's known value. | ||
| 1116 | - Return true if we made a change. */ | ||
| 1117 | + It also updates the information about REG's known value. */ | ||
| 1118 | |||
| 1119 | -static bool | ||
| 1120 | +static void | ||
| 1121 | move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn) | ||
| 1122 | { | ||
| 1123 | rtx pat = PATTERN (insn); | ||
| 1124 | @@ -1627,7 +1207,6 @@ | ||
| 1125 | rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno], | ||
| 1126 | GET_MODE (reg)); | ||
| 1127 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | ||
| 1128 | - bool changed = false; | ||
| 1129 | |||
| 1130 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | ||
| 1131 | use (set (reg) (reg)) instead. | ||
| 1132 | @@ -1642,13 +1221,13 @@ | ||
| 1133 | (reg)), would be discarded. Maybe we should | ||
| 1134 | try a truncMN pattern? */ | ||
| 1135 | if (INTVAL (off) == reg_offset [regno]) | ||
| 1136 | - changed = validate_change (insn, &SET_SRC (pat), reg, 0); | ||
| 1137 | + validate_change (insn, &SET_SRC (pat), reg, 0); | ||
| 1138 | } | ||
| 1139 | else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed) | ||
| 1140 | && have_add2_insn (reg, new_src)) | ||
| 1141 | { | ||
| 1142 | rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); | ||
| 1143 | - changed = validate_change (insn, &SET_SRC (pat), tem, 0); | ||
| 1144 | + validate_change (insn, &SET_SRC (pat), tem, 0); | ||
| 1145 | } | ||
| 1146 | else if (sym == NULL_RTX && GET_MODE (reg) != BImode) | ||
| 1147 | { | ||
| 1148 | @@ -1673,9 +1252,8 @@ | ||
| 1149 | gen_rtx_STRICT_LOW_PART (VOIDmode, | ||
| 1150 | narrow_reg), | ||
| 1151 | narrow_src); | ||
| 1152 | - changed = validate_change (insn, &PATTERN (insn), | ||
| 1153 | - new_set, 0); | ||
| 1154 | - if (changed) | ||
| 1155 | + if (validate_change (insn, &PATTERN (insn), | ||
| 1156 | + new_set, 0)) | ||
| 1157 | break; | ||
| 1158 | } | ||
| 1159 | } | ||
| 1160 | @@ -1685,7 +1263,6 @@ | ||
| 1161 | reg_mode[regno] = GET_MODE (reg); | ||
| 1162 | reg_symbol_ref[regno] = sym; | ||
| 1163 | reg_offset[regno] = INTVAL (off); | ||
| 1164 | - return changed; | ||
| 1165 | } | ||
| 1166 | |||
| 1167 | |||
| 1168 | @@ -1695,10 +1272,9 @@ | ||
| 1169 | value (SYM + offset) and change INSN into an add instruction | ||
| 1170 | (set (REG) (plus (the found register) (OFF - offset))) if such | ||
| 1171 | a register is found. It also updates the information about | ||
| 1172 | - REG's known value. | ||
| 1173 | - Return true iff we made a change. */ | ||
| 1174 | + REG's known value. */ | ||
| 1175 | |||
| 1176 | -static bool | ||
| 1177 | +static void | ||
| 1178 | move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn) | ||
| 1179 | { | ||
| 1180 | rtx pat = PATTERN (insn); | ||
| 1181 | @@ -1708,7 +1284,6 @@ | ||
| 1182 | int min_regno; | ||
| 1183 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | ||
| 1184 | int i; | ||
| 1185 | - bool changed = false; | ||
| 1186 | |||
| 1187 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 1188 | if (reg_set_luid[i] > move2add_last_label_luid | ||
| 1189 | @@ -1753,25 +1328,20 @@ | ||
| 1190 | GET_MODE (reg)); | ||
| 1191 | tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); | ||
| 1192 | } | ||
| 1193 | - if (validate_change (insn, &SET_SRC (pat), tem, 0)) | ||
| 1194 | - changed = true; | ||
| 1195 | + validate_change (insn, &SET_SRC (pat), tem, 0); | ||
| 1196 | } | ||
| 1197 | reg_set_luid[regno] = move2add_luid; | ||
| 1198 | reg_base_reg[regno] = -1; | ||
| 1199 | reg_mode[regno] = GET_MODE (reg); | ||
| 1200 | reg_symbol_ref[regno] = sym; | ||
| 1201 | reg_offset[regno] = INTVAL (off); | ||
| 1202 | - return changed; | ||
| 1203 | } | ||
| 1204 | |||
| 1205 | -/* Convert move insns with constant inputs to additions if they are cheaper. | ||
| 1206 | - Return true if any changes were made. */ | ||
| 1207 | -static bool | ||
| 1208 | +static void | ||
| 1209 | reload_cse_move2add (rtx first) | ||
| 1210 | { | ||
| 1211 | int i; | ||
| 1212 | rtx insn; | ||
| 1213 | - bool changed = false; | ||
| 1214 | |||
| 1215 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | ||
| 1216 | { | ||
| 1217 | @@ -1832,7 +1402,7 @@ | ||
| 1218 | && reg_base_reg[regno] < 0 | ||
| 1219 | && reg_symbol_ref[regno] == NULL_RTX) | ||
| 1220 | { | ||
| 1221 | - changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn); | ||
| 1222 | + move2add_use_add2_insn (reg, NULL_RTX, src, insn); | ||
| 1223 | continue; | ||
| 1224 | } | ||
| 1225 | |||
| 1226 | @@ -1893,7 +1463,6 @@ | ||
| 1227 | } | ||
| 1228 | if (success) | ||
| 1229 | delete_insn (insn); | ||
| 1230 | - changed |= success; | ||
| 1231 | insn = next; | ||
| 1232 | reg_mode[regno] = GET_MODE (reg); | ||
| 1233 | reg_offset[regno] = | ||
| 1234 | @@ -1939,12 +1508,12 @@ | ||
| 1235 | && reg_base_reg[regno] < 0 | ||
| 1236 | && reg_symbol_ref[regno] != NULL_RTX | ||
| 1237 | && rtx_equal_p (sym, reg_symbol_ref[regno])) | ||
| 1238 | - changed |= move2add_use_add2_insn (reg, sym, off, insn); | ||
| 1239 | + move2add_use_add2_insn (reg, sym, off, insn); | ||
| 1240 | |||
| 1241 | /* Otherwise, we have to find a register whose value is sum | ||
| 1242 | of sym and some constant value. */ | ||
| 1243 | else | ||
| 1244 | - changed |= move2add_use_add3_insn (reg, sym, off, insn); | ||
| 1245 | + move2add_use_add3_insn (reg, sym, off, insn); | ||
| 1246 | |||
| 1247 | continue; | ||
| 1248 | } | ||
| 1249 | @@ -1999,7 +1568,6 @@ | ||
| 1250 | } | ||
| 1251 | } | ||
| 1252 | } | ||
| 1253 | - return changed; | ||
| 1254 | } | ||
| 1255 | |||
| 1256 | /* SET is a SET or CLOBBER that sets DST. DATA is the insn which | ||
| 1257 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99432.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99432.patch deleted file mode 100644 index b63c9b35e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99432.patch +++ /dev/null | |||
| @@ -1,70 +0,0 @@ | |||
| 1 | 2010-11-03 Nathan Froyd <froydnj@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #10002 | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * config/arm/arm.c (arm_legitimate_index_p): Split | ||
| 7 | VALID_NEON_QREG_MODE and VALID_NEON_DREG_MODE cases. Permit | ||
| 8 | slightly larger constants in the latter case. | ||
| 9 | (thumb2_legitimate_index_p): Likewise. | ||
| 10 | |||
| 11 | === modified file 'gcc/config/arm/arm.c' | ||
| 12 | --- old/gcc/config/arm/arm.c 2010-11-04 12:49:37 +0000 | ||
| 13 | +++ new/gcc/config/arm/arm.c 2010-11-11 11:00:53 +0000 | ||
| 14 | @@ -5611,13 +5611,25 @@ | ||
| 15 | && INTVAL (index) > -1024 | ||
| 16 | && (INTVAL (index) & 3) == 0); | ||
| 17 | |||
| 18 | - if (TARGET_NEON | ||
| 19 | - && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) | ||
| 20 | + /* For quad modes, we restrict the constant offset to be slightly less | ||
| 21 | + than what the instruction format permits. We do this because for | ||
| 22 | + quad mode moves, we will actually decompose them into two separate | ||
| 23 | + double-mode reads or writes. INDEX must therefore be a valid | ||
| 24 | + (double-mode) offset and so should INDEX+8. */ | ||
| 25 | + if (TARGET_NEON && VALID_NEON_QREG_MODE (mode)) | ||
| 26 | return (code == CONST_INT | ||
| 27 | && INTVAL (index) < 1016 | ||
| 28 | && INTVAL (index) > -1024 | ||
| 29 | && (INTVAL (index) & 3) == 0); | ||
| 30 | |||
| 31 | + /* We have no such constraint on double mode offsets, so we permit the | ||
| 32 | + full range of the instruction format. */ | ||
| 33 | + if (TARGET_NEON && VALID_NEON_DREG_MODE (mode)) | ||
| 34 | + return (code == CONST_INT | ||
| 35 | + && INTVAL (index) < 1024 | ||
| 36 | + && INTVAL (index) > -1024 | ||
| 37 | + && (INTVAL (index) & 3) == 0); | ||
| 38 | + | ||
| 39 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) | ||
| 40 | return (code == CONST_INT | ||
| 41 | && INTVAL (index) < 1024 | ||
| 42 | @@ -5731,13 +5743,25 @@ | ||
| 43 | && (INTVAL (index) & 3) == 0); | ||
| 44 | } | ||
| 45 | |||
| 46 | - if (TARGET_NEON | ||
| 47 | - && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) | ||
| 48 | + /* For quad modes, we restrict the constant offset to be slightly less | ||
| 49 | + than what the instruction format permits. We do this because for | ||
| 50 | + quad mode moves, we will actually decompose them into two separate | ||
| 51 | + double-mode reads or writes. INDEX must therefore be a valid | ||
| 52 | + (double-mode) offset and so should INDEX+8. */ | ||
| 53 | + if (TARGET_NEON && VALID_NEON_QREG_MODE (mode)) | ||
| 54 | return (code == CONST_INT | ||
| 55 | && INTVAL (index) < 1016 | ||
| 56 | && INTVAL (index) > -1024 | ||
| 57 | && (INTVAL (index) & 3) == 0); | ||
| 58 | |||
| 59 | + /* We have no such constraint on double mode offsets, so we permit the | ||
| 60 | + full range of the instruction format. */ | ||
| 61 | + if (TARGET_NEON && VALID_NEON_DREG_MODE (mode)) | ||
| 62 | + return (code == CONST_INT | ||
| 63 | + && INTVAL (index) < 1024 | ||
| 64 | + && INTVAL (index) > -1024 | ||
| 65 | + && (INTVAL (index) & 3) == 0); | ||
| 66 | + | ||
| 67 | if (arm_address_register_rtx_p (index, strict_p) | ||
| 68 | && (GET_MODE_SIZE (mode) <= 4)) | ||
| 69 | return 1; | ||
| 70 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99433.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99433.patch deleted file mode 100644 index 6bc33f2be..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99433.patch +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | 2010-10-29 Julian Brown <julian@codesourcery.com> | ||
| 2 | |||
| 3 | Launchpad #629671 | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * config/arm/arm.h (REG_CLASS_CONTENTS): Remove soft frame pointer | ||
| 7 | from CORE_REGS and GENERAL_REGS classes. | ||
| 8 | * config/arm/arm.md (*thumb1_movsi_insn): Ignore all parts of final | ||
| 9 | constraint for register preferencing. | ||
| 10 | |||
| 11 | === modified file 'gcc/config/arm/arm.h' | ||
| 12 | --- old/gcc/config/arm/arm.h 2010-11-04 10:45:05 +0000 | ||
| 13 | +++ new/gcc/config/arm/arm.h 2010-11-11 11:12:14 +0000 | ||
| 14 | @@ -1262,8 +1262,8 @@ | ||
| 15 | { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ | ||
| 16 | { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \ | ||
| 17 | { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \ | ||
| 18 | - { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ | ||
| 19 | - { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ | ||
| 20 | + { 0x0000DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ | ||
| 21 | + { 0x0000FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ | ||
| 22 | { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ | ||
| 23 | } | ||
| 24 | |||
| 25 | |||
| 26 | === modified file 'gcc/config/arm/arm.md' | ||
| 27 | --- old/gcc/config/arm/arm.md 2010-11-04 10:45:05 +0000 | ||
| 28 | +++ new/gcc/config/arm/arm.md 2010-11-11 11:12:14 +0000 | ||
| 29 | @@ -5160,8 +5160,8 @@ | ||
| 30 | }) | ||
| 31 | |||
| 32 | (define_insn "*thumb1_movsi_insn" | ||
| 33 | - [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*lhk") | ||
| 34 | - (match_operand:SI 1 "general_operand" "l, I,J,K,>,l,mi,l,*lhk"))] | ||
| 35 | + [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*l*h*k") | ||
| 36 | + (match_operand:SI 1 "general_operand" "l, I,J,K,>,l,mi,l,*l*h*k"))] | ||
| 37 | "TARGET_THUMB1 | ||
| 38 | && ( register_operand (operands[0], SImode) | ||
| 39 | || register_operand (operands[1], SImode))" | ||
| 40 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99434.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99434.patch deleted file mode 100644 index adda68c62..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99434.patch +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | 2010-11-3 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-11-02 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * Makefile.in (LIBGCC2_CFLAGS): Add -fno-stack-protector, to | ||
| 9 | explicitly disable stack protection when building libgcc. | ||
| 10 | (CRTSTUFF_CFLAGS): Same, for crtbegin/end. | ||
| 11 | |||
| 12 | --- old/gcc/Makefile.in 2010-11-08 22:08:43 +0000 | ||
| 13 | +++ new/gcc/Makefile.in 2010-11-11 11:34:59 +0000 | ||
| 14 | @@ -646,6 +646,7 @@ | ||
| 15 | LIBGCC2_CFLAGS = -O2 $(LIBGCC2_INCLUDES) $(GCC_CFLAGS) $(TARGET_LIBGCC2_CFLAGS) \ | ||
| 16 | $(LIBGCC2_DEBUG_CFLAGS) $(GTHREAD_FLAGS) \ | ||
| 17 | -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED \ | ||
| 18 | + -fno-stack-protector \ | ||
| 19 | $(INHIBIT_LIBC_CFLAGS) | ||
| 20 | |||
| 21 | # Additional options to use when compiling libgcc2.a. | ||
| 22 | @@ -659,6 +660,7 @@ | ||
| 23 | CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \ | ||
| 24 | -finhibit-size-directive -fno-inline -fno-exceptions \ | ||
| 25 | -fno-zero-initialized-in-bss -fno-toplevel-reorder -fno-tree-vectorize \ | ||
| 26 | + -fno-stack-protector \ | ||
| 27 | $(INHIBIT_LIBC_CFLAGS) | ||
| 28 | |||
| 29 | # Additional sources to handle exceptions; overridden by targets as needed. | ||
| 30 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99435.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99435.patch deleted file mode 100644 index d66df137f..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99435.patch +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | 2010-11-08 Yao Qi <yao@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | 2010-08-02 Bernd Schmidt <bernds@codesourcery.com> | ||
| 7 | |||
| 8 | * config/arm/arm.c (arm_rtx_costs_1): Remove second clause from the | ||
| 9 | if statement which adds extra costs to frame-related | ||
| 10 | expressions. | ||
| 11 | |||
| 12 | === modified file 'gcc/config/arm/arm.c' | ||
| 13 | --- old/gcc/config/arm/arm.c 2010-11-11 11:00:53 +0000 | ||
| 14 | +++ new/gcc/config/arm/arm.c 2010-11-11 11:50:33 +0000 | ||
| 15 | @@ -6805,12 +6805,10 @@ | ||
| 16 | since then they might not be moved outside of loops. As a compromise | ||
| 17 | we allow integration with ops that have a constant as their second | ||
| 18 | operand. */ | ||
| 19 | - if ((REG_OR_SUBREG_REG (XEXP (x, 0)) | ||
| 20 | - && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) | ||
| 21 | - && GET_CODE (XEXP (x, 1)) != CONST_INT) | ||
| 22 | - || (REG_OR_SUBREG_REG (XEXP (x, 0)) | ||
| 23 | - && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) | ||
| 24 | - *total = 4; | ||
| 25 | + if (REG_OR_SUBREG_REG (XEXP (x, 0)) | ||
| 26 | + && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) | ||
| 27 | + && GET_CODE (XEXP (x, 1)) != CONST_INT) | ||
| 28 | + *total = COSTS_N_INSNS (1); | ||
| 29 | |||
| 30 | if (mode == DImode) | ||
| 31 | { | ||
| 32 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99436.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99436.patch deleted file mode 100644 index 1373b83ed..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99436.patch +++ /dev/null | |||
| @@ -1,210 +0,0 @@ | |||
| 1 | 2010-11-24 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * combine.c (subst, combine_simlify_rtx): Add new argument, use it | ||
| 5 | to track processing of conditionals. Update all callers. | ||
| 6 | (try_combine, simplify_if_then_else): Update. | ||
| 7 | |||
| 8 | === modified file 'gcc/combine.c' | ||
| 9 | Index: gcc-4_5-branch/gcc/combine.c | ||
| 10 | =================================================================== | ||
| 11 | --- gcc-4_5-branch.orig/gcc/combine.c 2011-07-22 17:24:46.000000000 -0700 | ||
| 12 | +++ gcc-4_5-branch/gcc/combine.c 2011-07-22 17:34:41.961747206 -0700 | ||
| 13 | @@ -392,8 +392,8 @@ | ||
| 14 | static void undo_all (void); | ||
| 15 | static void undo_commit (void); | ||
| 16 | static rtx *find_split_point (rtx *, rtx); | ||
| 17 | -static rtx subst (rtx, rtx, rtx, int, int); | ||
| 18 | -static rtx combine_simplify_rtx (rtx, enum machine_mode, int); | ||
| 19 | +static rtx subst (rtx, rtx, rtx, int, int, int); | ||
| 20 | +static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int); | ||
| 21 | static rtx simplify_if_then_else (rtx); | ||
| 22 | static rtx simplify_set (rtx); | ||
| 23 | static rtx simplify_logical (rtx); | ||
| 24 | @@ -2962,12 +2962,12 @@ | ||
| 25 | if (i1) | ||
| 26 | { | ||
| 27 | subst_low_luid = DF_INSN_LUID (i1); | ||
| 28 | - i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); | ||
| 29 | + i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0); | ||
| 30 | } | ||
| 31 | else | ||
| 32 | { | ||
| 33 | subst_low_luid = DF_INSN_LUID (i2); | ||
| 34 | - i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); | ||
| 35 | + i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0); | ||
| 36 | } | ||
| 37 | } | ||
| 38 | |||
| 39 | @@ -2978,7 +2978,7 @@ | ||
| 40 | to avoid self-referential rtl. */ | ||
| 41 | |||
| 42 | subst_low_luid = DF_INSN_LUID (i2); | ||
| 43 | - newpat = subst (PATTERN (i3), i2dest, i2src, 0, | ||
| 44 | + newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0, | ||
| 45 | ! i1_feeds_i3 && i1dest_in_i1src); | ||
| 46 | substed_i2 = 1; | ||
| 47 | |||
| 48 | @@ -3009,7 +3009,7 @@ | ||
| 49 | |||
| 50 | n_occurrences = 0; | ||
| 51 | subst_low_luid = DF_INSN_LUID (i1); | ||
| 52 | - newpat = subst (newpat, i1dest, i1src, 0, 0); | ||
| 53 | + newpat = subst (newpat, i1dest, i1src, 0, 0, 0); | ||
| 54 | substed_i1 = 1; | ||
| 55 | } | ||
| 56 | |||
| 57 | @@ -3071,7 +3071,7 @@ | ||
| 58 | else | ||
| 59 | /* See comment where i2pat is assigned. */ | ||
| 60 | XVECEXP (newpat, 0, --total_sets) | ||
| 61 | - = subst (i2pat, i1dest, i1src, 0, 0); | ||
| 62 | + = subst (i2pat, i1dest, i1src, 0, 0, 0); | ||
| 63 | } | ||
| 64 | } | ||
| 65 | |||
| 66 | @@ -4623,11 +4623,13 @@ | ||
| 67 | |||
| 68 | IN_DEST is nonzero if we are processing the SET_DEST of a SET. | ||
| 69 | |||
| 70 | + IN_COND is nonzero if we are on top level of the condition. | ||
| 71 | + | ||
| 72 | UNIQUE_COPY is nonzero if each substitution must be unique. We do this | ||
| 73 | by copying if `n_occurrences' is nonzero. */ | ||
| 74 | |||
| 75 | static rtx | ||
| 76 | -subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy) | ||
| 77 | +subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy) | ||
| 78 | { | ||
| 79 | enum rtx_code code = GET_CODE (x); | ||
| 80 | enum machine_mode op0_mode = VOIDmode; | ||
| 81 | @@ -4688,7 +4690,7 @@ | ||
| 82 | && GET_CODE (XVECEXP (x, 0, 0)) == SET | ||
| 83 | && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) | ||
| 84 | { | ||
| 85 | - new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy); | ||
| 86 | + new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy); | ||
| 87 | |||
| 88 | /* If this substitution failed, this whole thing fails. */ | ||
| 89 | if (GET_CODE (new_rtx) == CLOBBER | ||
| 90 | @@ -4705,7 +4707,7 @@ | ||
| 91 | && GET_CODE (dest) != CC0 | ||
| 92 | && GET_CODE (dest) != PC) | ||
| 93 | { | ||
| 94 | - new_rtx = subst (dest, from, to, 0, unique_copy); | ||
| 95 | + new_rtx = subst (dest, from, to, 0, 0, unique_copy); | ||
| 96 | |||
| 97 | /* If this substitution failed, this whole thing fails. */ | ||
| 98 | if (GET_CODE (new_rtx) == CLOBBER | ||
| 99 | @@ -4751,8 +4753,8 @@ | ||
| 100 | } | ||
| 101 | else | ||
| 102 | { | ||
| 103 | - new_rtx = subst (XVECEXP (x, i, j), from, to, 0, | ||
| 104 | - unique_copy); | ||
| 105 | + new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0, | ||
| 106 | + unique_copy); | ||
| 107 | |||
| 108 | /* If this substitution failed, this whole thing | ||
| 109 | fails. */ | ||
| 110 | @@ -4829,7 +4831,9 @@ | ||
| 111 | && (code == SUBREG || code == STRICT_LOW_PART | ||
| 112 | || code == ZERO_EXTRACT)) | ||
| 113 | || code == SET) | ||
| 114 | - && i == 0), unique_copy); | ||
| 115 | + && i == 0), | ||
| 116 | + code == IF_THEN_ELSE && i == 0, | ||
| 117 | + unique_copy); | ||
| 118 | |||
| 119 | /* If we found that we will have to reject this combination, | ||
| 120 | indicate that by returning the CLOBBER ourselves, rather than | ||
| 121 | @@ -4886,7 +4890,7 @@ | ||
| 122 | /* If X is sufficiently simple, don't bother trying to do anything | ||
| 123 | with it. */ | ||
| 124 | if (code != CONST_INT && code != REG && code != CLOBBER) | ||
| 125 | - x = combine_simplify_rtx (x, op0_mode, in_dest); | ||
| 126 | + x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond); | ||
| 127 | |||
| 128 | if (GET_CODE (x) == code) | ||
| 129 | break; | ||
| 130 | @@ -4906,10 +4910,12 @@ | ||
| 131 | expression. | ||
| 132 | |||
| 133 | OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero | ||
| 134 | - if we are inside a SET_DEST. */ | ||
| 135 | + if we are inside a SET_DEST. IN_COND is nonzero if we are on the top level | ||
| 136 | + of a condition. */ | ||
| 137 | |||
| 138 | static rtx | ||
| 139 | -combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest) | ||
| 140 | +combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest, | ||
| 141 | + int in_cond) | ||
| 142 | { | ||
| 143 | enum rtx_code code = GET_CODE (x); | ||
| 144 | enum machine_mode mode = GET_MODE (x); | ||
| 145 | @@ -4964,8 +4970,8 @@ | ||
| 146 | false arms to store-flag values. Be careful to use copy_rtx | ||
| 147 | here since true_rtx or false_rtx might share RTL with x as a | ||
| 148 | result of the if_then_else_cond call above. */ | ||
| 149 | - true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0); | ||
| 150 | - false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0); | ||
| 151 | + true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0); | ||
| 152 | + false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0); | ||
| 153 | |||
| 154 | /* If true_rtx and false_rtx are not general_operands, an if_then_else | ||
| 155 | is unlikely to be simpler. */ | ||
| 156 | @@ -5309,7 +5315,7 @@ | ||
| 157 | { | ||
| 158 | /* Try to simplify the expression further. */ | ||
| 159 | rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); | ||
| 160 | - temp = combine_simplify_rtx (tor, VOIDmode, in_dest); | ||
| 161 | + temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0); | ||
| 162 | |||
| 163 | /* If we could, great. If not, do not go ahead with the IOR | ||
| 164 | replacement, since PLUS appears in many special purpose | ||
| 165 | @@ -5402,7 +5408,16 @@ | ||
| 166 | ZERO_EXTRACT is indeed appropriate, it will be placed back by | ||
| 167 | the call to make_compound_operation in the SET case. */ | ||
| 168 | |||
| 169 | - if (STORE_FLAG_VALUE == 1 | ||
| 170 | + if (in_cond) | ||
| 171 | + /* Don't apply below optimizations if the caller would | ||
| 172 | + prefer a comparison rather than a value. | ||
| 173 | + E.g., for the condition in an IF_THEN_ELSE most targets need | ||
| 174 | + an explicit comparison. */ | ||
| 175 | + { | ||
| 176 | + ; | ||
| 177 | + } | ||
| 178 | + | ||
| 179 | + else if (STORE_FLAG_VALUE == 1 | ||
| 180 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | ||
| 181 | && op1 == const0_rtx | ||
| 182 | && mode == GET_MODE (op0) | ||
| 183 | @@ -5646,11 +5661,11 @@ | ||
| 184 | if (reg_mentioned_p (from, true_rtx)) | ||
| 185 | true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, | ||
| 186 | from, true_val), | ||
| 187 | - pc_rtx, pc_rtx, 0, 0); | ||
| 188 | + pc_rtx, pc_rtx, 0, 0, 0); | ||
| 189 | if (reg_mentioned_p (from, false_rtx)) | ||
| 190 | false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, | ||
| 191 | from, false_val), | ||
| 192 | - pc_rtx, pc_rtx, 0, 0); | ||
| 193 | + pc_rtx, pc_rtx, 0, 0, 0); | ||
| 194 | |||
| 195 | SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); | ||
| 196 | SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); | ||
| 197 | @@ -5867,11 +5882,11 @@ | ||
| 198 | { | ||
| 199 | temp = subst (simplify_gen_relational (true_code, m, VOIDmode, | ||
| 200 | cond_op0, cond_op1), | ||
| 201 | - pc_rtx, pc_rtx, 0, 0); | ||
| 202 | + pc_rtx, pc_rtx, 0, 0, 0); | ||
| 203 | temp = simplify_gen_binary (MULT, m, temp, | ||
| 204 | simplify_gen_binary (MULT, m, c1, | ||
| 205 | const_true_rtx)); | ||
| 206 | - temp = subst (temp, pc_rtx, pc_rtx, 0, 0); | ||
| 207 | + temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0); | ||
| 208 | temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp); | ||
| 209 | |||
| 210 | if (extend_op != UNKNOWN) | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99437.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99437.patch deleted file mode 100644 index 94d966608..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99437.patch +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | 2010-11-24 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 2 | |||
| 3 | Launchpad #618684 | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | |||
| 7 | 2010-04-10 Bernd Schmidt <bernds@codesourcery.com> | ||
| 8 | |||
| 9 | * reload1.c (eliminate_regs_in_insn): Don't restore an operand | ||
| 10 | if doing so would replace the entire pattern. | ||
| 11 | |||
| 12 | === modified file 'gcc/reload1.c' | ||
| 13 | --- old/gcc/reload1.c 2010-10-04 00:50:43 +0000 | ||
| 14 | +++ new/gcc/reload1.c 2010-11-24 13:40:23 +0000 | ||
| 15 | @@ -3567,7 +3567,10 @@ | ||
| 16 | { | ||
| 17 | /* Restore the old body. */ | ||
| 18 | for (i = 0; i < recog_data.n_operands; i++) | ||
| 19 | - *recog_data.operand_loc[i] = orig_operand[i]; | ||
| 20 | + /* Restoring a top-level match_parallel would clobber the new_body | ||
| 21 | + we installed in the insn. */ | ||
| 22 | + if (recog_data.operand_loc[i] != &PATTERN (insn)) | ||
| 23 | + *recog_data.operand_loc[i] = orig_operand[i]; | ||
| 24 | for (i = 0; i < recog_data.n_dups; i++) | ||
| 25 | *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; | ||
| 26 | } | ||
| 27 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99439.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99439.patch deleted file mode 100644 index cec7f57d4..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99439.patch +++ /dev/null | |||
| @@ -1,1500 +0,0 @@ | |||
| 1 | 2010-11-16 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | 2010-07-21 Richard Henderson <rth@redhat.com> | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * config/i386/i386.c (setup_incoming_varargs_64): Emit a simple | ||
| 7 | comparison for avoiding xmm register saves. Emit the xmm register | ||
| 8 | saves explicitly. | ||
| 9 | * config/i386/i386.md (UNSPEC_SSE_PROLOGUE_SAVE): Remove. | ||
| 10 | (UNSPEC_SSE_PROLOGUE_SAVE_LOW): Remove. | ||
| 11 | (sse_prologue_save, sse_prologue_save_insn1, sse_prologue_save_insn): | ||
| 12 | Remove patterns and the associated splitters. | ||
| 13 | |||
| 14 | 2010-07-22 Richard Henderson <rth@redhat.com> | ||
| 15 | |||
| 16 | gcc/ | ||
| 17 | PR target/45027 | ||
| 18 | * config/i386/i386.c (setup_incoming_varargs_64): Force the use | ||
| 19 | of V4SFmode for the SSE saves; increase stack alignment if needed. | ||
| 20 | |||
| 21 | 2010-11-16 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 22 | |||
| 23 | Re-merge, backport from mainline: | ||
| 24 | |||
| 25 | 2010-07-15 Bernd Schmidt <bernds@codesourcery.com> | ||
| 26 | |||
| 27 | gcc/ | ||
| 28 | * postreload.c (last_label_ruid, first_index_reg, last_index_reg): | ||
| 29 | New static variables. | ||
| 30 | (reload_combine_recognize_pattern): New static function, broken out | ||
| 31 | of reload_combine. | ||
| 32 | (reload_combine): Use it. Only initialize first_index_reg and | ||
| 33 | last_index_reg once. | ||
| 34 | |||
| 35 | 2010-07-17 Bernd Schmidt <bernds@codesourcery.com> | ||
| 36 | |||
| 37 | PR target/42235 | ||
| 38 | gcc/ | ||
| 39 | * postreload.c (reload_cse_move2add): Return bool, true if anything. | ||
| 40 | changed. All callers changed. | ||
| 41 | (move2add_use_add2_insn): Likewise. | ||
| 42 | (move2add_use_add3_insn): Likewise. | ||
| 43 | (reload_cse_regs): If reload_cse_move2add changed anything, rerun | ||
| 44 | reload_combine. | ||
| 45 | (RELOAD_COMBINE_MAX_USES): Bump to 16. | ||
| 46 | (last_jump_ruid): New static variable. | ||
| 47 | (struct reg_use): New members CONTAINING_MEM and RUID. | ||
| 48 | (reg_state): New members ALL_OFFSETS_MATCH and REAL_STORE_RUID. | ||
| 49 | (reload_combine_split_one_ruid, reload_combine_split_ruids, | ||
| 50 | reload_combine_purge_insn_uses, reload_combine_closest_single_use | ||
| 51 | reload_combine_purge_reg_uses_after_ruid, | ||
| 52 | reload_combine_recognize_const_pattern): New static functions. | ||
| 53 | (reload_combine_recognize_pattern): Verify that ALL_OFFSETS_MATCH | ||
| 54 | is true for our reg and that we have available index regs. | ||
| 55 | (reload_combine_note_use): New args RUID and CONTAINING_MEM. All | ||
| 56 | callers changed. Use them to initialize fields in struct reg_use. | ||
| 57 | (reload_combine): Initialize last_jump_ruid. Be careful when to | ||
| 58 | take PREV_INSN of the scanned insn. Update REAL_STORE_RUID fields. | ||
| 59 | Call reload_combine_recognize_const_pattern. | ||
| 60 | (reload_combine_note_store): Update REAL_STORE_RUID field. | ||
| 61 | |||
| 62 | gcc/testsuite/ | ||
| 63 | * gcc.target/arm/pr42235.c: New test. | ||
| 64 | |||
| 65 | 2010-07-19 Bernd Schmidt <bernds@codesourcery.com> | ||
| 66 | |||
| 67 | gcc/ | ||
| 68 | * postreload.c (reload_combine_closest_single_use): Ignore the | ||
| 69 | number of uses for DEBUG_INSNs. | ||
| 70 | (fixup_debug_insns): New static function. | ||
| 71 | (reload_combine_recognize_const_pattern): Use it. Don't let the | ||
| 72 | main loop be affected by DEBUG_INSNs. | ||
| 73 | Really disallow moving adds past a jump insn. | ||
| 74 | (reload_combine_recognize_pattern): Don't update use_ruid here. | ||
| 75 | (reload_combine_note_use): Do it here. | ||
| 76 | (reload_combine): Use control_flow_insn_p rather than JUMP_P. | ||
| 77 | |||
| 78 | 2010-07-20 Bernd Schmidt <bernds@codesourcery.com> | ||
| 79 | |||
| 80 | gcc/ | ||
| 81 | * postreload.c (fixup_debug_insns): Remove arg REGNO. New args | ||
| 82 | FROM and TO. All callers changed. Don't look for tracked uses, | ||
| 83 | just scan the RTL for DEBUG_INSNs and substitute. | ||
| 84 | (reload_combine_recognize_pattern): Call fixup_debug_insns. | ||
| 85 | (reload_combine): Ignore DEBUG_INSNs. | ||
| 86 | |||
| 87 | 2010-07-22 Bernd Schmidt <bernds@codesourcery.com> | ||
| 88 | |||
| 89 | PR bootstrap/44970 | ||
| 90 | PR middle-end/45009 | ||
| 91 | gcc/ | ||
| 92 | * postreload.c: Include "target.h". | ||
| 93 | (reload_combine_closest_single_use): Don't take DEBUG_INSNs | ||
| 94 | into account. | ||
| 95 | (fixup_debug_insns): Don't copy the rtx. | ||
| 96 | (reload_combine_recognize_const_pattern): DEBUG_INSNs can't have uses. | ||
| 97 | Don't copy when replacing. Call fixup_debug_insns in the case where | ||
| 98 | we merged one add with another. | ||
| 99 | (reload_combine_recognize_pattern): Fail if there aren't any uses. | ||
| 100 | Try harder to determine whether we're picking a valid index register. | ||
| 101 | Don't set store_ruid for an insn we're going to scan in the | ||
| 102 | next iteration. | ||
| 103 | (reload_combine): Remove unused code. | ||
| 104 | (reload_combine_note_use): When updating use information for | ||
| 105 | an old insn, ignore a use that occurs after store_ruid. | ||
| 106 | * Makefile.in (postreload.o): Update dependencies. | ||
| 107 | |||
| 108 | 2010-07-27 Bernd Schmidt <bernds@codesourcery.com> | ||
| 109 | |||
| 110 | gcc/ | ||
| 111 | * postreload.c (reload_combine_recognize_const_pattern): Move test | ||
| 112 | for limiting the insn movement to the right scope. | ||
| 113 | |||
| 114 | 2010-07-27 Bernd Schmidt <bernds@codesourcery.com> | ||
| 115 | |||
| 116 | gcc/ | ||
| 117 | * postreload.c (try_replace_in_use): New static function. | ||
| 118 | (reload_combine_recognize_const_pattern): Use it here. Allow | ||
| 119 | substituting into a final add insn, and substituting into a memory | ||
| 120 | reference in an insn that sets the reg. | ||
| 121 | |||
| 122 | === modified file 'gcc/Makefile.in' | ||
| 123 | --- old/gcc/Makefile.in 2010-11-11 11:34:59 +0000 | ||
| 124 | +++ new/gcc/Makefile.in 2010-11-16 18:05:53 +0000 | ||
| 125 | @@ -3157,7 +3157,7 @@ | ||
| 126 | $(RTL_H) $(REAL_H) $(FLAGS_H) $(EXPR_H) $(OPTABS_H) reload.h $(REGS_H) \ | ||
| 127 | hard-reg-set.h insn-config.h $(BASIC_BLOCK_H) $(RECOG_H) output.h \ | ||
| 128 | $(FUNCTION_H) $(TOPLEV_H) cselib.h $(TM_P_H) $(EXCEPT_H) $(TREE_H) $(MACHMODE_H) \ | ||
| 129 | - $(OBSTACK_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H) | ||
| 130 | + $(OBSTACK_H) $(TARGET_H) $(TIMEVAR_H) $(TREE_PASS_H) $(DF_H) $(DBGCNT_H) | ||
| 131 | postreload-gcse.o : postreload-gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ | ||
| 132 | $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) insn-config.h \ | ||
| 133 | $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \ | ||
| 134 | |||
| 135 | === modified file 'gcc/config/i386/i386.c' | ||
| 136 | --- old/gcc/config/i386/i386.c 2010-09-30 20:24:54 +0000 | ||
| 137 | +++ new/gcc/config/i386/i386.c 2010-11-16 18:05:53 +0000 | ||
| 138 | @@ -6737,12 +6737,8 @@ | ||
| 139 | setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum) | ||
| 140 | { | ||
| 141 | rtx save_area, mem; | ||
| 142 | - rtx label; | ||
| 143 | - rtx label_ref; | ||
| 144 | - rtx tmp_reg; | ||
| 145 | - rtx nsse_reg; | ||
| 146 | alias_set_type set; | ||
| 147 | - int i; | ||
| 148 | + int i, max; | ||
| 149 | |||
| 150 | /* GPR size of varargs save area. */ | ||
| 151 | if (cfun->va_list_gpr_size) | ||
| 152 | @@ -6752,7 +6748,7 @@ | ||
| 153 | |||
| 154 | /* FPR size of varargs save area. We don't need it if we don't pass | ||
| 155 | anything in SSE registers. */ | ||
| 156 | - if (cum->sse_nregs && cfun->va_list_fpr_size) | ||
| 157 | + if (TARGET_SSE && cfun->va_list_fpr_size) | ||
| 158 | ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16; | ||
| 159 | else | ||
| 160 | ix86_varargs_fpr_size = 0; | ||
| 161 | @@ -6763,10 +6759,11 @@ | ||
| 162 | save_area = frame_pointer_rtx; | ||
| 163 | set = get_varargs_alias_set (); | ||
| 164 | |||
| 165 | - for (i = cum->regno; | ||
| 166 | - i < X86_64_REGPARM_MAX | ||
| 167 | - && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD; | ||
| 168 | - i++) | ||
| 169 | + max = cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD; | ||
| 170 | + if (max > X86_64_REGPARM_MAX) | ||
| 171 | + max = X86_64_REGPARM_MAX; | ||
| 172 | + | ||
| 173 | + for (i = cum->regno; i < max; i++) | ||
| 174 | { | ||
| 175 | mem = gen_rtx_MEM (Pmode, | ||
| 176 | plus_constant (save_area, i * UNITS_PER_WORD)); | ||
| 177 | @@ -6778,62 +6775,42 @@ | ||
| 178 | |||
| 179 | if (ix86_varargs_fpr_size) | ||
| 180 | { | ||
| 181 | - /* Stack must be aligned to 16byte for FP register save area. */ | ||
| 182 | - if (crtl->stack_alignment_needed < 128) | ||
| 183 | - crtl->stack_alignment_needed = 128; | ||
| 184 | + enum machine_mode smode; | ||
| 185 | + rtx label, test; | ||
| 186 | |||
| 187 | /* Now emit code to save SSE registers. The AX parameter contains number | ||
| 188 | - of SSE parameter registers used to call this function. We use | ||
| 189 | - sse_prologue_save insn template that produces computed jump across | ||
| 190 | - SSE saves. We need some preparation work to get this working. */ | ||
| 191 | + of SSE parameter registers used to call this function, though all we | ||
| 192 | + actually check here is the zero/non-zero status. */ | ||
| 193 | |||
| 194 | label = gen_label_rtx (); | ||
| 195 | - label_ref = gen_rtx_LABEL_REF (Pmode, label); | ||
| 196 | - | ||
| 197 | - /* Compute address to jump to : | ||
| 198 | - label - eax*4 + nnamed_sse_arguments*4 Or | ||
| 199 | - label - eax*5 + nnamed_sse_arguments*5 for AVX. */ | ||
| 200 | - tmp_reg = gen_reg_rtx (Pmode); | ||
| 201 | - nsse_reg = gen_reg_rtx (Pmode); | ||
| 202 | - emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG))); | ||
| 203 | - emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, | ||
| 204 | - gen_rtx_MULT (Pmode, nsse_reg, | ||
| 205 | - GEN_INT (4)))); | ||
| 206 | - | ||
| 207 | - /* vmovaps is one byte longer than movaps. */ | ||
| 208 | - if (TARGET_AVX) | ||
| 209 | - emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, | ||
| 210 | - gen_rtx_PLUS (Pmode, tmp_reg, | ||
| 211 | - nsse_reg))); | ||
| 212 | - | ||
| 213 | - if (cum->sse_regno) | ||
| 214 | - emit_move_insn | ||
| 215 | - (nsse_reg, | ||
| 216 | - gen_rtx_CONST (DImode, | ||
| 217 | - gen_rtx_PLUS (DImode, | ||
| 218 | - label_ref, | ||
| 219 | - GEN_INT (cum->sse_regno | ||
| 220 | - * (TARGET_AVX ? 5 : 4))))); | ||
| 221 | - else | ||
| 222 | - emit_move_insn (nsse_reg, label_ref); | ||
| 223 | - emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg)); | ||
| 224 | - | ||
| 225 | - /* Compute address of memory block we save into. We always use pointer | ||
| 226 | - pointing 127 bytes after first byte to store - this is needed to keep | ||
| 227 | - instruction size limited by 4 bytes (5 bytes for AVX) with one | ||
| 228 | - byte displacement. */ | ||
| 229 | - tmp_reg = gen_reg_rtx (Pmode); | ||
| 230 | - emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, | ||
| 231 | - plus_constant (save_area, | ||
| 232 | - ix86_varargs_gpr_size + 127))); | ||
| 233 | - mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127)); | ||
| 234 | - MEM_NOTRAP_P (mem) = 1; | ||
| 235 | - set_mem_alias_set (mem, set); | ||
| 236 | - set_mem_align (mem, BITS_PER_WORD); | ||
| 237 | - | ||
| 238 | - /* And finally do the dirty job! */ | ||
| 239 | - emit_insn (gen_sse_prologue_save (mem, nsse_reg, | ||
| 240 | - GEN_INT (cum->sse_regno), label)); | ||
| 241 | + test = gen_rtx_EQ (VOIDmode, gen_rtx_REG (QImode, AX_REG), const0_rtx); | ||
| 242 | + emit_jump_insn (gen_cbranchqi4 (test, XEXP (test, 0), XEXP (test, 1), | ||
| 243 | + label)); | ||
| 244 | + | ||
| 245 | + /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if | ||
| 246 | + we used movdqa (i.e. TImode) instead? Perhaps even better would | ||
| 247 | + be if we could determine the real mode of the data, via a hook | ||
| 248 | + into pass_stdarg. Ignore all that for now. */ | ||
| 249 | + smode = V4SFmode; | ||
| 250 | + if (crtl->stack_alignment_needed < GET_MODE_ALIGNMENT (smode)) | ||
| 251 | + crtl->stack_alignment_needed = GET_MODE_ALIGNMENT (smode); | ||
| 252 | + | ||
| 253 | + max = cum->sse_regno + cfun->va_list_fpr_size / 16; | ||
| 254 | + if (max > X86_64_SSE_REGPARM_MAX) | ||
| 255 | + max = X86_64_SSE_REGPARM_MAX; | ||
| 256 | + | ||
| 257 | + for (i = cum->sse_regno; i < max; ++i) | ||
| 258 | + { | ||
| 259 | + mem = plus_constant (save_area, i * 16 + ix86_varargs_gpr_size); | ||
| 260 | + mem = gen_rtx_MEM (smode, mem); | ||
| 261 | + MEM_NOTRAP_P (mem) = 1; | ||
| 262 | + set_mem_alias_set (mem, set); | ||
| 263 | + set_mem_align (mem, GET_MODE_ALIGNMENT (smode)); | ||
| 264 | + | ||
| 265 | + emit_move_insn (mem, gen_rtx_REG (smode, SSE_REGNO (i))); | ||
| 266 | + } | ||
| 267 | + | ||
| 268 | + emit_label (label); | ||
| 269 | } | ||
| 270 | } | ||
| 271 | |||
| 272 | |||
| 273 | === modified file 'gcc/config/i386/i386.md' | ||
| 274 | --- old/gcc/config/i386/i386.md 2010-10-22 04:56:41 +0000 | ||
| 275 | +++ new/gcc/config/i386/i386.md 2010-11-27 15:24:12 +0000 | ||
| 276 | @@ -80,7 +80,6 @@ | ||
| 277 | ; Prologue support | ||
| 278 | (UNSPEC_STACK_ALLOC 11) | ||
| 279 | (UNSPEC_SET_GOT 12) | ||
| 280 | - (UNSPEC_SSE_PROLOGUE_SAVE 13) | ||
| 281 | (UNSPEC_REG_SAVE 14) | ||
| 282 | (UNSPEC_DEF_CFA 15) | ||
| 283 | (UNSPEC_SET_RIP 16) | ||
| 284 | @@ -20252,74 +20251,6 @@ | ||
| 285 | { return ASM_SHORT "0x0b0f"; } | ||
| 286 | [(set_attr "length" "2")]) | ||
| 287 | |||
| 288 | -(define_expand "sse_prologue_save" | ||
| 289 | - [(parallel [(set (match_operand:BLK 0 "" "") | ||
| 290 | - (unspec:BLK [(reg:DI XMM0_REG) | ||
| 291 | - (reg:DI XMM1_REG) | ||
| 292 | - (reg:DI XMM2_REG) | ||
| 293 | - (reg:DI XMM3_REG) | ||
| 294 | - (reg:DI XMM4_REG) | ||
| 295 | - (reg:DI XMM5_REG) | ||
| 296 | - (reg:DI XMM6_REG) | ||
| 297 | - (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE)) | ||
| 298 | - (use (match_operand:DI 1 "register_operand" "")) | ||
| 299 | - (use (match_operand:DI 2 "immediate_operand" "")) | ||
| 300 | - (use (label_ref:DI (match_operand 3 "" "")))])] | ||
| 301 | - "TARGET_64BIT" | ||
| 302 | - "") | ||
| 303 | - | ||
| 304 | -(define_insn "*sse_prologue_save_insn" | ||
| 305 | - [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R") | ||
| 306 | - (match_operand:DI 4 "const_int_operand" "n"))) | ||
| 307 | - (unspec:BLK [(reg:DI XMM0_REG) | ||
| 308 | - (reg:DI XMM1_REG) | ||
| 309 | - (reg:DI XMM2_REG) | ||
| 310 | - (reg:DI XMM3_REG) | ||
| 311 | - (reg:DI XMM4_REG) | ||
| 312 | - (reg:DI XMM5_REG) | ||
| 313 | - (reg:DI XMM6_REG) | ||
| 314 | - (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE)) | ||
| 315 | - (use (match_operand:DI 1 "register_operand" "r")) | ||
| 316 | - (use (match_operand:DI 2 "const_int_operand" "i")) | ||
| 317 | - (use (label_ref:DI (match_operand 3 "" "X")))] | ||
| 318 | - "TARGET_64BIT | ||
| 319 | - && INTVAL (operands[4]) + X86_64_SSE_REGPARM_MAX * 16 - 16 < 128 | ||
| 320 | - && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128" | ||
| 321 | -{ | ||
| 322 | - int i; | ||
| 323 | - operands[0] = gen_rtx_MEM (Pmode, | ||
| 324 | - gen_rtx_PLUS (Pmode, operands[0], operands[4])); | ||
| 325 | - /* VEX instruction with a REX prefix will #UD. */ | ||
| 326 | - if (TARGET_AVX && GET_CODE (XEXP (operands[0], 0)) != PLUS) | ||
| 327 | - gcc_unreachable (); | ||
| 328 | - | ||
| 329 | - output_asm_insn ("jmp\t%A1", operands); | ||
| 330 | - for (i = X86_64_SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--) | ||
| 331 | - { | ||
| 332 | - operands[4] = adjust_address (operands[0], DImode, i*16); | ||
| 333 | - operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i)); | ||
| 334 | - PUT_MODE (operands[4], TImode); | ||
| 335 | - if (GET_CODE (XEXP (operands[0], 0)) != PLUS) | ||
| 336 | - output_asm_insn ("rex", operands); | ||
| 337 | - output_asm_insn ("%vmovaps\t{%5, %4|%4, %5}", operands); | ||
| 338 | - } | ||
| 339 | - (*targetm.asm_out.internal_label) (asm_out_file, "L", | ||
| 340 | - CODE_LABEL_NUMBER (operands[3])); | ||
| 341 | - return ""; | ||
| 342 | -} | ||
| 343 | - [(set_attr "type" "other") | ||
| 344 | - (set_attr "length_immediate" "0") | ||
| 345 | - (set_attr "length_address" "0") | ||
| 346 | - (set (attr "length") | ||
| 347 | - (if_then_else | ||
| 348 | - (eq (symbol_ref "TARGET_AVX") (const_int 0)) | ||
| 349 | - (const_string "34") | ||
| 350 | - (const_string "42"))) | ||
| 351 | - (set_attr "memory" "store") | ||
| 352 | - (set_attr "modrm" "0") | ||
| 353 | - (set_attr "prefix" "maybe_vex") | ||
| 354 | - (set_attr "mode" "DI")]) | ||
| 355 | - | ||
| 356 | (define_expand "prefetch" | ||
| 357 | [(prefetch (match_operand 0 "address_operand" "") | ||
| 358 | (match_operand:SI 1 "const_int_operand" "") | ||
| 359 | |||
| 360 | === modified file 'gcc/postreload.c' | ||
| 361 | --- old/gcc/postreload.c 2010-11-08 22:08:43 +0000 | ||
| 362 | +++ new/gcc/postreload.c 2010-11-16 18:05:53 +0000 | ||
| 363 | @@ -44,6 +44,7 @@ | ||
| 364 | #include "toplev.h" | ||
| 365 | #include "except.h" | ||
| 366 | #include "tree.h" | ||
| 367 | +#include "target.h" | ||
| 368 | #include "timevar.h" | ||
| 369 | #include "tree-pass.h" | ||
| 370 | #include "df.h" | ||
| 371 | @@ -56,10 +57,10 @@ | ||
| 372 | static int reload_cse_simplify_operands (rtx, rtx); | ||
| 373 | |||
| 374 | static void reload_combine (void); | ||
| 375 | -static void reload_combine_note_use (rtx *, rtx); | ||
| 376 | +static void reload_combine_note_use (rtx *, rtx, int, rtx); | ||
| 377 | static void reload_combine_note_store (rtx, const_rtx, void *); | ||
| 378 | |||
| 379 | -static void reload_cse_move2add (rtx); | ||
| 380 | +static bool reload_cse_move2add (rtx); | ||
| 381 | static void move2add_note_store (rtx, const_rtx, void *); | ||
| 382 | |||
| 383 | /* Call cse / combine like post-reload optimization phases. | ||
| 384 | @@ -67,11 +68,16 @@ | ||
| 385 | void | ||
| 386 | reload_cse_regs (rtx first ATTRIBUTE_UNUSED) | ||
| 387 | { | ||
| 388 | + bool moves_converted; | ||
| 389 | reload_cse_regs_1 (first); | ||
| 390 | reload_combine (); | ||
| 391 | - reload_cse_move2add (first); | ||
| 392 | + moves_converted = reload_cse_move2add (first); | ||
| 393 | if (flag_expensive_optimizations) | ||
| 394 | - reload_cse_regs_1 (first); | ||
| 395 | + { | ||
| 396 | + if (moves_converted) | ||
| 397 | + reload_combine (); | ||
| 398 | + reload_cse_regs_1 (first); | ||
| 399 | + } | ||
| 400 | } | ||
| 401 | |||
| 402 | /* See whether a single set SET is a noop. */ | ||
| 403 | @@ -660,30 +666,43 @@ | ||
| 404 | |||
| 405 | /* The maximum number of uses of a register we can keep track of to | ||
| 406 | replace them with reg+reg addressing. */ | ||
| 407 | -#define RELOAD_COMBINE_MAX_USES 6 | ||
| 408 | +#define RELOAD_COMBINE_MAX_USES 16 | ||
| 409 | |||
| 410 | -/* INSN is the insn where a register has been used, and USEP points to the | ||
| 411 | - location of the register within the rtl. */ | ||
| 412 | -struct reg_use { rtx insn, *usep; }; | ||
| 413 | +/* Describes a recorded use of a register. */ | ||
| 414 | +struct reg_use | ||
| 415 | +{ | ||
| 416 | + /* The insn where a register has been used. */ | ||
| 417 | + rtx insn; | ||
| 418 | + /* Points to the memory reference enclosing the use, if any, NULL_RTX | ||
| 419 | + otherwise. */ | ||
| 420 | + rtx containing_mem; | ||
| 421 | + /* Location of the register withing INSN. */ | ||
| 422 | + rtx *usep; | ||
| 423 | + /* The reverse uid of the insn. */ | ||
| 424 | + int ruid; | ||
| 425 | +}; | ||
| 426 | |||
| 427 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | ||
| 428 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | ||
| 429 | - indicates where it becomes live again. | ||
| 430 | + indicates where it is first set or clobbered. | ||
| 431 | Otherwise, USE_INDEX is the index of the last encountered use of the | ||
| 432 | - register (which is first among these we have seen since we scan backwards), | ||
| 433 | - OFFSET contains the constant offset that is added to the register in | ||
| 434 | - all encountered uses, and USE_RUID indicates the first encountered, i.e. | ||
| 435 | - last, of these uses. | ||
| 436 | + register (which is first among these we have seen since we scan backwards). | ||
| 437 | + USE_RUID indicates the first encountered, i.e. last, of these uses. | ||
| 438 | + If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS | ||
| 439 | + with a constant offset; OFFSET contains this constant in that case. | ||
| 440 | STORE_RUID is always meaningful if we only want to use a value in a | ||
| 441 | register in a different place: it denotes the next insn in the insn | ||
| 442 | - stream (i.e. the last encountered) that sets or clobbers the register. */ | ||
| 443 | + stream (i.e. the last encountered) that sets or clobbers the register. | ||
| 444 | + REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */ | ||
| 445 | static struct | ||
| 446 | { | ||
| 447 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | ||
| 448 | + rtx offset; | ||
| 449 | int use_index; | ||
| 450 | - rtx offset; | ||
| 451 | int store_ruid; | ||
| 452 | + int real_store_ruid; | ||
| 453 | int use_ruid; | ||
| 454 | + bool all_offsets_match; | ||
| 455 | } reg_state[FIRST_PSEUDO_REGISTER]; | ||
| 456 | |||
| 457 | /* Reverse linear uid. This is increased in reload_combine while scanning | ||
| 458 | @@ -691,42 +710,548 @@ | ||
| 459 | and the store_ruid / use_ruid fields in reg_state. */ | ||
| 460 | static int reload_combine_ruid; | ||
| 461 | |||
| 462 | +/* The RUID of the last label we encountered in reload_combine. */ | ||
| 463 | +static int last_label_ruid; | ||
| 464 | + | ||
| 465 | +/* The RUID of the last jump we encountered in reload_combine. */ | ||
| 466 | +static int last_jump_ruid; | ||
| 467 | + | ||
| 468 | +/* The register numbers of the first and last index register. A value of | ||
| 469 | + -1 in LAST_INDEX_REG indicates that we've previously computed these | ||
| 470 | + values and found no suitable index registers. */ | ||
| 471 | +static int first_index_reg = -1; | ||
| 472 | +static int last_index_reg; | ||
| 473 | + | ||
| 474 | #define LABEL_LIVE(LABEL) \ | ||
| 475 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | ||
| 476 | |||
| 477 | +/* Subroutine of reload_combine_split_ruids, called to fix up a single | ||
| 478 | + ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */ | ||
| 479 | + | ||
| 480 | +static inline void | ||
| 481 | +reload_combine_split_one_ruid (int *pruid, int split_ruid) | ||
| 482 | +{ | ||
| 483 | + if (*pruid > split_ruid) | ||
| 484 | + (*pruid)++; | ||
| 485 | +} | ||
| 486 | + | ||
| 487 | +/* Called when we insert a new insn in a position we've already passed in | ||
| 488 | + the scan. Examine all our state, increasing all ruids that are higher | ||
| 489 | + than SPLIT_RUID by one in order to make room for a new insn. */ | ||
| 490 | + | ||
| 491 | +static void | ||
| 492 | +reload_combine_split_ruids (int split_ruid) | ||
| 493 | +{ | ||
| 494 | + unsigned i; | ||
| 495 | + | ||
| 496 | + reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid); | ||
| 497 | + reload_combine_split_one_ruid (&last_label_ruid, split_ruid); | ||
| 498 | + reload_combine_split_one_ruid (&last_jump_ruid, split_ruid); | ||
| 499 | + | ||
| 500 | + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 501 | + { | ||
| 502 | + int j, idx = reg_state[i].use_index; | ||
| 503 | + reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid); | ||
| 504 | + reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid); | ||
| 505 | + reload_combine_split_one_ruid (®_state[i].real_store_ruid, | ||
| 506 | + split_ruid); | ||
| 507 | + if (idx < 0) | ||
| 508 | + continue; | ||
| 509 | + for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++) | ||
| 510 | + { | ||
| 511 | + reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid, | ||
| 512 | + split_ruid); | ||
| 513 | + } | ||
| 514 | + } | ||
| 515 | +} | ||
| 516 | + | ||
| 517 | +/* Called when we are about to rescan a previously encountered insn with | ||
| 518 | + reload_combine_note_use after modifying some part of it. This clears all | ||
| 519 | + information about uses in that particular insn. */ | ||
| 520 | + | ||
| 521 | +static void | ||
| 522 | +reload_combine_purge_insn_uses (rtx insn) | ||
| 523 | +{ | ||
| 524 | + unsigned i; | ||
| 525 | + | ||
| 526 | + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 527 | + { | ||
| 528 | + int j, k, idx = reg_state[i].use_index; | ||
| 529 | + if (idx < 0) | ||
| 530 | + continue; | ||
| 531 | + j = k = RELOAD_COMBINE_MAX_USES; | ||
| 532 | + while (j-- > idx) | ||
| 533 | + { | ||
| 534 | + if (reg_state[i].reg_use[j].insn != insn) | ||
| 535 | + { | ||
| 536 | + k--; | ||
| 537 | + if (k != j) | ||
| 538 | + reg_state[i].reg_use[k] = reg_state[i].reg_use[j]; | ||
| 539 | + } | ||
| 540 | + } | ||
| 541 | + reg_state[i].use_index = k; | ||
| 542 | + } | ||
| 543 | +} | ||
| 544 | + | ||
| 545 | +/* Called when we need to forget about all uses of REGNO after an insn | ||
| 546 | + which is identified by RUID. */ | ||
| 547 | + | ||
| 548 | +static void | ||
| 549 | +reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid) | ||
| 550 | +{ | ||
| 551 | + int j, k, idx = reg_state[regno].use_index; | ||
| 552 | + if (idx < 0) | ||
| 553 | + return; | ||
| 554 | + j = k = RELOAD_COMBINE_MAX_USES; | ||
| 555 | + while (j-- > idx) | ||
| 556 | + { | ||
| 557 | + if (reg_state[regno].reg_use[j].ruid >= ruid) | ||
| 558 | + { | ||
| 559 | + k--; | ||
| 560 | + if (k != j) | ||
| 561 | + reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j]; | ||
| 562 | + } | ||
| 563 | + } | ||
| 564 | + reg_state[regno].use_index = k; | ||
| 565 | +} | ||
| 566 | + | ||
| 567 | +/* Find the use of REGNO with the ruid that is highest among those | ||
| 568 | + lower than RUID_LIMIT, and return it if it is the only use of this | ||
| 569 | + reg in the insn. Return NULL otherwise. */ | ||
| 570 | + | ||
| 571 | +static struct reg_use * | ||
| 572 | +reload_combine_closest_single_use (unsigned regno, int ruid_limit) | ||
| 573 | +{ | ||
| 574 | + int i, best_ruid = 0; | ||
| 575 | + int use_idx = reg_state[regno].use_index; | ||
| 576 | + struct reg_use *retval; | ||
| 577 | + | ||
| 578 | + if (use_idx < 0) | ||
| 579 | + return NULL; | ||
| 580 | + retval = NULL; | ||
| 581 | + for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 582 | + { | ||
| 583 | + struct reg_use *use = reg_state[regno].reg_use + i; | ||
| 584 | + int this_ruid = use->ruid; | ||
| 585 | + if (this_ruid >= ruid_limit) | ||
| 586 | + continue; | ||
| 587 | + if (this_ruid > best_ruid) | ||
| 588 | + { | ||
| 589 | + best_ruid = this_ruid; | ||
| 590 | + retval = use; | ||
| 591 | + } | ||
| 592 | + else if (this_ruid == best_ruid) | ||
| 593 | + retval = NULL; | ||
| 594 | + } | ||
| 595 | + if (last_label_ruid >= best_ruid) | ||
| 596 | + return NULL; | ||
| 597 | + return retval; | ||
| 598 | +} | ||
| 599 | + | ||
| 600 | +/* After we've moved an add insn, fix up any debug insns that occur | ||
| 601 | + between the old location of the add and the new location. REG is | ||
| 602 | + the destination register of the add insn; REPLACEMENT is the | ||
| 603 | + SET_SRC of the add. FROM and TO specify the range in which we | ||
| 604 | + should make this change on debug insns. */ | ||
| 605 | + | ||
| 606 | +static void | ||
| 607 | +fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to) | ||
| 608 | +{ | ||
| 609 | + rtx insn; | ||
| 610 | + for (insn = from; insn != to; insn = NEXT_INSN (insn)) | ||
| 611 | + { | ||
| 612 | + rtx t; | ||
| 613 | + | ||
| 614 | + if (!DEBUG_INSN_P (insn)) | ||
| 615 | + continue; | ||
| 616 | + | ||
| 617 | + t = INSN_VAR_LOCATION_LOC (insn); | ||
| 618 | + t = simplify_replace_rtx (t, reg, replacement); | ||
| 619 | + validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0); | ||
| 620 | + } | ||
| 621 | +} | ||
| 622 | + | ||
| 623 | +/* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG | ||
| 624 | + with SRC in the insn described by USE, taking costs into account. Return | ||
| 625 | + true if we made the replacement. */ | ||
| 626 | + | ||
| 627 | +static bool | ||
| 628 | +try_replace_in_use (struct reg_use *use, rtx reg, rtx src) | ||
| 629 | +{ | ||
| 630 | + rtx use_insn = use->insn; | ||
| 631 | + rtx mem = use->containing_mem; | ||
| 632 | + bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); | ||
| 633 | + | ||
| 634 | + if (mem != NULL_RTX) | ||
| 635 | + { | ||
| 636 | + addr_space_t as = MEM_ADDR_SPACE (mem); | ||
| 637 | + rtx oldaddr = XEXP (mem, 0); | ||
| 638 | + rtx newaddr = NULL_RTX; | ||
| 639 | + int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed); | ||
| 640 | + int new_cost; | ||
| 641 | + | ||
| 642 | + newaddr = simplify_replace_rtx (oldaddr, reg, src); | ||
| 643 | + if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as)) | ||
| 644 | + { | ||
| 645 | + XEXP (mem, 0) = newaddr; | ||
| 646 | + new_cost = address_cost (newaddr, GET_MODE (mem), as, speed); | ||
| 647 | + XEXP (mem, 0) = oldaddr; | ||
| 648 | + if (new_cost <= old_cost | ||
| 649 | + && validate_change (use_insn, | ||
| 650 | + &XEXP (mem, 0), newaddr, 0)) | ||
| 651 | + return true; | ||
| 652 | + } | ||
| 653 | + } | ||
| 654 | + else | ||
| 655 | + { | ||
| 656 | + rtx new_set = single_set (use_insn); | ||
| 657 | + if (new_set | ||
| 658 | + && REG_P (SET_DEST (new_set)) | ||
| 659 | + && GET_CODE (SET_SRC (new_set)) == PLUS | ||
| 660 | + && REG_P (XEXP (SET_SRC (new_set), 0)) | ||
| 661 | + && CONSTANT_P (XEXP (SET_SRC (new_set), 1))) | ||
| 662 | + { | ||
| 663 | + rtx new_src; | ||
| 664 | + int old_cost = rtx_cost (SET_SRC (new_set), SET, speed); | ||
| 665 | + | ||
| 666 | + gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg)); | ||
| 667 | + new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src); | ||
| 668 | + | ||
| 669 | + if (rtx_cost (new_src, SET, speed) <= old_cost | ||
| 670 | + && validate_change (use_insn, &SET_SRC (new_set), | ||
| 671 | + new_src, 0)) | ||
| 672 | + return true; | ||
| 673 | + } | ||
| 674 | + } | ||
| 675 | + return false; | ||
| 676 | +} | ||
| 677 | + | ||
| 678 | +/* Called by reload_combine when scanning INSN. This function tries to detect | ||
| 679 | + patterns where a constant is added to a register, and the result is used | ||
| 680 | + in an address. | ||
| 681 | + Return true if no further processing is needed on INSN; false if it wasn't | ||
| 682 | + recognized and should be handled normally. */ | ||
| 683 | + | ||
| 684 | +static bool | ||
| 685 | +reload_combine_recognize_const_pattern (rtx insn) | ||
| 686 | +{ | ||
| 687 | + int from_ruid = reload_combine_ruid; | ||
| 688 | + rtx set, pat, reg, src, addreg; | ||
| 689 | + unsigned int regno; | ||
| 690 | + struct reg_use *use; | ||
| 691 | + bool must_move_add; | ||
| 692 | + rtx add_moved_after_insn = NULL_RTX; | ||
| 693 | + int add_moved_after_ruid = 0; | ||
| 694 | + int clobbered_regno = -1; | ||
| 695 | + | ||
| 696 | + set = single_set (insn); | ||
| 697 | + if (set == NULL_RTX) | ||
| 698 | + return false; | ||
| 699 | + | ||
| 700 | + reg = SET_DEST (set); | ||
| 701 | + src = SET_SRC (set); | ||
| 702 | + if (!REG_P (reg) | ||
| 703 | + || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1 | ||
| 704 | + || GET_MODE (reg) != Pmode | ||
| 705 | + || reg == stack_pointer_rtx) | ||
| 706 | + return false; | ||
| 707 | + | ||
| 708 | + regno = REGNO (reg); | ||
| 709 | + | ||
| 710 | + /* We look for a REG1 = REG2 + CONSTANT insn, followed by either | ||
| 711 | + uses of REG1 inside an address, or inside another add insn. If | ||
| 712 | + possible and profitable, merge the addition into subsequent | ||
| 713 | + uses. */ | ||
| 714 | + if (GET_CODE (src) != PLUS | ||
| 715 | + || !REG_P (XEXP (src, 0)) | ||
| 716 | + || !CONSTANT_P (XEXP (src, 1))) | ||
| 717 | + return false; | ||
| 718 | + | ||
| 719 | + addreg = XEXP (src, 0); | ||
| 720 | + must_move_add = rtx_equal_p (reg, addreg); | ||
| 721 | + | ||
| 722 | + pat = PATTERN (insn); | ||
| 723 | + if (must_move_add && set != pat) | ||
| 724 | + { | ||
| 725 | + /* We have to be careful when moving the add; apart from the | ||
| 726 | + single_set there may also be clobbers. Recognize one special | ||
| 727 | + case, that of one clobber alongside the set (likely a clobber | ||
| 728 | + of the CC register). */ | ||
| 729 | + gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL); | ||
| 730 | + if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set | ||
| 731 | + || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER | ||
| 732 | + || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))) | ||
| 733 | + return false; | ||
| 734 | + clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0)); | ||
| 735 | + } | ||
| 736 | + | ||
| 737 | + do | ||
| 738 | + { | ||
| 739 | + use = reload_combine_closest_single_use (regno, from_ruid); | ||
| 740 | + | ||
| 741 | + if (use) | ||
| 742 | + /* Start the search for the next use from here. */ | ||
| 743 | + from_ruid = use->ruid; | ||
| 744 | + | ||
| 745 | + if (use && GET_MODE (*use->usep) == Pmode) | ||
| 746 | + { | ||
| 747 | + bool delete_add = false; | ||
| 748 | + rtx use_insn = use->insn; | ||
| 749 | + int use_ruid = use->ruid; | ||
| 750 | + | ||
| 751 | + /* Avoid moving the add insn past a jump. */ | ||
| 752 | + if (must_move_add && use_ruid <= last_jump_ruid) | ||
| 753 | + break; | ||
| 754 | + | ||
| 755 | + /* If the add clobbers another hard reg in parallel, don't move | ||
| 756 | + it past a real set of this hard reg. */ | ||
| 757 | + if (must_move_add && clobbered_regno >= 0 | ||
| 758 | + && reg_state[clobbered_regno].real_store_ruid >= use_ruid) | ||
| 759 | + break; | ||
| 760 | + | ||
| 761 | + gcc_assert (reg_state[regno].store_ruid <= use_ruid); | ||
| 762 | + /* Avoid moving a use of ADDREG past a point where it is stored. */ | ||
| 763 | + if (reg_state[REGNO (addreg)].store_ruid > use_ruid) | ||
| 764 | + break; | ||
| 765 | + | ||
| 766 | + /* We also must not move the addition past an insn that sets | ||
| 767 | + the same register, unless we can combine two add insns. */ | ||
| 768 | + if (must_move_add && reg_state[regno].store_ruid == use_ruid) | ||
| 769 | + { | ||
| 770 | + if (use->containing_mem == NULL_RTX) | ||
| 771 | + delete_add = true; | ||
| 772 | + else | ||
| 773 | + break; | ||
| 774 | + } | ||
| 775 | + | ||
| 776 | + if (try_replace_in_use (use, reg, src)) | ||
| 777 | + { | ||
| 778 | + reload_combine_purge_insn_uses (use_insn); | ||
| 779 | + reload_combine_note_use (&PATTERN (use_insn), use_insn, | ||
| 780 | + use_ruid, NULL_RTX); | ||
| 781 | + | ||
| 782 | + if (delete_add) | ||
| 783 | + { | ||
| 784 | + fixup_debug_insns (reg, src, insn, use_insn); | ||
| 785 | + delete_insn (insn); | ||
| 786 | + return true; | ||
| 787 | + } | ||
| 788 | + if (must_move_add) | ||
| 789 | + { | ||
| 790 | + add_moved_after_insn = use_insn; | ||
| 791 | + add_moved_after_ruid = use_ruid; | ||
| 792 | + } | ||
| 793 | + continue; | ||
| 794 | + } | ||
| 795 | + } | ||
| 796 | + /* If we get here, we couldn't handle this use. */ | ||
| 797 | + if (must_move_add) | ||
| 798 | + break; | ||
| 799 | + } | ||
| 800 | + while (use); | ||
| 801 | + | ||
| 802 | + if (!must_move_add || add_moved_after_insn == NULL_RTX) | ||
| 803 | + /* Process the add normally. */ | ||
| 804 | + return false; | ||
| 805 | + | ||
| 806 | + fixup_debug_insns (reg, src, insn, add_moved_after_insn); | ||
| 807 | + | ||
| 808 | + reorder_insns (insn, insn, add_moved_after_insn); | ||
| 809 | + reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid); | ||
| 810 | + reload_combine_split_ruids (add_moved_after_ruid - 1); | ||
| 811 | + reload_combine_note_use (&PATTERN (insn), insn, | ||
| 812 | + add_moved_after_ruid, NULL_RTX); | ||
| 813 | + reg_state[regno].store_ruid = add_moved_after_ruid; | ||
| 814 | + | ||
| 815 | + return true; | ||
| 816 | +} | ||
| 817 | + | ||
| 818 | +/* Called by reload_combine when scanning INSN. Try to detect a pattern we | ||
| 819 | + can handle and improve. Return true if no further processing is needed on | ||
| 820 | + INSN; false if it wasn't recognized and should be handled normally. */ | ||
| 821 | + | ||
| 822 | +static bool | ||
| 823 | +reload_combine_recognize_pattern (rtx insn) | ||
| 824 | +{ | ||
| 825 | + rtx set, reg, src; | ||
| 826 | + unsigned int regno; | ||
| 827 | + | ||
| 828 | + set = single_set (insn); | ||
| 829 | + if (set == NULL_RTX) | ||
| 830 | + return false; | ||
| 831 | + | ||
| 832 | + reg = SET_DEST (set); | ||
| 833 | + src = SET_SRC (set); | ||
| 834 | + if (!REG_P (reg) | ||
| 835 | + || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1) | ||
| 836 | + return false; | ||
| 837 | + | ||
| 838 | + regno = REGNO (reg); | ||
| 839 | + | ||
| 840 | + /* Look for (set (REGX) (CONST_INT)) | ||
| 841 | + (set (REGX) (PLUS (REGX) (REGY))) | ||
| 842 | + ... | ||
| 843 | + ... (MEM (REGX)) ... | ||
| 844 | + and convert it to | ||
| 845 | + (set (REGZ) (CONST_INT)) | ||
| 846 | + ... | ||
| 847 | + ... (MEM (PLUS (REGZ) (REGY)))... . | ||
| 848 | + | ||
| 849 | + First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | ||
| 850 | + and that we know all uses of REGX before it dies. | ||
| 851 | + Also, explicitly check that REGX != REGY; our life information | ||
| 852 | + does not yet show whether REGY changes in this insn. */ | ||
| 853 | + | ||
| 854 | + if (GET_CODE (src) == PLUS | ||
| 855 | + && reg_state[regno].all_offsets_match | ||
| 856 | + && last_index_reg != -1 | ||
| 857 | + && REG_P (XEXP (src, 1)) | ||
| 858 | + && rtx_equal_p (XEXP (src, 0), reg) | ||
| 859 | + && !rtx_equal_p (XEXP (src, 1), reg) | ||
| 860 | + && reg_state[regno].use_index >= 0 | ||
| 861 | + && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES | ||
| 862 | + && last_label_ruid < reg_state[regno].use_ruid) | ||
| 863 | + { | ||
| 864 | + rtx base = XEXP (src, 1); | ||
| 865 | + rtx prev = prev_nonnote_insn (insn); | ||
| 866 | + rtx prev_set = prev ? single_set (prev) : NULL_RTX; | ||
| 867 | + rtx index_reg = NULL_RTX; | ||
| 868 | + rtx reg_sum = NULL_RTX; | ||
| 869 | + int i; | ||
| 870 | + | ||
| 871 | + /* Now we need to set INDEX_REG to an index register (denoted as | ||
| 872 | + REGZ in the illustration above) and REG_SUM to the expression | ||
| 873 | + register+register that we want to use to substitute uses of REG | ||
| 874 | + (typically in MEMs) with. First check REG and BASE for being | ||
| 875 | + index registers; we can use them even if they are not dead. */ | ||
| 876 | + if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | ||
| 877 | + || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | ||
| 878 | + REGNO (base))) | ||
| 879 | + { | ||
| 880 | + index_reg = reg; | ||
| 881 | + reg_sum = src; | ||
| 882 | + } | ||
| 883 | + else | ||
| 884 | + { | ||
| 885 | + /* Otherwise, look for a free index register. Since we have | ||
| 886 | + checked above that neither REG nor BASE are index registers, | ||
| 887 | + if we find anything at all, it will be different from these | ||
| 888 | + two registers. */ | ||
| 889 | + for (i = first_index_reg; i <= last_index_reg; i++) | ||
| 890 | + { | ||
| 891 | + if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) | ||
| 892 | + && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | ||
| 893 | + && reg_state[i].store_ruid <= reg_state[regno].use_ruid | ||
| 894 | + && (call_used_regs[i] || df_regs_ever_live_p (i)) | ||
| 895 | + && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM) | ||
| 896 | + && !fixed_regs[i] && !global_regs[i] | ||
| 897 | + && hard_regno_nregs[i][GET_MODE (reg)] == 1 | ||
| 898 | + && targetm.hard_regno_scratch_ok (i)) | ||
| 899 | + { | ||
| 900 | + index_reg = gen_rtx_REG (GET_MODE (reg), i); | ||
| 901 | + reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | ||
| 902 | + break; | ||
| 903 | + } | ||
| 904 | + } | ||
| 905 | + } | ||
| 906 | + | ||
| 907 | + /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that | ||
| 908 | + (REGY), i.e. BASE, is not clobbered before the last use we'll | ||
| 909 | + create. */ | ||
| 910 | + if (reg_sum | ||
| 911 | + && prev_set | ||
| 912 | + && CONST_INT_P (SET_SRC (prev_set)) | ||
| 913 | + && rtx_equal_p (SET_DEST (prev_set), reg) | ||
| 914 | + && (reg_state[REGNO (base)].store_ruid | ||
| 915 | + <= reg_state[regno].use_ruid)) | ||
| 916 | + { | ||
| 917 | + /* Change destination register and, if necessary, the constant | ||
| 918 | + value in PREV, the constant loading instruction. */ | ||
| 919 | + validate_change (prev, &SET_DEST (prev_set), index_reg, 1); | ||
| 920 | + if (reg_state[regno].offset != const0_rtx) | ||
| 921 | + validate_change (prev, | ||
| 922 | + &SET_SRC (prev_set), | ||
| 923 | + GEN_INT (INTVAL (SET_SRC (prev_set)) | ||
| 924 | + + INTVAL (reg_state[regno].offset)), | ||
| 925 | + 1); | ||
| 926 | + | ||
| 927 | + /* Now for every use of REG that we have recorded, replace REG | ||
| 928 | + with REG_SUM. */ | ||
| 929 | + for (i = reg_state[regno].use_index; | ||
| 930 | + i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 931 | + validate_unshare_change (reg_state[regno].reg_use[i].insn, | ||
| 932 | + reg_state[regno].reg_use[i].usep, | ||
| 933 | + /* Each change must have its own | ||
| 934 | + replacement. */ | ||
| 935 | + reg_sum, 1); | ||
| 936 | + | ||
| 937 | + if (apply_change_group ()) | ||
| 938 | + { | ||
| 939 | + struct reg_use *lowest_ruid = NULL; | ||
| 940 | + | ||
| 941 | + /* For every new use of REG_SUM, we have to record the use | ||
| 942 | + of BASE therein, i.e. operand 1. */ | ||
| 943 | + for (i = reg_state[regno].use_index; | ||
| 944 | + i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 945 | + { | ||
| 946 | + struct reg_use *use = reg_state[regno].reg_use + i; | ||
| 947 | + reload_combine_note_use (&XEXP (*use->usep, 1), use->insn, | ||
| 948 | + use->ruid, use->containing_mem); | ||
| 949 | + if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid) | ||
| 950 | + lowest_ruid = use; | ||
| 951 | + } | ||
| 952 | + | ||
| 953 | + fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn); | ||
| 954 | + | ||
| 955 | + /* Delete the reg-reg addition. */ | ||
| 956 | + delete_insn (insn); | ||
| 957 | + | ||
| 958 | + if (reg_state[regno].offset != const0_rtx) | ||
| 959 | + /* Previous REG_EQUIV / REG_EQUAL notes for PREV | ||
| 960 | + are now invalid. */ | ||
| 961 | + remove_reg_equal_equiv_notes (prev); | ||
| 962 | + | ||
| 963 | + reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 964 | + return true; | ||
| 965 | + } | ||
| 966 | + } | ||
| 967 | + } | ||
| 968 | + return false; | ||
| 969 | +} | ||
| 970 | + | ||
| 971 | static void | ||
| 972 | reload_combine (void) | ||
| 973 | { | ||
| 974 | - rtx insn, set; | ||
| 975 | - int first_index_reg = -1; | ||
| 976 | - int last_index_reg = 0; | ||
| 977 | + rtx insn, prev; | ||
| 978 | int i; | ||
| 979 | basic_block bb; | ||
| 980 | unsigned int r; | ||
| 981 | - int last_label_ruid; | ||
| 982 | int min_labelno, n_labels; | ||
| 983 | HARD_REG_SET ever_live_at_start, *label_live; | ||
| 984 | |||
| 985 | - /* If reg+reg can be used in offsetable memory addresses, the main chunk of | ||
| 986 | - reload has already used it where appropriate, so there is no use in | ||
| 987 | - trying to generate it now. */ | ||
| 988 | - if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS) | ||
| 989 | - return; | ||
| 990 | - | ||
| 991 | /* To avoid wasting too much time later searching for an index register, | ||
| 992 | determine the minimum and maximum index register numbers. */ | ||
| 993 | - for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | ||
| 994 | - if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | ||
| 995 | - { | ||
| 996 | - if (first_index_reg == -1) | ||
| 997 | - first_index_reg = r; | ||
| 998 | - | ||
| 999 | - last_index_reg = r; | ||
| 1000 | - } | ||
| 1001 | - | ||
| 1002 | - /* If no index register is available, we can quit now. */ | ||
| 1003 | - if (first_index_reg == -1) | ||
| 1004 | - return; | ||
| 1005 | + if (INDEX_REG_CLASS == NO_REGS) | ||
| 1006 | + last_index_reg = -1; | ||
| 1007 | + else if (first_index_reg == -1 && last_index_reg == 0) | ||
| 1008 | + { | ||
| 1009 | + for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | ||
| 1010 | + if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | ||
| 1011 | + { | ||
| 1012 | + if (first_index_reg == -1) | ||
| 1013 | + first_index_reg = r; | ||
| 1014 | + | ||
| 1015 | + last_index_reg = r; | ||
| 1016 | + } | ||
| 1017 | + | ||
| 1018 | + /* If no index register is available, we can quit now. Set LAST_INDEX_REG | ||
| 1019 | + to -1 so we'll know to quit early the next time we get here. */ | ||
| 1020 | + if (first_index_reg == -1) | ||
| 1021 | + { | ||
| 1022 | + last_index_reg = -1; | ||
| 1023 | + return; | ||
| 1024 | + } | ||
| 1025 | + } | ||
| 1026 | |||
| 1027 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime | ||
| 1028 | information is a bit fuzzy immediately after reload, but it's | ||
| 1029 | @@ -753,20 +1278,23 @@ | ||
| 1030 | } | ||
| 1031 | |||
| 1032 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ | ||
| 1033 | - last_label_ruid = reload_combine_ruid = 0; | ||
| 1034 | + last_label_ruid = last_jump_ruid = reload_combine_ruid = 0; | ||
| 1035 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | ||
| 1036 | { | ||
| 1037 | - reg_state[r].store_ruid = reload_combine_ruid; | ||
| 1038 | + reg_state[r].store_ruid = 0; | ||
| 1039 | + reg_state[r].real_store_ruid = 0; | ||
| 1040 | if (fixed_regs[r]) | ||
| 1041 | reg_state[r].use_index = -1; | ||
| 1042 | else | ||
| 1043 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 1044 | } | ||
| 1045 | |||
| 1046 | - for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | ||
| 1047 | + for (insn = get_last_insn (); insn; insn = prev) | ||
| 1048 | { | ||
| 1049 | rtx note; | ||
| 1050 | |||
| 1051 | + prev = PREV_INSN (insn); | ||
| 1052 | + | ||
| 1053 | /* We cannot do our optimization across labels. Invalidating all the use | ||
| 1054 | information we have would be costly, so we just note where the label | ||
| 1055 | is and then later disable any optimization that would cross it. */ | ||
| 1056 | @@ -777,141 +1305,17 @@ | ||
| 1057 | if (! fixed_regs[r]) | ||
| 1058 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 1059 | |||
| 1060 | - if (! INSN_P (insn)) | ||
| 1061 | + if (! NONDEBUG_INSN_P (insn)) | ||
| 1062 | continue; | ||
| 1063 | |||
| 1064 | reload_combine_ruid++; | ||
| 1065 | |||
| 1066 | - /* Look for (set (REGX) (CONST_INT)) | ||
| 1067 | - (set (REGX) (PLUS (REGX) (REGY))) | ||
| 1068 | - ... | ||
| 1069 | - ... (MEM (REGX)) ... | ||
| 1070 | - and convert it to | ||
| 1071 | - (set (REGZ) (CONST_INT)) | ||
| 1072 | - ... | ||
| 1073 | - ... (MEM (PLUS (REGZ) (REGY)))... . | ||
| 1074 | - | ||
| 1075 | - First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | ||
| 1076 | - and that we know all uses of REGX before it dies. | ||
| 1077 | - Also, explicitly check that REGX != REGY; our life information | ||
| 1078 | - does not yet show whether REGY changes in this insn. */ | ||
| 1079 | - set = single_set (insn); | ||
| 1080 | - if (set != NULL_RTX | ||
| 1081 | - && REG_P (SET_DEST (set)) | ||
| 1082 | - && (hard_regno_nregs[REGNO (SET_DEST (set))] | ||
| 1083 | - [GET_MODE (SET_DEST (set))] | ||
| 1084 | - == 1) | ||
| 1085 | - && GET_CODE (SET_SRC (set)) == PLUS | ||
| 1086 | - && REG_P (XEXP (SET_SRC (set), 1)) | ||
| 1087 | - && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set)) | ||
| 1088 | - && !rtx_equal_p (XEXP (SET_SRC (set), 1), SET_DEST (set)) | ||
| 1089 | - && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid) | ||
| 1090 | - { | ||
| 1091 | - rtx reg = SET_DEST (set); | ||
| 1092 | - rtx plus = SET_SRC (set); | ||
| 1093 | - rtx base = XEXP (plus, 1); | ||
| 1094 | - rtx prev = prev_nonnote_nondebug_insn (insn); | ||
| 1095 | - rtx prev_set = prev ? single_set (prev) : NULL_RTX; | ||
| 1096 | - unsigned int regno = REGNO (reg); | ||
| 1097 | - rtx index_reg = NULL_RTX; | ||
| 1098 | - rtx reg_sum = NULL_RTX; | ||
| 1099 | - | ||
| 1100 | - /* Now we need to set INDEX_REG to an index register (denoted as | ||
| 1101 | - REGZ in the illustration above) and REG_SUM to the expression | ||
| 1102 | - register+register that we want to use to substitute uses of REG | ||
| 1103 | - (typically in MEMs) with. First check REG and BASE for being | ||
| 1104 | - index registers; we can use them even if they are not dead. */ | ||
| 1105 | - if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | ||
| 1106 | - || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | ||
| 1107 | - REGNO (base))) | ||
| 1108 | - { | ||
| 1109 | - index_reg = reg; | ||
| 1110 | - reg_sum = plus; | ||
| 1111 | - } | ||
| 1112 | - else | ||
| 1113 | - { | ||
| 1114 | - /* Otherwise, look for a free index register. Since we have | ||
| 1115 | - checked above that neither REG nor BASE are index registers, | ||
| 1116 | - if we find anything at all, it will be different from these | ||
| 1117 | - two registers. */ | ||
| 1118 | - for (i = first_index_reg; i <= last_index_reg; i++) | ||
| 1119 | - { | ||
| 1120 | - if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | ||
| 1121 | - i) | ||
| 1122 | - && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | ||
| 1123 | - && reg_state[i].store_ruid <= reg_state[regno].use_ruid | ||
| 1124 | - && hard_regno_nregs[i][GET_MODE (reg)] == 1) | ||
| 1125 | - { | ||
| 1126 | - index_reg = gen_rtx_REG (GET_MODE (reg), i); | ||
| 1127 | - reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | ||
| 1128 | - break; | ||
| 1129 | - } | ||
| 1130 | - } | ||
| 1131 | - } | ||
| 1132 | - | ||
| 1133 | - /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that | ||
| 1134 | - (REGY), i.e. BASE, is not clobbered before the last use we'll | ||
| 1135 | - create. */ | ||
| 1136 | - if (reg_sum | ||
| 1137 | - && prev_set | ||
| 1138 | - && CONST_INT_P (SET_SRC (prev_set)) | ||
| 1139 | - && rtx_equal_p (SET_DEST (prev_set), reg) | ||
| 1140 | - && reg_state[regno].use_index >= 0 | ||
| 1141 | - && (reg_state[REGNO (base)].store_ruid | ||
| 1142 | - <= reg_state[regno].use_ruid)) | ||
| 1143 | - { | ||
| 1144 | - int i; | ||
| 1145 | - | ||
| 1146 | - /* Change destination register and, if necessary, the constant | ||
| 1147 | - value in PREV, the constant loading instruction. */ | ||
| 1148 | - validate_change (prev, &SET_DEST (prev_set), index_reg, 1); | ||
| 1149 | - if (reg_state[regno].offset != const0_rtx) | ||
| 1150 | - validate_change (prev, | ||
| 1151 | - &SET_SRC (prev_set), | ||
| 1152 | - GEN_INT (INTVAL (SET_SRC (prev_set)) | ||
| 1153 | - + INTVAL (reg_state[regno].offset)), | ||
| 1154 | - 1); | ||
| 1155 | - | ||
| 1156 | - /* Now for every use of REG that we have recorded, replace REG | ||
| 1157 | - with REG_SUM. */ | ||
| 1158 | - for (i = reg_state[regno].use_index; | ||
| 1159 | - i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 1160 | - validate_unshare_change (reg_state[regno].reg_use[i].insn, | ||
| 1161 | - reg_state[regno].reg_use[i].usep, | ||
| 1162 | - /* Each change must have its own | ||
| 1163 | - replacement. */ | ||
| 1164 | - reg_sum, 1); | ||
| 1165 | - | ||
| 1166 | - if (apply_change_group ()) | ||
| 1167 | - { | ||
| 1168 | - /* For every new use of REG_SUM, we have to record the use | ||
| 1169 | - of BASE therein, i.e. operand 1. */ | ||
| 1170 | - for (i = reg_state[regno].use_index; | ||
| 1171 | - i < RELOAD_COMBINE_MAX_USES; i++) | ||
| 1172 | - reload_combine_note_use | ||
| 1173 | - (&XEXP (*reg_state[regno].reg_use[i].usep, 1), | ||
| 1174 | - reg_state[regno].reg_use[i].insn); | ||
| 1175 | - | ||
| 1176 | - if (reg_state[REGNO (base)].use_ruid | ||
| 1177 | - > reg_state[regno].use_ruid) | ||
| 1178 | - reg_state[REGNO (base)].use_ruid | ||
| 1179 | - = reg_state[regno].use_ruid; | ||
| 1180 | - | ||
| 1181 | - /* Delete the reg-reg addition. */ | ||
| 1182 | - delete_insn (insn); | ||
| 1183 | - | ||
| 1184 | - if (reg_state[regno].offset != const0_rtx) | ||
| 1185 | - /* Previous REG_EQUIV / REG_EQUAL notes for PREV | ||
| 1186 | - are now invalid. */ | ||
| 1187 | - remove_reg_equal_equiv_notes (prev); | ||
| 1188 | - | ||
| 1189 | - reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 1190 | - reg_state[REGNO (index_reg)].store_ruid | ||
| 1191 | - = reload_combine_ruid; | ||
| 1192 | - continue; | ||
| 1193 | - } | ||
| 1194 | - } | ||
| 1195 | - } | ||
| 1196 | + if (control_flow_insn_p (insn)) | ||
| 1197 | + last_jump_ruid = reload_combine_ruid; | ||
| 1198 | + | ||
| 1199 | + if (reload_combine_recognize_const_pattern (insn) | ||
| 1200 | + || reload_combine_recognize_pattern (insn)) | ||
| 1201 | + continue; | ||
| 1202 | |||
| 1203 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); | ||
| 1204 | |||
| 1205 | @@ -967,7 +1371,8 @@ | ||
| 1206 | reg_state[i].use_index = -1; | ||
| 1207 | } | ||
| 1208 | |||
| 1209 | - reload_combine_note_use (&PATTERN (insn), insn); | ||
| 1210 | + reload_combine_note_use (&PATTERN (insn), insn, | ||
| 1211 | + reload_combine_ruid, NULL_RTX); | ||
| 1212 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | ||
| 1213 | { | ||
| 1214 | if (REG_NOTE_KIND (note) == REG_INC | ||
| 1215 | @@ -976,6 +1381,7 @@ | ||
| 1216 | int regno = REGNO (XEXP (note, 0)); | ||
| 1217 | |||
| 1218 | reg_state[regno].store_ruid = reload_combine_ruid; | ||
| 1219 | + reg_state[regno].real_store_ruid = reload_combine_ruid; | ||
| 1220 | reg_state[regno].use_index = -1; | ||
| 1221 | } | ||
| 1222 | } | ||
| 1223 | @@ -985,8 +1391,8 @@ | ||
| 1224 | } | ||
| 1225 | |||
| 1226 | /* Check if DST is a register or a subreg of a register; if it is, | ||
| 1227 | - update reg_state[regno].store_ruid and reg_state[regno].use_index | ||
| 1228 | - accordingly. Called via note_stores from reload_combine. */ | ||
| 1229 | + update store_ruid, real_store_ruid and use_index in the reg_state | ||
| 1230 | + structure accordingly. Called via note_stores from reload_combine. */ | ||
| 1231 | |||
| 1232 | static void | ||
| 1233 | reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) | ||
| 1234 | @@ -1010,14 +1416,14 @@ | ||
| 1235 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be | ||
| 1236 | careful with registers / register parts that are not full words. | ||
| 1237 | Similarly for ZERO_EXTRACT. */ | ||
| 1238 | - if (GET_CODE (set) != SET | ||
| 1239 | - || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT | ||
| 1240 | + if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT | ||
| 1241 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) | ||
| 1242 | { | ||
| 1243 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) | ||
| 1244 | { | ||
| 1245 | reg_state[i].use_index = -1; | ||
| 1246 | reg_state[i].store_ruid = reload_combine_ruid; | ||
| 1247 | + reg_state[i].real_store_ruid = reload_combine_ruid; | ||
| 1248 | } | ||
| 1249 | } | ||
| 1250 | else | ||
| 1251 | @@ -1025,6 +1431,8 @@ | ||
| 1252 | for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) | ||
| 1253 | { | ||
| 1254 | reg_state[i].store_ruid = reload_combine_ruid; | ||
| 1255 | + if (GET_CODE (set) == SET) | ||
| 1256 | + reg_state[i].real_store_ruid = reload_combine_ruid; | ||
| 1257 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | ||
| 1258 | } | ||
| 1259 | } | ||
| 1260 | @@ -1035,7 +1443,7 @@ | ||
| 1261 | *XP is the pattern of INSN, or a part of it. | ||
| 1262 | Called from reload_combine, and recursively by itself. */ | ||
| 1263 | static void | ||
| 1264 | -reload_combine_note_use (rtx *xp, rtx insn) | ||
| 1265 | +reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem) | ||
| 1266 | { | ||
| 1267 | rtx x = *xp; | ||
| 1268 | enum rtx_code code = x->code; | ||
| 1269 | @@ -1048,7 +1456,7 @@ | ||
| 1270 | case SET: | ||
| 1271 | if (REG_P (SET_DEST (x))) | ||
| 1272 | { | ||
| 1273 | - reload_combine_note_use (&SET_SRC (x), insn); | ||
| 1274 | + reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX); | ||
| 1275 | return; | ||
| 1276 | } | ||
| 1277 | break; | ||
| 1278 | @@ -1104,6 +1512,11 @@ | ||
| 1279 | return; | ||
| 1280 | } | ||
| 1281 | |||
| 1282 | + /* We may be called to update uses in previously seen insns. | ||
| 1283 | + Don't add uses beyond the last store we saw. */ | ||
| 1284 | + if (ruid < reg_state[regno].store_ruid) | ||
| 1285 | + return; | ||
| 1286 | + | ||
| 1287 | /* If this register is already used in some unknown fashion, we | ||
| 1288 | can't do anything. | ||
| 1289 | If we decrement the index from zero to -1, we can't store more | ||
| 1290 | @@ -1112,29 +1525,34 @@ | ||
| 1291 | if (use_index < 0) | ||
| 1292 | return; | ||
| 1293 | |||
| 1294 | - if (use_index != RELOAD_COMBINE_MAX_USES - 1) | ||
| 1295 | - { | ||
| 1296 | - /* We have found another use for a register that is already | ||
| 1297 | - used later. Check if the offsets match; if not, mark the | ||
| 1298 | - register as used in an unknown fashion. */ | ||
| 1299 | - if (! rtx_equal_p (offset, reg_state[regno].offset)) | ||
| 1300 | - { | ||
| 1301 | - reg_state[regno].use_index = -1; | ||
| 1302 | - return; | ||
| 1303 | - } | ||
| 1304 | - } | ||
| 1305 | - else | ||
| 1306 | + if (use_index == RELOAD_COMBINE_MAX_USES - 1) | ||
| 1307 | { | ||
| 1308 | /* This is the first use of this register we have seen since we | ||
| 1309 | marked it as dead. */ | ||
| 1310 | reg_state[regno].offset = offset; | ||
| 1311 | - reg_state[regno].use_ruid = reload_combine_ruid; | ||
| 1312 | - } | ||
| 1313 | + reg_state[regno].all_offsets_match = true; | ||
| 1314 | + reg_state[regno].use_ruid = ruid; | ||
| 1315 | + } | ||
| 1316 | + else | ||
| 1317 | + { | ||
| 1318 | + if (reg_state[regno].use_ruid > ruid) | ||
| 1319 | + reg_state[regno].use_ruid = ruid; | ||
| 1320 | + | ||
| 1321 | + if (! rtx_equal_p (offset, reg_state[regno].offset)) | ||
| 1322 | + reg_state[regno].all_offsets_match = false; | ||
| 1323 | + } | ||
| 1324 | + | ||
| 1325 | reg_state[regno].reg_use[use_index].insn = insn; | ||
| 1326 | + reg_state[regno].reg_use[use_index].ruid = ruid; | ||
| 1327 | + reg_state[regno].reg_use[use_index].containing_mem = containing_mem; | ||
| 1328 | reg_state[regno].reg_use[use_index].usep = xp; | ||
| 1329 | return; | ||
| 1330 | } | ||
| 1331 | |||
| 1332 | + case MEM: | ||
| 1333 | + containing_mem = x; | ||
| 1334 | + break; | ||
| 1335 | + | ||
| 1336 | default: | ||
| 1337 | break; | ||
| 1338 | } | ||
| 1339 | @@ -1144,11 +1562,12 @@ | ||
| 1340 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | ||
| 1341 | { | ||
| 1342 | if (fmt[i] == 'e') | ||
| 1343 | - reload_combine_note_use (&XEXP (x, i), insn); | ||
| 1344 | + reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem); | ||
| 1345 | else if (fmt[i] == 'E') | ||
| 1346 | { | ||
| 1347 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | ||
| 1348 | - reload_combine_note_use (&XVECEXP (x, i, j), insn); | ||
| 1349 | + reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid, | ||
| 1350 | + containing_mem); | ||
| 1351 | } | ||
| 1352 | } | ||
| 1353 | } | ||
| 1354 | @@ -1196,9 +1615,10 @@ | ||
| 1355 | while REG is known to already have value (SYM + offset). | ||
| 1356 | This function tries to change INSN into an add instruction | ||
| 1357 | (set (REG) (plus (REG) (OFF - offset))) using the known value. | ||
| 1358 | - It also updates the information about REG's known value. */ | ||
| 1359 | + It also updates the information about REG's known value. | ||
| 1360 | + Return true if we made a change. */ | ||
| 1361 | |||
| 1362 | -static void | ||
| 1363 | +static bool | ||
| 1364 | move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn) | ||
| 1365 | { | ||
| 1366 | rtx pat = PATTERN (insn); | ||
| 1367 | @@ -1207,6 +1627,7 @@ | ||
| 1368 | rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno], | ||
| 1369 | GET_MODE (reg)); | ||
| 1370 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | ||
| 1371 | + bool changed = false; | ||
| 1372 | |||
| 1373 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; | ||
| 1374 | use (set (reg) (reg)) instead. | ||
| 1375 | @@ -1221,13 +1642,13 @@ | ||
| 1376 | (reg)), would be discarded. Maybe we should | ||
| 1377 | try a truncMN pattern? */ | ||
| 1378 | if (INTVAL (off) == reg_offset [regno]) | ||
| 1379 | - validate_change (insn, &SET_SRC (pat), reg, 0); | ||
| 1380 | + changed = validate_change (insn, &SET_SRC (pat), reg, 0); | ||
| 1381 | } | ||
| 1382 | else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed) | ||
| 1383 | && have_add2_insn (reg, new_src)) | ||
| 1384 | { | ||
| 1385 | rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); | ||
| 1386 | - validate_change (insn, &SET_SRC (pat), tem, 0); | ||
| 1387 | + changed = validate_change (insn, &SET_SRC (pat), tem, 0); | ||
| 1388 | } | ||
| 1389 | else if (sym == NULL_RTX && GET_MODE (reg) != BImode) | ||
| 1390 | { | ||
| 1391 | @@ -1252,8 +1673,9 @@ | ||
| 1392 | gen_rtx_STRICT_LOW_PART (VOIDmode, | ||
| 1393 | narrow_reg), | ||
| 1394 | narrow_src); | ||
| 1395 | - if (validate_change (insn, &PATTERN (insn), | ||
| 1396 | - new_set, 0)) | ||
| 1397 | + changed = validate_change (insn, &PATTERN (insn), | ||
| 1398 | + new_set, 0); | ||
| 1399 | + if (changed) | ||
| 1400 | break; | ||
| 1401 | } | ||
| 1402 | } | ||
| 1403 | @@ -1263,6 +1685,7 @@ | ||
| 1404 | reg_mode[regno] = GET_MODE (reg); | ||
| 1405 | reg_symbol_ref[regno] = sym; | ||
| 1406 | reg_offset[regno] = INTVAL (off); | ||
| 1407 | + return changed; | ||
| 1408 | } | ||
| 1409 | |||
| 1410 | |||
| 1411 | @@ -1272,9 +1695,10 @@ | ||
| 1412 | value (SYM + offset) and change INSN into an add instruction | ||
| 1413 | (set (REG) (plus (the found register) (OFF - offset))) if such | ||
| 1414 | a register is found. It also updates the information about | ||
| 1415 | - REG's known value. */ | ||
| 1416 | + REG's known value. | ||
| 1417 | + Return true iff we made a change. */ | ||
| 1418 | |||
| 1419 | -static void | ||
| 1420 | +static bool | ||
| 1421 | move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn) | ||
| 1422 | { | ||
| 1423 | rtx pat = PATTERN (insn); | ||
| 1424 | @@ -1284,6 +1708,7 @@ | ||
| 1425 | int min_regno; | ||
| 1426 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | ||
| 1427 | int i; | ||
| 1428 | + bool changed = false; | ||
| 1429 | |||
| 1430 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | ||
| 1431 | if (reg_set_luid[i] > move2add_last_label_luid | ||
| 1432 | @@ -1328,20 +1753,25 @@ | ||
| 1433 | GET_MODE (reg)); | ||
| 1434 | tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); | ||
| 1435 | } | ||
| 1436 | - validate_change (insn, &SET_SRC (pat), tem, 0); | ||
| 1437 | + if (validate_change (insn, &SET_SRC (pat), tem, 0)) | ||
| 1438 | + changed = true; | ||
| 1439 | } | ||
| 1440 | reg_set_luid[regno] = move2add_luid; | ||
| 1441 | reg_base_reg[regno] = -1; | ||
| 1442 | reg_mode[regno] = GET_MODE (reg); | ||
| 1443 | reg_symbol_ref[regno] = sym; | ||
| 1444 | reg_offset[regno] = INTVAL (off); | ||
| 1445 | + return changed; | ||
| 1446 | } | ||
| 1447 | |||
| 1448 | -static void | ||
| 1449 | +/* Convert move insns with constant inputs to additions if they are cheaper. | ||
| 1450 | + Return true if any changes were made. */ | ||
| 1451 | +static bool | ||
| 1452 | reload_cse_move2add (rtx first) | ||
| 1453 | { | ||
| 1454 | int i; | ||
| 1455 | rtx insn; | ||
| 1456 | + bool changed = false; | ||
| 1457 | |||
| 1458 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | ||
| 1459 | { | ||
| 1460 | @@ -1402,7 +1832,7 @@ | ||
| 1461 | && reg_base_reg[regno] < 0 | ||
| 1462 | && reg_symbol_ref[regno] == NULL_RTX) | ||
| 1463 | { | ||
| 1464 | - move2add_use_add2_insn (reg, NULL_RTX, src, insn); | ||
| 1465 | + changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn); | ||
| 1466 | continue; | ||
| 1467 | } | ||
| 1468 | |||
| 1469 | @@ -1463,6 +1893,7 @@ | ||
| 1470 | } | ||
| 1471 | if (success) | ||
| 1472 | delete_insn (insn); | ||
| 1473 | + changed |= success; | ||
| 1474 | insn = next; | ||
| 1475 | reg_mode[regno] = GET_MODE (reg); | ||
| 1476 | reg_offset[regno] = | ||
| 1477 | @@ -1508,12 +1939,12 @@ | ||
| 1478 | && reg_base_reg[regno] < 0 | ||
| 1479 | && reg_symbol_ref[regno] != NULL_RTX | ||
| 1480 | && rtx_equal_p (sym, reg_symbol_ref[regno])) | ||
| 1481 | - move2add_use_add2_insn (reg, sym, off, insn); | ||
| 1482 | + changed |= move2add_use_add2_insn (reg, sym, off, insn); | ||
| 1483 | |||
| 1484 | /* Otherwise, we have to find a register whose value is sum | ||
| 1485 | of sym and some constant value. */ | ||
| 1486 | else | ||
| 1487 | - move2add_use_add3_insn (reg, sym, off, insn); | ||
| 1488 | + changed |= move2add_use_add3_insn (reg, sym, off, insn); | ||
| 1489 | |||
| 1490 | continue; | ||
| 1491 | } | ||
| 1492 | @@ -1568,6 +1999,7 @@ | ||
| 1493 | } | ||
| 1494 | } | ||
| 1495 | } | ||
| 1496 | + return changed; | ||
| 1497 | } | ||
| 1498 | |||
| 1499 | /* SET is a SET or CLOBBER that sets DST. DATA is the insn which | ||
| 1500 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99440.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99440.patch deleted file mode 100644 index b7a28de65..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99440.patch +++ /dev/null | |||
| @@ -1,78 +0,0 @@ | |||
| 1 | 2010-11-24 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | 2010-07-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | ||
| 4 | |||
| 5 | PR bootstrap/44768 | ||
| 6 | |||
| 7 | * cfgexpand.c (estimated_stack_frame_size): Make self-contained | ||
| 8 | with respect to current_function_decl. Pass decl of the function. | ||
| 9 | * tree-inline.h (estimated_stack_frame_size): Adjust prototype. | ||
| 10 | * ipa-inline.c (compute_inline_parameters): Pass decl to | ||
| 11 | estimated_stack_frame_size. | ||
| 12 | |||
| 13 | === modified file 'gcc/cfgexpand.c' | ||
| 14 | --- old/gcc/cfgexpand.c 2010-10-04 00:50:43 +0000 | ||
| 15 | +++ new/gcc/cfgexpand.c 2010-11-24 08:43:48 +0000 | ||
| 16 | @@ -1248,8 +1248,8 @@ | ||
| 17 | stack_vars_alloc = stack_vars_num = 0; | ||
| 18 | } | ||
| 19 | |||
| 20 | -/* Make a fair guess for the size of the stack frame of the current | ||
| 21 | - function. This doesn't have to be exact, the result is only used | ||
| 22 | +/* Make a fair guess for the size of the stack frame of the decl | ||
| 23 | + passed. This doesn't have to be exact, the result is only used | ||
| 24 | in the inline heuristics. So we don't want to run the full stack | ||
| 25 | var packing algorithm (which is quadratic in the number of stack | ||
| 26 | vars). Instead, we calculate the total size of all stack vars. | ||
| 27 | @@ -1257,11 +1257,14 @@ | ||
| 28 | vars doesn't happen very often. */ | ||
| 29 | |||
| 30 | HOST_WIDE_INT | ||
| 31 | -estimated_stack_frame_size (void) | ||
| 32 | +estimated_stack_frame_size (tree decl) | ||
| 33 | { | ||
| 34 | HOST_WIDE_INT size = 0; | ||
| 35 | size_t i; | ||
| 36 | tree t, outer_block = DECL_INITIAL (current_function_decl); | ||
| 37 | + tree old_cur_fun_decl = current_function_decl; | ||
| 38 | + current_function_decl = decl; | ||
| 39 | + push_cfun (DECL_STRUCT_FUNCTION (decl)); | ||
| 40 | |||
| 41 | init_vars_expansion (); | ||
| 42 | |||
| 43 | @@ -1284,7 +1287,8 @@ | ||
| 44 | size += account_stack_vars (); | ||
| 45 | fini_vars_expansion (); | ||
| 46 | } | ||
| 47 | - | ||
| 48 | + pop_cfun (); | ||
| 49 | + current_function_decl = old_cur_fun_decl; | ||
| 50 | return size; | ||
| 51 | } | ||
| 52 | |||
| 53 | |||
| 54 | === modified file 'gcc/ipa-inline.c' | ||
| 55 | --- old/gcc/ipa-inline.c 2010-06-30 21:30:12 +0000 | ||
| 56 | +++ new/gcc/ipa-inline.c 2010-11-24 08:43:48 +0000 | ||
| 57 | @@ -1967,7 +1967,7 @@ | ||
| 58 | |||
| 59 | /* Estimate the stack size for the function. But not at -O0 | ||
| 60 | because estimated_stack_frame_size is a quadratic problem. */ | ||
| 61 | - self_stack_size = optimize ? estimated_stack_frame_size () : 0; | ||
| 62 | + self_stack_size = optimize ? estimated_stack_frame_size (node->decl) : 0; | ||
| 63 | inline_summary (node)->estimated_self_stack_size = self_stack_size; | ||
| 64 | node->global.estimated_stack_size = self_stack_size; | ||
| 65 | node->global.stack_frame_offset = 0; | ||
| 66 | |||
| 67 | === modified file 'gcc/tree-inline.h' | ||
| 68 | --- old/gcc/tree-inline.h 2009-09-14 18:18:58 +0000 | ||
| 69 | +++ new/gcc/tree-inline.h 2010-11-24 08:43:48 +0000 | ||
| 70 | @@ -187,6 +187,6 @@ | ||
| 71 | extern tree remap_type (tree type, copy_body_data *id); | ||
| 72 | extern gimple_seq copy_gimple_seq_and_replace_locals (gimple_seq seq); | ||
| 73 | |||
| 74 | -extern HOST_WIDE_INT estimated_stack_frame_size (void); | ||
| 75 | +extern HOST_WIDE_INT estimated_stack_frame_size (tree); | ||
| 76 | |||
| 77 | #endif /* GCC_TREE_INLINE_H */ | ||
| 78 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99441.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99441.patch deleted file mode 100644 index 5495b8d80..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99441.patch +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | 2010-11-25 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-10-28 Andrew Stubbs <ams@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * config/arm/arm.c (const_ok_for_arm): Support 0xXY00XY00 pattern | ||
| 9 | constants in thumb2. | ||
| 10 | |||
| 11 | === modified file 'gcc/config/arm/arm.c' | ||
| 12 | --- old/gcc/config/arm/arm.c 2010-11-11 11:50:33 +0000 | ||
| 13 | +++ new/gcc/config/arm/arm.c 2010-12-10 15:30:47 +0000 | ||
| 14 | @@ -2340,11 +2340,17 @@ | ||
| 15 | { | ||
| 16 | HOST_WIDE_INT v; | ||
| 17 | |||
| 18 | - /* Allow repeated pattern. */ | ||
| 19 | + /* Allow repeated patterns 0x00XY00XY or 0xXYXYXYXY. */ | ||
| 20 | v = i & 0xff; | ||
| 21 | v |= v << 16; | ||
| 22 | if (i == v || i == (v | (v << 8))) | ||
| 23 | return TRUE; | ||
| 24 | + | ||
| 25 | + /* Allow repeated pattern 0xXY00XY00. */ | ||
| 26 | + v = i & 0xff00; | ||
| 27 | + v |= v << 16; | ||
| 28 | + if (i == v) | ||
| 29 | + return TRUE; | ||
| 30 | } | ||
| 31 | |||
| 32 | return FALSE; | ||
| 33 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99442.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99442.patch deleted file mode 100644 index 62c44784b..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99442.patch +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | 2010-11-24 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * loop-iv.c (get_biv_step): Workaround loop analysis ICE. | ||
| 5 | |||
| 6 | === modified file 'gcc/loop-iv.c' | ||
| 7 | --- old/gcc/loop-iv.c 2009-11-25 10:55:54 +0000 | ||
| 8 | +++ new/gcc/loop-iv.c 2010-12-10 15:32:04 +0000 | ||
| 9 | @@ -796,6 +796,13 @@ | ||
| 10 | outer_step)) | ||
| 11 | return false; | ||
| 12 | |||
| 13 | + /* CSL local: workaround get_biv_step_1() inability to handle DU | ||
| 14 | + chains originating at sets of subregs. Such subregs are introduced | ||
| 15 | + by Tom's extension elimination pass. For upstream duscussion see | ||
| 16 | + http://gcc.gnu.org/ml/gcc/2010-11/msg00552.html . */ | ||
| 17 | + if (!((*inner_mode == *outer_mode) != (*extend != UNKNOWN))) | ||
| 18 | + return false; | ||
| 19 | + | ||
| 20 | gcc_assert ((*inner_mode == *outer_mode) != (*extend != UNKNOWN)); | ||
| 21 | gcc_assert (*inner_mode != *outer_mode || *outer_step == const0_rtx); | ||
| 22 | |||
| 23 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99443.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99443.patch deleted file mode 100644 index 802c3816f..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99443.patch +++ /dev/null | |||
| @@ -1,873 +0,0 @@ | |||
| 1 | 2010-11-26 Tom de Vries <tom@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * gcc/ee.c: New file. | ||
| 5 | * gcc/tree-pass.h (pass_ee): Declare. | ||
| 6 | * gcc/opts.c (decode_options): Set flag_ee at -O2. | ||
| 7 | * gcc/timevar.def (TV_EE): New timevar. | ||
| 8 | * gcc/common.opt (fextension-elimination): New option. | ||
| 9 | * gcc/Makefile.in (ee.o): New rule. | ||
| 10 | * gcc/passes.c (pass_ee): Add it. | ||
| 11 | * gcc/testsuite/gcc.dg/extend-4.c: New test. | ||
| 12 | * gcc/testsuite/gcc.dg/extend-1.c: New test. | ||
| 13 | * gcc/testsuite/gcc.dg/extend-2.c: New test. | ||
| 14 | * gcc/testsuite/gcc.dg/extend-2-64.c: New test. | ||
| 15 | * gcc/testsuite/gcc.dg/extend-3.c: New test. | ||
| 16 | |||
| 17 | === modified file 'gcc/Makefile.in' | ||
| 18 | --- old/gcc/Makefile.in 2010-11-16 18:05:53 +0000 | ||
| 19 | +++ new/gcc/Makefile.in 2010-12-10 15:33:37 +0000 | ||
| 20 | @@ -1194,6 +1194,7 @@ | ||
| 21 | dse.o \ | ||
| 22 | dwarf2asm.o \ | ||
| 23 | dwarf2out.o \ | ||
| 24 | + ee.o \ | ||
| 25 | ebitmap.o \ | ||
| 26 | emit-rtl.o \ | ||
| 27 | et-forest.o \ | ||
| 28 | @@ -2965,6 +2966,11 @@ | ||
| 29 | web.o : web.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \ | ||
| 30 | hard-reg-set.h $(FLAGS_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \ | ||
| 31 | $(DF_H) $(OBSTACK_H) $(TIMEVAR_H) $(TREE_PASS_H) | ||
| 32 | +ee.o : ee.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \ | ||
| 33 | + hard-reg-set.h $(FLAGS_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h \ | ||
| 34 | + $(DF_H) $(TIMEVAR_H) tree-pass.h $(RECOG_H) $(EXPR_H) \ | ||
| 35 | + $(REGS_H) $(TREE_H) $(TM_P_H) insn-config.h $(INSN_ATTR_H) $(TOPLEV_H) $(DIAGNOSTIC_CORE_H) \ | ||
| 36 | + $(TARGET_H) $(OPTABS_H) insn-codes.h rtlhooks-def.h $(PARAMS_H) $(CGRAPH_H) | ||
| 37 | gcse.o : gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \ | ||
| 38 | $(REGS_H) hard-reg-set.h $(FLAGS_H) $(REAL_H) insn-config.h $(GGC_H) \ | ||
| 39 | $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \ | ||
| 40 | |||
| 41 | === modified file 'gcc/common.opt' | ||
| 42 | --- old/gcc/common.opt 2010-11-04 12:43:52 +0000 | ||
| 43 | +++ new/gcc/common.opt 2010-12-10 15:33:37 +0000 | ||
| 44 | @@ -496,6 +496,10 @@ | ||
| 45 | Common Report Var(flag_early_inlining) Init(1) Optimization | ||
| 46 | Perform early inlining | ||
| 47 | |||
| 48 | +fextension-elimination | ||
| 49 | +Common Report Var(flag_ee) Init(0) Optimization | ||
| 50 | +Perform extension elimination | ||
| 51 | + | ||
| 52 | feliminate-dwarf2-dups | ||
| 53 | Common Report Var(flag_eliminate_dwarf2_dups) | ||
| 54 | Perform DWARF2 duplicate elimination | ||
| 55 | |||
| 56 | === added file 'gcc/ee.c' | ||
| 57 | --- old/gcc/ee.c 1970-01-01 00:00:00 +0000 | ||
| 58 | +++ new/gcc/ee.c 2010-12-10 15:33:37 +0000 | ||
| 59 | @@ -0,0 +1,662 @@ | ||
| 60 | +/* Redundant extension elimination | ||
| 61 | + Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 62 | + Contributed by Tom de Vries (tom@codesourcery.com) | ||
| 63 | + | ||
| 64 | +This file is part of GCC. | ||
| 65 | + | ||
| 66 | +GCC is free software; you can redistribute it and/or modify it under | ||
| 67 | +the terms of the GNU General Public License as published by the Free | ||
| 68 | +Software Foundation; either version 3, or (at your option) any later | ||
| 69 | +version. | ||
| 70 | + | ||
| 71 | +GCC is distributed in the hope that it will be useful, but WITHOUT ANY | ||
| 72 | +WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 73 | +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
| 74 | +for more details. | ||
| 75 | + | ||
| 76 | +You should have received a copy of the GNU General Public License | ||
| 77 | +along with GCC; see the file COPYING3. If not see | ||
| 78 | +<http://www.gnu.org/licenses/>. */ | ||
| 79 | + | ||
| 80 | +/* | ||
| 81 | + | ||
| 82 | + MOTIVATING EXAMPLE | ||
| 83 | + | ||
| 84 | + The motivating example for this pass is: | ||
| 85 | + | ||
| 86 | + void f(unsigned char *p, short s, int c, int *z) | ||
| 87 | + { | ||
| 88 | + if (c) | ||
| 89 | + *z = 0; | ||
| 90 | + *p ^= (unsigned char)s; | ||
| 91 | + } | ||
| 92 | + | ||
| 93 | + For MIPS, compilation results in the following insns. | ||
| 94 | + | ||
| 95 | + (set (reg/v:SI 199) | ||
| 96 | + (sign_extend:SI (subreg:HI (reg:SI 200) 2))) | ||
| 97 | + | ||
| 98 | + ... | ||
| 99 | + | ||
| 100 | + (set (reg:QI 203) | ||
| 101 | + (subreg:QI (reg/v:SI 199) 3)) | ||
| 102 | + | ||
| 103 | + These insns are the only def and the only use of reg 199, each located in a | ||
| 104 | + different bb. | ||
| 105 | + | ||
| 106 | + The sign-extension preserves the lower half of reg 200 and copies them to | ||
| 107 | + reg 199, and the subreg use of reg 199 only reads the least significant byte. | ||
| 108 | + The sign extension is therefore redundant (the extension part, not the copy | ||
| 109 | + part), and can safely be replaced with a regcopy from reg 200 to reg 199. | ||
| 110 | + | ||
| 111 | + | ||
| 112 | + OTHER SIGN/ZERO EXTENSION ELIMINATION PASSES | ||
| 113 | + | ||
| 114 | + There are other passes which eliminate sign/zero-extension: combine and | ||
| 115 | + implicit_zee. Both attempt to eliminate extensions by combining them with | ||
| 116 | + other instructions. The combine pass does this at bb level, | ||
| 117 | + implicit_zee works at inter-bb level. | ||
| 118 | + | ||
| 119 | + The combine pass combine an extension with either: | ||
| 120 | + - all uses of the extension, or | ||
| 121 | + - all defs of the operand of the extension. | ||
| 122 | + The implicit_zee pass only implements the latter. | ||
| 123 | + | ||
| 124 | + For our motivating example, combine doesn't work since the def and the use of | ||
| 125 | + reg 199 are in a different bb. | ||
| 126 | + | ||
| 127 | + Implicit_zee does not work since it only combines an extension with the defs | ||
| 128 | + of its operand. | ||
| 129 | + | ||
| 130 | + | ||
| 131 | + INTENDED EFFECT | ||
| 132 | + | ||
| 133 | + This pass works by removing sign/zero-extensions, or replacing them with | ||
| 134 | + regcopies. The idea there is that the regcopy might be eliminated by a later | ||
| 135 | + pass. In case the regcopy cannot be eliminated, it might at least be cheaper | ||
| 136 | + than the extension. | ||
| 137 | + | ||
| 138 | + | ||
| 139 | + IMPLEMENTATION | ||
| 140 | + | ||
| 141 | + The pass scans twice over all instructions. | ||
| 142 | + | ||
| 143 | + The first scan registers all uses of a reg in the biggest_use array. After | ||
| 144 | + that first scan, the biggest_use array contains the size in bits of the | ||
| 145 | + biggest use of each reg. | ||
| 146 | + | ||
| 147 | + The second scan finds extensions, determines whether they are redundant based | ||
| 148 | + on the biggest use, and deletes or replaces them. | ||
| 149 | + | ||
| 150 | + In case that the src and dest reg of the replacement are not of the same size, | ||
| 151 | + we do not replace with a normal regcopy, but with a truncate or with the copy | ||
| 152 | + of a paradoxical subreg instead. | ||
| 153 | + | ||
| 154 | + | ||
| 155 | + LIMITATIONS | ||
| 156 | + | ||
| 157 | + The scope of the analysis is limited to an extension and its uses. The other | ||
| 158 | + type of analysis (related to the defs of the operand of an extension) is not | ||
| 159 | + done. | ||
| 160 | + | ||
| 161 | + Furthermore, we do the analysis of biggest use per reg. So when determining | ||
| 162 | + whether an extension is redundant, we take all uses of a the dest reg into | ||
| 163 | + account, also the ones that are not uses of the extension. This could be | ||
| 164 | + overcome by calculating the def-use chains and using those for analysis | ||
| 165 | + instead. | ||
| 166 | + | ||
| 167 | + Finally, during the analysis each insn is looked at in isolation. There is no | ||
| 168 | + propagation of information during the analysis. To overcome this limitation, | ||
| 169 | + a backward iterative bit-level liveness analysis is needed. */ | ||
| 170 | + | ||
| 171 | + | ||
| 172 | +#include "config.h" | ||
| 173 | +#include "system.h" | ||
| 174 | +#include "coretypes.h" | ||
| 175 | +#include "tm.h" | ||
| 176 | +#include "rtl.h" | ||
| 177 | +#include "tree.h" | ||
| 178 | +#include "tm_p.h" | ||
| 179 | +#include "flags.h" | ||
| 180 | +#include "regs.h" | ||
| 181 | +#include "hard-reg-set.h" | ||
| 182 | +#include "basic-block.h" | ||
| 183 | +#include "insn-config.h" | ||
| 184 | +#include "function.h" | ||
| 185 | +#include "expr.h" | ||
| 186 | +#include "insn-attr.h" | ||
| 187 | +#include "recog.h" | ||
| 188 | +#include "toplev.h" | ||
| 189 | +#include "target.h" | ||
| 190 | +#include "timevar.h" | ||
| 191 | +#include "optabs.h" | ||
| 192 | +#include "insn-codes.h" | ||
| 193 | +#include "rtlhooks-def.h" | ||
| 194 | +#include "output.h" | ||
| 195 | +#include "params.h" | ||
| 196 | +#include "timevar.h" | ||
| 197 | +#include "tree-pass.h" | ||
| 198 | +#include "cgraph.h" | ||
| 199 | + | ||
| 200 | +#define SKIP_REG (-1) | ||
| 201 | + | ||
| 202 | +/* Array to register the biggest use of a reg, in bits. */ | ||
| 203 | + | ||
| 204 | +static int *biggest_use; | ||
| 205 | + | ||
| 206 | +/* Forward declaration. */ | ||
| 207 | + | ||
| 208 | +static void note_use (rtx *x, void *data); | ||
| 209 | + | ||
| 210 | +/* The following two functions are borrowed from trunk/gcc/toplev.c. They can be | ||
| 211 | + removed for a check-in into gcc trunk. */ | ||
| 212 | + | ||
| 213 | +/* Given X, an unsigned number, return the number of least significant bits | ||
| 214 | + that are zero. When X == 0, the result is the word size. */ | ||
| 215 | + | ||
| 216 | +static int | ||
| 217 | +ctz_hwi (unsigned HOST_WIDE_INT x) | ||
| 218 | +{ | ||
| 219 | + return x ? floor_log2 (x & -x) : HOST_BITS_PER_WIDE_INT; | ||
| 220 | +} | ||
| 221 | + | ||
| 222 | +/* Similarly for most significant bits. */ | ||
| 223 | + | ||
| 224 | +static int | ||
| 225 | +clz_hwi (unsigned HOST_WIDE_INT x) | ||
| 226 | +{ | ||
| 227 | + return HOST_BITS_PER_WIDE_INT - 1 - floor_log2(x); | ||
| 228 | +} | ||
| 229 | + | ||
| 230 | +/* Check whether this is a paradoxical subreg. */ | ||
| 231 | + | ||
| 232 | +static bool | ||
| 233 | +paradoxical_subreg_p (rtx subreg) | ||
| 234 | +{ | ||
| 235 | + enum machine_mode subreg_mode, reg_mode; | ||
| 236 | + | ||
| 237 | + if (GET_CODE (subreg) != SUBREG) | ||
| 238 | + return false; | ||
| 239 | + | ||
| 240 | + subreg_mode = GET_MODE (subreg); | ||
| 241 | + reg_mode = GET_MODE (SUBREG_REG (subreg)); | ||
| 242 | + | ||
| 243 | + if (GET_MODE_SIZE (subreg_mode) > GET_MODE_SIZE (reg_mode)) | ||
| 244 | + return true; | ||
| 245 | + | ||
| 246 | + return false; | ||
| 247 | +} | ||
| 248 | + | ||
| 249 | +/* Get the size and reg number of a REG or SUBREG use. */ | ||
| 250 | + | ||
| 251 | +static bool | ||
| 252 | +reg_use_p (rtx use, int *size, unsigned int *regno) | ||
| 253 | +{ | ||
| 254 | + rtx reg; | ||
| 255 | + | ||
| 256 | + if (REG_P (use)) | ||
| 257 | + { | ||
| 258 | + *regno = REGNO (use); | ||
| 259 | + *size = GET_MODE_BITSIZE (GET_MODE (use)); | ||
| 260 | + return true; | ||
| 261 | + } | ||
| 262 | + else if (GET_CODE (use) == SUBREG) | ||
| 263 | + { | ||
| 264 | + reg = SUBREG_REG (use); | ||
| 265 | + | ||
| 266 | + if (!REG_P (reg)) | ||
| 267 | + return false; | ||
| 268 | + | ||
| 269 | + *regno = REGNO (reg); | ||
| 270 | + | ||
| 271 | + if (paradoxical_subreg_p (use)) | ||
| 272 | + *size = GET_MODE_BITSIZE (GET_MODE (reg)); | ||
| 273 | + else | ||
| 274 | + *size = subreg_lsb (use) + GET_MODE_BITSIZE (GET_MODE (use)); | ||
| 275 | + | ||
| 276 | + return true; | ||
| 277 | + } | ||
| 278 | + | ||
| 279 | + return false; | ||
| 280 | +} | ||
| 281 | + | ||
| 282 | +/* Register the use of a reg. */ | ||
| 283 | + | ||
| 284 | +static void | ||
| 285 | +register_use (int size, unsigned int regno) | ||
| 286 | +{ | ||
| 287 | + int *current = &biggest_use[regno]; | ||
| 288 | + | ||
| 289 | + if (*current == SKIP_REG) | ||
| 290 | + return; | ||
| 291 | + | ||
| 292 | + *current = MAX (*current, size); | ||
| 293 | +} | ||
| 294 | + | ||
| 295 | +/* Handle embedded uses. */ | ||
| 296 | + | ||
| 297 | +static void | ||
| 298 | +note_embedded_uses (rtx use, rtx pattern) | ||
| 299 | +{ | ||
| 300 | + const char *format_ptr; | ||
| 301 | + int i, j; | ||
| 302 | + | ||
| 303 | + format_ptr = GET_RTX_FORMAT (GET_CODE (use)); | ||
| 304 | + for (i = 0; i < GET_RTX_LENGTH (GET_CODE (use)); i++) | ||
| 305 | + if (format_ptr[i] == 'e') | ||
| 306 | + note_use (&XEXP (use, i), pattern); | ||
| 307 | + else if (format_ptr[i] == 'E') | ||
| 308 | + for (j = 0; j < XVECLEN (use, i); j++) | ||
| 309 | + note_use (&XVECEXP (use, i, j), pattern); | ||
| 310 | +} | ||
| 311 | + | ||
| 312 | +/* Get the set that has use as its SRC operand. */ | ||
| 313 | + | ||
| 314 | +static rtx | ||
| 315 | +get_set (rtx use, rtx pattern) | ||
| 316 | +{ | ||
| 317 | + rtx sub; | ||
| 318 | + int i; | ||
| 319 | + | ||
| 320 | + if (GET_CODE (pattern) == SET && SET_SRC (pattern) == use) | ||
| 321 | + return pattern; | ||
| 322 | + | ||
| 323 | + if (GET_CODE (pattern) == PARALLEL) | ||
| 324 | + for (i = 0; i < XVECLEN (pattern, 0); ++i) | ||
| 325 | + { | ||
| 326 | + sub = XVECEXP (pattern, 0, i); | ||
| 327 | + if (GET_CODE (sub) == SET && SET_SRC (sub) == use) | ||
| 328 | + return sub; | ||
| 329 | + } | ||
| 330 | + | ||
| 331 | + return NULL_RTX; | ||
| 332 | +} | ||
| 333 | + | ||
| 334 | +/* Handle a restricted op use. In this context restricted means that a bit in an | ||
| 335 | + operand influences only the same bit or more significant bits in the result. | ||
| 336 | + The bitwise ops are a subclass, but PLUS is one as well. */ | ||
| 337 | + | ||
| 338 | +static void | ||
| 339 | +note_restricted_op_use (rtx use, unsigned int nr_operands, rtx pattern) | ||
| 340 | +{ | ||
| 341 | + unsigned int i, smallest; | ||
| 342 | + int operand_size[2]; | ||
| 343 | + int used_size; | ||
| 344 | + unsigned int operand_regno[2]; | ||
| 345 | + bool operand_reg[2]; | ||
| 346 | + bool operand_ignore[2]; | ||
| 347 | + rtx set; | ||
| 348 | + | ||
| 349 | + /* Init operand_reg, operand_size, operand_regno and operand_ignore. */ | ||
| 350 | + for (i = 0; i < nr_operands; ++i) | ||
| 351 | + { | ||
| 352 | + operand_reg[i] = reg_use_p (XEXP (use, i), &operand_size[i], | ||
| 353 | + &operand_regno[i]); | ||
| 354 | + operand_ignore[i] = false; | ||
| 355 | + } | ||
| 356 | + | ||
| 357 | + /* Handle case of reg and-masked with const. */ | ||
| 358 | + if (GET_CODE (use) == AND && CONST_INT_P (XEXP (use, 1)) && operand_reg[0]) | ||
| 359 | + { | ||
| 360 | + used_size = | ||
| 361 | + HOST_BITS_PER_WIDE_INT - clz_hwi (UINTVAL (XEXP (use, 1))); | ||
| 362 | + operand_size[0] = MIN (operand_size[0], used_size); | ||
| 363 | + } | ||
| 364 | + | ||
| 365 | + /* Handle case of reg or-masked with const. */ | ||
| 366 | + if (GET_CODE (use) == IOR && CONST_INT_P (XEXP (use, 1)) && operand_reg[0]) | ||
| 367 | + { | ||
| 368 | + used_size = | ||
| 369 | + HOST_BITS_PER_WIDE_INT - clz_hwi (~UINTVAL (XEXP (use, 1))); | ||
| 370 | + operand_size[0] = MIN (operand_size[0], used_size); | ||
| 371 | + } | ||
| 372 | + | ||
| 373 | + /* Ignore the use of a in 'a = a + b'. */ | ||
| 374 | + set = get_set (use, pattern); | ||
| 375 | + if (set != NULL_RTX && REG_P (SET_DEST (set))) | ||
| 376 | + for (i = 0; i < nr_operands; ++i) | ||
| 377 | + operand_ignore[i] = (operand_reg[i] | ||
| 378 | + && (REGNO (SET_DEST (set)) == operand_regno[i])); | ||
| 379 | + | ||
| 380 | + /* Handle the case a reg is combined with don't care bits. */ | ||
| 381 | + if (nr_operands == 2 && operand_reg[0] && operand_reg[1] | ||
| 382 | + && operand_size[0] != operand_size[1]) | ||
| 383 | + { | ||
| 384 | + smallest = operand_size[0] > operand_size[1]; | ||
| 385 | + | ||
| 386 | + if (paradoxical_subreg_p (XEXP (use, smallest)) | ||
| 387 | + && !SUBREG_PROMOTED_VAR_P (XEXP (use, smallest))) | ||
| 388 | + operand_size[1 - smallest] = operand_size[smallest]; | ||
| 389 | + } | ||
| 390 | + | ||
| 391 | + /* Register the operand use, if necessary. */ | ||
| 392 | + for (i = 0; i < nr_operands; ++i) | ||
| 393 | + if (!operand_reg[i]) | ||
| 394 | + note_use (&XEXP (use, i), pattern); | ||
| 395 | + else if (!operand_ignore[i]) | ||
| 396 | + register_use (operand_size[i], operand_regno[i]); | ||
| 397 | +} | ||
| 398 | + | ||
| 399 | +/* Handle all uses noted by note_uses. */ | ||
| 400 | + | ||
| 401 | +static void | ||
| 402 | +note_use (rtx *x, void *data) | ||
| 403 | +{ | ||
| 404 | + rtx use = *x; | ||
| 405 | + rtx pattern = (rtx)data; | ||
| 406 | + int use_size; | ||
| 407 | + unsigned int use_regno; | ||
| 408 | + | ||
| 409 | + switch (GET_CODE (use)) | ||
| 410 | + { | ||
| 411 | + case REG: | ||
| 412 | + case SUBREG: | ||
| 413 | + if (!reg_use_p (use, &use_size, &use_regno)) | ||
| 414 | + { | ||
| 415 | + note_embedded_uses (use, pattern); | ||
| 416 | + return; | ||
| 417 | + } | ||
| 418 | + register_use (use_size, use_regno); | ||
| 419 | + return; | ||
| 420 | + case IOR: | ||
| 421 | + case AND: | ||
| 422 | + case XOR: | ||
| 423 | + case PLUS: | ||
| 424 | + case MINUS: | ||
| 425 | + note_restricted_op_use (use, 2, pattern); | ||
| 426 | + return; | ||
| 427 | + case NOT: | ||
| 428 | + case NEG: | ||
| 429 | + note_restricted_op_use (use, 1, pattern); | ||
| 430 | + return; | ||
| 431 | + case ASHIFT: | ||
| 432 | + if (!reg_use_p (XEXP (use, 0), &use_size, &use_regno) | ||
| 433 | + || !CONST_INT_P (XEXP (use, 1)) | ||
| 434 | + || INTVAL (XEXP (use, 1)) <= 0 | ||
| 435 | + || paradoxical_subreg_p (XEXP (use, 0))) | ||
| 436 | + { | ||
| 437 | + note_embedded_uses (use, pattern); | ||
| 438 | + return; | ||
| 439 | + } | ||
| 440 | + register_use (use_size - INTVAL (XEXP (use, 1)), use_regno); | ||
| 441 | + return; | ||
| 442 | + default: | ||
| 443 | + note_embedded_uses (use, pattern); | ||
| 444 | + return; | ||
| 445 | + } | ||
| 446 | +} | ||
| 447 | + | ||
| 448 | +/* Check whether reg is implicitly used. */ | ||
| 449 | + | ||
| 450 | +static bool | ||
| 451 | +implicit_use_p (int regno) | ||
| 452 | +{ | ||
| 453 | +#ifdef EPILOGUE_USES | ||
| 454 | + if (EPILOGUE_USES (regno)) | ||
| 455 | + return true; | ||
| 456 | +#endif | ||
| 457 | + | ||
| 458 | +#ifdef EH_USES | ||
| 459 | + if (EH_USES (regno)) | ||
| 460 | + return true; | ||
| 461 | +#endif | ||
| 462 | + | ||
| 463 | + return false; | ||
| 464 | +} | ||
| 465 | + | ||
| 466 | +/* Note the uses of argument registers in a call. */ | ||
| 467 | + | ||
| 468 | +static void | ||
| 469 | +note_call_uses (rtx insn) | ||
| 470 | +{ | ||
| 471 | + rtx link, link_expr; | ||
| 472 | + | ||
| 473 | + if (!CALL_P (insn)) | ||
| 474 | + return; | ||
| 475 | + | ||
| 476 | + for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | ||
| 477 | + { | ||
| 478 | + link_expr = XEXP (link, 0); | ||
| 479 | + | ||
| 480 | + if (GET_CODE (link_expr) == USE) | ||
| 481 | + note_use (&XEXP (link_expr, 0), link); | ||
| 482 | + } | ||
| 483 | +} | ||
| 484 | + | ||
| 485 | +/* Calculate the biggest use mode for all regs. */ | ||
| 486 | + | ||
| 487 | +static void | ||
| 488 | +calculate_biggest_use (void) | ||
| 489 | +{ | ||
| 490 | + int i; | ||
| 491 | + basic_block bb; | ||
| 492 | + rtx insn; | ||
| 493 | + | ||
| 494 | + /* Initialize biggest_use for all regs to 0. If a reg is used implicitly, we | ||
| 495 | + handle that reg conservatively and set it to SKIP_REG instead. */ | ||
| 496 | + for (i = 0; i < max_reg_num (); i++) | ||
| 497 | + biggest_use[i] = ((implicit_use_p (i) || HARD_REGISTER_NUM_P (i)) | ||
| 498 | + ? SKIP_REG : 0); | ||
| 499 | + | ||
| 500 | + /* For all insns, call note_use for each use in insn. */ | ||
| 501 | + FOR_EACH_BB (bb) | ||
| 502 | + FOR_BB_INSNS (bb, insn) | ||
| 503 | + { | ||
| 504 | + if (!NONDEBUG_INSN_P (insn)) | ||
| 505 | + continue; | ||
| 506 | + | ||
| 507 | + note_uses (&PATTERN (insn), note_use, PATTERN (insn)); | ||
| 508 | + | ||
| 509 | + if (CALL_P (insn)) | ||
| 510 | + note_call_uses (insn); | ||
| 511 | + } | ||
| 512 | + | ||
| 513 | + /* Dump the biggest uses found. */ | ||
| 514 | + if (dump_file) | ||
| 515 | + for (i = 0; i < max_reg_num (); i++) | ||
| 516 | + if (biggest_use[i] > 0) | ||
| 517 | + fprintf (dump_file, "reg %d: size %d\n", i, biggest_use[i]); | ||
| 518 | +} | ||
| 519 | + | ||
| 520 | +/* Check whether this is a sign/zero extension. */ | ||
| 521 | + | ||
| 522 | +static bool | ||
| 523 | +extension_p (rtx insn, rtx *dest, rtx *inner, int *preserved_size) | ||
| 524 | +{ | ||
| 525 | + rtx src, op0; | ||
| 526 | + | ||
| 527 | + /* Detect set of reg. */ | ||
| 528 | + if (GET_CODE (PATTERN (insn)) != SET) | ||
| 529 | + return false; | ||
| 530 | + | ||
| 531 | + src = SET_SRC (PATTERN (insn)); | ||
| 532 | + *dest = SET_DEST (PATTERN (insn)); | ||
| 533 | + | ||
| 534 | + if (!REG_P (*dest)) | ||
| 535 | + return false; | ||
| 536 | + | ||
| 537 | + /* Detect sign or zero extension. */ | ||
| 538 | + if (GET_CODE (src) == ZERO_EXTEND || GET_CODE (src) == SIGN_EXTEND | ||
| 539 | + || (GET_CODE (src) == AND && CONST_INT_P (XEXP (src, 1)))) | ||
| 540 | + { | ||
| 541 | + op0 = XEXP (src, 0); | ||
| 542 | + | ||
| 543 | + /* Determine amount of least significant bits preserved by operation. */ | ||
| 544 | + if (GET_CODE (src) == AND) | ||
| 545 | + *preserved_size = ctz_hwi (~UINTVAL (XEXP (src, 1))); | ||
| 546 | + else | ||
| 547 | + *preserved_size = GET_MODE_BITSIZE (GET_MODE (op0)); | ||
| 548 | + | ||
| 549 | + if (GET_CODE (op0) == SUBREG) | ||
| 550 | + { | ||
| 551 | + if (subreg_lsb (op0) != 0) | ||
| 552 | + return false; | ||
| 553 | + | ||
| 554 | + *inner = SUBREG_REG (op0); | ||
| 555 | + return true; | ||
| 556 | + } | ||
| 557 | + else if (REG_P (op0)) | ||
| 558 | + { | ||
| 559 | + *inner = op0; | ||
| 560 | + return true; | ||
| 561 | + } | ||
| 562 | + } | ||
| 563 | + | ||
| 564 | + return false; | ||
| 565 | +} | ||
| 566 | + | ||
| 567 | +/* Check whether this is a redundant sign/zero extension. */ | ||
| 568 | + | ||
| 569 | +static bool | ||
| 570 | +redundant_extension_p (rtx insn, rtx *dest, rtx *inner) | ||
| 571 | +{ | ||
| 572 | + int biggest_dest_use; | ||
| 573 | + int preserved_size; | ||
| 574 | + | ||
| 575 | + if (!extension_p (insn, dest, inner, &preserved_size)) | ||
| 576 | + return false; | ||
| 577 | + | ||
| 578 | + if (dump_file) | ||
| 579 | + fprintf (dump_file, "considering extension %u with preserved size %d\n", | ||
| 580 | + INSN_UID (insn), preserved_size); | ||
| 581 | + | ||
| 582 | + biggest_dest_use = biggest_use[REGNO (*dest)]; | ||
| 583 | + | ||
| 584 | + if (biggest_dest_use == SKIP_REG) | ||
| 585 | + return false; | ||
| 586 | + | ||
| 587 | + if (preserved_size < biggest_dest_use) | ||
| 588 | + return false; | ||
| 589 | + | ||
| 590 | + if (dump_file) | ||
| 591 | + fprintf (dump_file, "found superfluous extension %u\n", INSN_UID (insn)); | ||
| 592 | + | ||
| 593 | + return true; | ||
| 594 | +} | ||
| 595 | + | ||
| 596 | +/* Try to remove or replace the redundant extension. */ | ||
| 597 | + | ||
| 598 | +static void | ||
| 599 | +try_remove_or_replace_extension (rtx insn, rtx dest, rtx inner) | ||
| 600 | +{ | ||
| 601 | + rtx cp_src, cp_dest, seq, one; | ||
| 602 | + | ||
| 603 | + if (GET_MODE_CLASS (GET_MODE (dest)) != GET_MODE_CLASS (GET_MODE (inner))) | ||
| 604 | + return; | ||
| 605 | + | ||
| 606 | + /* Check whether replacement is needed. */ | ||
| 607 | + if (dest != inner) | ||
| 608 | + { | ||
| 609 | + start_sequence (); | ||
| 610 | + | ||
| 611 | + /* Determine the proper replacement operation. */ | ||
| 612 | + if (GET_MODE (dest) == GET_MODE (inner)) | ||
| 613 | + { | ||
| 614 | + cp_src = inner; | ||
| 615 | + cp_dest = dest; | ||
| 616 | + } | ||
| 617 | + else if (GET_MODE_SIZE (GET_MODE (dest)) | ||
| 618 | + > GET_MODE_SIZE (GET_MODE (inner))) | ||
| 619 | + { | ||
| 620 | + emit_clobber (dest); | ||
| 621 | + cp_src = inner; | ||
| 622 | + cp_dest = gen_lowpart_SUBREG (GET_MODE (inner), dest); | ||
| 623 | + } | ||
| 624 | + else | ||
| 625 | + { | ||
| 626 | + cp_src = gen_rtx_TRUNCATE (GET_MODE (dest), inner); | ||
| 627 | + cp_dest = dest; | ||
| 628 | + } | ||
| 629 | + | ||
| 630 | + emit_move_insn (cp_dest, cp_src); | ||
| 631 | + | ||
| 632 | + seq = get_insns (); | ||
| 633 | + end_sequence (); | ||
| 634 | + | ||
| 635 | + /* If the replacement is not supported, bail out. */ | ||
| 636 | + for (one = seq; one != NULL_RTX; one = NEXT_INSN (one)) | ||
| 637 | + if (recog_memoized (one) < 0 && GET_CODE (PATTERN (one)) != CLOBBER) | ||
| 638 | + return; | ||
| 639 | + | ||
| 640 | + /* Insert the replacement. */ | ||
| 641 | + emit_insn_before (seq, insn); | ||
| 642 | + } | ||
| 643 | + | ||
| 644 | + /* Note replacement/removal in the dump. */ | ||
| 645 | + if (dump_file) | ||
| 646 | + { | ||
| 647 | + fprintf (dump_file, "superfluous extension %u ", INSN_UID (insn)); | ||
| 648 | + if (dest != inner) | ||
| 649 | + fprintf (dump_file, "replaced by %u\n", INSN_UID (seq)); | ||
| 650 | + else | ||
| 651 | + fprintf (dump_file, "removed\n"); | ||
| 652 | + } | ||
| 653 | + | ||
| 654 | + /* Remove the extension. */ | ||
| 655 | + delete_insn (insn); | ||
| 656 | +} | ||
| 657 | + | ||
| 658 | +/* Find redundant extensions and remove or replace them if possible. */ | ||
| 659 | + | ||
| 660 | +static void | ||
| 661 | +remove_redundant_extensions (void) | ||
| 662 | +{ | ||
| 663 | + basic_block bb; | ||
| 664 | + rtx insn, next, dest, inner; | ||
| 665 | + | ||
| 666 | + biggest_use = XNEWVEC (int, max_reg_num ()); | ||
| 667 | + calculate_biggest_use (); | ||
| 668 | + | ||
| 669 | + /* Remove redundant extensions. */ | ||
| 670 | + FOR_EACH_BB (bb) | ||
| 671 | + FOR_BB_INSNS_SAFE (bb, insn, next) | ||
| 672 | + { | ||
| 673 | + if (!NONDEBUG_INSN_P (insn)) | ||
| 674 | + continue; | ||
| 675 | + | ||
| 676 | + if (!redundant_extension_p (insn, &dest, &inner)) | ||
| 677 | + continue; | ||
| 678 | + | ||
| 679 | + try_remove_or_replace_extension (insn, dest, inner); | ||
| 680 | + } | ||
| 681 | + | ||
| 682 | + free (biggest_use); | ||
| 683 | +} | ||
| 684 | + | ||
| 685 | +/* Remove redundant extensions. */ | ||
| 686 | + | ||
| 687 | +static unsigned int | ||
| 688 | +rest_of_handle_ee (void) | ||
| 689 | +{ | ||
| 690 | + remove_redundant_extensions (); | ||
| 691 | + return 0; | ||
| 692 | +} | ||
| 693 | + | ||
| 694 | +/* Run ee pass when flag_ee is set at optimization level > 0. */ | ||
| 695 | + | ||
| 696 | +static bool | ||
| 697 | +gate_handle_ee (void) | ||
| 698 | +{ | ||
| 699 | + return (optimize > 0 && flag_ee); | ||
| 700 | +} | ||
| 701 | + | ||
| 702 | +struct rtl_opt_pass pass_ee = | ||
| 703 | +{ | ||
| 704 | + { | ||
| 705 | + RTL_PASS, | ||
| 706 | + "ee", /* name */ | ||
| 707 | + gate_handle_ee, /* gate */ | ||
| 708 | + rest_of_handle_ee, /* execute */ | ||
| 709 | + NULL, /* sub */ | ||
| 710 | + NULL, /* next */ | ||
| 711 | + 0, /* static_pass_number */ | ||
| 712 | + TV_EE, /* tv_id */ | ||
| 713 | + 0, /* properties_required */ | ||
| 714 | + 0, /* properties_provided */ | ||
| 715 | + 0, /* properties_destroyed */ | ||
| 716 | + 0, /* todo_flags_start */ | ||
| 717 | + TODO_ggc_collect | | ||
| 718 | + TODO_dump_func | | ||
| 719 | + TODO_verify_rtl_sharing, /* todo_flags_finish */ | ||
| 720 | + } | ||
| 721 | +}; | ||
| 722 | |||
| 723 | === modified file 'gcc/opts.c' | ||
| 724 | --- old/gcc/opts.c 2010-05-17 09:13:28 +0000 | ||
| 725 | +++ new/gcc/opts.c 2010-12-10 15:33:37 +0000 | ||
| 726 | @@ -907,6 +907,7 @@ | ||
| 727 | flag_tree_switch_conversion = opt2; | ||
| 728 | flag_ipa_cp = opt2; | ||
| 729 | flag_ipa_sra = opt2; | ||
| 730 | + flag_ee = opt2; | ||
| 731 | |||
| 732 | /* Track fields in field-sensitive alias analysis. */ | ||
| 733 | set_param_value ("max-fields-for-field-sensitive", | ||
| 734 | |||
| 735 | === modified file 'gcc/passes.c' | ||
| 736 | --- old/gcc/passes.c 2010-09-01 13:29:58 +0000 | ||
| 737 | +++ new/gcc/passes.c 2010-12-10 15:33:37 +0000 | ||
| 738 | @@ -974,6 +974,7 @@ | ||
| 739 | NEXT_PASS (pass_lower_subreg); | ||
| 740 | NEXT_PASS (pass_df_initialize_opt); | ||
| 741 | NEXT_PASS (pass_cse); | ||
| 742 | + NEXT_PASS (pass_ee); | ||
| 743 | NEXT_PASS (pass_rtl_fwprop); | ||
| 744 | NEXT_PASS (pass_rtl_cprop); | ||
| 745 | NEXT_PASS (pass_rtl_pre); | ||
| 746 | |||
| 747 | === added file 'gcc/testsuite/gcc.dg/extend-1.c' | ||
| 748 | --- old/gcc/testsuite/gcc.dg/extend-1.c 1970-01-01 00:00:00 +0000 | ||
| 749 | +++ new/gcc/testsuite/gcc.dg/extend-1.c 2010-12-10 15:33:37 +0000 | ||
| 750 | @@ -0,0 +1,13 @@ | ||
| 751 | +/* { dg-do compile } */ | ||
| 752 | +/* { dg-options "-O2 -fdump-rtl-ee" } */ | ||
| 753 | + | ||
| 754 | +void f(unsigned char * p, short s, int c, int *z) | ||
| 755 | +{ | ||
| 756 | + if (c) | ||
| 757 | + *z = 0; | ||
| 758 | + *p ^= (unsigned char)s; | ||
| 759 | +} | ||
| 760 | + | ||
| 761 | +/* { dg-final { scan-rtl-dump-times "sign_extend:" 0 "ee" { target mips*-*-* } } } */ | ||
| 762 | +/* { dg-final { scan-rtl-dump-times "superfluous extension \[0-9\]+ replaced" 1 "ee" { target mips*-*-* } } } */ | ||
| 763 | +/* { dg-final { cleanup-rtl-dump "ee" } } */ | ||
| 764 | |||
| 765 | === added file 'gcc/testsuite/gcc.dg/extend-2-64.c' | ||
| 766 | --- old/gcc/testsuite/gcc.dg/extend-2-64.c 1970-01-01 00:00:00 +0000 | ||
| 767 | +++ new/gcc/testsuite/gcc.dg/extend-2-64.c 2010-12-10 15:33:37 +0000 | ||
| 768 | @@ -0,0 +1,20 @@ | ||
| 769 | +/* { dg-do compile } */ | ||
| 770 | +/* { dg-options "-O2 -fdump-rtl-ee" } */ | ||
| 771 | +/* { dg-require-effective-target mips64 } */ | ||
| 772 | + | ||
| 773 | +void f(unsigned char * p, short *s, int c) | ||
| 774 | +{ | ||
| 775 | + short or = 0; | ||
| 776 | + while (c) | ||
| 777 | + { | ||
| 778 | + or = or | s[c]; | ||
| 779 | + c --; | ||
| 780 | + } | ||
| 781 | + *p = (unsigned char)or; | ||
| 782 | +} | ||
| 783 | + | ||
| 784 | +/* { dg-final { scan-rtl-dump-times "zero_extend:" 1 "ee" { target mips*-*-* } } } */ | ||
| 785 | +/* { dg-final { scan-rtl-dump-times "sign_extend:" 0 "ee" { target mips*-*-* } } } */ | ||
| 786 | +/* { dg-final { scan-rtl-dump-times "superfluous extension \[0-9\]+ replaced" 3 "ee" { target mips*-*-* } } } */ | ||
| 787 | +/* { dg-final { cleanup-rtl-dump "ee" } } */ | ||
| 788 | + | ||
| 789 | |||
| 790 | === added file 'gcc/testsuite/gcc.dg/extend-2.c' | ||
| 791 | --- old/gcc/testsuite/gcc.dg/extend-2.c 1970-01-01 00:00:00 +0000 | ||
| 792 | +++ new/gcc/testsuite/gcc.dg/extend-2.c 2010-12-10 15:33:37 +0000 | ||
| 793 | @@ -0,0 +1,20 @@ | ||
| 794 | +/* { dg-do compile } */ | ||
| 795 | +/* { dg-options "-O2 -fdump-rtl-ee" } */ | ||
| 796 | +/* { dg-require-effective-target ilp32 } */ | ||
| 797 | + | ||
| 798 | +void f(unsigned char * p, short *s, int c) | ||
| 799 | +{ | ||
| 800 | + short or = 0; | ||
| 801 | + while (c) | ||
| 802 | + { | ||
| 803 | + or = or | s[c]; | ||
| 804 | + c --; | ||
| 805 | + } | ||
| 806 | + *p = (unsigned char)or; | ||
| 807 | +} | ||
| 808 | + | ||
| 809 | +/* { dg-final { scan-rtl-dump-times "zero_extend" 0 "ee" { target mips*-*-* } } } */ | ||
| 810 | +/* { dg-final { scan-rtl-dump-times "sign_extend" 0 "ee" { target mips*-*-* } } } */ | ||
| 811 | +/* { dg-final { scan-rtl-dump-times "superfluous extension \[0-9\]+ replaced" 2 "ee" { target mips*-*-* } } } */ | ||
| 812 | +/* { dg-final { cleanup-rtl-dump "ee" } } */ | ||
| 813 | + | ||
| 814 | |||
| 815 | === added file 'gcc/testsuite/gcc.dg/extend-3.c' | ||
| 816 | --- old/gcc/testsuite/gcc.dg/extend-3.c 1970-01-01 00:00:00 +0000 | ||
| 817 | +++ new/gcc/testsuite/gcc.dg/extend-3.c 2010-12-10 15:33:37 +0000 | ||
| 818 | @@ -0,0 +1,12 @@ | ||
| 819 | +/* { dg-do compile } */ | ||
| 820 | +/* { dg-options "-O2 -fdump-rtl-ee" } */ | ||
| 821 | + | ||
| 822 | +unsigned int f(unsigned char byte) | ||
| 823 | +{ | ||
| 824 | + return byte << 25; | ||
| 825 | +} | ||
| 826 | + | ||
| 827 | +/* { dg-final { scan-rtl-dump-times "zero_extend:" 0 "ee" { target mips*-*-* } } } */ | ||
| 828 | +/* { dg-final { scan-rtl-dump "superfluous extension \[0-9\]+ replaced" "ee" { target mips*-*-* } } } */ | ||
| 829 | +/* { dg-final { cleanup-rtl-dump "ee" } } */ | ||
| 830 | + | ||
| 831 | |||
| 832 | === added file 'gcc/testsuite/gcc.dg/extend-4.c' | ||
| 833 | --- old/gcc/testsuite/gcc.dg/extend-4.c 1970-01-01 00:00:00 +0000 | ||
| 834 | +++ new/gcc/testsuite/gcc.dg/extend-4.c 2010-12-10 15:33:37 +0000 | ||
| 835 | @@ -0,0 +1,13 @@ | ||
| 836 | +/* { dg-do compile } */ | ||
| 837 | +/* { dg-options "-O2 -fdump-rtl-ee" } */ | ||
| 838 | + | ||
| 839 | +unsigned char f(unsigned int a) | ||
| 840 | +{ | ||
| 841 | + unsigned int b = a & 0x10ff; | ||
| 842 | + return b; | ||
| 843 | +} | ||
| 844 | + | ||
| 845 | +/* { dg-final { scan-rtl-dump-times "and:" 0 "ee" { target mips*-*-* } } } */ | ||
| 846 | +/* { dg-final { scan-rtl-dump-times "superfluous extension \[0-9\]+ replaced" 1 "ee" { target mips*-*-* } } } */ | ||
| 847 | +/* { dg-final { cleanup-rtl-dump "ee" } } */ | ||
| 848 | + | ||
| 849 | |||
| 850 | === modified file 'gcc/timevar.def' | ||
| 851 | --- old/gcc/timevar.def 2009-11-27 12:43:08 +0000 | ||
| 852 | +++ new/gcc/timevar.def 2010-12-10 15:33:37 +0000 | ||
| 853 | @@ -162,6 +162,7 @@ | ||
| 854 | DEFTIMEVAR (TV_VARCONST , "varconst") | ||
| 855 | DEFTIMEVAR (TV_LOWER_SUBREG , "lower subreg") | ||
| 856 | DEFTIMEVAR (TV_JUMP , "jump") | ||
| 857 | +DEFTIMEVAR (TV_EE , "extension elimination") | ||
| 858 | DEFTIMEVAR (TV_FWPROP , "forward prop") | ||
| 859 | DEFTIMEVAR (TV_CSE , "CSE") | ||
| 860 | DEFTIMEVAR (TV_DCE , "dead code elimination") | ||
| 861 | |||
| 862 | === modified file 'gcc/tree-pass.h' | ||
| 863 | --- old/gcc/tree-pass.h 2010-09-01 13:29:58 +0000 | ||
| 864 | +++ new/gcc/tree-pass.h 2010-12-10 15:33:37 +0000 | ||
| 865 | @@ -468,6 +468,7 @@ | ||
| 866 | extern struct rtl_opt_pass pass_initial_value_sets; | ||
| 867 | extern struct rtl_opt_pass pass_unshare_all_rtl; | ||
| 868 | extern struct rtl_opt_pass pass_instantiate_virtual_regs; | ||
| 869 | +extern struct rtl_opt_pass pass_ee; | ||
| 870 | extern struct rtl_opt_pass pass_rtl_fwprop; | ||
| 871 | extern struct rtl_opt_pass pass_rtl_fwprop_addr; | ||
| 872 | extern struct rtl_opt_pass pass_jump2; | ||
| 873 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99444.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99444.patch deleted file mode 100644 index 80eebeec0..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99444.patch +++ /dev/null | |||
| @@ -1,183 +0,0 @@ | |||
| 1 | 2010-12-02 Bernd Schmidt <bernds@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #10089 | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * expr.c (store_field): Avoid a direct store if the mode is larger | ||
| 7 | than the size of the bit field. | ||
| 8 | * stor-layout.c (layout_decl): If flag_strict_volatile_bitfields, | ||
| 9 | treat non-volatile bit fields like volatile ones. | ||
| 10 | * toplev.c (process_options): Disallow combination of | ||
| 11 | -fstrict-volatile-bitfields and ABI versions less than 2. | ||
| 12 | * config/arm/arm.c (arm_option_override): Don't enable | ||
| 13 | flag_strict_volatile_bitfields if the ABI version is less than 2. | ||
| 14 | * config/h8300/h8300.c (h8300_option_override): Likewise. | ||
| 15 | * config/rx/rx.c (rx_option_override): Likewise. | ||
| 16 | * config/m32c/m32c.c (m32c_option_override): Likewise. | ||
| 17 | * config/sh/sh.c (sh_option_override): Likewise. | ||
| 18 | |||
| 19 | gcc/testsuite/ | ||
| 20 | * gcc.target/arm/volatile-bitfields-4.c: New test. | ||
| 21 | * c-c++-common/abi-bf.c: New test. | ||
| 22 | |||
| 23 | === modified file 'gcc/config/arm/arm.c' | ||
| 24 | --- old/gcc/config/arm/arm.c 2010-12-10 15:30:47 +0000 | ||
| 25 | +++ new/gcc/config/arm/arm.c 2010-12-10 15:34:19 +0000 | ||
| 26 | @@ -1934,7 +1934,8 @@ | ||
| 27 | set_param_value ("gcse-unrestricted-cost", 2); | ||
| 28 | |||
| 29 | /* ARM EABI defaults to strict volatile bitfields. */ | ||
| 30 | - if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0) | ||
| 31 | + if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0 | ||
| 32 | + && abi_version_at_least(2)) | ||
| 33 | flag_strict_volatile_bitfields = 1; | ||
| 34 | |||
| 35 | /* Register global variables with the garbage collector. */ | ||
| 36 | |||
| 37 | === modified file 'gcc/config/h8300/h8300.c' | ||
| 38 | --- old/gcc/config/h8300/h8300.c 2010-11-04 12:43:52 +0000 | ||
| 39 | +++ new/gcc/config/h8300/h8300.c 2010-12-10 15:34:19 +0000 | ||
| 40 | @@ -405,7 +405,7 @@ | ||
| 41 | } | ||
| 42 | |||
| 43 | /* This target defaults to strict volatile bitfields. */ | ||
| 44 | - if (flag_strict_volatile_bitfields < 0) | ||
| 45 | + if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) | ||
| 46 | flag_strict_volatile_bitfields = 1; | ||
| 47 | } | ||
| 48 | |||
| 49 | |||
| 50 | === modified file 'gcc/config/m32c/m32c.c' | ||
| 51 | --- old/gcc/config/m32c/m32c.c 2010-11-04 12:43:52 +0000 | ||
| 52 | +++ new/gcc/config/m32c/m32c.c 2010-12-10 15:34:19 +0000 | ||
| 53 | @@ -430,7 +430,7 @@ | ||
| 54 | flag_ivopts = 0; | ||
| 55 | |||
| 56 | /* This target defaults to strict volatile bitfields. */ | ||
| 57 | - if (flag_strict_volatile_bitfields < 0) | ||
| 58 | + if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) | ||
| 59 | flag_strict_volatile_bitfields = 1; | ||
| 60 | } | ||
| 61 | |||
| 62 | |||
| 63 | === modified file 'gcc/config/rx/rx.c' | ||
| 64 | --- old/gcc/config/rx/rx.c 2010-11-04 12:43:52 +0000 | ||
| 65 | +++ new/gcc/config/rx/rx.c 2010-12-10 15:34:19 +0000 | ||
| 66 | @@ -2191,7 +2191,7 @@ | ||
| 67 | rx_option_override (void) | ||
| 68 | { | ||
| 69 | /* This target defaults to strict volatile bitfields. */ | ||
| 70 | - if (flag_strict_volatile_bitfields < 0) | ||
| 71 | + if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) | ||
| 72 | flag_strict_volatile_bitfields = 1; | ||
| 73 | } | ||
| 74 | |||
| 75 | |||
| 76 | === modified file 'gcc/config/sh/sh.c' | ||
| 77 | --- old/gcc/config/sh/sh.c 2010-11-04 12:43:52 +0000 | ||
| 78 | +++ new/gcc/config/sh/sh.c 2010-12-10 15:34:19 +0000 | ||
| 79 | @@ -952,7 +952,7 @@ | ||
| 80 | sh_fix_range (sh_fixed_range_str); | ||
| 81 | |||
| 82 | /* This target defaults to strict volatile bitfields. */ | ||
| 83 | - if (flag_strict_volatile_bitfields < 0) | ||
| 84 | + if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) | ||
| 85 | flag_strict_volatile_bitfields = 1; | ||
| 86 | } | ||
| 87 | |||
| 88 | |||
| 89 | === modified file 'gcc/expr.c' | ||
| 90 | --- old/gcc/expr.c 2010-11-04 12:43:52 +0000 | ||
| 91 | +++ new/gcc/expr.c 2010-12-10 15:34:19 +0000 | ||
| 92 | @@ -5848,6 +5848,8 @@ | ||
| 93 | || bitpos % GET_MODE_ALIGNMENT (mode)) | ||
| 94 | && SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (target))) | ||
| 95 | || (bitpos % BITS_PER_UNIT != 0))) | ||
| 96 | + || (bitsize >= 0 && mode != BLKmode | ||
| 97 | + && GET_MODE_BITSIZE (mode) > bitsize) | ||
| 98 | /* If the RHS and field are a constant size and the size of the | ||
| 99 | RHS isn't the same size as the bitfield, we must use bitfield | ||
| 100 | operations. */ | ||
| 101 | |||
| 102 | === modified file 'gcc/stor-layout.c' | ||
| 103 | --- old/gcc/stor-layout.c 2010-11-26 12:03:32 +0000 | ||
| 104 | +++ new/gcc/stor-layout.c 2010-12-10 15:34:19 +0000 | ||
| 105 | @@ -621,12 +621,13 @@ | ||
| 106 | /* See if we can use an ordinary integer mode for a bit-field. | ||
| 107 | Conditions are: a fixed size that is correct for another mode, | ||
| 108 | occupying a complete byte or bytes on proper boundary, | ||
| 109 | - and not volatile or not -fstrict-volatile-bitfields. */ | ||
| 110 | + and not -fstrict-volatile-bitfields. If the latter is set, | ||
| 111 | + we unfortunately can't check TREE_THIS_VOLATILE, as a cast | ||
| 112 | + may make a volatile object later. */ | ||
| 113 | if (TYPE_SIZE (type) != 0 | ||
| 114 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | ||
| 115 | && GET_MODE_CLASS (TYPE_MODE (type)) == MODE_INT | ||
| 116 | - && !(TREE_THIS_VOLATILE (decl) | ||
| 117 | - && flag_strict_volatile_bitfields > 0)) | ||
| 118 | + && flag_strict_volatile_bitfields <= 0) | ||
| 119 | { | ||
| 120 | enum machine_mode xmode | ||
| 121 | = mode_for_size_tree (DECL_SIZE (decl), MODE_INT, 1); | ||
| 122 | |||
| 123 | === added file 'gcc/testsuite/c-c++-common/abi-bf.c' | ||
| 124 | --- old/gcc/testsuite/c-c++-common/abi-bf.c 1970-01-01 00:00:00 +0000 | ||
| 125 | +++ new/gcc/testsuite/c-c++-common/abi-bf.c 2010-12-10 15:34:19 +0000 | ||
| 126 | @@ -0,0 +1,3 @@ | ||
| 127 | +/* { dg-warning "incompatible" } */ | ||
| 128 | +/* { dg-do compile } */ | ||
| 129 | +/* { dg-options "-fstrict-volatile-bitfields -fabi-version=1" } */ | ||
| 130 | |||
| 131 | === added file 'gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c' | ||
| 132 | --- old/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c 1970-01-01 00:00:00 +0000 | ||
| 133 | +++ new/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c 2010-12-10 15:34:19 +0000 | ||
| 134 | @@ -0,0 +1,30 @@ | ||
| 135 | +/* { dg-require-effective-target arm_eabi } */ | ||
| 136 | +/* { dg-do compile } */ | ||
| 137 | +/* { dg-options "-O2" } */ | ||
| 138 | +/* { dg-final { scan-assembler-times "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */ | ||
| 139 | +/* { dg-final { scan-assembler-times "str\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */ | ||
| 140 | +/* { dg-final { scan-assembler-not "strb" } } */ | ||
| 141 | + | ||
| 142 | +struct thing { | ||
| 143 | + unsigned a: 8; | ||
| 144 | + unsigned b: 8; | ||
| 145 | + unsigned c: 8; | ||
| 146 | + unsigned d: 8; | ||
| 147 | +}; | ||
| 148 | + | ||
| 149 | +struct thing2 { | ||
| 150 | + volatile unsigned a: 8; | ||
| 151 | + volatile unsigned b: 8; | ||
| 152 | + volatile unsigned c: 8; | ||
| 153 | + volatile unsigned d: 8; | ||
| 154 | +}; | ||
| 155 | + | ||
| 156 | +void test1(volatile struct thing *t) | ||
| 157 | +{ | ||
| 158 | + t->a = 5; | ||
| 159 | +} | ||
| 160 | + | ||
| 161 | +void test2(struct thing2 *t) | ||
| 162 | +{ | ||
| 163 | + t->a = 5; | ||
| 164 | +} | ||
| 165 | |||
| 166 | === modified file 'gcc/toplev.c' | ||
| 167 | --- old/gcc/toplev.c 2010-03-31 01:44:10 +0000 | ||
| 168 | +++ new/gcc/toplev.c 2010-12-10 15:34:19 +0000 | ||
| 169 | @@ -1851,6 +1851,13 @@ | ||
| 170 | sorry ("Graphite loop optimizations cannot be used"); | ||
| 171 | #endif | ||
| 172 | |||
| 173 | + if (flag_strict_volatile_bitfields > 0 && !abi_version_at_least (2)) | ||
| 174 | + { | ||
| 175 | + warning (0, "-fstrict-volatile-bitfield disabled; " | ||
| 176 | + "it is incompatible with ABI versions < 2"); | ||
| 177 | + flag_strict_volatile_bitfields = 0; | ||
| 178 | + } | ||
| 179 | + | ||
| 180 | /* Unrolling all loops implies that standard loop unrolling must also | ||
| 181 | be done. */ | ||
| 182 | if (flag_unroll_all_loops) | ||
| 183 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99449.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99449.patch deleted file mode 100644 index e6b0fad08..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99449.patch +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | 2010-12-21 Ulrich Weigand <uweigand@de.ibm.com> | ||
| 2 | |||
| 3 | LP: #617384 | ||
| 4 | Backport from mainline: | ||
| 5 | |||
| 6 | gcc/ | ||
| 7 | * config/arm/arm.c (require_pic_register): Set INSN_LOCATOR for all | ||
| 8 | instructions injected into the prologue to prologue_locator. | ||
| 9 | |||
| 10 | === modified file 'gcc/config/arm/arm.c' | ||
| 11 | --- old/gcc/config/arm/arm.c 2010-12-10 15:34:19 +0000 | ||
| 12 | +++ new/gcc/config/arm/arm.c 2010-12-21 14:13:38 +0000 | ||
| 13 | @@ -5080,7 +5080,7 @@ | ||
| 14 | } | ||
| 15 | else | ||
| 16 | { | ||
| 17 | - rtx seq; | ||
| 18 | + rtx seq, insn; | ||
| 19 | |||
| 20 | if (!cfun->machine->pic_reg) | ||
| 21 | cfun->machine->pic_reg = gen_reg_rtx (Pmode); | ||
| 22 | @@ -5097,6 +5097,11 @@ | ||
| 23 | |||
| 24 | seq = get_insns (); | ||
| 25 | end_sequence (); | ||
| 26 | + | ||
| 27 | + for (insn = seq; insn; insn = NEXT_INSN (insn)) | ||
| 28 | + if (INSN_P (insn)) | ||
| 29 | + INSN_LOCATOR (insn) = prologue_locator; | ||
| 30 | + | ||
| 31 | /* We can be called during expansion of PHI nodes, where | ||
| 32 | we can't yet emit instructions directly in the final | ||
| 33 | insn stream. Queue the insns on the entry edge, they will | ||
| 34 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99450.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99450.patch deleted file mode 100644 index 49fa07fca..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99450.patch +++ /dev/null | |||
| @@ -1,104 +0,0 @@ | |||
| 1 | 2010-12-21 Ulrich Weigand <uweigand@de.ibm.com> | ||
| 2 | |||
| 3 | LP: #662324 | ||
| 4 | Backport from mainline: | ||
| 5 | |||
| 6 | 2010-12-17 Dodji Seketeli <dodji@redhat.com> | ||
| 7 | |||
| 8 | gcc/ | ||
| 9 | * dwarf2out.c (gen_type_die_with_usage): Do not try to emit debug | ||
| 10 | info for a redundant typedef that has DECL_ORIGINAL_TYPE set. Use | ||
| 11 | that underlying type instead. | ||
| 12 | |||
| 13 | gcc/testsuite/ | ||
| 14 | * g++.dg/debug/dwarf2/self-ref-1.C: New test. | ||
| 15 | * g++.dg/debug/dwarf2/self-ref-2.C: Likewise. | ||
| 16 | |||
| 17 | === modified file 'gcc/dwarf2out.c' | ||
| 18 | --- old/gcc/dwarf2out.c 2010-10-04 00:50:43 +0000 | ||
| 19 | +++ new/gcc/dwarf2out.c 2010-12-21 18:46:10 +0000 | ||
| 20 | @@ -18993,6 +18993,16 @@ | ||
| 21 | if (type == NULL_TREE || type == error_mark_node) | ||
| 22 | return; | ||
| 23 | |||
| 24 | + if (TYPE_NAME (type) != NULL_TREE | ||
| 25 | + && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL | ||
| 26 | + && is_redundant_typedef (TYPE_NAME (type)) | ||
| 27 | + && DECL_ORIGINAL_TYPE (TYPE_NAME (type))) | ||
| 28 | + /* The DECL of this type is a typedef we don't want to emit debug | ||
| 29 | + info for but we want debug info for its underlying typedef. | ||
| 30 | + This can happen for e.g, the injected-class-name of a C++ | ||
| 31 | + type. */ | ||
| 32 | + type = DECL_ORIGINAL_TYPE (TYPE_NAME (type)); | ||
| 33 | + | ||
| 34 | /* If TYPE is a typedef type variant, let's generate debug info | ||
| 35 | for the parent typedef which TYPE is a type of. */ | ||
| 36 | if (TYPE_NAME (type) && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL | ||
| 37 | |||
| 38 | === added file 'gcc/testsuite/g++.dg/debug/dwarf2/self-ref-1.C' | ||
| 39 | --- old/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-1.C 1970-01-01 00:00:00 +0000 | ||
| 40 | +++ new/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-1.C 2010-12-21 18:46:10 +0000 | ||
| 41 | @@ -0,0 +1,28 @@ | ||
| 42 | +// Origin: PR debug/45088 | ||
| 43 | +// { dg-do compile } | ||
| 44 | +// { dg-options "-g -dA" } | ||
| 45 | +// { dg-final { scan-assembler-times "\[^\n\r\]*\\(DIE\[^\n\r\]*DW_TAG_pointer_type\\)\[\n\r\]{1,2}\[^\n\r\]*DW_AT_byte_size\[\n\r\]{1,2}\[^\n\r\]*DW_AT_type" 4 } } | ||
| 46 | + | ||
| 47 | +struct A | ||
| 48 | +{ | ||
| 49 | + virtual ~A(); | ||
| 50 | +}; | ||
| 51 | + | ||
| 52 | +struct B : public A | ||
| 53 | +{ | ||
| 54 | + virtual ~B(){} | ||
| 55 | +}; | ||
| 56 | + | ||
| 57 | +struct C : public B | ||
| 58 | +{ | ||
| 59 | + A* a1; | ||
| 60 | +}; | ||
| 61 | + | ||
| 62 | +int | ||
| 63 | +main() | ||
| 64 | +{ | ||
| 65 | + C c; | ||
| 66 | + c.a1 = 0; | ||
| 67 | + return 0; | ||
| 68 | +} | ||
| 69 | + | ||
| 70 | |||
| 71 | === added file 'gcc/testsuite/g++.dg/debug/dwarf2/self-ref-2.C' | ||
| 72 | --- old/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-2.C 1970-01-01 00:00:00 +0000 | ||
| 73 | +++ new/gcc/testsuite/g++.dg/debug/dwarf2/self-ref-2.C 2010-12-21 18:46:10 +0000 | ||
| 74 | @@ -0,0 +1,29 @@ | ||
| 75 | +// Origin: PR debug/45088 | ||
| 76 | +// { dg-do compile } | ||
| 77 | +// { dg-options "-g -dA" } | ||
| 78 | +// { dg-final { scan-assembler-times "\[^\n\r\]*\\(DIE\[^\n\r\]*DW_TAG_pointer_type\\)\[\n\r\]{1,2}\[^\n\r\]*DW_AT_byte_size\[\n\r\]{1,2}\[^\n\r\]*DW_AT_type" 4 } } | ||
| 79 | + | ||
| 80 | +template<class T> | ||
| 81 | +struct A | ||
| 82 | +{ | ||
| 83 | + virtual ~A(); | ||
| 84 | +}; | ||
| 85 | + | ||
| 86 | +struct B : public A<int> | ||
| 87 | +{ | ||
| 88 | + virtual ~B(){} | ||
| 89 | +}; | ||
| 90 | + | ||
| 91 | +struct C : public B | ||
| 92 | +{ | ||
| 93 | + A<int>* a1; | ||
| 94 | +}; | ||
| 95 | + | ||
| 96 | +int | ||
| 97 | +main() | ||
| 98 | +{ | ||
| 99 | + C c; | ||
| 100 | + c.a1 = 0; | ||
| 101 | + return 0; | ||
| 102 | +} | ||
| 103 | + | ||
| 104 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99451.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99451.patch deleted file mode 100644 index d87c312d0..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99451.patch +++ /dev/null | |||
| @@ -1,45 +0,0 @@ | |||
| 1 | 2010-12-22 Ulrich Weigand <uweigand@de.ibm.com> | ||
| 2 | |||
| 3 | LP: #693425 | ||
| 4 | Backport from mainline: | ||
| 5 | |||
| 6 | gcc/ | ||
| 7 | * config/spu/spu.md ("mov<mode>"): Use nonimmediate_operand | ||
| 8 | predicate for destination operand. | ||
| 9 | * config/spu/spu.c (spu_expand_mov): If move destination is an | ||
| 10 | invalid subreg, perform move in the subreg's inner mode instead. | ||
| 11 | |||
| 12 | === modified file 'gcc/config/spu/spu.c' | ||
| 13 | --- old/gcc/config/spu/spu.c 2010-08-04 09:53:04 +0000 | ||
| 14 | +++ new/gcc/config/spu/spu.c 2010-12-22 15:20:44 +0000 | ||
| 15 | @@ -4572,7 +4572,13 @@ | ||
| 16 | spu_expand_mov (rtx * ops, enum machine_mode mode) | ||
| 17 | { | ||
| 18 | if (GET_CODE (ops[0]) == SUBREG && !valid_subreg (ops[0])) | ||
| 19 | - abort (); | ||
| 20 | + { | ||
| 21 | + /* Perform the move in the destination SUBREG's inner mode. */ | ||
| 22 | + ops[0] = SUBREG_REG (ops[0]); | ||
| 23 | + mode = GET_MODE (ops[0]); | ||
| 24 | + ops[1] = gen_lowpart_common (mode, ops[1]); | ||
| 25 | + gcc_assert (ops[1]); | ||
| 26 | + } | ||
| 27 | |||
| 28 | if (GET_CODE (ops[1]) == SUBREG && !valid_subreg (ops[1])) | ||
| 29 | { | ||
| 30 | |||
| 31 | === modified file 'gcc/config/spu/spu.md' | ||
| 32 | --- old/gcc/config/spu/spu.md 2009-05-23 01:28:14 +0000 | ||
| 33 | +++ new/gcc/config/spu/spu.md 2010-12-22 15:20:44 +0000 | ||
| 34 | @@ -269,8 +269,8 @@ | ||
| 35 | ;; mov | ||
| 36 | |||
| 37 | (define_expand "mov<mode>" | ||
| 38 | - [(set (match_operand:ALL 0 "spu_nonimm_operand" "=r,r,r,m") | ||
| 39 | - (match_operand:ALL 1 "general_operand" "r,i,m,r"))] | ||
| 40 | + [(set (match_operand:ALL 0 "nonimmediate_operand" "") | ||
| 41 | + (match_operand:ALL 1 "general_operand" ""))] | ||
| 42 | "" | ||
| 43 | { | ||
| 44 | if (spu_expand_mov(operands, <MODE>mode)) | ||
| 45 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99452.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99452.patch deleted file mode 100644 index 6cfc01fef..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99452.patch +++ /dev/null | |||
| @@ -1,201 +0,0 @@ | |||
| 1 | 2010-12-14 Sandra Loosemore <sandra@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2010-12-14 Jakub Jelinek <jakub@redhat.com> | ||
| 6 | |||
| 7 | PR tree-optimization/46909 | ||
| 8 | |||
| 9 | gcc/ | ||
| 10 | * tree-ssa-ccp.c (and_var_with_comparison_1): Save partial | ||
| 11 | result even in the is_and case, if both partial results | ||
| 12 | are the same, return it. | ||
| 13 | (or_var_with_comparison_1): Use is_or predicate instead of | ||
| 14 | innercode == TRUTH_OR_EXPR test. Save partial result | ||
| 15 | even in the is_or case, if both partial results are the | ||
| 16 | same, return it. In the !is_or case when both partial | ||
| 17 | results are the same, return the partial result instead | ||
| 18 | of boolean_true_node. | ||
| 19 | |||
| 20 | gcc/testsuite/ | ||
| 21 | * gcc.c-torture/execute/pr46909-1.c: New test. | ||
| 22 | * gcc.c-torture/execute/pr46909-2.c: New test. | ||
| 23 | * gcc.dg/pr46909.c: New test. | ||
| 24 | |||
| 25 | === added file 'gcc/testsuite/gcc.c-torture/execute/pr46909-1.c' | ||
| 26 | --- old/gcc/testsuite/gcc.c-torture/execute/pr46909-1.c 1970-01-01 00:00:00 +0000 | ||
| 27 | +++ new/gcc/testsuite/gcc.c-torture/execute/pr46909-1.c 2011-01-05 11:27:00 +0000 | ||
| 28 | @@ -0,0 +1,22 @@ | ||
| 29 | +/* PR tree-optimization/46909 */ | ||
| 30 | + | ||
| 31 | +extern void abort (); | ||
| 32 | + | ||
| 33 | +int | ||
| 34 | +__attribute__ ((__noinline__)) | ||
| 35 | +foo (unsigned int x) | ||
| 36 | +{ | ||
| 37 | + if (! (x == 4 || x == 6) || (x == 2 || x == 6)) | ||
| 38 | + return 1; | ||
| 39 | + return -1; | ||
| 40 | +} | ||
| 41 | + | ||
| 42 | +int | ||
| 43 | +main () | ||
| 44 | +{ | ||
| 45 | + int i; | ||
| 46 | + for (i = -10; i < 10; i++) | ||
| 47 | + if (foo (i) != 1 - 2 * (i == 4)) | ||
| 48 | + abort (); | ||
| 49 | + return 0; | ||
| 50 | +} | ||
| 51 | |||
| 52 | === added file 'gcc/testsuite/gcc.c-torture/execute/pr46909-2.c' | ||
| 53 | --- old/gcc/testsuite/gcc.c-torture/execute/pr46909-2.c 1970-01-01 00:00:00 +0000 | ||
| 54 | +++ new/gcc/testsuite/gcc.c-torture/execute/pr46909-2.c 2011-01-05 11:27:00 +0000 | ||
| 55 | @@ -0,0 +1,22 @@ | ||
| 56 | +/* PR tree-optimization/46909 */ | ||
| 57 | + | ||
| 58 | +extern void abort (void); | ||
| 59 | + | ||
| 60 | +int | ||
| 61 | +__attribute__((noinline)) | ||
| 62 | +foo (int x) | ||
| 63 | +{ | ||
| 64 | + if ((x != 0 && x != 13) || x == 5 || x == 20) | ||
| 65 | + return 1; | ||
| 66 | + return -1; | ||
| 67 | +} | ||
| 68 | + | ||
| 69 | +int | ||
| 70 | +main (void) | ||
| 71 | +{ | ||
| 72 | + int i; | ||
| 73 | + for (i = -10; i < 30; i++) | ||
| 74 | + if (foo (i) != 1 - 2 * (i == 0) - 2 * (i == 13)) | ||
| 75 | + abort (); | ||
| 76 | + return 0; | ||
| 77 | +} | ||
| 78 | |||
| 79 | === added file 'gcc/testsuite/gcc.dg/pr46909.c' | ||
| 80 | --- old/gcc/testsuite/gcc.dg/pr46909.c 1970-01-01 00:00:00 +0000 | ||
| 81 | +++ new/gcc/testsuite/gcc.dg/pr46909.c 2011-01-05 11:27:00 +0000 | ||
| 82 | @@ -0,0 +1,17 @@ | ||
| 83 | +/* PR tree-optimization/46909 */ | ||
| 84 | +/* { dg-do compile } */ | ||
| 85 | +/* { dg-options "-O2 -fdump-tree-ifcombine" } */ | ||
| 86 | + | ||
| 87 | +extern void abort (); | ||
| 88 | + | ||
| 89 | +int | ||
| 90 | +__attribute__ ((__noinline__)) | ||
| 91 | +foo (unsigned int x) | ||
| 92 | +{ | ||
| 93 | + if (! (x == 4 || x == 6) || (x == 2 || x == 6)) | ||
| 94 | + return 1; | ||
| 95 | + return -1; | ||
| 96 | +} | ||
| 97 | + | ||
| 98 | +/* { dg-final { scan-tree-dump "optimizing two comparisons to x_\[0-9\]+\\(D\\) != 4" "ifcombine" } } */ | ||
| 99 | +/* { dg-final { cleanup-tree-dump "ifcombine" } } */ | ||
| 100 | |||
| 101 | === modified file 'gcc/tree-ssa-ccp.c' | ||
| 102 | --- old/gcc/tree-ssa-ccp.c 2010-09-16 09:15:46 +0000 | ||
| 103 | +++ new/gcc/tree-ssa-ccp.c 2011-01-05 11:27:00 +0000 | ||
| 104 | @@ -3508,14 +3508,11 @@ | ||
| 105 | /* Handle the OR case, where we are redistributing: | ||
| 106 | (inner1 OR inner2) AND (op2a code2 op2b) | ||
| 107 | => (t OR (inner2 AND (op2a code2 op2b))) */ | ||
| 108 | - else | ||
| 109 | - { | ||
| 110 | - if (integer_onep (t)) | ||
| 111 | - return boolean_true_node; | ||
| 112 | - else | ||
| 113 | - /* Save partial result for later. */ | ||
| 114 | - partial = t; | ||
| 115 | - } | ||
| 116 | + else if (integer_onep (t)) | ||
| 117 | + return boolean_true_node; | ||
| 118 | + | ||
| 119 | + /* Save partial result for later. */ | ||
| 120 | + partial = t; | ||
| 121 | } | ||
| 122 | |||
| 123 | /* Compute the second partial result, (inner2 AND (op2a code op2b)) */ | ||
| 124 | @@ -3536,6 +3533,10 @@ | ||
| 125 | return inner1; | ||
| 126 | else if (integer_zerop (t)) | ||
| 127 | return boolean_false_node; | ||
| 128 | + /* If both are the same, we can apply the identity | ||
| 129 | + (x AND x) == x. */ | ||
| 130 | + else if (partial && same_bool_result_p (t, partial)) | ||
| 131 | + return t; | ||
| 132 | } | ||
| 133 | |||
| 134 | /* Handle the OR case. where we are redistributing: | ||
| 135 | @@ -3945,7 +3946,7 @@ | ||
| 136 | => (t OR inner2) | ||
| 137 | If the partial result t is a constant, we win. Otherwise | ||
| 138 | continue on to try reassociating with the other inner test. */ | ||
| 139 | - if (innercode == TRUTH_OR_EXPR) | ||
| 140 | + if (is_or) | ||
| 141 | { | ||
| 142 | if (integer_onep (t)) | ||
| 143 | return boolean_true_node; | ||
| 144 | @@ -3956,14 +3957,11 @@ | ||
| 145 | /* Handle the AND case, where we are redistributing: | ||
| 146 | (inner1 AND inner2) OR (op2a code2 op2b) | ||
| 147 | => (t AND (inner2 OR (op2a code op2b))) */ | ||
| 148 | - else | ||
| 149 | - { | ||
| 150 | - if (integer_zerop (t)) | ||
| 151 | - return boolean_false_node; | ||
| 152 | - else | ||
| 153 | - /* Save partial result for later. */ | ||
| 154 | - partial = t; | ||
| 155 | - } | ||
| 156 | + else if (integer_zerop (t)) | ||
| 157 | + return boolean_false_node; | ||
| 158 | + | ||
| 159 | + /* Save partial result for later. */ | ||
| 160 | + partial = t; | ||
| 161 | } | ||
| 162 | |||
| 163 | /* Compute the second partial result, (inner2 OR (op2a code op2b)) */ | ||
| 164 | @@ -3977,13 +3975,18 @@ | ||
| 165 | { | ||
| 166 | /* Handle the OR case, where we are reassociating: | ||
| 167 | (inner1 OR inner2) OR (op2a code2 op2b) | ||
| 168 | - => (inner1 OR t) */ | ||
| 169 | - if (innercode == TRUTH_OR_EXPR) | ||
| 170 | + => (inner1 OR t) | ||
| 171 | + => (t OR partial) */ | ||
| 172 | + if (is_or) | ||
| 173 | { | ||
| 174 | if (integer_zerop (t)) | ||
| 175 | return inner1; | ||
| 176 | else if (integer_onep (t)) | ||
| 177 | return boolean_true_node; | ||
| 178 | + /* If both are the same, we can apply the identity | ||
| 179 | + (x OR x) == x. */ | ||
| 180 | + else if (partial && same_bool_result_p (t, partial)) | ||
| 181 | + return t; | ||
| 182 | } | ||
| 183 | |||
| 184 | /* Handle the AND case, where we are redistributing: | ||
| 185 | @@ -4000,13 +4003,13 @@ | ||
| 186 | operand to the redistributed AND expression. The | ||
| 187 | interesting case is when at least one is true. | ||
| 188 | Or, if both are the same, we can apply the identity | ||
| 189 | - (x AND x) == true. */ | ||
| 190 | + (x AND x) == x. */ | ||
| 191 | if (integer_onep (partial)) | ||
| 192 | return t; | ||
| 193 | else if (integer_onep (t)) | ||
| 194 | return partial; | ||
| 195 | else if (same_bool_result_p (t, partial)) | ||
| 196 | - return boolean_true_node; | ||
| 197 | + return t; | ||
| 198 | } | ||
| 199 | } | ||
| 200 | } | ||
| 201 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99453.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99453.patch deleted file mode 100644 index 8eb35325e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99453.patch +++ /dev/null | |||
| @@ -1,72 +0,0 @@ | |||
| 1 | 2010-12-17 Bernd Schmidt <bernds@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #10208 | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * config/arm/arm.c (arm_select_cc_mode): Before calling | ||
| 7 | arm_select_dominance_cc_mode for AND or IOR operations, ensure | ||
| 8 | that op is NE or EQ. | ||
| 9 | |||
| 10 | gcc/testsuite/ | ||
| 11 | * gcc.c-torture/compile/20101217-1.c: New test. | ||
| 12 | |||
| 13 | === modified file 'gcc/config/arm/arm.c' | ||
| 14 | --- old/gcc/config/arm/arm.c 2010-12-21 14:13:38 +0000 | ||
| 15 | +++ new/gcc/config/arm/arm.c 2011-01-05 11:32:50 +0000 | ||
| 16 | @@ -10609,12 +10609,14 @@ | ||
| 17 | |||
| 18 | /* Alternate canonicalizations of the above. These are somewhat cleaner. */ | ||
| 19 | if (GET_CODE (x) == AND | ||
| 20 | + && (op == EQ || op == NE) | ||
| 21 | && COMPARISON_P (XEXP (x, 0)) | ||
| 22 | && COMPARISON_P (XEXP (x, 1))) | ||
| 23 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), | ||
| 24 | DOM_CC_X_AND_Y); | ||
| 25 | |||
| 26 | if (GET_CODE (x) == IOR | ||
| 27 | + && (op == EQ || op == NE) | ||
| 28 | && COMPARISON_P (XEXP (x, 0)) | ||
| 29 | && COMPARISON_P (XEXP (x, 1))) | ||
| 30 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), | ||
| 31 | |||
| 32 | === added file 'gcc/testsuite/gcc.c-torture/compile/20101217-1.c' | ||
| 33 | --- old/gcc/testsuite/gcc.c-torture/compile/20101217-1.c 1970-01-01 00:00:00 +0000 | ||
| 34 | +++ new/gcc/testsuite/gcc.c-torture/compile/20101217-1.c 2011-01-05 11:32:50 +0000 | ||
| 35 | @@ -0,0 +1,36 @@ | ||
| 36 | +/* Testcase provided by HUAWEI. */ | ||
| 37 | +#include <stdio.h> | ||
| 38 | +int main() | ||
| 39 | +{ | ||
| 40 | + int cur_k; | ||
| 41 | + int cur_j=0; | ||
| 42 | + int cur_i=28; | ||
| 43 | + unsigned char temp_data[8]; | ||
| 44 | + unsigned int Data_Size=20; | ||
| 45 | + | ||
| 46 | + for (cur_k=0;cur_j<7;cur_j++,cur_i++) { | ||
| 47 | + if (cur_j%2==0) { | ||
| 48 | + temp_data[cur_k++]=0; | ||
| 49 | + } | ||
| 50 | + if (cur_k==7) { | ||
| 51 | + for (;cur_k>0;cur_k--) { | ||
| 52 | + if (cur_k>2) { | ||
| 53 | + if ((temp_data[7-cur_k]=='n' || temp_data[7-cur_k]=='N' ) && (temp_data[7-cur_k+1]=='a' || temp_data[7-cur_k+1]=='A' )) { | ||
| 54 | + break; | ||
| 55 | + } | ||
| 56 | + } | ||
| 57 | + if (cur_k==1) { | ||
| 58 | + if (temp_data[7-cur_k]=='n' || temp_data[7-cur_k]=='N' ) { | ||
| 59 | + break; | ||
| 60 | + } | ||
| 61 | + } | ||
| 62 | + } | ||
| 63 | + if (cur_k==7) { | ||
| 64 | + } else { | ||
| 65 | + if (cur_k>0) | ||
| 66 | + printf("dfjk"); | ||
| 67 | + } | ||
| 68 | + } | ||
| 69 | + } | ||
| 70 | +return 0; | ||
| 71 | +} | ||
| 72 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99454.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99454.patch deleted file mode 100644 index 8aa06cc51..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99454.patch +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | 2010-12-18 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | 2010-12-17 Andrew Stubbs <ams@codesourcery.com> | ||
| 7 | |||
| 8 | * config/arm/arm.md (maddhisi4, *maddhidi4): Use the canonical | ||
| 9 | operand order for plus. | ||
| 10 | Drop redundant % from constraints. | ||
| 11 | |||
| 12 | === modified file 'gcc/config/arm/arm.md' | ||
| 13 | --- old/gcc/config/arm/arm.md 2010-11-11 11:12:14 +0000 | ||
| 14 | +++ new/gcc/config/arm/arm.md 2011-01-05 11:42:19 +0000 | ||
| 15 | @@ -1791,11 +1791,11 @@ | ||
| 16 | |||
| 17 | (define_insn "maddhisi4" | ||
| 18 | [(set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 19 | - (plus:SI (match_operand:SI 3 "s_register_operand" "r") | ||
| 20 | - (mult:SI (sign_extend:SI | ||
| 21 | - (match_operand:HI 1 "s_register_operand" "%r")) | ||
| 22 | + (plus:SI (mult:SI (sign_extend:SI | ||
| 23 | + (match_operand:HI 1 "s_register_operand" "r")) | ||
| 24 | (sign_extend:SI | ||
| 25 | - (match_operand:HI 2 "s_register_operand" "r")))))] | ||
| 26 | + (match_operand:HI 2 "s_register_operand" "r"))) | ||
| 27 | + (match_operand:SI 3 "s_register_operand" "r")))] | ||
| 28 | "TARGET_DSP_MULTIPLY" | ||
| 29 | "smlabb%?\\t%0, %1, %2, %3" | ||
| 30 | [(set_attr "insn" "smlaxy") | ||
| 31 | @@ -1805,11 +1805,11 @@ | ||
| 32 | (define_insn "*maddhidi4" | ||
| 33 | [(set (match_operand:DI 0 "s_register_operand" "=r") | ||
| 34 | (plus:DI | ||
| 35 | - (match_operand:DI 3 "s_register_operand" "0") | ||
| 36 | (mult:DI (sign_extend:DI | ||
| 37 | - (match_operand:HI 1 "s_register_operand" "%r")) | ||
| 38 | + (match_operand:HI 1 "s_register_operand" "r")) | ||
| 39 | (sign_extend:DI | ||
| 40 | - (match_operand:HI 2 "s_register_operand" "r")))))] | ||
| 41 | + (match_operand:HI 2 "s_register_operand" "r"))) | ||
| 42 | + (match_operand:DI 3 "s_register_operand" "0")))] | ||
| 43 | "TARGET_DSP_MULTIPLY" | ||
| 44 | "smlalbb%?\\t%Q0, %R0, %1, %2" | ||
| 45 | [(set_attr "insn" "smlalxy") | ||
| 46 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99455.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99455.patch deleted file mode 100644 index 5e8383a7d..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99455.patch +++ /dev/null | |||
| @@ -1,65 +0,0 @@ | |||
| 1 | 2010-12-21 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #10201 | ||
| 4 | |||
| 5 | Backport from mainline: | ||
| 6 | |||
| 7 | 2010-12-16 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 8 | |||
| 9 | PR target/46883 | ||
| 10 | gcc/ | ||
| 11 | * config/arm/arm.md | ||
| 12 | (zero_extendhisi2 for register input splitter): Change | ||
| 13 | "register_operand" to "s_register_operand". | ||
| 14 | (zero_extendqisi2 for register input splitter): Same. | ||
| 15 | |||
| 16 | gcc/testsuite/ | ||
| 17 | * gcc.target/arm/pr46883.c: New testcase. | ||
| 18 | |||
| 19 | === modified file 'gcc/config/arm/arm.md' | ||
| 20 | --- old/gcc/config/arm/arm.md 2011-01-05 11:42:19 +0000 | ||
| 21 | +++ new/gcc/config/arm/arm.md 2011-01-05 11:52:16 +0000 | ||
| 22 | @@ -4114,8 +4114,8 @@ | ||
| 23 | }) | ||
| 24 | |||
| 25 | (define_split | ||
| 26 | - [(set (match_operand:SI 0 "register_operand" "") | ||
| 27 | - (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] | ||
| 28 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 29 | + (zero_extend:SI (match_operand:HI 1 "s_register_operand" "")))] | ||
| 30 | "!TARGET_THUMB2 && !arm_arch6" | ||
| 31 | [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) | ||
| 32 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))] | ||
| 33 | @@ -4234,8 +4234,8 @@ | ||
| 34 | }) | ||
| 35 | |||
| 36 | (define_split | ||
| 37 | - [(set (match_operand:SI 0 "register_operand" "") | ||
| 38 | - (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] | ||
| 39 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 40 | + (zero_extend:SI (match_operand:QI 1 "s_register_operand" "")))] | ||
| 41 | "!arm_arch6" | ||
| 42 | [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24))) | ||
| 43 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | ||
| 44 | |||
| 45 | === added file 'gcc/testsuite/gcc.target/arm/pr46883.c' | ||
| 46 | --- old/gcc/testsuite/gcc.target/arm/pr46883.c 1970-01-01 00:00:00 +0000 | ||
| 47 | +++ new/gcc/testsuite/gcc.target/arm/pr46883.c 2011-01-05 11:52:16 +0000 | ||
| 48 | @@ -0,0 +1,16 @@ | ||
| 49 | +/* { dg-do compile } */ | ||
| 50 | +/* { dg-options "-O1 -march=armv5te" } */ | ||
| 51 | + | ||
| 52 | +void bar (unsigned char *q, unsigned short *data16s, int len) | ||
| 53 | +{ | ||
| 54 | + int i; | ||
| 55 | + | ||
| 56 | + for (i = 0; i < len; i++) | ||
| 57 | + { | ||
| 58 | + q[2 * i] = | ||
| 59 | + (((data16s[i] & 0xFF) << 8) | ((data16s[i] >> 8) & 0xFF)) & 0xFF; | ||
| 60 | + q[2 * i + 1] = | ||
| 61 | + ((unsigned short) | ||
| 62 | + (((data16s[i] & 0xFF) << 8) | ((data16s[i] >> 8) & 0xFF))) >> 8; | ||
| 63 | + } | ||
| 64 | +} | ||
| 65 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99456.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99456.patch deleted file mode 100644 index 35f98d24a..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99456.patch +++ /dev/null | |||
| @@ -1,3163 +0,0 @@ | |||
| 1 | 2011-01-03 Bernd Schmidt <bernds@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * doc/tm.texi (RETURN_ADDR_REGNUM): Document. | ||
| 5 | * doc/md.texi (simple_return): Document pattern. | ||
| 6 | (return): Add a sentence to clarify. | ||
| 7 | * doc/rtl.texi (simple_return): Document. | ||
| 8 | * doc/invoke.texi (Optimize Options): Document -fshrink-wrap. | ||
| 9 | * common.opt (fshrink-wrap): New. | ||
| 10 | * opts.c (decode_options): Set it for -O2 and above. | ||
| 11 | * gengenrtl.c (special_rtx): PC, CC0, RETURN and SIMPLE_RETURN | ||
| 12 | are special. | ||
| 13 | * rtl.h (ANY_RETURN_P): New macro. | ||
| 14 | (global_rtl_index): Add GR_RETURN and GR_SIMPLE_RETURN. | ||
| 15 | (ret_rtx, simple_return_rtx): New macros. | ||
| 16 | * genemit.c (gen_exp): RETURN and SIMPLE_RETURN have unique rtxs. | ||
| 17 | (gen_expand, gen_split): Use ANY_RETURN_P. | ||
| 18 | * rtl.c (copy_rtx): RETURN and SIMPLE_RETURN are shared. | ||
| 19 | * emit-rtl.c (verify_rtx_sharing): Likewise. | ||
| 20 | (skip_consecutive_labels): Return the argument if it is a return rtx. | ||
| 21 | (classify_insn): Handle both kinds of return. | ||
| 22 | (init_emit_regs): Create global rtl for ret_rtx and simple_return_rtx. | ||
| 23 | * df-scan.c (df_uses_record): Handle SIMPLE_RETURN. | ||
| 24 | * rtl.def (SIMPLE_RETURN): New. | ||
| 25 | * rtlanal.c (tablejump_p): Check JUMP_LABEL for returns. | ||
| 26 | * final.c (final_scan_insn): Recognize both kinds of return. | ||
| 27 | * reorg.c (function_return_label, function_simple_return_label): New | ||
| 28 | static variables. | ||
| 29 | (end_of_function_label): Remove. | ||
| 30 | (simplejump_or_return_p): New static function. | ||
| 31 | (find_end_label): Add a new arg, KIND. All callers changed. | ||
| 32 | Depending on KIND, look for a label suitable for return or | ||
| 33 | simple_return. | ||
| 34 | (make_return_insns): Make corresponding changes. | ||
| 35 | (get_jump_flags): Check JUMP_LABELs for returns. | ||
| 36 | (follow_jumps): Likewise. | ||
| 37 | (get_branch_condition): Check target for return patterns rather | ||
| 38 | than NULL. | ||
| 39 | (own_thread_p): Likewise for thread. | ||
| 40 | (steal_delay_list_from_target): Check JUMP_LABELs for returns. | ||
| 41 | Use simplejump_or_return_p. | ||
| 42 | (fill_simple_delay_slots): Likewise. | ||
| 43 | (optimize_skip): Likewise. | ||
| 44 | (fill_slots_from_thread): Likewise. | ||
| 45 | (relax_delay_slots): Likewise. | ||
| 46 | (dbr_schedule): Adjust handling of end_of_function_label for the | ||
| 47 | two new variables. | ||
| 48 | * ifcvt.c (find_if_case_1): Take care when redirecting jumps to the | ||
| 49 | exit block. | ||
| 50 | (dead_or_predicable): Change NEW_DEST arg to DEST_EDGE. All callers | ||
| 51 | changed. Ensure that the right label is passed to redirect_jump. | ||
| 52 | * jump.c (condjump_p, condjump_in_parallel_p, any_condjump_p, | ||
| 53 | returnjump_p): Handle SIMPLE_RETURNs. | ||
| 54 | (delete_related_insns): Check JUMP_LABEL for returns. | ||
| 55 | (redirect_target): New static function. | ||
| 56 | (redirect_exp_1): Use it. Handle any kind of return rtx as a label | ||
| 57 | rather than interpreting NULL as a return. | ||
| 58 | (redirect_jump_1): Assert that nlabel is not NULL. | ||
| 59 | (redirect_jump): Likewise. | ||
| 60 | (redirect_jump_2): Handle any kind of return rtx as a label rather | ||
| 61 | than interpreting NULL as a return. | ||
| 62 | * dwarf2out.c (compute_barrier_args_size_1): Check JUMP_LABEL for | ||
| 63 | returns. | ||
| 64 | * function.c (emit_return_into_block): Remove useless declaration. | ||
| 65 | (record_hard_reg_sets, frame_required_for_rtx, gen_return_pattern, | ||
| 66 | requires_stack_frame_p): New static functions. | ||
| 67 | (emit_return_into_block): New arg SIMPLE_P. All callers changed. | ||
| 68 | Generate either kind of return pattern and update the JUMP_LABEL. | ||
| 69 | (thread_prologue_and_epilogue_insns): Implement a form of | ||
| 70 | shrink-wrapping. Ensure JUMP_LABELs for return insns are set. | ||
| 71 | * print-rtl.c (print_rtx): Handle returns in JUMP_LABELs. | ||
| 72 | * cfglayout.c (fixup_reorder_chain): Ensure JUMP_LABELs for returns | ||
| 73 | remain correct. | ||
| 74 | * resource.c (find_dead_or_set_registers): Check JUMP_LABELs for | ||
| 75 | returns. | ||
| 76 | (mark_target_live_regs): Don't pass a return rtx to next_active_insn. | ||
| 77 | * basic-block.h (force_nonfallthru_and_redirect): Declare. | ||
| 78 | * sched-vis.c (print_pattern): Add case for SIMPLE_RETURN. | ||
| 79 | * cfgrtl.c (force_nonfallthru_and_redirect): No longer static. New arg | ||
| 80 | JUMP_LABEL. All callers changed. Use the label when generating | ||
| 81 | return insns. | ||
| 82 | |||
| 83 | * config/i386/i386.md (returns, return_str, return_cond): New | ||
| 84 | code_iterator and corresponding code_attrs. | ||
| 85 | (<return_str>return): Renamed from return and adapted. | ||
| 86 | (<return_str>return_internal): Likewise for return_internal. | ||
| 87 | (<return_str>return_internal_long): Likewise for return_internal_long. | ||
| 88 | (<return_str>return_pop_internal): Likewise for return_pop_internal. | ||
| 89 | (<return_str>return_indirect_internal): Likewise for | ||
| 90 | return_indirect_internal. | ||
| 91 | * config/i386/i386.c (ix86_expand_epilogue): Expand a simple_return as | ||
| 92 | the last insn. | ||
| 93 | (ix86_pad_returns): Handle both kinds of return rtx. | ||
| 94 | * config/arm/arm.c (use_simple_return_p): new function. | ||
| 95 | (is_jump_table): Handle returns in JUMP_LABELs. | ||
| 96 | (output_return_instruction): New arg SIMPLE. All callers changed. | ||
| 97 | Use it to determine which kind of return to generate. | ||
| 98 | (arm_final_prescan_insn): Handle both kinds of return. | ||
| 99 | * config/arm/arm.md (returns, return_str, return_simple_p, | ||
| 100 | return_cond): New code_iterator and corresponding code_attrs. | ||
| 101 | (<return_str>return): Renamed from return and adapted. | ||
| 102 | (arm_<return_str>return): Renamed from arm_return and adapted. | ||
| 103 | (cond_<return_str>return): Renamed from cond_return and adapted. | ||
| 104 | (cond_<return_str>return_inverted): Renamed from cond_return_inverted | ||
| 105 | and adapted. | ||
| 106 | (epilogue): Use ret_rtx instead of gen_rtx_RETURN. | ||
| 107 | * config/arm/thumb2.md (thumb2_<return_str>return): Renamed from | ||
| 108 | thumb2_return and adapted. | ||
| 109 | * config/arm/arm.h (RETURN_ADDR_REGNUM): Define. | ||
| 110 | * config/arm/arm-protos.h (use_simple_return_p): Declare. | ||
| 111 | (output_return_instruction): Adjust declaration. | ||
| 112 | * config/mips/mips.c (mips_expand_epilogue): Generate a simple_return | ||
| 113 | as final insn. | ||
| 114 | * config/mips/mips.md (simple_return): New expander. | ||
| 115 | (*simple_return, simple_return_internal): New patterns. | ||
| 116 | * config/sh/sh.c (barrier_align): Handle return in a JUMP_LABEL. | ||
| 117 | (split_branches): Don't pass a null label to redirect_jump. | ||
| 118 | |||
| 119 | From mainline: | ||
| 120 | * vec.h (FOR_EACH_VEC_ELT, FOR_EACH_VEC_ELT_REVERSE): New macros. | ||
| 121 | * haifa-sched.c (find_fallthru_edge_from): Rename from | ||
| 122 | find_fallthru_edge. All callers changed. | ||
| 123 | * sched-int.h (find_fallthru_edge_from): Rename declaration as well. | ||
| 124 | * basic-block.h (find_fallthru_edge): New inline function. | ||
| 125 | |||
| 126 | === modified file 'gcc/basic-block.h' | ||
| 127 | --- old/gcc/basic-block.h 2010-09-01 13:29:58 +0000 | ||
| 128 | +++ new/gcc/basic-block.h 2011-01-05 12:12:18 +0000 | ||
| 129 | @@ -884,6 +884,7 @@ | ||
| 130 | |||
| 131 | /* In cfgrtl.c */ | ||
| 132 | extern basic_block force_nonfallthru (edge); | ||
| 133 | +extern basic_block force_nonfallthru_and_redirect (edge, basic_block, rtx); | ||
| 134 | extern rtx block_label (basic_block); | ||
| 135 | extern bool purge_all_dead_edges (void); | ||
| 136 | extern bool purge_dead_edges (basic_block); | ||
| 137 | @@ -1004,6 +1005,20 @@ | ||
| 138 | return false; | ||
| 139 | } | ||
| 140 | |||
| 141 | +/* Return the fallthru edge in EDGES if it exists, NULL otherwise. */ | ||
| 142 | +static inline edge | ||
| 143 | +find_fallthru_edge (VEC(edge,gc) *edges) | ||
| 144 | +{ | ||
| 145 | + edge e; | ||
| 146 | + edge_iterator ei; | ||
| 147 | + | ||
| 148 | + FOR_EACH_EDGE (e, ei, edges) | ||
| 149 | + if (e->flags & EDGE_FALLTHRU) | ||
| 150 | + break; | ||
| 151 | + | ||
| 152 | + return e; | ||
| 153 | +} | ||
| 154 | + | ||
| 155 | /* In cfgloopmanip.c. */ | ||
| 156 | extern edge mfb_kj_edge; | ||
| 157 | extern bool mfb_keep_just (edge); | ||
| 158 | |||
| 159 | === modified file 'gcc/cfganal.c' | ||
| 160 | --- old/gcc/cfganal.c 2009-11-25 10:55:54 +0000 | ||
| 161 | +++ new/gcc/cfganal.c 2011-01-05 12:12:18 +0000 | ||
| 162 | @@ -271,6 +271,37 @@ | ||
| 163 | EDGE_SUCC (bb, 0)->flags |= EDGE_CAN_FALLTHRU; | ||
| 164 | EDGE_SUCC (bb, 1)->flags |= EDGE_CAN_FALLTHRU; | ||
| 165 | } | ||
| 166 | + /* dwarf2out expects that a NOTE_INSN_EPILOGUE_BEGIN is always paired | ||
| 167 | + with a return or a sibcall. Ensure that this remains the case if | ||
| 168 | + they are in different basic blocks. */ | ||
| 169 | + FOR_EACH_BB (bb) | ||
| 170 | + { | ||
| 171 | + edge e; | ||
| 172 | + edge_iterator ei; | ||
| 173 | + rtx insn, end; | ||
| 174 | + | ||
| 175 | + end = BB_END (bb); | ||
| 176 | + FOR_BB_INSNS (bb, insn) | ||
| 177 | + if (GET_CODE (insn) == NOTE | ||
| 178 | + && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG | ||
| 179 | + && !(CALL_P (end) && SIBLING_CALL_P (end)) | ||
| 180 | + && !returnjump_p (end)) | ||
| 181 | + { | ||
| 182 | + basic_block other_bb = NULL; | ||
| 183 | + FOR_EACH_EDGE (e, ei, bb->succs) | ||
| 184 | + { | ||
| 185 | + if (e->flags & EDGE_FALLTHRU) | ||
| 186 | + other_bb = e->dest; | ||
| 187 | + else | ||
| 188 | + e->flags &= ~EDGE_CAN_FALLTHRU; | ||
| 189 | + } | ||
| 190 | + FOR_EACH_EDGE (e, ei, other_bb->preds) | ||
| 191 | + { | ||
| 192 | + if (!(e->flags & EDGE_FALLTHRU)) | ||
| 193 | + e->flags &= ~EDGE_CAN_FALLTHRU; | ||
| 194 | + } | ||
| 195 | + } | ||
| 196 | + } | ||
| 197 | } | ||
| 198 | |||
| 199 | /* Find unreachable blocks. An unreachable block will have 0 in | ||
| 200 | |||
| 201 | === modified file 'gcc/cfglayout.c' | ||
| 202 | --- old/gcc/cfglayout.c 2010-05-17 16:30:54 +0000 | ||
| 203 | +++ new/gcc/cfglayout.c 2011-01-05 12:12:18 +0000 | ||
| 204 | @@ -766,6 +766,7 @@ | ||
| 205 | { | ||
| 206 | edge e_fall, e_taken, e; | ||
| 207 | rtx bb_end_insn; | ||
| 208 | + rtx ret_label = NULL_RTX; | ||
| 209 | basic_block nb; | ||
| 210 | edge_iterator ei; | ||
| 211 | |||
| 212 | @@ -785,6 +786,7 @@ | ||
| 213 | bb_end_insn = BB_END (bb); | ||
| 214 | if (JUMP_P (bb_end_insn)) | ||
| 215 | { | ||
| 216 | + ret_label = JUMP_LABEL (bb_end_insn); | ||
| 217 | if (any_condjump_p (bb_end_insn)) | ||
| 218 | { | ||
| 219 | /* This might happen if the conditional jump has side | ||
| 220 | @@ -899,7 +901,7 @@ | ||
| 221 | } | ||
| 222 | |||
| 223 | /* We got here if we need to add a new jump insn. */ | ||
| 224 | - nb = force_nonfallthru (e_fall); | ||
| 225 | + nb = force_nonfallthru_and_redirect (e_fall, e_fall->dest, ret_label); | ||
| 226 | if (nb) | ||
| 227 | { | ||
| 228 | nb->il.rtl->visited = 1; | ||
| 229 | @@ -1118,24 +1120,30 @@ | ||
| 230 | bool | ||
| 231 | cfg_layout_can_duplicate_bb_p (const_basic_block bb) | ||
| 232 | { | ||
| 233 | + rtx insn; | ||
| 234 | + | ||
| 235 | /* Do not attempt to duplicate tablejumps, as we need to unshare | ||
| 236 | the dispatch table. This is difficult to do, as the instructions | ||
| 237 | computing jump destination may be hoisted outside the basic block. */ | ||
| 238 | if (tablejump_p (BB_END (bb), NULL, NULL)) | ||
| 239 | return false; | ||
| 240 | |||
| 241 | - /* Do not duplicate blocks containing insns that can't be copied. */ | ||
| 242 | - if (targetm.cannot_copy_insn_p) | ||
| 243 | + insn = BB_HEAD (bb); | ||
| 244 | + while (1) | ||
| 245 | { | ||
| 246 | - rtx insn = BB_HEAD (bb); | ||
| 247 | - while (1) | ||
| 248 | - { | ||
| 249 | - if (INSN_P (insn) && targetm.cannot_copy_insn_p (insn)) | ||
| 250 | - return false; | ||
| 251 | - if (insn == BB_END (bb)) | ||
| 252 | - break; | ||
| 253 | - insn = NEXT_INSN (insn); | ||
| 254 | - } | ||
| 255 | + /* Do not duplicate blocks containing insns that can't be copied. */ | ||
| 256 | + if (INSN_P (insn) && targetm.cannot_copy_insn_p | ||
| 257 | + && targetm.cannot_copy_insn_p (insn)) | ||
| 258 | + return false; | ||
| 259 | + /* dwarf2out expects that these notes are always paired with a | ||
| 260 | + returnjump or sibling call. */ | ||
| 261 | + if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG | ||
| 262 | + && !returnjump_p (BB_END (bb)) | ||
| 263 | + && (!CALL_P (BB_END (bb)) || !SIBLING_CALL_P (BB_END (bb)))) | ||
| 264 | + return false; | ||
| 265 | + if (insn == BB_END (bb)) | ||
| 266 | + break; | ||
| 267 | + insn = NEXT_INSN (insn); | ||
| 268 | } | ||
| 269 | |||
| 270 | return true; | ||
| 271 | @@ -1167,6 +1175,9 @@ | ||
| 272 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) | ||
| 273 | break; | ||
| 274 | copy = emit_copy_of_insn_after (insn, get_last_insn ()); | ||
| 275 | + if (JUMP_P (insn) && JUMP_LABEL (insn) != NULL_RTX | ||
| 276 | + && ANY_RETURN_P (JUMP_LABEL (insn))) | ||
| 277 | + JUMP_LABEL (copy) = JUMP_LABEL (insn); | ||
| 278 | maybe_copy_epilogue_insn (insn, copy); | ||
| 279 | break; | ||
| 280 | |||
| 281 | |||
| 282 | === modified file 'gcc/cfgrtl.c' | ||
| 283 | --- old/gcc/cfgrtl.c 2010-09-20 21:30:35 +0000 | ||
| 284 | +++ new/gcc/cfgrtl.c 2011-01-05 12:12:18 +0000 | ||
| 285 | @@ -1107,10 +1107,13 @@ | ||
| 286 | } | ||
| 287 | |||
| 288 | /* Like force_nonfallthru below, but additionally performs redirection | ||
| 289 | - Used by redirect_edge_and_branch_force. */ | ||
| 290 | + Used by redirect_edge_and_branch_force. JUMP_LABEL is used only | ||
| 291 | + when redirecting to the EXIT_BLOCK, it is either a return or a | ||
| 292 | + simple_return rtx indicating which kind of returnjump to create. | ||
| 293 | + It should be NULL otherwise. */ | ||
| 294 | |||
| 295 | -static basic_block | ||
| 296 | -force_nonfallthru_and_redirect (edge e, basic_block target) | ||
| 297 | +basic_block | ||
| 298 | +force_nonfallthru_and_redirect (edge e, basic_block target, rtx jump_label) | ||
| 299 | { | ||
| 300 | basic_block jump_block, new_bb = NULL, src = e->src; | ||
| 301 | rtx note; | ||
| 302 | @@ -1242,11 +1245,25 @@ | ||
| 303 | e->flags &= ~EDGE_FALLTHRU; | ||
| 304 | if (target == EXIT_BLOCK_PTR) | ||
| 305 | { | ||
| 306 | + if (jump_label == ret_rtx) | ||
| 307 | + { | ||
| 308 | #ifdef HAVE_return | ||
| 309 | - emit_jump_insn_after_setloc (gen_return (), BB_END (jump_block), loc); | ||
| 310 | -#else | ||
| 311 | - gcc_unreachable (); | ||
| 312 | -#endif | ||
| 313 | + emit_jump_insn_after_setloc (gen_return (), BB_END (jump_block), | ||
| 314 | + loc); | ||
| 315 | +#else | ||
| 316 | + gcc_unreachable (); | ||
| 317 | +#endif | ||
| 318 | + } | ||
| 319 | + else | ||
| 320 | + { | ||
| 321 | + gcc_assert (jump_label == simple_return_rtx); | ||
| 322 | +#ifdef HAVE_simple_return | ||
| 323 | + emit_jump_insn_after_setloc (gen_simple_return (), | ||
| 324 | + BB_END (jump_block), loc); | ||
| 325 | +#else | ||
| 326 | + gcc_unreachable (); | ||
| 327 | +#endif | ||
| 328 | + } | ||
| 329 | } | ||
| 330 | else | ||
| 331 | { | ||
| 332 | @@ -1273,7 +1290,7 @@ | ||
| 333 | basic_block | ||
| 334 | force_nonfallthru (edge e) | ||
| 335 | { | ||
| 336 | - return force_nonfallthru_and_redirect (e, e->dest); | ||
| 337 | + return force_nonfallthru_and_redirect (e, e->dest, NULL_RTX); | ||
| 338 | } | ||
| 339 | |||
| 340 | /* Redirect edge even at the expense of creating new jump insn or | ||
| 341 | @@ -1290,7 +1307,7 @@ | ||
| 342 | /* In case the edge redirection failed, try to force it to be non-fallthru | ||
| 343 | and redirect newly created simplejump. */ | ||
| 344 | df_set_bb_dirty (e->src); | ||
| 345 | - return force_nonfallthru_and_redirect (e, target); | ||
| 346 | + return force_nonfallthru_and_redirect (e, target, NULL_RTX); | ||
| 347 | } | ||
| 348 | |||
| 349 | /* The given edge should potentially be a fallthru edge. If that is in | ||
| 350 | |||
| 351 | === modified file 'gcc/common.opt' | ||
| 352 | --- old/gcc/common.opt 2010-12-10 15:33:37 +0000 | ||
| 353 | +++ new/gcc/common.opt 2011-01-05 12:12:18 +0000 | ||
| 354 | @@ -1147,6 +1147,11 @@ | ||
| 355 | Common C ObjC C++ ObjC++ Report Var(flag_show_column) Init(1) | ||
| 356 | Show column numbers in diagnostics, when available. Default on | ||
| 357 | |||
| 358 | +fshrink-wrap | ||
| 359 | +Common Report Var(flag_shrink_wrap) Optimization | ||
| 360 | +Emit function prologues only before parts of the function that need it, | ||
| 361 | +rather than at the top of the function. | ||
| 362 | + | ||
| 363 | fsignaling-nans | ||
| 364 | Common Report Var(flag_signaling_nans) Optimization | ||
| 365 | Disable optimizations observable by IEEE signaling NaNs | ||
| 366 | |||
| 367 | === modified file 'gcc/config/arm/arm-protos.h' | ||
| 368 | --- old/gcc/config/arm/arm-protos.h 2010-11-04 10:45:05 +0000 | ||
| 369 | +++ new/gcc/config/arm/arm-protos.h 2011-01-05 12:12:18 +0000 | ||
| 370 | @@ -26,6 +26,7 @@ | ||
| 371 | extern void arm_override_options (void); | ||
| 372 | extern void arm_optimization_options (int, int); | ||
| 373 | extern int use_return_insn (int, rtx); | ||
| 374 | +extern bool use_simple_return_p (void); | ||
| 375 | extern enum reg_class arm_regno_class (int); | ||
| 376 | extern void arm_load_pic_register (unsigned long); | ||
| 377 | extern int arm_volatile_func (void); | ||
| 378 | @@ -137,7 +138,7 @@ | ||
| 379 | extern const char *output_add_immediate (rtx *); | ||
| 380 | extern const char *arithmetic_instr (rtx, int); | ||
| 381 | extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int); | ||
| 382 | -extern const char *output_return_instruction (rtx, int, int); | ||
| 383 | +extern const char *output_return_instruction (rtx, bool, bool, bool); | ||
| 384 | extern void arm_poke_function_name (FILE *, const char *); | ||
| 385 | extern void arm_print_operand (FILE *, rtx, int); | ||
| 386 | extern void arm_print_operand_address (FILE *, rtx); | ||
| 387 | |||
| 388 | === modified file 'gcc/config/arm/arm.c' | ||
| 389 | --- old/gcc/config/arm/arm.c 2011-01-05 11:32:50 +0000 | ||
| 390 | +++ new/gcc/config/arm/arm.c 2011-01-05 12:12:18 +0000 | ||
| 391 | @@ -2163,6 +2163,18 @@ | ||
| 392 | return addr; | ||
| 393 | } | ||
| 394 | |||
| 395 | +/* Return true if we should try to use a simple_return insn, i.e. perform | ||
| 396 | + shrink-wrapping if possible. This is the case if we need to emit a | ||
| 397 | + prologue, which we can test by looking at the offsets. */ | ||
| 398 | +bool | ||
| 399 | +use_simple_return_p (void) | ||
| 400 | +{ | ||
| 401 | + arm_stack_offsets *offsets; | ||
| 402 | + | ||
| 403 | + offsets = arm_get_frame_offsets (); | ||
| 404 | + return offsets->outgoing_args != 0; | ||
| 405 | +} | ||
| 406 | + | ||
| 407 | /* Return 1 if it is possible to return using a single instruction. | ||
| 408 | If SIBLING is non-null, this is a test for a return before a sibling | ||
| 409 | call. SIBLING is the call insn, so we can examine its register usage. */ | ||
| 410 | @@ -11284,6 +11296,7 @@ | ||
| 411 | |||
| 412 | if (GET_CODE (insn) == JUMP_INSN | ||
| 413 | && JUMP_LABEL (insn) != NULL | ||
| 414 | + && !ANY_RETURN_P (JUMP_LABEL (insn)) | ||
| 415 | && ((table = next_real_insn (JUMP_LABEL (insn))) | ||
| 416 | == next_real_insn (insn)) | ||
| 417 | && table != NULL | ||
| 418 | @@ -14168,7 +14181,7 @@ | ||
| 419 | /* Generate a function exit sequence. If REALLY_RETURN is false, then do | ||
| 420 | everything bar the final return instruction. */ | ||
| 421 | const char * | ||
| 422 | -output_return_instruction (rtx operand, int really_return, int reverse) | ||
| 423 | +output_return_instruction (rtx operand, bool really_return, bool reverse, bool simple) | ||
| 424 | { | ||
| 425 | char conditional[10]; | ||
| 426 | char instr[100]; | ||
| 427 | @@ -14206,10 +14219,15 @@ | ||
| 428 | |||
| 429 | sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); | ||
| 430 | |||
| 431 | - cfun->machine->return_used_this_function = 1; | ||
| 432 | + if (simple) | ||
| 433 | + live_regs_mask = 0; | ||
| 434 | + else | ||
| 435 | + { | ||
| 436 | + cfun->machine->return_used_this_function = 1; | ||
| 437 | |||
| 438 | - offsets = arm_get_frame_offsets (); | ||
| 439 | - live_regs_mask = offsets->saved_regs_mask; | ||
| 440 | + offsets = arm_get_frame_offsets (); | ||
| 441 | + live_regs_mask = offsets->saved_regs_mask; | ||
| 442 | + } | ||
| 443 | |||
| 444 | if (live_regs_mask) | ||
| 445 | { | ||
| 446 | @@ -17108,6 +17126,7 @@ | ||
| 447 | |||
| 448 | /* If we start with a return insn, we only succeed if we find another one. */ | ||
| 449 | int seeking_return = 0; | ||
| 450 | + enum rtx_code return_code = UNKNOWN; | ||
| 451 | |||
| 452 | /* START_INSN will hold the insn from where we start looking. This is the | ||
| 453 | first insn after the following code_label if REVERSE is true. */ | ||
| 454 | @@ -17146,7 +17165,7 @@ | ||
| 455 | else | ||
| 456 | return; | ||
| 457 | } | ||
| 458 | - else if (GET_CODE (body) == RETURN) | ||
| 459 | + else if (ANY_RETURN_P (body)) | ||
| 460 | { | ||
| 461 | start_insn = next_nonnote_insn (start_insn); | ||
| 462 | if (GET_CODE (start_insn) == BARRIER) | ||
| 463 | @@ -17157,6 +17176,7 @@ | ||
| 464 | { | ||
| 465 | reverse = TRUE; | ||
| 466 | seeking_return = 1; | ||
| 467 | + return_code = GET_CODE (body); | ||
| 468 | } | ||
| 469 | else | ||
| 470 | return; | ||
| 471 | @@ -17197,11 +17217,15 @@ | ||
| 472 | label = XEXP (XEXP (SET_SRC (body), 2), 0); | ||
| 473 | then_not_else = FALSE; | ||
| 474 | } | ||
| 475 | - else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) | ||
| 476 | - seeking_return = 1; | ||
| 477 | - else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) | ||
| 478 | + else if (ANY_RETURN_P (XEXP (SET_SRC (body), 1))) | ||
| 479 | + { | ||
| 480 | + seeking_return = 1; | ||
| 481 | + return_code = GET_CODE (XEXP (SET_SRC (body), 1)); | ||
| 482 | + } | ||
| 483 | + else if (ANY_RETURN_P (XEXP (SET_SRC (body), 2))) | ||
| 484 | { | ||
| 485 | seeking_return = 1; | ||
| 486 | + return_code = GET_CODE (XEXP (SET_SRC (body), 2)); | ||
| 487 | then_not_else = FALSE; | ||
| 488 | } | ||
| 489 | else | ||
| 490 | @@ -17302,8 +17326,7 @@ | ||
| 491 | && !use_return_insn (TRUE, NULL) | ||
| 492 | && !optimize_size) | ||
| 493 | fail = TRUE; | ||
| 494 | - else if (GET_CODE (scanbody) == RETURN | ||
| 495 | - && seeking_return) | ||
| 496 | + else if (GET_CODE (scanbody) == return_code) | ||
| 497 | { | ||
| 498 | arm_ccfsm_state = 2; | ||
| 499 | succeed = TRUE; | ||
| 500 | |||
| 501 | === modified file 'gcc/config/arm/arm.h' | ||
| 502 | --- old/gcc/config/arm/arm.h 2010-11-11 11:12:14 +0000 | ||
| 503 | +++ new/gcc/config/arm/arm.h 2011-01-05 12:12:18 +0000 | ||
| 504 | @@ -2622,6 +2622,8 @@ | ||
| 505 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | ||
| 506 | arm_return_addr (COUNT, FRAME) | ||
| 507 | |||
| 508 | +#define RETURN_ADDR_REGNUM LR_REGNUM | ||
| 509 | + | ||
| 510 | /* Mask of the bits in the PC that contain the real return address | ||
| 511 | when running in 26-bit mode. */ | ||
| 512 | #define RETURN_ADDR_MASK26 (0x03fffffc) | ||
| 513 | |||
| 514 | === modified file 'gcc/config/arm/arm.md' | ||
| 515 | --- old/gcc/config/arm/arm.md 2011-01-05 11:52:16 +0000 | ||
| 516 | +++ new/gcc/config/arm/arm.md 2011-01-05 12:12:18 +0000 | ||
| 517 | @@ -8882,66 +8882,72 @@ | ||
| 518 | [(set_attr "type" "call")] | ||
| 519 | ) | ||
| 520 | |||
| 521 | -(define_expand "return" | ||
| 522 | - [(return)] | ||
| 523 | - "TARGET_32BIT && USE_RETURN_INSN (FALSE)" | ||
| 524 | +;; Both kinds of return insn. | ||
| 525 | +(define_code_iterator returns [return simple_return]) | ||
| 526 | +(define_code_attr return_str [(return "") (simple_return "simple_")]) | ||
| 527 | +(define_code_attr return_simple_p [(return "false") (simple_return "true")]) | ||
| 528 | +(define_code_attr return_cond [(return " && USE_RETURN_INSN (FALSE)") | ||
| 529 | + (simple_return " && use_simple_return_p ()")]) | ||
| 530 | + | ||
| 531 | +(define_expand "<return_str>return" | ||
| 532 | + [(returns)] | ||
| 533 | + "TARGET_32BIT<return_cond>" | ||
| 534 | "") | ||
| 535 | |||
| 536 | -;; Often the return insn will be the same as loading from memory, so set attr | ||
| 537 | -(define_insn "*arm_return" | ||
| 538 | - [(return)] | ||
| 539 | - "TARGET_ARM && USE_RETURN_INSN (FALSE)" | ||
| 540 | - "* | ||
| 541 | - { | ||
| 542 | - if (arm_ccfsm_state == 2) | ||
| 543 | - { | ||
| 544 | - arm_ccfsm_state += 2; | ||
| 545 | - return \"\"; | ||
| 546 | - } | ||
| 547 | - return output_return_instruction (const_true_rtx, TRUE, FALSE); | ||
| 548 | - }" | ||
| 549 | +(define_insn "*arm_<return_str>return" | ||
| 550 | + [(returns)] | ||
| 551 | + "TARGET_ARM<return_cond>" | ||
| 552 | +{ | ||
| 553 | + if (arm_ccfsm_state == 2) | ||
| 554 | + { | ||
| 555 | + arm_ccfsm_state += 2; | ||
| 556 | + return ""; | ||
| 557 | + } | ||
| 558 | + return output_return_instruction (const_true_rtx, true, false, | ||
| 559 | + <return_simple_p>); | ||
| 560 | +} | ||
| 561 | [(set_attr "type" "load1") | ||
| 562 | (set_attr "length" "12") | ||
| 563 | (set_attr "predicable" "yes")] | ||
| 564 | ) | ||
| 565 | |||
| 566 | -(define_insn "*cond_return" | ||
| 567 | +(define_insn "*cond_<return_str>return" | ||
| 568 | [(set (pc) | ||
| 569 | (if_then_else (match_operator 0 "arm_comparison_operator" | ||
| 570 | [(match_operand 1 "cc_register" "") (const_int 0)]) | ||
| 571 | - (return) | ||
| 572 | + (returns) | ||
| 573 | (pc)))] | ||
| 574 | - "TARGET_ARM && USE_RETURN_INSN (TRUE)" | ||
| 575 | - "* | ||
| 576 | - { | ||
| 577 | - if (arm_ccfsm_state == 2) | ||
| 578 | - { | ||
| 579 | - arm_ccfsm_state += 2; | ||
| 580 | - return \"\"; | ||
| 581 | - } | ||
| 582 | - return output_return_instruction (operands[0], TRUE, FALSE); | ||
| 583 | - }" | ||
| 584 | + "TARGET_ARM<return_cond>" | ||
| 585 | +{ | ||
| 586 | + if (arm_ccfsm_state == 2) | ||
| 587 | + { | ||
| 588 | + arm_ccfsm_state += 2; | ||
| 589 | + return ""; | ||
| 590 | + } | ||
| 591 | + return output_return_instruction (operands[0], true, false, | ||
| 592 | + <return_simple_p>); | ||
| 593 | +} | ||
| 594 | [(set_attr "conds" "use") | ||
| 595 | (set_attr "length" "12") | ||
| 596 | (set_attr "type" "load1")] | ||
| 597 | ) | ||
| 598 | |||
| 599 | -(define_insn "*cond_return_inverted" | ||
| 600 | +(define_insn "*cond_<return_str>return_inverted" | ||
| 601 | [(set (pc) | ||
| 602 | (if_then_else (match_operator 0 "arm_comparison_operator" | ||
| 603 | [(match_operand 1 "cc_register" "") (const_int 0)]) | ||
| 604 | (pc) | ||
| 605 | - (return)))] | ||
| 606 | - "TARGET_ARM && USE_RETURN_INSN (TRUE)" | ||
| 607 | - "* | ||
| 608 | - { | ||
| 609 | - if (arm_ccfsm_state == 2) | ||
| 610 | - { | ||
| 611 | - arm_ccfsm_state += 2; | ||
| 612 | - return \"\"; | ||
| 613 | - } | ||
| 614 | - return output_return_instruction (operands[0], TRUE, TRUE); | ||
| 615 | - }" | ||
| 616 | + (returns)))] | ||
| 617 | + "TARGET_ARM<return_cond>" | ||
| 618 | +{ | ||
| 619 | + if (arm_ccfsm_state == 2) | ||
| 620 | + { | ||
| 621 | + arm_ccfsm_state += 2; | ||
| 622 | + return ""; | ||
| 623 | + } | ||
| 624 | + return output_return_instruction (operands[0], true, true, | ||
| 625 | + <return_simple_p>); | ||
| 626 | +} | ||
| 627 | [(set_attr "conds" "use") | ||
| 628 | (set_attr "length" "12") | ||
| 629 | (set_attr "type" "load1")] | ||
| 630 | @@ -10809,8 +10815,7 @@ | ||
| 631 | DONE; | ||
| 632 | } | ||
| 633 | emit_jump_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, | ||
| 634 | - gen_rtvec (1, | ||
| 635 | - gen_rtx_RETURN (VOIDmode)), | ||
| 636 | + gen_rtvec (1, ret_rtx), | ||
| 637 | VUNSPEC_EPILOGUE)); | ||
| 638 | DONE; | ||
| 639 | " | ||
| 640 | @@ -10827,7 +10832,7 @@ | ||
| 641 | "TARGET_32BIT" | ||
| 642 | "* | ||
| 643 | if (use_return_insn (FALSE, next_nonnote_insn (insn))) | ||
| 644 | - return output_return_instruction (const_true_rtx, FALSE, FALSE); | ||
| 645 | + return output_return_instruction (const_true_rtx, false, false, false); | ||
| 646 | return arm_output_epilogue (next_nonnote_insn (insn)); | ||
| 647 | " | ||
| 648 | ;; Length is absolute worst case | ||
| 649 | |||
| 650 | === modified file 'gcc/config/arm/thumb2.md' | ||
| 651 | --- old/gcc/config/arm/thumb2.md 2010-09-22 05:54:42 +0000 | ||
| 652 | +++ new/gcc/config/arm/thumb2.md 2011-01-05 12:12:18 +0000 | ||
| 653 | @@ -1020,16 +1020,15 @@ | ||
| 654 | |||
| 655 | ;; Note: this is not predicable, to avoid issues with linker-generated | ||
| 656 | ;; interworking stubs. | ||
| 657 | -(define_insn "*thumb2_return" | ||
| 658 | - [(return)] | ||
| 659 | - "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)" | ||
| 660 | - "* | ||
| 661 | - { | ||
| 662 | - return output_return_instruction (const_true_rtx, TRUE, FALSE); | ||
| 663 | - }" | ||
| 664 | +(define_insn "*thumb2_<return_str>return" | ||
| 665 | + [(returns)] | ||
| 666 | + "TARGET_THUMB2<return_cond>" | ||
| 667 | +{ | ||
| 668 | + return output_return_instruction (const_true_rtx, true, false, | ||
| 669 | + <return_simple_p>); | ||
| 670 | +} | ||
| 671 | [(set_attr "type" "load1") | ||
| 672 | - (set_attr "length" "12")] | ||
| 673 | -) | ||
| 674 | + (set_attr "length" "12")]) | ||
| 675 | |||
| 676 | (define_insn_and_split "thumb2_eh_return" | ||
| 677 | [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")] | ||
| 678 | |||
| 679 | === modified file 'gcc/config/i386/i386.c' | ||
| 680 | --- old/gcc/config/i386/i386.c 2010-11-16 18:05:53 +0000 | ||
| 681 | +++ new/gcc/config/i386/i386.c 2011-01-05 12:12:18 +0000 | ||
| 682 | @@ -9308,13 +9308,13 @@ | ||
| 683 | |||
| 684 | pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx, | ||
| 685 | popc, -1, true); | ||
| 686 | - emit_jump_insn (gen_return_indirect_internal (ecx)); | ||
| 687 | + emit_jump_insn (gen_simple_return_indirect_internal (ecx)); | ||
| 688 | } | ||
| 689 | else | ||
| 690 | - emit_jump_insn (gen_return_pop_internal (popc)); | ||
| 691 | + emit_jump_insn (gen_simple_return_pop_internal (popc)); | ||
| 692 | } | ||
| 693 | else | ||
| 694 | - emit_jump_insn (gen_return_internal ()); | ||
| 695 | + emit_jump_insn (gen_simple_return_internal ()); | ||
| 696 | |||
| 697 | /* Restore the state back to the state from the prologue, | ||
| 698 | so that it's correct for the next epilogue. */ | ||
| 699 | @@ -26596,7 +26596,7 @@ | ||
| 700 | rtx prev; | ||
| 701 | bool replace = false; | ||
| 702 | |||
| 703 | - if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN | ||
| 704 | + if (!JUMP_P (ret) || !ANY_RETURN_P (PATTERN (ret)) | ||
| 705 | || optimize_bb_for_size_p (bb)) | ||
| 706 | continue; | ||
| 707 | for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev)) | ||
| 708 | @@ -26626,7 +26626,10 @@ | ||
| 709 | } | ||
| 710 | if (replace) | ||
| 711 | { | ||
| 712 | - emit_jump_insn_before (gen_return_internal_long (), ret); | ||
| 713 | + if (PATTERN (ret) == ret_rtx) | ||
| 714 | + emit_jump_insn_before (gen_return_internal_long (), ret); | ||
| 715 | + else | ||
| 716 | + emit_jump_insn_before (gen_simple_return_internal_long (), ret); | ||
| 717 | delete_insn (ret); | ||
| 718 | } | ||
| 719 | } | ||
| 720 | |||
| 721 | === modified file 'gcc/config/i386/i386.md' | ||
| 722 | --- old/gcc/config/i386/i386.md 2010-11-27 15:24:12 +0000 | ||
| 723 | +++ new/gcc/config/i386/i386.md 2011-01-05 12:12:18 +0000 | ||
| 724 | @@ -13797,24 +13797,29 @@ | ||
| 725 | "" | ||
| 726 | [(set_attr "length" "0")]) | ||
| 727 | |||
| 728 | +(define_code_iterator returns [return simple_return]) | ||
| 729 | +(define_code_attr return_str [(return "") (simple_return "simple_")]) | ||
| 730 | +(define_code_attr return_cond [(return "ix86_can_use_return_insn_p ()") | ||
| 731 | + (simple_return "")]) | ||
| 732 | + | ||
| 733 | ;; Insn emitted into the body of a function to return from a function. | ||
| 734 | ;; This is only done if the function's epilogue is known to be simple. | ||
| 735 | ;; See comments for ix86_can_use_return_insn_p in i386.c. | ||
| 736 | |||
| 737 | -(define_expand "return" | ||
| 738 | - [(return)] | ||
| 739 | - "ix86_can_use_return_insn_p ()" | ||
| 740 | +(define_expand "<return_str>return" | ||
| 741 | + [(returns)] | ||
| 742 | + "<return_cond>" | ||
| 743 | { | ||
| 744 | if (crtl->args.pops_args) | ||
| 745 | { | ||
| 746 | rtx popc = GEN_INT (crtl->args.pops_args); | ||
| 747 | - emit_jump_insn (gen_return_pop_internal (popc)); | ||
| 748 | + emit_jump_insn (gen_<return_str>return_pop_internal (popc)); | ||
| 749 | DONE; | ||
| 750 | } | ||
| 751 | }) | ||
| 752 | |||
| 753 | -(define_insn "return_internal" | ||
| 754 | - [(return)] | ||
| 755 | +(define_insn "<return_str>return_internal" | ||
| 756 | + [(returns)] | ||
| 757 | "reload_completed" | ||
| 758 | "ret" | ||
| 759 | [(set_attr "length" "1") | ||
| 760 | @@ -13825,8 +13830,8 @@ | ||
| 761 | ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET | ||
| 762 | ;; instruction Athlon and K8 have. | ||
| 763 | |||
| 764 | -(define_insn "return_internal_long" | ||
| 765 | - [(return) | ||
| 766 | +(define_insn "<return_str>return_internal_long" | ||
| 767 | + [(returns) | ||
| 768 | (unspec [(const_int 0)] UNSPEC_REP)] | ||
| 769 | "reload_completed" | ||
| 770 | "rep\;ret" | ||
| 771 | @@ -13836,8 +13841,8 @@ | ||
| 772 | (set_attr "prefix_rep" "1") | ||
| 773 | (set_attr "modrm" "0")]) | ||
| 774 | |||
| 775 | -(define_insn "return_pop_internal" | ||
| 776 | - [(return) | ||
| 777 | +(define_insn "<return_str>return_pop_internal" | ||
| 778 | + [(returns) | ||
| 779 | (use (match_operand:SI 0 "const_int_operand" ""))] | ||
| 780 | "reload_completed" | ||
| 781 | "ret\t%0" | ||
| 782 | @@ -13846,8 +13851,8 @@ | ||
| 783 | (set_attr "length_immediate" "2") | ||
| 784 | (set_attr "modrm" "0")]) | ||
| 785 | |||
| 786 | -(define_insn "return_indirect_internal" | ||
| 787 | - [(return) | ||
| 788 | +(define_insn "<return_str>return_indirect_internal" | ||
| 789 | + [(returns) | ||
| 790 | (use (match_operand:SI 0 "register_operand" "r"))] | ||
| 791 | "reload_completed" | ||
| 792 | "jmp\t%A0" | ||
| 793 | |||
| 794 | === modified file 'gcc/config/mips/mips.c' | ||
| 795 | --- old/gcc/config/mips/mips.c 2010-11-21 10:38:43 +0000 | ||
| 796 | +++ new/gcc/config/mips/mips.c 2011-01-05 12:12:18 +0000 | ||
| 797 | @@ -10497,7 +10497,8 @@ | ||
| 798 | regno = GP_REG_FIRST + 7; | ||
| 799 | else | ||
| 800 | regno = RETURN_ADDR_REGNUM; | ||
| 801 | - emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno))); | ||
| 802 | + emit_jump_insn (gen_simple_return_internal (gen_rtx_REG (Pmode, | ||
| 803 | + regno))); | ||
| 804 | } | ||
| 805 | } | ||
| 806 | |||
| 807 | |||
| 808 | === modified file 'gcc/config/mips/mips.md' | ||
| 809 | --- old/gcc/config/mips/mips.md 2010-04-02 18:54:46 +0000 | ||
| 810 | +++ new/gcc/config/mips/mips.md 2011-01-05 12:12:18 +0000 | ||
| 811 | @@ -5815,6 +5815,18 @@ | ||
| 812 | [(set_attr "type" "jump") | ||
| 813 | (set_attr "mode" "none")]) | ||
| 814 | |||
| 815 | +(define_expand "simple_return" | ||
| 816 | + [(simple_return)] | ||
| 817 | + "!mips_can_use_return_insn ()" | ||
| 818 | + { mips_expand_before_return (); }) | ||
| 819 | + | ||
| 820 | +(define_insn "*simple_return" | ||
| 821 | + [(simple_return)] | ||
| 822 | + "!mips_can_use_return_insn ()" | ||
| 823 | + "%*j\t$31%/" | ||
| 824 | + [(set_attr "type" "jump") | ||
| 825 | + (set_attr "mode" "none")]) | ||
| 826 | + | ||
| 827 | ;; Normal return. | ||
| 828 | |||
| 829 | (define_insn "return_internal" | ||
| 830 | @@ -5825,6 +5837,14 @@ | ||
| 831 | [(set_attr "type" "jump") | ||
| 832 | (set_attr "mode" "none")]) | ||
| 833 | |||
| 834 | +(define_insn "simple_return_internal" | ||
| 835 | + [(simple_return) | ||
| 836 | + (use (match_operand 0 "pmode_register_operand" ""))] | ||
| 837 | + "" | ||
| 838 | + "%*j\t%0%/" | ||
| 839 | + [(set_attr "type" "jump") | ||
| 840 | + (set_attr "mode" "none")]) | ||
| 841 | + | ||
| 842 | ;; Exception return. | ||
| 843 | (define_insn "mips_eret" | ||
| 844 | [(return) | ||
| 845 | |||
| 846 | === modified file 'gcc/config/sh/sh.c' | ||
| 847 | --- old/gcc/config/sh/sh.c 2010-12-10 15:34:19 +0000 | ||
| 848 | +++ new/gcc/config/sh/sh.c 2011-01-05 12:12:18 +0000 | ||
| 849 | @@ -5252,7 +5252,8 @@ | ||
| 850 | } | ||
| 851 | if (prev | ||
| 852 | && JUMP_P (prev) | ||
| 853 | - && JUMP_LABEL (prev)) | ||
| 854 | + && JUMP_LABEL (prev) | ||
| 855 | + && !ANY_RETURN_P (JUMP_LABEL (prev))) | ||
| 856 | { | ||
| 857 | rtx x; | ||
| 858 | if (jump_to_next | ||
| 859 | @@ -5951,7 +5952,7 @@ | ||
| 860 | JUMP_LABEL (insn) = far_label; | ||
| 861 | LABEL_NUSES (far_label)++; | ||
| 862 | } | ||
| 863 | - redirect_jump (insn, NULL_RTX, 1); | ||
| 864 | + redirect_jump (insn, ret_rtx, 1); | ||
| 865 | far_label = 0; | ||
| 866 | } | ||
| 867 | } | ||
| 868 | |||
| 869 | === modified file 'gcc/df-scan.c' | ||
| 870 | --- old/gcc/df-scan.c 2010-11-16 22:17:17 +0000 | ||
| 871 | +++ new/gcc/df-scan.c 2011-01-05 12:12:18 +0000 | ||
| 872 | @@ -3296,6 +3296,7 @@ | ||
| 873 | } | ||
| 874 | |||
| 875 | case RETURN: | ||
| 876 | + case SIMPLE_RETURN: | ||
| 877 | break; | ||
| 878 | |||
| 879 | case ASM_OPERANDS: | ||
| 880 | |||
| 881 | === modified file 'gcc/doc/invoke.texi' | ||
| 882 | --- old/gcc/doc/invoke.texi 2010-11-04 14:29:09 +0000 | ||
| 883 | +++ new/gcc/doc/invoke.texi 2011-01-05 12:12:18 +0000 | ||
| 884 | @@ -5750,6 +5750,7 @@ | ||
| 885 | -fipa-pure-const @gol | ||
| 886 | -fipa-reference @gol | ||
| 887 | -fmerge-constants | ||
| 888 | +-fshrink-wrap @gol | ||
| 889 | -fsplit-wide-types @gol | ||
| 890 | -ftree-builtin-call-dce @gol | ||
| 891 | -ftree-ccp @gol | ||
| 892 | @@ -6504,6 +6505,12 @@ | ||
| 893 | When pipelining loops during selective scheduling, also pipeline outer loops. | ||
| 894 | This option has no effect until @option{-fsel-sched-pipelining} is turned on. | ||
| 895 | |||
| 896 | +@item -fshrink-wrap | ||
| 897 | +@opindex fshrink-wrap | ||
| 898 | +Emit function prologues only before parts of the function that need it, | ||
| 899 | +rather than at the top of the function. This flag is enabled by default at | ||
| 900 | +@option{-O} and higher. | ||
| 901 | + | ||
| 902 | @item -fcaller-saves | ||
| 903 | @opindex fcaller-saves | ||
| 904 | Enable values to be allocated in registers that will be clobbered by | ||
| 905 | |||
| 906 | === modified file 'gcc/doc/md.texi' | ||
| 907 | --- old/gcc/doc/md.texi 2009-12-15 18:36:44 +0000 | ||
| 908 | +++ new/gcc/doc/md.texi 2011-01-05 12:12:18 +0000 | ||
| 909 | @@ -4801,7 +4801,19 @@ | ||
| 910 | multiple instructions are usually needed to return from a function, but | ||
| 911 | some class of functions only requires one instruction to implement a | ||
| 912 | return. Normally, the applicable functions are those which do not need | ||
| 913 | -to save any registers or allocate stack space. | ||
| 914 | +to save any registers or allocate stack space, although some targets | ||
| 915 | +have instructions that can perform both the epilogue and function return | ||
| 916 | +in one instruction. | ||
| 917 | + | ||
| 918 | +@cindex @code{simple_return} instruction pattern | ||
| 919 | +@item @samp{simple_return} | ||
| 920 | +Subroutine return instruction. This instruction pattern name should be | ||
| 921 | +defined only if a single instruction can do all the work of returning | ||
| 922 | +from a function on a path where no epilogue is required. This pattern | ||
| 923 | +is very similar to the @code{return} instruction pattern, but it is emitted | ||
| 924 | +only by the shrink-wrapping optimization on paths where the function | ||
| 925 | +prologue has not been executed, and a function return should occur without | ||
| 926 | +any of the effects of the epilogue. | ||
| 927 | |||
| 928 | @findex reload_completed | ||
| 929 | @findex leaf_function_p | ||
| 930 | |||
| 931 | === modified file 'gcc/doc/rtl.texi' | ||
| 932 | --- old/gcc/doc/rtl.texi 2010-07-06 19:23:53 +0000 | ||
| 933 | +++ new/gcc/doc/rtl.texi 2011-01-05 12:12:18 +0000 | ||
| 934 | @@ -2888,6 +2888,13 @@ | ||
| 935 | Note that an insn pattern of @code{(return)} is logically equivalent to | ||
| 936 | @code{(set (pc) (return))}, but the latter form is never used. | ||
| 937 | |||
| 938 | +@findex simple_return | ||
| 939 | +@item (simple_return) | ||
| 940 | +Like @code{(return)}, but truly represents only a function return, while | ||
| 941 | +@code{(return)} may represent an insn that also performs other functions | ||
| 942 | +of the function epilogue. Like @code{(return)}, this may also occur in | ||
| 943 | +conditional jumps. | ||
| 944 | + | ||
| 945 | @findex call | ||
| 946 | @item (call @var{function} @var{nargs}) | ||
| 947 | Represents a function call. @var{function} is a @code{mem} expression | ||
| 948 | @@ -3017,7 +3024,7 @@ | ||
| 949 | brackets stand for a vector; the operand of @code{parallel} is a | ||
| 950 | vector of expressions. @var{x0}, @var{x1} and so on are individual | ||
| 951 | side effect expressions---expressions of code @code{set}, @code{call}, | ||
| 952 | -@code{return}, @code{clobber} or @code{use}. | ||
| 953 | +@code{return}, @code{simple_return}, @code{clobber} or @code{use}. | ||
| 954 | |||
| 955 | ``In parallel'' means that first all the values used in the individual | ||
| 956 | side-effects are computed, and second all the actual side-effects are | ||
| 957 | @@ -3656,14 +3663,16 @@ | ||
| 958 | @table @code | ||
| 959 | @findex PATTERN | ||
| 960 | @item PATTERN (@var{i}) | ||
| 961 | -An expression for the side effect performed by this insn. This must be | ||
| 962 | -one of the following codes: @code{set}, @code{call}, @code{use}, | ||
| 963 | -@code{clobber}, @code{return}, @code{asm_input}, @code{asm_output}, | ||
| 964 | -@code{addr_vec}, @code{addr_diff_vec}, @code{trap_if}, @code{unspec}, | ||
| 965 | -@code{unspec_volatile}, @code{parallel}, @code{cond_exec}, or @code{sequence}. If it is a @code{parallel}, | ||
| 966 | -each element of the @code{parallel} must be one these codes, except that | ||
| 967 | -@code{parallel} expressions cannot be nested and @code{addr_vec} and | ||
| 968 | -@code{addr_diff_vec} are not permitted inside a @code{parallel} expression. | ||
| 969 | +An expression for the side effect performed by this insn. This must | ||
| 970 | +be one of the following codes: @code{set}, @code{call}, @code{use}, | ||
| 971 | +@code{clobber}, @code{return}, @code{simple_return}, @code{asm_input}, | ||
| 972 | +@code{asm_output}, @code{addr_vec}, @code{addr_diff_vec}, | ||
| 973 | +@code{trap_if}, @code{unspec}, @code{unspec_volatile}, | ||
| 974 | +@code{parallel}, @code{cond_exec}, or @code{sequence}. If it is a | ||
| 975 | +@code{parallel}, each element of the @code{parallel} must be one these | ||
| 976 | +codes, except that @code{parallel} expressions cannot be nested and | ||
| 977 | +@code{addr_vec} and @code{addr_diff_vec} are not permitted inside a | ||
| 978 | +@code{parallel} expression. | ||
| 979 | |||
| 980 | @findex INSN_CODE | ||
| 981 | @item INSN_CODE (@var{i}) | ||
| 982 | |||
| 983 | === modified file 'gcc/doc/tm.texi' | ||
| 984 | --- old/gcc/doc/tm.texi 2010-09-01 13:29:58 +0000 | ||
| 985 | +++ new/gcc/doc/tm.texi 2011-01-05 12:12:18 +0000 | ||
| 986 | @@ -3287,6 +3287,12 @@ | ||
| 987 | from the frame pointer of the previous stack frame. | ||
| 988 | @end defmac | ||
| 989 | |||
| 990 | +@defmac RETURN_ADDR_REGNUM | ||
| 991 | +If defined, a C expression whose value is the register number of the return | ||
| 992 | +address for the current function. Targets that pass the return address on | ||
| 993 | +the stack should not define this macro. | ||
| 994 | +@end defmac | ||
| 995 | + | ||
| 996 | @defmac INCOMING_RETURN_ADDR_RTX | ||
| 997 | A C expression whose value is RTL representing the location of the | ||
| 998 | incoming return address at the beginning of any function, before the | ||
| 999 | |||
| 1000 | === modified file 'gcc/dwarf2out.c' | ||
| 1001 | --- old/gcc/dwarf2out.c 2010-12-21 18:46:10 +0000 | ||
| 1002 | +++ new/gcc/dwarf2out.c 2011-01-05 12:12:18 +0000 | ||
| 1003 | @@ -1396,7 +1396,7 @@ | ||
| 1004 | { | ||
| 1005 | rtx dest = JUMP_LABEL (insn); | ||
| 1006 | |||
| 1007 | - if (dest) | ||
| 1008 | + if (dest && !ANY_RETURN_P (dest)) | ||
| 1009 | { | ||
| 1010 | if (barrier_args_size [INSN_UID (dest)] < 0) | ||
| 1011 | { | ||
| 1012 | |||
| 1013 | === modified file 'gcc/emit-rtl.c' | ||
| 1014 | --- old/gcc/emit-rtl.c 2010-10-04 00:50:43 +0000 | ||
| 1015 | +++ new/gcc/emit-rtl.c 2011-01-05 12:12:18 +0000 | ||
| 1016 | @@ -2432,6 +2432,8 @@ | ||
| 1017 | case CODE_LABEL: | ||
| 1018 | case PC: | ||
| 1019 | case CC0: | ||
| 1020 | + case RETURN: | ||
| 1021 | + case SIMPLE_RETURN: | ||
| 1022 | case SCRATCH: | ||
| 1023 | return; | ||
| 1024 | /* SCRATCH must be shared because they represent distinct values. */ | ||
| 1025 | @@ -3323,14 +3325,17 @@ | ||
| 1026 | return insn; | ||
| 1027 | } | ||
| 1028 | |||
| 1029 | -/* Return the last label to mark the same position as LABEL. Return null | ||
| 1030 | - if LABEL itself is null. */ | ||
| 1031 | +/* Return the last label to mark the same position as LABEL. Return LABEL | ||
| 1032 | + itself if it is null or any return rtx. */ | ||
| 1033 | |||
| 1034 | rtx | ||
| 1035 | skip_consecutive_labels (rtx label) | ||
| 1036 | { | ||
| 1037 | rtx insn; | ||
| 1038 | |||
| 1039 | + if (label && ANY_RETURN_P (label)) | ||
| 1040 | + return label; | ||
| 1041 | + | ||
| 1042 | for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn)) | ||
| 1043 | if (LABEL_P (insn)) | ||
| 1044 | label = insn; | ||
| 1045 | @@ -5209,7 +5214,7 @@ | ||
| 1046 | return CODE_LABEL; | ||
| 1047 | if (GET_CODE (x) == CALL) | ||
| 1048 | return CALL_INSN; | ||
| 1049 | - if (GET_CODE (x) == RETURN) | ||
| 1050 | + if (GET_CODE (x) == RETURN || GET_CODE (x) == SIMPLE_RETURN) | ||
| 1051 | return JUMP_INSN; | ||
| 1052 | if (GET_CODE (x) == SET) | ||
| 1053 | { | ||
| 1054 | @@ -5715,8 +5720,10 @@ | ||
| 1055 | init_reg_modes_target (); | ||
| 1056 | |||
| 1057 | /* Assign register numbers to the globally defined register rtx. */ | ||
| 1058 | - pc_rtx = gen_rtx_PC (VOIDmode); | ||
| 1059 | - cc0_rtx = gen_rtx_CC0 (VOIDmode); | ||
| 1060 | + pc_rtx = gen_rtx_fmt_ (PC, VOIDmode); | ||
| 1061 | + ret_rtx = gen_rtx_fmt_ (RETURN, VOIDmode); | ||
| 1062 | + simple_return_rtx = gen_rtx_fmt_ (SIMPLE_RETURN, VOIDmode); | ||
| 1063 | + cc0_rtx = gen_rtx_fmt_ (CC0, VOIDmode); | ||
| 1064 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); | ||
| 1065 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | ||
| 1066 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM); | ||
| 1067 | |||
| 1068 | === modified file 'gcc/final.c' | ||
| 1069 | --- old/gcc/final.c 2010-03-26 16:18:51 +0000 | ||
| 1070 | +++ new/gcc/final.c 2011-01-05 12:12:18 +0000 | ||
| 1071 | @@ -2428,7 +2428,7 @@ | ||
| 1072 | delete_insn (insn); | ||
| 1073 | break; | ||
| 1074 | } | ||
| 1075 | - else if (GET_CODE (SET_SRC (body)) == RETURN) | ||
| 1076 | + else if (ANY_RETURN_P (SET_SRC (body))) | ||
| 1077 | /* Replace (set (pc) (return)) with (return). */ | ||
| 1078 | PATTERN (insn) = body = SET_SRC (body); | ||
| 1079 | |||
| 1080 | |||
| 1081 | === modified file 'gcc/function.c' | ||
| 1082 | --- old/gcc/function.c 2010-08-16 19:18:08 +0000 | ||
| 1083 | +++ new/gcc/function.c 2011-01-05 12:12:18 +0000 | ||
| 1084 | @@ -147,9 +147,6 @@ | ||
| 1085 | can always export `prologue_epilogue_contains'. */ | ||
| 1086 | static void record_insns (rtx, rtx, htab_t *) ATTRIBUTE_UNUSED; | ||
| 1087 | static bool contains (const_rtx, htab_t); | ||
| 1088 | -#ifdef HAVE_return | ||
| 1089 | -static void emit_return_into_block (basic_block); | ||
| 1090 | -#endif | ||
| 1091 | static void prepare_function_start (void); | ||
| 1092 | static void do_clobber_return_reg (rtx, void *); | ||
| 1093 | static void do_use_return_reg (rtx, void *); | ||
| 1094 | @@ -4987,35 +4984,189 @@ | ||
| 1095 | return 0; | ||
| 1096 | } | ||
| 1097 | |||
| 1098 | +#ifdef HAVE_simple_return | ||
| 1099 | +/* This collects sets and clobbers of hard registers in a HARD_REG_SET, | ||
| 1100 | + which is pointed to by DATA. */ | ||
| 1101 | +static void | ||
| 1102 | +record_hard_reg_sets (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) | ||
| 1103 | +{ | ||
| 1104 | + HARD_REG_SET *pset = (HARD_REG_SET *)data; | ||
| 1105 | + if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) | ||
| 1106 | + { | ||
| 1107 | + int nregs = hard_regno_nregs[REGNO (x)][GET_MODE (x)]; | ||
| 1108 | + while (nregs-- > 0) | ||
| 1109 | + SET_HARD_REG_BIT (*pset, REGNO (x) + nregs); | ||
| 1110 | + } | ||
| 1111 | +} | ||
| 1112 | + | ||
| 1113 | +/* A subroutine of requires_stack_frame_p, called via for_each_rtx. | ||
| 1114 | + If any change is made, set CHANGED | ||
| 1115 | + to true. */ | ||
| 1116 | + | ||
| 1117 | +static int | ||
| 1118 | +frame_required_for_rtx (rtx *loc, void *data ATTRIBUTE_UNUSED) | ||
| 1119 | +{ | ||
| 1120 | + rtx x = *loc; | ||
| 1121 | + if (x == stack_pointer_rtx || x == hard_frame_pointer_rtx | ||
| 1122 | + || x == arg_pointer_rtx || x == pic_offset_table_rtx | ||
| 1123 | +#ifdef RETURN_ADDR_REGNUM | ||
| 1124 | + || (REG_P (x) && REGNO (x) == RETURN_ADDR_REGNUM) | ||
| 1125 | +#endif | ||
| 1126 | + ) | ||
| 1127 | + return 1; | ||
| 1128 | + return 0; | ||
| 1129 | +} | ||
| 1130 | + | ||
| 1131 | +static bool | ||
| 1132 | +requires_stack_frame_p (rtx insn) | ||
| 1133 | +{ | ||
| 1134 | + HARD_REG_SET hardregs; | ||
| 1135 | + unsigned regno; | ||
| 1136 | + | ||
| 1137 | + if (!INSN_P (insn) || DEBUG_INSN_P (insn)) | ||
| 1138 | + return false; | ||
| 1139 | + if (CALL_P (insn)) | ||
| 1140 | + return !SIBLING_CALL_P (insn); | ||
| 1141 | + if (for_each_rtx (&PATTERN (insn), frame_required_for_rtx, NULL)) | ||
| 1142 | + return true; | ||
| 1143 | + CLEAR_HARD_REG_SET (hardregs); | ||
| 1144 | + note_stores (PATTERN (insn), record_hard_reg_sets, &hardregs); | ||
| 1145 | + AND_COMPL_HARD_REG_SET (hardregs, call_used_reg_set); | ||
| 1146 | + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | ||
| 1147 | + if (TEST_HARD_REG_BIT (hardregs, regno) | ||
| 1148 | + && df_regs_ever_live_p (regno)) | ||
| 1149 | + return true; | ||
| 1150 | + return false; | ||
| 1151 | +} | ||
| 1152 | +#endif | ||
| 1153 | + | ||
| 1154 | #ifdef HAVE_return | ||
| 1155 | -/* Insert gen_return at the end of block BB. This also means updating | ||
| 1156 | - block_for_insn appropriately. */ | ||
| 1157 | + | ||
| 1158 | +static rtx | ||
| 1159 | +gen_return_pattern (bool simple_p) | ||
| 1160 | +{ | ||
| 1161 | +#ifdef HAVE_simple_return | ||
| 1162 | + return simple_p ? gen_simple_return () : gen_return (); | ||
| 1163 | +#else | ||
| 1164 | + gcc_assert (!simple_p); | ||
| 1165 | + return gen_return (); | ||
| 1166 | +#endif | ||
| 1167 | +} | ||
| 1168 | + | ||
| 1169 | +/* Insert an appropriate return pattern at the end of block BB. This | ||
| 1170 | + also means updating block_for_insn appropriately. */ | ||
| 1171 | |||
| 1172 | static void | ||
| 1173 | -emit_return_into_block (basic_block bb) | ||
| 1174 | +emit_return_into_block (bool simple_p, basic_block bb) | ||
| 1175 | { | ||
| 1176 | - emit_jump_insn_after (gen_return (), BB_END (bb)); | ||
| 1177 | + rtx jump; | ||
| 1178 | + jump = emit_jump_insn_after (gen_return_pattern (simple_p), BB_END (bb)); | ||
| 1179 | + JUMP_LABEL (jump) = simple_p ? simple_return_rtx : ret_rtx; | ||
| 1180 | } | ||
| 1181 | -#endif /* HAVE_return */ | ||
| 1182 | +#endif | ||
| 1183 | |||
| 1184 | /* Generate the prologue and epilogue RTL if the machine supports it. Thread | ||
| 1185 | this into place with notes indicating where the prologue ends and where | ||
| 1186 | - the epilogue begins. Update the basic block information when possible. */ | ||
| 1187 | + the epilogue begins. Update the basic block information when possible. | ||
| 1188 | + | ||
| 1189 | + Notes on epilogue placement: | ||
| 1190 | + There are several kinds of edges to the exit block: | ||
| 1191 | + * a single fallthru edge from LAST_BB | ||
| 1192 | + * possibly, edges from blocks containing sibcalls | ||
| 1193 | + * possibly, fake edges from infinite loops | ||
| 1194 | + | ||
| 1195 | + The epilogue is always emitted on the fallthru edge from the last basic | ||
| 1196 | + block in the function, LAST_BB, into the exit block. | ||
| 1197 | + | ||
| 1198 | + If LAST_BB is empty except for a label, it is the target of every | ||
| 1199 | + other basic block in the function that ends in a return. If a | ||
| 1200 | + target has a return or simple_return pattern (possibly with | ||
| 1201 | + conditional variants), these basic blocks can be changed so that a | ||
| 1202 | + return insn is emitted into them, and their target is adjusted to | ||
| 1203 | + the real exit block. | ||
| 1204 | + | ||
| 1205 | + Notes on shrink wrapping: We implement a fairly conservative | ||
| 1206 | + version of shrink-wrapping rather than the textbook one. We only | ||
| 1207 | + generate a single prologue and a single epilogue. This is | ||
| 1208 | + sufficient to catch a number of interesting cases involving early | ||
| 1209 | + exits. | ||
| 1210 | + | ||
| 1211 | + First, we identify the blocks that require the prologue to occur before | ||
| 1212 | + them. These are the ones that modify a call-saved register, or reference | ||
| 1213 | + any of the stack or frame pointer registers. To simplify things, we then | ||
| 1214 | + mark everything reachable from these blocks as also requiring a prologue. | ||
| 1215 | + This takes care of loops automatically, and avoids the need to examine | ||
| 1216 | + whether MEMs reference the frame, since it is sufficient to check for | ||
| 1217 | + occurrences of the stack or frame pointer. | ||
| 1218 | + | ||
| 1219 | + We then compute the set of blocks for which the need for a prologue | ||
| 1220 | + is anticipatable (borrowing terminology from the shrink-wrapping | ||
| 1221 | + description in Muchnick's book). These are the blocks which either | ||
| 1222 | + require a prologue themselves, or those that have only successors | ||
| 1223 | + where the prologue is anticipatable. The prologue needs to be | ||
| 1224 | + inserted on all edges from BB1->BB2 where BB2 is in ANTIC and BB1 | ||
| 1225 | + is not. For the moment, we ensure that only one such edge exists. | ||
| 1226 | + | ||
| 1227 | + The epilogue is placed as described above, but we make a | ||
| 1228 | + distinction between inserting return and simple_return patterns | ||
| 1229 | + when modifying other blocks that end in a return. Blocks that end | ||
| 1230 | + in a sibcall omit the sibcall_epilogue if the block is not in | ||
| 1231 | + ANTIC. */ | ||
| 1232 | |||
| 1233 | static void | ||
| 1234 | thread_prologue_and_epilogue_insns (void) | ||
| 1235 | { | ||
| 1236 | int inserted = 0; | ||
| 1237 | + basic_block last_bb; | ||
| 1238 | + bool last_bb_active; | ||
| 1239 | +#ifdef HAVE_simple_return | ||
| 1240 | + bool unconverted_simple_returns = false; | ||
| 1241 | + basic_block simple_return_block = NULL; | ||
| 1242 | +#endif | ||
| 1243 | + rtx returnjump ATTRIBUTE_UNUSED; | ||
| 1244 | + rtx seq ATTRIBUTE_UNUSED, epilogue_end ATTRIBUTE_UNUSED; | ||
| 1245 | + rtx prologue_seq ATTRIBUTE_UNUSED, split_prologue_seq ATTRIBUTE_UNUSED; | ||
| 1246 | + edge entry_edge, orig_entry_edge, exit_fallthru_edge; | ||
| 1247 | edge e; | ||
| 1248 | -#if defined (HAVE_sibcall_epilogue) || defined (HAVE_epilogue) || defined (HAVE_return) || defined (HAVE_prologue) | ||
| 1249 | - rtx seq; | ||
| 1250 | -#endif | ||
| 1251 | -#if defined (HAVE_epilogue) || defined(HAVE_return) | ||
| 1252 | - rtx epilogue_end = NULL_RTX; | ||
| 1253 | -#endif | ||
| 1254 | edge_iterator ei; | ||
| 1255 | + bitmap_head bb_flags; | ||
| 1256 | + | ||
| 1257 | + df_analyze (); | ||
| 1258 | |||
| 1259 | rtl_profile_for_bb (ENTRY_BLOCK_PTR); | ||
| 1260 | + | ||
| 1261 | + epilogue_end = NULL_RTX; | ||
| 1262 | + | ||
| 1263 | + /* Can't deal with multiple successors of the entry block at the | ||
| 1264 | + moment. Function should always have at least one entry | ||
| 1265 | + point. */ | ||
| 1266 | + gcc_assert (single_succ_p (ENTRY_BLOCK_PTR)); | ||
| 1267 | + entry_edge = single_succ_edge (ENTRY_BLOCK_PTR); | ||
| 1268 | + orig_entry_edge = entry_edge; | ||
| 1269 | + | ||
| 1270 | + exit_fallthru_edge = find_fallthru_edge (EXIT_BLOCK_PTR->preds); | ||
| 1271 | + if (exit_fallthru_edge != NULL) | ||
| 1272 | + { | ||
| 1273 | + rtx label; | ||
| 1274 | + | ||
| 1275 | + last_bb = exit_fallthru_edge->src; | ||
| 1276 | + /* Test whether there are active instructions in the last block. */ | ||
| 1277 | + label = BB_END (last_bb); | ||
| 1278 | + while (label && !LABEL_P (label)) | ||
| 1279 | + { | ||
| 1280 | + if (active_insn_p (label)) | ||
| 1281 | + break; | ||
| 1282 | + label = PREV_INSN (label); | ||
| 1283 | + } | ||
| 1284 | + | ||
| 1285 | + last_bb_active = BB_HEAD (last_bb) != label || !LABEL_P (label); | ||
| 1286 | + } | ||
| 1287 | + else | ||
| 1288 | + { | ||
| 1289 | + last_bb = NULL; | ||
| 1290 | + last_bb_active = false; | ||
| 1291 | + } | ||
| 1292 | + | ||
| 1293 | #ifdef HAVE_prologue | ||
| 1294 | if (HAVE_prologue) | ||
| 1295 | { | ||
| 1296 | @@ -5040,19 +5191,168 @@ | ||
| 1297 | emit_insn (gen_blockage ()); | ||
| 1298 | #endif | ||
| 1299 | |||
| 1300 | - seq = get_insns (); | ||
| 1301 | + prologue_seq = get_insns (); | ||
| 1302 | end_sequence (); | ||
| 1303 | set_insn_locators (seq, prologue_locator); | ||
| 1304 | - | ||
| 1305 | - /* Can't deal with multiple successors of the entry block | ||
| 1306 | - at the moment. Function should always have at least one | ||
| 1307 | - entry point. */ | ||
| 1308 | - gcc_assert (single_succ_p (ENTRY_BLOCK_PTR)); | ||
| 1309 | - | ||
| 1310 | - insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR)); | ||
| 1311 | - inserted = 1; | ||
| 1312 | - } | ||
| 1313 | -#endif | ||
| 1314 | + } | ||
| 1315 | +#endif | ||
| 1316 | + | ||
| 1317 | + bitmap_initialize (&bb_flags, &bitmap_default_obstack); | ||
| 1318 | + | ||
| 1319 | +#ifdef HAVE_simple_return | ||
| 1320 | + /* Try to perform a kind of shrink-wrapping, making sure the | ||
| 1321 | + prologue/epilogue is emitted only around those parts of the | ||
| 1322 | + function that require it. */ | ||
| 1323 | + | ||
| 1324 | + if (flag_shrink_wrap && HAVE_simple_return && !flag_non_call_exceptions | ||
| 1325 | + && HAVE_prologue && !crtl->calls_eh_return) | ||
| 1326 | + { | ||
| 1327 | + HARD_REG_SET prologue_clobbered, live_on_edge; | ||
| 1328 | + rtx p_insn; | ||
| 1329 | + VEC(basic_block, heap) *vec; | ||
| 1330 | + basic_block bb; | ||
| 1331 | + bitmap_head bb_antic_flags; | ||
| 1332 | + bitmap_head bb_on_list; | ||
| 1333 | + | ||
| 1334 | + bitmap_initialize (&bb_antic_flags, &bitmap_default_obstack); | ||
| 1335 | + bitmap_initialize (&bb_on_list, &bitmap_default_obstack); | ||
| 1336 | + | ||
| 1337 | + vec = VEC_alloc (basic_block, heap, n_basic_blocks); | ||
| 1338 | + | ||
| 1339 | + FOR_EACH_BB (bb) | ||
| 1340 | + { | ||
| 1341 | + rtx insn; | ||
| 1342 | + FOR_BB_INSNS (bb, insn) | ||
| 1343 | + { | ||
| 1344 | + if (requires_stack_frame_p (insn)) | ||
| 1345 | + { | ||
| 1346 | + bitmap_set_bit (&bb_flags, bb->index); | ||
| 1347 | + VEC_quick_push (basic_block, vec, bb); | ||
| 1348 | + break; | ||
| 1349 | + } | ||
| 1350 | + } | ||
| 1351 | + } | ||
| 1352 | + | ||
| 1353 | + /* For every basic block that needs a prologue, mark all blocks | ||
| 1354 | + reachable from it, so as to ensure they are also seen as | ||
| 1355 | + requiring a prologue. */ | ||
| 1356 | + while (!VEC_empty (basic_block, vec)) | ||
| 1357 | + { | ||
| 1358 | + basic_block tmp_bb = VEC_pop (basic_block, vec); | ||
| 1359 | + edge e; | ||
| 1360 | + edge_iterator ei; | ||
| 1361 | + FOR_EACH_EDGE (e, ei, tmp_bb->succs) | ||
| 1362 | + { | ||
| 1363 | + if (e->dest == EXIT_BLOCK_PTR | ||
| 1364 | + || bitmap_bit_p (&bb_flags, e->dest->index)) | ||
| 1365 | + continue; | ||
| 1366 | + bitmap_set_bit (&bb_flags, e->dest->index); | ||
| 1367 | + VEC_quick_push (basic_block, vec, e->dest); | ||
| 1368 | + } | ||
| 1369 | + } | ||
| 1370 | + /* If the last basic block contains only a label, we'll be able | ||
| 1371 | + to convert jumps to it to (potentially conditional) return | ||
| 1372 | + insns later. This means we don't necessarily need a prologue | ||
| 1373 | + for paths reaching it. */ | ||
| 1374 | + if (last_bb) | ||
| 1375 | + { | ||
| 1376 | + if (!last_bb_active) | ||
| 1377 | + bitmap_clear_bit (&bb_flags, last_bb->index); | ||
| 1378 | + else if (!bitmap_bit_p (&bb_flags, last_bb->index)) | ||
| 1379 | + goto fail_shrinkwrap; | ||
| 1380 | + } | ||
| 1381 | + | ||
| 1382 | + /* Now walk backwards from every block that is marked as needing | ||
| 1383 | + a prologue to compute the bb_antic_flags bitmap. */ | ||
| 1384 | + bitmap_copy (&bb_antic_flags, &bb_flags); | ||
| 1385 | + FOR_EACH_BB (bb) | ||
| 1386 | + { | ||
| 1387 | + edge e; | ||
| 1388 | + edge_iterator ei; | ||
| 1389 | + if (!bitmap_bit_p (&bb_flags, bb->index)) | ||
| 1390 | + continue; | ||
| 1391 | + FOR_EACH_EDGE (e, ei, bb->preds) | ||
| 1392 | + if (!bitmap_bit_p (&bb_antic_flags, e->src->index)) | ||
| 1393 | + { | ||
| 1394 | + VEC_quick_push (basic_block, vec, e->src); | ||
| 1395 | + bitmap_set_bit (&bb_on_list, e->src->index); | ||
| 1396 | + } | ||
| 1397 | + } | ||
| 1398 | + while (!VEC_empty (basic_block, vec)) | ||
| 1399 | + { | ||
| 1400 | + basic_block tmp_bb = VEC_pop (basic_block, vec); | ||
| 1401 | + edge e; | ||
| 1402 | + edge_iterator ei; | ||
| 1403 | + bool all_set = true; | ||
| 1404 | + | ||
| 1405 | + bitmap_clear_bit (&bb_on_list, tmp_bb->index); | ||
| 1406 | + FOR_EACH_EDGE (e, ei, tmp_bb->succs) | ||
| 1407 | + { | ||
| 1408 | + if (!bitmap_bit_p (&bb_antic_flags, e->dest->index)) | ||
| 1409 | + { | ||
| 1410 | + all_set = false; | ||
| 1411 | + break; | ||
| 1412 | + } | ||
| 1413 | + } | ||
| 1414 | + if (all_set) | ||
| 1415 | + { | ||
| 1416 | + bitmap_set_bit (&bb_antic_flags, tmp_bb->index); | ||
| 1417 | + FOR_EACH_EDGE (e, ei, tmp_bb->preds) | ||
| 1418 | + if (!bitmap_bit_p (&bb_antic_flags, e->src->index)) | ||
| 1419 | + { | ||
| 1420 | + VEC_quick_push (basic_block, vec, e->src); | ||
| 1421 | + bitmap_set_bit (&bb_on_list, e->src->index); | ||
| 1422 | + } | ||
| 1423 | + } | ||
| 1424 | + } | ||
| 1425 | + /* Find exactly one edge that leads to a block in ANTIC from | ||
| 1426 | + a block that isn't. */ | ||
| 1427 | + if (!bitmap_bit_p (&bb_antic_flags, entry_edge->dest->index)) | ||
| 1428 | + FOR_EACH_BB (bb) | ||
| 1429 | + { | ||
| 1430 | + if (!bitmap_bit_p (&bb_antic_flags, bb->index)) | ||
| 1431 | + continue; | ||
| 1432 | + FOR_EACH_EDGE (e, ei, bb->preds) | ||
| 1433 | + if (!bitmap_bit_p (&bb_antic_flags, e->src->index)) | ||
| 1434 | + { | ||
| 1435 | + if (entry_edge != orig_entry_edge) | ||
| 1436 | + { | ||
| 1437 | + entry_edge = orig_entry_edge; | ||
| 1438 | + goto fail_shrinkwrap; | ||
| 1439 | + } | ||
| 1440 | + entry_edge = e; | ||
| 1441 | + } | ||
| 1442 | + } | ||
| 1443 | + | ||
| 1444 | + /* Test whether the prologue is known to clobber any register | ||
| 1445 | + (other than FP or SP) which are live on the edge. */ | ||
| 1446 | + CLEAR_HARD_REG_SET (prologue_clobbered); | ||
| 1447 | + for (p_insn = prologue_seq; p_insn; p_insn = NEXT_INSN (p_insn)) | ||
| 1448 | + if (NONDEBUG_INSN_P (p_insn)) | ||
| 1449 | + note_stores (PATTERN (p_insn), record_hard_reg_sets, | ||
| 1450 | + &prologue_clobbered); | ||
| 1451 | + CLEAR_HARD_REG_BIT (prologue_clobbered, STACK_POINTER_REGNUM); | ||
| 1452 | + if (frame_pointer_needed) | ||
| 1453 | + CLEAR_HARD_REG_BIT (prologue_clobbered, HARD_FRAME_POINTER_REGNUM); | ||
| 1454 | + | ||
| 1455 | + CLEAR_HARD_REG_SET (live_on_edge); | ||
| 1456 | + reg_set_to_hard_reg_set (&live_on_edge, | ||
| 1457 | + df_get_live_in (entry_edge->dest)); | ||
| 1458 | + if (hard_reg_set_intersect_p (live_on_edge, prologue_clobbered)) | ||
| 1459 | + entry_edge = orig_entry_edge; | ||
| 1460 | + | ||
| 1461 | + fail_shrinkwrap: | ||
| 1462 | + bitmap_clear (&bb_antic_flags); | ||
| 1463 | + bitmap_clear (&bb_on_list); | ||
| 1464 | + VEC_free (basic_block, heap, vec); | ||
| 1465 | + } | ||
| 1466 | +#endif | ||
| 1467 | + | ||
| 1468 | + if (prologue_seq != NULL_RTX) | ||
| 1469 | + { | ||
| 1470 | + insert_insn_on_edge (prologue_seq, entry_edge); | ||
| 1471 | + inserted = true; | ||
| 1472 | + } | ||
| 1473 | |||
| 1474 | /* If the exit block has no non-fake predecessors, we don't need | ||
| 1475 | an epilogue. */ | ||
| 1476 | @@ -5063,100 +5363,130 @@ | ||
| 1477 | goto epilogue_done; | ||
| 1478 | |||
| 1479 | rtl_profile_for_bb (EXIT_BLOCK_PTR); | ||
| 1480 | + | ||
| 1481 | #ifdef HAVE_return | ||
| 1482 | - if (optimize && HAVE_return) | ||
| 1483 | + /* If we're allowed to generate a simple return instruction, then by | ||
| 1484 | + definition we don't need a full epilogue. If the last basic | ||
| 1485 | + block before the exit block does not contain active instructions, | ||
| 1486 | + examine its predecessors and try to emit (conditional) return | ||
| 1487 | + instructions. */ | ||
| 1488 | + if (optimize && !last_bb_active | ||
| 1489 | + && (HAVE_return || entry_edge != orig_entry_edge)) | ||
| 1490 | { | ||
| 1491 | - /* If we're allowed to generate a simple return instruction, | ||
| 1492 | - then by definition we don't need a full epilogue. Examine | ||
| 1493 | - the block that falls through to EXIT. If it does not | ||
| 1494 | - contain any code, examine its predecessors and try to | ||
| 1495 | - emit (conditional) return instructions. */ | ||
| 1496 | - | ||
| 1497 | - basic_block last; | ||
| 1498 | + edge_iterator ei2; | ||
| 1499 | + int i; | ||
| 1500 | + basic_block bb; | ||
| 1501 | rtx label; | ||
| 1502 | + VEC(basic_block,heap) *src_bbs; | ||
| 1503 | |||
| 1504 | - FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) | ||
| 1505 | - if (e->flags & EDGE_FALLTHRU) | ||
| 1506 | - break; | ||
| 1507 | - if (e == NULL) | ||
| 1508 | + if (exit_fallthru_edge == NULL) | ||
| 1509 | goto epilogue_done; | ||
| 1510 | - last = e->src; | ||
| 1511 | - | ||
| 1512 | - /* Verify that there are no active instructions in the last block. */ | ||
| 1513 | - label = BB_END (last); | ||
| 1514 | - while (label && !LABEL_P (label)) | ||
| 1515 | + label = BB_HEAD (last_bb); | ||
| 1516 | + | ||
| 1517 | + src_bbs = VEC_alloc (basic_block, heap, EDGE_COUNT (last_bb->preds)); | ||
| 1518 | + FOR_EACH_EDGE (e, ei2, last_bb->preds) | ||
| 1519 | + if (e->src != ENTRY_BLOCK_PTR) | ||
| 1520 | + VEC_quick_push (basic_block, src_bbs, e->src); | ||
| 1521 | + | ||
| 1522 | + FOR_EACH_VEC_ELT (basic_block, src_bbs, i, bb) | ||
| 1523 | { | ||
| 1524 | - if (active_insn_p (label)) | ||
| 1525 | - break; | ||
| 1526 | - label = PREV_INSN (label); | ||
| 1527 | + bool simple_p; | ||
| 1528 | + rtx jump; | ||
| 1529 | + e = find_edge (bb, last_bb); | ||
| 1530 | + | ||
| 1531 | + jump = BB_END (bb); | ||
| 1532 | + | ||
| 1533 | +#ifdef HAVE_simple_return | ||
| 1534 | + simple_p = (entry_edge != orig_entry_edge | ||
| 1535 | + ? !bitmap_bit_p (&bb_flags, bb->index) : false); | ||
| 1536 | +#else | ||
| 1537 | + simple_p = false; | ||
| 1538 | +#endif | ||
| 1539 | + | ||
| 1540 | + if (!simple_p | ||
| 1541 | + && (!HAVE_return || !JUMP_P (jump) | ||
| 1542 | + || JUMP_LABEL (jump) != label)) | ||
| 1543 | + continue; | ||
| 1544 | + | ||
| 1545 | + /* If we have an unconditional jump, we can replace that | ||
| 1546 | + with a simple return instruction. */ | ||
| 1547 | + if (!JUMP_P (jump)) | ||
| 1548 | + { | ||
| 1549 | + emit_barrier_after (BB_END (bb)); | ||
| 1550 | + emit_return_into_block (simple_p, bb); | ||
| 1551 | + } | ||
| 1552 | + else if (simplejump_p (jump)) | ||
| 1553 | + { | ||
| 1554 | + emit_return_into_block (simple_p, bb); | ||
| 1555 | + delete_insn (jump); | ||
| 1556 | + } | ||
| 1557 | + else if (condjump_p (jump) && JUMP_LABEL (jump) != label) | ||
| 1558 | + { | ||
| 1559 | + basic_block new_bb; | ||
| 1560 | + edge new_e; | ||
| 1561 | + | ||
| 1562 | + gcc_assert (simple_p); | ||
| 1563 | + new_bb = split_edge (e); | ||
| 1564 | + emit_barrier_after (BB_END (new_bb)); | ||
| 1565 | + emit_return_into_block (simple_p, new_bb); | ||
| 1566 | +#ifdef HAVE_simple_return | ||
| 1567 | + simple_return_block = new_bb; | ||
| 1568 | +#endif | ||
| 1569 | + new_e = single_succ_edge (new_bb); | ||
| 1570 | + redirect_edge_succ (new_e, EXIT_BLOCK_PTR); | ||
| 1571 | + | ||
| 1572 | + continue; | ||
| 1573 | + } | ||
| 1574 | + /* If we have a conditional jump branching to the last | ||
| 1575 | + block, we can try to replace that with a conditional | ||
| 1576 | + return instruction. */ | ||
| 1577 | + else if (condjump_p (jump)) | ||
| 1578 | + { | ||
| 1579 | + rtx dest; | ||
| 1580 | + if (simple_p) | ||
| 1581 | + dest = simple_return_rtx; | ||
| 1582 | + else | ||
| 1583 | + dest = ret_rtx; | ||
| 1584 | + if (! redirect_jump (jump, dest, 0)) | ||
| 1585 | + { | ||
| 1586 | +#ifdef HAVE_simple_return | ||
| 1587 | + if (simple_p) | ||
| 1588 | + unconverted_simple_returns = true; | ||
| 1589 | +#endif | ||
| 1590 | + continue; | ||
| 1591 | + } | ||
| 1592 | + | ||
| 1593 | + /* If this block has only one successor, it both jumps | ||
| 1594 | + and falls through to the fallthru block, so we can't | ||
| 1595 | + delete the edge. */ | ||
| 1596 | + if (single_succ_p (bb)) | ||
| 1597 | + continue; | ||
| 1598 | + } | ||
| 1599 | + else | ||
| 1600 | + { | ||
| 1601 | +#ifdef HAVE_simple_return | ||
| 1602 | + if (simple_p) | ||
| 1603 | + unconverted_simple_returns = true; | ||
| 1604 | +#endif | ||
| 1605 | + continue; | ||
| 1606 | + } | ||
| 1607 | + | ||
| 1608 | + /* Fix up the CFG for the successful change we just made. */ | ||
| 1609 | + redirect_edge_succ (e, EXIT_BLOCK_PTR); | ||
| 1610 | } | ||
| 1611 | + VEC_free (basic_block, heap, src_bbs); | ||
| 1612 | |||
| 1613 | - if (BB_HEAD (last) == label && LABEL_P (label)) | ||
| 1614 | + if (HAVE_return) | ||
| 1615 | { | ||
| 1616 | - edge_iterator ei2; | ||
| 1617 | - | ||
| 1618 | - for (ei2 = ei_start (last->preds); (e = ei_safe_edge (ei2)); ) | ||
| 1619 | - { | ||
| 1620 | - basic_block bb = e->src; | ||
| 1621 | - rtx jump; | ||
| 1622 | - | ||
| 1623 | - if (bb == ENTRY_BLOCK_PTR) | ||
| 1624 | - { | ||
| 1625 | - ei_next (&ei2); | ||
| 1626 | - continue; | ||
| 1627 | - } | ||
| 1628 | - | ||
| 1629 | - jump = BB_END (bb); | ||
| 1630 | - if (!JUMP_P (jump) || JUMP_LABEL (jump) != label) | ||
| 1631 | - { | ||
| 1632 | - ei_next (&ei2); | ||
| 1633 | - continue; | ||
| 1634 | - } | ||
| 1635 | - | ||
| 1636 | - /* If we have an unconditional jump, we can replace that | ||
| 1637 | - with a simple return instruction. */ | ||
| 1638 | - if (simplejump_p (jump)) | ||
| 1639 | - { | ||
| 1640 | - emit_return_into_block (bb); | ||
| 1641 | - delete_insn (jump); | ||
| 1642 | - } | ||
| 1643 | - | ||
| 1644 | - /* If we have a conditional jump, we can try to replace | ||
| 1645 | - that with a conditional return instruction. */ | ||
| 1646 | - else if (condjump_p (jump)) | ||
| 1647 | - { | ||
| 1648 | - if (! redirect_jump (jump, 0, 0)) | ||
| 1649 | - { | ||
| 1650 | - ei_next (&ei2); | ||
| 1651 | - continue; | ||
| 1652 | - } | ||
| 1653 | - | ||
| 1654 | - /* If this block has only one successor, it both jumps | ||
| 1655 | - and falls through to the fallthru block, so we can't | ||
| 1656 | - delete the edge. */ | ||
| 1657 | - if (single_succ_p (bb)) | ||
| 1658 | - { | ||
| 1659 | - ei_next (&ei2); | ||
| 1660 | - continue; | ||
| 1661 | - } | ||
| 1662 | - } | ||
| 1663 | - else | ||
| 1664 | - { | ||
| 1665 | - ei_next (&ei2); | ||
| 1666 | - continue; | ||
| 1667 | - } | ||
| 1668 | - | ||
| 1669 | - /* Fix up the CFG for the successful change we just made. */ | ||
| 1670 | - redirect_edge_succ (e, EXIT_BLOCK_PTR); | ||
| 1671 | - } | ||
| 1672 | - | ||
| 1673 | /* Emit a return insn for the exit fallthru block. Whether | ||
| 1674 | this is still reachable will be determined later. */ | ||
| 1675 | |||
| 1676 | - emit_barrier_after (BB_END (last)); | ||
| 1677 | - emit_return_into_block (last); | ||
| 1678 | - epilogue_end = BB_END (last); | ||
| 1679 | - single_succ_edge (last)->flags &= ~EDGE_FALLTHRU; | ||
| 1680 | + emit_barrier_after (BB_END (last_bb)); | ||
| 1681 | + emit_return_into_block (false, last_bb); | ||
| 1682 | + epilogue_end = BB_END (last_bb); | ||
| 1683 | + if (JUMP_P (epilogue_end)) | ||
| 1684 | + JUMP_LABEL (epilogue_end) = ret_rtx; | ||
| 1685 | + single_succ_edge (last_bb)->flags &= ~EDGE_FALLTHRU; | ||
| 1686 | goto epilogue_done; | ||
| 1687 | } | ||
| 1688 | } | ||
| 1689 | @@ -5193,15 +5523,10 @@ | ||
| 1690 | } | ||
| 1691 | #endif | ||
| 1692 | |||
| 1693 | - /* Find the edge that falls through to EXIT. Other edges may exist | ||
| 1694 | - due to RETURN instructions, but those don't need epilogues. | ||
| 1695 | - There really shouldn't be a mixture -- either all should have | ||
| 1696 | - been converted or none, however... */ | ||
| 1697 | + /* If nothing falls through into the exit block, we don't need an | ||
| 1698 | + epilogue. */ | ||
| 1699 | |||
| 1700 | - FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) | ||
| 1701 | - if (e->flags & EDGE_FALLTHRU) | ||
| 1702 | - break; | ||
| 1703 | - if (e == NULL) | ||
| 1704 | + if (exit_fallthru_edge == NULL) | ||
| 1705 | goto epilogue_done; | ||
| 1706 | |||
| 1707 | #ifdef HAVE_epilogue | ||
| 1708 | @@ -5217,25 +5542,38 @@ | ||
| 1709 | set_insn_locators (seq, epilogue_locator); | ||
| 1710 | |||
| 1711 | seq = get_insns (); | ||
| 1712 | + returnjump = get_last_insn (); | ||
| 1713 | end_sequence (); | ||
| 1714 | |||
| 1715 | - insert_insn_on_edge (seq, e); | ||
| 1716 | + insert_insn_on_edge (seq, exit_fallthru_edge); | ||
| 1717 | inserted = 1; | ||
| 1718 | + if (JUMP_P (returnjump)) | ||
| 1719 | + { | ||
| 1720 | + rtx pat = PATTERN (returnjump); | ||
| 1721 | + if (GET_CODE (pat) == PARALLEL) | ||
| 1722 | + pat = XVECEXP (pat, 0, 0); | ||
| 1723 | + if (ANY_RETURN_P (pat)) | ||
| 1724 | + JUMP_LABEL (returnjump) = pat; | ||
| 1725 | + else | ||
| 1726 | + JUMP_LABEL (returnjump) = ret_rtx; | ||
| 1727 | + } | ||
| 1728 | + else | ||
| 1729 | + returnjump = NULL_RTX; | ||
| 1730 | } | ||
| 1731 | else | ||
| 1732 | #endif | ||
| 1733 | { | ||
| 1734 | basic_block cur_bb; | ||
| 1735 | |||
| 1736 | - if (! next_active_insn (BB_END (e->src))) | ||
| 1737 | + if (! next_active_insn (BB_END (exit_fallthru_edge->src))) | ||
| 1738 | goto epilogue_done; | ||
| 1739 | /* We have a fall-through edge to the exit block, the source is not | ||
| 1740 | - at the end of the function, and there will be an assembler epilogue | ||
| 1741 | - at the end of the function. | ||
| 1742 | - We can't use force_nonfallthru here, because that would try to | ||
| 1743 | - use return. Inserting a jump 'by hand' is extremely messy, so | ||
| 1744 | + at the end of the function, and there will be an assembler epilogue | ||
| 1745 | + at the end of the function. | ||
| 1746 | + We can't use force_nonfallthru here, because that would try to | ||
| 1747 | + use return. Inserting a jump 'by hand' is extremely messy, so | ||
| 1748 | we take advantage of cfg_layout_finalize using | ||
| 1749 | - fixup_fallthru_exit_predecessor. */ | ||
| 1750 | + fixup_fallthru_exit_predecessor. */ | ||
| 1751 | cfg_layout_initialize (0); | ||
| 1752 | FOR_EACH_BB (cur_bb) | ||
| 1753 | if (cur_bb->index >= NUM_FIXED_BLOCKS | ||
| 1754 | @@ -5244,6 +5582,7 @@ | ||
| 1755 | cfg_layout_finalize (); | ||
| 1756 | } | ||
| 1757 | epilogue_done: | ||
| 1758 | + | ||
| 1759 | default_rtl_profile (); | ||
| 1760 | |||
| 1761 | if (inserted) | ||
| 1762 | @@ -5260,33 +5599,93 @@ | ||
| 1763 | } | ||
| 1764 | } | ||
| 1765 | |||
| 1766 | +#ifdef HAVE_simple_return | ||
| 1767 | + /* If there were branches to an empty LAST_BB which we tried to | ||
| 1768 | + convert to conditional simple_returns, but couldn't for some | ||
| 1769 | + reason, create a block to hold a simple_return insn and redirect | ||
| 1770 | + those remaining edges. */ | ||
| 1771 | + if (unconverted_simple_returns) | ||
| 1772 | + { | ||
| 1773 | + edge_iterator ei2; | ||
| 1774 | + basic_block exit_pred = EXIT_BLOCK_PTR->prev_bb; | ||
| 1775 | + | ||
| 1776 | + gcc_assert (entry_edge != orig_entry_edge); | ||
| 1777 | + | ||
| 1778 | +#ifdef HAVE_epilogue | ||
| 1779 | + if (simple_return_block == NULL && returnjump != NULL_RTX | ||
| 1780 | + && JUMP_LABEL (returnjump) == simple_return_rtx) | ||
| 1781 | + { | ||
| 1782 | + edge e = split_block (exit_fallthru_edge->src, | ||
| 1783 | + PREV_INSN (returnjump)); | ||
| 1784 | + simple_return_block = e->dest; | ||
| 1785 | + } | ||
| 1786 | +#endif | ||
| 1787 | + if (simple_return_block == NULL) | ||
| 1788 | + { | ||
| 1789 | + basic_block bb; | ||
| 1790 | + rtx start; | ||
| 1791 | + | ||
| 1792 | + bb = create_basic_block (NULL, NULL, exit_pred); | ||
| 1793 | + start = emit_jump_insn_after (gen_simple_return (), | ||
| 1794 | + BB_END (bb)); | ||
| 1795 | + JUMP_LABEL (start) = simple_return_rtx; | ||
| 1796 | + emit_barrier_after (start); | ||
| 1797 | + | ||
| 1798 | + simple_return_block = bb; | ||
| 1799 | + make_edge (bb, EXIT_BLOCK_PTR, 0); | ||
| 1800 | + } | ||
| 1801 | + | ||
| 1802 | + restart_scan: | ||
| 1803 | + for (ei2 = ei_start (last_bb->preds); (e = ei_safe_edge (ei2)); ) | ||
| 1804 | + { | ||
| 1805 | + basic_block bb = e->src; | ||
| 1806 | + | ||
| 1807 | + if (bb != ENTRY_BLOCK_PTR | ||
| 1808 | + && !bitmap_bit_p (&bb_flags, bb->index)) | ||
| 1809 | + { | ||
| 1810 | + redirect_edge_and_branch_force (e, simple_return_block); | ||
| 1811 | + goto restart_scan; | ||
| 1812 | + } | ||
| 1813 | + ei_next (&ei2); | ||
| 1814 | + | ||
| 1815 | + } | ||
| 1816 | + } | ||
| 1817 | +#endif | ||
| 1818 | + | ||
| 1819 | #ifdef HAVE_sibcall_epilogue | ||
| 1820 | /* Emit sibling epilogues before any sibling call sites. */ | ||
| 1821 | for (ei = ei_start (EXIT_BLOCK_PTR->preds); (e = ei_safe_edge (ei)); ) | ||
| 1822 | { | ||
| 1823 | basic_block bb = e->src; | ||
| 1824 | rtx insn = BB_END (bb); | ||
| 1825 | + rtx ep_seq; | ||
| 1826 | |||
| 1827 | if (!CALL_P (insn) | ||
| 1828 | - || ! SIBLING_CALL_P (insn)) | ||
| 1829 | + || ! SIBLING_CALL_P (insn) | ||
| 1830 | + || (entry_edge != orig_entry_edge | ||
| 1831 | + && !bitmap_bit_p (&bb_flags, bb->index))) | ||
| 1832 | { | ||
| 1833 | ei_next (&ei); | ||
| 1834 | continue; | ||
| 1835 | } | ||
| 1836 | |||
| 1837 | - start_sequence (); | ||
| 1838 | - emit_note (NOTE_INSN_EPILOGUE_BEG); | ||
| 1839 | - emit_insn (gen_sibcall_epilogue ()); | ||
| 1840 | - seq = get_insns (); | ||
| 1841 | - end_sequence (); | ||
| 1842 | - | ||
| 1843 | - /* Retain a map of the epilogue insns. Used in life analysis to | ||
| 1844 | - avoid getting rid of sibcall epilogue insns. Do this before we | ||
| 1845 | - actually emit the sequence. */ | ||
| 1846 | - record_insns (seq, NULL, &epilogue_insn_hash); | ||
| 1847 | - set_insn_locators (seq, epilogue_locator); | ||
| 1848 | - | ||
| 1849 | - emit_insn_before (seq, insn); | ||
| 1850 | + ep_seq = gen_sibcall_epilogue (); | ||
| 1851 | + if (ep_seq) | ||
| 1852 | + { | ||
| 1853 | + start_sequence (); | ||
| 1854 | + emit_note (NOTE_INSN_EPILOGUE_BEG); | ||
| 1855 | + emit_insn (ep_seq); | ||
| 1856 | + seq = get_insns (); | ||
| 1857 | + end_sequence (); | ||
| 1858 | + | ||
| 1859 | + /* Retain a map of the epilogue insns. Used in life analysis to | ||
| 1860 | + avoid getting rid of sibcall epilogue insns. Do this before we | ||
| 1861 | + actually emit the sequence. */ | ||
| 1862 | + record_insns (seq, NULL, &epilogue_insn_hash); | ||
| 1863 | + set_insn_locators (seq, epilogue_locator); | ||
| 1864 | + | ||
| 1865 | + emit_insn_before (seq, insn); | ||
| 1866 | + } | ||
| 1867 | ei_next (&ei); | ||
| 1868 | } | ||
| 1869 | #endif | ||
| 1870 | @@ -5311,6 +5710,8 @@ | ||
| 1871 | } | ||
| 1872 | #endif | ||
| 1873 | |||
| 1874 | + bitmap_clear (&bb_flags); | ||
| 1875 | + | ||
| 1876 | /* Threading the prologue and epilogue changes the artificial refs | ||
| 1877 | in the entry and exit blocks. */ | ||
| 1878 | epilogue_completed = 1; | ||
| 1879 | |||
| 1880 | === modified file 'gcc/genemit.c' | ||
| 1881 | --- old/gcc/genemit.c 2009-11-27 11:37:06 +0000 | ||
| 1882 | +++ new/gcc/genemit.c 2011-01-05 12:12:18 +0000 | ||
| 1883 | @@ -222,6 +222,12 @@ | ||
| 1884 | case PC: | ||
| 1885 | printf ("pc_rtx"); | ||
| 1886 | return; | ||
| 1887 | + case RETURN: | ||
| 1888 | + printf ("ret_rtx"); | ||
| 1889 | + return; | ||
| 1890 | + case SIMPLE_RETURN: | ||
| 1891 | + printf ("simple_return_rtx"); | ||
| 1892 | + return; | ||
| 1893 | case CLOBBER: | ||
| 1894 | if (REG_P (XEXP (x, 0))) | ||
| 1895 | { | ||
| 1896 | @@ -544,8 +550,8 @@ | ||
| 1897 | || (GET_CODE (next) == PARALLEL | ||
| 1898 | && ((GET_CODE (XVECEXP (next, 0, 0)) == SET | ||
| 1899 | && GET_CODE (SET_DEST (XVECEXP (next, 0, 0))) == PC) | ||
| 1900 | - || GET_CODE (XVECEXP (next, 0, 0)) == RETURN)) | ||
| 1901 | - || GET_CODE (next) == RETURN) | ||
| 1902 | + || ANY_RETURN_P (XVECEXP (next, 0, 0)))) | ||
| 1903 | + || ANY_RETURN_P (next)) | ||
| 1904 | printf (" emit_jump_insn ("); | ||
| 1905 | else if ((GET_CODE (next) == SET && GET_CODE (SET_SRC (next)) == CALL) | ||
| 1906 | || GET_CODE (next) == CALL | ||
| 1907 | @@ -660,7 +666,7 @@ | ||
| 1908 | || (GET_CODE (next) == PARALLEL | ||
| 1909 | && GET_CODE (XVECEXP (next, 0, 0)) == SET | ||
| 1910 | && GET_CODE (SET_DEST (XVECEXP (next, 0, 0))) == PC) | ||
| 1911 | - || GET_CODE (next) == RETURN) | ||
| 1912 | + || ANY_RETURN_P (next)) | ||
| 1913 | printf (" emit_jump_insn ("); | ||
| 1914 | else if ((GET_CODE (next) == SET && GET_CODE (SET_SRC (next)) == CALL) | ||
| 1915 | || GET_CODE (next) == CALL | ||
| 1916 | |||
| 1917 | === modified file 'gcc/gengenrtl.c' | ||
| 1918 | --- old/gcc/gengenrtl.c 2007-08-22 23:30:39 +0000 | ||
| 1919 | +++ new/gcc/gengenrtl.c 2011-01-05 12:12:18 +0000 | ||
| 1920 | @@ -146,6 +146,10 @@ | ||
| 1921 | || strcmp (defs[idx].enumname, "REG") == 0 | ||
| 1922 | || strcmp (defs[idx].enumname, "SUBREG") == 0 | ||
| 1923 | || strcmp (defs[idx].enumname, "MEM") == 0 | ||
| 1924 | + || strcmp (defs[idx].enumname, "PC") == 0 | ||
| 1925 | + || strcmp (defs[idx].enumname, "CC0") == 0 | ||
| 1926 | + || strcmp (defs[idx].enumname, "RETURN") == 0 | ||
| 1927 | + || strcmp (defs[idx].enumname, "SIMPLE_RETURN") == 0 | ||
| 1928 | || strcmp (defs[idx].enumname, "CONST_VECTOR") == 0); | ||
| 1929 | } | ||
| 1930 | |||
| 1931 | |||
| 1932 | === modified file 'gcc/haifa-sched.c' | ||
| 1933 | --- old/gcc/haifa-sched.c 2010-08-12 08:14:47 +0000 | ||
| 1934 | +++ new/gcc/haifa-sched.c 2011-01-05 12:12:18 +0000 | ||
| 1935 | @@ -4231,7 +4231,7 @@ | ||
| 1936 | /* Helper function. | ||
| 1937 | Find fallthru edge from PRED. */ | ||
| 1938 | edge | ||
| 1939 | -find_fallthru_edge (basic_block pred) | ||
| 1940 | +find_fallthru_edge_from (basic_block pred) | ||
| 1941 | { | ||
| 1942 | edge e; | ||
| 1943 | edge_iterator ei; | ||
| 1944 | @@ -4298,7 +4298,7 @@ | ||
| 1945 | edge e; | ||
| 1946 | |||
| 1947 | last = EXIT_BLOCK_PTR->prev_bb; | ||
| 1948 | - e = find_fallthru_edge (last); | ||
| 1949 | + e = find_fallthru_edge_from (last); | ||
| 1950 | |||
| 1951 | if (e) | ||
| 1952 | { | ||
| 1953 | @@ -5234,6 +5234,11 @@ | ||
| 1954 | gcc_assert (/* Usual case. */ | ||
| 1955 | (EDGE_COUNT (bb->succs) > 1 | ||
| 1956 | && !BARRIER_P (NEXT_INSN (head))) | ||
| 1957 | + /* Special cases, see cfglayout.c: | ||
| 1958 | + fixup_reorder_chain. */ | ||
| 1959 | + || (EDGE_COUNT (bb->succs) == 1 | ||
| 1960 | + && (!onlyjump_p (head) | ||
| 1961 | + || returnjump_p (head))) | ||
| 1962 | /* Or jump to the next instruction. */ | ||
| 1963 | || (EDGE_COUNT (bb->succs) == 1 | ||
| 1964 | && (BB_HEAD (EDGE_I (bb->succs, 0)->dest) | ||
| 1965 | |||
| 1966 | === modified file 'gcc/ifcvt.c' | ||
| 1967 | --- old/gcc/ifcvt.c 2010-11-26 12:03:32 +0000 | ||
| 1968 | +++ new/gcc/ifcvt.c 2011-01-05 12:12:18 +0000 | ||
| 1969 | @@ -105,7 +105,7 @@ | ||
| 1970 | static int find_if_case_2 (basic_block, edge, edge); | ||
| 1971 | static int find_memory (rtx *, void *); | ||
| 1972 | static int dead_or_predicable (basic_block, basic_block, basic_block, | ||
| 1973 | - basic_block, int); | ||
| 1974 | + edge, int); | ||
| 1975 | static void noce_emit_move_insn (rtx, rtx); | ||
| 1976 | static rtx block_has_only_trap (basic_block); | ||
| 1977 | |||
| 1978 | @@ -3791,6 +3791,7 @@ | ||
| 1979 | basic_block then_bb = then_edge->dest; | ||
| 1980 | basic_block else_bb = else_edge->dest; | ||
| 1981 | basic_block new_bb; | ||
| 1982 | + rtx else_target = NULL_RTX; | ||
| 1983 | int then_bb_index; | ||
| 1984 | |||
| 1985 | /* If we are partitioning hot/cold basic blocks, we don't want to | ||
| 1986 | @@ -3840,9 +3841,16 @@ | ||
| 1987 | predictable_edge_p (then_edge))))) | ||
| 1988 | return FALSE; | ||
| 1989 | |||
| 1990 | + if (else_bb == EXIT_BLOCK_PTR) | ||
| 1991 | + { | ||
| 1992 | + rtx jump = BB_END (else_edge->src); | ||
| 1993 | + gcc_assert (JUMP_P (jump)); | ||
| 1994 | + else_target = JUMP_LABEL (jump); | ||
| 1995 | + } | ||
| 1996 | + | ||
| 1997 | /* Registers set are dead, or are predicable. */ | ||
| 1998 | if (! dead_or_predicable (test_bb, then_bb, else_bb, | ||
| 1999 | - single_succ (then_bb), 1)) | ||
| 2000 | + single_succ_edge (then_bb), 1)) | ||
| 2001 | return FALSE; | ||
| 2002 | |||
| 2003 | /* Conversion went ok, including moving the insns and fixing up the | ||
| 2004 | @@ -3859,6 +3867,9 @@ | ||
| 2005 | redirect_edge_succ (FALLTHRU_EDGE (test_bb), else_bb); | ||
| 2006 | new_bb = 0; | ||
| 2007 | } | ||
| 2008 | + else if (else_bb == EXIT_BLOCK_PTR) | ||
| 2009 | + new_bb = force_nonfallthru_and_redirect (FALLTHRU_EDGE (test_bb), | ||
| 2010 | + else_bb, else_target); | ||
| 2011 | else | ||
| 2012 | new_bb = redirect_edge_and_branch_force (FALLTHRU_EDGE (test_bb), | ||
| 2013 | else_bb); | ||
| 2014 | @@ -3957,7 +3968,7 @@ | ||
| 2015 | return FALSE; | ||
| 2016 | |||
| 2017 | /* Registers set are dead, or are predicable. */ | ||
| 2018 | - if (! dead_or_predicable (test_bb, else_bb, then_bb, else_succ->dest, 0)) | ||
| 2019 | + if (! dead_or_predicable (test_bb, else_bb, then_bb, else_succ, 0)) | ||
| 2020 | return FALSE; | ||
| 2021 | |||
| 2022 | /* Conversion went ok, including moving the insns and fixing up the | ||
| 2023 | @@ -3995,12 +4006,34 @@ | ||
| 2024 | |||
| 2025 | static int | ||
| 2026 | dead_or_predicable (basic_block test_bb, basic_block merge_bb, | ||
| 2027 | - basic_block other_bb, basic_block new_dest, int reversep) | ||
| 2028 | + basic_block other_bb, edge dest_edge, int reversep) | ||
| 2029 | { | ||
| 2030 | - rtx head, end, jump, earliest = NULL_RTX, old_dest, new_label = NULL_RTX; | ||
| 2031 | + basic_block new_dest = dest_edge->dest; | ||
| 2032 | + rtx head, end, jump, earliest = NULL_RTX, old_dest; | ||
| 2033 | bitmap merge_set = NULL; | ||
| 2034 | /* Number of pending changes. */ | ||
| 2035 | int n_validated_changes = 0; | ||
| 2036 | + rtx new_dest_label; | ||
| 2037 | + | ||
| 2038 | + jump = BB_END (dest_edge->src); | ||
| 2039 | + if (JUMP_P (jump)) | ||
| 2040 | + { | ||
| 2041 | + new_dest_label = JUMP_LABEL (jump); | ||
| 2042 | + if (new_dest_label == NULL_RTX) | ||
| 2043 | + { | ||
| 2044 | + new_dest_label = PATTERN (jump); | ||
| 2045 | + gcc_assert (ANY_RETURN_P (new_dest_label)); | ||
| 2046 | + } | ||
| 2047 | + } | ||
| 2048 | + else if (other_bb != new_dest) | ||
| 2049 | + { | ||
| 2050 | + if (new_dest == EXIT_BLOCK_PTR) | ||
| 2051 | + new_dest_label = ret_rtx; | ||
| 2052 | + else | ||
| 2053 | + new_dest_label = block_label (new_dest); | ||
| 2054 | + } | ||
| 2055 | + else | ||
| 2056 | + new_dest_label = NULL_RTX; | ||
| 2057 | |||
| 2058 | jump = BB_END (test_bb); | ||
| 2059 | |||
| 2060 | @@ -4220,10 +4253,9 @@ | ||
| 2061 | old_dest = JUMP_LABEL (jump); | ||
| 2062 | if (other_bb != new_dest) | ||
| 2063 | { | ||
| 2064 | - new_label = block_label (new_dest); | ||
| 2065 | if (reversep | ||
| 2066 | - ? ! invert_jump_1 (jump, new_label) | ||
| 2067 | - : ! redirect_jump_1 (jump, new_label)) | ||
| 2068 | + ? ! invert_jump_1 (jump, new_dest_label) | ||
| 2069 | + : ! redirect_jump_1 (jump, new_dest_label)) | ||
| 2070 | goto cancel; | ||
| 2071 | } | ||
| 2072 | |||
| 2073 | @@ -4234,7 +4266,7 @@ | ||
| 2074 | |||
| 2075 | if (other_bb != new_dest) | ||
| 2076 | { | ||
| 2077 | - redirect_jump_2 (jump, old_dest, new_label, 0, reversep); | ||
| 2078 | + redirect_jump_2 (jump, old_dest, new_dest_label, 0, reversep); | ||
| 2079 | |||
| 2080 | redirect_edge_succ (BRANCH_EDGE (test_bb), new_dest); | ||
| 2081 | if (reversep) | ||
| 2082 | |||
| 2083 | === modified file 'gcc/jump.c' | ||
| 2084 | --- old/gcc/jump.c 2010-12-13 10:05:52 +0000 | ||
| 2085 | +++ new/gcc/jump.c 2011-01-05 12:12:18 +0000 | ||
| 2086 | @@ -29,7 +29,8 @@ | ||
| 2087 | JUMP_LABEL internal field. With this we can detect labels that | ||
| 2088 | become unused because of the deletion of all the jumps that | ||
| 2089 | formerly used them. The JUMP_LABEL info is sometimes looked | ||
| 2090 | - at by later passes. | ||
| 2091 | + at by later passes. For return insns, it contains either a | ||
| 2092 | + RETURN or a SIMPLE_RETURN rtx. | ||
| 2093 | |||
| 2094 | The subroutines redirect_jump and invert_jump are used | ||
| 2095 | from other passes as well. */ | ||
| 2096 | @@ -742,10 +743,10 @@ | ||
| 2097 | return (GET_CODE (x) == IF_THEN_ELSE | ||
| 2098 | && ((GET_CODE (XEXP (x, 2)) == PC | ||
| 2099 | && (GET_CODE (XEXP (x, 1)) == LABEL_REF | ||
| 2100 | - || GET_CODE (XEXP (x, 1)) == RETURN)) | ||
| 2101 | + || ANY_RETURN_P (XEXP (x, 1)))) | ||
| 2102 | || (GET_CODE (XEXP (x, 1)) == PC | ||
| 2103 | && (GET_CODE (XEXP (x, 2)) == LABEL_REF | ||
| 2104 | - || GET_CODE (XEXP (x, 2)) == RETURN)))); | ||
| 2105 | + || ANY_RETURN_P (XEXP (x, 2)))))); | ||
| 2106 | } | ||
| 2107 | |||
| 2108 | /* Return nonzero if INSN is a (possibly) conditional jump inside a | ||
| 2109 | @@ -774,11 +775,11 @@ | ||
| 2110 | return 0; | ||
| 2111 | if (XEXP (SET_SRC (x), 2) == pc_rtx | ||
| 2112 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF | ||
| 2113 | - || GET_CODE (XEXP (SET_SRC (x), 1)) == RETURN)) | ||
| 2114 | + || ANY_RETURN_P (XEXP (SET_SRC (x), 1)) == RETURN)) | ||
| 2115 | return 1; | ||
| 2116 | if (XEXP (SET_SRC (x), 1) == pc_rtx | ||
| 2117 | && (GET_CODE (XEXP (SET_SRC (x), 2)) == LABEL_REF | ||
| 2118 | - || GET_CODE (XEXP (SET_SRC (x), 2)) == RETURN)) | ||
| 2119 | + || ANY_RETURN_P (XEXP (SET_SRC (x), 2)))) | ||
| 2120 | return 1; | ||
| 2121 | return 0; | ||
| 2122 | } | ||
| 2123 | @@ -840,8 +841,9 @@ | ||
| 2124 | a = GET_CODE (XEXP (SET_SRC (x), 1)); | ||
| 2125 | b = GET_CODE (XEXP (SET_SRC (x), 2)); | ||
| 2126 | |||
| 2127 | - return ((b == PC && (a == LABEL_REF || a == RETURN)) | ||
| 2128 | - || (a == PC && (b == LABEL_REF || b == RETURN))); | ||
| 2129 | + return ((b == PC && (a == LABEL_REF || a == RETURN || a == SIMPLE_RETURN)) | ||
| 2130 | + || (a == PC | ||
| 2131 | + && (b == LABEL_REF || b == RETURN || b == SIMPLE_RETURN))); | ||
| 2132 | } | ||
| 2133 | |||
| 2134 | /* Return the label of a conditional jump. */ | ||
| 2135 | @@ -878,6 +880,7 @@ | ||
| 2136 | switch (GET_CODE (x)) | ||
| 2137 | { | ||
| 2138 | case RETURN: | ||
| 2139 | + case SIMPLE_RETURN: | ||
| 2140 | case EH_RETURN: | ||
| 2141 | return true; | ||
| 2142 | |||
| 2143 | @@ -1200,7 +1203,7 @@ | ||
| 2144 | /* If deleting a jump, decrement the count of the label, | ||
| 2145 | and delete the label if it is now unused. */ | ||
| 2146 | |||
| 2147 | - if (JUMP_P (insn) && JUMP_LABEL (insn)) | ||
| 2148 | + if (JUMP_P (insn) && JUMP_LABEL (insn) && !ANY_RETURN_P (JUMP_LABEL (insn))) | ||
| 2149 | { | ||
| 2150 | rtx lab = JUMP_LABEL (insn), lab_next; | ||
| 2151 | |||
| 2152 | @@ -1331,6 +1334,18 @@ | ||
| 2153 | is also an unconditional jump in that case. */ | ||
| 2154 | } | ||
| 2155 | |||
| 2156 | +/* A helper function for redirect_exp_1; examines its input X and returns | ||
| 2157 | + either a LABEL_REF around a label, or a RETURN if X was NULL. */ | ||
| 2158 | +static rtx | ||
| 2159 | +redirect_target (rtx x) | ||
| 2160 | +{ | ||
| 2161 | + if (x == NULL_RTX) | ||
| 2162 | + return ret_rtx; | ||
| 2163 | + if (!ANY_RETURN_P (x)) | ||
| 2164 | + return gen_rtx_LABEL_REF (Pmode, x); | ||
| 2165 | + return x; | ||
| 2166 | +} | ||
| 2167 | + | ||
| 2168 | /* Throughout LOC, redirect OLABEL to NLABEL. Treat null OLABEL or | ||
| 2169 | NLABEL as a return. Accrue modifications into the change group. */ | ||
| 2170 | |||
| 2171 | @@ -1342,37 +1357,19 @@ | ||
| 2172 | int i; | ||
| 2173 | const char *fmt; | ||
| 2174 | |||
| 2175 | - if (code == LABEL_REF) | ||
| 2176 | - { | ||
| 2177 | - if (XEXP (x, 0) == olabel) | ||
| 2178 | - { | ||
| 2179 | - rtx n; | ||
| 2180 | - if (nlabel) | ||
| 2181 | - n = gen_rtx_LABEL_REF (Pmode, nlabel); | ||
| 2182 | - else | ||
| 2183 | - n = gen_rtx_RETURN (VOIDmode); | ||
| 2184 | - | ||
| 2185 | - validate_change (insn, loc, n, 1); | ||
| 2186 | - return; | ||
| 2187 | - } | ||
| 2188 | - } | ||
| 2189 | - else if (code == RETURN && olabel == 0) | ||
| 2190 | - { | ||
| 2191 | - if (nlabel) | ||
| 2192 | - x = gen_rtx_LABEL_REF (Pmode, nlabel); | ||
| 2193 | - else | ||
| 2194 | - x = gen_rtx_RETURN (VOIDmode); | ||
| 2195 | - if (loc == &PATTERN (insn)) | ||
| 2196 | - x = gen_rtx_SET (VOIDmode, pc_rtx, x); | ||
| 2197 | - validate_change (insn, loc, x, 1); | ||
| 2198 | + if ((code == LABEL_REF && XEXP (x, 0) == olabel) | ||
| 2199 | + || x == olabel) | ||
| 2200 | + { | ||
| 2201 | + validate_change (insn, loc, redirect_target (nlabel), 1); | ||
| 2202 | return; | ||
| 2203 | } | ||
| 2204 | |||
| 2205 | - if (code == SET && nlabel == 0 && SET_DEST (x) == pc_rtx | ||
| 2206 | + if (code == SET && SET_DEST (x) == pc_rtx | ||
| 2207 | + && ANY_RETURN_P (nlabel) | ||
| 2208 | && GET_CODE (SET_SRC (x)) == LABEL_REF | ||
| 2209 | && XEXP (SET_SRC (x), 0) == olabel) | ||
| 2210 | { | ||
| 2211 | - validate_change (insn, loc, gen_rtx_RETURN (VOIDmode), 1); | ||
| 2212 | + validate_change (insn, loc, nlabel, 1); | ||
| 2213 | return; | ||
| 2214 | } | ||
| 2215 | |||
| 2216 | @@ -1409,6 +1406,7 @@ | ||
| 2217 | int ochanges = num_validated_changes (); | ||
| 2218 | rtx *loc, asmop; | ||
| 2219 | |||
| 2220 | + gcc_assert (nlabel); | ||
| 2221 | asmop = extract_asm_operands (PATTERN (jump)); | ||
| 2222 | if (asmop) | ||
| 2223 | { | ||
| 2224 | @@ -1430,17 +1428,20 @@ | ||
| 2225 | jump target label is unused as a result, it and the code following | ||
| 2226 | it may be deleted. | ||
| 2227 | |||
| 2228 | - If NLABEL is zero, we are to turn the jump into a (possibly conditional) | ||
| 2229 | - RETURN insn. | ||
| 2230 | + Normally, NLABEL will be a label, but it may also be a RETURN or | ||
| 2231 | + SIMPLE_RETURN rtx; in that case we are to turn the jump into a | ||
| 2232 | + (possibly conditional) return insn. | ||
| 2233 | |||
| 2234 | The return value will be 1 if the change was made, 0 if it wasn't | ||
| 2235 | - (this can only occur for NLABEL == 0). */ | ||
| 2236 | + (this can only occur when trying to produce return insns). */ | ||
| 2237 | |||
| 2238 | int | ||
| 2239 | redirect_jump (rtx jump, rtx nlabel, int delete_unused) | ||
| 2240 | { | ||
| 2241 | rtx olabel = JUMP_LABEL (jump); | ||
| 2242 | |||
| 2243 | + gcc_assert (nlabel != NULL_RTX); | ||
| 2244 | + | ||
| 2245 | if (nlabel == olabel) | ||
| 2246 | return 1; | ||
| 2247 | |||
| 2248 | @@ -1452,7 +1453,7 @@ | ||
| 2249 | } | ||
| 2250 | |||
| 2251 | /* Fix up JUMP_LABEL and label ref counts after OLABEL has been replaced with | ||
| 2252 | - NLABEL in JUMP. | ||
| 2253 | + NEW_DEST in JUMP. | ||
| 2254 | If DELETE_UNUSED is positive, delete related insn to OLABEL if its ref | ||
| 2255 | count has dropped to zero. */ | ||
| 2256 | void | ||
| 2257 | @@ -1468,13 +1469,14 @@ | ||
| 2258 | about this. */ | ||
| 2259 | gcc_assert (delete_unused >= 0); | ||
| 2260 | JUMP_LABEL (jump) = nlabel; | ||
| 2261 | - if (nlabel) | ||
| 2262 | + if (nlabel && !ANY_RETURN_P (nlabel)) | ||
| 2263 | ++LABEL_NUSES (nlabel); | ||
| 2264 | |||
| 2265 | /* Update labels in any REG_EQUAL note. */ | ||
| 2266 | if ((note = find_reg_note (jump, REG_EQUAL, NULL_RTX)) != NULL_RTX) | ||
| 2267 | { | ||
| 2268 | - if (!nlabel || (invert && !invert_exp_1 (XEXP (note, 0), jump))) | ||
| 2269 | + if (ANY_RETURN_P (nlabel) | ||
| 2270 | + || (invert && !invert_exp_1 (XEXP (note, 0), jump))) | ||
| 2271 | remove_note (jump, note); | ||
| 2272 | else | ||
| 2273 | { | ||
| 2274 | @@ -1483,7 +1485,8 @@ | ||
| 2275 | } | ||
| 2276 | } | ||
| 2277 | |||
| 2278 | - if (olabel && --LABEL_NUSES (olabel) == 0 && delete_unused > 0 | ||
| 2279 | + if (olabel && !ANY_RETURN_P (olabel) | ||
| 2280 | + && --LABEL_NUSES (olabel) == 0 && delete_unused > 0 | ||
| 2281 | /* Undefined labels will remain outside the insn stream. */ | ||
| 2282 | && INSN_UID (olabel)) | ||
| 2283 | delete_related_insns (olabel); | ||
| 2284 | |||
| 2285 | === modified file 'gcc/opts.c' | ||
| 2286 | --- old/gcc/opts.c 2010-12-10 15:33:37 +0000 | ||
| 2287 | +++ new/gcc/opts.c 2011-01-05 12:12:18 +0000 | ||
| 2288 | @@ -908,6 +908,7 @@ | ||
| 2289 | flag_ipa_cp = opt2; | ||
| 2290 | flag_ipa_sra = opt2; | ||
| 2291 | flag_ee = opt2; | ||
| 2292 | + flag_shrink_wrap = opt2; | ||
| 2293 | |||
| 2294 | /* Track fields in field-sensitive alias analysis. */ | ||
| 2295 | set_param_value ("max-fields-for-field-sensitive", | ||
| 2296 | |||
| 2297 | === modified file 'gcc/print-rtl.c' | ||
| 2298 | --- old/gcc/print-rtl.c 2010-03-26 16:18:51 +0000 | ||
| 2299 | +++ new/gcc/print-rtl.c 2011-01-05 12:12:18 +0000 | ||
| 2300 | @@ -308,9 +308,16 @@ | ||
| 2301 | } | ||
| 2302 | } | ||
| 2303 | else if (i == 8 && JUMP_P (in_rtx) && JUMP_LABEL (in_rtx) != NULL) | ||
| 2304 | - /* Output the JUMP_LABEL reference. */ | ||
| 2305 | - fprintf (outfile, "\n%s%*s -> %d", print_rtx_head, indent * 2, "", | ||
| 2306 | - INSN_UID (JUMP_LABEL (in_rtx))); | ||
| 2307 | + { | ||
| 2308 | + /* Output the JUMP_LABEL reference. */ | ||
| 2309 | + fprintf (outfile, "\n%s%*s -> ", print_rtx_head, indent * 2, ""); | ||
| 2310 | + if (GET_CODE (JUMP_LABEL (in_rtx)) == RETURN) | ||
| 2311 | + fprintf (outfile, "return"); | ||
| 2312 | + else if (GET_CODE (JUMP_LABEL (in_rtx)) == SIMPLE_RETURN) | ||
| 2313 | + fprintf (outfile, "simple_return"); | ||
| 2314 | + else | ||
| 2315 | + fprintf (outfile, "%d", INSN_UID (JUMP_LABEL (in_rtx))); | ||
| 2316 | + } | ||
| 2317 | else if (i == 0 && GET_CODE (in_rtx) == VALUE) | ||
| 2318 | { | ||
| 2319 | #ifndef GENERATOR_FILE | ||
| 2320 | |||
| 2321 | === modified file 'gcc/reorg.c' | ||
| 2322 | --- old/gcc/reorg.c 2010-09-15 22:51:44 +0000 | ||
| 2323 | +++ new/gcc/reorg.c 2011-01-05 12:12:18 +0000 | ||
| 2324 | @@ -161,8 +161,11 @@ | ||
| 2325 | #define unfilled_slots_next \ | ||
| 2326 | ((rtx *) obstack_next_free (&unfilled_slots_obstack)) | ||
| 2327 | |||
| 2328 | -/* Points to the label before the end of the function. */ | ||
| 2329 | -static rtx end_of_function_label; | ||
| 2330 | +/* Points to the label before the end of the function, or before a | ||
| 2331 | + return insn. */ | ||
| 2332 | +static rtx function_return_label; | ||
| 2333 | +/* Likewise for a simple_return. */ | ||
| 2334 | +static rtx function_simple_return_label; | ||
| 2335 | |||
| 2336 | /* Mapping between INSN_UID's and position in the code since INSN_UID's do | ||
| 2337 | not always monotonically increase. */ | ||
| 2338 | @@ -175,7 +178,7 @@ | ||
| 2339 | static int resource_conflicts_p (struct resources *, struct resources *); | ||
| 2340 | static int insn_references_resource_p (rtx, struct resources *, bool); | ||
| 2341 | static int insn_sets_resource_p (rtx, struct resources *, bool); | ||
| 2342 | -static rtx find_end_label (void); | ||
| 2343 | +static rtx find_end_label (rtx); | ||
| 2344 | static rtx emit_delay_sequence (rtx, rtx, int); | ||
| 2345 | static rtx add_to_delay_list (rtx, rtx); | ||
| 2346 | static rtx delete_from_delay_slot (rtx); | ||
| 2347 | @@ -220,6 +223,15 @@ | ||
| 2348 | static void make_return_insns (rtx); | ||
| 2349 | #endif | ||
| 2350 | |||
| 2351 | +/* Return true iff INSN is a simplejump, or any kind of return insn. */ | ||
| 2352 | + | ||
| 2353 | +static bool | ||
| 2354 | +simplejump_or_return_p (rtx insn) | ||
| 2355 | +{ | ||
| 2356 | + return (JUMP_P (insn) | ||
| 2357 | + && (simplejump_p (insn) || ANY_RETURN_P (PATTERN (insn)))); | ||
| 2358 | +} | ||
| 2359 | + | ||
| 2360 | /* Return TRUE if this insn should stop the search for insn to fill delay | ||
| 2361 | slots. LABELS_P indicates that labels should terminate the search. | ||
| 2362 | In all cases, jumps terminate the search. */ | ||
| 2363 | @@ -335,23 +347,29 @@ | ||
| 2364 | |||
| 2365 | ??? There may be a problem with the current implementation. Suppose | ||
| 2366 | we start with a bare RETURN insn and call find_end_label. It may set | ||
| 2367 | - end_of_function_label just before the RETURN. Suppose the machinery | ||
| 2368 | + function_return_label just before the RETURN. Suppose the machinery | ||
| 2369 | is able to fill the delay slot of the RETURN insn afterwards. Then | ||
| 2370 | - end_of_function_label is no longer valid according to the property | ||
| 2371 | + function_return_label is no longer valid according to the property | ||
| 2372 | described above and find_end_label will still return it unmodified. | ||
| 2373 | Note that this is probably mitigated by the following observation: | ||
| 2374 | - once end_of_function_label is made, it is very likely the target of | ||
| 2375 | + once function_return_label is made, it is very likely the target of | ||
| 2376 | a jump, so filling the delay slot of the RETURN will be much more | ||
| 2377 | difficult. */ | ||
| 2378 | |||
| 2379 | static rtx | ||
| 2380 | -find_end_label (void) | ||
| 2381 | +find_end_label (rtx kind) | ||
| 2382 | { | ||
| 2383 | rtx insn; | ||
| 2384 | + rtx *plabel; | ||
| 2385 | + | ||
| 2386 | + if (kind == ret_rtx) | ||
| 2387 | + plabel = &function_return_label; | ||
| 2388 | + else | ||
| 2389 | + plabel = &function_simple_return_label; | ||
| 2390 | |||
| 2391 | /* If we found one previously, return it. */ | ||
| 2392 | - if (end_of_function_label) | ||
| 2393 | - return end_of_function_label; | ||
| 2394 | + if (*plabel) | ||
| 2395 | + return *plabel; | ||
| 2396 | |||
| 2397 | /* Otherwise, see if there is a label at the end of the function. If there | ||
| 2398 | is, it must be that RETURN insns aren't needed, so that is our return | ||
| 2399 | @@ -366,44 +384,44 @@ | ||
| 2400 | |||
| 2401 | /* When a target threads its epilogue we might already have a | ||
| 2402 | suitable return insn. If so put a label before it for the | ||
| 2403 | - end_of_function_label. */ | ||
| 2404 | + function_return_label. */ | ||
| 2405 | if (BARRIER_P (insn) | ||
| 2406 | && JUMP_P (PREV_INSN (insn)) | ||
| 2407 | - && GET_CODE (PATTERN (PREV_INSN (insn))) == RETURN) | ||
| 2408 | + && PATTERN (PREV_INSN (insn)) == kind) | ||
| 2409 | { | ||
| 2410 | rtx temp = PREV_INSN (PREV_INSN (insn)); | ||
| 2411 | - end_of_function_label = gen_label_rtx (); | ||
| 2412 | - LABEL_NUSES (end_of_function_label) = 0; | ||
| 2413 | + rtx label = gen_label_rtx (); | ||
| 2414 | + LABEL_NUSES (label) = 0; | ||
| 2415 | |||
| 2416 | /* Put the label before an USE insns that may precede the RETURN insn. */ | ||
| 2417 | while (GET_CODE (temp) == USE) | ||
| 2418 | temp = PREV_INSN (temp); | ||
| 2419 | |||
| 2420 | - emit_label_after (end_of_function_label, temp); | ||
| 2421 | + emit_label_after (label, temp); | ||
| 2422 | + *plabel = label; | ||
| 2423 | } | ||
| 2424 | |||
| 2425 | else if (LABEL_P (insn)) | ||
| 2426 | - end_of_function_label = insn; | ||
| 2427 | + *plabel = insn; | ||
| 2428 | else | ||
| 2429 | { | ||
| 2430 | - end_of_function_label = gen_label_rtx (); | ||
| 2431 | - LABEL_NUSES (end_of_function_label) = 0; | ||
| 2432 | + rtx label = gen_label_rtx (); | ||
| 2433 | + LABEL_NUSES (label) = 0; | ||
| 2434 | /* If the basic block reorder pass moves the return insn to | ||
| 2435 | some other place try to locate it again and put our | ||
| 2436 | - end_of_function_label there. */ | ||
| 2437 | - while (insn && ! (JUMP_P (insn) | ||
| 2438 | - && (GET_CODE (PATTERN (insn)) == RETURN))) | ||
| 2439 | + function_return_label there. */ | ||
| 2440 | + while (insn && ! (JUMP_P (insn) && (PATTERN (insn) == kind))) | ||
| 2441 | insn = PREV_INSN (insn); | ||
| 2442 | if (insn) | ||
| 2443 | { | ||
| 2444 | insn = PREV_INSN (insn); | ||
| 2445 | |||
| 2446 | - /* Put the label before an USE insns that may proceed the | ||
| 2447 | + /* Put the label before an USE insns that may precede the | ||
| 2448 | RETURN insn. */ | ||
| 2449 | while (GET_CODE (insn) == USE) | ||
| 2450 | insn = PREV_INSN (insn); | ||
| 2451 | |||
| 2452 | - emit_label_after (end_of_function_label, insn); | ||
| 2453 | + emit_label_after (label, insn); | ||
| 2454 | } | ||
| 2455 | else | ||
| 2456 | { | ||
| 2457 | @@ -413,19 +431,16 @@ | ||
| 2458 | && ! HAVE_return | ||
| 2459 | #endif | ||
| 2460 | ) | ||
| 2461 | - { | ||
| 2462 | - /* The RETURN insn has its delay slot filled so we cannot | ||
| 2463 | - emit the label just before it. Since we already have | ||
| 2464 | - an epilogue and cannot emit a new RETURN, we cannot | ||
| 2465 | - emit the label at all. */ | ||
| 2466 | - end_of_function_label = NULL_RTX; | ||
| 2467 | - return end_of_function_label; | ||
| 2468 | - } | ||
| 2469 | + /* The RETURN insn has its delay slot filled so we cannot | ||
| 2470 | + emit the label just before it. Since we already have | ||
| 2471 | + an epilogue and cannot emit a new RETURN, we cannot | ||
| 2472 | + emit the label at all. */ | ||
| 2473 | + return NULL_RTX; | ||
| 2474 | #endif /* HAVE_epilogue */ | ||
| 2475 | |||
| 2476 | /* Otherwise, make a new label and emit a RETURN and BARRIER, | ||
| 2477 | if needed. */ | ||
| 2478 | - emit_label (end_of_function_label); | ||
| 2479 | + emit_label (label); | ||
| 2480 | #ifdef HAVE_return | ||
| 2481 | /* We don't bother trying to create a return insn if the | ||
| 2482 | epilogue has filled delay-slots; we would have to try and | ||
| 2483 | @@ -437,19 +452,21 @@ | ||
| 2484 | /* The return we make may have delay slots too. */ | ||
| 2485 | rtx insn = gen_return (); | ||
| 2486 | insn = emit_jump_insn (insn); | ||
| 2487 | + JUMP_LABEL (insn) = ret_rtx; | ||
| 2488 | emit_barrier (); | ||
| 2489 | if (num_delay_slots (insn) > 0) | ||
| 2490 | obstack_ptr_grow (&unfilled_slots_obstack, insn); | ||
| 2491 | } | ||
| 2492 | #endif | ||
| 2493 | } | ||
| 2494 | + *plabel = label; | ||
| 2495 | } | ||
| 2496 | |||
| 2497 | /* Show one additional use for this label so it won't go away until | ||
| 2498 | we are done. */ | ||
| 2499 | - ++LABEL_NUSES (end_of_function_label); | ||
| 2500 | + ++LABEL_NUSES (*plabel); | ||
| 2501 | |||
| 2502 | - return end_of_function_label; | ||
| 2503 | + return *plabel; | ||
| 2504 | } | ||
| 2505 | |||
| 2506 | /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace | ||
| 2507 | @@ -797,10 +814,8 @@ | ||
| 2508 | if ((next_trial == next_active_insn (JUMP_LABEL (insn)) | ||
| 2509 | && ! (next_trial == 0 && crtl->epilogue_delay_list != 0)) | ||
| 2510 | || (next_trial != 0 | ||
| 2511 | - && JUMP_P (next_trial) | ||
| 2512 | - && JUMP_LABEL (insn) == JUMP_LABEL (next_trial) | ||
| 2513 | - && (simplejump_p (next_trial) | ||
| 2514 | - || GET_CODE (PATTERN (next_trial)) == RETURN))) | ||
| 2515 | + && simplejump_or_return_p (next_trial) | ||
| 2516 | + && JUMP_LABEL (insn) == JUMP_LABEL (next_trial))) | ||
| 2517 | { | ||
| 2518 | if (eligible_for_annul_false (insn, 0, trial, flags)) | ||
| 2519 | { | ||
| 2520 | @@ -819,13 +834,11 @@ | ||
| 2521 | branch, thread our jump to the target of that branch. Don't | ||
| 2522 | change this into a RETURN here, because it may not accept what | ||
| 2523 | we have in the delay slot. We'll fix this up later. */ | ||
| 2524 | - if (next_trial && JUMP_P (next_trial) | ||
| 2525 | - && (simplejump_p (next_trial) | ||
| 2526 | - || GET_CODE (PATTERN (next_trial)) == RETURN)) | ||
| 2527 | + if (next_trial && simplejump_or_return_p (next_trial)) | ||
| 2528 | { | ||
| 2529 | rtx target_label = JUMP_LABEL (next_trial); | ||
| 2530 | - if (target_label == 0) | ||
| 2531 | - target_label = find_end_label (); | ||
| 2532 | + if (ANY_RETURN_P (target_label)) | ||
| 2533 | + target_label = find_end_label (target_label); | ||
| 2534 | |||
| 2535 | if (target_label) | ||
| 2536 | { | ||
| 2537 | @@ -866,7 +879,7 @@ | ||
| 2538 | if (JUMP_P (insn) | ||
| 2539 | && (condjump_p (insn) || condjump_in_parallel_p (insn)) | ||
| 2540 | && INSN_UID (insn) <= max_uid | ||
| 2541 | - && label != 0 | ||
| 2542 | + && label != 0 && !ANY_RETURN_P (label) | ||
| 2543 | && INSN_UID (label) <= max_uid) | ||
| 2544 | flags | ||
| 2545 | = (uid_to_ruid[INSN_UID (label)] > uid_to_ruid[INSN_UID (insn)]) | ||
| 2546 | @@ -1038,7 +1051,7 @@ | ||
| 2547 | pat = XVECEXP (pat, 0, 0); | ||
| 2548 | |||
| 2549 | if (GET_CODE (pat) == RETURN) | ||
| 2550 | - return target == 0 ? const_true_rtx : 0; | ||
| 2551 | + return ANY_RETURN_P (target) ? const_true_rtx : 0; | ||
| 2552 | |||
| 2553 | else if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx) | ||
| 2554 | return 0; | ||
| 2555 | @@ -1318,7 +1331,11 @@ | ||
| 2556 | } | ||
| 2557 | |||
| 2558 | /* Show the place to which we will be branching. */ | ||
| 2559 | - *pnew_thread = next_active_insn (JUMP_LABEL (XVECEXP (seq, 0, 0))); | ||
| 2560 | + temp = JUMP_LABEL (XVECEXP (seq, 0, 0)); | ||
| 2561 | + if (ANY_RETURN_P (temp)) | ||
| 2562 | + *pnew_thread = temp; | ||
| 2563 | + else | ||
| 2564 | + *pnew_thread = next_active_insn (temp); | ||
| 2565 | |||
| 2566 | /* Add any new insns to the delay list and update the count of the | ||
| 2567 | number of slots filled. */ | ||
| 2568 | @@ -1358,8 +1375,7 @@ | ||
| 2569 | /* We can't do anything if SEQ's delay insn isn't an | ||
| 2570 | unconditional branch. */ | ||
| 2571 | |||
| 2572 | - if (! simplejump_p (XVECEXP (seq, 0, 0)) | ||
| 2573 | - && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) != RETURN) | ||
| 2574 | + if (! simplejump_or_return_p (XVECEXP (seq, 0, 0))) | ||
| 2575 | return delay_list; | ||
| 2576 | |||
| 2577 | for (i = 1; i < XVECLEN (seq, 0); i++) | ||
| 2578 | @@ -1827,7 +1843,7 @@ | ||
| 2579 | rtx insn; | ||
| 2580 | |||
| 2581 | /* We don't own the function end. */ | ||
| 2582 | - if (thread == 0) | ||
| 2583 | + if (ANY_RETURN_P (thread)) | ||
| 2584 | return 0; | ||
| 2585 | |||
| 2586 | /* Get the first active insn, or THREAD, if it is an active insn. */ | ||
| 2587 | @@ -2245,7 +2261,8 @@ | ||
| 2588 | && (!JUMP_P (insn) | ||
| 2589 | || ((condjump_p (insn) || condjump_in_parallel_p (insn)) | ||
| 2590 | && ! simplejump_p (insn) | ||
| 2591 | - && JUMP_LABEL (insn) != 0))) | ||
| 2592 | + && JUMP_LABEL (insn) != 0 | ||
| 2593 | + && !ANY_RETURN_P (JUMP_LABEL (insn))))) | ||
| 2594 | { | ||
| 2595 | /* Invariant: If insn is a JUMP_INSN, the insn's jump | ||
| 2596 | label. Otherwise, zero. */ | ||
| 2597 | @@ -2270,7 +2287,7 @@ | ||
| 2598 | target = JUMP_LABEL (insn); | ||
| 2599 | } | ||
| 2600 | |||
| 2601 | - if (target == 0) | ||
| 2602 | + if (target == 0 || ANY_RETURN_P (target)) | ||
| 2603 | for (trial = next_nonnote_insn (insn); trial; trial = next_trial) | ||
| 2604 | { | ||
| 2605 | next_trial = next_nonnote_insn (trial); | ||
| 2606 | @@ -2349,6 +2366,7 @@ | ||
| 2607 | && JUMP_P (trial) | ||
| 2608 | && simplejump_p (trial) | ||
| 2609 | && (target == 0 || JUMP_LABEL (trial) == target) | ||
| 2610 | + && !ANY_RETURN_P (JUMP_LABEL (trial)) | ||
| 2611 | && (next_trial = next_active_insn (JUMP_LABEL (trial))) != 0 | ||
| 2612 | && ! (NONJUMP_INSN_P (next_trial) | ||
| 2613 | && GET_CODE (PATTERN (next_trial)) == SEQUENCE) | ||
| 2614 | @@ -2371,7 +2389,7 @@ | ||
| 2615 | if (new_label != 0) | ||
| 2616 | new_label = get_label_before (new_label); | ||
| 2617 | else | ||
| 2618 | - new_label = find_end_label (); | ||
| 2619 | + new_label = find_end_label (simple_return_rtx); | ||
| 2620 | |||
| 2621 | if (new_label) | ||
| 2622 | { | ||
| 2623 | @@ -2503,7 +2521,8 @@ | ||
| 2624 | |||
| 2625 | /* Follow any unconditional jump at LABEL; | ||
| 2626 | return the ultimate label reached by any such chain of jumps. | ||
| 2627 | - Return null if the chain ultimately leads to a return instruction. | ||
| 2628 | + Return a suitable return rtx if the chain ultimately leads to a | ||
| 2629 | + return instruction. | ||
| 2630 | If LABEL is not followed by a jump, return LABEL. | ||
| 2631 | If the chain loops or we can't find end, return LABEL, | ||
| 2632 | since that tells caller to avoid changing the insn. */ | ||
| 2633 | @@ -2518,6 +2537,7 @@ | ||
| 2634 | |||
| 2635 | for (depth = 0; | ||
| 2636 | (depth < 10 | ||
| 2637 | + && !ANY_RETURN_P (value) | ||
| 2638 | && (insn = next_active_insn (value)) != 0 | ||
| 2639 | && JUMP_P (insn) | ||
| 2640 | && ((JUMP_LABEL (insn) != 0 && any_uncondjump_p (insn) | ||
| 2641 | @@ -2527,18 +2547,22 @@ | ||
| 2642 | && BARRIER_P (next)); | ||
| 2643 | depth++) | ||
| 2644 | { | ||
| 2645 | - rtx tem; | ||
| 2646 | + rtx this_label = JUMP_LABEL (insn); | ||
| 2647 | |||
| 2648 | /* If we have found a cycle, make the insn jump to itself. */ | ||
| 2649 | - if (JUMP_LABEL (insn) == label) | ||
| 2650 | + if (this_label == label) | ||
| 2651 | return label; | ||
| 2652 | |||
| 2653 | - tem = next_active_insn (JUMP_LABEL (insn)); | ||
| 2654 | - if (tem && (GET_CODE (PATTERN (tem)) == ADDR_VEC | ||
| 2655 | + if (!ANY_RETURN_P (this_label)) | ||
| 2656 | + { | ||
| 2657 | + rtx tem = next_active_insn (this_label); | ||
| 2658 | + if (tem | ||
| 2659 | + && (GET_CODE (PATTERN (tem)) == ADDR_VEC | ||
| 2660 | || GET_CODE (PATTERN (tem)) == ADDR_DIFF_VEC)) | ||
| 2661 | - break; | ||
| 2662 | + break; | ||
| 2663 | + } | ||
| 2664 | |||
| 2665 | - value = JUMP_LABEL (insn); | ||
| 2666 | + value = this_label; | ||
| 2667 | } | ||
| 2668 | if (depth == 10) | ||
| 2669 | return label; | ||
| 2670 | @@ -2901,6 +2925,7 @@ | ||
| 2671 | arithmetic insn after the jump insn and put the arithmetic insn in the | ||
| 2672 | delay slot. If we can't do this, return. */ | ||
| 2673 | if (delay_list == 0 && likely && new_thread | ||
| 2674 | + && !ANY_RETURN_P (new_thread) | ||
| 2675 | && NONJUMP_INSN_P (new_thread) | ||
| 2676 | && GET_CODE (PATTERN (new_thread)) != ASM_INPUT | ||
| 2677 | && asm_noperands (PATTERN (new_thread)) < 0) | ||
| 2678 | @@ -2985,16 +3010,14 @@ | ||
| 2679 | |||
| 2680 | gcc_assert (thread_if_true); | ||
| 2681 | |||
| 2682 | - if (new_thread && JUMP_P (new_thread) | ||
| 2683 | - && (simplejump_p (new_thread) | ||
| 2684 | - || GET_CODE (PATTERN (new_thread)) == RETURN) | ||
| 2685 | + if (new_thread && simplejump_or_return_p (new_thread) | ||
| 2686 | && redirect_with_delay_list_safe_p (insn, | ||
| 2687 | JUMP_LABEL (new_thread), | ||
| 2688 | delay_list)) | ||
| 2689 | new_thread = follow_jumps (JUMP_LABEL (new_thread)); | ||
| 2690 | |||
| 2691 | - if (new_thread == 0) | ||
| 2692 | - label = find_end_label (); | ||
| 2693 | + if (ANY_RETURN_P (new_thread)) | ||
| 2694 | + label = find_end_label (new_thread); | ||
| 2695 | else if (LABEL_P (new_thread)) | ||
| 2696 | label = new_thread; | ||
| 2697 | else | ||
| 2698 | @@ -3340,11 +3363,12 @@ | ||
| 2699 | group of consecutive labels. */ | ||
| 2700 | if (JUMP_P (insn) | ||
| 2701 | && (condjump_p (insn) || condjump_in_parallel_p (insn)) | ||
| 2702 | - && (target_label = JUMP_LABEL (insn)) != 0) | ||
| 2703 | + && (target_label = JUMP_LABEL (insn)) != 0 | ||
| 2704 | + && !ANY_RETURN_P (target_label)) | ||
| 2705 | { | ||
| 2706 | target_label = skip_consecutive_labels (follow_jumps (target_label)); | ||
| 2707 | - if (target_label == 0) | ||
| 2708 | - target_label = find_end_label (); | ||
| 2709 | + if (ANY_RETURN_P (target_label)) | ||
| 2710 | + target_label = find_end_label (target_label); | ||
| 2711 | |||
| 2712 | if (target_label && next_active_insn (target_label) == next | ||
| 2713 | && ! condjump_in_parallel_p (insn)) | ||
| 2714 | @@ -3359,9 +3383,8 @@ | ||
| 2715 | /* See if this jump conditionally branches around an unconditional | ||
| 2716 | jump. If so, invert this jump and point it to the target of the | ||
| 2717 | second jump. */ | ||
| 2718 | - if (next && JUMP_P (next) | ||
| 2719 | + if (next && simplejump_or_return_p (next) | ||
| 2720 | && any_condjump_p (insn) | ||
| 2721 | - && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN) | ||
| 2722 | && target_label | ||
| 2723 | && next_active_insn (target_label) == next_active_insn (next) | ||
| 2724 | && no_labels_between_p (insn, next)) | ||
| 2725 | @@ -3403,8 +3426,7 @@ | ||
| 2726 | Don't do this if we expect the conditional branch to be true, because | ||
| 2727 | we would then be making the more common case longer. */ | ||
| 2728 | |||
| 2729 | - if (JUMP_P (insn) | ||
| 2730 | - && (simplejump_p (insn) || GET_CODE (PATTERN (insn)) == RETURN) | ||
| 2731 | + if (simplejump_or_return_p (insn) | ||
| 2732 | && (other = prev_active_insn (insn)) != 0 | ||
| 2733 | && any_condjump_p (other) | ||
| 2734 | && no_labels_between_p (other, insn) | ||
| 2735 | @@ -3445,10 +3467,10 @@ | ||
| 2736 | Only do so if optimizing for size since this results in slower, but | ||
| 2737 | smaller code. */ | ||
| 2738 | if (optimize_function_for_size_p (cfun) | ||
| 2739 | - && GET_CODE (PATTERN (delay_insn)) == RETURN | ||
| 2740 | + && ANY_RETURN_P (PATTERN (delay_insn)) | ||
| 2741 | && next | ||
| 2742 | && JUMP_P (next) | ||
| 2743 | - && GET_CODE (PATTERN (next)) == RETURN) | ||
| 2744 | + && PATTERN (next) == PATTERN (delay_insn)) | ||
| 2745 | { | ||
| 2746 | rtx after; | ||
| 2747 | int i; | ||
| 2748 | @@ -3487,14 +3509,16 @@ | ||
| 2749 | continue; | ||
| 2750 | |||
| 2751 | target_label = JUMP_LABEL (delay_insn); | ||
| 2752 | + if (target_label && ANY_RETURN_P (target_label)) | ||
| 2753 | + continue; | ||
| 2754 | |||
| 2755 | if (target_label) | ||
| 2756 | { | ||
| 2757 | /* If this jump goes to another unconditional jump, thread it, but | ||
| 2758 | don't convert a jump into a RETURN here. */ | ||
| 2759 | trial = skip_consecutive_labels (follow_jumps (target_label)); | ||
| 2760 | - if (trial == 0) | ||
| 2761 | - trial = find_end_label (); | ||
| 2762 | + if (ANY_RETURN_P (trial)) | ||
| 2763 | + trial = find_end_label (trial); | ||
| 2764 | |||
| 2765 | if (trial && trial != target_label | ||
| 2766 | && redirect_with_delay_slots_safe_p (delay_insn, trial, insn)) | ||
| 2767 | @@ -3517,7 +3541,7 @@ | ||
| 2768 | later incorrectly compute register live/death info. */ | ||
| 2769 | rtx tmp = next_active_insn (trial); | ||
| 2770 | if (tmp == 0) | ||
| 2771 | - tmp = find_end_label (); | ||
| 2772 | + tmp = find_end_label (simple_return_rtx); | ||
| 2773 | |||
| 2774 | if (tmp) | ||
| 2775 | { | ||
| 2776 | @@ -3537,14 +3561,12 @@ | ||
| 2777 | delay list and that insn is redundant, thread the jump. */ | ||
| 2778 | if (trial && GET_CODE (PATTERN (trial)) == SEQUENCE | ||
| 2779 | && XVECLEN (PATTERN (trial), 0) == 2 | ||
| 2780 | - && JUMP_P (XVECEXP (PATTERN (trial), 0, 0)) | ||
| 2781 | - && (simplejump_p (XVECEXP (PATTERN (trial), 0, 0)) | ||
| 2782 | - || GET_CODE (PATTERN (XVECEXP (PATTERN (trial), 0, 0))) == RETURN) | ||
| 2783 | + && simplejump_or_return_p (XVECEXP (PATTERN (trial), 0, 0)) | ||
| 2784 | && redundant_insn (XVECEXP (PATTERN (trial), 0, 1), insn, 0)) | ||
| 2785 | { | ||
| 2786 | target_label = JUMP_LABEL (XVECEXP (PATTERN (trial), 0, 0)); | ||
| 2787 | - if (target_label == 0) | ||
| 2788 | - target_label = find_end_label (); | ||
| 2789 | + if (ANY_RETURN_P (target_label)) | ||
| 2790 | + target_label = find_end_label (target_label); | ||
| 2791 | |||
| 2792 | if (target_label | ||
| 2793 | && redirect_with_delay_slots_safe_p (delay_insn, target_label, | ||
| 2794 | @@ -3622,16 +3644,15 @@ | ||
| 2795 | a RETURN here. */ | ||
| 2796 | if (! INSN_ANNULLED_BRANCH_P (delay_insn) | ||
| 2797 | && any_condjump_p (delay_insn) | ||
| 2798 | - && next && JUMP_P (next) | ||
| 2799 | - && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN) | ||
| 2800 | + && next && simplejump_or_return_p (next) | ||
| 2801 | && next_active_insn (target_label) == next_active_insn (next) | ||
| 2802 | && no_labels_between_p (insn, next)) | ||
| 2803 | { | ||
| 2804 | rtx label = JUMP_LABEL (next); | ||
| 2805 | rtx old_label = JUMP_LABEL (delay_insn); | ||
| 2806 | |||
| 2807 | - if (label == 0) | ||
| 2808 | - label = find_end_label (); | ||
| 2809 | + if (ANY_RETURN_P (label)) | ||
| 2810 | + label = find_end_label (label); | ||
| 2811 | |||
| 2812 | /* find_end_label can generate a new label. Check this first. */ | ||
| 2813 | if (label | ||
| 2814 | @@ -3692,7 +3713,8 @@ | ||
| 2815 | make_return_insns (rtx first) | ||
| 2816 | { | ||
| 2817 | rtx insn, jump_insn, pat; | ||
| 2818 | - rtx real_return_label = end_of_function_label; | ||
| 2819 | + rtx real_return_label = function_return_label; | ||
| 2820 | + rtx real_simple_return_label = function_simple_return_label; | ||
| 2821 | int slots, i; | ||
| 2822 | |||
| 2823 | #ifdef DELAY_SLOTS_FOR_EPILOGUE | ||
| 2824 | @@ -3707,18 +3729,25 @@ | ||
| 2825 | #endif | ||
| 2826 | |||
| 2827 | /* See if there is a RETURN insn in the function other than the one we | ||
| 2828 | - made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change | ||
| 2829 | + made for FUNCTION_RETURN_LABEL. If so, set up anything we can't change | ||
| 2830 | into a RETURN to jump to it. */ | ||
| 2831 | for (insn = first; insn; insn = NEXT_INSN (insn)) | ||
| 2832 | - if (JUMP_P (insn) && GET_CODE (PATTERN (insn)) == RETURN) | ||
| 2833 | + if (JUMP_P (insn) && ANY_RETURN_P (PATTERN (insn))) | ||
| 2834 | { | ||
| 2835 | - real_return_label = get_label_before (insn); | ||
| 2836 | + rtx t = get_label_before (insn); | ||
| 2837 | + if (PATTERN (insn) == ret_rtx) | ||
| 2838 | + real_return_label = t; | ||
| 2839 | + else | ||
| 2840 | + real_simple_return_label = t; | ||
| 2841 | break; | ||
| 2842 | } | ||
| 2843 | |||
| 2844 | /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it | ||
| 2845 | - was equal to END_OF_FUNCTION_LABEL. */ | ||
| 2846 | - LABEL_NUSES (real_return_label)++; | ||
| 2847 | + was equal to FUNCTION_RETURN_LABEL. */ | ||
| 2848 | + if (real_return_label) | ||
| 2849 | + LABEL_NUSES (real_return_label)++; | ||
| 2850 | + if (real_simple_return_label) | ||
| 2851 | + LABEL_NUSES (real_simple_return_label)++; | ||
| 2852 | |||
| 2853 | /* Clear the list of insns to fill so we can use it. */ | ||
| 2854 | obstack_free (&unfilled_slots_obstack, unfilled_firstobj); | ||
| 2855 | @@ -3726,13 +3755,27 @@ | ||
| 2856 | for (insn = first; insn; insn = NEXT_INSN (insn)) | ||
| 2857 | { | ||
| 2858 | int flags; | ||
| 2859 | + rtx kind, real_label; | ||
| 2860 | |||
| 2861 | /* Only look at filled JUMP_INSNs that go to the end of function | ||
| 2862 | label. */ | ||
| 2863 | if (!NONJUMP_INSN_P (insn) | ||
| 2864 | || GET_CODE (PATTERN (insn)) != SEQUENCE | ||
| 2865 | - || !JUMP_P (XVECEXP (PATTERN (insn), 0, 0)) | ||
| 2866 | - || JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) != end_of_function_label) | ||
| 2867 | + || !JUMP_P (XVECEXP (PATTERN (insn), 0, 0))) | ||
| 2868 | + continue; | ||
| 2869 | + | ||
| 2870 | + if (JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) == function_return_label) | ||
| 2871 | + { | ||
| 2872 | + kind = ret_rtx; | ||
| 2873 | + real_label = real_return_label; | ||
| 2874 | + } | ||
| 2875 | + else if (JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) | ||
| 2876 | + == function_simple_return_label) | ||
| 2877 | + { | ||
| 2878 | + kind = simple_return_rtx; | ||
| 2879 | + real_label = real_simple_return_label; | ||
| 2880 | + } | ||
| 2881 | + else | ||
| 2882 | continue; | ||
| 2883 | |||
| 2884 | pat = PATTERN (insn); | ||
| 2885 | @@ -3740,14 +3783,12 @@ | ||
| 2886 | |||
| 2887 | /* If we can't make the jump into a RETURN, try to redirect it to the best | ||
| 2888 | RETURN and go on to the next insn. */ | ||
| 2889 | - if (! reorg_redirect_jump (jump_insn, NULL_RTX)) | ||
| 2890 | + if (! reorg_redirect_jump (jump_insn, kind)) | ||
| 2891 | { | ||
| 2892 | /* Make sure redirecting the jump will not invalidate the delay | ||
| 2893 | slot insns. */ | ||
| 2894 | - if (redirect_with_delay_slots_safe_p (jump_insn, | ||
| 2895 | - real_return_label, | ||
| 2896 | - insn)) | ||
| 2897 | - reorg_redirect_jump (jump_insn, real_return_label); | ||
| 2898 | + if (redirect_with_delay_slots_safe_p (jump_insn, real_label, insn)) | ||
| 2899 | + reorg_redirect_jump (jump_insn, real_label); | ||
| 2900 | continue; | ||
| 2901 | } | ||
| 2902 | |||
| 2903 | @@ -3787,7 +3828,7 @@ | ||
| 2904 | RETURN, delete the SEQUENCE and output the individual insns, | ||
| 2905 | followed by the RETURN. Then set things up so we try to find | ||
| 2906 | insns for its delay slots, if it needs some. */ | ||
| 2907 | - if (GET_CODE (PATTERN (jump_insn)) == RETURN) | ||
| 2908 | + if (ANY_RETURN_P (PATTERN (jump_insn))) | ||
| 2909 | { | ||
| 2910 | rtx prev = PREV_INSN (insn); | ||
| 2911 | |||
| 2912 | @@ -3804,13 +3845,16 @@ | ||
| 2913 | else | ||
| 2914 | /* It is probably more efficient to keep this with its current | ||
| 2915 | delay slot as a branch to a RETURN. */ | ||
| 2916 | - reorg_redirect_jump (jump_insn, real_return_label); | ||
| 2917 | + reorg_redirect_jump (jump_insn, real_label); | ||
| 2918 | } | ||
| 2919 | |||
| 2920 | /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any | ||
| 2921 | new delay slots we have created. */ | ||
| 2922 | - if (--LABEL_NUSES (real_return_label) == 0) | ||
| 2923 | + if (real_return_label != NULL_RTX && --LABEL_NUSES (real_return_label) == 0) | ||
| 2924 | delete_related_insns (real_return_label); | ||
| 2925 | + if (real_simple_return_label != NULL_RTX | ||
| 2926 | + && --LABEL_NUSES (real_simple_return_label) == 0) | ||
| 2927 | + delete_related_insns (real_simple_return_label); | ||
| 2928 | |||
| 2929 | fill_simple_delay_slots (1); | ||
| 2930 | fill_simple_delay_slots (0); | ||
| 2931 | @@ -3878,7 +3922,7 @@ | ||
| 2932 | init_resource_info (epilogue_insn); | ||
| 2933 | |||
| 2934 | /* Show we haven't computed an end-of-function label yet. */ | ||
| 2935 | - end_of_function_label = 0; | ||
| 2936 | + function_return_label = function_simple_return_label = NULL_RTX; | ||
| 2937 | |||
| 2938 | /* Initialize the statistics for this function. */ | ||
| 2939 | memset (num_insns_needing_delays, 0, sizeof num_insns_needing_delays); | ||
| 2940 | @@ -3900,11 +3944,23 @@ | ||
| 2941 | /* If we made an end of function label, indicate that it is now | ||
| 2942 | safe to delete it by undoing our prior adjustment to LABEL_NUSES. | ||
| 2943 | If it is now unused, delete it. */ | ||
| 2944 | - if (end_of_function_label && --LABEL_NUSES (end_of_function_label) == 0) | ||
| 2945 | - delete_related_insns (end_of_function_label); | ||
| 2946 | + if (function_return_label && --LABEL_NUSES (function_return_label) == 0) | ||
| 2947 | + delete_related_insns (function_return_label); | ||
| 2948 | + if (function_simple_return_label | ||
| 2949 | + && --LABEL_NUSES (function_simple_return_label) == 0) | ||
| 2950 | + delete_related_insns (function_simple_return_label); | ||
| 2951 | |||
| 2952 | +#if defined HAVE_return || defined HAVE_simple_return | ||
| 2953 | + if ( | ||
| 2954 | #ifdef HAVE_return | ||
| 2955 | - if (HAVE_return && end_of_function_label != 0) | ||
| 2956 | + (HAVE_return && function_return_label != 0) | ||
| 2957 | +#else | ||
| 2958 | + 0 | ||
| 2959 | +#endif | ||
| 2960 | +#ifdef HAVE_simple_return | ||
| 2961 | + || (HAVE_simple_return && function_simple_return_label != 0) | ||
| 2962 | +#endif | ||
| 2963 | + ) | ||
| 2964 | make_return_insns (first); | ||
| 2965 | #endif | ||
| 2966 | |||
| 2967 | |||
| 2968 | === modified file 'gcc/resource.c' | ||
| 2969 | --- old/gcc/resource.c 2009-11-25 10:55:54 +0000 | ||
| 2970 | +++ new/gcc/resource.c 2011-01-05 12:12:18 +0000 | ||
| 2971 | @@ -495,6 +495,8 @@ | ||
| 2972 | || GET_CODE (PATTERN (this_jump_insn)) == RETURN) | ||
| 2973 | { | ||
| 2974 | next = JUMP_LABEL (this_jump_insn); | ||
| 2975 | + if (next && ANY_RETURN_P (next)) | ||
| 2976 | + next = NULL_RTX; | ||
| 2977 | if (jump_insn == 0) | ||
| 2978 | { | ||
| 2979 | jump_insn = insn; | ||
| 2980 | @@ -562,9 +564,10 @@ | ||
| 2981 | AND_COMPL_HARD_REG_SET (scratch, needed.regs); | ||
| 2982 | AND_COMPL_HARD_REG_SET (fallthrough_res.regs, scratch); | ||
| 2983 | |||
| 2984 | - find_dead_or_set_registers (JUMP_LABEL (this_jump_insn), | ||
| 2985 | - &target_res, 0, jump_count, | ||
| 2986 | - target_set, needed); | ||
| 2987 | + if (!ANY_RETURN_P (JUMP_LABEL (this_jump_insn))) | ||
| 2988 | + find_dead_or_set_registers (JUMP_LABEL (this_jump_insn), | ||
| 2989 | + &target_res, 0, jump_count, | ||
| 2990 | + target_set, needed); | ||
| 2991 | find_dead_or_set_registers (next, | ||
| 2992 | &fallthrough_res, 0, jump_count, | ||
| 2993 | set, needed); | ||
| 2994 | @@ -1097,6 +1100,8 @@ | ||
| 2995 | struct resources new_resources; | ||
| 2996 | rtx stop_insn = next_active_insn (jump_insn); | ||
| 2997 | |||
| 2998 | + if (jump_target && ANY_RETURN_P (jump_target)) | ||
| 2999 | + jump_target = NULL_RTX; | ||
| 3000 | mark_target_live_regs (insns, next_active_insn (jump_target), | ||
| 3001 | &new_resources); | ||
| 3002 | CLEAR_RESOURCE (&set); | ||
| 3003 | |||
| 3004 | === modified file 'gcc/rtl.c' | ||
| 3005 | --- old/gcc/rtl.c 2010-12-13 10:05:52 +0000 | ||
| 3006 | +++ new/gcc/rtl.c 2011-01-05 12:12:18 +0000 | ||
| 3007 | @@ -256,6 +256,8 @@ | ||
| 3008 | case CODE_LABEL: | ||
| 3009 | case PC: | ||
| 3010 | case CC0: | ||
| 3011 | + case RETURN: | ||
| 3012 | + case SIMPLE_RETURN: | ||
| 3013 | case SCRATCH: | ||
| 3014 | /* SCRATCH must be shared because they represent distinct values. */ | ||
| 3015 | return orig; | ||
| 3016 | |||
| 3017 | === modified file 'gcc/rtl.def' | ||
| 3018 | --- old/gcc/rtl.def 2010-04-02 18:54:46 +0000 | ||
| 3019 | +++ new/gcc/rtl.def 2011-01-05 12:12:18 +0000 | ||
| 3020 | @@ -296,6 +296,10 @@ | ||
| 3021 | |||
| 3022 | DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA) | ||
| 3023 | |||
| 3024 | +/* A plain return, to be used on paths that are reached without going | ||
| 3025 | + through the function prologue. */ | ||
| 3026 | +DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA) | ||
| 3027 | + | ||
| 3028 | /* Special for EH return from subroutine. */ | ||
| 3029 | |||
| 3030 | DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA) | ||
| 3031 | |||
| 3032 | === modified file 'gcc/rtl.h' | ||
| 3033 | --- old/gcc/rtl.h 2010-11-16 22:17:17 +0000 | ||
| 3034 | +++ new/gcc/rtl.h 2011-01-05 12:12:18 +0000 | ||
| 3035 | @@ -411,6 +411,10 @@ | ||
| 3036 | (JUMP_P (INSN) && (GET_CODE (PATTERN (INSN)) == ADDR_VEC || \ | ||
| 3037 | GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC)) | ||
| 3038 | |||
| 3039 | +/* Predicate yielding nonzero iff X is a return or simple_preturn. */ | ||
| 3040 | +#define ANY_RETURN_P(X) \ | ||
| 3041 | + (GET_CODE (X) == RETURN || GET_CODE (X) == SIMPLE_RETURN) | ||
| 3042 | + | ||
| 3043 | /* 1 if X is a unary operator. */ | ||
| 3044 | |||
| 3045 | #define UNARY_P(X) \ | ||
| 3046 | @@ -1998,6 +2002,8 @@ | ||
| 3047 | { | ||
| 3048 | GR_PC, | ||
| 3049 | GR_CC0, | ||
| 3050 | + GR_RETURN, | ||
| 3051 | + GR_SIMPLE_RETURN, | ||
| 3052 | GR_STACK_POINTER, | ||
| 3053 | GR_FRAME_POINTER, | ||
| 3054 | /* For register elimination to work properly these hard_frame_pointer_rtx, | ||
| 3055 | @@ -2032,6 +2038,8 @@ | ||
| 3056 | |||
| 3057 | /* Standard pieces of rtx, to be substituted directly into things. */ | ||
| 3058 | #define pc_rtx (global_rtl[GR_PC]) | ||
| 3059 | +#define ret_rtx (global_rtl[GR_RETURN]) | ||
| 3060 | +#define simple_return_rtx (global_rtl[GR_SIMPLE_RETURN]) | ||
| 3061 | #define cc0_rtx (global_rtl[GR_CC0]) | ||
| 3062 | |||
| 3063 | /* All references to certain hard regs, except those created | ||
| 3064 | |||
| 3065 | === modified file 'gcc/rtlanal.c' | ||
| 3066 | --- old/gcc/rtlanal.c 2010-11-16 22:17:17 +0000 | ||
| 3067 | +++ new/gcc/rtlanal.c 2011-01-05 12:12:18 +0000 | ||
| 3068 | @@ -2673,6 +2673,7 @@ | ||
| 3069 | |||
| 3070 | if (JUMP_P (insn) | ||
| 3071 | && (label = JUMP_LABEL (insn)) != NULL_RTX | ||
| 3072 | + && !ANY_RETURN_P (label) | ||
| 3073 | && (table = next_active_insn (label)) != NULL_RTX | ||
| 3074 | && JUMP_TABLE_DATA_P (table)) | ||
| 3075 | { | ||
| 3076 | |||
| 3077 | === modified file 'gcc/sched-int.h' | ||
| 3078 | --- old/gcc/sched-int.h 2010-06-02 16:31:39 +0000 | ||
| 3079 | +++ new/gcc/sched-int.h 2011-01-05 12:12:18 +0000 | ||
| 3080 | @@ -199,7 +199,7 @@ | ||
| 3081 | |||
| 3082 | extern void ebb_compute_jump_reg_dependencies (rtx, regset, regset, regset); | ||
| 3083 | |||
| 3084 | -extern edge find_fallthru_edge (basic_block); | ||
| 3085 | +extern edge find_fallthru_edge_from (basic_block); | ||
| 3086 | |||
| 3087 | extern void (* sched_init_only_bb) (basic_block, basic_block); | ||
| 3088 | extern basic_block (* sched_split_block) (basic_block, rtx); | ||
| 3089 | |||
| 3090 | === modified file 'gcc/sched-vis.c' | ||
| 3091 | --- old/gcc/sched-vis.c 2009-11-25 10:55:54 +0000 | ||
| 3092 | +++ new/gcc/sched-vis.c 2011-01-05 12:12:18 +0000 | ||
| 3093 | @@ -549,6 +549,9 @@ | ||
| 3094 | case RETURN: | ||
| 3095 | sprintf (buf, "return"); | ||
| 3096 | break; | ||
| 3097 | + case SIMPLE_RETURN: | ||
| 3098 | + sprintf (buf, "simple_return"); | ||
| 3099 | + break; | ||
| 3100 | case CALL: | ||
| 3101 | print_exp (buf, x, verbose); | ||
| 3102 | break; | ||
| 3103 | |||
| 3104 | === modified file 'gcc/sel-sched-ir.c' | ||
| 3105 | --- old/gcc/sel-sched-ir.c 2010-08-31 11:52:01 +0000 | ||
| 3106 | +++ new/gcc/sel-sched-ir.c 2011-01-05 12:12:18 +0000 | ||
| 3107 | @@ -686,7 +686,7 @@ | ||
| 3108 | |||
| 3109 | /* Find fallthrough edge. */ | ||
| 3110 | gcc_assert (BLOCK_FOR_INSN (insn)->prev_bb); | ||
| 3111 | - candidate = find_fallthru_edge (BLOCK_FOR_INSN (insn)->prev_bb); | ||
| 3112 | + candidate = find_fallthru_edge_from (BLOCK_FOR_INSN (insn)->prev_bb); | ||
| 3113 | |||
| 3114 | if (!candidate | ||
| 3115 | || (candidate->src != BLOCK_FOR_INSN (last_scheduled_insn) | ||
| 3116 | |||
| 3117 | === modified file 'gcc/sel-sched.c' | ||
| 3118 | --- old/gcc/sel-sched.c 2010-11-12 15:47:38 +0000 | ||
| 3119 | +++ new/gcc/sel-sched.c 2011-01-05 12:12:18 +0000 | ||
| 3120 | @@ -617,8 +617,8 @@ | ||
| 3121 | if (bb == BLOCK_FOR_INSN (succ)) | ||
| 3122 | return true; | ||
| 3123 | |||
| 3124 | - if (find_fallthru_edge (bb)) | ||
| 3125 | - bb = find_fallthru_edge (bb)->dest; | ||
| 3126 | + if (find_fallthru_edge_from (bb)) | ||
| 3127 | + bb = find_fallthru_edge_from (bb)->dest; | ||
| 3128 | else | ||
| 3129 | return false; | ||
| 3130 | |||
| 3131 | @@ -4911,7 +4911,7 @@ | ||
| 3132 | next = PREV_INSN (insn); | ||
| 3133 | BND_TO (bnd) = insn; | ||
| 3134 | |||
| 3135 | - ft_edge = find_fallthru_edge (block_from); | ||
| 3136 | + ft_edge = find_fallthru_edge_from (block_from); | ||
| 3137 | block_next = ft_edge->dest; | ||
| 3138 | /* There must be a fallthrough block (or where should go | ||
| 3139 | control flow in case of false jump predicate otherwise?). */ | ||
| 3140 | |||
| 3141 | === modified file 'gcc/vec.h' | ||
| 3142 | --- old/gcc/vec.h 2010-01-09 14:46:25 +0000 | ||
| 3143 | +++ new/gcc/vec.h 2011-01-05 12:12:18 +0000 | ||
| 3144 | @@ -188,6 +188,18 @@ | ||
| 3145 | |||
| 3146 | #define VEC_iterate(T,V,I,P) (VEC_OP(T,base,iterate)(VEC_BASE(V),I,&(P))) | ||
| 3147 | |||
| 3148 | +/* Convenience macro for forward iteration. */ | ||
| 3149 | + | ||
| 3150 | +#define FOR_EACH_VEC_ELT(T, V, I, P) \ | ||
| 3151 | + for (I = 0; VEC_iterate (T, (V), (I), (P)); ++(I)) | ||
| 3152 | + | ||
| 3153 | +/* Convenience macro for reverse iteration. */ | ||
| 3154 | + | ||
| 3155 | +#define FOR_EACH_VEC_ELT_REVERSE(T,V,I,P) \ | ||
| 3156 | + for (I = VEC_length (T, (V)) - 1; \ | ||
| 3157 | + VEC_iterate (T, (V), (I), (P)); \ | ||
| 3158 | + (I)--) | ||
| 3159 | + | ||
| 3160 | /* Allocate new vector. | ||
| 3161 | VEC(T,A) *VEC_T_A_alloc(int reserve); | ||
| 3162 | |||
| 3163 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99457.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99457.patch deleted file mode 100644 index 47b897d5e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99457.patch +++ /dev/null | |||
| @@ -1,4236 +0,0 @@ | |||
| 1 | 2010-12-03 Yao Qi <yao@codesourcery.com> | ||
| 2 | |||
| 3 | * config/arm/arm-ldmstm.ml: Rewrite ldm/stm RTL patterns to fix | ||
| 4 | regressions. | ||
| 5 | * config/arm/ldmstm.md: Regenreate. | ||
| 6 | |||
| 7 | 2010-12-03 Yao Qi <yao@codesourcery.com> | ||
| 8 | |||
| 9 | Backport from FSF mainline: | ||
| 10 | |||
| 11 | 2010-08-02 Bernd Schmidt <bernds@codesourcery.com> | ||
| 12 | |||
| 13 | PR target/40457 | ||
| 14 | * config/arm/arm.h (arm_regs_in_sequence): Declare. | ||
| 15 | * config/arm/arm-protos.h (emit_ldm_seq, emit_stm_seq, | ||
| 16 | load_multiple_sequence, store_multiple_sequence): Delete | ||
| 17 | declarations. | ||
| 18 | (arm_gen_load_multiple, arm_gen_store_multiple): Adjust | ||
| 19 | declarations. | ||
| 20 | * config/arm/ldmstm.md: New file. | ||
| 21 | * config/arm/arm.c (arm_regs_in_sequence): New array. | ||
| 22 | (load_multiple_sequence): Now static. New args SAVED_ORDER, | ||
| 23 | CHECK_REGS. All callers changed. | ||
| 24 | If SAVED_ORDER is nonnull, copy the computed order into it. | ||
| 25 | If CHECK_REGS is false, don't sort REGS. Handle Thumb mode. | ||
| 26 | (store_multiple_sequence): Now static. New args NOPS_TOTAL, | ||
| 27 | SAVED_ORDER, REG_RTXS and CHECK_REGS. All callers changed. | ||
| 28 | If SAVED_ORDER is nonnull, copy the computed order into it. | ||
| 29 | If CHECK_REGS is false, don't sort REGS. Set up REG_RTXS just | ||
| 30 | like REGS. Handle Thumb mode. | ||
| 31 | (arm_gen_load_multiple_1): New function, broken out of | ||
| 32 | arm_gen_load_multiple. | ||
| 33 | (arm_gen_store_multiple_1): New function, broken out of | ||
| 34 | arm_gen_store_multiple. | ||
| 35 | (arm_gen_multiple_op): New function, with code from | ||
| 36 | arm_gen_load_multiple and arm_gen_store_multiple moved here. | ||
| 37 | (arm_gen_load_multiple, arm_gen_store_multiple): Now just | ||
| 38 | wrappers around arm_gen_multiple_op. Remove argument UP, all callers | ||
| 39 | changed. | ||
| 40 | (gen_ldm_seq, gen_stm_seq, gen_const_stm_seq): New functions. | ||
| 41 | * config/arm/predicates.md (commutative_binary_operator): New. | ||
| 42 | (load_multiple_operation, store_multiple_operation): Handle more | ||
| 43 | variants of these patterns with different starting offsets. Handle | ||
| 44 | Thumb-1. | ||
| 45 | * config/arm/arm.md: Include "ldmstm.md". | ||
| 46 | (ldmsi_postinc4, ldmsi_postinc4_thumb1, ldmsi_postinc3, ldmsi_postinc2, | ||
| 47 | ldmsi4, ldmsi3, ldmsi2, stmsi_postinc4, stmsi_postinc4_thumb1, | ||
| 48 | stmsi_postinc3, stmsi_postinc2, stmsi4, stmsi3, stmsi2 and related | ||
| 49 | peepholes): Delete. | ||
| 50 | * config/arm/ldmstm.md: New file. | ||
| 51 | * config/arm/arm-ldmstm.ml: New file. | ||
| 52 | |||
| 53 | * config/arm/arm.c (arm_rtx_costs_1): Remove second clause from the | ||
| 54 | if statement which adds extra costs to frame-related expressions. | ||
| 55 | |||
| 56 | 2010-05-06 Bernd Schmidt <bernds@codesourcery.com> | ||
| 57 | |||
| 58 | * config/arm/arm.h (MAX_LDM_STM_OPS): New macro. | ||
| 59 | * config/arm/arm.c (multiple_operation_profitable_p, | ||
| 60 | compute_offset_order): New static functions. | ||
| 61 | (load_multiple_sequence, store_multiple_sequence): Use them. | ||
| 62 | Replace constant 4 with MAX_LDM_STM_OPS. Compute order[0] from | ||
| 63 | memory offsets, not register numbers. | ||
| 64 | (emit_ldm_seq, emit_stm_seq): Replace constant 4 with MAX_LDM_STM_OPS. | ||
| 65 | |||
| 66 | 2010-04-16 Bernd Schmidt <bernds@codesourcery.com> | ||
| 67 | |||
| 68 | * recog.h (struct recog_data): New field is_operator. | ||
| 69 | (struct insn_operand_data): New field is_operator. | ||
| 70 | * recog.c (extract_insn): Set recog_data.is_operator. | ||
| 71 | * genoutput.c (output_operand_data): Emit code to set the | ||
| 72 | is_operator field. | ||
| 73 | * reload.c (find_reloads): Use it rather than testing for an | ||
| 74 | empty constraint string. | ||
| 75 | |||
| 76 | === added file 'gcc/config/arm/arm-ldmstm.ml' | ||
| 77 | --- old/gcc/config/arm/arm-ldmstm.ml 1970-01-01 00:00:00 +0000 | ||
| 78 | +++ new/gcc/config/arm/arm-ldmstm.ml 2010-11-16 13:08:47 +0000 | ||
| 79 | @@ -0,0 +1,333 @@ | ||
| 80 | +(* Auto-generate ARM ldm/stm patterns | ||
| 81 | + Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 82 | + Contributed by CodeSourcery. | ||
| 83 | + | ||
| 84 | + This file is part of GCC. | ||
| 85 | + | ||
| 86 | + GCC is free software; you can redistribute it and/or modify it under | ||
| 87 | + the terms of the GNU General Public License as published by the Free | ||
| 88 | + Software Foundation; either version 3, or (at your option) any later | ||
| 89 | + version. | ||
| 90 | + | ||
| 91 | + GCC is distributed in the hope that it will be useful, but WITHOUT ANY | ||
| 92 | + WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 93 | + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
| 94 | + for more details. | ||
| 95 | + | ||
| 96 | + You should have received a copy of the GNU General Public License | ||
| 97 | + along with GCC; see the file COPYING3. If not see | ||
| 98 | + <http://www.gnu.org/licenses/>. | ||
| 99 | + | ||
| 100 | + This is an O'Caml program. The O'Caml compiler is available from: | ||
| 101 | + | ||
| 102 | + http://caml.inria.fr/ | ||
| 103 | + | ||
| 104 | + Or from your favourite OS's friendly packaging system. Tested with version | ||
| 105 | + 3.09.2, though other versions will probably work too. | ||
| 106 | + | ||
| 107 | + Run with: | ||
| 108 | + ocaml arm-ldmstm.ml >/path/to/gcc/config/arm/ldmstm.ml | ||
| 109 | +*) | ||
| 110 | + | ||
| 111 | +type amode = IA | IB | DA | DB | ||
| 112 | + | ||
| 113 | +type optype = IN | OUT | INOUT | ||
| 114 | + | ||
| 115 | +let rec string_of_addrmode addrmode = | ||
| 116 | + match addrmode with | ||
| 117 | + IA -> "ia" | IB -> "ib" | DA -> "da" | DB -> "db" | ||
| 118 | + | ||
| 119 | +let rec initial_offset addrmode nregs = | ||
| 120 | + match addrmode with | ||
| 121 | + IA -> 0 | ||
| 122 | + | IB -> 4 | ||
| 123 | + | DA -> -4 * nregs + 4 | ||
| 124 | + | DB -> -4 * nregs | ||
| 125 | + | ||
| 126 | +let rec final_offset addrmode nregs = | ||
| 127 | + match addrmode with | ||
| 128 | + IA -> nregs * 4 | ||
| 129 | + | IB -> nregs * 4 | ||
| 130 | + | DA -> -4 * nregs | ||
| 131 | + | DB -> -4 * nregs | ||
| 132 | + | ||
| 133 | +let constr thumb = | ||
| 134 | + if thumb then "l" else "rk" | ||
| 135 | + | ||
| 136 | +let inout_constr op_type = | ||
| 137 | + match op_type with | ||
| 138 | + OUT -> "=" | ||
| 139 | + | INOUT -> "+&" | ||
| 140 | + | IN -> "" | ||
| 141 | + | ||
| 142 | +let destreg nregs first op_type thumb = | ||
| 143 | + if not first then | ||
| 144 | + Printf.sprintf "(match_dup %d)" (nregs) | ||
| 145 | + else | ||
| 146 | + Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")") | ||
| 147 | + (nregs) (inout_constr op_type) (constr thumb) | ||
| 148 | + | ||
| 149 | +let write_ldm_set thumb nregs offset opnr first = | ||
| 150 | + let indent = " " in | ||
| 151 | + Printf.printf "%s" (if first then " [" else indent); | ||
| 152 | + Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr; | ||
| 153 | + Printf.printf "%s (mem:SI " indent; | ||
| 154 | + begin if offset != 0 then Printf.printf "(plus:SI " end; | ||
| 155 | + Printf.printf "%s" (destreg nregs first IN thumb); | ||
| 156 | + begin if offset != 0 then Printf.printf "\n%s (const_int %d))" indent offset end; | ||
| 157 | + Printf.printf "))" | ||
| 158 | + | ||
| 159 | +let write_stm_set thumb nregs offset opnr first = | ||
| 160 | + let indent = " " in | ||
| 161 | + Printf.printf "%s" (if first then " [" else indent); | ||
| 162 | + Printf.printf "(set (mem:SI "; | ||
| 163 | + begin if offset != 0 then Printf.printf "(plus:SI " end; | ||
| 164 | + Printf.printf "%s" (destreg nregs first IN thumb); | ||
| 165 | + begin if offset != 0 then Printf.printf " (const_int %d))" offset end; | ||
| 166 | + Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr | ||
| 167 | + | ||
| 168 | +let write_ldm_peep_set extra_indent nregs opnr first = | ||
| 169 | + let indent = " " ^ extra_indent in | ||
| 170 | + Printf.printf "%s" (if first then extra_indent ^ " [" else indent); | ||
| 171 | + Printf.printf "(set (match_operand:SI %d \"s_register_operand\" \"\")\n" opnr; | ||
| 172 | + Printf.printf "%s (match_operand:SI %d \"memory_operand\" \"\"))" indent (nregs + opnr) | ||
| 173 | + | ||
| 174 | +let write_stm_peep_set extra_indent nregs opnr first = | ||
| 175 | + let indent = " " ^ extra_indent in | ||
| 176 | + Printf.printf "%s" (if first then extra_indent ^ " [" else indent); | ||
| 177 | + Printf.printf "(set (match_operand:SI %d \"memory_operand\" \"\")\n" (nregs + opnr); | ||
| 178 | + Printf.printf "%s (match_operand:SI %d \"s_register_operand\" \"\"))" indent opnr | ||
| 179 | + | ||
| 180 | +let write_any_load optype nregs opnr first = | ||
| 181 | + let indent = " " in | ||
| 182 | + Printf.printf "%s" (if first then " [" else indent); | ||
| 183 | + Printf.printf "(set (match_operand:SI %d \"s_register_operand\" \"\")\n" opnr; | ||
| 184 | + Printf.printf "%s (match_operand:SI %d \"%s\" \"\"))" indent (nregs * 2 + opnr) optype | ||
| 185 | + | ||
| 186 | +let write_const_store nregs opnr first = | ||
| 187 | + let indent = " " in | ||
| 188 | + Printf.printf "%s(set (match_operand:SI %d \"memory_operand\" \"\")\n" indent (nregs + opnr); | ||
| 189 | + Printf.printf "%s (match_dup %d))" indent opnr | ||
| 190 | + | ||
| 191 | +let write_const_stm_peep_set nregs opnr first = | ||
| 192 | + write_any_load "const_int_operand" nregs opnr first; | ||
| 193 | + Printf.printf "\n"; | ||
| 194 | + write_const_store nregs opnr false | ||
| 195 | + | ||
| 196 | + | ||
| 197 | +let rec write_pat_sets func opnr offset first n_left = | ||
| 198 | + func offset opnr first; | ||
| 199 | + begin | ||
| 200 | + if n_left > 1 then begin | ||
| 201 | + Printf.printf "\n"; | ||
| 202 | + write_pat_sets func (opnr + 1) (offset + 4) false (n_left - 1); | ||
| 203 | + end else | ||
| 204 | + Printf.printf "]" | ||
| 205 | + end | ||
| 206 | + | ||
| 207 | +let rec write_peep_sets func opnr first n_left = | ||
| 208 | + func opnr first; | ||
| 209 | + begin | ||
| 210 | + if n_left > 1 then begin | ||
| 211 | + Printf.printf "\n"; | ||
| 212 | + write_peep_sets func (opnr + 1) false (n_left - 1); | ||
| 213 | + end | ||
| 214 | + end | ||
| 215 | + | ||
| 216 | +let can_thumb addrmode update is_store = | ||
| 217 | + match addrmode, update, is_store with | ||
| 218 | + (* Thumb1 mode only supports IA with update. However, for LDMIA, | ||
| 219 | + if the address register also appears in the list of loaded | ||
| 220 | + registers, the loaded value is stored, hence the RTL pattern | ||
| 221 | + to describe such an insn does not have an update. We check | ||
| 222 | + in the match_parallel predicate that the condition described | ||
| 223 | + above is met. *) | ||
| 224 | + IA, _, false -> true | ||
| 225 | + | IA, true, true -> true | ||
| 226 | + | _ -> false | ||
| 227 | + | ||
| 228 | +let target addrmode thumb = | ||
| 229 | + match addrmode, thumb with | ||
| 230 | + IA, true -> "TARGET_THUMB1" | ||
| 231 | + | IA, false -> "TARGET_32BIT" | ||
| 232 | + | DB, false -> "TARGET_32BIT" | ||
| 233 | + | _, false -> "TARGET_ARM" | ||
| 234 | + | ||
| 235 | +let write_pattern_1 name ls addrmode nregs write_set_fn update thumb = | ||
| 236 | + let astr = string_of_addrmode addrmode in | ||
| 237 | + Printf.printf "(define_insn \"*%s%s%d_%s%s\"\n" | ||
| 238 | + (if thumb then "thumb_" else "") name nregs astr | ||
| 239 | + (if update then "_update" else ""); | ||
| 240 | + Printf.printf " [(match_parallel 0 \"%s_multiple_operation\"\n" ls; | ||
| 241 | + begin | ||
| 242 | + if update then begin | ||
| 243 | + Printf.printf " [(set %s\n (plus:SI " | ||
| 244 | + (destreg 1 true OUT thumb); (*destreg 2 true IN thumb*) | ||
| 245 | + Printf.printf "(match_operand:SI 2 \"s_register_operand\" \"1\")"; | ||
| 246 | + Printf.printf " (const_int %d)))\n" | ||
| 247 | + (final_offset addrmode nregs) | ||
| 248 | + end | ||
| 249 | + end; | ||
| 250 | + write_pat_sets | ||
| 251 | + (write_set_fn thumb (if update then 2 else 1)) (if update then 3 else 2) | ||
| 252 | + (initial_offset addrmode nregs) | ||
| 253 | + (not update) nregs; | ||
| 254 | + Printf.printf ")]\n \"%s && XVECLEN (operands[0], 0) == %d\"\n" | ||
| 255 | + (target addrmode thumb) | ||
| 256 | + (if update then nregs + 1 else nregs); | ||
| 257 | + Printf.printf " \"%s%%(%s%%)\\t%%%d%s, {" | ||
| 258 | + name astr (1) (if update then "!" else ""); | ||
| 259 | + for n = 1 to nregs; do | ||
| 260 | + Printf.printf "%%%d%s" (n+(if update then 2 else 1)) (if n < nregs then ", " else "") | ||
| 261 | + done; | ||
| 262 | + Printf.printf "}\"\n"; | ||
| 263 | + Printf.printf " [(set_attr \"type\" \"%s%d\")" ls nregs; | ||
| 264 | + begin if not thumb then | ||
| 265 | + Printf.printf "\n (set_attr \"predicable\" \"yes\")"; | ||
| 266 | + end; | ||
| 267 | + Printf.printf "])\n\n" | ||
| 268 | + | ||
| 269 | +let write_ldm_pattern addrmode nregs update = | ||
| 270 | + write_pattern_1 "ldm" "load" addrmode nregs write_ldm_set update false; | ||
| 271 | + begin if can_thumb addrmode update false then | ||
| 272 | + write_pattern_1 "ldm" "load" addrmode nregs write_ldm_set update true; | ||
| 273 | + end | ||
| 274 | + | ||
| 275 | +let write_stm_pattern addrmode nregs update = | ||
| 276 | + write_pattern_1 "stm" "store" addrmode nregs write_stm_set update false; | ||
| 277 | + begin if can_thumb addrmode update true then | ||
| 278 | + write_pattern_1 "stm" "store" addrmode nregs write_stm_set update true; | ||
| 279 | + end | ||
| 280 | + | ||
| 281 | +let write_ldm_commutative_peephole thumb = | ||
| 282 | + let nregs = 2 in | ||
| 283 | + Printf.printf "(define_peephole2\n"; | ||
| 284 | + write_peep_sets (write_ldm_peep_set "" nregs) 0 true nregs; | ||
| 285 | + let indent = " " in | ||
| 286 | + if thumb then begin | ||
| 287 | + Printf.printf "\n%s(set (match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2); | ||
| 288 | + Printf.printf "%s (match_operator:SI %d \"commutative_binary_operator\"\n" indent (nregs * 2 + 1); | ||
| 289 | + Printf.printf "%s [(match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2 + 2); | ||
| 290 | + Printf.printf "%s (match_operand:SI %d \"s_register_operand\" \"\")]))]\n" indent (nregs * 2 + 3) | ||
| 291 | + end else begin | ||
| 292 | + Printf.printf "\n%s(parallel\n" indent; | ||
| 293 | + Printf.printf "%s [(set (match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2); | ||
| 294 | + Printf.printf "%s (match_operator:SI %d \"commutative_binary_operator\"\n" indent (nregs * 2 + 1); | ||
| 295 | + Printf.printf "%s [(match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2 + 2); | ||
| 296 | + Printf.printf "%s (match_operand:SI %d \"s_register_operand\" \"\")]))\n" indent (nregs * 2 + 3); | ||
| 297 | + Printf.printf "%s (clobber (reg:CC CC_REGNUM))])]\n" indent | ||
| 298 | + end; | ||
| 299 | + Printf.printf " \"(((operands[%d] == operands[0] && operands[%d] == operands[1])\n" (nregs * 2 + 2) (nregs * 2 + 3); | ||
| 300 | + Printf.printf " || (operands[%d] == operands[0] && operands[%d] == operands[1]))\n" (nregs * 2 + 3) (nregs * 2 + 2); | ||
| 301 | + Printf.printf " && peep2_reg_dead_p (%d, operands[0]) && peep2_reg_dead_p (%d, operands[1]))\"\n" (nregs + 1) (nregs + 1); | ||
| 302 | + begin | ||
| 303 | + if thumb then | ||
| 304 | + Printf.printf " [(set (match_dup %d) (match_op_dup %d [(match_dup %d) (match_dup %d)]))]\n" | ||
| 305 | + (nregs * 2) (nregs * 2 + 1) (nregs * 2 + 2) (nregs * 2 + 3) | ||
| 306 | + else begin | ||
| 307 | + Printf.printf " [(parallel\n"; | ||
| 308 | + Printf.printf " [(set (match_dup %d) (match_op_dup %d [(match_dup %d) (match_dup %d)]))\n" | ||
| 309 | + (nregs * 2) (nregs * 2 + 1) (nregs * 2 + 2) (nregs * 2 + 3); | ||
| 310 | + Printf.printf " (clobber (reg:CC CC_REGNUM))])]\n" | ||
| 311 | + end | ||
| 312 | + end; | ||
| 313 | + Printf.printf "{\n if (!gen_ldm_seq (operands, %d, true))\n FAIL;\n" nregs; | ||
| 314 | + Printf.printf "})\n\n" | ||
| 315 | + | ||
| 316 | +let write_ldm_peephole nregs = | ||
| 317 | + Printf.printf "(define_peephole2\n"; | ||
| 318 | + write_peep_sets (write_ldm_peep_set "" nregs) 0 true nregs; | ||
| 319 | + Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; | ||
| 320 | + Printf.printf " if (gen_ldm_seq (operands, %d, false))\n DONE;\n else\n FAIL;\n})\n\n" nregs | ||
| 321 | + | ||
| 322 | +let write_ldm_peephole_b nregs = | ||
| 323 | + if nregs > 2 then begin | ||
| 324 | + Printf.printf "(define_peephole2\n"; | ||
| 325 | + write_ldm_peep_set "" nregs 0 true; | ||
| 326 | + Printf.printf "\n (parallel\n"; | ||
| 327 | + write_peep_sets (write_ldm_peep_set " " nregs) 1 true (nregs - 1); | ||
| 328 | + Printf.printf "])]\n \"\"\n [(const_int 0)]\n{\n"; | ||
| 329 | + Printf.printf " if (gen_ldm_seq (operands, %d, false))\n DONE;\n else\n FAIL;\n})\n\n" nregs | ||
| 330 | + end | ||
| 331 | + | ||
| 332 | +let write_stm_peephole nregs = | ||
| 333 | + Printf.printf "(define_peephole2\n"; | ||
| 334 | + write_peep_sets (write_stm_peep_set "" nregs) 0 true nregs; | ||
| 335 | + Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; | ||
| 336 | + Printf.printf " if (gen_stm_seq (operands, %d))\n DONE;\n else\n FAIL;\n})\n\n" nregs | ||
| 337 | + | ||
| 338 | +let write_stm_peephole_b nregs = | ||
| 339 | + if nregs > 2 then begin | ||
| 340 | + Printf.printf "(define_peephole2\n"; | ||
| 341 | + write_stm_peep_set "" nregs 0 true; | ||
| 342 | + Printf.printf "\n (parallel\n"; | ||
| 343 | + write_peep_sets (write_stm_peep_set "" nregs) 1 true (nregs - 1); | ||
| 344 | + Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; | ||
| 345 | + Printf.printf " if (gen_stm_seq (operands, %d))\n DONE;\n else\n FAIL;\n})\n\n" nregs | ||
| 346 | + end | ||
| 347 | + | ||
| 348 | +let write_const_stm_peephole_a nregs = | ||
| 349 | + Printf.printf "(define_peephole2\n"; | ||
| 350 | + write_peep_sets (write_const_stm_peep_set nregs) 0 true nregs; | ||
| 351 | + Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; | ||
| 352 | + Printf.printf " if (gen_const_stm_seq (operands, %d))\n DONE;\n else\n FAIL;\n})\n\n" nregs | ||
| 353 | + | ||
| 354 | +let write_const_stm_peephole_b nregs = | ||
| 355 | + Printf.printf "(define_peephole2\n"; | ||
| 356 | + write_peep_sets (write_any_load "const_int_operand" nregs) 0 true nregs; | ||
| 357 | + Printf.printf "\n"; | ||
| 358 | + write_peep_sets (write_const_store nregs) 0 false nregs; | ||
| 359 | + Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; | ||
| 360 | + Printf.printf " if (gen_const_stm_seq (operands, %d))\n DONE;\n else\n FAIL;\n})\n\n" nregs | ||
| 361 | + | ||
| 362 | +let patterns () = | ||
| 363 | + let addrmodes = [ IA; IB; DA; DB ] in | ||
| 364 | + let sizes = [ 4; 3; 2] in | ||
| 365 | + List.iter | ||
| 366 | + (fun n -> | ||
| 367 | + List.iter | ||
| 368 | + (fun addrmode -> | ||
| 369 | + write_ldm_pattern addrmode n false; | ||
| 370 | + write_ldm_pattern addrmode n true; | ||
| 371 | + write_stm_pattern addrmode n false; | ||
| 372 | + write_stm_pattern addrmode n true) | ||
| 373 | + addrmodes; | ||
| 374 | + write_ldm_peephole n; | ||
| 375 | + write_ldm_peephole_b n; | ||
| 376 | + write_const_stm_peephole_a n; | ||
| 377 | + write_const_stm_peephole_b n; | ||
| 378 | + write_stm_peephole n;) | ||
| 379 | + sizes; | ||
| 380 | + write_ldm_commutative_peephole false; | ||
| 381 | + write_ldm_commutative_peephole true | ||
| 382 | + | ||
| 383 | +let print_lines = List.iter (fun s -> Format.printf "%s@\n" s) | ||
| 384 | + | ||
| 385 | +(* Do it. *) | ||
| 386 | + | ||
| 387 | +let _ = | ||
| 388 | + print_lines [ | ||
| 389 | +"/* ARM ldm/stm instruction patterns. This file was automatically generated"; | ||
| 390 | +" using arm-ldmstm.ml. Please do not edit manually."; | ||
| 391 | +""; | ||
| 392 | +" Copyright (C) 2010 Free Software Foundation, Inc."; | ||
| 393 | +" Contributed by CodeSourcery."; | ||
| 394 | +""; | ||
| 395 | +" This file is part of GCC."; | ||
| 396 | +""; | ||
| 397 | +" GCC is free software; you can redistribute it and/or modify it"; | ||
| 398 | +" under the terms of the GNU General Public License as published"; | ||
| 399 | +" by the Free Software Foundation; either version 3, or (at your"; | ||
| 400 | +" option) any later version."; | ||
| 401 | +""; | ||
| 402 | +" GCC is distributed in the hope that it will be useful, but WITHOUT"; | ||
| 403 | +" ANY WARRANTY; without even the implied warranty of MERCHANTABILITY"; | ||
| 404 | +" or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public"; | ||
| 405 | +" License for more details."; | ||
| 406 | +""; | ||
| 407 | +" You should have received a copy of the GNU General Public License and"; | ||
| 408 | +" a copy of the GCC Runtime Library Exception along with this program;"; | ||
| 409 | +" see the files COPYING3 and COPYING.RUNTIME respectively. If not, see"; | ||
| 410 | +" <http://www.gnu.org/licenses/>. */"; | ||
| 411 | +""]; | ||
| 412 | + patterns (); | ||
| 413 | |||
| 414 | === modified file 'gcc/config/arm/arm-protos.h' | ||
| 415 | --- old/gcc/config/arm/arm-protos.h 2011-01-05 12:12:18 +0000 | ||
| 416 | +++ new/gcc/config/arm/arm-protos.h 2011-01-05 18:20:37 +0000 | ||
| 417 | @@ -100,14 +100,11 @@ | ||
| 418 | extern int label_mentioned_p (rtx); | ||
| 419 | extern RTX_CODE minmax_code (rtx); | ||
| 420 | extern int adjacent_mem_locations (rtx, rtx); | ||
| 421 | -extern int load_multiple_sequence (rtx *, int, int *, int *, HOST_WIDE_INT *); | ||
| 422 | -extern const char *emit_ldm_seq (rtx *, int); | ||
| 423 | -extern int store_multiple_sequence (rtx *, int, int *, int *, HOST_WIDE_INT *); | ||
| 424 | -extern const char * emit_stm_seq (rtx *, int); | ||
| 425 | -extern rtx arm_gen_load_multiple (int, int, rtx, int, int, | ||
| 426 | - rtx, HOST_WIDE_INT *); | ||
| 427 | -extern rtx arm_gen_store_multiple (int, int, rtx, int, int, | ||
| 428 | - rtx, HOST_WIDE_INT *); | ||
| 429 | +extern bool gen_ldm_seq (rtx *, int, bool); | ||
| 430 | +extern bool gen_stm_seq (rtx *, int); | ||
| 431 | +extern bool gen_const_stm_seq (rtx *, int); | ||
| 432 | +extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); | ||
| 433 | +extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); | ||
| 434 | extern int arm_gen_movmemqi (rtx *); | ||
| 435 | extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx); | ||
| 436 | extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx, | ||
| 437 | |||
| 438 | === modified file 'gcc/config/arm/arm.c' | ||
| 439 | --- old/gcc/config/arm/arm.c 2011-01-05 12:12:18 +0000 | ||
| 440 | +++ new/gcc/config/arm/arm.c 2011-01-05 18:20:37 +0000 | ||
| 441 | @@ -753,6 +753,12 @@ | ||
| 442 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" | ||
| 443 | }; | ||
| 444 | |||
| 445 | +/* The register numbers in sequence, for passing to arm_gen_load_multiple. */ | ||
| 446 | +int arm_regs_in_sequence[] = | ||
| 447 | +{ | ||
| 448 | + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 | ||
| 449 | +}; | ||
| 450 | + | ||
| 451 | #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl") | ||
| 452 | #define streq(string1, string2) (strcmp (string1, string2) == 0) | ||
| 453 | |||
| 454 | @@ -9680,142 +9686,16 @@ | ||
| 455 | return 0; | ||
| 456 | } | ||
| 457 | |||
| 458 | -int | ||
| 459 | -load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, | ||
| 460 | - HOST_WIDE_INT *load_offset) | ||
| 461 | -{ | ||
| 462 | - int unsorted_regs[4]; | ||
| 463 | - HOST_WIDE_INT unsorted_offsets[4]; | ||
| 464 | - int order[4]; | ||
| 465 | - int base_reg = -1; | ||
| 466 | - int i; | ||
| 467 | - | ||
| 468 | - if (low_irq_latency) | ||
| 469 | - return 0; | ||
| 470 | - | ||
| 471 | - /* Can only handle 2, 3, or 4 insns at present, | ||
| 472 | - though could be easily extended if required. */ | ||
| 473 | - gcc_assert (nops >= 2 && nops <= 4); | ||
| 474 | - | ||
| 475 | - memset (order, 0, 4 * sizeof (int)); | ||
| 476 | - | ||
| 477 | - /* Loop over the operands and check that the memory references are | ||
| 478 | - suitable (i.e. immediate offsets from the same base register). At | ||
| 479 | - the same time, extract the target register, and the memory | ||
| 480 | - offsets. */ | ||
| 481 | - for (i = 0; i < nops; i++) | ||
| 482 | - { | ||
| 483 | - rtx reg; | ||
| 484 | - rtx offset; | ||
| 485 | - | ||
| 486 | - /* Convert a subreg of a mem into the mem itself. */ | ||
| 487 | - if (GET_CODE (operands[nops + i]) == SUBREG) | ||
| 488 | - operands[nops + i] = alter_subreg (operands + (nops + i)); | ||
| 489 | - | ||
| 490 | - gcc_assert (GET_CODE (operands[nops + i]) == MEM); | ||
| 491 | - | ||
| 492 | - /* Don't reorder volatile memory references; it doesn't seem worth | ||
| 493 | - looking for the case where the order is ok anyway. */ | ||
| 494 | - if (MEM_VOLATILE_P (operands[nops + i])) | ||
| 495 | - return 0; | ||
| 496 | - | ||
| 497 | - offset = const0_rtx; | ||
| 498 | - | ||
| 499 | - if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | ||
| 500 | - || (GET_CODE (reg) == SUBREG | ||
| 501 | - && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | ||
| 502 | - || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | ||
| 503 | - && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | ||
| 504 | - == REG) | ||
| 505 | - || (GET_CODE (reg) == SUBREG | ||
| 506 | - && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | ||
| 507 | - && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | ||
| 508 | - == CONST_INT))) | ||
| 509 | - { | ||
| 510 | - if (i == 0) | ||
| 511 | - { | ||
| 512 | - base_reg = REGNO (reg); | ||
| 513 | - unsorted_regs[0] = (GET_CODE (operands[i]) == REG | ||
| 514 | - ? REGNO (operands[i]) | ||
| 515 | - : REGNO (SUBREG_REG (operands[i]))); | ||
| 516 | - order[0] = 0; | ||
| 517 | - } | ||
| 518 | - else | ||
| 519 | - { | ||
| 520 | - if (base_reg != (int) REGNO (reg)) | ||
| 521 | - /* Not addressed from the same base register. */ | ||
| 522 | - return 0; | ||
| 523 | - | ||
| 524 | - unsorted_regs[i] = (GET_CODE (operands[i]) == REG | ||
| 525 | - ? REGNO (operands[i]) | ||
| 526 | - : REGNO (SUBREG_REG (operands[i]))); | ||
| 527 | - if (unsorted_regs[i] < unsorted_regs[order[0]]) | ||
| 528 | - order[0] = i; | ||
| 529 | - } | ||
| 530 | - | ||
| 531 | - /* If it isn't an integer register, or if it overwrites the | ||
| 532 | - base register but isn't the last insn in the list, then | ||
| 533 | - we can't do this. */ | ||
| 534 | - if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 | ||
| 535 | - || (i != nops - 1 && unsorted_regs[i] == base_reg)) | ||
| 536 | - return 0; | ||
| 537 | - | ||
| 538 | - unsorted_offsets[i] = INTVAL (offset); | ||
| 539 | - } | ||
| 540 | - else | ||
| 541 | - /* Not a suitable memory address. */ | ||
| 542 | - return 0; | ||
| 543 | - } | ||
| 544 | - | ||
| 545 | - /* All the useful information has now been extracted from the | ||
| 546 | - operands into unsorted_regs and unsorted_offsets; additionally, | ||
| 547 | - order[0] has been set to the lowest numbered register in the | ||
| 548 | - list. Sort the registers into order, and check that the memory | ||
| 549 | - offsets are ascending and adjacent. */ | ||
| 550 | - | ||
| 551 | - for (i = 1; i < nops; i++) | ||
| 552 | - { | ||
| 553 | - int j; | ||
| 554 | - | ||
| 555 | - order[i] = order[i - 1]; | ||
| 556 | - for (j = 0; j < nops; j++) | ||
| 557 | - if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | ||
| 558 | - && (order[i] == order[i - 1] | ||
| 559 | - || unsorted_regs[j] < unsorted_regs[order[i]])) | ||
| 560 | - order[i] = j; | ||
| 561 | - | ||
| 562 | - /* Have we found a suitable register? if not, one must be used more | ||
| 563 | - than once. */ | ||
| 564 | - if (order[i] == order[i - 1]) | ||
| 565 | - return 0; | ||
| 566 | - | ||
| 567 | - /* Is the memory address adjacent and ascending? */ | ||
| 568 | - if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | ||
| 569 | - return 0; | ||
| 570 | - } | ||
| 571 | - | ||
| 572 | - if (base) | ||
| 573 | - { | ||
| 574 | - *base = base_reg; | ||
| 575 | - | ||
| 576 | - for (i = 0; i < nops; i++) | ||
| 577 | - regs[i] = unsorted_regs[order[i]]; | ||
| 578 | - | ||
| 579 | - *load_offset = unsorted_offsets[order[0]]; | ||
| 580 | - } | ||
| 581 | - | ||
| 582 | - if (unsorted_offsets[order[0]] == 0) | ||
| 583 | - return 1; /* ldmia */ | ||
| 584 | - | ||
| 585 | - if (TARGET_ARM && unsorted_offsets[order[0]] == 4) | ||
| 586 | - return 2; /* ldmib */ | ||
| 587 | - | ||
| 588 | - if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) | ||
| 589 | - return 3; /* ldmda */ | ||
| 590 | - | ||
| 591 | - if (unsorted_offsets[order[nops - 1]] == -4) | ||
| 592 | - return 4; /* ldmdb */ | ||
| 593 | - | ||
| 594 | + | ||
| 595 | +/* Return true iff it would be profitable to turn a sequence of NOPS loads | ||
| 596 | + or stores (depending on IS_STORE) into a load-multiple or store-multiple | ||
| 597 | + instruction. ADD_OFFSET is nonzero if the base address register needs | ||
| 598 | + to be modified with an add instruction before we can use it. */ | ||
| 599 | + | ||
| 600 | +static bool | ||
| 601 | +multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED, | ||
| 602 | + int nops, HOST_WIDE_INT add_offset) | ||
| 603 | + { | ||
| 604 | /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm | ||
| 605 | if the offset isn't small enough. The reason 2 ldrs are faster | ||
| 606 | is because these ARMs are able to do more than one cache access | ||
| 607 | @@ -9845,91 +9725,239 @@ | ||
| 608 | We cheat here and test 'arm_ld_sched' which we currently know to | ||
| 609 | only be true for the ARM8, ARM9 and StrongARM. If this ever | ||
| 610 | changes, then the test below needs to be reworked. */ | ||
| 611 | - if (nops == 2 && arm_ld_sched) | ||
| 612 | + if (nops == 2 && arm_ld_sched && add_offset != 0) | ||
| 613 | + return false; | ||
| 614 | + | ||
| 615 | + return true; | ||
| 616 | +} | ||
| 617 | + | ||
| 618 | +/* Subroutine of load_multiple_sequence and store_multiple_sequence. | ||
| 619 | + Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute | ||
| 620 | + an array ORDER which describes the sequence to use when accessing the | ||
| 621 | + offsets that produces an ascending order. In this sequence, each | ||
| 622 | + offset must be larger by exactly 4 than the previous one. ORDER[0] | ||
| 623 | + must have been filled in with the lowest offset by the caller. | ||
| 624 | + If UNSORTED_REGS is nonnull, it is an array of register numbers that | ||
| 625 | + we use to verify that ORDER produces an ascending order of registers. | ||
| 626 | + Return true if it was possible to construct such an order, false if | ||
| 627 | + not. */ | ||
| 628 | + | ||
| 629 | +static bool | ||
| 630 | +compute_offset_order (int nops, HOST_WIDE_INT *unsorted_offsets, int *order, | ||
| 631 | + int *unsorted_regs) | ||
| 632 | +{ | ||
| 633 | + int i; | ||
| 634 | + for (i = 1; i < nops; i++) | ||
| 635 | + { | ||
| 636 | + int j; | ||
| 637 | + | ||
| 638 | + order[i] = order[i - 1]; | ||
| 639 | + for (j = 0; j < nops; j++) | ||
| 640 | + if (unsorted_offsets[j] == unsorted_offsets[order[i - 1]] + 4) | ||
| 641 | + { | ||
| 642 | + /* We must find exactly one offset that is higher than the | ||
| 643 | + previous one by 4. */ | ||
| 644 | + if (order[i] != order[i - 1]) | ||
| 645 | + return false; | ||
| 646 | + order[i] = j; | ||
| 647 | + } | ||
| 648 | + if (order[i] == order[i - 1]) | ||
| 649 | + return false; | ||
| 650 | + /* The register numbers must be ascending. */ | ||
| 651 | + if (unsorted_regs != NULL | ||
| 652 | + && unsorted_regs[order[i]] <= unsorted_regs[order[i - 1]]) | ||
| 653 | + return false; | ||
| 654 | + } | ||
| 655 | + return true; | ||
| 656 | +} | ||
| 657 | + | ||
| 658 | +/* Used to determine in a peephole whether a sequence of load | ||
| 659 | + instructions can be changed into a load-multiple instruction. | ||
| 660 | + NOPS is the number of separate load instructions we are examining. The | ||
| 661 | + first NOPS entries in OPERANDS are the destination registers, the | ||
| 662 | + next NOPS entries are memory operands. If this function is | ||
| 663 | + successful, *BASE is set to the common base register of the memory | ||
| 664 | + accesses; *LOAD_OFFSET is set to the first memory location's offset | ||
| 665 | + from that base register. | ||
| 666 | + REGS is an array filled in with the destination register numbers. | ||
| 667 | + SAVED_ORDER (if nonnull), is an array filled in with an order that maps | ||
| 668 | + insn numbers to to an ascending order of stores. If CHECK_REGS is true, | ||
| 669 | + the sequence of registers in REGS matches the loads from ascending memory | ||
| 670 | + locations, and the function verifies that the register numbers are | ||
| 671 | + themselves ascending. If CHECK_REGS is false, the register numbers | ||
| 672 | + are stored in the order they are found in the operands. */ | ||
| 673 | +static int | ||
| 674 | +load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, | ||
| 675 | + int *base, HOST_WIDE_INT *load_offset, bool check_regs) | ||
| 676 | +{ | ||
| 677 | + int unsorted_regs[MAX_LDM_STM_OPS]; | ||
| 678 | + HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS]; | ||
| 679 | + int order[MAX_LDM_STM_OPS]; | ||
| 680 | + rtx base_reg_rtx = NULL; | ||
| 681 | + int base_reg = -1; | ||
| 682 | + int i, ldm_case; | ||
| 683 | + | ||
| 684 | + if (low_irq_latency) | ||
| 685 | return 0; | ||
| 686 | |||
| 687 | - /* Can't do it without setting up the offset, only do this if it takes | ||
| 688 | - no more than one insn. */ | ||
| 689 | - return (const_ok_for_arm (unsorted_offsets[order[0]]) | ||
| 690 | - || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; | ||
| 691 | -} | ||
| 692 | - | ||
| 693 | -const char * | ||
| 694 | -emit_ldm_seq (rtx *operands, int nops) | ||
| 695 | -{ | ||
| 696 | - int regs[4]; | ||
| 697 | - int base_reg; | ||
| 698 | - HOST_WIDE_INT offset; | ||
| 699 | - char buf[100]; | ||
| 700 | - int i; | ||
| 701 | - | ||
| 702 | - switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | ||
| 703 | + /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be | ||
| 704 | + easily extended if required. */ | ||
| 705 | + gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS); | ||
| 706 | + | ||
| 707 | + memset (order, 0, MAX_LDM_STM_OPS * sizeof (int)); | ||
| 708 | + | ||
| 709 | + /* Loop over the operands and check that the memory references are | ||
| 710 | + suitable (i.e. immediate offsets from the same base register). At | ||
| 711 | + the same time, extract the target register, and the memory | ||
| 712 | + offsets. */ | ||
| 713 | + for (i = 0; i < nops; i++) | ||
| 714 | { | ||
| 715 | - case 1: | ||
| 716 | - strcpy (buf, "ldm%(ia%)\t"); | ||
| 717 | - break; | ||
| 718 | - | ||
| 719 | - case 2: | ||
| 720 | - strcpy (buf, "ldm%(ib%)\t"); | ||
| 721 | - break; | ||
| 722 | - | ||
| 723 | - case 3: | ||
| 724 | - strcpy (buf, "ldm%(da%)\t"); | ||
| 725 | - break; | ||
| 726 | - | ||
| 727 | - case 4: | ||
| 728 | - strcpy (buf, "ldm%(db%)\t"); | ||
| 729 | - break; | ||
| 730 | - | ||
| 731 | - case 5: | ||
| 732 | - if (offset >= 0) | ||
| 733 | - sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | ||
| 734 | - reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | ||
| 735 | - (long) offset); | ||
| 736 | + rtx reg; | ||
| 737 | + rtx offset; | ||
| 738 | + | ||
| 739 | + /* Convert a subreg of a mem into the mem itself. */ | ||
| 740 | + if (GET_CODE (operands[nops + i]) == SUBREG) | ||
| 741 | + operands[nops + i] = alter_subreg (operands + (nops + i)); | ||
| 742 | + | ||
| 743 | + gcc_assert (GET_CODE (operands[nops + i]) == MEM); | ||
| 744 | + | ||
| 745 | + /* Don't reorder volatile memory references; it doesn't seem worth | ||
| 746 | + looking for the case where the order is ok anyway. */ | ||
| 747 | + if (MEM_VOLATILE_P (operands[nops + i])) | ||
| 748 | + return 0; | ||
| 749 | + | ||
| 750 | + offset = const0_rtx; | ||
| 751 | + | ||
| 752 | + if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | ||
| 753 | + || (GET_CODE (reg) == SUBREG | ||
| 754 | + && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | ||
| 755 | + || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | ||
| 756 | + && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | ||
| 757 | + == REG) | ||
| 758 | + || (GET_CODE (reg) == SUBREG | ||
| 759 | + && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | ||
| 760 | + && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | ||
| 761 | + == CONST_INT))) | ||
| 762 | + { | ||
| 763 | + if (i == 0) | ||
| 764 | + { | ||
| 765 | + base_reg = REGNO (reg); | ||
| 766 | + base_reg_rtx = reg; | ||
| 767 | + if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM) | ||
| 768 | + return 0; | ||
| 769 | + } | ||
| 770 | + else if (base_reg != (int) REGNO (reg)) | ||
| 771 | + /* Not addressed from the same base register. */ | ||
| 772 | + return 0; | ||
| 773 | + | ||
| 774 | + unsorted_regs[i] = (GET_CODE (operands[i]) == REG | ||
| 775 | + ? REGNO (operands[i]) | ||
| 776 | + : REGNO (SUBREG_REG (operands[i]))); | ||
| 777 | + | ||
| 778 | + /* If it isn't an integer register, or if it overwrites the | ||
| 779 | + base register but isn't the last insn in the list, then | ||
| 780 | + we can't do this. */ | ||
| 781 | + if (unsorted_regs[i] < 0 | ||
| 782 | + || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) | ||
| 783 | + || unsorted_regs[i] > 14 | ||
| 784 | + || (i != nops - 1 && unsorted_regs[i] == base_reg)) | ||
| 785 | + return 0; | ||
| 786 | + | ||
| 787 | + unsorted_offsets[i] = INTVAL (offset); | ||
| 788 | + if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) | ||
| 789 | + order[0] = i; | ||
| 790 | + } | ||
| 791 | else | ||
| 792 | - sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | ||
| 793 | - reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | ||
| 794 | - (long) -offset); | ||
| 795 | - output_asm_insn (buf, operands); | ||
| 796 | - base_reg = regs[0]; | ||
| 797 | - strcpy (buf, "ldm%(ia%)\t"); | ||
| 798 | - break; | ||
| 799 | - | ||
| 800 | - default: | ||
| 801 | - gcc_unreachable (); | ||
| 802 | - } | ||
| 803 | - | ||
| 804 | - sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, | ||
| 805 | - reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); | ||
| 806 | - | ||
| 807 | - for (i = 1; i < nops; i++) | ||
| 808 | - sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | ||
| 809 | - reg_names[regs[i]]); | ||
| 810 | - | ||
| 811 | - strcat (buf, "}\t%@ phole ldm"); | ||
| 812 | - | ||
| 813 | - output_asm_insn (buf, operands); | ||
| 814 | - return ""; | ||
| 815 | + /* Not a suitable memory address. */ | ||
| 816 | + return 0; | ||
| 817 | + } | ||
| 818 | + | ||
| 819 | + /* All the useful information has now been extracted from the | ||
| 820 | + operands into unsorted_regs and unsorted_offsets; additionally, | ||
| 821 | + order[0] has been set to the lowest offset in the list. Sort | ||
| 822 | + the offsets into order, verifying that they are adjacent, and | ||
| 823 | + check that the register numbers are ascending. */ | ||
| 824 | + if (!compute_offset_order (nops, unsorted_offsets, order, | ||
| 825 | + check_regs ? unsorted_regs : NULL)) | ||
| 826 | + return 0; | ||
| 827 | + | ||
| 828 | + if (saved_order) | ||
| 829 | + memcpy (saved_order, order, sizeof order); | ||
| 830 | + | ||
| 831 | + if (base) | ||
| 832 | + { | ||
| 833 | + *base = base_reg; | ||
| 834 | + | ||
| 835 | + for (i = 0; i < nops; i++) | ||
| 836 | + regs[i] = unsorted_regs[check_regs ? order[i] : i]; | ||
| 837 | + | ||
| 838 | + *load_offset = unsorted_offsets[order[0]]; | ||
| 839 | + } | ||
| 840 | + | ||
| 841 | + if (TARGET_THUMB1 | ||
| 842 | + && !peep2_reg_dead_p (nops, base_reg_rtx)) | ||
| 843 | + return 0; | ||
| 844 | + | ||
| 845 | + if (unsorted_offsets[order[0]] == 0) | ||
| 846 | + ldm_case = 1; /* ldmia */ | ||
| 847 | + else if (TARGET_ARM && unsorted_offsets[order[0]] == 4) | ||
| 848 | + ldm_case = 2; /* ldmib */ | ||
| 849 | + else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) | ||
| 850 | + ldm_case = 3; /* ldmda */ | ||
| 851 | + else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4) | ||
| 852 | + ldm_case = 4; /* ldmdb */ | ||
| 853 | + else if (const_ok_for_arm (unsorted_offsets[order[0]]) | ||
| 854 | + || const_ok_for_arm (-unsorted_offsets[order[0]])) | ||
| 855 | + ldm_case = 5; | ||
| 856 | + else | ||
| 857 | + return 0; | ||
| 858 | + | ||
| 859 | + if (!multiple_operation_profitable_p (false, nops, | ||
| 860 | + ldm_case == 5 | ||
| 861 | + ? unsorted_offsets[order[0]] : 0)) | ||
| 862 | + return 0; | ||
| 863 | + | ||
| 864 | + return ldm_case; | ||
| 865 | } | ||
| 866 | |||
| 867 | -int | ||
| 868 | -store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, | ||
| 869 | - HOST_WIDE_INT * load_offset) | ||
| 870 | +/* Used to determine in a peephole whether a sequence of store instructions can | ||
| 871 | + be changed into a store-multiple instruction. | ||
| 872 | + NOPS is the number of separate store instructions we are examining. | ||
| 873 | + NOPS_TOTAL is the total number of instructions recognized by the peephole | ||
| 874 | + pattern. | ||
| 875 | + The first NOPS entries in OPERANDS are the source registers, the next | ||
| 876 | + NOPS entries are memory operands. If this function is successful, *BASE is | ||
| 877 | + set to the common base register of the memory accesses; *LOAD_OFFSET is set | ||
| 878 | + to the first memory location's offset from that base register. REGS is an | ||
| 879 | + array filled in with the source register numbers, REG_RTXS (if nonnull) is | ||
| 880 | + likewise filled with the corresponding rtx's. | ||
| 881 | + SAVED_ORDER (if nonnull), is an array filled in with an order that maps insn | ||
| 882 | + numbers to to an ascending order of stores. | ||
| 883 | + If CHECK_REGS is true, the sequence of registers in *REGS matches the stores | ||
| 884 | + from ascending memory locations, and the function verifies that the register | ||
| 885 | + numbers are themselves ascending. If CHECK_REGS is false, the register | ||
| 886 | + numbers are stored in the order they are found in the operands. */ | ||
| 887 | +static int | ||
| 888 | +store_multiple_sequence (rtx *operands, int nops, int nops_total, | ||
| 889 | + int *regs, rtx *reg_rtxs, int *saved_order, int *base, | ||
| 890 | + HOST_WIDE_INT *load_offset, bool check_regs) | ||
| 891 | { | ||
| 892 | - int unsorted_regs[4]; | ||
| 893 | - HOST_WIDE_INT unsorted_offsets[4]; | ||
| 894 | - int order[4]; | ||
| 895 | + int unsorted_regs[MAX_LDM_STM_OPS]; | ||
| 896 | + rtx unsorted_reg_rtxs[MAX_LDM_STM_OPS]; | ||
| 897 | + HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS]; | ||
| 898 | + int order[MAX_LDM_STM_OPS]; | ||
| 899 | int base_reg = -1; | ||
| 900 | - int i; | ||
| 901 | + rtx base_reg_rtx = NULL; | ||
| 902 | + int i, stm_case; | ||
| 903 | |||
| 904 | if (low_irq_latency) | ||
| 905 | return 0; | ||
| 906 | |||
| 907 | - /* Can only handle 2, 3, or 4 insns at present, though could be easily | ||
| 908 | - extended if required. */ | ||
| 909 | - gcc_assert (nops >= 2 && nops <= 4); | ||
| 910 | + /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be | ||
| 911 | + easily extended if required. */ | ||
| 912 | + gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS); | ||
| 913 | |||
| 914 | - memset (order, 0, 4 * sizeof (int)); | ||
| 915 | + memset (order, 0, MAX_LDM_STM_OPS * sizeof (int)); | ||
| 916 | |||
| 917 | /* Loop over the operands and check that the memory references are | ||
| 918 | suitable (i.e. immediate offsets from the same base register). At | ||
| 919 | @@ -9964,32 +9992,32 @@ | ||
| 920 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | ||
| 921 | == CONST_INT))) | ||
| 922 | { | ||
| 923 | + unsorted_reg_rtxs[i] = (GET_CODE (operands[i]) == REG | ||
| 924 | + ? operands[i] : SUBREG_REG (operands[i])); | ||
| 925 | + unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]); | ||
| 926 | + | ||
| 927 | if (i == 0) | ||
| 928 | { | ||
| 929 | base_reg = REGNO (reg); | ||
| 930 | - unsorted_regs[0] = (GET_CODE (operands[i]) == REG | ||
| 931 | - ? REGNO (operands[i]) | ||
| 932 | - : REGNO (SUBREG_REG (operands[i]))); | ||
| 933 | - order[0] = 0; | ||
| 934 | - } | ||
| 935 | - else | ||
| 936 | - { | ||
| 937 | - if (base_reg != (int) REGNO (reg)) | ||
| 938 | - /* Not addressed from the same base register. */ | ||
| 939 | + base_reg_rtx = reg; | ||
| 940 | + if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM) | ||
| 941 | return 0; | ||
| 942 | - | ||
| 943 | - unsorted_regs[i] = (GET_CODE (operands[i]) == REG | ||
| 944 | - ? REGNO (operands[i]) | ||
| 945 | - : REGNO (SUBREG_REG (operands[i]))); | ||
| 946 | - if (unsorted_regs[i] < unsorted_regs[order[0]]) | ||
| 947 | - order[0] = i; | ||
| 948 | } | ||
| 949 | + else if (base_reg != (int) REGNO (reg)) | ||
| 950 | + /* Not addressed from the same base register. */ | ||
| 951 | + return 0; | ||
| 952 | |||
| 953 | /* If it isn't an integer register, then we can't do this. */ | ||
| 954 | - if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) | ||
| 955 | + if (unsorted_regs[i] < 0 | ||
| 956 | + || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) | ||
| 957 | + || (TARGET_THUMB2 && unsorted_regs[i] == base_reg) | ||
| 958 | + || (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM) | ||
| 959 | + || unsorted_regs[i] > 14) | ||
| 960 | return 0; | ||
| 961 | |||
| 962 | unsorted_offsets[i] = INTVAL (offset); | ||
| 963 | + if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) | ||
| 964 | + order[0] = i; | ||
| 965 | } | ||
| 966 | else | ||
| 967 | /* Not a suitable memory address. */ | ||
| 968 | @@ -9998,111 +10026,65 @@ | ||
| 969 | |||
| 970 | /* All the useful information has now been extracted from the | ||
| 971 | operands into unsorted_regs and unsorted_offsets; additionally, | ||
| 972 | - order[0] has been set to the lowest numbered register in the | ||
| 973 | - list. Sort the registers into order, and check that the memory | ||
| 974 | - offsets are ascending and adjacent. */ | ||
| 975 | - | ||
| 976 | - for (i = 1; i < nops; i++) | ||
| 977 | - { | ||
| 978 | - int j; | ||
| 979 | - | ||
| 980 | - order[i] = order[i - 1]; | ||
| 981 | - for (j = 0; j < nops; j++) | ||
| 982 | - if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | ||
| 983 | - && (order[i] == order[i - 1] | ||
| 984 | - || unsorted_regs[j] < unsorted_regs[order[i]])) | ||
| 985 | - order[i] = j; | ||
| 986 | - | ||
| 987 | - /* Have we found a suitable register? if not, one must be used more | ||
| 988 | - than once. */ | ||
| 989 | - if (order[i] == order[i - 1]) | ||
| 990 | - return 0; | ||
| 991 | - | ||
| 992 | - /* Is the memory address adjacent and ascending? */ | ||
| 993 | - if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | ||
| 994 | - return 0; | ||
| 995 | - } | ||
| 996 | + order[0] has been set to the lowest offset in the list. Sort | ||
| 997 | + the offsets into order, verifying that they are adjacent, and | ||
| 998 | + check that the register numbers are ascending. */ | ||
| 999 | + if (!compute_offset_order (nops, unsorted_offsets, order, | ||
| 1000 | + check_regs ? unsorted_regs : NULL)) | ||
| 1001 | + return 0; | ||
| 1002 | + | ||
| 1003 | + if (saved_order) | ||
| 1004 | + memcpy (saved_order, order, sizeof order); | ||
| 1005 | |||
| 1006 | if (base) | ||
| 1007 | { | ||
| 1008 | *base = base_reg; | ||
| 1009 | |||
| 1010 | for (i = 0; i < nops; i++) | ||
| 1011 | - regs[i] = unsorted_regs[order[i]]; | ||
| 1012 | + { | ||
| 1013 | + regs[i] = unsorted_regs[check_regs ? order[i] : i]; | ||
| 1014 | + if (reg_rtxs) | ||
| 1015 | + reg_rtxs[i] = unsorted_reg_rtxs[check_regs ? order[i] : i]; | ||
| 1016 | + } | ||
| 1017 | |||
| 1018 | *load_offset = unsorted_offsets[order[0]]; | ||
| 1019 | } | ||
| 1020 | |||
| 1021 | + if (TARGET_THUMB1 | ||
| 1022 | + && !peep2_reg_dead_p (nops_total, base_reg_rtx)) | ||
| 1023 | + return 0; | ||
| 1024 | + | ||
| 1025 | if (unsorted_offsets[order[0]] == 0) | ||
| 1026 | - return 1; /* stmia */ | ||
| 1027 | - | ||
| 1028 | - if (unsorted_offsets[order[0]] == 4) | ||
| 1029 | - return 2; /* stmib */ | ||
| 1030 | - | ||
| 1031 | - if (unsorted_offsets[order[nops - 1]] == 0) | ||
| 1032 | - return 3; /* stmda */ | ||
| 1033 | - | ||
| 1034 | - if (unsorted_offsets[order[nops - 1]] == -4) | ||
| 1035 | - return 4; /* stmdb */ | ||
| 1036 | - | ||
| 1037 | - return 0; | ||
| 1038 | -} | ||
| 1039 | - | ||
| 1040 | -const char * | ||
| 1041 | -emit_stm_seq (rtx *operands, int nops) | ||
| 1042 | -{ | ||
| 1043 | - int regs[4]; | ||
| 1044 | - int base_reg; | ||
| 1045 | - HOST_WIDE_INT offset; | ||
| 1046 | - char buf[100]; | ||
| 1047 | - int i; | ||
| 1048 | - | ||
| 1049 | - switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | ||
| 1050 | - { | ||
| 1051 | - case 1: | ||
| 1052 | - strcpy (buf, "stm%(ia%)\t"); | ||
| 1053 | - break; | ||
| 1054 | - | ||
| 1055 | - case 2: | ||
| 1056 | - strcpy (buf, "stm%(ib%)\t"); | ||
| 1057 | - break; | ||
| 1058 | - | ||
| 1059 | - case 3: | ||
| 1060 | - strcpy (buf, "stm%(da%)\t"); | ||
| 1061 | - break; | ||
| 1062 | - | ||
| 1063 | - case 4: | ||
| 1064 | - strcpy (buf, "stm%(db%)\t"); | ||
| 1065 | - break; | ||
| 1066 | - | ||
| 1067 | - default: | ||
| 1068 | - gcc_unreachable (); | ||
| 1069 | - } | ||
| 1070 | - | ||
| 1071 | - sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, | ||
| 1072 | - reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); | ||
| 1073 | - | ||
| 1074 | - for (i = 1; i < nops; i++) | ||
| 1075 | - sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | ||
| 1076 | - reg_names[regs[i]]); | ||
| 1077 | - | ||
| 1078 | - strcat (buf, "}\t%@ phole stm"); | ||
| 1079 | - | ||
| 1080 | - output_asm_insn (buf, operands); | ||
| 1081 | - return ""; | ||
| 1082 | + stm_case = 1; /* stmia */ | ||
| 1083 | + else if (TARGET_ARM && unsorted_offsets[order[0]] == 4) | ||
| 1084 | + stm_case = 2; /* stmib */ | ||
| 1085 | + else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) | ||
| 1086 | + stm_case = 3; /* stmda */ | ||
| 1087 | + else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4) | ||
| 1088 | + stm_case = 4; /* stmdb */ | ||
| 1089 | + else | ||
| 1090 | + return 0; | ||
| 1091 | + | ||
| 1092 | + if (!multiple_operation_profitable_p (false, nops, 0)) | ||
| 1093 | + return 0; | ||
| 1094 | + | ||
| 1095 | + return stm_case; | ||
| 1096 | } | ||
| 1097 | |||
| 1098 | /* Routines for use in generating RTL. */ | ||
| 1099 | |||
| 1100 | -rtx | ||
| 1101 | -arm_gen_load_multiple (int base_regno, int count, rtx from, int up, | ||
| 1102 | - int write_back, rtx basemem, HOST_WIDE_INT *offsetp) | ||
| 1103 | +/* Generate a load-multiple instruction. COUNT is the number of loads in | ||
| 1104 | + the instruction; REGS and MEMS are arrays containing the operands. | ||
| 1105 | + BASEREG is the base register to be used in addressing the memory operands. | ||
| 1106 | + WBACK_OFFSET is nonzero if the instruction should update the base | ||
| 1107 | + register. */ | ||
| 1108 | + | ||
| 1109 | +static rtx | ||
| 1110 | +arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, | ||
| 1111 | + HOST_WIDE_INT wback_offset) | ||
| 1112 | { | ||
| 1113 | - HOST_WIDE_INT offset = *offsetp; | ||
| 1114 | int i = 0, j; | ||
| 1115 | rtx result; | ||
| 1116 | - int sign = up ? 1 : -1; | ||
| 1117 | - rtx mem, addr; | ||
| 1118 | |||
| 1119 | /* XScale has load-store double instructions, but they have stricter | ||
| 1120 | alignment requirements than load-store multiple, so we cannot | ||
| 1121 | @@ -10139,18 +10121,10 @@ | ||
| 1122 | start_sequence (); | ||
| 1123 | |||
| 1124 | for (i = 0; i < count; i++) | ||
| 1125 | - { | ||
| 1126 | - addr = plus_constant (from, i * 4 * sign); | ||
| 1127 | - mem = adjust_automodify_address (basemem, SImode, addr, offset); | ||
| 1128 | - emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); | ||
| 1129 | - offset += 4 * sign; | ||
| 1130 | - } | ||
| 1131 | + emit_move_insn (gen_rtx_REG (SImode, regs[i]), mems[i]); | ||
| 1132 | |||
| 1133 | - if (write_back) | ||
| 1134 | - { | ||
| 1135 | - emit_move_insn (from, plus_constant (from, count * 4 * sign)); | ||
| 1136 | - *offsetp = offset; | ||
| 1137 | - } | ||
| 1138 | + if (wback_offset != 0) | ||
| 1139 | + emit_move_insn (basereg, plus_constant (basereg, wback_offset)); | ||
| 1140 | |||
| 1141 | seq = get_insns (); | ||
| 1142 | end_sequence (); | ||
| 1143 | @@ -10159,41 +10133,40 @@ | ||
| 1144 | } | ||
| 1145 | |||
| 1146 | result = gen_rtx_PARALLEL (VOIDmode, | ||
| 1147 | - rtvec_alloc (count + (write_back ? 1 : 0))); | ||
| 1148 | - if (write_back) | ||
| 1149 | + rtvec_alloc (count + (wback_offset != 0 ? 1 : 0))); | ||
| 1150 | + if (wback_offset != 0) | ||
| 1151 | { | ||
| 1152 | XVECEXP (result, 0, 0) | ||
| 1153 | - = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign)); | ||
| 1154 | + = gen_rtx_SET (VOIDmode, basereg, | ||
| 1155 | + plus_constant (basereg, wback_offset)); | ||
| 1156 | i = 1; | ||
| 1157 | count++; | ||
| 1158 | } | ||
| 1159 | |||
| 1160 | for (j = 0; i < count; i++, j++) | ||
| 1161 | - { | ||
| 1162 | - addr = plus_constant (from, j * 4 * sign); | ||
| 1163 | - mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); | ||
| 1164 | - XVECEXP (result, 0, i) | ||
| 1165 | - = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); | ||
| 1166 | - offset += 4 * sign; | ||
| 1167 | - } | ||
| 1168 | - | ||
| 1169 | - if (write_back) | ||
| 1170 | - *offsetp = offset; | ||
| 1171 | + XVECEXP (result, 0, i) | ||
| 1172 | + = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regs[j]), mems[j]); | ||
| 1173 | |||
| 1174 | return result; | ||
| 1175 | } | ||
| 1176 | |||
| 1177 | -rtx | ||
| 1178 | -arm_gen_store_multiple (int base_regno, int count, rtx to, int up, | ||
| 1179 | - int write_back, rtx basemem, HOST_WIDE_INT *offsetp) | ||
| 1180 | +/* Generate a store-multiple instruction. COUNT is the number of stores in | ||
| 1181 | + the instruction; REGS and MEMS are arrays containing the operands. | ||
| 1182 | + BASEREG is the base register to be used in addressing the memory operands. | ||
| 1183 | + WBACK_OFFSET is nonzero if the instruction should update the base | ||
| 1184 | + register. */ | ||
| 1185 | + | ||
| 1186 | +static rtx | ||
| 1187 | +arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, | ||
| 1188 | + HOST_WIDE_INT wback_offset) | ||
| 1189 | { | ||
| 1190 | - HOST_WIDE_INT offset = *offsetp; | ||
| 1191 | int i = 0, j; | ||
| 1192 | rtx result; | ||
| 1193 | - int sign = up ? 1 : -1; | ||
| 1194 | - rtx mem, addr; | ||
| 1195 | - | ||
| 1196 | - /* See arm_gen_load_multiple for discussion of | ||
| 1197 | + | ||
| 1198 | + if (GET_CODE (basereg) == PLUS) | ||
| 1199 | + basereg = XEXP (basereg, 0); | ||
| 1200 | + | ||
| 1201 | + /* See arm_gen_load_multiple_1 for discussion of | ||
| 1202 | the pros/cons of ldm/stm usage for XScale. */ | ||
| 1203 | if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size)) | ||
| 1204 | { | ||
| 1205 | @@ -10202,18 +10175,10 @@ | ||
| 1206 | start_sequence (); | ||
| 1207 | |||
| 1208 | for (i = 0; i < count; i++) | ||
| 1209 | - { | ||
| 1210 | - addr = plus_constant (to, i * 4 * sign); | ||
| 1211 | - mem = adjust_automodify_address (basemem, SImode, addr, offset); | ||
| 1212 | - emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); | ||
| 1213 | - offset += 4 * sign; | ||
| 1214 | - } | ||
| 1215 | + emit_move_insn (mems[i], gen_rtx_REG (SImode, regs[i])); | ||
| 1216 | |||
| 1217 | - if (write_back) | ||
| 1218 | - { | ||
| 1219 | - emit_move_insn (to, plus_constant (to, count * 4 * sign)); | ||
| 1220 | - *offsetp = offset; | ||
| 1221 | - } | ||
| 1222 | + if (wback_offset != 0) | ||
| 1223 | + emit_move_insn (basereg, plus_constant (basereg, wback_offset)); | ||
| 1224 | |||
| 1225 | seq = get_insns (); | ||
| 1226 | end_sequence (); | ||
| 1227 | @@ -10222,29 +10187,319 @@ | ||
| 1228 | } | ||
| 1229 | |||
| 1230 | result = gen_rtx_PARALLEL (VOIDmode, | ||
| 1231 | - rtvec_alloc (count + (write_back ? 1 : 0))); | ||
| 1232 | - if (write_back) | ||
| 1233 | + rtvec_alloc (count + (wback_offset != 0 ? 1 : 0))); | ||
| 1234 | + if (wback_offset != 0) | ||
| 1235 | { | ||
| 1236 | XVECEXP (result, 0, 0) | ||
| 1237 | - = gen_rtx_SET (VOIDmode, to, | ||
| 1238 | - plus_constant (to, count * 4 * sign)); | ||
| 1239 | + = gen_rtx_SET (VOIDmode, basereg, | ||
| 1240 | + plus_constant (basereg, wback_offset)); | ||
| 1241 | i = 1; | ||
| 1242 | count++; | ||
| 1243 | } | ||
| 1244 | |||
| 1245 | for (j = 0; i < count; i++, j++) | ||
| 1246 | + XVECEXP (result, 0, i) | ||
| 1247 | + = gen_rtx_SET (VOIDmode, mems[j], gen_rtx_REG (SImode, regs[j])); | ||
| 1248 | + | ||
| 1249 | + return result; | ||
| 1250 | +} | ||
| 1251 | + | ||
| 1252 | +/* Generate either a load-multiple or a store-multiple instruction. This | ||
| 1253 | + function can be used in situations where we can start with a single MEM | ||
| 1254 | + rtx and adjust its address upwards. | ||
| 1255 | + COUNT is the number of operations in the instruction, not counting a | ||
| 1256 | + possible update of the base register. REGS is an array containing the | ||
| 1257 | + register operands. | ||
| 1258 | + BASEREG is the base register to be used in addressing the memory operands, | ||
| 1259 | + which are constructed from BASEMEM. | ||
| 1260 | + WRITE_BACK specifies whether the generated instruction should include an | ||
| 1261 | + update of the base register. | ||
| 1262 | + OFFSETP is used to pass an offset to and from this function; this offset | ||
| 1263 | + is not used when constructing the address (instead BASEMEM should have an | ||
| 1264 | + appropriate offset in its address), it is used only for setting | ||
| 1265 | + MEM_OFFSET. It is updated only if WRITE_BACK is true.*/ | ||
| 1266 | + | ||
| 1267 | +static rtx | ||
| 1268 | +arm_gen_multiple_op (bool is_load, int *regs, int count, rtx basereg, | ||
| 1269 | + bool write_back, rtx basemem, HOST_WIDE_INT *offsetp) | ||
| 1270 | +{ | ||
| 1271 | + rtx mems[MAX_LDM_STM_OPS]; | ||
| 1272 | + HOST_WIDE_INT offset = *offsetp; | ||
| 1273 | + int i; | ||
| 1274 | + | ||
| 1275 | + gcc_assert (count <= MAX_LDM_STM_OPS); | ||
| 1276 | + | ||
| 1277 | + if (GET_CODE (basereg) == PLUS) | ||
| 1278 | + basereg = XEXP (basereg, 0); | ||
| 1279 | + | ||
| 1280 | + for (i = 0; i < count; i++) | ||
| 1281 | { | ||
| 1282 | - addr = plus_constant (to, j * 4 * sign); | ||
| 1283 | - mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); | ||
| 1284 | - XVECEXP (result, 0, i) | ||
| 1285 | - = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); | ||
| 1286 | - offset += 4 * sign; | ||
| 1287 | + rtx addr = plus_constant (basereg, i * 4); | ||
| 1288 | + mems[i] = adjust_automodify_address_nv (basemem, SImode, addr, offset); | ||
| 1289 | + offset += 4; | ||
| 1290 | } | ||
| 1291 | |||
| 1292 | if (write_back) | ||
| 1293 | *offsetp = offset; | ||
| 1294 | |||
| 1295 | - return result; | ||
| 1296 | + if (is_load) | ||
| 1297 | + return arm_gen_load_multiple_1 (count, regs, mems, basereg, | ||
| 1298 | + write_back ? 4 * count : 0); | ||
| 1299 | + else | ||
| 1300 | + return arm_gen_store_multiple_1 (count, regs, mems, basereg, | ||
| 1301 | + write_back ? 4 * count : 0); | ||
| 1302 | +} | ||
| 1303 | + | ||
| 1304 | +rtx | ||
| 1305 | +arm_gen_load_multiple (int *regs, int count, rtx basereg, int write_back, | ||
| 1306 | + rtx basemem, HOST_WIDE_INT *offsetp) | ||
| 1307 | +{ | ||
| 1308 | + return arm_gen_multiple_op (TRUE, regs, count, basereg, write_back, basemem, | ||
| 1309 | + offsetp); | ||
| 1310 | +} | ||
| 1311 | + | ||
| 1312 | +rtx | ||
| 1313 | +arm_gen_store_multiple (int *regs, int count, rtx basereg, int write_back, | ||
| 1314 | + rtx basemem, HOST_WIDE_INT *offsetp) | ||
| 1315 | +{ | ||
| 1316 | + return arm_gen_multiple_op (FALSE, regs, count, basereg, write_back, basemem, | ||
| 1317 | + offsetp); | ||
| 1318 | +} | ||
| 1319 | + | ||
| 1320 | +/* Called from a peephole2 expander to turn a sequence of loads into an | ||
| 1321 | + LDM instruction. OPERANDS are the operands found by the peephole matcher; | ||
| 1322 | + NOPS indicates how many separate loads we are trying to combine. SORT_REGS | ||
| 1323 | + is true if we can reorder the registers because they are used commutatively | ||
| 1324 | + subsequently. | ||
| 1325 | + Returns true iff we could generate a new instruction. */ | ||
| 1326 | + | ||
| 1327 | +bool | ||
| 1328 | +gen_ldm_seq (rtx *operands, int nops, bool sort_regs) | ||
| 1329 | +{ | ||
| 1330 | + int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; | ||
| 1331 | + rtx mems[MAX_LDM_STM_OPS]; | ||
| 1332 | + int i, j, base_reg; | ||
| 1333 | + rtx base_reg_rtx; | ||
| 1334 | + HOST_WIDE_INT offset; | ||
| 1335 | + int write_back = FALSE; | ||
| 1336 | + int ldm_case; | ||
| 1337 | + rtx addr; | ||
| 1338 | + | ||
| 1339 | + ldm_case = load_multiple_sequence (operands, nops, regs, mem_order, | ||
| 1340 | + &base_reg, &offset, !sort_regs); | ||
| 1341 | + | ||
| 1342 | + if (ldm_case == 0) | ||
| 1343 | + return false; | ||
| 1344 | + | ||
| 1345 | + if (sort_regs) | ||
| 1346 | + for (i = 0; i < nops - 1; i++) | ||
| 1347 | + for (j = i + 1; j < nops; j++) | ||
| 1348 | + if (regs[i] > regs[j]) | ||
| 1349 | + { | ||
| 1350 | + int t = regs[i]; | ||
| 1351 | + regs[i] = regs[j]; | ||
| 1352 | + regs[j] = t; | ||
| 1353 | + } | ||
| 1354 | + base_reg_rtx = gen_rtx_REG (Pmode, base_reg); | ||
| 1355 | + | ||
| 1356 | + if (TARGET_THUMB1) | ||
| 1357 | + { | ||
| 1358 | + gcc_assert (peep2_reg_dead_p (nops, base_reg_rtx)); | ||
| 1359 | + gcc_assert (ldm_case == 1 || ldm_case == 5); | ||
| 1360 | + write_back = TRUE; | ||
| 1361 | + } | ||
| 1362 | + | ||
| 1363 | + if (ldm_case == 5) | ||
| 1364 | + { | ||
| 1365 | + rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG (SImode, regs[0]); | ||
| 1366 | + emit_insn (gen_addsi3 (newbase, base_reg_rtx, GEN_INT (offset))); | ||
| 1367 | + offset = 0; | ||
| 1368 | + if (!TARGET_THUMB1) | ||
| 1369 | + { | ||
| 1370 | + base_reg = regs[0]; | ||
| 1371 | + base_reg_rtx = newbase; | ||
| 1372 | + } | ||
| 1373 | + } | ||
| 1374 | + | ||
| 1375 | + for (i = 0; i < nops; i++) | ||
| 1376 | + { | ||
| 1377 | + addr = plus_constant (base_reg_rtx, offset + i * 4); | ||
| 1378 | + mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], | ||
| 1379 | + SImode, addr, 0); | ||
| 1380 | + } | ||
| 1381 | + emit_insn (arm_gen_load_multiple_1 (nops, regs, mems, base_reg_rtx, | ||
| 1382 | + write_back ? offset + i * 4 : 0)); | ||
| 1383 | + return true; | ||
| 1384 | +} | ||
| 1385 | + | ||
| 1386 | +/* Called from a peephole2 expander to turn a sequence of stores into an | ||
| 1387 | + STM instruction. OPERANDS are the operands found by the peephole matcher; | ||
| 1388 | + NOPS indicates how many separate stores we are trying to combine. | ||
| 1389 | + Returns true iff we could generate a new instruction. */ | ||
| 1390 | + | ||
| 1391 | +bool | ||
| 1392 | +gen_stm_seq (rtx *operands, int nops) | ||
| 1393 | +{ | ||
| 1394 | + int i; | ||
| 1395 | + int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; | ||
| 1396 | + rtx mems[MAX_LDM_STM_OPS]; | ||
| 1397 | + int base_reg; | ||
| 1398 | + rtx base_reg_rtx; | ||
| 1399 | + HOST_WIDE_INT offset; | ||
| 1400 | + int write_back = FALSE; | ||
| 1401 | + int stm_case; | ||
| 1402 | + rtx addr; | ||
| 1403 | + bool base_reg_dies; | ||
| 1404 | + | ||
| 1405 | + stm_case = store_multiple_sequence (operands, nops, nops, regs, NULL, | ||
| 1406 | + mem_order, &base_reg, &offset, true); | ||
| 1407 | + | ||
| 1408 | + if (stm_case == 0) | ||
| 1409 | + return false; | ||
| 1410 | + | ||
| 1411 | + base_reg_rtx = gen_rtx_REG (Pmode, base_reg); | ||
| 1412 | + | ||
| 1413 | + base_reg_dies = peep2_reg_dead_p (nops, base_reg_rtx); | ||
| 1414 | + if (TARGET_THUMB1) | ||
| 1415 | + { | ||
| 1416 | + gcc_assert (base_reg_dies); | ||
| 1417 | + write_back = TRUE; | ||
| 1418 | + } | ||
| 1419 | + | ||
| 1420 | + if (stm_case == 5) | ||
| 1421 | + { | ||
| 1422 | + gcc_assert (base_reg_dies); | ||
| 1423 | + emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset))); | ||
| 1424 | + offset = 0; | ||
| 1425 | + } | ||
| 1426 | + | ||
| 1427 | + addr = plus_constant (base_reg_rtx, offset); | ||
| 1428 | + | ||
| 1429 | + for (i = 0; i < nops; i++) | ||
| 1430 | + { | ||
| 1431 | + addr = plus_constant (base_reg_rtx, offset + i * 4); | ||
| 1432 | + mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], | ||
| 1433 | + SImode, addr, 0); | ||
| 1434 | + } | ||
| 1435 | + emit_insn (arm_gen_store_multiple_1 (nops, regs, mems, base_reg_rtx, | ||
| 1436 | + write_back ? offset + i * 4 : 0)); | ||
| 1437 | + return true; | ||
| 1438 | +} | ||
| 1439 | + | ||
| 1440 | +/* Called from a peephole2 expander to turn a sequence of stores that are | ||
| 1441 | + preceded by constant loads into an STM instruction. OPERANDS are the | ||
| 1442 | + operands found by the peephole matcher; NOPS indicates how many | ||
| 1443 | + separate stores we are trying to combine; there are 2 * NOPS | ||
| 1444 | + instructions in the peephole. | ||
| 1445 | + Returns true iff we could generate a new instruction. */ | ||
| 1446 | + | ||
| 1447 | +bool | ||
| 1448 | +gen_const_stm_seq (rtx *operands, int nops) | ||
| 1449 | +{ | ||
| 1450 | + int regs[MAX_LDM_STM_OPS], sorted_regs[MAX_LDM_STM_OPS]; | ||
| 1451 | + int reg_order[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; | ||
| 1452 | + rtx reg_rtxs[MAX_LDM_STM_OPS], orig_reg_rtxs[MAX_LDM_STM_OPS]; | ||
| 1453 | + rtx mems[MAX_LDM_STM_OPS]; | ||
| 1454 | + int base_reg; | ||
| 1455 | + rtx base_reg_rtx; | ||
| 1456 | + HOST_WIDE_INT offset; | ||
| 1457 | + int write_back = FALSE; | ||
| 1458 | + int stm_case; | ||
| 1459 | + rtx addr; | ||
| 1460 | + bool base_reg_dies; | ||
| 1461 | + int i, j; | ||
| 1462 | + HARD_REG_SET allocated; | ||
| 1463 | + | ||
| 1464 | + stm_case = store_multiple_sequence (operands, nops, 2 * nops, regs, reg_rtxs, | ||
| 1465 | + mem_order, &base_reg, &offset, false); | ||
| 1466 | + | ||
| 1467 | + if (stm_case == 0) | ||
| 1468 | + return false; | ||
| 1469 | + | ||
| 1470 | + memcpy (orig_reg_rtxs, reg_rtxs, sizeof orig_reg_rtxs); | ||
| 1471 | + | ||
| 1472 | + /* If the same register is used more than once, try to find a free | ||
| 1473 | + register. */ | ||
| 1474 | + CLEAR_HARD_REG_SET (allocated); | ||
| 1475 | + for (i = 0; i < nops; i++) | ||
| 1476 | + { | ||
| 1477 | + for (j = i + 1; j < nops; j++) | ||
| 1478 | + if (regs[i] == regs[j]) | ||
| 1479 | + { | ||
| 1480 | + rtx t = peep2_find_free_register (0, nops * 2, | ||
| 1481 | + TARGET_THUMB1 ? "l" : "r", | ||
| 1482 | + SImode, &allocated); | ||
| 1483 | + if (t == NULL_RTX) | ||
| 1484 | + return false; | ||
| 1485 | + reg_rtxs[i] = t; | ||
| 1486 | + regs[i] = REGNO (t); | ||
| 1487 | + } | ||
| 1488 | + } | ||
| 1489 | + | ||
| 1490 | + /* Compute an ordering that maps the register numbers to an ascending | ||
| 1491 | + sequence. */ | ||
| 1492 | + reg_order[0] = 0; | ||
| 1493 | + for (i = 0; i < nops; i++) | ||
| 1494 | + if (regs[i] < regs[reg_order[0]]) | ||
| 1495 | + reg_order[0] = i; | ||
| 1496 | + | ||
| 1497 | + for (i = 1; i < nops; i++) | ||
| 1498 | + { | ||
| 1499 | + int this_order = reg_order[i - 1]; | ||
| 1500 | + for (j = 0; j < nops; j++) | ||
| 1501 | + if (regs[j] > regs[reg_order[i - 1]] | ||
| 1502 | + && (this_order == reg_order[i - 1] | ||
| 1503 | + || regs[j] < regs[this_order])) | ||
| 1504 | + this_order = j; | ||
| 1505 | + reg_order[i] = this_order; | ||
| 1506 | + } | ||
| 1507 | + | ||
| 1508 | + /* Ensure that registers that must be live after the instruction end | ||
| 1509 | + up with the correct value. */ | ||
| 1510 | + for (i = 0; i < nops; i++) | ||
| 1511 | + { | ||
| 1512 | + int this_order = reg_order[i]; | ||
| 1513 | + if ((this_order != mem_order[i] | ||
| 1514 | + || orig_reg_rtxs[this_order] != reg_rtxs[this_order]) | ||
| 1515 | + && !peep2_reg_dead_p (nops * 2, orig_reg_rtxs[this_order])) | ||
| 1516 | + return false; | ||
| 1517 | + } | ||
| 1518 | + | ||
| 1519 | + /* Load the constants. */ | ||
| 1520 | + for (i = 0; i < nops; i++) | ||
| 1521 | + { | ||
| 1522 | + rtx op = operands[2 * nops + mem_order[i]]; | ||
| 1523 | + sorted_regs[i] = regs[reg_order[i]]; | ||
| 1524 | + emit_move_insn (reg_rtxs[reg_order[i]], op); | ||
| 1525 | + } | ||
| 1526 | + | ||
| 1527 | + base_reg_rtx = gen_rtx_REG (Pmode, base_reg); | ||
| 1528 | + | ||
| 1529 | + base_reg_dies = peep2_reg_dead_p (nops * 2, base_reg_rtx); | ||
| 1530 | + if (TARGET_THUMB1) | ||
| 1531 | + { | ||
| 1532 | + gcc_assert (base_reg_dies); | ||
| 1533 | + write_back = TRUE; | ||
| 1534 | + } | ||
| 1535 | + | ||
| 1536 | + if (stm_case == 5) | ||
| 1537 | + { | ||
| 1538 | + gcc_assert (base_reg_dies); | ||
| 1539 | + emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset))); | ||
| 1540 | + offset = 0; | ||
| 1541 | + } | ||
| 1542 | + | ||
| 1543 | + addr = plus_constant (base_reg_rtx, offset); | ||
| 1544 | + | ||
| 1545 | + for (i = 0; i < nops; i++) | ||
| 1546 | + { | ||
| 1547 | + addr = plus_constant (base_reg_rtx, offset + i * 4); | ||
| 1548 | + mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], | ||
| 1549 | + SImode, addr, 0); | ||
| 1550 | + } | ||
| 1551 | + emit_insn (arm_gen_store_multiple_1 (nops, sorted_regs, mems, base_reg_rtx, | ||
| 1552 | + write_back ? offset + i * 4 : 0)); | ||
| 1553 | + return true; | ||
| 1554 | } | ||
| 1555 | |||
| 1556 | int | ||
| 1557 | @@ -10280,20 +10535,21 @@ | ||
| 1558 | for (i = 0; in_words_to_go >= 2; i+=4) | ||
| 1559 | { | ||
| 1560 | if (in_words_to_go > 4) | ||
| 1561 | - emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, | ||
| 1562 | - srcbase, &srcoffset)); | ||
| 1563 | + emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, src, | ||
| 1564 | + TRUE, srcbase, &srcoffset)); | ||
| 1565 | else | ||
| 1566 | - emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, | ||
| 1567 | - FALSE, srcbase, &srcoffset)); | ||
| 1568 | + emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, in_words_to_go, | ||
| 1569 | + src, FALSE, srcbase, | ||
| 1570 | + &srcoffset)); | ||
| 1571 | |||
| 1572 | if (out_words_to_go) | ||
| 1573 | { | ||
| 1574 | if (out_words_to_go > 4) | ||
| 1575 | - emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, | ||
| 1576 | - dstbase, &dstoffset)); | ||
| 1577 | + emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, dst, | ||
| 1578 | + TRUE, dstbase, &dstoffset)); | ||
| 1579 | else if (out_words_to_go != 1) | ||
| 1580 | - emit_insn (arm_gen_store_multiple (0, out_words_to_go, | ||
| 1581 | - dst, TRUE, | ||
| 1582 | + emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, | ||
| 1583 | + out_words_to_go, dst, | ||
| 1584 | (last_bytes == 0 | ||
| 1585 | ? FALSE : TRUE), | ||
| 1586 | dstbase, &dstoffset)); | ||
| 1587 | |||
| 1588 | === modified file 'gcc/config/arm/arm.h' | ||
| 1589 | --- old/gcc/config/arm/arm.h 2011-01-05 12:12:18 +0000 | ||
| 1590 | +++ new/gcc/config/arm/arm.h 2011-01-05 18:20:37 +0000 | ||
| 1591 | @@ -1143,6 +1143,9 @@ | ||
| 1592 | ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ | ||
| 1593 | || (MODE) == CImode || (MODE) == XImode) | ||
| 1594 | |||
| 1595 | +/* The register numbers in sequence, for passing to arm_gen_load_multiple. */ | ||
| 1596 | +extern int arm_regs_in_sequence[]; | ||
| 1597 | + | ||
| 1598 | /* The order in which register should be allocated. It is good to use ip | ||
| 1599 | since no saving is required (though calls clobber it) and it never contains | ||
| 1600 | function parameters. It is quite good to use lr since other calls may | ||
| 1601 | @@ -2823,4 +2826,8 @@ | ||
| 1602 | #define NEED_INDICATE_EXEC_STACK 0 | ||
| 1603 | #endif | ||
| 1604 | |||
| 1605 | +/* The maximum number of parallel loads or stores we support in an ldm/stm | ||
| 1606 | + instruction. */ | ||
| 1607 | +#define MAX_LDM_STM_OPS 4 | ||
| 1608 | + | ||
| 1609 | #endif /* ! GCC_ARM_H */ | ||
| 1610 | |||
| 1611 | === modified file 'gcc/config/arm/arm.md' | ||
| 1612 | --- old/gcc/config/arm/arm.md 2011-01-05 12:12:18 +0000 | ||
| 1613 | +++ new/gcc/config/arm/arm.md 2011-01-05 18:20:37 +0000 | ||
| 1614 | @@ -6282,7 +6282,7 @@ | ||
| 1615 | |||
| 1616 | ;; load- and store-multiple insns | ||
| 1617 | ;; The arm can load/store any set of registers, provided that they are in | ||
| 1618 | -;; ascending order; but that is beyond GCC so stick with what it knows. | ||
| 1619 | +;; ascending order, but these expanders assume a contiguous set. | ||
| 1620 | |||
| 1621 | (define_expand "load_multiple" | ||
| 1622 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") | ||
| 1623 | @@ -6303,126 +6303,12 @@ | ||
| 1624 | FAIL; | ||
| 1625 | |||
| 1626 | operands[3] | ||
| 1627 | - = arm_gen_load_multiple (REGNO (operands[0]), INTVAL (operands[2]), | ||
| 1628 | + = arm_gen_load_multiple (arm_regs_in_sequence + REGNO (operands[0]), | ||
| 1629 | + INTVAL (operands[2]), | ||
| 1630 | force_reg (SImode, XEXP (operands[1], 0)), | ||
| 1631 | - TRUE, FALSE, operands[1], &offset); | ||
| 1632 | + FALSE, operands[1], &offset); | ||
| 1633 | }) | ||
| 1634 | |||
| 1635 | -;; Load multiple with write-back | ||
| 1636 | - | ||
| 1637 | -(define_insn "*ldmsi_postinc4" | ||
| 1638 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1639 | - [(set (match_operand:SI 1 "s_register_operand" "=r") | ||
| 1640 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1641 | - (const_int 16))) | ||
| 1642 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1643 | - (mem:SI (match_dup 2))) | ||
| 1644 | - (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 1645 | - (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | ||
| 1646 | - (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 1647 | - (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | ||
| 1648 | - (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 1649 | - (mem:SI (plus:SI (match_dup 2) (const_int 12))))])] | ||
| 1650 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | ||
| 1651 | - "ldm%(ia%)\\t%1!, {%3, %4, %5, %6}" | ||
| 1652 | - [(set_attr "type" "load4") | ||
| 1653 | - (set_attr "predicable" "yes")] | ||
| 1654 | -) | ||
| 1655 | - | ||
| 1656 | -(define_insn "*ldmsi_postinc4_thumb1" | ||
| 1657 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1658 | - [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 1659 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1660 | - (const_int 16))) | ||
| 1661 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1662 | - (mem:SI (match_dup 2))) | ||
| 1663 | - (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 1664 | - (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | ||
| 1665 | - (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 1666 | - (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | ||
| 1667 | - (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 1668 | - (mem:SI (plus:SI (match_dup 2) (const_int 12))))])] | ||
| 1669 | - "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" | ||
| 1670 | - "ldmia\\t%1!, {%3, %4, %5, %6}" | ||
| 1671 | - [(set_attr "type" "load4")] | ||
| 1672 | -) | ||
| 1673 | - | ||
| 1674 | -(define_insn "*ldmsi_postinc3" | ||
| 1675 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1676 | - [(set (match_operand:SI 1 "s_register_operand" "=r") | ||
| 1677 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1678 | - (const_int 12))) | ||
| 1679 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1680 | - (mem:SI (match_dup 2))) | ||
| 1681 | - (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 1682 | - (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | ||
| 1683 | - (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 1684 | - (mem:SI (plus:SI (match_dup 2) (const_int 8))))])] | ||
| 1685 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 1686 | - "ldm%(ia%)\\t%1!, {%3, %4, %5}" | ||
| 1687 | - [(set_attr "type" "load3") | ||
| 1688 | - (set_attr "predicable" "yes")] | ||
| 1689 | -) | ||
| 1690 | - | ||
| 1691 | -(define_insn "*ldmsi_postinc2" | ||
| 1692 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1693 | - [(set (match_operand:SI 1 "s_register_operand" "=r") | ||
| 1694 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1695 | - (const_int 8))) | ||
| 1696 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1697 | - (mem:SI (match_dup 2))) | ||
| 1698 | - (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 1699 | - (mem:SI (plus:SI (match_dup 2) (const_int 4))))])] | ||
| 1700 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 1701 | - "ldm%(ia%)\\t%1!, {%3, %4}" | ||
| 1702 | - [(set_attr "type" "load2") | ||
| 1703 | - (set_attr "predicable" "yes")] | ||
| 1704 | -) | ||
| 1705 | - | ||
| 1706 | -;; Ordinary load multiple | ||
| 1707 | - | ||
| 1708 | -(define_insn "*ldmsi4" | ||
| 1709 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1710 | - [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 1711 | - (mem:SI (match_operand:SI 1 "s_register_operand" "r"))) | ||
| 1712 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1713 | - (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | ||
| 1714 | - (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 1715 | - (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | ||
| 1716 | - (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 1717 | - (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | ||
| 1718 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 1719 | - "ldm%(ia%)\\t%1, {%2, %3, %4, %5}" | ||
| 1720 | - [(set_attr "type" "load4") | ||
| 1721 | - (set_attr "predicable" "yes")] | ||
| 1722 | -) | ||
| 1723 | - | ||
| 1724 | -(define_insn "*ldmsi3" | ||
| 1725 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1726 | - [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 1727 | - (mem:SI (match_operand:SI 1 "s_register_operand" "r"))) | ||
| 1728 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1729 | - (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | ||
| 1730 | - (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 1731 | - (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | ||
| 1732 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 1733 | - "ldm%(ia%)\\t%1, {%2, %3, %4}" | ||
| 1734 | - [(set_attr "type" "load3") | ||
| 1735 | - (set_attr "predicable" "yes")] | ||
| 1736 | -) | ||
| 1737 | - | ||
| 1738 | -(define_insn "*ldmsi2" | ||
| 1739 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1740 | - [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 1741 | - (mem:SI (match_operand:SI 1 "s_register_operand" "r"))) | ||
| 1742 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1743 | - (mem:SI (plus:SI (match_dup 1) (const_int 4))))])] | ||
| 1744 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" | ||
| 1745 | - "ldm%(ia%)\\t%1, {%2, %3}" | ||
| 1746 | - [(set_attr "type" "load2") | ||
| 1747 | - (set_attr "predicable" "yes")] | ||
| 1748 | -) | ||
| 1749 | - | ||
| 1750 | (define_expand "store_multiple" | ||
| 1751 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") | ||
| 1752 | (match_operand:SI 1 "" "")) | ||
| 1753 | @@ -6442,125 +6328,12 @@ | ||
| 1754 | FAIL; | ||
| 1755 | |||
| 1756 | operands[3] | ||
| 1757 | - = arm_gen_store_multiple (REGNO (operands[1]), INTVAL (operands[2]), | ||
| 1758 | + = arm_gen_store_multiple (arm_regs_in_sequence + REGNO (operands[1]), | ||
| 1759 | + INTVAL (operands[2]), | ||
| 1760 | force_reg (SImode, XEXP (operands[0], 0)), | ||
| 1761 | - TRUE, FALSE, operands[0], &offset); | ||
| 1762 | + FALSE, operands[0], &offset); | ||
| 1763 | }) | ||
| 1764 | |||
| 1765 | -;; Store multiple with write-back | ||
| 1766 | - | ||
| 1767 | -(define_insn "*stmsi_postinc4" | ||
| 1768 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1769 | - [(set (match_operand:SI 1 "s_register_operand" "=r") | ||
| 1770 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1771 | - (const_int 16))) | ||
| 1772 | - (set (mem:SI (match_dup 2)) | ||
| 1773 | - (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 1774 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 1775 | - (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 1776 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 1777 | - (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 1778 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | ||
| 1779 | - (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 1780 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | ||
| 1781 | - "stm%(ia%)\\t%1!, {%3, %4, %5, %6}" | ||
| 1782 | - [(set_attr "predicable" "yes") | ||
| 1783 | - (set_attr "type" "store4")] | ||
| 1784 | -) | ||
| 1785 | - | ||
| 1786 | -(define_insn "*stmsi_postinc4_thumb1" | ||
| 1787 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1788 | - [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 1789 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1790 | - (const_int 16))) | ||
| 1791 | - (set (mem:SI (match_dup 2)) | ||
| 1792 | - (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 1793 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 1794 | - (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 1795 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 1796 | - (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 1797 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | ||
| 1798 | - (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 1799 | - "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" | ||
| 1800 | - "stmia\\t%1!, {%3, %4, %5, %6}" | ||
| 1801 | - [(set_attr "type" "store4")] | ||
| 1802 | -) | ||
| 1803 | - | ||
| 1804 | -(define_insn "*stmsi_postinc3" | ||
| 1805 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1806 | - [(set (match_operand:SI 1 "s_register_operand" "=r") | ||
| 1807 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1808 | - (const_int 12))) | ||
| 1809 | - (set (mem:SI (match_dup 2)) | ||
| 1810 | - (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 1811 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 1812 | - (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 1813 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 1814 | - (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 1815 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 1816 | - "stm%(ia%)\\t%1!, {%3, %4, %5}" | ||
| 1817 | - [(set_attr "predicable" "yes") | ||
| 1818 | - (set_attr "type" "store3")] | ||
| 1819 | -) | ||
| 1820 | - | ||
| 1821 | -(define_insn "*stmsi_postinc2" | ||
| 1822 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1823 | - [(set (match_operand:SI 1 "s_register_operand" "=r") | ||
| 1824 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1825 | - (const_int 8))) | ||
| 1826 | - (set (mem:SI (match_dup 2)) | ||
| 1827 | - (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 1828 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 1829 | - (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 1830 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 1831 | - "stm%(ia%)\\t%1!, {%3, %4}" | ||
| 1832 | - [(set_attr "predicable" "yes") | ||
| 1833 | - (set_attr "type" "store2")] | ||
| 1834 | -) | ||
| 1835 | - | ||
| 1836 | -;; Ordinary store multiple | ||
| 1837 | - | ||
| 1838 | -(define_insn "*stmsi4" | ||
| 1839 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1840 | - [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1841 | - (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 1842 | - (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | ||
| 1843 | - (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 1844 | - (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 1845 | - (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 1846 | - (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | ||
| 1847 | - (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 1848 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 1849 | - "stm%(ia%)\\t%1, {%2, %3, %4, %5}" | ||
| 1850 | - [(set_attr "predicable" "yes") | ||
| 1851 | - (set_attr "type" "store4")] | ||
| 1852 | -) | ||
| 1853 | - | ||
| 1854 | -(define_insn "*stmsi3" | ||
| 1855 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1856 | - [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1857 | - (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 1858 | - (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | ||
| 1859 | - (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 1860 | - (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 1861 | - (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 1862 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 1863 | - "stm%(ia%)\\t%1, {%2, %3, %4}" | ||
| 1864 | - [(set_attr "predicable" "yes") | ||
| 1865 | - (set_attr "type" "store3")] | ||
| 1866 | -) | ||
| 1867 | - | ||
| 1868 | -(define_insn "*stmsi2" | ||
| 1869 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1870 | - [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1871 | - (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 1872 | - (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | ||
| 1873 | - (match_operand:SI 3 "arm_hard_register_operand" ""))])] | ||
| 1874 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" | ||
| 1875 | - "stm%(ia%)\\t%1, {%2, %3}" | ||
| 1876 | - [(set_attr "predicable" "yes") | ||
| 1877 | - (set_attr "type" "store2")] | ||
| 1878 | -) | ||
| 1879 | |||
| 1880 | ;; Move a block of memory if it is word aligned and MORE than 2 words long. | ||
| 1881 | ;; We could let this apply for blocks of less than this, but it clobbers so | ||
| 1882 | @@ -9031,8 +8804,8 @@ | ||
| 1883 | if (REGNO (reg) == R0_REGNUM) | ||
| 1884 | { | ||
| 1885 | /* On thumb we have to use a write-back instruction. */ | ||
| 1886 | - emit_insn (arm_gen_store_multiple (R0_REGNUM, 4, addr, TRUE, | ||
| 1887 | - TARGET_THUMB ? TRUE : FALSE, mem, &offset)); | ||
| 1888 | + emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, addr, | ||
| 1889 | + TARGET_THUMB ? TRUE : FALSE, mem, &offset)); | ||
| 1890 | size = TARGET_ARM ? 16 : 0; | ||
| 1891 | } | ||
| 1892 | else | ||
| 1893 | @@ -9078,8 +8851,8 @@ | ||
| 1894 | if (REGNO (reg) == R0_REGNUM) | ||
| 1895 | { | ||
| 1896 | /* On thumb we have to use a write-back instruction. */ | ||
| 1897 | - emit_insn (arm_gen_load_multiple (R0_REGNUM, 4, addr, TRUE, | ||
| 1898 | - TARGET_THUMB ? TRUE : FALSE, mem, &offset)); | ||
| 1899 | + emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, addr, | ||
| 1900 | + TARGET_THUMB ? TRUE : FALSE, mem, &offset)); | ||
| 1901 | size = TARGET_ARM ? 16 : 0; | ||
| 1902 | } | ||
| 1903 | else | ||
| 1904 | @@ -10672,87 +10445,6 @@ | ||
| 1905 | "" | ||
| 1906 | ) | ||
| 1907 | |||
| 1908 | -; Peepholes to spot possible load- and store-multiples, if the ordering is | ||
| 1909 | -; reversed, check that the memory references aren't volatile. | ||
| 1910 | - | ||
| 1911 | -(define_peephole | ||
| 1912 | - [(set (match_operand:SI 0 "s_register_operand" "=rk") | ||
| 1913 | - (match_operand:SI 4 "memory_operand" "m")) | ||
| 1914 | - (set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 1915 | - (match_operand:SI 5 "memory_operand" "m")) | ||
| 1916 | - (set (match_operand:SI 2 "s_register_operand" "=rk") | ||
| 1917 | - (match_operand:SI 6 "memory_operand" "m")) | ||
| 1918 | - (set (match_operand:SI 3 "s_register_operand" "=rk") | ||
| 1919 | - (match_operand:SI 7 "memory_operand" "m"))] | ||
| 1920 | - "TARGET_ARM && load_multiple_sequence (operands, 4, NULL, NULL, NULL)" | ||
| 1921 | - "* | ||
| 1922 | - return emit_ldm_seq (operands, 4); | ||
| 1923 | - " | ||
| 1924 | -) | ||
| 1925 | - | ||
| 1926 | -(define_peephole | ||
| 1927 | - [(set (match_operand:SI 0 "s_register_operand" "=rk") | ||
| 1928 | - (match_operand:SI 3 "memory_operand" "m")) | ||
| 1929 | - (set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 1930 | - (match_operand:SI 4 "memory_operand" "m")) | ||
| 1931 | - (set (match_operand:SI 2 "s_register_operand" "=rk") | ||
| 1932 | - (match_operand:SI 5 "memory_operand" "m"))] | ||
| 1933 | - "TARGET_ARM && load_multiple_sequence (operands, 3, NULL, NULL, NULL)" | ||
| 1934 | - "* | ||
| 1935 | - return emit_ldm_seq (operands, 3); | ||
| 1936 | - " | ||
| 1937 | -) | ||
| 1938 | - | ||
| 1939 | -(define_peephole | ||
| 1940 | - [(set (match_operand:SI 0 "s_register_operand" "=rk") | ||
| 1941 | - (match_operand:SI 2 "memory_operand" "m")) | ||
| 1942 | - (set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 1943 | - (match_operand:SI 3 "memory_operand" "m"))] | ||
| 1944 | - "TARGET_ARM && load_multiple_sequence (operands, 2, NULL, NULL, NULL)" | ||
| 1945 | - "* | ||
| 1946 | - return emit_ldm_seq (operands, 2); | ||
| 1947 | - " | ||
| 1948 | -) | ||
| 1949 | - | ||
| 1950 | -(define_peephole | ||
| 1951 | - [(set (match_operand:SI 4 "memory_operand" "=m") | ||
| 1952 | - (match_operand:SI 0 "s_register_operand" "rk")) | ||
| 1953 | - (set (match_operand:SI 5 "memory_operand" "=m") | ||
| 1954 | - (match_operand:SI 1 "s_register_operand" "rk")) | ||
| 1955 | - (set (match_operand:SI 6 "memory_operand" "=m") | ||
| 1956 | - (match_operand:SI 2 "s_register_operand" "rk")) | ||
| 1957 | - (set (match_operand:SI 7 "memory_operand" "=m") | ||
| 1958 | - (match_operand:SI 3 "s_register_operand" "rk"))] | ||
| 1959 | - "TARGET_ARM && store_multiple_sequence (operands, 4, NULL, NULL, NULL)" | ||
| 1960 | - "* | ||
| 1961 | - return emit_stm_seq (operands, 4); | ||
| 1962 | - " | ||
| 1963 | -) | ||
| 1964 | - | ||
| 1965 | -(define_peephole | ||
| 1966 | - [(set (match_operand:SI 3 "memory_operand" "=m") | ||
| 1967 | - (match_operand:SI 0 "s_register_operand" "rk")) | ||
| 1968 | - (set (match_operand:SI 4 "memory_operand" "=m") | ||
| 1969 | - (match_operand:SI 1 "s_register_operand" "rk")) | ||
| 1970 | - (set (match_operand:SI 5 "memory_operand" "=m") | ||
| 1971 | - (match_operand:SI 2 "s_register_operand" "rk"))] | ||
| 1972 | - "TARGET_ARM && store_multiple_sequence (operands, 3, NULL, NULL, NULL)" | ||
| 1973 | - "* | ||
| 1974 | - return emit_stm_seq (operands, 3); | ||
| 1975 | - " | ||
| 1976 | -) | ||
| 1977 | - | ||
| 1978 | -(define_peephole | ||
| 1979 | - [(set (match_operand:SI 2 "memory_operand" "=m") | ||
| 1980 | - (match_operand:SI 0 "s_register_operand" "rk")) | ||
| 1981 | - (set (match_operand:SI 3 "memory_operand" "=m") | ||
| 1982 | - (match_operand:SI 1 "s_register_operand" "rk"))] | ||
| 1983 | - "TARGET_ARM && store_multiple_sequence (operands, 2, NULL, NULL, NULL)" | ||
| 1984 | - "* | ||
| 1985 | - return emit_stm_seq (operands, 2); | ||
| 1986 | - " | ||
| 1987 | -) | ||
| 1988 | - | ||
| 1989 | (define_split | ||
| 1990 | [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 1991 | (and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "") | ||
| 1992 | @@ -11559,6 +11251,8 @@ | ||
| 1993 | " | ||
| 1994 | ) | ||
| 1995 | |||
| 1996 | +;; Load the load/store multiple patterns | ||
| 1997 | +(include "ldmstm.md") | ||
| 1998 | ;; Load the FPA co-processor patterns | ||
| 1999 | (include "fpa.md") | ||
| 2000 | ;; Load the Maverick co-processor patterns | ||
| 2001 | |||
| 2002 | === added file 'gcc/config/arm/ldmstm.md' | ||
| 2003 | --- old/gcc/config/arm/ldmstm.md 1970-01-01 00:00:00 +0000 | ||
| 2004 | +++ new/gcc/config/arm/ldmstm.md 2010-11-16 13:08:47 +0000 | ||
| 2005 | @@ -0,0 +1,1191 @@ | ||
| 2006 | +/* ARM ldm/stm instruction patterns. This file was automatically generated | ||
| 2007 | + using arm-ldmstm.ml. Please do not edit manually. | ||
| 2008 | + | ||
| 2009 | + Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 2010 | + Contributed by CodeSourcery. | ||
| 2011 | + | ||
| 2012 | + This file is part of GCC. | ||
| 2013 | + | ||
| 2014 | + GCC is free software; you can redistribute it and/or modify it | ||
| 2015 | + under the terms of the GNU General Public License as published | ||
| 2016 | + by the Free Software Foundation; either version 3, or (at your | ||
| 2017 | + option) any later version. | ||
| 2018 | + | ||
| 2019 | + GCC is distributed in the hope that it will be useful, but WITHOUT | ||
| 2020 | + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
| 2021 | + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | ||
| 2022 | + License for more details. | ||
| 2023 | + | ||
| 2024 | + You should have received a copy of the GNU General Public License and | ||
| 2025 | + a copy of the GCC Runtime Library Exception along with this program; | ||
| 2026 | + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | ||
| 2027 | + <http://www.gnu.org/licenses/>. */ | ||
| 2028 | + | ||
| 2029 | +(define_insn "*ldm4_ia" | ||
| 2030 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2031 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2032 | + (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))) | ||
| 2033 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2034 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2035 | + (const_int 4)))) | ||
| 2036 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2037 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2038 | + (const_int 8)))) | ||
| 2039 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2040 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2041 | + (const_int 12))))])] | ||
| 2042 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2043 | + "ldm%(ia%)\t%1, {%2, %3, %4, %5}" | ||
| 2044 | + [(set_attr "type" "load4") | ||
| 2045 | + (set_attr "predicable" "yes")]) | ||
| 2046 | + | ||
| 2047 | +(define_insn "*thumb_ldm4_ia" | ||
| 2048 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2049 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2050 | + (mem:SI (match_operand:SI 1 "s_register_operand" "l"))) | ||
| 2051 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2052 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2053 | + (const_int 4)))) | ||
| 2054 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2055 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2056 | + (const_int 8)))) | ||
| 2057 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2058 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2059 | + (const_int 12))))])] | ||
| 2060 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" | ||
| 2061 | + "ldm%(ia%)\t%1, {%2, %3, %4, %5}" | ||
| 2062 | + [(set_attr "type" "load4")]) | ||
| 2063 | + | ||
| 2064 | +(define_insn "*ldm4_ia_update" | ||
| 2065 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2066 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2067 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) | ||
| 2068 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2069 | + (mem:SI (match_dup 2))) | ||
| 2070 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2071 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2072 | + (const_int 4)))) | ||
| 2073 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2074 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2075 | + (const_int 8)))) | ||
| 2076 | + (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 2077 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2078 | + (const_int 12))))])] | ||
| 2079 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | ||
| 2080 | + "ldm%(ia%)\t%1!, {%3, %4, %5, %6}" | ||
| 2081 | + [(set_attr "type" "load4") | ||
| 2082 | + (set_attr "predicable" "yes")]) | ||
| 2083 | + | ||
| 2084 | +(define_insn "*thumb_ldm4_ia_update" | ||
| 2085 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2086 | + [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 2087 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) | ||
| 2088 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2089 | + (mem:SI (match_dup 2))) | ||
| 2090 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2091 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2092 | + (const_int 4)))) | ||
| 2093 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2094 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2095 | + (const_int 8)))) | ||
| 2096 | + (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 2097 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2098 | + (const_int 12))))])] | ||
| 2099 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" | ||
| 2100 | + "ldm%(ia%)\t%1!, {%3, %4, %5, %6}" | ||
| 2101 | + [(set_attr "type" "load4")]) | ||
| 2102 | + | ||
| 2103 | +(define_insn "*stm4_ia" | ||
| 2104 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2105 | + [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk")) | ||
| 2106 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2107 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | ||
| 2108 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2109 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 2110 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2111 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | ||
| 2112 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2113 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2114 | + "stm%(ia%)\t%1, {%2, %3, %4, %5}" | ||
| 2115 | + [(set_attr "type" "store4") | ||
| 2116 | + (set_attr "predicable" "yes")]) | ||
| 2117 | + | ||
| 2118 | +(define_insn "*stm4_ia_update" | ||
| 2119 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2120 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2121 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) | ||
| 2122 | + (set (mem:SI (match_dup 2)) | ||
| 2123 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2124 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2125 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2126 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2127 | + (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 2128 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | ||
| 2129 | + (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 2130 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | ||
| 2131 | + "stm%(ia%)\t%1!, {%3, %4, %5, %6}" | ||
| 2132 | + [(set_attr "type" "store4") | ||
| 2133 | + (set_attr "predicable" "yes")]) | ||
| 2134 | + | ||
| 2135 | +(define_insn "*thumb_stm4_ia_update" | ||
| 2136 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2137 | + [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 2138 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) | ||
| 2139 | + (set (mem:SI (match_dup 2)) | ||
| 2140 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2141 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2142 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2143 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2144 | + (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 2145 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | ||
| 2146 | + (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 2147 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" | ||
| 2148 | + "stm%(ia%)\t%1!, {%3, %4, %5, %6}" | ||
| 2149 | + [(set_attr "type" "store4")]) | ||
| 2150 | + | ||
| 2151 | +(define_insn "*ldm4_ib" | ||
| 2152 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2153 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2154 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2155 | + (const_int 4)))) | ||
| 2156 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2157 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2158 | + (const_int 8)))) | ||
| 2159 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2160 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2161 | + (const_int 12)))) | ||
| 2162 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2163 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2164 | + (const_int 16))))])] | ||
| 2165 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2166 | + "ldm%(ib%)\t%1, {%2, %3, %4, %5}" | ||
| 2167 | + [(set_attr "type" "load4") | ||
| 2168 | + (set_attr "predicable" "yes")]) | ||
| 2169 | + | ||
| 2170 | +(define_insn "*ldm4_ib_update" | ||
| 2171 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2172 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2173 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) | ||
| 2174 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2175 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2176 | + (const_int 4)))) | ||
| 2177 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2178 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2179 | + (const_int 8)))) | ||
| 2180 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2181 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2182 | + (const_int 12)))) | ||
| 2183 | + (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 2184 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2185 | + (const_int 16))))])] | ||
| 2186 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 5" | ||
| 2187 | + "ldm%(ib%)\t%1!, {%3, %4, %5, %6}" | ||
| 2188 | + [(set_attr "type" "load4") | ||
| 2189 | + (set_attr "predicable" "yes")]) | ||
| 2190 | + | ||
| 2191 | +(define_insn "*stm4_ib" | ||
| 2192 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2193 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4))) | ||
| 2194 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2195 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 2196 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2197 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | ||
| 2198 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2199 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | ||
| 2200 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2201 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2202 | + "stm%(ib%)\t%1, {%2, %3, %4, %5}" | ||
| 2203 | + [(set_attr "type" "store4") | ||
| 2204 | + (set_attr "predicable" "yes")]) | ||
| 2205 | + | ||
| 2206 | +(define_insn "*stm4_ib_update" | ||
| 2207 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2208 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2209 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) | ||
| 2210 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2211 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2212 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2213 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2214 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | ||
| 2215 | + (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 2216 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | ||
| 2217 | + (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 2218 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 5" | ||
| 2219 | + "stm%(ib%)\t%1!, {%3, %4, %5, %6}" | ||
| 2220 | + [(set_attr "type" "store4") | ||
| 2221 | + (set_attr "predicable" "yes")]) | ||
| 2222 | + | ||
| 2223 | +(define_insn "*ldm4_da" | ||
| 2224 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2225 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2226 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2227 | + (const_int -12)))) | ||
| 2228 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2229 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2230 | + (const_int -8)))) | ||
| 2231 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2232 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2233 | + (const_int -4)))) | ||
| 2234 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2235 | + (mem:SI (match_dup 1)))])] | ||
| 2236 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2237 | + "ldm%(da%)\t%1, {%2, %3, %4, %5}" | ||
| 2238 | + [(set_attr "type" "load4") | ||
| 2239 | + (set_attr "predicable" "yes")]) | ||
| 2240 | + | ||
| 2241 | +(define_insn "*ldm4_da_update" | ||
| 2242 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2243 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2244 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16))) | ||
| 2245 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2246 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2247 | + (const_int -12)))) | ||
| 2248 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2249 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2250 | + (const_int -8)))) | ||
| 2251 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2252 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2253 | + (const_int -4)))) | ||
| 2254 | + (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 2255 | + (mem:SI (match_dup 2)))])] | ||
| 2256 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 5" | ||
| 2257 | + "ldm%(da%)\t%1!, {%3, %4, %5, %6}" | ||
| 2258 | + [(set_attr "type" "load4") | ||
| 2259 | + (set_attr "predicable" "yes")]) | ||
| 2260 | + | ||
| 2261 | +(define_insn "*stm4_da" | ||
| 2262 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2263 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -12))) | ||
| 2264 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2265 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -8))) | ||
| 2266 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2267 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) | ||
| 2268 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2269 | + (set (mem:SI (match_dup 1)) | ||
| 2270 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2271 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2272 | + "stm%(da%)\t%1, {%2, %3, %4, %5}" | ||
| 2273 | + [(set_attr "type" "store4") | ||
| 2274 | + (set_attr "predicable" "yes")]) | ||
| 2275 | + | ||
| 2276 | +(define_insn "*stm4_da_update" | ||
| 2277 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2278 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2279 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16))) | ||
| 2280 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -12))) | ||
| 2281 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2282 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) | ||
| 2283 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2284 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) | ||
| 2285 | + (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 2286 | + (set (mem:SI (match_dup 2)) | ||
| 2287 | + (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 2288 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 5" | ||
| 2289 | + "stm%(da%)\t%1!, {%3, %4, %5, %6}" | ||
| 2290 | + [(set_attr "type" "store4") | ||
| 2291 | + (set_attr "predicable" "yes")]) | ||
| 2292 | + | ||
| 2293 | +(define_insn "*ldm4_db" | ||
| 2294 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2295 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2296 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2297 | + (const_int -16)))) | ||
| 2298 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2299 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2300 | + (const_int -12)))) | ||
| 2301 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2302 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2303 | + (const_int -8)))) | ||
| 2304 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2305 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2306 | + (const_int -4))))])] | ||
| 2307 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2308 | + "ldm%(db%)\t%1, {%2, %3, %4, %5}" | ||
| 2309 | + [(set_attr "type" "load4") | ||
| 2310 | + (set_attr "predicable" "yes")]) | ||
| 2311 | + | ||
| 2312 | +(define_insn "*ldm4_db_update" | ||
| 2313 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2314 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2315 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16))) | ||
| 2316 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2317 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2318 | + (const_int -16)))) | ||
| 2319 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2320 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2321 | + (const_int -12)))) | ||
| 2322 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2323 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2324 | + (const_int -8)))) | ||
| 2325 | + (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 2326 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2327 | + (const_int -4))))])] | ||
| 2328 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | ||
| 2329 | + "ldm%(db%)\t%1!, {%3, %4, %5, %6}" | ||
| 2330 | + [(set_attr "type" "load4") | ||
| 2331 | + (set_attr "predicable" "yes")]) | ||
| 2332 | + | ||
| 2333 | +(define_insn "*stm4_db" | ||
| 2334 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2335 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -16))) | ||
| 2336 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2337 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -12))) | ||
| 2338 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2339 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -8))) | ||
| 2340 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2341 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) | ||
| 2342 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2343 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2344 | + "stm%(db%)\t%1, {%2, %3, %4, %5}" | ||
| 2345 | + [(set_attr "type" "store4") | ||
| 2346 | + (set_attr "predicable" "yes")]) | ||
| 2347 | + | ||
| 2348 | +(define_insn "*stm4_db_update" | ||
| 2349 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2350 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2351 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16))) | ||
| 2352 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -16))) | ||
| 2353 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2354 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -12))) | ||
| 2355 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2356 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) | ||
| 2357 | + (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 2358 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) | ||
| 2359 | + (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 2360 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | ||
| 2361 | + "stm%(db%)\t%1!, {%3, %4, %5, %6}" | ||
| 2362 | + [(set_attr "type" "store4") | ||
| 2363 | + (set_attr "predicable" "yes")]) | ||
| 2364 | + | ||
| 2365 | +(define_peephole2 | ||
| 2366 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2367 | + (match_operand:SI 4 "memory_operand" "")) | ||
| 2368 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 2369 | + (match_operand:SI 5 "memory_operand" "")) | ||
| 2370 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2371 | + (match_operand:SI 6 "memory_operand" "")) | ||
| 2372 | + (set (match_operand:SI 3 "s_register_operand" "") | ||
| 2373 | + (match_operand:SI 7 "memory_operand" ""))] | ||
| 2374 | + "" | ||
| 2375 | + [(const_int 0)] | ||
| 2376 | +{ | ||
| 2377 | + if (gen_ldm_seq (operands, 4, false)) | ||
| 2378 | + DONE; | ||
| 2379 | + else | ||
| 2380 | + FAIL; | ||
| 2381 | +}) | ||
| 2382 | + | ||
| 2383 | +(define_peephole2 | ||
| 2384 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2385 | + (match_operand:SI 4 "memory_operand" "")) | ||
| 2386 | + (parallel | ||
| 2387 | + [(set (match_operand:SI 1 "s_register_operand" "") | ||
| 2388 | + (match_operand:SI 5 "memory_operand" "")) | ||
| 2389 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2390 | + (match_operand:SI 6 "memory_operand" "")) | ||
| 2391 | + (set (match_operand:SI 3 "s_register_operand" "") | ||
| 2392 | + (match_operand:SI 7 "memory_operand" ""))])] | ||
| 2393 | + "" | ||
| 2394 | + [(const_int 0)] | ||
| 2395 | +{ | ||
| 2396 | + if (gen_ldm_seq (operands, 4, false)) | ||
| 2397 | + DONE; | ||
| 2398 | + else | ||
| 2399 | + FAIL; | ||
| 2400 | +}) | ||
| 2401 | + | ||
| 2402 | +(define_peephole2 | ||
| 2403 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2404 | + (match_operand:SI 8 "const_int_operand" "")) | ||
| 2405 | + (set (match_operand:SI 4 "memory_operand" "") | ||
| 2406 | + (match_dup 0)) | ||
| 2407 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 2408 | + (match_operand:SI 9 "const_int_operand" "")) | ||
| 2409 | + (set (match_operand:SI 5 "memory_operand" "") | ||
| 2410 | + (match_dup 1)) | ||
| 2411 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2412 | + (match_operand:SI 10 "const_int_operand" "")) | ||
| 2413 | + (set (match_operand:SI 6 "memory_operand" "") | ||
| 2414 | + (match_dup 2)) | ||
| 2415 | + (set (match_operand:SI 3 "s_register_operand" "") | ||
| 2416 | + (match_operand:SI 11 "const_int_operand" "")) | ||
| 2417 | + (set (match_operand:SI 7 "memory_operand" "") | ||
| 2418 | + (match_dup 3))] | ||
| 2419 | + "" | ||
| 2420 | + [(const_int 0)] | ||
| 2421 | +{ | ||
| 2422 | + if (gen_const_stm_seq (operands, 4)) | ||
| 2423 | + DONE; | ||
| 2424 | + else | ||
| 2425 | + FAIL; | ||
| 2426 | +}) | ||
| 2427 | + | ||
| 2428 | +(define_peephole2 | ||
| 2429 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2430 | + (match_operand:SI 8 "const_int_operand" "")) | ||
| 2431 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 2432 | + (match_operand:SI 9 "const_int_operand" "")) | ||
| 2433 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2434 | + (match_operand:SI 10 "const_int_operand" "")) | ||
| 2435 | + (set (match_operand:SI 3 "s_register_operand" "") | ||
| 2436 | + (match_operand:SI 11 "const_int_operand" "")) | ||
| 2437 | + (set (match_operand:SI 4 "memory_operand" "") | ||
| 2438 | + (match_dup 0)) | ||
| 2439 | + (set (match_operand:SI 5 "memory_operand" "") | ||
| 2440 | + (match_dup 1)) | ||
| 2441 | + (set (match_operand:SI 6 "memory_operand" "") | ||
| 2442 | + (match_dup 2)) | ||
| 2443 | + (set (match_operand:SI 7 "memory_operand" "") | ||
| 2444 | + (match_dup 3))] | ||
| 2445 | + "" | ||
| 2446 | + [(const_int 0)] | ||
| 2447 | +{ | ||
| 2448 | + if (gen_const_stm_seq (operands, 4)) | ||
| 2449 | + DONE; | ||
| 2450 | + else | ||
| 2451 | + FAIL; | ||
| 2452 | +}) | ||
| 2453 | + | ||
| 2454 | +(define_peephole2 | ||
| 2455 | + [(set (match_operand:SI 4 "memory_operand" "") | ||
| 2456 | + (match_operand:SI 0 "s_register_operand" "")) | ||
| 2457 | + (set (match_operand:SI 5 "memory_operand" "") | ||
| 2458 | + (match_operand:SI 1 "s_register_operand" "")) | ||
| 2459 | + (set (match_operand:SI 6 "memory_operand" "") | ||
| 2460 | + (match_operand:SI 2 "s_register_operand" "")) | ||
| 2461 | + (set (match_operand:SI 7 "memory_operand" "") | ||
| 2462 | + (match_operand:SI 3 "s_register_operand" ""))] | ||
| 2463 | + "" | ||
| 2464 | + [(const_int 0)] | ||
| 2465 | +{ | ||
| 2466 | + if (gen_stm_seq (operands, 4)) | ||
| 2467 | + DONE; | ||
| 2468 | + else | ||
| 2469 | + FAIL; | ||
| 2470 | +}) | ||
| 2471 | + | ||
| 2472 | +(define_insn "*ldm3_ia" | ||
| 2473 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2474 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2475 | + (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))) | ||
| 2476 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2477 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2478 | + (const_int 4)))) | ||
| 2479 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2480 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2481 | + (const_int 8))))])] | ||
| 2482 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 2483 | + "ldm%(ia%)\t%1, {%2, %3, %4}" | ||
| 2484 | + [(set_attr "type" "load3") | ||
| 2485 | + (set_attr "predicable" "yes")]) | ||
| 2486 | + | ||
| 2487 | +(define_insn "*thumb_ldm3_ia" | ||
| 2488 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2489 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2490 | + (mem:SI (match_operand:SI 1 "s_register_operand" "l"))) | ||
| 2491 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2492 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2493 | + (const_int 4)))) | ||
| 2494 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2495 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2496 | + (const_int 8))))])] | ||
| 2497 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" | ||
| 2498 | + "ldm%(ia%)\t%1, {%2, %3, %4}" | ||
| 2499 | + [(set_attr "type" "load3")]) | ||
| 2500 | + | ||
| 2501 | +(define_insn "*ldm3_ia_update" | ||
| 2502 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2503 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2504 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) | ||
| 2505 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2506 | + (mem:SI (match_dup 2))) | ||
| 2507 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2508 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2509 | + (const_int 4)))) | ||
| 2510 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2511 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2512 | + (const_int 8))))])] | ||
| 2513 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2514 | + "ldm%(ia%)\t%1!, {%3, %4, %5}" | ||
| 2515 | + [(set_attr "type" "load3") | ||
| 2516 | + (set_attr "predicable" "yes")]) | ||
| 2517 | + | ||
| 2518 | +(define_insn "*thumb_ldm3_ia_update" | ||
| 2519 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2520 | + [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 2521 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) | ||
| 2522 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2523 | + (mem:SI (match_dup 2))) | ||
| 2524 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2525 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2526 | + (const_int 4)))) | ||
| 2527 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2528 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2529 | + (const_int 8))))])] | ||
| 2530 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" | ||
| 2531 | + "ldm%(ia%)\t%1!, {%3, %4, %5}" | ||
| 2532 | + [(set_attr "type" "load3")]) | ||
| 2533 | + | ||
| 2534 | +(define_insn "*stm3_ia" | ||
| 2535 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2536 | + [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk")) | ||
| 2537 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2538 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | ||
| 2539 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2540 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 2541 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2542 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 2543 | + "stm%(ia%)\t%1, {%2, %3, %4}" | ||
| 2544 | + [(set_attr "type" "store3") | ||
| 2545 | + (set_attr "predicable" "yes")]) | ||
| 2546 | + | ||
| 2547 | +(define_insn "*stm3_ia_update" | ||
| 2548 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2549 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2550 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) | ||
| 2551 | + (set (mem:SI (match_dup 2)) | ||
| 2552 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2553 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2554 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2555 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2556 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2557 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2558 | + "stm%(ia%)\t%1!, {%3, %4, %5}" | ||
| 2559 | + [(set_attr "type" "store3") | ||
| 2560 | + (set_attr "predicable" "yes")]) | ||
| 2561 | + | ||
| 2562 | +(define_insn "*thumb_stm3_ia_update" | ||
| 2563 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2564 | + [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 2565 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) | ||
| 2566 | + (set (mem:SI (match_dup 2)) | ||
| 2567 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2568 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2569 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2570 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2571 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2572 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" | ||
| 2573 | + "stm%(ia%)\t%1!, {%3, %4, %5}" | ||
| 2574 | + [(set_attr "type" "store3")]) | ||
| 2575 | + | ||
| 2576 | +(define_insn "*ldm3_ib" | ||
| 2577 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2578 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2579 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2580 | + (const_int 4)))) | ||
| 2581 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2582 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2583 | + (const_int 8)))) | ||
| 2584 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2585 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2586 | + (const_int 12))))])] | ||
| 2587 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2588 | + "ldm%(ib%)\t%1, {%2, %3, %4}" | ||
| 2589 | + [(set_attr "type" "load3") | ||
| 2590 | + (set_attr "predicable" "yes")]) | ||
| 2591 | + | ||
| 2592 | +(define_insn "*ldm3_ib_update" | ||
| 2593 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2594 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2595 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) | ||
| 2596 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2597 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2598 | + (const_int 4)))) | ||
| 2599 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2600 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2601 | + (const_int 8)))) | ||
| 2602 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2603 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2604 | + (const_int 12))))])] | ||
| 2605 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2606 | + "ldm%(ib%)\t%1!, {%3, %4, %5}" | ||
| 2607 | + [(set_attr "type" "load3") | ||
| 2608 | + (set_attr "predicable" "yes")]) | ||
| 2609 | + | ||
| 2610 | +(define_insn "*stm3_ib" | ||
| 2611 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2612 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4))) | ||
| 2613 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2614 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 2615 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2616 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | ||
| 2617 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2618 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2619 | + "stm%(ib%)\t%1, {%2, %3, %4}" | ||
| 2620 | + [(set_attr "type" "store3") | ||
| 2621 | + (set_attr "predicable" "yes")]) | ||
| 2622 | + | ||
| 2623 | +(define_insn "*stm3_ib_update" | ||
| 2624 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2625 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2626 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) | ||
| 2627 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2628 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2629 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2630 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2631 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | ||
| 2632 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2633 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2634 | + "stm%(ib%)\t%1!, {%3, %4, %5}" | ||
| 2635 | + [(set_attr "type" "store3") | ||
| 2636 | + (set_attr "predicable" "yes")]) | ||
| 2637 | + | ||
| 2638 | +(define_insn "*ldm3_da" | ||
| 2639 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2640 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2641 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2642 | + (const_int -8)))) | ||
| 2643 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2644 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2645 | + (const_int -4)))) | ||
| 2646 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2647 | + (mem:SI (match_dup 1)))])] | ||
| 2648 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2649 | + "ldm%(da%)\t%1, {%2, %3, %4}" | ||
| 2650 | + [(set_attr "type" "load3") | ||
| 2651 | + (set_attr "predicable" "yes")]) | ||
| 2652 | + | ||
| 2653 | +(define_insn "*ldm3_da_update" | ||
| 2654 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2655 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2656 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12))) | ||
| 2657 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2658 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2659 | + (const_int -8)))) | ||
| 2660 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2661 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2662 | + (const_int -4)))) | ||
| 2663 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2664 | + (mem:SI (match_dup 2)))])] | ||
| 2665 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2666 | + "ldm%(da%)\t%1!, {%3, %4, %5}" | ||
| 2667 | + [(set_attr "type" "load3") | ||
| 2668 | + (set_attr "predicable" "yes")]) | ||
| 2669 | + | ||
| 2670 | +(define_insn "*stm3_da" | ||
| 2671 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2672 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -8))) | ||
| 2673 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2674 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) | ||
| 2675 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2676 | + (set (mem:SI (match_dup 1)) | ||
| 2677 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2678 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2679 | + "stm%(da%)\t%1, {%2, %3, %4}" | ||
| 2680 | + [(set_attr "type" "store3") | ||
| 2681 | + (set_attr "predicable" "yes")]) | ||
| 2682 | + | ||
| 2683 | +(define_insn "*stm3_da_update" | ||
| 2684 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2685 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2686 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12))) | ||
| 2687 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) | ||
| 2688 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2689 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) | ||
| 2690 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2691 | + (set (mem:SI (match_dup 2)) | ||
| 2692 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2693 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2694 | + "stm%(da%)\t%1!, {%3, %4, %5}" | ||
| 2695 | + [(set_attr "type" "store3") | ||
| 2696 | + (set_attr "predicable" "yes")]) | ||
| 2697 | + | ||
| 2698 | +(define_insn "*ldm3_db" | ||
| 2699 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2700 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2701 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2702 | + (const_int -12)))) | ||
| 2703 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2704 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2705 | + (const_int -8)))) | ||
| 2706 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2707 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2708 | + (const_int -4))))])] | ||
| 2709 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 2710 | + "ldm%(db%)\t%1, {%2, %3, %4}" | ||
| 2711 | + [(set_attr "type" "load3") | ||
| 2712 | + (set_attr "predicable" "yes")]) | ||
| 2713 | + | ||
| 2714 | +(define_insn "*ldm3_db_update" | ||
| 2715 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2716 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2717 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12))) | ||
| 2718 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2719 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2720 | + (const_int -12)))) | ||
| 2721 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2722 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2723 | + (const_int -8)))) | ||
| 2724 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2725 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2726 | + (const_int -4))))])] | ||
| 2727 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2728 | + "ldm%(db%)\t%1!, {%3, %4, %5}" | ||
| 2729 | + [(set_attr "type" "load3") | ||
| 2730 | + (set_attr "predicable" "yes")]) | ||
| 2731 | + | ||
| 2732 | +(define_insn "*stm3_db" | ||
| 2733 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2734 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -12))) | ||
| 2735 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2736 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -8))) | ||
| 2737 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2738 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) | ||
| 2739 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2740 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 2741 | + "stm%(db%)\t%1, {%2, %3, %4}" | ||
| 2742 | + [(set_attr "type" "store3") | ||
| 2743 | + (set_attr "predicable" "yes")]) | ||
| 2744 | + | ||
| 2745 | +(define_insn "*stm3_db_update" | ||
| 2746 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2747 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2748 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12))) | ||
| 2749 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -12))) | ||
| 2750 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2751 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) | ||
| 2752 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2753 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) | ||
| 2754 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2755 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2756 | + "stm%(db%)\t%1!, {%3, %4, %5}" | ||
| 2757 | + [(set_attr "type" "store3") | ||
| 2758 | + (set_attr "predicable" "yes")]) | ||
| 2759 | + | ||
| 2760 | +(define_peephole2 | ||
| 2761 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2762 | + (match_operand:SI 3 "memory_operand" "")) | ||
| 2763 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 2764 | + (match_operand:SI 4 "memory_operand" "")) | ||
| 2765 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2766 | + (match_operand:SI 5 "memory_operand" ""))] | ||
| 2767 | + "" | ||
| 2768 | + [(const_int 0)] | ||
| 2769 | +{ | ||
| 2770 | + if (gen_ldm_seq (operands, 3, false)) | ||
| 2771 | + DONE; | ||
| 2772 | + else | ||
| 2773 | + FAIL; | ||
| 2774 | +}) | ||
| 2775 | + | ||
| 2776 | +(define_peephole2 | ||
| 2777 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2778 | + (match_operand:SI 3 "memory_operand" "")) | ||
| 2779 | + (parallel | ||
| 2780 | + [(set (match_operand:SI 1 "s_register_operand" "") | ||
| 2781 | + (match_operand:SI 4 "memory_operand" "")) | ||
| 2782 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2783 | + (match_operand:SI 5 "memory_operand" ""))])] | ||
| 2784 | + "" | ||
| 2785 | + [(const_int 0)] | ||
| 2786 | +{ | ||
| 2787 | + if (gen_ldm_seq (operands, 3, false)) | ||
| 2788 | + DONE; | ||
| 2789 | + else | ||
| 2790 | + FAIL; | ||
| 2791 | +}) | ||
| 2792 | + | ||
| 2793 | +(define_peephole2 | ||
| 2794 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2795 | + (match_operand:SI 6 "const_int_operand" "")) | ||
| 2796 | + (set (match_operand:SI 3 "memory_operand" "") | ||
| 2797 | + (match_dup 0)) | ||
| 2798 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 2799 | + (match_operand:SI 7 "const_int_operand" "")) | ||
| 2800 | + (set (match_operand:SI 4 "memory_operand" "") | ||
| 2801 | + (match_dup 1)) | ||
| 2802 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2803 | + (match_operand:SI 8 "const_int_operand" "")) | ||
| 2804 | + (set (match_operand:SI 5 "memory_operand" "") | ||
| 2805 | + (match_dup 2))] | ||
| 2806 | + "" | ||
| 2807 | + [(const_int 0)] | ||
| 2808 | +{ | ||
| 2809 | + if (gen_const_stm_seq (operands, 3)) | ||
| 2810 | + DONE; | ||
| 2811 | + else | ||
| 2812 | + FAIL; | ||
| 2813 | +}) | ||
| 2814 | + | ||
| 2815 | +(define_peephole2 | ||
| 2816 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2817 | + (match_operand:SI 6 "const_int_operand" "")) | ||
| 2818 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 2819 | + (match_operand:SI 7 "const_int_operand" "")) | ||
| 2820 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2821 | + (match_operand:SI 8 "const_int_operand" "")) | ||
| 2822 | + (set (match_operand:SI 3 "memory_operand" "") | ||
| 2823 | + (match_dup 0)) | ||
| 2824 | + (set (match_operand:SI 4 "memory_operand" "") | ||
| 2825 | + (match_dup 1)) | ||
| 2826 | + (set (match_operand:SI 5 "memory_operand" "") | ||
| 2827 | + (match_dup 2))] | ||
| 2828 | + "" | ||
| 2829 | + [(const_int 0)] | ||
| 2830 | +{ | ||
| 2831 | + if (gen_const_stm_seq (operands, 3)) | ||
| 2832 | + DONE; | ||
| 2833 | + else | ||
| 2834 | + FAIL; | ||
| 2835 | +}) | ||
| 2836 | + | ||
| 2837 | +(define_peephole2 | ||
| 2838 | + [(set (match_operand:SI 3 "memory_operand" "") | ||
| 2839 | + (match_operand:SI 0 "s_register_operand" "")) | ||
| 2840 | + (set (match_operand:SI 4 "memory_operand" "") | ||
| 2841 | + (match_operand:SI 1 "s_register_operand" "")) | ||
| 2842 | + (set (match_operand:SI 5 "memory_operand" "") | ||
| 2843 | + (match_operand:SI 2 "s_register_operand" ""))] | ||
| 2844 | + "" | ||
| 2845 | + [(const_int 0)] | ||
| 2846 | +{ | ||
| 2847 | + if (gen_stm_seq (operands, 3)) | ||
| 2848 | + DONE; | ||
| 2849 | + else | ||
| 2850 | + FAIL; | ||
| 2851 | +}) | ||
| 2852 | + | ||
| 2853 | +(define_insn "*ldm2_ia" | ||
| 2854 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2855 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2856 | + (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))) | ||
| 2857 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2858 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2859 | + (const_int 4))))])] | ||
| 2860 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" | ||
| 2861 | + "ldm%(ia%)\t%1, {%2, %3}" | ||
| 2862 | + [(set_attr "type" "load2") | ||
| 2863 | + (set_attr "predicable" "yes")]) | ||
| 2864 | + | ||
| 2865 | +(define_insn "*thumb_ldm2_ia" | ||
| 2866 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2867 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2868 | + (mem:SI (match_operand:SI 1 "s_register_operand" "l"))) | ||
| 2869 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2870 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2871 | + (const_int 4))))])] | ||
| 2872 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2" | ||
| 2873 | + "ldm%(ia%)\t%1, {%2, %3}" | ||
| 2874 | + [(set_attr "type" "load2")]) | ||
| 2875 | + | ||
| 2876 | +(define_insn "*ldm2_ia_update" | ||
| 2877 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2878 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2879 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) | ||
| 2880 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2881 | + (mem:SI (match_dup 2))) | ||
| 2882 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2883 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2884 | + (const_int 4))))])] | ||
| 2885 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 2886 | + "ldm%(ia%)\t%1!, {%3, %4}" | ||
| 2887 | + [(set_attr "type" "load2") | ||
| 2888 | + (set_attr "predicable" "yes")]) | ||
| 2889 | + | ||
| 2890 | +(define_insn "*thumb_ldm2_ia_update" | ||
| 2891 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2892 | + [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 2893 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) | ||
| 2894 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2895 | + (mem:SI (match_dup 2))) | ||
| 2896 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2897 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2898 | + (const_int 4))))])] | ||
| 2899 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" | ||
| 2900 | + "ldm%(ia%)\t%1!, {%3, %4}" | ||
| 2901 | + [(set_attr "type" "load2")]) | ||
| 2902 | + | ||
| 2903 | +(define_insn "*stm2_ia" | ||
| 2904 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2905 | + [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk")) | ||
| 2906 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2907 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | ||
| 2908 | + (match_operand:SI 3 "arm_hard_register_operand" ""))])] | ||
| 2909 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" | ||
| 2910 | + "stm%(ia%)\t%1, {%2, %3}" | ||
| 2911 | + [(set_attr "type" "store2") | ||
| 2912 | + (set_attr "predicable" "yes")]) | ||
| 2913 | + | ||
| 2914 | +(define_insn "*stm2_ia_update" | ||
| 2915 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2916 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2917 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) | ||
| 2918 | + (set (mem:SI (match_dup 2)) | ||
| 2919 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2920 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2921 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2922 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 2923 | + "stm%(ia%)\t%1!, {%3, %4}" | ||
| 2924 | + [(set_attr "type" "store2") | ||
| 2925 | + (set_attr "predicable" "yes")]) | ||
| 2926 | + | ||
| 2927 | +(define_insn "*thumb_stm2_ia_update" | ||
| 2928 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2929 | + [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 2930 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) | ||
| 2931 | + (set (mem:SI (match_dup 2)) | ||
| 2932 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2933 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2934 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2935 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" | ||
| 2936 | + "stm%(ia%)\t%1!, {%3, %4}" | ||
| 2937 | + [(set_attr "type" "store2")]) | ||
| 2938 | + | ||
| 2939 | +(define_insn "*ldm2_ib" | ||
| 2940 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2941 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2942 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2943 | + (const_int 4)))) | ||
| 2944 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2945 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2946 | + (const_int 8))))])] | ||
| 2947 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 2" | ||
| 2948 | + "ldm%(ib%)\t%1, {%2, %3}" | ||
| 2949 | + [(set_attr "type" "load2") | ||
| 2950 | + (set_attr "predicable" "yes")]) | ||
| 2951 | + | ||
| 2952 | +(define_insn "*ldm2_ib_update" | ||
| 2953 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2954 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2955 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) | ||
| 2956 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2957 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2958 | + (const_int 4)))) | ||
| 2959 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2960 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2961 | + (const_int 8))))])] | ||
| 2962 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2963 | + "ldm%(ib%)\t%1!, {%3, %4}" | ||
| 2964 | + [(set_attr "type" "load2") | ||
| 2965 | + (set_attr "predicable" "yes")]) | ||
| 2966 | + | ||
| 2967 | +(define_insn "*stm2_ib" | ||
| 2968 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2969 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4))) | ||
| 2970 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2971 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 2972 | + (match_operand:SI 3 "arm_hard_register_operand" ""))])] | ||
| 2973 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 2" | ||
| 2974 | + "stm%(ib%)\t%1, {%2, %3}" | ||
| 2975 | + [(set_attr "type" "store2") | ||
| 2976 | + (set_attr "predicable" "yes")]) | ||
| 2977 | + | ||
| 2978 | +(define_insn "*stm2_ib_update" | ||
| 2979 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2980 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2981 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) | ||
| 2982 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2983 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2984 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2985 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2986 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2987 | + "stm%(ib%)\t%1!, {%3, %4}" | ||
| 2988 | + [(set_attr "type" "store2") | ||
| 2989 | + (set_attr "predicable" "yes")]) | ||
| 2990 | + | ||
| 2991 | +(define_insn "*ldm2_da" | ||
| 2992 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2993 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2994 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2995 | + (const_int -4)))) | ||
| 2996 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2997 | + (mem:SI (match_dup 1)))])] | ||
| 2998 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 2" | ||
| 2999 | + "ldm%(da%)\t%1, {%2, %3}" | ||
| 3000 | + [(set_attr "type" "load2") | ||
| 3001 | + (set_attr "predicable" "yes")]) | ||
| 3002 | + | ||
| 3003 | +(define_insn "*ldm2_da_update" | ||
| 3004 | + [(match_parallel 0 "load_multiple_operation" | ||
| 3005 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 3006 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8))) | ||
| 3007 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 3008 | + (mem:SI (plus:SI (match_dup 2) | ||
| 3009 | + (const_int -4)))) | ||
| 3010 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 3011 | + (mem:SI (match_dup 2)))])] | ||
| 3012 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 3013 | + "ldm%(da%)\t%1!, {%3, %4}" | ||
| 3014 | + [(set_attr "type" "load2") | ||
| 3015 | + (set_attr "predicable" "yes")]) | ||
| 3016 | + | ||
| 3017 | +(define_insn "*stm2_da" | ||
| 3018 | + [(match_parallel 0 "store_multiple_operation" | ||
| 3019 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -4))) | ||
| 3020 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 3021 | + (set (mem:SI (match_dup 1)) | ||
| 3022 | + (match_operand:SI 3 "arm_hard_register_operand" ""))])] | ||
| 3023 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 2" | ||
| 3024 | + "stm%(da%)\t%1, {%2, %3}" | ||
| 3025 | + [(set_attr "type" "store2") | ||
| 3026 | + (set_attr "predicable" "yes")]) | ||
| 3027 | + | ||
| 3028 | +(define_insn "*stm2_da_update" | ||
| 3029 | + [(match_parallel 0 "store_multiple_operation" | ||
| 3030 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 3031 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8))) | ||
| 3032 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) | ||
| 3033 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 3034 | + (set (mem:SI (match_dup 2)) | ||
| 3035 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 3036 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 3037 | + "stm%(da%)\t%1!, {%3, %4}" | ||
| 3038 | + [(set_attr "type" "store2") | ||
| 3039 | + (set_attr "predicable" "yes")]) | ||
| 3040 | + | ||
| 3041 | +(define_insn "*ldm2_db" | ||
| 3042 | + [(match_parallel 0 "load_multiple_operation" | ||
| 3043 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 3044 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 3045 | + (const_int -8)))) | ||
| 3046 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 3047 | + (mem:SI (plus:SI (match_dup 1) | ||
| 3048 | + (const_int -4))))])] | ||
| 3049 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" | ||
| 3050 | + "ldm%(db%)\t%1, {%2, %3}" | ||
| 3051 | + [(set_attr "type" "load2") | ||
| 3052 | + (set_attr "predicable" "yes")]) | ||
| 3053 | + | ||
| 3054 | +(define_insn "*ldm2_db_update" | ||
| 3055 | + [(match_parallel 0 "load_multiple_operation" | ||
| 3056 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 3057 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8))) | ||
| 3058 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 3059 | + (mem:SI (plus:SI (match_dup 2) | ||
| 3060 | + (const_int -8)))) | ||
| 3061 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 3062 | + (mem:SI (plus:SI (match_dup 2) | ||
| 3063 | + (const_int -4))))])] | ||
| 3064 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 3065 | + "ldm%(db%)\t%1!, {%3, %4}" | ||
| 3066 | + [(set_attr "type" "load2") | ||
| 3067 | + (set_attr "predicable" "yes")]) | ||
| 3068 | + | ||
| 3069 | +(define_insn "*stm2_db" | ||
| 3070 | + [(match_parallel 0 "store_multiple_operation" | ||
| 3071 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -8))) | ||
| 3072 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 3073 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) | ||
| 3074 | + (match_operand:SI 3 "arm_hard_register_operand" ""))])] | ||
| 3075 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" | ||
| 3076 | + "stm%(db%)\t%1, {%2, %3}" | ||
| 3077 | + [(set_attr "type" "store2") | ||
| 3078 | + (set_attr "predicable" "yes")]) | ||
| 3079 | + | ||
| 3080 | +(define_insn "*stm2_db_update" | ||
| 3081 | + [(match_parallel 0 "store_multiple_operation" | ||
| 3082 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 3083 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8))) | ||
| 3084 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) | ||
| 3085 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 3086 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) | ||
| 3087 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 3088 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 3089 | + "stm%(db%)\t%1!, {%3, %4}" | ||
| 3090 | + [(set_attr "type" "store2") | ||
| 3091 | + (set_attr "predicable" "yes")]) | ||
| 3092 | + | ||
| 3093 | +(define_peephole2 | ||
| 3094 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 3095 | + (match_operand:SI 2 "memory_operand" "")) | ||
| 3096 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 3097 | + (match_operand:SI 3 "memory_operand" ""))] | ||
| 3098 | + "" | ||
| 3099 | + [(const_int 0)] | ||
| 3100 | +{ | ||
| 3101 | + if (gen_ldm_seq (operands, 2, false)) | ||
| 3102 | + DONE; | ||
| 3103 | + else | ||
| 3104 | + FAIL; | ||
| 3105 | +}) | ||
| 3106 | + | ||
| 3107 | +(define_peephole2 | ||
| 3108 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 3109 | + (match_operand:SI 4 "const_int_operand" "")) | ||
| 3110 | + (set (match_operand:SI 2 "memory_operand" "") | ||
| 3111 | + (match_dup 0)) | ||
| 3112 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 3113 | + (match_operand:SI 5 "const_int_operand" "")) | ||
| 3114 | + (set (match_operand:SI 3 "memory_operand" "") | ||
| 3115 | + (match_dup 1))] | ||
| 3116 | + "" | ||
| 3117 | + [(const_int 0)] | ||
| 3118 | +{ | ||
| 3119 | + if (gen_const_stm_seq (operands, 2)) | ||
| 3120 | + DONE; | ||
| 3121 | + else | ||
| 3122 | + FAIL; | ||
| 3123 | +}) | ||
| 3124 | + | ||
| 3125 | +(define_peephole2 | ||
| 3126 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 3127 | + (match_operand:SI 4 "const_int_operand" "")) | ||
| 3128 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 3129 | + (match_operand:SI 5 "const_int_operand" "")) | ||
| 3130 | + (set (match_operand:SI 2 "memory_operand" "") | ||
| 3131 | + (match_dup 0)) | ||
| 3132 | + (set (match_operand:SI 3 "memory_operand" "") | ||
| 3133 | + (match_dup 1))] | ||
| 3134 | + "" | ||
| 3135 | + [(const_int 0)] | ||
| 3136 | +{ | ||
| 3137 | + if (gen_const_stm_seq (operands, 2)) | ||
| 3138 | + DONE; | ||
| 3139 | + else | ||
| 3140 | + FAIL; | ||
| 3141 | +}) | ||
| 3142 | + | ||
| 3143 | +(define_peephole2 | ||
| 3144 | + [(set (match_operand:SI 2 "memory_operand" "") | ||
| 3145 | + (match_operand:SI 0 "s_register_operand" "")) | ||
| 3146 | + (set (match_operand:SI 3 "memory_operand" "") | ||
| 3147 | + (match_operand:SI 1 "s_register_operand" ""))] | ||
| 3148 | + "" | ||
| 3149 | + [(const_int 0)] | ||
| 3150 | +{ | ||
| 3151 | + if (gen_stm_seq (operands, 2)) | ||
| 3152 | + DONE; | ||
| 3153 | + else | ||
| 3154 | + FAIL; | ||
| 3155 | +}) | ||
| 3156 | + | ||
| 3157 | +(define_peephole2 | ||
| 3158 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 3159 | + (match_operand:SI 2 "memory_operand" "")) | ||
| 3160 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 3161 | + (match_operand:SI 3 "memory_operand" "")) | ||
| 3162 | + (parallel | ||
| 3163 | + [(set (match_operand:SI 4 "s_register_operand" "") | ||
| 3164 | + (match_operator:SI 5 "commutative_binary_operator" | ||
| 3165 | + [(match_operand:SI 6 "s_register_operand" "") | ||
| 3166 | + (match_operand:SI 7 "s_register_operand" "")])) | ||
| 3167 | + (clobber (reg:CC CC_REGNUM))])] | ||
| 3168 | + "(((operands[6] == operands[0] && operands[7] == operands[1]) | ||
| 3169 | + || (operands[7] == operands[0] && operands[6] == operands[1])) | ||
| 3170 | + && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[1]))" | ||
| 3171 | + [(parallel | ||
| 3172 | + [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)])) | ||
| 3173 | + (clobber (reg:CC CC_REGNUM))])] | ||
| 3174 | +{ | ||
| 3175 | + if (!gen_ldm_seq (operands, 2, true)) | ||
| 3176 | + FAIL; | ||
| 3177 | +}) | ||
| 3178 | + | ||
| 3179 | +(define_peephole2 | ||
| 3180 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 3181 | + (match_operand:SI 2 "memory_operand" "")) | ||
| 3182 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 3183 | + (match_operand:SI 3 "memory_operand" "")) | ||
| 3184 | + (set (match_operand:SI 4 "s_register_operand" "") | ||
| 3185 | + (match_operator:SI 5 "commutative_binary_operator" | ||
| 3186 | + [(match_operand:SI 6 "s_register_operand" "") | ||
| 3187 | + (match_operand:SI 7 "s_register_operand" "")]))] | ||
| 3188 | + "(((operands[6] == operands[0] && operands[7] == operands[1]) | ||
| 3189 | + || (operands[7] == operands[0] && operands[6] == operands[1])) | ||
| 3190 | + && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[1]))" | ||
| 3191 | + [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))] | ||
| 3192 | +{ | ||
| 3193 | + if (!gen_ldm_seq (operands, 2, true)) | ||
| 3194 | + FAIL; | ||
| 3195 | +}) | ||
| 3196 | + | ||
| 3197 | |||
| 3198 | === modified file 'gcc/config/arm/predicates.md' | ||
| 3199 | --- old/gcc/config/arm/predicates.md 2010-11-04 10:45:05 +0000 | ||
| 3200 | +++ new/gcc/config/arm/predicates.md 2010-11-16 12:32:34 +0000 | ||
| 3201 | @@ -211,6 +211,11 @@ | ||
| 3202 | (and (match_code "ior,xor,and") | ||
| 3203 | (match_test "mode == GET_MODE (op)"))) | ||
| 3204 | |||
| 3205 | +;; True for commutative operators | ||
| 3206 | +(define_special_predicate "commutative_binary_operator" | ||
| 3207 | + (and (match_code "ior,xor,and,plus") | ||
| 3208 | + (match_test "mode == GET_MODE (op)"))) | ||
| 3209 | + | ||
| 3210 | ;; True for shift operators. | ||
| 3211 | (define_special_predicate "shift_operator" | ||
| 3212 | (and (ior (ior (and (match_code "mult") | ||
| 3213 | @@ -334,16 +339,20 @@ | ||
| 3214 | (match_code "parallel") | ||
| 3215 | { | ||
| 3216 | HOST_WIDE_INT count = XVECLEN (op, 0); | ||
| 3217 | - int dest_regno; | ||
| 3218 | + unsigned dest_regno; | ||
| 3219 | rtx src_addr; | ||
| 3220 | HOST_WIDE_INT i = 1, base = 0; | ||
| 3221 | + HOST_WIDE_INT offset = 0; | ||
| 3222 | rtx elt; | ||
| 3223 | + bool addr_reg_loaded = false; | ||
| 3224 | + bool update = false; | ||
| 3225 | |||
| 3226 | if (low_irq_latency) | ||
| 3227 | return false; | ||
| 3228 | |||
| 3229 | if (count <= 1 | ||
| 3230 | - || GET_CODE (XVECEXP (op, 0, 0)) != SET) | ||
| 3231 | + || GET_CODE (XVECEXP (op, 0, 0)) != SET | ||
| 3232 | + || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))) | ||
| 3233 | return false; | ||
| 3234 | |||
| 3235 | /* Check to see if this might be a write-back. */ | ||
| 3236 | @@ -351,6 +360,7 @@ | ||
| 3237 | { | ||
| 3238 | i++; | ||
| 3239 | base = 1; | ||
| 3240 | + update = true; | ||
| 3241 | |||
| 3242 | /* Now check it more carefully. */ | ||
| 3243 | if (GET_CODE (SET_DEST (elt)) != REG | ||
| 3244 | @@ -369,6 +379,15 @@ | ||
| 3245 | |||
| 3246 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); | ||
| 3247 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); | ||
| 3248 | + if (GET_CODE (src_addr) == PLUS) | ||
| 3249 | + { | ||
| 3250 | + if (GET_CODE (XEXP (src_addr, 1)) != CONST_INT) | ||
| 3251 | + return false; | ||
| 3252 | + offset = INTVAL (XEXP (src_addr, 1)); | ||
| 3253 | + src_addr = XEXP (src_addr, 0); | ||
| 3254 | + } | ||
| 3255 | + if (!REG_P (src_addr)) | ||
| 3256 | + return false; | ||
| 3257 | |||
| 3258 | for (; i < count; i++) | ||
| 3259 | { | ||
| 3260 | @@ -377,16 +396,28 @@ | ||
| 3261 | if (GET_CODE (elt) != SET | ||
| 3262 | || GET_CODE (SET_DEST (elt)) != REG | ||
| 3263 | || GET_MODE (SET_DEST (elt)) != SImode | ||
| 3264 | - || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base) | ||
| 3265 | + || REGNO (SET_DEST (elt)) <= dest_regno | ||
| 3266 | || GET_CODE (SET_SRC (elt)) != MEM | ||
| 3267 | || GET_MODE (SET_SRC (elt)) != SImode | ||
| 3268 | - || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | ||
| 3269 | - || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | ||
| 3270 | - || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | ||
| 3271 | - || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4) | ||
| 3272 | + || ((GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | ||
| 3273 | + || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | ||
| 3274 | + || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | ||
| 3275 | + || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != offset + (i - base) * 4) | ||
| 3276 | + && (!REG_P (XEXP (SET_SRC (elt), 0)) | ||
| 3277 | + || offset + (i - base) * 4 != 0))) | ||
| 3278 | return false; | ||
| 3279 | + dest_regno = REGNO (SET_DEST (elt)); | ||
| 3280 | + if (dest_regno == REGNO (src_addr)) | ||
| 3281 | + addr_reg_loaded = true; | ||
| 3282 | } | ||
| 3283 | - | ||
| 3284 | + /* For Thumb, we only have updating instructions. If the pattern does | ||
| 3285 | + not describe an update, it must be because the address register is | ||
| 3286 | + in the list of loaded registers - on the hardware, this has the effect | ||
| 3287 | + of overriding the update. */ | ||
| 3288 | + if (update && addr_reg_loaded) | ||
| 3289 | + return false; | ||
| 3290 | + if (TARGET_THUMB1) | ||
| 3291 | + return update || addr_reg_loaded; | ||
| 3292 | return true; | ||
| 3293 | }) | ||
| 3294 | |||
| 3295 | @@ -394,9 +425,9 @@ | ||
| 3296 | (match_code "parallel") | ||
| 3297 | { | ||
| 3298 | HOST_WIDE_INT count = XVECLEN (op, 0); | ||
| 3299 | - int src_regno; | ||
| 3300 | + unsigned src_regno; | ||
| 3301 | rtx dest_addr; | ||
| 3302 | - HOST_WIDE_INT i = 1, base = 0; | ||
| 3303 | + HOST_WIDE_INT i = 1, base = 0, offset = 0; | ||
| 3304 | rtx elt; | ||
| 3305 | |||
| 3306 | if (low_irq_latency) | ||
| 3307 | @@ -430,6 +461,16 @@ | ||
| 3308 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); | ||
| 3309 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); | ||
| 3310 | |||
| 3311 | + if (GET_CODE (dest_addr) == PLUS) | ||
| 3312 | + { | ||
| 3313 | + if (GET_CODE (XEXP (dest_addr, 1)) != CONST_INT) | ||
| 3314 | + return false; | ||
| 3315 | + offset = INTVAL (XEXP (dest_addr, 1)); | ||
| 3316 | + dest_addr = XEXP (dest_addr, 0); | ||
| 3317 | + } | ||
| 3318 | + if (!REG_P (dest_addr)) | ||
| 3319 | + return false; | ||
| 3320 | + | ||
| 3321 | for (; i < count; i++) | ||
| 3322 | { | ||
| 3323 | elt = XVECEXP (op, 0, i); | ||
| 3324 | @@ -437,14 +478,17 @@ | ||
| 3325 | if (GET_CODE (elt) != SET | ||
| 3326 | || GET_CODE (SET_SRC (elt)) != REG | ||
| 3327 | || GET_MODE (SET_SRC (elt)) != SImode | ||
| 3328 | - || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base) | ||
| 3329 | + || REGNO (SET_SRC (elt)) <= src_regno | ||
| 3330 | || GET_CODE (SET_DEST (elt)) != MEM | ||
| 3331 | || GET_MODE (SET_DEST (elt)) != SImode | ||
| 3332 | - || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | ||
| 3333 | - || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | ||
| 3334 | - || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | ||
| 3335 | - || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4) | ||
| 3336 | + || ((GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | ||
| 3337 | + || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | ||
| 3338 | + || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | ||
| 3339 | + || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != offset + (i - base) * 4) | ||
| 3340 | + && (!REG_P (XEXP (SET_DEST (elt), 0)) | ||
| 3341 | + || offset + (i - base) * 4 != 0))) | ||
| 3342 | return false; | ||
| 3343 | + src_regno = REGNO (SET_SRC (elt)); | ||
| 3344 | } | ||
| 3345 | |||
| 3346 | return true; | ||
| 3347 | |||
| 3348 | === modified file 'gcc/config/i386/i386.md' | ||
| 3349 | --- old/gcc/config/i386/i386.md 2011-01-05 12:12:18 +0000 | ||
| 3350 | +++ new/gcc/config/i386/i386.md 2011-01-05 18:20:37 +0000 | ||
| 3351 | @@ -20023,15 +20023,14 @@ | ||
| 3352 | ;; leal (%edx,%eax,4), %eax | ||
| 3353 | |||
| 3354 | (define_peephole2 | ||
| 3355 | - [(parallel [(set (match_operand 0 "register_operand" "") | ||
| 3356 | + [(match_scratch:SI 5 "r") | ||
| 3357 | + (parallel [(set (match_operand 0 "register_operand" "") | ||
| 3358 | (ashift (match_operand 1 "register_operand" "") | ||
| 3359 | (match_operand 2 "const_int_operand" ""))) | ||
| 3360 | (clobber (reg:CC FLAGS_REG))]) | ||
| 3361 | - (set (match_operand 3 "register_operand") | ||
| 3362 | - (match_operand 4 "x86_64_general_operand" "")) | ||
| 3363 | - (parallel [(set (match_operand 5 "register_operand" "") | ||
| 3364 | - (plus (match_operand 6 "register_operand" "") | ||
| 3365 | - (match_operand 7 "register_operand" ""))) | ||
| 3366 | + (parallel [(set (match_operand 3 "register_operand" "") | ||
| 3367 | + (plus (match_dup 0) | ||
| 3368 | + (match_operand 4 "x86_64_general_operand" ""))) | ||
| 3369 | (clobber (reg:CC FLAGS_REG))])] | ||
| 3370 | "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3 | ||
| 3371 | /* Validate MODE for lea. */ | ||
| 3372 | @@ -20041,30 +20040,21 @@ | ||
| 3373 | || GET_MODE (operands[0]) == SImode | ||
| 3374 | || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)) | ||
| 3375 | /* We reorder load and the shift. */ | ||
| 3376 | - && !rtx_equal_p (operands[1], operands[3]) | ||
| 3377 | - && !reg_overlap_mentioned_p (operands[0], operands[4]) | ||
| 3378 | - /* Last PLUS must consist of operand 0 and 3. */ | ||
| 3379 | - && !rtx_equal_p (operands[0], operands[3]) | ||
| 3380 | - && (rtx_equal_p (operands[3], operands[6]) | ||
| 3381 | - || rtx_equal_p (operands[3], operands[7])) | ||
| 3382 | - && (rtx_equal_p (operands[0], operands[6]) | ||
| 3383 | - || rtx_equal_p (operands[0], operands[7])) | ||
| 3384 | - /* The intermediate operand 0 must die or be same as output. */ | ||
| 3385 | - && (rtx_equal_p (operands[0], operands[5]) | ||
| 3386 | - || peep2_reg_dead_p (3, operands[0]))" | ||
| 3387 | - [(set (match_dup 3) (match_dup 4)) | ||
| 3388 | + && !reg_overlap_mentioned_p (operands[0], operands[4])" | ||
| 3389 | + [(set (match_dup 5) (match_dup 4)) | ||
| 3390 | (set (match_dup 0) (match_dup 1))] | ||
| 3391 | { | ||
| 3392 | - enum machine_mode mode = GET_MODE (operands[5]) == DImode ? DImode : SImode; | ||
| 3393 | + enum machine_mode mode = GET_MODE (operands[1]) == DImode ? DImode : SImode; | ||
| 3394 | int scale = 1 << INTVAL (operands[2]); | ||
| 3395 | rtx index = gen_lowpart (Pmode, operands[1]); | ||
| 3396 | - rtx base = gen_lowpart (Pmode, operands[3]); | ||
| 3397 | - rtx dest = gen_lowpart (mode, operands[5]); | ||
| 3398 | + rtx base = gen_lowpart (Pmode, operands[5]); | ||
| 3399 | + rtx dest = gen_lowpart (mode, operands[3]); | ||
| 3400 | |||
| 3401 | operands[1] = gen_rtx_PLUS (Pmode, base, | ||
| 3402 | gen_rtx_MULT (Pmode, index, GEN_INT (scale))); | ||
| 3403 | if (mode != Pmode) | ||
| 3404 | operands[1] = gen_rtx_SUBREG (mode, operands[1], 0); | ||
| 3405 | + operands[5] = base; | ||
| 3406 | operands[0] = dest; | ||
| 3407 | }) | ||
| 3408 | |||
| 3409 | |||
| 3410 | === modified file 'gcc/df-problems.c' | ||
| 3411 | --- old/gcc/df-problems.c 2010-11-16 22:17:17 +0000 | ||
| 3412 | +++ new/gcc/df-problems.c 2010-12-02 13:42:47 +0000 | ||
| 3413 | @@ -3748,9 +3748,22 @@ | ||
| 3414 | for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++) | ||
| 3415 | { | ||
| 3416 | df_ref def = *def_rec; | ||
| 3417 | - /* If the def is to only part of the reg, it does | ||
| 3418 | - not kill the other defs that reach here. */ | ||
| 3419 | - if (!(DF_REF_FLAGS (def) & (DF_REF_PARTIAL | DF_REF_CONDITIONAL))) | ||
| 3420 | + bitmap_set_bit (defs, DF_REF_REGNO (def)); | ||
| 3421 | + } | ||
| 3422 | +} | ||
| 3423 | + | ||
| 3424 | +/* Find the set of real DEFs, which are not clobbers, for INSN. */ | ||
| 3425 | + | ||
| 3426 | +void | ||
| 3427 | +df_simulate_find_noclobber_defs (rtx insn, bitmap defs) | ||
| 3428 | +{ | ||
| 3429 | + df_ref *def_rec; | ||
| 3430 | + unsigned int uid = INSN_UID (insn); | ||
| 3431 | + | ||
| 3432 | + for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++) | ||
| 3433 | + { | ||
| 3434 | + df_ref def = *def_rec; | ||
| 3435 | + if (!(DF_REF_FLAGS (def) & (DF_REF_MUST_CLOBBER | DF_REF_MAY_CLOBBER))) | ||
| 3436 | bitmap_set_bit (defs, DF_REF_REGNO (def)); | ||
| 3437 | } | ||
| 3438 | } | ||
| 3439 | @@ -3921,7 +3934,7 @@ | ||
| 3440 | { | ||
| 3441 | df_ref def = *def_rec; | ||
| 3442 | if (DF_REF_FLAGS (def) & DF_REF_AT_TOP) | ||
| 3443 | - bitmap_clear_bit (live, DF_REF_REGNO (def)); | ||
| 3444 | + bitmap_set_bit (live, DF_REF_REGNO (def)); | ||
| 3445 | } | ||
| 3446 | } | ||
| 3447 | |||
| 3448 | @@ -3942,7 +3955,7 @@ | ||
| 3449 | while here the scan is performed forwards! So, first assume that the | ||
| 3450 | def is live, and if this is not true REG_UNUSED notes will rectify the | ||
| 3451 | situation. */ | ||
| 3452 | - df_simulate_find_defs (insn, live); | ||
| 3453 | + df_simulate_find_noclobber_defs (insn, live); | ||
| 3454 | |||
| 3455 | /* Clear all of the registers that go dead. */ | ||
| 3456 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | ||
| 3457 | |||
| 3458 | === modified file 'gcc/df.h' | ||
| 3459 | --- old/gcc/df.h 2010-01-29 12:14:47 +0000 | ||
| 3460 | +++ new/gcc/df.h 2010-12-02 13:42:47 +0000 | ||
| 3461 | @@ -978,6 +978,7 @@ | ||
| 3462 | extern void df_md_add_problem (void); | ||
| 3463 | extern void df_md_simulate_artificial_defs_at_top (basic_block, bitmap); | ||
| 3464 | extern void df_md_simulate_one_insn (basic_block, rtx, bitmap); | ||
| 3465 | +extern void df_simulate_find_noclobber_defs (rtx, bitmap); | ||
| 3466 | extern void df_simulate_find_defs (rtx, bitmap); | ||
| 3467 | extern void df_simulate_defs (rtx, bitmap); | ||
| 3468 | extern void df_simulate_uses (rtx, bitmap); | ||
| 3469 | |||
| 3470 | === modified file 'gcc/fwprop.c' | ||
| 3471 | --- old/gcc/fwprop.c 2010-04-02 18:54:46 +0000 | ||
| 3472 | +++ new/gcc/fwprop.c 2010-11-16 12:32:34 +0000 | ||
| 3473 | @@ -228,7 +228,10 @@ | ||
| 3474 | |||
| 3475 | process_uses (df_get_artificial_uses (bb_index), DF_REF_AT_TOP); | ||
| 3476 | process_defs (df_get_artificial_defs (bb_index), DF_REF_AT_TOP); | ||
| 3477 | - df_simulate_initialize_forwards (bb, local_lr); | ||
| 3478 | + | ||
| 3479 | + /* We don't call df_simulate_initialize_forwards, as it may overestimate | ||
| 3480 | + the live registers if there are unused artificial defs. We prefer | ||
| 3481 | + liveness to be underestimated. */ | ||
| 3482 | |||
| 3483 | FOR_BB_INSNS (bb, insn) | ||
| 3484 | if (INSN_P (insn)) | ||
| 3485 | |||
| 3486 | === modified file 'gcc/genoutput.c' | ||
| 3487 | --- old/gcc/genoutput.c 2009-04-08 14:00:34 +0000 | ||
| 3488 | +++ new/gcc/genoutput.c 2010-11-16 12:32:34 +0000 | ||
| 3489 | @@ -266,6 +266,8 @@ | ||
| 3490 | |||
| 3491 | printf (" %d,\n", d->strict_low); | ||
| 3492 | |||
| 3493 | + printf (" %d,\n", d->constraint == NULL ? 1 : 0); | ||
| 3494 | + | ||
| 3495 | printf (" %d\n", d->eliminable); | ||
| 3496 | |||
| 3497 | printf(" },\n"); | ||
| 3498 | |||
| 3499 | === modified file 'gcc/genrecog.c' | ||
| 3500 | --- old/gcc/genrecog.c 2009-06-22 09:29:13 +0000 | ||
| 3501 | +++ new/gcc/genrecog.c 2010-11-16 12:32:34 +0000 | ||
| 3502 | @@ -1782,20 +1782,11 @@ | ||
| 3503 | int odepth = strlen (oldpos); | ||
| 3504 | int ndepth = strlen (newpos); | ||
| 3505 | int depth; | ||
| 3506 | - int old_has_insn, new_has_insn; | ||
| 3507 | |||
| 3508 | /* Pop up as many levels as necessary. */ | ||
| 3509 | for (depth = odepth; strncmp (oldpos, newpos, depth) != 0; --depth) | ||
| 3510 | continue; | ||
| 3511 | |||
| 3512 | - /* Hunt for the last [A-Z] in both strings. */ | ||
| 3513 | - for (old_has_insn = odepth - 1; old_has_insn >= 0; --old_has_insn) | ||
| 3514 | - if (ISUPPER (oldpos[old_has_insn])) | ||
| 3515 | - break; | ||
| 3516 | - for (new_has_insn = ndepth - 1; new_has_insn >= 0; --new_has_insn) | ||
| 3517 | - if (ISUPPER (newpos[new_has_insn])) | ||
| 3518 | - break; | ||
| 3519 | - | ||
| 3520 | /* Go down to desired level. */ | ||
| 3521 | while (depth < ndepth) | ||
| 3522 | { | ||
| 3523 | |||
| 3524 | === modified file 'gcc/ifcvt.c' | ||
| 3525 | --- old/gcc/ifcvt.c 2011-01-05 12:12:18 +0000 | ||
| 3526 | +++ new/gcc/ifcvt.c 2011-01-05 18:20:37 +0000 | ||
| 3527 | @@ -4011,6 +4011,7 @@ | ||
| 3528 | basic_block new_dest = dest_edge->dest; | ||
| 3529 | rtx head, end, jump, earliest = NULL_RTX, old_dest; | ||
| 3530 | bitmap merge_set = NULL; | ||
| 3531 | + bitmap merge_set_noclobber = NULL; | ||
| 3532 | /* Number of pending changes. */ | ||
| 3533 | int n_validated_changes = 0; | ||
| 3534 | rtx new_dest_label; | ||
| 3535 | @@ -4169,6 +4170,7 @@ | ||
| 3536 | end of the block. */ | ||
| 3537 | |||
| 3538 | merge_set = BITMAP_ALLOC (®_obstack); | ||
| 3539 | + merge_set_noclobber = BITMAP_ALLOC (®_obstack); | ||
| 3540 | |||
| 3541 | /* If we allocated new pseudos (e.g. in the conditional move | ||
| 3542 | expander called from noce_emit_cmove), we must resize the | ||
| 3543 | @@ -4187,6 +4189,7 @@ | ||
| 3544 | df_ref def = *def_rec; | ||
| 3545 | bitmap_set_bit (merge_set, DF_REF_REGNO (def)); | ||
| 3546 | } | ||
| 3547 | + df_simulate_find_noclobber_defs (insn, merge_set_noclobber); | ||
| 3548 | } | ||
| 3549 | } | ||
| 3550 | |||
| 3551 | @@ -4197,7 +4200,7 @@ | ||
| 3552 | unsigned i; | ||
| 3553 | bitmap_iterator bi; | ||
| 3554 | |||
| 3555 | - EXECUTE_IF_SET_IN_BITMAP (merge_set, 0, i, bi) | ||
| 3556 | + EXECUTE_IF_SET_IN_BITMAP (merge_set_noclobber, 0, i, bi) | ||
| 3557 | { | ||
| 3558 | if (i < FIRST_PSEUDO_REGISTER | ||
| 3559 | && ! fixed_regs[i] | ||
| 3560 | @@ -4233,7 +4236,7 @@ | ||
| 3561 | TEST_SET & DF_LIVE_IN (merge_bb) | ||
| 3562 | are empty. */ | ||
| 3563 | |||
| 3564 | - if (bitmap_intersect_p (merge_set, test_set) | ||
| 3565 | + if (bitmap_intersect_p (merge_set_noclobber, test_set) | ||
| 3566 | || bitmap_intersect_p (merge_set, test_live) | ||
| 3567 | || bitmap_intersect_p (test_set, df_get_live_in (merge_bb))) | ||
| 3568 | intersect = true; | ||
| 3569 | @@ -4320,6 +4323,7 @@ | ||
| 3570 | remove_reg_equal_equiv_notes_for_regno (i); | ||
| 3571 | |||
| 3572 | BITMAP_FREE (merge_set); | ||
| 3573 | + BITMAP_FREE (merge_set_noclobber); | ||
| 3574 | } | ||
| 3575 | |||
| 3576 | reorder_insns (head, end, PREV_INSN (earliest)); | ||
| 3577 | @@ -4340,7 +4344,10 @@ | ||
| 3578 | cancel_changes (0); | ||
| 3579 | fail: | ||
| 3580 | if (merge_set) | ||
| 3581 | - BITMAP_FREE (merge_set); | ||
| 3582 | + { | ||
| 3583 | + BITMAP_FREE (merge_set); | ||
| 3584 | + BITMAP_FREE (merge_set_noclobber); | ||
| 3585 | + } | ||
| 3586 | return FALSE; | ||
| 3587 | } | ||
| 3588 | |||
| 3589 | |||
| 3590 | === modified file 'gcc/recog.c' | ||
| 3591 | --- old/gcc/recog.c 2010-08-05 15:28:47 +0000 | ||
| 3592 | +++ new/gcc/recog.c 2010-11-16 12:32:34 +0000 | ||
| 3593 | @@ -2082,6 +2082,7 @@ | ||
| 3594 | recog_data.operand_loc, | ||
| 3595 | recog_data.constraints, | ||
| 3596 | recog_data.operand_mode, NULL); | ||
| 3597 | + memset (recog_data.is_operator, 0, sizeof recog_data.is_operator); | ||
| 3598 | if (noperands > 0) | ||
| 3599 | { | ||
| 3600 | const char *p = recog_data.constraints[0]; | ||
| 3601 | @@ -2111,6 +2112,7 @@ | ||
| 3602 | for (i = 0; i < noperands; i++) | ||
| 3603 | { | ||
| 3604 | recog_data.constraints[i] = insn_data[icode].operand[i].constraint; | ||
| 3605 | + recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator; | ||
| 3606 | recog_data.operand_mode[i] = insn_data[icode].operand[i].mode; | ||
| 3607 | /* VOIDmode match_operands gets mode from their real operand. */ | ||
| 3608 | if (recog_data.operand_mode[i] == VOIDmode) | ||
| 3609 | @@ -2909,6 +2911,10 @@ | ||
| 3610 | |||
| 3611 | static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1]; | ||
| 3612 | static int peep2_current; | ||
| 3613 | + | ||
| 3614 | +static bool peep2_do_rebuild_jump_labels; | ||
| 3615 | +static bool peep2_do_cleanup_cfg; | ||
| 3616 | + | ||
| 3617 | /* The number of instructions available to match a peep2. */ | ||
| 3618 | int peep2_current_count; | ||
| 3619 | |||
| 3620 | @@ -2917,6 +2923,16 @@ | ||
| 3621 | DF_LIVE_OUT for the block. */ | ||
| 3622 | #define PEEP2_EOB pc_rtx | ||
| 3623 | |||
| 3624 | +/* Wrap N to fit into the peep2_insn_data buffer. */ | ||
| 3625 | + | ||
| 3626 | +static int | ||
| 3627 | +peep2_buf_position (int n) | ||
| 3628 | +{ | ||
| 3629 | + if (n >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3630 | + n -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3631 | + return n; | ||
| 3632 | +} | ||
| 3633 | + | ||
| 3634 | /* Return the Nth non-note insn after `current', or return NULL_RTX if it | ||
| 3635 | does not exist. Used by the recognizer to find the next insn to match | ||
| 3636 | in a multi-insn pattern. */ | ||
| 3637 | @@ -2926,9 +2942,7 @@ | ||
| 3638 | { | ||
| 3639 | gcc_assert (n <= peep2_current_count); | ||
| 3640 | |||
| 3641 | - n += peep2_current; | ||
| 3642 | - if (n >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3643 | - n -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3644 | + n = peep2_buf_position (peep2_current + n); | ||
| 3645 | |||
| 3646 | return peep2_insn_data[n].insn; | ||
| 3647 | } | ||
| 3648 | @@ -2941,9 +2955,7 @@ | ||
| 3649 | { | ||
| 3650 | gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1); | ||
| 3651 | |||
| 3652 | - ofs += peep2_current; | ||
| 3653 | - if (ofs >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3654 | - ofs -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3655 | + ofs = peep2_buf_position (peep2_current + ofs); | ||
| 3656 | |||
| 3657 | gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX); | ||
| 3658 | |||
| 3659 | @@ -2959,9 +2971,7 @@ | ||
| 3660 | |||
| 3661 | gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1); | ||
| 3662 | |||
| 3663 | - ofs += peep2_current; | ||
| 3664 | - if (ofs >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3665 | - ofs -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3666 | + ofs = peep2_buf_position (peep2_current + ofs); | ||
| 3667 | |||
| 3668 | gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX); | ||
| 3669 | |||
| 3670 | @@ -2996,12 +3006,8 @@ | ||
| 3671 | gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1); | ||
| 3672 | gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1); | ||
| 3673 | |||
| 3674 | - from += peep2_current; | ||
| 3675 | - if (from >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3676 | - from -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3677 | - to += peep2_current; | ||
| 3678 | - if (to >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3679 | - to -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3680 | + from = peep2_buf_position (peep2_current + from); | ||
| 3681 | + to = peep2_buf_position (peep2_current + to); | ||
| 3682 | |||
| 3683 | gcc_assert (peep2_insn_data[from].insn != NULL_RTX); | ||
| 3684 | REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before); | ||
| 3685 | @@ -3010,8 +3016,7 @@ | ||
| 3686 | { | ||
| 3687 | HARD_REG_SET this_live; | ||
| 3688 | |||
| 3689 | - if (++from >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3690 | - from = 0; | ||
| 3691 | + from = peep2_buf_position (from + 1); | ||
| 3692 | gcc_assert (peep2_insn_data[from].insn != NULL_RTX); | ||
| 3693 | REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before); | ||
| 3694 | IOR_HARD_REG_SET (live, this_live); | ||
| 3695 | @@ -3104,19 +3109,234 @@ | ||
| 3696 | COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live); | ||
| 3697 | } | ||
| 3698 | |||
| 3699 | +/* While scanning basic block BB, we found a match of length MATCH_LEN, | ||
| 3700 | + starting at INSN. Perform the replacement, removing the old insns and | ||
| 3701 | + replacing them with ATTEMPT. Returns the last insn emitted. */ | ||
| 3702 | + | ||
| 3703 | +static rtx | ||
| 3704 | +peep2_attempt (basic_block bb, rtx insn, int match_len, rtx attempt) | ||
| 3705 | +{ | ||
| 3706 | + int i; | ||
| 3707 | + rtx last, note, before_try, x; | ||
| 3708 | + bool was_call = false; | ||
| 3709 | + | ||
| 3710 | + /* If we are splitting a CALL_INSN, look for the CALL_INSN | ||
| 3711 | + in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other | ||
| 3712 | + cfg-related call notes. */ | ||
| 3713 | + for (i = 0; i <= match_len; ++i) | ||
| 3714 | + { | ||
| 3715 | + int j; | ||
| 3716 | + rtx old_insn, new_insn, note; | ||
| 3717 | + | ||
| 3718 | + j = peep2_buf_position (peep2_current + i); | ||
| 3719 | + old_insn = peep2_insn_data[j].insn; | ||
| 3720 | + if (!CALL_P (old_insn)) | ||
| 3721 | + continue; | ||
| 3722 | + was_call = true; | ||
| 3723 | + | ||
| 3724 | + new_insn = attempt; | ||
| 3725 | + while (new_insn != NULL_RTX) | ||
| 3726 | + { | ||
| 3727 | + if (CALL_P (new_insn)) | ||
| 3728 | + break; | ||
| 3729 | + new_insn = NEXT_INSN (new_insn); | ||
| 3730 | + } | ||
| 3731 | + | ||
| 3732 | + gcc_assert (new_insn != NULL_RTX); | ||
| 3733 | + | ||
| 3734 | + CALL_INSN_FUNCTION_USAGE (new_insn) | ||
| 3735 | + = CALL_INSN_FUNCTION_USAGE (old_insn); | ||
| 3736 | + | ||
| 3737 | + for (note = REG_NOTES (old_insn); | ||
| 3738 | + note; | ||
| 3739 | + note = XEXP (note, 1)) | ||
| 3740 | + switch (REG_NOTE_KIND (note)) | ||
| 3741 | + { | ||
| 3742 | + case REG_NORETURN: | ||
| 3743 | + case REG_SETJMP: | ||
| 3744 | + add_reg_note (new_insn, REG_NOTE_KIND (note), | ||
| 3745 | + XEXP (note, 0)); | ||
| 3746 | + break; | ||
| 3747 | + default: | ||
| 3748 | + /* Discard all other reg notes. */ | ||
| 3749 | + break; | ||
| 3750 | + } | ||
| 3751 | + | ||
| 3752 | + /* Croak if there is another call in the sequence. */ | ||
| 3753 | + while (++i <= match_len) | ||
| 3754 | + { | ||
| 3755 | + j = peep2_buf_position (peep2_current + i); | ||
| 3756 | + old_insn = peep2_insn_data[j].insn; | ||
| 3757 | + gcc_assert (!CALL_P (old_insn)); | ||
| 3758 | + } | ||
| 3759 | + break; | ||
| 3760 | + } | ||
| 3761 | + | ||
| 3762 | + i = peep2_buf_position (peep2_current + match_len); | ||
| 3763 | + | ||
| 3764 | + note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX); | ||
| 3765 | + | ||
| 3766 | + /* Replace the old sequence with the new. */ | ||
| 3767 | + last = emit_insn_after_setloc (attempt, | ||
| 3768 | + peep2_insn_data[i].insn, | ||
| 3769 | + INSN_LOCATOR (peep2_insn_data[i].insn)); | ||
| 3770 | + before_try = PREV_INSN (insn); | ||
| 3771 | + delete_insn_chain (insn, peep2_insn_data[i].insn, false); | ||
| 3772 | + | ||
| 3773 | + /* Re-insert the EH_REGION notes. */ | ||
| 3774 | + if (note || (was_call && nonlocal_goto_handler_labels)) | ||
| 3775 | + { | ||
| 3776 | + edge eh_edge; | ||
| 3777 | + edge_iterator ei; | ||
| 3778 | + | ||
| 3779 | + FOR_EACH_EDGE (eh_edge, ei, bb->succs) | ||
| 3780 | + if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL)) | ||
| 3781 | + break; | ||
| 3782 | + | ||
| 3783 | + if (note) | ||
| 3784 | + copy_reg_eh_region_note_backward (note, last, before_try); | ||
| 3785 | + | ||
| 3786 | + if (eh_edge) | ||
| 3787 | + for (x = last; x != before_try; x = PREV_INSN (x)) | ||
| 3788 | + if (x != BB_END (bb) | ||
| 3789 | + && (can_throw_internal (x) | ||
| 3790 | + || can_nonlocal_goto (x))) | ||
| 3791 | + { | ||
| 3792 | + edge nfte, nehe; | ||
| 3793 | + int flags; | ||
| 3794 | + | ||
| 3795 | + nfte = split_block (bb, x); | ||
| 3796 | + flags = (eh_edge->flags | ||
| 3797 | + & (EDGE_EH | EDGE_ABNORMAL)); | ||
| 3798 | + if (CALL_P (x)) | ||
| 3799 | + flags |= EDGE_ABNORMAL_CALL; | ||
| 3800 | + nehe = make_edge (nfte->src, eh_edge->dest, | ||
| 3801 | + flags); | ||
| 3802 | + | ||
| 3803 | + nehe->probability = eh_edge->probability; | ||
| 3804 | + nfte->probability | ||
| 3805 | + = REG_BR_PROB_BASE - nehe->probability; | ||
| 3806 | + | ||
| 3807 | + peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest); | ||
| 3808 | + bb = nfte->src; | ||
| 3809 | + eh_edge = nehe; | ||
| 3810 | + } | ||
| 3811 | + | ||
| 3812 | + /* Converting possibly trapping insn to non-trapping is | ||
| 3813 | + possible. Zap dummy outgoing edges. */ | ||
| 3814 | + peep2_do_cleanup_cfg |= purge_dead_edges (bb); | ||
| 3815 | + } | ||
| 3816 | + | ||
| 3817 | + /* If we generated a jump instruction, it won't have | ||
| 3818 | + JUMP_LABEL set. Recompute after we're done. */ | ||
| 3819 | + for (x = last; x != before_try; x = PREV_INSN (x)) | ||
| 3820 | + if (JUMP_P (x)) | ||
| 3821 | + { | ||
| 3822 | + peep2_do_rebuild_jump_labels = true; | ||
| 3823 | + break; | ||
| 3824 | + } | ||
| 3825 | + | ||
| 3826 | + return last; | ||
| 3827 | +} | ||
| 3828 | + | ||
| 3829 | +/* After performing a replacement in basic block BB, fix up the life | ||
| 3830 | + information in our buffer. LAST is the last of the insns that we | ||
| 3831 | + emitted as a replacement. PREV is the insn before the start of | ||
| 3832 | + the replacement. MATCH_LEN is the number of instructions that were | ||
| 3833 | + matched, and which now need to be replaced in the buffer. */ | ||
| 3834 | + | ||
| 3835 | +static void | ||
| 3836 | +peep2_update_life (basic_block bb, int match_len, rtx last, rtx prev) | ||
| 3837 | +{ | ||
| 3838 | + int i = peep2_buf_position (peep2_current + match_len + 1); | ||
| 3839 | + rtx x; | ||
| 3840 | + regset_head live; | ||
| 3841 | + | ||
| 3842 | + INIT_REG_SET (&live); | ||
| 3843 | + COPY_REG_SET (&live, peep2_insn_data[i].live_before); | ||
| 3844 | + | ||
| 3845 | + gcc_assert (peep2_current_count >= match_len + 1); | ||
| 3846 | + peep2_current_count -= match_len + 1; | ||
| 3847 | + | ||
| 3848 | + x = last; | ||
| 3849 | + do | ||
| 3850 | + { | ||
| 3851 | + if (INSN_P (x)) | ||
| 3852 | + { | ||
| 3853 | + df_insn_rescan (x); | ||
| 3854 | + if (peep2_current_count < MAX_INSNS_PER_PEEP2) | ||
| 3855 | + { | ||
| 3856 | + peep2_current_count++; | ||
| 3857 | + if (--i < 0) | ||
| 3858 | + i = MAX_INSNS_PER_PEEP2; | ||
| 3859 | + peep2_insn_data[i].insn = x; | ||
| 3860 | + df_simulate_one_insn_backwards (bb, x, &live); | ||
| 3861 | + COPY_REG_SET (peep2_insn_data[i].live_before, &live); | ||
| 3862 | + } | ||
| 3863 | + } | ||
| 3864 | + x = PREV_INSN (x); | ||
| 3865 | + } | ||
| 3866 | + while (x != prev); | ||
| 3867 | + CLEAR_REG_SET (&live); | ||
| 3868 | + | ||
| 3869 | + peep2_current = i; | ||
| 3870 | +} | ||
| 3871 | + | ||
| 3872 | +/* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible. | ||
| 3873 | + Return true if we added it, false otherwise. The caller will try to match | ||
| 3874 | + peepholes against the buffer if we return false; otherwise it will try to | ||
| 3875 | + add more instructions to the buffer. */ | ||
| 3876 | + | ||
| 3877 | +static bool | ||
| 3878 | +peep2_fill_buffer (basic_block bb, rtx insn, regset live) | ||
| 3879 | +{ | ||
| 3880 | + int pos; | ||
| 3881 | + | ||
| 3882 | + /* Once we have filled the maximum number of insns the buffer can hold, | ||
| 3883 | + allow the caller to match the insns against peepholes. We wait until | ||
| 3884 | + the buffer is full in case the target has similar peepholes of different | ||
| 3885 | + length; we always want to match the longest if possible. */ | ||
| 3886 | + if (peep2_current_count == MAX_INSNS_PER_PEEP2) | ||
| 3887 | + return false; | ||
| 3888 | + | ||
| 3889 | + /* If an insn has RTX_FRAME_RELATED_P set, peephole substitution would lose | ||
| 3890 | + the REG_FRAME_RELATED_EXPR that is attached. */ | ||
| 3891 | + if (RTX_FRAME_RELATED_P (insn)) | ||
| 3892 | + { | ||
| 3893 | + /* Let the buffer drain first. */ | ||
| 3894 | + if (peep2_current_count > 0) | ||
| 3895 | + return false; | ||
| 3896 | + /* Step over the insn then return true without adding the insn | ||
| 3897 | + to the buffer; this will cause us to process the next | ||
| 3898 | + insn. */ | ||
| 3899 | + df_simulate_one_insn_forwards (bb, insn, live); | ||
| 3900 | + return true; | ||
| 3901 | + } | ||
| 3902 | + | ||
| 3903 | + pos = peep2_buf_position (peep2_current + peep2_current_count); | ||
| 3904 | + peep2_insn_data[pos].insn = insn; | ||
| 3905 | + COPY_REG_SET (peep2_insn_data[pos].live_before, live); | ||
| 3906 | + peep2_current_count++; | ||
| 3907 | + | ||
| 3908 | + df_simulate_one_insn_forwards (bb, insn, live); | ||
| 3909 | + return true; | ||
| 3910 | +} | ||
| 3911 | + | ||
| 3912 | /* Perform the peephole2 optimization pass. */ | ||
| 3913 | |||
| 3914 | static void | ||
| 3915 | peephole2_optimize (void) | ||
| 3916 | { | ||
| 3917 | - rtx insn, prev; | ||
| 3918 | + rtx insn; | ||
| 3919 | bitmap live; | ||
| 3920 | int i; | ||
| 3921 | basic_block bb; | ||
| 3922 | - bool do_cleanup_cfg = false; | ||
| 3923 | - bool do_rebuild_jump_labels = false; | ||
| 3924 | + | ||
| 3925 | + peep2_do_cleanup_cfg = false; | ||
| 3926 | + peep2_do_rebuild_jump_labels = false; | ||
| 3927 | |||
| 3928 | df_set_flags (DF_LR_RUN_DCE); | ||
| 3929 | + df_note_add_problem (); | ||
| 3930 | df_analyze (); | ||
| 3931 | |||
| 3932 | /* Initialize the regsets we're going to use. */ | ||
| 3933 | @@ -3126,214 +3346,59 @@ | ||
| 3934 | |||
| 3935 | FOR_EACH_BB_REVERSE (bb) | ||
| 3936 | { | ||
| 3937 | + bool past_end = false; | ||
| 3938 | + int pos; | ||
| 3939 | + | ||
| 3940 | rtl_profile_for_bb (bb); | ||
| 3941 | |||
| 3942 | /* Start up propagation. */ | ||
| 3943 | - bitmap_copy (live, DF_LR_OUT (bb)); | ||
| 3944 | - df_simulate_initialize_backwards (bb, live); | ||
| 3945 | + bitmap_copy (live, DF_LR_IN (bb)); | ||
| 3946 | + df_simulate_initialize_forwards (bb, live); | ||
| 3947 | peep2_reinit_state (live); | ||
| 3948 | |||
| 3949 | - for (insn = BB_END (bb); ; insn = prev) | ||
| 3950 | + insn = BB_HEAD (bb); | ||
| 3951 | + for (;;) | ||
| 3952 | { | ||
| 3953 | - prev = PREV_INSN (insn); | ||
| 3954 | - if (NONDEBUG_INSN_P (insn)) | ||
| 3955 | + rtx attempt, head; | ||
| 3956 | + int match_len; | ||
| 3957 | + | ||
| 3958 | + if (!past_end && !NONDEBUG_INSN_P (insn)) | ||
| 3959 | { | ||
| 3960 | - rtx attempt, before_try, x; | ||
| 3961 | - int match_len; | ||
| 3962 | - rtx note; | ||
| 3963 | - bool was_call = false; | ||
| 3964 | - | ||
| 3965 | - /* Record this insn. */ | ||
| 3966 | - if (--peep2_current < 0) | ||
| 3967 | - peep2_current = MAX_INSNS_PER_PEEP2; | ||
| 3968 | - if (peep2_current_count < MAX_INSNS_PER_PEEP2 | ||
| 3969 | - && peep2_insn_data[peep2_current].insn == NULL_RTX) | ||
| 3970 | - peep2_current_count++; | ||
| 3971 | - peep2_insn_data[peep2_current].insn = insn; | ||
| 3972 | - df_simulate_one_insn_backwards (bb, insn, live); | ||
| 3973 | - COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live); | ||
| 3974 | - | ||
| 3975 | - if (RTX_FRAME_RELATED_P (insn)) | ||
| 3976 | - { | ||
| 3977 | - /* If an insn has RTX_FRAME_RELATED_P set, peephole | ||
| 3978 | - substitution would lose the | ||
| 3979 | - REG_FRAME_RELATED_EXPR that is attached. */ | ||
| 3980 | - peep2_reinit_state (live); | ||
| 3981 | - attempt = NULL; | ||
| 3982 | - } | ||
| 3983 | - else | ||
| 3984 | - /* Match the peephole. */ | ||
| 3985 | - attempt = peephole2_insns (PATTERN (insn), insn, &match_len); | ||
| 3986 | - | ||
| 3987 | - if (attempt != NULL) | ||
| 3988 | - { | ||
| 3989 | - /* If we are splitting a CALL_INSN, look for the CALL_INSN | ||
| 3990 | - in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other | ||
| 3991 | - cfg-related call notes. */ | ||
| 3992 | - for (i = 0; i <= match_len; ++i) | ||
| 3993 | - { | ||
| 3994 | - int j; | ||
| 3995 | - rtx old_insn, new_insn, note; | ||
| 3996 | - | ||
| 3997 | - j = i + peep2_current; | ||
| 3998 | - if (j >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3999 | - j -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 4000 | - old_insn = peep2_insn_data[j].insn; | ||
| 4001 | - if (!CALL_P (old_insn)) | ||
| 4002 | - continue; | ||
| 4003 | - was_call = true; | ||
| 4004 | - | ||
| 4005 | - new_insn = attempt; | ||
| 4006 | - while (new_insn != NULL_RTX) | ||
| 4007 | - { | ||
| 4008 | - if (CALL_P (new_insn)) | ||
| 4009 | - break; | ||
| 4010 | - new_insn = NEXT_INSN (new_insn); | ||
| 4011 | - } | ||
| 4012 | - | ||
| 4013 | - gcc_assert (new_insn != NULL_RTX); | ||
| 4014 | - | ||
| 4015 | - CALL_INSN_FUNCTION_USAGE (new_insn) | ||
| 4016 | - = CALL_INSN_FUNCTION_USAGE (old_insn); | ||
| 4017 | - | ||
| 4018 | - for (note = REG_NOTES (old_insn); | ||
| 4019 | - note; | ||
| 4020 | - note = XEXP (note, 1)) | ||
| 4021 | - switch (REG_NOTE_KIND (note)) | ||
| 4022 | - { | ||
| 4023 | - case REG_NORETURN: | ||
| 4024 | - case REG_SETJMP: | ||
| 4025 | - add_reg_note (new_insn, REG_NOTE_KIND (note), | ||
| 4026 | - XEXP (note, 0)); | ||
| 4027 | - break; | ||
| 4028 | - default: | ||
| 4029 | - /* Discard all other reg notes. */ | ||
| 4030 | - break; | ||
| 4031 | - } | ||
| 4032 | - | ||
| 4033 | - /* Croak if there is another call in the sequence. */ | ||
| 4034 | - while (++i <= match_len) | ||
| 4035 | - { | ||
| 4036 | - j = i + peep2_current; | ||
| 4037 | - if (j >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 4038 | - j -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 4039 | - old_insn = peep2_insn_data[j].insn; | ||
| 4040 | - gcc_assert (!CALL_P (old_insn)); | ||
| 4041 | - } | ||
| 4042 | - break; | ||
| 4043 | - } | ||
| 4044 | - | ||
| 4045 | - i = match_len + peep2_current; | ||
| 4046 | - if (i >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 4047 | - i -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 4048 | - | ||
| 4049 | - note = find_reg_note (peep2_insn_data[i].insn, | ||
| 4050 | - REG_EH_REGION, NULL_RTX); | ||
| 4051 | - | ||
| 4052 | - /* Replace the old sequence with the new. */ | ||
| 4053 | - attempt = emit_insn_after_setloc (attempt, | ||
| 4054 | - peep2_insn_data[i].insn, | ||
| 4055 | - INSN_LOCATOR (peep2_insn_data[i].insn)); | ||
| 4056 | - before_try = PREV_INSN (insn); | ||
| 4057 | - delete_insn_chain (insn, peep2_insn_data[i].insn, false); | ||
| 4058 | - | ||
| 4059 | - /* Re-insert the EH_REGION notes. */ | ||
| 4060 | - if (note || (was_call && nonlocal_goto_handler_labels)) | ||
| 4061 | - { | ||
| 4062 | - edge eh_edge; | ||
| 4063 | - edge_iterator ei; | ||
| 4064 | - | ||
| 4065 | - FOR_EACH_EDGE (eh_edge, ei, bb->succs) | ||
| 4066 | - if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL)) | ||
| 4067 | - break; | ||
| 4068 | - | ||
| 4069 | - if (note) | ||
| 4070 | - copy_reg_eh_region_note_backward (note, attempt, | ||
| 4071 | - before_try); | ||
| 4072 | - | ||
| 4073 | - if (eh_edge) | ||
| 4074 | - for (x = attempt ; x != before_try ; x = PREV_INSN (x)) | ||
| 4075 | - if (x != BB_END (bb) | ||
| 4076 | - && (can_throw_internal (x) | ||
| 4077 | - || can_nonlocal_goto (x))) | ||
| 4078 | - { | ||
| 4079 | - edge nfte, nehe; | ||
| 4080 | - int flags; | ||
| 4081 | - | ||
| 4082 | - nfte = split_block (bb, x); | ||
| 4083 | - flags = (eh_edge->flags | ||
| 4084 | - & (EDGE_EH | EDGE_ABNORMAL)); | ||
| 4085 | - if (CALL_P (x)) | ||
| 4086 | - flags |= EDGE_ABNORMAL_CALL; | ||
| 4087 | - nehe = make_edge (nfte->src, eh_edge->dest, | ||
| 4088 | - flags); | ||
| 4089 | - | ||
| 4090 | - nehe->probability = eh_edge->probability; | ||
| 4091 | - nfte->probability | ||
| 4092 | - = REG_BR_PROB_BASE - nehe->probability; | ||
| 4093 | - | ||
| 4094 | - do_cleanup_cfg |= purge_dead_edges (nfte->dest); | ||
| 4095 | - bb = nfte->src; | ||
| 4096 | - eh_edge = nehe; | ||
| 4097 | - } | ||
| 4098 | - | ||
| 4099 | - /* Converting possibly trapping insn to non-trapping is | ||
| 4100 | - possible. Zap dummy outgoing edges. */ | ||
| 4101 | - do_cleanup_cfg |= purge_dead_edges (bb); | ||
| 4102 | - } | ||
| 4103 | - | ||
| 4104 | - if (targetm.have_conditional_execution ()) | ||
| 4105 | - { | ||
| 4106 | - for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) | ||
| 4107 | - peep2_insn_data[i].insn = NULL_RTX; | ||
| 4108 | - peep2_insn_data[peep2_current].insn = PEEP2_EOB; | ||
| 4109 | - peep2_current_count = 0; | ||
| 4110 | - } | ||
| 4111 | - else | ||
| 4112 | - { | ||
| 4113 | - /* Back up lifetime information past the end of the | ||
| 4114 | - newly created sequence. */ | ||
| 4115 | - if (++i >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 4116 | - i = 0; | ||
| 4117 | - bitmap_copy (live, peep2_insn_data[i].live_before); | ||
| 4118 | - | ||
| 4119 | - /* Update life information for the new sequence. */ | ||
| 4120 | - x = attempt; | ||
| 4121 | - do | ||
| 4122 | - { | ||
| 4123 | - if (INSN_P (x)) | ||
| 4124 | - { | ||
| 4125 | - if (--i < 0) | ||
| 4126 | - i = MAX_INSNS_PER_PEEP2; | ||
| 4127 | - if (peep2_current_count < MAX_INSNS_PER_PEEP2 | ||
| 4128 | - && peep2_insn_data[i].insn == NULL_RTX) | ||
| 4129 | - peep2_current_count++; | ||
| 4130 | - peep2_insn_data[i].insn = x; | ||
| 4131 | - df_insn_rescan (x); | ||
| 4132 | - df_simulate_one_insn_backwards (bb, x, live); | ||
| 4133 | - bitmap_copy (peep2_insn_data[i].live_before, | ||
| 4134 | - live); | ||
| 4135 | - } | ||
| 4136 | - x = PREV_INSN (x); | ||
| 4137 | - } | ||
| 4138 | - while (x != prev); | ||
| 4139 | - | ||
| 4140 | - peep2_current = i; | ||
| 4141 | - } | ||
| 4142 | - | ||
| 4143 | - /* If we generated a jump instruction, it won't have | ||
| 4144 | - JUMP_LABEL set. Recompute after we're done. */ | ||
| 4145 | - for (x = attempt; x != before_try; x = PREV_INSN (x)) | ||
| 4146 | - if (JUMP_P (x)) | ||
| 4147 | - { | ||
| 4148 | - do_rebuild_jump_labels = true; | ||
| 4149 | - break; | ||
| 4150 | - } | ||
| 4151 | - } | ||
| 4152 | + next_insn: | ||
| 4153 | + insn = NEXT_INSN (insn); | ||
| 4154 | + if (insn == NEXT_INSN (BB_END (bb))) | ||
| 4155 | + past_end = true; | ||
| 4156 | + continue; | ||
| 4157 | } | ||
| 4158 | + if (!past_end && peep2_fill_buffer (bb, insn, live)) | ||
| 4159 | + goto next_insn; | ||
| 4160 | |||
| 4161 | - if (insn == BB_HEAD (bb)) | ||
| 4162 | + /* If we did not fill an empty buffer, it signals the end of the | ||
| 4163 | + block. */ | ||
| 4164 | + if (peep2_current_count == 0) | ||
| 4165 | break; | ||
| 4166 | + | ||
| 4167 | + /* The buffer filled to the current maximum, so try to match. */ | ||
| 4168 | + | ||
| 4169 | + pos = peep2_buf_position (peep2_current + peep2_current_count); | ||
| 4170 | + peep2_insn_data[pos].insn = PEEP2_EOB; | ||
| 4171 | + COPY_REG_SET (peep2_insn_data[pos].live_before, live); | ||
| 4172 | + | ||
| 4173 | + /* Match the peephole. */ | ||
| 4174 | + head = peep2_insn_data[peep2_current].insn; | ||
| 4175 | + attempt = peephole2_insns (PATTERN (head), head, &match_len); | ||
| 4176 | + if (attempt != NULL) | ||
| 4177 | + { | ||
| 4178 | + rtx last; | ||
| 4179 | + last = peep2_attempt (bb, head, match_len, attempt); | ||
| 4180 | + peep2_update_life (bb, match_len, last, PREV_INSN (attempt)); | ||
| 4181 | + } | ||
| 4182 | + else | ||
| 4183 | + { | ||
| 4184 | + /* If no match, advance the buffer by one insn. */ | ||
| 4185 | + peep2_current = peep2_buf_position (peep2_current + 1); | ||
| 4186 | + peep2_current_count--; | ||
| 4187 | + } | ||
| 4188 | } | ||
| 4189 | } | ||
| 4190 | |||
| 4191 | @@ -3341,7 +3406,7 @@ | ||
| 4192 | for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) | ||
| 4193 | BITMAP_FREE (peep2_insn_data[i].live_before); | ||
| 4194 | BITMAP_FREE (live); | ||
| 4195 | - if (do_rebuild_jump_labels) | ||
| 4196 | + if (peep2_do_rebuild_jump_labels) | ||
| 4197 | rebuild_jump_labels (get_insns ()); | ||
| 4198 | } | ||
| 4199 | #endif /* HAVE_peephole2 */ | ||
| 4200 | |||
| 4201 | === modified file 'gcc/recog.h' | ||
| 4202 | --- old/gcc/recog.h 2009-10-26 21:55:59 +0000 | ||
| 4203 | +++ new/gcc/recog.h 2010-11-16 12:32:34 +0000 | ||
| 4204 | @@ -194,6 +194,9 @@ | ||
| 4205 | /* Gives the constraint string for operand N. */ | ||
| 4206 | const char *constraints[MAX_RECOG_OPERANDS]; | ||
| 4207 | |||
| 4208 | + /* Nonzero if operand N is a match_operator or a match_parallel. */ | ||
| 4209 | + char is_operator[MAX_RECOG_OPERANDS]; | ||
| 4210 | + | ||
| 4211 | /* Gives the mode of operand N. */ | ||
| 4212 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; | ||
| 4213 | |||
| 4214 | @@ -260,6 +263,8 @@ | ||
| 4215 | |||
| 4216 | const char strict_low; | ||
| 4217 | |||
| 4218 | + const char is_operator; | ||
| 4219 | + | ||
| 4220 | const char eliminable; | ||
| 4221 | }; | ||
| 4222 | |||
| 4223 | |||
| 4224 | === modified file 'gcc/reload.c' | ||
| 4225 | --- old/gcc/reload.c 2009-12-21 16:32:44 +0000 | ||
| 4226 | +++ new/gcc/reload.c 2010-11-16 12:32:34 +0000 | ||
| 4227 | @@ -3631,7 +3631,7 @@ | ||
| 4228 | || modified[j] != RELOAD_WRITE) | ||
| 4229 | && j != i | ||
| 4230 | /* Ignore things like match_operator operands. */ | ||
| 4231 | - && *recog_data.constraints[j] != 0 | ||
| 4232 | + && !recog_data.is_operator[j] | ||
| 4233 | /* Don't count an input operand that is constrained to match | ||
| 4234 | the early clobber operand. */ | ||
| 4235 | && ! (this_alternative_matches[j] == i | ||
| 4236 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99464.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99464.patch deleted file mode 100644 index e8c8e6388..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99464.patch +++ /dev/null | |||
| @@ -1,157 +0,0 @@ | |||
| 1 | LP: #681138 | ||
| 2 | Backport from mainline: | ||
| 3 | |||
| 4 | gcc/ | ||
| 5 | * config/arm/sync.md (sync_clobber, sync_t2_reqd): New code attribute. | ||
| 6 | (arm_sync_old_<sync_optab>si, arm_sync_old_<sync_optab><mode>): Use | ||
| 7 | the sync_clobber and sync_t2_reqd code attributes. | ||
| 8 | * config/arm/arm.c (arm_output_sync_loop): Reverse the operation if | ||
| 9 | the t2 argument is NULL. | ||
| 10 | |||
| 11 | === modified file 'gcc/config/arm/arm.c' | ||
| 12 | Index: gcc-4_5-branch/gcc/config/arm/arm.c | ||
| 13 | =================================================================== | ||
| 14 | --- gcc-4_5-branch.orig/gcc/config/arm/arm.c | ||
| 15 | +++ gcc-4_5-branch/gcc/config/arm/arm.c | ||
| 16 | @@ -23098,10 +23098,46 @@ arm_output_sync_loop (emit_f emit, | ||
| 17 | break; | ||
| 18 | } | ||
| 19 | |||
| 20 | - arm_output_strex (emit, mode, "", t2, t1, memory); | ||
| 21 | - operands[0] = t2; | ||
| 22 | - arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0"); | ||
| 23 | - arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", LOCAL_LABEL_PREFIX); | ||
| 24 | + if (t2) | ||
| 25 | + { | ||
| 26 | + arm_output_strex (emit, mode, "", t2, t1, memory); | ||
| 27 | + operands[0] = t2; | ||
| 28 | + arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0"); | ||
| 29 | + arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", | ||
| 30 | + LOCAL_LABEL_PREFIX); | ||
| 31 | + } | ||
| 32 | + else | ||
| 33 | + { | ||
| 34 | + /* Use old_value for the return value because for some operations | ||
| 35 | + the old_value can easily be restored. This saves one register. */ | ||
| 36 | + arm_output_strex (emit, mode, "", old_value, t1, memory); | ||
| 37 | + operands[0] = old_value; | ||
| 38 | + arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0"); | ||
| 39 | + arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", | ||
| 40 | + LOCAL_LABEL_PREFIX); | ||
| 41 | + | ||
| 42 | + switch (sync_op) | ||
| 43 | + { | ||
| 44 | + case SYNC_OP_ADD: | ||
| 45 | + arm_output_op3 (emit, "sub", old_value, t1, new_value); | ||
| 46 | + break; | ||
| 47 | + | ||
| 48 | + case SYNC_OP_SUB: | ||
| 49 | + arm_output_op3 (emit, "add", old_value, t1, new_value); | ||
| 50 | + break; | ||
| 51 | + | ||
| 52 | + case SYNC_OP_XOR: | ||
| 53 | + arm_output_op3 (emit, "eor", old_value, t1, new_value); | ||
| 54 | + break; | ||
| 55 | + | ||
| 56 | + case SYNC_OP_NONE: | ||
| 57 | + arm_output_op2 (emit, "mov", old_value, required_value); | ||
| 58 | + break; | ||
| 59 | + | ||
| 60 | + default: | ||
| 61 | + gcc_unreachable (); | ||
| 62 | + } | ||
| 63 | + } | ||
| 64 | |||
| 65 | arm_process_output_memory_barrier (emit, NULL); | ||
| 66 | arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX); | ||
| 67 | Index: gcc-4_5-branch/gcc/config/arm/sync.md | ||
| 68 | =================================================================== | ||
| 69 | --- gcc-4_5-branch.orig/gcc/config/arm/sync.md | ||
| 70 | +++ gcc-4_5-branch/gcc/config/arm/sync.md | ||
| 71 | @@ -103,6 +103,18 @@ | ||
| 72 | (plus "add") | ||
| 73 | (minus "sub")]) | ||
| 74 | |||
| 75 | +(define_code_attr sync_clobber [(ior "=&r") | ||
| 76 | + (and "=&r") | ||
| 77 | + (xor "X") | ||
| 78 | + (plus "X") | ||
| 79 | + (minus "X")]) | ||
| 80 | + | ||
| 81 | +(define_code_attr sync_t2_reqd [(ior "4") | ||
| 82 | + (and "4") | ||
| 83 | + (xor "*") | ||
| 84 | + (plus "*") | ||
| 85 | + (minus "*")]) | ||
| 86 | + | ||
| 87 | (define_expand "sync_<sync_optab>si" | ||
| 88 | [(match_operand:SI 0 "memory_operand") | ||
| 89 | (match_operand:SI 1 "s_register_operand") | ||
| 90 | @@ -286,7 +298,6 @@ | ||
| 91 | VUNSPEC_SYNC_COMPARE_AND_SWAP)) | ||
| 92 | (set (match_dup 1) (unspec_volatile:SI [(match_dup 2)] | ||
| 93 | VUNSPEC_SYNC_COMPARE_AND_SWAP)) | ||
| 94 | - (clobber:SI (match_scratch:SI 4 "=&r")) | ||
| 95 | (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)] | ||
| 96 | VUNSPEC_SYNC_COMPARE_AND_SWAP)) | ||
| 97 | ] | ||
| 98 | @@ -299,7 +310,6 @@ | ||
| 99 | (set_attr "sync_required_value" "2") | ||
| 100 | (set_attr "sync_new_value" "3") | ||
| 101 | (set_attr "sync_t1" "0") | ||
| 102 | - (set_attr "sync_t2" "4") | ||
| 103 | (set_attr "conds" "clob") | ||
| 104 | (set_attr "predicable" "no")]) | ||
| 105 | |||
| 106 | @@ -313,7 +323,6 @@ | ||
| 107 | VUNSPEC_SYNC_COMPARE_AND_SWAP))) | ||
| 108 | (set (match_dup 1) (unspec_volatile:NARROW [(match_dup 2)] | ||
| 109 | VUNSPEC_SYNC_COMPARE_AND_SWAP)) | ||
| 110 | - (clobber:SI (match_scratch:SI 4 "=&r")) | ||
| 111 | (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)] | ||
| 112 | VUNSPEC_SYNC_COMPARE_AND_SWAP)) | ||
| 113 | ] | ||
| 114 | @@ -326,7 +335,6 @@ | ||
| 115 | (set_attr "sync_required_value" "2") | ||
| 116 | (set_attr "sync_new_value" "3") | ||
| 117 | (set_attr "sync_t1" "0") | ||
| 118 | - (set_attr "sync_t2" "4") | ||
| 119 | (set_attr "conds" "clob") | ||
| 120 | (set_attr "predicable" "no")]) | ||
| 121 | |||
| 122 | @@ -487,7 +495,7 @@ | ||
| 123 | VUNSPEC_SYNC_OLD_OP)) | ||
| 124 | (clobber (reg:CC CC_REGNUM)) | ||
| 125 | (clobber (match_scratch:SI 3 "=&r")) | ||
| 126 | - (clobber (match_scratch:SI 4 "=&r"))] | ||
| 127 | + (clobber (match_scratch:SI 4 "<sync_clobber>"))] | ||
| 128 | "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER" | ||
| 129 | { | ||
| 130 | return arm_output_sync_insn (insn, operands); | ||
| 131 | @@ -496,7 +504,7 @@ | ||
| 132 | (set_attr "sync_memory" "1") | ||
| 133 | (set_attr "sync_new_value" "2") | ||
| 134 | (set_attr "sync_t1" "3") | ||
| 135 | - (set_attr "sync_t2" "4") | ||
| 136 | + (set_attr "sync_t2" "<sync_t2_reqd>") | ||
| 137 | (set_attr "sync_op" "<sync_optab>") | ||
| 138 | (set_attr "conds" "clob") | ||
| 139 | (set_attr "predicable" "no")]) | ||
| 140 | @@ -540,7 +548,7 @@ | ||
| 141 | VUNSPEC_SYNC_OLD_OP)) | ||
| 142 | (clobber (reg:CC CC_REGNUM)) | ||
| 143 | (clobber (match_scratch:SI 3 "=&r")) | ||
| 144 | - (clobber (match_scratch:SI 4 "=&r"))] | ||
| 145 | + (clobber (match_scratch:SI 4 "<sync_clobber>"))] | ||
| 146 | "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER" | ||
| 147 | { | ||
| 148 | return arm_output_sync_insn (insn, operands); | ||
| 149 | @@ -549,7 +557,7 @@ | ||
| 150 | (set_attr "sync_memory" "1") | ||
| 151 | (set_attr "sync_new_value" "2") | ||
| 152 | (set_attr "sync_t1" "3") | ||
| 153 | - (set_attr "sync_t2" "4") | ||
| 154 | + (set_attr "sync_t2" "<sync_t2_reqd>") | ||
| 155 | (set_attr "sync_op" "<sync_optab>") | ||
| 156 | (set_attr "conds" "clob") | ||
| 157 | (set_attr "predicable" "no")]) | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99465.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99465.patch deleted file mode 100644 index 32c2999a7..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99465.patch +++ /dev/null | |||
| @@ -1,94 +0,0 @@ | |||
| 1 | 2011-01-18 Ulrich Weigand <uweigand@de.ibm.com> | ||
| 2 | |||
| 3 | LP: #685352 | ||
| 4 | Backport from mainline: | ||
| 5 | |||
| 6 | 2011-01-18 Jakub Jelinek <jakub@redhat.com> | ||
| 7 | |||
| 8 | gcc/ | ||
| 9 | PR rtl-optimization/47299 | ||
| 10 | * expr.c (expand_expr_real_2) <case WIDEN_MULT_EXPR>: Don't use | ||
| 11 | subtarget. Use normal multiplication if both operands are | ||
| 12 | constants. | ||
| 13 | * expmed.c (expand_widening_mult): Don't try to optimize constant | ||
| 14 | multiplication if op0 has VOIDmode. Convert op1 constant to mode | ||
| 15 | before using it. | ||
| 16 | |||
| 17 | gcc/testsuite/ | ||
| 18 | PR rtl-optimization/47299 | ||
| 19 | * gcc.c-torture/execute/pr47299.c: New test. | ||
| 20 | |||
| 21 | === modified file 'gcc/expmed.c' | ||
| 22 | Index: gcc-4_5-branch/gcc/expmed.c | ||
| 23 | =================================================================== | ||
| 24 | --- gcc-4_5-branch.orig/gcc/expmed.c | ||
| 25 | +++ gcc-4_5-branch/gcc/expmed.c | ||
| 26 | @@ -3355,12 +3355,17 @@ expand_widening_mult (enum machine_mode | ||
| 27 | int unsignedp, optab this_optab) | ||
| 28 | { | ||
| 29 | bool speed = optimize_insn_for_speed_p (); | ||
| 30 | + rtx cop1; | ||
| 31 | |||
| 32 | if (CONST_INT_P (op1) | ||
| 33 | - && (INTVAL (op1) >= 0 | ||
| 34 | + && GET_MODE (op0) != VOIDmode | ||
| 35 | + && (cop1 = convert_modes (mode, GET_MODE (op0), op1, | ||
| 36 | + this_optab == umul_widen_optab)) | ||
| 37 | + && CONST_INT_P (cop1) | ||
| 38 | + && (INTVAL (cop1) >= 0 | ||
| 39 | || GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)) | ||
| 40 | { | ||
| 41 | - HOST_WIDE_INT coeff = INTVAL (op1); | ||
| 42 | + HOST_WIDE_INT coeff = INTVAL (cop1); | ||
| 43 | int max_cost; | ||
| 44 | enum mult_variant variant; | ||
| 45 | struct algorithm algorithm; | ||
| 46 | Index: gcc-4_5-branch/gcc/expr.c | ||
| 47 | =================================================================== | ||
| 48 | --- gcc-4_5-branch.orig/gcc/expr.c | ||
| 49 | +++ gcc-4_5-branch/gcc/expr.c | ||
| 50 | @@ -7624,10 +7624,10 @@ expand_expr_real_2 (sepops ops, rtx targ | ||
| 51 | if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing) | ||
| 52 | { | ||
| 53 | if (TYPE_UNSIGNED (TREE_TYPE (treeop0))) | ||
| 54 | - expand_operands (treeop0, treeop1, subtarget, &op0, &op1, | ||
| 55 | + expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, | ||
| 56 | EXPAND_NORMAL); | ||
| 57 | else | ||
| 58 | - expand_operands (treeop0, treeop1, subtarget, &op1, &op0, | ||
| 59 | + expand_operands (treeop0, treeop1, NULL_RTX, &op1, &op0, | ||
| 60 | EXPAND_NORMAL); | ||
| 61 | goto binop3; | ||
| 62 | } | ||
| 63 | @@ -7645,7 +7645,8 @@ expand_expr_real_2 (sepops ops, rtx targ | ||
| 64 | optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab; | ||
| 65 | this_optab = zextend_p ? umul_widen_optab : smul_widen_optab; | ||
| 66 | |||
| 67 | - if (mode == GET_MODE_2XWIDER_MODE (innermode)) | ||
| 68 | + if (mode == GET_MODE_2XWIDER_MODE (innermode) | ||
| 69 | + && TREE_CODE (treeop0) != INTEGER_CST) | ||
| 70 | { | ||
| 71 | if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing) | ||
| 72 | { | ||
| 73 | Index: gcc-4_5-branch/gcc/testsuite/gcc.c-torture/execute/pr47299.c | ||
| 74 | =================================================================== | ||
| 75 | --- /dev/null | ||
| 76 | +++ gcc-4_5-branch/gcc/testsuite/gcc.c-torture/execute/pr47299.c | ||
| 77 | @@ -0,0 +1,17 @@ | ||
| 78 | +/* PR rtl-optimization/47299 */ | ||
| 79 | + | ||
| 80 | +extern void abort (void); | ||
| 81 | + | ||
| 82 | +__attribute__ ((noinline, noclone)) unsigned short | ||
| 83 | +foo (unsigned char x) | ||
| 84 | +{ | ||
| 85 | + return x * 255; | ||
| 86 | +} | ||
| 87 | + | ||
| 88 | +int | ||
| 89 | +main () | ||
| 90 | +{ | ||
| 91 | + if (foo (0x40) != 0x3fc0) | ||
| 92 | + abort (); | ||
| 93 | + return 0; | ||
| 94 | +} | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99466.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99466.patch deleted file mode 100644 index 580d4f472..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99466.patch +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | 2011-01-19 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | ||
| 2 | |||
| 3 | Backport from FSF mainline | ||
| 4 | |||
| 5 | 2011-01-18 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | ||
| 6 | |||
| 7 | * config/arm/cortex-a9.md (cortex-a9-neon.md): Actually | ||
| 8 | include. | ||
| 9 | (cortex_a9_dp): Handle neon types correctly. | ||
| 10 | |||
| 11 | === modified file 'gcc/config/arm/cortex-a9.md' | ||
| 12 | Index: gcc-4_5-branch/gcc/config/arm/cortex-a9.md | ||
| 13 | =================================================================== | ||
| 14 | --- gcc-4_5-branch.orig/gcc/config/arm/cortex-a9.md | ||
| 15 | +++ gcc-4_5-branch/gcc/config/arm/cortex-a9.md | ||
| 16 | @@ -79,10 +79,11 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cort | ||
| 17 | ;; which can go down E2 without any problem. | ||
| 18 | (define_insn_reservation "cortex_a9_dp" 2 | ||
| 19 | (and (eq_attr "tune" "cortexa9") | ||
| 20 | - (ior (eq_attr "type" "alu") | ||
| 21 | - (ior (and (eq_attr "type" "alu_shift_reg, alu_shift") | ||
| 22 | - (eq_attr "insn" "mov")) | ||
| 23 | - (eq_attr "neon_type" "none")))) | ||
| 24 | + (ior (and (eq_attr "type" "alu") | ||
| 25 | + (eq_attr "neon_type" "none")) | ||
| 26 | + (and (and (eq_attr "type" "alu_shift_reg, alu_shift") | ||
| 27 | + (eq_attr "insn" "mov")) | ||
| 28 | + (eq_attr "neon_type" "none")))) | ||
| 29 | "cortex_a9_p0_default|cortex_a9_p1_default") | ||
| 30 | |||
| 31 | ;; An instruction using the shifter will go down E1. | ||
| 32 | @@ -263,3 +264,6 @@ cortex_a9_store3_4, cortex_a9_store1_2, | ||
| 33 | (and (eq_attr "tune" "cortexa9") | ||
| 34 | (eq_attr "type" "fdivd")) | ||
| 35 | "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24") | ||
| 36 | + | ||
| 37 | +;; Include Neon pipeline description | ||
| 38 | +(include "cortex-a9-neon.md") | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99468.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99468.patch deleted file mode 100644 index cf22aaf16..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99468.patch +++ /dev/null | |||
| @@ -1,811 +0,0 @@ | |||
| 1 | 2010-12-13 Tom de Vries <tom@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * tree-if-switch-conversion.c: New pass. | ||
| 5 | * tree-pass.h (pass_if_to_switch): Declare. | ||
| 6 | * common.opt (ftree-if-to-switch-conversion): New switch. | ||
| 7 | * opts.c (decode_options): Set flag_tree_if_to_switch_conversion at -O2 | ||
| 8 | and higher. | ||
| 9 | * passes.c (init_optimization_passes): Use new pass. | ||
| 10 | * params.def (PARAM_IF_TO_SWITCH_THRESHOLD): New param. | ||
| 11 | * doc/invoke.texi (-ftree-if-to-switch-conversion) | ||
| 12 | (if-to-switch-threshold): New item. | ||
| 13 | * doc/invoke.texi (Optimization Options, option -O2): Add | ||
| 14 | -ftree-if-to-switch-conversion. | ||
| 15 | * Makefile.in (OBJS-common): Add tree-if-switch-conversion.o. | ||
| 16 | * Makefile.in (tree-if-switch-conversion.o): New rule. | ||
| 17 | |||
| 18 | === modified file 'gcc/Makefile.in' | ||
| 19 | Index: gcc-4_5-branch/gcc/Makefile.in | ||
| 20 | =================================================================== | ||
| 21 | --- gcc-4_5-branch.orig/gcc/Makefile.in | ||
| 22 | +++ gcc-4_5-branch/gcc/Makefile.in | ||
| 23 | @@ -1354,6 +1354,7 @@ OBJS-common = \ | ||
| 24 | tree-profile.o \ | ||
| 25 | tree-scalar-evolution.o \ | ||
| 26 | tree-sra.o \ | ||
| 27 | + tree-if-switch-conversion.o \ | ||
| 28 | tree-switch-conversion.o \ | ||
| 29 | tree-ssa-address.o \ | ||
| 30 | tree-ssa-alias.o \ | ||
| 31 | @@ -3013,6 +3014,11 @@ tree-sra.o : tree-sra.c $(CONFIG_H) $(SY | ||
| 32 | $(TM_H) $(TREE_H) $(GIMPLE_H) $(CGRAPH_H) $(TREE_FLOW_H) $(IPA_PROP_H) \ | ||
| 33 | $(DIAGNOSTIC_H) statistics.h $(TREE_DUMP_H) $(TIMEVAR_H) $(PARAMS_H) \ | ||
| 34 | $(TARGET_H) $(FLAGS_H) $(EXPR_H) $(TREE_INLINE_H) | ||
| 35 | +tree-if-switch-conversion.o : tree-if-switch-conversion.c $(CONFIG_H) \ | ||
| 36 | + $(SYSTEM_H) $(TREE_H) $(TM_P_H) $(TREE_FLOW_H) $(DIAGNOSTIC_H) \ | ||
| 37 | + $(TREE_INLINE_H) $(TIMEVAR_H) $(TM_H) coretypes.h $(TREE_DUMP_H) \ | ||
| 38 | + $(GIMPLE_H) $(TREE_PASS_H) $(FLAGS_H) $(EXPR_H) $(BASIC_BLOCK_H) output.h \ | ||
| 39 | + $(GGC_H) $(OBSTACK_H) $(PARAMS_H) $(CPPLIB_H) $(PARAMS_H) | ||
| 40 | tree-switch-conversion.o : tree-switch-conversion.c $(CONFIG_H) $(SYSTEM_H) \ | ||
| 41 | $(TREE_H) $(TM_P_H) $(TREE_FLOW_H) $(DIAGNOSTIC_H) $(TREE_INLINE_H) \ | ||
| 42 | $(TIMEVAR_H) $(TM_H) coretypes.h $(TREE_DUMP_H) $(GIMPLE_H) \ | ||
| 43 | Index: gcc-4_5-branch/gcc/common.opt | ||
| 44 | =================================================================== | ||
| 45 | --- gcc-4_5-branch.orig/gcc/common.opt | ||
| 46 | +++ gcc-4_5-branch/gcc/common.opt | ||
| 47 | @@ -1285,6 +1285,10 @@ ftree-switch-conversion | ||
| 48 | Common Report Var(flag_tree_switch_conversion) Optimization | ||
| 49 | Perform conversions of switch initializations. | ||
| 50 | |||
| 51 | +ftree-if-to-switch-conversion | ||
| 52 | +Common Report Var(flag_tree_if_to_switch_conversion) Optimization | ||
| 53 | +Perform conversions of chains of ifs into switches. | ||
| 54 | + | ||
| 55 | ftree-dce | ||
| 56 | Common Report Var(flag_tree_dce) Optimization | ||
| 57 | Enable SSA dead code elimination optimization on trees | ||
| 58 | Index: gcc-4_5-branch/gcc/doc/invoke.texi | ||
| 59 | =================================================================== | ||
| 60 | --- gcc-4_5-branch.orig/gcc/doc/invoke.texi | ||
| 61 | +++ gcc-4_5-branch/gcc/doc/invoke.texi | ||
| 62 | @@ -382,7 +382,8 @@ Objective-C and Objective-C++ Dialects}. | ||
| 63 | -fstrict-aliasing -fstrict-overflow -fthread-jumps -ftracer @gol | ||
| 64 | -ftree-builtin-call-dce -ftree-ccp -ftree-ch -ftree-copy-prop @gol | ||
| 65 | -ftree-copyrename -ftree-dce @gol | ||
| 66 | --ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre -ftree-loop-im @gol | ||
| 67 | +-ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre @gol | ||
| 68 | +-ftree-if-to-switch-conversion -ftree-loop-im @gol | ||
| 69 | -ftree-phiprop -ftree-loop-distribution @gol | ||
| 70 | -ftree-loop-ivcanon -ftree-loop-linear -ftree-loop-optimize @gol | ||
| 71 | -ftree-parallelize-loops=@var{n} -ftree-pre -ftree-pta -ftree-reassoc @gol | ||
| 72 | @@ -5798,6 +5799,7 @@ also turns on the following optimization | ||
| 73 | -fsched-interblock -fsched-spec @gol | ||
| 74 | -fschedule-insns -fschedule-insns2 @gol | ||
| 75 | -fstrict-aliasing -fstrict-overflow @gol | ||
| 76 | +-ftree-if-to-switch-conversion @gol | ||
| 77 | -ftree-switch-conversion @gol | ||
| 78 | -ftree-pre @gol | ||
| 79 | -ftree-vrp} | ||
| 80 | @@ -6634,6 +6636,10 @@ Perform conversion of simple initializat | ||
| 81 | initializations from a scalar array. This flag is enabled by default | ||
| 82 | at @option{-O2} and higher. | ||
| 83 | |||
| 84 | +@item -ftree-if-to-switch-conversion | ||
| 85 | +Perform conversion of chains of ifs into switches. This flag is enabled by | ||
| 86 | +default at @option{-O2} and higher. | ||
| 87 | + | ||
| 88 | @item -ftree-dce | ||
| 89 | @opindex ftree-dce | ||
| 90 | Perform dead code elimination (DCE) on trees. This flag is enabled by | ||
| 91 | @@ -8577,6 +8583,12 @@ loop in the loop nest by a given number | ||
| 92 | length can be changed using the @option{loop-block-tile-size} | ||
| 93 | parameter. The default value is 51 iterations. | ||
| 94 | |||
| 95 | +@item if-to-switch-threshold | ||
| 96 | +If-chain to switch conversion, enabled by | ||
| 97 | +@option{-ftree-if-to-switch-conversion} convert chains of ifs of sufficient | ||
| 98 | +length into switches. The parameter @option{if-to-switch-threshold} can be | ||
| 99 | +used to set the minimal required length. The default value is 3. | ||
| 100 | + | ||
| 101 | @end table | ||
| 102 | @end table | ||
| 103 | |||
| 104 | Index: gcc-4_5-branch/gcc/opts.c | ||
| 105 | =================================================================== | ||
| 106 | --- gcc-4_5-branch.orig/gcc/opts.c | ||
| 107 | +++ gcc-4_5-branch/gcc/opts.c | ||
| 108 | @@ -905,6 +905,7 @@ decode_options (unsigned int argc, const | ||
| 109 | flag_tree_builtin_call_dce = opt2; | ||
| 110 | flag_tree_pre = opt2; | ||
| 111 | flag_tree_switch_conversion = opt2; | ||
| 112 | + flag_tree_if_to_switch_conversion = opt2; | ||
| 113 | flag_ipa_cp = opt2; | ||
| 114 | flag_ipa_sra = opt2; | ||
| 115 | flag_ee = opt2; | ||
| 116 | Index: gcc-4_5-branch/gcc/params.def | ||
| 117 | =================================================================== | ||
| 118 | --- gcc-4_5-branch.orig/gcc/params.def | ||
| 119 | +++ gcc-4_5-branch/gcc/params.def | ||
| 120 | @@ -826,6 +826,11 @@ DEFPARAM (PARAM_IPA_SRA_PTR_GROWTH_FACTO | ||
| 121 | "a pointer to an aggregate with", | ||
| 122 | 2, 0, 0) | ||
| 123 | |||
| 124 | +DEFPARAM (PARAM_IF_TO_SWITCH_THRESHOLD, | ||
| 125 | + "if-to-switch-threshold", | ||
| 126 | + "Threshold for converting an if-chain into a switch", | ||
| 127 | + 3, 0, 0) | ||
| 128 | + | ||
| 129 | /* | ||
| 130 | Local variables: | ||
| 131 | mode:c | ||
| 132 | Index: gcc-4_5-branch/gcc/passes.c | ||
| 133 | =================================================================== | ||
| 134 | --- gcc-4_5-branch.orig/gcc/passes.c | ||
| 135 | +++ gcc-4_5-branch/gcc/passes.c | ||
| 136 | @@ -788,6 +788,7 @@ init_optimization_passes (void) | ||
| 137 | NEXT_PASS (pass_cd_dce); | ||
| 138 | NEXT_PASS (pass_early_ipa_sra); | ||
| 139 | NEXT_PASS (pass_tail_recursion); | ||
| 140 | + NEXT_PASS (pass_if_to_switch); | ||
| 141 | NEXT_PASS (pass_convert_switch); | ||
| 142 | NEXT_PASS (pass_cleanup_eh); | ||
| 143 | NEXT_PASS (pass_profile); | ||
| 144 | @@ -844,6 +845,7 @@ init_optimization_passes (void) | ||
| 145 | NEXT_PASS (pass_phiprop); | ||
| 146 | NEXT_PASS (pass_fre); | ||
| 147 | NEXT_PASS (pass_copy_prop); | ||
| 148 | + NEXT_PASS (pass_if_to_switch); | ||
| 149 | NEXT_PASS (pass_merge_phi); | ||
| 150 | NEXT_PASS (pass_vrp); | ||
| 151 | NEXT_PASS (pass_dce); | ||
| 152 | Index: gcc-4_5-branch/gcc/tree-if-switch-conversion.c | ||
| 153 | =================================================================== | ||
| 154 | --- /dev/null | ||
| 155 | +++ gcc-4_5-branch/gcc/tree-if-switch-conversion.c | ||
| 156 | @@ -0,0 +1,643 @@ | ||
| 157 | +/* Convert a chain of ifs into a switch. | ||
| 158 | + Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 159 | + Contributed by Tom de Vries <tom@codesourcery.com> | ||
| 160 | + | ||
| 161 | +This file is part of GCC. | ||
| 162 | + | ||
| 163 | +GCC is free software; you can redistribute it and/or modify it | ||
| 164 | +under the terms of the GNU General Public License as published by the | ||
| 165 | +Free Software Foundation; either version 3, or (at your option) any | ||
| 166 | +later version. | ||
| 167 | + | ||
| 168 | +GCC is distributed in the hope that it will be useful, but WITHOUT | ||
| 169 | +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 170 | +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
| 171 | +for more details. | ||
| 172 | + | ||
| 173 | +You should have received a copy of the GNU General Public License | ||
| 174 | +along with GCC; see the file COPYING3. If not, write to the Free | ||
| 175 | +Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA | ||
| 176 | +02110-1301, USA. */ | ||
| 177 | + | ||
| 178 | + | ||
| 179 | +/* The following pass converts a chain of ifs into a switch. | ||
| 180 | + | ||
| 181 | + The if-chain has the following properties: | ||
| 182 | + - all bbs end in a GIMPLE_COND. | ||
| 183 | + - all but the first bb are empty, apart from the GIMPLE_COND. | ||
| 184 | + - the GIMPLE_CONDs compare the same variable against integer constants. | ||
| 185 | + - the true gotos all target the same bb. | ||
| 186 | + - the false gotos target the next in the if-chain. | ||
| 187 | + | ||
| 188 | + F.i., consider the following if-chain: | ||
| 189 | + ... | ||
| 190 | + <bb 4>: | ||
| 191 | + ... | ||
| 192 | + if (D.1993_3 == 32) | ||
| 193 | + goto <bb 3>; | ||
| 194 | + else | ||
| 195 | + goto <bb 5>; | ||
| 196 | + | ||
| 197 | + <bb 5>: | ||
| 198 | + if (D.1993_3 == 13) | ||
| 199 | + goto <bb 3>; | ||
| 200 | + else | ||
| 201 | + goto <bb 6>; | ||
| 202 | + | ||
| 203 | + <bb 6>: | ||
| 204 | + if (D.1993_3 == 10) | ||
| 205 | + goto <bb 3>; | ||
| 206 | + else | ||
| 207 | + goto <bb 7>; | ||
| 208 | + | ||
| 209 | + <bb 7>: | ||
| 210 | + if (D.1993_3 == 9) | ||
| 211 | + goto <bb 3>; | ||
| 212 | + else | ||
| 213 | + goto <bb 8>; | ||
| 214 | + ... | ||
| 215 | + | ||
| 216 | + The pass will report this if-chain like this: | ||
| 217 | + ... | ||
| 218 | + var: D.1993_3 | ||
| 219 | + first: <bb 4> | ||
| 220 | + true: <bb 3> | ||
| 221 | + last: <bb 7> | ||
| 222 | + constants: 9 10 13 32 | ||
| 223 | + ... | ||
| 224 | + | ||
| 225 | + and then convert the if-chain into a switch: | ||
| 226 | + ... | ||
| 227 | + <bb 4>: | ||
| 228 | + ... | ||
| 229 | + switch (D.1993_3) <default: <L8>, | ||
| 230 | + case 9: <L7>, | ||
| 231 | + case 10: <L7>, | ||
| 232 | + case 13: <L7>, | ||
| 233 | + case 32: <L7>> | ||
| 234 | + ... | ||
| 235 | + | ||
| 236 | + The conversion does not happen if the chain is too short. The threshold is | ||
| 237 | + determined by the parameter PARAM_IF_TO_SWITCH_THRESHOLD. | ||
| 238 | + | ||
| 239 | + The pass will try to construct a chain for each bb, unless the bb it is | ||
| 240 | + already contained in a chain. This ensures that all chains will be found, | ||
| 241 | + and that no chain will be constructed twice. The pass constructs and | ||
| 242 | + converts the chains one-by-one, rather than first calculating all the chains | ||
| 243 | + and then doing the conversions. | ||
| 244 | + | ||
| 245 | + The pass could detect range-checks in analyze_bb as well, and handle them. | ||
| 246 | + Simple ones, like 'c <= 5', and more complex ones, like | ||
| 247 | + '(unsigned char) c + 247 <= 1', which is generated by the C front-end from | ||
| 248 | + code like '(c == 9 || c == 10)' or '(9 <= c && c <= 10)'. */ | ||
| 249 | + | ||
| 250 | +#include "config.h" | ||
| 251 | +#include "system.h" | ||
| 252 | +#include "coretypes.h" | ||
| 253 | +#include "tm.h" | ||
| 254 | + | ||
| 255 | +#include "params.h" | ||
| 256 | +#include "flags.h" | ||
| 257 | +#include "tree.h" | ||
| 258 | +#include "basic-block.h" | ||
| 259 | +#include "tree-flow.h" | ||
| 260 | +#include "tree-flow-inline.h" | ||
| 261 | +#include "tree-ssa-operands.h" | ||
| 262 | +#include "diagnostic.h" | ||
| 263 | +#include "tree-pass.h" | ||
| 264 | +#include "tree-dump.h" | ||
| 265 | +#include "timevar.h" | ||
| 266 | + | ||
| 267 | +/* Information we've collected about a single bb. */ | ||
| 268 | + | ||
| 269 | +struct ifsc_info | ||
| 270 | +{ | ||
| 271 | + /* The variable of the bb's ending GIMPLE_COND, NULL_TREE if not present. */ | ||
| 272 | + tree var; | ||
| 273 | + /* The cond_code of the bb's ending GIMPLE_COND. */ | ||
| 274 | + enum tree_code cond_code; | ||
| 275 | + /* The constant of the bb's ending GIMPLE_COND. */ | ||
| 276 | + tree constant; | ||
| 277 | + /* Successor edge of the bb if its GIMPLE_COND is true. */ | ||
| 278 | + edge true_edge; | ||
| 279 | + /* Successor edge of the bb if its GIMPLE_COND is false. */ | ||
| 280 | + edge false_edge; | ||
| 281 | + /* Set if the bb has valid ifsc_info. */ | ||
| 282 | + bool valid; | ||
| 283 | + /* Set if the bb is part of a chain. */ | ||
| 284 | + bool chained; | ||
| 285 | +}; | ||
| 286 | + | ||
| 287 | +/* Macros to access the fields of struct ifsc_info. */ | ||
| 288 | + | ||
| 289 | +#define BB_IFSC_VAR(bb) (((struct ifsc_info *)bb->aux)->var) | ||
| 290 | +#define BB_IFSC_COND_CODE(bb) (((struct ifsc_info *)bb->aux)->cond_code) | ||
| 291 | +#define BB_IFSC_CONSTANT(bb) (((struct ifsc_info *)bb->aux)->constant) | ||
| 292 | +#define BB_IFSC_TRUE_EDGE(bb) (((struct ifsc_info *)bb->aux)->true_edge) | ||
| 293 | +#define BB_IFSC_FALSE_EDGE(bb) (((struct ifsc_info *)bb->aux)->false_edge) | ||
| 294 | +#define BB_IFSC_VALID(bb) (((struct ifsc_info *)bb->aux)->valid) | ||
| 295 | +#define BB_IFSC_CHAINED(bb) (((struct ifsc_info *)bb->aux)->chained) | ||
| 296 | + | ||
| 297 | +/* Data-type describing an if-chain. */ | ||
| 298 | + | ||
| 299 | +struct if_chain | ||
| 300 | +{ | ||
| 301 | + /* First bb in the chain. */ | ||
| 302 | + basic_block first; | ||
| 303 | + /* Last bb in the chain. */ | ||
| 304 | + basic_block last; | ||
| 305 | + /* Variable that GIMPLE_CONDs of all bbs in chain compare against. */ | ||
| 306 | + tree var; | ||
| 307 | + /* bb that all GIMPLE_CONDs jump to if comparison succeeds. */ | ||
| 308 | + basic_block true_dest; | ||
| 309 | + /* Constants that GIMPLE_CONDs of all bbs in chain compare var against. */ | ||
| 310 | + VEC (tree, heap) *constants; | ||
| 311 | + /* Same as previous, but sorted and with duplicates removed. */ | ||
| 312 | + VEC (tree, heap) *unique_constants; | ||
| 313 | +}; | ||
| 314 | + | ||
| 315 | +/* Utility macro. */ | ||
| 316 | + | ||
| 317 | +#define SWAP(T, X, Y) do { T tmp = (X); (X) = (Y); (Y) = tmp; } while (0) | ||
| 318 | + | ||
| 319 | +/* Helper function for sort_constants. */ | ||
| 320 | + | ||
| 321 | +static int | ||
| 322 | +compare_constants (const void *p1, const void *p2) | ||
| 323 | +{ | ||
| 324 | + const_tree const c1 = *(const_tree const*)p1; | ||
| 325 | + const_tree const c2 = *(const_tree const*)p2; | ||
| 326 | + | ||
| 327 | + return tree_int_cst_compare (c1, c2); | ||
| 328 | +} | ||
| 329 | + | ||
| 330 | +/* Sort constants in constants and copy to unique_constants, while skipping | ||
| 331 | + duplicates. */ | ||
| 332 | + | ||
| 333 | +static void | ||
| 334 | +sort_constants (VEC (tree,heap) *constants, VEC (tree,heap) **unique_constants) | ||
| 335 | +{ | ||
| 336 | + size_t len = VEC_length (tree, constants); | ||
| 337 | + unsigned int ix; | ||
| 338 | + tree prev = NULL_TREE, constant; | ||
| 339 | + | ||
| 340 | + /* Sort constants. */ | ||
| 341 | + qsort (VEC_address (tree, constants), len, sizeof (tree), | ||
| 342 | + compare_constants); | ||
| 343 | + | ||
| 344 | + /* Copy to unique_constants, while skipping duplicates. */ | ||
| 345 | + for (ix = 0; VEC_iterate (tree, constants, ix, constant); ix++) | ||
| 346 | + { | ||
| 347 | + if (prev != NULL_TREE && tree_int_cst_compare (prev, constant) == 0) | ||
| 348 | + continue; | ||
| 349 | + prev = constant; | ||
| 350 | + | ||
| 351 | + VEC_safe_push (tree, heap, *unique_constants, constant); | ||
| 352 | + } | ||
| 353 | +} | ||
| 354 | + | ||
| 355 | +/* Get true_edge and false_edge of a bb ending in a conditional jump. */ | ||
| 356 | + | ||
| 357 | +static void | ||
| 358 | +get_edges (basic_block bb, edge *true_edge, edge *false_edge) | ||
| 359 | +{ | ||
| 360 | + edge e0, e1; | ||
| 361 | + int e0_true; | ||
| 362 | + int n = EDGE_COUNT (bb->succs); | ||
| 363 | + gcc_assert (n == 2); | ||
| 364 | + | ||
| 365 | + e0 = EDGE_SUCC (bb, 0); | ||
| 366 | + e1 = EDGE_SUCC (bb, 1); | ||
| 367 | + | ||
| 368 | + e0_true = e0->flags & EDGE_TRUE_VALUE; | ||
| 369 | + | ||
| 370 | + *true_edge = e0_true ? e0 : e1; | ||
| 371 | + *false_edge = e0_true ? e1 : e0; | ||
| 372 | + | ||
| 373 | + gcc_assert ((*true_edge)->flags & EDGE_TRUE_VALUE); | ||
| 374 | + gcc_assert ((*false_edge)->flags & EDGE_FALSE_VALUE); | ||
| 375 | + | ||
| 376 | + gcc_assert (((*true_edge)->flags & EDGE_FALLTHRU) == 0); | ||
| 377 | + gcc_assert (((*false_edge)->flags & EDGE_FALLTHRU) == 0); | ||
| 378 | +} | ||
| 379 | + | ||
| 380 | +/* Analyze bb and store results in ifsc_info struct. */ | ||
| 381 | + | ||
| 382 | +static void | ||
| 383 | +analyze_bb (basic_block bb) | ||
| 384 | +{ | ||
| 385 | + gimple stmt = last_stmt (bb); | ||
| 386 | + tree lhs, rhs, var, constant; | ||
| 387 | + edge true_edge, false_edge; | ||
| 388 | + enum tree_code cond_code; | ||
| 389 | + | ||
| 390 | + /* Don't redo analysis. */ | ||
| 391 | + if (BB_IFSC_VALID (bb)) | ||
| 392 | + return; | ||
| 393 | + BB_IFSC_VALID (bb) = true; | ||
| 394 | + | ||
| 395 | + | ||
| 396 | + /* bb needs to end in GIMPLE_COND. */ | ||
| 397 | + if (!stmt || gimple_code (stmt) != GIMPLE_COND) | ||
| 398 | + return; | ||
| 399 | + | ||
| 400 | + /* bb needs to end in EQ_EXPR or NE_EXPR. */ | ||
| 401 | + cond_code = gimple_cond_code (stmt); | ||
| 402 | + if (cond_code != EQ_EXPR && cond_code != NE_EXPR) | ||
| 403 | + return; | ||
| 404 | + | ||
| 405 | + lhs = gimple_cond_lhs (stmt); | ||
| 406 | + rhs = gimple_cond_rhs (stmt); | ||
| 407 | + | ||
| 408 | + /* GIMPLE_COND needs to compare variable to constant. */ | ||
| 409 | + if ((TREE_CONSTANT (lhs) == 0) | ||
| 410 | + == (TREE_CONSTANT (rhs) == 0)) | ||
| 411 | + return; | ||
| 412 | + | ||
| 413 | + var = TREE_CONSTANT (lhs) ? rhs : lhs; | ||
| 414 | + constant = TREE_CONSTANT (lhs)? lhs : rhs; | ||
| 415 | + | ||
| 416 | + /* Switches cannot handle non-integral types. */ | ||
| 417 | + if (!INTEGRAL_TYPE_P(TREE_TYPE (var))) | ||
| 418 | + return; | ||
| 419 | + | ||
| 420 | + get_edges (bb, &true_edge, &false_edge); | ||
| 421 | + | ||
| 422 | + if (cond_code == NE_EXPR) | ||
| 423 | + SWAP (edge, true_edge, false_edge); | ||
| 424 | + | ||
| 425 | + /* TODO: loosen this constraint. In principle it's ok if true_edge->dest has | ||
| 426 | + phis, as long as for each phi all the edges coming from the chain have the | ||
| 427 | + same value. */ | ||
| 428 | + if (!gimple_seq_empty_p (phi_nodes (true_edge->dest))) | ||
| 429 | + return; | ||
| 430 | + | ||
| 431 | + /* Store analysis in ifsc_info struct. */ | ||
| 432 | + BB_IFSC_VAR (bb) = var; | ||
| 433 | + BB_IFSC_COND_CODE (bb) = cond_code; | ||
| 434 | + BB_IFSC_CONSTANT (bb) = constant; | ||
| 435 | + BB_IFSC_TRUE_EDGE (bb) = true_edge; | ||
| 436 | + BB_IFSC_FALSE_EDGE (bb) = false_edge; | ||
| 437 | +} | ||
| 438 | + | ||
| 439 | +/* Grow if-chain forward. */ | ||
| 440 | + | ||
| 441 | +static void | ||
| 442 | +grow_if_chain_forward (struct if_chain *chain) | ||
| 443 | +{ | ||
| 444 | + basic_block next_bb; | ||
| 445 | + | ||
| 446 | + while (1) | ||
| 447 | + { | ||
| 448 | + next_bb = BB_IFSC_FALSE_EDGE (chain->last)->dest; | ||
| 449 | + | ||
| 450 | + /* next_bb is already part of another chain. */ | ||
| 451 | + if (BB_IFSC_CHAINED (next_bb)) | ||
| 452 | + break; | ||
| 453 | + | ||
| 454 | + /* next_bb needs to be dominated by the last bb. */ | ||
| 455 | + if (!single_pred_p (next_bb)) | ||
| 456 | + break; | ||
| 457 | + | ||
| 458 | + analyze_bb (next_bb); | ||
| 459 | + | ||
| 460 | + /* Does next_bb fit in chain? */ | ||
| 461 | + if (BB_IFSC_VAR (next_bb) != chain->var | ||
| 462 | + || BB_IFSC_TRUE_EDGE (next_bb)->dest != chain->true_dest) | ||
| 463 | + break; | ||
| 464 | + | ||
| 465 | + /* We can only add empty bbs at the end of the chain. */ | ||
| 466 | + if (first_stmt (next_bb) != last_stmt (next_bb)) | ||
| 467 | + break; | ||
| 468 | + | ||
| 469 | + /* Add next_bb at end of chain. */ | ||
| 470 | + VEC_safe_push (tree, heap, chain->constants, BB_IFSC_CONSTANT (next_bb)); | ||
| 471 | + BB_IFSC_CHAINED (next_bb) = true; | ||
| 472 | + chain->last = next_bb; | ||
| 473 | + } | ||
| 474 | +} | ||
| 475 | + | ||
| 476 | +/* Grow if-chain backward. */ | ||
| 477 | + | ||
| 478 | +static void | ||
| 479 | +grow_if_chain_backward (struct if_chain *chain) | ||
| 480 | +{ | ||
| 481 | + basic_block prev_bb; | ||
| 482 | + | ||
| 483 | + while (1) | ||
| 484 | + { | ||
| 485 | + /* First bb is not empty, cannot grow backwards. */ | ||
| 486 | + if (first_stmt (chain->first) != last_stmt (chain->first)) | ||
| 487 | + break; | ||
| 488 | + | ||
| 489 | + /* First bb has no single predecessor, cannot grow backwards. */ | ||
| 490 | + if (!single_pred_p (chain->first)) | ||
| 491 | + break; | ||
| 492 | + | ||
| 493 | + prev_bb = single_pred (chain->first); | ||
| 494 | + | ||
| 495 | + /* prev_bb is already part of another chain. */ | ||
| 496 | + if (BB_IFSC_CHAINED (prev_bb)) | ||
| 497 | + break; | ||
| 498 | + | ||
| 499 | + analyze_bb (prev_bb); | ||
| 500 | + | ||
| 501 | + /* Does prev_bb fit in chain? */ | ||
| 502 | + if (BB_IFSC_VAR (prev_bb) != chain->var | ||
| 503 | + || BB_IFSC_TRUE_EDGE (prev_bb)->dest != chain->true_dest) | ||
| 504 | + break; | ||
| 505 | + | ||
| 506 | + /* Add prev_bb at beginning of chain. */ | ||
| 507 | + VEC_safe_push (tree, heap, chain->constants, BB_IFSC_CONSTANT (prev_bb)); | ||
| 508 | + BB_IFSC_CHAINED (prev_bb) = true; | ||
| 509 | + chain->first = prev_bb; | ||
| 510 | + } | ||
| 511 | +} | ||
| 512 | + | ||
| 513 | +/* Grow if-chain containing bb. */ | ||
| 514 | + | ||
| 515 | +static void | ||
| 516 | +grow_if_chain (basic_block bb, struct if_chain *chain) | ||
| 517 | +{ | ||
| 518 | + /* Initialize chain to empty. */ | ||
| 519 | + VEC_truncate (tree, chain->constants, 0); | ||
| 520 | + VEC_truncate (tree, chain->unique_constants, 0); | ||
| 521 | + | ||
| 522 | + /* bb is already part of another chain. */ | ||
| 523 | + if (BB_IFSC_CHAINED (bb)) | ||
| 524 | + return; | ||
| 525 | + | ||
| 526 | + analyze_bb (bb); | ||
| 527 | + | ||
| 528 | + /* bb is not fit to be part of a chain. */ | ||
| 529 | + if (BB_IFSC_VAR (bb) == NULL_TREE) | ||
| 530 | + return; | ||
| 531 | + | ||
| 532 | + /* Set bb as initial part of the chain. */ | ||
| 533 | + VEC_safe_push (tree, heap, chain->constants, BB_IFSC_CONSTANT (bb)); | ||
| 534 | + chain->first = chain->last = bb; | ||
| 535 | + chain->var = BB_IFSC_VAR (bb); | ||
| 536 | + chain->true_dest = BB_IFSC_TRUE_EDGE (bb)->dest; | ||
| 537 | + | ||
| 538 | + /* bb is part of a chain now. */ | ||
| 539 | + BB_IFSC_CHAINED (bb) = true; | ||
| 540 | + | ||
| 541 | + /* Grow chain to its maximum size. */ | ||
| 542 | + grow_if_chain_forward (chain); | ||
| 543 | + grow_if_chain_backward (chain); | ||
| 544 | + | ||
| 545 | + /* Sort constants and skip duplicates. */ | ||
| 546 | + sort_constants (chain->constants, &chain->unique_constants); | ||
| 547 | +} | ||
| 548 | + | ||
| 549 | +static void | ||
| 550 | +dump_tree_vector (VEC (tree, heap) *vec) | ||
| 551 | +{ | ||
| 552 | + unsigned int ix; | ||
| 553 | + tree constant; | ||
| 554 | + | ||
| 555 | + for (ix = 0; VEC_iterate (tree, vec, ix, constant); ix++) | ||
| 556 | + { | ||
| 557 | + if (ix != 0) | ||
| 558 | + fprintf (dump_file, " "); | ||
| 559 | + print_generic_expr (dump_file, constant, 0); | ||
| 560 | + } | ||
| 561 | + fprintf (dump_file, "\n"); | ||
| 562 | +} | ||
| 563 | + | ||
| 564 | +/* Dump if-chain to dump_file. */ | ||
| 565 | + | ||
| 566 | +static void | ||
| 567 | +dump_if_chain (struct if_chain *chain) | ||
| 568 | +{ | ||
| 569 | + if (!dump_file) | ||
| 570 | + return; | ||
| 571 | + | ||
| 572 | + fprintf (dump_file, "var: "); | ||
| 573 | + print_generic_expr (dump_file, chain->var, 0); | ||
| 574 | + fprintf (dump_file, "\n"); | ||
| 575 | + fprintf (dump_file, "first: <bb %d>\n", chain->first->index); | ||
| 576 | + fprintf (dump_file, "true: <bb %d>\n", chain->true_dest->index); | ||
| 577 | + fprintf (dump_file, "last: <bb %d>\n",chain->last->index); | ||
| 578 | + | ||
| 579 | + fprintf (dump_file, "constants: "); | ||
| 580 | + dump_tree_vector (chain->constants); | ||
| 581 | + | ||
| 582 | + if (VEC_length (tree, chain->unique_constants) | ||
| 583 | + != VEC_length (tree, chain->constants)) | ||
| 584 | + { | ||
| 585 | + fprintf (dump_file, "unique_constants: "); | ||
| 586 | + dump_tree_vector (chain->unique_constants); | ||
| 587 | + } | ||
| 588 | +} | ||
| 589 | + | ||
| 590 | +/* Remove redundant bbs and edges. */ | ||
| 591 | + | ||
| 592 | +static void | ||
| 593 | +remove_redundant_bbs_and_edges (struct if_chain *chain, int *false_prob) | ||
| 594 | +{ | ||
| 595 | + basic_block bb, next; | ||
| 596 | + edge true_edge, false_edge; | ||
| 597 | + | ||
| 598 | + for (bb = chain->first;; bb = next) | ||
| 599 | + { | ||
| 600 | + true_edge = BB_IFSC_TRUE_EDGE (bb); | ||
| 601 | + false_edge = BB_IFSC_FALSE_EDGE (bb); | ||
| 602 | + | ||
| 603 | + /* Determine next, before we delete false_edge. */ | ||
| 604 | + next = false_edge->dest; | ||
| 605 | + | ||
| 606 | + /* Accumulate probability. */ | ||
| 607 | + *false_prob = (*false_prob * false_edge->probability) / REG_BR_PROB_BASE; | ||
| 608 | + | ||
| 609 | + /* Don't remove the new true_edge. */ | ||
| 610 | + if (bb != chain->first) | ||
| 611 | + remove_edge (true_edge); | ||
| 612 | + | ||
| 613 | + /* Don't remove the new false_edge. */ | ||
| 614 | + if (bb != chain->last) | ||
| 615 | + remove_edge (false_edge); | ||
| 616 | + | ||
| 617 | + /* Don't remove the first bb. */ | ||
| 618 | + if (bb != chain->first) | ||
| 619 | + delete_basic_block (bb); | ||
| 620 | + | ||
| 621 | + /* Stop after last. */ | ||
| 622 | + if (bb == chain->last) | ||
| 623 | + break; | ||
| 624 | + } | ||
| 625 | +} | ||
| 626 | + | ||
| 627 | +/* Update control flow graph. */ | ||
| 628 | + | ||
| 629 | +static void | ||
| 630 | +update_cfg (struct if_chain *chain) | ||
| 631 | +{ | ||
| 632 | + edge true_edge, false_edge; | ||
| 633 | + int false_prob; | ||
| 634 | + int flags_mask = ~(EDGE_FALLTHRU|EDGE_TRUE_VALUE|EDGE_FALSE_VALUE); | ||
| 635 | + | ||
| 636 | + /* We keep these 2 edges, and remove the rest. We need this specific | ||
| 637 | + false_edge, because a phi in chain->last->dest might reference (the index | ||
| 638 | + of) this edge. For true_edge, we could pick any of them. */ | ||
| 639 | + true_edge = BB_IFSC_TRUE_EDGE (chain->first); | ||
| 640 | + false_edge = BB_IFSC_FALSE_EDGE (chain->last); | ||
| 641 | + | ||
| 642 | + /* Update true edge. */ | ||
| 643 | + true_edge->flags &= flags_mask; | ||
| 644 | + | ||
| 645 | + /* Update false edge. */ | ||
| 646 | + redirect_edge_pred (false_edge, chain->first); | ||
| 647 | + false_edge->flags &= flags_mask; | ||
| 648 | + | ||
| 649 | + false_prob = REG_BR_PROB_BASE; | ||
| 650 | + remove_redundant_bbs_and_edges (chain, &false_prob); | ||
| 651 | + | ||
| 652 | + /* Repair probabilities. */ | ||
| 653 | + true_edge->probability = REG_BR_PROB_BASE - false_prob; | ||
| 654 | + false_edge->probability = false_prob; | ||
| 655 | + | ||
| 656 | + /* Force recalculation of dominance info. */ | ||
| 657 | + free_dominance_info (CDI_DOMINATORS); | ||
| 658 | + free_dominance_info (CDI_POST_DOMINATORS); | ||
| 659 | +} | ||
| 660 | + | ||
| 661 | +/* Create switch statement. Borrows from gimplify_switch_expr. */ | ||
| 662 | + | ||
| 663 | +static void | ||
| 664 | +convert_if_chain_to_switch (struct if_chain *chain) | ||
| 665 | +{ | ||
| 666 | + tree label_decl_true, label_decl_false; | ||
| 667 | + gimple label_true, label_false, gimple_switch; | ||
| 668 | + gimple_stmt_iterator gsi; | ||
| 669 | + tree default_case, other_case, constant; | ||
| 670 | + unsigned int ix; | ||
| 671 | + VEC (tree, heap) *labels; | ||
| 672 | + | ||
| 673 | + labels = VEC_alloc (tree, heap, 8); | ||
| 674 | + | ||
| 675 | + /* Create and insert true jump label. */ | ||
| 676 | + label_decl_true = create_artificial_label (UNKNOWN_LOCATION); | ||
| 677 | + label_true = gimple_build_label (label_decl_true); | ||
| 678 | + gsi = gsi_start_bb (chain->true_dest); | ||
| 679 | + gsi_insert_before (&gsi, label_true, GSI_SAME_STMT); | ||
| 680 | + | ||
| 681 | + /* Create and insert false jump label. */ | ||
| 682 | + label_decl_false = create_artificial_label (UNKNOWN_LOCATION); | ||
| 683 | + label_false = gimple_build_label (label_decl_false); | ||
| 684 | + gsi = gsi_start_bb (BB_IFSC_FALSE_EDGE (chain->last)->dest); | ||
| 685 | + gsi_insert_before (&gsi, label_false, GSI_SAME_STMT); | ||
| 686 | + | ||
| 687 | + /* Create default case label. */ | ||
| 688 | + default_case = build3 (CASE_LABEL_EXPR, void_type_node, | ||
| 689 | + NULL_TREE, NULL_TREE, | ||
| 690 | + label_decl_false); | ||
| 691 | + | ||
| 692 | + /* Create case labels. */ | ||
| 693 | + for (ix = 0; VEC_iterate (tree, chain->unique_constants, ix, constant); ix++) | ||
| 694 | + { | ||
| 695 | + /* TODO: use ranges, as in gimplify_switch_expr. */ | ||
| 696 | + other_case = build3 (CASE_LABEL_EXPR, void_type_node, | ||
| 697 | + constant, NULL_TREE, | ||
| 698 | + label_decl_true); | ||
| 699 | + VEC_safe_push (tree, heap, labels, other_case); | ||
| 700 | + } | ||
| 701 | + | ||
| 702 | + /* Create and insert switch. */ | ||
| 703 | + gimple_switch = gimple_build_switch_vec (chain->var, default_case, labels); | ||
| 704 | + gsi = gsi_for_stmt (last_stmt (chain->first)); | ||
| 705 | + gsi_insert_before (&gsi, gimple_switch, GSI_SAME_STMT); | ||
| 706 | + | ||
| 707 | + /* Remove now obsolete if. */ | ||
| 708 | + gsi_remove (&gsi, true); | ||
| 709 | + | ||
| 710 | + VEC_free (tree, heap, labels); | ||
| 711 | +} | ||
| 712 | + | ||
| 713 | +/* Allocation and initialization. */ | ||
| 714 | + | ||
| 715 | +static void | ||
| 716 | +init_pass (struct if_chain *chain) | ||
| 717 | +{ | ||
| 718 | + alloc_aux_for_blocks (sizeof (struct ifsc_info)); | ||
| 719 | + | ||
| 720 | + chain->constants = VEC_alloc (tree, heap, 8); | ||
| 721 | + chain->unique_constants = VEC_alloc (tree, heap, 8); | ||
| 722 | +} | ||
| 723 | + | ||
| 724 | +/* Deallocation. */ | ||
| 725 | + | ||
| 726 | +static void | ||
| 727 | +finish_pass (struct if_chain *chain) | ||
| 728 | +{ | ||
| 729 | + free_aux_for_blocks (); | ||
| 730 | + | ||
| 731 | + VEC_free (tree, heap, chain->constants); | ||
| 732 | + VEC_free (tree, heap, chain->unique_constants); | ||
| 733 | +} | ||
| 734 | + | ||
| 735 | +/* Find if-chains and convert them to switches. */ | ||
| 736 | + | ||
| 737 | +static unsigned int | ||
| 738 | +do_if_to_switch (void) | ||
| 739 | +{ | ||
| 740 | + basic_block bb; | ||
| 741 | + struct if_chain chain; | ||
| 742 | + unsigned int convert_threshold = PARAM_VALUE (PARAM_IF_TO_SWITCH_THRESHOLD); | ||
| 743 | + | ||
| 744 | + init_pass (&chain); | ||
| 745 | + | ||
| 746 | + for (bb = cfun->cfg->x_entry_block_ptr->next_bb; | ||
| 747 | + bb != cfun->cfg->x_exit_block_ptr;) | ||
| 748 | + { | ||
| 749 | + grow_if_chain (bb, &chain); | ||
| 750 | + | ||
| 751 | + do | ||
| 752 | + bb = bb->next_bb; | ||
| 753 | + while (BB_IFSC_CHAINED (bb)); | ||
| 754 | + | ||
| 755 | + /* Determine if the chain is long enough. */ | ||
| 756 | + if (VEC_length (tree, chain.unique_constants) < convert_threshold) | ||
| 757 | + continue; | ||
| 758 | + | ||
| 759 | + dump_if_chain (&chain); | ||
| 760 | + | ||
| 761 | + convert_if_chain_to_switch (&chain); | ||
| 762 | + | ||
| 763 | + update_cfg (&chain); | ||
| 764 | + } | ||
| 765 | + | ||
| 766 | + finish_pass (&chain); | ||
| 767 | + | ||
| 768 | + return 0; | ||
| 769 | +} | ||
| 770 | + | ||
| 771 | +/* The pass gate. */ | ||
| 772 | + | ||
| 773 | +static bool | ||
| 774 | +if_to_switch_gate (void) | ||
| 775 | +{ | ||
| 776 | + return flag_tree_if_to_switch_conversion; | ||
| 777 | +} | ||
| 778 | + | ||
| 779 | +/* The pass definition. */ | ||
| 780 | + | ||
| 781 | +struct gimple_opt_pass pass_if_to_switch = | ||
| 782 | +{ | ||
| 783 | + { | ||
| 784 | + GIMPLE_PASS, | ||
| 785 | + "iftoswitch", /* name */ | ||
| 786 | + if_to_switch_gate, /* gate */ | ||
| 787 | + do_if_to_switch, /* execute */ | ||
| 788 | + NULL, /* sub */ | ||
| 789 | + NULL, /* next */ | ||
| 790 | + 0, /* static_pass_number */ | ||
| 791 | + TV_TREE_SWITCH_CONVERSION, /* tv_id */ | ||
| 792 | + PROP_cfg | PROP_ssa, /* properties_required */ | ||
| 793 | + 0, /* properties_provided */ | ||
| 794 | + 0, /* properties_destroyed */ | ||
| 795 | + 0, /* todo_flags_start */ | ||
| 796 | + TODO_update_ssa | TODO_dump_func | ||
| 797 | + | TODO_ggc_collect | TODO_verify_ssa /* todo_flags_finish */ | ||
| 798 | + } | ||
| 799 | +}; | ||
| 800 | Index: gcc-4_5-branch/gcc/tree-pass.h | ||
| 801 | =================================================================== | ||
| 802 | --- gcc-4_5-branch.orig/gcc/tree-pass.h | ||
| 803 | +++ gcc-4_5-branch/gcc/tree-pass.h | ||
| 804 | @@ -560,6 +560,7 @@ extern struct gimple_opt_pass pass_inlin | ||
| 805 | extern struct gimple_opt_pass pass_all_early_optimizations; | ||
| 806 | extern struct gimple_opt_pass pass_update_address_taken; | ||
| 807 | extern struct gimple_opt_pass pass_convert_switch; | ||
| 808 | +extern struct gimple_opt_pass pass_if_to_switch; | ||
| 809 | |||
| 810 | /* The root of the compilation pass tree, once constructed. */ | ||
| 811 | extern struct opt_pass *all_passes, *all_small_ipa_passes, *all_lowering_passes, | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99473.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99473.patch deleted file mode 100644 index 3ac7f7f6f..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99473.patch +++ /dev/null | |||
| @@ -1,409 +0,0 @@ | |||
| 1 | 2010-02-04 Tom de Vries <tom@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | stmt.c (set_jump_prob): Fix assert condition. | ||
| 5 | |||
| 6 | 2010-01-27 Tom de Vries <tom@codesourcery.com> | ||
| 7 | |||
| 8 | gcc/ | ||
| 9 | stmt.c (rtx_seq_cost): Use insn_rtx_cost instead of rtx_cost. | ||
| 10 | |||
| 11 | 2010-01-26 Tom de Vries <tom@codesourcery.com> | ||
| 12 | |||
| 13 | gcc/ | ||
| 14 | * stmt.c (struct case_bit_test): Add rev_hi and rev_lo field. | ||
| 15 | * stmt.c (emit_case_bit_test_jump): New function. | ||
| 16 | * stmt.c (rtx_seq_cost): New function. | ||
| 17 | * stmt.c (choose_case_bit_test_expand_method): New function. | ||
| 18 | * stmt.c (set_bit): New function. | ||
| 19 | * stmt.c (emit_case_bit_test): Adjust comment. | ||
| 20 | * stmt.c (emit_case_bit_test): Set and update rev_hi and rev_lo fields. | ||
| 21 | * stmt.c (emit_case_bit_test): Use set_bit. | ||
| 22 | * stmt.c (emit_case_bit_test): Use choose_case_bit_test_expand_method. | ||
| 23 | * stmt.c (emit_case_bit_test): Use emit_case_bit_test_jump. | ||
| 24 | * testsuite/gcc.dg/switch-bittest.c: New test. | ||
| 25 | |||
| 26 | 2010-01-25 Tom de Vries <tom@codesourcery.com> | ||
| 27 | |||
| 28 | gcc/ | ||
| 29 | * stmt.c (emit_case_bit_tests): Change prototype. | ||
| 30 | * stmt.c (struct case_bit_test): Add prob field. | ||
| 31 | * stmt.c (get_label_prob): New function. | ||
| 32 | * stmt.c (set_jump_prob): New function. | ||
| 33 | * stmt.c (emit_case_bit_tests): Use get_label_prob. | ||
| 34 | * stmt.c (emit_case_bit_tests): Set prob field. | ||
| 35 | * stmt.c (emit_case_bit_tests): Use set_jump_prob. | ||
| 36 | * stmt.c (expand_case): Add new args to emit_case_bit_tests invocation. | ||
| 37 | * testsuite/gcc.dg/switch-prob.c: Add test. | ||
| 38 | |||
| 39 | === modified file 'gcc/stmt.c' | ||
| 40 | Index: gcc-4_5-branch/gcc/stmt.c | ||
| 41 | =================================================================== | ||
| 42 | --- gcc-4_5-branch.orig/gcc/stmt.c | ||
| 43 | +++ gcc-4_5-branch/gcc/stmt.c | ||
| 44 | @@ -117,7 +117,8 @@ static void expand_value_return (rtx); | ||
| 45 | static int estimate_case_costs (case_node_ptr); | ||
| 46 | static bool lshift_cheap_p (void); | ||
| 47 | static int case_bit_test_cmp (const void *, const void *); | ||
| 48 | -static void emit_case_bit_tests (tree, tree, tree, tree, case_node_ptr, rtx); | ||
| 49 | +static void emit_case_bit_tests (tree, tree, tree, tree, case_node_ptr, tree, | ||
| 50 | + rtx, basic_block); | ||
| 51 | static void balance_case_nodes (case_node_ptr *, case_node_ptr); | ||
| 52 | static int node_has_low_bound (case_node_ptr, tree); | ||
| 53 | static int node_has_high_bound (case_node_ptr, tree); | ||
| 54 | @@ -2107,8 +2108,11 @@ struct case_bit_test | ||
| 55 | { | ||
| 56 | HOST_WIDE_INT hi; | ||
| 57 | HOST_WIDE_INT lo; | ||
| 58 | + HOST_WIDE_INT rev_hi; | ||
| 59 | + HOST_WIDE_INT rev_lo; | ||
| 60 | rtx label; | ||
| 61 | int bits; | ||
| 62 | + int prob; | ||
| 63 | }; | ||
| 64 | |||
| 65 | /* Determine whether "1 << x" is relatively cheap in word_mode. */ | ||
| 66 | @@ -2148,10 +2152,193 @@ case_bit_test_cmp (const void *p1, const | ||
| 67 | return CODE_LABEL_NUMBER (d2->label) - CODE_LABEL_NUMBER (d1->label); | ||
| 68 | } | ||
| 69 | |||
| 70 | +/* Emit a bit test and a conditional jump. */ | ||
| 71 | + | ||
| 72 | +static void | ||
| 73 | +emit_case_bit_test_jump (unsigned int count, rtx index, rtx label, | ||
| 74 | + unsigned int method, HOST_WIDE_INT hi, | ||
| 75 | + HOST_WIDE_INT lo, HOST_WIDE_INT rev_hi, | ||
| 76 | + HOST_WIDE_INT rev_lo) | ||
| 77 | +{ | ||
| 78 | + rtx expr; | ||
| 79 | + | ||
| 80 | + if (method == 1) | ||
| 81 | + { | ||
| 82 | + /* (1 << index). */ | ||
| 83 | + if (count == 0) | ||
| 84 | + index = expand_binop (word_mode, ashl_optab, const1_rtx, | ||
| 85 | + index, NULL_RTX, 1, OPTAB_WIDEN); | ||
| 86 | + /* CST. */ | ||
| 87 | + expr = immed_double_const (lo, hi, word_mode); | ||
| 88 | + /* ((1 << index) & CST). */ | ||
| 89 | + expr = expand_binop (word_mode, and_optab, index, expr, | ||
| 90 | + NULL_RTX, 1, OPTAB_WIDEN); | ||
| 91 | + /* if (((1 << index) & CST)). */ | ||
| 92 | + emit_cmp_and_jump_insns (expr, const0_rtx, NE, NULL_RTX, | ||
| 93 | + word_mode, 1, label); | ||
| 94 | + } | ||
| 95 | + else if (method == 2) | ||
| 96 | + { | ||
| 97 | + /* (bit_reverse (CST)) */ | ||
| 98 | + expr = immed_double_const (rev_lo, rev_hi, word_mode); | ||
| 99 | + /* ((bit_reverse (CST)) << index) */ | ||
| 100 | + expr = expand_binop (word_mode, ashl_optab, expr, | ||
| 101 | + index, NULL_RTX, 1, OPTAB_WIDEN); | ||
| 102 | + /* if (((bit_reverse (CST)) << index) < 0). */ | ||
| 103 | + emit_cmp_and_jump_insns (expr, const0_rtx, LT, NULL_RTX, | ||
| 104 | + word_mode, 0, label); | ||
| 105 | + } | ||
| 106 | + else | ||
| 107 | + gcc_unreachable (); | ||
| 108 | +} | ||
| 109 | + | ||
| 110 | +/* Return the cost of rtx sequence SEQ. The sequence is supposed to contain one | ||
| 111 | + jump, which has no effect in the cost. */ | ||
| 112 | + | ||
| 113 | +static unsigned int | ||
| 114 | +rtx_seq_cost (rtx seq) | ||
| 115 | +{ | ||
| 116 | + rtx one; | ||
| 117 | + unsigned int nr_branches = 0; | ||
| 118 | + unsigned int sum = 0, cost; | ||
| 119 | + | ||
| 120 | + for (one = seq; one != NULL_RTX; one = NEXT_INSN (one)) | ||
| 121 | + if (JUMP_P (one)) | ||
| 122 | + nr_branches++; | ||
| 123 | + else | ||
| 124 | + { | ||
| 125 | + cost = insn_rtx_cost (PATTERN (one), optimize_insn_for_speed_p ()); | ||
| 126 | + if (dump_file) | ||
| 127 | + { | ||
| 128 | + print_rtl_single (dump_file, one); | ||
| 129 | + fprintf (dump_file, "cost: %u\n", cost); | ||
| 130 | + } | ||
| 131 | + sum += cost; | ||
| 132 | + } | ||
| 133 | + | ||
| 134 | + gcc_assert (nr_branches == 1); | ||
| 135 | + | ||
| 136 | + if (dump_file) | ||
| 137 | + fprintf (dump_file, "total cost: %u\n", sum); | ||
| 138 | + return sum; | ||
| 139 | +} | ||
| 140 | + | ||
| 141 | +/* Generate the rtx sequences for 2 bit test expansion methods, measure the cost | ||
| 142 | + and choose the cheapest. */ | ||
| 143 | + | ||
| 144 | +static unsigned int | ||
| 145 | +choose_case_bit_test_expand_method (rtx label) | ||
| 146 | +{ | ||
| 147 | + rtx seq, index; | ||
| 148 | + unsigned int cost[2]; | ||
| 149 | + static bool method_known = false; | ||
| 150 | + static unsigned int method; | ||
| 151 | + | ||
| 152 | + /* If already known, return the method. */ | ||
| 153 | + if (method_known) | ||
| 154 | + return method; | ||
| 155 | + | ||
| 156 | + index = gen_rtx_REG (word_mode, 10000); | ||
| 157 | + | ||
| 158 | + for (method = 1; method <= 2; ++method) | ||
| 159 | + { | ||
| 160 | + start_sequence (); | ||
| 161 | + emit_case_bit_test_jump (0, index, label, method, 0, 0x0f0f0f0f, 0, | ||
| 162 | + 0x0f0f0f0f); | ||
| 163 | + seq = get_insns (); | ||
| 164 | + end_sequence (); | ||
| 165 | + cost[method - 1] = rtx_seq_cost (seq); | ||
| 166 | + } | ||
| 167 | + | ||
| 168 | + /* Determine method based on heuristic. */ | ||
| 169 | + method = ((cost[1] < cost[0]) ? 1 : 0) + 1; | ||
| 170 | + | ||
| 171 | + /* Save and return method. */ | ||
| 172 | + method_known = true; | ||
| 173 | + return method; | ||
| 174 | +} | ||
| 175 | + | ||
| 176 | +/* Get the edge probability of the edge from SRC to LABEL_DECL. */ | ||
| 177 | + | ||
| 178 | +static int | ||
| 179 | +get_label_prob (basic_block src, tree label_decl) | ||
| 180 | +{ | ||
| 181 | + basic_block dest; | ||
| 182 | + int prob = 0, nr_prob = 0; | ||
| 183 | + unsigned int i; | ||
| 184 | + edge e; | ||
| 185 | + | ||
| 186 | + if (label_decl == NULL_TREE) | ||
| 187 | + return 0; | ||
| 188 | + | ||
| 189 | + dest = VEC_index (basic_block, label_to_block_map, | ||
| 190 | + LABEL_DECL_UID (label_decl)); | ||
| 191 | + | ||
| 192 | + for (i = 0; i < EDGE_COUNT (src->succs); ++i) | ||
| 193 | + { | ||
| 194 | + e = EDGE_SUCC (src, i); | ||
| 195 | + | ||
| 196 | + if (e->dest != dest) | ||
| 197 | + continue; | ||
| 198 | + | ||
| 199 | + prob += e->probability; | ||
| 200 | + nr_prob++; | ||
| 201 | + } | ||
| 202 | + | ||
| 203 | + gcc_assert (nr_prob == 1); | ||
| 204 | + | ||
| 205 | + return prob; | ||
| 206 | +} | ||
| 207 | + | ||
| 208 | +/* Add probability note with scaled PROB to JUMP and update INV_SCALE. This | ||
| 209 | + function is intended to be used with a series of conditional jumps to L[i] | ||
| 210 | + where the probabilities p[i] to get to L[i] are known, and the jump | ||
| 211 | + probabilities j[i] need to be computed. | ||
| 212 | + | ||
| 213 | + The algorithm to calculate the probabilities is | ||
| 214 | + | ||
| 215 | + scale = REG_BR_PROB_BASE; | ||
| 216 | + for (i = 0; i < n; ++i) | ||
| 217 | + { | ||
| 218 | + j[i] = p[i] * scale / REG_BR_PROB_BASE; | ||
| 219 | + f[i] = REG_BR_PROB_BASE - j[i]; | ||
| 220 | + scale = scale / (f[i] / REG_BR_PROB_BASE); | ||
| 221 | + } | ||
| 222 | + | ||
| 223 | + The implementation uses inv_scale (REG_BR_PROB_BASE / scale) instead of | ||
| 224 | + scale, because scale tends to grow bigger than REG_BR_PROB_BASE. */ | ||
| 225 | + | ||
| 226 | +static void | ||
| 227 | +set_jump_prob (rtx jump, int prob, int *inv_scale) | ||
| 228 | +{ | ||
| 229 | + /* j[i] = p[i] * scale / REG_BR_PROB_BASE. */ | ||
| 230 | + int jump_prob = prob * REG_BR_PROB_BASE / *inv_scale; | ||
| 231 | + /* f[i] = REG_BR_PROB_BASE - j[i]. */ | ||
| 232 | + int fallthrough_prob = REG_BR_PROB_BASE - jump_prob; | ||
| 233 | + | ||
| 234 | + gcc_assert (jump_prob <= REG_BR_PROB_BASE); | ||
| 235 | + add_reg_note (jump, REG_BR_PROB, GEN_INT (jump_prob)); | ||
| 236 | + | ||
| 237 | + /* scale = scale / (f[i] / REG_BR_PROB_BASE). */ | ||
| 238 | + *inv_scale = *inv_scale * fallthrough_prob / REG_BR_PROB_BASE; | ||
| 239 | +} | ||
| 240 | + | ||
| 241 | +/* Set bit in hwi hi/lo pair. */ | ||
| 242 | + | ||
| 243 | +static void | ||
| 244 | +set_bit (HOST_WIDE_INT *hi, HOST_WIDE_INT *lo, unsigned int j) | ||
| 245 | +{ | ||
| 246 | + if (j >= HOST_BITS_PER_WIDE_INT) | ||
| 247 | + *hi |= (HOST_WIDE_INT) 1 << (j - HOST_BITS_PER_INT); | ||
| 248 | + else | ||
| 249 | + *lo |= (HOST_WIDE_INT) 1 << j; | ||
| 250 | +} | ||
| 251 | + | ||
| 252 | /* Expand a switch statement by a short sequence of bit-wise | ||
| 253 | comparisons. "switch(x)" is effectively converted into | ||
| 254 | - "if ((1 << (x-MINVAL)) & CST)" where CST and MINVAL are | ||
| 255 | - integer constants. | ||
| 256 | + "if ((1 << (x-MINVAL)) & CST)" or | ||
| 257 | + "if (((bit_reverse (CST)) << (x-MINVAL)) < 0)", where CST | ||
| 258 | + and MINVAL are integer constants. | ||
| 259 | |||
| 260 | INDEX_EXPR is the value being switched on, which is of | ||
| 261 | type INDEX_TYPE. MINVAL is the lowest case value of in | ||
| 262 | @@ -2165,14 +2352,17 @@ case_bit_test_cmp (const void *p1, const | ||
| 263 | |||
| 264 | static void | ||
| 265 | emit_case_bit_tests (tree index_type, tree index_expr, tree minval, | ||
| 266 | - tree range, case_node_ptr nodes, rtx default_label) | ||
| 267 | + tree range, case_node_ptr nodes, tree default_label_decl, | ||
| 268 | + rtx default_label, basic_block bb) | ||
| 269 | { | ||
| 270 | struct case_bit_test test[MAX_CASE_BIT_TESTS]; | ||
| 271 | enum machine_mode mode; | ||
| 272 | rtx expr, index, label; | ||
| 273 | unsigned int i,j,lo,hi; | ||
| 274 | struct case_node *n; | ||
| 275 | - unsigned int count; | ||
| 276 | + unsigned int count, method; | ||
| 277 | + int inv_scale = REG_BR_PROB_BASE; | ||
| 278 | + int default_prob = get_label_prob (bb, default_label_decl); | ||
| 279 | |||
| 280 | count = 0; | ||
| 281 | for (n = nodes; n; n = n->right) | ||
| 282 | @@ -2187,8 +2377,11 @@ emit_case_bit_tests (tree index_type, tr | ||
| 283 | gcc_assert (count < MAX_CASE_BIT_TESTS); | ||
| 284 | test[i].hi = 0; | ||
| 285 | test[i].lo = 0; | ||
| 286 | + test[i].rev_hi = 0; | ||
| 287 | + test[i].rev_lo = 0; | ||
| 288 | test[i].label = label; | ||
| 289 | test[i].bits = 1; | ||
| 290 | + test[i].prob = get_label_prob (bb, n->code_label); | ||
| 291 | count++; | ||
| 292 | } | ||
| 293 | else | ||
| 294 | @@ -2199,10 +2392,11 @@ emit_case_bit_tests (tree index_type, tr | ||
| 295 | hi = tree_low_cst (fold_build2 (MINUS_EXPR, index_type, | ||
| 296 | n->high, minval), 1); | ||
| 297 | for (j = lo; j <= hi; j++) | ||
| 298 | - if (j >= HOST_BITS_PER_WIDE_INT) | ||
| 299 | - test[i].hi |= (HOST_WIDE_INT) 1 << (j - HOST_BITS_PER_INT); | ||
| 300 | - else | ||
| 301 | - test[i].lo |= (HOST_WIDE_INT) 1 << j; | ||
| 302 | + { | ||
| 303 | + set_bit (&test[i].hi, &test[i].lo, j); | ||
| 304 | + set_bit (&test[i].rev_hi, &test[i].rev_lo, | ||
| 305 | + GET_MODE_BITSIZE (word_mode) - j - 1); | ||
| 306 | + } | ||
| 307 | } | ||
| 308 | |||
| 309 | qsort (test, count, sizeof(*test), case_bit_test_cmp); | ||
| 310 | @@ -2216,20 +2410,20 @@ emit_case_bit_tests (tree index_type, tr | ||
| 311 | mode = TYPE_MODE (index_type); | ||
| 312 | expr = expand_normal (range); | ||
| 313 | if (default_label) | ||
| 314 | - emit_cmp_and_jump_insns (index, expr, GTU, NULL_RTX, mode, 1, | ||
| 315 | - default_label); | ||
| 316 | + { | ||
| 317 | + emit_cmp_and_jump_insns (index, expr, GTU, NULL_RTX, mode, 1, | ||
| 318 | + default_label); | ||
| 319 | + set_jump_prob (get_last_insn (), default_prob / 2, &inv_scale); | ||
| 320 | + } | ||
| 321 | |||
| 322 | index = convert_to_mode (word_mode, index, 0); | ||
| 323 | - index = expand_binop (word_mode, ashl_optab, const1_rtx, | ||
| 324 | - index, NULL_RTX, 1, OPTAB_WIDEN); | ||
| 325 | |||
| 326 | + method = choose_case_bit_test_expand_method (test[0].label); | ||
| 327 | for (i = 0; i < count; i++) | ||
| 328 | { | ||
| 329 | - expr = immed_double_const (test[i].lo, test[i].hi, word_mode); | ||
| 330 | - expr = expand_binop (word_mode, and_optab, index, expr, | ||
| 331 | - NULL_RTX, 1, OPTAB_WIDEN); | ||
| 332 | - emit_cmp_and_jump_insns (expr, const0_rtx, NE, NULL_RTX, | ||
| 333 | - word_mode, 1, test[i].label); | ||
| 334 | + emit_case_bit_test_jump (i, index, test[i].label, method, test[i].hi, | ||
| 335 | + test[i].lo, test[i].rev_hi, test[i].rev_lo); | ||
| 336 | + set_jump_prob (get_last_insn (), test[i].prob, &inv_scale); | ||
| 337 | } | ||
| 338 | |||
| 339 | if (default_label) | ||
| 340 | @@ -2400,7 +2594,8 @@ expand_case (gimple stmt) | ||
| 341 | range = maxval; | ||
| 342 | } | ||
| 343 | emit_case_bit_tests (index_type, index_expr, minval, range, | ||
| 344 | - case_list, default_label); | ||
| 345 | + case_list, default_label_decl, default_label, | ||
| 346 | + gimple_bb (stmt)); | ||
| 347 | } | ||
| 348 | |||
| 349 | /* If range of values is much bigger than number of values, | ||
| 350 | Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/switch-bittest.c | ||
| 351 | =================================================================== | ||
| 352 | --- /dev/null | ||
| 353 | +++ gcc-4_5-branch/gcc/testsuite/gcc.dg/switch-bittest.c | ||
| 354 | @@ -0,0 +1,25 @@ | ||
| 355 | +/* { dg-do compile } */ | ||
| 356 | +/* { dg-options "-O2 -fdump-rtl-expand" } */ | ||
| 357 | + | ||
| 358 | +const char * | ||
| 359 | +f (const char *p) | ||
| 360 | +{ | ||
| 361 | + while (1) | ||
| 362 | + { | ||
| 363 | + switch (*p) | ||
| 364 | + { | ||
| 365 | + case 9: | ||
| 366 | + case 10: | ||
| 367 | + case 13: | ||
| 368 | + case 32: | ||
| 369 | + break; | ||
| 370 | + default: | ||
| 371 | + return p; | ||
| 372 | + } | ||
| 373 | + } | ||
| 374 | +} | ||
| 375 | + | ||
| 376 | +/* { dg-final { scan-rtl-dump-times "jump_insn" 4 "expand" { target mips*-*-* } } } */ | ||
| 377 | +/* { dg-final { scan-rtl-dump-times "REG_BR_PROB" 2 "expand" { target mips*-*-* } } } */ | ||
| 378 | +/* { dg-final { scan-rtl-dump-times "lt " 1 "expand" { target mips*-*-* } } } */ | ||
| 379 | +/* { dg-final { cleanup-rtl-dump "expand" } } */ | ||
| 380 | Index: gcc-4_5-branch/gcc/testsuite/gcc.dg/switch-prob.c | ||
| 381 | =================================================================== | ||
| 382 | --- /dev/null | ||
| 383 | +++ gcc-4_5-branch/gcc/testsuite/gcc.dg/switch-prob.c | ||
| 384 | @@ -0,0 +1,25 @@ | ||
| 385 | +/* { dg-do compile } */ | ||
| 386 | +/* { dg-options "-O2 -fdump-rtl-expand" } */ | ||
| 387 | + | ||
| 388 | +const char * | ||
| 389 | +f (const char *p) | ||
| 390 | +{ | ||
| 391 | + while (1) | ||
| 392 | + { | ||
| 393 | + switch (*p) | ||
| 394 | + { | ||
| 395 | + case 9: | ||
| 396 | + case 10: | ||
| 397 | + case 13: | ||
| 398 | + case 32: | ||
| 399 | + break; | ||
| 400 | + default: | ||
| 401 | + return p; | ||
| 402 | + } | ||
| 403 | + } | ||
| 404 | +} | ||
| 405 | + | ||
| 406 | +/* { dg-final { scan-rtl-dump-times "jump_insn" 4 "expand" { target mips*-*-* } } } */ | ||
| 407 | +/* { dg-final { scan-rtl-dump-times "REG_BR_PROB" 2 "expand" { target mips*-*-* } } } */ | ||
| 408 | +/* { dg-final { scan-rtl-dump-times "heuristics" 0 "expand" { target mips*-*-* } } } */ | ||
| 409 | +/* { dg-final { cleanup-rtl-dump "expand" } } */ | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99474.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99474.patch deleted file mode 100644 index 9b0fb0b48..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99474.patch +++ /dev/null | |||
| @@ -1,3346 +0,0 @@ | |||
| 1 | 2011-01-14 Bernd Schmidt <bernds@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * function.c (thread_prologue_and_epilogue_insns): Avoid uninitialized | ||
| 5 | variable. | ||
| 6 | |||
| 7 | 2011-01-12 Bernd Schmidt <bernds@codesourcery.com> | ||
| 8 | |||
| 9 | gcc/ | ||
| 10 | * config/s390/s390.c (s390_emit_epilogue): Don't use gen_rtx_RETURN. | ||
| 11 | * config/rx/rx.c (gen_rx_rtsd_vector): Likewise. | ||
| 12 | * config/m68hc11/m68hc11.md (return): Likewise. | ||
| 13 | * config/cris/cris.c (cris_expand_return): Likewise. | ||
| 14 | * config/m68k/m68k.c (m68k_expand_epilogue): Likewise. | ||
| 15 | * config/picochip/picochip.c (picochip_expand_epilogue): Likewise. | ||
| 16 | * config/h8300/h8300.c (h8300_push_pop, h8300_expand_epilogue): | ||
| 17 | Likewise. | ||
| 18 | * config/v850/v850.c (expand_epilogue): Likewise. | ||
| 19 | * config/bfin/bfin.c (bfin_expand_call): Likewise. | ||
| 20 | |||
| 21 | 2011-01-04 Catherine Moore <clm@codesourcery.com> | ||
| 22 | |||
| 23 | gcc/ | ||
| 24 | * config/rs6000/rs6000.c (rs6000_make_savres_rtx): Change | ||
| 25 | gen_rtx_RETURN to ret_rtx. | ||
| 26 | (rs6000_emit_epilogue): Likewise. | ||
| 27 | (rs6000_output_mi_thunk): Likewise. | ||
| 28 | |||
| 29 | 2011-01-03 Bernd Schmidt <bernds@codesourcery.com> | ||
| 30 | |||
| 31 | gcc/ | ||
| 32 | * doc/tm.texi (RETURN_ADDR_REGNUM): Document. | ||
| 33 | * doc/md.texi (simple_return): Document pattern. | ||
| 34 | (return): Add a sentence to clarify. | ||
| 35 | * doc/rtl.texi (simple_return): Document. | ||
| 36 | * doc/invoke.texi (Optimize Options): Document -fshrink-wrap. | ||
| 37 | * common.opt (fshrink-wrap): New. | ||
| 38 | * opts.c (decode_options): Set it for -O2 and above. | ||
| 39 | * gengenrtl.c (special_rtx): PC, CC0, RETURN and SIMPLE_RETURN | ||
| 40 | are special. | ||
| 41 | * rtl.h (ANY_RETURN_P): New macro. | ||
| 42 | (global_rtl_index): Add GR_RETURN and GR_SIMPLE_RETURN. | ||
| 43 | (ret_rtx, simple_return_rtx): New macros. | ||
| 44 | * genemit.c (gen_exp): RETURN and SIMPLE_RETURN have unique rtxs. | ||
| 45 | (gen_expand, gen_split): Use ANY_RETURN_P. | ||
| 46 | * rtl.c (copy_rtx): RETURN and SIMPLE_RETURN are shared. | ||
| 47 | * emit-rtl.c (verify_rtx_sharing): Likewise. | ||
| 48 | (skip_consecutive_labels): Return the argument if it is a return rtx. | ||
| 49 | (classify_insn): Handle both kinds of return. | ||
| 50 | (init_emit_regs): Create global rtl for ret_rtx and simple_return_rtx. | ||
| 51 | * df-scan.c (df_uses_record): Handle SIMPLE_RETURN. | ||
| 52 | * rtl.def (SIMPLE_RETURN): New. | ||
| 53 | * rtlanal.c (tablejump_p): Check JUMP_LABEL for returns. | ||
| 54 | * final.c (final_scan_insn): Recognize both kinds of return. | ||
| 55 | * reorg.c (function_return_label, function_simple_return_label): New | ||
| 56 | static variables. | ||
| 57 | (end_of_function_label): Remove. | ||
| 58 | (simplejump_or_return_p): New static function. | ||
| 59 | (find_end_label): Add a new arg, KIND. All callers changed. | ||
| 60 | Depending on KIND, look for a label suitable for return or | ||
| 61 | simple_return. | ||
| 62 | (make_return_insns): Make corresponding changes. | ||
| 63 | (get_jump_flags): Check JUMP_LABELs for returns. | ||
| 64 | (follow_jumps): Likewise. | ||
| 65 | (get_branch_condition): Check target for return patterns rather | ||
| 66 | than NULL. | ||
| 67 | (own_thread_p): Likewise for thread. | ||
| 68 | (steal_delay_list_from_target): Check JUMP_LABELs for returns. | ||
| 69 | Use simplejump_or_return_p. | ||
| 70 | (fill_simple_delay_slots): Likewise. | ||
| 71 | (optimize_skip): Likewise. | ||
| 72 | (fill_slots_from_thread): Likewise. | ||
| 73 | (relax_delay_slots): Likewise. | ||
| 74 | (dbr_schedule): Adjust handling of end_of_function_label for the | ||
| 75 | two new variables. | ||
| 76 | * ifcvt.c (find_if_case_1): Take care when redirecting jumps to the | ||
| 77 | exit block. | ||
| 78 | (dead_or_predicable): Change NEW_DEST arg to DEST_EDGE. All callers | ||
| 79 | changed. Ensure that the right label is passed to redirect_jump. | ||
| 80 | * jump.c (condjump_p, condjump_in_parallel_p, any_condjump_p, | ||
| 81 | returnjump_p): Handle SIMPLE_RETURNs. | ||
| 82 | (delete_related_insns): Check JUMP_LABEL for returns. | ||
| 83 | (redirect_target): New static function. | ||
| 84 | (redirect_exp_1): Use it. Handle any kind of return rtx as a label | ||
| 85 | rather than interpreting NULL as a return. | ||
| 86 | (redirect_jump_1): Assert that nlabel is not NULL. | ||
| 87 | (redirect_jump): Likewise. | ||
| 88 | (redirect_jump_2): Handle any kind of return rtx as a label rather | ||
| 89 | than interpreting NULL as a return. | ||
| 90 | * dwarf2out.c (compute_barrier_args_size_1): Check JUMP_LABEL for | ||
| 91 | returns. | ||
| 92 | * function.c (emit_return_into_block): Remove useless declaration. | ||
| 93 | (record_hard_reg_sets, frame_required_for_rtx, gen_return_pattern, | ||
| 94 | requires_stack_frame_p): New static functions. | ||
| 95 | (emit_return_into_block): New arg SIMPLE_P. All callers changed. | ||
| 96 | Generate either kind of return pattern and update the JUMP_LABEL. | ||
| 97 | (thread_prologue_and_epilogue_insns): Implement a form of | ||
| 98 | shrink-wrapping. Ensure JUMP_LABELs for return insns are set. | ||
| 99 | * print-rtl.c (print_rtx): Handle returns in JUMP_LABELs. | ||
| 100 | * cfglayout.c (fixup_reorder_chain): Ensure JUMP_LABELs for returns | ||
| 101 | remain correct. | ||
| 102 | * resource.c (find_dead_or_set_registers): Check JUMP_LABELs for | ||
| 103 | returns. | ||
| 104 | (mark_target_live_regs): Don't pass a return rtx to next_active_insn. | ||
| 105 | * basic-block.h (force_nonfallthru_and_redirect): Declare. | ||
| 106 | * sched-vis.c (print_pattern): Add case for SIMPLE_RETURN. | ||
| 107 | * cfgrtl.c (force_nonfallthru_and_redirect): No longer static. New arg | ||
| 108 | JUMP_LABEL. All callers changed. Use the label when generating | ||
| 109 | return insns. | ||
| 110 | |||
| 111 | * config/i386/i386.md (returns, return_str, return_cond): New | ||
| 112 | code_iterator and corresponding code_attrs. | ||
| 113 | (<return_str>return): Renamed from return and adapted. | ||
| 114 | (<return_str>return_internal): Likewise for return_internal. | ||
| 115 | (<return_str>return_internal_long): Likewise for return_internal_long. | ||
| 116 | (<return_str>return_pop_internal): Likewise for return_pop_internal. | ||
| 117 | (<return_str>return_indirect_internal): Likewise for | ||
| 118 | return_indirect_internal. | ||
| 119 | * config/i386/i386.c (ix86_expand_epilogue): Expand a simple_return as | ||
| 120 | the last insn. | ||
| 121 | (ix86_pad_returns): Handle both kinds of return rtx. | ||
| 122 | * config/arm/arm.c (use_simple_return_p): new function. | ||
| 123 | (is_jump_table): Handle returns in JUMP_LABELs. | ||
| 124 | (output_return_instruction): New arg SIMPLE. All callers changed. | ||
| 125 | Use it to determine which kind of return to generate. | ||
| 126 | (arm_final_prescan_insn): Handle both kinds of return. | ||
| 127 | * config/arm/arm.md (returns, return_str, return_simple_p, | ||
| 128 | return_cond): New code_iterator and corresponding code_attrs. | ||
| 129 | (<return_str>return): Renamed from return and adapted. | ||
| 130 | (arm_<return_str>return): Renamed from arm_return and adapted. | ||
| 131 | (cond_<return_str>return): Renamed from cond_return and adapted. | ||
| 132 | (cond_<return_str>return_inverted): Renamed from cond_return_inverted | ||
| 133 | and adapted. | ||
| 134 | (epilogue): Use ret_rtx instead of gen_rtx_RETURN. | ||
| 135 | * config/arm/thumb2.md (thumb2_<return_str>return): Renamed from | ||
| 136 | thumb2_return and adapted. | ||
| 137 | * config/arm/arm.h (RETURN_ADDR_REGNUM): Define. | ||
| 138 | * config/arm/arm-protos.h (use_simple_return_p): Declare. | ||
| 139 | (output_return_instruction): Adjust declaration. | ||
| 140 | * config/mips/mips.c (mips_expand_epilogue): Generate a simple_return | ||
| 141 | as final insn. | ||
| 142 | * config/mips/mips.md (simple_return): New expander. | ||
| 143 | (*simple_return, simple_return_internal): New patterns. | ||
| 144 | * config/sh/sh.c (barrier_align): Handle return in a JUMP_LABEL. | ||
| 145 | (split_branches): Don't pass a null label to redirect_jump. | ||
| 146 | |||
| 147 | From mainline: | ||
| 148 | * vec.h (FOR_EACH_VEC_ELT, FOR_EACH_VEC_ELT_REVERSE): New macros. | ||
| 149 | * haifa-sched.c (find_fallthru_edge_from): Rename from | ||
| 150 | find_fallthru_edge. All callers changed. | ||
| 151 | * sched-int.h (find_fallthru_edge_from): Rename declaration as well. | ||
| 152 | * basic-block.h (find_fallthru_edge): New inline function. | ||
| 153 | |||
| 154 | === modified file 'gcc/basic-block.h' | ||
| 155 | Index: gcc-4_5-branch/gcc/basic-block.h | ||
| 156 | =================================================================== | ||
| 157 | --- gcc-4_5-branch.orig/gcc/basic-block.h | ||
| 158 | +++ gcc-4_5-branch/gcc/basic-block.h | ||
| 159 | @@ -884,6 +884,7 @@ extern void flow_edge_list_print (const | ||
| 160 | |||
| 161 | /* In cfgrtl.c */ | ||
| 162 | extern basic_block force_nonfallthru (edge); | ||
| 163 | +extern basic_block force_nonfallthru_and_redirect (edge, basic_block, rtx); | ||
| 164 | extern rtx block_label (basic_block); | ||
| 165 | extern bool purge_all_dead_edges (void); | ||
| 166 | extern bool purge_dead_edges (basic_block); | ||
| 167 | @@ -1004,6 +1005,20 @@ bb_has_abnormal_pred (basic_block bb) | ||
| 168 | return false; | ||
| 169 | } | ||
| 170 | |||
| 171 | +/* Return the fallthru edge in EDGES if it exists, NULL otherwise. */ | ||
| 172 | +static inline edge | ||
| 173 | +find_fallthru_edge (VEC(edge,gc) *edges) | ||
| 174 | +{ | ||
| 175 | + edge e; | ||
| 176 | + edge_iterator ei; | ||
| 177 | + | ||
| 178 | + FOR_EACH_EDGE (e, ei, edges) | ||
| 179 | + if (e->flags & EDGE_FALLTHRU) | ||
| 180 | + break; | ||
| 181 | + | ||
| 182 | + return e; | ||
| 183 | +} | ||
| 184 | + | ||
| 185 | /* In cfgloopmanip.c. */ | ||
| 186 | extern edge mfb_kj_edge; | ||
| 187 | extern bool mfb_keep_just (edge); | ||
| 188 | Index: gcc-4_5-branch/gcc/cfganal.c | ||
| 189 | =================================================================== | ||
| 190 | --- gcc-4_5-branch.orig/gcc/cfganal.c | ||
| 191 | +++ gcc-4_5-branch/gcc/cfganal.c | ||
| 192 | @@ -271,6 +271,37 @@ set_edge_can_fallthru_flag (void) | ||
| 193 | EDGE_SUCC (bb, 0)->flags |= EDGE_CAN_FALLTHRU; | ||
| 194 | EDGE_SUCC (bb, 1)->flags |= EDGE_CAN_FALLTHRU; | ||
| 195 | } | ||
| 196 | + /* dwarf2out expects that a NOTE_INSN_EPILOGUE_BEGIN is always paired | ||
| 197 | + with a return or a sibcall. Ensure that this remains the case if | ||
| 198 | + they are in different basic blocks. */ | ||
| 199 | + FOR_EACH_BB (bb) | ||
| 200 | + { | ||
| 201 | + edge e; | ||
| 202 | + edge_iterator ei; | ||
| 203 | + rtx insn, end; | ||
| 204 | + | ||
| 205 | + end = BB_END (bb); | ||
| 206 | + FOR_BB_INSNS (bb, insn) | ||
| 207 | + if (GET_CODE (insn) == NOTE | ||
| 208 | + && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG | ||
| 209 | + && !(CALL_P (end) && SIBLING_CALL_P (end)) | ||
| 210 | + && !returnjump_p (end)) | ||
| 211 | + { | ||
| 212 | + basic_block other_bb = NULL; | ||
| 213 | + FOR_EACH_EDGE (e, ei, bb->succs) | ||
| 214 | + { | ||
| 215 | + if (e->flags & EDGE_FALLTHRU) | ||
| 216 | + other_bb = e->dest; | ||
| 217 | + else | ||
| 218 | + e->flags &= ~EDGE_CAN_FALLTHRU; | ||
| 219 | + } | ||
| 220 | + FOR_EACH_EDGE (e, ei, other_bb->preds) | ||
| 221 | + { | ||
| 222 | + if (!(e->flags & EDGE_FALLTHRU)) | ||
| 223 | + e->flags &= ~EDGE_CAN_FALLTHRU; | ||
| 224 | + } | ||
| 225 | + } | ||
| 226 | + } | ||
| 227 | } | ||
| 228 | |||
| 229 | /* Find unreachable blocks. An unreachable block will have 0 in | ||
| 230 | Index: gcc-4_5-branch/gcc/cfglayout.c | ||
| 231 | =================================================================== | ||
| 232 | --- gcc-4_5-branch.orig/gcc/cfglayout.c | ||
| 233 | +++ gcc-4_5-branch/gcc/cfglayout.c | ||
| 234 | @@ -766,6 +766,7 @@ fixup_reorder_chain (void) | ||
| 235 | { | ||
| 236 | edge e_fall, e_taken, e; | ||
| 237 | rtx bb_end_insn; | ||
| 238 | + rtx ret_label = NULL_RTX; | ||
| 239 | basic_block nb; | ||
| 240 | edge_iterator ei; | ||
| 241 | |||
| 242 | @@ -785,6 +786,7 @@ fixup_reorder_chain (void) | ||
| 243 | bb_end_insn = BB_END (bb); | ||
| 244 | if (JUMP_P (bb_end_insn)) | ||
| 245 | { | ||
| 246 | + ret_label = JUMP_LABEL (bb_end_insn); | ||
| 247 | if (any_condjump_p (bb_end_insn)) | ||
| 248 | { | ||
| 249 | /* This might happen if the conditional jump has side | ||
| 250 | @@ -899,7 +901,7 @@ fixup_reorder_chain (void) | ||
| 251 | } | ||
| 252 | |||
| 253 | /* We got here if we need to add a new jump insn. */ | ||
| 254 | - nb = force_nonfallthru (e_fall); | ||
| 255 | + nb = force_nonfallthru_and_redirect (e_fall, e_fall->dest, ret_label); | ||
| 256 | if (nb) | ||
| 257 | { | ||
| 258 | nb->il.rtl->visited = 1; | ||
| 259 | @@ -1118,24 +1120,30 @@ extern bool cfg_layout_can_duplicate_bb_ | ||
| 260 | bool | ||
| 261 | cfg_layout_can_duplicate_bb_p (const_basic_block bb) | ||
| 262 | { | ||
| 263 | + rtx insn; | ||
| 264 | + | ||
| 265 | /* Do not attempt to duplicate tablejumps, as we need to unshare | ||
| 266 | the dispatch table. This is difficult to do, as the instructions | ||
| 267 | computing jump destination may be hoisted outside the basic block. */ | ||
| 268 | if (tablejump_p (BB_END (bb), NULL, NULL)) | ||
| 269 | return false; | ||
| 270 | |||
| 271 | - /* Do not duplicate blocks containing insns that can't be copied. */ | ||
| 272 | - if (targetm.cannot_copy_insn_p) | ||
| 273 | + insn = BB_HEAD (bb); | ||
| 274 | + while (1) | ||
| 275 | { | ||
| 276 | - rtx insn = BB_HEAD (bb); | ||
| 277 | - while (1) | ||
| 278 | - { | ||
| 279 | - if (INSN_P (insn) && targetm.cannot_copy_insn_p (insn)) | ||
| 280 | - return false; | ||
| 281 | - if (insn == BB_END (bb)) | ||
| 282 | - break; | ||
| 283 | - insn = NEXT_INSN (insn); | ||
| 284 | - } | ||
| 285 | + /* Do not duplicate blocks containing insns that can't be copied. */ | ||
| 286 | + if (INSN_P (insn) && targetm.cannot_copy_insn_p | ||
| 287 | + && targetm.cannot_copy_insn_p (insn)) | ||
| 288 | + return false; | ||
| 289 | + /* dwarf2out expects that these notes are always paired with a | ||
| 290 | + returnjump or sibling call. */ | ||
| 291 | + if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG | ||
| 292 | + && !returnjump_p (BB_END (bb)) | ||
| 293 | + && (!CALL_P (BB_END (bb)) || !SIBLING_CALL_P (BB_END (bb)))) | ||
| 294 | + return false; | ||
| 295 | + if (insn == BB_END (bb)) | ||
| 296 | + break; | ||
| 297 | + insn = NEXT_INSN (insn); | ||
| 298 | } | ||
| 299 | |||
| 300 | return true; | ||
| 301 | @@ -1180,6 +1188,9 @@ duplicate_insn_chain (rtx from, rtx to) | ||
| 302 | break; | ||
| 303 | } | ||
| 304 | copy = emit_copy_of_insn_after (insn, get_last_insn ()); | ||
| 305 | + if (JUMP_P (insn) && JUMP_LABEL (insn) != NULL_RTX | ||
| 306 | + && ANY_RETURN_P (JUMP_LABEL (insn))) | ||
| 307 | + JUMP_LABEL (copy) = JUMP_LABEL (insn); | ||
| 308 | maybe_copy_epilogue_insn (insn, copy); | ||
| 309 | break; | ||
| 310 | |||
| 311 | Index: gcc-4_5-branch/gcc/cfgrtl.c | ||
| 312 | =================================================================== | ||
| 313 | --- gcc-4_5-branch.orig/gcc/cfgrtl.c | ||
| 314 | +++ gcc-4_5-branch/gcc/cfgrtl.c | ||
| 315 | @@ -1107,10 +1107,13 @@ rtl_redirect_edge_and_branch (edge e, ba | ||
| 316 | } | ||
| 317 | |||
| 318 | /* Like force_nonfallthru below, but additionally performs redirection | ||
| 319 | - Used by redirect_edge_and_branch_force. */ | ||
| 320 | + Used by redirect_edge_and_branch_force. JUMP_LABEL is used only | ||
| 321 | + when redirecting to the EXIT_BLOCK, it is either a return or a | ||
| 322 | + simple_return rtx indicating which kind of returnjump to create. | ||
| 323 | + It should be NULL otherwise. */ | ||
| 324 | |||
| 325 | -static basic_block | ||
| 326 | -force_nonfallthru_and_redirect (edge e, basic_block target) | ||
| 327 | +basic_block | ||
| 328 | +force_nonfallthru_and_redirect (edge e, basic_block target, rtx jump_label) | ||
| 329 | { | ||
| 330 | basic_block jump_block, new_bb = NULL, src = e->src; | ||
| 331 | rtx note; | ||
| 332 | @@ -1242,11 +1245,25 @@ force_nonfallthru_and_redirect (edge e, | ||
| 333 | e->flags &= ~EDGE_FALLTHRU; | ||
| 334 | if (target == EXIT_BLOCK_PTR) | ||
| 335 | { | ||
| 336 | + if (jump_label == ret_rtx) | ||
| 337 | + { | ||
| 338 | #ifdef HAVE_return | ||
| 339 | - emit_jump_insn_after_setloc (gen_return (), BB_END (jump_block), loc); | ||
| 340 | + emit_jump_insn_after_setloc (gen_return (), BB_END (jump_block), | ||
| 341 | + loc); | ||
| 342 | #else | ||
| 343 | - gcc_unreachable (); | ||
| 344 | + gcc_unreachable (); | ||
| 345 | #endif | ||
| 346 | + } | ||
| 347 | + else | ||
| 348 | + { | ||
| 349 | + gcc_assert (jump_label == simple_return_rtx); | ||
| 350 | +#ifdef HAVE_simple_return | ||
| 351 | + emit_jump_insn_after_setloc (gen_simple_return (), | ||
| 352 | + BB_END (jump_block), loc); | ||
| 353 | +#else | ||
| 354 | + gcc_unreachable (); | ||
| 355 | +#endif | ||
| 356 | + } | ||
| 357 | } | ||
| 358 | else | ||
| 359 | { | ||
| 360 | @@ -1273,7 +1290,7 @@ force_nonfallthru_and_redirect (edge e, | ||
| 361 | basic_block | ||
| 362 | force_nonfallthru (edge e) | ||
| 363 | { | ||
| 364 | - return force_nonfallthru_and_redirect (e, e->dest); | ||
| 365 | + return force_nonfallthru_and_redirect (e, e->dest, NULL_RTX); | ||
| 366 | } | ||
| 367 | |||
| 368 | /* Redirect edge even at the expense of creating new jump insn or | ||
| 369 | @@ -1290,7 +1307,7 @@ rtl_redirect_edge_and_branch_force (edge | ||
| 370 | /* In case the edge redirection failed, try to force it to be non-fallthru | ||
| 371 | and redirect newly created simplejump. */ | ||
| 372 | df_set_bb_dirty (e->src); | ||
| 373 | - return force_nonfallthru_and_redirect (e, target); | ||
| 374 | + return force_nonfallthru_and_redirect (e, target, NULL_RTX); | ||
| 375 | } | ||
| 376 | |||
| 377 | /* The given edge should potentially be a fallthru edge. If that is in | ||
| 378 | Index: gcc-4_5-branch/gcc/common.opt | ||
| 379 | =================================================================== | ||
| 380 | --- gcc-4_5-branch.orig/gcc/common.opt | ||
| 381 | +++ gcc-4_5-branch/gcc/common.opt | ||
| 382 | @@ -1147,6 +1147,11 @@ fshow-column | ||
| 383 | Common C ObjC C++ ObjC++ Report Var(flag_show_column) Init(1) | ||
| 384 | Show column numbers in diagnostics, when available. Default on | ||
| 385 | |||
| 386 | +fshrink-wrap | ||
| 387 | +Common Report Var(flag_shrink_wrap) Optimization | ||
| 388 | +Emit function prologues only before parts of the function that need it, | ||
| 389 | +rather than at the top of the function. | ||
| 390 | + | ||
| 391 | fsignaling-nans | ||
| 392 | Common Report Var(flag_signaling_nans) Optimization | ||
| 393 | Disable optimizations observable by IEEE signaling NaNs | ||
| 394 | Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h | ||
| 395 | =================================================================== | ||
| 396 | --- gcc-4_5-branch.orig/gcc/config/arm/arm-protos.h | ||
| 397 | +++ gcc-4_5-branch/gcc/config/arm/arm-protos.h | ||
| 398 | @@ -26,6 +26,7 @@ | ||
| 399 | extern void arm_override_options (void); | ||
| 400 | extern void arm_optimization_options (int, int); | ||
| 401 | extern int use_return_insn (int, rtx); | ||
| 402 | +extern bool use_simple_return_p (void); | ||
| 403 | extern enum reg_class arm_regno_class (int); | ||
| 404 | extern void arm_load_pic_register (unsigned long); | ||
| 405 | extern int arm_volatile_func (void); | ||
| 406 | @@ -137,7 +138,7 @@ extern int arm_address_offset_is_imm (rt | ||
| 407 | extern const char *output_add_immediate (rtx *); | ||
| 408 | extern const char *arithmetic_instr (rtx, int); | ||
| 409 | extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int); | ||
| 410 | -extern const char *output_return_instruction (rtx, int, int); | ||
| 411 | +extern const char *output_return_instruction (rtx, bool, bool, bool); | ||
| 412 | extern void arm_poke_function_name (FILE *, const char *); | ||
| 413 | extern void arm_print_operand (FILE *, rtx, int); | ||
| 414 | extern void arm_print_operand_address (FILE *, rtx); | ||
| 415 | Index: gcc-4_5-branch/gcc/config/arm/arm.c | ||
| 416 | =================================================================== | ||
| 417 | --- gcc-4_5-branch.orig/gcc/config/arm/arm.c | ||
| 418 | +++ gcc-4_5-branch/gcc/config/arm/arm.c | ||
| 419 | @@ -2163,6 +2163,18 @@ arm_trampoline_adjust_address (rtx addr) | ||
| 420 | return addr; | ||
| 421 | } | ||
| 422 | |||
| 423 | +/* Return true if we should try to use a simple_return insn, i.e. perform | ||
| 424 | + shrink-wrapping if possible. This is the case if we need to emit a | ||
| 425 | + prologue, which we can test by looking at the offsets. */ | ||
| 426 | +bool | ||
| 427 | +use_simple_return_p (void) | ||
| 428 | +{ | ||
| 429 | + arm_stack_offsets *offsets; | ||
| 430 | + | ||
| 431 | + offsets = arm_get_frame_offsets (); | ||
| 432 | + return offsets->outgoing_args != 0; | ||
| 433 | +} | ||
| 434 | + | ||
| 435 | /* Return 1 if it is possible to return using a single instruction. | ||
| 436 | If SIBLING is non-null, this is a test for a return before a sibling | ||
| 437 | call. SIBLING is the call insn, so we can examine its register usage. */ | ||
| 438 | @@ -11284,6 +11296,7 @@ is_jump_table (rtx insn) | ||
| 439 | |||
| 440 | if (GET_CODE (insn) == JUMP_INSN | ||
| 441 | && JUMP_LABEL (insn) != NULL | ||
| 442 | + && !ANY_RETURN_P (JUMP_LABEL (insn)) | ||
| 443 | && ((table = next_real_insn (JUMP_LABEL (insn))) | ||
| 444 | == next_real_insn (insn)) | ||
| 445 | && table != NULL | ||
| 446 | @@ -14168,7 +14181,7 @@ arm_get_vfp_saved_size (void) | ||
| 447 | /* Generate a function exit sequence. If REALLY_RETURN is false, then do | ||
| 448 | everything bar the final return instruction. */ | ||
| 449 | const char * | ||
| 450 | -output_return_instruction (rtx operand, int really_return, int reverse) | ||
| 451 | +output_return_instruction (rtx operand, bool really_return, bool reverse, bool simple) | ||
| 452 | { | ||
| 453 | char conditional[10]; | ||
| 454 | char instr[100]; | ||
| 455 | @@ -14206,10 +14219,15 @@ output_return_instruction (rtx operand, | ||
| 456 | |||
| 457 | sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); | ||
| 458 | |||
| 459 | - cfun->machine->return_used_this_function = 1; | ||
| 460 | + if (simple) | ||
| 461 | + live_regs_mask = 0; | ||
| 462 | + else | ||
| 463 | + { | ||
| 464 | + cfun->machine->return_used_this_function = 1; | ||
| 465 | |||
| 466 | - offsets = arm_get_frame_offsets (); | ||
| 467 | - live_regs_mask = offsets->saved_regs_mask; | ||
| 468 | + offsets = arm_get_frame_offsets (); | ||
| 469 | + live_regs_mask = offsets->saved_regs_mask; | ||
| 470 | + } | ||
| 471 | |||
| 472 | if (live_regs_mask) | ||
| 473 | { | ||
| 474 | @@ -17108,6 +17126,7 @@ arm_final_prescan_insn (rtx insn) | ||
| 475 | |||
| 476 | /* If we start with a return insn, we only succeed if we find another one. */ | ||
| 477 | int seeking_return = 0; | ||
| 478 | + enum rtx_code return_code = UNKNOWN; | ||
| 479 | |||
| 480 | /* START_INSN will hold the insn from where we start looking. This is the | ||
| 481 | first insn after the following code_label if REVERSE is true. */ | ||
| 482 | @@ -17146,7 +17165,7 @@ arm_final_prescan_insn (rtx insn) | ||
| 483 | else | ||
| 484 | return; | ||
| 485 | } | ||
| 486 | - else if (GET_CODE (body) == RETURN) | ||
| 487 | + else if (ANY_RETURN_P (body)) | ||
| 488 | { | ||
| 489 | start_insn = next_nonnote_insn (start_insn); | ||
| 490 | if (GET_CODE (start_insn) == BARRIER) | ||
| 491 | @@ -17157,6 +17176,7 @@ arm_final_prescan_insn (rtx insn) | ||
| 492 | { | ||
| 493 | reverse = TRUE; | ||
| 494 | seeking_return = 1; | ||
| 495 | + return_code = GET_CODE (body); | ||
| 496 | } | ||
| 497 | else | ||
| 498 | return; | ||
| 499 | @@ -17197,11 +17217,15 @@ arm_final_prescan_insn (rtx insn) | ||
| 500 | label = XEXP (XEXP (SET_SRC (body), 2), 0); | ||
| 501 | then_not_else = FALSE; | ||
| 502 | } | ||
| 503 | - else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) | ||
| 504 | - seeking_return = 1; | ||
| 505 | - else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) | ||
| 506 | + else if (ANY_RETURN_P (XEXP (SET_SRC (body), 1))) | ||
| 507 | + { | ||
| 508 | + seeking_return = 1; | ||
| 509 | + return_code = GET_CODE (XEXP (SET_SRC (body), 1)); | ||
| 510 | + } | ||
| 511 | + else if (ANY_RETURN_P (XEXP (SET_SRC (body), 2))) | ||
| 512 | { | ||
| 513 | seeking_return = 1; | ||
| 514 | + return_code = GET_CODE (XEXP (SET_SRC (body), 2)); | ||
| 515 | then_not_else = FALSE; | ||
| 516 | } | ||
| 517 | else | ||
| 518 | @@ -17302,8 +17326,7 @@ arm_final_prescan_insn (rtx insn) | ||
| 519 | && !use_return_insn (TRUE, NULL) | ||
| 520 | && !optimize_size) | ||
| 521 | fail = TRUE; | ||
| 522 | - else if (GET_CODE (scanbody) == RETURN | ||
| 523 | - && seeking_return) | ||
| 524 | + else if (GET_CODE (scanbody) == return_code) | ||
| 525 | { | ||
| 526 | arm_ccfsm_state = 2; | ||
| 527 | succeed = TRUE; | ||
| 528 | Index: gcc-4_5-branch/gcc/config/arm/arm.h | ||
| 529 | =================================================================== | ||
| 530 | --- gcc-4_5-branch.orig/gcc/config/arm/arm.h | ||
| 531 | +++ gcc-4_5-branch/gcc/config/arm/arm.h | ||
| 532 | @@ -2622,6 +2622,8 @@ extern int making_const_table; | ||
| 533 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | ||
| 534 | arm_return_addr (COUNT, FRAME) | ||
| 535 | |||
| 536 | +#define RETURN_ADDR_REGNUM LR_REGNUM | ||
| 537 | + | ||
| 538 | /* Mask of the bits in the PC that contain the real return address | ||
| 539 | when running in 26-bit mode. */ | ||
| 540 | #define RETURN_ADDR_MASK26 (0x03fffffc) | ||
| 541 | Index: gcc-4_5-branch/gcc/config/arm/arm.md | ||
| 542 | =================================================================== | ||
| 543 | --- gcc-4_5-branch.orig/gcc/config/arm/arm.md | ||
| 544 | +++ gcc-4_5-branch/gcc/config/arm/arm.md | ||
| 545 | @@ -8882,66 +8882,72 @@ | ||
| 546 | [(set_attr "type" "call")] | ||
| 547 | ) | ||
| 548 | |||
| 549 | -(define_expand "return" | ||
| 550 | - [(return)] | ||
| 551 | - "TARGET_32BIT && USE_RETURN_INSN (FALSE)" | ||
| 552 | +;; Both kinds of return insn. | ||
| 553 | +(define_code_iterator returns [return simple_return]) | ||
| 554 | +(define_code_attr return_str [(return "") (simple_return "simple_")]) | ||
| 555 | +(define_code_attr return_simple_p [(return "false") (simple_return "true")]) | ||
| 556 | +(define_code_attr return_cond [(return " && USE_RETURN_INSN (FALSE)") | ||
| 557 | + (simple_return " && use_simple_return_p ()")]) | ||
| 558 | + | ||
| 559 | +(define_expand "<return_str>return" | ||
| 560 | + [(returns)] | ||
| 561 | + "TARGET_32BIT<return_cond>" | ||
| 562 | "") | ||
| 563 | |||
| 564 | -;; Often the return insn will be the same as loading from memory, so set attr | ||
| 565 | -(define_insn "*arm_return" | ||
| 566 | - [(return)] | ||
| 567 | - "TARGET_ARM && USE_RETURN_INSN (FALSE)" | ||
| 568 | - "* | ||
| 569 | - { | ||
| 570 | - if (arm_ccfsm_state == 2) | ||
| 571 | - { | ||
| 572 | - arm_ccfsm_state += 2; | ||
| 573 | - return \"\"; | ||
| 574 | - } | ||
| 575 | - return output_return_instruction (const_true_rtx, TRUE, FALSE); | ||
| 576 | - }" | ||
| 577 | +(define_insn "*arm_<return_str>return" | ||
| 578 | + [(returns)] | ||
| 579 | + "TARGET_ARM<return_cond>" | ||
| 580 | +{ | ||
| 581 | + if (arm_ccfsm_state == 2) | ||
| 582 | + { | ||
| 583 | + arm_ccfsm_state += 2; | ||
| 584 | + return ""; | ||
| 585 | + } | ||
| 586 | + return output_return_instruction (const_true_rtx, true, false, | ||
| 587 | + <return_simple_p>); | ||
| 588 | +} | ||
| 589 | [(set_attr "type" "load1") | ||
| 590 | (set_attr "length" "12") | ||
| 591 | (set_attr "predicable" "yes")] | ||
| 592 | ) | ||
| 593 | |||
| 594 | -(define_insn "*cond_return" | ||
| 595 | +(define_insn "*cond_<return_str>return" | ||
| 596 | [(set (pc) | ||
| 597 | (if_then_else (match_operator 0 "arm_comparison_operator" | ||
| 598 | [(match_operand 1 "cc_register" "") (const_int 0)]) | ||
| 599 | - (return) | ||
| 600 | + (returns) | ||
| 601 | (pc)))] | ||
| 602 | - "TARGET_ARM && USE_RETURN_INSN (TRUE)" | ||
| 603 | - "* | ||
| 604 | - { | ||
| 605 | - if (arm_ccfsm_state == 2) | ||
| 606 | - { | ||
| 607 | - arm_ccfsm_state += 2; | ||
| 608 | - return \"\"; | ||
| 609 | - } | ||
| 610 | - return output_return_instruction (operands[0], TRUE, FALSE); | ||
| 611 | - }" | ||
| 612 | + "TARGET_ARM<return_cond>" | ||
| 613 | +{ | ||
| 614 | + if (arm_ccfsm_state == 2) | ||
| 615 | + { | ||
| 616 | + arm_ccfsm_state += 2; | ||
| 617 | + return ""; | ||
| 618 | + } | ||
| 619 | + return output_return_instruction (operands[0], true, false, | ||
| 620 | + <return_simple_p>); | ||
| 621 | +} | ||
| 622 | [(set_attr "conds" "use") | ||
| 623 | (set_attr "length" "12") | ||
| 624 | (set_attr "type" "load1")] | ||
| 625 | ) | ||
| 626 | |||
| 627 | -(define_insn "*cond_return_inverted" | ||
| 628 | +(define_insn "*cond_<return_str>return_inverted" | ||
| 629 | [(set (pc) | ||
| 630 | (if_then_else (match_operator 0 "arm_comparison_operator" | ||
| 631 | [(match_operand 1 "cc_register" "") (const_int 0)]) | ||
| 632 | (pc) | ||
| 633 | - (return)))] | ||
| 634 | - "TARGET_ARM && USE_RETURN_INSN (TRUE)" | ||
| 635 | - "* | ||
| 636 | - { | ||
| 637 | - if (arm_ccfsm_state == 2) | ||
| 638 | - { | ||
| 639 | - arm_ccfsm_state += 2; | ||
| 640 | - return \"\"; | ||
| 641 | - } | ||
| 642 | - return output_return_instruction (operands[0], TRUE, TRUE); | ||
| 643 | - }" | ||
| 644 | + (returns)))] | ||
| 645 | + "TARGET_ARM<return_cond>" | ||
| 646 | +{ | ||
| 647 | + if (arm_ccfsm_state == 2) | ||
| 648 | + { | ||
| 649 | + arm_ccfsm_state += 2; | ||
| 650 | + return ""; | ||
| 651 | + } | ||
| 652 | + return output_return_instruction (operands[0], true, true, | ||
| 653 | + <return_simple_p>); | ||
| 654 | +} | ||
| 655 | [(set_attr "conds" "use") | ||
| 656 | (set_attr "length" "12") | ||
| 657 | (set_attr "type" "load1")] | ||
| 658 | @@ -10809,8 +10815,7 @@ | ||
| 659 | DONE; | ||
| 660 | } | ||
| 661 | emit_jump_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, | ||
| 662 | - gen_rtvec (1, | ||
| 663 | - gen_rtx_RETURN (VOIDmode)), | ||
| 664 | + gen_rtvec (1, ret_rtx), | ||
| 665 | VUNSPEC_EPILOGUE)); | ||
| 666 | DONE; | ||
| 667 | " | ||
| 668 | @@ -10827,7 +10832,7 @@ | ||
| 669 | "TARGET_32BIT" | ||
| 670 | "* | ||
| 671 | if (use_return_insn (FALSE, next_nonnote_insn (insn))) | ||
| 672 | - return output_return_instruction (const_true_rtx, FALSE, FALSE); | ||
| 673 | + return output_return_instruction (const_true_rtx, false, false, false); | ||
| 674 | return arm_output_epilogue (next_nonnote_insn (insn)); | ||
| 675 | " | ||
| 676 | ;; Length is absolute worst case | ||
| 677 | Index: gcc-4_5-branch/gcc/config/arm/thumb2.md | ||
| 678 | =================================================================== | ||
| 679 | --- gcc-4_5-branch.orig/gcc/config/arm/thumb2.md | ||
| 680 | +++ gcc-4_5-branch/gcc/config/arm/thumb2.md | ||
| 681 | @@ -1020,16 +1020,15 @@ | ||
| 682 | |||
| 683 | ;; Note: this is not predicable, to avoid issues with linker-generated | ||
| 684 | ;; interworking stubs. | ||
| 685 | -(define_insn "*thumb2_return" | ||
| 686 | - [(return)] | ||
| 687 | - "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)" | ||
| 688 | - "* | ||
| 689 | - { | ||
| 690 | - return output_return_instruction (const_true_rtx, TRUE, FALSE); | ||
| 691 | - }" | ||
| 692 | +(define_insn "*thumb2_<return_str>return" | ||
| 693 | + [(returns)] | ||
| 694 | + "TARGET_THUMB2<return_cond>" | ||
| 695 | +{ | ||
| 696 | + return output_return_instruction (const_true_rtx, true, false, | ||
| 697 | + <return_simple_p>); | ||
| 698 | +} | ||
| 699 | [(set_attr "type" "load1") | ||
| 700 | - (set_attr "length" "12")] | ||
| 701 | -) | ||
| 702 | + (set_attr "length" "12")]) | ||
| 703 | |||
| 704 | (define_insn_and_split "thumb2_eh_return" | ||
| 705 | [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")] | ||
| 706 | Index: gcc-4_5-branch/gcc/config/bfin/bfin.c | ||
| 707 | =================================================================== | ||
| 708 | --- gcc-4_5-branch.orig/gcc/config/bfin/bfin.c | ||
| 709 | +++ gcc-4_5-branch/gcc/config/bfin/bfin.c | ||
| 710 | @@ -2359,7 +2359,7 @@ bfin_expand_call (rtx retval, rtx fnaddr | ||
| 711 | XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, picreg); | ||
| 712 | XVECEXP (pat, 0, n++) = gen_rtx_USE (VOIDmode, cookie); | ||
| 713 | if (sibcall) | ||
| 714 | - XVECEXP (pat, 0, n++) = gen_rtx_RETURN (VOIDmode); | ||
| 715 | + XVECEXP (pat, 0, n++) = ret_rtx; | ||
| 716 | else | ||
| 717 | XVECEXP (pat, 0, n++) = gen_rtx_CLOBBER (VOIDmode, retsreg); | ||
| 718 | call = emit_call_insn (pat); | ||
| 719 | Index: gcc-4_5-branch/gcc/config/cris/cris.c | ||
| 720 | =================================================================== | ||
| 721 | --- gcc-4_5-branch.orig/gcc/config/cris/cris.c | ||
| 722 | +++ gcc-4_5-branch/gcc/config/cris/cris.c | ||
| 723 | @@ -1771,7 +1771,7 @@ cris_expand_return (bool on_stack) | ||
| 724 | we do that until they're fixed. Currently, all return insns in a | ||
| 725 | function must be the same (not really a limiting factor) so we need | ||
| 726 | to check that it doesn't change half-way through. */ | ||
| 727 | - emit_jump_insn (gen_rtx_RETURN (VOIDmode)); | ||
| 728 | + emit_jump_insn (ret_rtx); | ||
| 729 | |||
| 730 | CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack); | ||
| 731 | CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack); | ||
| 732 | Index: gcc-4_5-branch/gcc/config/h8300/h8300.c | ||
| 733 | =================================================================== | ||
| 734 | --- gcc-4_5-branch.orig/gcc/config/h8300/h8300.c | ||
| 735 | +++ gcc-4_5-branch/gcc/config/h8300/h8300.c | ||
| 736 | @@ -691,7 +691,7 @@ h8300_push_pop (int regno, int nregs, bo | ||
| 737 | /* Add the return instruction. */ | ||
| 738 | if (return_p) | ||
| 739 | { | ||
| 740 | - RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode); | ||
| 741 | + RTVEC_ELT (vec, i) = ret_rtx; | ||
| 742 | i++; | ||
| 743 | } | ||
| 744 | |||
| 745 | @@ -975,7 +975,7 @@ h8300_expand_epilogue (void) | ||
| 746 | } | ||
| 747 | |||
| 748 | if (!returned_p) | ||
| 749 | - emit_jump_insn (gen_rtx_RETURN (VOIDmode)); | ||
| 750 | + emit_jump_insn (ret_rtx); | ||
| 751 | } | ||
| 752 | |||
| 753 | /* Return nonzero if the current function is an interrupt | ||
| 754 | Index: gcc-4_5-branch/gcc/config/i386/i386.c | ||
| 755 | =================================================================== | ||
| 756 | --- gcc-4_5-branch.orig/gcc/config/i386/i386.c | ||
| 757 | +++ gcc-4_5-branch/gcc/config/i386/i386.c | ||
| 758 | @@ -9308,13 +9308,13 @@ ix86_expand_epilogue (int style) | ||
| 759 | |||
| 760 | pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx, | ||
| 761 | popc, -1, true); | ||
| 762 | - emit_jump_insn (gen_return_indirect_internal (ecx)); | ||
| 763 | + emit_jump_insn (gen_simple_return_indirect_internal (ecx)); | ||
| 764 | } | ||
| 765 | else | ||
| 766 | - emit_jump_insn (gen_return_pop_internal (popc)); | ||
| 767 | + emit_jump_insn (gen_simple_return_pop_internal (popc)); | ||
| 768 | } | ||
| 769 | else | ||
| 770 | - emit_jump_insn (gen_return_internal ()); | ||
| 771 | + emit_jump_insn (gen_simple_return_internal ()); | ||
| 772 | |||
| 773 | /* Restore the state back to the state from the prologue, | ||
| 774 | so that it's correct for the next epilogue. */ | ||
| 775 | @@ -26615,7 +26615,7 @@ ix86_pad_returns (void) | ||
| 776 | rtx prev; | ||
| 777 | bool replace = false; | ||
| 778 | |||
| 779 | - if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN | ||
| 780 | + if (!JUMP_P (ret) || !ANY_RETURN_P (PATTERN (ret)) | ||
| 781 | || optimize_bb_for_size_p (bb)) | ||
| 782 | continue; | ||
| 783 | for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev)) | ||
| 784 | @@ -26645,7 +26645,10 @@ ix86_pad_returns (void) | ||
| 785 | } | ||
| 786 | if (replace) | ||
| 787 | { | ||
| 788 | - emit_jump_insn_before (gen_return_internal_long (), ret); | ||
| 789 | + if (PATTERN (ret) == ret_rtx) | ||
| 790 | + emit_jump_insn_before (gen_return_internal_long (), ret); | ||
| 791 | + else | ||
| 792 | + emit_jump_insn_before (gen_simple_return_internal_long (), ret); | ||
| 793 | delete_insn (ret); | ||
| 794 | } | ||
| 795 | } | ||
| 796 | Index: gcc-4_5-branch/gcc/config/i386/i386.md | ||
| 797 | =================================================================== | ||
| 798 | --- gcc-4_5-branch.orig/gcc/config/i386/i386.md | ||
| 799 | +++ gcc-4_5-branch/gcc/config/i386/i386.md | ||
| 800 | @@ -13798,24 +13798,29 @@ | ||
| 801 | "" | ||
| 802 | [(set_attr "length" "0")]) | ||
| 803 | |||
| 804 | +(define_code_iterator returns [return simple_return]) | ||
| 805 | +(define_code_attr return_str [(return "") (simple_return "simple_")]) | ||
| 806 | +(define_code_attr return_cond [(return "ix86_can_use_return_insn_p ()") | ||
| 807 | + (simple_return "")]) | ||
| 808 | + | ||
| 809 | ;; Insn emitted into the body of a function to return from a function. | ||
| 810 | ;; This is only done if the function's epilogue is known to be simple. | ||
| 811 | ;; See comments for ix86_can_use_return_insn_p in i386.c. | ||
| 812 | |||
| 813 | -(define_expand "return" | ||
| 814 | - [(return)] | ||
| 815 | - "ix86_can_use_return_insn_p ()" | ||
| 816 | +(define_expand "<return_str>return" | ||
| 817 | + [(returns)] | ||
| 818 | + "<return_cond>" | ||
| 819 | { | ||
| 820 | if (crtl->args.pops_args) | ||
| 821 | { | ||
| 822 | rtx popc = GEN_INT (crtl->args.pops_args); | ||
| 823 | - emit_jump_insn (gen_return_pop_internal (popc)); | ||
| 824 | + emit_jump_insn (gen_<return_str>return_pop_internal (popc)); | ||
| 825 | DONE; | ||
| 826 | } | ||
| 827 | }) | ||
| 828 | |||
| 829 | -(define_insn "return_internal" | ||
| 830 | - [(return)] | ||
| 831 | +(define_insn "<return_str>return_internal" | ||
| 832 | + [(returns)] | ||
| 833 | "reload_completed" | ||
| 834 | "ret" | ||
| 835 | [(set_attr "length" "1") | ||
| 836 | @@ -13826,8 +13831,8 @@ | ||
| 837 | ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET | ||
| 838 | ;; instruction Athlon and K8 have. | ||
| 839 | |||
| 840 | -(define_insn "return_internal_long" | ||
| 841 | - [(return) | ||
| 842 | +(define_insn "<return_str>return_internal_long" | ||
| 843 | + [(returns) | ||
| 844 | (unspec [(const_int 0)] UNSPEC_REP)] | ||
| 845 | "reload_completed" | ||
| 846 | "rep\;ret" | ||
| 847 | @@ -13837,8 +13842,8 @@ | ||
| 848 | (set_attr "prefix_rep" "1") | ||
| 849 | (set_attr "modrm" "0")]) | ||
| 850 | |||
| 851 | -(define_insn "return_pop_internal" | ||
| 852 | - [(return) | ||
| 853 | +(define_insn "<return_str>return_pop_internal" | ||
| 854 | + [(returns) | ||
| 855 | (use (match_operand:SI 0 "const_int_operand" ""))] | ||
| 856 | "reload_completed" | ||
| 857 | "ret\t%0" | ||
| 858 | @@ -13847,8 +13852,8 @@ | ||
| 859 | (set_attr "length_immediate" "2") | ||
| 860 | (set_attr "modrm" "0")]) | ||
| 861 | |||
| 862 | -(define_insn "return_indirect_internal" | ||
| 863 | - [(return) | ||
| 864 | +(define_insn "<return_str>return_indirect_internal" | ||
| 865 | + [(returns) | ||
| 866 | (use (match_operand:SI 0 "register_operand" "r"))] | ||
| 867 | "reload_completed" | ||
| 868 | "jmp\t%A0" | ||
| 869 | Index: gcc-4_5-branch/gcc/config/m68hc11/m68hc11.md | ||
| 870 | =================================================================== | ||
| 871 | --- gcc-4_5-branch.orig/gcc/config/m68hc11/m68hc11.md | ||
| 872 | +++ gcc-4_5-branch/gcc/config/m68hc11/m68hc11.md | ||
| 873 | @@ -6576,7 +6576,7 @@ | ||
| 874 | if (ret_size && ret_size <= 2) | ||
| 875 | { | ||
| 876 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, | ||
| 877 | - gen_rtvec (2, gen_rtx_RETURN (VOIDmode), | ||
| 878 | + gen_rtvec (2, ret_rtx, | ||
| 879 | gen_rtx_USE (VOIDmode, | ||
| 880 | gen_rtx_REG (HImode, 1))))); | ||
| 881 | DONE; | ||
| 882 | @@ -6584,7 +6584,7 @@ | ||
| 883 | if (ret_size) | ||
| 884 | { | ||
| 885 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, | ||
| 886 | - gen_rtvec (2, gen_rtx_RETURN (VOIDmode), | ||
| 887 | + gen_rtvec (2, ret_rtx, | ||
| 888 | gen_rtx_USE (VOIDmode, | ||
| 889 | gen_rtx_REG (SImode, 0))))); | ||
| 890 | DONE; | ||
| 891 | Index: gcc-4_5-branch/gcc/config/m68k/m68k.c | ||
| 892 | =================================================================== | ||
| 893 | --- gcc-4_5-branch.orig/gcc/config/m68k/m68k.c | ||
| 894 | +++ gcc-4_5-branch/gcc/config/m68k/m68k.c | ||
| 895 | @@ -1366,7 +1366,7 @@ m68k_expand_epilogue (bool sibcall_p) | ||
| 896 | EH_RETURN_STACKADJ_RTX)); | ||
| 897 | |||
| 898 | if (!sibcall_p) | ||
| 899 | - emit_jump_insn (gen_rtx_RETURN (VOIDmode)); | ||
| 900 | + emit_jump_insn (ret_rtx); | ||
| 901 | } | ||
| 902 | |||
| 903 | /* Return true if X is a valid comparison operator for the dbcc | ||
| 904 | Index: gcc-4_5-branch/gcc/config/mips/mips.c | ||
| 905 | =================================================================== | ||
| 906 | --- gcc-4_5-branch.orig/gcc/config/mips/mips.c | ||
| 907 | +++ gcc-4_5-branch/gcc/config/mips/mips.c | ||
| 908 | @@ -10497,7 +10497,8 @@ mips_expand_epilogue (bool sibcall_p) | ||
| 909 | regno = GP_REG_FIRST + 7; | ||
| 910 | else | ||
| 911 | regno = RETURN_ADDR_REGNUM; | ||
| 912 | - emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno))); | ||
| 913 | + emit_jump_insn (gen_simple_return_internal (gen_rtx_REG (Pmode, | ||
| 914 | + regno))); | ||
| 915 | } | ||
| 916 | } | ||
| 917 | |||
| 918 | Index: gcc-4_5-branch/gcc/config/mips/mips.md | ||
| 919 | =================================================================== | ||
| 920 | --- gcc-4_5-branch.orig/gcc/config/mips/mips.md | ||
| 921 | +++ gcc-4_5-branch/gcc/config/mips/mips.md | ||
| 922 | @@ -5815,6 +5815,18 @@ | ||
| 923 | [(set_attr "type" "jump") | ||
| 924 | (set_attr "mode" "none")]) | ||
| 925 | |||
| 926 | +(define_expand "simple_return" | ||
| 927 | + [(simple_return)] | ||
| 928 | + "!mips_can_use_return_insn ()" | ||
| 929 | + { mips_expand_before_return (); }) | ||
| 930 | + | ||
| 931 | +(define_insn "*simple_return" | ||
| 932 | + [(simple_return)] | ||
| 933 | + "!mips_can_use_return_insn ()" | ||
| 934 | + "%*j\t$31%/" | ||
| 935 | + [(set_attr "type" "jump") | ||
| 936 | + (set_attr "mode" "none")]) | ||
| 937 | + | ||
| 938 | ;; Normal return. | ||
| 939 | |||
| 940 | (define_insn "return_internal" | ||
| 941 | @@ -5825,6 +5837,14 @@ | ||
| 942 | [(set_attr "type" "jump") | ||
| 943 | (set_attr "mode" "none")]) | ||
| 944 | |||
| 945 | +(define_insn "simple_return_internal" | ||
| 946 | + [(simple_return) | ||
| 947 | + (use (match_operand 0 "pmode_register_operand" ""))] | ||
| 948 | + "" | ||
| 949 | + "%*j\t%0%/" | ||
| 950 | + [(set_attr "type" "jump") | ||
| 951 | + (set_attr "mode" "none")]) | ||
| 952 | + | ||
| 953 | ;; Exception return. | ||
| 954 | (define_insn "mips_eret" | ||
| 955 | [(return) | ||
| 956 | Index: gcc-4_5-branch/gcc/config/picochip/picochip.c | ||
| 957 | =================================================================== | ||
| 958 | --- gcc-4_5-branch.orig/gcc/config/picochip/picochip.c | ||
| 959 | +++ gcc-4_5-branch/gcc/config/picochip/picochip.c | ||
| 960 | @@ -1996,7 +1996,7 @@ picochip_expand_epilogue (int is_sibling | ||
| 961 | rtvec p; | ||
| 962 | p = rtvec_alloc (2); | ||
| 963 | |||
| 964 | - RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); | ||
| 965 | + RTVEC_ELT (p, 0) = ret_rtx; | ||
| 966 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | ||
| 967 | gen_rtx_REG (Pmode, LINK_REGNUM)); | ||
| 968 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | ||
| 969 | Index: gcc-4_5-branch/gcc/config/rs6000/rs6000.c | ||
| 970 | =================================================================== | ||
| 971 | --- gcc-4_5-branch.orig/gcc/config/rs6000/rs6000.c | ||
| 972 | +++ gcc-4_5-branch/gcc/config/rs6000/rs6000.c | ||
| 973 | @@ -18563,7 +18563,7 @@ rs6000_make_savres_rtx (rs6000_stack_t * | ||
| 974 | p = rtvec_alloc ((lr ? 4 : 3) + n_regs); | ||
| 975 | |||
| 976 | if (!savep && lr) | ||
| 977 | - RTVEC_ELT (p, offset++) = gen_rtx_RETURN (VOIDmode); | ||
| 978 | + RTVEC_ELT (p, offset++) = ret_rtx; | ||
| 979 | |||
| 980 | RTVEC_ELT (p, offset++) | ||
| 981 | = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 65)); | ||
| 982 | @@ -19638,7 +19638,7 @@ rs6000_emit_epilogue (int sibcall) | ||
| 983 | alloc_rname = ggc_strdup (rname); | ||
| 984 | |||
| 985 | j = 0; | ||
| 986 | - RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode); | ||
| 987 | + RTVEC_ELT (p, j++) = ret_rtx; | ||
| 988 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, | ||
| 989 | gen_rtx_REG (Pmode, | ||
| 990 | LR_REGNO)); | ||
| 991 | @@ -20254,7 +20254,7 @@ rs6000_emit_epilogue (int sibcall) | ||
| 992 | else | ||
| 993 | p = rtvec_alloc (2); | ||
| 994 | |||
| 995 | - RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); | ||
| 996 | + RTVEC_ELT (p, 0) = ret_rtx; | ||
| 997 | RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr) | ||
| 998 | ? gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 65)) | ||
| 999 | : gen_rtx_CLOBBER (VOIDmode, | ||
| 1000 | @@ -20695,7 +20695,7 @@ rs6000_output_mi_thunk (FILE *file, tree | ||
| 1001 | gen_rtx_USE (VOIDmode, | ||
| 1002 | gen_rtx_REG (SImode, | ||
| 1003 | LR_REGNO)), | ||
| 1004 | - gen_rtx_RETURN (VOIDmode)))); | ||
| 1005 | + ret_rtx))); | ||
| 1006 | SIBLING_CALL_P (insn) = 1; | ||
| 1007 | emit_barrier (); | ||
| 1008 | |||
| 1009 | Index: gcc-4_5-branch/gcc/config/rx/rx.c | ||
| 1010 | =================================================================== | ||
| 1011 | --- gcc-4_5-branch.orig/gcc/config/rx/rx.c | ||
| 1012 | +++ gcc-4_5-branch/gcc/config/rx/rx.c | ||
| 1013 | @@ -1562,7 +1562,7 @@ gen_rx_rtsd_vector (unsigned int adjust, | ||
| 1014 | : plus_constant (stack_pointer_rtx, | ||
| 1015 | i * UNITS_PER_WORD))); | ||
| 1016 | |||
| 1017 | - XVECEXP (vector, 0, count - 1) = gen_rtx_RETURN (VOIDmode); | ||
| 1018 | + XVECEXP (vector, 0, count - 1) = ret_rtx; | ||
| 1019 | |||
| 1020 | return vector; | ||
| 1021 | } | ||
| 1022 | Index: gcc-4_5-branch/gcc/config/s390/s390.c | ||
| 1023 | =================================================================== | ||
| 1024 | --- gcc-4_5-branch.orig/gcc/config/s390/s390.c | ||
| 1025 | +++ gcc-4_5-branch/gcc/config/s390/s390.c | ||
| 1026 | @@ -8170,7 +8170,7 @@ s390_emit_epilogue (bool sibcall) | ||
| 1027 | |||
| 1028 | p = rtvec_alloc (2); | ||
| 1029 | |||
| 1030 | - RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); | ||
| 1031 | + RTVEC_ELT (p, 0) = ret_rtx; | ||
| 1032 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg); | ||
| 1033 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | ||
| 1034 | } | ||
| 1035 | Index: gcc-4_5-branch/gcc/config/sh/sh.c | ||
| 1036 | =================================================================== | ||
| 1037 | --- gcc-4_5-branch.orig/gcc/config/sh/sh.c | ||
| 1038 | +++ gcc-4_5-branch/gcc/config/sh/sh.c | ||
| 1039 | @@ -5252,7 +5252,8 @@ barrier_align (rtx barrier_or_label) | ||
| 1040 | } | ||
| 1041 | if (prev | ||
| 1042 | && JUMP_P (prev) | ||
| 1043 | - && JUMP_LABEL (prev)) | ||
| 1044 | + && JUMP_LABEL (prev) | ||
| 1045 | + && !ANY_RETURN_P (JUMP_LABEL (prev))) | ||
| 1046 | { | ||
| 1047 | rtx x; | ||
| 1048 | if (jump_to_next | ||
| 1049 | @@ -5951,7 +5952,7 @@ split_branches (rtx first) | ||
| 1050 | JUMP_LABEL (insn) = far_label; | ||
| 1051 | LABEL_NUSES (far_label)++; | ||
| 1052 | } | ||
| 1053 | - redirect_jump (insn, NULL_RTX, 1); | ||
| 1054 | + redirect_jump (insn, ret_rtx, 1); | ||
| 1055 | far_label = 0; | ||
| 1056 | } | ||
| 1057 | } | ||
| 1058 | Index: gcc-4_5-branch/gcc/config/v850/v850.c | ||
| 1059 | =================================================================== | ||
| 1060 | --- gcc-4_5-branch.orig/gcc/config/v850/v850.c | ||
| 1061 | +++ gcc-4_5-branch/gcc/config/v850/v850.c | ||
| 1062 | @@ -1832,7 +1832,7 @@ expand_epilogue (void) | ||
| 1063 | { | ||
| 1064 | restore_all = gen_rtx_PARALLEL (VOIDmode, | ||
| 1065 | rtvec_alloc (num_restore + 2)); | ||
| 1066 | - XVECEXP (restore_all, 0, 0) = gen_rtx_RETURN (VOIDmode); | ||
| 1067 | + XVECEXP (restore_all, 0, 0) = ret_rtx; | ||
| 1068 | XVECEXP (restore_all, 0, 1) | ||
| 1069 | = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | ||
| 1070 | gen_rtx_PLUS (Pmode, | ||
| 1071 | Index: gcc-4_5-branch/gcc/df-scan.c | ||
| 1072 | =================================================================== | ||
| 1073 | --- gcc-4_5-branch.orig/gcc/df-scan.c | ||
| 1074 | +++ gcc-4_5-branch/gcc/df-scan.c | ||
| 1075 | @@ -3296,6 +3296,7 @@ df_uses_record (enum df_ref_class cl, st | ||
| 1076 | } | ||
| 1077 | |||
| 1078 | case RETURN: | ||
| 1079 | + case SIMPLE_RETURN: | ||
| 1080 | break; | ||
| 1081 | |||
| 1082 | case ASM_OPERANDS: | ||
| 1083 | Index: gcc-4_5-branch/gcc/doc/invoke.texi | ||
| 1084 | =================================================================== | ||
| 1085 | --- gcc-4_5-branch.orig/gcc/doc/invoke.texi | ||
| 1086 | +++ gcc-4_5-branch/gcc/doc/invoke.texi | ||
| 1087 | @@ -5751,6 +5751,7 @@ compilation time. | ||
| 1088 | -fipa-pure-const @gol | ||
| 1089 | -fipa-reference @gol | ||
| 1090 | -fmerge-constants | ||
| 1091 | +-fshrink-wrap @gol | ||
| 1092 | -fsplit-wide-types @gol | ||
| 1093 | -ftree-builtin-call-dce @gol | ||
| 1094 | -ftree-ccp @gol | ||
| 1095 | @@ -6506,6 +6507,12 @@ This option has no effect until one of @ | ||
| 1096 | When pipelining loops during selective scheduling, also pipeline outer loops. | ||
| 1097 | This option has no effect until @option{-fsel-sched-pipelining} is turned on. | ||
| 1098 | |||
| 1099 | +@item -fshrink-wrap | ||
| 1100 | +@opindex fshrink-wrap | ||
| 1101 | +Emit function prologues only before parts of the function that need it, | ||
| 1102 | +rather than at the top of the function. This flag is enabled by default at | ||
| 1103 | +@option{-O} and higher. | ||
| 1104 | + | ||
| 1105 | @item -fcaller-saves | ||
| 1106 | @opindex fcaller-saves | ||
| 1107 | Enable values to be allocated in registers that will be clobbered by | ||
| 1108 | Index: gcc-4_5-branch/gcc/doc/md.texi | ||
| 1109 | =================================================================== | ||
| 1110 | --- gcc-4_5-branch.orig/gcc/doc/md.texi | ||
| 1111 | +++ gcc-4_5-branch/gcc/doc/md.texi | ||
| 1112 | @@ -4801,7 +4801,19 @@ RTL generation phase. In this case it i | ||
| 1113 | multiple instructions are usually needed to return from a function, but | ||
| 1114 | some class of functions only requires one instruction to implement a | ||
| 1115 | return. Normally, the applicable functions are those which do not need | ||
| 1116 | -to save any registers or allocate stack space. | ||
| 1117 | +to save any registers or allocate stack space, although some targets | ||
| 1118 | +have instructions that can perform both the epilogue and function return | ||
| 1119 | +in one instruction. | ||
| 1120 | + | ||
| 1121 | +@cindex @code{simple_return} instruction pattern | ||
| 1122 | +@item @samp{simple_return} | ||
| 1123 | +Subroutine return instruction. This instruction pattern name should be | ||
| 1124 | +defined only if a single instruction can do all the work of returning | ||
| 1125 | +from a function on a path where no epilogue is required. This pattern | ||
| 1126 | +is very similar to the @code{return} instruction pattern, but it is emitted | ||
| 1127 | +only by the shrink-wrapping optimization on paths where the function | ||
| 1128 | +prologue has not been executed, and a function return should occur without | ||
| 1129 | +any of the effects of the epilogue. | ||
| 1130 | |||
| 1131 | @findex reload_completed | ||
| 1132 | @findex leaf_function_p | ||
| 1133 | Index: gcc-4_5-branch/gcc/doc/rtl.texi | ||
| 1134 | =================================================================== | ||
| 1135 | --- gcc-4_5-branch.orig/gcc/doc/rtl.texi | ||
| 1136 | +++ gcc-4_5-branch/gcc/doc/rtl.texi | ||
| 1137 | @@ -2888,6 +2888,13 @@ placed in @code{pc} to return to the cal | ||
| 1138 | Note that an insn pattern of @code{(return)} is logically equivalent to | ||
| 1139 | @code{(set (pc) (return))}, but the latter form is never used. | ||
| 1140 | |||
| 1141 | +@findex simple_return | ||
| 1142 | +@item (simple_return) | ||
| 1143 | +Like @code{(return)}, but truly represents only a function return, while | ||
| 1144 | +@code{(return)} may represent an insn that also performs other functions | ||
| 1145 | +of the function epilogue. Like @code{(return)}, this may also occur in | ||
| 1146 | +conditional jumps. | ||
| 1147 | + | ||
| 1148 | @findex call | ||
| 1149 | @item (call @var{function} @var{nargs}) | ||
| 1150 | Represents a function call. @var{function} is a @code{mem} expression | ||
| 1151 | @@ -3017,7 +3024,7 @@ Represents several side effects performe | ||
| 1152 | brackets stand for a vector; the operand of @code{parallel} is a | ||
| 1153 | vector of expressions. @var{x0}, @var{x1} and so on are individual | ||
| 1154 | side effect expressions---expressions of code @code{set}, @code{call}, | ||
| 1155 | -@code{return}, @code{clobber} or @code{use}. | ||
| 1156 | +@code{return}, @code{simple_return}, @code{clobber} or @code{use}. | ||
| 1157 | |||
| 1158 | ``In parallel'' means that first all the values used in the individual | ||
| 1159 | side-effects are computed, and second all the actual side-effects are | ||
| 1160 | @@ -3656,14 +3663,16 @@ and @code{call_insn} insns: | ||
| 1161 | @table @code | ||
| 1162 | @findex PATTERN | ||
| 1163 | @item PATTERN (@var{i}) | ||
| 1164 | -An expression for the side effect performed by this insn. This must be | ||
| 1165 | -one of the following codes: @code{set}, @code{call}, @code{use}, | ||
| 1166 | -@code{clobber}, @code{return}, @code{asm_input}, @code{asm_output}, | ||
| 1167 | -@code{addr_vec}, @code{addr_diff_vec}, @code{trap_if}, @code{unspec}, | ||
| 1168 | -@code{unspec_volatile}, @code{parallel}, @code{cond_exec}, or @code{sequence}. If it is a @code{parallel}, | ||
| 1169 | -each element of the @code{parallel} must be one these codes, except that | ||
| 1170 | -@code{parallel} expressions cannot be nested and @code{addr_vec} and | ||
| 1171 | -@code{addr_diff_vec} are not permitted inside a @code{parallel} expression. | ||
| 1172 | +An expression for the side effect performed by this insn. This must | ||
| 1173 | +be one of the following codes: @code{set}, @code{call}, @code{use}, | ||
| 1174 | +@code{clobber}, @code{return}, @code{simple_return}, @code{asm_input}, | ||
| 1175 | +@code{asm_output}, @code{addr_vec}, @code{addr_diff_vec}, | ||
| 1176 | +@code{trap_if}, @code{unspec}, @code{unspec_volatile}, | ||
| 1177 | +@code{parallel}, @code{cond_exec}, or @code{sequence}. If it is a | ||
| 1178 | +@code{parallel}, each element of the @code{parallel} must be one these | ||
| 1179 | +codes, except that @code{parallel} expressions cannot be nested and | ||
| 1180 | +@code{addr_vec} and @code{addr_diff_vec} are not permitted inside a | ||
| 1181 | +@code{parallel} expression. | ||
| 1182 | |||
| 1183 | @findex INSN_CODE | ||
| 1184 | @item INSN_CODE (@var{i}) | ||
| 1185 | Index: gcc-4_5-branch/gcc/doc/tm.texi | ||
| 1186 | =================================================================== | ||
| 1187 | --- gcc-4_5-branch.orig/gcc/doc/tm.texi | ||
| 1188 | +++ gcc-4_5-branch/gcc/doc/tm.texi | ||
| 1189 | @@ -3287,6 +3287,12 @@ Define this if the return address of a p | ||
| 1190 | from the frame pointer of the previous stack frame. | ||
| 1191 | @end defmac | ||
| 1192 | |||
| 1193 | +@defmac RETURN_ADDR_REGNUM | ||
| 1194 | +If defined, a C expression whose value is the register number of the return | ||
| 1195 | +address for the current function. Targets that pass the return address on | ||
| 1196 | +the stack should not define this macro. | ||
| 1197 | +@end defmac | ||
| 1198 | + | ||
| 1199 | @defmac INCOMING_RETURN_ADDR_RTX | ||
| 1200 | A C expression whose value is RTL representing the location of the | ||
| 1201 | incoming return address at the beginning of any function, before the | ||
| 1202 | Index: gcc-4_5-branch/gcc/dwarf2out.c | ||
| 1203 | =================================================================== | ||
| 1204 | --- gcc-4_5-branch.orig/gcc/dwarf2out.c | ||
| 1205 | +++ gcc-4_5-branch/gcc/dwarf2out.c | ||
| 1206 | @@ -1396,7 +1396,7 @@ compute_barrier_args_size_1 (rtx insn, H | ||
| 1207 | { | ||
| 1208 | rtx dest = JUMP_LABEL (insn); | ||
| 1209 | |||
| 1210 | - if (dest) | ||
| 1211 | + if (dest && !ANY_RETURN_P (dest)) | ||
| 1212 | { | ||
| 1213 | if (barrier_args_size [INSN_UID (dest)] < 0) | ||
| 1214 | { | ||
| 1215 | Index: gcc-4_5-branch/gcc/emit-rtl.c | ||
| 1216 | =================================================================== | ||
| 1217 | --- gcc-4_5-branch.orig/gcc/emit-rtl.c | ||
| 1218 | +++ gcc-4_5-branch/gcc/emit-rtl.c | ||
| 1219 | @@ -2432,6 +2432,8 @@ verify_rtx_sharing (rtx orig, rtx insn) | ||
| 1220 | case CODE_LABEL: | ||
| 1221 | case PC: | ||
| 1222 | case CC0: | ||
| 1223 | + case RETURN: | ||
| 1224 | + case SIMPLE_RETURN: | ||
| 1225 | case SCRATCH: | ||
| 1226 | return; | ||
| 1227 | /* SCRATCH must be shared because they represent distinct values. */ | ||
| 1228 | @@ -3323,14 +3325,17 @@ prev_label (rtx insn) | ||
| 1229 | return insn; | ||
| 1230 | } | ||
| 1231 | |||
| 1232 | -/* Return the last label to mark the same position as LABEL. Return null | ||
| 1233 | - if LABEL itself is null. */ | ||
| 1234 | +/* Return the last label to mark the same position as LABEL. Return LABEL | ||
| 1235 | + itself if it is null or any return rtx. */ | ||
| 1236 | |||
| 1237 | rtx | ||
| 1238 | skip_consecutive_labels (rtx label) | ||
| 1239 | { | ||
| 1240 | rtx insn; | ||
| 1241 | |||
| 1242 | + if (label && ANY_RETURN_P (label)) | ||
| 1243 | + return label; | ||
| 1244 | + | ||
| 1245 | for (insn = label; insn != 0 && !INSN_P (insn); insn = NEXT_INSN (insn)) | ||
| 1246 | if (LABEL_P (insn)) | ||
| 1247 | label = insn; | ||
| 1248 | @@ -5209,7 +5214,7 @@ classify_insn (rtx x) | ||
| 1249 | return CODE_LABEL; | ||
| 1250 | if (GET_CODE (x) == CALL) | ||
| 1251 | return CALL_INSN; | ||
| 1252 | - if (GET_CODE (x) == RETURN) | ||
| 1253 | + if (GET_CODE (x) == RETURN || GET_CODE (x) == SIMPLE_RETURN) | ||
| 1254 | return JUMP_INSN; | ||
| 1255 | if (GET_CODE (x) == SET) | ||
| 1256 | { | ||
| 1257 | @@ -5715,8 +5720,10 @@ init_emit_regs (void) | ||
| 1258 | init_reg_modes_target (); | ||
| 1259 | |||
| 1260 | /* Assign register numbers to the globally defined register rtx. */ | ||
| 1261 | - pc_rtx = gen_rtx_PC (VOIDmode); | ||
| 1262 | - cc0_rtx = gen_rtx_CC0 (VOIDmode); | ||
| 1263 | + pc_rtx = gen_rtx_fmt_ (PC, VOIDmode); | ||
| 1264 | + ret_rtx = gen_rtx_fmt_ (RETURN, VOIDmode); | ||
| 1265 | + simple_return_rtx = gen_rtx_fmt_ (SIMPLE_RETURN, VOIDmode); | ||
| 1266 | + cc0_rtx = gen_rtx_fmt_ (CC0, VOIDmode); | ||
| 1267 | stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM); | ||
| 1268 | frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM); | ||
| 1269 | hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM); | ||
| 1270 | Index: gcc-4_5-branch/gcc/final.c | ||
| 1271 | =================================================================== | ||
| 1272 | --- gcc-4_5-branch.orig/gcc/final.c | ||
| 1273 | +++ gcc-4_5-branch/gcc/final.c | ||
| 1274 | @@ -2428,7 +2428,7 @@ final_scan_insn (rtx insn, FILE *file, i | ||
| 1275 | delete_insn (insn); | ||
| 1276 | break; | ||
| 1277 | } | ||
| 1278 | - else if (GET_CODE (SET_SRC (body)) == RETURN) | ||
| 1279 | + else if (ANY_RETURN_P (SET_SRC (body))) | ||
| 1280 | /* Replace (set (pc) (return)) with (return). */ | ||
| 1281 | PATTERN (insn) = body = SET_SRC (body); | ||
| 1282 | |||
| 1283 | Index: gcc-4_5-branch/gcc/function.c | ||
| 1284 | =================================================================== | ||
| 1285 | --- gcc-4_5-branch.orig/gcc/function.c | ||
| 1286 | +++ gcc-4_5-branch/gcc/function.c | ||
| 1287 | @@ -147,9 +147,6 @@ extern tree debug_find_var_in_block_tree | ||
| 1288 | can always export `prologue_epilogue_contains'. */ | ||
| 1289 | static void record_insns (rtx, rtx, htab_t *) ATTRIBUTE_UNUSED; | ||
| 1290 | static bool contains (const_rtx, htab_t); | ||
| 1291 | -#ifdef HAVE_return | ||
| 1292 | -static void emit_return_into_block (basic_block); | ||
| 1293 | -#endif | ||
| 1294 | static void prepare_function_start (void); | ||
| 1295 | static void do_clobber_return_reg (rtx, void *); | ||
| 1296 | static void do_use_return_reg (rtx, void *); | ||
| 1297 | @@ -4987,35 +4984,190 @@ prologue_epilogue_contains (const_rtx in | ||
| 1298 | return 0; | ||
| 1299 | } | ||
| 1300 | |||
| 1301 | +#ifdef HAVE_simple_return | ||
| 1302 | +/* This collects sets and clobbers of hard registers in a HARD_REG_SET, | ||
| 1303 | + which is pointed to by DATA. */ | ||
| 1304 | +static void | ||
| 1305 | +record_hard_reg_sets (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) | ||
| 1306 | +{ | ||
| 1307 | + HARD_REG_SET *pset = (HARD_REG_SET *)data; | ||
| 1308 | + if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) | ||
| 1309 | + { | ||
| 1310 | + int nregs = hard_regno_nregs[REGNO (x)][GET_MODE (x)]; | ||
| 1311 | + while (nregs-- > 0) | ||
| 1312 | + SET_HARD_REG_BIT (*pset, REGNO (x) + nregs); | ||
| 1313 | + } | ||
| 1314 | +} | ||
| 1315 | + | ||
| 1316 | +/* A subroutine of requires_stack_frame_p, called via for_each_rtx. | ||
| 1317 | + If any change is made, set CHANGED | ||
| 1318 | + to true. */ | ||
| 1319 | + | ||
| 1320 | +static int | ||
| 1321 | +frame_required_for_rtx (rtx *loc, void *data ATTRIBUTE_UNUSED) | ||
| 1322 | +{ | ||
| 1323 | + rtx x = *loc; | ||
| 1324 | + if (x == stack_pointer_rtx || x == hard_frame_pointer_rtx | ||
| 1325 | + || x == arg_pointer_rtx || x == pic_offset_table_rtx | ||
| 1326 | +#ifdef RETURN_ADDR_REGNUM | ||
| 1327 | + || (REG_P (x) && REGNO (x) == RETURN_ADDR_REGNUM) | ||
| 1328 | +#endif | ||
| 1329 | + ) | ||
| 1330 | + return 1; | ||
| 1331 | + return 0; | ||
| 1332 | +} | ||
| 1333 | + | ||
| 1334 | +static bool | ||
| 1335 | +requires_stack_frame_p (rtx insn) | ||
| 1336 | +{ | ||
| 1337 | + HARD_REG_SET hardregs; | ||
| 1338 | + unsigned regno; | ||
| 1339 | + | ||
| 1340 | + if (!INSN_P (insn) || DEBUG_INSN_P (insn)) | ||
| 1341 | + return false; | ||
| 1342 | + if (CALL_P (insn)) | ||
| 1343 | + return !SIBLING_CALL_P (insn); | ||
| 1344 | + if (for_each_rtx (&PATTERN (insn), frame_required_for_rtx, NULL)) | ||
| 1345 | + return true; | ||
| 1346 | + CLEAR_HARD_REG_SET (hardregs); | ||
| 1347 | + note_stores (PATTERN (insn), record_hard_reg_sets, &hardregs); | ||
| 1348 | + AND_COMPL_HARD_REG_SET (hardregs, call_used_reg_set); | ||
| 1349 | + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | ||
| 1350 | + if (TEST_HARD_REG_BIT (hardregs, regno) | ||
| 1351 | + && df_regs_ever_live_p (regno)) | ||
| 1352 | + return true; | ||
| 1353 | + return false; | ||
| 1354 | +} | ||
| 1355 | +#endif | ||
| 1356 | + | ||
| 1357 | #ifdef HAVE_return | ||
| 1358 | -/* Insert gen_return at the end of block BB. This also means updating | ||
| 1359 | - block_for_insn appropriately. */ | ||
| 1360 | + | ||
| 1361 | +static rtx | ||
| 1362 | +gen_return_pattern (bool simple_p) | ||
| 1363 | +{ | ||
| 1364 | +#ifdef HAVE_simple_return | ||
| 1365 | + return simple_p ? gen_simple_return () : gen_return (); | ||
| 1366 | +#else | ||
| 1367 | + gcc_assert (!simple_p); | ||
| 1368 | + return gen_return (); | ||
| 1369 | +#endif | ||
| 1370 | +} | ||
| 1371 | + | ||
| 1372 | +/* Insert an appropriate return pattern at the end of block BB. This | ||
| 1373 | + also means updating block_for_insn appropriately. */ | ||
| 1374 | |||
| 1375 | static void | ||
| 1376 | -emit_return_into_block (basic_block bb) | ||
| 1377 | +emit_return_into_block (bool simple_p, basic_block bb) | ||
| 1378 | { | ||
| 1379 | - emit_jump_insn_after (gen_return (), BB_END (bb)); | ||
| 1380 | + rtx jump; | ||
| 1381 | + jump = emit_jump_insn_after (gen_return_pattern (simple_p), BB_END (bb)); | ||
| 1382 | + JUMP_LABEL (jump) = simple_p ? simple_return_rtx : ret_rtx; | ||
| 1383 | } | ||
| 1384 | -#endif /* HAVE_return */ | ||
| 1385 | +#endif | ||
| 1386 | |||
| 1387 | /* Generate the prologue and epilogue RTL if the machine supports it. Thread | ||
| 1388 | this into place with notes indicating where the prologue ends and where | ||
| 1389 | - the epilogue begins. Update the basic block information when possible. */ | ||
| 1390 | + the epilogue begins. Update the basic block information when possible. | ||
| 1391 | + | ||
| 1392 | + Notes on epilogue placement: | ||
| 1393 | + There are several kinds of edges to the exit block: | ||
| 1394 | + * a single fallthru edge from LAST_BB | ||
| 1395 | + * possibly, edges from blocks containing sibcalls | ||
| 1396 | + * possibly, fake edges from infinite loops | ||
| 1397 | + | ||
| 1398 | + The epilogue is always emitted on the fallthru edge from the last basic | ||
| 1399 | + block in the function, LAST_BB, into the exit block. | ||
| 1400 | + | ||
| 1401 | + If LAST_BB is empty except for a label, it is the target of every | ||
| 1402 | + other basic block in the function that ends in a return. If a | ||
| 1403 | + target has a return or simple_return pattern (possibly with | ||
| 1404 | + conditional variants), these basic blocks can be changed so that a | ||
| 1405 | + return insn is emitted into them, and their target is adjusted to | ||
| 1406 | + the real exit block. | ||
| 1407 | + | ||
| 1408 | + Notes on shrink wrapping: We implement a fairly conservative | ||
| 1409 | + version of shrink-wrapping rather than the textbook one. We only | ||
| 1410 | + generate a single prologue and a single epilogue. This is | ||
| 1411 | + sufficient to catch a number of interesting cases involving early | ||
| 1412 | + exits. | ||
| 1413 | + | ||
| 1414 | + First, we identify the blocks that require the prologue to occur before | ||
| 1415 | + them. These are the ones that modify a call-saved register, or reference | ||
| 1416 | + any of the stack or frame pointer registers. To simplify things, we then | ||
| 1417 | + mark everything reachable from these blocks as also requiring a prologue. | ||
| 1418 | + This takes care of loops automatically, and avoids the need to examine | ||
| 1419 | + whether MEMs reference the frame, since it is sufficient to check for | ||
| 1420 | + occurrences of the stack or frame pointer. | ||
| 1421 | + | ||
| 1422 | + We then compute the set of blocks for which the need for a prologue | ||
| 1423 | + is anticipatable (borrowing terminology from the shrink-wrapping | ||
| 1424 | + description in Muchnick's book). These are the blocks which either | ||
| 1425 | + require a prologue themselves, or those that have only successors | ||
| 1426 | + where the prologue is anticipatable. The prologue needs to be | ||
| 1427 | + inserted on all edges from BB1->BB2 where BB2 is in ANTIC and BB1 | ||
| 1428 | + is not. For the moment, we ensure that only one such edge exists. | ||
| 1429 | + | ||
| 1430 | + The epilogue is placed as described above, but we make a | ||
| 1431 | + distinction between inserting return and simple_return patterns | ||
| 1432 | + when modifying other blocks that end in a return. Blocks that end | ||
| 1433 | + in a sibcall omit the sibcall_epilogue if the block is not in | ||
| 1434 | + ANTIC. */ | ||
| 1435 | |||
| 1436 | static void | ||
| 1437 | thread_prologue_and_epilogue_insns (void) | ||
| 1438 | { | ||
| 1439 | int inserted = 0; | ||
| 1440 | + basic_block last_bb; | ||
| 1441 | + bool last_bb_active; | ||
| 1442 | +#ifdef HAVE_simple_return | ||
| 1443 | + bool unconverted_simple_returns = false; | ||
| 1444 | + basic_block simple_return_block = NULL; | ||
| 1445 | +#endif | ||
| 1446 | + rtx returnjump ATTRIBUTE_UNUSED; | ||
| 1447 | + rtx seq ATTRIBUTE_UNUSED, epilogue_end ATTRIBUTE_UNUSED; | ||
| 1448 | + rtx prologue_seq ATTRIBUTE_UNUSED, split_prologue_seq ATTRIBUTE_UNUSED; | ||
| 1449 | + edge entry_edge, orig_entry_edge, exit_fallthru_edge; | ||
| 1450 | edge e; | ||
| 1451 | -#if defined (HAVE_sibcall_epilogue) || defined (HAVE_epilogue) || defined (HAVE_return) || defined (HAVE_prologue) | ||
| 1452 | - rtx seq; | ||
| 1453 | -#endif | ||
| 1454 | -#if defined (HAVE_epilogue) || defined(HAVE_return) | ||
| 1455 | - rtx epilogue_end = NULL_RTX; | ||
| 1456 | -#endif | ||
| 1457 | edge_iterator ei; | ||
| 1458 | + bitmap_head bb_flags; | ||
| 1459 | + | ||
| 1460 | + df_analyze (); | ||
| 1461 | |||
| 1462 | rtl_profile_for_bb (ENTRY_BLOCK_PTR); | ||
| 1463 | + | ||
| 1464 | + epilogue_end = NULL_RTX; | ||
| 1465 | + returnjump = NULL_RTX; | ||
| 1466 | + | ||
| 1467 | + /* Can't deal with multiple successors of the entry block at the | ||
| 1468 | + moment. Function should always have at least one entry | ||
| 1469 | + point. */ | ||
| 1470 | + gcc_assert (single_succ_p (ENTRY_BLOCK_PTR)); | ||
| 1471 | + entry_edge = single_succ_edge (ENTRY_BLOCK_PTR); | ||
| 1472 | + orig_entry_edge = entry_edge; | ||
| 1473 | + | ||
| 1474 | + exit_fallthru_edge = find_fallthru_edge (EXIT_BLOCK_PTR->preds); | ||
| 1475 | + if (exit_fallthru_edge != NULL) | ||
| 1476 | + { | ||
| 1477 | + rtx label; | ||
| 1478 | + | ||
| 1479 | + last_bb = exit_fallthru_edge->src; | ||
| 1480 | + /* Test whether there are active instructions in the last block. */ | ||
| 1481 | + label = BB_END (last_bb); | ||
| 1482 | + while (label && !LABEL_P (label)) | ||
| 1483 | + { | ||
| 1484 | + if (active_insn_p (label)) | ||
| 1485 | + break; | ||
| 1486 | + label = PREV_INSN (label); | ||
| 1487 | + } | ||
| 1488 | + | ||
| 1489 | + last_bb_active = BB_HEAD (last_bb) != label || !LABEL_P (label); | ||
| 1490 | + } | ||
| 1491 | + else | ||
| 1492 | + { | ||
| 1493 | + last_bb = NULL; | ||
| 1494 | + last_bb_active = false; | ||
| 1495 | + } | ||
| 1496 | + | ||
| 1497 | #ifdef HAVE_prologue | ||
| 1498 | if (HAVE_prologue) | ||
| 1499 | { | ||
| 1500 | @@ -5040,20 +5192,169 @@ thread_prologue_and_epilogue_insns (void | ||
| 1501 | emit_insn (gen_blockage ()); | ||
| 1502 | #endif | ||
| 1503 | |||
| 1504 | - seq = get_insns (); | ||
| 1505 | + prologue_seq = get_insns (); | ||
| 1506 | end_sequence (); | ||
| 1507 | set_insn_locators (seq, prologue_locator); | ||
| 1508 | + } | ||
| 1509 | +#endif | ||
| 1510 | |||
| 1511 | - /* Can't deal with multiple successors of the entry block | ||
| 1512 | - at the moment. Function should always have at least one | ||
| 1513 | - entry point. */ | ||
| 1514 | - gcc_assert (single_succ_p (ENTRY_BLOCK_PTR)); | ||
| 1515 | + bitmap_initialize (&bb_flags, &bitmap_default_obstack); | ||
| 1516 | |||
| 1517 | - insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR)); | ||
| 1518 | - inserted = 1; | ||
| 1519 | +#ifdef HAVE_simple_return | ||
| 1520 | + /* Try to perform a kind of shrink-wrapping, making sure the | ||
| 1521 | + prologue/epilogue is emitted only around those parts of the | ||
| 1522 | + function that require it. */ | ||
| 1523 | + | ||
| 1524 | + if (flag_shrink_wrap && HAVE_simple_return && !flag_non_call_exceptions | ||
| 1525 | + && HAVE_prologue && !crtl->calls_eh_return) | ||
| 1526 | + { | ||
| 1527 | + HARD_REG_SET prologue_clobbered, live_on_edge; | ||
| 1528 | + rtx p_insn; | ||
| 1529 | + VEC(basic_block, heap) *vec; | ||
| 1530 | + basic_block bb; | ||
| 1531 | + bitmap_head bb_antic_flags; | ||
| 1532 | + bitmap_head bb_on_list; | ||
| 1533 | + | ||
| 1534 | + bitmap_initialize (&bb_antic_flags, &bitmap_default_obstack); | ||
| 1535 | + bitmap_initialize (&bb_on_list, &bitmap_default_obstack); | ||
| 1536 | + | ||
| 1537 | + vec = VEC_alloc (basic_block, heap, n_basic_blocks); | ||
| 1538 | + | ||
| 1539 | + FOR_EACH_BB (bb) | ||
| 1540 | + { | ||
| 1541 | + rtx insn; | ||
| 1542 | + FOR_BB_INSNS (bb, insn) | ||
| 1543 | + { | ||
| 1544 | + if (requires_stack_frame_p (insn)) | ||
| 1545 | + { | ||
| 1546 | + bitmap_set_bit (&bb_flags, bb->index); | ||
| 1547 | + VEC_quick_push (basic_block, vec, bb); | ||
| 1548 | + break; | ||
| 1549 | + } | ||
| 1550 | + } | ||
| 1551 | + } | ||
| 1552 | + | ||
| 1553 | + /* For every basic block that needs a prologue, mark all blocks | ||
| 1554 | + reachable from it, so as to ensure they are also seen as | ||
| 1555 | + requiring a prologue. */ | ||
| 1556 | + while (!VEC_empty (basic_block, vec)) | ||
| 1557 | + { | ||
| 1558 | + basic_block tmp_bb = VEC_pop (basic_block, vec); | ||
| 1559 | + edge e; | ||
| 1560 | + edge_iterator ei; | ||
| 1561 | + FOR_EACH_EDGE (e, ei, tmp_bb->succs) | ||
| 1562 | + { | ||
| 1563 | + if (e->dest == EXIT_BLOCK_PTR | ||
| 1564 | + || bitmap_bit_p (&bb_flags, e->dest->index)) | ||
| 1565 | + continue; | ||
| 1566 | + bitmap_set_bit (&bb_flags, e->dest->index); | ||
| 1567 | + VEC_quick_push (basic_block, vec, e->dest); | ||
| 1568 | + } | ||
| 1569 | + } | ||
| 1570 | + /* If the last basic block contains only a label, we'll be able | ||
| 1571 | + to convert jumps to it to (potentially conditional) return | ||
| 1572 | + insns later. This means we don't necessarily need a prologue | ||
| 1573 | + for paths reaching it. */ | ||
| 1574 | + if (last_bb) | ||
| 1575 | + { | ||
| 1576 | + if (!last_bb_active) | ||
| 1577 | + bitmap_clear_bit (&bb_flags, last_bb->index); | ||
| 1578 | + else if (!bitmap_bit_p (&bb_flags, last_bb->index)) | ||
| 1579 | + goto fail_shrinkwrap; | ||
| 1580 | + } | ||
| 1581 | + | ||
| 1582 | + /* Now walk backwards from every block that is marked as needing | ||
| 1583 | + a prologue to compute the bb_antic_flags bitmap. */ | ||
| 1584 | + bitmap_copy (&bb_antic_flags, &bb_flags); | ||
| 1585 | + FOR_EACH_BB (bb) | ||
| 1586 | + { | ||
| 1587 | + edge e; | ||
| 1588 | + edge_iterator ei; | ||
| 1589 | + if (!bitmap_bit_p (&bb_flags, bb->index)) | ||
| 1590 | + continue; | ||
| 1591 | + FOR_EACH_EDGE (e, ei, bb->preds) | ||
| 1592 | + if (!bitmap_bit_p (&bb_antic_flags, e->src->index)) | ||
| 1593 | + { | ||
| 1594 | + VEC_quick_push (basic_block, vec, e->src); | ||
| 1595 | + bitmap_set_bit (&bb_on_list, e->src->index); | ||
| 1596 | + } | ||
| 1597 | + } | ||
| 1598 | + while (!VEC_empty (basic_block, vec)) | ||
| 1599 | + { | ||
| 1600 | + basic_block tmp_bb = VEC_pop (basic_block, vec); | ||
| 1601 | + edge e; | ||
| 1602 | + edge_iterator ei; | ||
| 1603 | + bool all_set = true; | ||
| 1604 | + | ||
| 1605 | + bitmap_clear_bit (&bb_on_list, tmp_bb->index); | ||
| 1606 | + FOR_EACH_EDGE (e, ei, tmp_bb->succs) | ||
| 1607 | + { | ||
| 1608 | + if (!bitmap_bit_p (&bb_antic_flags, e->dest->index)) | ||
| 1609 | + { | ||
| 1610 | + all_set = false; | ||
| 1611 | + break; | ||
| 1612 | + } | ||
| 1613 | + } | ||
| 1614 | + if (all_set) | ||
| 1615 | + { | ||
| 1616 | + bitmap_set_bit (&bb_antic_flags, tmp_bb->index); | ||
| 1617 | + FOR_EACH_EDGE (e, ei, tmp_bb->preds) | ||
| 1618 | + if (!bitmap_bit_p (&bb_antic_flags, e->src->index)) | ||
| 1619 | + { | ||
| 1620 | + VEC_quick_push (basic_block, vec, e->src); | ||
| 1621 | + bitmap_set_bit (&bb_on_list, e->src->index); | ||
| 1622 | + } | ||
| 1623 | + } | ||
| 1624 | + } | ||
| 1625 | + /* Find exactly one edge that leads to a block in ANTIC from | ||
| 1626 | + a block that isn't. */ | ||
| 1627 | + if (!bitmap_bit_p (&bb_antic_flags, entry_edge->dest->index)) | ||
| 1628 | + FOR_EACH_BB (bb) | ||
| 1629 | + { | ||
| 1630 | + if (!bitmap_bit_p (&bb_antic_flags, bb->index)) | ||
| 1631 | + continue; | ||
| 1632 | + FOR_EACH_EDGE (e, ei, bb->preds) | ||
| 1633 | + if (!bitmap_bit_p (&bb_antic_flags, e->src->index)) | ||
| 1634 | + { | ||
| 1635 | + if (entry_edge != orig_entry_edge) | ||
| 1636 | + { | ||
| 1637 | + entry_edge = orig_entry_edge; | ||
| 1638 | + goto fail_shrinkwrap; | ||
| 1639 | + } | ||
| 1640 | + entry_edge = e; | ||
| 1641 | + } | ||
| 1642 | + } | ||
| 1643 | + | ||
| 1644 | + /* Test whether the prologue is known to clobber any register | ||
| 1645 | + (other than FP or SP) which are live on the edge. */ | ||
| 1646 | + CLEAR_HARD_REG_SET (prologue_clobbered); | ||
| 1647 | + for (p_insn = prologue_seq; p_insn; p_insn = NEXT_INSN (p_insn)) | ||
| 1648 | + if (NONDEBUG_INSN_P (p_insn)) | ||
| 1649 | + note_stores (PATTERN (p_insn), record_hard_reg_sets, | ||
| 1650 | + &prologue_clobbered); | ||
| 1651 | + CLEAR_HARD_REG_BIT (prologue_clobbered, STACK_POINTER_REGNUM); | ||
| 1652 | + if (frame_pointer_needed) | ||
| 1653 | + CLEAR_HARD_REG_BIT (prologue_clobbered, HARD_FRAME_POINTER_REGNUM); | ||
| 1654 | + | ||
| 1655 | + CLEAR_HARD_REG_SET (live_on_edge); | ||
| 1656 | + reg_set_to_hard_reg_set (&live_on_edge, | ||
| 1657 | + df_get_live_in (entry_edge->dest)); | ||
| 1658 | + if (hard_reg_set_intersect_p (live_on_edge, prologue_clobbered)) | ||
| 1659 | + entry_edge = orig_entry_edge; | ||
| 1660 | + | ||
| 1661 | + fail_shrinkwrap: | ||
| 1662 | + bitmap_clear (&bb_antic_flags); | ||
| 1663 | + bitmap_clear (&bb_on_list); | ||
| 1664 | + VEC_free (basic_block, heap, vec); | ||
| 1665 | } | ||
| 1666 | #endif | ||
| 1667 | |||
| 1668 | + if (prologue_seq != NULL_RTX) | ||
| 1669 | + { | ||
| 1670 | + insert_insn_on_edge (prologue_seq, entry_edge); | ||
| 1671 | + inserted = true; | ||
| 1672 | + } | ||
| 1673 | + | ||
| 1674 | /* If the exit block has no non-fake predecessors, we don't need | ||
| 1675 | an epilogue. */ | ||
| 1676 | FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) | ||
| 1677 | @@ -5063,100 +5364,130 @@ thread_prologue_and_epilogue_insns (void | ||
| 1678 | goto epilogue_done; | ||
| 1679 | |||
| 1680 | rtl_profile_for_bb (EXIT_BLOCK_PTR); | ||
| 1681 | + | ||
| 1682 | #ifdef HAVE_return | ||
| 1683 | - if (optimize && HAVE_return) | ||
| 1684 | + /* If we're allowed to generate a simple return instruction, then by | ||
| 1685 | + definition we don't need a full epilogue. If the last basic | ||
| 1686 | + block before the exit block does not contain active instructions, | ||
| 1687 | + examine its predecessors and try to emit (conditional) return | ||
| 1688 | + instructions. */ | ||
| 1689 | + if (optimize && !last_bb_active | ||
| 1690 | + && (HAVE_return || entry_edge != orig_entry_edge)) | ||
| 1691 | { | ||
| 1692 | - /* If we're allowed to generate a simple return instruction, | ||
| 1693 | - then by definition we don't need a full epilogue. Examine | ||
| 1694 | - the block that falls through to EXIT. If it does not | ||
| 1695 | - contain any code, examine its predecessors and try to | ||
| 1696 | - emit (conditional) return instructions. */ | ||
| 1697 | - | ||
| 1698 | - basic_block last; | ||
| 1699 | + edge_iterator ei2; | ||
| 1700 | + int i; | ||
| 1701 | + basic_block bb; | ||
| 1702 | rtx label; | ||
| 1703 | + VEC(basic_block,heap) *src_bbs; | ||
| 1704 | |||
| 1705 | - FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) | ||
| 1706 | - if (e->flags & EDGE_FALLTHRU) | ||
| 1707 | - break; | ||
| 1708 | - if (e == NULL) | ||
| 1709 | + if (exit_fallthru_edge == NULL) | ||
| 1710 | goto epilogue_done; | ||
| 1711 | - last = e->src; | ||
| 1712 | + label = BB_HEAD (last_bb); | ||
| 1713 | |||
| 1714 | - /* Verify that there are no active instructions in the last block. */ | ||
| 1715 | - label = BB_END (last); | ||
| 1716 | - while (label && !LABEL_P (label)) | ||
| 1717 | - { | ||
| 1718 | - if (active_insn_p (label)) | ||
| 1719 | - break; | ||
| 1720 | - label = PREV_INSN (label); | ||
| 1721 | - } | ||
| 1722 | + src_bbs = VEC_alloc (basic_block, heap, EDGE_COUNT (last_bb->preds)); | ||
| 1723 | + FOR_EACH_EDGE (e, ei2, last_bb->preds) | ||
| 1724 | + if (e->src != ENTRY_BLOCK_PTR) | ||
| 1725 | + VEC_quick_push (basic_block, src_bbs, e->src); | ||
| 1726 | |||
| 1727 | - if (BB_HEAD (last) == label && LABEL_P (label)) | ||
| 1728 | + FOR_EACH_VEC_ELT (basic_block, src_bbs, i, bb) | ||
| 1729 | { | ||
| 1730 | - edge_iterator ei2; | ||
| 1731 | + bool simple_p; | ||
| 1732 | + rtx jump; | ||
| 1733 | + e = find_edge (bb, last_bb); | ||
| 1734 | |||
| 1735 | - for (ei2 = ei_start (last->preds); (e = ei_safe_edge (ei2)); ) | ||
| 1736 | - { | ||
| 1737 | - basic_block bb = e->src; | ||
| 1738 | - rtx jump; | ||
| 1739 | + jump = BB_END (bb); | ||
| 1740 | |||
| 1741 | - if (bb == ENTRY_BLOCK_PTR) | ||
| 1742 | - { | ||
| 1743 | - ei_next (&ei2); | ||
| 1744 | - continue; | ||
| 1745 | - } | ||
| 1746 | +#ifdef HAVE_simple_return | ||
| 1747 | + simple_p = (entry_edge != orig_entry_edge | ||
| 1748 | + ? !bitmap_bit_p (&bb_flags, bb->index) : false); | ||
| 1749 | +#else | ||
| 1750 | + simple_p = false; | ||
| 1751 | +#endif | ||
| 1752 | |||
| 1753 | - jump = BB_END (bb); | ||
| 1754 | - if (!JUMP_P (jump) || JUMP_LABEL (jump) != label) | ||
| 1755 | - { | ||
| 1756 | - ei_next (&ei2); | ||
| 1757 | - continue; | ||
| 1758 | - } | ||
| 1759 | + if (!simple_p | ||
| 1760 | + && (!HAVE_return || !JUMP_P (jump) | ||
| 1761 | + || JUMP_LABEL (jump) != label)) | ||
| 1762 | + continue; | ||
| 1763 | |||
| 1764 | - /* If we have an unconditional jump, we can replace that | ||
| 1765 | - with a simple return instruction. */ | ||
| 1766 | - if (simplejump_p (jump)) | ||
| 1767 | - { | ||
| 1768 | - emit_return_into_block (bb); | ||
| 1769 | - delete_insn (jump); | ||
| 1770 | - } | ||
| 1771 | + /* If we have an unconditional jump, we can replace that | ||
| 1772 | + with a simple return instruction. */ | ||
| 1773 | + if (!JUMP_P (jump)) | ||
| 1774 | + { | ||
| 1775 | + emit_barrier_after (BB_END (bb)); | ||
| 1776 | + emit_return_into_block (simple_p, bb); | ||
| 1777 | + } | ||
| 1778 | + else if (simplejump_p (jump)) | ||
| 1779 | + { | ||
| 1780 | + emit_return_into_block (simple_p, bb); | ||
| 1781 | + delete_insn (jump); | ||
| 1782 | + } | ||
| 1783 | + else if (condjump_p (jump) && JUMP_LABEL (jump) != label) | ||
| 1784 | + { | ||
| 1785 | + basic_block new_bb; | ||
| 1786 | + edge new_e; | ||
| 1787 | |||
| 1788 | - /* If we have a conditional jump, we can try to replace | ||
| 1789 | - that with a conditional return instruction. */ | ||
| 1790 | - else if (condjump_p (jump)) | ||
| 1791 | - { | ||
| 1792 | - if (! redirect_jump (jump, 0, 0)) | ||
| 1793 | - { | ||
| 1794 | - ei_next (&ei2); | ||
| 1795 | - continue; | ||
| 1796 | - } | ||
| 1797 | + gcc_assert (simple_p); | ||
| 1798 | + new_bb = split_edge (e); | ||
| 1799 | + emit_barrier_after (BB_END (new_bb)); | ||
| 1800 | + emit_return_into_block (simple_p, new_bb); | ||
| 1801 | +#ifdef HAVE_simple_return | ||
| 1802 | + simple_return_block = new_bb; | ||
| 1803 | +#endif | ||
| 1804 | + new_e = single_succ_edge (new_bb); | ||
| 1805 | + redirect_edge_succ (new_e, EXIT_BLOCK_PTR); | ||
| 1806 | |||
| 1807 | - /* If this block has only one successor, it both jumps | ||
| 1808 | - and falls through to the fallthru block, so we can't | ||
| 1809 | - delete the edge. */ | ||
| 1810 | - if (single_succ_p (bb)) | ||
| 1811 | - { | ||
| 1812 | - ei_next (&ei2); | ||
| 1813 | - continue; | ||
| 1814 | - } | ||
| 1815 | - } | ||
| 1816 | + continue; | ||
| 1817 | + } | ||
| 1818 | + /* If we have a conditional jump branching to the last | ||
| 1819 | + block, we can try to replace that with a conditional | ||
| 1820 | + return instruction. */ | ||
| 1821 | + else if (condjump_p (jump)) | ||
| 1822 | + { | ||
| 1823 | + rtx dest; | ||
| 1824 | + if (simple_p) | ||
| 1825 | + dest = simple_return_rtx; | ||
| 1826 | else | ||
| 1827 | + dest = ret_rtx; | ||
| 1828 | + if (! redirect_jump (jump, dest, 0)) | ||
| 1829 | { | ||
| 1830 | - ei_next (&ei2); | ||
| 1831 | +#ifdef HAVE_simple_return | ||
| 1832 | + if (simple_p) | ||
| 1833 | + unconverted_simple_returns = true; | ||
| 1834 | +#endif | ||
| 1835 | continue; | ||
| 1836 | } | ||
| 1837 | |||
| 1838 | - /* Fix up the CFG for the successful change we just made. */ | ||
| 1839 | - redirect_edge_succ (e, EXIT_BLOCK_PTR); | ||
| 1840 | + /* If this block has only one successor, it both jumps | ||
| 1841 | + and falls through to the fallthru block, so we can't | ||
| 1842 | + delete the edge. */ | ||
| 1843 | + if (single_succ_p (bb)) | ||
| 1844 | + continue; | ||
| 1845 | + } | ||
| 1846 | + else | ||
| 1847 | + { | ||
| 1848 | +#ifdef HAVE_simple_return | ||
| 1849 | + if (simple_p) | ||
| 1850 | + unconverted_simple_returns = true; | ||
| 1851 | +#endif | ||
| 1852 | + continue; | ||
| 1853 | } | ||
| 1854 | |||
| 1855 | + /* Fix up the CFG for the successful change we just made. */ | ||
| 1856 | + redirect_edge_succ (e, EXIT_BLOCK_PTR); | ||
| 1857 | + } | ||
| 1858 | + VEC_free (basic_block, heap, src_bbs); | ||
| 1859 | + | ||
| 1860 | + if (HAVE_return) | ||
| 1861 | + { | ||
| 1862 | /* Emit a return insn for the exit fallthru block. Whether | ||
| 1863 | this is still reachable will be determined later. */ | ||
| 1864 | |||
| 1865 | - emit_barrier_after (BB_END (last)); | ||
| 1866 | - emit_return_into_block (last); | ||
| 1867 | - epilogue_end = BB_END (last); | ||
| 1868 | - single_succ_edge (last)->flags &= ~EDGE_FALLTHRU; | ||
| 1869 | + emit_barrier_after (BB_END (last_bb)); | ||
| 1870 | + emit_return_into_block (false, last_bb); | ||
| 1871 | + epilogue_end = BB_END (last_bb); | ||
| 1872 | + if (JUMP_P (epilogue_end)) | ||
| 1873 | + JUMP_LABEL (epilogue_end) = ret_rtx; | ||
| 1874 | + single_succ_edge (last_bb)->flags &= ~EDGE_FALLTHRU; | ||
| 1875 | goto epilogue_done; | ||
| 1876 | } | ||
| 1877 | } | ||
| 1878 | @@ -5193,15 +5524,10 @@ thread_prologue_and_epilogue_insns (void | ||
| 1879 | } | ||
| 1880 | #endif | ||
| 1881 | |||
| 1882 | - /* Find the edge that falls through to EXIT. Other edges may exist | ||
| 1883 | - due to RETURN instructions, but those don't need epilogues. | ||
| 1884 | - There really shouldn't be a mixture -- either all should have | ||
| 1885 | - been converted or none, however... */ | ||
| 1886 | + /* If nothing falls through into the exit block, we don't need an | ||
| 1887 | + epilogue. */ | ||
| 1888 | |||
| 1889 | - FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) | ||
| 1890 | - if (e->flags & EDGE_FALLTHRU) | ||
| 1891 | - break; | ||
| 1892 | - if (e == NULL) | ||
| 1893 | + if (exit_fallthru_edge == NULL) | ||
| 1894 | goto epilogue_done; | ||
| 1895 | |||
| 1896 | #ifdef HAVE_epilogue | ||
| 1897 | @@ -5217,25 +5543,36 @@ thread_prologue_and_epilogue_insns (void | ||
| 1898 | set_insn_locators (seq, epilogue_locator); | ||
| 1899 | |||
| 1900 | seq = get_insns (); | ||
| 1901 | + returnjump = get_last_insn (); | ||
| 1902 | end_sequence (); | ||
| 1903 | |||
| 1904 | - insert_insn_on_edge (seq, e); | ||
| 1905 | + insert_insn_on_edge (seq, exit_fallthru_edge); | ||
| 1906 | inserted = 1; | ||
| 1907 | + if (JUMP_P (returnjump)) | ||
| 1908 | + { | ||
| 1909 | + rtx pat = PATTERN (returnjump); | ||
| 1910 | + if (GET_CODE (pat) == PARALLEL) | ||
| 1911 | + pat = XVECEXP (pat, 0, 0); | ||
| 1912 | + if (ANY_RETURN_P (pat)) | ||
| 1913 | + JUMP_LABEL (returnjump) = pat; | ||
| 1914 | + else | ||
| 1915 | + JUMP_LABEL (returnjump) = ret_rtx; | ||
| 1916 | + } | ||
| 1917 | } | ||
| 1918 | else | ||
| 1919 | #endif | ||
| 1920 | { | ||
| 1921 | basic_block cur_bb; | ||
| 1922 | |||
| 1923 | - if (! next_active_insn (BB_END (e->src))) | ||
| 1924 | + if (! next_active_insn (BB_END (exit_fallthru_edge->src))) | ||
| 1925 | goto epilogue_done; | ||
| 1926 | /* We have a fall-through edge to the exit block, the source is not | ||
| 1927 | - at the end of the function, and there will be an assembler epilogue | ||
| 1928 | - at the end of the function. | ||
| 1929 | - We can't use force_nonfallthru here, because that would try to | ||
| 1930 | - use return. Inserting a jump 'by hand' is extremely messy, so | ||
| 1931 | + at the end of the function, and there will be an assembler epilogue | ||
| 1932 | + at the end of the function. | ||
| 1933 | + We can't use force_nonfallthru here, because that would try to | ||
| 1934 | + use return. Inserting a jump 'by hand' is extremely messy, so | ||
| 1935 | we take advantage of cfg_layout_finalize using | ||
| 1936 | - fixup_fallthru_exit_predecessor. */ | ||
| 1937 | + fixup_fallthru_exit_predecessor. */ | ||
| 1938 | cfg_layout_initialize (0); | ||
| 1939 | FOR_EACH_BB (cur_bb) | ||
| 1940 | if (cur_bb->index >= NUM_FIXED_BLOCKS | ||
| 1941 | @@ -5244,6 +5581,7 @@ thread_prologue_and_epilogue_insns (void | ||
| 1942 | cfg_layout_finalize (); | ||
| 1943 | } | ||
| 1944 | epilogue_done: | ||
| 1945 | + | ||
| 1946 | default_rtl_profile (); | ||
| 1947 | |||
| 1948 | if (inserted) | ||
| 1949 | @@ -5260,33 +5598,93 @@ epilogue_done: | ||
| 1950 | } | ||
| 1951 | } | ||
| 1952 | |||
| 1953 | +#ifdef HAVE_simple_return | ||
| 1954 | + /* If there were branches to an empty LAST_BB which we tried to | ||
| 1955 | + convert to conditional simple_returns, but couldn't for some | ||
| 1956 | + reason, create a block to hold a simple_return insn and redirect | ||
| 1957 | + those remaining edges. */ | ||
| 1958 | + if (unconverted_simple_returns) | ||
| 1959 | + { | ||
| 1960 | + edge_iterator ei2; | ||
| 1961 | + basic_block exit_pred = EXIT_BLOCK_PTR->prev_bb; | ||
| 1962 | + | ||
| 1963 | + gcc_assert (entry_edge != orig_entry_edge); | ||
| 1964 | + | ||
| 1965 | +#ifdef HAVE_epilogue | ||
| 1966 | + if (simple_return_block == NULL && returnjump != NULL_RTX | ||
| 1967 | + && JUMP_LABEL (returnjump) == simple_return_rtx) | ||
| 1968 | + { | ||
| 1969 | + edge e = split_block (exit_fallthru_edge->src, | ||
| 1970 | + PREV_INSN (returnjump)); | ||
| 1971 | + simple_return_block = e->dest; | ||
| 1972 | + } | ||
| 1973 | +#endif | ||
| 1974 | + if (simple_return_block == NULL) | ||
| 1975 | + { | ||
| 1976 | + basic_block bb; | ||
| 1977 | + rtx start; | ||
| 1978 | + | ||
| 1979 | + bb = create_basic_block (NULL, NULL, exit_pred); | ||
| 1980 | + start = emit_jump_insn_after (gen_simple_return (), | ||
| 1981 | + BB_END (bb)); | ||
| 1982 | + JUMP_LABEL (start) = simple_return_rtx; | ||
| 1983 | + emit_barrier_after (start); | ||
| 1984 | + | ||
| 1985 | + simple_return_block = bb; | ||
| 1986 | + make_edge (bb, EXIT_BLOCK_PTR, 0); | ||
| 1987 | + } | ||
| 1988 | + | ||
| 1989 | + restart_scan: | ||
| 1990 | + for (ei2 = ei_start (last_bb->preds); (e = ei_safe_edge (ei2)); ) | ||
| 1991 | + { | ||
| 1992 | + basic_block bb = e->src; | ||
| 1993 | + | ||
| 1994 | + if (bb != ENTRY_BLOCK_PTR | ||
| 1995 | + && !bitmap_bit_p (&bb_flags, bb->index)) | ||
| 1996 | + { | ||
| 1997 | + redirect_edge_and_branch_force (e, simple_return_block); | ||
| 1998 | + goto restart_scan; | ||
| 1999 | + } | ||
| 2000 | + ei_next (&ei2); | ||
| 2001 | + | ||
| 2002 | + } | ||
| 2003 | + } | ||
| 2004 | +#endif | ||
| 2005 | + | ||
| 2006 | #ifdef HAVE_sibcall_epilogue | ||
| 2007 | /* Emit sibling epilogues before any sibling call sites. */ | ||
| 2008 | for (ei = ei_start (EXIT_BLOCK_PTR->preds); (e = ei_safe_edge (ei)); ) | ||
| 2009 | { | ||
| 2010 | basic_block bb = e->src; | ||
| 2011 | rtx insn = BB_END (bb); | ||
| 2012 | + rtx ep_seq; | ||
| 2013 | |||
| 2014 | if (!CALL_P (insn) | ||
| 2015 | - || ! SIBLING_CALL_P (insn)) | ||
| 2016 | + || ! SIBLING_CALL_P (insn) | ||
| 2017 | + || (entry_edge != orig_entry_edge | ||
| 2018 | + && !bitmap_bit_p (&bb_flags, bb->index))) | ||
| 2019 | { | ||
| 2020 | ei_next (&ei); | ||
| 2021 | continue; | ||
| 2022 | } | ||
| 2023 | |||
| 2024 | - start_sequence (); | ||
| 2025 | - emit_note (NOTE_INSN_EPILOGUE_BEG); | ||
| 2026 | - emit_insn (gen_sibcall_epilogue ()); | ||
| 2027 | - seq = get_insns (); | ||
| 2028 | - end_sequence (); | ||
| 2029 | + ep_seq = gen_sibcall_epilogue (); | ||
| 2030 | + if (ep_seq) | ||
| 2031 | + { | ||
| 2032 | + start_sequence (); | ||
| 2033 | + emit_note (NOTE_INSN_EPILOGUE_BEG); | ||
| 2034 | + emit_insn (ep_seq); | ||
| 2035 | + seq = get_insns (); | ||
| 2036 | + end_sequence (); | ||
| 2037 | |||
| 2038 | - /* Retain a map of the epilogue insns. Used in life analysis to | ||
| 2039 | - avoid getting rid of sibcall epilogue insns. Do this before we | ||
| 2040 | - actually emit the sequence. */ | ||
| 2041 | - record_insns (seq, NULL, &epilogue_insn_hash); | ||
| 2042 | - set_insn_locators (seq, epilogue_locator); | ||
| 2043 | + /* Retain a map of the epilogue insns. Used in life analysis to | ||
| 2044 | + avoid getting rid of sibcall epilogue insns. Do this before we | ||
| 2045 | + actually emit the sequence. */ | ||
| 2046 | + record_insns (seq, NULL, &epilogue_insn_hash); | ||
| 2047 | + set_insn_locators (seq, epilogue_locator); | ||
| 2048 | |||
| 2049 | - emit_insn_before (seq, insn); | ||
| 2050 | + emit_insn_before (seq, insn); | ||
| 2051 | + } | ||
| 2052 | ei_next (&ei); | ||
| 2053 | } | ||
| 2054 | #endif | ||
| 2055 | @@ -5311,6 +5709,8 @@ epilogue_done: | ||
| 2056 | } | ||
| 2057 | #endif | ||
| 2058 | |||
| 2059 | + bitmap_clear (&bb_flags); | ||
| 2060 | + | ||
| 2061 | /* Threading the prologue and epilogue changes the artificial refs | ||
| 2062 | in the entry and exit blocks. */ | ||
| 2063 | epilogue_completed = 1; | ||
| 2064 | Index: gcc-4_5-branch/gcc/genemit.c | ||
| 2065 | =================================================================== | ||
| 2066 | --- gcc-4_5-branch.orig/gcc/genemit.c | ||
| 2067 | +++ gcc-4_5-branch/gcc/genemit.c | ||
| 2068 | @@ -222,6 +222,12 @@ gen_exp (rtx x, enum rtx_code subroutine | ||
| 2069 | case PC: | ||
| 2070 | printf ("pc_rtx"); | ||
| 2071 | return; | ||
| 2072 | + case RETURN: | ||
| 2073 | + printf ("ret_rtx"); | ||
| 2074 | + return; | ||
| 2075 | + case SIMPLE_RETURN: | ||
| 2076 | + printf ("simple_return_rtx"); | ||
| 2077 | + return; | ||
| 2078 | case CLOBBER: | ||
| 2079 | if (REG_P (XEXP (x, 0))) | ||
| 2080 | { | ||
| 2081 | @@ -544,8 +550,8 @@ gen_expand (rtx expand) | ||
| 2082 | || (GET_CODE (next) == PARALLEL | ||
| 2083 | && ((GET_CODE (XVECEXP (next, 0, 0)) == SET | ||
| 2084 | && GET_CODE (SET_DEST (XVECEXP (next, 0, 0))) == PC) | ||
| 2085 | - || GET_CODE (XVECEXP (next, 0, 0)) == RETURN)) | ||
| 2086 | - || GET_CODE (next) == RETURN) | ||
| 2087 | + || ANY_RETURN_P (XVECEXP (next, 0, 0)))) | ||
| 2088 | + || ANY_RETURN_P (next)) | ||
| 2089 | printf (" emit_jump_insn ("); | ||
| 2090 | else if ((GET_CODE (next) == SET && GET_CODE (SET_SRC (next)) == CALL) | ||
| 2091 | || GET_CODE (next) == CALL | ||
| 2092 | @@ -660,7 +666,7 @@ gen_split (rtx split) | ||
| 2093 | || (GET_CODE (next) == PARALLEL | ||
| 2094 | && GET_CODE (XVECEXP (next, 0, 0)) == SET | ||
| 2095 | && GET_CODE (SET_DEST (XVECEXP (next, 0, 0))) == PC) | ||
| 2096 | - || GET_CODE (next) == RETURN) | ||
| 2097 | + || ANY_RETURN_P (next)) | ||
| 2098 | printf (" emit_jump_insn ("); | ||
| 2099 | else if ((GET_CODE (next) == SET && GET_CODE (SET_SRC (next)) == CALL) | ||
| 2100 | || GET_CODE (next) == CALL | ||
| 2101 | Index: gcc-4_5-branch/gcc/gengenrtl.c | ||
| 2102 | =================================================================== | ||
| 2103 | --- gcc-4_5-branch.orig/gcc/gengenrtl.c | ||
| 2104 | +++ gcc-4_5-branch/gcc/gengenrtl.c | ||
| 2105 | @@ -146,6 +146,10 @@ special_rtx (int idx) | ||
| 2106 | || strcmp (defs[idx].enumname, "REG") == 0 | ||
| 2107 | || strcmp (defs[idx].enumname, "SUBREG") == 0 | ||
| 2108 | || strcmp (defs[idx].enumname, "MEM") == 0 | ||
| 2109 | + || strcmp (defs[idx].enumname, "PC") == 0 | ||
| 2110 | + || strcmp (defs[idx].enumname, "CC0") == 0 | ||
| 2111 | + || strcmp (defs[idx].enumname, "RETURN") == 0 | ||
| 2112 | + || strcmp (defs[idx].enumname, "SIMPLE_RETURN") == 0 | ||
| 2113 | || strcmp (defs[idx].enumname, "CONST_VECTOR") == 0); | ||
| 2114 | } | ||
| 2115 | |||
| 2116 | Index: gcc-4_5-branch/gcc/haifa-sched.c | ||
| 2117 | =================================================================== | ||
| 2118 | --- gcc-4_5-branch.orig/gcc/haifa-sched.c | ||
| 2119 | +++ gcc-4_5-branch/gcc/haifa-sched.c | ||
| 2120 | @@ -4231,7 +4231,7 @@ xrecalloc (void *p, size_t new_nmemb, si | ||
| 2121 | /* Helper function. | ||
| 2122 | Find fallthru edge from PRED. */ | ||
| 2123 | edge | ||
| 2124 | -find_fallthru_edge (basic_block pred) | ||
| 2125 | +find_fallthru_edge_from (basic_block pred) | ||
| 2126 | { | ||
| 2127 | edge e; | ||
| 2128 | edge_iterator ei; | ||
| 2129 | @@ -4298,7 +4298,7 @@ init_before_recovery (basic_block *befor | ||
| 2130 | edge e; | ||
| 2131 | |||
| 2132 | last = EXIT_BLOCK_PTR->prev_bb; | ||
| 2133 | - e = find_fallthru_edge (last); | ||
| 2134 | + e = find_fallthru_edge_from (last); | ||
| 2135 | |||
| 2136 | if (e) | ||
| 2137 | { | ||
| 2138 | @@ -5234,6 +5234,11 @@ check_cfg (rtx head, rtx tail) | ||
| 2139 | gcc_assert (/* Usual case. */ | ||
| 2140 | (EDGE_COUNT (bb->succs) > 1 | ||
| 2141 | && !BARRIER_P (NEXT_INSN (head))) | ||
| 2142 | + /* Special cases, see cfglayout.c: | ||
| 2143 | + fixup_reorder_chain. */ | ||
| 2144 | + || (EDGE_COUNT (bb->succs) == 1 | ||
| 2145 | + && (!onlyjump_p (head) | ||
| 2146 | + || returnjump_p (head))) | ||
| 2147 | /* Or jump to the next instruction. */ | ||
| 2148 | || (EDGE_COUNT (bb->succs) == 1 | ||
| 2149 | && (BB_HEAD (EDGE_I (bb->succs, 0)->dest) | ||
| 2150 | Index: gcc-4_5-branch/gcc/ifcvt.c | ||
| 2151 | =================================================================== | ||
| 2152 | --- gcc-4_5-branch.orig/gcc/ifcvt.c | ||
| 2153 | +++ gcc-4_5-branch/gcc/ifcvt.c | ||
| 2154 | @@ -105,7 +105,7 @@ static int find_if_case_1 (basic_block, | ||
| 2155 | static int find_if_case_2 (basic_block, edge, edge); | ||
| 2156 | static int find_memory (rtx *, void *); | ||
| 2157 | static int dead_or_predicable (basic_block, basic_block, basic_block, | ||
| 2158 | - basic_block, int); | ||
| 2159 | + edge, int); | ||
| 2160 | static void noce_emit_move_insn (rtx, rtx); | ||
| 2161 | static rtx block_has_only_trap (basic_block); | ||
| 2162 | |||
| 2163 | @@ -3791,6 +3791,7 @@ find_if_case_1 (basic_block test_bb, edg | ||
| 2164 | basic_block then_bb = then_edge->dest; | ||
| 2165 | basic_block else_bb = else_edge->dest; | ||
| 2166 | basic_block new_bb; | ||
| 2167 | + rtx else_target = NULL_RTX; | ||
| 2168 | int then_bb_index; | ||
| 2169 | |||
| 2170 | /* If we are partitioning hot/cold basic blocks, we don't want to | ||
| 2171 | @@ -3840,9 +3841,16 @@ find_if_case_1 (basic_block test_bb, edg | ||
| 2172 | predictable_edge_p (then_edge))))) | ||
| 2173 | return FALSE; | ||
| 2174 | |||
| 2175 | + if (else_bb == EXIT_BLOCK_PTR) | ||
| 2176 | + { | ||
| 2177 | + rtx jump = BB_END (else_edge->src); | ||
| 2178 | + gcc_assert (JUMP_P (jump)); | ||
| 2179 | + else_target = JUMP_LABEL (jump); | ||
| 2180 | + } | ||
| 2181 | + | ||
| 2182 | /* Registers set are dead, or are predicable. */ | ||
| 2183 | if (! dead_or_predicable (test_bb, then_bb, else_bb, | ||
| 2184 | - single_succ (then_bb), 1)) | ||
| 2185 | + single_succ_edge (then_bb), 1)) | ||
| 2186 | return FALSE; | ||
| 2187 | |||
| 2188 | /* Conversion went ok, including moving the insns and fixing up the | ||
| 2189 | @@ -3859,6 +3867,9 @@ find_if_case_1 (basic_block test_bb, edg | ||
| 2190 | redirect_edge_succ (FALLTHRU_EDGE (test_bb), else_bb); | ||
| 2191 | new_bb = 0; | ||
| 2192 | } | ||
| 2193 | + else if (else_bb == EXIT_BLOCK_PTR) | ||
| 2194 | + new_bb = force_nonfallthru_and_redirect (FALLTHRU_EDGE (test_bb), | ||
| 2195 | + else_bb, else_target); | ||
| 2196 | else | ||
| 2197 | new_bb = redirect_edge_and_branch_force (FALLTHRU_EDGE (test_bb), | ||
| 2198 | else_bb); | ||
| 2199 | @@ -3957,7 +3968,7 @@ find_if_case_2 (basic_block test_bb, edg | ||
| 2200 | return FALSE; | ||
| 2201 | |||
| 2202 | /* Registers set are dead, or are predicable. */ | ||
| 2203 | - if (! dead_or_predicable (test_bb, else_bb, then_bb, else_succ->dest, 0)) | ||
| 2204 | + if (! dead_or_predicable (test_bb, else_bb, then_bb, else_succ, 0)) | ||
| 2205 | return FALSE; | ||
| 2206 | |||
| 2207 | /* Conversion went ok, including moving the insns and fixing up the | ||
| 2208 | @@ -3995,12 +4006,34 @@ find_memory (rtx *px, void *data ATTRIBU | ||
| 2209 | |||
| 2210 | static int | ||
| 2211 | dead_or_predicable (basic_block test_bb, basic_block merge_bb, | ||
| 2212 | - basic_block other_bb, basic_block new_dest, int reversep) | ||
| 2213 | + basic_block other_bb, edge dest_edge, int reversep) | ||
| 2214 | { | ||
| 2215 | - rtx head, end, jump, earliest = NULL_RTX, old_dest, new_label = NULL_RTX; | ||
| 2216 | + basic_block new_dest = dest_edge->dest; | ||
| 2217 | + rtx head, end, jump, earliest = NULL_RTX, old_dest; | ||
| 2218 | bitmap merge_set = NULL; | ||
| 2219 | /* Number of pending changes. */ | ||
| 2220 | int n_validated_changes = 0; | ||
| 2221 | + rtx new_dest_label; | ||
| 2222 | + | ||
| 2223 | + jump = BB_END (dest_edge->src); | ||
| 2224 | + if (JUMP_P (jump)) | ||
| 2225 | + { | ||
| 2226 | + new_dest_label = JUMP_LABEL (jump); | ||
| 2227 | + if (new_dest_label == NULL_RTX) | ||
| 2228 | + { | ||
| 2229 | + new_dest_label = PATTERN (jump); | ||
| 2230 | + gcc_assert (ANY_RETURN_P (new_dest_label)); | ||
| 2231 | + } | ||
| 2232 | + } | ||
| 2233 | + else if (other_bb != new_dest) | ||
| 2234 | + { | ||
| 2235 | + if (new_dest == EXIT_BLOCK_PTR) | ||
| 2236 | + new_dest_label = ret_rtx; | ||
| 2237 | + else | ||
| 2238 | + new_dest_label = block_label (new_dest); | ||
| 2239 | + } | ||
| 2240 | + else | ||
| 2241 | + new_dest_label = NULL_RTX; | ||
| 2242 | |||
| 2243 | jump = BB_END (test_bb); | ||
| 2244 | |||
| 2245 | @@ -4220,10 +4253,9 @@ dead_or_predicable (basic_block test_bb, | ||
| 2246 | old_dest = JUMP_LABEL (jump); | ||
| 2247 | if (other_bb != new_dest) | ||
| 2248 | { | ||
| 2249 | - new_label = block_label (new_dest); | ||
| 2250 | if (reversep | ||
| 2251 | - ? ! invert_jump_1 (jump, new_label) | ||
| 2252 | - : ! redirect_jump_1 (jump, new_label)) | ||
| 2253 | + ? ! invert_jump_1 (jump, new_dest_label) | ||
| 2254 | + : ! redirect_jump_1 (jump, new_dest_label)) | ||
| 2255 | goto cancel; | ||
| 2256 | } | ||
| 2257 | |||
| 2258 | @@ -4234,7 +4266,7 @@ dead_or_predicable (basic_block test_bb, | ||
| 2259 | |||
| 2260 | if (other_bb != new_dest) | ||
| 2261 | { | ||
| 2262 | - redirect_jump_2 (jump, old_dest, new_label, 0, reversep); | ||
| 2263 | + redirect_jump_2 (jump, old_dest, new_dest_label, 0, reversep); | ||
| 2264 | |||
| 2265 | redirect_edge_succ (BRANCH_EDGE (test_bb), new_dest); | ||
| 2266 | if (reversep) | ||
| 2267 | Index: gcc-4_5-branch/gcc/jump.c | ||
| 2268 | =================================================================== | ||
| 2269 | --- gcc-4_5-branch.orig/gcc/jump.c | ||
| 2270 | +++ gcc-4_5-branch/gcc/jump.c | ||
| 2271 | @@ -29,7 +29,8 @@ along with GCC; see the file COPYING3. | ||
| 2272 | JUMP_LABEL internal field. With this we can detect labels that | ||
| 2273 | become unused because of the deletion of all the jumps that | ||
| 2274 | formerly used them. The JUMP_LABEL info is sometimes looked | ||
| 2275 | - at by later passes. | ||
| 2276 | + at by later passes. For return insns, it contains either a | ||
| 2277 | + RETURN or a SIMPLE_RETURN rtx. | ||
| 2278 | |||
| 2279 | The subroutines redirect_jump and invert_jump are used | ||
| 2280 | from other passes as well. */ | ||
| 2281 | @@ -742,10 +743,10 @@ condjump_p (const_rtx insn) | ||
| 2282 | return (GET_CODE (x) == IF_THEN_ELSE | ||
| 2283 | && ((GET_CODE (XEXP (x, 2)) == PC | ||
| 2284 | && (GET_CODE (XEXP (x, 1)) == LABEL_REF | ||
| 2285 | - || GET_CODE (XEXP (x, 1)) == RETURN)) | ||
| 2286 | + || ANY_RETURN_P (XEXP (x, 1)))) | ||
| 2287 | || (GET_CODE (XEXP (x, 1)) == PC | ||
| 2288 | && (GET_CODE (XEXP (x, 2)) == LABEL_REF | ||
| 2289 | - || GET_CODE (XEXP (x, 2)) == RETURN)))); | ||
| 2290 | + || ANY_RETURN_P (XEXP (x, 2)))))); | ||
| 2291 | } | ||
| 2292 | |||
| 2293 | /* Return nonzero if INSN is a (possibly) conditional jump inside a | ||
| 2294 | @@ -774,11 +775,11 @@ condjump_in_parallel_p (const_rtx insn) | ||
| 2295 | return 0; | ||
| 2296 | if (XEXP (SET_SRC (x), 2) == pc_rtx | ||
| 2297 | && (GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF | ||
| 2298 | - || GET_CODE (XEXP (SET_SRC (x), 1)) == RETURN)) | ||
| 2299 | + || ANY_RETURN_P (XEXP (SET_SRC (x), 1)) == RETURN)) | ||
| 2300 | return 1; | ||
| 2301 | if (XEXP (SET_SRC (x), 1) == pc_rtx | ||
| 2302 | && (GET_CODE (XEXP (SET_SRC (x), 2)) == LABEL_REF | ||
| 2303 | - || GET_CODE (XEXP (SET_SRC (x), 2)) == RETURN)) | ||
| 2304 | + || ANY_RETURN_P (XEXP (SET_SRC (x), 2)))) | ||
| 2305 | return 1; | ||
| 2306 | return 0; | ||
| 2307 | } | ||
| 2308 | @@ -840,8 +841,9 @@ any_condjump_p (const_rtx insn) | ||
| 2309 | a = GET_CODE (XEXP (SET_SRC (x), 1)); | ||
| 2310 | b = GET_CODE (XEXP (SET_SRC (x), 2)); | ||
| 2311 | |||
| 2312 | - return ((b == PC && (a == LABEL_REF || a == RETURN)) | ||
| 2313 | - || (a == PC && (b == LABEL_REF || b == RETURN))); | ||
| 2314 | + return ((b == PC && (a == LABEL_REF || a == RETURN || a == SIMPLE_RETURN)) | ||
| 2315 | + || (a == PC | ||
| 2316 | + && (b == LABEL_REF || b == RETURN || b == SIMPLE_RETURN))); | ||
| 2317 | } | ||
| 2318 | |||
| 2319 | /* Return the label of a conditional jump. */ | ||
| 2320 | @@ -878,6 +880,7 @@ returnjump_p_1 (rtx *loc, void *data ATT | ||
| 2321 | switch (GET_CODE (x)) | ||
| 2322 | { | ||
| 2323 | case RETURN: | ||
| 2324 | + case SIMPLE_RETURN: | ||
| 2325 | case EH_RETURN: | ||
| 2326 | return true; | ||
| 2327 | |||
| 2328 | @@ -1200,7 +1203,7 @@ delete_related_insns (rtx insn) | ||
| 2329 | /* If deleting a jump, decrement the count of the label, | ||
| 2330 | and delete the label if it is now unused. */ | ||
| 2331 | |||
| 2332 | - if (JUMP_P (insn) && JUMP_LABEL (insn)) | ||
| 2333 | + if (JUMP_P (insn) && JUMP_LABEL (insn) && !ANY_RETURN_P (JUMP_LABEL (insn))) | ||
| 2334 | { | ||
| 2335 | rtx lab = JUMP_LABEL (insn), lab_next; | ||
| 2336 | |||
| 2337 | @@ -1331,6 +1334,18 @@ delete_for_peephole (rtx from, rtx to) | ||
| 2338 | is also an unconditional jump in that case. */ | ||
| 2339 | } | ||
| 2340 | |||
| 2341 | +/* A helper function for redirect_exp_1; examines its input X and returns | ||
| 2342 | + either a LABEL_REF around a label, or a RETURN if X was NULL. */ | ||
| 2343 | +static rtx | ||
| 2344 | +redirect_target (rtx x) | ||
| 2345 | +{ | ||
| 2346 | + if (x == NULL_RTX) | ||
| 2347 | + return ret_rtx; | ||
| 2348 | + if (!ANY_RETURN_P (x)) | ||
| 2349 | + return gen_rtx_LABEL_REF (Pmode, x); | ||
| 2350 | + return x; | ||
| 2351 | +} | ||
| 2352 | + | ||
| 2353 | /* Throughout LOC, redirect OLABEL to NLABEL. Treat null OLABEL or | ||
| 2354 | NLABEL as a return. Accrue modifications into the change group. */ | ||
| 2355 | |||
| 2356 | @@ -1342,37 +1357,19 @@ redirect_exp_1 (rtx *loc, rtx olabel, rt | ||
| 2357 | int i; | ||
| 2358 | const char *fmt; | ||
| 2359 | |||
| 2360 | - if (code == LABEL_REF) | ||
| 2361 | - { | ||
| 2362 | - if (XEXP (x, 0) == olabel) | ||
| 2363 | - { | ||
| 2364 | - rtx n; | ||
| 2365 | - if (nlabel) | ||
| 2366 | - n = gen_rtx_LABEL_REF (Pmode, nlabel); | ||
| 2367 | - else | ||
| 2368 | - n = gen_rtx_RETURN (VOIDmode); | ||
| 2369 | - | ||
| 2370 | - validate_change (insn, loc, n, 1); | ||
| 2371 | - return; | ||
| 2372 | - } | ||
| 2373 | - } | ||
| 2374 | - else if (code == RETURN && olabel == 0) | ||
| 2375 | + if ((code == LABEL_REF && XEXP (x, 0) == olabel) | ||
| 2376 | + || x == olabel) | ||
| 2377 | { | ||
| 2378 | - if (nlabel) | ||
| 2379 | - x = gen_rtx_LABEL_REF (Pmode, nlabel); | ||
| 2380 | - else | ||
| 2381 | - x = gen_rtx_RETURN (VOIDmode); | ||
| 2382 | - if (loc == &PATTERN (insn)) | ||
| 2383 | - x = gen_rtx_SET (VOIDmode, pc_rtx, x); | ||
| 2384 | - validate_change (insn, loc, x, 1); | ||
| 2385 | + validate_change (insn, loc, redirect_target (nlabel), 1); | ||
| 2386 | return; | ||
| 2387 | } | ||
| 2388 | |||
| 2389 | - if (code == SET && nlabel == 0 && SET_DEST (x) == pc_rtx | ||
| 2390 | + if (code == SET && SET_DEST (x) == pc_rtx | ||
| 2391 | + && ANY_RETURN_P (nlabel) | ||
| 2392 | && GET_CODE (SET_SRC (x)) == LABEL_REF | ||
| 2393 | && XEXP (SET_SRC (x), 0) == olabel) | ||
| 2394 | { | ||
| 2395 | - validate_change (insn, loc, gen_rtx_RETURN (VOIDmode), 1); | ||
| 2396 | + validate_change (insn, loc, nlabel, 1); | ||
| 2397 | return; | ||
| 2398 | } | ||
| 2399 | |||
| 2400 | @@ -1409,6 +1406,7 @@ redirect_jump_1 (rtx jump, rtx nlabel) | ||
| 2401 | int ochanges = num_validated_changes (); | ||
| 2402 | rtx *loc, asmop; | ||
| 2403 | |||
| 2404 | + gcc_assert (nlabel); | ||
| 2405 | asmop = extract_asm_operands (PATTERN (jump)); | ||
| 2406 | if (asmop) | ||
| 2407 | { | ||
| 2408 | @@ -1430,17 +1428,20 @@ redirect_jump_1 (rtx jump, rtx nlabel) | ||
| 2409 | jump target label is unused as a result, it and the code following | ||
| 2410 | it may be deleted. | ||
| 2411 | |||
| 2412 | - If NLABEL is zero, we are to turn the jump into a (possibly conditional) | ||
| 2413 | - RETURN insn. | ||
| 2414 | + Normally, NLABEL will be a label, but it may also be a RETURN or | ||
| 2415 | + SIMPLE_RETURN rtx; in that case we are to turn the jump into a | ||
| 2416 | + (possibly conditional) return insn. | ||
| 2417 | |||
| 2418 | The return value will be 1 if the change was made, 0 if it wasn't | ||
| 2419 | - (this can only occur for NLABEL == 0). */ | ||
| 2420 | + (this can only occur when trying to produce return insns). */ | ||
| 2421 | |||
| 2422 | int | ||
| 2423 | redirect_jump (rtx jump, rtx nlabel, int delete_unused) | ||
| 2424 | { | ||
| 2425 | rtx olabel = JUMP_LABEL (jump); | ||
| 2426 | |||
| 2427 | + gcc_assert (nlabel != NULL_RTX); | ||
| 2428 | + | ||
| 2429 | if (nlabel == olabel) | ||
| 2430 | return 1; | ||
| 2431 | |||
| 2432 | @@ -1452,7 +1453,7 @@ redirect_jump (rtx jump, rtx nlabel, int | ||
| 2433 | } | ||
| 2434 | |||
| 2435 | /* Fix up JUMP_LABEL and label ref counts after OLABEL has been replaced with | ||
| 2436 | - NLABEL in JUMP. | ||
| 2437 | + NEW_DEST in JUMP. | ||
| 2438 | If DELETE_UNUSED is positive, delete related insn to OLABEL if its ref | ||
| 2439 | count has dropped to zero. */ | ||
| 2440 | void | ||
| 2441 | @@ -1468,13 +1469,14 @@ redirect_jump_2 (rtx jump, rtx olabel, r | ||
| 2442 | about this. */ | ||
| 2443 | gcc_assert (delete_unused >= 0); | ||
| 2444 | JUMP_LABEL (jump) = nlabel; | ||
| 2445 | - if (nlabel) | ||
| 2446 | + if (nlabel && !ANY_RETURN_P (nlabel)) | ||
| 2447 | ++LABEL_NUSES (nlabel); | ||
| 2448 | |||
| 2449 | /* Update labels in any REG_EQUAL note. */ | ||
| 2450 | if ((note = find_reg_note (jump, REG_EQUAL, NULL_RTX)) != NULL_RTX) | ||
| 2451 | { | ||
| 2452 | - if (!nlabel || (invert && !invert_exp_1 (XEXP (note, 0), jump))) | ||
| 2453 | + if (ANY_RETURN_P (nlabel) | ||
| 2454 | + || (invert && !invert_exp_1 (XEXP (note, 0), jump))) | ||
| 2455 | remove_note (jump, note); | ||
| 2456 | else | ||
| 2457 | { | ||
| 2458 | @@ -1483,7 +1485,8 @@ redirect_jump_2 (rtx jump, rtx olabel, r | ||
| 2459 | } | ||
| 2460 | } | ||
| 2461 | |||
| 2462 | - if (olabel && --LABEL_NUSES (olabel) == 0 && delete_unused > 0 | ||
| 2463 | + if (olabel && !ANY_RETURN_P (olabel) | ||
| 2464 | + && --LABEL_NUSES (olabel) == 0 && delete_unused > 0 | ||
| 2465 | /* Undefined labels will remain outside the insn stream. */ | ||
| 2466 | && INSN_UID (olabel)) | ||
| 2467 | delete_related_insns (olabel); | ||
| 2468 | Index: gcc-4_5-branch/gcc/opts.c | ||
| 2469 | =================================================================== | ||
| 2470 | --- gcc-4_5-branch.orig/gcc/opts.c | ||
| 2471 | +++ gcc-4_5-branch/gcc/opts.c | ||
| 2472 | @@ -909,6 +909,7 @@ decode_options (unsigned int argc, const | ||
| 2473 | flag_ipa_cp = opt2; | ||
| 2474 | flag_ipa_sra = opt2; | ||
| 2475 | flag_ee = opt2; | ||
| 2476 | + flag_shrink_wrap = opt2; | ||
| 2477 | |||
| 2478 | /* Track fields in field-sensitive alias analysis. */ | ||
| 2479 | set_param_value ("max-fields-for-field-sensitive", | ||
| 2480 | Index: gcc-4_5-branch/gcc/print-rtl.c | ||
| 2481 | =================================================================== | ||
| 2482 | --- gcc-4_5-branch.orig/gcc/print-rtl.c | ||
| 2483 | +++ gcc-4_5-branch/gcc/print-rtl.c | ||
| 2484 | @@ -308,9 +308,16 @@ print_rtx (const_rtx in_rtx) | ||
| 2485 | } | ||
| 2486 | } | ||
| 2487 | else if (i == 8 && JUMP_P (in_rtx) && JUMP_LABEL (in_rtx) != NULL) | ||
| 2488 | - /* Output the JUMP_LABEL reference. */ | ||
| 2489 | - fprintf (outfile, "\n%s%*s -> %d", print_rtx_head, indent * 2, "", | ||
| 2490 | - INSN_UID (JUMP_LABEL (in_rtx))); | ||
| 2491 | + { | ||
| 2492 | + /* Output the JUMP_LABEL reference. */ | ||
| 2493 | + fprintf (outfile, "\n%s%*s -> ", print_rtx_head, indent * 2, ""); | ||
| 2494 | + if (GET_CODE (JUMP_LABEL (in_rtx)) == RETURN) | ||
| 2495 | + fprintf (outfile, "return"); | ||
| 2496 | + else if (GET_CODE (JUMP_LABEL (in_rtx)) == SIMPLE_RETURN) | ||
| 2497 | + fprintf (outfile, "simple_return"); | ||
| 2498 | + else | ||
| 2499 | + fprintf (outfile, "%d", INSN_UID (JUMP_LABEL (in_rtx))); | ||
| 2500 | + } | ||
| 2501 | else if (i == 0 && GET_CODE (in_rtx) == VALUE) | ||
| 2502 | { | ||
| 2503 | #ifndef GENERATOR_FILE | ||
| 2504 | Index: gcc-4_5-branch/gcc/reorg.c | ||
| 2505 | =================================================================== | ||
| 2506 | --- gcc-4_5-branch.orig/gcc/reorg.c | ||
| 2507 | +++ gcc-4_5-branch/gcc/reorg.c | ||
| 2508 | @@ -161,8 +161,11 @@ static rtx *unfilled_firstobj; | ||
| 2509 | #define unfilled_slots_next \ | ||
| 2510 | ((rtx *) obstack_next_free (&unfilled_slots_obstack)) | ||
| 2511 | |||
| 2512 | -/* Points to the label before the end of the function. */ | ||
| 2513 | -static rtx end_of_function_label; | ||
| 2514 | +/* Points to the label before the end of the function, or before a | ||
| 2515 | + return insn. */ | ||
| 2516 | +static rtx function_return_label; | ||
| 2517 | +/* Likewise for a simple_return. */ | ||
| 2518 | +static rtx function_simple_return_label; | ||
| 2519 | |||
| 2520 | /* Mapping between INSN_UID's and position in the code since INSN_UID's do | ||
| 2521 | not always monotonically increase. */ | ||
| 2522 | @@ -175,7 +178,7 @@ static int stop_search_p (rtx, int); | ||
| 2523 | static int resource_conflicts_p (struct resources *, struct resources *); | ||
| 2524 | static int insn_references_resource_p (rtx, struct resources *, bool); | ||
| 2525 | static int insn_sets_resource_p (rtx, struct resources *, bool); | ||
| 2526 | -static rtx find_end_label (void); | ||
| 2527 | +static rtx find_end_label (rtx); | ||
| 2528 | static rtx emit_delay_sequence (rtx, rtx, int); | ||
| 2529 | static rtx add_to_delay_list (rtx, rtx); | ||
| 2530 | static rtx delete_from_delay_slot (rtx); | ||
| 2531 | @@ -220,6 +223,15 @@ static void relax_delay_slots (rtx); | ||
| 2532 | static void make_return_insns (rtx); | ||
| 2533 | #endif | ||
| 2534 | |||
| 2535 | +/* Return true iff INSN is a simplejump, or any kind of return insn. */ | ||
| 2536 | + | ||
| 2537 | +static bool | ||
| 2538 | +simplejump_or_return_p (rtx insn) | ||
| 2539 | +{ | ||
| 2540 | + return (JUMP_P (insn) | ||
| 2541 | + && (simplejump_p (insn) || ANY_RETURN_P (PATTERN (insn)))); | ||
| 2542 | +} | ||
| 2543 | + | ||
| 2544 | /* Return TRUE if this insn should stop the search for insn to fill delay | ||
| 2545 | slots. LABELS_P indicates that labels should terminate the search. | ||
| 2546 | In all cases, jumps terminate the search. */ | ||
| 2547 | @@ -335,23 +347,29 @@ insn_sets_resource_p (rtx insn, struct r | ||
| 2548 | |||
| 2549 | ??? There may be a problem with the current implementation. Suppose | ||
| 2550 | we start with a bare RETURN insn and call find_end_label. It may set | ||
| 2551 | - end_of_function_label just before the RETURN. Suppose the machinery | ||
| 2552 | + function_return_label just before the RETURN. Suppose the machinery | ||
| 2553 | is able to fill the delay slot of the RETURN insn afterwards. Then | ||
| 2554 | - end_of_function_label is no longer valid according to the property | ||
| 2555 | + function_return_label is no longer valid according to the property | ||
| 2556 | described above and find_end_label will still return it unmodified. | ||
| 2557 | Note that this is probably mitigated by the following observation: | ||
| 2558 | - once end_of_function_label is made, it is very likely the target of | ||
| 2559 | + once function_return_label is made, it is very likely the target of | ||
| 2560 | a jump, so filling the delay slot of the RETURN will be much more | ||
| 2561 | difficult. */ | ||
| 2562 | |||
| 2563 | static rtx | ||
| 2564 | -find_end_label (void) | ||
| 2565 | +find_end_label (rtx kind) | ||
| 2566 | { | ||
| 2567 | rtx insn; | ||
| 2568 | + rtx *plabel; | ||
| 2569 | + | ||
| 2570 | + if (kind == ret_rtx) | ||
| 2571 | + plabel = &function_return_label; | ||
| 2572 | + else | ||
| 2573 | + plabel = &function_simple_return_label; | ||
| 2574 | |||
| 2575 | /* If we found one previously, return it. */ | ||
| 2576 | - if (end_of_function_label) | ||
| 2577 | - return end_of_function_label; | ||
| 2578 | + if (*plabel) | ||
| 2579 | + return *plabel; | ||
| 2580 | |||
| 2581 | /* Otherwise, see if there is a label at the end of the function. If there | ||
| 2582 | is, it must be that RETURN insns aren't needed, so that is our return | ||
| 2583 | @@ -366,44 +384,44 @@ find_end_label (void) | ||
| 2584 | |||
| 2585 | /* When a target threads its epilogue we might already have a | ||
| 2586 | suitable return insn. If so put a label before it for the | ||
| 2587 | - end_of_function_label. */ | ||
| 2588 | + function_return_label. */ | ||
| 2589 | if (BARRIER_P (insn) | ||
| 2590 | && JUMP_P (PREV_INSN (insn)) | ||
| 2591 | - && GET_CODE (PATTERN (PREV_INSN (insn))) == RETURN) | ||
| 2592 | + && PATTERN (PREV_INSN (insn)) == kind) | ||
| 2593 | { | ||
| 2594 | rtx temp = PREV_INSN (PREV_INSN (insn)); | ||
| 2595 | - end_of_function_label = gen_label_rtx (); | ||
| 2596 | - LABEL_NUSES (end_of_function_label) = 0; | ||
| 2597 | + rtx label = gen_label_rtx (); | ||
| 2598 | + LABEL_NUSES (label) = 0; | ||
| 2599 | |||
| 2600 | /* Put the label before an USE insns that may precede the RETURN insn. */ | ||
| 2601 | while (GET_CODE (temp) == USE) | ||
| 2602 | temp = PREV_INSN (temp); | ||
| 2603 | |||
| 2604 | - emit_label_after (end_of_function_label, temp); | ||
| 2605 | + emit_label_after (label, temp); | ||
| 2606 | + *plabel = label; | ||
| 2607 | } | ||
| 2608 | |||
| 2609 | else if (LABEL_P (insn)) | ||
| 2610 | - end_of_function_label = insn; | ||
| 2611 | + *plabel = insn; | ||
| 2612 | else | ||
| 2613 | { | ||
| 2614 | - end_of_function_label = gen_label_rtx (); | ||
| 2615 | - LABEL_NUSES (end_of_function_label) = 0; | ||
| 2616 | + rtx label = gen_label_rtx (); | ||
| 2617 | + LABEL_NUSES (label) = 0; | ||
| 2618 | /* If the basic block reorder pass moves the return insn to | ||
| 2619 | some other place try to locate it again and put our | ||
| 2620 | - end_of_function_label there. */ | ||
| 2621 | - while (insn && ! (JUMP_P (insn) | ||
| 2622 | - && (GET_CODE (PATTERN (insn)) == RETURN))) | ||
| 2623 | + function_return_label there. */ | ||
| 2624 | + while (insn && ! (JUMP_P (insn) && (PATTERN (insn) == kind))) | ||
| 2625 | insn = PREV_INSN (insn); | ||
| 2626 | if (insn) | ||
| 2627 | { | ||
| 2628 | insn = PREV_INSN (insn); | ||
| 2629 | |||
| 2630 | - /* Put the label before an USE insns that may proceed the | ||
| 2631 | + /* Put the label before an USE insns that may precede the | ||
| 2632 | RETURN insn. */ | ||
| 2633 | while (GET_CODE (insn) == USE) | ||
| 2634 | insn = PREV_INSN (insn); | ||
| 2635 | |||
| 2636 | - emit_label_after (end_of_function_label, insn); | ||
| 2637 | + emit_label_after (label, insn); | ||
| 2638 | } | ||
| 2639 | else | ||
| 2640 | { | ||
| 2641 | @@ -413,19 +431,16 @@ find_end_label (void) | ||
| 2642 | && ! HAVE_return | ||
| 2643 | #endif | ||
| 2644 | ) | ||
| 2645 | - { | ||
| 2646 | - /* The RETURN insn has its delay slot filled so we cannot | ||
| 2647 | - emit the label just before it. Since we already have | ||
| 2648 | - an epilogue and cannot emit a new RETURN, we cannot | ||
| 2649 | - emit the label at all. */ | ||
| 2650 | - end_of_function_label = NULL_RTX; | ||
| 2651 | - return end_of_function_label; | ||
| 2652 | - } | ||
| 2653 | + /* The RETURN insn has its delay slot filled so we cannot | ||
| 2654 | + emit the label just before it. Since we already have | ||
| 2655 | + an epilogue and cannot emit a new RETURN, we cannot | ||
| 2656 | + emit the label at all. */ | ||
| 2657 | + return NULL_RTX; | ||
| 2658 | #endif /* HAVE_epilogue */ | ||
| 2659 | |||
| 2660 | /* Otherwise, make a new label and emit a RETURN and BARRIER, | ||
| 2661 | if needed. */ | ||
| 2662 | - emit_label (end_of_function_label); | ||
| 2663 | + emit_label (label); | ||
| 2664 | #ifdef HAVE_return | ||
| 2665 | /* We don't bother trying to create a return insn if the | ||
| 2666 | epilogue has filled delay-slots; we would have to try and | ||
| 2667 | @@ -437,19 +452,21 @@ find_end_label (void) | ||
| 2668 | /* The return we make may have delay slots too. */ | ||
| 2669 | rtx insn = gen_return (); | ||
| 2670 | insn = emit_jump_insn (insn); | ||
| 2671 | + JUMP_LABEL (insn) = ret_rtx; | ||
| 2672 | emit_barrier (); | ||
| 2673 | if (num_delay_slots (insn) > 0) | ||
| 2674 | obstack_ptr_grow (&unfilled_slots_obstack, insn); | ||
| 2675 | } | ||
| 2676 | #endif | ||
| 2677 | } | ||
| 2678 | + *plabel = label; | ||
| 2679 | } | ||
| 2680 | |||
| 2681 | /* Show one additional use for this label so it won't go away until | ||
| 2682 | we are done. */ | ||
| 2683 | - ++LABEL_NUSES (end_of_function_label); | ||
| 2684 | + ++LABEL_NUSES (*plabel); | ||
| 2685 | |||
| 2686 | - return end_of_function_label; | ||
| 2687 | + return *plabel; | ||
| 2688 | } | ||
| 2689 | |||
| 2690 | /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace | ||
| 2691 | @@ -797,10 +814,8 @@ optimize_skip (rtx insn) | ||
| 2692 | if ((next_trial == next_active_insn (JUMP_LABEL (insn)) | ||
| 2693 | && ! (next_trial == 0 && crtl->epilogue_delay_list != 0)) | ||
| 2694 | || (next_trial != 0 | ||
| 2695 | - && JUMP_P (next_trial) | ||
| 2696 | - && JUMP_LABEL (insn) == JUMP_LABEL (next_trial) | ||
| 2697 | - && (simplejump_p (next_trial) | ||
| 2698 | - || GET_CODE (PATTERN (next_trial)) == RETURN))) | ||
| 2699 | + && simplejump_or_return_p (next_trial) | ||
| 2700 | + && JUMP_LABEL (insn) == JUMP_LABEL (next_trial))) | ||
| 2701 | { | ||
| 2702 | if (eligible_for_annul_false (insn, 0, trial, flags)) | ||
| 2703 | { | ||
| 2704 | @@ -819,13 +834,11 @@ optimize_skip (rtx insn) | ||
| 2705 | branch, thread our jump to the target of that branch. Don't | ||
| 2706 | change this into a RETURN here, because it may not accept what | ||
| 2707 | we have in the delay slot. We'll fix this up later. */ | ||
| 2708 | - if (next_trial && JUMP_P (next_trial) | ||
| 2709 | - && (simplejump_p (next_trial) | ||
| 2710 | - || GET_CODE (PATTERN (next_trial)) == RETURN)) | ||
| 2711 | + if (next_trial && simplejump_or_return_p (next_trial)) | ||
| 2712 | { | ||
| 2713 | rtx target_label = JUMP_LABEL (next_trial); | ||
| 2714 | - if (target_label == 0) | ||
| 2715 | - target_label = find_end_label (); | ||
| 2716 | + if (ANY_RETURN_P (target_label)) | ||
| 2717 | + target_label = find_end_label (target_label); | ||
| 2718 | |||
| 2719 | if (target_label) | ||
| 2720 | { | ||
| 2721 | @@ -866,7 +879,7 @@ get_jump_flags (rtx insn, rtx label) | ||
| 2722 | if (JUMP_P (insn) | ||
| 2723 | && (condjump_p (insn) || condjump_in_parallel_p (insn)) | ||
| 2724 | && INSN_UID (insn) <= max_uid | ||
| 2725 | - && label != 0 | ||
| 2726 | + && label != 0 && !ANY_RETURN_P (label) | ||
| 2727 | && INSN_UID (label) <= max_uid) | ||
| 2728 | flags | ||
| 2729 | = (uid_to_ruid[INSN_UID (label)] > uid_to_ruid[INSN_UID (insn)]) | ||
| 2730 | @@ -1038,7 +1051,7 @@ get_branch_condition (rtx insn, rtx targ | ||
| 2731 | pat = XVECEXP (pat, 0, 0); | ||
| 2732 | |||
| 2733 | if (GET_CODE (pat) == RETURN) | ||
| 2734 | - return target == 0 ? const_true_rtx : 0; | ||
| 2735 | + return ANY_RETURN_P (target) ? const_true_rtx : 0; | ||
| 2736 | |||
| 2737 | else if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx) | ||
| 2738 | return 0; | ||
| 2739 | @@ -1318,7 +1331,11 @@ steal_delay_list_from_target (rtx insn, | ||
| 2740 | } | ||
| 2741 | |||
| 2742 | /* Show the place to which we will be branching. */ | ||
| 2743 | - *pnew_thread = next_active_insn (JUMP_LABEL (XVECEXP (seq, 0, 0))); | ||
| 2744 | + temp = JUMP_LABEL (XVECEXP (seq, 0, 0)); | ||
| 2745 | + if (ANY_RETURN_P (temp)) | ||
| 2746 | + *pnew_thread = temp; | ||
| 2747 | + else | ||
| 2748 | + *pnew_thread = next_active_insn (temp); | ||
| 2749 | |||
| 2750 | /* Add any new insns to the delay list and update the count of the | ||
| 2751 | number of slots filled. */ | ||
| 2752 | @@ -1358,8 +1375,7 @@ steal_delay_list_from_fallthrough (rtx i | ||
| 2753 | /* We can't do anything if SEQ's delay insn isn't an | ||
| 2754 | unconditional branch. */ | ||
| 2755 | |||
| 2756 | - if (! simplejump_p (XVECEXP (seq, 0, 0)) | ||
| 2757 | - && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) != RETURN) | ||
| 2758 | + if (! simplejump_or_return_p (XVECEXP (seq, 0, 0))) | ||
| 2759 | return delay_list; | ||
| 2760 | |||
| 2761 | for (i = 1; i < XVECLEN (seq, 0); i++) | ||
| 2762 | @@ -1827,7 +1843,7 @@ own_thread_p (rtx thread, rtx label, int | ||
| 2763 | rtx insn; | ||
| 2764 | |||
| 2765 | /* We don't own the function end. */ | ||
| 2766 | - if (thread == 0) | ||
| 2767 | + if (ANY_RETURN_P (thread)) | ||
| 2768 | return 0; | ||
| 2769 | |||
| 2770 | /* Get the first active insn, or THREAD, if it is an active insn. */ | ||
| 2771 | @@ -2245,7 +2261,8 @@ fill_simple_delay_slots (int non_jumps_p | ||
| 2772 | && (!JUMP_P (insn) | ||
| 2773 | || ((condjump_p (insn) || condjump_in_parallel_p (insn)) | ||
| 2774 | && ! simplejump_p (insn) | ||
| 2775 | - && JUMP_LABEL (insn) != 0))) | ||
| 2776 | + && JUMP_LABEL (insn) != 0 | ||
| 2777 | + && !ANY_RETURN_P (JUMP_LABEL (insn))))) | ||
| 2778 | { | ||
| 2779 | /* Invariant: If insn is a JUMP_INSN, the insn's jump | ||
| 2780 | label. Otherwise, zero. */ | ||
| 2781 | @@ -2270,7 +2287,7 @@ fill_simple_delay_slots (int non_jumps_p | ||
| 2782 | target = JUMP_LABEL (insn); | ||
| 2783 | } | ||
| 2784 | |||
| 2785 | - if (target == 0) | ||
| 2786 | + if (target == 0 || ANY_RETURN_P (target)) | ||
| 2787 | for (trial = next_nonnote_insn (insn); trial; trial = next_trial) | ||
| 2788 | { | ||
| 2789 | next_trial = next_nonnote_insn (trial); | ||
| 2790 | @@ -2349,6 +2366,7 @@ fill_simple_delay_slots (int non_jumps_p | ||
| 2791 | && JUMP_P (trial) | ||
| 2792 | && simplejump_p (trial) | ||
| 2793 | && (target == 0 || JUMP_LABEL (trial) == target) | ||
| 2794 | + && !ANY_RETURN_P (JUMP_LABEL (trial)) | ||
| 2795 | && (next_trial = next_active_insn (JUMP_LABEL (trial))) != 0 | ||
| 2796 | && ! (NONJUMP_INSN_P (next_trial) | ||
| 2797 | && GET_CODE (PATTERN (next_trial)) == SEQUENCE) | ||
| 2798 | @@ -2371,7 +2389,7 @@ fill_simple_delay_slots (int non_jumps_p | ||
| 2799 | if (new_label != 0) | ||
| 2800 | new_label = get_label_before (new_label); | ||
| 2801 | else | ||
| 2802 | - new_label = find_end_label (); | ||
| 2803 | + new_label = find_end_label (simple_return_rtx); | ||
| 2804 | |||
| 2805 | if (new_label) | ||
| 2806 | { | ||
| 2807 | @@ -2503,7 +2521,8 @@ fill_simple_delay_slots (int non_jumps_p | ||
| 2808 | |||
| 2809 | /* Follow any unconditional jump at LABEL; | ||
| 2810 | return the ultimate label reached by any such chain of jumps. | ||
| 2811 | - Return null if the chain ultimately leads to a return instruction. | ||
| 2812 | + Return a suitable return rtx if the chain ultimately leads to a | ||
| 2813 | + return instruction. | ||
| 2814 | If LABEL is not followed by a jump, return LABEL. | ||
| 2815 | If the chain loops or we can't find end, return LABEL, | ||
| 2816 | since that tells caller to avoid changing the insn. */ | ||
| 2817 | @@ -2518,6 +2537,7 @@ follow_jumps (rtx label) | ||
| 2818 | |||
| 2819 | for (depth = 0; | ||
| 2820 | (depth < 10 | ||
| 2821 | + && !ANY_RETURN_P (value) | ||
| 2822 | && (insn = next_active_insn (value)) != 0 | ||
| 2823 | && JUMP_P (insn) | ||
| 2824 | && ((JUMP_LABEL (insn) != 0 && any_uncondjump_p (insn) | ||
| 2825 | @@ -2527,18 +2547,22 @@ follow_jumps (rtx label) | ||
| 2826 | && BARRIER_P (next)); | ||
| 2827 | depth++) | ||
| 2828 | { | ||
| 2829 | - rtx tem; | ||
| 2830 | + rtx this_label = JUMP_LABEL (insn); | ||
| 2831 | |||
| 2832 | /* If we have found a cycle, make the insn jump to itself. */ | ||
| 2833 | - if (JUMP_LABEL (insn) == label) | ||
| 2834 | + if (this_label == label) | ||
| 2835 | return label; | ||
| 2836 | |||
| 2837 | - tem = next_active_insn (JUMP_LABEL (insn)); | ||
| 2838 | - if (tem && (GET_CODE (PATTERN (tem)) == ADDR_VEC | ||
| 2839 | + if (!ANY_RETURN_P (this_label)) | ||
| 2840 | + { | ||
| 2841 | + rtx tem = next_active_insn (this_label); | ||
| 2842 | + if (tem | ||
| 2843 | + && (GET_CODE (PATTERN (tem)) == ADDR_VEC | ||
| 2844 | || GET_CODE (PATTERN (tem)) == ADDR_DIFF_VEC)) | ||
| 2845 | - break; | ||
| 2846 | + break; | ||
| 2847 | + } | ||
| 2848 | |||
| 2849 | - value = JUMP_LABEL (insn); | ||
| 2850 | + value = this_label; | ||
| 2851 | } | ||
| 2852 | if (depth == 10) | ||
| 2853 | return label; | ||
| 2854 | @@ -2901,6 +2925,7 @@ fill_slots_from_thread (rtx insn, rtx co | ||
| 2855 | arithmetic insn after the jump insn and put the arithmetic insn in the | ||
| 2856 | delay slot. If we can't do this, return. */ | ||
| 2857 | if (delay_list == 0 && likely && new_thread | ||
| 2858 | + && !ANY_RETURN_P (new_thread) | ||
| 2859 | && NONJUMP_INSN_P (new_thread) | ||
| 2860 | && GET_CODE (PATTERN (new_thread)) != ASM_INPUT | ||
| 2861 | && asm_noperands (PATTERN (new_thread)) < 0) | ||
| 2862 | @@ -2985,16 +3010,14 @@ fill_slots_from_thread (rtx insn, rtx co | ||
| 2863 | |||
| 2864 | gcc_assert (thread_if_true); | ||
| 2865 | |||
| 2866 | - if (new_thread && JUMP_P (new_thread) | ||
| 2867 | - && (simplejump_p (new_thread) | ||
| 2868 | - || GET_CODE (PATTERN (new_thread)) == RETURN) | ||
| 2869 | + if (new_thread && simplejump_or_return_p (new_thread) | ||
| 2870 | && redirect_with_delay_list_safe_p (insn, | ||
| 2871 | JUMP_LABEL (new_thread), | ||
| 2872 | delay_list)) | ||
| 2873 | new_thread = follow_jumps (JUMP_LABEL (new_thread)); | ||
| 2874 | |||
| 2875 | - if (new_thread == 0) | ||
| 2876 | - label = find_end_label (); | ||
| 2877 | + if (ANY_RETURN_P (new_thread)) | ||
| 2878 | + label = find_end_label (new_thread); | ||
| 2879 | else if (LABEL_P (new_thread)) | ||
| 2880 | label = new_thread; | ||
| 2881 | else | ||
| 2882 | @@ -3340,11 +3363,12 @@ relax_delay_slots (rtx first) | ||
| 2883 | group of consecutive labels. */ | ||
| 2884 | if (JUMP_P (insn) | ||
| 2885 | && (condjump_p (insn) || condjump_in_parallel_p (insn)) | ||
| 2886 | - && (target_label = JUMP_LABEL (insn)) != 0) | ||
| 2887 | + && (target_label = JUMP_LABEL (insn)) != 0 | ||
| 2888 | + && !ANY_RETURN_P (target_label)) | ||
| 2889 | { | ||
| 2890 | target_label = skip_consecutive_labels (follow_jumps (target_label)); | ||
| 2891 | - if (target_label == 0) | ||
| 2892 | - target_label = find_end_label (); | ||
| 2893 | + if (ANY_RETURN_P (target_label)) | ||
| 2894 | + target_label = find_end_label (target_label); | ||
| 2895 | |||
| 2896 | if (target_label && next_active_insn (target_label) == next | ||
| 2897 | && ! condjump_in_parallel_p (insn)) | ||
| 2898 | @@ -3359,9 +3383,8 @@ relax_delay_slots (rtx first) | ||
| 2899 | /* See if this jump conditionally branches around an unconditional | ||
| 2900 | jump. If so, invert this jump and point it to the target of the | ||
| 2901 | second jump. */ | ||
| 2902 | - if (next && JUMP_P (next) | ||
| 2903 | + if (next && simplejump_or_return_p (next) | ||
| 2904 | && any_condjump_p (insn) | ||
| 2905 | - && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN) | ||
| 2906 | && target_label | ||
| 2907 | && next_active_insn (target_label) == next_active_insn (next) | ||
| 2908 | && no_labels_between_p (insn, next)) | ||
| 2909 | @@ -3403,8 +3426,7 @@ relax_delay_slots (rtx first) | ||
| 2910 | Don't do this if we expect the conditional branch to be true, because | ||
| 2911 | we would then be making the more common case longer. */ | ||
| 2912 | |||
| 2913 | - if (JUMP_P (insn) | ||
| 2914 | - && (simplejump_p (insn) || GET_CODE (PATTERN (insn)) == RETURN) | ||
| 2915 | + if (simplejump_or_return_p (insn) | ||
| 2916 | && (other = prev_active_insn (insn)) != 0 | ||
| 2917 | && any_condjump_p (other) | ||
| 2918 | && no_labels_between_p (other, insn) | ||
| 2919 | @@ -3445,10 +3467,10 @@ relax_delay_slots (rtx first) | ||
| 2920 | Only do so if optimizing for size since this results in slower, but | ||
| 2921 | smaller code. */ | ||
| 2922 | if (optimize_function_for_size_p (cfun) | ||
| 2923 | - && GET_CODE (PATTERN (delay_insn)) == RETURN | ||
| 2924 | + && ANY_RETURN_P (PATTERN (delay_insn)) | ||
| 2925 | && next | ||
| 2926 | && JUMP_P (next) | ||
| 2927 | - && GET_CODE (PATTERN (next)) == RETURN) | ||
| 2928 | + && PATTERN (next) == PATTERN (delay_insn)) | ||
| 2929 | { | ||
| 2930 | rtx after; | ||
| 2931 | int i; | ||
| 2932 | @@ -3487,14 +3509,16 @@ relax_delay_slots (rtx first) | ||
| 2933 | continue; | ||
| 2934 | |||
| 2935 | target_label = JUMP_LABEL (delay_insn); | ||
| 2936 | + if (target_label && ANY_RETURN_P (target_label)) | ||
| 2937 | + continue; | ||
| 2938 | |||
| 2939 | if (target_label) | ||
| 2940 | { | ||
| 2941 | /* If this jump goes to another unconditional jump, thread it, but | ||
| 2942 | don't convert a jump into a RETURN here. */ | ||
| 2943 | trial = skip_consecutive_labels (follow_jumps (target_label)); | ||
| 2944 | - if (trial == 0) | ||
| 2945 | - trial = find_end_label (); | ||
| 2946 | + if (ANY_RETURN_P (trial)) | ||
| 2947 | + trial = find_end_label (trial); | ||
| 2948 | |||
| 2949 | if (trial && trial != target_label | ||
| 2950 | && redirect_with_delay_slots_safe_p (delay_insn, trial, insn)) | ||
| 2951 | @@ -3517,7 +3541,7 @@ relax_delay_slots (rtx first) | ||
| 2952 | later incorrectly compute register live/death info. */ | ||
| 2953 | rtx tmp = next_active_insn (trial); | ||
| 2954 | if (tmp == 0) | ||
| 2955 | - tmp = find_end_label (); | ||
| 2956 | + tmp = find_end_label (simple_return_rtx); | ||
| 2957 | |||
| 2958 | if (tmp) | ||
| 2959 | { | ||
| 2960 | @@ -3537,14 +3561,12 @@ relax_delay_slots (rtx first) | ||
| 2961 | delay list and that insn is redundant, thread the jump. */ | ||
| 2962 | if (trial && GET_CODE (PATTERN (trial)) == SEQUENCE | ||
| 2963 | && XVECLEN (PATTERN (trial), 0) == 2 | ||
| 2964 | - && JUMP_P (XVECEXP (PATTERN (trial), 0, 0)) | ||
| 2965 | - && (simplejump_p (XVECEXP (PATTERN (trial), 0, 0)) | ||
| 2966 | - || GET_CODE (PATTERN (XVECEXP (PATTERN (trial), 0, 0))) == RETURN) | ||
| 2967 | + && simplejump_or_return_p (XVECEXP (PATTERN (trial), 0, 0)) | ||
| 2968 | && redundant_insn (XVECEXP (PATTERN (trial), 0, 1), insn, 0)) | ||
| 2969 | { | ||
| 2970 | target_label = JUMP_LABEL (XVECEXP (PATTERN (trial), 0, 0)); | ||
| 2971 | - if (target_label == 0) | ||
| 2972 | - target_label = find_end_label (); | ||
| 2973 | + if (ANY_RETURN_P (target_label)) | ||
| 2974 | + target_label = find_end_label (target_label); | ||
| 2975 | |||
| 2976 | if (target_label | ||
| 2977 | && redirect_with_delay_slots_safe_p (delay_insn, target_label, | ||
| 2978 | @@ -3622,16 +3644,15 @@ relax_delay_slots (rtx first) | ||
| 2979 | a RETURN here. */ | ||
| 2980 | if (! INSN_ANNULLED_BRANCH_P (delay_insn) | ||
| 2981 | && any_condjump_p (delay_insn) | ||
| 2982 | - && next && JUMP_P (next) | ||
| 2983 | - && (simplejump_p (next) || GET_CODE (PATTERN (next)) == RETURN) | ||
| 2984 | + && next && simplejump_or_return_p (next) | ||
| 2985 | && next_active_insn (target_label) == next_active_insn (next) | ||
| 2986 | && no_labels_between_p (insn, next)) | ||
| 2987 | { | ||
| 2988 | rtx label = JUMP_LABEL (next); | ||
| 2989 | rtx old_label = JUMP_LABEL (delay_insn); | ||
| 2990 | |||
| 2991 | - if (label == 0) | ||
| 2992 | - label = find_end_label (); | ||
| 2993 | + if (ANY_RETURN_P (label)) | ||
| 2994 | + label = find_end_label (label); | ||
| 2995 | |||
| 2996 | /* find_end_label can generate a new label. Check this first. */ | ||
| 2997 | if (label | ||
| 2998 | @@ -3692,7 +3713,8 @@ static void | ||
| 2999 | make_return_insns (rtx first) | ||
| 3000 | { | ||
| 3001 | rtx insn, jump_insn, pat; | ||
| 3002 | - rtx real_return_label = end_of_function_label; | ||
| 3003 | + rtx real_return_label = function_return_label; | ||
| 3004 | + rtx real_simple_return_label = function_simple_return_label; | ||
| 3005 | int slots, i; | ||
| 3006 | |||
| 3007 | #ifdef DELAY_SLOTS_FOR_EPILOGUE | ||
| 3008 | @@ -3707,18 +3729,25 @@ make_return_insns (rtx first) | ||
| 3009 | #endif | ||
| 3010 | |||
| 3011 | /* See if there is a RETURN insn in the function other than the one we | ||
| 3012 | - made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change | ||
| 3013 | + made for FUNCTION_RETURN_LABEL. If so, set up anything we can't change | ||
| 3014 | into a RETURN to jump to it. */ | ||
| 3015 | for (insn = first; insn; insn = NEXT_INSN (insn)) | ||
| 3016 | - if (JUMP_P (insn) && GET_CODE (PATTERN (insn)) == RETURN) | ||
| 3017 | + if (JUMP_P (insn) && ANY_RETURN_P (PATTERN (insn))) | ||
| 3018 | { | ||
| 3019 | - real_return_label = get_label_before (insn); | ||
| 3020 | + rtx t = get_label_before (insn); | ||
| 3021 | + if (PATTERN (insn) == ret_rtx) | ||
| 3022 | + real_return_label = t; | ||
| 3023 | + else | ||
| 3024 | + real_simple_return_label = t; | ||
| 3025 | break; | ||
| 3026 | } | ||
| 3027 | |||
| 3028 | /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it | ||
| 3029 | - was equal to END_OF_FUNCTION_LABEL. */ | ||
| 3030 | - LABEL_NUSES (real_return_label)++; | ||
| 3031 | + was equal to FUNCTION_RETURN_LABEL. */ | ||
| 3032 | + if (real_return_label) | ||
| 3033 | + LABEL_NUSES (real_return_label)++; | ||
| 3034 | + if (real_simple_return_label) | ||
| 3035 | + LABEL_NUSES (real_simple_return_label)++; | ||
| 3036 | |||
| 3037 | /* Clear the list of insns to fill so we can use it. */ | ||
| 3038 | obstack_free (&unfilled_slots_obstack, unfilled_firstobj); | ||
| 3039 | @@ -3726,13 +3755,27 @@ make_return_insns (rtx first) | ||
| 3040 | for (insn = first; insn; insn = NEXT_INSN (insn)) | ||
| 3041 | { | ||
| 3042 | int flags; | ||
| 3043 | + rtx kind, real_label; | ||
| 3044 | |||
| 3045 | /* Only look at filled JUMP_INSNs that go to the end of function | ||
| 3046 | label. */ | ||
| 3047 | if (!NONJUMP_INSN_P (insn) | ||
| 3048 | || GET_CODE (PATTERN (insn)) != SEQUENCE | ||
| 3049 | - || !JUMP_P (XVECEXP (PATTERN (insn), 0, 0)) | ||
| 3050 | - || JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) != end_of_function_label) | ||
| 3051 | + || !JUMP_P (XVECEXP (PATTERN (insn), 0, 0))) | ||
| 3052 | + continue; | ||
| 3053 | + | ||
| 3054 | + if (JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) == function_return_label) | ||
| 3055 | + { | ||
| 3056 | + kind = ret_rtx; | ||
| 3057 | + real_label = real_return_label; | ||
| 3058 | + } | ||
| 3059 | + else if (JUMP_LABEL (XVECEXP (PATTERN (insn), 0, 0)) | ||
| 3060 | + == function_simple_return_label) | ||
| 3061 | + { | ||
| 3062 | + kind = simple_return_rtx; | ||
| 3063 | + real_label = real_simple_return_label; | ||
| 3064 | + } | ||
| 3065 | + else | ||
| 3066 | continue; | ||
| 3067 | |||
| 3068 | pat = PATTERN (insn); | ||
| 3069 | @@ -3740,14 +3783,12 @@ make_return_insns (rtx first) | ||
| 3070 | |||
| 3071 | /* If we can't make the jump into a RETURN, try to redirect it to the best | ||
| 3072 | RETURN and go on to the next insn. */ | ||
| 3073 | - if (! reorg_redirect_jump (jump_insn, NULL_RTX)) | ||
| 3074 | + if (! reorg_redirect_jump (jump_insn, kind)) | ||
| 3075 | { | ||
| 3076 | /* Make sure redirecting the jump will not invalidate the delay | ||
| 3077 | slot insns. */ | ||
| 3078 | - if (redirect_with_delay_slots_safe_p (jump_insn, | ||
| 3079 | - real_return_label, | ||
| 3080 | - insn)) | ||
| 3081 | - reorg_redirect_jump (jump_insn, real_return_label); | ||
| 3082 | + if (redirect_with_delay_slots_safe_p (jump_insn, real_label, insn)) | ||
| 3083 | + reorg_redirect_jump (jump_insn, real_label); | ||
| 3084 | continue; | ||
| 3085 | } | ||
| 3086 | |||
| 3087 | @@ -3787,7 +3828,7 @@ make_return_insns (rtx first) | ||
| 3088 | RETURN, delete the SEQUENCE and output the individual insns, | ||
| 3089 | followed by the RETURN. Then set things up so we try to find | ||
| 3090 | insns for its delay slots, if it needs some. */ | ||
| 3091 | - if (GET_CODE (PATTERN (jump_insn)) == RETURN) | ||
| 3092 | + if (ANY_RETURN_P (PATTERN (jump_insn))) | ||
| 3093 | { | ||
| 3094 | rtx prev = PREV_INSN (insn); | ||
| 3095 | |||
| 3096 | @@ -3804,13 +3845,16 @@ make_return_insns (rtx first) | ||
| 3097 | else | ||
| 3098 | /* It is probably more efficient to keep this with its current | ||
| 3099 | delay slot as a branch to a RETURN. */ | ||
| 3100 | - reorg_redirect_jump (jump_insn, real_return_label); | ||
| 3101 | + reorg_redirect_jump (jump_insn, real_label); | ||
| 3102 | } | ||
| 3103 | |||
| 3104 | /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any | ||
| 3105 | new delay slots we have created. */ | ||
| 3106 | - if (--LABEL_NUSES (real_return_label) == 0) | ||
| 3107 | + if (real_return_label != NULL_RTX && --LABEL_NUSES (real_return_label) == 0) | ||
| 3108 | delete_related_insns (real_return_label); | ||
| 3109 | + if (real_simple_return_label != NULL_RTX | ||
| 3110 | + && --LABEL_NUSES (real_simple_return_label) == 0) | ||
| 3111 | + delete_related_insns (real_simple_return_label); | ||
| 3112 | |||
| 3113 | fill_simple_delay_slots (1); | ||
| 3114 | fill_simple_delay_slots (0); | ||
| 3115 | @@ -3878,7 +3922,7 @@ dbr_schedule (rtx first) | ||
| 3116 | init_resource_info (epilogue_insn); | ||
| 3117 | |||
| 3118 | /* Show we haven't computed an end-of-function label yet. */ | ||
| 3119 | - end_of_function_label = 0; | ||
| 3120 | + function_return_label = function_simple_return_label = NULL_RTX; | ||
| 3121 | |||
| 3122 | /* Initialize the statistics for this function. */ | ||
| 3123 | memset (num_insns_needing_delays, 0, sizeof num_insns_needing_delays); | ||
| 3124 | @@ -3900,11 +3944,23 @@ dbr_schedule (rtx first) | ||
| 3125 | /* If we made an end of function label, indicate that it is now | ||
| 3126 | safe to delete it by undoing our prior adjustment to LABEL_NUSES. | ||
| 3127 | If it is now unused, delete it. */ | ||
| 3128 | - if (end_of_function_label && --LABEL_NUSES (end_of_function_label) == 0) | ||
| 3129 | - delete_related_insns (end_of_function_label); | ||
| 3130 | + if (function_return_label && --LABEL_NUSES (function_return_label) == 0) | ||
| 3131 | + delete_related_insns (function_return_label); | ||
| 3132 | + if (function_simple_return_label | ||
| 3133 | + && --LABEL_NUSES (function_simple_return_label) == 0) | ||
| 3134 | + delete_related_insns (function_simple_return_label); | ||
| 3135 | |||
| 3136 | +#if defined HAVE_return || defined HAVE_simple_return | ||
| 3137 | + if ( | ||
| 3138 | #ifdef HAVE_return | ||
| 3139 | - if (HAVE_return && end_of_function_label != 0) | ||
| 3140 | + (HAVE_return && function_return_label != 0) | ||
| 3141 | +#else | ||
| 3142 | + 0 | ||
| 3143 | +#endif | ||
| 3144 | +#ifdef HAVE_simple_return | ||
| 3145 | + || (HAVE_simple_return && function_simple_return_label != 0) | ||
| 3146 | +#endif | ||
| 3147 | + ) | ||
| 3148 | make_return_insns (first); | ||
| 3149 | #endif | ||
| 3150 | |||
| 3151 | Index: gcc-4_5-branch/gcc/resource.c | ||
| 3152 | =================================================================== | ||
| 3153 | --- gcc-4_5-branch.orig/gcc/resource.c | ||
| 3154 | +++ gcc-4_5-branch/gcc/resource.c | ||
| 3155 | @@ -495,6 +495,8 @@ find_dead_or_set_registers (rtx target, | ||
| 3156 | || GET_CODE (PATTERN (this_jump_insn)) == RETURN) | ||
| 3157 | { | ||
| 3158 | next = JUMP_LABEL (this_jump_insn); | ||
| 3159 | + if (next && ANY_RETURN_P (next)) | ||
| 3160 | + next = NULL_RTX; | ||
| 3161 | if (jump_insn == 0) | ||
| 3162 | { | ||
| 3163 | jump_insn = insn; | ||
| 3164 | @@ -562,9 +564,10 @@ find_dead_or_set_registers (rtx target, | ||
| 3165 | AND_COMPL_HARD_REG_SET (scratch, needed.regs); | ||
| 3166 | AND_COMPL_HARD_REG_SET (fallthrough_res.regs, scratch); | ||
| 3167 | |||
| 3168 | - find_dead_or_set_registers (JUMP_LABEL (this_jump_insn), | ||
| 3169 | - &target_res, 0, jump_count, | ||
| 3170 | - target_set, needed); | ||
| 3171 | + if (!ANY_RETURN_P (JUMP_LABEL (this_jump_insn))) | ||
| 3172 | + find_dead_or_set_registers (JUMP_LABEL (this_jump_insn), | ||
| 3173 | + &target_res, 0, jump_count, | ||
| 3174 | + target_set, needed); | ||
| 3175 | find_dead_or_set_registers (next, | ||
| 3176 | &fallthrough_res, 0, jump_count, | ||
| 3177 | set, needed); | ||
| 3178 | @@ -1097,6 +1100,8 @@ mark_target_live_regs (rtx insns, rtx ta | ||
| 3179 | struct resources new_resources; | ||
| 3180 | rtx stop_insn = next_active_insn (jump_insn); | ||
| 3181 | |||
| 3182 | + if (jump_target && ANY_RETURN_P (jump_target)) | ||
| 3183 | + jump_target = NULL_RTX; | ||
| 3184 | mark_target_live_regs (insns, next_active_insn (jump_target), | ||
| 3185 | &new_resources); | ||
| 3186 | CLEAR_RESOURCE (&set); | ||
| 3187 | Index: gcc-4_5-branch/gcc/rtl.c | ||
| 3188 | =================================================================== | ||
| 3189 | --- gcc-4_5-branch.orig/gcc/rtl.c | ||
| 3190 | +++ gcc-4_5-branch/gcc/rtl.c | ||
| 3191 | @@ -256,6 +256,8 @@ copy_rtx (rtx orig) | ||
| 3192 | case CODE_LABEL: | ||
| 3193 | case PC: | ||
| 3194 | case CC0: | ||
| 3195 | + case RETURN: | ||
| 3196 | + case SIMPLE_RETURN: | ||
| 3197 | case SCRATCH: | ||
| 3198 | /* SCRATCH must be shared because they represent distinct values. */ | ||
| 3199 | return orig; | ||
| 3200 | Index: gcc-4_5-branch/gcc/rtl.def | ||
| 3201 | =================================================================== | ||
| 3202 | --- gcc-4_5-branch.orig/gcc/rtl.def | ||
| 3203 | +++ gcc-4_5-branch/gcc/rtl.def | ||
| 3204 | @@ -296,6 +296,10 @@ DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXT | ||
| 3205 | |||
| 3206 | DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA) | ||
| 3207 | |||
| 3208 | +/* A plain return, to be used on paths that are reached without going | ||
| 3209 | + through the function prologue. */ | ||
| 3210 | +DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA) | ||
| 3211 | + | ||
| 3212 | /* Special for EH return from subroutine. */ | ||
| 3213 | |||
| 3214 | DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA) | ||
| 3215 | Index: gcc-4_5-branch/gcc/rtl.h | ||
| 3216 | =================================================================== | ||
| 3217 | --- gcc-4_5-branch.orig/gcc/rtl.h | ||
| 3218 | +++ gcc-4_5-branch/gcc/rtl.h | ||
| 3219 | @@ -411,6 +411,10 @@ struct GTY(()) rtvec_def { | ||
| 3220 | (JUMP_P (INSN) && (GET_CODE (PATTERN (INSN)) == ADDR_VEC || \ | ||
| 3221 | GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC)) | ||
| 3222 | |||
| 3223 | +/* Predicate yielding nonzero iff X is a return or simple_preturn. */ | ||
| 3224 | +#define ANY_RETURN_P(X) \ | ||
| 3225 | + (GET_CODE (X) == RETURN || GET_CODE (X) == SIMPLE_RETURN) | ||
| 3226 | + | ||
| 3227 | /* 1 if X is a unary operator. */ | ||
| 3228 | |||
| 3229 | #define UNARY_P(X) \ | ||
| 3230 | @@ -1998,6 +2002,8 @@ enum global_rtl_index | ||
| 3231 | { | ||
| 3232 | GR_PC, | ||
| 3233 | GR_CC0, | ||
| 3234 | + GR_RETURN, | ||
| 3235 | + GR_SIMPLE_RETURN, | ||
| 3236 | GR_STACK_POINTER, | ||
| 3237 | GR_FRAME_POINTER, | ||
| 3238 | /* For register elimination to work properly these hard_frame_pointer_rtx, | ||
| 3239 | @@ -2032,6 +2038,8 @@ extern GTY(()) rtx global_rtl[GR_MAX]; | ||
| 3240 | |||
| 3241 | /* Standard pieces of rtx, to be substituted directly into things. */ | ||
| 3242 | #define pc_rtx (global_rtl[GR_PC]) | ||
| 3243 | +#define ret_rtx (global_rtl[GR_RETURN]) | ||
| 3244 | +#define simple_return_rtx (global_rtl[GR_SIMPLE_RETURN]) | ||
| 3245 | #define cc0_rtx (global_rtl[GR_CC0]) | ||
| 3246 | |||
| 3247 | /* All references to certain hard regs, except those created | ||
| 3248 | Index: gcc-4_5-branch/gcc/rtlanal.c | ||
| 3249 | =================================================================== | ||
| 3250 | --- gcc-4_5-branch.orig/gcc/rtlanal.c | ||
| 3251 | +++ gcc-4_5-branch/gcc/rtlanal.c | ||
| 3252 | @@ -2673,6 +2673,7 @@ tablejump_p (const_rtx insn, rtx *labelp | ||
| 3253 | |||
| 3254 | if (JUMP_P (insn) | ||
| 3255 | && (label = JUMP_LABEL (insn)) != NULL_RTX | ||
| 3256 | + && !ANY_RETURN_P (label) | ||
| 3257 | && (table = next_active_insn (label)) != NULL_RTX | ||
| 3258 | && JUMP_TABLE_DATA_P (table)) | ||
| 3259 | { | ||
| 3260 | Index: gcc-4_5-branch/gcc/sched-int.h | ||
| 3261 | =================================================================== | ||
| 3262 | --- gcc-4_5-branch.orig/gcc/sched-int.h | ||
| 3263 | +++ gcc-4_5-branch/gcc/sched-int.h | ||
| 3264 | @@ -199,7 +199,7 @@ extern int max_issue (struct ready_list | ||
| 3265 | |||
| 3266 | extern void ebb_compute_jump_reg_dependencies (rtx, regset, regset, regset); | ||
| 3267 | |||
| 3268 | -extern edge find_fallthru_edge (basic_block); | ||
| 3269 | +extern edge find_fallthru_edge_from (basic_block); | ||
| 3270 | |||
| 3271 | extern void (* sched_init_only_bb) (basic_block, basic_block); | ||
| 3272 | extern basic_block (* sched_split_block) (basic_block, rtx); | ||
| 3273 | Index: gcc-4_5-branch/gcc/sched-vis.c | ||
| 3274 | =================================================================== | ||
| 3275 | --- gcc-4_5-branch.orig/gcc/sched-vis.c | ||
| 3276 | +++ gcc-4_5-branch/gcc/sched-vis.c | ||
| 3277 | @@ -549,6 +549,9 @@ print_pattern (char *buf, const_rtx x, i | ||
| 3278 | case RETURN: | ||
| 3279 | sprintf (buf, "return"); | ||
| 3280 | break; | ||
| 3281 | + case SIMPLE_RETURN: | ||
| 3282 | + sprintf (buf, "simple_return"); | ||
| 3283 | + break; | ||
| 3284 | case CALL: | ||
| 3285 | print_exp (buf, x, verbose); | ||
| 3286 | break; | ||
| 3287 | Index: gcc-4_5-branch/gcc/sel-sched-ir.c | ||
| 3288 | =================================================================== | ||
| 3289 | --- gcc-4_5-branch.orig/gcc/sel-sched-ir.c | ||
| 3290 | +++ gcc-4_5-branch/gcc/sel-sched-ir.c | ||
| 3291 | @@ -686,7 +686,7 @@ merge_fences (fence_t f, insn_t insn, | ||
| 3292 | |||
| 3293 | /* Find fallthrough edge. */ | ||
| 3294 | gcc_assert (BLOCK_FOR_INSN (insn)->prev_bb); | ||
| 3295 | - candidate = find_fallthru_edge (BLOCK_FOR_INSN (insn)->prev_bb); | ||
| 3296 | + candidate = find_fallthru_edge_from (BLOCK_FOR_INSN (insn)->prev_bb); | ||
| 3297 | |||
| 3298 | if (!candidate | ||
| 3299 | || (candidate->src != BLOCK_FOR_INSN (last_scheduled_insn) | ||
| 3300 | Index: gcc-4_5-branch/gcc/sel-sched.c | ||
| 3301 | =================================================================== | ||
| 3302 | --- gcc-4_5-branch.orig/gcc/sel-sched.c | ||
| 3303 | +++ gcc-4_5-branch/gcc/sel-sched.c | ||
| 3304 | @@ -617,8 +617,8 @@ in_fallthru_bb_p (rtx insn, rtx succ) | ||
| 3305 | if (bb == BLOCK_FOR_INSN (succ)) | ||
| 3306 | return true; | ||
| 3307 | |||
| 3308 | - if (find_fallthru_edge (bb)) | ||
| 3309 | - bb = find_fallthru_edge (bb)->dest; | ||
| 3310 | + if (find_fallthru_edge_from (bb)) | ||
| 3311 | + bb = find_fallthru_edge_from (bb)->dest; | ||
| 3312 | else | ||
| 3313 | return false; | ||
| 3314 | |||
| 3315 | @@ -4911,7 +4911,7 @@ move_cond_jump (rtx insn, bnd_t bnd) | ||
| 3316 | next = PREV_INSN (insn); | ||
| 3317 | BND_TO (bnd) = insn; | ||
| 3318 | |||
| 3319 | - ft_edge = find_fallthru_edge (block_from); | ||
| 3320 | + ft_edge = find_fallthru_edge_from (block_from); | ||
| 3321 | block_next = ft_edge->dest; | ||
| 3322 | /* There must be a fallthrough block (or where should go | ||
| 3323 | control flow in case of false jump predicate otherwise?). */ | ||
| 3324 | Index: gcc-4_5-branch/gcc/vec.h | ||
| 3325 | =================================================================== | ||
| 3326 | --- gcc-4_5-branch.orig/gcc/vec.h | ||
| 3327 | +++ gcc-4_5-branch/gcc/vec.h | ||
| 3328 | @@ -188,6 +188,18 @@ along with GCC; see the file COPYING3. | ||
| 3329 | |||
| 3330 | #define VEC_iterate(T,V,I,P) (VEC_OP(T,base,iterate)(VEC_BASE(V),I,&(P))) | ||
| 3331 | |||
| 3332 | +/* Convenience macro for forward iteration. */ | ||
| 3333 | + | ||
| 3334 | +#define FOR_EACH_VEC_ELT(T, V, I, P) \ | ||
| 3335 | + for (I = 0; VEC_iterate (T, (V), (I), (P)); ++(I)) | ||
| 3336 | + | ||
| 3337 | +/* Convenience macro for reverse iteration. */ | ||
| 3338 | + | ||
| 3339 | +#define FOR_EACH_VEC_ELT_REVERSE(T,V,I,P) \ | ||
| 3340 | + for (I = VEC_length (T, (V)) - 1; \ | ||
| 3341 | + VEC_iterate (T, (V), (I), (P)); \ | ||
| 3342 | + (I)--) | ||
| 3343 | + | ||
| 3344 | /* Allocate new vector. | ||
| 3345 | VEC(T,A) *VEC_T_A_alloc(int reserve); | ||
| 3346 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch deleted file mode 100644 index 337b05580..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch +++ /dev/null | |||
| @@ -1,4075 +0,0 @@ | |||
| 1 | 2011-02-08 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from FSF mainline: | ||
| 4 | |||
| 5 | 2010-06-30 H.J. Lu <hongjiu.lu@intel.com> | ||
| 6 | |||
| 7 | PR target/44721 | ||
| 8 | * config/i386/i386.md (peephole2 for arithmetic ops with memory): | ||
| 9 | Fix last commit. | ||
| 10 | |||
| 11 | 2010-06-30 Richard Guenther <rguenther@suse.de> | ||
| 12 | |||
| 13 | PR target/44722 | ||
| 14 | * config/i386/i386.md (peephole2 for fix:SSEMODEI24): Guard | ||
| 15 | against oscillation with reverse peephole2. | ||
| 16 | |||
| 17 | 2010-07-01 Bernd Schmidt <bernds@codesourcery.com> | ||
| 18 | |||
| 19 | PR target/44727 | ||
| 20 | * config/i386/i386.md (peephole2 for arithmetic ops with memory): | ||
| 21 | Make sure operand 0 dies. | ||
| 22 | |||
| 23 | 2010-12-03 Yao Qi <yao@codesourcery.com> | ||
| 24 | |||
| 25 | * config/arm/arm-ldmstm.ml: Rewrite ldm/stm RTL patterns to fix | ||
| 26 | regressions. | ||
| 27 | * config/arm/ldmstm.md: Regenreate. | ||
| 28 | |||
| 29 | 2010-12-03 Yao Qi <yao@codesourcery.com> | ||
| 30 | |||
| 31 | Backport from FSF mainline: | ||
| 32 | |||
| 33 | 2010-08-02 Bernd Schmidt <bernds@codesourcery.com> | ||
| 34 | |||
| 35 | PR target/40457 | ||
| 36 | * config/arm/arm.h (arm_regs_in_sequence): Declare. | ||
| 37 | * config/arm/arm-protos.h (emit_ldm_seq, emit_stm_seq, | ||
| 38 | load_multiple_sequence, store_multiple_sequence): Delete | ||
| 39 | declarations. | ||
| 40 | (arm_gen_load_multiple, arm_gen_store_multiple): Adjust | ||
| 41 | declarations. | ||
| 42 | * config/arm/ldmstm.md: New file. | ||
| 43 | * config/arm/arm.c (arm_regs_in_sequence): New array. | ||
| 44 | (load_multiple_sequence): Now static. New args SAVED_ORDER, | ||
| 45 | CHECK_REGS. All callers changed. | ||
| 46 | If SAVED_ORDER is nonnull, copy the computed order into it. | ||
| 47 | If CHECK_REGS is false, don't sort REGS. Handle Thumb mode. | ||
| 48 | (store_multiple_sequence): Now static. New args NOPS_TOTAL, | ||
| 49 | SAVED_ORDER, REG_RTXS and CHECK_REGS. All callers changed. | ||
| 50 | If SAVED_ORDER is nonnull, copy the computed order into it. | ||
| 51 | If CHECK_REGS is false, don't sort REGS. Set up REG_RTXS just | ||
| 52 | like REGS. Handle Thumb mode. | ||
| 53 | (arm_gen_load_multiple_1): New function, broken out of | ||
| 54 | arm_gen_load_multiple. | ||
| 55 | (arm_gen_store_multiple_1): New function, broken out of | ||
| 56 | arm_gen_store_multiple. | ||
| 57 | (arm_gen_multiple_op): New function, with code from | ||
| 58 | arm_gen_load_multiple and arm_gen_store_multiple moved here. | ||
| 59 | (arm_gen_load_multiple, arm_gen_store_multiple): Now just | ||
| 60 | wrappers around arm_gen_multiple_op. Remove argument UP, all callers | ||
| 61 | changed. | ||
| 62 | (gen_ldm_seq, gen_stm_seq, gen_const_stm_seq): New functions. | ||
| 63 | * config/arm/predicates.md (commutative_binary_operator): New. | ||
| 64 | (load_multiple_operation, store_multiple_operation): Handle more | ||
| 65 | variants of these patterns with different starting offsets. Handle | ||
| 66 | Thumb-1. | ||
| 67 | * config/arm/arm.md: Include "ldmstm.md". | ||
| 68 | (ldmsi_postinc4, ldmsi_postinc4_thumb1, ldmsi_postinc3, ldmsi_postinc2, | ||
| 69 | ldmsi4, ldmsi3, ldmsi2, stmsi_postinc4, stmsi_postinc4_thumb1, | ||
| 70 | stmsi_postinc3, stmsi_postinc2, stmsi4, stmsi3, stmsi2 and related | ||
| 71 | peepholes): Delete. | ||
| 72 | * config/arm/ldmstm.md: New file. | ||
| 73 | * config/arm/arm-ldmstm.ml: New file. | ||
| 74 | |||
| 75 | * config/arm/arm.c (arm_rtx_costs_1): Remove second clause from the | ||
| 76 | if statement which adds extra costs to frame-related expressions. | ||
| 77 | |||
| 78 | 2010-05-06 Bernd Schmidt <bernds@codesourcery.com> | ||
| 79 | |||
| 80 | * config/arm/arm.h (MAX_LDM_STM_OPS): New macro. | ||
| 81 | * config/arm/arm.c (multiple_operation_profitable_p, | ||
| 82 | compute_offset_order): New static functions. | ||
| 83 | (load_multiple_sequence, store_multiple_sequence): Use them. | ||
| 84 | Replace constant 4 with MAX_LDM_STM_OPS. Compute order[0] from | ||
| 85 | memory offsets, not register numbers. | ||
| 86 | (emit_ldm_seq, emit_stm_seq): Replace constant 4 with MAX_LDM_STM_OPS. | ||
| 87 | |||
| 88 | 2010-04-16 Bernd Schmidt <bernds@codesourcery.com> | ||
| 89 | |||
| 90 | * recog.h (struct recog_data): New field is_operator. | ||
| 91 | (struct insn_operand_data): New field is_operator. | ||
| 92 | * recog.c (extract_insn): Set recog_data.is_operator. | ||
| 93 | * genoutput.c (output_operand_data): Emit code to set the | ||
| 94 | is_operator field. | ||
| 95 | * reload.c (find_reloads): Use it rather than testing for an | ||
| 96 | empty constraint string. | ||
| 97 | |||
| 98 | === added file 'gcc/config/arm/arm-ldmstm.ml' | ||
| 99 | Index: gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml | ||
| 100 | =================================================================== | ||
| 101 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 102 | +++ gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml 2012-03-06 12:51:19.980547615 -0800 | ||
| 103 | @@ -0,0 +1,333 @@ | ||
| 104 | +(* Auto-generate ARM ldm/stm patterns | ||
| 105 | + Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 106 | + Contributed by CodeSourcery. | ||
| 107 | + | ||
| 108 | + This file is part of GCC. | ||
| 109 | + | ||
| 110 | + GCC is free software; you can redistribute it and/or modify it under | ||
| 111 | + the terms of the GNU General Public License as published by the Free | ||
| 112 | + Software Foundation; either version 3, or (at your option) any later | ||
| 113 | + version. | ||
| 114 | + | ||
| 115 | + GCC is distributed in the hope that it will be useful, but WITHOUT ANY | ||
| 116 | + WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 117 | + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
| 118 | + for more details. | ||
| 119 | + | ||
| 120 | + You should have received a copy of the GNU General Public License | ||
| 121 | + along with GCC; see the file COPYING3. If not see | ||
| 122 | + <http://www.gnu.org/licenses/>. | ||
| 123 | + | ||
| 124 | + This is an O'Caml program. The O'Caml compiler is available from: | ||
| 125 | + | ||
| 126 | + http://caml.inria.fr/ | ||
| 127 | + | ||
| 128 | + Or from your favourite OS's friendly packaging system. Tested with version | ||
| 129 | + 3.09.2, though other versions will probably work too. | ||
| 130 | + | ||
| 131 | + Run with: | ||
| 132 | + ocaml arm-ldmstm.ml >/path/to/gcc/config/arm/ldmstm.ml | ||
| 133 | +*) | ||
| 134 | + | ||
| 135 | +type amode = IA | IB | DA | DB | ||
| 136 | + | ||
| 137 | +type optype = IN | OUT | INOUT | ||
| 138 | + | ||
| 139 | +let rec string_of_addrmode addrmode = | ||
| 140 | + match addrmode with | ||
| 141 | + IA -> "ia" | IB -> "ib" | DA -> "da" | DB -> "db" | ||
| 142 | + | ||
| 143 | +let rec initial_offset addrmode nregs = | ||
| 144 | + match addrmode with | ||
| 145 | + IA -> 0 | ||
| 146 | + | IB -> 4 | ||
| 147 | + | DA -> -4 * nregs + 4 | ||
| 148 | + | DB -> -4 * nregs | ||
| 149 | + | ||
| 150 | +let rec final_offset addrmode nregs = | ||
| 151 | + match addrmode with | ||
| 152 | + IA -> nregs * 4 | ||
| 153 | + | IB -> nregs * 4 | ||
| 154 | + | DA -> -4 * nregs | ||
| 155 | + | DB -> -4 * nregs | ||
| 156 | + | ||
| 157 | +let constr thumb = | ||
| 158 | + if thumb then "l" else "rk" | ||
| 159 | + | ||
| 160 | +let inout_constr op_type = | ||
| 161 | + match op_type with | ||
| 162 | + OUT -> "=" | ||
| 163 | + | INOUT -> "+&" | ||
| 164 | + | IN -> "" | ||
| 165 | + | ||
| 166 | +let destreg nregs first op_type thumb = | ||
| 167 | + if not first then | ||
| 168 | + Printf.sprintf "(match_dup %d)" (nregs) | ||
| 169 | + else | ||
| 170 | + Printf.sprintf ("(match_operand:SI %d \"s_register_operand\" \"%s%s\")") | ||
| 171 | + (nregs) (inout_constr op_type) (constr thumb) | ||
| 172 | + | ||
| 173 | +let write_ldm_set thumb nregs offset opnr first = | ||
| 174 | + let indent = " " in | ||
| 175 | + Printf.printf "%s" (if first then " [" else indent); | ||
| 176 | + Printf.printf "(set (match_operand:SI %d \"arm_hard_register_operand\" \"\")\n" opnr; | ||
| 177 | + Printf.printf "%s (mem:SI " indent; | ||
| 178 | + begin if offset != 0 then Printf.printf "(plus:SI " end; | ||
| 179 | + Printf.printf "%s" (destreg nregs first IN thumb); | ||
| 180 | + begin if offset != 0 then Printf.printf "\n%s (const_int %d))" indent offset end; | ||
| 181 | + Printf.printf "))" | ||
| 182 | + | ||
| 183 | +let write_stm_set thumb nregs offset opnr first = | ||
| 184 | + let indent = " " in | ||
| 185 | + Printf.printf "%s" (if first then " [" else indent); | ||
| 186 | + Printf.printf "(set (mem:SI "; | ||
| 187 | + begin if offset != 0 then Printf.printf "(plus:SI " end; | ||
| 188 | + Printf.printf "%s" (destreg nregs first IN thumb); | ||
| 189 | + begin if offset != 0 then Printf.printf " (const_int %d))" offset end; | ||
| 190 | + Printf.printf ")\n%s (match_operand:SI %d \"arm_hard_register_operand\" \"\"))" indent opnr | ||
| 191 | + | ||
| 192 | +let write_ldm_peep_set extra_indent nregs opnr first = | ||
| 193 | + let indent = " " ^ extra_indent in | ||
| 194 | + Printf.printf "%s" (if first then extra_indent ^ " [" else indent); | ||
| 195 | + Printf.printf "(set (match_operand:SI %d \"s_register_operand\" \"\")\n" opnr; | ||
| 196 | + Printf.printf "%s (match_operand:SI %d \"memory_operand\" \"\"))" indent (nregs + opnr) | ||
| 197 | + | ||
| 198 | +let write_stm_peep_set extra_indent nregs opnr first = | ||
| 199 | + let indent = " " ^ extra_indent in | ||
| 200 | + Printf.printf "%s" (if first then extra_indent ^ " [" else indent); | ||
| 201 | + Printf.printf "(set (match_operand:SI %d \"memory_operand\" \"\")\n" (nregs + opnr); | ||
| 202 | + Printf.printf "%s (match_operand:SI %d \"s_register_operand\" \"\"))" indent opnr | ||
| 203 | + | ||
| 204 | +let write_any_load optype nregs opnr first = | ||
| 205 | + let indent = " " in | ||
| 206 | + Printf.printf "%s" (if first then " [" else indent); | ||
| 207 | + Printf.printf "(set (match_operand:SI %d \"s_register_operand\" \"\")\n" opnr; | ||
| 208 | + Printf.printf "%s (match_operand:SI %d \"%s\" \"\"))" indent (nregs * 2 + opnr) optype | ||
| 209 | + | ||
| 210 | +let write_const_store nregs opnr first = | ||
| 211 | + let indent = " " in | ||
| 212 | + Printf.printf "%s(set (match_operand:SI %d \"memory_operand\" \"\")\n" indent (nregs + opnr); | ||
| 213 | + Printf.printf "%s (match_dup %d))" indent opnr | ||
| 214 | + | ||
| 215 | +let write_const_stm_peep_set nregs opnr first = | ||
| 216 | + write_any_load "const_int_operand" nregs opnr first; | ||
| 217 | + Printf.printf "\n"; | ||
| 218 | + write_const_store nregs opnr false | ||
| 219 | + | ||
| 220 | + | ||
| 221 | +let rec write_pat_sets func opnr offset first n_left = | ||
| 222 | + func offset opnr first; | ||
| 223 | + begin | ||
| 224 | + if n_left > 1 then begin | ||
| 225 | + Printf.printf "\n"; | ||
| 226 | + write_pat_sets func (opnr + 1) (offset + 4) false (n_left - 1); | ||
| 227 | + end else | ||
| 228 | + Printf.printf "]" | ||
| 229 | + end | ||
| 230 | + | ||
| 231 | +let rec write_peep_sets func opnr first n_left = | ||
| 232 | + func opnr first; | ||
| 233 | + begin | ||
| 234 | + if n_left > 1 then begin | ||
| 235 | + Printf.printf "\n"; | ||
| 236 | + write_peep_sets func (opnr + 1) false (n_left - 1); | ||
| 237 | + end | ||
| 238 | + end | ||
| 239 | + | ||
| 240 | +let can_thumb addrmode update is_store = | ||
| 241 | + match addrmode, update, is_store with | ||
| 242 | + (* Thumb1 mode only supports IA with update. However, for LDMIA, | ||
| 243 | + if the address register also appears in the list of loaded | ||
| 244 | + registers, the loaded value is stored, hence the RTL pattern | ||
| 245 | + to describe such an insn does not have an update. We check | ||
| 246 | + in the match_parallel predicate that the condition described | ||
| 247 | + above is met. *) | ||
| 248 | + IA, _, false -> true | ||
| 249 | + | IA, true, true -> true | ||
| 250 | + | _ -> false | ||
| 251 | + | ||
| 252 | +let target addrmode thumb = | ||
| 253 | + match addrmode, thumb with | ||
| 254 | + IA, true -> "TARGET_THUMB1" | ||
| 255 | + | IA, false -> "TARGET_32BIT" | ||
| 256 | + | DB, false -> "TARGET_32BIT" | ||
| 257 | + | _, false -> "TARGET_ARM" | ||
| 258 | + | ||
| 259 | +let write_pattern_1 name ls addrmode nregs write_set_fn update thumb = | ||
| 260 | + let astr = string_of_addrmode addrmode in | ||
| 261 | + Printf.printf "(define_insn \"*%s%s%d_%s%s\"\n" | ||
| 262 | + (if thumb then "thumb_" else "") name nregs astr | ||
| 263 | + (if update then "_update" else ""); | ||
| 264 | + Printf.printf " [(match_parallel 0 \"%s_multiple_operation\"\n" ls; | ||
| 265 | + begin | ||
| 266 | + if update then begin | ||
| 267 | + Printf.printf " [(set %s\n (plus:SI " | ||
| 268 | + (destreg 1 true OUT thumb); (*destreg 2 true IN thumb*) | ||
| 269 | + Printf.printf "(match_operand:SI 2 \"s_register_operand\" \"1\")"; | ||
| 270 | + Printf.printf " (const_int %d)))\n" | ||
| 271 | + (final_offset addrmode nregs) | ||
| 272 | + end | ||
| 273 | + end; | ||
| 274 | + write_pat_sets | ||
| 275 | + (write_set_fn thumb (if update then 2 else 1)) (if update then 3 else 2) | ||
| 276 | + (initial_offset addrmode nregs) | ||
| 277 | + (not update) nregs; | ||
| 278 | + Printf.printf ")]\n \"%s && XVECLEN (operands[0], 0) == %d\"\n" | ||
| 279 | + (target addrmode thumb) | ||
| 280 | + (if update then nregs + 1 else nregs); | ||
| 281 | + Printf.printf " \"%s%%(%s%%)\\t%%%d%s, {" | ||
| 282 | + name astr (1) (if update then "!" else ""); | ||
| 283 | + for n = 1 to nregs; do | ||
| 284 | + Printf.printf "%%%d%s" (n+(if update then 2 else 1)) (if n < nregs then ", " else "") | ||
| 285 | + done; | ||
| 286 | + Printf.printf "}\"\n"; | ||
| 287 | + Printf.printf " [(set_attr \"type\" \"%s%d\")" ls nregs; | ||
| 288 | + begin if not thumb then | ||
| 289 | + Printf.printf "\n (set_attr \"predicable\" \"yes\")"; | ||
| 290 | + end; | ||
| 291 | + Printf.printf "])\n\n" | ||
| 292 | + | ||
| 293 | +let write_ldm_pattern addrmode nregs update = | ||
| 294 | + write_pattern_1 "ldm" "load" addrmode nregs write_ldm_set update false; | ||
| 295 | + begin if can_thumb addrmode update false then | ||
| 296 | + write_pattern_1 "ldm" "load" addrmode nregs write_ldm_set update true; | ||
| 297 | + end | ||
| 298 | + | ||
| 299 | +let write_stm_pattern addrmode nregs update = | ||
| 300 | + write_pattern_1 "stm" "store" addrmode nregs write_stm_set update false; | ||
| 301 | + begin if can_thumb addrmode update true then | ||
| 302 | + write_pattern_1 "stm" "store" addrmode nregs write_stm_set update true; | ||
| 303 | + end | ||
| 304 | + | ||
| 305 | +let write_ldm_commutative_peephole thumb = | ||
| 306 | + let nregs = 2 in | ||
| 307 | + Printf.printf "(define_peephole2\n"; | ||
| 308 | + write_peep_sets (write_ldm_peep_set "" nregs) 0 true nregs; | ||
| 309 | + let indent = " " in | ||
| 310 | + if thumb then begin | ||
| 311 | + Printf.printf "\n%s(set (match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2); | ||
| 312 | + Printf.printf "%s (match_operator:SI %d \"commutative_binary_operator\"\n" indent (nregs * 2 + 1); | ||
| 313 | + Printf.printf "%s [(match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2 + 2); | ||
| 314 | + Printf.printf "%s (match_operand:SI %d \"s_register_operand\" \"\")]))]\n" indent (nregs * 2 + 3) | ||
| 315 | + end else begin | ||
| 316 | + Printf.printf "\n%s(parallel\n" indent; | ||
| 317 | + Printf.printf "%s [(set (match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2); | ||
| 318 | + Printf.printf "%s (match_operator:SI %d \"commutative_binary_operator\"\n" indent (nregs * 2 + 1); | ||
| 319 | + Printf.printf "%s [(match_operand:SI %d \"s_register_operand\" \"\")\n" indent (nregs * 2 + 2); | ||
| 320 | + Printf.printf "%s (match_operand:SI %d \"s_register_operand\" \"\")]))\n" indent (nregs * 2 + 3); | ||
| 321 | + Printf.printf "%s (clobber (reg:CC CC_REGNUM))])]\n" indent | ||
| 322 | + end; | ||
| 323 | + Printf.printf " \"(((operands[%d] == operands[0] && operands[%d] == operands[1])\n" (nregs * 2 + 2) (nregs * 2 + 3); | ||
| 324 | + Printf.printf " || (operands[%d] == operands[0] && operands[%d] == operands[1]))\n" (nregs * 2 + 3) (nregs * 2 + 2); | ||
| 325 | + Printf.printf " && peep2_reg_dead_p (%d, operands[0]) && peep2_reg_dead_p (%d, operands[1]))\"\n" (nregs + 1) (nregs + 1); | ||
| 326 | + begin | ||
| 327 | + if thumb then | ||
| 328 | + Printf.printf " [(set (match_dup %d) (match_op_dup %d [(match_dup %d) (match_dup %d)]))]\n" | ||
| 329 | + (nregs * 2) (nregs * 2 + 1) (nregs * 2 + 2) (nregs * 2 + 3) | ||
| 330 | + else begin | ||
| 331 | + Printf.printf " [(parallel\n"; | ||
| 332 | + Printf.printf " [(set (match_dup %d) (match_op_dup %d [(match_dup %d) (match_dup %d)]))\n" | ||
| 333 | + (nregs * 2) (nregs * 2 + 1) (nregs * 2 + 2) (nregs * 2 + 3); | ||
| 334 | + Printf.printf " (clobber (reg:CC CC_REGNUM))])]\n" | ||
| 335 | + end | ||
| 336 | + end; | ||
| 337 | + Printf.printf "{\n if (!gen_ldm_seq (operands, %d, true))\n FAIL;\n" nregs; | ||
| 338 | + Printf.printf "})\n\n" | ||
| 339 | + | ||
| 340 | +let write_ldm_peephole nregs = | ||
| 341 | + Printf.printf "(define_peephole2\n"; | ||
| 342 | + write_peep_sets (write_ldm_peep_set "" nregs) 0 true nregs; | ||
| 343 | + Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; | ||
| 344 | + Printf.printf " if (gen_ldm_seq (operands, %d, false))\n DONE;\n else\n FAIL;\n})\n\n" nregs | ||
| 345 | + | ||
| 346 | +let write_ldm_peephole_b nregs = | ||
| 347 | + if nregs > 2 then begin | ||
| 348 | + Printf.printf "(define_peephole2\n"; | ||
| 349 | + write_ldm_peep_set "" nregs 0 true; | ||
| 350 | + Printf.printf "\n (parallel\n"; | ||
| 351 | + write_peep_sets (write_ldm_peep_set " " nregs) 1 true (nregs - 1); | ||
| 352 | + Printf.printf "])]\n \"\"\n [(const_int 0)]\n{\n"; | ||
| 353 | + Printf.printf " if (gen_ldm_seq (operands, %d, false))\n DONE;\n else\n FAIL;\n})\n\n" nregs | ||
| 354 | + end | ||
| 355 | + | ||
| 356 | +let write_stm_peephole nregs = | ||
| 357 | + Printf.printf "(define_peephole2\n"; | ||
| 358 | + write_peep_sets (write_stm_peep_set "" nregs) 0 true nregs; | ||
| 359 | + Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; | ||
| 360 | + Printf.printf " if (gen_stm_seq (operands, %d))\n DONE;\n else\n FAIL;\n})\n\n" nregs | ||
| 361 | + | ||
| 362 | +let write_stm_peephole_b nregs = | ||
| 363 | + if nregs > 2 then begin | ||
| 364 | + Printf.printf "(define_peephole2\n"; | ||
| 365 | + write_stm_peep_set "" nregs 0 true; | ||
| 366 | + Printf.printf "\n (parallel\n"; | ||
| 367 | + write_peep_sets (write_stm_peep_set "" nregs) 1 true (nregs - 1); | ||
| 368 | + Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; | ||
| 369 | + Printf.printf " if (gen_stm_seq (operands, %d))\n DONE;\n else\n FAIL;\n})\n\n" nregs | ||
| 370 | + end | ||
| 371 | + | ||
| 372 | +let write_const_stm_peephole_a nregs = | ||
| 373 | + Printf.printf "(define_peephole2\n"; | ||
| 374 | + write_peep_sets (write_const_stm_peep_set nregs) 0 true nregs; | ||
| 375 | + Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; | ||
| 376 | + Printf.printf " if (gen_const_stm_seq (operands, %d))\n DONE;\n else\n FAIL;\n})\n\n" nregs | ||
| 377 | + | ||
| 378 | +let write_const_stm_peephole_b nregs = | ||
| 379 | + Printf.printf "(define_peephole2\n"; | ||
| 380 | + write_peep_sets (write_any_load "const_int_operand" nregs) 0 true nregs; | ||
| 381 | + Printf.printf "\n"; | ||
| 382 | + write_peep_sets (write_const_store nregs) 0 false nregs; | ||
| 383 | + Printf.printf "]\n \"\"\n [(const_int 0)]\n{\n"; | ||
| 384 | + Printf.printf " if (gen_const_stm_seq (operands, %d))\n DONE;\n else\n FAIL;\n})\n\n" nregs | ||
| 385 | + | ||
| 386 | +let patterns () = | ||
| 387 | + let addrmodes = [ IA; IB; DA; DB ] in | ||
| 388 | + let sizes = [ 4; 3; 2] in | ||
| 389 | + List.iter | ||
| 390 | + (fun n -> | ||
| 391 | + List.iter | ||
| 392 | + (fun addrmode -> | ||
| 393 | + write_ldm_pattern addrmode n false; | ||
| 394 | + write_ldm_pattern addrmode n true; | ||
| 395 | + write_stm_pattern addrmode n false; | ||
| 396 | + write_stm_pattern addrmode n true) | ||
| 397 | + addrmodes; | ||
| 398 | + write_ldm_peephole n; | ||
| 399 | + write_ldm_peephole_b n; | ||
| 400 | + write_const_stm_peephole_a n; | ||
| 401 | + write_const_stm_peephole_b n; | ||
| 402 | + write_stm_peephole n;) | ||
| 403 | + sizes; | ||
| 404 | + write_ldm_commutative_peephole false; | ||
| 405 | + write_ldm_commutative_peephole true | ||
| 406 | + | ||
| 407 | +let print_lines = List.iter (fun s -> Format.printf "%s@\n" s) | ||
| 408 | + | ||
| 409 | +(* Do it. *) | ||
| 410 | + | ||
| 411 | +let _ = | ||
| 412 | + print_lines [ | ||
| 413 | +"/* ARM ldm/stm instruction patterns. This file was automatically generated"; | ||
| 414 | +" using arm-ldmstm.ml. Please do not edit manually."; | ||
| 415 | +""; | ||
| 416 | +" Copyright (C) 2010 Free Software Foundation, Inc."; | ||
| 417 | +" Contributed by CodeSourcery."; | ||
| 418 | +""; | ||
| 419 | +" This file is part of GCC."; | ||
| 420 | +""; | ||
| 421 | +" GCC is free software; you can redistribute it and/or modify it"; | ||
| 422 | +" under the terms of the GNU General Public License as published"; | ||
| 423 | +" by the Free Software Foundation; either version 3, or (at your"; | ||
| 424 | +" option) any later version."; | ||
| 425 | +""; | ||
| 426 | +" GCC is distributed in the hope that it will be useful, but WITHOUT"; | ||
| 427 | +" ANY WARRANTY; without even the implied warranty of MERCHANTABILITY"; | ||
| 428 | +" or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public"; | ||
| 429 | +" License for more details."; | ||
| 430 | +""; | ||
| 431 | +" You should have received a copy of the GNU General Public License and"; | ||
| 432 | +" a copy of the GCC Runtime Library Exception along with this program;"; | ||
| 433 | +" see the files COPYING3 and COPYING.RUNTIME respectively. If not, see"; | ||
| 434 | +" <http://www.gnu.org/licenses/>. */"; | ||
| 435 | +""]; | ||
| 436 | + patterns (); | ||
| 437 | Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h | ||
| 438 | =================================================================== | ||
| 439 | --- gcc-4_5-branch.orig/gcc/config/arm/arm-protos.h 2012-03-06 12:47:54.000000000 -0800 | ||
| 440 | +++ gcc-4_5-branch/gcc/config/arm/arm-protos.h 2012-03-06 12:51:19.980547615 -0800 | ||
| 441 | @@ -99,14 +99,11 @@ | ||
| 442 | extern int label_mentioned_p (rtx); | ||
| 443 | extern RTX_CODE minmax_code (rtx); | ||
| 444 | extern int adjacent_mem_locations (rtx, rtx); | ||
| 445 | -extern int load_multiple_sequence (rtx *, int, int *, int *, HOST_WIDE_INT *); | ||
| 446 | -extern const char *emit_ldm_seq (rtx *, int); | ||
| 447 | -extern int store_multiple_sequence (rtx *, int, int *, int *, HOST_WIDE_INT *); | ||
| 448 | -extern const char * emit_stm_seq (rtx *, int); | ||
| 449 | -extern rtx arm_gen_load_multiple (int, int, rtx, int, int, | ||
| 450 | - rtx, HOST_WIDE_INT *); | ||
| 451 | -extern rtx arm_gen_store_multiple (int, int, rtx, int, int, | ||
| 452 | - rtx, HOST_WIDE_INT *); | ||
| 453 | +extern bool gen_ldm_seq (rtx *, int, bool); | ||
| 454 | +extern bool gen_stm_seq (rtx *, int); | ||
| 455 | +extern bool gen_const_stm_seq (rtx *, int); | ||
| 456 | +extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); | ||
| 457 | +extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); | ||
| 458 | extern int arm_gen_movmemqi (rtx *); | ||
| 459 | extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx); | ||
| 460 | extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx, | ||
| 461 | Index: gcc-4_5-branch/gcc/config/arm/arm.c | ||
| 462 | =================================================================== | ||
| 463 | --- gcc-4_5-branch.orig/gcc/config/arm/arm.c 2012-03-06 12:47:56.000000000 -0800 | ||
| 464 | +++ gcc-4_5-branch/gcc/config/arm/arm.c 2012-03-06 12:51:19.988547639 -0800 | ||
| 465 | @@ -753,6 +753,12 @@ | ||
| 466 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" | ||
| 467 | }; | ||
| 468 | |||
| 469 | +/* The register numbers in sequence, for passing to arm_gen_load_multiple. */ | ||
| 470 | +int arm_regs_in_sequence[] = | ||
| 471 | +{ | ||
| 472 | + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 | ||
| 473 | +}; | ||
| 474 | + | ||
| 475 | #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl") | ||
| 476 | #define streq(string1, string2) (strcmp (string1, string2) == 0) | ||
| 477 | |||
| 478 | @@ -9647,24 +9653,125 @@ | ||
| 479 | return 0; | ||
| 480 | } | ||
| 481 | |||
| 482 | -int | ||
| 483 | -load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, | ||
| 484 | - HOST_WIDE_INT *load_offset) | ||
| 485 | + | ||
| 486 | +/* Return true iff it would be profitable to turn a sequence of NOPS loads | ||
| 487 | + or stores (depending on IS_STORE) into a load-multiple or store-multiple | ||
| 488 | + instruction. ADD_OFFSET is nonzero if the base address register needs | ||
| 489 | + to be modified with an add instruction before we can use it. */ | ||
| 490 | + | ||
| 491 | +static bool | ||
| 492 | +multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED, | ||
| 493 | + int nops, HOST_WIDE_INT add_offset) | ||
| 494 | + { | ||
| 495 | + /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm | ||
| 496 | + if the offset isn't small enough. The reason 2 ldrs are faster | ||
| 497 | + is because these ARMs are able to do more than one cache access | ||
| 498 | + in a single cycle. The ARM9 and StrongARM have Harvard caches, | ||
| 499 | + whilst the ARM8 has a double bandwidth cache. This means that | ||
| 500 | + these cores can do both an instruction fetch and a data fetch in | ||
| 501 | + a single cycle, so the trick of calculating the address into a | ||
| 502 | + scratch register (one of the result regs) and then doing a load | ||
| 503 | + multiple actually becomes slower (and no smaller in code size). | ||
| 504 | + That is the transformation | ||
| 505 | + | ||
| 506 | + ldr rd1, [rbase + offset] | ||
| 507 | + ldr rd2, [rbase + offset + 4] | ||
| 508 | + | ||
| 509 | + to | ||
| 510 | + | ||
| 511 | + add rd1, rbase, offset | ||
| 512 | + ldmia rd1, {rd1, rd2} | ||
| 513 | + | ||
| 514 | + produces worse code -- '3 cycles + any stalls on rd2' instead of | ||
| 515 | + '2 cycles + any stalls on rd2'. On ARMs with only one cache | ||
| 516 | + access per cycle, the first sequence could never complete in less | ||
| 517 | + than 6 cycles, whereas the ldm sequence would only take 5 and | ||
| 518 | + would make better use of sequential accesses if not hitting the | ||
| 519 | + cache. | ||
| 520 | + | ||
| 521 | + We cheat here and test 'arm_ld_sched' which we currently know to | ||
| 522 | + only be true for the ARM8, ARM9 and StrongARM. If this ever | ||
| 523 | + changes, then the test below needs to be reworked. */ | ||
| 524 | + if (nops == 2 && arm_ld_sched && add_offset != 0) | ||
| 525 | + return false; | ||
| 526 | + | ||
| 527 | + return true; | ||
| 528 | +} | ||
| 529 | + | ||
| 530 | +/* Subroutine of load_multiple_sequence and store_multiple_sequence. | ||
| 531 | + Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute | ||
| 532 | + an array ORDER which describes the sequence to use when accessing the | ||
| 533 | + offsets that produces an ascending order. In this sequence, each | ||
| 534 | + offset must be larger by exactly 4 than the previous one. ORDER[0] | ||
| 535 | + must have been filled in with the lowest offset by the caller. | ||
| 536 | + If UNSORTED_REGS is nonnull, it is an array of register numbers that | ||
| 537 | + we use to verify that ORDER produces an ascending order of registers. | ||
| 538 | + Return true if it was possible to construct such an order, false if | ||
| 539 | + not. */ | ||
| 540 | + | ||
| 541 | +static bool | ||
| 542 | +compute_offset_order (int nops, HOST_WIDE_INT *unsorted_offsets, int *order, | ||
| 543 | + int *unsorted_regs) | ||
| 544 | { | ||
| 545 | - int unsorted_regs[4]; | ||
| 546 | - HOST_WIDE_INT unsorted_offsets[4]; | ||
| 547 | - int order[4]; | ||
| 548 | - int base_reg = -1; | ||
| 549 | int i; | ||
| 550 | + for (i = 1; i < nops; i++) | ||
| 551 | + { | ||
| 552 | + int j; | ||
| 553 | + | ||
| 554 | + order[i] = order[i - 1]; | ||
| 555 | + for (j = 0; j < nops; j++) | ||
| 556 | + if (unsorted_offsets[j] == unsorted_offsets[order[i - 1]] + 4) | ||
| 557 | + { | ||
| 558 | + /* We must find exactly one offset that is higher than the | ||
| 559 | + previous one by 4. */ | ||
| 560 | + if (order[i] != order[i - 1]) | ||
| 561 | + return false; | ||
| 562 | + order[i] = j; | ||
| 563 | + } | ||
| 564 | + if (order[i] == order[i - 1]) | ||
| 565 | + return false; | ||
| 566 | + /* The register numbers must be ascending. */ | ||
| 567 | + if (unsorted_regs != NULL | ||
| 568 | + && unsorted_regs[order[i]] <= unsorted_regs[order[i - 1]]) | ||
| 569 | + return false; | ||
| 570 | + } | ||
| 571 | + return true; | ||
| 572 | +} | ||
| 573 | + | ||
| 574 | +/* Used to determine in a peephole whether a sequence of load | ||
| 575 | + instructions can be changed into a load-multiple instruction. | ||
| 576 | + NOPS is the number of separate load instructions we are examining. The | ||
| 577 | + first NOPS entries in OPERANDS are the destination registers, the | ||
| 578 | + next NOPS entries are memory operands. If this function is | ||
| 579 | + successful, *BASE is set to the common base register of the memory | ||
| 580 | + accesses; *LOAD_OFFSET is set to the first memory location's offset | ||
| 581 | + from that base register. | ||
| 582 | + REGS is an array filled in with the destination register numbers. | ||
| 583 | + SAVED_ORDER (if nonnull), is an array filled in with an order that maps | ||
| 584 | + insn numbers to to an ascending order of stores. If CHECK_REGS is true, | ||
| 585 | + the sequence of registers in REGS matches the loads from ascending memory | ||
| 586 | + locations, and the function verifies that the register numbers are | ||
| 587 | + themselves ascending. If CHECK_REGS is false, the register numbers | ||
| 588 | + are stored in the order they are found in the operands. */ | ||
| 589 | +static int | ||
| 590 | +load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, | ||
| 591 | + int *base, HOST_WIDE_INT *load_offset, bool check_regs) | ||
| 592 | +{ | ||
| 593 | + int unsorted_regs[MAX_LDM_STM_OPS]; | ||
| 594 | + HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS]; | ||
| 595 | + int order[MAX_LDM_STM_OPS]; | ||
| 596 | + rtx base_reg_rtx = NULL; | ||
| 597 | + int base_reg = -1; | ||
| 598 | + int i, ldm_case; | ||
| 599 | |||
| 600 | if (low_irq_latency) | ||
| 601 | return 0; | ||
| 602 | |||
| 603 | - /* Can only handle 2, 3, or 4 insns at present, | ||
| 604 | - though could be easily extended if required. */ | ||
| 605 | - gcc_assert (nops >= 2 && nops <= 4); | ||
| 606 | + /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be | ||
| 607 | + easily extended if required. */ | ||
| 608 | + gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS); | ||
| 609 | |||
| 610 | - memset (order, 0, 4 * sizeof (int)); | ||
| 611 | + memset (order, 0, MAX_LDM_STM_OPS * sizeof (int)); | ||
| 612 | |||
| 613 | /* Loop over the operands and check that the memory references are | ||
| 614 | suitable (i.e. immediate offsets from the same base register). At | ||
| 615 | @@ -9702,32 +9809,30 @@ | ||
| 616 | if (i == 0) | ||
| 617 | { | ||
| 618 | base_reg = REGNO (reg); | ||
| 619 | - unsorted_regs[0] = (GET_CODE (operands[i]) == REG | ||
| 620 | - ? REGNO (operands[i]) | ||
| 621 | - : REGNO (SUBREG_REG (operands[i]))); | ||
| 622 | - order[0] = 0; | ||
| 623 | - } | ||
| 624 | - else | ||
| 625 | - { | ||
| 626 | - if (base_reg != (int) REGNO (reg)) | ||
| 627 | - /* Not addressed from the same base register. */ | ||
| 628 | + base_reg_rtx = reg; | ||
| 629 | + if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM) | ||
| 630 | return 0; | ||
| 631 | - | ||
| 632 | - unsorted_regs[i] = (GET_CODE (operands[i]) == REG | ||
| 633 | - ? REGNO (operands[i]) | ||
| 634 | - : REGNO (SUBREG_REG (operands[i]))); | ||
| 635 | - if (unsorted_regs[i] < unsorted_regs[order[0]]) | ||
| 636 | - order[0] = i; | ||
| 637 | } | ||
| 638 | + else if (base_reg != (int) REGNO (reg)) | ||
| 639 | + /* Not addressed from the same base register. */ | ||
| 640 | + return 0; | ||
| 641 | + | ||
| 642 | + unsorted_regs[i] = (GET_CODE (operands[i]) == REG | ||
| 643 | + ? REGNO (operands[i]) | ||
| 644 | + : REGNO (SUBREG_REG (operands[i]))); | ||
| 645 | |||
| 646 | /* If it isn't an integer register, or if it overwrites the | ||
| 647 | base register but isn't the last insn in the list, then | ||
| 648 | we can't do this. */ | ||
| 649 | - if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 | ||
| 650 | + if (unsorted_regs[i] < 0 | ||
| 651 | + || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) | ||
| 652 | + || unsorted_regs[i] > 14 | ||
| 653 | || (i != nops - 1 && unsorted_regs[i] == base_reg)) | ||
| 654 | return 0; | ||
| 655 | |||
| 656 | unsorted_offsets[i] = INTVAL (offset); | ||
| 657 | + if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) | ||
| 658 | + order[0] = i; | ||
| 659 | } | ||
| 660 | else | ||
| 661 | /* Not a suitable memory address. */ | ||
| 662 | @@ -9736,167 +9841,90 @@ | ||
| 663 | |||
| 664 | /* All the useful information has now been extracted from the | ||
| 665 | operands into unsorted_regs and unsorted_offsets; additionally, | ||
| 666 | - order[0] has been set to the lowest numbered register in the | ||
| 667 | - list. Sort the registers into order, and check that the memory | ||
| 668 | - offsets are ascending and adjacent. */ | ||
| 669 | - | ||
| 670 | - for (i = 1; i < nops; i++) | ||
| 671 | - { | ||
| 672 | - int j; | ||
| 673 | - | ||
| 674 | - order[i] = order[i - 1]; | ||
| 675 | - for (j = 0; j < nops; j++) | ||
| 676 | - if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | ||
| 677 | - && (order[i] == order[i - 1] | ||
| 678 | - || unsorted_regs[j] < unsorted_regs[order[i]])) | ||
| 679 | - order[i] = j; | ||
| 680 | - | ||
| 681 | - /* Have we found a suitable register? if not, one must be used more | ||
| 682 | - than once. */ | ||
| 683 | - if (order[i] == order[i - 1]) | ||
| 684 | - return 0; | ||
| 685 | + order[0] has been set to the lowest offset in the list. Sort | ||
| 686 | + the offsets into order, verifying that they are adjacent, and | ||
| 687 | + check that the register numbers are ascending. */ | ||
| 688 | + if (!compute_offset_order (nops, unsorted_offsets, order, | ||
| 689 | + check_regs ? unsorted_regs : NULL)) | ||
| 690 | + return 0; | ||
| 691 | |||
| 692 | - /* Is the memory address adjacent and ascending? */ | ||
| 693 | - if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | ||
| 694 | - return 0; | ||
| 695 | - } | ||
| 696 | + if (saved_order) | ||
| 697 | + memcpy (saved_order, order, sizeof order); | ||
| 698 | |||
| 699 | if (base) | ||
| 700 | { | ||
| 701 | *base = base_reg; | ||
| 702 | |||
| 703 | for (i = 0; i < nops; i++) | ||
| 704 | - regs[i] = unsorted_regs[order[i]]; | ||
| 705 | + regs[i] = unsorted_regs[check_regs ? order[i] : i]; | ||
| 706 | |||
| 707 | *load_offset = unsorted_offsets[order[0]]; | ||
| 708 | } | ||
| 709 | |||
| 710 | - if (unsorted_offsets[order[0]] == 0) | ||
| 711 | - return 1; /* ldmia */ | ||
| 712 | - | ||
| 713 | - if (TARGET_ARM && unsorted_offsets[order[0]] == 4) | ||
| 714 | - return 2; /* ldmib */ | ||
| 715 | - | ||
| 716 | - if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) | ||
| 717 | - return 3; /* ldmda */ | ||
| 718 | - | ||
| 719 | - if (unsorted_offsets[order[nops - 1]] == -4) | ||
| 720 | - return 4; /* ldmdb */ | ||
| 721 | - | ||
| 722 | - /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm | ||
| 723 | - if the offset isn't small enough. The reason 2 ldrs are faster | ||
| 724 | - is because these ARMs are able to do more than one cache access | ||
| 725 | - in a single cycle. The ARM9 and StrongARM have Harvard caches, | ||
| 726 | - whilst the ARM8 has a double bandwidth cache. This means that | ||
| 727 | - these cores can do both an instruction fetch and a data fetch in | ||
| 728 | - a single cycle, so the trick of calculating the address into a | ||
| 729 | - scratch register (one of the result regs) and then doing a load | ||
| 730 | - multiple actually becomes slower (and no smaller in code size). | ||
| 731 | - That is the transformation | ||
| 732 | - | ||
| 733 | - ldr rd1, [rbase + offset] | ||
| 734 | - ldr rd2, [rbase + offset + 4] | ||
| 735 | - | ||
| 736 | - to | ||
| 737 | - | ||
| 738 | - add rd1, rbase, offset | ||
| 739 | - ldmia rd1, {rd1, rd2} | ||
| 740 | - | ||
| 741 | - produces worse code -- '3 cycles + any stalls on rd2' instead of | ||
| 742 | - '2 cycles + any stalls on rd2'. On ARMs with only one cache | ||
| 743 | - access per cycle, the first sequence could never complete in less | ||
| 744 | - than 6 cycles, whereas the ldm sequence would only take 5 and | ||
| 745 | - would make better use of sequential accesses if not hitting the | ||
| 746 | - cache. | ||
| 747 | - | ||
| 748 | - We cheat here and test 'arm_ld_sched' which we currently know to | ||
| 749 | - only be true for the ARM8, ARM9 and StrongARM. If this ever | ||
| 750 | - changes, then the test below needs to be reworked. */ | ||
| 751 | - if (nops == 2 && arm_ld_sched) | ||
| 752 | + if (TARGET_THUMB1 | ||
| 753 | + && !peep2_reg_dead_p (nops, base_reg_rtx)) | ||
| 754 | return 0; | ||
| 755 | |||
| 756 | - /* Can't do it without setting up the offset, only do this if it takes | ||
| 757 | - no more than one insn. */ | ||
| 758 | - return (const_ok_for_arm (unsorted_offsets[order[0]]) | ||
| 759 | - || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; | ||
| 760 | -} | ||
| 761 | - | ||
| 762 | -const char * | ||
| 763 | -emit_ldm_seq (rtx *operands, int nops) | ||
| 764 | -{ | ||
| 765 | - int regs[4]; | ||
| 766 | - int base_reg; | ||
| 767 | - HOST_WIDE_INT offset; | ||
| 768 | - char buf[100]; | ||
| 769 | - int i; | ||
| 770 | - | ||
| 771 | - switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | ||
| 772 | - { | ||
| 773 | - case 1: | ||
| 774 | - strcpy (buf, "ldm%(ia%)\t"); | ||
| 775 | - break; | ||
| 776 | - | ||
| 777 | - case 2: | ||
| 778 | - strcpy (buf, "ldm%(ib%)\t"); | ||
| 779 | - break; | ||
| 780 | - | ||
| 781 | - case 3: | ||
| 782 | - strcpy (buf, "ldm%(da%)\t"); | ||
| 783 | - break; | ||
| 784 | - | ||
| 785 | - case 4: | ||
| 786 | - strcpy (buf, "ldm%(db%)\t"); | ||
| 787 | - break; | ||
| 788 | - | ||
| 789 | - case 5: | ||
| 790 | - if (offset >= 0) | ||
| 791 | - sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | ||
| 792 | - reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | ||
| 793 | - (long) offset); | ||
| 794 | - else | ||
| 795 | - sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | ||
| 796 | - reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | ||
| 797 | - (long) -offset); | ||
| 798 | - output_asm_insn (buf, operands); | ||
| 799 | - base_reg = regs[0]; | ||
| 800 | - strcpy (buf, "ldm%(ia%)\t"); | ||
| 801 | - break; | ||
| 802 | - | ||
| 803 | - default: | ||
| 804 | - gcc_unreachable (); | ||
| 805 | - } | ||
| 806 | - | ||
| 807 | - sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, | ||
| 808 | - reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); | ||
| 809 | - | ||
| 810 | - for (i = 1; i < nops; i++) | ||
| 811 | - sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | ||
| 812 | - reg_names[regs[i]]); | ||
| 813 | + if (unsorted_offsets[order[0]] == 0) | ||
| 814 | + ldm_case = 1; /* ldmia */ | ||
| 815 | + else if (TARGET_ARM && unsorted_offsets[order[0]] == 4) | ||
| 816 | + ldm_case = 2; /* ldmib */ | ||
| 817 | + else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) | ||
| 818 | + ldm_case = 3; /* ldmda */ | ||
| 819 | + else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4) | ||
| 820 | + ldm_case = 4; /* ldmdb */ | ||
| 821 | + else if (const_ok_for_arm (unsorted_offsets[order[0]]) | ||
| 822 | + || const_ok_for_arm (-unsorted_offsets[order[0]])) | ||
| 823 | + ldm_case = 5; | ||
| 824 | + else | ||
| 825 | + return 0; | ||
| 826 | |||
| 827 | - strcat (buf, "}\t%@ phole ldm"); | ||
| 828 | + if (!multiple_operation_profitable_p (false, nops, | ||
| 829 | + ldm_case == 5 | ||
| 830 | + ? unsorted_offsets[order[0]] : 0)) | ||
| 831 | + return 0; | ||
| 832 | |||
| 833 | - output_asm_insn (buf, operands); | ||
| 834 | - return ""; | ||
| 835 | + return ldm_case; | ||
| 836 | } | ||
| 837 | |||
| 838 | -int | ||
| 839 | -store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, | ||
| 840 | - HOST_WIDE_INT * load_offset) | ||
| 841 | -{ | ||
| 842 | - int unsorted_regs[4]; | ||
| 843 | - HOST_WIDE_INT unsorted_offsets[4]; | ||
| 844 | - int order[4]; | ||
| 845 | +/* Used to determine in a peephole whether a sequence of store instructions can | ||
| 846 | + be changed into a store-multiple instruction. | ||
| 847 | + NOPS is the number of separate store instructions we are examining. | ||
| 848 | + NOPS_TOTAL is the total number of instructions recognized by the peephole | ||
| 849 | + pattern. | ||
| 850 | + The first NOPS entries in OPERANDS are the source registers, the next | ||
| 851 | + NOPS entries are memory operands. If this function is successful, *BASE is | ||
| 852 | + set to the common base register of the memory accesses; *LOAD_OFFSET is set | ||
| 853 | + to the first memory location's offset from that base register. REGS is an | ||
| 854 | + array filled in with the source register numbers, REG_RTXS (if nonnull) is | ||
| 855 | + likewise filled with the corresponding rtx's. | ||
| 856 | + SAVED_ORDER (if nonnull), is an array filled in with an order that maps insn | ||
| 857 | + numbers to to an ascending order of stores. | ||
| 858 | + If CHECK_REGS is true, the sequence of registers in *REGS matches the stores | ||
| 859 | + from ascending memory locations, and the function verifies that the register | ||
| 860 | + numbers are themselves ascending. If CHECK_REGS is false, the register | ||
| 861 | + numbers are stored in the order they are found in the operands. */ | ||
| 862 | +static int | ||
| 863 | +store_multiple_sequence (rtx *operands, int nops, int nops_total, | ||
| 864 | + int *regs, rtx *reg_rtxs, int *saved_order, int *base, | ||
| 865 | + HOST_WIDE_INT *load_offset, bool check_regs) | ||
| 866 | +{ | ||
| 867 | + int unsorted_regs[MAX_LDM_STM_OPS]; | ||
| 868 | + rtx unsorted_reg_rtxs[MAX_LDM_STM_OPS]; | ||
| 869 | + HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS]; | ||
| 870 | + int order[MAX_LDM_STM_OPS]; | ||
| 871 | int base_reg = -1; | ||
| 872 | - int i; | ||
| 873 | + rtx base_reg_rtx = NULL; | ||
| 874 | + int i, stm_case; | ||
| 875 | |||
| 876 | if (low_irq_latency) | ||
| 877 | return 0; | ||
| 878 | |||
| 879 | - /* Can only handle 2, 3, or 4 insns at present, though could be easily | ||
| 880 | - extended if required. */ | ||
| 881 | - gcc_assert (nops >= 2 && nops <= 4); | ||
| 882 | + /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be | ||
| 883 | + easily extended if required. */ | ||
| 884 | + gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS); | ||
| 885 | |||
| 886 | - memset (order, 0, 4 * sizeof (int)); | ||
| 887 | + memset (order, 0, MAX_LDM_STM_OPS * sizeof (int)); | ||
| 888 | |||
| 889 | /* Loop over the operands and check that the memory references are | ||
| 890 | suitable (i.e. immediate offsets from the same base register). At | ||
| 891 | @@ -9931,32 +9959,32 @@ | ||
| 892 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | ||
| 893 | == CONST_INT))) | ||
| 894 | { | ||
| 895 | + unsorted_reg_rtxs[i] = (GET_CODE (operands[i]) == REG | ||
| 896 | + ? operands[i] : SUBREG_REG (operands[i])); | ||
| 897 | + unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]); | ||
| 898 | + | ||
| 899 | if (i == 0) | ||
| 900 | { | ||
| 901 | base_reg = REGNO (reg); | ||
| 902 | - unsorted_regs[0] = (GET_CODE (operands[i]) == REG | ||
| 903 | - ? REGNO (operands[i]) | ||
| 904 | - : REGNO (SUBREG_REG (operands[i]))); | ||
| 905 | - order[0] = 0; | ||
| 906 | - } | ||
| 907 | - else | ||
| 908 | - { | ||
| 909 | - if (base_reg != (int) REGNO (reg)) | ||
| 910 | - /* Not addressed from the same base register. */ | ||
| 911 | + base_reg_rtx = reg; | ||
| 912 | + if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM) | ||
| 913 | return 0; | ||
| 914 | - | ||
| 915 | - unsorted_regs[i] = (GET_CODE (operands[i]) == REG | ||
| 916 | - ? REGNO (operands[i]) | ||
| 917 | - : REGNO (SUBREG_REG (operands[i]))); | ||
| 918 | - if (unsorted_regs[i] < unsorted_regs[order[0]]) | ||
| 919 | - order[0] = i; | ||
| 920 | } | ||
| 921 | + else if (base_reg != (int) REGNO (reg)) | ||
| 922 | + /* Not addressed from the same base register. */ | ||
| 923 | + return 0; | ||
| 924 | |||
| 925 | /* If it isn't an integer register, then we can't do this. */ | ||
| 926 | - if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) | ||
| 927 | + if (unsorted_regs[i] < 0 | ||
| 928 | + || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) | ||
| 929 | + || (TARGET_THUMB2 && unsorted_regs[i] == base_reg) | ||
| 930 | + || (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM) | ||
| 931 | + || unsorted_regs[i] > 14) | ||
| 932 | return 0; | ||
| 933 | |||
| 934 | unsorted_offsets[i] = INTVAL (offset); | ||
| 935 | + if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) | ||
| 936 | + order[0] = i; | ||
| 937 | } | ||
| 938 | else | ||
| 939 | /* Not a suitable memory address. */ | ||
| 940 | @@ -9965,111 +9993,65 @@ | ||
| 941 | |||
| 942 | /* All the useful information has now been extracted from the | ||
| 943 | operands into unsorted_regs and unsorted_offsets; additionally, | ||
| 944 | - order[0] has been set to the lowest numbered register in the | ||
| 945 | - list. Sort the registers into order, and check that the memory | ||
| 946 | - offsets are ascending and adjacent. */ | ||
| 947 | - | ||
| 948 | - for (i = 1; i < nops; i++) | ||
| 949 | - { | ||
| 950 | - int j; | ||
| 951 | - | ||
| 952 | - order[i] = order[i - 1]; | ||
| 953 | - for (j = 0; j < nops; j++) | ||
| 954 | - if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | ||
| 955 | - && (order[i] == order[i - 1] | ||
| 956 | - || unsorted_regs[j] < unsorted_regs[order[i]])) | ||
| 957 | - order[i] = j; | ||
| 958 | - | ||
| 959 | - /* Have we found a suitable register? if not, one must be used more | ||
| 960 | - than once. */ | ||
| 961 | - if (order[i] == order[i - 1]) | ||
| 962 | - return 0; | ||
| 963 | + order[0] has been set to the lowest offset in the list. Sort | ||
| 964 | + the offsets into order, verifying that they are adjacent, and | ||
| 965 | + check that the register numbers are ascending. */ | ||
| 966 | + if (!compute_offset_order (nops, unsorted_offsets, order, | ||
| 967 | + check_regs ? unsorted_regs : NULL)) | ||
| 968 | + return 0; | ||
| 969 | |||
| 970 | - /* Is the memory address adjacent and ascending? */ | ||
| 971 | - if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | ||
| 972 | - return 0; | ||
| 973 | - } | ||
| 974 | + if (saved_order) | ||
| 975 | + memcpy (saved_order, order, sizeof order); | ||
| 976 | |||
| 977 | if (base) | ||
| 978 | { | ||
| 979 | *base = base_reg; | ||
| 980 | |||
| 981 | for (i = 0; i < nops; i++) | ||
| 982 | - regs[i] = unsorted_regs[order[i]]; | ||
| 983 | + { | ||
| 984 | + regs[i] = unsorted_regs[check_regs ? order[i] : i]; | ||
| 985 | + if (reg_rtxs) | ||
| 986 | + reg_rtxs[i] = unsorted_reg_rtxs[check_regs ? order[i] : i]; | ||
| 987 | + } | ||
| 988 | |||
| 989 | *load_offset = unsorted_offsets[order[0]]; | ||
| 990 | } | ||
| 991 | |||
| 992 | - if (unsorted_offsets[order[0]] == 0) | ||
| 993 | - return 1; /* stmia */ | ||
| 994 | - | ||
| 995 | - if (unsorted_offsets[order[0]] == 4) | ||
| 996 | - return 2; /* stmib */ | ||
| 997 | - | ||
| 998 | - if (unsorted_offsets[order[nops - 1]] == 0) | ||
| 999 | - return 3; /* stmda */ | ||
| 1000 | - | ||
| 1001 | - if (unsorted_offsets[order[nops - 1]] == -4) | ||
| 1002 | - return 4; /* stmdb */ | ||
| 1003 | - | ||
| 1004 | - return 0; | ||
| 1005 | -} | ||
| 1006 | - | ||
| 1007 | -const char * | ||
| 1008 | -emit_stm_seq (rtx *operands, int nops) | ||
| 1009 | -{ | ||
| 1010 | - int regs[4]; | ||
| 1011 | - int base_reg; | ||
| 1012 | - HOST_WIDE_INT offset; | ||
| 1013 | - char buf[100]; | ||
| 1014 | - int i; | ||
| 1015 | - | ||
| 1016 | - switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | ||
| 1017 | - { | ||
| 1018 | - case 1: | ||
| 1019 | - strcpy (buf, "stm%(ia%)\t"); | ||
| 1020 | - break; | ||
| 1021 | - | ||
| 1022 | - case 2: | ||
| 1023 | - strcpy (buf, "stm%(ib%)\t"); | ||
| 1024 | - break; | ||
| 1025 | - | ||
| 1026 | - case 3: | ||
| 1027 | - strcpy (buf, "stm%(da%)\t"); | ||
| 1028 | - break; | ||
| 1029 | - | ||
| 1030 | - case 4: | ||
| 1031 | - strcpy (buf, "stm%(db%)\t"); | ||
| 1032 | - break; | ||
| 1033 | - | ||
| 1034 | - default: | ||
| 1035 | - gcc_unreachable (); | ||
| 1036 | - } | ||
| 1037 | - | ||
| 1038 | - sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, | ||
| 1039 | - reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); | ||
| 1040 | + if (TARGET_THUMB1 | ||
| 1041 | + && !peep2_reg_dead_p (nops_total, base_reg_rtx)) | ||
| 1042 | + return 0; | ||
| 1043 | |||
| 1044 | - for (i = 1; i < nops; i++) | ||
| 1045 | - sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | ||
| 1046 | - reg_names[regs[i]]); | ||
| 1047 | + if (unsorted_offsets[order[0]] == 0) | ||
| 1048 | + stm_case = 1; /* stmia */ | ||
| 1049 | + else if (TARGET_ARM && unsorted_offsets[order[0]] == 4) | ||
| 1050 | + stm_case = 2; /* stmib */ | ||
| 1051 | + else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) | ||
| 1052 | + stm_case = 3; /* stmda */ | ||
| 1053 | + else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4) | ||
| 1054 | + stm_case = 4; /* stmdb */ | ||
| 1055 | + else | ||
| 1056 | + return 0; | ||
| 1057 | |||
| 1058 | - strcat (buf, "}\t%@ phole stm"); | ||
| 1059 | + if (!multiple_operation_profitable_p (false, nops, 0)) | ||
| 1060 | + return 0; | ||
| 1061 | |||
| 1062 | - output_asm_insn (buf, operands); | ||
| 1063 | - return ""; | ||
| 1064 | + return stm_case; | ||
| 1065 | } | ||
| 1066 | |||
| 1067 | /* Routines for use in generating RTL. */ | ||
| 1068 | |||
| 1069 | -rtx | ||
| 1070 | -arm_gen_load_multiple (int base_regno, int count, rtx from, int up, | ||
| 1071 | - int write_back, rtx basemem, HOST_WIDE_INT *offsetp) | ||
| 1072 | +/* Generate a load-multiple instruction. COUNT is the number of loads in | ||
| 1073 | + the instruction; REGS and MEMS are arrays containing the operands. | ||
| 1074 | + BASEREG is the base register to be used in addressing the memory operands. | ||
| 1075 | + WBACK_OFFSET is nonzero if the instruction should update the base | ||
| 1076 | + register. */ | ||
| 1077 | + | ||
| 1078 | +static rtx | ||
| 1079 | +arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, | ||
| 1080 | + HOST_WIDE_INT wback_offset) | ||
| 1081 | { | ||
| 1082 | - HOST_WIDE_INT offset = *offsetp; | ||
| 1083 | int i = 0, j; | ||
| 1084 | rtx result; | ||
| 1085 | - int sign = up ? 1 : -1; | ||
| 1086 | - rtx mem, addr; | ||
| 1087 | |||
| 1088 | /* XScale has load-store double instructions, but they have stricter | ||
| 1089 | alignment requirements than load-store multiple, so we cannot | ||
| 1090 | @@ -10106,18 +10088,10 @@ | ||
| 1091 | start_sequence (); | ||
| 1092 | |||
| 1093 | for (i = 0; i < count; i++) | ||
| 1094 | - { | ||
| 1095 | - addr = plus_constant (from, i * 4 * sign); | ||
| 1096 | - mem = adjust_automodify_address (basemem, SImode, addr, offset); | ||
| 1097 | - emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); | ||
| 1098 | - offset += 4 * sign; | ||
| 1099 | - } | ||
| 1100 | + emit_move_insn (gen_rtx_REG (SImode, regs[i]), mems[i]); | ||
| 1101 | |||
| 1102 | - if (write_back) | ||
| 1103 | - { | ||
| 1104 | - emit_move_insn (from, plus_constant (from, count * 4 * sign)); | ||
| 1105 | - *offsetp = offset; | ||
| 1106 | - } | ||
| 1107 | + if (wback_offset != 0) | ||
| 1108 | + emit_move_insn (basereg, plus_constant (basereg, wback_offset)); | ||
| 1109 | |||
| 1110 | seq = get_insns (); | ||
| 1111 | end_sequence (); | ||
| 1112 | @@ -10126,41 +10100,40 @@ | ||
| 1113 | } | ||
| 1114 | |||
| 1115 | result = gen_rtx_PARALLEL (VOIDmode, | ||
| 1116 | - rtvec_alloc (count + (write_back ? 1 : 0))); | ||
| 1117 | - if (write_back) | ||
| 1118 | + rtvec_alloc (count + (wback_offset != 0 ? 1 : 0))); | ||
| 1119 | + if (wback_offset != 0) | ||
| 1120 | { | ||
| 1121 | XVECEXP (result, 0, 0) | ||
| 1122 | - = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign)); | ||
| 1123 | + = gen_rtx_SET (VOIDmode, basereg, | ||
| 1124 | + plus_constant (basereg, wback_offset)); | ||
| 1125 | i = 1; | ||
| 1126 | count++; | ||
| 1127 | } | ||
| 1128 | |||
| 1129 | for (j = 0; i < count; i++, j++) | ||
| 1130 | - { | ||
| 1131 | - addr = plus_constant (from, j * 4 * sign); | ||
| 1132 | - mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); | ||
| 1133 | - XVECEXP (result, 0, i) | ||
| 1134 | - = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); | ||
| 1135 | - offset += 4 * sign; | ||
| 1136 | - } | ||
| 1137 | - | ||
| 1138 | - if (write_back) | ||
| 1139 | - *offsetp = offset; | ||
| 1140 | + XVECEXP (result, 0, i) | ||
| 1141 | + = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regs[j]), mems[j]); | ||
| 1142 | |||
| 1143 | return result; | ||
| 1144 | } | ||
| 1145 | |||
| 1146 | -rtx | ||
| 1147 | -arm_gen_store_multiple (int base_regno, int count, rtx to, int up, | ||
| 1148 | - int write_back, rtx basemem, HOST_WIDE_INT *offsetp) | ||
| 1149 | +/* Generate a store-multiple instruction. COUNT is the number of stores in | ||
| 1150 | + the instruction; REGS and MEMS are arrays containing the operands. | ||
| 1151 | + BASEREG is the base register to be used in addressing the memory operands. | ||
| 1152 | + WBACK_OFFSET is nonzero if the instruction should update the base | ||
| 1153 | + register. */ | ||
| 1154 | + | ||
| 1155 | +static rtx | ||
| 1156 | +arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, | ||
| 1157 | + HOST_WIDE_INT wback_offset) | ||
| 1158 | { | ||
| 1159 | - HOST_WIDE_INT offset = *offsetp; | ||
| 1160 | int i = 0, j; | ||
| 1161 | rtx result; | ||
| 1162 | - int sign = up ? 1 : -1; | ||
| 1163 | - rtx mem, addr; | ||
| 1164 | |||
| 1165 | - /* See arm_gen_load_multiple for discussion of | ||
| 1166 | + if (GET_CODE (basereg) == PLUS) | ||
| 1167 | + basereg = XEXP (basereg, 0); | ||
| 1168 | + | ||
| 1169 | + /* See arm_gen_load_multiple_1 for discussion of | ||
| 1170 | the pros/cons of ldm/stm usage for XScale. */ | ||
| 1171 | if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size)) | ||
| 1172 | { | ||
| 1173 | @@ -10169,18 +10142,10 @@ | ||
| 1174 | start_sequence (); | ||
| 1175 | |||
| 1176 | for (i = 0; i < count; i++) | ||
| 1177 | - { | ||
| 1178 | - addr = plus_constant (to, i * 4 * sign); | ||
| 1179 | - mem = adjust_automodify_address (basemem, SImode, addr, offset); | ||
| 1180 | - emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); | ||
| 1181 | - offset += 4 * sign; | ||
| 1182 | - } | ||
| 1183 | + emit_move_insn (mems[i], gen_rtx_REG (SImode, regs[i])); | ||
| 1184 | |||
| 1185 | - if (write_back) | ||
| 1186 | - { | ||
| 1187 | - emit_move_insn (to, plus_constant (to, count * 4 * sign)); | ||
| 1188 | - *offsetp = offset; | ||
| 1189 | - } | ||
| 1190 | + if (wback_offset != 0) | ||
| 1191 | + emit_move_insn (basereg, plus_constant (basereg, wback_offset)); | ||
| 1192 | |||
| 1193 | seq = get_insns (); | ||
| 1194 | end_sequence (); | ||
| 1195 | @@ -10189,29 +10154,319 @@ | ||
| 1196 | } | ||
| 1197 | |||
| 1198 | result = gen_rtx_PARALLEL (VOIDmode, | ||
| 1199 | - rtvec_alloc (count + (write_back ? 1 : 0))); | ||
| 1200 | - if (write_back) | ||
| 1201 | + rtvec_alloc (count + (wback_offset != 0 ? 1 : 0))); | ||
| 1202 | + if (wback_offset != 0) | ||
| 1203 | { | ||
| 1204 | XVECEXP (result, 0, 0) | ||
| 1205 | - = gen_rtx_SET (VOIDmode, to, | ||
| 1206 | - plus_constant (to, count * 4 * sign)); | ||
| 1207 | + = gen_rtx_SET (VOIDmode, basereg, | ||
| 1208 | + plus_constant (basereg, wback_offset)); | ||
| 1209 | i = 1; | ||
| 1210 | count++; | ||
| 1211 | } | ||
| 1212 | |||
| 1213 | for (j = 0; i < count; i++, j++) | ||
| 1214 | + XVECEXP (result, 0, i) | ||
| 1215 | + = gen_rtx_SET (VOIDmode, mems[j], gen_rtx_REG (SImode, regs[j])); | ||
| 1216 | + | ||
| 1217 | + return result; | ||
| 1218 | +} | ||
| 1219 | + | ||
| 1220 | +/* Generate either a load-multiple or a store-multiple instruction. This | ||
| 1221 | + function can be used in situations where we can start with a single MEM | ||
| 1222 | + rtx and adjust its address upwards. | ||
| 1223 | + COUNT is the number of operations in the instruction, not counting a | ||
| 1224 | + possible update of the base register. REGS is an array containing the | ||
| 1225 | + register operands. | ||
| 1226 | + BASEREG is the base register to be used in addressing the memory operands, | ||
| 1227 | + which are constructed from BASEMEM. | ||
| 1228 | + WRITE_BACK specifies whether the generated instruction should include an | ||
| 1229 | + update of the base register. | ||
| 1230 | + OFFSETP is used to pass an offset to and from this function; this offset | ||
| 1231 | + is not used when constructing the address (instead BASEMEM should have an | ||
| 1232 | + appropriate offset in its address), it is used only for setting | ||
| 1233 | + MEM_OFFSET. It is updated only if WRITE_BACK is true.*/ | ||
| 1234 | + | ||
| 1235 | +static rtx | ||
| 1236 | +arm_gen_multiple_op (bool is_load, int *regs, int count, rtx basereg, | ||
| 1237 | + bool write_back, rtx basemem, HOST_WIDE_INT *offsetp) | ||
| 1238 | +{ | ||
| 1239 | + rtx mems[MAX_LDM_STM_OPS]; | ||
| 1240 | + HOST_WIDE_INT offset = *offsetp; | ||
| 1241 | + int i; | ||
| 1242 | + | ||
| 1243 | + gcc_assert (count <= MAX_LDM_STM_OPS); | ||
| 1244 | + | ||
| 1245 | + if (GET_CODE (basereg) == PLUS) | ||
| 1246 | + basereg = XEXP (basereg, 0); | ||
| 1247 | + | ||
| 1248 | + for (i = 0; i < count; i++) | ||
| 1249 | { | ||
| 1250 | - addr = plus_constant (to, j * 4 * sign); | ||
| 1251 | - mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); | ||
| 1252 | - XVECEXP (result, 0, i) | ||
| 1253 | - = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); | ||
| 1254 | - offset += 4 * sign; | ||
| 1255 | + rtx addr = plus_constant (basereg, i * 4); | ||
| 1256 | + mems[i] = adjust_automodify_address_nv (basemem, SImode, addr, offset); | ||
| 1257 | + offset += 4; | ||
| 1258 | } | ||
| 1259 | |||
| 1260 | if (write_back) | ||
| 1261 | *offsetp = offset; | ||
| 1262 | |||
| 1263 | - return result; | ||
| 1264 | + if (is_load) | ||
| 1265 | + return arm_gen_load_multiple_1 (count, regs, mems, basereg, | ||
| 1266 | + write_back ? 4 * count : 0); | ||
| 1267 | + else | ||
| 1268 | + return arm_gen_store_multiple_1 (count, regs, mems, basereg, | ||
| 1269 | + write_back ? 4 * count : 0); | ||
| 1270 | +} | ||
| 1271 | + | ||
| 1272 | +rtx | ||
| 1273 | +arm_gen_load_multiple (int *regs, int count, rtx basereg, int write_back, | ||
| 1274 | + rtx basemem, HOST_WIDE_INT *offsetp) | ||
| 1275 | +{ | ||
| 1276 | + return arm_gen_multiple_op (TRUE, regs, count, basereg, write_back, basemem, | ||
| 1277 | + offsetp); | ||
| 1278 | +} | ||
| 1279 | + | ||
| 1280 | +rtx | ||
| 1281 | +arm_gen_store_multiple (int *regs, int count, rtx basereg, int write_back, | ||
| 1282 | + rtx basemem, HOST_WIDE_INT *offsetp) | ||
| 1283 | +{ | ||
| 1284 | + return arm_gen_multiple_op (FALSE, regs, count, basereg, write_back, basemem, | ||
| 1285 | + offsetp); | ||
| 1286 | +} | ||
| 1287 | + | ||
| 1288 | +/* Called from a peephole2 expander to turn a sequence of loads into an | ||
| 1289 | + LDM instruction. OPERANDS are the operands found by the peephole matcher; | ||
| 1290 | + NOPS indicates how many separate loads we are trying to combine. SORT_REGS | ||
| 1291 | + is true if we can reorder the registers because they are used commutatively | ||
| 1292 | + subsequently. | ||
| 1293 | + Returns true iff we could generate a new instruction. */ | ||
| 1294 | + | ||
| 1295 | +bool | ||
| 1296 | +gen_ldm_seq (rtx *operands, int nops, bool sort_regs) | ||
| 1297 | +{ | ||
| 1298 | + int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; | ||
| 1299 | + rtx mems[MAX_LDM_STM_OPS]; | ||
| 1300 | + int i, j, base_reg; | ||
| 1301 | + rtx base_reg_rtx; | ||
| 1302 | + HOST_WIDE_INT offset; | ||
| 1303 | + int write_back = FALSE; | ||
| 1304 | + int ldm_case; | ||
| 1305 | + rtx addr; | ||
| 1306 | + | ||
| 1307 | + ldm_case = load_multiple_sequence (operands, nops, regs, mem_order, | ||
| 1308 | + &base_reg, &offset, !sort_regs); | ||
| 1309 | + | ||
| 1310 | + if (ldm_case == 0) | ||
| 1311 | + return false; | ||
| 1312 | + | ||
| 1313 | + if (sort_regs) | ||
| 1314 | + for (i = 0; i < nops - 1; i++) | ||
| 1315 | + for (j = i + 1; j < nops; j++) | ||
| 1316 | + if (regs[i] > regs[j]) | ||
| 1317 | + { | ||
| 1318 | + int t = regs[i]; | ||
| 1319 | + regs[i] = regs[j]; | ||
| 1320 | + regs[j] = t; | ||
| 1321 | + } | ||
| 1322 | + base_reg_rtx = gen_rtx_REG (Pmode, base_reg); | ||
| 1323 | + | ||
| 1324 | + if (TARGET_THUMB1) | ||
| 1325 | + { | ||
| 1326 | + gcc_assert (peep2_reg_dead_p (nops, base_reg_rtx)); | ||
| 1327 | + gcc_assert (ldm_case == 1 || ldm_case == 5); | ||
| 1328 | + write_back = TRUE; | ||
| 1329 | + } | ||
| 1330 | + | ||
| 1331 | + if (ldm_case == 5) | ||
| 1332 | + { | ||
| 1333 | + rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG (SImode, regs[0]); | ||
| 1334 | + emit_insn (gen_addsi3 (newbase, base_reg_rtx, GEN_INT (offset))); | ||
| 1335 | + offset = 0; | ||
| 1336 | + if (!TARGET_THUMB1) | ||
| 1337 | + { | ||
| 1338 | + base_reg = regs[0]; | ||
| 1339 | + base_reg_rtx = newbase; | ||
| 1340 | + } | ||
| 1341 | + } | ||
| 1342 | + | ||
| 1343 | + for (i = 0; i < nops; i++) | ||
| 1344 | + { | ||
| 1345 | + addr = plus_constant (base_reg_rtx, offset + i * 4); | ||
| 1346 | + mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], | ||
| 1347 | + SImode, addr, 0); | ||
| 1348 | + } | ||
| 1349 | + emit_insn (arm_gen_load_multiple_1 (nops, regs, mems, base_reg_rtx, | ||
| 1350 | + write_back ? offset + i * 4 : 0)); | ||
| 1351 | + return true; | ||
| 1352 | +} | ||
| 1353 | + | ||
| 1354 | +/* Called from a peephole2 expander to turn a sequence of stores into an | ||
| 1355 | + STM instruction. OPERANDS are the operands found by the peephole matcher; | ||
| 1356 | + NOPS indicates how many separate stores we are trying to combine. | ||
| 1357 | + Returns true iff we could generate a new instruction. */ | ||
| 1358 | + | ||
| 1359 | +bool | ||
| 1360 | +gen_stm_seq (rtx *operands, int nops) | ||
| 1361 | +{ | ||
| 1362 | + int i; | ||
| 1363 | + int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; | ||
| 1364 | + rtx mems[MAX_LDM_STM_OPS]; | ||
| 1365 | + int base_reg; | ||
| 1366 | + rtx base_reg_rtx; | ||
| 1367 | + HOST_WIDE_INT offset; | ||
| 1368 | + int write_back = FALSE; | ||
| 1369 | + int stm_case; | ||
| 1370 | + rtx addr; | ||
| 1371 | + bool base_reg_dies; | ||
| 1372 | + | ||
| 1373 | + stm_case = store_multiple_sequence (operands, nops, nops, regs, NULL, | ||
| 1374 | + mem_order, &base_reg, &offset, true); | ||
| 1375 | + | ||
| 1376 | + if (stm_case == 0) | ||
| 1377 | + return false; | ||
| 1378 | + | ||
| 1379 | + base_reg_rtx = gen_rtx_REG (Pmode, base_reg); | ||
| 1380 | + | ||
| 1381 | + base_reg_dies = peep2_reg_dead_p (nops, base_reg_rtx); | ||
| 1382 | + if (TARGET_THUMB1) | ||
| 1383 | + { | ||
| 1384 | + gcc_assert (base_reg_dies); | ||
| 1385 | + write_back = TRUE; | ||
| 1386 | + } | ||
| 1387 | + | ||
| 1388 | + if (stm_case == 5) | ||
| 1389 | + { | ||
| 1390 | + gcc_assert (base_reg_dies); | ||
| 1391 | + emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset))); | ||
| 1392 | + offset = 0; | ||
| 1393 | + } | ||
| 1394 | + | ||
| 1395 | + addr = plus_constant (base_reg_rtx, offset); | ||
| 1396 | + | ||
| 1397 | + for (i = 0; i < nops; i++) | ||
| 1398 | + { | ||
| 1399 | + addr = plus_constant (base_reg_rtx, offset + i * 4); | ||
| 1400 | + mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], | ||
| 1401 | + SImode, addr, 0); | ||
| 1402 | + } | ||
| 1403 | + emit_insn (arm_gen_store_multiple_1 (nops, regs, mems, base_reg_rtx, | ||
| 1404 | + write_back ? offset + i * 4 : 0)); | ||
| 1405 | + return true; | ||
| 1406 | +} | ||
| 1407 | + | ||
| 1408 | +/* Called from a peephole2 expander to turn a sequence of stores that are | ||
| 1409 | + preceded by constant loads into an STM instruction. OPERANDS are the | ||
| 1410 | + operands found by the peephole matcher; NOPS indicates how many | ||
| 1411 | + separate stores we are trying to combine; there are 2 * NOPS | ||
| 1412 | + instructions in the peephole. | ||
| 1413 | + Returns true iff we could generate a new instruction. */ | ||
| 1414 | + | ||
| 1415 | +bool | ||
| 1416 | +gen_const_stm_seq (rtx *operands, int nops) | ||
| 1417 | +{ | ||
| 1418 | + int regs[MAX_LDM_STM_OPS], sorted_regs[MAX_LDM_STM_OPS]; | ||
| 1419 | + int reg_order[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; | ||
| 1420 | + rtx reg_rtxs[MAX_LDM_STM_OPS], orig_reg_rtxs[MAX_LDM_STM_OPS]; | ||
| 1421 | + rtx mems[MAX_LDM_STM_OPS]; | ||
| 1422 | + int base_reg; | ||
| 1423 | + rtx base_reg_rtx; | ||
| 1424 | + HOST_WIDE_INT offset; | ||
| 1425 | + int write_back = FALSE; | ||
| 1426 | + int stm_case; | ||
| 1427 | + rtx addr; | ||
| 1428 | + bool base_reg_dies; | ||
| 1429 | + int i, j; | ||
| 1430 | + HARD_REG_SET allocated; | ||
| 1431 | + | ||
| 1432 | + stm_case = store_multiple_sequence (operands, nops, 2 * nops, regs, reg_rtxs, | ||
| 1433 | + mem_order, &base_reg, &offset, false); | ||
| 1434 | + | ||
| 1435 | + if (stm_case == 0) | ||
| 1436 | + return false; | ||
| 1437 | + | ||
| 1438 | + memcpy (orig_reg_rtxs, reg_rtxs, sizeof orig_reg_rtxs); | ||
| 1439 | + | ||
| 1440 | + /* If the same register is used more than once, try to find a free | ||
| 1441 | + register. */ | ||
| 1442 | + CLEAR_HARD_REG_SET (allocated); | ||
| 1443 | + for (i = 0; i < nops; i++) | ||
| 1444 | + { | ||
| 1445 | + for (j = i + 1; j < nops; j++) | ||
| 1446 | + if (regs[i] == regs[j]) | ||
| 1447 | + { | ||
| 1448 | + rtx t = peep2_find_free_register (0, nops * 2, | ||
| 1449 | + TARGET_THUMB1 ? "l" : "r", | ||
| 1450 | + SImode, &allocated); | ||
| 1451 | + if (t == NULL_RTX) | ||
| 1452 | + return false; | ||
| 1453 | + reg_rtxs[i] = t; | ||
| 1454 | + regs[i] = REGNO (t); | ||
| 1455 | + } | ||
| 1456 | + } | ||
| 1457 | + | ||
| 1458 | + /* Compute an ordering that maps the register numbers to an ascending | ||
| 1459 | + sequence. */ | ||
| 1460 | + reg_order[0] = 0; | ||
| 1461 | + for (i = 0; i < nops; i++) | ||
| 1462 | + if (regs[i] < regs[reg_order[0]]) | ||
| 1463 | + reg_order[0] = i; | ||
| 1464 | + | ||
| 1465 | + for (i = 1; i < nops; i++) | ||
| 1466 | + { | ||
| 1467 | + int this_order = reg_order[i - 1]; | ||
| 1468 | + for (j = 0; j < nops; j++) | ||
| 1469 | + if (regs[j] > regs[reg_order[i - 1]] | ||
| 1470 | + && (this_order == reg_order[i - 1] | ||
| 1471 | + || regs[j] < regs[this_order])) | ||
| 1472 | + this_order = j; | ||
| 1473 | + reg_order[i] = this_order; | ||
| 1474 | + } | ||
| 1475 | + | ||
| 1476 | + /* Ensure that registers that must be live after the instruction end | ||
| 1477 | + up with the correct value. */ | ||
| 1478 | + for (i = 0; i < nops; i++) | ||
| 1479 | + { | ||
| 1480 | + int this_order = reg_order[i]; | ||
| 1481 | + if ((this_order != mem_order[i] | ||
| 1482 | + || orig_reg_rtxs[this_order] != reg_rtxs[this_order]) | ||
| 1483 | + && !peep2_reg_dead_p (nops * 2, orig_reg_rtxs[this_order])) | ||
| 1484 | + return false; | ||
| 1485 | + } | ||
| 1486 | + | ||
| 1487 | + /* Load the constants. */ | ||
| 1488 | + for (i = 0; i < nops; i++) | ||
| 1489 | + { | ||
| 1490 | + rtx op = operands[2 * nops + mem_order[i]]; | ||
| 1491 | + sorted_regs[i] = regs[reg_order[i]]; | ||
| 1492 | + emit_move_insn (reg_rtxs[reg_order[i]], op); | ||
| 1493 | + } | ||
| 1494 | + | ||
| 1495 | + base_reg_rtx = gen_rtx_REG (Pmode, base_reg); | ||
| 1496 | + | ||
| 1497 | + base_reg_dies = peep2_reg_dead_p (nops * 2, base_reg_rtx); | ||
| 1498 | + if (TARGET_THUMB1) | ||
| 1499 | + { | ||
| 1500 | + gcc_assert (base_reg_dies); | ||
| 1501 | + write_back = TRUE; | ||
| 1502 | + } | ||
| 1503 | + | ||
| 1504 | + if (stm_case == 5) | ||
| 1505 | + { | ||
| 1506 | + gcc_assert (base_reg_dies); | ||
| 1507 | + emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset))); | ||
| 1508 | + offset = 0; | ||
| 1509 | + } | ||
| 1510 | + | ||
| 1511 | + addr = plus_constant (base_reg_rtx, offset); | ||
| 1512 | + | ||
| 1513 | + for (i = 0; i < nops; i++) | ||
| 1514 | + { | ||
| 1515 | + addr = plus_constant (base_reg_rtx, offset + i * 4); | ||
| 1516 | + mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], | ||
| 1517 | + SImode, addr, 0); | ||
| 1518 | + } | ||
| 1519 | + emit_insn (arm_gen_store_multiple_1 (nops, sorted_regs, mems, base_reg_rtx, | ||
| 1520 | + write_back ? offset + i * 4 : 0)); | ||
| 1521 | + return true; | ||
| 1522 | } | ||
| 1523 | |||
| 1524 | int | ||
| 1525 | @@ -10247,20 +10502,21 @@ | ||
| 1526 | for (i = 0; in_words_to_go >= 2; i+=4) | ||
| 1527 | { | ||
| 1528 | if (in_words_to_go > 4) | ||
| 1529 | - emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, | ||
| 1530 | - srcbase, &srcoffset)); | ||
| 1531 | + emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, src, | ||
| 1532 | + TRUE, srcbase, &srcoffset)); | ||
| 1533 | else | ||
| 1534 | - emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, | ||
| 1535 | - FALSE, srcbase, &srcoffset)); | ||
| 1536 | + emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, in_words_to_go, | ||
| 1537 | + src, FALSE, srcbase, | ||
| 1538 | + &srcoffset)); | ||
| 1539 | |||
| 1540 | if (out_words_to_go) | ||
| 1541 | { | ||
| 1542 | if (out_words_to_go > 4) | ||
| 1543 | - emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, | ||
| 1544 | - dstbase, &dstoffset)); | ||
| 1545 | + emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, dst, | ||
| 1546 | + TRUE, dstbase, &dstoffset)); | ||
| 1547 | else if (out_words_to_go != 1) | ||
| 1548 | - emit_insn (arm_gen_store_multiple (0, out_words_to_go, | ||
| 1549 | - dst, TRUE, | ||
| 1550 | + emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, | ||
| 1551 | + out_words_to_go, dst, | ||
| 1552 | (last_bytes == 0 | ||
| 1553 | ? FALSE : TRUE), | ||
| 1554 | dstbase, &dstoffset)); | ||
| 1555 | Index: gcc-4_5-branch/gcc/config/arm/arm.h | ||
| 1556 | =================================================================== | ||
| 1557 | --- gcc-4_5-branch.orig/gcc/config/arm/arm.h 2012-03-06 12:47:55.000000000 -0800 | ||
| 1558 | +++ gcc-4_5-branch/gcc/config/arm/arm.h 2012-03-06 12:51:19.988547639 -0800 | ||
| 1559 | @@ -1143,6 +1143,9 @@ | ||
| 1560 | ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ | ||
| 1561 | || (MODE) == CImode || (MODE) == XImode) | ||
| 1562 | |||
| 1563 | +/* The register numbers in sequence, for passing to arm_gen_load_multiple. */ | ||
| 1564 | +extern int arm_regs_in_sequence[]; | ||
| 1565 | + | ||
| 1566 | /* The order in which register should be allocated. It is good to use ip | ||
| 1567 | since no saving is required (though calls clobber it) and it never contains | ||
| 1568 | function parameters. It is quite good to use lr since other calls may | ||
| 1569 | @@ -2821,4 +2824,8 @@ | ||
| 1570 | #define NEED_INDICATE_EXEC_STACK 0 | ||
| 1571 | #endif | ||
| 1572 | |||
| 1573 | +/* The maximum number of parallel loads or stores we support in an ldm/stm | ||
| 1574 | + instruction. */ | ||
| 1575 | +#define MAX_LDM_STM_OPS 4 | ||
| 1576 | + | ||
| 1577 | #endif /* ! GCC_ARM_H */ | ||
| 1578 | Index: gcc-4_5-branch/gcc/config/arm/arm.md | ||
| 1579 | =================================================================== | ||
| 1580 | --- gcc-4_5-branch.orig/gcc/config/arm/arm.md 2012-03-06 12:47:56.000000000 -0800 | ||
| 1581 | +++ gcc-4_5-branch/gcc/config/arm/arm.md 2012-03-06 12:51:19.992547622 -0800 | ||
| 1582 | @@ -6282,7 +6282,7 @@ | ||
| 1583 | |||
| 1584 | ;; load- and store-multiple insns | ||
| 1585 | ;; The arm can load/store any set of registers, provided that they are in | ||
| 1586 | -;; ascending order; but that is beyond GCC so stick with what it knows. | ||
| 1587 | +;; ascending order, but these expanders assume a contiguous set. | ||
| 1588 | |||
| 1589 | (define_expand "load_multiple" | ||
| 1590 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") | ||
| 1591 | @@ -6303,126 +6303,12 @@ | ||
| 1592 | FAIL; | ||
| 1593 | |||
| 1594 | operands[3] | ||
| 1595 | - = arm_gen_load_multiple (REGNO (operands[0]), INTVAL (operands[2]), | ||
| 1596 | + = arm_gen_load_multiple (arm_regs_in_sequence + REGNO (operands[0]), | ||
| 1597 | + INTVAL (operands[2]), | ||
| 1598 | force_reg (SImode, XEXP (operands[1], 0)), | ||
| 1599 | - TRUE, FALSE, operands[1], &offset); | ||
| 1600 | + FALSE, operands[1], &offset); | ||
| 1601 | }) | ||
| 1602 | |||
| 1603 | -;; Load multiple with write-back | ||
| 1604 | - | ||
| 1605 | -(define_insn "*ldmsi_postinc4" | ||
| 1606 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1607 | - [(set (match_operand:SI 1 "s_register_operand" "=r") | ||
| 1608 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1609 | - (const_int 16))) | ||
| 1610 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1611 | - (mem:SI (match_dup 2))) | ||
| 1612 | - (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 1613 | - (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | ||
| 1614 | - (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 1615 | - (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | ||
| 1616 | - (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 1617 | - (mem:SI (plus:SI (match_dup 2) (const_int 12))))])] | ||
| 1618 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | ||
| 1619 | - "ldm%(ia%)\\t%1!, {%3, %4, %5, %6}" | ||
| 1620 | - [(set_attr "type" "load4") | ||
| 1621 | - (set_attr "predicable" "yes")] | ||
| 1622 | -) | ||
| 1623 | - | ||
| 1624 | -(define_insn "*ldmsi_postinc4_thumb1" | ||
| 1625 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1626 | - [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 1627 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1628 | - (const_int 16))) | ||
| 1629 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1630 | - (mem:SI (match_dup 2))) | ||
| 1631 | - (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 1632 | - (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | ||
| 1633 | - (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 1634 | - (mem:SI (plus:SI (match_dup 2) (const_int 8)))) | ||
| 1635 | - (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 1636 | - (mem:SI (plus:SI (match_dup 2) (const_int 12))))])] | ||
| 1637 | - "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" | ||
| 1638 | - "ldmia\\t%1!, {%3, %4, %5, %6}" | ||
| 1639 | - [(set_attr "type" "load4")] | ||
| 1640 | -) | ||
| 1641 | - | ||
| 1642 | -(define_insn "*ldmsi_postinc3" | ||
| 1643 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1644 | - [(set (match_operand:SI 1 "s_register_operand" "=r") | ||
| 1645 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1646 | - (const_int 12))) | ||
| 1647 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1648 | - (mem:SI (match_dup 2))) | ||
| 1649 | - (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 1650 | - (mem:SI (plus:SI (match_dup 2) (const_int 4)))) | ||
| 1651 | - (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 1652 | - (mem:SI (plus:SI (match_dup 2) (const_int 8))))])] | ||
| 1653 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 1654 | - "ldm%(ia%)\\t%1!, {%3, %4, %5}" | ||
| 1655 | - [(set_attr "type" "load3") | ||
| 1656 | - (set_attr "predicable" "yes")] | ||
| 1657 | -) | ||
| 1658 | - | ||
| 1659 | -(define_insn "*ldmsi_postinc2" | ||
| 1660 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1661 | - [(set (match_operand:SI 1 "s_register_operand" "=r") | ||
| 1662 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1663 | - (const_int 8))) | ||
| 1664 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1665 | - (mem:SI (match_dup 2))) | ||
| 1666 | - (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 1667 | - (mem:SI (plus:SI (match_dup 2) (const_int 4))))])] | ||
| 1668 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 1669 | - "ldm%(ia%)\\t%1!, {%3, %4}" | ||
| 1670 | - [(set_attr "type" "load2") | ||
| 1671 | - (set_attr "predicable" "yes")] | ||
| 1672 | -) | ||
| 1673 | - | ||
| 1674 | -;; Ordinary load multiple | ||
| 1675 | - | ||
| 1676 | -(define_insn "*ldmsi4" | ||
| 1677 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1678 | - [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 1679 | - (mem:SI (match_operand:SI 1 "s_register_operand" "r"))) | ||
| 1680 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1681 | - (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | ||
| 1682 | - (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 1683 | - (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | ||
| 1684 | - (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 1685 | - (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | ||
| 1686 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 1687 | - "ldm%(ia%)\\t%1, {%2, %3, %4, %5}" | ||
| 1688 | - [(set_attr "type" "load4") | ||
| 1689 | - (set_attr "predicable" "yes")] | ||
| 1690 | -) | ||
| 1691 | - | ||
| 1692 | -(define_insn "*ldmsi3" | ||
| 1693 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1694 | - [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 1695 | - (mem:SI (match_operand:SI 1 "s_register_operand" "r"))) | ||
| 1696 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1697 | - (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | ||
| 1698 | - (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 1699 | - (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | ||
| 1700 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 1701 | - "ldm%(ia%)\\t%1, {%2, %3, %4}" | ||
| 1702 | - [(set_attr "type" "load3") | ||
| 1703 | - (set_attr "predicable" "yes")] | ||
| 1704 | -) | ||
| 1705 | - | ||
| 1706 | -(define_insn "*ldmsi2" | ||
| 1707 | - [(match_parallel 0 "load_multiple_operation" | ||
| 1708 | - [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 1709 | - (mem:SI (match_operand:SI 1 "s_register_operand" "r"))) | ||
| 1710 | - (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 1711 | - (mem:SI (plus:SI (match_dup 1) (const_int 4))))])] | ||
| 1712 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" | ||
| 1713 | - "ldm%(ia%)\\t%1, {%2, %3}" | ||
| 1714 | - [(set_attr "type" "load2") | ||
| 1715 | - (set_attr "predicable" "yes")] | ||
| 1716 | -) | ||
| 1717 | - | ||
| 1718 | (define_expand "store_multiple" | ||
| 1719 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") | ||
| 1720 | (match_operand:SI 1 "" "")) | ||
| 1721 | @@ -6442,125 +6328,12 @@ | ||
| 1722 | FAIL; | ||
| 1723 | |||
| 1724 | operands[3] | ||
| 1725 | - = arm_gen_store_multiple (REGNO (operands[1]), INTVAL (operands[2]), | ||
| 1726 | + = arm_gen_store_multiple (arm_regs_in_sequence + REGNO (operands[1]), | ||
| 1727 | + INTVAL (operands[2]), | ||
| 1728 | force_reg (SImode, XEXP (operands[0], 0)), | ||
| 1729 | - TRUE, FALSE, operands[0], &offset); | ||
| 1730 | + FALSE, operands[0], &offset); | ||
| 1731 | }) | ||
| 1732 | |||
| 1733 | -;; Store multiple with write-back | ||
| 1734 | - | ||
| 1735 | -(define_insn "*stmsi_postinc4" | ||
| 1736 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1737 | - [(set (match_operand:SI 1 "s_register_operand" "=r") | ||
| 1738 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1739 | - (const_int 16))) | ||
| 1740 | - (set (mem:SI (match_dup 2)) | ||
| 1741 | - (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 1742 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 1743 | - (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 1744 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 1745 | - (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 1746 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | ||
| 1747 | - (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 1748 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | ||
| 1749 | - "stm%(ia%)\\t%1!, {%3, %4, %5, %6}" | ||
| 1750 | - [(set_attr "predicable" "yes") | ||
| 1751 | - (set_attr "type" "store4")] | ||
| 1752 | -) | ||
| 1753 | - | ||
| 1754 | -(define_insn "*stmsi_postinc4_thumb1" | ||
| 1755 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1756 | - [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 1757 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1758 | - (const_int 16))) | ||
| 1759 | - (set (mem:SI (match_dup 2)) | ||
| 1760 | - (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 1761 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 1762 | - (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 1763 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 1764 | - (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 1765 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | ||
| 1766 | - (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 1767 | - "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" | ||
| 1768 | - "stmia\\t%1!, {%3, %4, %5, %6}" | ||
| 1769 | - [(set_attr "type" "store4")] | ||
| 1770 | -) | ||
| 1771 | - | ||
| 1772 | -(define_insn "*stmsi_postinc3" | ||
| 1773 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1774 | - [(set (match_operand:SI 1 "s_register_operand" "=r") | ||
| 1775 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1776 | - (const_int 12))) | ||
| 1777 | - (set (mem:SI (match_dup 2)) | ||
| 1778 | - (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 1779 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 1780 | - (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 1781 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 1782 | - (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 1783 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 1784 | - "stm%(ia%)\\t%1!, {%3, %4, %5}" | ||
| 1785 | - [(set_attr "predicable" "yes") | ||
| 1786 | - (set_attr "type" "store3")] | ||
| 1787 | -) | ||
| 1788 | - | ||
| 1789 | -(define_insn "*stmsi_postinc2" | ||
| 1790 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1791 | - [(set (match_operand:SI 1 "s_register_operand" "=r") | ||
| 1792 | - (plus:SI (match_operand:SI 2 "s_register_operand" "1") | ||
| 1793 | - (const_int 8))) | ||
| 1794 | - (set (mem:SI (match_dup 2)) | ||
| 1795 | - (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 1796 | - (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 1797 | - (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 1798 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 1799 | - "stm%(ia%)\\t%1!, {%3, %4}" | ||
| 1800 | - [(set_attr "predicable" "yes") | ||
| 1801 | - (set_attr "type" "store2")] | ||
| 1802 | -) | ||
| 1803 | - | ||
| 1804 | -;; Ordinary store multiple | ||
| 1805 | - | ||
| 1806 | -(define_insn "*stmsi4" | ||
| 1807 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1808 | - [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1809 | - (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 1810 | - (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | ||
| 1811 | - (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 1812 | - (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 1813 | - (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 1814 | - (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | ||
| 1815 | - (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 1816 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 1817 | - "stm%(ia%)\\t%1, {%2, %3, %4, %5}" | ||
| 1818 | - [(set_attr "predicable" "yes") | ||
| 1819 | - (set_attr "type" "store4")] | ||
| 1820 | -) | ||
| 1821 | - | ||
| 1822 | -(define_insn "*stmsi3" | ||
| 1823 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1824 | - [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1825 | - (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 1826 | - (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | ||
| 1827 | - (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 1828 | - (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 1829 | - (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 1830 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 1831 | - "stm%(ia%)\\t%1, {%2, %3, %4}" | ||
| 1832 | - [(set_attr "predicable" "yes") | ||
| 1833 | - (set_attr "type" "store3")] | ||
| 1834 | -) | ||
| 1835 | - | ||
| 1836 | -(define_insn "*stmsi2" | ||
| 1837 | - [(match_parallel 0 "store_multiple_operation" | ||
| 1838 | - [(set (mem:SI (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1839 | - (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 1840 | - (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | ||
| 1841 | - (match_operand:SI 3 "arm_hard_register_operand" ""))])] | ||
| 1842 | - "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" | ||
| 1843 | - "stm%(ia%)\\t%1, {%2, %3}" | ||
| 1844 | - [(set_attr "predicable" "yes") | ||
| 1845 | - (set_attr "type" "store2")] | ||
| 1846 | -) | ||
| 1847 | |||
| 1848 | ;; Move a block of memory if it is word aligned and MORE than 2 words long. | ||
| 1849 | ;; We could let this apply for blocks of less than this, but it clobbers so | ||
| 1850 | @@ -9025,8 +8798,8 @@ | ||
| 1851 | if (REGNO (reg) == R0_REGNUM) | ||
| 1852 | { | ||
| 1853 | /* On thumb we have to use a write-back instruction. */ | ||
| 1854 | - emit_insn (arm_gen_store_multiple (R0_REGNUM, 4, addr, TRUE, | ||
| 1855 | - TARGET_THUMB ? TRUE : FALSE, mem, &offset)); | ||
| 1856 | + emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, addr, | ||
| 1857 | + TARGET_THUMB ? TRUE : FALSE, mem, &offset)); | ||
| 1858 | size = TARGET_ARM ? 16 : 0; | ||
| 1859 | } | ||
| 1860 | else | ||
| 1861 | @@ -9072,8 +8845,8 @@ | ||
| 1862 | if (REGNO (reg) == R0_REGNUM) | ||
| 1863 | { | ||
| 1864 | /* On thumb we have to use a write-back instruction. */ | ||
| 1865 | - emit_insn (arm_gen_load_multiple (R0_REGNUM, 4, addr, TRUE, | ||
| 1866 | - TARGET_THUMB ? TRUE : FALSE, mem, &offset)); | ||
| 1867 | + emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, addr, | ||
| 1868 | + TARGET_THUMB ? TRUE : FALSE, mem, &offset)); | ||
| 1869 | size = TARGET_ARM ? 16 : 0; | ||
| 1870 | } | ||
| 1871 | else | ||
| 1872 | @@ -10666,87 +10439,6 @@ | ||
| 1873 | "" | ||
| 1874 | ) | ||
| 1875 | |||
| 1876 | -; Peepholes to spot possible load- and store-multiples, if the ordering is | ||
| 1877 | -; reversed, check that the memory references aren't volatile. | ||
| 1878 | - | ||
| 1879 | -(define_peephole | ||
| 1880 | - [(set (match_operand:SI 0 "s_register_operand" "=rk") | ||
| 1881 | - (match_operand:SI 4 "memory_operand" "m")) | ||
| 1882 | - (set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 1883 | - (match_operand:SI 5 "memory_operand" "m")) | ||
| 1884 | - (set (match_operand:SI 2 "s_register_operand" "=rk") | ||
| 1885 | - (match_operand:SI 6 "memory_operand" "m")) | ||
| 1886 | - (set (match_operand:SI 3 "s_register_operand" "=rk") | ||
| 1887 | - (match_operand:SI 7 "memory_operand" "m"))] | ||
| 1888 | - "TARGET_ARM && load_multiple_sequence (operands, 4, NULL, NULL, NULL)" | ||
| 1889 | - "* | ||
| 1890 | - return emit_ldm_seq (operands, 4); | ||
| 1891 | - " | ||
| 1892 | -) | ||
| 1893 | - | ||
| 1894 | -(define_peephole | ||
| 1895 | - [(set (match_operand:SI 0 "s_register_operand" "=rk") | ||
| 1896 | - (match_operand:SI 3 "memory_operand" "m")) | ||
| 1897 | - (set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 1898 | - (match_operand:SI 4 "memory_operand" "m")) | ||
| 1899 | - (set (match_operand:SI 2 "s_register_operand" "=rk") | ||
| 1900 | - (match_operand:SI 5 "memory_operand" "m"))] | ||
| 1901 | - "TARGET_ARM && load_multiple_sequence (operands, 3, NULL, NULL, NULL)" | ||
| 1902 | - "* | ||
| 1903 | - return emit_ldm_seq (operands, 3); | ||
| 1904 | - " | ||
| 1905 | -) | ||
| 1906 | - | ||
| 1907 | -(define_peephole | ||
| 1908 | - [(set (match_operand:SI 0 "s_register_operand" "=rk") | ||
| 1909 | - (match_operand:SI 2 "memory_operand" "m")) | ||
| 1910 | - (set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 1911 | - (match_operand:SI 3 "memory_operand" "m"))] | ||
| 1912 | - "TARGET_ARM && load_multiple_sequence (operands, 2, NULL, NULL, NULL)" | ||
| 1913 | - "* | ||
| 1914 | - return emit_ldm_seq (operands, 2); | ||
| 1915 | - " | ||
| 1916 | -) | ||
| 1917 | - | ||
| 1918 | -(define_peephole | ||
| 1919 | - [(set (match_operand:SI 4 "memory_operand" "=m") | ||
| 1920 | - (match_operand:SI 0 "s_register_operand" "rk")) | ||
| 1921 | - (set (match_operand:SI 5 "memory_operand" "=m") | ||
| 1922 | - (match_operand:SI 1 "s_register_operand" "rk")) | ||
| 1923 | - (set (match_operand:SI 6 "memory_operand" "=m") | ||
| 1924 | - (match_operand:SI 2 "s_register_operand" "rk")) | ||
| 1925 | - (set (match_operand:SI 7 "memory_operand" "=m") | ||
| 1926 | - (match_operand:SI 3 "s_register_operand" "rk"))] | ||
| 1927 | - "TARGET_ARM && store_multiple_sequence (operands, 4, NULL, NULL, NULL)" | ||
| 1928 | - "* | ||
| 1929 | - return emit_stm_seq (operands, 4); | ||
| 1930 | - " | ||
| 1931 | -) | ||
| 1932 | - | ||
| 1933 | -(define_peephole | ||
| 1934 | - [(set (match_operand:SI 3 "memory_operand" "=m") | ||
| 1935 | - (match_operand:SI 0 "s_register_operand" "rk")) | ||
| 1936 | - (set (match_operand:SI 4 "memory_operand" "=m") | ||
| 1937 | - (match_operand:SI 1 "s_register_operand" "rk")) | ||
| 1938 | - (set (match_operand:SI 5 "memory_operand" "=m") | ||
| 1939 | - (match_operand:SI 2 "s_register_operand" "rk"))] | ||
| 1940 | - "TARGET_ARM && store_multiple_sequence (operands, 3, NULL, NULL, NULL)" | ||
| 1941 | - "* | ||
| 1942 | - return emit_stm_seq (operands, 3); | ||
| 1943 | - " | ||
| 1944 | -) | ||
| 1945 | - | ||
| 1946 | -(define_peephole | ||
| 1947 | - [(set (match_operand:SI 2 "memory_operand" "=m") | ||
| 1948 | - (match_operand:SI 0 "s_register_operand" "rk")) | ||
| 1949 | - (set (match_operand:SI 3 "memory_operand" "=m") | ||
| 1950 | - (match_operand:SI 1 "s_register_operand" "rk"))] | ||
| 1951 | - "TARGET_ARM && store_multiple_sequence (operands, 2, NULL, NULL, NULL)" | ||
| 1952 | - "* | ||
| 1953 | - return emit_stm_seq (operands, 2); | ||
| 1954 | - " | ||
| 1955 | -) | ||
| 1956 | - | ||
| 1957 | (define_split | ||
| 1958 | [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 1959 | (and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "") | ||
| 1960 | @@ -11549,6 +11241,8 @@ | ||
| 1961 | " | ||
| 1962 | ) | ||
| 1963 | |||
| 1964 | +;; Load the load/store multiple patterns | ||
| 1965 | +(include "ldmstm.md") | ||
| 1966 | ;; Load the FPA co-processor patterns | ||
| 1967 | (include "fpa.md") | ||
| 1968 | ;; Load the Maverick co-processor patterns | ||
| 1969 | Index: gcc-4_5-branch/gcc/config/arm/ldmstm.md | ||
| 1970 | =================================================================== | ||
| 1971 | --- /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
| 1972 | +++ gcc-4_5-branch/gcc/config/arm/ldmstm.md 2012-03-06 12:51:19.992547622 -0800 | ||
| 1973 | @@ -0,0 +1,1191 @@ | ||
| 1974 | +/* ARM ldm/stm instruction patterns. This file was automatically generated | ||
| 1975 | + using arm-ldmstm.ml. Please do not edit manually. | ||
| 1976 | + | ||
| 1977 | + Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 1978 | + Contributed by CodeSourcery. | ||
| 1979 | + | ||
| 1980 | + This file is part of GCC. | ||
| 1981 | + | ||
| 1982 | + GCC is free software; you can redistribute it and/or modify it | ||
| 1983 | + under the terms of the GNU General Public License as published | ||
| 1984 | + by the Free Software Foundation; either version 3, or (at your | ||
| 1985 | + option) any later version. | ||
| 1986 | + | ||
| 1987 | + GCC is distributed in the hope that it will be useful, but WITHOUT | ||
| 1988 | + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
| 1989 | + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | ||
| 1990 | + License for more details. | ||
| 1991 | + | ||
| 1992 | + You should have received a copy of the GNU General Public License and | ||
| 1993 | + a copy of the GCC Runtime Library Exception along with this program; | ||
| 1994 | + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | ||
| 1995 | + <http://www.gnu.org/licenses/>. */ | ||
| 1996 | + | ||
| 1997 | +(define_insn "*ldm4_ia" | ||
| 1998 | + [(match_parallel 0 "load_multiple_operation" | ||
| 1999 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2000 | + (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))) | ||
| 2001 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2002 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2003 | + (const_int 4)))) | ||
| 2004 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2005 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2006 | + (const_int 8)))) | ||
| 2007 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2008 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2009 | + (const_int 12))))])] | ||
| 2010 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2011 | + "ldm%(ia%)\t%1, {%2, %3, %4, %5}" | ||
| 2012 | + [(set_attr "type" "load4") | ||
| 2013 | + (set_attr "predicable" "yes")]) | ||
| 2014 | + | ||
| 2015 | +(define_insn "*thumb_ldm4_ia" | ||
| 2016 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2017 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2018 | + (mem:SI (match_operand:SI 1 "s_register_operand" "l"))) | ||
| 2019 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2020 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2021 | + (const_int 4)))) | ||
| 2022 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2023 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2024 | + (const_int 8)))) | ||
| 2025 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2026 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2027 | + (const_int 12))))])] | ||
| 2028 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" | ||
| 2029 | + "ldm%(ia%)\t%1, {%2, %3, %4, %5}" | ||
| 2030 | + [(set_attr "type" "load4")]) | ||
| 2031 | + | ||
| 2032 | +(define_insn "*ldm4_ia_update" | ||
| 2033 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2034 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2035 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) | ||
| 2036 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2037 | + (mem:SI (match_dup 2))) | ||
| 2038 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2039 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2040 | + (const_int 4)))) | ||
| 2041 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2042 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2043 | + (const_int 8)))) | ||
| 2044 | + (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 2045 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2046 | + (const_int 12))))])] | ||
| 2047 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | ||
| 2048 | + "ldm%(ia%)\t%1!, {%3, %4, %5, %6}" | ||
| 2049 | + [(set_attr "type" "load4") | ||
| 2050 | + (set_attr "predicable" "yes")]) | ||
| 2051 | + | ||
| 2052 | +(define_insn "*thumb_ldm4_ia_update" | ||
| 2053 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2054 | + [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 2055 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) | ||
| 2056 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2057 | + (mem:SI (match_dup 2))) | ||
| 2058 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2059 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2060 | + (const_int 4)))) | ||
| 2061 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2062 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2063 | + (const_int 8)))) | ||
| 2064 | + (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 2065 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2066 | + (const_int 12))))])] | ||
| 2067 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" | ||
| 2068 | + "ldm%(ia%)\t%1!, {%3, %4, %5, %6}" | ||
| 2069 | + [(set_attr "type" "load4")]) | ||
| 2070 | + | ||
| 2071 | +(define_insn "*stm4_ia" | ||
| 2072 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2073 | + [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk")) | ||
| 2074 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2075 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | ||
| 2076 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2077 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 2078 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2079 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | ||
| 2080 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2081 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2082 | + "stm%(ia%)\t%1, {%2, %3, %4, %5}" | ||
| 2083 | + [(set_attr "type" "store4") | ||
| 2084 | + (set_attr "predicable" "yes")]) | ||
| 2085 | + | ||
| 2086 | +(define_insn "*stm4_ia_update" | ||
| 2087 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2088 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2089 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) | ||
| 2090 | + (set (mem:SI (match_dup 2)) | ||
| 2091 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2092 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2093 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2094 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2095 | + (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 2096 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | ||
| 2097 | + (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 2098 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | ||
| 2099 | + "stm%(ia%)\t%1!, {%3, %4, %5, %6}" | ||
| 2100 | + [(set_attr "type" "store4") | ||
| 2101 | + (set_attr "predicable" "yes")]) | ||
| 2102 | + | ||
| 2103 | +(define_insn "*thumb_stm4_ia_update" | ||
| 2104 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2105 | + [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 2106 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) | ||
| 2107 | + (set (mem:SI (match_dup 2)) | ||
| 2108 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2109 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2110 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2111 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2112 | + (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 2113 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | ||
| 2114 | + (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 2115 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" | ||
| 2116 | + "stm%(ia%)\t%1!, {%3, %4, %5, %6}" | ||
| 2117 | + [(set_attr "type" "store4")]) | ||
| 2118 | + | ||
| 2119 | +(define_insn "*ldm4_ib" | ||
| 2120 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2121 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2122 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2123 | + (const_int 4)))) | ||
| 2124 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2125 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2126 | + (const_int 8)))) | ||
| 2127 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2128 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2129 | + (const_int 12)))) | ||
| 2130 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2131 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2132 | + (const_int 16))))])] | ||
| 2133 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2134 | + "ldm%(ib%)\t%1, {%2, %3, %4, %5}" | ||
| 2135 | + [(set_attr "type" "load4") | ||
| 2136 | + (set_attr "predicable" "yes")]) | ||
| 2137 | + | ||
| 2138 | +(define_insn "*ldm4_ib_update" | ||
| 2139 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2140 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2141 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) | ||
| 2142 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2143 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2144 | + (const_int 4)))) | ||
| 2145 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2146 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2147 | + (const_int 8)))) | ||
| 2148 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2149 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2150 | + (const_int 12)))) | ||
| 2151 | + (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 2152 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2153 | + (const_int 16))))])] | ||
| 2154 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 5" | ||
| 2155 | + "ldm%(ib%)\t%1!, {%3, %4, %5, %6}" | ||
| 2156 | + [(set_attr "type" "load4") | ||
| 2157 | + (set_attr "predicable" "yes")]) | ||
| 2158 | + | ||
| 2159 | +(define_insn "*stm4_ib" | ||
| 2160 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2161 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4))) | ||
| 2162 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2163 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 2164 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2165 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | ||
| 2166 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2167 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | ||
| 2168 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2169 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2170 | + "stm%(ib%)\t%1, {%2, %3, %4, %5}" | ||
| 2171 | + [(set_attr "type" "store4") | ||
| 2172 | + (set_attr "predicable" "yes")]) | ||
| 2173 | + | ||
| 2174 | +(define_insn "*stm4_ib_update" | ||
| 2175 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2176 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2177 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) | ||
| 2178 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2179 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2180 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2181 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2182 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | ||
| 2183 | + (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 2184 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 16))) | ||
| 2185 | + (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 2186 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 5" | ||
| 2187 | + "stm%(ib%)\t%1!, {%3, %4, %5, %6}" | ||
| 2188 | + [(set_attr "type" "store4") | ||
| 2189 | + (set_attr "predicable" "yes")]) | ||
| 2190 | + | ||
| 2191 | +(define_insn "*ldm4_da" | ||
| 2192 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2193 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2194 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2195 | + (const_int -12)))) | ||
| 2196 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2197 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2198 | + (const_int -8)))) | ||
| 2199 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2200 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2201 | + (const_int -4)))) | ||
| 2202 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2203 | + (mem:SI (match_dup 1)))])] | ||
| 2204 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2205 | + "ldm%(da%)\t%1, {%2, %3, %4, %5}" | ||
| 2206 | + [(set_attr "type" "load4") | ||
| 2207 | + (set_attr "predicable" "yes")]) | ||
| 2208 | + | ||
| 2209 | +(define_insn "*ldm4_da_update" | ||
| 2210 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2211 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2212 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16))) | ||
| 2213 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2214 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2215 | + (const_int -12)))) | ||
| 2216 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2217 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2218 | + (const_int -8)))) | ||
| 2219 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2220 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2221 | + (const_int -4)))) | ||
| 2222 | + (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 2223 | + (mem:SI (match_dup 2)))])] | ||
| 2224 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 5" | ||
| 2225 | + "ldm%(da%)\t%1!, {%3, %4, %5, %6}" | ||
| 2226 | + [(set_attr "type" "load4") | ||
| 2227 | + (set_attr "predicable" "yes")]) | ||
| 2228 | + | ||
| 2229 | +(define_insn "*stm4_da" | ||
| 2230 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2231 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -12))) | ||
| 2232 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2233 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -8))) | ||
| 2234 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2235 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) | ||
| 2236 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2237 | + (set (mem:SI (match_dup 1)) | ||
| 2238 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2239 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2240 | + "stm%(da%)\t%1, {%2, %3, %4, %5}" | ||
| 2241 | + [(set_attr "type" "store4") | ||
| 2242 | + (set_attr "predicable" "yes")]) | ||
| 2243 | + | ||
| 2244 | +(define_insn "*stm4_da_update" | ||
| 2245 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2246 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2247 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16))) | ||
| 2248 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -12))) | ||
| 2249 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2250 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) | ||
| 2251 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2252 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) | ||
| 2253 | + (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 2254 | + (set (mem:SI (match_dup 2)) | ||
| 2255 | + (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 2256 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 5" | ||
| 2257 | + "stm%(da%)\t%1!, {%3, %4, %5, %6}" | ||
| 2258 | + [(set_attr "type" "store4") | ||
| 2259 | + (set_attr "predicable" "yes")]) | ||
| 2260 | + | ||
| 2261 | +(define_insn "*ldm4_db" | ||
| 2262 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2263 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2264 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2265 | + (const_int -16)))) | ||
| 2266 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2267 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2268 | + (const_int -12)))) | ||
| 2269 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2270 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2271 | + (const_int -8)))) | ||
| 2272 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2273 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2274 | + (const_int -4))))])] | ||
| 2275 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2276 | + "ldm%(db%)\t%1, {%2, %3, %4, %5}" | ||
| 2277 | + [(set_attr "type" "load4") | ||
| 2278 | + (set_attr "predicable" "yes")]) | ||
| 2279 | + | ||
| 2280 | +(define_insn "*ldm4_db_update" | ||
| 2281 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2282 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2283 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16))) | ||
| 2284 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2285 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2286 | + (const_int -16)))) | ||
| 2287 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2288 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2289 | + (const_int -12)))) | ||
| 2290 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2291 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2292 | + (const_int -8)))) | ||
| 2293 | + (set (match_operand:SI 6 "arm_hard_register_operand" "") | ||
| 2294 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2295 | + (const_int -4))))])] | ||
| 2296 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | ||
| 2297 | + "ldm%(db%)\t%1!, {%3, %4, %5, %6}" | ||
| 2298 | + [(set_attr "type" "load4") | ||
| 2299 | + (set_attr "predicable" "yes")]) | ||
| 2300 | + | ||
| 2301 | +(define_insn "*stm4_db" | ||
| 2302 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2303 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -16))) | ||
| 2304 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2305 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -12))) | ||
| 2306 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2307 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -8))) | ||
| 2308 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2309 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) | ||
| 2310 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2311 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2312 | + "stm%(db%)\t%1, {%2, %3, %4, %5}" | ||
| 2313 | + [(set_attr "type" "store4") | ||
| 2314 | + (set_attr "predicable" "yes")]) | ||
| 2315 | + | ||
| 2316 | +(define_insn "*stm4_db_update" | ||
| 2317 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2318 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2319 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -16))) | ||
| 2320 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -16))) | ||
| 2321 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2322 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -12))) | ||
| 2323 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2324 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) | ||
| 2325 | + (match_operand:SI 5 "arm_hard_register_operand" "")) | ||
| 2326 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) | ||
| 2327 | + (match_operand:SI 6 "arm_hard_register_operand" ""))])] | ||
| 2328 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" | ||
| 2329 | + "stm%(db%)\t%1!, {%3, %4, %5, %6}" | ||
| 2330 | + [(set_attr "type" "store4") | ||
| 2331 | + (set_attr "predicable" "yes")]) | ||
| 2332 | + | ||
| 2333 | +(define_peephole2 | ||
| 2334 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2335 | + (match_operand:SI 4 "memory_operand" "")) | ||
| 2336 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 2337 | + (match_operand:SI 5 "memory_operand" "")) | ||
| 2338 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2339 | + (match_operand:SI 6 "memory_operand" "")) | ||
| 2340 | + (set (match_operand:SI 3 "s_register_operand" "") | ||
| 2341 | + (match_operand:SI 7 "memory_operand" ""))] | ||
| 2342 | + "" | ||
| 2343 | + [(const_int 0)] | ||
| 2344 | +{ | ||
| 2345 | + if (gen_ldm_seq (operands, 4, false)) | ||
| 2346 | + DONE; | ||
| 2347 | + else | ||
| 2348 | + FAIL; | ||
| 2349 | +}) | ||
| 2350 | + | ||
| 2351 | +(define_peephole2 | ||
| 2352 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2353 | + (match_operand:SI 4 "memory_operand" "")) | ||
| 2354 | + (parallel | ||
| 2355 | + [(set (match_operand:SI 1 "s_register_operand" "") | ||
| 2356 | + (match_operand:SI 5 "memory_operand" "")) | ||
| 2357 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2358 | + (match_operand:SI 6 "memory_operand" "")) | ||
| 2359 | + (set (match_operand:SI 3 "s_register_operand" "") | ||
| 2360 | + (match_operand:SI 7 "memory_operand" ""))])] | ||
| 2361 | + "" | ||
| 2362 | + [(const_int 0)] | ||
| 2363 | +{ | ||
| 2364 | + if (gen_ldm_seq (operands, 4, false)) | ||
| 2365 | + DONE; | ||
| 2366 | + else | ||
| 2367 | + FAIL; | ||
| 2368 | +}) | ||
| 2369 | + | ||
| 2370 | +(define_peephole2 | ||
| 2371 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2372 | + (match_operand:SI 8 "const_int_operand" "")) | ||
| 2373 | + (set (match_operand:SI 4 "memory_operand" "") | ||
| 2374 | + (match_dup 0)) | ||
| 2375 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 2376 | + (match_operand:SI 9 "const_int_operand" "")) | ||
| 2377 | + (set (match_operand:SI 5 "memory_operand" "") | ||
| 2378 | + (match_dup 1)) | ||
| 2379 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2380 | + (match_operand:SI 10 "const_int_operand" "")) | ||
| 2381 | + (set (match_operand:SI 6 "memory_operand" "") | ||
| 2382 | + (match_dup 2)) | ||
| 2383 | + (set (match_operand:SI 3 "s_register_operand" "") | ||
| 2384 | + (match_operand:SI 11 "const_int_operand" "")) | ||
| 2385 | + (set (match_operand:SI 7 "memory_operand" "") | ||
| 2386 | + (match_dup 3))] | ||
| 2387 | + "" | ||
| 2388 | + [(const_int 0)] | ||
| 2389 | +{ | ||
| 2390 | + if (gen_const_stm_seq (operands, 4)) | ||
| 2391 | + DONE; | ||
| 2392 | + else | ||
| 2393 | + FAIL; | ||
| 2394 | +}) | ||
| 2395 | + | ||
| 2396 | +(define_peephole2 | ||
| 2397 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2398 | + (match_operand:SI 8 "const_int_operand" "")) | ||
| 2399 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 2400 | + (match_operand:SI 9 "const_int_operand" "")) | ||
| 2401 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2402 | + (match_operand:SI 10 "const_int_operand" "")) | ||
| 2403 | + (set (match_operand:SI 3 "s_register_operand" "") | ||
| 2404 | + (match_operand:SI 11 "const_int_operand" "")) | ||
| 2405 | + (set (match_operand:SI 4 "memory_operand" "") | ||
| 2406 | + (match_dup 0)) | ||
| 2407 | + (set (match_operand:SI 5 "memory_operand" "") | ||
| 2408 | + (match_dup 1)) | ||
| 2409 | + (set (match_operand:SI 6 "memory_operand" "") | ||
| 2410 | + (match_dup 2)) | ||
| 2411 | + (set (match_operand:SI 7 "memory_operand" "") | ||
| 2412 | + (match_dup 3))] | ||
| 2413 | + "" | ||
| 2414 | + [(const_int 0)] | ||
| 2415 | +{ | ||
| 2416 | + if (gen_const_stm_seq (operands, 4)) | ||
| 2417 | + DONE; | ||
| 2418 | + else | ||
| 2419 | + FAIL; | ||
| 2420 | +}) | ||
| 2421 | + | ||
| 2422 | +(define_peephole2 | ||
| 2423 | + [(set (match_operand:SI 4 "memory_operand" "") | ||
| 2424 | + (match_operand:SI 0 "s_register_operand" "")) | ||
| 2425 | + (set (match_operand:SI 5 "memory_operand" "") | ||
| 2426 | + (match_operand:SI 1 "s_register_operand" "")) | ||
| 2427 | + (set (match_operand:SI 6 "memory_operand" "") | ||
| 2428 | + (match_operand:SI 2 "s_register_operand" "")) | ||
| 2429 | + (set (match_operand:SI 7 "memory_operand" "") | ||
| 2430 | + (match_operand:SI 3 "s_register_operand" ""))] | ||
| 2431 | + "" | ||
| 2432 | + [(const_int 0)] | ||
| 2433 | +{ | ||
| 2434 | + if (gen_stm_seq (operands, 4)) | ||
| 2435 | + DONE; | ||
| 2436 | + else | ||
| 2437 | + FAIL; | ||
| 2438 | +}) | ||
| 2439 | + | ||
| 2440 | +(define_insn "*ldm3_ia" | ||
| 2441 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2442 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2443 | + (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))) | ||
| 2444 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2445 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2446 | + (const_int 4)))) | ||
| 2447 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2448 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2449 | + (const_int 8))))])] | ||
| 2450 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 2451 | + "ldm%(ia%)\t%1, {%2, %3, %4}" | ||
| 2452 | + [(set_attr "type" "load3") | ||
| 2453 | + (set_attr "predicable" "yes")]) | ||
| 2454 | + | ||
| 2455 | +(define_insn "*thumb_ldm3_ia" | ||
| 2456 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2457 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2458 | + (mem:SI (match_operand:SI 1 "s_register_operand" "l"))) | ||
| 2459 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2460 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2461 | + (const_int 4)))) | ||
| 2462 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2463 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2464 | + (const_int 8))))])] | ||
| 2465 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" | ||
| 2466 | + "ldm%(ia%)\t%1, {%2, %3, %4}" | ||
| 2467 | + [(set_attr "type" "load3")]) | ||
| 2468 | + | ||
| 2469 | +(define_insn "*ldm3_ia_update" | ||
| 2470 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2471 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2472 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) | ||
| 2473 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2474 | + (mem:SI (match_dup 2))) | ||
| 2475 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2476 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2477 | + (const_int 4)))) | ||
| 2478 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2479 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2480 | + (const_int 8))))])] | ||
| 2481 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2482 | + "ldm%(ia%)\t%1!, {%3, %4, %5}" | ||
| 2483 | + [(set_attr "type" "load3") | ||
| 2484 | + (set_attr "predicable" "yes")]) | ||
| 2485 | + | ||
| 2486 | +(define_insn "*thumb_ldm3_ia_update" | ||
| 2487 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2488 | + [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 2489 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) | ||
| 2490 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2491 | + (mem:SI (match_dup 2))) | ||
| 2492 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2493 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2494 | + (const_int 4)))) | ||
| 2495 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2496 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2497 | + (const_int 8))))])] | ||
| 2498 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" | ||
| 2499 | + "ldm%(ia%)\t%1!, {%3, %4, %5}" | ||
| 2500 | + [(set_attr "type" "load3")]) | ||
| 2501 | + | ||
| 2502 | +(define_insn "*stm3_ia" | ||
| 2503 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2504 | + [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk")) | ||
| 2505 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2506 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | ||
| 2507 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2508 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 2509 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2510 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 2511 | + "stm%(ia%)\t%1, {%2, %3, %4}" | ||
| 2512 | + [(set_attr "type" "store3") | ||
| 2513 | + (set_attr "predicable" "yes")]) | ||
| 2514 | + | ||
| 2515 | +(define_insn "*stm3_ia_update" | ||
| 2516 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2517 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2518 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) | ||
| 2519 | + (set (mem:SI (match_dup 2)) | ||
| 2520 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2521 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2522 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2523 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2524 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2525 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2526 | + "stm%(ia%)\t%1!, {%3, %4, %5}" | ||
| 2527 | + [(set_attr "type" "store3") | ||
| 2528 | + (set_attr "predicable" "yes")]) | ||
| 2529 | + | ||
| 2530 | +(define_insn "*thumb_stm3_ia_update" | ||
| 2531 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2532 | + [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 2533 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) | ||
| 2534 | + (set (mem:SI (match_dup 2)) | ||
| 2535 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2536 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2537 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2538 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2539 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2540 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 4" | ||
| 2541 | + "stm%(ia%)\t%1!, {%3, %4, %5}" | ||
| 2542 | + [(set_attr "type" "store3")]) | ||
| 2543 | + | ||
| 2544 | +(define_insn "*ldm3_ib" | ||
| 2545 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2546 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2547 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2548 | + (const_int 4)))) | ||
| 2549 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2550 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2551 | + (const_int 8)))) | ||
| 2552 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2553 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2554 | + (const_int 12))))])] | ||
| 2555 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2556 | + "ldm%(ib%)\t%1, {%2, %3, %4}" | ||
| 2557 | + [(set_attr "type" "load3") | ||
| 2558 | + (set_attr "predicable" "yes")]) | ||
| 2559 | + | ||
| 2560 | +(define_insn "*ldm3_ib_update" | ||
| 2561 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2562 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2563 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) | ||
| 2564 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2565 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2566 | + (const_int 4)))) | ||
| 2567 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2568 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2569 | + (const_int 8)))) | ||
| 2570 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2571 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2572 | + (const_int 12))))])] | ||
| 2573 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2574 | + "ldm%(ib%)\t%1!, {%3, %4, %5}" | ||
| 2575 | + [(set_attr "type" "load3") | ||
| 2576 | + (set_attr "predicable" "yes")]) | ||
| 2577 | + | ||
| 2578 | +(define_insn "*stm3_ib" | ||
| 2579 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2580 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4))) | ||
| 2581 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2582 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 2583 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2584 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | ||
| 2585 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2586 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2587 | + "stm%(ib%)\t%1, {%2, %3, %4}" | ||
| 2588 | + [(set_attr "type" "store3") | ||
| 2589 | + (set_attr "predicable" "yes")]) | ||
| 2590 | + | ||
| 2591 | +(define_insn "*stm3_ib_update" | ||
| 2592 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2593 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2594 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) | ||
| 2595 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2596 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2597 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2598 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2599 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) | ||
| 2600 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2601 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2602 | + "stm%(ib%)\t%1!, {%3, %4, %5}" | ||
| 2603 | + [(set_attr "type" "store3") | ||
| 2604 | + (set_attr "predicable" "yes")]) | ||
| 2605 | + | ||
| 2606 | +(define_insn "*ldm3_da" | ||
| 2607 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2608 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2609 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2610 | + (const_int -8)))) | ||
| 2611 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2612 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2613 | + (const_int -4)))) | ||
| 2614 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2615 | + (mem:SI (match_dup 1)))])] | ||
| 2616 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2617 | + "ldm%(da%)\t%1, {%2, %3, %4}" | ||
| 2618 | + [(set_attr "type" "load3") | ||
| 2619 | + (set_attr "predicable" "yes")]) | ||
| 2620 | + | ||
| 2621 | +(define_insn "*ldm3_da_update" | ||
| 2622 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2623 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2624 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12))) | ||
| 2625 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2626 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2627 | + (const_int -8)))) | ||
| 2628 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2629 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2630 | + (const_int -4)))) | ||
| 2631 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2632 | + (mem:SI (match_dup 2)))])] | ||
| 2633 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2634 | + "ldm%(da%)\t%1!, {%3, %4, %5}" | ||
| 2635 | + [(set_attr "type" "load3") | ||
| 2636 | + (set_attr "predicable" "yes")]) | ||
| 2637 | + | ||
| 2638 | +(define_insn "*stm3_da" | ||
| 2639 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2640 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -8))) | ||
| 2641 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2642 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) | ||
| 2643 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2644 | + (set (mem:SI (match_dup 1)) | ||
| 2645 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2646 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2647 | + "stm%(da%)\t%1, {%2, %3, %4}" | ||
| 2648 | + [(set_attr "type" "store3") | ||
| 2649 | + (set_attr "predicable" "yes")]) | ||
| 2650 | + | ||
| 2651 | +(define_insn "*stm3_da_update" | ||
| 2652 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2653 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2654 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12))) | ||
| 2655 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) | ||
| 2656 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2657 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) | ||
| 2658 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2659 | + (set (mem:SI (match_dup 2)) | ||
| 2660 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2661 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 4" | ||
| 2662 | + "stm%(da%)\t%1!, {%3, %4, %5}" | ||
| 2663 | + [(set_attr "type" "store3") | ||
| 2664 | + (set_attr "predicable" "yes")]) | ||
| 2665 | + | ||
| 2666 | +(define_insn "*ldm3_db" | ||
| 2667 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2668 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2669 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2670 | + (const_int -12)))) | ||
| 2671 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2672 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2673 | + (const_int -8)))) | ||
| 2674 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2675 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2676 | + (const_int -4))))])] | ||
| 2677 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 2678 | + "ldm%(db%)\t%1, {%2, %3, %4}" | ||
| 2679 | + [(set_attr "type" "load3") | ||
| 2680 | + (set_attr "predicable" "yes")]) | ||
| 2681 | + | ||
| 2682 | +(define_insn "*ldm3_db_update" | ||
| 2683 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2684 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2685 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12))) | ||
| 2686 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2687 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2688 | + (const_int -12)))) | ||
| 2689 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2690 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2691 | + (const_int -8)))) | ||
| 2692 | + (set (match_operand:SI 5 "arm_hard_register_operand" "") | ||
| 2693 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2694 | + (const_int -4))))])] | ||
| 2695 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2696 | + "ldm%(db%)\t%1!, {%3, %4, %5}" | ||
| 2697 | + [(set_attr "type" "load3") | ||
| 2698 | + (set_attr "predicable" "yes")]) | ||
| 2699 | + | ||
| 2700 | +(define_insn "*stm3_db" | ||
| 2701 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2702 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -12))) | ||
| 2703 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2704 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -8))) | ||
| 2705 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2706 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) | ||
| 2707 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2708 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 2709 | + "stm%(db%)\t%1, {%2, %3, %4}" | ||
| 2710 | + [(set_attr "type" "store3") | ||
| 2711 | + (set_attr "predicable" "yes")]) | ||
| 2712 | + | ||
| 2713 | +(define_insn "*stm3_db_update" | ||
| 2714 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2715 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2716 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -12))) | ||
| 2717 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -12))) | ||
| 2718 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2719 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) | ||
| 2720 | + (match_operand:SI 4 "arm_hard_register_operand" "")) | ||
| 2721 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) | ||
| 2722 | + (match_operand:SI 5 "arm_hard_register_operand" ""))])] | ||
| 2723 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" | ||
| 2724 | + "stm%(db%)\t%1!, {%3, %4, %5}" | ||
| 2725 | + [(set_attr "type" "store3") | ||
| 2726 | + (set_attr "predicable" "yes")]) | ||
| 2727 | + | ||
| 2728 | +(define_peephole2 | ||
| 2729 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2730 | + (match_operand:SI 3 "memory_operand" "")) | ||
| 2731 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 2732 | + (match_operand:SI 4 "memory_operand" "")) | ||
| 2733 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2734 | + (match_operand:SI 5 "memory_operand" ""))] | ||
| 2735 | + "" | ||
| 2736 | + [(const_int 0)] | ||
| 2737 | +{ | ||
| 2738 | + if (gen_ldm_seq (operands, 3, false)) | ||
| 2739 | + DONE; | ||
| 2740 | + else | ||
| 2741 | + FAIL; | ||
| 2742 | +}) | ||
| 2743 | + | ||
| 2744 | +(define_peephole2 | ||
| 2745 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2746 | + (match_operand:SI 3 "memory_operand" "")) | ||
| 2747 | + (parallel | ||
| 2748 | + [(set (match_operand:SI 1 "s_register_operand" "") | ||
| 2749 | + (match_operand:SI 4 "memory_operand" "")) | ||
| 2750 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2751 | + (match_operand:SI 5 "memory_operand" ""))])] | ||
| 2752 | + "" | ||
| 2753 | + [(const_int 0)] | ||
| 2754 | +{ | ||
| 2755 | + if (gen_ldm_seq (operands, 3, false)) | ||
| 2756 | + DONE; | ||
| 2757 | + else | ||
| 2758 | + FAIL; | ||
| 2759 | +}) | ||
| 2760 | + | ||
| 2761 | +(define_peephole2 | ||
| 2762 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2763 | + (match_operand:SI 6 "const_int_operand" "")) | ||
| 2764 | + (set (match_operand:SI 3 "memory_operand" "") | ||
| 2765 | + (match_dup 0)) | ||
| 2766 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 2767 | + (match_operand:SI 7 "const_int_operand" "")) | ||
| 2768 | + (set (match_operand:SI 4 "memory_operand" "") | ||
| 2769 | + (match_dup 1)) | ||
| 2770 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2771 | + (match_operand:SI 8 "const_int_operand" "")) | ||
| 2772 | + (set (match_operand:SI 5 "memory_operand" "") | ||
| 2773 | + (match_dup 2))] | ||
| 2774 | + "" | ||
| 2775 | + [(const_int 0)] | ||
| 2776 | +{ | ||
| 2777 | + if (gen_const_stm_seq (operands, 3)) | ||
| 2778 | + DONE; | ||
| 2779 | + else | ||
| 2780 | + FAIL; | ||
| 2781 | +}) | ||
| 2782 | + | ||
| 2783 | +(define_peephole2 | ||
| 2784 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 2785 | + (match_operand:SI 6 "const_int_operand" "")) | ||
| 2786 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 2787 | + (match_operand:SI 7 "const_int_operand" "")) | ||
| 2788 | + (set (match_operand:SI 2 "s_register_operand" "") | ||
| 2789 | + (match_operand:SI 8 "const_int_operand" "")) | ||
| 2790 | + (set (match_operand:SI 3 "memory_operand" "") | ||
| 2791 | + (match_dup 0)) | ||
| 2792 | + (set (match_operand:SI 4 "memory_operand" "") | ||
| 2793 | + (match_dup 1)) | ||
| 2794 | + (set (match_operand:SI 5 "memory_operand" "") | ||
| 2795 | + (match_dup 2))] | ||
| 2796 | + "" | ||
| 2797 | + [(const_int 0)] | ||
| 2798 | +{ | ||
| 2799 | + if (gen_const_stm_seq (operands, 3)) | ||
| 2800 | + DONE; | ||
| 2801 | + else | ||
| 2802 | + FAIL; | ||
| 2803 | +}) | ||
| 2804 | + | ||
| 2805 | +(define_peephole2 | ||
| 2806 | + [(set (match_operand:SI 3 "memory_operand" "") | ||
| 2807 | + (match_operand:SI 0 "s_register_operand" "")) | ||
| 2808 | + (set (match_operand:SI 4 "memory_operand" "") | ||
| 2809 | + (match_operand:SI 1 "s_register_operand" "")) | ||
| 2810 | + (set (match_operand:SI 5 "memory_operand" "") | ||
| 2811 | + (match_operand:SI 2 "s_register_operand" ""))] | ||
| 2812 | + "" | ||
| 2813 | + [(const_int 0)] | ||
| 2814 | +{ | ||
| 2815 | + if (gen_stm_seq (operands, 3)) | ||
| 2816 | + DONE; | ||
| 2817 | + else | ||
| 2818 | + FAIL; | ||
| 2819 | +}) | ||
| 2820 | + | ||
| 2821 | +(define_insn "*ldm2_ia" | ||
| 2822 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2823 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2824 | + (mem:SI (match_operand:SI 1 "s_register_operand" "rk"))) | ||
| 2825 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2826 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2827 | + (const_int 4))))])] | ||
| 2828 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" | ||
| 2829 | + "ldm%(ia%)\t%1, {%2, %3}" | ||
| 2830 | + [(set_attr "type" "load2") | ||
| 2831 | + (set_attr "predicable" "yes")]) | ||
| 2832 | + | ||
| 2833 | +(define_insn "*thumb_ldm2_ia" | ||
| 2834 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2835 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2836 | + (mem:SI (match_operand:SI 1 "s_register_operand" "l"))) | ||
| 2837 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2838 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2839 | + (const_int 4))))])] | ||
| 2840 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 2" | ||
| 2841 | + "ldm%(ia%)\t%1, {%2, %3}" | ||
| 2842 | + [(set_attr "type" "load2")]) | ||
| 2843 | + | ||
| 2844 | +(define_insn "*ldm2_ia_update" | ||
| 2845 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2846 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2847 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) | ||
| 2848 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2849 | + (mem:SI (match_dup 2))) | ||
| 2850 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2851 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2852 | + (const_int 4))))])] | ||
| 2853 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 2854 | + "ldm%(ia%)\t%1!, {%3, %4}" | ||
| 2855 | + [(set_attr "type" "load2") | ||
| 2856 | + (set_attr "predicable" "yes")]) | ||
| 2857 | + | ||
| 2858 | +(define_insn "*thumb_ldm2_ia_update" | ||
| 2859 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2860 | + [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 2861 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) | ||
| 2862 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2863 | + (mem:SI (match_dup 2))) | ||
| 2864 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2865 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2866 | + (const_int 4))))])] | ||
| 2867 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" | ||
| 2868 | + "ldm%(ia%)\t%1!, {%3, %4}" | ||
| 2869 | + [(set_attr "type" "load2")]) | ||
| 2870 | + | ||
| 2871 | +(define_insn "*stm2_ia" | ||
| 2872 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2873 | + [(set (mem:SI (match_operand:SI 1 "s_register_operand" "rk")) | ||
| 2874 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2875 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | ||
| 2876 | + (match_operand:SI 3 "arm_hard_register_operand" ""))])] | ||
| 2877 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" | ||
| 2878 | + "stm%(ia%)\t%1, {%2, %3}" | ||
| 2879 | + [(set_attr "type" "store2") | ||
| 2880 | + (set_attr "predicable" "yes")]) | ||
| 2881 | + | ||
| 2882 | +(define_insn "*stm2_ia_update" | ||
| 2883 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2884 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2885 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) | ||
| 2886 | + (set (mem:SI (match_dup 2)) | ||
| 2887 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2888 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2889 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2890 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 2891 | + "stm%(ia%)\t%1!, {%3, %4}" | ||
| 2892 | + [(set_attr "type" "store2") | ||
| 2893 | + (set_attr "predicable" "yes")]) | ||
| 2894 | + | ||
| 2895 | +(define_insn "*thumb_stm2_ia_update" | ||
| 2896 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2897 | + [(set (match_operand:SI 1 "s_register_operand" "=l") | ||
| 2898 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) | ||
| 2899 | + (set (mem:SI (match_dup 2)) | ||
| 2900 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2901 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2902 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2903 | + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 3" | ||
| 2904 | + "stm%(ia%)\t%1!, {%3, %4}" | ||
| 2905 | + [(set_attr "type" "store2")]) | ||
| 2906 | + | ||
| 2907 | +(define_insn "*ldm2_ib" | ||
| 2908 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2909 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2910 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2911 | + (const_int 4)))) | ||
| 2912 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2913 | + (mem:SI (plus:SI (match_dup 1) | ||
| 2914 | + (const_int 8))))])] | ||
| 2915 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 2" | ||
| 2916 | + "ldm%(ib%)\t%1, {%2, %3}" | ||
| 2917 | + [(set_attr "type" "load2") | ||
| 2918 | + (set_attr "predicable" "yes")]) | ||
| 2919 | + | ||
| 2920 | +(define_insn "*ldm2_ib_update" | ||
| 2921 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2922 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2923 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) | ||
| 2924 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2925 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2926 | + (const_int 4)))) | ||
| 2927 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2928 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2929 | + (const_int 8))))])] | ||
| 2930 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2931 | + "ldm%(ib%)\t%1!, {%3, %4}" | ||
| 2932 | + [(set_attr "type" "load2") | ||
| 2933 | + (set_attr "predicable" "yes")]) | ||
| 2934 | + | ||
| 2935 | +(define_insn "*stm2_ib" | ||
| 2936 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2937 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int 4))) | ||
| 2938 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2939 | + (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | ||
| 2940 | + (match_operand:SI 3 "arm_hard_register_operand" ""))])] | ||
| 2941 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 2" | ||
| 2942 | + "stm%(ib%)\t%1, {%2, %3}" | ||
| 2943 | + [(set_attr "type" "store2") | ||
| 2944 | + (set_attr "predicable" "yes")]) | ||
| 2945 | + | ||
| 2946 | +(define_insn "*stm2_ib_update" | ||
| 2947 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2948 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2949 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) | ||
| 2950 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) | ||
| 2951 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 2952 | + (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) | ||
| 2953 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 2954 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2955 | + "stm%(ib%)\t%1!, {%3, %4}" | ||
| 2956 | + [(set_attr "type" "store2") | ||
| 2957 | + (set_attr "predicable" "yes")]) | ||
| 2958 | + | ||
| 2959 | +(define_insn "*ldm2_da" | ||
| 2960 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2961 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 2962 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 2963 | + (const_int -4)))) | ||
| 2964 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2965 | + (mem:SI (match_dup 1)))])] | ||
| 2966 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 2" | ||
| 2967 | + "ldm%(da%)\t%1, {%2, %3}" | ||
| 2968 | + [(set_attr "type" "load2") | ||
| 2969 | + (set_attr "predicable" "yes")]) | ||
| 2970 | + | ||
| 2971 | +(define_insn "*ldm2_da_update" | ||
| 2972 | + [(match_parallel 0 "load_multiple_operation" | ||
| 2973 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2974 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8))) | ||
| 2975 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 2976 | + (mem:SI (plus:SI (match_dup 2) | ||
| 2977 | + (const_int -4)))) | ||
| 2978 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 2979 | + (mem:SI (match_dup 2)))])] | ||
| 2980 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 2981 | + "ldm%(da%)\t%1!, {%3, %4}" | ||
| 2982 | + [(set_attr "type" "load2") | ||
| 2983 | + (set_attr "predicable" "yes")]) | ||
| 2984 | + | ||
| 2985 | +(define_insn "*stm2_da" | ||
| 2986 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2987 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -4))) | ||
| 2988 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 2989 | + (set (mem:SI (match_dup 1)) | ||
| 2990 | + (match_operand:SI 3 "arm_hard_register_operand" ""))])] | ||
| 2991 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 2" | ||
| 2992 | + "stm%(da%)\t%1, {%2, %3}" | ||
| 2993 | + [(set_attr "type" "store2") | ||
| 2994 | + (set_attr "predicable" "yes")]) | ||
| 2995 | + | ||
| 2996 | +(define_insn "*stm2_da_update" | ||
| 2997 | + [(match_parallel 0 "store_multiple_operation" | ||
| 2998 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 2999 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8))) | ||
| 3000 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) | ||
| 3001 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 3002 | + (set (mem:SI (match_dup 2)) | ||
| 3003 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 3004 | + "TARGET_ARM && XVECLEN (operands[0], 0) == 3" | ||
| 3005 | + "stm%(da%)\t%1!, {%3, %4}" | ||
| 3006 | + [(set_attr "type" "store2") | ||
| 3007 | + (set_attr "predicable" "yes")]) | ||
| 3008 | + | ||
| 3009 | +(define_insn "*ldm2_db" | ||
| 3010 | + [(match_parallel 0 "load_multiple_operation" | ||
| 3011 | + [(set (match_operand:SI 2 "arm_hard_register_operand" "") | ||
| 3012 | + (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") | ||
| 3013 | + (const_int -8)))) | ||
| 3014 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 3015 | + (mem:SI (plus:SI (match_dup 1) | ||
| 3016 | + (const_int -4))))])] | ||
| 3017 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" | ||
| 3018 | + "ldm%(db%)\t%1, {%2, %3}" | ||
| 3019 | + [(set_attr "type" "load2") | ||
| 3020 | + (set_attr "predicable" "yes")]) | ||
| 3021 | + | ||
| 3022 | +(define_insn "*ldm2_db_update" | ||
| 3023 | + [(match_parallel 0 "load_multiple_operation" | ||
| 3024 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 3025 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8))) | ||
| 3026 | + (set (match_operand:SI 3 "arm_hard_register_operand" "") | ||
| 3027 | + (mem:SI (plus:SI (match_dup 2) | ||
| 3028 | + (const_int -8)))) | ||
| 3029 | + (set (match_operand:SI 4 "arm_hard_register_operand" "") | ||
| 3030 | + (mem:SI (plus:SI (match_dup 2) | ||
| 3031 | + (const_int -4))))])] | ||
| 3032 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 3033 | + "ldm%(db%)\t%1!, {%3, %4}" | ||
| 3034 | + [(set_attr "type" "load2") | ||
| 3035 | + (set_attr "predicable" "yes")]) | ||
| 3036 | + | ||
| 3037 | +(define_insn "*stm2_db" | ||
| 3038 | + [(match_parallel 0 "store_multiple_operation" | ||
| 3039 | + [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "rk") (const_int -8))) | ||
| 3040 | + (match_operand:SI 2 "arm_hard_register_operand" "")) | ||
| 3041 | + (set (mem:SI (plus:SI (match_dup 1) (const_int -4))) | ||
| 3042 | + (match_operand:SI 3 "arm_hard_register_operand" ""))])] | ||
| 3043 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" | ||
| 3044 | + "stm%(db%)\t%1, {%2, %3}" | ||
| 3045 | + [(set_attr "type" "store2") | ||
| 3046 | + (set_attr "predicable" "yes")]) | ||
| 3047 | + | ||
| 3048 | +(define_insn "*stm2_db_update" | ||
| 3049 | + [(match_parallel 0 "store_multiple_operation" | ||
| 3050 | + [(set (match_operand:SI 1 "s_register_operand" "=rk") | ||
| 3051 | + (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int -8))) | ||
| 3052 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -8))) | ||
| 3053 | + (match_operand:SI 3 "arm_hard_register_operand" "")) | ||
| 3054 | + (set (mem:SI (plus:SI (match_dup 2) (const_int -4))) | ||
| 3055 | + (match_operand:SI 4 "arm_hard_register_operand" ""))])] | ||
| 3056 | + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" | ||
| 3057 | + "stm%(db%)\t%1!, {%3, %4}" | ||
| 3058 | + [(set_attr "type" "store2") | ||
| 3059 | + (set_attr "predicable" "yes")]) | ||
| 3060 | + | ||
| 3061 | +(define_peephole2 | ||
| 3062 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 3063 | + (match_operand:SI 2 "memory_operand" "")) | ||
| 3064 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 3065 | + (match_operand:SI 3 "memory_operand" ""))] | ||
| 3066 | + "" | ||
| 3067 | + [(const_int 0)] | ||
| 3068 | +{ | ||
| 3069 | + if (gen_ldm_seq (operands, 2, false)) | ||
| 3070 | + DONE; | ||
| 3071 | + else | ||
| 3072 | + FAIL; | ||
| 3073 | +}) | ||
| 3074 | + | ||
| 3075 | +(define_peephole2 | ||
| 3076 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 3077 | + (match_operand:SI 4 "const_int_operand" "")) | ||
| 3078 | + (set (match_operand:SI 2 "memory_operand" "") | ||
| 3079 | + (match_dup 0)) | ||
| 3080 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 3081 | + (match_operand:SI 5 "const_int_operand" "")) | ||
| 3082 | + (set (match_operand:SI 3 "memory_operand" "") | ||
| 3083 | + (match_dup 1))] | ||
| 3084 | + "" | ||
| 3085 | + [(const_int 0)] | ||
| 3086 | +{ | ||
| 3087 | + if (gen_const_stm_seq (operands, 2)) | ||
| 3088 | + DONE; | ||
| 3089 | + else | ||
| 3090 | + FAIL; | ||
| 3091 | +}) | ||
| 3092 | + | ||
| 3093 | +(define_peephole2 | ||
| 3094 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 3095 | + (match_operand:SI 4 "const_int_operand" "")) | ||
| 3096 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 3097 | + (match_operand:SI 5 "const_int_operand" "")) | ||
| 3098 | + (set (match_operand:SI 2 "memory_operand" "") | ||
| 3099 | + (match_dup 0)) | ||
| 3100 | + (set (match_operand:SI 3 "memory_operand" "") | ||
| 3101 | + (match_dup 1))] | ||
| 3102 | + "" | ||
| 3103 | + [(const_int 0)] | ||
| 3104 | +{ | ||
| 3105 | + if (gen_const_stm_seq (operands, 2)) | ||
| 3106 | + DONE; | ||
| 3107 | + else | ||
| 3108 | + FAIL; | ||
| 3109 | +}) | ||
| 3110 | + | ||
| 3111 | +(define_peephole2 | ||
| 3112 | + [(set (match_operand:SI 2 "memory_operand" "") | ||
| 3113 | + (match_operand:SI 0 "s_register_operand" "")) | ||
| 3114 | + (set (match_operand:SI 3 "memory_operand" "") | ||
| 3115 | + (match_operand:SI 1 "s_register_operand" ""))] | ||
| 3116 | + "" | ||
| 3117 | + [(const_int 0)] | ||
| 3118 | +{ | ||
| 3119 | + if (gen_stm_seq (operands, 2)) | ||
| 3120 | + DONE; | ||
| 3121 | + else | ||
| 3122 | + FAIL; | ||
| 3123 | +}) | ||
| 3124 | + | ||
| 3125 | +(define_peephole2 | ||
| 3126 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 3127 | + (match_operand:SI 2 "memory_operand" "")) | ||
| 3128 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 3129 | + (match_operand:SI 3 "memory_operand" "")) | ||
| 3130 | + (parallel | ||
| 3131 | + [(set (match_operand:SI 4 "s_register_operand" "") | ||
| 3132 | + (match_operator:SI 5 "commutative_binary_operator" | ||
| 3133 | + [(match_operand:SI 6 "s_register_operand" "") | ||
| 3134 | + (match_operand:SI 7 "s_register_operand" "")])) | ||
| 3135 | + (clobber (reg:CC CC_REGNUM))])] | ||
| 3136 | + "(((operands[6] == operands[0] && operands[7] == operands[1]) | ||
| 3137 | + || (operands[7] == operands[0] && operands[6] == operands[1])) | ||
| 3138 | + && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[1]))" | ||
| 3139 | + [(parallel | ||
| 3140 | + [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)])) | ||
| 3141 | + (clobber (reg:CC CC_REGNUM))])] | ||
| 3142 | +{ | ||
| 3143 | + if (!gen_ldm_seq (operands, 2, true)) | ||
| 3144 | + FAIL; | ||
| 3145 | +}) | ||
| 3146 | + | ||
| 3147 | +(define_peephole2 | ||
| 3148 | + [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 3149 | + (match_operand:SI 2 "memory_operand" "")) | ||
| 3150 | + (set (match_operand:SI 1 "s_register_operand" "") | ||
| 3151 | + (match_operand:SI 3 "memory_operand" "")) | ||
| 3152 | + (set (match_operand:SI 4 "s_register_operand" "") | ||
| 3153 | + (match_operator:SI 5 "commutative_binary_operator" | ||
| 3154 | + [(match_operand:SI 6 "s_register_operand" "") | ||
| 3155 | + (match_operand:SI 7 "s_register_operand" "")]))] | ||
| 3156 | + "(((operands[6] == operands[0] && operands[7] == operands[1]) | ||
| 3157 | + || (operands[7] == operands[0] && operands[6] == operands[1])) | ||
| 3158 | + && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[1]))" | ||
| 3159 | + [(set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))] | ||
| 3160 | +{ | ||
| 3161 | + if (!gen_ldm_seq (operands, 2, true)) | ||
| 3162 | + FAIL; | ||
| 3163 | +}) | ||
| 3164 | + | ||
| 3165 | Index: gcc-4_5-branch/gcc/config/arm/predicates.md | ||
| 3166 | =================================================================== | ||
| 3167 | --- gcc-4_5-branch.orig/gcc/config/arm/predicates.md 2012-03-06 12:47:54.000000000 -0800 | ||
| 3168 | +++ gcc-4_5-branch/gcc/config/arm/predicates.md 2012-03-06 12:51:19.992547622 -0800 | ||
| 3169 | @@ -211,6 +211,11 @@ | ||
| 3170 | (and (match_code "ior,xor,and") | ||
| 3171 | (match_test "mode == GET_MODE (op)"))) | ||
| 3172 | |||
| 3173 | +;; True for commutative operators | ||
| 3174 | +(define_special_predicate "commutative_binary_operator" | ||
| 3175 | + (and (match_code "ior,xor,and,plus") | ||
| 3176 | + (match_test "mode == GET_MODE (op)"))) | ||
| 3177 | + | ||
| 3178 | ;; True for shift operators. | ||
| 3179 | (define_special_predicate "shift_operator" | ||
| 3180 | (and (ior (ior (and (match_code "mult") | ||
| 3181 | @@ -334,16 +339,20 @@ | ||
| 3182 | (match_code "parallel") | ||
| 3183 | { | ||
| 3184 | HOST_WIDE_INT count = XVECLEN (op, 0); | ||
| 3185 | - int dest_regno; | ||
| 3186 | + unsigned dest_regno; | ||
| 3187 | rtx src_addr; | ||
| 3188 | HOST_WIDE_INT i = 1, base = 0; | ||
| 3189 | + HOST_WIDE_INT offset = 0; | ||
| 3190 | rtx elt; | ||
| 3191 | + bool addr_reg_loaded = false; | ||
| 3192 | + bool update = false; | ||
| 3193 | |||
| 3194 | if (low_irq_latency) | ||
| 3195 | return false; | ||
| 3196 | |||
| 3197 | if (count <= 1 | ||
| 3198 | - || GET_CODE (XVECEXP (op, 0, 0)) != SET) | ||
| 3199 | + || GET_CODE (XVECEXP (op, 0, 0)) != SET | ||
| 3200 | + || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))) | ||
| 3201 | return false; | ||
| 3202 | |||
| 3203 | /* Check to see if this might be a write-back. */ | ||
| 3204 | @@ -351,6 +360,7 @@ | ||
| 3205 | { | ||
| 3206 | i++; | ||
| 3207 | base = 1; | ||
| 3208 | + update = true; | ||
| 3209 | |||
| 3210 | /* Now check it more carefully. */ | ||
| 3211 | if (GET_CODE (SET_DEST (elt)) != REG | ||
| 3212 | @@ -369,6 +379,15 @@ | ||
| 3213 | |||
| 3214 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); | ||
| 3215 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); | ||
| 3216 | + if (GET_CODE (src_addr) == PLUS) | ||
| 3217 | + { | ||
| 3218 | + if (GET_CODE (XEXP (src_addr, 1)) != CONST_INT) | ||
| 3219 | + return false; | ||
| 3220 | + offset = INTVAL (XEXP (src_addr, 1)); | ||
| 3221 | + src_addr = XEXP (src_addr, 0); | ||
| 3222 | + } | ||
| 3223 | + if (!REG_P (src_addr)) | ||
| 3224 | + return false; | ||
| 3225 | |||
| 3226 | for (; i < count; i++) | ||
| 3227 | { | ||
| 3228 | @@ -377,16 +396,28 @@ | ||
| 3229 | if (GET_CODE (elt) != SET | ||
| 3230 | || GET_CODE (SET_DEST (elt)) != REG | ||
| 3231 | || GET_MODE (SET_DEST (elt)) != SImode | ||
| 3232 | - || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base) | ||
| 3233 | + || REGNO (SET_DEST (elt)) <= dest_regno | ||
| 3234 | || GET_CODE (SET_SRC (elt)) != MEM | ||
| 3235 | || GET_MODE (SET_SRC (elt)) != SImode | ||
| 3236 | - || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | ||
| 3237 | - || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | ||
| 3238 | - || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | ||
| 3239 | - || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4) | ||
| 3240 | + || ((GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | ||
| 3241 | + || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | ||
| 3242 | + || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | ||
| 3243 | + || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != offset + (i - base) * 4) | ||
| 3244 | + && (!REG_P (XEXP (SET_SRC (elt), 0)) | ||
| 3245 | + || offset + (i - base) * 4 != 0))) | ||
| 3246 | return false; | ||
| 3247 | + dest_regno = REGNO (SET_DEST (elt)); | ||
| 3248 | + if (dest_regno == REGNO (src_addr)) | ||
| 3249 | + addr_reg_loaded = true; | ||
| 3250 | } | ||
| 3251 | - | ||
| 3252 | + /* For Thumb, we only have updating instructions. If the pattern does | ||
| 3253 | + not describe an update, it must be because the address register is | ||
| 3254 | + in the list of loaded registers - on the hardware, this has the effect | ||
| 3255 | + of overriding the update. */ | ||
| 3256 | + if (update && addr_reg_loaded) | ||
| 3257 | + return false; | ||
| 3258 | + if (TARGET_THUMB1) | ||
| 3259 | + return update || addr_reg_loaded; | ||
| 3260 | return true; | ||
| 3261 | }) | ||
| 3262 | |||
| 3263 | @@ -394,9 +425,9 @@ | ||
| 3264 | (match_code "parallel") | ||
| 3265 | { | ||
| 3266 | HOST_WIDE_INT count = XVECLEN (op, 0); | ||
| 3267 | - int src_regno; | ||
| 3268 | + unsigned src_regno; | ||
| 3269 | rtx dest_addr; | ||
| 3270 | - HOST_WIDE_INT i = 1, base = 0; | ||
| 3271 | + HOST_WIDE_INT i = 1, base = 0, offset = 0; | ||
| 3272 | rtx elt; | ||
| 3273 | |||
| 3274 | if (low_irq_latency) | ||
| 3275 | @@ -430,6 +461,16 @@ | ||
| 3276 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); | ||
| 3277 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); | ||
| 3278 | |||
| 3279 | + if (GET_CODE (dest_addr) == PLUS) | ||
| 3280 | + { | ||
| 3281 | + if (GET_CODE (XEXP (dest_addr, 1)) != CONST_INT) | ||
| 3282 | + return false; | ||
| 3283 | + offset = INTVAL (XEXP (dest_addr, 1)); | ||
| 3284 | + dest_addr = XEXP (dest_addr, 0); | ||
| 3285 | + } | ||
| 3286 | + if (!REG_P (dest_addr)) | ||
| 3287 | + return false; | ||
| 3288 | + | ||
| 3289 | for (; i < count; i++) | ||
| 3290 | { | ||
| 3291 | elt = XVECEXP (op, 0, i); | ||
| 3292 | @@ -437,14 +478,17 @@ | ||
| 3293 | if (GET_CODE (elt) != SET | ||
| 3294 | || GET_CODE (SET_SRC (elt)) != REG | ||
| 3295 | || GET_MODE (SET_SRC (elt)) != SImode | ||
| 3296 | - || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base) | ||
| 3297 | + || REGNO (SET_SRC (elt)) <= src_regno | ||
| 3298 | || GET_CODE (SET_DEST (elt)) != MEM | ||
| 3299 | || GET_MODE (SET_DEST (elt)) != SImode | ||
| 3300 | - || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | ||
| 3301 | - || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | ||
| 3302 | - || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | ||
| 3303 | - || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4) | ||
| 3304 | + || ((GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | ||
| 3305 | + || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | ||
| 3306 | + || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | ||
| 3307 | + || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != offset + (i - base) * 4) | ||
| 3308 | + && (!REG_P (XEXP (SET_DEST (elt), 0)) | ||
| 3309 | + || offset + (i - base) * 4 != 0))) | ||
| 3310 | return false; | ||
| 3311 | + src_regno = REGNO (SET_SRC (elt)); | ||
| 3312 | } | ||
| 3313 | |||
| 3314 | return true; | ||
| 3315 | Index: gcc-4_5-branch/gcc/config/i386/i386.md | ||
| 3316 | =================================================================== | ||
| 3317 | --- gcc-4_5-branch.orig/gcc/config/i386/i386.md 2012-03-06 12:47:55.000000000 -0800 | ||
| 3318 | +++ gcc-4_5-branch/gcc/config/i386/i386.md 2012-03-06 12:51:19.996547605 -0800 | ||
| 3319 | @@ -4960,6 +4960,7 @@ | ||
| 3320 | (set (match_operand:SSEMODEI24 2 "register_operand" "") | ||
| 3321 | (fix:SSEMODEI24 (match_dup 0)))] | ||
| 3322 | "TARGET_SHORTEN_X87_SSE | ||
| 3323 | + && !(TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()) | ||
| 3324 | && peep2_reg_dead_p (2, operands[0])" | ||
| 3325 | [(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))] | ||
| 3326 | "") | ||
| 3327 | @@ -20089,15 +20090,14 @@ | ||
| 3328 | ;; leal (%edx,%eax,4), %eax | ||
| 3329 | |||
| 3330 | (define_peephole2 | ||
| 3331 | - [(parallel [(set (match_operand 0 "register_operand" "") | ||
| 3332 | + [(match_scratch:P 5 "r") | ||
| 3333 | + (parallel [(set (match_operand 0 "register_operand" "") | ||
| 3334 | (ashift (match_operand 1 "register_operand" "") | ||
| 3335 | (match_operand 2 "const_int_operand" ""))) | ||
| 3336 | (clobber (reg:CC FLAGS_REG))]) | ||
| 3337 | - (set (match_operand 3 "register_operand") | ||
| 3338 | - (match_operand 4 "x86_64_general_operand" "")) | ||
| 3339 | - (parallel [(set (match_operand 5 "register_operand" "") | ||
| 3340 | - (plus (match_operand 6 "register_operand" "") | ||
| 3341 | - (match_operand 7 "register_operand" ""))) | ||
| 3342 | + (parallel [(set (match_operand 3 "register_operand" "") | ||
| 3343 | + (plus (match_dup 0) | ||
| 3344 | + (match_operand 4 "x86_64_general_operand" ""))) | ||
| 3345 | (clobber (reg:CC FLAGS_REG))])] | ||
| 3346 | "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3 | ||
| 3347 | /* Validate MODE for lea. */ | ||
| 3348 | @@ -20106,31 +20106,27 @@ | ||
| 3349 | || GET_MODE (operands[0]) == HImode)) | ||
| 3350 | || GET_MODE (operands[0]) == SImode | ||
| 3351 | || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)) | ||
| 3352 | + && (rtx_equal_p (operands[0], operands[3]) | ||
| 3353 | + || peep2_reg_dead_p (2, operands[0])) | ||
| 3354 | /* We reorder load and the shift. */ | ||
| 3355 | - && !rtx_equal_p (operands[1], operands[3]) | ||
| 3356 | - && !reg_overlap_mentioned_p (operands[0], operands[4]) | ||
| 3357 | - /* Last PLUS must consist of operand 0 and 3. */ | ||
| 3358 | - && !rtx_equal_p (operands[0], operands[3]) | ||
| 3359 | - && (rtx_equal_p (operands[3], operands[6]) | ||
| 3360 | - || rtx_equal_p (operands[3], operands[7])) | ||
| 3361 | - && (rtx_equal_p (operands[0], operands[6]) | ||
| 3362 | - || rtx_equal_p (operands[0], operands[7])) | ||
| 3363 | - /* The intermediate operand 0 must die or be same as output. */ | ||
| 3364 | - && (rtx_equal_p (operands[0], operands[5]) | ||
| 3365 | - || peep2_reg_dead_p (3, operands[0]))" | ||
| 3366 | - [(set (match_dup 3) (match_dup 4)) | ||
| 3367 | + && !reg_overlap_mentioned_p (operands[0], operands[4])" | ||
| 3368 | + [(set (match_dup 5) (match_dup 4)) | ||
| 3369 | (set (match_dup 0) (match_dup 1))] | ||
| 3370 | { | ||
| 3371 | - enum machine_mode mode = GET_MODE (operands[5]) == DImode ? DImode : SImode; | ||
| 3372 | + enum machine_mode mode = GET_MODE (operands[1]) == DImode ? DImode : SImode; | ||
| 3373 | int scale = 1 << INTVAL (operands[2]); | ||
| 3374 | rtx index = gen_lowpart (Pmode, operands[1]); | ||
| 3375 | - rtx base = gen_lowpart (Pmode, operands[3]); | ||
| 3376 | - rtx dest = gen_lowpart (mode, operands[5]); | ||
| 3377 | + rtx base = gen_lowpart (Pmode, operands[5]); | ||
| 3378 | + rtx dest = gen_lowpart (mode, operands[3]); | ||
| 3379 | |||
| 3380 | operands[1] = gen_rtx_PLUS (Pmode, base, | ||
| 3381 | gen_rtx_MULT (Pmode, index, GEN_INT (scale))); | ||
| 3382 | + operands[5] = base; | ||
| 3383 | if (mode != Pmode) | ||
| 3384 | - operands[1] = gen_rtx_SUBREG (mode, operands[1], 0); | ||
| 3385 | + { | ||
| 3386 | + operands[1] = gen_rtx_SUBREG (mode, operands[1], 0); | ||
| 3387 | + operands[5] = gen_rtx_SUBREG (mode, operands[5], 0); | ||
| 3388 | + } | ||
| 3389 | operands[0] = dest; | ||
| 3390 | }) | ||
| 3391 | |||
| 3392 | Index: gcc-4_5-branch/gcc/genoutput.c | ||
| 3393 | =================================================================== | ||
| 3394 | --- gcc-4_5-branch.orig/gcc/genoutput.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 3395 | +++ gcc-4_5-branch/gcc/genoutput.c 2012-03-06 12:51:20.000547582 -0800 | ||
| 3396 | @@ -266,6 +266,8 @@ | ||
| 3397 | |||
| 3398 | printf (" %d,\n", d->strict_low); | ||
| 3399 | |||
| 3400 | + printf (" %d,\n", d->constraint == NULL ? 1 : 0); | ||
| 3401 | + | ||
| 3402 | printf (" %d\n", d->eliminable); | ||
| 3403 | |||
| 3404 | printf(" },\n"); | ||
| 3405 | Index: gcc-4_5-branch/gcc/genrecog.c | ||
| 3406 | =================================================================== | ||
| 3407 | --- gcc-4_5-branch.orig/gcc/genrecog.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 3408 | +++ gcc-4_5-branch/gcc/genrecog.c 2012-03-06 12:51:20.000547582 -0800 | ||
| 3409 | @@ -1782,20 +1782,11 @@ | ||
| 3410 | int odepth = strlen (oldpos); | ||
| 3411 | int ndepth = strlen (newpos); | ||
| 3412 | int depth; | ||
| 3413 | - int old_has_insn, new_has_insn; | ||
| 3414 | |||
| 3415 | /* Pop up as many levels as necessary. */ | ||
| 3416 | for (depth = odepth; strncmp (oldpos, newpos, depth) != 0; --depth) | ||
| 3417 | continue; | ||
| 3418 | |||
| 3419 | - /* Hunt for the last [A-Z] in both strings. */ | ||
| 3420 | - for (old_has_insn = odepth - 1; old_has_insn >= 0; --old_has_insn) | ||
| 3421 | - if (ISUPPER (oldpos[old_has_insn])) | ||
| 3422 | - break; | ||
| 3423 | - for (new_has_insn = ndepth - 1; new_has_insn >= 0; --new_has_insn) | ||
| 3424 | - if (ISUPPER (newpos[new_has_insn])) | ||
| 3425 | - break; | ||
| 3426 | - | ||
| 3427 | /* Go down to desired level. */ | ||
| 3428 | while (depth < ndepth) | ||
| 3429 | { | ||
| 3430 | Index: gcc-4_5-branch/gcc/recog.c | ||
| 3431 | =================================================================== | ||
| 3432 | --- gcc-4_5-branch.orig/gcc/recog.c 2012-03-06 12:47:48.000000000 -0800 | ||
| 3433 | +++ gcc-4_5-branch/gcc/recog.c 2012-03-06 13:04:05.780584592 -0800 | ||
| 3434 | @@ -2082,6 +2082,7 @@ | ||
| 3435 | recog_data.operand_loc, | ||
| 3436 | recog_data.constraints, | ||
| 3437 | recog_data.operand_mode, NULL); | ||
| 3438 | + memset (recog_data.is_operator, 0, sizeof recog_data.is_operator); | ||
| 3439 | if (noperands > 0) | ||
| 3440 | { | ||
| 3441 | const char *p = recog_data.constraints[0]; | ||
| 3442 | @@ -2111,6 +2112,7 @@ | ||
| 3443 | for (i = 0; i < noperands; i++) | ||
| 3444 | { | ||
| 3445 | recog_data.constraints[i] = insn_data[icode].operand[i].constraint; | ||
| 3446 | + recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator; | ||
| 3447 | recog_data.operand_mode[i] = insn_data[icode].operand[i].mode; | ||
| 3448 | /* VOIDmode match_operands gets mode from their real operand. */ | ||
| 3449 | if (recog_data.operand_mode[i] == VOIDmode) | ||
| 3450 | @@ -2909,6 +2911,10 @@ | ||
| 3451 | |||
| 3452 | static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1]; | ||
| 3453 | static int peep2_current; | ||
| 3454 | + | ||
| 3455 | +static bool peep2_do_rebuild_jump_labels; | ||
| 3456 | +static bool peep2_do_cleanup_cfg; | ||
| 3457 | + | ||
| 3458 | /* The number of instructions available to match a peep2. */ | ||
| 3459 | int peep2_current_count; | ||
| 3460 | |||
| 3461 | @@ -2917,6 +2923,16 @@ | ||
| 3462 | DF_LIVE_OUT for the block. */ | ||
| 3463 | #define PEEP2_EOB pc_rtx | ||
| 3464 | |||
| 3465 | +/* Wrap N to fit into the peep2_insn_data buffer. */ | ||
| 3466 | + | ||
| 3467 | +static int | ||
| 3468 | +peep2_buf_position (int n) | ||
| 3469 | +{ | ||
| 3470 | + if (n >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3471 | + n -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3472 | + return n; | ||
| 3473 | +} | ||
| 3474 | + | ||
| 3475 | /* Return the Nth non-note insn after `current', or return NULL_RTX if it | ||
| 3476 | does not exist. Used by the recognizer to find the next insn to match | ||
| 3477 | in a multi-insn pattern. */ | ||
| 3478 | @@ -2926,9 +2942,7 @@ | ||
| 3479 | { | ||
| 3480 | gcc_assert (n <= peep2_current_count); | ||
| 3481 | |||
| 3482 | - n += peep2_current; | ||
| 3483 | - if (n >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3484 | - n -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3485 | + n = peep2_buf_position (peep2_current + n); | ||
| 3486 | |||
| 3487 | return peep2_insn_data[n].insn; | ||
| 3488 | } | ||
| 3489 | @@ -2941,9 +2955,7 @@ | ||
| 3490 | { | ||
| 3491 | gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1); | ||
| 3492 | |||
| 3493 | - ofs += peep2_current; | ||
| 3494 | - if (ofs >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3495 | - ofs -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3496 | + ofs = peep2_buf_position (peep2_current + ofs); | ||
| 3497 | |||
| 3498 | gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX); | ||
| 3499 | |||
| 3500 | @@ -2959,9 +2971,7 @@ | ||
| 3501 | |||
| 3502 | gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1); | ||
| 3503 | |||
| 3504 | - ofs += peep2_current; | ||
| 3505 | - if (ofs >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3506 | - ofs -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3507 | + ofs = peep2_buf_position (peep2_current + ofs); | ||
| 3508 | |||
| 3509 | gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX); | ||
| 3510 | |||
| 3511 | @@ -2997,12 +3007,8 @@ | ||
| 3512 | gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1); | ||
| 3513 | gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1); | ||
| 3514 | |||
| 3515 | - from += peep2_current; | ||
| 3516 | - if (from >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3517 | - from -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3518 | - to += peep2_current; | ||
| 3519 | - if (to >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3520 | - to -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3521 | + from = peep2_buf_position (peep2_current + from); | ||
| 3522 | + to = peep2_buf_position (peep2_current + to); | ||
| 3523 | |||
| 3524 | gcc_assert (peep2_insn_data[from].insn != NULL_RTX); | ||
| 3525 | REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before); | ||
| 3526 | @@ -3016,8 +3022,7 @@ | ||
| 3527 | *def_rec; def_rec++) | ||
| 3528 | SET_HARD_REG_BIT (live, DF_REF_REGNO (*def_rec)); | ||
| 3529 | |||
| 3530 | - if (++from >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3531 | - from = 0; | ||
| 3532 | + from = peep2_buf_position (from + 1); | ||
| 3533 | } | ||
| 3534 | |||
| 3535 | cl = (class_str[0] == 'r' ? GENERAL_REGS | ||
| 3536 | @@ -3107,19 +3112,234 @@ | ||
| 3537 | COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live); | ||
| 3538 | } | ||
| 3539 | |||
| 3540 | +/* While scanning basic block BB, we found a match of length MATCH_LEN, | ||
| 3541 | + starting at INSN. Perform the replacement, removing the old insns and | ||
| 3542 | + replacing them with ATTEMPT. Returns the last insn emitted. */ | ||
| 3543 | + | ||
| 3544 | +static rtx | ||
| 3545 | +peep2_attempt (basic_block bb, rtx insn, int match_len, rtx attempt) | ||
| 3546 | +{ | ||
| 3547 | + int i; | ||
| 3548 | + rtx last, note, before_try, x; | ||
| 3549 | + bool was_call = false; | ||
| 3550 | + | ||
| 3551 | + /* If we are splitting a CALL_INSN, look for the CALL_INSN | ||
| 3552 | + in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other | ||
| 3553 | + cfg-related call notes. */ | ||
| 3554 | + for (i = 0; i <= match_len; ++i) | ||
| 3555 | + { | ||
| 3556 | + int j; | ||
| 3557 | + rtx old_insn, new_insn, note; | ||
| 3558 | + | ||
| 3559 | + j = peep2_buf_position (peep2_current + i); | ||
| 3560 | + old_insn = peep2_insn_data[j].insn; | ||
| 3561 | + if (!CALL_P (old_insn)) | ||
| 3562 | + continue; | ||
| 3563 | + was_call = true; | ||
| 3564 | + | ||
| 3565 | + new_insn = attempt; | ||
| 3566 | + while (new_insn != NULL_RTX) | ||
| 3567 | + { | ||
| 3568 | + if (CALL_P (new_insn)) | ||
| 3569 | + break; | ||
| 3570 | + new_insn = NEXT_INSN (new_insn); | ||
| 3571 | + } | ||
| 3572 | + | ||
| 3573 | + gcc_assert (new_insn != NULL_RTX); | ||
| 3574 | + | ||
| 3575 | + CALL_INSN_FUNCTION_USAGE (new_insn) | ||
| 3576 | + = CALL_INSN_FUNCTION_USAGE (old_insn); | ||
| 3577 | + | ||
| 3578 | + for (note = REG_NOTES (old_insn); | ||
| 3579 | + note; | ||
| 3580 | + note = XEXP (note, 1)) | ||
| 3581 | + switch (REG_NOTE_KIND (note)) | ||
| 3582 | + { | ||
| 3583 | + case REG_NORETURN: | ||
| 3584 | + case REG_SETJMP: | ||
| 3585 | + add_reg_note (new_insn, REG_NOTE_KIND (note), | ||
| 3586 | + XEXP (note, 0)); | ||
| 3587 | + break; | ||
| 3588 | + default: | ||
| 3589 | + /* Discard all other reg notes. */ | ||
| 3590 | + break; | ||
| 3591 | + } | ||
| 3592 | + | ||
| 3593 | + /* Croak if there is another call in the sequence. */ | ||
| 3594 | + while (++i <= match_len) | ||
| 3595 | + { | ||
| 3596 | + j = peep2_buf_position (peep2_current + i); | ||
| 3597 | + old_insn = peep2_insn_data[j].insn; | ||
| 3598 | + gcc_assert (!CALL_P (old_insn)); | ||
| 3599 | + } | ||
| 3600 | + break; | ||
| 3601 | + } | ||
| 3602 | + | ||
| 3603 | + i = peep2_buf_position (peep2_current + match_len); | ||
| 3604 | + | ||
| 3605 | + note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX); | ||
| 3606 | + | ||
| 3607 | + /* Replace the old sequence with the new. */ | ||
| 3608 | + last = emit_insn_after_setloc (attempt, | ||
| 3609 | + peep2_insn_data[i].insn, | ||
| 3610 | + INSN_LOCATOR (peep2_insn_data[i].insn)); | ||
| 3611 | + before_try = PREV_INSN (insn); | ||
| 3612 | + delete_insn_chain (insn, peep2_insn_data[i].insn, false); | ||
| 3613 | + | ||
| 3614 | + /* Re-insert the EH_REGION notes. */ | ||
| 3615 | + if (note || (was_call && nonlocal_goto_handler_labels)) | ||
| 3616 | + { | ||
| 3617 | + edge eh_edge; | ||
| 3618 | + edge_iterator ei; | ||
| 3619 | + | ||
| 3620 | + FOR_EACH_EDGE (eh_edge, ei, bb->succs) | ||
| 3621 | + if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL)) | ||
| 3622 | + break; | ||
| 3623 | + | ||
| 3624 | + if (note) | ||
| 3625 | + copy_reg_eh_region_note_backward (note, last, before_try); | ||
| 3626 | + | ||
| 3627 | + if (eh_edge) | ||
| 3628 | + for (x = last; x != before_try; x = PREV_INSN (x)) | ||
| 3629 | + if (x != BB_END (bb) | ||
| 3630 | + && (can_throw_internal (x) | ||
| 3631 | + || can_nonlocal_goto (x))) | ||
| 3632 | + { | ||
| 3633 | + edge nfte, nehe; | ||
| 3634 | + int flags; | ||
| 3635 | + | ||
| 3636 | + nfte = split_block (bb, x); | ||
| 3637 | + flags = (eh_edge->flags | ||
| 3638 | + & (EDGE_EH | EDGE_ABNORMAL)); | ||
| 3639 | + if (CALL_P (x)) | ||
| 3640 | + flags |= EDGE_ABNORMAL_CALL; | ||
| 3641 | + nehe = make_edge (nfte->src, eh_edge->dest, | ||
| 3642 | + flags); | ||
| 3643 | + | ||
| 3644 | + nehe->probability = eh_edge->probability; | ||
| 3645 | + nfte->probability | ||
| 3646 | + = REG_BR_PROB_BASE - nehe->probability; | ||
| 3647 | + | ||
| 3648 | + peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest); | ||
| 3649 | + bb = nfte->src; | ||
| 3650 | + eh_edge = nehe; | ||
| 3651 | + } | ||
| 3652 | + | ||
| 3653 | + /* Converting possibly trapping insn to non-trapping is | ||
| 3654 | + possible. Zap dummy outgoing edges. */ | ||
| 3655 | + peep2_do_cleanup_cfg |= purge_dead_edges (bb); | ||
| 3656 | + } | ||
| 3657 | + | ||
| 3658 | + /* If we generated a jump instruction, it won't have | ||
| 3659 | + JUMP_LABEL set. Recompute after we're done. */ | ||
| 3660 | + for (x = last; x != before_try; x = PREV_INSN (x)) | ||
| 3661 | + if (JUMP_P (x)) | ||
| 3662 | + { | ||
| 3663 | + peep2_do_rebuild_jump_labels = true; | ||
| 3664 | + break; | ||
| 3665 | + } | ||
| 3666 | + | ||
| 3667 | + return last; | ||
| 3668 | +} | ||
| 3669 | + | ||
| 3670 | +/* After performing a replacement in basic block BB, fix up the life | ||
| 3671 | + information in our buffer. LAST is the last of the insns that we | ||
| 3672 | + emitted as a replacement. PREV is the insn before the start of | ||
| 3673 | + the replacement. MATCH_LEN is the number of instructions that were | ||
| 3674 | + matched, and which now need to be replaced in the buffer. */ | ||
| 3675 | + | ||
| 3676 | +static void | ||
| 3677 | +peep2_update_life (basic_block bb, int match_len, rtx last, rtx prev) | ||
| 3678 | +{ | ||
| 3679 | + int i = peep2_buf_position (peep2_current + match_len + 1); | ||
| 3680 | + rtx x; | ||
| 3681 | + regset_head live; | ||
| 3682 | + | ||
| 3683 | + INIT_REG_SET (&live); | ||
| 3684 | + COPY_REG_SET (&live, peep2_insn_data[i].live_before); | ||
| 3685 | + | ||
| 3686 | + gcc_assert (peep2_current_count >= match_len + 1); | ||
| 3687 | + peep2_current_count -= match_len + 1; | ||
| 3688 | + | ||
| 3689 | + x = last; | ||
| 3690 | + do | ||
| 3691 | + { | ||
| 3692 | + if (INSN_P (x)) | ||
| 3693 | + { | ||
| 3694 | + df_insn_rescan (x); | ||
| 3695 | + if (peep2_current_count < MAX_INSNS_PER_PEEP2) | ||
| 3696 | + { | ||
| 3697 | + peep2_current_count++; | ||
| 3698 | + if (--i < 0) | ||
| 3699 | + i = MAX_INSNS_PER_PEEP2; | ||
| 3700 | + peep2_insn_data[i].insn = x; | ||
| 3701 | + df_simulate_one_insn_backwards (bb, x, &live); | ||
| 3702 | + COPY_REG_SET (peep2_insn_data[i].live_before, &live); | ||
| 3703 | + } | ||
| 3704 | + } | ||
| 3705 | + x = PREV_INSN (x); | ||
| 3706 | + } | ||
| 3707 | + while (x != prev); | ||
| 3708 | + CLEAR_REG_SET (&live); | ||
| 3709 | + | ||
| 3710 | + peep2_current = i; | ||
| 3711 | +} | ||
| 3712 | + | ||
| 3713 | +/* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible. | ||
| 3714 | + Return true if we added it, false otherwise. The caller will try to match | ||
| 3715 | + peepholes against the buffer if we return false; otherwise it will try to | ||
| 3716 | + add more instructions to the buffer. */ | ||
| 3717 | + | ||
| 3718 | +static bool | ||
| 3719 | +peep2_fill_buffer (basic_block bb, rtx insn, regset live) | ||
| 3720 | +{ | ||
| 3721 | + int pos; | ||
| 3722 | + | ||
| 3723 | + /* Once we have filled the maximum number of insns the buffer can hold, | ||
| 3724 | + allow the caller to match the insns against peepholes. We wait until | ||
| 3725 | + the buffer is full in case the target has similar peepholes of different | ||
| 3726 | + length; we always want to match the longest if possible. */ | ||
| 3727 | + if (peep2_current_count == MAX_INSNS_PER_PEEP2) | ||
| 3728 | + return false; | ||
| 3729 | + | ||
| 3730 | + /* If an insn has RTX_FRAME_RELATED_P set, peephole substitution would lose | ||
| 3731 | + the REG_FRAME_RELATED_EXPR that is attached. */ | ||
| 3732 | + if (RTX_FRAME_RELATED_P (insn)) | ||
| 3733 | + { | ||
| 3734 | + /* Let the buffer drain first. */ | ||
| 3735 | + if (peep2_current_count > 0) | ||
| 3736 | + return false; | ||
| 3737 | + /* Step over the insn then return true without adding the insn | ||
| 3738 | + to the buffer; this will cause us to process the next | ||
| 3739 | + insn. */ | ||
| 3740 | + df_simulate_one_insn_forwards (bb, insn, live); | ||
| 3741 | + return true; | ||
| 3742 | + } | ||
| 3743 | + | ||
| 3744 | + pos = peep2_buf_position (peep2_current + peep2_current_count); | ||
| 3745 | + peep2_insn_data[pos].insn = insn; | ||
| 3746 | + COPY_REG_SET (peep2_insn_data[pos].live_before, live); | ||
| 3747 | + peep2_current_count++; | ||
| 3748 | + | ||
| 3749 | + df_simulate_one_insn_forwards (bb, insn, live); | ||
| 3750 | + return true; | ||
| 3751 | +} | ||
| 3752 | + | ||
| 3753 | /* Perform the peephole2 optimization pass. */ | ||
| 3754 | |||
| 3755 | static void | ||
| 3756 | peephole2_optimize (void) | ||
| 3757 | { | ||
| 3758 | - rtx insn, prev; | ||
| 3759 | + rtx insn; | ||
| 3760 | bitmap live; | ||
| 3761 | int i; | ||
| 3762 | basic_block bb; | ||
| 3763 | - bool do_cleanup_cfg = false; | ||
| 3764 | - bool do_rebuild_jump_labels = false; | ||
| 3765 | + | ||
| 3766 | + peep2_do_cleanup_cfg = false; | ||
| 3767 | + peep2_do_rebuild_jump_labels = false; | ||
| 3768 | |||
| 3769 | df_set_flags (DF_LR_RUN_DCE); | ||
| 3770 | + df_note_add_problem (); | ||
| 3771 | df_analyze (); | ||
| 3772 | |||
| 3773 | /* Initialize the regsets we're going to use. */ | ||
| 3774 | @@ -3129,214 +3349,59 @@ | ||
| 3775 | |||
| 3776 | FOR_EACH_BB_REVERSE (bb) | ||
| 3777 | { | ||
| 3778 | + bool past_end = false; | ||
| 3779 | + int pos; | ||
| 3780 | + | ||
| 3781 | rtl_profile_for_bb (bb); | ||
| 3782 | |||
| 3783 | /* Start up propagation. */ | ||
| 3784 | - bitmap_copy (live, DF_LR_OUT (bb)); | ||
| 3785 | - df_simulate_initialize_backwards (bb, live); | ||
| 3786 | + bitmap_copy (live, DF_LR_IN (bb)); | ||
| 3787 | + df_simulate_initialize_forwards (bb, live); | ||
| 3788 | peep2_reinit_state (live); | ||
| 3789 | |||
| 3790 | - for (insn = BB_END (bb); ; insn = prev) | ||
| 3791 | + insn = BB_HEAD (bb); | ||
| 3792 | + for (;;) | ||
| 3793 | { | ||
| 3794 | - prev = PREV_INSN (insn); | ||
| 3795 | - if (NONDEBUG_INSN_P (insn)) | ||
| 3796 | - { | ||
| 3797 | - rtx attempt, before_try, x; | ||
| 3798 | - int match_len; | ||
| 3799 | - rtx note; | ||
| 3800 | - bool was_call = false; | ||
| 3801 | - | ||
| 3802 | - /* Record this insn. */ | ||
| 3803 | - if (--peep2_current < 0) | ||
| 3804 | - peep2_current = MAX_INSNS_PER_PEEP2; | ||
| 3805 | - if (peep2_current_count < MAX_INSNS_PER_PEEP2 | ||
| 3806 | - && peep2_insn_data[peep2_current].insn == NULL_RTX) | ||
| 3807 | - peep2_current_count++; | ||
| 3808 | - peep2_insn_data[peep2_current].insn = insn; | ||
| 3809 | - df_simulate_one_insn_backwards (bb, insn, live); | ||
| 3810 | - COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live); | ||
| 3811 | + rtx attempt, head; | ||
| 3812 | + int match_len; | ||
| 3813 | |||
| 3814 | - if (RTX_FRAME_RELATED_P (insn)) | ||
| 3815 | - { | ||
| 3816 | - /* If an insn has RTX_FRAME_RELATED_P set, peephole | ||
| 3817 | - substitution would lose the | ||
| 3818 | - REG_FRAME_RELATED_EXPR that is attached. */ | ||
| 3819 | - peep2_reinit_state (live); | ||
| 3820 | - attempt = NULL; | ||
| 3821 | - } | ||
| 3822 | - else | ||
| 3823 | - /* Match the peephole. */ | ||
| 3824 | - attempt = peephole2_insns (PATTERN (insn), insn, &match_len); | ||
| 3825 | - | ||
| 3826 | - if (attempt != NULL) | ||
| 3827 | - { | ||
| 3828 | - /* If we are splitting a CALL_INSN, look for the CALL_INSN | ||
| 3829 | - in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other | ||
| 3830 | - cfg-related call notes. */ | ||
| 3831 | - for (i = 0; i <= match_len; ++i) | ||
| 3832 | - { | ||
| 3833 | - int j; | ||
| 3834 | - rtx old_insn, new_insn, note; | ||
| 3835 | - | ||
| 3836 | - j = i + peep2_current; | ||
| 3837 | - if (j >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3838 | - j -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3839 | - old_insn = peep2_insn_data[j].insn; | ||
| 3840 | - if (!CALL_P (old_insn)) | ||
| 3841 | - continue; | ||
| 3842 | - was_call = true; | ||
| 3843 | - | ||
| 3844 | - new_insn = attempt; | ||
| 3845 | - while (new_insn != NULL_RTX) | ||
| 3846 | - { | ||
| 3847 | - if (CALL_P (new_insn)) | ||
| 3848 | - break; | ||
| 3849 | - new_insn = NEXT_INSN (new_insn); | ||
| 3850 | - } | ||
| 3851 | - | ||
| 3852 | - gcc_assert (new_insn != NULL_RTX); | ||
| 3853 | - | ||
| 3854 | - CALL_INSN_FUNCTION_USAGE (new_insn) | ||
| 3855 | - = CALL_INSN_FUNCTION_USAGE (old_insn); | ||
| 3856 | - | ||
| 3857 | - for (note = REG_NOTES (old_insn); | ||
| 3858 | - note; | ||
| 3859 | - note = XEXP (note, 1)) | ||
| 3860 | - switch (REG_NOTE_KIND (note)) | ||
| 3861 | - { | ||
| 3862 | - case REG_NORETURN: | ||
| 3863 | - case REG_SETJMP: | ||
| 3864 | - add_reg_note (new_insn, REG_NOTE_KIND (note), | ||
| 3865 | - XEXP (note, 0)); | ||
| 3866 | - break; | ||
| 3867 | - default: | ||
| 3868 | - /* Discard all other reg notes. */ | ||
| 3869 | - break; | ||
| 3870 | - } | ||
| 3871 | - | ||
| 3872 | - /* Croak if there is another call in the sequence. */ | ||
| 3873 | - while (++i <= match_len) | ||
| 3874 | - { | ||
| 3875 | - j = i + peep2_current; | ||
| 3876 | - if (j >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3877 | - j -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3878 | - old_insn = peep2_insn_data[j].insn; | ||
| 3879 | - gcc_assert (!CALL_P (old_insn)); | ||
| 3880 | - } | ||
| 3881 | - break; | ||
| 3882 | - } | ||
| 3883 | - | ||
| 3884 | - i = match_len + peep2_current; | ||
| 3885 | - if (i >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3886 | - i -= MAX_INSNS_PER_PEEP2 + 1; | ||
| 3887 | - | ||
| 3888 | - note = find_reg_note (peep2_insn_data[i].insn, | ||
| 3889 | - REG_EH_REGION, NULL_RTX); | ||
| 3890 | - | ||
| 3891 | - /* Replace the old sequence with the new. */ | ||
| 3892 | - attempt = emit_insn_after_setloc (attempt, | ||
| 3893 | - peep2_insn_data[i].insn, | ||
| 3894 | - INSN_LOCATOR (peep2_insn_data[i].insn)); | ||
| 3895 | - before_try = PREV_INSN (insn); | ||
| 3896 | - delete_insn_chain (insn, peep2_insn_data[i].insn, false); | ||
| 3897 | - | ||
| 3898 | - /* Re-insert the EH_REGION notes. */ | ||
| 3899 | - if (note || (was_call && nonlocal_goto_handler_labels)) | ||
| 3900 | - { | ||
| 3901 | - edge eh_edge; | ||
| 3902 | - edge_iterator ei; | ||
| 3903 | - | ||
| 3904 | - FOR_EACH_EDGE (eh_edge, ei, bb->succs) | ||
| 3905 | - if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL)) | ||
| 3906 | - break; | ||
| 3907 | - | ||
| 3908 | - if (note) | ||
| 3909 | - copy_reg_eh_region_note_backward (note, attempt, | ||
| 3910 | - before_try); | ||
| 3911 | - | ||
| 3912 | - if (eh_edge) | ||
| 3913 | - for (x = attempt ; x != before_try ; x = PREV_INSN (x)) | ||
| 3914 | - if (x != BB_END (bb) | ||
| 3915 | - && (can_throw_internal (x) | ||
| 3916 | - || can_nonlocal_goto (x))) | ||
| 3917 | - { | ||
| 3918 | - edge nfte, nehe; | ||
| 3919 | - int flags; | ||
| 3920 | - | ||
| 3921 | - nfte = split_block (bb, x); | ||
| 3922 | - flags = (eh_edge->flags | ||
| 3923 | - & (EDGE_EH | EDGE_ABNORMAL)); | ||
| 3924 | - if (CALL_P (x)) | ||
| 3925 | - flags |= EDGE_ABNORMAL_CALL; | ||
| 3926 | - nehe = make_edge (nfte->src, eh_edge->dest, | ||
| 3927 | - flags); | ||
| 3928 | - | ||
| 3929 | - nehe->probability = eh_edge->probability; | ||
| 3930 | - nfte->probability | ||
| 3931 | - = REG_BR_PROB_BASE - nehe->probability; | ||
| 3932 | - | ||
| 3933 | - do_cleanup_cfg |= purge_dead_edges (nfte->dest); | ||
| 3934 | - bb = nfte->src; | ||
| 3935 | - eh_edge = nehe; | ||
| 3936 | - } | ||
| 3937 | - | ||
| 3938 | - /* Converting possibly trapping insn to non-trapping is | ||
| 3939 | - possible. Zap dummy outgoing edges. */ | ||
| 3940 | - do_cleanup_cfg |= purge_dead_edges (bb); | ||
| 3941 | - } | ||
| 3942 | + if (!past_end && !NONDEBUG_INSN_P (insn)) | ||
| 3943 | + { | ||
| 3944 | + next_insn: | ||
| 3945 | + insn = NEXT_INSN (insn); | ||
| 3946 | + if (insn == NEXT_INSN (BB_END (bb))) | ||
| 3947 | + past_end = true; | ||
| 3948 | + continue; | ||
| 3949 | + } | ||
| 3950 | + if (!past_end && peep2_fill_buffer (bb, insn, live)) | ||
| 3951 | + goto next_insn; | ||
| 3952 | |||
| 3953 | - if (targetm.have_conditional_execution ()) | ||
| 3954 | - { | ||
| 3955 | - for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) | ||
| 3956 | - peep2_insn_data[i].insn = NULL_RTX; | ||
| 3957 | - peep2_insn_data[peep2_current].insn = PEEP2_EOB; | ||
| 3958 | - peep2_current_count = 0; | ||
| 3959 | - } | ||
| 3960 | - else | ||
| 3961 | - { | ||
| 3962 | - /* Back up lifetime information past the end of the | ||
| 3963 | - newly created sequence. */ | ||
| 3964 | - if (++i >= MAX_INSNS_PER_PEEP2 + 1) | ||
| 3965 | - i = 0; | ||
| 3966 | - bitmap_copy (live, peep2_insn_data[i].live_before); | ||
| 3967 | - | ||
| 3968 | - /* Update life information for the new sequence. */ | ||
| 3969 | - x = attempt; | ||
| 3970 | - do | ||
| 3971 | - { | ||
| 3972 | - if (INSN_P (x)) | ||
| 3973 | - { | ||
| 3974 | - if (--i < 0) | ||
| 3975 | - i = MAX_INSNS_PER_PEEP2; | ||
| 3976 | - if (peep2_current_count < MAX_INSNS_PER_PEEP2 | ||
| 3977 | - && peep2_insn_data[i].insn == NULL_RTX) | ||
| 3978 | - peep2_current_count++; | ||
| 3979 | - peep2_insn_data[i].insn = x; | ||
| 3980 | - df_insn_rescan (x); | ||
| 3981 | - df_simulate_one_insn_backwards (bb, x, live); | ||
| 3982 | - bitmap_copy (peep2_insn_data[i].live_before, | ||
| 3983 | - live); | ||
| 3984 | - } | ||
| 3985 | - x = PREV_INSN (x); | ||
| 3986 | - } | ||
| 3987 | - while (x != prev); | ||
| 3988 | + /* If we did not fill an empty buffer, it signals the end of the | ||
| 3989 | + block. */ | ||
| 3990 | + if (peep2_current_count == 0) | ||
| 3991 | + break; | ||
| 3992 | |||
| 3993 | - peep2_current = i; | ||
| 3994 | - } | ||
| 3995 | + /* The buffer filled to the current maximum, so try to match. */ | ||
| 3996 | |||
| 3997 | - /* If we generated a jump instruction, it won't have | ||
| 3998 | - JUMP_LABEL set. Recompute after we're done. */ | ||
| 3999 | - for (x = attempt; x != before_try; x = PREV_INSN (x)) | ||
| 4000 | - if (JUMP_P (x)) | ||
| 4001 | - { | ||
| 4002 | - do_rebuild_jump_labels = true; | ||
| 4003 | - break; | ||
| 4004 | - } | ||
| 4005 | - } | ||
| 4006 | + pos = peep2_buf_position (peep2_current + peep2_current_count); | ||
| 4007 | + peep2_insn_data[pos].insn = PEEP2_EOB; | ||
| 4008 | + COPY_REG_SET (peep2_insn_data[pos].live_before, live); | ||
| 4009 | + | ||
| 4010 | + /* Match the peephole. */ | ||
| 4011 | + head = peep2_insn_data[peep2_current].insn; | ||
| 4012 | + attempt = peephole2_insns (PATTERN (head), head, &match_len); | ||
| 4013 | + if (attempt != NULL) | ||
| 4014 | + { | ||
| 4015 | + rtx last; | ||
| 4016 | + last = peep2_attempt (bb, head, match_len, attempt); | ||
| 4017 | + peep2_update_life (bb, match_len, last, PREV_INSN (attempt)); | ||
| 4018 | + } | ||
| 4019 | + else | ||
| 4020 | + { | ||
| 4021 | + /* If no match, advance the buffer by one insn. */ | ||
| 4022 | + peep2_current = peep2_buf_position (peep2_current + 1); | ||
| 4023 | + peep2_current_count--; | ||
| 4024 | } | ||
| 4025 | - | ||
| 4026 | - if (insn == BB_HEAD (bb)) | ||
| 4027 | - break; | ||
| 4028 | } | ||
| 4029 | } | ||
| 4030 | |||
| 4031 | @@ -3344,7 +3409,7 @@ | ||
| 4032 | for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) | ||
| 4033 | BITMAP_FREE (peep2_insn_data[i].live_before); | ||
| 4034 | BITMAP_FREE (live); | ||
| 4035 | - if (do_rebuild_jump_labels) | ||
| 4036 | + if (peep2_do_rebuild_jump_labels) | ||
| 4037 | rebuild_jump_labels (get_insns ()); | ||
| 4038 | } | ||
| 4039 | #endif /* HAVE_peephole2 */ | ||
| 4040 | Index: gcc-4_5-branch/gcc/recog.h | ||
| 4041 | =================================================================== | ||
| 4042 | --- gcc-4_5-branch.orig/gcc/recog.h 2012-03-06 11:53:32.000000000 -0800 | ||
| 4043 | +++ gcc-4_5-branch/gcc/recog.h 2012-03-06 12:51:20.000547582 -0800 | ||
| 4044 | @@ -194,6 +194,9 @@ | ||
| 4045 | /* Gives the constraint string for operand N. */ | ||
| 4046 | const char *constraints[MAX_RECOG_OPERANDS]; | ||
| 4047 | |||
| 4048 | + /* Nonzero if operand N is a match_operator or a match_parallel. */ | ||
| 4049 | + char is_operator[MAX_RECOG_OPERANDS]; | ||
| 4050 | + | ||
| 4051 | /* Gives the mode of operand N. */ | ||
| 4052 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; | ||
| 4053 | |||
| 4054 | @@ -260,6 +263,8 @@ | ||
| 4055 | |||
| 4056 | const char strict_low; | ||
| 4057 | |||
| 4058 | + const char is_operator; | ||
| 4059 | + | ||
| 4060 | const char eliminable; | ||
| 4061 | }; | ||
| 4062 | |||
| 4063 | Index: gcc-4_5-branch/gcc/reload.c | ||
| 4064 | =================================================================== | ||
| 4065 | --- gcc-4_5-branch.orig/gcc/reload.c 2012-03-06 11:53:32.000000000 -0800 | ||
| 4066 | +++ gcc-4_5-branch/gcc/reload.c 2012-03-06 12:51:20.004547561 -0800 | ||
| 4067 | @@ -3631,7 +3631,7 @@ | ||
| 4068 | || modified[j] != RELOAD_WRITE) | ||
| 4069 | && j != i | ||
| 4070 | /* Ignore things like match_operator operands. */ | ||
| 4071 | - && *recog_data.constraints[j] != 0 | ||
| 4072 | + && !recog_data.is_operator[j] | ||
| 4073 | /* Don't count an input operand that is constrained to match | ||
| 4074 | the early clobber operand. */ | ||
| 4075 | && ! (this_alternative_matches[j] == i | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99478.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99478.patch deleted file mode 100644 index 38463a9b4..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99478.patch +++ /dev/null | |||
| @@ -1,74 +0,0 @@ | |||
| 1 | 2011-01-11 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | ||
| 2 | |||
| 3 | * config/arm/t-arm: Fix up last commit. | ||
| 4 | |||
| 5 | 2011-01-11 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | ||
| 6 | |||
| 7 | * config/arm/t-arm: Update MD_INCLUDES to include | ||
| 8 | all the files correctly. | ||
| 9 | * config/arm/arm.md: Update comments. | ||
| 10 | |||
| 11 | === modified file 'gcc/config/arm/arm.md' | ||
| 12 | --- old/gcc/config/arm/arm.md 2011-02-22 11:38:56 +0000 | ||
| 13 | +++ new/gcc/config/arm/arm.md 2011-03-01 14:32:39 +0000 | ||
| 14 | @@ -11246,6 +11246,7 @@ | ||
| 15 | " | ||
| 16 | ) | ||
| 17 | |||
| 18 | +;; Make sure that the includes are reflected in MD_INCLUDES. | ||
| 19 | ;; Load the load/store multiple patterns | ||
| 20 | (include "ldmstm.md") | ||
| 21 | ;; Load the FPA co-processor patterns | ||
| 22 | |||
| 23 | === modified file 'gcc/config/arm/t-arm' | ||
| 24 | --- old/gcc/config/arm/t-arm 2010-08-16 09:41:58 +0000 | ||
| 25 | +++ new/gcc/config/arm/t-arm 2011-01-11 21:01:30 +0000 | ||
| 26 | @@ -18,20 +18,33 @@ | ||
| 27 | # along with GCC; see the file COPYING3. If not see | ||
| 28 | # <http://www.gnu.org/licenses/>. | ||
| 29 | |||
| 30 | -MD_INCLUDES= $(srcdir)/config/arm/arm-tune.md \ | ||
| 31 | - $(srcdir)/config/arm/predicates.md \ | ||
| 32 | - $(srcdir)/config/arm/arm-generic.md \ | ||
| 33 | - $(srcdir)/config/arm/arm1020e.md \ | ||
| 34 | - $(srcdir)/config/arm/arm1026ejs.md \ | ||
| 35 | - $(srcdir)/config/arm/arm1136jfs.md \ | ||
| 36 | - $(srcdir)/config/arm/arm926ejs.md \ | ||
| 37 | - $(srcdir)/config/arm/cirrus.md \ | ||
| 38 | - $(srcdir)/config/arm/fpa.md \ | ||
| 39 | - $(srcdir)/config/arm/vec-common.md \ | ||
| 40 | - $(srcdir)/config/arm/iwmmxt.md \ | ||
| 41 | - $(srcdir)/config/arm/vfp.md \ | ||
| 42 | - $(srcdir)/config/arm/neon.md \ | ||
| 43 | - $(srcdir)/config/arm/thumb2.md | ||
| 44 | +MD_INCLUDES= $(srcdir)/config/arm/arm-tune.md \ | ||
| 45 | + $(srcdir)/config/arm/predicates.md \ | ||
| 46 | + $(srcdir)/config/arm/arm-generic.md \ | ||
| 47 | + $(srcdir)/config/arm/arm1020e.md \ | ||
| 48 | + $(srcdir)/config/arm/arm1026ejs.md \ | ||
| 49 | + $(srcdir)/config/arm/arm1136jfs.md \ | ||
| 50 | + $(srcdir)/config/arm/arm926ejs.md \ | ||
| 51 | + $(srcdir)/config/arm/cirrus.md \ | ||
| 52 | + $(srcdir)/config/arm/fpa.md \ | ||
| 53 | + $(srcdir)/config/arm/vec-common.md \ | ||
| 54 | + $(srcdir)/config/arm/iwmmxt.md \ | ||
| 55 | + $(srcdir)/config/arm/vfp.md \ | ||
| 56 | + $(srcdir)/config/arm/cortex-a5.md \ | ||
| 57 | + $(srcdir)/config/arm/cortex-a8.md \ | ||
| 58 | + $(srcdir)/config/arm/cortex-a9.md \ | ||
| 59 | + $(srcdir)/config/arm/cortex-a9-neon.md \ | ||
| 60 | + $(srcdir)/config/arm/cortex-r4.md \ | ||
| 61 | + $(srcdir)/config/arm/cortex-r4f.md \ | ||
| 62 | + $(srcdir)/config/arm/cortex-m4.md \ | ||
| 63 | + $(srcdir)/config/arm/cortex-m4-fpu.md \ | ||
| 64 | + $(srcdir)/config/arm/vfp11.md \ | ||
| 65 | + $(srcdir)/config/arm/ldmstm.md \ | ||
| 66 | + $(srcdir)/config/arm/thumb2.md \ | ||
| 67 | + $(srcdir)/config/arm/neon.md \ | ||
| 68 | + $(srcdir)/config/arm/sync.md \ | ||
| 69 | + $(srcdir)/config/arm/cortex-a8-neon.md \ | ||
| 70 | + $(srcdir)/config/arm/constraints.md | ||
| 71 | |||
| 72 | LIB1ASMSRC = arm/lib1funcs.asm | ||
| 73 | LIB1ASMFUNCS = _thumb1_case_sqi _thumb1_case_uqi _thumb1_case_shi \ | ||
| 74 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99479.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99479.patch deleted file mode 100644 index 2920466d8..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99479.patch +++ /dev/null | |||
| @@ -1,101 +0,0 @@ | |||
| 1 | 2011-02-24 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from FSF mainline: | ||
| 4 | |||
| 5 | 2010-08-10 Bernd Schmidt <bernds@codesourcery.com> | ||
| 6 | |||
| 7 | PR bootstrap/45177 | ||
| 8 | * config/arm/arm.c (multiple_operation_profitable_p): Move xscale | ||
| 9 | test here from arm_gen_load_multiple_1. | ||
| 10 | (arm_gen_load_multiple_1, arm_gen_store_multiple_1): Use | ||
| 11 | multiple_operation_profitable_p. | ||
| 12 | |||
| 13 | === modified file 'gcc/config/arm/arm.c' | ||
| 14 | --- old/gcc/config/arm/arm.c 2011-02-22 11:38:56 +0000 | ||
| 15 | +++ new/gcc/config/arm/arm.c 2011-02-24 17:30:32 +0000 | ||
| 16 | @@ -9728,6 +9728,36 @@ | ||
| 17 | if (nops == 2 && arm_ld_sched && add_offset != 0) | ||
| 18 | return false; | ||
| 19 | |||
| 20 | + /* XScale has load-store double instructions, but they have stricter | ||
| 21 | + alignment requirements than load-store multiple, so we cannot | ||
| 22 | + use them. | ||
| 23 | + | ||
| 24 | + For XScale ldm requires 2 + NREGS cycles to complete and blocks | ||
| 25 | + the pipeline until completion. | ||
| 26 | + | ||
| 27 | + NREGS CYCLES | ||
| 28 | + 1 3 | ||
| 29 | + 2 4 | ||
| 30 | + 3 5 | ||
| 31 | + 4 6 | ||
| 32 | + | ||
| 33 | + An ldr instruction takes 1-3 cycles, but does not block the | ||
| 34 | + pipeline. | ||
| 35 | + | ||
| 36 | + NREGS CYCLES | ||
| 37 | + 1 1-3 | ||
| 38 | + 2 2-6 | ||
| 39 | + 3 3-9 | ||
| 40 | + 4 4-12 | ||
| 41 | + | ||
| 42 | + Best case ldr will always win. However, the more ldr instructions | ||
| 43 | + we issue, the less likely we are to be able to schedule them well. | ||
| 44 | + Using ldr instructions also increases code size. | ||
| 45 | + | ||
| 46 | + As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | ||
| 47 | + for counts of 3 or 4 regs. */ | ||
| 48 | + if (nops <= 2 && arm_tune_xscale && !optimize_size) | ||
| 49 | + return false; | ||
| 50 | return true; | ||
| 51 | } | ||
| 52 | |||
| 53 | @@ -10086,35 +10116,7 @@ | ||
| 54 | int i = 0, j; | ||
| 55 | rtx result; | ||
| 56 | |||
| 57 | - /* XScale has load-store double instructions, but they have stricter | ||
| 58 | - alignment requirements than load-store multiple, so we cannot | ||
| 59 | - use them. | ||
| 60 | - | ||
| 61 | - For XScale ldm requires 2 + NREGS cycles to complete and blocks | ||
| 62 | - the pipeline until completion. | ||
| 63 | - | ||
| 64 | - NREGS CYCLES | ||
| 65 | - 1 3 | ||
| 66 | - 2 4 | ||
| 67 | - 3 5 | ||
| 68 | - 4 6 | ||
| 69 | - | ||
| 70 | - An ldr instruction takes 1-3 cycles, but does not block the | ||
| 71 | - pipeline. | ||
| 72 | - | ||
| 73 | - NREGS CYCLES | ||
| 74 | - 1 1-3 | ||
| 75 | - 2 2-6 | ||
| 76 | - 3 3-9 | ||
| 77 | - 4 4-12 | ||
| 78 | - | ||
| 79 | - Best case ldr will always win. However, the more ldr instructions | ||
| 80 | - we issue, the less likely we are to be able to schedule them well. | ||
| 81 | - Using ldr instructions also increases code size. | ||
| 82 | - | ||
| 83 | - As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | ||
| 84 | - for counts of 3 or 4 regs. */ | ||
| 85 | - if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size)) | ||
| 86 | + if (low_irq_latency || !multiple_operation_profitable_p (false, count, 0)) | ||
| 87 | { | ||
| 88 | rtx seq; | ||
| 89 | |||
| 90 | @@ -10166,9 +10168,7 @@ | ||
| 91 | if (GET_CODE (basereg) == PLUS) | ||
| 92 | basereg = XEXP (basereg, 0); | ||
| 93 | |||
| 94 | - /* See arm_gen_load_multiple_1 for discussion of | ||
| 95 | - the pros/cons of ldm/stm usage for XScale. */ | ||
| 96 | - if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size)) | ||
| 97 | + if (low_irq_latency || !multiple_operation_profitable_p (false, count, 0)) | ||
| 98 | { | ||
| 99 | rtx seq; | ||
| 100 | |||
| 101 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99480.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99480.patch deleted file mode 100644 index 76d3c9565..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99480.patch +++ /dev/null | |||
| @@ -1,64 +0,0 @@ | |||
| 1 | 2011-02-02 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 2 | |||
| 3 | |||
| 4 | gcc/ | ||
| 5 | PR target/47551 | ||
| 6 | * config/arm/arm.c (coproc_secondary_reload_class): Handle | ||
| 7 | structure modes. Don't check neon_vector_mem_operand for | ||
| 8 | vector or structure modes. | ||
| 9 | |||
| 10 | gcc/testsuite/ | ||
| 11 | PR target/47551 | ||
| 12 | * gcc.target/arm/neon-modes-2.c: New test. | ||
| 13 | |||
| 14 | === modified file 'gcc/config/arm/arm.c' | ||
| 15 | --- old/gcc/config/arm/arm.c 2011-02-24 17:30:32 +0000 | ||
| 16 | +++ new/gcc/config/arm/arm.c 2011-03-02 11:29:06 +0000 | ||
| 17 | @@ -9303,11 +9303,14 @@ | ||
| 18 | return GENERAL_REGS; | ||
| 19 | } | ||
| 20 | |||
| 21 | + /* The neon move patterns handle all legitimate vector and struct | ||
| 22 | + addresses. */ | ||
| 23 | if (TARGET_NEON | ||
| 24 | + && MEM_P (x) | ||
| 25 | && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT | ||
| 26 | - || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | ||
| 27 | - && neon_vector_mem_operand (x, 0)) | ||
| 28 | - return NO_REGS; | ||
| 29 | + || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT | ||
| 30 | + || VALID_NEON_STRUCT_MODE (mode))) | ||
| 31 | + return NO_REGS; | ||
| 32 | |||
| 33 | if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) | ||
| 34 | return NO_REGS; | ||
| 35 | |||
| 36 | === added file 'gcc/testsuite/gcc.target/arm/neon-modes-2.c' | ||
| 37 | --- old/gcc/testsuite/gcc.target/arm/neon-modes-2.c 1970-01-01 00:00:00 +0000 | ||
| 38 | +++ new/gcc/testsuite/gcc.target/arm/neon-modes-2.c 2011-02-02 13:48:10 +0000 | ||
| 39 | @@ -0,0 +1,24 @@ | ||
| 40 | +/* { dg-do compile } */ | ||
| 41 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 42 | +/* { dg-options "-O1" } */ | ||
| 43 | +/* { dg-add-options arm_neon } */ | ||
| 44 | + | ||
| 45 | +#include "arm_neon.h" | ||
| 46 | + | ||
| 47 | +#define SETUP(A) x##A = vld3_u32 (ptr + A * 0x20) | ||
| 48 | +#define MODIFY(A) x##A = vld3_lane_u32 (ptr + A * 0x20 + 0x10, x##A, 1) | ||
| 49 | +#define STORE(A) vst3_u32 (ptr + A * 0x20, x##A) | ||
| 50 | + | ||
| 51 | +#define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5) | ||
| 52 | + | ||
| 53 | +void | ||
| 54 | +bar (uint32_t *ptr, int y) | ||
| 55 | +{ | ||
| 56 | + uint32x2x3_t MANY (SETUP); | ||
| 57 | + int *x = __builtin_alloca (y); | ||
| 58 | + int z[0x1000]; | ||
| 59 | + foo (x, z); | ||
| 60 | + MANY (MODIFY); | ||
| 61 | + foo (x, z); | ||
| 62 | + MANY (STORE); | ||
| 63 | +} | ||
| 64 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99483.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99483.patch deleted file mode 100644 index c0be4a03b..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99483.patch +++ /dev/null | |||
| @@ -1,63 +0,0 @@ | |||
| 1 | 2011-02-11 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * cse.c (count_reg_usage): Check side_effects_p. Remove the | ||
| 5 | separate check for volatile asms. | ||
| 6 | |||
| 7 | gcc/testsuite/ | ||
| 8 | * gcc.dg/torture/volatile-pic-1.c: New test. | ||
| 9 | |||
| 10 | === modified file 'gcc/cse.c' | ||
| 11 | --- old/gcc/cse.c 2010-11-26 12:03:32 +0000 | ||
| 12 | +++ new/gcc/cse.c 2011-02-11 09:27:19 +0000 | ||
| 13 | @@ -6634,9 +6634,10 @@ | ||
| 14 | case CALL_INSN: | ||
| 15 | case INSN: | ||
| 16 | case JUMP_INSN: | ||
| 17 | - /* We expect dest to be NULL_RTX here. If the insn may trap, mark | ||
| 18 | - this fact by setting DEST to pc_rtx. */ | ||
| 19 | - if (insn_could_throw_p (x)) | ||
| 20 | + /* We expect dest to be NULL_RTX here. If the insn may trap, | ||
| 21 | + or if it cannot be deleted due to side-effects, mark this fact | ||
| 22 | + by setting DEST to pc_rtx. */ | ||
| 23 | + if (insn_could_throw_p (x) || side_effects_p (PATTERN (x))) | ||
| 24 | dest = pc_rtx; | ||
| 25 | if (code == CALL_INSN) | ||
| 26 | count_reg_usage (CALL_INSN_FUNCTION_USAGE (x), counts, dest, incr); | ||
| 27 | @@ -6676,10 +6677,6 @@ | ||
| 28 | return; | ||
| 29 | |||
| 30 | case ASM_OPERANDS: | ||
| 31 | - /* If the asm is volatile, then this insn cannot be deleted, | ||
| 32 | - and so the inputs *must* be live. */ | ||
| 33 | - if (MEM_VOLATILE_P (x)) | ||
| 34 | - dest = NULL_RTX; | ||
| 35 | /* Iterate over just the inputs, not the constraints as well. */ | ||
| 36 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--) | ||
| 37 | count_reg_usage (ASM_OPERANDS_INPUT (x, i), counts, dest, incr); | ||
| 38 | |||
| 39 | === added file 'gcc/testsuite/gcc.dg/torture/volatile-pic-1.c' | ||
| 40 | --- old/gcc/testsuite/gcc.dg/torture/volatile-pic-1.c 1970-01-01 00:00:00 +0000 | ||
| 41 | +++ new/gcc/testsuite/gcc.dg/torture/volatile-pic-1.c 2011-02-11 09:27:19 +0000 | ||
| 42 | @@ -0,0 +1,20 @@ | ||
| 43 | +/* { dg-do run } */ | ||
| 44 | +/* { dg-require-visibility "" } */ | ||
| 45 | +/* { dg-require-effective-target fpic } */ | ||
| 46 | +/* { dg-options "-fPIC" } */ | ||
| 47 | + | ||
| 48 | +volatile int x __attribute__((visibility("hidden"))); | ||
| 49 | + | ||
| 50 | +void __attribute__((noinline)) bar (void) | ||
| 51 | +{ | ||
| 52 | +#if defined (__arm__) | ||
| 53 | + asm volatile ("mov r3,%0" :: "r" (0xdeadbeef) : "r3"); | ||
| 54 | +#endif | ||
| 55 | + (void) x; | ||
| 56 | +} | ||
| 57 | + | ||
| 58 | +int main (void) | ||
| 59 | +{ | ||
| 60 | + bar (); | ||
| 61 | + return 0; | ||
| 62 | +} | ||
| 63 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99486.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99486.patch deleted file mode 100644 index e6b58ac87..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99486.patch +++ /dev/null | |||
| @@ -1,230 +0,0 @@ | |||
| 1 | 2011-03-09 Bernd Schmidt <bernds@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #10649 | ||
| 4 | gcc/ | ||
| 5 | * dwarf2out.c (dwarf2out_begin_epilogue): Accept simplejumps | ||
| 6 | as well as returnjumps. | ||
| 7 | * cfganal.c (set_edge_can_fallthru_flag): Revert previous change | ||
| 8 | that tried to keep epilogue blocks adjacent. | ||
| 9 | |||
| 10 | 2011-02-03 Bernd Schmidt <bernds@codesourcery.com> | ||
| 11 | |||
| 12 | gcc/ | ||
| 13 | * function.c (prepare_shrink_wrap): New function. | ||
| 14 | (thread_prologue_and_epilogue_insns): Call it. | ||
| 15 | |||
| 16 | === modified file 'gcc/cfganal.c' | ||
| 17 | --- old/gcc/cfganal.c 2011-02-08 10:51:58 +0000 | ||
| 18 | +++ new/gcc/cfganal.c 2011-03-10 14:55:10 +0000 | ||
| 19 | @@ -271,37 +271,6 @@ | ||
| 20 | EDGE_SUCC (bb, 0)->flags |= EDGE_CAN_FALLTHRU; | ||
| 21 | EDGE_SUCC (bb, 1)->flags |= EDGE_CAN_FALLTHRU; | ||
| 22 | } | ||
| 23 | - /* dwarf2out expects that a NOTE_INSN_EPILOGUE_BEGIN is always paired | ||
| 24 | - with a return or a sibcall. Ensure that this remains the case if | ||
| 25 | - they are in different basic blocks. */ | ||
| 26 | - FOR_EACH_BB (bb) | ||
| 27 | - { | ||
| 28 | - edge e; | ||
| 29 | - edge_iterator ei; | ||
| 30 | - rtx insn, end; | ||
| 31 | - | ||
| 32 | - end = BB_END (bb); | ||
| 33 | - FOR_BB_INSNS (bb, insn) | ||
| 34 | - if (GET_CODE (insn) == NOTE | ||
| 35 | - && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG | ||
| 36 | - && !(CALL_P (end) && SIBLING_CALL_P (end)) | ||
| 37 | - && !returnjump_p (end)) | ||
| 38 | - { | ||
| 39 | - basic_block other_bb = NULL; | ||
| 40 | - FOR_EACH_EDGE (e, ei, bb->succs) | ||
| 41 | - { | ||
| 42 | - if (e->flags & EDGE_FALLTHRU) | ||
| 43 | - other_bb = e->dest; | ||
| 44 | - else | ||
| 45 | - e->flags &= ~EDGE_CAN_FALLTHRU; | ||
| 46 | - } | ||
| 47 | - FOR_EACH_EDGE (e, ei, other_bb->preds) | ||
| 48 | - { | ||
| 49 | - if (!(e->flags & EDGE_FALLTHRU)) | ||
| 50 | - e->flags &= ~EDGE_CAN_FALLTHRU; | ||
| 51 | - } | ||
| 52 | - } | ||
| 53 | - } | ||
| 54 | } | ||
| 55 | |||
| 56 | /* Find unreachable blocks. An unreachable block will have 0 in | ||
| 57 | |||
| 58 | === modified file 'gcc/dwarf2out.c' | ||
| 59 | --- old/gcc/dwarf2out.c 2011-02-08 10:51:58 +0000 | ||
| 60 | +++ new/gcc/dwarf2out.c 2011-03-10 14:55:10 +0000 | ||
| 61 | @@ -2782,10 +2782,10 @@ | ||
| 62 | dwarf2out_frame_debug_expr (insn, label); | ||
| 63 | } | ||
| 64 | |||
| 65 | -/* Determine if we need to save and restore CFI information around this | ||
| 66 | - epilogue. If SIBCALL is true, then this is a sibcall epilogue. If | ||
| 67 | - we do need to save/restore, then emit the save now, and insert a | ||
| 68 | - NOTE_INSN_CFA_RESTORE_STATE at the appropriate place in the stream. */ | ||
| 69 | +/* Determine if we need to save and restore CFI information around | ||
| 70 | + this epilogue. If we do need to save/restore, then emit the save | ||
| 71 | + now, and insert a NOTE_INSN_CFA_RESTORE_STATE at the appropriate | ||
| 72 | + place in the stream. */ | ||
| 73 | |||
| 74 | void | ||
| 75 | dwarf2out_begin_epilogue (rtx insn) | ||
| 76 | @@ -2800,8 +2800,10 @@ | ||
| 77 | if (!INSN_P (i)) | ||
| 78 | continue; | ||
| 79 | |||
| 80 | - /* Look for both regular and sibcalls to end the block. */ | ||
| 81 | - if (returnjump_p (i)) | ||
| 82 | + /* Look for both regular and sibcalls to end the block. Various | ||
| 83 | + optimization passes may cause us to jump to a common epilogue | ||
| 84 | + tail, so we also accept simplejumps. */ | ||
| 85 | + if (returnjump_p (i) || simplejump_p (i)) | ||
| 86 | break; | ||
| 87 | if (CALL_P (i) && SIBLING_CALL_P (i)) | ||
| 88 | break; | ||
| 89 | |||
| 90 | === modified file 'gcc/function.c' | ||
| 91 | --- old/gcc/function.c 2011-02-08 10:51:58 +0000 | ||
| 92 | +++ new/gcc/function.c 2011-03-10 14:55:10 +0000 | ||
| 93 | @@ -5038,6 +5038,127 @@ | ||
| 94 | return true; | ||
| 95 | return false; | ||
| 96 | } | ||
| 97 | + | ||
| 98 | +/* Look for sets of call-saved registers in the first block of the | ||
| 99 | + function, and move them down into successor blocks if the register | ||
| 100 | + is used only on one path. This exposes more opportunities for | ||
| 101 | + shrink-wrapping. | ||
| 102 | + These kinds of sets often occur when incoming argument registers are | ||
| 103 | + moved to call-saved registers because their values are live across | ||
| 104 | + one or more calls during the function. */ | ||
| 105 | + | ||
| 106 | +static void | ||
| 107 | +prepare_shrink_wrap (basic_block entry_block) | ||
| 108 | +{ | ||
| 109 | + rtx insn, curr; | ||
| 110 | + FOR_BB_INSNS_SAFE (entry_block, insn, curr) | ||
| 111 | + { | ||
| 112 | + basic_block next_bb; | ||
| 113 | + edge e, live_edge; | ||
| 114 | + edge_iterator ei; | ||
| 115 | + rtx set, scan; | ||
| 116 | + unsigned destreg, srcreg; | ||
| 117 | + | ||
| 118 | + if (!NONDEBUG_INSN_P (insn)) | ||
| 119 | + continue; | ||
| 120 | + set = single_set (insn); | ||
| 121 | + if (!set) | ||
| 122 | + continue; | ||
| 123 | + | ||
| 124 | + if (!REG_P (SET_SRC (set)) || !REG_P (SET_DEST (set))) | ||
| 125 | + continue; | ||
| 126 | + srcreg = REGNO (SET_SRC (set)); | ||
| 127 | + destreg = REGNO (SET_DEST (set)); | ||
| 128 | + if (hard_regno_nregs[srcreg][GET_MODE (SET_SRC (set))] > 1 | ||
| 129 | + || hard_regno_nregs[destreg][GET_MODE (SET_DEST (set))] > 1) | ||
| 130 | + continue; | ||
| 131 | + | ||
| 132 | + next_bb = entry_block; | ||
| 133 | + scan = insn; | ||
| 134 | + | ||
| 135 | + for (;;) | ||
| 136 | + { | ||
| 137 | + live_edge = NULL; | ||
| 138 | + FOR_EACH_EDGE (e, ei, next_bb->succs) | ||
| 139 | + { | ||
| 140 | + if (REGNO_REG_SET_P (df_get_live_in (e->dest), destreg)) | ||
| 141 | + { | ||
| 142 | + if (live_edge) | ||
| 143 | + { | ||
| 144 | + live_edge = NULL; | ||
| 145 | + break; | ||
| 146 | + } | ||
| 147 | + live_edge = e; | ||
| 148 | + } | ||
| 149 | + } | ||
| 150 | + if (!live_edge) | ||
| 151 | + break; | ||
| 152 | + /* We can sometimes encounter dead code. Don't try to move it | ||
| 153 | + into the exit block. */ | ||
| 154 | + if (live_edge->dest == EXIT_BLOCK_PTR) | ||
| 155 | + break; | ||
| 156 | + if (EDGE_COUNT (live_edge->dest->preds) > 1) | ||
| 157 | + break; | ||
| 158 | + while (scan != BB_END (next_bb)) | ||
| 159 | + { | ||
| 160 | + scan = NEXT_INSN (scan); | ||
| 161 | + if (NONDEBUG_INSN_P (scan)) | ||
| 162 | + { | ||
| 163 | + rtx link; | ||
| 164 | + HARD_REG_SET set_regs; | ||
| 165 | + | ||
| 166 | + CLEAR_HARD_REG_SET (set_regs); | ||
| 167 | + note_stores (PATTERN (scan), record_hard_reg_sets, | ||
| 168 | + &set_regs); | ||
| 169 | + if (CALL_P (scan)) | ||
| 170 | + IOR_HARD_REG_SET (set_regs, call_used_reg_set); | ||
| 171 | + for (link = REG_NOTES (scan); link; link = XEXP (link, 1)) | ||
| 172 | + if (REG_NOTE_KIND (link) == REG_INC) | ||
| 173 | + record_hard_reg_sets (XEXP (link, 0), NULL, &set_regs); | ||
| 174 | + | ||
| 175 | + if (TEST_HARD_REG_BIT (set_regs, srcreg) | ||
| 176 | + || reg_referenced_p (SET_DEST (set), | ||
| 177 | + PATTERN (scan))) | ||
| 178 | + { | ||
| 179 | + scan = NULL_RTX; | ||
| 180 | + break; | ||
| 181 | + } | ||
| 182 | + if (CALL_P (scan)) | ||
| 183 | + { | ||
| 184 | + rtx link = CALL_INSN_FUNCTION_USAGE (scan); | ||
| 185 | + while (link) | ||
| 186 | + { | ||
| 187 | + rtx tmp = XEXP (link, 0); | ||
| 188 | + if (GET_CODE (tmp) == USE | ||
| 189 | + && reg_referenced_p (SET_DEST (set), tmp)) | ||
| 190 | + break; | ||
| 191 | + link = XEXP (link, 1); | ||
| 192 | + } | ||
| 193 | + if (link) | ||
| 194 | + { | ||
| 195 | + scan = NULL_RTX; | ||
| 196 | + break; | ||
| 197 | + } | ||
| 198 | + } | ||
| 199 | + } | ||
| 200 | + } | ||
| 201 | + if (!scan) | ||
| 202 | + break; | ||
| 203 | + next_bb = live_edge->dest; | ||
| 204 | + } | ||
| 205 | + | ||
| 206 | + if (next_bb != entry_block) | ||
| 207 | + { | ||
| 208 | + rtx after = BB_HEAD (next_bb); | ||
| 209 | + while (!NOTE_P (after) | ||
| 210 | + || NOTE_KIND (after) != NOTE_INSN_BASIC_BLOCK) | ||
| 211 | + after = NEXT_INSN (after); | ||
| 212 | + emit_insn_after (PATTERN (insn), after); | ||
| 213 | + delete_insn (insn); | ||
| 214 | + } | ||
| 215 | + } | ||
| 216 | +} | ||
| 217 | + | ||
| 218 | #endif | ||
| 219 | |||
| 220 | #ifdef HAVE_return | ||
| 221 | @@ -5215,6 +5336,8 @@ | ||
| 222 | bitmap_head bb_antic_flags; | ||
| 223 | bitmap_head bb_on_list; | ||
| 224 | |||
| 225 | + prepare_shrink_wrap (entry_edge->dest); | ||
| 226 | + | ||
| 227 | bitmap_initialize (&bb_antic_flags, &bitmap_default_obstack); | ||
| 228 | bitmap_initialize (&bb_on_list, &bitmap_default_obstack); | ||
| 229 | |||
| 230 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99487.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99487.patch deleted file mode 100644 index 186c17717..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99487.patch +++ /dev/null | |||
| @@ -1,42 +0,0 @@ | |||
| 1 | 2011-03-11 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | Michael Hope <michael.hope@linaro.org> | ||
| 3 | Matthias Klose <doko@ubuntu.org> | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * function. (thread_prologue_and_epilogue_insns): Initialize | ||
| 7 | prologue_seq. | ||
| 8 | * opts.c (decode_options): Move flag_shrink_wrap to -O1. | ||
| 9 | |||
| 10 | === modified file 'gcc/function.c' | ||
| 11 | --- old/gcc/function.c 2011-03-10 14:55:10 +0000 | ||
| 12 | +++ new/gcc/function.c 2011-03-11 10:35:05 +0000 | ||
| 13 | @@ -5252,6 +5252,8 @@ | ||
| 14 | edge_iterator ei; | ||
| 15 | bitmap_head bb_flags; | ||
| 16 | |||
| 17 | + prologue_seq = NULL_RTX; | ||
| 18 | + | ||
| 19 | df_analyze (); | ||
| 20 | |||
| 21 | rtl_profile_for_bb (ENTRY_BLOCK_PTR); | ||
| 22 | |||
| 23 | === modified file 'gcc/opts.c' | ||
| 24 | --- old/gcc/opts.c 2011-02-08 10:51:58 +0000 | ||
| 25 | +++ new/gcc/opts.c 2011-03-11 10:35:05 +0000 | ||
| 26 | @@ -877,6 +877,7 @@ | ||
| 27 | flag_tree_copy_prop = opt1; | ||
| 28 | flag_tree_sink = opt1; | ||
| 29 | flag_tree_ch = opt1; | ||
| 30 | + flag_shrink_wrap = opt1; | ||
| 31 | |||
| 32 | /* -O2 optimizations. */ | ||
| 33 | opt2 = (optimize >= 2); | ||
| 34 | @@ -909,7 +910,6 @@ | ||
| 35 | flag_ipa_cp = opt2; | ||
| 36 | flag_ipa_sra = opt2; | ||
| 37 | flag_ee = opt2; | ||
| 38 | - flag_shrink_wrap = opt2; | ||
| 39 | |||
| 40 | /* Track fields in field-sensitive alias analysis. */ | ||
| 41 | set_param_value ("max-fields-for-field-sensitive", | ||
| 42 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99488.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99488.patch deleted file mode 100644 index 2f41a0a73..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99488.patch +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | 2011-03-03 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * ee.c (reg_use_p): Handle subregs of promoted vars. | ||
| 5 | |||
| 6 | === modified file 'gcc/ee.c' | ||
| 7 | --- old/gcc/ee.c 2010-12-10 15:33:37 +0000 | ||
| 8 | +++ new/gcc/ee.c 2011-03-03 17:08:58 +0000 | ||
| 9 | @@ -209,7 +209,11 @@ | ||
| 10 | |||
| 11 | *regno = REGNO (reg); | ||
| 12 | |||
| 13 | - if (paradoxical_subreg_p (use)) | ||
| 14 | + /* Non-paradoxical SUBREGs of promoted vars guarantee that the | ||
| 15 | + upper (elided) bits of the inner register have a particular value. | ||
| 16 | + For our purposes, such SUBREGs act as a full reference to the | ||
| 17 | + inner register. */ | ||
| 18 | + if (paradoxical_subreg_p (use) || SUBREG_PROMOTED_VAR_P (use)) | ||
| 19 | *size = GET_MODE_BITSIZE (GET_MODE (reg)); | ||
| 20 | else | ||
| 21 | *size = subreg_lsb (use) + GET_MODE_BITSIZE (GET_MODE (use)); | ||
| 22 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99489.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99489.patch deleted file mode 100644 index 12fb56ad0..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99489.patch +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | 2011-03-10 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> | ||
| 2 | |||
| 3 | LP:730440 | ||
| 4 | PR target/47668 | ||
| 5 | gcc/ | ||
| 6 | * config/arm/arm.md (arm_movtas_ze): Use 'L' instead of 'c'. | ||
| 7 | gcc/testsuite/ | ||
| 8 | * gcc.target/arm/pr47688.c: New. | ||
| 9 | |||
| 10 | === modified file 'gcc/config/arm/arm.md' | ||
| 11 | --- old/gcc/config/arm/arm.md 2011-03-01 14:32:39 +0000 | ||
| 12 | +++ new/gcc/config/arm/arm.md 2011-03-11 14:26:34 +0000 | ||
| 13 | @@ -11133,13 +11133,15 @@ | ||
| 14 | [(set_attr "conds" "clob")] | ||
| 15 | ) | ||
| 16 | |||
| 17 | +;; We only care about the lower 16 bits of the constant | ||
| 18 | +;; being inserted into the upper 16 bits of the register. | ||
| 19 | (define_insn "*arm_movtas_ze" | ||
| 20 | [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") | ||
| 21 | (const_int 16) | ||
| 22 | (const_int 16)) | ||
| 23 | (match_operand:SI 1 "const_int_operand" ""))] | ||
| 24 | "arm_arch_thumb2" | ||
| 25 | - "movt%?\t%0, %c1" | ||
| 26 | + "movt%?\t%0, %L1" | ||
| 27 | [(set_attr "predicable" "yes") | ||
| 28 | (set_attr "length" "4")] | ||
| 29 | ) | ||
| 30 | |||
| 31 | === added file 'gcc/testsuite/gcc.target/arm/pr47688.c' | ||
| 32 | --- old/gcc/testsuite/gcc.target/arm/pr47688.c 1970-01-01 00:00:00 +0000 | ||
| 33 | +++ new/gcc/testsuite/gcc.target/arm/pr47688.c 2011-03-11 14:26:34 +0000 | ||
| 34 | @@ -0,0 +1,26 @@ | ||
| 35 | +/* { dg-options "-mthumb -O2" } */ | ||
| 36 | +/* { dg-require-effective-target arm_thumb2_ok } */ | ||
| 37 | +/* { dg-final { scan-assembler-not "-32768" } } */ | ||
| 38 | + | ||
| 39 | +typedef union | ||
| 40 | +{ | ||
| 41 | + unsigned long int u_32_value; | ||
| 42 | + struct | ||
| 43 | + { | ||
| 44 | + unsigned short int u_16_value_0; | ||
| 45 | + unsigned short int u_16_value_1; | ||
| 46 | + } u_16_values; | ||
| 47 | +} my_union; | ||
| 48 | + | ||
| 49 | + | ||
| 50 | +unsigned long int Test(const unsigned short int wXe) | ||
| 51 | +{ | ||
| 52 | + my_union dwCalcVal; | ||
| 53 | + | ||
| 54 | + dwCalcVal.u_16_values.u_16_value_0=wXe; | ||
| 55 | + dwCalcVal.u_16_values.u_16_value_1=0x8000u; | ||
| 56 | + | ||
| 57 | + dwCalcVal.u_32_value /=3; | ||
| 58 | + | ||
| 59 | + return (dwCalcVal.u_32_value); | ||
| 60 | +} | ||
| 61 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99494.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99494.patch deleted file mode 100644 index 56897e984..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99494.patch +++ /dev/null | |||
| @@ -1,1272 +0,0 @@ | |||
| 1 | 2011-04-09 Andrew Stubbs <ams@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 6 | |||
| 7 | * config.sub: Recognize *-linux-android*. | ||
| 8 | |||
| 9 | 2010-05-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 10 | |||
| 11 | Add support for Bionic C library | ||
| 12 | gcc/ | ||
| 13 | * config.gcc (LIBC_GLIBC, LIBC_BIONIC, LIBC_UCLIBC): New tm_define | ||
| 14 | macro. | ||
| 15 | (DEFAULT_LIBC): New tm_define macro set to one of LIBC_*. | ||
| 16 | (bfin*-uclinux, moxie-*-uclinux*, m68k-*-uclinux*): Update. | ||
| 17 | |||
| 18 | * config/linux.h (OPTION_GLIBC, OPTION_UCLIBC, OPTION_BIONIC): Define. | ||
| 19 | (LINUX_TARGET_OS_CPP_BUILTINS): Define __gnu_linux__ only for GLIBC. | ||
| 20 | (CHOOSE_DYNAMIC_LINKER1, CHOOSE_DYNAMIC_LINKER): Make it easier | ||
| 21 | to support multiple C libraries. Handle Bionic. | ||
| 22 | (BIONIC_DYNAMIC_LINKER, BIONIC_DYNAMIC_LINKER32,) | ||
| 23 | (BIONIC_DYNAMIC_LINKER64): Define. | ||
| 24 | (LINUX_DYNAMIC_LINKER, LINUX_DYNAMIC_LINKER32, LINUX_DYNAMIC_LINKER64): | ||
| 25 | Update. | ||
| 26 | (TARGET_HAS_SINCOS): Enable for Bionic. | ||
| 27 | |||
| 28 | * config/linux.opt: Rewrite to handle more than 2 C libraries. Make | ||
| 29 | the last option specified on command line take effect. | ||
| 30 | (linux_uclibc): Rename to linux_libc, initialize using DEFAULT_LIBC. | ||
| 31 | (mbionic): New. | ||
| 32 | (mglibc, muclibc): Update. | ||
| 33 | |||
| 34 | * config/alpha/linux-elf.h, config/rs6000/linux64.h, | ||
| 35 | * config/rs6000/sysv4.h (CHOOSE_DYNAMIC_LINKER): Update to use | ||
| 36 | DEFAULT_LIBC. | ||
| 37 | |||
| 38 | * doc/invoke.texi (-mglibc, -muclibc): Update. | ||
| 39 | (-mbionic): Document. | ||
| 40 | |||
| 41 | gcc/testsuite/ | ||
| 42 | * gcc.dg/glibc-uclibc-1.c, gcc.dg/glibc-uclibc-2.c: Remove, no longer | ||
| 43 | necessary. | ||
| 44 | |||
| 45 | 2010-05-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 46 | |||
| 47 | Support compilation for Android platform. Reimplement -mandroid. | ||
| 48 | gcc/ | ||
| 49 | * config.gcc (*linux*): Include linux-android.h and linux-android.opt. | ||
| 50 | (*android*): Set ANDROID_DEFAULT. | ||
| 51 | (arm*-*-linux*): Include linux-android.h. | ||
| 52 | (arm*-*-eabi*): Don't include previous -mandroid implementation. | ||
| 53 | * config/arm/eabi.h: Remove, move Android-specific parts ... | ||
| 54 | * config/linux-android.h: ... here. New file. | ||
| 55 | * config/arm/eabi.opt: Rename to ... | ||
| 56 | * config/linux-android.opt: ... this. | ||
| 57 | (mandroid): Allow -mno-android option. Initialize based on | ||
| 58 | ANDROID_DEFAULT. | ||
| 59 | * config/linux.h (STARTFILE_SPEC, ENDFILE_SPEC, CC1_SPEC, LIB_SPEC): | ||
| 60 | Move logic to corresponding LINUX_TARGET_* macros. | ||
| 61 | (TARGET_OS_CPP_BUILTINS): Define __ANDROID__, when appropriate. | ||
| 62 | * config/linux-eabi.h (LINK_SPEC, CC1_SPEC, CC1PLUS_SPEC, LIB_SPEC,) | ||
| 63 | (STARTFILE_SPEC, ENDFILE_SPEC): Define to choose between Linux and | ||
| 64 | Android definitions. | ||
| 65 | (LINUX_TARGET_OS_CPP_BUILTINS): Define __ANDROID__ if TARGET_ANDROID. | ||
| 66 | * doc/invoke.texi (-mandroid, -tno-android-cc, -tno-android-ld): | ||
| 67 | Document. | ||
| 68 | |||
| 69 | 2010-06-01 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 70 | |||
| 71 | gcc/ | ||
| 72 | * config/arm/t-linux-androideabi: New. | ||
| 73 | * config.gcc (arm*-*-linux-androideabi): Include multilib configuration. | ||
| 74 | |||
| 75 | 2010-05-27 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 76 | |||
| 77 | gcc/ | ||
| 78 | * gthr-posix.h (pthread_cancel): Don't declare if compiling against | ||
| 79 | Bionic C library. | ||
| 80 | (__gthread_active_p): Check for pthread_create if compiling against | ||
| 81 | Bionic C library. | ||
| 82 | |||
| 83 | 2010-06-01 Maxim Kuvyrkov <maxim@codesourcery.com> | ||
| 84 | |||
| 85 | libstdc++-v3/ | ||
| 86 | * acinclude.m4: Support Bionic C library. | ||
| 87 | Explicitly specify -fexceptions for exception check. | ||
| 88 | * configure.host: Support Bionic C library. | ||
| 89 | * configure: Regenerate. | ||
| 90 | * config/os/bionic/ctype_base.h, config/os/bionic/ctype_inline.h, | ||
| 91 | * config/os/bionic/ctype_noincline.h, config/os/bionic/os_defines.h: | ||
| 92 | New files, based on config/os/newlib/*. | ||
| 93 | |||
| 94 | === modified file 'config.sub' | ||
| 95 | Index: gcc-4.5.3/config.sub | ||
| 96 | =================================================================== | ||
| 97 | --- gcc-4.5.3.orig/config.sub | ||
| 98 | +++ gcc-4.5.3/config.sub | ||
| 99 | @@ -4,7 +4,7 @@ | ||
| 100 | # 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 | ||
| 101 | # Free Software Foundation, Inc. | ||
| 102 | |||
| 103 | -timestamp='2010-03-22' | ||
| 104 | +timestamp='2010-04-23' | ||
| 105 | |||
| 106 | # This file is (in principle) common to ALL GNU software. | ||
| 107 | # The presence of a machine in this file suggests that SOME GNU software | ||
| 108 | @@ -124,8 +124,9 @@ esac | ||
| 109 | # Here we must recognize all the valid KERNEL-OS combinations. | ||
| 110 | maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` | ||
| 111 | case $maybe_os in | ||
| 112 | - nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \ | ||
| 113 | - uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \ | ||
| 114 | + nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \ | ||
| 115 | + linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ | ||
| 116 | + knetbsd*-gnu* | netbsd*-gnu* | \ | ||
| 117 | kopensolaris*-gnu* | \ | ||
| 118 | storm-chaos* | os2-emx* | rtmk-nova*) | ||
| 119 | os=-$maybe_os | ||
| 120 | @@ -1307,7 +1308,8 @@ case $os in | ||
| 121 | | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ | ||
| 122 | | -chorusos* | -chorusrdb* | -cegcc* \ | ||
| 123 | | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ | ||
| 124 | - | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \ | ||
| 125 | + | -mingw32* | -linux-gnu* | -linux-android* \ | ||
| 126 | + | -linux-newlib* | -linux-uclibc* \ | ||
| 127 | | -uxpv* | -beos* | -mpeix* | -udk* \ | ||
| 128 | | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ | ||
| 129 | | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ | ||
| 130 | Index: gcc-4.5.3/gcc/config.gcc | ||
| 131 | =================================================================== | ||
| 132 | --- gcc-4.5.3.orig/gcc/config.gcc | ||
| 133 | +++ gcc-4.5.3/gcc/config.gcc | ||
| 134 | @@ -513,26 +513,48 @@ case ${target} in | ||
| 135 | *-*-gnu*) | ||
| 136 | tmake_file="$tmake_file t-gnu";; | ||
| 137 | esac | ||
| 138 | - # glibc / uclibc switch. uclibc isn't usable for GNU/Hurd and neither for | ||
| 139 | - # GNU/k*BSD. | ||
| 140 | + # Common C libraries. | ||
| 141 | + tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3" | ||
| 142 | + # glibc / uclibc / bionic switch. | ||
| 143 | + # uclibc and bionic aren't usable for GNU/Hurd and neither for GNU/k*BSD. | ||
| 144 | case $target in | ||
| 145 | *linux*) | ||
| 146 | extra_options="$extra_options linux.opt";; | ||
| 147 | *) | ||
| 148 | tm_defines="$tm_defines OPTION_GLIBC=1";; | ||
| 149 | esac | ||
| 150 | - case ${target} in | ||
| 151 | + case $target in | ||
| 152 | + *-*-*android*) | ||
| 153 | + tm_defines="$tm_defines DEFAULT_LIBC=LIBC_BIONIC" | ||
| 154 | + ;; | ||
| 155 | *-*-*uclibc*) | ||
| 156 | - tm_defines="${tm_defines} UCLIBC_DEFAULT=1" | ||
| 157 | + tm_defines="$tm_defines DEFAULT_LIBC=LIBC_UCLIBC" | ||
| 158 | ;; | ||
| 159 | *) | ||
| 160 | - tm_defines="${tm_defines} UCLIBC_DEFAULT=0" | ||
| 161 | + tm_defines="$tm_defines DEFAULT_LIBC=LIBC_GLIBC" | ||
| 162 | ;; | ||
| 163 | esac | ||
| 164 | - # Assume that glibc or uClibc are being used and so __cxa_atexit is provided. | ||
| 165 | + # Assume that glibc or uClibc or Bionic are being used and so __cxa_atexit | ||
| 166 | + # is provided. | ||
| 167 | default_use_cxa_atexit=yes | ||
| 168 | use_gcc_tgmath=no | ||
| 169 | use_gcc_stdint=wrap | ||
| 170 | + # Add Android userspace support to Linux targets. | ||
| 171 | + case $target in | ||
| 172 | + *linux*) | ||
| 173 | + tm_file="$tm_file linux-android.h" | ||
| 174 | + extra_options="$extra_options linux-android.opt" | ||
| 175 | + ;; | ||
| 176 | + esac | ||
| 177 | + # Enable compilation for Android by default for *android* targets. | ||
| 178 | + case $target in | ||
| 179 | + *-*-*android*) | ||
| 180 | + tm_defines="$tm_defines ANDROID_DEFAULT=1" | ||
| 181 | + ;; | ||
| 182 | + *) | ||
| 183 | + tm_defines="$tm_defines ANDROID_DEFAULT=0" | ||
| 184 | + ;; | ||
| 185 | + esac | ||
| 186 | ;; | ||
| 187 | *-*-netbsd*) | ||
| 188 | tmake_file="t-slibgcc-elf-ver t-libc-ok t-netbsd t-libgcc-pic" | ||
| 189 | @@ -728,7 +750,7 @@ arm*-*-netbsd*) | ||
| 190 | use_collect2=yes | ||
| 191 | ;; | ||
| 192 | arm*-*-linux*) # ARM GNU/Linux with ELF | ||
| 193 | - tm_file="dbxelf.h elfos.h linux.h glibc-stdint.h arm/elf.h arm/linux-gas.h arm/linux-elf.h" | ||
| 194 | + tm_file="dbxelf.h elfos.h linux.h linux-android.h glibc-stdint.h arm/elf.h arm/linux-gas.h arm/linux-elf.h" | ||
| 195 | case $target in | ||
| 196 | arm*b-*) | ||
| 197 | tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1" | ||
| 198 | @@ -739,6 +761,12 @@ arm*-*-linux*) # ARM GNU/Linux with EL | ||
| 199 | arm*-*-linux-*eabi) | ||
| 200 | tm_file="$tm_file arm/bpabi.h arm/linux-eabi.h" | ||
| 201 | tmake_file="$tmake_file arm/t-arm-elf arm/t-bpabi arm/t-linux-eabi t-slibgcc-libgcc" | ||
| 202 | + # Define multilib configuration for arm-linux-androideabi. | ||
| 203 | + case ${target} in | ||
| 204 | + *-androideabi) | ||
| 205 | + tmake_file="$tmake_file arm/t-linux-androideabi" | ||
| 206 | + ;; | ||
| 207 | + esac | ||
| 208 | # The BPABI long long divmod functions return a 128-bit value in | ||
| 209 | # registers r0-r3. Correctly modeling that requires the use of | ||
| 210 | # TImode. | ||
| 211 | @@ -785,9 +813,8 @@ arm*-*-eabi* | arm*-*-symbianelf* ) | ||
| 212 | tmake_file="arm/t-arm arm/t-arm-elf" | ||
| 213 | case ${target} in | ||
| 214 | arm*-*-eabi*) | ||
| 215 | - tm_file="$tm_file arm/eabi.h newlib-stdint.h" | ||
| 216 | + tm_file="$tm_file newlib-stdint.h" | ||
| 217 | tmake_file="${tmake_file} arm/t-bpabi" | ||
| 218 | - extra_options="${extra_options} arm/eabi.opt" | ||
| 219 | use_gcc_stdint=wrap | ||
| 220 | ;; | ||
| 221 | arm*-*-symbianelf*) | ||
| 222 | @@ -843,7 +870,7 @@ bfin*-elf*) | ||
| 223 | bfin*-uclinux*) | ||
| 224 | tm_file="${tm_file} dbxelf.h elfos.h bfin/elf.h linux.h glibc-stdint.h bfin/uclinux.h" | ||
| 225 | tmake_file=bfin/t-bfin-uclinux | ||
| 226 | - tm_defines="${tm_defines} UCLIBC_DEFAULT=1" | ||
| 227 | + tm_defines="${tm_defines} DEFAULT_LIBC=LIBC_UCLIBC" | ||
| 228 | extra_options="${extra_options} linux.opt" | ||
| 229 | use_collect2=no | ||
| 230 | ;; | ||
| 231 | @@ -924,7 +951,7 @@ moxie-*-uclinux*) | ||
| 232 | tm_file="dbxelf.h elfos.h svr4.h ${tm_file} linux.h glibc-stdint.h moxie/uclinux.h" | ||
| 233 | extra_parts="crti.o crtn.o crtbegin.o crtend.o" | ||
| 234 | tmake_file="${tmake_file} moxie/t-moxie moxie/t-moxie-softfp soft-fp/t-softfp" | ||
| 235 | - tm_defines="${tm_defines} UCLIBC_DEFAULT=1" | ||
| 236 | + tm_defines="${tm_defines} DEFAULT_LIBC=LIBC_UCLIBC" | ||
| 237 | extra_options="${extra_options} linux.opt" | ||
| 238 | ;; | ||
| 239 | h8300-*-rtems*) | ||
| 240 | @@ -1644,7 +1671,7 @@ m68k-*-uclinux*) # Motorola m68k/ColdFi | ||
| 241 | default_m68k_cpu=68020 | ||
| 242 | default_cf_cpu=5206 | ||
| 243 | tm_file="${tm_file} dbxelf.h elfos.h svr4.h linux.h glibc-stdint.h flat.h m68k/linux.h m68k/uclinux.h ./sysroot-suffix.h" | ||
| 244 | - tm_defines="${tm_defines} MOTOROLA=1 UCLIBC_DEFAULT=1" | ||
| 245 | + tm_defines="${tm_defines} MOTOROLA=1 DEFAULT_LIBC=LIBC_UCLIBC" | ||
| 246 | extra_options="${extra_options} linux.opt" | ||
| 247 | tmake_file="m68k/t-floatlib m68k/t-uclinux m68k/t-mlibs" | ||
| 248 | ;; | ||
| 249 | Index: gcc-4.5.3/gcc/config/alpha/linux-elf.h | ||
| 250 | =================================================================== | ||
| 251 | --- gcc-4.5.3.orig/gcc/config/alpha/linux-elf.h | ||
| 252 | +++ gcc-4.5.3/gcc/config/alpha/linux-elf.h | ||
| 253 | @@ -29,10 +29,12 @@ along with GCC; see the file COPYING3. | ||
| 254 | |||
| 255 | #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" | ||
| 256 | #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" | ||
| 257 | -#if UCLIBC_DEFAULT | ||
| 258 | -#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:%{muclibc:%e-mglibc and -muclibc used together}" G ";:" U "}" | ||
| 259 | +#if DEFAULT_LIBC == LIBC_UCLIBC | ||
| 260 | +#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" | ||
| 261 | +#elif DEFAULT_LIBC == LIBC_GLIBC | ||
| 262 | +#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}" | ||
| 263 | #else | ||
| 264 | -#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:%{mglibc:%e-mglibc and -muclibc used together}" U ";:" G "}" | ||
| 265 | +#error "Unsupported DEFAULT_LIBC" | ||
| 266 | #endif | ||
| 267 | #define LINUX_DYNAMIC_LINKER \ | ||
| 268 | CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER) | ||
| 269 | Index: gcc-4.5.3/gcc/config/arm/eabi.h | ||
| 270 | =================================================================== | ||
| 271 | --- gcc-4.5.3.orig/gcc/config/arm/eabi.h | ||
| 272 | +++ /dev/null | ||
| 273 | @@ -1,125 +0,0 @@ | ||
| 274 | -/* Configuration file for ARM EABI targets. | ||
| 275 | - Copyright (C) 2008 | ||
| 276 | - Free Software Foundation, Inc. | ||
| 277 | - Contributed by Doug Kwan (dougkwan@google.com) | ||
| 278 | - | ||
| 279 | - This file is part of GCC. | ||
| 280 | - | ||
| 281 | - GCC is free software; you can redistribute it and/or modify it | ||
| 282 | - under the terms of the GNU General Public License as published | ||
| 283 | - by the Free Software Foundation; either version 3, or (at your | ||
| 284 | - option) any later version. | ||
| 285 | - | ||
| 286 | - GCC is distributed in the hope that it will be useful, but WITHOUT | ||
| 287 | - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
| 288 | - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | ||
| 289 | - License for more details. | ||
| 290 | - | ||
| 291 | - You should have received a copy of the GNU General Public License | ||
| 292 | - along with GCC; see the file COPYING3. If not see | ||
| 293 | - <http://www.gnu.org/licenses/>. */ | ||
| 294 | - | ||
| 295 | -/* This file contains macro overrides for EABI targets. */ | ||
| 296 | - | ||
| 297 | -#undef TARGET_OS_CPP_BUILTINS | ||
| 298 | -#define TARGET_OS_CPP_BUILTINS() \ | ||
| 299 | - do \ | ||
| 300 | - { \ | ||
| 301 | - TARGET_BPABI_CPP_BUILTINS (); \ | ||
| 302 | - if (TARGET_ANDROID) \ | ||
| 303 | - builtin_define ("__ANDROID__"); \ | ||
| 304 | - } \ | ||
| 305 | - while (false) | ||
| 306 | - | ||
| 307 | -#undef SUBSUBTARGET_EXTRA_SPECS | ||
| 308 | -#define SUBSUBTARGET_EXTRA_SPECS \ | ||
| 309 | - { "link_android", ANDROID_LINK_SPEC }, \ | ||
| 310 | - { "link_default", BPABI_LINK_SPEC }, \ | ||
| 311 | - { "cc1_android", ANDROID_CC1_SPEC }, \ | ||
| 312 | - { "cc1_default", CC1_DEFAULT_SPEC }, \ | ||
| 313 | - { "cc1plus_android", ANDROID_CC1PLUS_SPEC }, \ | ||
| 314 | - { "cc1plus_default", CC1PLUS_DEFAULT_SPEC }, \ | ||
| 315 | - { "lib_android", ANDROID_LIB_SPEC }, \ | ||
| 316 | - { "lib_default", LIB_DEFAULT_SPEC }, \ | ||
| 317 | - { "startfile_android", ANDROID_STARTFILE_SPEC }, \ | ||
| 318 | - { "startfile_default", UNKNOWN_ELF_STARTFILE_SPEC }, \ | ||
| 319 | - { "endfile_android", ANDROID_ENDFILE_SPEC }, \ | ||
| 320 | - { "endfile_default", UNKNOWN_ELF_ENDFILE_SPEC }, \ | ||
| 321 | - | ||
| 322 | -#undef ANDROID_LINK_SPEC | ||
| 323 | -#define ANDROID_LINK_SPEC \ | ||
| 324 | -"%{mbig-endian:-EB} %{mlittle-endian:-EL} " \ | ||
| 325 | -"%{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic} " \ | ||
| 326 | -"%{!static:" \ | ||
| 327 | - "%{shared: -Bsymbolic} " \ | ||
| 328 | - "%{!shared:" \ | ||
| 329 | - "%{rdynamic:-export-dynamic} " \ | ||
| 330 | - "%{!dynamic-linker:-dynamic-linker /system/bin/linker}}} " \ | ||
| 331 | -"-X" SUBTARGET_EXTRA_LINK_SPEC | ||
| 332 | - | ||
| 333 | -/* Override LINK_SPEC in bpabi.h. */ | ||
| 334 | -#undef LINK_SPEC | ||
| 335 | -#define LINK_SPEC \ | ||
| 336 | -"%{mandroid: %(link_android) ;" \ | ||
| 337 | -" : %(link_default)}" | ||
| 338 | - | ||
| 339 | -/* Android uses -fno-exceptions by default. */ | ||
| 340 | -#undef ANDROID_CC1_SPEC | ||
| 341 | -#define ANDROID_CC1_SPEC "%{!fexceptions:-fno-exceptions}" | ||
| 342 | - | ||
| 343 | -/* Default CC1_SPEC as in arm.h. */ | ||
| 344 | -#undef CC1_DEFAULT_SPEC | ||
| 345 | -#define CC1_DEFAULT_SPEC "" | ||
| 346 | - | ||
| 347 | -#undef CC1_SPEC | ||
| 348 | -#define CC1_SPEC \ | ||
| 349 | -"%{mandroid: %(cc1_android) ;" \ | ||
| 350 | -" : %(cc1_default)}" | ||
| 351 | - | ||
| 352 | -/* Android uses -fno-rtti by default. */ | ||
| 353 | -#undef ANDROID_CC1PLUS_SPEC | ||
| 354 | -#define ANDROID_CC1PLUS_SPEC "%{!frtti:-fno-rtti}" | ||
| 355 | - | ||
| 356 | -/* Default CC1PLUS_SPEC as in gcc.c. */ | ||
| 357 | -#undef CC1PLUS_DEFAULT_SPEC | ||
| 358 | -#define CC1PLUS_DEFAULT_SPEC "" | ||
| 359 | - | ||
| 360 | -#undef CC1PLUS_SPEC | ||
| 361 | -#define CC1PLUS_SPEC \ | ||
| 362 | -"%{mandroid: %(cc1plus_android) ;" \ | ||
| 363 | -" : %(cc1plus_default)}" | ||
| 364 | - | ||
| 365 | -#undef ANDROID_LIB_SPEC | ||
| 366 | -#define ANDROID_LIB_SPEC "-lc %{!static:-ldl}" | ||
| 367 | - | ||
| 368 | -/* Default LIB_SPEC as in gcc.c. */ | ||
| 369 | -#undef LIB_DEFAULT_SPEC | ||
| 370 | -#define LIB_DEFAULT_SPEC \ | ||
| 371 | -"%{!shared:%{g*:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}" | ||
| 372 | - | ||
| 373 | -#undef LIB_SPEC | ||
| 374 | -#define LIB_SPEC \ | ||
| 375 | -"%{mandroid: %(lib_android) ;" \ | ||
| 376 | -" : %(lib_default)}" | ||
| 377 | - | ||
| 378 | -#undef ANDROID_STARTFILE_SPEC | ||
| 379 | -#define ANDROID_STARTFILE_SPEC \ | ||
| 380 | -"%{!shared:" \ | ||
| 381 | - "%{static: crtbegin_static%O%s ;" \ | ||
| 382 | - " : crtbegin_dynamic%O%s}}" | ||
| 383 | - | ||
| 384 | -/* Override STARTFILE_SPEC in unknown-elf.h. */ | ||
| 385 | -#undef STARTFILE_SPEC | ||
| 386 | -#define STARTFILE_SPEC \ | ||
| 387 | -"%{mandroid: %(startfile_android) ;" \ | ||
| 388 | -" : %(startfile_default)}" | ||
| 389 | - | ||
| 390 | -#undef ANDROID_ENDFILE_SPEC | ||
| 391 | -#define ANDROID_ENDFILE_SPEC "%{!shared:crtend_android%O%s}" | ||
| 392 | - | ||
| 393 | -/* Override ENDFILE_SPEC in unknown-elf.h. */ | ||
| 394 | -#undef ENDFILE_SPEC | ||
| 395 | -#define ENDFILE_SPEC \ | ||
| 396 | -"%{mandroid: %(endfile_android) ;" \ | ||
| 397 | -" : %(endfile_default)}" | ||
| 398 | - | ||
| 399 | Index: gcc-4.5.3/gcc/config/arm/eabi.opt | ||
| 400 | =================================================================== | ||
| 401 | --- gcc-4.5.3.orig/gcc/config/arm/eabi.opt | ||
| 402 | +++ /dev/null | ||
| 403 | @@ -1,23 +0,0 @@ | ||
| 404 | -; EABI specific options for ARM port of the compiler. | ||
| 405 | - | ||
| 406 | -; Copyright (C) 2008 Free Software Foundation, Inc. | ||
| 407 | -; | ||
| 408 | -; This file is part of GCC. | ||
| 409 | -; | ||
| 410 | -; GCC is free software; you can redistribute it and/or modify it under | ||
| 411 | -; the terms of the GNU General Public License as published by the Free | ||
| 412 | -; Software Foundation; either version 3, or (at your option) any later | ||
| 413 | -; version. | ||
| 414 | -; | ||
| 415 | -; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | ||
| 416 | -; WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 417 | -; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
| 418 | -; for more details. | ||
| 419 | -; | ||
| 420 | -; You should have received a copy of the GNU General Public License | ||
| 421 | -; along with GCC; see the file COPYING3. If not see | ||
| 422 | -; <http://www.gnu.org/licenses/>. | ||
| 423 | - | ||
| 424 | -mandroid | ||
| 425 | -Target Report RejectNegative Mask(ANDROID) | ||
| 426 | -Generate code for the Android operating system. | ||
| 427 | Index: gcc-4.5.3/gcc/config/arm/linux-eabi.h | ||
| 428 | =================================================================== | ||
| 429 | --- gcc-4.5.3.orig/gcc/config/arm/linux-eabi.h | ||
| 430 | +++ gcc-4.5.3/gcc/config/arm/linux-eabi.h | ||
| 431 | @@ -70,7 +70,30 @@ | ||
| 432 | /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to | ||
| 433 | use the GNU/Linux version, not the generic BPABI version. */ | ||
| 434 | #undef LINK_SPEC | ||
| 435 | -#define LINK_SPEC LINUX_TARGET_LINK_SPEC BE8_LINK_SPEC TARGET_FIX_V4BX_SPEC | ||
| 436 | +#define LINK_SPEC BE8_LINK_SPEC TARGET_FIX_V4BX_SPEC \ | ||
| 437 | + LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \ | ||
| 438 | + LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC) | ||
| 439 | + | ||
| 440 | +#undef CC1_SPEC | ||
| 441 | +#define CC1_SPEC \ | ||
| 442 | + LINUX_OR_ANDROID_CC (LINUX_TARGET_CC1_SPEC, \ | ||
| 443 | + LINUX_TARGET_CC1_SPEC " " ANDROID_CC1_SPEC) | ||
| 444 | + | ||
| 445 | +#define CC1PLUS_SPEC \ | ||
| 446 | + LINUX_OR_ANDROID_CC ("", ANDROID_CC1PLUS_SPEC) | ||
| 447 | + | ||
| 448 | +#undef LIB_SPEC | ||
| 449 | +#define LIB_SPEC \ | ||
| 450 | + LINUX_OR_ANDROID_LD (LINUX_TARGET_LIB_SPEC, \ | ||
| 451 | + LINUX_TARGET_LIB_SPEC " " ANDROID_LIB_SPEC) | ||
| 452 | + | ||
| 453 | +#undef STARTFILE_SPEC | ||
| 454 | +#define STARTFILE_SPEC \ | ||
| 455 | + LINUX_OR_ANDROID_LD (LINUX_TARGET_STARTFILE_SPEC, ANDROID_STARTFILE_SPEC) | ||
| 456 | + | ||
| 457 | +#undef ENDFILE_SPEC | ||
| 458 | +#define ENDFILE_SPEC \ | ||
| 459 | + LINUX_OR_ANDROID_LD (LINUX_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC) | ||
| 460 | |||
| 461 | /* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we | ||
| 462 | do not use -lfloat. */ | ||
| 463 | Index: gcc-4.5.3/gcc/config/arm/t-linux-androideabi | ||
| 464 | =================================================================== | ||
| 465 | --- /dev/null | ||
| 466 | +++ gcc-4.5.3/gcc/config/arm/t-linux-androideabi | ||
| 467 | @@ -0,0 +1,10 @@ | ||
| 468 | +MULTILIB_OPTIONS = march=armv7-a mthumb | ||
| 469 | +MULTILIB_DIRNAMES = armv7-a thumb | ||
| 470 | +MULTILIB_EXCEPTIONS = | ||
| 471 | +MULTILIB_MATCHES = | ||
| 472 | +MULTILIB_OSDIRNAMES = | ||
| 473 | + | ||
| 474 | +# The "special" multilib can be used to build native applications for Android, | ||
| 475 | +# as opposed to native shared libraries that are then called via JNI. | ||
| 476 | +#MULTILIB_OPTIONS += tno-android-cc | ||
| 477 | +#MULTILIB_DIRNAMES += special | ||
| 478 | Index: gcc-4.5.3/gcc/config/linux-android.h | ||
| 479 | =================================================================== | ||
| 480 | --- /dev/null | ||
| 481 | +++ gcc-4.5.3/gcc/config/linux-android.h | ||
| 482 | @@ -0,0 +1,53 @@ | ||
| 483 | +/* Configuration file for Linux Android targets. | ||
| 484 | + Copyright (C) 2010 | ||
| 485 | + Free Software Foundation, Inc. | ||
| 486 | + Contributed by CodeSourcery, Inc. | ||
| 487 | + | ||
| 488 | + This file is part of GCC. | ||
| 489 | + | ||
| 490 | + GCC is free software; you can redistribute it and/or modify it | ||
| 491 | + under the terms of the GNU General Public License as published | ||
| 492 | + by the Free Software Foundation; either version 3, or (at your | ||
| 493 | + option) any later version. | ||
| 494 | + | ||
| 495 | + GCC is distributed in the hope that it will be useful, but WITHOUT | ||
| 496 | + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
| 497 | + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | ||
| 498 | + License for more details. | ||
| 499 | + | ||
| 500 | + You should have received a copy of the GNU General Public License | ||
| 501 | + along with GCC; see the file COPYING3. If not see | ||
| 502 | + <http://www.gnu.org/licenses/>. */ | ||
| 503 | + | ||
| 504 | +#if ANDROID_DEFAULT | ||
| 505 | +# define NOANDROID "mno-android" | ||
| 506 | +#else | ||
| 507 | +# define NOANDROID "!mandroid" | ||
| 508 | +#endif | ||
| 509 | + | ||
| 510 | +#define LINUX_OR_ANDROID_CC(LINUX_SPEC, ANDROID_SPEC) \ | ||
| 511 | + "%{" NOANDROID "|tno-android-cc:" LINUX_SPEC ";:" ANDROID_SPEC "}" | ||
| 512 | + | ||
| 513 | +#define LINUX_OR_ANDROID_LD(LINUX_SPEC, ANDROID_SPEC) \ | ||
| 514 | + "%{" NOANDROID "|tno-android-ld:" LINUX_SPEC ";:" ANDROID_SPEC "}" | ||
| 515 | + | ||
| 516 | +#define ANDROID_LINK_SPEC \ | ||
| 517 | + "%{shared: -Bsymbolic}" | ||
| 518 | + | ||
| 519 | +#define ANDROID_CC1_SPEC \ | ||
| 520 | + "%{!mglibc:%{!muclibc:%{!mbionic: -mbionic}}} " \ | ||
| 521 | + "%{!fno-pic:%{!fno-PIC:%{!fpic:%{!fPIC: -fPIC}}}}" | ||
| 522 | + | ||
| 523 | +#define ANDROID_CC1PLUS_SPEC \ | ||
| 524 | + "%{!fexceptions:%{!fno-exceptions: -fno-exceptions}} " \ | ||
| 525 | + "%{!frtti:%{!fno-rtti: -fno-rtti}}" | ||
| 526 | + | ||
| 527 | +#define ANDROID_LIB_SPEC \ | ||
| 528 | + "%{!static: -ldl}" | ||
| 529 | + | ||
| 530 | +#define ANDROID_STARTFILE_SPEC \ | ||
| 531 | + "%{!shared:" \ | ||
| 532 | + " %{static: crtbegin_static%O%s;: crtbegin_dynamic%O%s}}" | ||
| 533 | + | ||
| 534 | +#define ANDROID_ENDFILE_SPEC \ | ||
| 535 | + "%{!shared: crtend_android%O%s}" | ||
| 536 | Index: gcc-4.5.3/gcc/config/linux-android.opt | ||
| 537 | =================================================================== | ||
| 538 | --- /dev/null | ||
| 539 | +++ gcc-4.5.3/gcc/config/linux-android.opt | ||
| 540 | @@ -0,0 +1,23 @@ | ||
| 541 | +; Android specific options. | ||
| 542 | + | ||
| 543 | +; Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 544 | +; | ||
| 545 | +; This file is part of GCC. | ||
| 546 | +; | ||
| 547 | +; GCC is free software; you can redistribute it and/or modify it under | ||
| 548 | +; the terms of the GNU General Public License as published by the Free | ||
| 549 | +; Software Foundation; either version 3, or (at your option) any later | ||
| 550 | +; version. | ||
| 551 | +; | ||
| 552 | +; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | ||
| 553 | +; WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 554 | +; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
| 555 | +; for more details. | ||
| 556 | +; | ||
| 557 | +; You should have received a copy of the GNU General Public License | ||
| 558 | +; along with GCC; see the file COPYING3. If not see | ||
| 559 | +; <http://www.gnu.org/licenses/>. | ||
| 560 | + | ||
| 561 | +mandroid | ||
| 562 | +Target Report Mask(ANDROID) Var(flag_android) Init(ANDROID_DEFAULT ? OPTION_MASK_ANDROID : 0) | ||
| 563 | +Generate code for the Android platform. | ||
| 564 | Index: gcc-4.5.3/gcc/config/linux.h | ||
| 565 | =================================================================== | ||
| 566 | --- gcc-4.5.3.orig/gcc/config/linux.h | ||
| 567 | +++ gcc-4.5.3/gcc/config/linux.h | ||
| 568 | @@ -1,6 +1,6 @@ | ||
| 569 | /* Definitions for Linux-based GNU systems with ELF format | ||
| 570 | Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003, 2004, 2005, 2006, | ||
| 571 | - 2007, 2009 Free Software Foundation, Inc. | ||
| 572 | + 2007, 2009, 2010 Free Software Foundation, Inc. | ||
| 573 | Contributed by Eric Youngdale. | ||
| 574 | Modified for stabs-in-ELF by H.J. Lu (hjl@lucon.org). | ||
| 575 | |||
| 576 | @@ -42,16 +42,17 @@ see the files COPYING3 and COPYING.RUNTI | ||
| 577 | provides part of the support for getting C++ file-scope static | ||
| 578 | object constructed before entering `main'. */ | ||
| 579 | |||
| 580 | -#undef STARTFILE_SPEC | ||
| 581 | #if defined HAVE_LD_PIE | ||
| 582 | -#define STARTFILE_SPEC \ | ||
| 583 | +#define LINUX_TARGET_STARTFILE_SPEC \ | ||
| 584 | "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \ | ||
| 585 | crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}" | ||
| 586 | #else | ||
| 587 | -#define STARTFILE_SPEC \ | ||
| 588 | +#define LINUX_TARGET_STARTFILE_SPEC \ | ||
| 589 | "%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \ | ||
| 590 | crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}" | ||
| 591 | #endif | ||
| 592 | +#undef STARTFILE_SPEC | ||
| 593 | +#define STARTFILE_SPEC LINUX_TARGET_STARTFILE_SPEC | ||
| 594 | |||
| 595 | /* Provide a ENDFILE_SPEC appropriate for GNU/Linux. Here we tack on | ||
| 596 | the GNU/Linux magical crtend.o file (see crtstuff.c) which | ||
| 597 | @@ -59,33 +60,44 @@ see the files COPYING3 and COPYING.RUNTI | ||
| 598 | object constructed before entering `main', followed by a normal | ||
| 599 | GNU/Linux "finalizer" file, `crtn.o'. */ | ||
| 600 | |||
| 601 | -#undef ENDFILE_SPEC | ||
| 602 | -#define ENDFILE_SPEC \ | ||
| 603 | +#define LINUX_TARGET_ENDFILE_SPEC \ | ||
| 604 | "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s" | ||
| 605 | +#undef ENDFILE_SPEC | ||
| 606 | +#define ENDFILE_SPEC LINUX_TARGET_ENDFILE_SPEC | ||
| 607 | |||
| 608 | /* This is for -profile to use -lc_p instead of -lc. */ | ||
| 609 | +#define LINUX_TARGET_CC1_SPEC "%{profile:-p}" | ||
| 610 | #ifndef CC1_SPEC | ||
| 611 | -#define CC1_SPEC "%{profile:-p}" | ||
| 612 | +#define CC1_SPEC LINUX_TARGET_CC1_SPEC | ||
| 613 | #endif | ||
| 614 | |||
| 615 | /* The GNU C++ standard library requires that these macros be defined. */ | ||
| 616 | #undef CPLUSPLUS_CPP_SPEC | ||
| 617 | #define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" | ||
| 618 | |||
| 619 | -#undef LIB_SPEC | ||
| 620 | -#define LIB_SPEC \ | ||
| 621 | +#define LINUX_TARGET_LIB_SPEC \ | ||
| 622 | "%{pthread:-lpthread} \ | ||
| 623 | %{shared:-lc} \ | ||
| 624 | %{!shared:%{mieee-fp:-lieee} %{profile:-lc_p}%{!profile:-lc}}" | ||
| 625 | +#undef LIB_SPEC | ||
| 626 | +#define LIB_SPEC LINUX_TARGET_LIB_SPEC | ||
| 627 | + | ||
| 628 | +/* C libraries supported on Linux. */ | ||
| 629 | +#define OPTION_GLIBC (linux_libc == LIBC_GLIBC) | ||
| 630 | +#define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC) | ||
| 631 | +#define OPTION_BIONIC (linux_libc == LIBC_BIONIC) | ||
| 632 | |||
| 633 | #define LINUX_TARGET_OS_CPP_BUILTINS() \ | ||
| 634 | do { \ | ||
| 635 | - builtin_define ("__gnu_linux__"); \ | ||
| 636 | + if (OPTION_GLIBC) \ | ||
| 637 | + builtin_define ("__gnu_linux__"); \ | ||
| 638 | builtin_define_std ("linux"); \ | ||
| 639 | builtin_define_std ("unix"); \ | ||
| 640 | builtin_assert ("system=linux"); \ | ||
| 641 | builtin_assert ("system=unix"); \ | ||
| 642 | builtin_assert ("system=posix"); \ | ||
| 643 | + if (OPTION_ANDROID) \ | ||
| 644 | + builtin_define ("__ANDROID__"); \ | ||
| 645 | } while (0) | ||
| 646 | |||
| 647 | #if defined(HAVE_LD_EH_FRAME_HDR) | ||
| 648 | @@ -105,13 +117,24 @@ see the files COPYING3 and COPYING.RUNTI | ||
| 649 | #endif | ||
| 650 | |||
| 651 | /* Determine which dynamic linker to use depending on whether GLIBC or | ||
| 652 | - uClibc is the default C library and whether -muclibc or -mglibc has | ||
| 653 | - been passed to change the default. */ | ||
| 654 | -#if UCLIBC_DEFAULT | ||
| 655 | -#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:%{muclibc:%e-mglibc and -muclibc used together}" G ";:" U "}" | ||
| 656 | + uClibc or Bionic is the default C library and whether | ||
| 657 | + -muclibc or -mglibc or -mbionic has been passed to change the default. */ | ||
| 658 | + | ||
| 659 | +#define CHOOSE_DYNAMIC_LINKER1(LIBC1, LIBC2, LIBC3, LD1, LD2, LD3) \ | ||
| 660 | + "%{" LIBC2 ":" LD2 ";:%{" LIBC3 ":" LD3 ";:" LD1 "}}" | ||
| 661 | + | ||
| 662 | +#if DEFAULT_LIBC == LIBC_GLIBC | ||
| 663 | +#define CHOOSE_DYNAMIC_LINKER(G, U, B) \ | ||
| 664 | + CHOOSE_DYNAMIC_LINKER1 ("mglibc", "muclibc", "mbionic", G, U, B) | ||
| 665 | +#elif DEFAULT_LIBC == LIBC_UCLIBC | ||
| 666 | +#define CHOOSE_DYNAMIC_LINKER(G, U, B) \ | ||
| 667 | + CHOOSE_DYNAMIC_LINKER1 ("muclibc", "mglibc", "mbionic", U, G, B) | ||
| 668 | +#elif DEFAULT_LIBC == LIBC_BIONIC | ||
| 669 | +#define CHOOSE_DYNAMIC_LINKER(G, U, B) \ | ||
| 670 | + CHOOSE_DYNAMIC_LINKER1 ("mbionic", "mglibc", "muclibc", B, G, U) | ||
| 671 | #else | ||
| 672 | -#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:%{mglibc:%e-mglibc and -muclibc used together}" U ";:" G "}" | ||
| 673 | -#endif | ||
| 674 | +#error "Unsupported DEFAULT_LIBC" | ||
| 675 | +#endif /* DEFAULT_LIBC */ | ||
| 676 | |||
| 677 | /* For most targets the following definitions suffice; | ||
| 678 | GLIBC_DYNAMIC_LINKER must be defined for each target using them, or | ||
| 679 | @@ -120,18 +143,25 @@ see the files COPYING3 and COPYING.RUNTI | ||
| 680 | #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" | ||
| 681 | #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0" | ||
| 682 | #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0" | ||
| 683 | -#define LINUX_DYNAMIC_LINKER \ | ||
| 684 | - CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER) | ||
| 685 | -#define LINUX_DYNAMIC_LINKER32 \ | ||
| 686 | - CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32) | ||
| 687 | -#define LINUX_DYNAMIC_LINKER64 \ | ||
| 688 | - CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64) | ||
| 689 | +#define BIONIC_DYNAMIC_LINKER "/system/bin/linker" | ||
| 690 | +#define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker" | ||
| 691 | +#define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64" | ||
| 692 | + | ||
| 693 | +#define LINUX_DYNAMIC_LINKER \ | ||
| 694 | + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, \ | ||
| 695 | + BIONIC_DYNAMIC_LINKER) | ||
| 696 | +#define LINUX_DYNAMIC_LINKER32 \ | ||
| 697 | + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, \ | ||
| 698 | + BIONIC_DYNAMIC_LINKER32) | ||
| 699 | +#define LINUX_DYNAMIC_LINKER64 \ | ||
| 700 | + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, \ | ||
| 701 | + BIONIC_DYNAMIC_LINKER64) | ||
| 702 | |||
| 703 | /* Determine whether the entire c99 runtime | ||
| 704 | is present in the runtime library. */ | ||
| 705 | #define TARGET_C99_FUNCTIONS (OPTION_GLIBC) | ||
| 706 | |||
| 707 | /* Whether we have sincos that follows the GNU extension. */ | ||
| 708 | -#define TARGET_HAS_SINCOS (OPTION_GLIBC) | ||
| 709 | +#define TARGET_HAS_SINCOS (OPTION_GLIBC | OPTION_BIONIC) | ||
| 710 | |||
| 711 | #define TARGET_POSIX_IO | ||
| 712 | Index: gcc-4.5.3/gcc/config/linux.opt | ||
| 713 | =================================================================== | ||
| 714 | --- gcc-4.5.3.orig/gcc/config/linux.opt | ||
| 715 | +++ gcc-4.5.3/gcc/config/linux.opt | ||
| 716 | @@ -1,6 +1,6 @@ | ||
| 717 | ; Processor-independent options for GNU/Linux. | ||
| 718 | ; | ||
| 719 | -; Copyright (C) 2006, 2007, 2009 Free Software Foundation, Inc. | ||
| 720 | +; Copyright (C) 2006, 2007, 2009, 2010 Free Software Foundation, Inc. | ||
| 721 | ; Contributed by CodeSourcery. | ||
| 722 | ; | ||
| 723 | ; This file is part of GCC. | ||
| 724 | @@ -19,10 +19,14 @@ | ||
| 725 | ; along with GCC; see the file COPYING3. If not see | ||
| 726 | ; <http://www.gnu.org/licenses/>. | ||
| 727 | |||
| 728 | +mbionic | ||
| 729 | +Target Report RejectNegative Var(linux_libc,LIBC_BIONIC) Init(DEFAULT_LIBC) Negative(mglibc) | ||
| 730 | +Use Bionic C library | ||
| 731 | + | ||
| 732 | mglibc | ||
| 733 | -Target RejectNegative Report InverseMask(UCLIBC, GLIBC) Var(linux_uclibc) Init(UCLIBC_DEFAULT ? OPTION_MASK_UCLIBC : 0) | ||
| 734 | -Use GNU libc instead of uClibc | ||
| 735 | +Target Report RejectNegative Var(linux_libc,LIBC_GLIBC) VarExists Negative(muclibc) | ||
| 736 | +Use GNU C library | ||
| 737 | |||
| 738 | muclibc | ||
| 739 | -Target RejectNegative Report Mask(UCLIBC) Var(linux_uclibc) VarExists | ||
| 740 | -Use uClibc instead of GNU libc | ||
| 741 | +Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) VarExists Negative(mbionic) | ||
| 742 | +Use uClibc C library | ||
| 743 | Index: gcc-4.5.3/gcc/config/rs6000/linux64.h | ||
| 744 | =================================================================== | ||
| 745 | --- gcc-4.5.3.orig/gcc/config/rs6000/linux64.h | ||
| 746 | +++ gcc-4.5.3/gcc/config/rs6000/linux64.h | ||
| 747 | @@ -344,10 +344,12 @@ extern int dot_symbols; | ||
| 748 | #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld64.so.1" | ||
| 749 | #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0" | ||
| 750 | #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0" | ||
| 751 | -#if UCLIBC_DEFAULT | ||
| 752 | -#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:%{muclibc:%e-mglibc and -muclibc used together}" G ";:" U "}" | ||
| 753 | +#if DEFAULT_LIBC == LIBC_UCLIBC | ||
| 754 | +#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" | ||
| 755 | +#elif DEFAULT_LIBC == LIBC_GLIBC | ||
| 756 | +#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}" | ||
| 757 | #else | ||
| 758 | -#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:%{mglibc:%e-mglibc and -muclibc used together}" U ";:" G "}" | ||
| 759 | +#error "Unsupported DEFAULT_LIBC" | ||
| 760 | #endif | ||
| 761 | #define LINUX_DYNAMIC_LINKER32 \ | ||
| 762 | CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32) | ||
| 763 | Index: gcc-4.5.3/gcc/config/rs6000/sysv4.h | ||
| 764 | =================================================================== | ||
| 765 | --- gcc-4.5.3.orig/gcc/config/rs6000/sysv4.h | ||
| 766 | +++ gcc-4.5.3/gcc/config/rs6000/sysv4.h | ||
| 767 | @@ -901,10 +901,12 @@ SVR4_ASM_SPEC \ | ||
| 768 | |||
| 769 | #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" | ||
| 770 | #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" | ||
| 771 | -#if UCLIBC_DEFAULT | ||
| 772 | -#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:%{muclibc:%e-mglibc and -muclibc used together}" G ";:" U "}" | ||
| 773 | +#if DEFAULT_LIBC == LIBC_UCLIBC | ||
| 774 | +#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" | ||
| 775 | +#elif DEFAULT_LIBC == LIBC_GLIBC | ||
| 776 | +#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}" | ||
| 777 | #else | ||
| 778 | -#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:%{mglibc:%e-mglibc and -muclibc used together}" U ";:" G "}" | ||
| 779 | +#error "Unsupported DEFAULT_LIBC" | ||
| 780 | #endif | ||
| 781 | #define LINUX_DYNAMIC_LINKER \ | ||
| 782 | CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER) | ||
| 783 | Index: gcc-4.5.3/gcc/doc/invoke.texi | ||
| 784 | =================================================================== | ||
| 785 | --- gcc-4.5.3.orig/gcc/doc/invoke.texi | ||
| 786 | +++ gcc-4.5.3/gcc/doc/invoke.texi | ||
| 787 | @@ -565,7 +565,8 @@ Objective-C and Objective-C++ Dialects}. | ||
| 788 | -mcpu=@var{cpu}} | ||
| 789 | |||
| 790 | @emph{GNU/Linux Options} | ||
| 791 | -@gccoptlist{-muclibc} | ||
| 792 | +@gccoptlist{-mglibc -muclibc -mbionic -mandroid @gol | ||
| 793 | +-tno-android-cc -tno-android-ld} | ||
| 794 | |||
| 795 | @emph{H8/300 Options} | ||
| 796 | @gccoptlist{-mrelax -mh -ms -mn -mint32 -malign-300} | ||
| 797 | @@ -11469,13 +11470,41 @@ These @samp{-m} options are defined for | ||
| 798 | @table @gcctabopt | ||
| 799 | @item -mglibc | ||
| 800 | @opindex mglibc | ||
| 801 | -Use the GNU C library instead of uClibc. This is the default except | ||
| 802 | -on @samp{*-*-linux-*uclibc*} targets. | ||
| 803 | +Use the GNU C library. This is the default except | ||
| 804 | +on @samp{*-*-linux-*uclibc*} and @samp{*-*-linux-*android*} targets. | ||
| 805 | |||
| 806 | @item -muclibc | ||
| 807 | @opindex muclibc | ||
| 808 | -Use uClibc instead of the GNU C library. This is the default on | ||
| 809 | +Use uClibc C library. This is the default on | ||
| 810 | @samp{*-*-linux-*uclibc*} targets. | ||
| 811 | + | ||
| 812 | +@item -mbionic | ||
| 813 | +@opindex mbionic | ||
| 814 | +Use Bionic C library. This is the default on | ||
| 815 | +@samp{*-*-linux-*android*} targets. | ||
| 816 | + | ||
| 817 | +@item -mandroid | ||
| 818 | +@opindex mandroid | ||
| 819 | +Compile code compatible with Android platform. This is the default on | ||
| 820 | +@samp{*-*-linux-*android*} targets. | ||
| 821 | + | ||
| 822 | +When compiling, this option enables @option{-mbionic}, @option{-fPIC}, | ||
| 823 | +@option{-fno-exceptions} and @option{-fno-rtti} by default. When linking, | ||
| 824 | +this option makes the GCC driver pass Android-specific options to the linker. | ||
| 825 | +Finally, this option causes the preprocessor macro @code{__ANDROID__} | ||
| 826 | +to be defined. | ||
| 827 | + | ||
| 828 | +@item -tno-android-cc | ||
| 829 | +@opindex tno-android-cc | ||
| 830 | +Disable compilation effects of @option{-mandroid}, i.e., do not enable | ||
| 831 | +@option{-mbionic}, @option{-fPIC}, @option{-fno-exceptions} and | ||
| 832 | +@option{-fno-rtti} by default. | ||
| 833 | + | ||
| 834 | +@item -tno-android-ld | ||
| 835 | +@opindex tno-android-ld | ||
| 836 | +Disable linking effects of @option{-mandroid}, i.e., pass standard Linux | ||
| 837 | +linking options to the linker. | ||
| 838 | + | ||
| 839 | @end table | ||
| 840 | |||
| 841 | @node H8/300 Options | ||
| 842 | Index: gcc-4.5.3/gcc/gthr-posix.h | ||
| 843 | =================================================================== | ||
| 844 | --- gcc-4.5.3.orig/gcc/gthr-posix.h | ||
| 845 | +++ gcc-4.5.3/gcc/gthr-posix.h | ||
| 846 | @@ -124,7 +124,9 @@ __gthrw(pthread_join) | ||
| 847 | __gthrw(pthread_equal) | ||
| 848 | __gthrw(pthread_self) | ||
| 849 | __gthrw(pthread_detach) | ||
| 850 | +#ifndef __BIONIC__ | ||
| 851 | __gthrw(pthread_cancel) | ||
| 852 | +#endif | ||
| 853 | __gthrw(sched_yield) | ||
| 854 | |||
| 855 | __gthrw(pthread_mutex_lock) | ||
| 856 | @@ -238,7 +240,15 @@ static inline int | ||
| 857 | __gthread_active_p (void) | ||
| 858 | { | ||
| 859 | static void *const __gthread_active_ptr | ||
| 860 | - = __extension__ (void *) &__gthrw_(pthread_cancel); | ||
| 861 | + = __extension__ (void *) &__gthrw_( | ||
| 862 | +/* Android's C library does not provide pthread_cancel, check for | ||
| 863 | + `pthread_create' instead. */ | ||
| 864 | +#ifndef __BIONIC__ | ||
| 865 | + pthread_cancel | ||
| 866 | +#else | ||
| 867 | + pthread_create | ||
| 868 | +#endif | ||
| 869 | + ); | ||
| 870 | return __gthread_active_ptr != 0; | ||
| 871 | } | ||
| 872 | |||
| 873 | Index: gcc-4.5.3/gcc/testsuite/gcc.dg/glibc-uclibc-1.c | ||
| 874 | =================================================================== | ||
| 875 | --- gcc-4.5.3.orig/gcc/testsuite/gcc.dg/glibc-uclibc-1.c | ||
| 876 | +++ /dev/null | ||
| 877 | @@ -1,6 +0,0 @@ | ||
| 878 | -/* Test -mglibc and -muclibc not allowed together. */ | ||
| 879 | -/* Origin: Joseph Myers <joseph@codesourcery.com> */ | ||
| 880 | -/* { dg-do link { target *-*-linux* } } */ | ||
| 881 | -/* { dg-options "-mglibc -muclibc" } */ | ||
| 882 | - | ||
| 883 | -/* { dg-message "-mglibc and -muclibc used together" "" { target *-*-* } 0 } */ | ||
| 884 | Index: gcc-4.5.3/gcc/testsuite/gcc.dg/glibc-uclibc-2.c | ||
| 885 | =================================================================== | ||
| 886 | --- gcc-4.5.3.orig/gcc/testsuite/gcc.dg/glibc-uclibc-2.c | ||
| 887 | +++ /dev/null | ||
| 888 | @@ -1,6 +0,0 @@ | ||
| 889 | -/* Test -mglibc and -muclibc not allowed together. */ | ||
| 890 | -/* Origin: Joseph Myers <joseph@codesourcery.com> */ | ||
| 891 | -/* { dg-do link { target *-*-linux* } } */ | ||
| 892 | -/* { dg-options "-muclibc -mglibc" } */ | ||
| 893 | - | ||
| 894 | -/* { dg-message "-mglibc and -muclibc used together" "" { target *-*-* } 0 } */ | ||
| 895 | Index: gcc-4.5.3/libstdc++-v3/acinclude.m4 | ||
| 896 | =================================================================== | ||
| 897 | --- gcc-4.5.3.orig/libstdc++-v3/acinclude.m4 | ||
| 898 | +++ gcc-4.5.3/libstdc++-v3/acinclude.m4 | ||
| 899 | @@ -95,7 +95,7 @@ AC_DEFUN([GLIBCXX_CONFIGURE], [ | ||
| 900 | ## (Right now, this only matters for enable_wchar_t, but nothing prevents | ||
| 901 | ## other macros from doing the same. This should be automated.) -pme | ||
| 902 | |||
| 903 | - # Check for uClibc since Linux platforms use different configuration | ||
| 904 | + # Check for C library flavor since Linux platforms use different configuration | ||
| 905 | # directories depending on the C library in use. | ||
| 906 | AC_EGREP_CPP([_using_uclibc], [ | ||
| 907 | #include <stdio.h> | ||
| 908 | @@ -104,6 +104,13 @@ AC_DEFUN([GLIBCXX_CONFIGURE], [ | ||
| 909 | #endif | ||
| 910 | ], uclibc=yes, uclibc=no) | ||
| 911 | |||
| 912 | + AC_EGREP_CPP([_using_bionic], [ | ||
| 913 | + #include <stdio.h> | ||
| 914 | + #if __BIONIC__ | ||
| 915 | + _using_bionic | ||
| 916 | + #endif | ||
| 917 | + ], bionic=yes, bionic=no) | ||
| 918 | + | ||
| 919 | # Find platform-specific directories containing configuration info. | ||
| 920 | # Also possibly modify flags used elsewhere, as needed by the platform. | ||
| 921 | GLIBCXX_CHECK_HOST | ||
| 922 | @@ -2722,7 +2729,7 @@ void foo() | ||
| 923 | } | ||
| 924 | EOF | ||
| 925 | old_CXXFLAGS="$CXXFLAGS" | ||
| 926 | - CXXFLAGS=-S | ||
| 927 | + CXXFLAGS="-S -fexceptions" | ||
| 928 | if AC_TRY_EVAL(ac_compile); then | ||
| 929 | if grep _Unwind_SjLj_Resume conftest.s >/dev/null 2>&1 ; then | ||
| 930 | enable_sjlj_exceptions=yes | ||
| 931 | Index: gcc-4.5.3/libstdc++-v3/config/os/bionic/ctype_base.h | ||
| 932 | =================================================================== | ||
| 933 | --- /dev/null | ||
| 934 | +++ gcc-4.5.3/libstdc++-v3/config/os/bionic/ctype_base.h | ||
| 935 | @@ -0,0 +1,57 @@ | ||
| 936 | +// Locale support -*- C++ -*- | ||
| 937 | + | ||
| 938 | +// Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 939 | +// | ||
| 940 | +// This file is part of the GNU ISO C++ Library. This library is free | ||
| 941 | +// software; you can redistribute it and/or modify it under the | ||
| 942 | +// terms of the GNU General Public License as published by the | ||
| 943 | +// Free Software Foundation; either version 3, or (at your option) | ||
| 944 | +// any later version. | ||
| 945 | + | ||
| 946 | +// This library is distributed in the hope that it will be useful, | ||
| 947 | +// but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 948 | +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 949 | +// GNU General Public License for more details. | ||
| 950 | + | ||
| 951 | +// Under Section 7 of GPL version 3, you are granted additional | ||
| 952 | +// permissions described in the GCC Runtime Library Exception, version | ||
| 953 | +// 3.1, as published by the Free Software Foundation. | ||
| 954 | + | ||
| 955 | +// You should have received a copy of the GNU General Public License and | ||
| 956 | +// a copy of the GCC Runtime Library Exception along with this program; | ||
| 957 | +// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | ||
| 958 | +// <http://www.gnu.org/licenses/>. | ||
| 959 | + | ||
| 960 | +// | ||
| 961 | +// ISO C++ 14882: 22.1 Locales | ||
| 962 | +// | ||
| 963 | + | ||
| 964 | +// Information as gleaned from /usr/include/ctype.h, for solaris2.5.1 | ||
| 965 | + | ||
| 966 | +// Support for Solaris 2.5.1 | ||
| 967 | + | ||
| 968 | +_GLIBCXX_BEGIN_NAMESPACE(std) | ||
| 969 | + | ||
| 970 | + /// @brief Base class for ctype. | ||
| 971 | + struct ctype_base | ||
| 972 | + { | ||
| 973 | + // Non-standard typedefs. | ||
| 974 | + typedef const int* __to_type; | ||
| 975 | + | ||
| 976 | + // NB: Offsets into ctype<char>::_M_table force a particular size | ||
| 977 | + // on the mask type. Because of this, we don't use an enum. | ||
| 978 | + typedef char mask; | ||
| 979 | + static const mask upper = _U; | ||
| 980 | + static const mask lower = _L; | ||
| 981 | + static const mask alpha = _U | _L; | ||
| 982 | + static const mask digit = _N; | ||
| 983 | + static const mask xdigit = _X | _N; | ||
| 984 | + static const mask space = _S; | ||
| 985 | + static const mask print = _P | _U | _L | _N | _B; | ||
| 986 | + static const mask graph = _P | _U | _L | _N; | ||
| 987 | + static const mask cntrl = _C; | ||
| 988 | + static const mask punct = _P; | ||
| 989 | + static const mask alnum = _U | _L | _N; | ||
| 990 | + }; | ||
| 991 | + | ||
| 992 | +_GLIBCXX_END_NAMESPACE | ||
| 993 | Index: gcc-4.5.3/libstdc++-v3/config/os/bionic/ctype_inline.h | ||
| 994 | =================================================================== | ||
| 995 | --- /dev/null | ||
| 996 | +++ gcc-4.5.3/libstdc++-v3/config/os/bionic/ctype_inline.h | ||
| 997 | @@ -0,0 +1,71 @@ | ||
| 998 | +// Locale support -*- C++ -*- | ||
| 999 | + | ||
| 1000 | +// Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 1001 | +// | ||
| 1002 | +// This file is part of the GNU ISO C++ Library. This library is free | ||
| 1003 | +// software; you can redistribute it and/or modify it under the | ||
| 1004 | +// terms of the GNU General Public License as published by the | ||
| 1005 | +// Free Software Foundation; either version 3, or (at your option) | ||
| 1006 | +// any later version. | ||
| 1007 | + | ||
| 1008 | +// This library is distributed in the hope that it will be useful, | ||
| 1009 | +// but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 1010 | +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 1011 | +// GNU General Public License for more details. | ||
| 1012 | + | ||
| 1013 | +// Under Section 7 of GPL version 3, you are granted additional | ||
| 1014 | +// permissions described in the GCC Runtime Library Exception, version | ||
| 1015 | +// 3.1, as published by the Free Software Foundation. | ||
| 1016 | + | ||
| 1017 | +// You should have received a copy of the GNU General Public License and | ||
| 1018 | +// a copy of the GCC Runtime Library Exception along with this program; | ||
| 1019 | +// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | ||
| 1020 | +// <http://www.gnu.org/licenses/>. | ||
| 1021 | + | ||
| 1022 | +/** @file ctype_inline.h | ||
| 1023 | + * This is an internal header file, included by other library headers. | ||
| 1024 | + * You should not attempt to use it directly. | ||
| 1025 | + */ | ||
| 1026 | + | ||
| 1027 | +// | ||
| 1028 | +// ISO C++ 14882: 22.1 Locales | ||
| 1029 | +// | ||
| 1030 | + | ||
| 1031 | +// ctype bits to be inlined go here. Non-inlinable (ie virtual do_*) | ||
| 1032 | +// functions go in ctype.cc | ||
| 1033 | + | ||
| 1034 | +_GLIBCXX_BEGIN_NAMESPACE(std) | ||
| 1035 | + | ||
| 1036 | + bool | ||
| 1037 | + ctype<char>:: | ||
| 1038 | + is(mask __m, char __c) const | ||
| 1039 | + { return _M_table[static_cast<unsigned char>(__c)] & __m; } | ||
| 1040 | + | ||
| 1041 | + const char* | ||
| 1042 | + ctype<char>:: | ||
| 1043 | + is(const char* __low, const char* __high, mask* __vec) const | ||
| 1044 | + { | ||
| 1045 | + while (__low < __high) | ||
| 1046 | + *__vec++ = _M_table[static_cast<unsigned char>(*__low++)]; | ||
| 1047 | + return __high; | ||
| 1048 | + } | ||
| 1049 | + | ||
| 1050 | + const char* | ||
| 1051 | + ctype<char>:: | ||
| 1052 | + scan_is(mask __m, const char* __low, const char* __high) const | ||
| 1053 | + { | ||
| 1054 | + while (__low < __high && !this->is(__m, *__low)) | ||
| 1055 | + ++__low; | ||
| 1056 | + return __low; | ||
| 1057 | + } | ||
| 1058 | + | ||
| 1059 | + const char* | ||
| 1060 | + ctype<char>:: | ||
| 1061 | + scan_not(mask __m, const char* __low, const char* __high) const | ||
| 1062 | + { | ||
| 1063 | + while (__low < __high && this->is(__m, *__low) != 0) | ||
| 1064 | + ++__low; | ||
| 1065 | + return __low; | ||
| 1066 | + } | ||
| 1067 | + | ||
| 1068 | +_GLIBCXX_END_NAMESPACE | ||
| 1069 | Index: gcc-4.5.3/libstdc++-v3/config/os/bionic/ctype_noninline.h | ||
| 1070 | =================================================================== | ||
| 1071 | --- /dev/null | ||
| 1072 | +++ gcc-4.5.3/libstdc++-v3/config/os/bionic/ctype_noninline.h | ||
| 1073 | @@ -0,0 +1,98 @@ | ||
| 1074 | +// Locale support -*- C++ -*- | ||
| 1075 | + | ||
| 1076 | +// Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 1077 | +// | ||
| 1078 | +// This file is part of the GNU ISO C++ Library. This library is free | ||
| 1079 | +// software; you can redistribute it and/or modify it under the | ||
| 1080 | +// terms of the GNU General Public License as published by the | ||
| 1081 | +// Free Software Foundation; either version 3, or (at your option) | ||
| 1082 | +// any later version. | ||
| 1083 | + | ||
| 1084 | +// This library is distributed in the hope that it will be useful, | ||
| 1085 | +// but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 1086 | +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 1087 | +// GNU General Public License for more details. | ||
| 1088 | + | ||
| 1089 | +// Under Section 7 of GPL version 3, you are granted additional | ||
| 1090 | +// permissions described in the GCC Runtime Library Exception, version | ||
| 1091 | +// 3.1, as published by the Free Software Foundation. | ||
| 1092 | + | ||
| 1093 | +// You should have received a copy of the GNU General Public License and | ||
| 1094 | +// a copy of the GCC Runtime Library Exception along with this program; | ||
| 1095 | +// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | ||
| 1096 | +// <http://www.gnu.org/licenses/>. | ||
| 1097 | + | ||
| 1098 | +/** @file ctype_noninline.h | ||
| 1099 | + * This is an internal header file, included by other library headers. | ||
| 1100 | + * You should not attempt to use it directly. | ||
| 1101 | + */ | ||
| 1102 | + | ||
| 1103 | +// | ||
| 1104 | +// ISO C++ 14882: 22.1 Locales | ||
| 1105 | +// | ||
| 1106 | + | ||
| 1107 | +// Information as gleaned from /usr/include/ctype.h | ||
| 1108 | + | ||
| 1109 | + const ctype_base::mask* | ||
| 1110 | + ctype<char>::classic_table() throw() | ||
| 1111 | + { return _ctype_ + 1; } | ||
| 1112 | + | ||
| 1113 | + ctype<char>::ctype(__c_locale, const mask* __table, bool __del, | ||
| 1114 | + size_t __refs) | ||
| 1115 | + : facet(__refs), _M_del(__table != 0 && __del), | ||
| 1116 | + _M_toupper(NULL), _M_tolower(NULL), | ||
| 1117 | + _M_table(__table ? __table : classic_table()) | ||
| 1118 | + { | ||
| 1119 | + memset(_M_widen, 0, sizeof(_M_widen)); | ||
| 1120 | + _M_widen_ok = 0; | ||
| 1121 | + memset(_M_narrow, 0, sizeof(_M_narrow)); | ||
| 1122 | + _M_narrow_ok = 0; | ||
| 1123 | + } | ||
| 1124 | + | ||
| 1125 | + ctype<char>::ctype(const mask* __table, bool __del, size_t __refs) | ||
| 1126 | + : facet(__refs), _M_del(__table != 0 && __del), | ||
| 1127 | + _M_toupper(NULL), _M_tolower(NULL), | ||
| 1128 | + _M_table(__table ? __table : classic_table()) | ||
| 1129 | + { | ||
| 1130 | + memset(_M_widen, 0, sizeof(_M_widen)); | ||
| 1131 | + _M_widen_ok = 0; | ||
| 1132 | + memset(_M_narrow, 0, sizeof(_M_narrow)); | ||
| 1133 | + _M_narrow_ok = 0; | ||
| 1134 | + } | ||
| 1135 | + | ||
| 1136 | + char | ||
| 1137 | + ctype<char>::do_toupper(char __c) const | ||
| 1138 | + { | ||
| 1139 | + int __x = __c; | ||
| 1140 | + return (this->is(ctype_base::lower, __c) ? (__x - 'a' + 'A') : __x); | ||
| 1141 | + } | ||
| 1142 | + | ||
| 1143 | + const char* | ||
| 1144 | + ctype<char>::do_toupper(char* __low, const char* __high) const | ||
| 1145 | + { | ||
| 1146 | + while (__low < __high) | ||
| 1147 | + { | ||
| 1148 | + *__low = this->do_toupper(*__low); | ||
| 1149 | + ++__low; | ||
| 1150 | + } | ||
| 1151 | + return __high; | ||
| 1152 | + } | ||
| 1153 | + | ||
| 1154 | + char | ||
| 1155 | + ctype<char>::do_tolower(char __c) const | ||
| 1156 | + { | ||
| 1157 | + int __x = __c; | ||
| 1158 | + return (this->is(ctype_base::upper, __c) ? (__x - 'A' + 'a') : __x); | ||
| 1159 | + } | ||
| 1160 | + | ||
| 1161 | + const char* | ||
| 1162 | + ctype<char>::do_tolower(char* __low, const char* __high) const | ||
| 1163 | + { | ||
| 1164 | + while (__low < __high) | ||
| 1165 | + { | ||
| 1166 | + *__low = this->do_tolower(*__low); | ||
| 1167 | + ++__low; | ||
| 1168 | + } | ||
| 1169 | + return __high; | ||
| 1170 | + } | ||
| 1171 | + | ||
| 1172 | Index: gcc-4.5.3/libstdc++-v3/config/os/bionic/os_defines.h | ||
| 1173 | =================================================================== | ||
| 1174 | --- /dev/null | ||
| 1175 | +++ gcc-4.5.3/libstdc++-v3/config/os/bionic/os_defines.h | ||
| 1176 | @@ -0,0 +1,36 @@ | ||
| 1177 | +// Specific definitions for Bionic -*- C++ -*- | ||
| 1178 | + | ||
| 1179 | +// Copyright (C) 2010 Free Software Foundation, Inc. | ||
| 1180 | +// | ||
| 1181 | +// This file is part of the GNU ISO C++ Library. This library is free | ||
| 1182 | +// software; you can redistribute it and/or modify it under the | ||
| 1183 | +// terms of the GNU General Public License as published by the | ||
| 1184 | +// Free Software Foundation; either version 3, or (at your option) | ||
| 1185 | +// any later version. | ||
| 1186 | + | ||
| 1187 | +// This library is distributed in the hope that it will be useful, | ||
| 1188 | +// but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 1189 | +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 1190 | +// GNU General Public License for more details. | ||
| 1191 | + | ||
| 1192 | +// Under Section 7 of GPL version 3, you are granted additional | ||
| 1193 | +// permissions described in the GCC Runtime Library Exception, version | ||
| 1194 | +// 3.1, as published by the Free Software Foundation. | ||
| 1195 | + | ||
| 1196 | +// You should have received a copy of the GNU General Public License and | ||
| 1197 | +// a copy of the GCC Runtime Library Exception along with this program; | ||
| 1198 | +// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | ||
| 1199 | +// <http://www.gnu.org/licenses/>. | ||
| 1200 | + | ||
| 1201 | +/** @file os_defines.h | ||
| 1202 | + * This is an internal header file, included by other library headers. | ||
| 1203 | + * You should not attempt to use it directly. | ||
| 1204 | + */ | ||
| 1205 | + | ||
| 1206 | +#ifndef _GLIBCXX_OS_DEFINES | ||
| 1207 | +#define _GLIBCXX_OS_DEFINES 1 | ||
| 1208 | + | ||
| 1209 | +// System-specific #define, typedefs, corrections, etc, go here. This | ||
| 1210 | +// file will come before all others. | ||
| 1211 | + | ||
| 1212 | +#endif | ||
| 1213 | Index: gcc-4.5.3/libstdc++-v3/configure | ||
| 1214 | =================================================================== | ||
| 1215 | --- gcc-4.5.3.orig/libstdc++-v3/configure | ||
| 1216 | +++ gcc-4.5.3/libstdc++-v3/configure | ||
| 1217 | @@ -5185,7 +5185,7 @@ fi | ||
| 1218 | ## (Right now, this only matters for enable_wchar_t, but nothing prevents | ||
| 1219 | ## other macros from doing the same. This should be automated.) -pme | ||
| 1220 | |||
| 1221 | - # Check for uClibc since Linux platforms use different configuration | ||
| 1222 | + # Check for C library flavor since Linux platforms use different configuration | ||
| 1223 | # directories depending on the C library in use. | ||
| 1224 | cat confdefs.h - <<_ACEOF >conftest.$ac_ext | ||
| 1225 | /* end confdefs.h. */ | ||
| 1226 | @@ -5205,6 +5205,24 @@ fi | ||
| 1227 | rm -f conftest* | ||
| 1228 | |||
| 1229 | |||
| 1230 | + cat confdefs.h - <<_ACEOF >conftest.$ac_ext | ||
| 1231 | +/* end confdefs.h. */ | ||
| 1232 | + | ||
| 1233 | + #include <stdio.h> | ||
| 1234 | + #if __BIONIC__ | ||
| 1235 | + _using_bionic | ||
| 1236 | + #endif | ||
| 1237 | + | ||
| 1238 | +_ACEOF | ||
| 1239 | +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | | ||
| 1240 | + $EGREP "_using_bionic" >/dev/null 2>&1; then : | ||
| 1241 | + bionic=yes | ||
| 1242 | +else | ||
| 1243 | + bionic=no | ||
| 1244 | +fi | ||
| 1245 | +rm -f conftest* | ||
| 1246 | + | ||
| 1247 | + | ||
| 1248 | # Find platform-specific directories containing configuration info. | ||
| 1249 | # Also possibly modify flags used elsewhere, as needed by the platform. | ||
| 1250 | |||
| 1251 | @@ -14897,7 +14915,7 @@ void foo() | ||
| 1252 | } | ||
| 1253 | EOF | ||
| 1254 | old_CXXFLAGS="$CXXFLAGS" | ||
| 1255 | - CXXFLAGS=-S | ||
| 1256 | + CXXFLAGS="-S -fexceptions" | ||
| 1257 | if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 | ||
| 1258 | (eval $ac_compile) 2>&5 | ||
| 1259 | ac_status=$? | ||
| 1260 | Index: gcc-4.5.3/libstdc++-v3/configure.host | ||
| 1261 | =================================================================== | ||
| 1262 | --- gcc-4.5.3.orig/libstdc++-v3/configure.host | ||
| 1263 | +++ gcc-4.5.3/libstdc++-v3/configure.host | ||
| 1264 | @@ -238,6 +238,8 @@ case "${host_os}" in | ||
| 1265 | gnu* | linux* | kfreebsd*-gnu | knetbsd*-gnu) | ||
| 1266 | if [ "$uclibc" = "yes" ]; then | ||
| 1267 | os_include_dir="os/uclibc" | ||
| 1268 | + elif [ "$bionic" = "yes" ]; then | ||
| 1269 | + os_include_dir="os/bionic" | ||
| 1270 | else | ||
| 1271 | os_include_dir="os/gnu-linux" | ||
| 1272 | fi | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99495.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99495.patch deleted file mode 100644 index bb866ce8d..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99495.patch +++ /dev/null | |||
| @@ -1,784 +0,0 @@ | |||
| 1 | 2011-03-24 Revital Eres <revital.eres@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * loop-doloop.c (doloop_condition_get): Support new form of | ||
| 5 | doloop pattern and use prev_nondebug_insn instead of PREV_INSN. | ||
| 6 | * config/arm/thumb2.md (*thumb2_addsi3_compare0): Remove "*". | ||
| 7 | (doloop_end): New. | ||
| 8 | * config/arm/arm.md (*addsi3_compare0): Remove "*". | ||
| 9 | * ddg.c (check_closing_branch_deps, get_node_of_insn_uid): | ||
| 10 | New functions. | ||
| 11 | (create_ddg): Pass sbitmap containing do-loop related | ||
| 12 | instructions instead of closing_branch_deps parameter and call | ||
| 13 | check_closing_branch_deps function. | ||
| 14 | * ddg.h (create_ddg): Adjust the function declaration. | ||
| 15 | * modulo-sched.c (PS_STAGE_COUNT): Rename to CALC_STAGE_COUNT | ||
| 16 | and redefine. | ||
| 17 | (doloop_register_get): Handle NONDEBUG_INSN_P. | ||
| 18 | (stage_count): New field in struct partial_schedule. | ||
| 19 | (mark_doloop_insns, calculate_stage_count): New functions. | ||
| 20 | (normalize_sched_times): Rename to reset_sched_times and handle | ||
| 21 | incrementing the sched time of the nodes by a constant value | ||
| 22 | passed as parameter. | ||
| 23 | (duplicate_insns_of_cycles): Skip closing branch. | ||
| 24 | (sms_schedule_by_order): Schedule closing branch when | ||
| 25 | closing_branch_deps is true. | ||
| 26 | (ps_insn_find_column): Handle closing branch. | ||
| 27 | (sms_schedule): Call reset_sched_times and handle case where | ||
| 28 | do-loop pattern is not decoupled from the other loop instructions. | ||
| 29 | Support new form of doloop pattern. | ||
| 30 | (ps_insert_empty_row): Update calls to normalize_sched_times | ||
| 31 | and rotate_partial_schedule functions. | ||
| 32 | |||
| 33 | === modified file 'gcc/config/arm/arm.md' | ||
| 34 | --- old/gcc/config/arm/arm.md 2011-03-11 14:26:34 +0000 | ||
| 35 | +++ new/gcc/config/arm/arm.md 2011-03-24 07:45:38 +0000 | ||
| 36 | @@ -734,7 +734,7 @@ | ||
| 37 | "" | ||
| 38 | ) | ||
| 39 | |||
| 40 | -(define_insn "*addsi3_compare0" | ||
| 41 | +(define_insn "addsi3_compare0" | ||
| 42 | [(set (reg:CC_NOOV CC_REGNUM) | ||
| 43 | (compare:CC_NOOV | ||
| 44 | (plus:SI (match_operand:SI 1 "s_register_operand" "r, r") | ||
| 45 | |||
| 46 | === modified file 'gcc/config/arm/thumb2.md' | ||
| 47 | --- old/gcc/config/arm/thumb2.md 2011-02-08 10:51:58 +0000 | ||
| 48 | +++ new/gcc/config/arm/thumb2.md 2011-03-24 07:45:38 +0000 | ||
| 49 | @@ -1194,7 +1194,7 @@ | ||
| 50 | (set_attr "length" "2")] | ||
| 51 | ) | ||
| 52 | |||
| 53 | -(define_insn "*thumb2_addsi3_compare0" | ||
| 54 | +(define_insn "thumb2_addsi3_compare0" | ||
| 55 | [(set (reg:CC_NOOV CC_REGNUM) | ||
| 56 | (compare:CC_NOOV | ||
| 57 | (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r") | ||
| 58 | @@ -1445,3 +1445,56 @@ | ||
| 59 | [(set_attr "length" "4,4,16") | ||
| 60 | (set_attr "predicable" "yes")] | ||
| 61 | ) | ||
| 62 | + | ||
| 63 | + | ||
| 64 | +;; Define the subtract-one-and-jump insns so loop.c | ||
| 65 | +;; knows what to generate. | ||
| 66 | +(define_expand "doloop_end" | ||
| 67 | + [(use (match_operand 0 "" "")) ; loop pseudo | ||
| 68 | + (use (match_operand 1 "" "")) ; iterations; zero if unknown | ||
| 69 | + (use (match_operand 2 "" "")) ; max iterations | ||
| 70 | + (use (match_operand 3 "" "")) ; loop level | ||
| 71 | + (use (match_operand 4 "" ""))] ; label | ||
| 72 | + "TARGET_32BIT" | ||
| 73 | + " | ||
| 74 | + { | ||
| 75 | + /* Currently SMS relies on the do-loop pattern to recognize loops | ||
| 76 | + where (1) the control part consists of all insns defining and/or | ||
| 77 | + using a certain 'count' register and (2) the loop count can be | ||
| 78 | + adjusted by modifying this register prior to the loop. | ||
| 79 | + ??? The possible introduction of a new block to initialize the | ||
| 80 | + new IV can potentially affect branch optimizations. */ | ||
| 81 | + if (optimize > 0 && flag_modulo_sched) | ||
| 82 | + { | ||
| 83 | + rtx s0; | ||
| 84 | + rtx bcomp; | ||
| 85 | + rtx loc_ref; | ||
| 86 | + rtx cc_reg; | ||
| 87 | + rtx insn; | ||
| 88 | + rtx cmp; | ||
| 89 | + | ||
| 90 | + /* Only use this on innermost loops. */ | ||
| 91 | + if (INTVAL (operands[3]) > 1) | ||
| 92 | + FAIL; | ||
| 93 | + | ||
| 94 | + if (GET_MODE (operands[0]) != SImode) | ||
| 95 | + FAIL; | ||
| 96 | + | ||
| 97 | + s0 = operands [0]; | ||
| 98 | + if (TARGET_THUMB2) | ||
| 99 | + insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1))); | ||
| 100 | + else | ||
| 101 | + insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1))); | ||
| 102 | + | ||
| 103 | + cmp = XVECEXP (PATTERN (insn), 0, 0); | ||
| 104 | + cc_reg = SET_DEST (cmp); | ||
| 105 | + bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx); | ||
| 106 | + loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]); | ||
| 107 | + emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | ||
| 108 | + gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp, | ||
| 109 | + loc_ref, pc_rtx))); | ||
| 110 | + DONE; | ||
| 111 | + }else | ||
| 112 | + FAIL; | ||
| 113 | + }") | ||
| 114 | + | ||
| 115 | |||
| 116 | === modified file 'gcc/ddg.c' | ||
| 117 | --- old/gcc/ddg.c 2010-07-19 08:58:53 +0000 | ||
| 118 | +++ new/gcc/ddg.c 2011-03-24 07:45:38 +0000 | ||
| 119 | @@ -60,6 +60,8 @@ | ||
| 120 | static ddg_edge_ptr create_ddg_edge (ddg_node_ptr, ddg_node_ptr, dep_type, | ||
| 121 | dep_data_type, int, int); | ||
| 122 | static void add_edge_to_ddg (ddg_ptr g, ddg_edge_ptr); | ||
| 123 | +static ddg_node_ptr get_node_of_insn_uid (ddg_ptr, int); | ||
| 124 | + | ||
| 125 | |||
| 126 | /* Auxiliary variable for mem_read_insn_p/mem_write_insn_p. */ | ||
| 127 | static bool mem_ref_p; | ||
| 128 | @@ -450,12 +452,65 @@ | ||
| 129 | sched_free_deps (head, tail, false); | ||
| 130 | } | ||
| 131 | |||
| 132 | +/* Given DOLOOP_INSNS which holds the instructions that | ||
| 133 | + belong to the do-loop part; mark closing_branch_deps field in ddg G | ||
| 134 | + as TRUE if the do-loop part's instructions are dependent on the other | ||
| 135 | + loop instructions. Otherwise mark it as FALSE. */ | ||
| 136 | +static void | ||
| 137 | +check_closing_branch_deps (ddg_ptr g, sbitmap doloop_insns) | ||
| 138 | +{ | ||
| 139 | + sbitmap_iterator sbi; | ||
| 140 | + unsigned int u = 0; | ||
| 141 | + | ||
| 142 | + EXECUTE_IF_SET_IN_SBITMAP (doloop_insns, 0, u, sbi) | ||
| 143 | + { | ||
| 144 | + ddg_edge_ptr e; | ||
| 145 | + ddg_node_ptr u_node = get_node_of_insn_uid (g, u); | ||
| 146 | + | ||
| 147 | + gcc_assert (u_node); | ||
| 148 | + | ||
| 149 | + for (e = u_node->in; e != 0; e = e->next_in) | ||
| 150 | + { | ||
| 151 | + ddg_node_ptr v_node = e->src; | ||
| 152 | + | ||
| 153 | + if (((unsigned int) INSN_UID (v_node->insn) == u) | ||
| 154 | + || DEBUG_INSN_P (v_node->insn)) | ||
| 155 | + continue; | ||
| 156 | + | ||
| 157 | + /* Ignore dependencies between memory writes and the | ||
| 158 | + jump. */ | ||
| 159 | + if (JUMP_P (u_node->insn) | ||
| 160 | + && e->type == OUTPUT_DEP | ||
| 161 | + && mem_write_insn_p (v_node->insn)) | ||
| 162 | + continue; | ||
| 163 | + if (!TEST_BIT (doloop_insns, INSN_UID (v_node->insn))) | ||
| 164 | + { | ||
| 165 | + g->closing_branch_deps = 1; | ||
| 166 | + return; | ||
| 167 | + } | ||
| 168 | + } | ||
| 169 | + for (e = u_node->out; e != 0; e = e->next_out) | ||
| 170 | + { | ||
| 171 | + ddg_node_ptr v_node = e->dest; | ||
| 172 | + | ||
| 173 | + if (((unsigned int) INSN_UID (v_node->insn) == u) | ||
| 174 | + || DEBUG_INSN_P (v_node->insn)) | ||
| 175 | + continue; | ||
| 176 | + if (!TEST_BIT (doloop_insns, INSN_UID (v_node->insn))) | ||
| 177 | + { | ||
| 178 | + g->closing_branch_deps = 1; | ||
| 179 | + return; | ||
| 180 | + } | ||
| 181 | + } | ||
| 182 | + } | ||
| 183 | + g->closing_branch_deps = 0; | ||
| 184 | +} | ||
| 185 | |||
| 186 | /* Given a basic block, create its DDG and return a pointer to a variable | ||
| 187 | of ddg type that represents it. | ||
| 188 | Initialize the ddg structure fields to the appropriate values. */ | ||
| 189 | ddg_ptr | ||
| 190 | -create_ddg (basic_block bb, int closing_branch_deps) | ||
| 191 | +create_ddg (basic_block bb, sbitmap doloop_insns) | ||
| 192 | { | ||
| 193 | ddg_ptr g; | ||
| 194 | rtx insn, first_note; | ||
| 195 | @@ -465,7 +520,6 @@ | ||
| 196 | g = (ddg_ptr) xcalloc (1, sizeof (struct ddg)); | ||
| 197 | |||
| 198 | g->bb = bb; | ||
| 199 | - g->closing_branch_deps = closing_branch_deps; | ||
| 200 | |||
| 201 | /* Count the number of insns in the BB. */ | ||
| 202 | for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); | ||
| 203 | @@ -538,6 +592,11 @@ | ||
| 204 | /* Build the data dependency graph. */ | ||
| 205 | build_intra_loop_deps (g); | ||
| 206 | build_inter_loop_deps (g); | ||
| 207 | + | ||
| 208 | + /* Check whether the do-loop part is decoupled from the other loop | ||
| 209 | + instructions. */ | ||
| 210 | + check_closing_branch_deps (g, doloop_insns); | ||
| 211 | + | ||
| 212 | return g; | ||
| 213 | } | ||
| 214 | |||
| 215 | @@ -831,6 +890,18 @@ | ||
| 216 | return NULL; | ||
| 217 | } | ||
| 218 | |||
| 219 | +/* Given the uid of an instruction UID return the node that represents it. */ | ||
| 220 | +static ddg_node_ptr | ||
| 221 | +get_node_of_insn_uid (ddg_ptr g, int uid) | ||
| 222 | +{ | ||
| 223 | + int i; | ||
| 224 | + | ||
| 225 | + for (i = 0; i < g->num_nodes; i++) | ||
| 226 | + if (uid == INSN_UID (g->nodes[i].insn)) | ||
| 227 | + return &g->nodes[i]; | ||
| 228 | + return NULL; | ||
| 229 | +} | ||
| 230 | + | ||
| 231 | /* Given a set OPS of nodes in the DDG, find the set of their successors | ||
| 232 | which are not in OPS, and set their bits in SUCC. Bits corresponding to | ||
| 233 | OPS are cleared from SUCC. Leaves the other bits in SUCC unchanged. */ | ||
| 234 | |||
| 235 | === modified file 'gcc/ddg.h' | ||
| 236 | --- old/gcc/ddg.h 2009-11-25 10:55:54 +0000 | ||
| 237 | +++ new/gcc/ddg.h 2011-03-24 07:45:38 +0000 | ||
| 238 | @@ -167,7 +167,7 @@ | ||
| 239 | }; | ||
| 240 | |||
| 241 | |||
| 242 | -ddg_ptr create_ddg (basic_block, int closing_branch_deps); | ||
| 243 | +ddg_ptr create_ddg (basic_block, sbitmap); | ||
| 244 | void free_ddg (ddg_ptr); | ||
| 245 | |||
| 246 | void print_ddg (FILE *, ddg_ptr); | ||
| 247 | |||
| 248 | === modified file 'gcc/loop-doloop.c' | ||
| 249 | --- old/gcc/loop-doloop.c 2010-07-19 08:58:53 +0000 | ||
| 250 | +++ new/gcc/loop-doloop.c 2011-03-24 07:45:38 +0000 | ||
| 251 | @@ -78,6 +78,8 @@ | ||
| 252 | rtx inc_src; | ||
| 253 | rtx condition; | ||
| 254 | rtx pattern; | ||
| 255 | + rtx cc_reg = NULL_RTX; | ||
| 256 | + rtx reg_orig = NULL_RTX; | ||
| 257 | |||
| 258 | /* The canonical doloop pattern we expect has one of the following | ||
| 259 | forms: | ||
| 260 | @@ -96,7 +98,16 @@ | ||
| 261 | 2) (set (reg) (plus (reg) (const_int -1)) | ||
| 262 | (set (pc) (if_then_else (reg != 0) | ||
| 263 | (label_ref (label)) | ||
| 264 | - (pc))). */ | ||
| 265 | + (pc))). | ||
| 266 | + | ||
| 267 | + Some targets (ARM) do the comparison before the branch, as in the | ||
| 268 | + following form: | ||
| 269 | + | ||
| 270 | + 3) (parallel [(set (cc) (compare ((plus (reg) (const_int -1), 0))) | ||
| 271 | + (set (reg) (plus (reg) (const_int -1)))]) | ||
| 272 | + (set (pc) (if_then_else (cc == NE) | ||
| 273 | + (label_ref (label)) | ||
| 274 | + (pc))) */ | ||
| 275 | |||
| 276 | pattern = PATTERN (doloop_pat); | ||
| 277 | |||
| 278 | @@ -104,19 +115,47 @@ | ||
| 279 | { | ||
| 280 | rtx cond; | ||
| 281 | rtx prev_insn = prev_nondebug_insn (doloop_pat); | ||
| 282 | + rtx cmp_arg1, cmp_arg2; | ||
| 283 | + rtx cmp_orig; | ||
| 284 | |||
| 285 | - /* We expect the decrement to immediately precede the branch. */ | ||
| 286 | + /* In case the pattern is not PARALLEL we expect two forms | ||
| 287 | + of doloop which are cases 2) and 3) above: in case 2) the | ||
| 288 | + decrement immediately precedes the branch, while in case 3) | ||
| 289 | + the compare and decrement instructions immediately precede | ||
| 290 | + the branch. */ | ||
| 291 | |||
| 292 | if (prev_insn == NULL_RTX || !INSN_P (prev_insn)) | ||
| 293 | return 0; | ||
| 294 | |||
| 295 | cmp = pattern; | ||
| 296 | - inc = PATTERN (PREV_INSN (doloop_pat)); | ||
| 297 | + if (GET_CODE (PATTERN (prev_insn)) == PARALLEL) | ||
| 298 | + { | ||
| 299 | + /* The third case: the compare and decrement instructions | ||
| 300 | + immediately precede the branch. */ | ||
| 301 | + cmp_orig = XVECEXP (PATTERN (prev_insn), 0, 0); | ||
| 302 | + if (GET_CODE (cmp_orig) != SET) | ||
| 303 | + return 0; | ||
| 304 | + if (GET_CODE (SET_SRC (cmp_orig)) != COMPARE) | ||
| 305 | + return 0; | ||
| 306 | + cmp_arg1 = XEXP (SET_SRC (cmp_orig), 0); | ||
| 307 | + cmp_arg2 = XEXP (SET_SRC (cmp_orig), 1); | ||
| 308 | + if (cmp_arg2 != const0_rtx | ||
| 309 | + || GET_CODE (cmp_arg1) != PLUS) | ||
| 310 | + return 0; | ||
| 311 | + reg_orig = XEXP (cmp_arg1, 0); | ||
| 312 | + if (XEXP (cmp_arg1, 1) != GEN_INT (-1) | ||
| 313 | + || !REG_P (reg_orig)) | ||
| 314 | + return 0; | ||
| 315 | + cc_reg = SET_DEST (cmp_orig); | ||
| 316 | + | ||
| 317 | + inc = XVECEXP (PATTERN (prev_insn), 0, 1); | ||
| 318 | + } | ||
| 319 | + else | ||
| 320 | + inc = PATTERN (prev_insn); | ||
| 321 | /* We expect the condition to be of the form (reg != 0) */ | ||
| 322 | cond = XEXP (SET_SRC (cmp), 0); | ||
| 323 | if (GET_CODE (cond) != NE || XEXP (cond, 1) != const0_rtx) | ||
| 324 | return 0; | ||
| 325 | - | ||
| 326 | } | ||
| 327 | else | ||
| 328 | { | ||
| 329 | @@ -162,11 +201,15 @@ | ||
| 330 | return 0; | ||
| 331 | |||
| 332 | if ((XEXP (condition, 0) == reg) | ||
| 333 | + /* For the third case: */ | ||
| 334 | + || ((cc_reg != NULL_RTX) | ||
| 335 | + && (XEXP (condition, 0) == cc_reg) | ||
| 336 | + && (reg_orig == reg)) | ||
| 337 | || (GET_CODE (XEXP (condition, 0)) == PLUS | ||
| 338 | - && XEXP (XEXP (condition, 0), 0) == reg)) | ||
| 339 | + && XEXP (XEXP (condition, 0), 0) == reg)) | ||
| 340 | { | ||
| 341 | if (GET_CODE (pattern) != PARALLEL) | ||
| 342 | - /* The second form we expect: | ||
| 343 | + /* For the second form we expect: | ||
| 344 | |||
| 345 | (set (reg) (plus (reg) (const_int -1)) | ||
| 346 | (set (pc) (if_then_else (reg != 0) | ||
| 347 | @@ -181,7 +224,24 @@ | ||
| 348 | (set (reg) (plus (reg) (const_int -1))) | ||
| 349 | (additional clobbers and uses)]) | ||
| 350 | |||
| 351 | - So we return that form instead. | ||
| 352 | + For the third form we expect: | ||
| 353 | + | ||
| 354 | + (parallel [(set (cc) (compare ((plus (reg) (const_int -1)), 0)) | ||
| 355 | + (set (reg) (plus (reg) (const_int -1)))]) | ||
| 356 | + (set (pc) (if_then_else (cc == NE) | ||
| 357 | + (label_ref (label)) | ||
| 358 | + (pc))) | ||
| 359 | + | ||
| 360 | + which is equivalent to the following: | ||
| 361 | + | ||
| 362 | + (parallel [(set (cc) (compare (reg, 1)) | ||
| 363 | + (set (reg) (plus (reg) (const_int -1))) | ||
| 364 | + (set (pc) (if_then_else (NE == cc) | ||
| 365 | + (label_ref (label)) | ||
| 366 | + (pc))))]) | ||
| 367 | + | ||
| 368 | + So we return the second form instead for the two cases. | ||
| 369 | + | ||
| 370 | */ | ||
| 371 | condition = gen_rtx_fmt_ee (NE, VOIDmode, inc_src, const1_rtx); | ||
| 372 | |||
| 373 | |||
| 374 | === modified file 'gcc/modulo-sched.c' | ||
| 375 | --- old/gcc/modulo-sched.c 2009-11-25 10:55:54 +0000 | ||
| 376 | +++ new/gcc/modulo-sched.c 2011-03-24 07:45:38 +0000 | ||
| 377 | @@ -116,8 +116,10 @@ | ||
| 378 | |||
| 379 | /* The number of different iterations the nodes in ps span, assuming | ||
| 380 | the stage boundaries are placed efficiently. */ | ||
| 381 | -#define PS_STAGE_COUNT(ps) ((PS_MAX_CYCLE (ps) - PS_MIN_CYCLE (ps) \ | ||
| 382 | - + 1 + (ps)->ii - 1) / (ps)->ii) | ||
| 383 | +#define CALC_STAGE_COUNT(min_cycle,max_cycle,ii) ((max_cycle - min_cycle \ | ||
| 384 | + + 1 + ii - 1) / ii) | ||
| 385 | +/* The stage count of ps. */ | ||
| 386 | +#define PS_STAGE_COUNT(ps) (((partial_schedule_ptr)(ps))->stage_count) | ||
| 387 | |||
| 388 | /* A single instruction in the partial schedule. */ | ||
| 389 | struct ps_insn | ||
| 390 | @@ -155,6 +157,8 @@ | ||
| 391 | int max_cycle; | ||
| 392 | |||
| 393 | ddg_ptr g; /* The DDG of the insns in the partial schedule. */ | ||
| 394 | + | ||
| 395 | + int stage_count; /* The stage count of the partial schedule. */ | ||
| 396 | }; | ||
| 397 | |||
| 398 | /* We use this to record all the register replacements we do in | ||
| 399 | @@ -195,6 +199,7 @@ | ||
| 400 | rtx, rtx); | ||
| 401 | static void duplicate_insns_of_cycles (partial_schedule_ptr, | ||
| 402 | int, int, int, rtx); | ||
| 403 | +static int calculate_stage_count (partial_schedule_ptr ps); | ||
| 404 | |||
| 405 | #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap) | ||
| 406 | #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time) | ||
| 407 | @@ -310,10 +315,10 @@ | ||
| 408 | either a single (parallel) branch-on-count or a (non-parallel) | ||
| 409 | branch immediately preceded by a single (decrement) insn. */ | ||
| 410 | first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail | ||
| 411 | - : PREV_INSN (tail)); | ||
| 412 | + : prev_nondebug_insn (tail)); | ||
| 413 | |||
| 414 | for (insn = head; insn != first_insn_not_to_check; insn = NEXT_INSN (insn)) | ||
| 415 | - if (reg_mentioned_p (reg, insn)) | ||
| 416 | + if (reg_mentioned_p (reg, insn) && NONDEBUG_INSN_P (insn)) | ||
| 417 | { | ||
| 418 | if (dump_file) | ||
| 419 | { | ||
| 420 | @@ -332,6 +337,24 @@ | ||
| 421 | #endif | ||
| 422 | } | ||
| 423 | |||
| 424 | +/* Mark in DOLOOP_INSNS the instructions that belong to the do-loop part. | ||
| 425 | + Use TAIL to recognize that part. */ | ||
| 426 | +static void | ||
| 427 | +mark_doloop_insns (sbitmap doloop_insns, rtx tail) | ||
| 428 | +{ | ||
| 429 | + rtx first_insn_not_to_check, insn; | ||
| 430 | + | ||
| 431 | + /* This is the first instruction which belongs the doloop part. */ | ||
| 432 | + first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail | ||
| 433 | + : prev_nondebug_insn (tail)); | ||
| 434 | + | ||
| 435 | + sbitmap_zero (doloop_insns); | ||
| 436 | + for (insn = first_insn_not_to_check; insn != NEXT_INSN (tail); | ||
| 437 | + insn = NEXT_INSN (insn)) | ||
| 438 | + if (NONDEBUG_INSN_P (insn)) | ||
| 439 | + SET_BIT (doloop_insns, INSN_UID (insn)); | ||
| 440 | +} | ||
| 441 | + | ||
| 442 | /* Check if COUNT_REG is set to a constant in the PRE_HEADER block, so | ||
| 443 | that the number of iterations is a compile-time constant. If so, | ||
| 444 | return the rtx that sets COUNT_REG to a constant, and set COUNT to | ||
| 445 | @@ -569,13 +592,12 @@ | ||
| 446 | } | ||
| 447 | } | ||
| 448 | |||
| 449 | -/* Bump the SCHED_TIMEs of all nodes to start from zero. Set the values | ||
| 450 | - of SCHED_ROW and SCHED_STAGE. */ | ||
| 451 | +/* Bump the SCHED_TIMEs of all nodes by AMOUNT. Set the values of | ||
| 452 | + SCHED_ROW and SCHED_STAGE. */ | ||
| 453 | static void | ||
| 454 | -normalize_sched_times (partial_schedule_ptr ps) | ||
| 455 | +reset_sched_times (partial_schedule_ptr ps, int amount) | ||
| 456 | { | ||
| 457 | int row; | ||
| 458 | - int amount = PS_MIN_CYCLE (ps); | ||
| 459 | int ii = ps->ii; | ||
| 460 | ps_insn_ptr crr_insn; | ||
| 461 | |||
| 462 | @@ -584,6 +606,10 @@ | ||
| 463 | { | ||
| 464 | ddg_node_ptr u = crr_insn->node; | ||
| 465 | int normalized_time = SCHED_TIME (u) - amount; | ||
| 466 | + int new_min_cycle = PS_MIN_CYCLE (ps) - amount; | ||
| 467 | + /* The first cycle in row zero after the rotation. */ | ||
| 468 | + int new_first_cycle_in_row_zero = | ||
| 469 | + new_min_cycle + ii - SMODULO (new_min_cycle, ii); | ||
| 470 | |||
| 471 | if (dump_file) | ||
| 472 | fprintf (dump_file, "crr_insn->node=%d, crr_insn->cycle=%d,\ | ||
| 473 | @@ -592,8 +618,30 @@ | ||
| 474 | gcc_assert (SCHED_TIME (u) >= ps->min_cycle); | ||
| 475 | gcc_assert (SCHED_TIME (u) <= ps->max_cycle); | ||
| 476 | SCHED_TIME (u) = normalized_time; | ||
| 477 | - SCHED_ROW (u) = normalized_time % ii; | ||
| 478 | - SCHED_STAGE (u) = normalized_time / ii; | ||
| 479 | + crr_insn->cycle = normalized_time; | ||
| 480 | + SCHED_ROW (u) = SMODULO (normalized_time, ii); | ||
| 481 | + | ||
| 482 | + /* If min_cycle is in row zero after the rotation then | ||
| 483 | + the stage count can be calculated by dividing the cycle | ||
| 484 | + with ii. Otherwise, the calculation is done by dividing the | ||
| 485 | + SMSed kernel into two intervals: | ||
| 486 | + | ||
| 487 | + 1) min_cycle <= interval 0 < first_cycle_in_row_zero | ||
| 488 | + 2) first_cycle_in_row_zero <= interval 1 < max_cycle | ||
| 489 | + | ||
| 490 | + Cycles in interval 0 are in stage 0. The stage of cycles | ||
| 491 | + in interval 1 should be added by 1 to take interval 0 into | ||
| 492 | + account. */ | ||
| 493 | + if (SMODULO (new_min_cycle, ii) == 0) | ||
| 494 | + SCHED_STAGE (u) = normalized_time / ii; | ||
| 495 | + else | ||
| 496 | + { | ||
| 497 | + if (crr_insn->cycle < new_first_cycle_in_row_zero) | ||
| 498 | + SCHED_STAGE (u) = 0; | ||
| 499 | + else | ||
| 500 | + SCHED_STAGE (u) = | ||
| 501 | + ((SCHED_TIME (u) - new_first_cycle_in_row_zero) / ii) + 1; | ||
| 502 | + } | ||
| 503 | } | ||
| 504 | } | ||
| 505 | |||
| 506 | @@ -646,9 +694,12 @@ | ||
| 507 | |||
| 508 | /* Do not duplicate any insn which refers to count_reg as it | ||
| 509 | belongs to the control part. | ||
| 510 | + If closing_branch_deps is true the closing branch is scheduled | ||
| 511 | + as well and thus should be ignored. | ||
| 512 | TODO: This should be done by analyzing the control part of | ||
| 513 | the loop. */ | ||
| 514 | - if (reg_mentioned_p (count_reg, u_node->insn)) | ||
| 515 | + if (reg_mentioned_p (count_reg, u_node->insn) | ||
| 516 | + || JUMP_P (ps_ij->node->insn)) | ||
| 517 | continue; | ||
| 518 | |||
| 519 | if (for_prolog) | ||
| 520 | @@ -894,7 +945,8 @@ | ||
| 521 | basic_block condition_bb = NULL; | ||
| 522 | edge latch_edge; | ||
| 523 | gcov_type trip_count = 0; | ||
| 524 | - | ||
| 525 | + sbitmap doloop_insns; | ||
| 526 | + | ||
| 527 | loop_optimizer_init (LOOPS_HAVE_PREHEADERS | ||
| 528 | | LOOPS_HAVE_RECORDED_EXITS); | ||
| 529 | if (number_of_loops () <= 1) | ||
| 530 | @@ -919,6 +971,7 @@ | ||
| 531 | setup_sched_infos (); | ||
| 532 | haifa_sched_init (); | ||
| 533 | |||
| 534 | + doloop_insns = sbitmap_alloc (get_max_uid () + 1); | ||
| 535 | /* Allocate memory to hold the DDG array one entry for each loop. | ||
| 536 | We use loop->num as index into this array. */ | ||
| 537 | g_arr = XCNEWVEC (ddg_ptr, number_of_loops ()); | ||
| 538 | @@ -1009,9 +1062,11 @@ | ||
| 539 | continue; | ||
| 540 | } | ||
| 541 | |||
| 542 | - /* Don't handle BBs with calls or barriers, or !single_set insns, | ||
| 543 | - or auto-increment insns (to avoid creating invalid reg-moves | ||
| 544 | - for the auto-increment insns). | ||
| 545 | + /* Don't handle BBs with calls or barriers or auto-increment insns | ||
| 546 | + (to avoid creating invalid reg-moves for the auto-increment insns), | ||
| 547 | + or !single_set with the exception of instructions that include | ||
| 548 | + count_reg---these instructions are part of the control part | ||
| 549 | + that do-loop recognizes. | ||
| 550 | ??? Should handle auto-increment insns. | ||
| 551 | ??? Should handle insns defining subregs. */ | ||
| 552 | for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn)) | ||
| 553 | @@ -1021,7 +1076,8 @@ | ||
| 554 | if (CALL_P (insn) | ||
| 555 | || BARRIER_P (insn) | ||
| 556 | || (NONDEBUG_INSN_P (insn) && !JUMP_P (insn) | ||
| 557 | - && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE) | ||
| 558 | + && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE | ||
| 559 | + && !reg_mentioned_p (count_reg, insn)) | ||
| 560 | || (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0) | ||
| 561 | || (INSN_P (insn) && (set = single_set (insn)) | ||
| 562 | && GET_CODE (SET_DEST (set)) == SUBREG)) | ||
| 563 | @@ -1048,14 +1104,16 @@ | ||
| 564 | |||
| 565 | continue; | ||
| 566 | } | ||
| 567 | - | ||
| 568 | - if (! (g = create_ddg (bb, 0))) | ||
| 569 | + mark_doloop_insns (doloop_insns, tail); | ||
| 570 | + if (! (g = create_ddg (bb, doloop_insns))) | ||
| 571 | { | ||
| 572 | if (dump_file) | ||
| 573 | fprintf (dump_file, "SMS create_ddg failed\n"); | ||
| 574 | continue; | ||
| 575 | } | ||
| 576 | - | ||
| 577 | + if (dump_file) | ||
| 578 | + fprintf (dump_file, "SMS closing_branch_deps: %d\n", | ||
| 579 | + g->closing_branch_deps); | ||
| 580 | g_arr[loop->num] = g; | ||
| 581 | if (dump_file) | ||
| 582 | fprintf (dump_file, "...OK\n"); | ||
| 583 | @@ -1157,11 +1215,13 @@ | ||
| 584 | |||
| 585 | ps = sms_schedule_by_order (g, mii, maxii, node_order); | ||
| 586 | |||
| 587 | - if (ps){ | ||
| 588 | - stage_count = PS_STAGE_COUNT (ps); | ||
| 589 | - gcc_assert(stage_count >= 1); | ||
| 590 | - } | ||
| 591 | - | ||
| 592 | + if (ps) | ||
| 593 | + { | ||
| 594 | + stage_count = calculate_stage_count (ps); | ||
| 595 | + gcc_assert(stage_count >= 1); | ||
| 596 | + PS_STAGE_COUNT(ps) = stage_count; | ||
| 597 | + } | ||
| 598 | + | ||
| 599 | /* Stage count of 1 means that there is no interleaving between | ||
| 600 | iterations, let the scheduling passes do the job. */ | ||
| 601 | if (stage_count <= 1 | ||
| 602 | @@ -1182,17 +1242,7 @@ | ||
| 603 | else | ||
| 604 | { | ||
| 605 | struct undo_replace_buff_elem *reg_move_replaces; | ||
| 606 | - | ||
| 607 | - if (dump_file) | ||
| 608 | - { | ||
| 609 | - fprintf (dump_file, | ||
| 610 | - "SMS succeeded %d %d (with ii, sc)\n", ps->ii, | ||
| 611 | - stage_count); | ||
| 612 | - print_partial_schedule (ps, dump_file); | ||
| 613 | - fprintf (dump_file, | ||
| 614 | - "SMS Branch (%d) will later be scheduled at cycle %d.\n", | ||
| 615 | - g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1); | ||
| 616 | - } | ||
| 617 | + int amount; | ||
| 618 | |||
| 619 | /* Set the stage boundaries. If the DDG is built with closing_branch_deps, | ||
| 620 | the closing_branch was scheduled and should appear in the last (ii-1) | ||
| 621 | @@ -1202,12 +1252,28 @@ | ||
| 622 | TODO: Revisit the issue of scheduling the insns of the | ||
| 623 | control part relative to the branch when the control part | ||
| 624 | has more than one insn. */ | ||
| 625 | - normalize_sched_times (ps); | ||
| 626 | - rotate_partial_schedule (ps, PS_MIN_CYCLE (ps)); | ||
| 627 | + amount = (g->closing_branch_deps)? SCHED_TIME (g->closing_branch) + 1: | ||
| 628 | + PS_MIN_CYCLE (ps); | ||
| 629 | + reset_sched_times (ps, amount); | ||
| 630 | + rotate_partial_schedule (ps, amount); | ||
| 631 | + | ||
| 632 | set_columns_for_ps (ps); | ||
| 633 | |||
| 634 | canon_loop (loop); | ||
| 635 | |||
| 636 | + if (dump_file) | ||
| 637 | + { | ||
| 638 | + fprintf (dump_file, | ||
| 639 | + "SMS succeeded %d %d (with ii, sc)\n", ps->ii, | ||
| 640 | + stage_count); | ||
| 641 | + print_partial_schedule (ps, dump_file); | ||
| 642 | + if (!g->closing_branch_deps) | ||
| 643 | + fprintf (dump_file, | ||
| 644 | + "SMS Branch (%d) will later be scheduled at \ | ||
| 645 | + cycle %d.\n", | ||
| 646 | + g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1); | ||
| 647 | + } | ||
| 648 | + | ||
| 649 | /* case the BCT count is not known , Do loop-versioning */ | ||
| 650 | if (count_reg && ! count_init) | ||
| 651 | { | ||
| 652 | @@ -1252,6 +1318,7 @@ | ||
| 653 | } | ||
| 654 | |||
| 655 | free (g_arr); | ||
| 656 | + sbitmap_free (doloop_insns); | ||
| 657 | |||
| 658 | /* Release scheduler data, needed until now because of DFA. */ | ||
| 659 | haifa_sched_finish (); | ||
| 660 | @@ -1759,8 +1826,9 @@ | ||
| 661 | RESET_BIT (tobe_scheduled, u); | ||
| 662 | continue; | ||
| 663 | } | ||
| 664 | - | ||
| 665 | - if (JUMP_P (insn)) /* Closing branch handled later. */ | ||
| 666 | + /* Closing branch handled later unless closing_branch_deps | ||
| 667 | + is true. */ | ||
| 668 | + if (JUMP_P (insn) && !g->closing_branch_deps) | ||
| 669 | { | ||
| 670 | RESET_BIT (tobe_scheduled, u); | ||
| 671 | continue; | ||
| 672 | @@ -1893,8 +1961,8 @@ | ||
| 673 | if (dump_file) | ||
| 674 | fprintf (dump_file, "split_row=%d\n", split_row); | ||
| 675 | |||
| 676 | - normalize_sched_times (ps); | ||
| 677 | - rotate_partial_schedule (ps, ps->min_cycle); | ||
| 678 | + reset_sched_times (ps, PS_MIN_CYCLE (ps)); | ||
| 679 | + rotate_partial_schedule (ps, PS_MIN_CYCLE (ps)); | ||
| 680 | |||
| 681 | rows_new = (ps_insn_ptr *) xcalloc (new_ii, sizeof (ps_insn_ptr)); | ||
| 682 | for (row = 0; row < split_row; row++) | ||
| 683 | @@ -2571,6 +2639,7 @@ | ||
| 684 | ps_insn_ptr next_ps_i; | ||
| 685 | ps_insn_ptr first_must_follow = NULL; | ||
| 686 | ps_insn_ptr last_must_precede = NULL; | ||
| 687 | + ps_insn_ptr last_in_row = NULL; | ||
| 688 | int row; | ||
| 689 | |||
| 690 | if (! ps_i) | ||
| 691 | @@ -2597,8 +2666,37 @@ | ||
| 692 | else | ||
| 693 | last_must_precede = next_ps_i; | ||
| 694 | } | ||
| 695 | + /* The closing branch must be the last in the row. */ | ||
| 696 | + if (must_precede | ||
| 697 | + && TEST_BIT (must_precede, next_ps_i->node->cuid) | ||
| 698 | + && JUMP_P (next_ps_i->node->insn)) | ||
| 699 | + return false; | ||
| 700 | + | ||
| 701 | + last_in_row = next_ps_i; | ||
| 702 | } | ||
| 703 | |||
| 704 | + /* If closing_branch_deps is true we are scheduling the closing | ||
| 705 | + branch as well. Make sure there is no dependent instruction after | ||
| 706 | + it as the branch should be the last instruction. */ | ||
| 707 | + if (JUMP_P (ps_i->node->insn)) | ||
| 708 | + { | ||
| 709 | + if (first_must_follow) | ||
| 710 | + return false; | ||
| 711 | + if (last_in_row) | ||
| 712 | + { | ||
| 713 | + /* Make the branch the last in the row. New instructions | ||
| 714 | + will be inserted at the beginning of the row or after the | ||
| 715 | + last must_precede instruction thus the branch is guaranteed | ||
| 716 | + to remain the last instruction in the row. */ | ||
| 717 | + last_in_row->next_in_row = ps_i; | ||
| 718 | + ps_i->prev_in_row = last_in_row; | ||
| 719 | + ps_i->next_in_row = NULL; | ||
| 720 | + } | ||
| 721 | + else | ||
| 722 | + ps->rows[row] = ps_i; | ||
| 723 | + return true; | ||
| 724 | + } | ||
| 725 | + | ||
| 726 | /* Now insert the node after INSERT_AFTER_PSI. */ | ||
| 727 | |||
| 728 | if (! last_must_precede) | ||
| 729 | @@ -2820,6 +2918,54 @@ | ||
| 730 | return ps_i; | ||
| 731 | } | ||
| 732 | |||
| 733 | +/* Calculate the stage count of the partial schedule PS. */ | ||
| 734 | +int | ||
| 735 | +calculate_stage_count (partial_schedule_ptr ps) | ||
| 736 | +{ | ||
| 737 | + int stage_count; | ||
| 738 | + | ||
| 739 | + /* If closing_branch_deps is false then the stage | ||
| 740 | + boundaries are placed efficiently, meaning that min_cycle will be | ||
| 741 | + placed at row 0. Otherwise, the closing branch will be placed in | ||
| 742 | + row ii-1. For the later case we assume the final SMSed kernel can | ||
| 743 | + be divided into two intervals. This assumption is used for the | ||
| 744 | + stage count calculation: | ||
| 745 | + | ||
| 746 | + 1) min_cycle <= interval 0 < first_cycle_in_row_zero | ||
| 747 | + 2) first_cycle_in_row_zero <= interval 1 < max_cycle | ||
| 748 | + */ | ||
| 749 | + stage_count = | ||
| 750 | + CALC_STAGE_COUNT (PS_MIN_CYCLE (ps), PS_MAX_CYCLE (ps), ps->ii); | ||
| 751 | + if (ps->g->closing_branch_deps) | ||
| 752 | + { | ||
| 753 | + int new_min_cycle; | ||
| 754 | + int new_min_cycle_row; | ||
| 755 | + int rotation_amount = SCHED_TIME (ps->g->closing_branch) + 1; | ||
| 756 | + | ||
| 757 | + /* This is the new value of min_cycle after the final rotation to | ||
| 758 | + bring closing branch into row ii-1. */ | ||
| 759 | + new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount; | ||
| 760 | + /* This is the row which the the new min_cycle will be placed in. */ | ||
| 761 | + new_min_cycle_row = SMODULO (new_min_cycle, ps->ii); | ||
| 762 | + /* If the row of min_cycle is zero then interval 0 is empty. | ||
| 763 | + Otherwise, we need to calculate interval 1 and add it by one | ||
| 764 | + to take interval 0 into account. */ | ||
| 765 | + if (new_min_cycle_row != 0) | ||
| 766 | + { | ||
| 767 | + int new_max_cycle, first_cycle_in_row_zero; | ||
| 768 | + | ||
| 769 | + new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount; | ||
| 770 | + first_cycle_in_row_zero = | ||
| 771 | + new_min_cycle + ps->ii - new_min_cycle_row; | ||
| 772 | + | ||
| 773 | + stage_count = | ||
| 774 | + CALC_STAGE_COUNT (first_cycle_in_row_zero, new_max_cycle, | ||
| 775 | + ps->ii) + 1; | ||
| 776 | + } | ||
| 777 | + } | ||
| 778 | + return stage_count; | ||
| 779 | +} | ||
| 780 | + | ||
| 781 | /* Rotate the rows of PS such that insns scheduled at time | ||
| 782 | START_CYCLE will appear in row 0. Updates max/min_cycles. */ | ||
| 783 | void | ||
| 784 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99498.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99498.patch deleted file mode 100644 index 9c305cc65..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99498.patch +++ /dev/null | |||
| @@ -1,186 +0,0 @@ | |||
| 1 | 2011-02-16 Nathan Sidwell <nathan@codesourcery.com> | ||
| 2 | |||
| 3 | Issue #10439 | ||
| 4 | gcc/ | ||
| 5 | * config/arm/unwind-arm.c (enum __cxa_type_match_result): New. | ||
| 6 | (cxa_type_match): Correct declaration. | ||
| 7 | (__gnu_unwind_pr_common): Reconstruct | ||
| 8 | additional indirection when __cxa_type_match returns | ||
| 9 | succeeded_with_ptr_to_base. | ||
| 10 | |||
| 11 | libstdc++/ | ||
| 12 | * libsupc++/eh_arm.c (__cxa_type_match): Construct address of | ||
| 13 | thrown object here. Return succeded_with_ptr_to_base for all | ||
| 14 | pointer cases. | ||
| 15 | |||
| 16 | === modified file 'gcc/config/arm/unwind-arm.c' | ||
| 17 | --- old/gcc/config/arm/unwind-arm.c 2010-08-12 12:39:35 +0000 | ||
| 18 | +++ new/gcc/config/arm/unwind-arm.c 2011-04-08 10:41:46 +0000 | ||
| 19 | @@ -32,13 +32,18 @@ | ||
| 20 | typedef unsigned char bool; | ||
| 21 | |||
| 22 | typedef struct _ZSt9type_info type_info; /* This names C++ type_info type */ | ||
| 23 | +enum __cxa_type_match_result | ||
| 24 | + { | ||
| 25 | + ctm_failed = 0, | ||
| 26 | + ctm_succeeded = 1, | ||
| 27 | + ctm_succeeded_with_ptr_to_base = 2 | ||
| 28 | + }; | ||
| 29 | |||
| 30 | void __attribute__((weak)) __cxa_call_unexpected(_Unwind_Control_Block *ucbp); | ||
| 31 | bool __attribute__((weak)) __cxa_begin_cleanup(_Unwind_Control_Block *ucbp); | ||
| 32 | -bool __attribute__((weak)) __cxa_type_match(_Unwind_Control_Block *ucbp, | ||
| 33 | - const type_info *rttip, | ||
| 34 | - bool is_reference, | ||
| 35 | - void **matched_object); | ||
| 36 | +enum __cxa_type_match_result __attribute__((weak)) __cxa_type_match | ||
| 37 | + (_Unwind_Control_Block *ucbp, const type_info *rttip, | ||
| 38 | + bool is_reference, void **matched_object); | ||
| 39 | |||
| 40 | _Unwind_Ptr __attribute__((weak)) | ||
| 41 | __gnu_Unwind_Find_exidx (_Unwind_Ptr, int *); | ||
| 42 | @@ -1107,6 +1112,7 @@ | ||
| 43 | _uw rtti; | ||
| 44 | bool is_reference = (data[0] & uint32_highbit) != 0; | ||
| 45 | void *matched; | ||
| 46 | + enum __cxa_type_match_result match_type; | ||
| 47 | |||
| 48 | /* Check for no-throw areas. */ | ||
| 49 | if (data[1] == (_uw) -2) | ||
| 50 | @@ -1118,17 +1124,31 @@ | ||
| 51 | { | ||
| 52 | /* Match a catch specification. */ | ||
| 53 | rtti = _Unwind_decode_target2 ((_uw) &data[1]); | ||
| 54 | - if (!__cxa_type_match (ucbp, (type_info *) rtti, | ||
| 55 | - is_reference, | ||
| 56 | - &matched)) | ||
| 57 | - matched = (void *)0; | ||
| 58 | + match_type = __cxa_type_match (ucbp, | ||
| 59 | + (type_info *) rtti, | ||
| 60 | + is_reference, | ||
| 61 | + &matched); | ||
| 62 | } | ||
| 63 | + else | ||
| 64 | + match_type = ctm_succeeded; | ||
| 65 | |||
| 66 | - if (matched) | ||
| 67 | + if (match_type) | ||
| 68 | { | ||
| 69 | ucbp->barrier_cache.sp = | ||
| 70 | _Unwind_GetGR (context, R_SP); | ||
| 71 | - ucbp->barrier_cache.bitpattern[0] = (_uw) matched; | ||
| 72 | + // ctm_succeeded_with_ptr_to_base really | ||
| 73 | + // means _c_t_m indirected the pointer | ||
| 74 | + // object. We have to reconstruct the | ||
| 75 | + // additional pointer layer by using a temporary. | ||
| 76 | + if (match_type == ctm_succeeded_with_ptr_to_base) | ||
| 77 | + { | ||
| 78 | + ucbp->barrier_cache.bitpattern[2] | ||
| 79 | + = (_uw) matched; | ||
| 80 | + ucbp->barrier_cache.bitpattern[0] | ||
| 81 | + = (_uw) &ucbp->barrier_cache.bitpattern[2]; | ||
| 82 | + } | ||
| 83 | + else | ||
| 84 | + ucbp->barrier_cache.bitpattern[0] = (_uw) matched; | ||
| 85 | ucbp->barrier_cache.bitpattern[1] = (_uw) data; | ||
| 86 | return _URC_HANDLER_FOUND; | ||
| 87 | } | ||
| 88 | |||
| 89 | === modified file 'libstdc++-v3/libsupc++/eh_arm.cc' | ||
| 90 | --- old/libstdc++-v3/libsupc++/eh_arm.cc 2009-04-09 14:00:19 +0000 | ||
| 91 | +++ new/libstdc++-v3/libsupc++/eh_arm.cc 2011-04-08 10:41:46 +0000 | ||
| 92 | @@ -30,10 +30,11 @@ | ||
| 93 | using namespace __cxxabiv1; | ||
| 94 | |||
| 95 | |||
| 96 | -// Given the thrown type THROW_TYPE, pointer to a variable containing a | ||
| 97 | -// pointer to the exception object THROWN_PTR_P and a type CATCH_TYPE to | ||
| 98 | -// compare against, return whether or not there is a match and if so, | ||
| 99 | -// update *THROWN_PTR_P. | ||
| 100 | +// Given the thrown type THROW_TYPE, exception object UE_HEADER and a | ||
| 101 | +// type CATCH_TYPE to compare against, return whether or not there is | ||
| 102 | +// a match and if so, update *THROWN_PTR_P to point to either the | ||
| 103 | +// type-matched object, or in the case of a pointer type, the object | ||
| 104 | +// pointed to by the pointer. | ||
| 105 | |||
| 106 | extern "C" __cxa_type_match_result | ||
| 107 | __cxa_type_match(_Unwind_Exception* ue_header, | ||
| 108 | @@ -41,51 +42,51 @@ | ||
| 109 | bool is_reference __attribute__((__unused__)), | ||
| 110 | void** thrown_ptr_p) | ||
| 111 | { | ||
| 112 | - bool forced_unwind = __is_gxx_forced_unwind_class(ue_header->exception_class); | ||
| 113 | - bool foreign_exception = !forced_unwind && !__is_gxx_exception_class(ue_header->exception_class); | ||
| 114 | - bool dependent_exception = | ||
| 115 | - __is_dependent_exception(ue_header->exception_class); | ||
| 116 | + bool forced_unwind | ||
| 117 | + = __is_gxx_forced_unwind_class(ue_header->exception_class); | ||
| 118 | + bool foreign_exception | ||
| 119 | + = !forced_unwind && !__is_gxx_exception_class(ue_header->exception_class); | ||
| 120 | + bool dependent_exception | ||
| 121 | + = __is_dependent_exception(ue_header->exception_class); | ||
| 122 | __cxa_exception* xh = __get_exception_header_from_ue(ue_header); | ||
| 123 | __cxa_dependent_exception *dx = __get_dependent_exception_from_ue(ue_header); | ||
| 124 | const std::type_info* throw_type; | ||
| 125 | + void *thrown_ptr = 0; | ||
| 126 | |||
| 127 | if (forced_unwind) | ||
| 128 | throw_type = &typeid(abi::__forced_unwind); | ||
| 129 | else if (foreign_exception) | ||
| 130 | throw_type = &typeid(abi::__foreign_exception); | ||
| 131 | - else if (dependent_exception) | ||
| 132 | - throw_type = __get_exception_header_from_obj | ||
| 133 | - (dx->primaryException)->exceptionType; | ||
| 134 | else | ||
| 135 | - throw_type = xh->exceptionType; | ||
| 136 | - | ||
| 137 | - void* thrown_ptr = *thrown_ptr_p; | ||
| 138 | + { | ||
| 139 | + if (dependent_exception) | ||
| 140 | + xh = __get_exception_header_from_obj (dx->primaryException); | ||
| 141 | + throw_type = xh->exceptionType; | ||
| 142 | + // We used to require the caller set the target of thrown_ptr_p, | ||
| 143 | + // but that's incorrect -- the EHABI makes no such requirement | ||
| 144 | + // -- and not all callers will set it. Fortunately callers that | ||
| 145 | + // do initialize will always pass us the value we calculate | ||
| 146 | + // here, so there's no backwards compatibility problem. | ||
| 147 | + thrown_ptr = __get_object_from_ue (ue_header); | ||
| 148 | + } | ||
| 149 | + | ||
| 150 | + __cxa_type_match_result result = ctm_succeeded; | ||
| 151 | |||
| 152 | // Pointer types need to adjust the actual pointer, not | ||
| 153 | // the pointer to pointer that is the exception object. | ||
| 154 | // This also has the effect of passing pointer types | ||
| 155 | // "by value" through the __cxa_begin_catch return value. | ||
| 156 | if (throw_type->__is_pointer_p()) | ||
| 157 | - thrown_ptr = *(void**) thrown_ptr; | ||
| 158 | + { | ||
| 159 | + thrown_ptr = *(void**) thrown_ptr; | ||
| 160 | + // We need to indicate the indirection to our caller. | ||
| 161 | + result = ctm_succeeded_with_ptr_to_base; | ||
| 162 | + } | ||
| 163 | |||
| 164 | if (catch_type->__do_catch(throw_type, &thrown_ptr, 1)) | ||
| 165 | { | ||
| 166 | *thrown_ptr_p = thrown_ptr; | ||
| 167 | - | ||
| 168 | - if (typeid(*catch_type) == typeid (typeid(void*))) | ||
| 169 | - { | ||
| 170 | - const __pointer_type_info *catch_pointer_type = | ||
| 171 | - static_cast<const __pointer_type_info *> (catch_type); | ||
| 172 | - const __pointer_type_info *throw_pointer_type = | ||
| 173 | - static_cast<const __pointer_type_info *> (throw_type); | ||
| 174 | - | ||
| 175 | - if (typeid (*catch_pointer_type->__pointee) != typeid (void) | ||
| 176 | - && (*catch_pointer_type->__pointee != | ||
| 177 | - *throw_pointer_type->__pointee)) | ||
| 178 | - return ctm_succeeded_with_ptr_to_base; | ||
| 179 | - } | ||
| 180 | - | ||
| 181 | - return ctm_succeeded; | ||
| 182 | + return result; | ||
| 183 | } | ||
| 184 | |||
| 185 | return ctm_failed; | ||
| 186 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99502.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99502.patch deleted file mode 100644 index 59bf01cc5..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99502.patch +++ /dev/null | |||
| @@ -1,134 +0,0 @@ | |||
| 1 | 2011-04-26 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | |||
| 5 | 2011-03-21 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 6 | |||
| 7 | gcc/ | ||
| 8 | * simplify-rtx.c (simplify_binary_operation_1): Handle | ||
| 9 | (xor (and A B) C) case when B and C are both constants. | ||
| 10 | |||
| 11 | gcc/testsuite/ | ||
| 12 | * gcc.target/arm/xor-and.c: New. | ||
| 13 | |||
| 14 | 2011-03-18 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 15 | |||
| 16 | gcc/ | ||
| 17 | * combine.c (try_combine): Do simplification only call of | ||
| 18 | subst() on i2 even when i1 is present. Update comments. | ||
| 19 | |||
| 20 | gcc/testsuite/ | ||
| 21 | * gcc.target/arm/unsigned-extend-1.c: New. | ||
| 22 | |||
| 23 | === modified file 'gcc/combine.c' | ||
| 24 | --- old/gcc/combine.c 2011-01-06 11:02:44 +0000 | ||
| 25 | +++ new/gcc/combine.c 2011-04-14 13:58:12 +0000 | ||
| 26 | @@ -2939,7 +2939,7 @@ | ||
| 27 | /* It is possible that the source of I2 or I1 may be performing | ||
| 28 | an unneeded operation, such as a ZERO_EXTEND of something | ||
| 29 | that is known to have the high part zero. Handle that case | ||
| 30 | - by letting subst look at the innermost one of them. | ||
| 31 | + by letting subst look at the inner insns. | ||
| 32 | |||
| 33 | Another way to do this would be to have a function that tries | ||
| 34 | to simplify a single insn instead of merging two or more | ||
| 35 | @@ -2964,11 +2964,9 @@ | ||
| 36 | subst_low_luid = DF_INSN_LUID (i1); | ||
| 37 | i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0); | ||
| 38 | } | ||
| 39 | - else | ||
| 40 | - { | ||
| 41 | - subst_low_luid = DF_INSN_LUID (i2); | ||
| 42 | - i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0); | ||
| 43 | - } | ||
| 44 | + | ||
| 45 | + subst_low_luid = DF_INSN_LUID (i2); | ||
| 46 | + i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0); | ||
| 47 | } | ||
| 48 | |||
| 49 | n_occurrences = 0; /* `subst' counts here */ | ||
| 50 | |||
| 51 | === modified file 'gcc/simplify-rtx.c' | ||
| 52 | --- old/gcc/simplify-rtx.c 2010-06-25 20:11:56 +0000 | ||
| 53 | +++ new/gcc/simplify-rtx.c 2011-04-14 13:58:12 +0000 | ||
| 54 | @@ -2413,6 +2413,46 @@ | ||
| 55 | XEXP (op0, 1), mode), | ||
| 56 | op1); | ||
| 57 | |||
| 58 | + /* Given (xor (and A B) C), using P^Q == (~P&Q) | (~Q&P), | ||
| 59 | + we can transform like this: | ||
| 60 | + (A&B)^C == ~(A&B)&C | ~C&(A&B) | ||
| 61 | + == (~A|~B)&C | ~C&(A&B) * DeMorgan's Law | ||
| 62 | + == ~A&C | ~B&C | A&(~C&B) * Distribute and re-order | ||
| 63 | + Attempt a few simplifications when B and C are both constants. */ | ||
| 64 | + if (GET_CODE (op0) == AND | ||
| 65 | + && CONST_INT_P (op1) | ||
| 66 | + && CONST_INT_P (XEXP (op0, 1))) | ||
| 67 | + { | ||
| 68 | + rtx a = XEXP (op0, 0); | ||
| 69 | + rtx b = XEXP (op0, 1); | ||
| 70 | + rtx c = op1; | ||
| 71 | + HOST_WIDE_INT bval = INTVAL (b); | ||
| 72 | + HOST_WIDE_INT cval = INTVAL (c); | ||
| 73 | + | ||
| 74 | + rtx na_c | ||
| 75 | + = simplify_binary_operation (AND, mode, | ||
| 76 | + simplify_gen_unary (NOT, mode, a, mode), | ||
| 77 | + c); | ||
| 78 | + if ((~cval & bval) == 0) | ||
| 79 | + { | ||
| 80 | + /* Try to simplify ~A&C | ~B&C. */ | ||
| 81 | + if (na_c != NULL_RTX) | ||
| 82 | + return simplify_gen_binary (IOR, mode, na_c, | ||
| 83 | + GEN_INT (~bval & cval)); | ||
| 84 | + } | ||
| 85 | + else | ||
| 86 | + { | ||
| 87 | + /* If ~A&C is zero, simplify A&(~C&B) | ~B&C. */ | ||
| 88 | + if (na_c == const0_rtx) | ||
| 89 | + { | ||
| 90 | + rtx a_nc_b = simplify_gen_binary (AND, mode, a, | ||
| 91 | + GEN_INT (~cval & bval)); | ||
| 92 | + return simplify_gen_binary (IOR, mode, a_nc_b, | ||
| 93 | + GEN_INT (~bval & cval)); | ||
| 94 | + } | ||
| 95 | + } | ||
| 96 | + } | ||
| 97 | + | ||
| 98 | /* (xor (comparison foo bar) (const_int 1)) can become the reversed | ||
| 99 | comparison if STORE_FLAG_VALUE is 1. */ | ||
| 100 | if (STORE_FLAG_VALUE == 1 | ||
| 101 | |||
| 102 | === added file 'gcc/testsuite/gcc.target/arm/unsigned-extend-1.c' | ||
| 103 | --- old/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c 1970-01-01 00:00:00 +0000 | ||
| 104 | +++ new/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c 2011-04-14 13:58:12 +0000 | ||
| 105 | @@ -0,0 +1,9 @@ | ||
| 106 | +/* { dg-do compile } */ | ||
| 107 | +/* { dg-options "-O2 -march=armv6" } */ | ||
| 108 | + | ||
| 109 | +unsigned char foo (unsigned char c) | ||
| 110 | +{ | ||
| 111 | + return (c >= '0') && (c <= '9'); | ||
| 112 | +} | ||
| 113 | + | ||
| 114 | +/* { dg-final { scan-assembler-not "uxtb" } } */ | ||
| 115 | |||
| 116 | === added file 'gcc/testsuite/gcc.target/arm/xor-and.c' | ||
| 117 | --- old/gcc/testsuite/gcc.target/arm/xor-and.c 1970-01-01 00:00:00 +0000 | ||
| 118 | +++ new/gcc/testsuite/gcc.target/arm/xor-and.c 2011-04-14 13:58:12 +0000 | ||
| 119 | @@ -0,0 +1,14 @@ | ||
| 120 | +/* { dg-do compile } */ | ||
| 121 | +/* { dg-options "-O -march=armv6" } */ | ||
| 122 | + | ||
| 123 | +unsigned short foo (unsigned short x) | ||
| 124 | +{ | ||
| 125 | + x ^= 0x4002; | ||
| 126 | + x >>= 1; | ||
| 127 | + x |= 0x8000; | ||
| 128 | + return x; | ||
| 129 | +} | ||
| 130 | + | ||
| 131 | +/* { dg-final { scan-assembler "orr" } } */ | ||
| 132 | +/* { dg-final { scan-assembler-not "mvn" } } */ | ||
| 133 | +/* { dg-final { scan-assembler-not "uxth" } } */ | ||
| 134 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99503.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99503.patch deleted file mode 100644 index abbd95b4d..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99503.patch +++ /dev/null | |||
| @@ -1,6070 +0,0 @@ | |||
| 1 | 2011-04-20 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 2 | |||
| 3 | gcc/testsuite/ | ||
| 4 | From Richard Earnshaw <rearnsha@arm.com> | ||
| 5 | |||
| 6 | PR target/46329 | ||
| 7 | * gcc.target/arm/pr46329.c: New test. | ||
| 8 | |||
| 9 | gcc/ | ||
| 10 | PR target/46329 | ||
| 11 | * config/arm/arm.c (arm_legitimate_constant_p_1): Return false | ||
| 12 | for all Neon struct constants. | ||
| 13 | |||
| 14 | 2011-04-20 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 15 | |||
| 16 | gcc/ | ||
| 17 | * doc/tm.texi (LEGITIMATE_CONSTANT_P): Replace with... | ||
| 18 | (TARGET_LEGITIMATE_CONSTANT_P): ...this. | ||
| 19 | * target.h (gcc_target): Add legitimate_constant_p. | ||
| 20 | * target-def.h (TARGET_LEGITIMATE_CONSTANT_P): Define. | ||
| 21 | (TARGET_INITIALIZER): Include it. | ||
| 22 | * calls.c (precompute_register_parameters): Replace uses of | ||
| 23 | LEGITIMATE_CONSTANT_P with targetm.legitimate_constant_p. | ||
| 24 | (emit_library_call_value_1): Likewise. | ||
| 25 | * expr.c (move_block_to_reg, can_store_by_pieces, emit_move_insn) | ||
| 26 | (compress_float_constant, emit_push_insn, expand_expr_real_1): Likewise. | ||
| 27 | * recog.c (general_operand, immediate_operand): Likewise. | ||
| 28 | * reload.c (find_reloads_toplev, find_reloads_address_part): Likewise. | ||
| 29 | * reload1.c (init_eliminable_invariants): Likewise. | ||
| 30 | * targhooks.h (default_legitimate_constant_p); Declare. | ||
| 31 | * targhooks.c (default_legitimate_constant_p): New function. | ||
| 32 | |||
| 33 | * config/arm/arm-protos.h (arm_cannot_force_const_mem): Delete. | ||
| 34 | * config/arm/arm.h (ARM_LEGITIMATE_CONSTANT_P): Likewise. | ||
| 35 | (THUMB_LEGITIMATE_CONSTANT_P, LEGITIMATE_CONSTANT_P): Likewise. | ||
| 36 | * config/arm/arm.c (TARGET_LEGITIMATE_CONSTANT_P): Define. | ||
| 37 | (arm_legitimate_constant_p_1, thumb_legitimate_constant_p) | ||
| 38 | (arm_legitimate_constant_p): New functions. | ||
| 39 | (arm_cannot_force_const_mem): Make static. | ||
| 40 | |||
| 41 | 2011-04-20 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 42 | |||
| 43 | gcc/ | ||
| 44 | * hooks.h (hook_bool_mode_uhwi_false): Declare. | ||
| 45 | * hooks.c (hook_bool_mode_uhwi_false): New function. | ||
| 46 | * doc/tm.texi (TARGET_ARRAY_MODE_SUPPORTED_P): Document. | ||
| 47 | * target.h (array_mode_supported_p): New hook. | ||
| 48 | * target-def.h (TARGET_ARRAY_MODE_SUPPORTED_P): Define if undefined. | ||
| 49 | (TARGET_INITIALIZER): Include it. | ||
| 50 | * stor-layout.c (mode_for_array): New function. | ||
| 51 | (layout_type): Use it. | ||
| 52 | * config/arm/arm.c (arm_array_mode_supported_p): New function. | ||
| 53 | (TARGET_ARRAY_MODE_SUPPORTED_P): Define. | ||
| 54 | |||
| 55 | 2011-04-20 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 56 | |||
| 57 | gcc/testsuite/ | ||
| 58 | Backport from mainline: | ||
| 59 | |||
| 60 | 2011-04-12 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 61 | |||
| 62 | * gcc.target/arm/neon-vld3-1.c: New test. | ||
| 63 | * gcc.target/arm/neon-vst3-1.c: New test. | ||
| 64 | * gcc.target/arm/neon/v*.c: Regenerate. | ||
| 65 | |||
| 66 | gcc/ | ||
| 67 | Backport from mainline: | ||
| 68 | |||
| 69 | 2011-04-12 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 70 | |||
| 71 | * config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the | ||
| 72 | size of a '%A' memory reference. | ||
| 73 | (T_DREG, T_QREG): New neon_builtin_type_bits. | ||
| 74 | (arm_init_neon_builtins): Assert that the load and store operands | ||
| 75 | are neon_struct_operands. | ||
| 76 | (locate_neon_builtin_icode): Provide the neon_builtin_type_bits. | ||
| 77 | (NEON_ARG_MEMORY): New builtin_arg. | ||
| 78 | (neon_dereference_pointer): New function. | ||
| 79 | (arm_expand_neon_args): Add a neon_builtin_type_bits argument. | ||
| 80 | Handle NEON_ARG_MEMORY. | ||
| 81 | (arm_expand_neon_builtin): Update after above interface changes. | ||
| 82 | Use NEON_ARG_MEMORY for loads and stores. | ||
| 83 | * config/arm/predicates.md (neon_struct_operand): New predicate. | ||
| 84 | * config/arm/neon.md (V_two_elem): Tweak formatting. | ||
| 85 | (V_three_elem): Use BLKmode for accesses that have no associated mode. | ||
| 86 | (neon_vld1<mode>, neon_vld1_dup<mode>) | ||
| 87 | (neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>) | ||
| 88 | (neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>) | ||
| 89 | (neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>) | ||
| 90 | (neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>) | ||
| 91 | (neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>) | ||
| 92 | (neon_vst4<mode>): Replace pointer operand with a memory operand. | ||
| 93 | Use %A in the output template. | ||
| 94 | (neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>) | ||
| 95 | (neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>) | ||
| 96 | (neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve | ||
| 97 | the width of the memory access. Remove post-increment. | ||
| 98 | * config/arm/neon-testgen.ml: Allow addresses to have an alignment. | ||
| 99 | |||
| 100 | 2011-04-20 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 101 | |||
| 102 | gcc/ | ||
| 103 | Backport from mainline: | ||
| 104 | |||
| 105 | 2011-03-30 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 106 | Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> | ||
| 107 | |||
| 108 | PR target/43590 | ||
| 109 | * config/arm/neon.md (neon_vld3qa<mode>, neon_vld4qa<mode>): Remove | ||
| 110 | operand 1 and reshuffle the operands to match. | ||
| 111 | (neon_vld3<mode>, neon_vld4<mode>): Update accordingly. | ||
| 112 | |||
| 113 | === modified file 'gcc/calls.c' | ||
| 114 | --- old/gcc/calls.c 2010-11-04 12:43:52 +0000 | ||
| 115 | +++ new/gcc/calls.c 2011-04-20 10:07:36 +0000 | ||
| 116 | @@ -674,7 +674,7 @@ | ||
| 117 | /* If the value is a non-legitimate constant, force it into a | ||
| 118 | pseudo now. TLS symbols sometimes need a call to resolve. */ | ||
| 119 | if (CONSTANT_P (args[i].value) | ||
| 120 | - && !LEGITIMATE_CONSTANT_P (args[i].value)) | ||
| 121 | + && !targetm.legitimate_constant_p (args[i].mode, args[i].value)) | ||
| 122 | args[i].value = force_reg (args[i].mode, args[i].value); | ||
| 123 | |||
| 124 | /* If we are to promote the function arg to a wider mode, | ||
| 125 | @@ -3413,7 +3413,8 @@ | ||
| 126 | |||
| 127 | /* Make sure it is a reasonable operand for a move or push insn. */ | ||
| 128 | if (!REG_P (addr) && !MEM_P (addr) | ||
| 129 | - && ! (CONSTANT_P (addr) && LEGITIMATE_CONSTANT_P (addr))) | ||
| 130 | + && !(CONSTANT_P (addr) | ||
| 131 | + && targetm.legitimate_constant_p (Pmode, addr))) | ||
| 132 | addr = force_operand (addr, NULL_RTX); | ||
| 133 | |||
| 134 | argvec[count].value = addr; | ||
| 135 | @@ -3453,7 +3454,7 @@ | ||
| 136 | |||
| 137 | /* Make sure it is a reasonable operand for a move or push insn. */ | ||
| 138 | if (!REG_P (val) && !MEM_P (val) | ||
| 139 | - && ! (CONSTANT_P (val) && LEGITIMATE_CONSTANT_P (val))) | ||
| 140 | + && !(CONSTANT_P (val) && targetm.legitimate_constant_p (mode, val))) | ||
| 141 | val = force_operand (val, NULL_RTX); | ||
| 142 | |||
| 143 | if (pass_by_reference (&args_so_far, mode, NULL_TREE, 1)) | ||
| 144 | |||
| 145 | === modified file 'gcc/config/arm/arm-protos.h' | ||
| 146 | --- old/gcc/config/arm/arm-protos.h 2011-02-08 12:07:29 +0000 | ||
| 147 | +++ new/gcc/config/arm/arm-protos.h 2011-04-20 10:07:36 +0000 | ||
| 148 | @@ -81,7 +81,6 @@ | ||
| 149 | extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx, | ||
| 150 | bool); | ||
| 151 | extern bool arm_tls_referenced_p (rtx); | ||
| 152 | -extern bool arm_cannot_force_const_mem (rtx); | ||
| 153 | |||
| 154 | extern int cirrus_memory_offset (rtx); | ||
| 155 | extern int arm_coproc_mem_operand (rtx, bool); | ||
| 156 | |||
| 157 | === modified file 'gcc/config/arm/arm.c' | ||
| 158 | --- old/gcc/config/arm/arm.c 2011-03-02 11:29:06 +0000 | ||
| 159 | +++ new/gcc/config/arm/arm.c 2011-04-20 10:10:50 +0000 | ||
| 160 | @@ -140,6 +140,8 @@ | ||
| 161 | static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, | ||
| 162 | tree); | ||
| 163 | static bool arm_have_conditional_execution (void); | ||
| 164 | +static bool arm_cannot_force_const_mem (rtx); | ||
| 165 | +static bool arm_legitimate_constant_p (enum machine_mode, rtx); | ||
| 166 | static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool); | ||
| 167 | static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); | ||
| 168 | static bool thumb2_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); | ||
| 169 | @@ -222,6 +224,8 @@ | ||
| 170 | static tree arm_promoted_type (const_tree t); | ||
| 171 | static tree arm_convert_to_type (tree type, tree expr); | ||
| 172 | static bool arm_scalar_mode_supported_p (enum machine_mode); | ||
| 173 | +static bool arm_array_mode_supported_p (enum machine_mode, | ||
| 174 | + unsigned HOST_WIDE_INT); | ||
| 175 | static bool arm_frame_pointer_required (void); | ||
| 176 | static bool arm_can_eliminate (const int, const int); | ||
| 177 | static void arm_asm_trampoline_template (FILE *); | ||
| 178 | @@ -355,6 +359,8 @@ | ||
| 179 | #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask | ||
| 180 | #undef TARGET_VECTOR_MODE_SUPPORTED_P | ||
| 181 | #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p | ||
| 182 | +#undef TARGET_ARRAY_MODE_SUPPORTED_P | ||
| 183 | +#define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p | ||
| 184 | |||
| 185 | #undef TARGET_MACHINE_DEPENDENT_REORG | ||
| 186 | #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg | ||
| 187 | @@ -467,6 +473,9 @@ | ||
| 188 | #undef TARGET_HAVE_CONDITIONAL_EXECUTION | ||
| 189 | #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution | ||
| 190 | |||
| 191 | +#undef TARGET_LEGITIMATE_CONSTANT_P | ||
| 192 | +#define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p | ||
| 193 | + | ||
| 194 | #undef TARGET_CANNOT_FORCE_CONST_MEM | ||
| 195 | #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem | ||
| 196 | |||
| 197 | @@ -6447,9 +6456,47 @@ | ||
| 198 | return for_each_rtx (&x, arm_tls_operand_p_1, NULL); | ||
| 199 | } | ||
| 200 | |||
| 201 | +/* Implement TARGET_LEGITIMATE_CONSTANT_P. | ||
| 202 | + | ||
| 203 | + On the ARM, allow any integer (invalid ones are removed later by insn | ||
| 204 | + patterns), nice doubles and symbol_refs which refer to the function's | ||
| 205 | + constant pool XXX. | ||
| 206 | + | ||
| 207 | + When generating pic allow anything. */ | ||
| 208 | + | ||
| 209 | +static bool | ||
| 210 | +arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x) | ||
| 211 | +{ | ||
| 212 | + /* At present, we have no support for Neon structure constants, so forbid | ||
| 213 | + them here. It might be possible to handle simple cases like 0 and -1 | ||
| 214 | + in future. */ | ||
| 215 | + if (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)) | ||
| 216 | + return false; | ||
| 217 | + | ||
| 218 | + return flag_pic || !label_mentioned_p (x); | ||
| 219 | +} | ||
| 220 | + | ||
| 221 | +static bool | ||
| 222 | +thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) | ||
| 223 | +{ | ||
| 224 | + return (GET_CODE (x) == CONST_INT | ||
| 225 | + || GET_CODE (x) == CONST_DOUBLE | ||
| 226 | + || CONSTANT_ADDRESS_P (x) | ||
| 227 | + || flag_pic); | ||
| 228 | +} | ||
| 229 | + | ||
| 230 | +static bool | ||
| 231 | +arm_legitimate_constant_p (enum machine_mode mode, rtx x) | ||
| 232 | +{ | ||
| 233 | + return (!arm_cannot_force_const_mem (x) | ||
| 234 | + && (TARGET_32BIT | ||
| 235 | + ? arm_legitimate_constant_p_1 (mode, x) | ||
| 236 | + : thumb_legitimate_constant_p (mode, x))); | ||
| 237 | +} | ||
| 238 | + | ||
| 239 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ | ||
| 240 | |||
| 241 | -bool | ||
| 242 | +static bool | ||
| 243 | arm_cannot_force_const_mem (rtx x) | ||
| 244 | { | ||
| 245 | rtx base, offset; | ||
| 246 | @@ -16847,7 +16894,7 @@ | ||
| 247 | { | ||
| 248 | rtx addr; | ||
| 249 | bool postinc = FALSE; | ||
| 250 | - unsigned align, modesize, align_bits; | ||
| 251 | + unsigned align, memsize, align_bits; | ||
| 252 | |||
| 253 | gcc_assert (GET_CODE (x) == MEM); | ||
| 254 | addr = XEXP (x, 0); | ||
| 255 | @@ -16862,12 +16909,12 @@ | ||
| 256 | instruction (for some alignments) as an aid to the memory subsystem | ||
| 257 | of the target. */ | ||
| 258 | align = MEM_ALIGN (x) >> 3; | ||
| 259 | - modesize = GET_MODE_SIZE (GET_MODE (x)); | ||
| 260 | + memsize = INTVAL (MEM_SIZE (x)); | ||
| 261 | |||
| 262 | /* Only certain alignment specifiers are supported by the hardware. */ | ||
| 263 | - if (modesize == 16 && (align % 32) == 0) | ||
| 264 | + if (memsize == 16 && (align % 32) == 0) | ||
| 265 | align_bits = 256; | ||
| 266 | - else if ((modesize == 8 || modesize == 16) && (align % 16) == 0) | ||
| 267 | + else if ((memsize == 8 || memsize == 16) && (align % 16) == 0) | ||
| 268 | align_bits = 128; | ||
| 269 | else if ((align % 8) == 0) | ||
| 270 | align_bits = 64; | ||
| 271 | @@ -16875,7 +16922,7 @@ | ||
| 272 | align_bits = 0; | ||
| 273 | |||
| 274 | if (align_bits != 0) | ||
| 275 | - asm_fprintf (stream, ", :%d", align_bits); | ||
| 276 | + asm_fprintf (stream, ":%d", align_bits); | ||
| 277 | |||
| 278 | asm_fprintf (stream, "]"); | ||
| 279 | |||
| 280 | @@ -18398,12 +18445,14 @@ | ||
| 281 | T_V2SI = 0x0004, | ||
| 282 | T_V2SF = 0x0008, | ||
| 283 | T_DI = 0x0010, | ||
| 284 | + T_DREG = 0x001F, | ||
| 285 | T_V16QI = 0x0020, | ||
| 286 | T_V8HI = 0x0040, | ||
| 287 | T_V4SI = 0x0080, | ||
| 288 | T_V4SF = 0x0100, | ||
| 289 | T_V2DI = 0x0200, | ||
| 290 | T_TI = 0x0400, | ||
| 291 | + T_QREG = 0x07E0, | ||
| 292 | T_EI = 0x0800, | ||
| 293 | T_OI = 0x1000 | ||
| 294 | }; | ||
| 295 | @@ -19049,10 +19098,9 @@ | ||
| 296 | if (is_load && k == 1) | ||
| 297 | { | ||
| 298 | /* Neon load patterns always have the memory operand | ||
| 299 | - (a SImode pointer) in the operand 1 position. We | ||
| 300 | - want a const pointer to the element type in that | ||
| 301 | - position. */ | ||
| 302 | - gcc_assert (insn_data[icode].operand[k].mode == SImode); | ||
| 303 | + in the operand 1 position. */ | ||
| 304 | + gcc_assert (insn_data[icode].operand[k].predicate | ||
| 305 | + == neon_struct_operand); | ||
| 306 | |||
| 307 | switch (1 << j) | ||
| 308 | { | ||
| 309 | @@ -19087,10 +19135,9 @@ | ||
| 310 | else if (is_store && k == 0) | ||
| 311 | { | ||
| 312 | /* Similarly, Neon store patterns use operand 0 as | ||
| 313 | - the memory location to store to (a SImode pointer). | ||
| 314 | - Use a pointer to the element type of the store in | ||
| 315 | - that position. */ | ||
| 316 | - gcc_assert (insn_data[icode].operand[k].mode == SImode); | ||
| 317 | + the memory location to store to. */ | ||
| 318 | + gcc_assert (insn_data[icode].operand[k].predicate | ||
| 319 | + == neon_struct_operand); | ||
| 320 | |||
| 321 | switch (1 << j) | ||
| 322 | { | ||
| 323 | @@ -19410,10 +19457,11 @@ | ||
| 324 | } | ||
| 325 | |||
| 326 | static enum insn_code | ||
| 327 | -locate_neon_builtin_icode (int fcode, neon_itype *itype) | ||
| 328 | +locate_neon_builtin_icode (int fcode, neon_itype *itype, | ||
| 329 | + enum neon_builtin_type_bits *type_bit) | ||
| 330 | { | ||
| 331 | neon_builtin_datum key, *found; | ||
| 332 | - int idx; | ||
| 333 | + int idx, type, ntypes; | ||
| 334 | |||
| 335 | key.base_fcode = fcode; | ||
| 336 | found = (neon_builtin_datum *) | ||
| 337 | @@ -19426,20 +19474,83 @@ | ||
| 338 | if (itype) | ||
| 339 | *itype = found->itype; | ||
| 340 | |||
| 341 | + if (type_bit) | ||
| 342 | + { | ||
| 343 | + ntypes = 0; | ||
| 344 | + for (type = 0; type < T_MAX; type++) | ||
| 345 | + if (found->bits & (1 << type)) | ||
| 346 | + { | ||
| 347 | + if (ntypes == idx) | ||
| 348 | + break; | ||
| 349 | + ntypes++; | ||
| 350 | + } | ||
| 351 | + gcc_assert (type < T_MAX); | ||
| 352 | + *type_bit = (enum neon_builtin_type_bits) (1 << type); | ||
| 353 | + } | ||
| 354 | return found->codes[idx]; | ||
| 355 | } | ||
| 356 | |||
| 357 | typedef enum { | ||
| 358 | NEON_ARG_COPY_TO_REG, | ||
| 359 | NEON_ARG_CONSTANT, | ||
| 360 | + NEON_ARG_MEMORY, | ||
| 361 | NEON_ARG_STOP | ||
| 362 | } builtin_arg; | ||
| 363 | |||
| 364 | #define NEON_MAX_BUILTIN_ARGS 5 | ||
| 365 | |||
| 366 | +/* EXP is a pointer argument to a Neon load or store intrinsic. Derive | ||
| 367 | + and return an expression for the accessed memory. | ||
| 368 | + | ||
| 369 | + The intrinsic function operates on a block of registers that has | ||
| 370 | + mode REG_MODE. This block contains vectors of type TYPE_BIT. | ||
| 371 | + The function references the memory at EXP in mode MEM_MODE; | ||
| 372 | + this mode may be BLKmode if no more suitable mode is available. */ | ||
| 373 | + | ||
| 374 | +static tree | ||
| 375 | +neon_dereference_pointer (tree exp, enum machine_mode mem_mode, | ||
| 376 | + enum machine_mode reg_mode, | ||
| 377 | + enum neon_builtin_type_bits type_bit) | ||
| 378 | +{ | ||
| 379 | + HOST_WIDE_INT reg_size, vector_size, nvectors, nelems; | ||
| 380 | + tree elem_type, upper_bound, array_type; | ||
| 381 | + | ||
| 382 | + /* Work out the size of the register block in bytes. */ | ||
| 383 | + reg_size = GET_MODE_SIZE (reg_mode); | ||
| 384 | + | ||
| 385 | + /* Work out the size of each vector in bytes. */ | ||
| 386 | + gcc_assert (type_bit & (T_DREG | T_QREG)); | ||
| 387 | + vector_size = (type_bit & T_QREG ? 16 : 8); | ||
| 388 | + | ||
| 389 | + /* Work out how many vectors there are. */ | ||
| 390 | + gcc_assert (reg_size % vector_size == 0); | ||
| 391 | + nvectors = reg_size / vector_size; | ||
| 392 | + | ||
| 393 | + /* Work out how many elements are being loaded or stored. | ||
| 394 | + MEM_MODE == REG_MODE implies a one-to-one mapping between register | ||
| 395 | + and memory elements; anything else implies a lane load or store. */ | ||
| 396 | + if (mem_mode == reg_mode) | ||
| 397 | + nelems = vector_size * nvectors; | ||
| 398 | + else | ||
| 399 | + nelems = nvectors; | ||
| 400 | + | ||
| 401 | + /* Work out the type of each element. */ | ||
| 402 | + gcc_assert (POINTER_TYPE_P (TREE_TYPE (exp))); | ||
| 403 | + elem_type = TREE_TYPE (TREE_TYPE (exp)); | ||
| 404 | + | ||
| 405 | + /* Create a type that describes the full access. */ | ||
| 406 | + upper_bound = build_int_cst (size_type_node, nelems - 1); | ||
| 407 | + array_type = build_array_type (elem_type, build_index_type (upper_bound)); | ||
| 408 | + | ||
| 409 | + /* Dereference EXP using that type. */ | ||
| 410 | + exp = convert (build_pointer_type (array_type), exp); | ||
| 411 | + return fold_build1 (INDIRECT_REF, array_type, exp); | ||
| 412 | +} | ||
| 413 | + | ||
| 414 | /* Expand a Neon builtin. */ | ||
| 415 | static rtx | ||
| 416 | arm_expand_neon_args (rtx target, int icode, int have_retval, | ||
| 417 | + enum neon_builtin_type_bits type_bit, | ||
| 418 | tree exp, ...) | ||
| 419 | { | ||
| 420 | va_list ap; | ||
| 421 | @@ -19448,7 +19559,9 @@ | ||
| 422 | rtx op[NEON_MAX_BUILTIN_ARGS]; | ||
| 423 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | ||
| 424 | enum machine_mode mode[NEON_MAX_BUILTIN_ARGS]; | ||
| 425 | + enum machine_mode other_mode; | ||
| 426 | int argc = 0; | ||
| 427 | + int opno; | ||
| 428 | |||
| 429 | if (have_retval | ||
| 430 | && (!target | ||
| 431 | @@ -19466,26 +19579,46 @@ | ||
| 432 | break; | ||
| 433 | else | ||
| 434 | { | ||
| 435 | + opno = argc + have_retval; | ||
| 436 | + mode[argc] = insn_data[icode].operand[opno].mode; | ||
| 437 | arg[argc] = CALL_EXPR_ARG (exp, argc); | ||
| 438 | + if (thisarg == NEON_ARG_MEMORY) | ||
| 439 | + { | ||
| 440 | + other_mode = insn_data[icode].operand[1 - opno].mode; | ||
| 441 | + arg[argc] = neon_dereference_pointer (arg[argc], mode[argc], | ||
| 442 | + other_mode, type_bit); | ||
| 443 | + } | ||
| 444 | op[argc] = expand_normal (arg[argc]); | ||
| 445 | - mode[argc] = insn_data[icode].operand[argc + have_retval].mode; | ||
| 446 | |||
| 447 | switch (thisarg) | ||
| 448 | { | ||
| 449 | case NEON_ARG_COPY_TO_REG: | ||
| 450 | /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/ | ||
| 451 | - if (!(*insn_data[icode].operand[argc + have_retval].predicate) | ||
| 452 | + if (!(*insn_data[icode].operand[opno].predicate) | ||
| 453 | (op[argc], mode[argc])) | ||
| 454 | op[argc] = copy_to_mode_reg (mode[argc], op[argc]); | ||
| 455 | break; | ||
| 456 | |||
| 457 | case NEON_ARG_CONSTANT: | ||
| 458 | /* FIXME: This error message is somewhat unhelpful. */ | ||
| 459 | - if (!(*insn_data[icode].operand[argc + have_retval].predicate) | ||
| 460 | + if (!(*insn_data[icode].operand[opno].predicate) | ||
| 461 | (op[argc], mode[argc])) | ||
| 462 | error ("argument must be a constant"); | ||
| 463 | break; | ||
| 464 | |||
| 465 | + case NEON_ARG_MEMORY: | ||
| 466 | + gcc_assert (MEM_P (op[argc])); | ||
| 467 | + PUT_MODE (op[argc], mode[argc]); | ||
| 468 | + /* ??? arm_neon.h uses the same built-in functions for signed | ||
| 469 | + and unsigned accesses, casting where necessary. This isn't | ||
| 470 | + alias safe. */ | ||
| 471 | + set_mem_alias_set (op[argc], 0); | ||
| 472 | + if (!(*insn_data[icode].operand[opno].predicate) | ||
| 473 | + (op[argc], mode[argc])) | ||
| 474 | + op[argc] = (replace_equiv_address | ||
| 475 | + (op[argc], force_reg (Pmode, XEXP (op[argc], 0)))); | ||
| 476 | + break; | ||
| 477 | + | ||
| 478 | case NEON_ARG_STOP: | ||
| 479 | gcc_unreachable (); | ||
| 480 | } | ||
| 481 | @@ -19564,14 +19697,15 @@ | ||
| 482 | arm_expand_neon_builtin (int fcode, tree exp, rtx target) | ||
| 483 | { | ||
| 484 | neon_itype itype; | ||
| 485 | - enum insn_code icode = locate_neon_builtin_icode (fcode, &itype); | ||
| 486 | + enum neon_builtin_type_bits type_bit; | ||
| 487 | + enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, &type_bit); | ||
| 488 | |||
| 489 | switch (itype) | ||
| 490 | { | ||
| 491 | case NEON_UNOP: | ||
| 492 | case NEON_CONVERT: | ||
| 493 | case NEON_DUPLANE: | ||
| 494 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 495 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 496 | NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); | ||
| 497 | |||
| 498 | case NEON_BINOP: | ||
| 499 | @@ -19581,90 +19715,90 @@ | ||
| 500 | case NEON_SCALARMULH: | ||
| 501 | case NEON_SHIFTINSERT: | ||
| 502 | case NEON_LOGICBINOP: | ||
| 503 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 504 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 505 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | ||
| 506 | NEON_ARG_STOP); | ||
| 507 | |||
| 508 | case NEON_TERNOP: | ||
| 509 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 510 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 511 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | ||
| 512 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | ||
| 513 | |||
| 514 | case NEON_GETLANE: | ||
| 515 | case NEON_FIXCONV: | ||
| 516 | case NEON_SHIFTIMM: | ||
| 517 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 518 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 519 | NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, | ||
| 520 | NEON_ARG_STOP); | ||
| 521 | |||
| 522 | case NEON_CREATE: | ||
| 523 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 524 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 525 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | ||
| 526 | |||
| 527 | case NEON_DUP: | ||
| 528 | case NEON_SPLIT: | ||
| 529 | case NEON_REINTERP: | ||
| 530 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 531 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 532 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | ||
| 533 | |||
| 534 | case NEON_COMBINE: | ||
| 535 | case NEON_VTBL: | ||
| 536 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 537 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 538 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | ||
| 539 | |||
| 540 | case NEON_RESULTPAIR: | ||
| 541 | - return arm_expand_neon_args (target, icode, 0, exp, | ||
| 542 | + return arm_expand_neon_args (target, icode, 0, type_bit, exp, | ||
| 543 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | ||
| 544 | NEON_ARG_STOP); | ||
| 545 | |||
| 546 | case NEON_LANEMUL: | ||
| 547 | case NEON_LANEMULL: | ||
| 548 | case NEON_LANEMULH: | ||
| 549 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 550 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 551 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | ||
| 552 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | ||
| 553 | |||
| 554 | case NEON_LANEMAC: | ||
| 555 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 556 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 557 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | ||
| 558 | NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP); | ||
| 559 | |||
| 560 | case NEON_SHIFTACC: | ||
| 561 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 562 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 563 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | ||
| 564 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | ||
| 565 | |||
| 566 | case NEON_SCALARMAC: | ||
| 567 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 568 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 569 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | ||
| 570 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | ||
| 571 | |||
| 572 | case NEON_SELECT: | ||
| 573 | case NEON_VTBX: | ||
| 574 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 575 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 576 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | ||
| 577 | NEON_ARG_STOP); | ||
| 578 | |||
| 579 | case NEON_LOAD1: | ||
| 580 | case NEON_LOADSTRUCT: | ||
| 581 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 582 | - NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | ||
| 583 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 584 | + NEON_ARG_MEMORY, NEON_ARG_STOP); | ||
| 585 | |||
| 586 | case NEON_LOAD1LANE: | ||
| 587 | case NEON_LOADSTRUCTLANE: | ||
| 588 | - return arm_expand_neon_args (target, icode, 1, exp, | ||
| 589 | - NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | ||
| 590 | + return arm_expand_neon_args (target, icode, 1, type_bit, exp, | ||
| 591 | + NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | ||
| 592 | NEON_ARG_STOP); | ||
| 593 | |||
| 594 | case NEON_STORE1: | ||
| 595 | case NEON_STORESTRUCT: | ||
| 596 | - return arm_expand_neon_args (target, icode, 0, exp, | ||
| 597 | - NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | ||
| 598 | + return arm_expand_neon_args (target, icode, 0, type_bit, exp, | ||
| 599 | + NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | ||
| 600 | |||
| 601 | case NEON_STORE1LANE: | ||
| 602 | case NEON_STORESTRUCTLANE: | ||
| 603 | - return arm_expand_neon_args (target, icode, 0, exp, | ||
| 604 | - NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | ||
| 605 | + return arm_expand_neon_args (target, icode, 0, type_bit, exp, | ||
| 606 | + NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | ||
| 607 | NEON_ARG_STOP); | ||
| 608 | } | ||
| 609 | |||
| 610 | @@ -22349,6 +22483,20 @@ | ||
| 611 | return false; | ||
| 612 | } | ||
| 613 | |||
| 614 | +/* Implements target hook array_mode_supported_p. */ | ||
| 615 | + | ||
| 616 | +static bool | ||
| 617 | +arm_array_mode_supported_p (enum machine_mode mode, | ||
| 618 | + unsigned HOST_WIDE_INT nelems) | ||
| 619 | +{ | ||
| 620 | + if (TARGET_NEON | ||
| 621 | + && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)) | ||
| 622 | + && (nelems >= 2 && nelems <= 4)) | ||
| 623 | + return true; | ||
| 624 | + | ||
| 625 | + return false; | ||
| 626 | +} | ||
| 627 | + | ||
| 628 | /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal | ||
| 629 | ARM insns and therefore guarantee that the shift count is modulo 256. | ||
| 630 | DImode shifts (those implemented by lib1funcs.asm or by optabs.c) | ||
| 631 | |||
| 632 | === modified file 'gcc/config/arm/arm.h' | ||
| 633 | --- old/gcc/config/arm/arm.h 2011-02-08 12:07:29 +0000 | ||
| 634 | +++ new/gcc/config/arm/arm.h 2011-04-20 10:07:36 +0000 | ||
| 635 | @@ -1996,27 +1996,6 @@ | ||
| 636 | #define TARGET_DEFAULT_WORD_RELOCATIONS 0 | ||
| 637 | #endif | ||
| 638 | |||
| 639 | -/* Nonzero if the constant value X is a legitimate general operand. | ||
| 640 | - It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | ||
| 641 | - | ||
| 642 | - On the ARM, allow any integer (invalid ones are removed later by insn | ||
| 643 | - patterns), nice doubles and symbol_refs which refer to the function's | ||
| 644 | - constant pool XXX. | ||
| 645 | - | ||
| 646 | - When generating pic allow anything. */ | ||
| 647 | -#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) | ||
| 648 | - | ||
| 649 | -#define THUMB_LEGITIMATE_CONSTANT_P(X) \ | ||
| 650 | - ( GET_CODE (X) == CONST_INT \ | ||
| 651 | - || GET_CODE (X) == CONST_DOUBLE \ | ||
| 652 | - || CONSTANT_ADDRESS_P (X) \ | ||
| 653 | - || flag_pic) | ||
| 654 | - | ||
| 655 | -#define LEGITIMATE_CONSTANT_P(X) \ | ||
| 656 | - (!arm_cannot_force_const_mem (X) \ | ||
| 657 | - && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \ | ||
| 658 | - : THUMB_LEGITIMATE_CONSTANT_P (X))) | ||
| 659 | - | ||
| 660 | #ifndef SUBTARGET_NAME_ENCODING_LENGTHS | ||
| 661 | #define SUBTARGET_NAME_ENCODING_LENGTHS | ||
| 662 | #endif | ||
| 663 | |||
| 664 | === modified file 'gcc/config/arm/neon-testgen.ml' | ||
| 665 | --- old/gcc/config/arm/neon-testgen.ml 2010-08-20 13:27:11 +0000 | ||
| 666 | +++ new/gcc/config/arm/neon-testgen.ml 2011-04-20 10:00:39 +0000 | ||
| 667 | @@ -177,7 +177,7 @@ | ||
| 668 | let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in | ||
| 669 | "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}" | ||
| 670 | | (PtrTo elt | CstPtrTo elt) -> | ||
| 671 | - "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\\\\\]" | ||
| 672 | + "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]" | ||
| 673 | | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]" | ||
| 674 | | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]" | ||
| 675 | | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]" | ||
| 676 | |||
| 677 | === modified file 'gcc/config/arm/neon.md' | ||
| 678 | --- old/gcc/config/arm/neon.md 2010-11-04 11:47:50 +0000 | ||
| 679 | +++ new/gcc/config/arm/neon.md 2011-04-20 10:00:39 +0000 | ||
| 680 | @@ -259,20 +259,18 @@ | ||
| 681 | |||
| 682 | ;; Mode of pair of elements for each vector mode, to define transfer | ||
| 683 | ;; size for structure lane/dup loads and stores. | ||
| 684 | -(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") | ||
| 685 | - (V4HI "SI") (V8HI "SI") | ||
| 686 | +(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") | ||
| 687 | + (V4HI "SI") (V8HI "SI") | ||
| 688 | (V2SI "V2SI") (V4SI "V2SI") | ||
| 689 | (V2SF "V2SF") (V4SF "V2SF") | ||
| 690 | (DI "V2DI") (V2DI "V2DI")]) | ||
| 691 | |||
| 692 | ;; Similar, for three elements. | ||
| 693 | -;; ??? Should we define extra modes so that sizes of all three-element | ||
| 694 | -;; accesses can be accurately represented? | ||
| 695 | -(define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI") | ||
| 696 | - (V4HI "V4HI") (V8HI "V4HI") | ||
| 697 | - (V2SI "V4SI") (V4SI "V4SI") | ||
| 698 | - (V2SF "V4SF") (V4SF "V4SF") | ||
| 699 | - (DI "EI") (V2DI "EI")]) | ||
| 700 | +(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK") | ||
| 701 | + (V4HI "BLK") (V8HI "BLK") | ||
| 702 | + (V2SI "BLK") (V4SI "BLK") | ||
| 703 | + (V2SF "BLK") (V4SF "BLK") | ||
| 704 | + (DI "EI") (V2DI "EI")]) | ||
| 705 | |||
| 706 | ;; Similar, for four elements. | ||
| 707 | (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") | ||
| 708 | @@ -4567,16 +4565,16 @@ | ||
| 709 | |||
| 710 | (define_insn "neon_vld1<mode>" | ||
| 711 | [(set (match_operand:VDQX 0 "s_register_operand" "=w") | ||
| 712 | - (unspec:VDQX [(mem:VDQX (match_operand:SI 1 "s_register_operand" "r"))] | ||
| 713 | + (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")] | ||
| 714 | UNSPEC_VLD1))] | ||
| 715 | "TARGET_NEON" | ||
| 716 | - "vld1.<V_sz_elem>\t%h0, [%1]" | ||
| 717 | + "vld1.<V_sz_elem>\t%h0, %A1" | ||
| 718 | [(set_attr "neon_type" "neon_vld1_1_2_regs")] | ||
| 719 | ) | ||
| 720 | |||
| 721 | (define_insn "neon_vld1_lane<mode>" | ||
| 722 | [(set (match_operand:VDX 0 "s_register_operand" "=w") | ||
| 723 | - (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r")) | ||
| 724 | + (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um") | ||
| 725 | (match_operand:VDX 2 "s_register_operand" "0") | ||
| 726 | (match_operand:SI 3 "immediate_operand" "i")] | ||
| 727 | UNSPEC_VLD1_LANE))] | ||
| 728 | @@ -4587,9 +4585,9 @@ | ||
| 729 | if (lane < 0 || lane >= max) | ||
| 730 | error ("lane out of range"); | ||
| 731 | if (max == 1) | ||
| 732 | - return "vld1.<V_sz_elem>\t%P0, [%1]"; | ||
| 733 | + return "vld1.<V_sz_elem>\t%P0, %A1"; | ||
| 734 | else | ||
| 735 | - return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]"; | ||
| 736 | + return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1"; | ||
| 737 | } | ||
| 738 | [(set (attr "neon_type") | ||
| 739 | (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2)) | ||
| 740 | @@ -4599,7 +4597,7 @@ | ||
| 741 | |||
| 742 | (define_insn "neon_vld1_lane<mode>" | ||
| 743 | [(set (match_operand:VQX 0 "s_register_operand" "=w") | ||
| 744 | - (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r")) | ||
| 745 | + (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um") | ||
| 746 | (match_operand:VQX 2 "s_register_operand" "0") | ||
| 747 | (match_operand:SI 3 "immediate_operand" "i")] | ||
| 748 | UNSPEC_VLD1_LANE))] | ||
| 749 | @@ -4618,9 +4616,9 @@ | ||
| 750 | } | ||
| 751 | operands[0] = gen_rtx_REG (<V_HALF>mode, regno); | ||
| 752 | if (max == 2) | ||
| 753 | - return "vld1.<V_sz_elem>\t%P0, [%1]"; | ||
| 754 | + return "vld1.<V_sz_elem>\t%P0, %A1"; | ||
| 755 | else | ||
| 756 | - return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]"; | ||
| 757 | + return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1"; | ||
| 758 | } | ||
| 759 | [(set (attr "neon_type") | ||
| 760 | (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2)) | ||
| 761 | @@ -4630,14 +4628,14 @@ | ||
| 762 | |||
| 763 | (define_insn "neon_vld1_dup<mode>" | ||
| 764 | [(set (match_operand:VDX 0 "s_register_operand" "=w") | ||
| 765 | - (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))] | ||
| 766 | + (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")] | ||
| 767 | UNSPEC_VLD1_DUP))] | ||
| 768 | "TARGET_NEON" | ||
| 769 | { | ||
| 770 | if (GET_MODE_NUNITS (<MODE>mode) > 1) | ||
| 771 | - return "vld1.<V_sz_elem>\t{%P0[]}, [%1]"; | ||
| 772 | + return "vld1.<V_sz_elem>\t{%P0[]}, %A1"; | ||
| 773 | else | ||
| 774 | - return "vld1.<V_sz_elem>\t%h0, [%1]"; | ||
| 775 | + return "vld1.<V_sz_elem>\t%h0, %A1"; | ||
| 776 | } | ||
| 777 | [(set (attr "neon_type") | ||
| 778 | (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) | ||
| 779 | @@ -4647,14 +4645,14 @@ | ||
| 780 | |||
| 781 | (define_insn "neon_vld1_dup<mode>" | ||
| 782 | [(set (match_operand:VQX 0 "s_register_operand" "=w") | ||
| 783 | - (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))] | ||
| 784 | + (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")] | ||
| 785 | UNSPEC_VLD1_DUP))] | ||
| 786 | "TARGET_NEON" | ||
| 787 | { | ||
| 788 | if (GET_MODE_NUNITS (<MODE>mode) > 2) | ||
| 789 | - return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, [%1]"; | ||
| 790 | + return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, %A1"; | ||
| 791 | else | ||
| 792 | - return "vld1.<V_sz_elem>\t%h0, [%1]"; | ||
| 793 | + return "vld1.<V_sz_elem>\t%h0, %A1"; | ||
| 794 | } | ||
| 795 | [(set (attr "neon_type") | ||
| 796 | (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) | ||
| 797 | @@ -4663,15 +4661,15 @@ | ||
| 798 | ) | ||
| 799 | |||
| 800 | (define_insn "neon_vst1<mode>" | ||
| 801 | - [(set (mem:VDQX (match_operand:SI 0 "s_register_operand" "r")) | ||
| 802 | + [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um") | ||
| 803 | (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")] | ||
| 804 | UNSPEC_VST1))] | ||
| 805 | "TARGET_NEON" | ||
| 806 | - "vst1.<V_sz_elem>\t%h1, [%0]" | ||
| 807 | + "vst1.<V_sz_elem>\t%h1, %A0" | ||
| 808 | [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]) | ||
| 809 | |||
| 810 | (define_insn "neon_vst1_lane<mode>" | ||
| 811 | - [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r")) | ||
| 812 | + [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um") | ||
| 813 | (vec_select:<V_elem> | ||
| 814 | (match_operand:VDX 1 "s_register_operand" "w") | ||
| 815 | (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))] | ||
| 816 | @@ -4682,9 +4680,9 @@ | ||
| 817 | if (lane < 0 || lane >= max) | ||
| 818 | error ("lane out of range"); | ||
| 819 | if (max == 1) | ||
| 820 | - return "vst1.<V_sz_elem>\t{%P1}, [%0]"; | ||
| 821 | + return "vst1.<V_sz_elem>\t{%P1}, %A0"; | ||
| 822 | else | ||
| 823 | - return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]"; | ||
| 824 | + return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0"; | ||
| 825 | } | ||
| 826 | [(set (attr "neon_type") | ||
| 827 | (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1)) | ||
| 828 | @@ -4692,7 +4690,7 @@ | ||
| 829 | (const_string "neon_vst1_vst2_lane")))]) | ||
| 830 | |||
| 831 | (define_insn "neon_vst1_lane<mode>" | ||
| 832 | - [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r")) | ||
| 833 | + [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um") | ||
| 834 | (vec_select:<V_elem> | ||
| 835 | (match_operand:VQX 1 "s_register_operand" "w") | ||
| 836 | (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))] | ||
| 837 | @@ -4711,24 +4709,24 @@ | ||
| 838 | } | ||
| 839 | operands[1] = gen_rtx_REG (<V_HALF>mode, regno); | ||
| 840 | if (max == 2) | ||
| 841 | - return "vst1.<V_sz_elem>\t{%P1}, [%0]"; | ||
| 842 | + return "vst1.<V_sz_elem>\t{%P1}, %A0"; | ||
| 843 | else | ||
| 844 | - return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]"; | ||
| 845 | + return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0"; | ||
| 846 | } | ||
| 847 | [(set_attr "neon_type" "neon_vst1_vst2_lane")] | ||
| 848 | ) | ||
| 849 | |||
| 850 | (define_insn "neon_vld2<mode>" | ||
| 851 | [(set (match_operand:TI 0 "s_register_operand" "=w") | ||
| 852 | - (unspec:TI [(mem:TI (match_operand:SI 1 "s_register_operand" "r")) | ||
| 853 | + (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um") | ||
| 854 | (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 855 | UNSPEC_VLD2))] | ||
| 856 | "TARGET_NEON" | ||
| 857 | { | ||
| 858 | if (<V_sz_elem> == 64) | ||
| 859 | - return "vld1.64\t%h0, [%1]"; | ||
| 860 | + return "vld1.64\t%h0, %A1"; | ||
| 861 | else | ||
| 862 | - return "vld2.<V_sz_elem>\t%h0, [%1]"; | ||
| 863 | + return "vld2.<V_sz_elem>\t%h0, %A1"; | ||
| 864 | } | ||
| 865 | [(set (attr "neon_type") | ||
| 866 | (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) | ||
| 867 | @@ -4738,16 +4736,16 @@ | ||
| 868 | |||
| 869 | (define_insn "neon_vld2<mode>" | ||
| 870 | [(set (match_operand:OI 0 "s_register_operand" "=w") | ||
| 871 | - (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r")) | ||
| 872 | + (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") | ||
| 873 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 874 | UNSPEC_VLD2))] | ||
| 875 | "TARGET_NEON" | ||
| 876 | - "vld2.<V_sz_elem>\t%h0, [%1]" | ||
| 877 | + "vld2.<V_sz_elem>\t%h0, %A1" | ||
| 878 | [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")]) | ||
| 879 | |||
| 880 | (define_insn "neon_vld2_lane<mode>" | ||
| 881 | [(set (match_operand:TI 0 "s_register_operand" "=w") | ||
| 882 | - (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r")) | ||
| 883 | + (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um") | ||
| 884 | (match_operand:TI 2 "s_register_operand" "0") | ||
| 885 | (match_operand:SI 3 "immediate_operand" "i") | ||
| 886 | (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 887 | @@ -4764,7 +4762,7 @@ | ||
| 888 | ops[1] = gen_rtx_REG (DImode, regno + 2); | ||
| 889 | ops[2] = operands[1]; | ||
| 890 | ops[3] = operands[3]; | ||
| 891 | - output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops); | ||
| 892 | + output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops); | ||
| 893 | return ""; | ||
| 894 | } | ||
| 895 | [(set_attr "neon_type" "neon_vld1_vld2_lane")] | ||
| 896 | @@ -4772,7 +4770,7 @@ | ||
| 897 | |||
| 898 | (define_insn "neon_vld2_lane<mode>" | ||
| 899 | [(set (match_operand:OI 0 "s_register_operand" "=w") | ||
| 900 | - (unspec:OI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r")) | ||
| 901 | + (unspec:OI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um") | ||
| 902 | (match_operand:OI 2 "s_register_operand" "0") | ||
| 903 | (match_operand:SI 3 "immediate_operand" "i") | ||
| 904 | (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 905 | @@ -4794,7 +4792,7 @@ | ||
| 906 | ops[1] = gen_rtx_REG (DImode, regno + 4); | ||
| 907 | ops[2] = operands[1]; | ||
| 908 | ops[3] = GEN_INT (lane); | ||
| 909 | - output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops); | ||
| 910 | + output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops); | ||
| 911 | return ""; | ||
| 912 | } | ||
| 913 | [(set_attr "neon_type" "neon_vld1_vld2_lane")] | ||
| 914 | @@ -4802,15 +4800,15 @@ | ||
| 915 | |||
| 916 | (define_insn "neon_vld2_dup<mode>" | ||
| 917 | [(set (match_operand:TI 0 "s_register_operand" "=w") | ||
| 918 | - (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r")) | ||
| 919 | + (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um") | ||
| 920 | (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 921 | UNSPEC_VLD2_DUP))] | ||
| 922 | "TARGET_NEON" | ||
| 923 | { | ||
| 924 | if (GET_MODE_NUNITS (<MODE>mode) > 1) | ||
| 925 | - return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, [%1]"; | ||
| 926 | + return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, %A1"; | ||
| 927 | else | ||
| 928 | - return "vld1.<V_sz_elem>\t%h0, [%1]"; | ||
| 929 | + return "vld1.<V_sz_elem>\t%h0, %A1"; | ||
| 930 | } | ||
| 931 | [(set (attr "neon_type") | ||
| 932 | (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) | ||
| 933 | @@ -4819,16 +4817,16 @@ | ||
| 934 | ) | ||
| 935 | |||
| 936 | (define_insn "neon_vst2<mode>" | ||
| 937 | - [(set (mem:TI (match_operand:SI 0 "s_register_operand" "r")) | ||
| 938 | + [(set (match_operand:TI 0 "neon_struct_operand" "=Um") | ||
| 939 | (unspec:TI [(match_operand:TI 1 "s_register_operand" "w") | ||
| 940 | (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 941 | UNSPEC_VST2))] | ||
| 942 | "TARGET_NEON" | ||
| 943 | { | ||
| 944 | if (<V_sz_elem> == 64) | ||
| 945 | - return "vst1.64\t%h1, [%0]"; | ||
| 946 | + return "vst1.64\t%h1, %A0"; | ||
| 947 | else | ||
| 948 | - return "vst2.<V_sz_elem>\t%h1, [%0]"; | ||
| 949 | + return "vst2.<V_sz_elem>\t%h1, %A0"; | ||
| 950 | } | ||
| 951 | [(set (attr "neon_type") | ||
| 952 | (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) | ||
| 953 | @@ -4837,17 +4835,17 @@ | ||
| 954 | ) | ||
| 955 | |||
| 956 | (define_insn "neon_vst2<mode>" | ||
| 957 | - [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r")) | ||
| 958 | + [(set (match_operand:OI 0 "neon_struct_operand" "=Um") | ||
| 959 | (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") | ||
| 960 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 961 | UNSPEC_VST2))] | ||
| 962 | "TARGET_NEON" | ||
| 963 | - "vst2.<V_sz_elem>\t%h1, [%0]" | ||
| 964 | + "vst2.<V_sz_elem>\t%h1, %A0" | ||
| 965 | [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")] | ||
| 966 | ) | ||
| 967 | |||
| 968 | (define_insn "neon_vst2_lane<mode>" | ||
| 969 | - [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r")) | ||
| 970 | + [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um") | ||
| 971 | (unspec:<V_two_elem> | ||
| 972 | [(match_operand:TI 1 "s_register_operand" "w") | ||
| 973 | (match_operand:SI 2 "immediate_operand" "i") | ||
| 974 | @@ -4865,14 +4863,14 @@ | ||
| 975 | ops[1] = gen_rtx_REG (DImode, regno); | ||
| 976 | ops[2] = gen_rtx_REG (DImode, regno + 2); | ||
| 977 | ops[3] = operands[2]; | ||
| 978 | - output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops); | ||
| 979 | + output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops); | ||
| 980 | return ""; | ||
| 981 | } | ||
| 982 | [(set_attr "neon_type" "neon_vst1_vst2_lane")] | ||
| 983 | ) | ||
| 984 | |||
| 985 | (define_insn "neon_vst2_lane<mode>" | ||
| 986 | - [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r")) | ||
| 987 | + [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um") | ||
| 988 | (unspec:<V_two_elem> | ||
| 989 | [(match_operand:OI 1 "s_register_operand" "w") | ||
| 990 | (match_operand:SI 2 "immediate_operand" "i") | ||
| 991 | @@ -4895,7 +4893,7 @@ | ||
| 992 | ops[1] = gen_rtx_REG (DImode, regno); | ||
| 993 | ops[2] = gen_rtx_REG (DImode, regno + 4); | ||
| 994 | ops[3] = GEN_INT (lane); | ||
| 995 | - output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops); | ||
| 996 | + output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops); | ||
| 997 | return ""; | ||
| 998 | } | ||
| 999 | [(set_attr "neon_type" "neon_vst1_vst2_lane")] | ||
| 1000 | @@ -4903,15 +4901,15 @@ | ||
| 1001 | |||
| 1002 | (define_insn "neon_vld3<mode>" | ||
| 1003 | [(set (match_operand:EI 0 "s_register_operand" "=w") | ||
| 1004 | - (unspec:EI [(mem:EI (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1005 | + (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um") | ||
| 1006 | (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1007 | UNSPEC_VLD3))] | ||
| 1008 | "TARGET_NEON" | ||
| 1009 | { | ||
| 1010 | if (<V_sz_elem> == 64) | ||
| 1011 | - return "vld1.64\t%h0, [%1]"; | ||
| 1012 | + return "vld1.64\t%h0, %A1"; | ||
| 1013 | else | ||
| 1014 | - return "vld3.<V_sz_elem>\t%h0, [%1]"; | ||
| 1015 | + return "vld3.<V_sz_elem>\t%h0, %A1"; | ||
| 1016 | } | ||
| 1017 | [(set (attr "neon_type") | ||
| 1018 | (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) | ||
| 1019 | @@ -4920,27 +4918,25 @@ | ||
| 1020 | ) | ||
| 1021 | |||
| 1022 | (define_expand "neon_vld3<mode>" | ||
| 1023 | - [(match_operand:CI 0 "s_register_operand" "=w") | ||
| 1024 | - (match_operand:SI 1 "s_register_operand" "+r") | ||
| 1025 | + [(match_operand:CI 0 "s_register_operand") | ||
| 1026 | + (match_operand:CI 1 "neon_struct_operand") | ||
| 1027 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1028 | "TARGET_NEON" | ||
| 1029 | { | ||
| 1030 | - emit_insn (gen_neon_vld3qa<mode> (operands[0], operands[0], | ||
| 1031 | - operands[1], operands[1])); | ||
| 1032 | - emit_insn (gen_neon_vld3qb<mode> (operands[0], operands[0], | ||
| 1033 | - operands[1], operands[1])); | ||
| 1034 | + rtx mem; | ||
| 1035 | + | ||
| 1036 | + mem = adjust_address (operands[1], EImode, 0); | ||
| 1037 | + emit_insn (gen_neon_vld3qa<mode> (operands[0], mem)); | ||
| 1038 | + mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode)); | ||
| 1039 | + emit_insn (gen_neon_vld3qb<mode> (operands[0], mem, operands[0])); | ||
| 1040 | DONE; | ||
| 1041 | }) | ||
| 1042 | |||
| 1043 | (define_insn "neon_vld3qa<mode>" | ||
| 1044 | [(set (match_operand:CI 0 "s_register_operand" "=w") | ||
| 1045 | - (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2")) | ||
| 1046 | - (match_operand:CI 1 "s_register_operand" "0") | ||
| 1047 | + (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um") | ||
| 1048 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1049 | - UNSPEC_VLD3A)) | ||
| 1050 | - (set (match_operand:SI 2 "s_register_operand" "=r") | ||
| 1051 | - (plus:SI (match_dup 3) | ||
| 1052 | - (const_int 24)))] | ||
| 1053 | + UNSPEC_VLD3A))] | ||
| 1054 | "TARGET_NEON" | ||
| 1055 | { | ||
| 1056 | int regno = REGNO (operands[0]); | ||
| 1057 | @@ -4948,8 +4944,8 @@ | ||
| 1058 | ops[0] = gen_rtx_REG (DImode, regno); | ||
| 1059 | ops[1] = gen_rtx_REG (DImode, regno + 4); | ||
| 1060 | ops[2] = gen_rtx_REG (DImode, regno + 8); | ||
| 1061 | - ops[3] = operands[2]; | ||
| 1062 | - output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops); | ||
| 1063 | + ops[3] = operands[1]; | ||
| 1064 | + output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops); | ||
| 1065 | return ""; | ||
| 1066 | } | ||
| 1067 | [(set_attr "neon_type" "neon_vld3_vld4")] | ||
| 1068 | @@ -4957,13 +4953,10 @@ | ||
| 1069 | |||
| 1070 | (define_insn "neon_vld3qb<mode>" | ||
| 1071 | [(set (match_operand:CI 0 "s_register_operand" "=w") | ||
| 1072 | - (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2")) | ||
| 1073 | - (match_operand:CI 1 "s_register_operand" "0") | ||
| 1074 | + (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um") | ||
| 1075 | + (match_operand:CI 2 "s_register_operand" "0") | ||
| 1076 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1077 | - UNSPEC_VLD3B)) | ||
| 1078 | - (set (match_operand:SI 2 "s_register_operand" "=r") | ||
| 1079 | - (plus:SI (match_dup 3) | ||
| 1080 | - (const_int 24)))] | ||
| 1081 | + UNSPEC_VLD3B))] | ||
| 1082 | "TARGET_NEON" | ||
| 1083 | { | ||
| 1084 | int regno = REGNO (operands[0]); | ||
| 1085 | @@ -4971,8 +4964,8 @@ | ||
| 1086 | ops[0] = gen_rtx_REG (DImode, regno + 2); | ||
| 1087 | ops[1] = gen_rtx_REG (DImode, regno + 6); | ||
| 1088 | ops[2] = gen_rtx_REG (DImode, regno + 10); | ||
| 1089 | - ops[3] = operands[2]; | ||
| 1090 | - output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops); | ||
| 1091 | + ops[3] = operands[1]; | ||
| 1092 | + output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops); | ||
| 1093 | return ""; | ||
| 1094 | } | ||
| 1095 | [(set_attr "neon_type" "neon_vld3_vld4")] | ||
| 1096 | @@ -4980,7 +4973,7 @@ | ||
| 1097 | |||
| 1098 | (define_insn "neon_vld3_lane<mode>" | ||
| 1099 | [(set (match_operand:EI 0 "s_register_operand" "=w") | ||
| 1100 | - (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1101 | + (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um") | ||
| 1102 | (match_operand:EI 2 "s_register_operand" "0") | ||
| 1103 | (match_operand:SI 3 "immediate_operand" "i") | ||
| 1104 | (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1105 | @@ -4998,7 +4991,7 @@ | ||
| 1106 | ops[2] = gen_rtx_REG (DImode, regno + 4); | ||
| 1107 | ops[3] = operands[1]; | ||
| 1108 | ops[4] = operands[3]; | ||
| 1109 | - output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]", | ||
| 1110 | + output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3", | ||
| 1111 | ops); | ||
| 1112 | return ""; | ||
| 1113 | } | ||
| 1114 | @@ -5007,7 +5000,7 @@ | ||
| 1115 | |||
| 1116 | (define_insn "neon_vld3_lane<mode>" | ||
| 1117 | [(set (match_operand:CI 0 "s_register_operand" "=w") | ||
| 1118 | - (unspec:CI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1119 | + (unspec:CI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um") | ||
| 1120 | (match_operand:CI 2 "s_register_operand" "0") | ||
| 1121 | (match_operand:SI 3 "immediate_operand" "i") | ||
| 1122 | (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1123 | @@ -5030,7 +5023,7 @@ | ||
| 1124 | ops[2] = gen_rtx_REG (DImode, regno + 8); | ||
| 1125 | ops[3] = operands[1]; | ||
| 1126 | ops[4] = GEN_INT (lane); | ||
| 1127 | - output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]", | ||
| 1128 | + output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3", | ||
| 1129 | ops); | ||
| 1130 | return ""; | ||
| 1131 | } | ||
| 1132 | @@ -5039,7 +5032,7 @@ | ||
| 1133 | |||
| 1134 | (define_insn "neon_vld3_dup<mode>" | ||
| 1135 | [(set (match_operand:EI 0 "s_register_operand" "=w") | ||
| 1136 | - (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1137 | + (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um") | ||
| 1138 | (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1139 | UNSPEC_VLD3_DUP))] | ||
| 1140 | "TARGET_NEON" | ||
| 1141 | @@ -5052,11 +5045,11 @@ | ||
| 1142 | ops[1] = gen_rtx_REG (DImode, regno + 2); | ||
| 1143 | ops[2] = gen_rtx_REG (DImode, regno + 4); | ||
| 1144 | ops[3] = operands[1]; | ||
| 1145 | - output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, [%3]", ops); | ||
| 1146 | + output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, %A3", ops); | ||
| 1147 | return ""; | ||
| 1148 | } | ||
| 1149 | else | ||
| 1150 | - return "vld1.<V_sz_elem>\t%h0, [%1]"; | ||
| 1151 | + return "vld1.<V_sz_elem>\t%h0, %A1"; | ||
| 1152 | } | ||
| 1153 | [(set (attr "neon_type") | ||
| 1154 | (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) | ||
| 1155 | @@ -5064,16 +5057,16 @@ | ||
| 1156 | (const_string "neon_vld1_1_2_regs")))]) | ||
| 1157 | |||
| 1158 | (define_insn "neon_vst3<mode>" | ||
| 1159 | - [(set (mem:EI (match_operand:SI 0 "s_register_operand" "r")) | ||
| 1160 | + [(set (match_operand:EI 0 "neon_struct_operand" "=Um") | ||
| 1161 | (unspec:EI [(match_operand:EI 1 "s_register_operand" "w") | ||
| 1162 | (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1163 | UNSPEC_VST3))] | ||
| 1164 | "TARGET_NEON" | ||
| 1165 | { | ||
| 1166 | if (<V_sz_elem> == 64) | ||
| 1167 | - return "vst1.64\t%h1, [%0]"; | ||
| 1168 | + return "vst1.64\t%h1, %A0"; | ||
| 1169 | else | ||
| 1170 | - return "vst3.<V_sz_elem>\t%h1, [%0]"; | ||
| 1171 | + return "vst3.<V_sz_elem>\t%h1, %A0"; | ||
| 1172 | } | ||
| 1173 | [(set (attr "neon_type") | ||
| 1174 | (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) | ||
| 1175 | @@ -5081,62 +5074,60 @@ | ||
| 1176 | (const_string "neon_vst2_4_regs_vst3_vst4")))]) | ||
| 1177 | |||
| 1178 | (define_expand "neon_vst3<mode>" | ||
| 1179 | - [(match_operand:SI 0 "s_register_operand" "+r") | ||
| 1180 | - (match_operand:CI 1 "s_register_operand" "w") | ||
| 1181 | + [(match_operand:CI 0 "neon_struct_operand") | ||
| 1182 | + (match_operand:CI 1 "s_register_operand") | ||
| 1183 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1184 | "TARGET_NEON" | ||
| 1185 | { | ||
| 1186 | - emit_insn (gen_neon_vst3qa<mode> (operands[0], operands[0], operands[1])); | ||
| 1187 | - emit_insn (gen_neon_vst3qb<mode> (operands[0], operands[0], operands[1])); | ||
| 1188 | + rtx mem; | ||
| 1189 | + | ||
| 1190 | + mem = adjust_address (operands[0], EImode, 0); | ||
| 1191 | + emit_insn (gen_neon_vst3qa<mode> (mem, operands[1])); | ||
| 1192 | + mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode)); | ||
| 1193 | + emit_insn (gen_neon_vst3qb<mode> (mem, operands[1])); | ||
| 1194 | DONE; | ||
| 1195 | }) | ||
| 1196 | |||
| 1197 | (define_insn "neon_vst3qa<mode>" | ||
| 1198 | - [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0")) | ||
| 1199 | - (unspec:EI [(match_operand:CI 2 "s_register_operand" "w") | ||
| 1200 | + [(set (match_operand:EI 0 "neon_struct_operand" "=Um") | ||
| 1201 | + (unspec:EI [(match_operand:CI 1 "s_register_operand" "w") | ||
| 1202 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1203 | - UNSPEC_VST3A)) | ||
| 1204 | - (set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 1205 | - (plus:SI (match_dup 1) | ||
| 1206 | - (const_int 24)))] | ||
| 1207 | + UNSPEC_VST3A))] | ||
| 1208 | "TARGET_NEON" | ||
| 1209 | { | ||
| 1210 | - int regno = REGNO (operands[2]); | ||
| 1211 | + int regno = REGNO (operands[1]); | ||
| 1212 | rtx ops[4]; | ||
| 1213 | ops[0] = operands[0]; | ||
| 1214 | ops[1] = gen_rtx_REG (DImode, regno); | ||
| 1215 | ops[2] = gen_rtx_REG (DImode, regno + 4); | ||
| 1216 | ops[3] = gen_rtx_REG (DImode, regno + 8); | ||
| 1217 | - output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops); | ||
| 1218 | + output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops); | ||
| 1219 | return ""; | ||
| 1220 | } | ||
| 1221 | [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] | ||
| 1222 | ) | ||
| 1223 | |||
| 1224 | (define_insn "neon_vst3qb<mode>" | ||
| 1225 | - [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0")) | ||
| 1226 | - (unspec:EI [(match_operand:CI 2 "s_register_operand" "w") | ||
| 1227 | + [(set (match_operand:EI 0 "neon_struct_operand" "=Um") | ||
| 1228 | + (unspec:EI [(match_operand:CI 1 "s_register_operand" "w") | ||
| 1229 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1230 | - UNSPEC_VST3B)) | ||
| 1231 | - (set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 1232 | - (plus:SI (match_dup 1) | ||
| 1233 | - (const_int 24)))] | ||
| 1234 | + UNSPEC_VST3B))] | ||
| 1235 | "TARGET_NEON" | ||
| 1236 | { | ||
| 1237 | - int regno = REGNO (operands[2]); | ||
| 1238 | + int regno = REGNO (operands[1]); | ||
| 1239 | rtx ops[4]; | ||
| 1240 | ops[0] = operands[0]; | ||
| 1241 | ops[1] = gen_rtx_REG (DImode, regno + 2); | ||
| 1242 | ops[2] = gen_rtx_REG (DImode, regno + 6); | ||
| 1243 | ops[3] = gen_rtx_REG (DImode, regno + 10); | ||
| 1244 | - output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops); | ||
| 1245 | + output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops); | ||
| 1246 | return ""; | ||
| 1247 | } | ||
| 1248 | [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] | ||
| 1249 | ) | ||
| 1250 | |||
| 1251 | (define_insn "neon_vst3_lane<mode>" | ||
| 1252 | - [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r")) | ||
| 1253 | + [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um") | ||
| 1254 | (unspec:<V_three_elem> | ||
| 1255 | [(match_operand:EI 1 "s_register_operand" "w") | ||
| 1256 | (match_operand:SI 2 "immediate_operand" "i") | ||
| 1257 | @@ -5155,7 +5146,7 @@ | ||
| 1258 | ops[2] = gen_rtx_REG (DImode, regno + 2); | ||
| 1259 | ops[3] = gen_rtx_REG (DImode, regno + 4); | ||
| 1260 | ops[4] = operands[2]; | ||
| 1261 | - output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]", | ||
| 1262 | + output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0", | ||
| 1263 | ops); | ||
| 1264 | return ""; | ||
| 1265 | } | ||
| 1266 | @@ -5163,7 +5154,7 @@ | ||
| 1267 | ) | ||
| 1268 | |||
| 1269 | (define_insn "neon_vst3_lane<mode>" | ||
| 1270 | - [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r")) | ||
| 1271 | + [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um") | ||
| 1272 | (unspec:<V_three_elem> | ||
| 1273 | [(match_operand:CI 1 "s_register_operand" "w") | ||
| 1274 | (match_operand:SI 2 "immediate_operand" "i") | ||
| 1275 | @@ -5187,7 +5178,7 @@ | ||
| 1276 | ops[2] = gen_rtx_REG (DImode, regno + 4); | ||
| 1277 | ops[3] = gen_rtx_REG (DImode, regno + 8); | ||
| 1278 | ops[4] = GEN_INT (lane); | ||
| 1279 | - output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]", | ||
| 1280 | + output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0", | ||
| 1281 | ops); | ||
| 1282 | return ""; | ||
| 1283 | } | ||
| 1284 | @@ -5195,15 +5186,15 @@ | ||
| 1285 | |||
| 1286 | (define_insn "neon_vld4<mode>" | ||
| 1287 | [(set (match_operand:OI 0 "s_register_operand" "=w") | ||
| 1288 | - (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1289 | + (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") | ||
| 1290 | (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1291 | UNSPEC_VLD4))] | ||
| 1292 | "TARGET_NEON" | ||
| 1293 | { | ||
| 1294 | if (<V_sz_elem> == 64) | ||
| 1295 | - return "vld1.64\t%h0, [%1]"; | ||
| 1296 | + return "vld1.64\t%h0, %A1"; | ||
| 1297 | else | ||
| 1298 | - return "vld4.<V_sz_elem>\t%h0, [%1]"; | ||
| 1299 | + return "vld4.<V_sz_elem>\t%h0, %A1"; | ||
| 1300 | } | ||
| 1301 | [(set (attr "neon_type") | ||
| 1302 | (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) | ||
| 1303 | @@ -5212,27 +5203,25 @@ | ||
| 1304 | ) | ||
| 1305 | |||
| 1306 | (define_expand "neon_vld4<mode>" | ||
| 1307 | - [(match_operand:XI 0 "s_register_operand" "=w") | ||
| 1308 | - (match_operand:SI 1 "s_register_operand" "+r") | ||
| 1309 | + [(match_operand:XI 0 "s_register_operand") | ||
| 1310 | + (match_operand:XI 1 "neon_struct_operand") | ||
| 1311 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1312 | "TARGET_NEON" | ||
| 1313 | { | ||
| 1314 | - emit_insn (gen_neon_vld4qa<mode> (operands[0], operands[0], | ||
| 1315 | - operands[1], operands[1])); | ||
| 1316 | - emit_insn (gen_neon_vld4qb<mode> (operands[0], operands[0], | ||
| 1317 | - operands[1], operands[1])); | ||
| 1318 | + rtx mem; | ||
| 1319 | + | ||
| 1320 | + mem = adjust_address (operands[1], OImode, 0); | ||
| 1321 | + emit_insn (gen_neon_vld4qa<mode> (operands[0], mem)); | ||
| 1322 | + mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode)); | ||
| 1323 | + emit_insn (gen_neon_vld4qb<mode> (operands[0], mem, operands[0])); | ||
| 1324 | DONE; | ||
| 1325 | }) | ||
| 1326 | |||
| 1327 | (define_insn "neon_vld4qa<mode>" | ||
| 1328 | [(set (match_operand:XI 0 "s_register_operand" "=w") | ||
| 1329 | - (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2")) | ||
| 1330 | - (match_operand:XI 1 "s_register_operand" "0") | ||
| 1331 | + (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um") | ||
| 1332 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1333 | - UNSPEC_VLD4A)) | ||
| 1334 | - (set (match_operand:SI 2 "s_register_operand" "=r") | ||
| 1335 | - (plus:SI (match_dup 3) | ||
| 1336 | - (const_int 32)))] | ||
| 1337 | + UNSPEC_VLD4A))] | ||
| 1338 | "TARGET_NEON" | ||
| 1339 | { | ||
| 1340 | int regno = REGNO (operands[0]); | ||
| 1341 | @@ -5241,8 +5230,8 @@ | ||
| 1342 | ops[1] = gen_rtx_REG (DImode, regno + 4); | ||
| 1343 | ops[2] = gen_rtx_REG (DImode, regno + 8); | ||
| 1344 | ops[3] = gen_rtx_REG (DImode, regno + 12); | ||
| 1345 | - ops[4] = operands[2]; | ||
| 1346 | - output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops); | ||
| 1347 | + ops[4] = operands[1]; | ||
| 1348 | + output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops); | ||
| 1349 | return ""; | ||
| 1350 | } | ||
| 1351 | [(set_attr "neon_type" "neon_vld3_vld4")] | ||
| 1352 | @@ -5250,13 +5239,10 @@ | ||
| 1353 | |||
| 1354 | (define_insn "neon_vld4qb<mode>" | ||
| 1355 | [(set (match_operand:XI 0 "s_register_operand" "=w") | ||
| 1356 | - (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2")) | ||
| 1357 | - (match_operand:XI 1 "s_register_operand" "0") | ||
| 1358 | + (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um") | ||
| 1359 | + (match_operand:XI 2 "s_register_operand" "0") | ||
| 1360 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1361 | - UNSPEC_VLD4B)) | ||
| 1362 | - (set (match_operand:SI 2 "s_register_operand" "=r") | ||
| 1363 | - (plus:SI (match_dup 3) | ||
| 1364 | - (const_int 32)))] | ||
| 1365 | + UNSPEC_VLD4B))] | ||
| 1366 | "TARGET_NEON" | ||
| 1367 | { | ||
| 1368 | int regno = REGNO (operands[0]); | ||
| 1369 | @@ -5265,8 +5251,8 @@ | ||
| 1370 | ops[1] = gen_rtx_REG (DImode, regno + 6); | ||
| 1371 | ops[2] = gen_rtx_REG (DImode, regno + 10); | ||
| 1372 | ops[3] = gen_rtx_REG (DImode, regno + 14); | ||
| 1373 | - ops[4] = operands[2]; | ||
| 1374 | - output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops); | ||
| 1375 | + ops[4] = operands[1]; | ||
| 1376 | + output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops); | ||
| 1377 | return ""; | ||
| 1378 | } | ||
| 1379 | [(set_attr "neon_type" "neon_vld3_vld4")] | ||
| 1380 | @@ -5274,7 +5260,7 @@ | ||
| 1381 | |||
| 1382 | (define_insn "neon_vld4_lane<mode>" | ||
| 1383 | [(set (match_operand:OI 0 "s_register_operand" "=w") | ||
| 1384 | - (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1385 | + (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um") | ||
| 1386 | (match_operand:OI 2 "s_register_operand" "0") | ||
| 1387 | (match_operand:SI 3 "immediate_operand" "i") | ||
| 1388 | (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1389 | @@ -5293,7 +5279,7 @@ | ||
| 1390 | ops[3] = gen_rtx_REG (DImode, regno + 6); | ||
| 1391 | ops[4] = operands[1]; | ||
| 1392 | ops[5] = operands[3]; | ||
| 1393 | - output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]", | ||
| 1394 | + output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4", | ||
| 1395 | ops); | ||
| 1396 | return ""; | ||
| 1397 | } | ||
| 1398 | @@ -5302,7 +5288,7 @@ | ||
| 1399 | |||
| 1400 | (define_insn "neon_vld4_lane<mode>" | ||
| 1401 | [(set (match_operand:XI 0 "s_register_operand" "=w") | ||
| 1402 | - (unspec:XI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1403 | + (unspec:XI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um") | ||
| 1404 | (match_operand:XI 2 "s_register_operand" "0") | ||
| 1405 | (match_operand:SI 3 "immediate_operand" "i") | ||
| 1406 | (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1407 | @@ -5326,7 +5312,7 @@ | ||
| 1408 | ops[3] = gen_rtx_REG (DImode, regno + 12); | ||
| 1409 | ops[4] = operands[1]; | ||
| 1410 | ops[5] = GEN_INT (lane); | ||
| 1411 | - output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]", | ||
| 1412 | + output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4", | ||
| 1413 | ops); | ||
| 1414 | return ""; | ||
| 1415 | } | ||
| 1416 | @@ -5335,7 +5321,7 @@ | ||
| 1417 | |||
| 1418 | (define_insn "neon_vld4_dup<mode>" | ||
| 1419 | [(set (match_operand:OI 0 "s_register_operand" "=w") | ||
| 1420 | - (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r")) | ||
| 1421 | + (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um") | ||
| 1422 | (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1423 | UNSPEC_VLD4_DUP))] | ||
| 1424 | "TARGET_NEON" | ||
| 1425 | @@ -5349,12 +5335,12 @@ | ||
| 1426 | ops[2] = gen_rtx_REG (DImode, regno + 4); | ||
| 1427 | ops[3] = gen_rtx_REG (DImode, regno + 6); | ||
| 1428 | ops[4] = operands[1]; | ||
| 1429 | - output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, [%4]", | ||
| 1430 | + output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, %A4", | ||
| 1431 | ops); | ||
| 1432 | return ""; | ||
| 1433 | } | ||
| 1434 | else | ||
| 1435 | - return "vld1.<V_sz_elem>\t%h0, [%1]"; | ||
| 1436 | + return "vld1.<V_sz_elem>\t%h0, %A1"; | ||
| 1437 | } | ||
| 1438 | [(set (attr "neon_type") | ||
| 1439 | (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) | ||
| 1440 | @@ -5363,16 +5349,16 @@ | ||
| 1441 | ) | ||
| 1442 | |||
| 1443 | (define_insn "neon_vst4<mode>" | ||
| 1444 | - [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r")) | ||
| 1445 | + [(set (match_operand:OI 0 "neon_struct_operand" "=Um") | ||
| 1446 | (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") | ||
| 1447 | (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1448 | UNSPEC_VST4))] | ||
| 1449 | "TARGET_NEON" | ||
| 1450 | { | ||
| 1451 | if (<V_sz_elem> == 64) | ||
| 1452 | - return "vst1.64\t%h1, [%0]"; | ||
| 1453 | + return "vst1.64\t%h1, %A0"; | ||
| 1454 | else | ||
| 1455 | - return "vst4.<V_sz_elem>\t%h1, [%0]"; | ||
| 1456 | + return "vst4.<V_sz_elem>\t%h1, %A0"; | ||
| 1457 | } | ||
| 1458 | [(set (attr "neon_type") | ||
| 1459 | (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) | ||
| 1460 | @@ -5381,64 +5367,62 @@ | ||
| 1461 | ) | ||
| 1462 | |||
| 1463 | (define_expand "neon_vst4<mode>" | ||
| 1464 | - [(match_operand:SI 0 "s_register_operand" "+r") | ||
| 1465 | - (match_operand:XI 1 "s_register_operand" "w") | ||
| 1466 | + [(match_operand:XI 0 "neon_struct_operand") | ||
| 1467 | + (match_operand:XI 1 "s_register_operand") | ||
| 1468 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1469 | "TARGET_NEON" | ||
| 1470 | { | ||
| 1471 | - emit_insn (gen_neon_vst4qa<mode> (operands[0], operands[0], operands[1])); | ||
| 1472 | - emit_insn (gen_neon_vst4qb<mode> (operands[0], operands[0], operands[1])); | ||
| 1473 | + rtx mem; | ||
| 1474 | + | ||
| 1475 | + mem = adjust_address (operands[0], OImode, 0); | ||
| 1476 | + emit_insn (gen_neon_vst4qa<mode> (mem, operands[1])); | ||
| 1477 | + mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode)); | ||
| 1478 | + emit_insn (gen_neon_vst4qb<mode> (mem, operands[1])); | ||
| 1479 | DONE; | ||
| 1480 | }) | ||
| 1481 | |||
| 1482 | (define_insn "neon_vst4qa<mode>" | ||
| 1483 | - [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0")) | ||
| 1484 | - (unspec:OI [(match_operand:XI 2 "s_register_operand" "w") | ||
| 1485 | + [(set (match_operand:OI 0 "neon_struct_operand" "=Um") | ||
| 1486 | + (unspec:OI [(match_operand:XI 1 "s_register_operand" "w") | ||
| 1487 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1488 | - UNSPEC_VST4A)) | ||
| 1489 | - (set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 1490 | - (plus:SI (match_dup 1) | ||
| 1491 | - (const_int 32)))] | ||
| 1492 | + UNSPEC_VST4A))] | ||
| 1493 | "TARGET_NEON" | ||
| 1494 | { | ||
| 1495 | - int regno = REGNO (operands[2]); | ||
| 1496 | + int regno = REGNO (operands[1]); | ||
| 1497 | rtx ops[5]; | ||
| 1498 | ops[0] = operands[0]; | ||
| 1499 | ops[1] = gen_rtx_REG (DImode, regno); | ||
| 1500 | ops[2] = gen_rtx_REG (DImode, regno + 4); | ||
| 1501 | ops[3] = gen_rtx_REG (DImode, regno + 8); | ||
| 1502 | ops[4] = gen_rtx_REG (DImode, regno + 12); | ||
| 1503 | - output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops); | ||
| 1504 | + output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops); | ||
| 1505 | return ""; | ||
| 1506 | } | ||
| 1507 | [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] | ||
| 1508 | ) | ||
| 1509 | |||
| 1510 | (define_insn "neon_vst4qb<mode>" | ||
| 1511 | - [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0")) | ||
| 1512 | - (unspec:OI [(match_operand:XI 2 "s_register_operand" "w") | ||
| 1513 | + [(set (match_operand:OI 0 "neon_struct_operand" "=Um") | ||
| 1514 | + (unspec:OI [(match_operand:XI 1 "s_register_operand" "w") | ||
| 1515 | (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] | ||
| 1516 | - UNSPEC_VST4B)) | ||
| 1517 | - (set (match_operand:SI 0 "s_register_operand" "=r") | ||
| 1518 | - (plus:SI (match_dup 1) | ||
| 1519 | - (const_int 32)))] | ||
| 1520 | + UNSPEC_VST4B))] | ||
| 1521 | "TARGET_NEON" | ||
| 1522 | { | ||
| 1523 | - int regno = REGNO (operands[2]); | ||
| 1524 | + int regno = REGNO (operands[1]); | ||
| 1525 | rtx ops[5]; | ||
| 1526 | ops[0] = operands[0]; | ||
| 1527 | ops[1] = gen_rtx_REG (DImode, regno + 2); | ||
| 1528 | ops[2] = gen_rtx_REG (DImode, regno + 6); | ||
| 1529 | ops[3] = gen_rtx_REG (DImode, regno + 10); | ||
| 1530 | ops[4] = gen_rtx_REG (DImode, regno + 14); | ||
| 1531 | - output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops); | ||
| 1532 | + output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops); | ||
| 1533 | return ""; | ||
| 1534 | } | ||
| 1535 | [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")] | ||
| 1536 | ) | ||
| 1537 | |||
| 1538 | (define_insn "neon_vst4_lane<mode>" | ||
| 1539 | - [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r")) | ||
| 1540 | + [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um") | ||
| 1541 | (unspec:<V_four_elem> | ||
| 1542 | [(match_operand:OI 1 "s_register_operand" "w") | ||
| 1543 | (match_operand:SI 2 "immediate_operand" "i") | ||
| 1544 | @@ -5458,7 +5442,7 @@ | ||
| 1545 | ops[3] = gen_rtx_REG (DImode, regno + 4); | ||
| 1546 | ops[4] = gen_rtx_REG (DImode, regno + 6); | ||
| 1547 | ops[5] = operands[2]; | ||
| 1548 | - output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]", | ||
| 1549 | + output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0", | ||
| 1550 | ops); | ||
| 1551 | return ""; | ||
| 1552 | } | ||
| 1553 | @@ -5466,7 +5450,7 @@ | ||
| 1554 | ) | ||
| 1555 | |||
| 1556 | (define_insn "neon_vst4_lane<mode>" | ||
| 1557 | - [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r")) | ||
| 1558 | + [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um") | ||
| 1559 | (unspec:<V_four_elem> | ||
| 1560 | [(match_operand:XI 1 "s_register_operand" "w") | ||
| 1561 | (match_operand:SI 2 "immediate_operand" "i") | ||
| 1562 | @@ -5491,7 +5475,7 @@ | ||
| 1563 | ops[3] = gen_rtx_REG (DImode, regno + 8); | ||
| 1564 | ops[4] = gen_rtx_REG (DImode, regno + 12); | ||
| 1565 | ops[5] = GEN_INT (lane); | ||
| 1566 | - output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]", | ||
| 1567 | + output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0", | ||
| 1568 | ops); | ||
| 1569 | return ""; | ||
| 1570 | } | ||
| 1571 | |||
| 1572 | === modified file 'gcc/config/arm/predicates.md' | ||
| 1573 | --- old/gcc/config/arm/predicates.md 2011-04-06 12:29:08 +0000 | ||
| 1574 | +++ new/gcc/config/arm/predicates.md 2011-04-20 10:00:39 +0000 | ||
| 1575 | @@ -681,3 +681,7 @@ | ||
| 1576 | } | ||
| 1577 | return true; | ||
| 1578 | }) | ||
| 1579 | + | ||
| 1580 | +(define_special_predicate "neon_struct_operand" | ||
| 1581 | + (and (match_code "mem") | ||
| 1582 | + (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)"))) | ||
| 1583 | |||
| 1584 | === modified file 'gcc/doc/tm.texi' | ||
| 1585 | --- old/gcc/doc/tm.texi 2011-02-08 10:51:58 +0000 | ||
| 1586 | +++ new/gcc/doc/tm.texi 2011-04-20 10:07:36 +0000 | ||
| 1587 | @@ -2642,8 +2642,8 @@ | ||
| 1588 | register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when | ||
| 1589 | @var{x} is a floating-point constant. If the constant can't be loaded | ||
| 1590 | into any kind of register, code generation will be better if | ||
| 1591 | -@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead | ||
| 1592 | -of using @code{PREFERRED_RELOAD_CLASS}. | ||
| 1593 | +@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead | ||
| 1594 | +of using @code{TARGET_PREFERRED_RELOAD_CLASS}. | ||
| 1595 | |||
| 1596 | If an insn has pseudos in it after register allocation, reload will go | ||
| 1597 | through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS} | ||
| 1598 | @@ -4367,6 +4367,34 @@ | ||
| 1599 | must have move patterns for this mode. | ||
| 1600 | @end deftypefn | ||
| 1601 | |||
| 1602 | +@deftypefn {Target Hook} bool TARGET_ARRAY_MODE_SUPPORTED_P (enum machine_mode @var{mode}, unsigned HOST_WIDE_INT @var{nelems}) | ||
| 1603 | +Return true if GCC should try to use a scalar mode to store an array | ||
| 1604 | +of @var{nelems} elements, given that each element has mode @var{mode}. | ||
| 1605 | +Returning true here overrides the usual @code{MAX_FIXED_MODE} limit | ||
| 1606 | +and allows GCC to use any defined integer mode. | ||
| 1607 | + | ||
| 1608 | +One use of this hook is to support vector load and store operations | ||
| 1609 | +that operate on several homogeneous vectors. For example, ARM Neon | ||
| 1610 | +has operations like: | ||
| 1611 | + | ||
| 1612 | +@smallexample | ||
| 1613 | +int8x8x3_t vld3_s8 (const int8_t *) | ||
| 1614 | +@end smallexample | ||
| 1615 | + | ||
| 1616 | +where the return type is defined as: | ||
| 1617 | + | ||
| 1618 | +@smallexample | ||
| 1619 | +typedef struct int8x8x3_t | ||
| 1620 | +@{ | ||
| 1621 | + int8x8_t val[3]; | ||
| 1622 | +@} int8x8x3_t; | ||
| 1623 | +@end smallexample | ||
| 1624 | + | ||
| 1625 | +If this hook allows @code{val} to have a scalar mode, then | ||
| 1626 | +@code{int8x8x3_t} can have the same mode. GCC can then store | ||
| 1627 | +@code{int8x8x3_t}s in registers rather than forcing them onto the stack. | ||
| 1628 | +@end deftypefn | ||
| 1629 | + | ||
| 1630 | @node Scalar Return | ||
| 1631 | @subsection How Scalar Function Values Are Returned | ||
| 1632 | @cindex return values in registers | ||
| 1633 | @@ -5600,13 +5628,13 @@ | ||
| 1634 | You may assume that @var{addr} is a valid address for the machine. | ||
| 1635 | @end defmac | ||
| 1636 | |||
| 1637 | -@defmac LEGITIMATE_CONSTANT_P (@var{x}) | ||
| 1638 | -A C expression that is nonzero if @var{x} is a legitimate constant for | ||
| 1639 | -an immediate operand on the target machine. You can assume that | ||
| 1640 | -@var{x} satisfies @code{CONSTANT_P}, so you need not check this. In fact, | ||
| 1641 | -@samp{1} is a suitable definition for this macro on machines where | ||
| 1642 | -anything @code{CONSTANT_P} is valid. | ||
| 1643 | -@end defmac | ||
| 1644 | +@deftypefn {Target Hook} bool TARGET_LEGITIMATE_CONSTANT_P (enum machine_mode @var{mode}, rtx @var{x}) | ||
| 1645 | +This hook returns true if @var{x} is a legitimate constant for a | ||
| 1646 | +@var{mode}-mode immediate operand on the target machine. You can assume that | ||
| 1647 | +@var{x} satisfies @code{CONSTANT_P}, so you need not check this. | ||
| 1648 | + | ||
| 1649 | +The default definition returns true. | ||
| 1650 | +@end deftypefn | ||
| 1651 | |||
| 1652 | @deftypefn {Target Hook} rtx TARGET_DELEGITIMIZE_ADDRESS (rtx @var{x}) | ||
| 1653 | This hook is used to undo the possibly obfuscating effects of the | ||
| 1654 | |||
| 1655 | === modified file 'gcc/expr.c' | ||
| 1656 | --- old/gcc/expr.c 2011-03-23 12:22:13 +0000 | ||
| 1657 | +++ new/gcc/expr.c 2011-04-20 10:07:36 +0000 | ||
| 1658 | @@ -1537,7 +1537,7 @@ | ||
| 1659 | if (nregs == 0) | ||
| 1660 | return; | ||
| 1661 | |||
| 1662 | - if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x)) | ||
| 1663 | + if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x)) | ||
| 1664 | x = validize_mem (force_const_mem (mode, x)); | ||
| 1665 | |||
| 1666 | /* See if the machine can do this with a load multiple insn. */ | ||
| 1667 | @@ -2366,7 +2366,7 @@ | ||
| 1668 | offset -= size; | ||
| 1669 | |||
| 1670 | cst = (*constfun) (constfundata, offset, mode); | ||
| 1671 | - if (!LEGITIMATE_CONSTANT_P (cst)) | ||
| 1672 | + if (!targetm.legitimate_constant_p (mode, cst)) | ||
| 1673 | return 0; | ||
| 1674 | |||
| 1675 | if (!reverse) | ||
| 1676 | @@ -3440,7 +3440,7 @@ | ||
| 1677 | |||
| 1678 | y_cst = y; | ||
| 1679 | |||
| 1680 | - if (!LEGITIMATE_CONSTANT_P (y)) | ||
| 1681 | + if (!targetm.legitimate_constant_p (mode, y)) | ||
| 1682 | { | ||
| 1683 | y = force_const_mem (mode, y); | ||
| 1684 | |||
| 1685 | @@ -3496,7 +3496,7 @@ | ||
| 1686 | |||
| 1687 | REAL_VALUE_FROM_CONST_DOUBLE (r, y); | ||
| 1688 | |||
| 1689 | - if (LEGITIMATE_CONSTANT_P (y)) | ||
| 1690 | + if (targetm.legitimate_constant_p (dstmode, y)) | ||
| 1691 | oldcost = rtx_cost (y, SET, speed); | ||
| 1692 | else | ||
| 1693 | oldcost = rtx_cost (force_const_mem (dstmode, y), SET, speed); | ||
| 1694 | @@ -3519,7 +3519,7 @@ | ||
| 1695 | |||
| 1696 | trunc_y = CONST_DOUBLE_FROM_REAL_VALUE (r, srcmode); | ||
| 1697 | |||
| 1698 | - if (LEGITIMATE_CONSTANT_P (trunc_y)) | ||
| 1699 | + if (targetm.legitimate_constant_p (srcmode, trunc_y)) | ||
| 1700 | { | ||
| 1701 | /* Skip if the target needs extra instructions to perform | ||
| 1702 | the extension. */ | ||
| 1703 | @@ -3932,7 +3932,7 @@ | ||
| 1704 | by setting SKIP to 0. */ | ||
| 1705 | skip = (reg_parm_stack_space == 0) ? 0 : not_stack; | ||
| 1706 | |||
| 1707 | - if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x)) | ||
| 1708 | + if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x)) | ||
| 1709 | x = validize_mem (force_const_mem (mode, x)); | ||
| 1710 | |||
| 1711 | /* If X is a hard register in a non-integer mode, copy it into a pseudo; | ||
| 1712 | @@ -8951,7 +8951,7 @@ | ||
| 1713 | constant and we don't need a memory reference. */ | ||
| 1714 | if (CONSTANT_P (op0) | ||
| 1715 | && mode2 != BLKmode | ||
| 1716 | - && LEGITIMATE_CONSTANT_P (op0) | ||
| 1717 | + && targetm.legitimate_constant_p (mode2, op0) | ||
| 1718 | && !must_force_mem) | ||
| 1719 | op0 = force_reg (mode2, op0); | ||
| 1720 | |||
| 1721 | |||
| 1722 | === modified file 'gcc/hooks.c' | ||
| 1723 | --- old/gcc/hooks.c 2009-11-26 01:52:19 +0000 | ||
| 1724 | +++ new/gcc/hooks.c 2011-04-20 10:06:58 +0000 | ||
| 1725 | @@ -86,6 +86,15 @@ | ||
| 1726 | return true; | ||
| 1727 | } | ||
| 1728 | |||
| 1729 | +/* Generic hook that takes (enum machine_mode, unsigned HOST_WIDE_INT) | ||
| 1730 | + and returns false. */ | ||
| 1731 | +bool | ||
| 1732 | +hook_bool_mode_uhwi_false (enum machine_mode mode ATTRIBUTE_UNUSED, | ||
| 1733 | + unsigned HOST_WIDE_INT value ATTRIBUTE_UNUSED) | ||
| 1734 | +{ | ||
| 1735 | + return false; | ||
| 1736 | +} | ||
| 1737 | + | ||
| 1738 | /* Generic hook that takes (FILE *, const char *) and does nothing. */ | ||
| 1739 | void | ||
| 1740 | hook_void_FILEptr_constcharptr (FILE *a ATTRIBUTE_UNUSED, const char *b ATTRIBUTE_UNUSED) | ||
| 1741 | |||
| 1742 | === modified file 'gcc/hooks.h' | ||
| 1743 | --- old/gcc/hooks.h 2009-11-26 01:52:19 +0000 | ||
| 1744 | +++ new/gcc/hooks.h 2011-04-20 10:06:58 +0000 | ||
| 1745 | @@ -32,6 +32,8 @@ | ||
| 1746 | extern bool hook_bool_mode_false (enum machine_mode); | ||
| 1747 | extern bool hook_bool_mode_const_rtx_false (enum machine_mode, const_rtx); | ||
| 1748 | extern bool hook_bool_mode_const_rtx_true (enum machine_mode, const_rtx); | ||
| 1749 | +extern bool hook_bool_mode_uhwi_false (enum machine_mode, | ||
| 1750 | + unsigned HOST_WIDE_INT); | ||
| 1751 | extern bool hook_bool_tree_false (tree); | ||
| 1752 | extern bool hook_bool_const_tree_false (const_tree); | ||
| 1753 | extern bool hook_bool_tree_true (tree); | ||
| 1754 | |||
| 1755 | === modified file 'gcc/recog.c' | ||
| 1756 | --- old/gcc/recog.c 2011-02-08 12:07:29 +0000 | ||
| 1757 | +++ new/gcc/recog.c 2011-04-20 10:07:36 +0000 | ||
| 1758 | @@ -932,7 +932,9 @@ | ||
| 1759 | return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode | ||
| 1760 | || mode == VOIDmode) | ||
| 1761 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | ||
| 1762 | - && LEGITIMATE_CONSTANT_P (op)); | ||
| 1763 | + && targetm.legitimate_constant_p (mode == VOIDmode | ||
| 1764 | + ? GET_MODE (op) | ||
| 1765 | + : mode, op)); | ||
| 1766 | |||
| 1767 | /* Except for certain constants with VOIDmode, already checked for, | ||
| 1768 | OP's mode must match MODE if MODE specifies a mode. */ | ||
| 1769 | @@ -1109,7 +1111,9 @@ | ||
| 1770 | && (GET_MODE (op) == mode || mode == VOIDmode | ||
| 1771 | || GET_MODE (op) == VOIDmode) | ||
| 1772 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | ||
| 1773 | - && LEGITIMATE_CONSTANT_P (op)); | ||
| 1774 | + && targetm.legitimate_constant_p (mode == VOIDmode | ||
| 1775 | + ? GET_MODE (op) | ||
| 1776 | + : mode, op)); | ||
| 1777 | } | ||
| 1778 | |||
| 1779 | /* Returns 1 if OP is an operand that is a CONST_INT. */ | ||
| 1780 | @@ -1175,7 +1179,9 @@ | ||
| 1781 | return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode | ||
| 1782 | || mode == VOIDmode) | ||
| 1783 | && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) | ||
| 1784 | - && LEGITIMATE_CONSTANT_P (op)); | ||
| 1785 | + && targetm.legitimate_constant_p (mode == VOIDmode | ||
| 1786 | + ? GET_MODE (op) | ||
| 1787 | + : mode, op)); | ||
| 1788 | } | ||
| 1789 | |||
| 1790 | if (GET_MODE (op) != mode && mode != VOIDmode) | ||
| 1791 | |||
| 1792 | === modified file 'gcc/reload.c' | ||
| 1793 | --- old/gcc/reload.c 2011-02-08 12:07:29 +0000 | ||
| 1794 | +++ new/gcc/reload.c 2011-04-20 10:07:36 +0000 | ||
| 1795 | @@ -4739,7 +4739,8 @@ | ||
| 1796 | simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno], | ||
| 1797 | GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); | ||
| 1798 | gcc_assert (tem); | ||
| 1799 | - if (CONSTANT_P (tem) && !LEGITIMATE_CONSTANT_P (tem)) | ||
| 1800 | + if (CONSTANT_P (tem) | ||
| 1801 | + && !targetm.legitimate_constant_p (GET_MODE (x), tem)) | ||
| 1802 | { | ||
| 1803 | tem = force_const_mem (GET_MODE (x), tem); | ||
| 1804 | i = find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), | ||
| 1805 | @@ -6061,7 +6062,7 @@ | ||
| 1806 | enum reload_type type, int ind_levels) | ||
| 1807 | { | ||
| 1808 | if (CONSTANT_P (x) | ||
| 1809 | - && (! LEGITIMATE_CONSTANT_P (x) | ||
| 1810 | + && (!targetm.legitimate_constant_p (mode, x) | ||
| 1811 | || PREFERRED_RELOAD_CLASS (x, rclass) == NO_REGS)) | ||
| 1812 | { | ||
| 1813 | x = force_const_mem (mode, x); | ||
| 1814 | @@ -6071,7 +6072,7 @@ | ||
| 1815 | |||
| 1816 | else if (GET_CODE (x) == PLUS | ||
| 1817 | && CONSTANT_P (XEXP (x, 1)) | ||
| 1818 | - && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1)) | ||
| 1819 | + && (!targetm.legitimate_constant_p (GET_MODE (x), XEXP (x, 1)) | ||
| 1820 | || PREFERRED_RELOAD_CLASS (XEXP (x, 1), rclass) == NO_REGS)) | ||
| 1821 | { | ||
| 1822 | rtx tem; | ||
| 1823 | |||
| 1824 | === modified file 'gcc/reload1.c' | ||
| 1825 | --- old/gcc/reload1.c 2011-03-02 13:30:06 +0000 | ||
| 1826 | +++ new/gcc/reload1.c 2011-04-20 10:07:36 +0000 | ||
| 1827 | @@ -4164,6 +4164,9 @@ | ||
| 1828 | } | ||
| 1829 | else if (function_invariant_p (x)) | ||
| 1830 | { | ||
| 1831 | + enum machine_mode mode; | ||
| 1832 | + | ||
| 1833 | + mode = GET_MODE (SET_DEST (set)); | ||
| 1834 | if (GET_CODE (x) == PLUS) | ||
| 1835 | { | ||
| 1836 | /* This is PLUS of frame pointer and a constant, | ||
| 1837 | @@ -4176,12 +4179,11 @@ | ||
| 1838 | reg_equiv_invariant[i] = x; | ||
| 1839 | num_eliminable_invariants++; | ||
| 1840 | } | ||
| 1841 | - else if (LEGITIMATE_CONSTANT_P (x)) | ||
| 1842 | + else if (targetm.legitimate_constant_p (mode, x)) | ||
| 1843 | reg_equiv_constant[i] = x; | ||
| 1844 | else | ||
| 1845 | { | ||
| 1846 | - reg_equiv_memory_loc[i] | ||
| 1847 | - = force_const_mem (GET_MODE (SET_DEST (set)), x); | ||
| 1848 | + reg_equiv_memory_loc[i] = force_const_mem (mode, x); | ||
| 1849 | if (! reg_equiv_memory_loc[i]) | ||
| 1850 | reg_equiv_init[i] = NULL_RTX; | ||
| 1851 | } | ||
| 1852 | |||
| 1853 | === modified file 'gcc/stor-layout.c' | ||
| 1854 | --- old/gcc/stor-layout.c 2011-04-06 12:29:08 +0000 | ||
| 1855 | +++ new/gcc/stor-layout.c 2011-04-20 10:06:58 +0000 | ||
| 1856 | @@ -507,6 +507,34 @@ | ||
| 1857 | return MIN (BIGGEST_ALIGNMENT, MAX (1, mode_base_align[mode]*BITS_PER_UNIT)); | ||
| 1858 | } | ||
| 1859 | |||
| 1860 | +/* Return the natural mode of an array, given that it is SIZE bytes in | ||
| 1861 | + total and has elements of type ELEM_TYPE. */ | ||
| 1862 | + | ||
| 1863 | +static enum machine_mode | ||
| 1864 | +mode_for_array (tree elem_type, tree size) | ||
| 1865 | +{ | ||
| 1866 | + tree elem_size; | ||
| 1867 | + unsigned HOST_WIDE_INT int_size, int_elem_size; | ||
| 1868 | + bool limit_p; | ||
| 1869 | + | ||
| 1870 | + /* One-element arrays get the component type's mode. */ | ||
| 1871 | + elem_size = TYPE_SIZE (elem_type); | ||
| 1872 | + if (simple_cst_equal (size, elem_size)) | ||
| 1873 | + return TYPE_MODE (elem_type); | ||
| 1874 | + | ||
| 1875 | + limit_p = true; | ||
| 1876 | + if (host_integerp (size, 1) && host_integerp (elem_size, 1)) | ||
| 1877 | + { | ||
| 1878 | + int_size = tree_low_cst (size, 1); | ||
| 1879 | + int_elem_size = tree_low_cst (elem_size, 1); | ||
| 1880 | + if (int_elem_size > 0 | ||
| 1881 | + && int_size % int_elem_size == 0 | ||
| 1882 | + && targetm.array_mode_supported_p (TYPE_MODE (elem_type), | ||
| 1883 | + int_size / int_elem_size)) | ||
| 1884 | + limit_p = false; | ||
| 1885 | + } | ||
| 1886 | + return mode_for_size_tree (size, MODE_INT, limit_p); | ||
| 1887 | +} | ||
| 1888 | |||
| 1889 | /* Subroutine of layout_decl: Force alignment required for the data type. | ||
| 1890 | But if the decl itself wants greater alignment, don't override that. */ | ||
| 1891 | @@ -2044,14 +2072,8 @@ | ||
| 1892 | && (TYPE_MODE (TREE_TYPE (type)) != BLKmode | ||
| 1893 | || TYPE_NO_FORCE_BLK (TREE_TYPE (type)))) | ||
| 1894 | { | ||
| 1895 | - /* One-element arrays get the component type's mode. */ | ||
| 1896 | - if (simple_cst_equal (TYPE_SIZE (type), | ||
| 1897 | - TYPE_SIZE (TREE_TYPE (type)))) | ||
| 1898 | - SET_TYPE_MODE (type, TYPE_MODE (TREE_TYPE (type))); | ||
| 1899 | - else | ||
| 1900 | - SET_TYPE_MODE (type, mode_for_size_tree (TYPE_SIZE (type), | ||
| 1901 | - MODE_INT, 1)); | ||
| 1902 | - | ||
| 1903 | + SET_TYPE_MODE (type, mode_for_array (TREE_TYPE (type), | ||
| 1904 | + TYPE_SIZE (type))); | ||
| 1905 | if (TYPE_MODE (type) != BLKmode | ||
| 1906 | && STRICT_ALIGNMENT && TYPE_ALIGN (type) < BIGGEST_ALIGNMENT | ||
| 1907 | && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (TYPE_MODE (type))) | ||
| 1908 | |||
| 1909 | === modified file 'gcc/target-def.h' | ||
| 1910 | --- old/gcc/target-def.h 2010-08-10 13:31:21 +0000 | ||
| 1911 | +++ new/gcc/target-def.h 2011-04-20 10:07:36 +0000 | ||
| 1912 | @@ -553,12 +553,17 @@ | ||
| 1913 | #define TARGET_VECTOR_MODE_SUPPORTED_P hook_bool_mode_false | ||
| 1914 | #endif | ||
| 1915 | |||
| 1916 | +#ifndef TARGET_ARRAY_MODE_SUPPORTED_P | ||
| 1917 | +#define TARGET_ARRAY_MODE_SUPPORTED_P hook_bool_mode_uhwi_false | ||
| 1918 | +#endif | ||
| 1919 | + | ||
| 1920 | /* In hooks.c. */ | ||
| 1921 | #define TARGET_CANNOT_MODIFY_JUMPS_P hook_bool_void_false | ||
| 1922 | #define TARGET_BRANCH_TARGET_REGISTER_CLASS \ | ||
| 1923 | default_branch_target_register_class | ||
| 1924 | #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED hook_bool_bool_false | ||
| 1925 | #define TARGET_HAVE_CONDITIONAL_EXECUTION default_have_conditional_execution | ||
| 1926 | +#define TARGET_LEGITIMATE_CONSTANT_P default_legitimate_constant_p | ||
| 1927 | #define TARGET_CANNOT_FORCE_CONST_MEM hook_bool_rtx_false | ||
| 1928 | #define TARGET_CANNOT_COPY_INSN_P NULL | ||
| 1929 | #define TARGET_COMMUTATIVE_P hook_bool_const_rtx_commutative_p | ||
| 1930 | @@ -961,6 +966,7 @@ | ||
| 1931 | TARGET_BRANCH_TARGET_REGISTER_CLASS, \ | ||
| 1932 | TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED, \ | ||
| 1933 | TARGET_HAVE_CONDITIONAL_EXECUTION, \ | ||
| 1934 | + TARGET_LEGITIMATE_CONSTANT_P, \ | ||
| 1935 | TARGET_CANNOT_FORCE_CONST_MEM, \ | ||
| 1936 | TARGET_CANNOT_COPY_INSN_P, \ | ||
| 1937 | TARGET_COMMUTATIVE_P, \ | ||
| 1938 | @@ -985,6 +991,7 @@ | ||
| 1939 | TARGET_ADDR_SPACE_HOOKS, \ | ||
| 1940 | TARGET_SCALAR_MODE_SUPPORTED_P, \ | ||
| 1941 | TARGET_VECTOR_MODE_SUPPORTED_P, \ | ||
| 1942 | + TARGET_ARRAY_MODE_SUPPORTED_P, \ | ||
| 1943 | TARGET_RTX_COSTS, \ | ||
| 1944 | TARGET_ADDRESS_COST, \ | ||
| 1945 | TARGET_ALLOCATE_INITIAL_VALUE, \ | ||
| 1946 | |||
| 1947 | === modified file 'gcc/target.h' | ||
| 1948 | --- old/gcc/target.h 2010-08-10 13:31:21 +0000 | ||
| 1949 | +++ new/gcc/target.h 2011-04-20 10:07:36 +0000 | ||
| 1950 | @@ -645,7 +645,10 @@ | ||
| 1951 | /* Return true if the target supports conditional execution. */ | ||
| 1952 | bool (* have_conditional_execution) (void); | ||
| 1953 | |||
| 1954 | - /* True if the constant X cannot be placed in the constant pool. */ | ||
| 1955 | + /* See tm.texi. */ | ||
| 1956 | + bool (* legitimate_constant_p) (enum machine_mode, rtx); | ||
| 1957 | + | ||
| 1958 | + /* True if the constant X cannot be placed in the constant pool. */ | ||
| 1959 | bool (* cannot_force_const_mem) (rtx); | ||
| 1960 | |||
| 1961 | /* True if the insn X cannot be duplicated. */ | ||
| 1962 | @@ -764,6 +767,9 @@ | ||
| 1963 | for further details. */ | ||
| 1964 | bool (* vector_mode_supported_p) (enum machine_mode mode); | ||
| 1965 | |||
| 1966 | + /* See tm.texi. */ | ||
| 1967 | + bool (* array_mode_supported_p) (enum machine_mode, unsigned HOST_WIDE_INT); | ||
| 1968 | + | ||
| 1969 | /* Compute a (partial) cost for rtx X. Return true if the complete | ||
| 1970 | cost has been computed, and false if subexpressions should be | ||
| 1971 | scanned. In either case, *TOTAL contains the cost result. */ | ||
| 1972 | |||
| 1973 | === modified file 'gcc/targhooks.c' | ||
| 1974 | --- old/gcc/targhooks.c 2010-03-27 10:27:39 +0000 | ||
| 1975 | +++ new/gcc/targhooks.c 2011-04-20 10:07:36 +0000 | ||
| 1976 | @@ -1008,4 +1008,15 @@ | ||
| 1977 | #endif | ||
| 1978 | } | ||
| 1979 | |||
| 1980 | +bool | ||
| 1981 | +default_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, | ||
| 1982 | + rtx x ATTRIBUTE_UNUSED) | ||
| 1983 | +{ | ||
| 1984 | +#ifdef LEGITIMATE_CONSTANT_P | ||
| 1985 | + return LEGITIMATE_CONSTANT_P (x); | ||
| 1986 | +#else | ||
| 1987 | + return true; | ||
| 1988 | +#endif | ||
| 1989 | +} | ||
| 1990 | + | ||
| 1991 | #include "gt-targhooks.h" | ||
| 1992 | |||
| 1993 | === modified file 'gcc/targhooks.h' | ||
| 1994 | --- old/gcc/targhooks.h 2010-03-27 10:27:39 +0000 | ||
| 1995 | +++ new/gcc/targhooks.h 2011-04-20 10:07:36 +0000 | ||
| 1996 | @@ -132,3 +132,4 @@ | ||
| 1997 | extern rtx default_addr_space_convert (rtx, tree, tree); | ||
| 1998 | extern unsigned int default_case_values_threshold (void); | ||
| 1999 | extern bool default_have_conditional_execution (void); | ||
| 2000 | +extern bool default_legitimate_constant_p (enum machine_mode, rtx); | ||
| 2001 | |||
| 2002 | === added file 'gcc/testsuite/gcc.target/arm/neon-vld3-1.c' | ||
| 2003 | --- old/gcc/testsuite/gcc.target/arm/neon-vld3-1.c 1970-01-01 00:00:00 +0000 | ||
| 2004 | +++ new/gcc/testsuite/gcc.target/arm/neon-vld3-1.c 2011-04-20 10:00:39 +0000 | ||
| 2005 | @@ -0,0 +1,27 @@ | ||
| 2006 | +/* { dg-do run } */ | ||
| 2007 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2008 | +/* { dg-options "-O2" } */ | ||
| 2009 | +/* { dg-add-options arm_neon } */ | ||
| 2010 | + | ||
| 2011 | +#include "arm_neon.h" | ||
| 2012 | + | ||
| 2013 | +uint32_t buffer[12]; | ||
| 2014 | + | ||
| 2015 | +void __attribute__((noinline)) | ||
| 2016 | +foo (uint32_t *a) | ||
| 2017 | +{ | ||
| 2018 | + uint32x4x3_t x; | ||
| 2019 | + | ||
| 2020 | + x = vld3q_u32 (a); | ||
| 2021 | + x.val[0] = vaddq_u32 (x.val[0], x.val[1]); | ||
| 2022 | + vst3q_u32 (a, x); | ||
| 2023 | +} | ||
| 2024 | + | ||
| 2025 | +int | ||
| 2026 | +main (void) | ||
| 2027 | +{ | ||
| 2028 | + buffer[0] = 1; | ||
| 2029 | + buffer[1] = 2; | ||
| 2030 | + foo (buffer); | ||
| 2031 | + return buffer[0] != 3; | ||
| 2032 | +} | ||
| 2033 | |||
| 2034 | === added file 'gcc/testsuite/gcc.target/arm/neon-vst3-1.c' | ||
| 2035 | --- old/gcc/testsuite/gcc.target/arm/neon-vst3-1.c 1970-01-01 00:00:00 +0000 | ||
| 2036 | +++ new/gcc/testsuite/gcc.target/arm/neon-vst3-1.c 2011-04-20 10:00:39 +0000 | ||
| 2037 | @@ -0,0 +1,25 @@ | ||
| 2038 | +/* { dg-do run } */ | ||
| 2039 | +/* { dg-require-effective-target arm_neon_hw } */ | ||
| 2040 | +/* { dg-options "-O2" } */ | ||
| 2041 | +/* { dg-add-options arm_neon } */ | ||
| 2042 | + | ||
| 2043 | +#include "arm_neon.h" | ||
| 2044 | + | ||
| 2045 | +uint32_t buffer[64]; | ||
| 2046 | + | ||
| 2047 | +void __attribute__((noinline)) | ||
| 2048 | +foo (uint32_t *a) | ||
| 2049 | +{ | ||
| 2050 | + uint32x4x3_t x; | ||
| 2051 | + | ||
| 2052 | + x = vld3q_u32 (a); | ||
| 2053 | + a[35] = 1; | ||
| 2054 | + vst3q_lane_u32 (a + 32, x, 1); | ||
| 2055 | +} | ||
| 2056 | + | ||
| 2057 | +int | ||
| 2058 | +main (void) | ||
| 2059 | +{ | ||
| 2060 | + foo (buffer); | ||
| 2061 | + return buffer[35] != 1; | ||
| 2062 | +} | ||
| 2063 | |||
| 2064 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c' | ||
| 2065 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2010-08-20 13:27:11 +0000 | ||
| 2066 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2011-04-20 10:00:39 +0000 | ||
| 2067 | @@ -15,5 +15,5 @@ | ||
| 2068 | out_float32x4_t = vld1q_dup_f32 (0); | ||
| 2069 | } | ||
| 2070 | |||
| 2071 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2072 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2073 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2074 | |||
| 2075 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c' | ||
| 2076 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2010-08-20 13:27:11 +0000 | ||
| 2077 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2011-04-20 10:00:39 +0000 | ||
| 2078 | @@ -15,5 +15,5 @@ | ||
| 2079 | out_poly16x8_t = vld1q_dup_p16 (0); | ||
| 2080 | } | ||
| 2081 | |||
| 2082 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2083 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2084 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2085 | |||
| 2086 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c' | ||
| 2087 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2010-08-20 13:27:11 +0000 | ||
| 2088 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2011-04-20 10:00:39 +0000 | ||
| 2089 | @@ -15,5 +15,5 @@ | ||
| 2090 | out_poly8x16_t = vld1q_dup_p8 (0); | ||
| 2091 | } | ||
| 2092 | |||
| 2093 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2094 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2095 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2096 | |||
| 2097 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c' | ||
| 2098 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2010-08-20 13:27:11 +0000 | ||
| 2099 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2011-04-20 10:00:39 +0000 | ||
| 2100 | @@ -15,5 +15,5 @@ | ||
| 2101 | out_int16x8_t = vld1q_dup_s16 (0); | ||
| 2102 | } | ||
| 2103 | |||
| 2104 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2105 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2106 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2107 | |||
| 2108 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c' | ||
| 2109 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2010-08-20 13:27:11 +0000 | ||
| 2110 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2011-04-20 10:00:39 +0000 | ||
| 2111 | @@ -15,5 +15,5 @@ | ||
| 2112 | out_int32x4_t = vld1q_dup_s32 (0); | ||
| 2113 | } | ||
| 2114 | |||
| 2115 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2116 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2117 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2118 | |||
| 2119 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c' | ||
| 2120 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2010-08-20 13:27:11 +0000 | ||
| 2121 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2011-04-20 10:00:39 +0000 | ||
| 2122 | @@ -15,5 +15,5 @@ | ||
| 2123 | out_int64x2_t = vld1q_dup_s64 (0); | ||
| 2124 | } | ||
| 2125 | |||
| 2126 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2127 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2128 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2129 | |||
| 2130 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c' | ||
| 2131 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2010-08-20 13:27:11 +0000 | ||
| 2132 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2011-04-20 10:00:39 +0000 | ||
| 2133 | @@ -15,5 +15,5 @@ | ||
| 2134 | out_int8x16_t = vld1q_dup_s8 (0); | ||
| 2135 | } | ||
| 2136 | |||
| 2137 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2138 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2139 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2140 | |||
| 2141 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c' | ||
| 2142 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2010-08-20 13:27:11 +0000 | ||
| 2143 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2011-04-20 10:00:39 +0000 | ||
| 2144 | @@ -15,5 +15,5 @@ | ||
| 2145 | out_uint16x8_t = vld1q_dup_u16 (0); | ||
| 2146 | } | ||
| 2147 | |||
| 2148 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2149 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2150 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2151 | |||
| 2152 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c' | ||
| 2153 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2010-08-20 13:27:11 +0000 | ||
| 2154 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2011-04-20 10:00:39 +0000 | ||
| 2155 | @@ -15,5 +15,5 @@ | ||
| 2156 | out_uint32x4_t = vld1q_dup_u32 (0); | ||
| 2157 | } | ||
| 2158 | |||
| 2159 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2160 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2161 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2162 | |||
| 2163 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c' | ||
| 2164 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2010-08-20 13:27:11 +0000 | ||
| 2165 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2011-04-20 10:00:39 +0000 | ||
| 2166 | @@ -15,5 +15,5 @@ | ||
| 2167 | out_uint64x2_t = vld1q_dup_u64 (0); | ||
| 2168 | } | ||
| 2169 | |||
| 2170 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2171 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2172 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2173 | |||
| 2174 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c' | ||
| 2175 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2010-08-20 13:27:11 +0000 | ||
| 2176 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2011-04-20 10:00:39 +0000 | ||
| 2177 | @@ -15,5 +15,5 @@ | ||
| 2178 | out_uint8x16_t = vld1q_dup_u8 (0); | ||
| 2179 | } | ||
| 2180 | |||
| 2181 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2182 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2183 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2184 | |||
| 2185 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c' | ||
| 2186 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 2187 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 2188 | @@ -16,5 +16,5 @@ | ||
| 2189 | out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1); | ||
| 2190 | } | ||
| 2191 | |||
| 2192 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2193 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2194 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2195 | |||
| 2196 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c' | ||
| 2197 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 2198 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 2199 | @@ -16,5 +16,5 @@ | ||
| 2200 | out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1); | ||
| 2201 | } | ||
| 2202 | |||
| 2203 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2204 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2205 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2206 | |||
| 2207 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c' | ||
| 2208 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 2209 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2011-04-20 10:00:39 +0000 | ||
| 2210 | @@ -16,5 +16,5 @@ | ||
| 2211 | out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1); | ||
| 2212 | } | ||
| 2213 | |||
| 2214 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2215 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2216 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2217 | |||
| 2218 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c' | ||
| 2219 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 2220 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 2221 | @@ -16,5 +16,5 @@ | ||
| 2222 | out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1); | ||
| 2223 | } | ||
| 2224 | |||
| 2225 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2226 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2227 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2228 | |||
| 2229 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c' | ||
| 2230 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 2231 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 2232 | @@ -16,5 +16,5 @@ | ||
| 2233 | out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1); | ||
| 2234 | } | ||
| 2235 | |||
| 2236 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2237 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2238 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2239 | |||
| 2240 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c' | ||
| 2241 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2010-08-20 13:27:11 +0000 | ||
| 2242 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2011-04-20 10:00:39 +0000 | ||
| 2243 | @@ -16,5 +16,5 @@ | ||
| 2244 | out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1); | ||
| 2245 | } | ||
| 2246 | |||
| 2247 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2248 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2249 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2250 | |||
| 2251 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c' | ||
| 2252 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 2253 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2011-04-20 10:00:39 +0000 | ||
| 2254 | @@ -16,5 +16,5 @@ | ||
| 2255 | out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1); | ||
| 2256 | } | ||
| 2257 | |||
| 2258 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2259 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2260 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2261 | |||
| 2262 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c' | ||
| 2263 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 2264 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 2265 | @@ -16,5 +16,5 @@ | ||
| 2266 | out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1); | ||
| 2267 | } | ||
| 2268 | |||
| 2269 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2270 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2271 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2272 | |||
| 2273 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c' | ||
| 2274 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 2275 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 2276 | @@ -16,5 +16,5 @@ | ||
| 2277 | out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1); | ||
| 2278 | } | ||
| 2279 | |||
| 2280 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2281 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2282 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2283 | |||
| 2284 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c' | ||
| 2285 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2010-08-20 13:27:11 +0000 | ||
| 2286 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2011-04-20 10:00:39 +0000 | ||
| 2287 | @@ -16,5 +16,5 @@ | ||
| 2288 | out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1); | ||
| 2289 | } | ||
| 2290 | |||
| 2291 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2292 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2293 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2294 | |||
| 2295 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c' | ||
| 2296 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 2297 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2011-04-20 10:00:39 +0000 | ||
| 2298 | @@ -16,5 +16,5 @@ | ||
| 2299 | out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1); | ||
| 2300 | } | ||
| 2301 | |||
| 2302 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2303 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2304 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2305 | |||
| 2306 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c' | ||
| 2307 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 2308 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2011-04-20 10:00:39 +0000 | ||
| 2309 | @@ -15,5 +15,5 @@ | ||
| 2310 | out_float32x4_t = vld1q_f32 (0); | ||
| 2311 | } | ||
| 2312 | |||
| 2313 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2314 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2315 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2316 | |||
| 2317 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c' | ||
| 2318 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 2319 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2011-04-20 10:00:39 +0000 | ||
| 2320 | @@ -15,5 +15,5 @@ | ||
| 2321 | out_poly16x8_t = vld1q_p16 (0); | ||
| 2322 | } | ||
| 2323 | |||
| 2324 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2325 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2326 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2327 | |||
| 2328 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c' | ||
| 2329 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 2330 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2011-04-20 10:00:39 +0000 | ||
| 2331 | @@ -15,5 +15,5 @@ | ||
| 2332 | out_poly8x16_t = vld1q_p8 (0); | ||
| 2333 | } | ||
| 2334 | |||
| 2335 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2336 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2337 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2338 | |||
| 2339 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c' | ||
| 2340 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 2341 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2011-04-20 10:00:39 +0000 | ||
| 2342 | @@ -15,5 +15,5 @@ | ||
| 2343 | out_int16x8_t = vld1q_s16 (0); | ||
| 2344 | } | ||
| 2345 | |||
| 2346 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2347 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2348 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2349 | |||
| 2350 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c' | ||
| 2351 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 2352 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2011-04-20 10:00:39 +0000 | ||
| 2353 | @@ -15,5 +15,5 @@ | ||
| 2354 | out_int32x4_t = vld1q_s32 (0); | ||
| 2355 | } | ||
| 2356 | |||
| 2357 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2358 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2359 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2360 | |||
| 2361 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c' | ||
| 2362 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2010-08-20 13:27:11 +0000 | ||
| 2363 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2011-04-20 10:00:39 +0000 | ||
| 2364 | @@ -15,5 +15,5 @@ | ||
| 2365 | out_int64x2_t = vld1q_s64 (0); | ||
| 2366 | } | ||
| 2367 | |||
| 2368 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2369 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2370 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2371 | |||
| 2372 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c' | ||
| 2373 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 2374 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2011-04-20 10:00:39 +0000 | ||
| 2375 | @@ -15,5 +15,5 @@ | ||
| 2376 | out_int8x16_t = vld1q_s8 (0); | ||
| 2377 | } | ||
| 2378 | |||
| 2379 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2380 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2381 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2382 | |||
| 2383 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c' | ||
| 2384 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 2385 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2011-04-20 10:00:39 +0000 | ||
| 2386 | @@ -15,5 +15,5 @@ | ||
| 2387 | out_uint16x8_t = vld1q_u16 (0); | ||
| 2388 | } | ||
| 2389 | |||
| 2390 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2391 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2392 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2393 | |||
| 2394 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c' | ||
| 2395 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 2396 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2011-04-20 10:00:39 +0000 | ||
| 2397 | @@ -15,5 +15,5 @@ | ||
| 2398 | out_uint32x4_t = vld1q_u32 (0); | ||
| 2399 | } | ||
| 2400 | |||
| 2401 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2402 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2403 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2404 | |||
| 2405 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c' | ||
| 2406 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2010-08-20 13:27:11 +0000 | ||
| 2407 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2011-04-20 10:00:39 +0000 | ||
| 2408 | @@ -15,5 +15,5 @@ | ||
| 2409 | out_uint64x2_t = vld1q_u64 (0); | ||
| 2410 | } | ||
| 2411 | |||
| 2412 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2413 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2414 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2415 | |||
| 2416 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c' | ||
| 2417 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 2418 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2011-04-20 10:00:39 +0000 | ||
| 2419 | @@ -15,5 +15,5 @@ | ||
| 2420 | out_uint8x16_t = vld1q_u8 (0); | ||
| 2421 | } | ||
| 2422 | |||
| 2423 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2424 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2425 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2426 | |||
| 2427 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c' | ||
| 2428 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2010-08-20 13:27:11 +0000 | ||
| 2429 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2011-04-20 10:00:39 +0000 | ||
| 2430 | @@ -15,5 +15,5 @@ | ||
| 2431 | out_float32x2_t = vld1_dup_f32 (0); | ||
| 2432 | } | ||
| 2433 | |||
| 2434 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2435 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2436 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2437 | |||
| 2438 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c' | ||
| 2439 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2010-08-20 13:27:11 +0000 | ||
| 2440 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2011-04-20 10:00:39 +0000 | ||
| 2441 | @@ -15,5 +15,5 @@ | ||
| 2442 | out_poly16x4_t = vld1_dup_p16 (0); | ||
| 2443 | } | ||
| 2444 | |||
| 2445 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2446 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2447 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2448 | |||
| 2449 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c' | ||
| 2450 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2010-08-20 13:27:11 +0000 | ||
| 2451 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2011-04-20 10:00:39 +0000 | ||
| 2452 | @@ -15,5 +15,5 @@ | ||
| 2453 | out_poly8x8_t = vld1_dup_p8 (0); | ||
| 2454 | } | ||
| 2455 | |||
| 2456 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2457 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2458 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2459 | |||
| 2460 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c' | ||
| 2461 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2010-08-20 13:27:11 +0000 | ||
| 2462 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2011-04-20 10:00:39 +0000 | ||
| 2463 | @@ -15,5 +15,5 @@ | ||
| 2464 | out_int16x4_t = vld1_dup_s16 (0); | ||
| 2465 | } | ||
| 2466 | |||
| 2467 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2468 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2469 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2470 | |||
| 2471 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c' | ||
| 2472 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2010-08-20 13:27:11 +0000 | ||
| 2473 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2011-04-20 10:00:39 +0000 | ||
| 2474 | @@ -15,5 +15,5 @@ | ||
| 2475 | out_int32x2_t = vld1_dup_s32 (0); | ||
| 2476 | } | ||
| 2477 | |||
| 2478 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2479 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2480 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2481 | |||
| 2482 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c' | ||
| 2483 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2010-08-20 13:27:11 +0000 | ||
| 2484 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2011-04-20 10:00:39 +0000 | ||
| 2485 | @@ -15,5 +15,5 @@ | ||
| 2486 | out_int64x1_t = vld1_dup_s64 (0); | ||
| 2487 | } | ||
| 2488 | |||
| 2489 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2490 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2491 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2492 | |||
| 2493 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c' | ||
| 2494 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2010-08-20 13:27:11 +0000 | ||
| 2495 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2011-04-20 10:00:39 +0000 | ||
| 2496 | @@ -15,5 +15,5 @@ | ||
| 2497 | out_int8x8_t = vld1_dup_s8 (0); | ||
| 2498 | } | ||
| 2499 | |||
| 2500 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2501 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2502 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2503 | |||
| 2504 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c' | ||
| 2505 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2010-08-20 13:27:11 +0000 | ||
| 2506 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2011-04-20 10:00:39 +0000 | ||
| 2507 | @@ -15,5 +15,5 @@ | ||
| 2508 | out_uint16x4_t = vld1_dup_u16 (0); | ||
| 2509 | } | ||
| 2510 | |||
| 2511 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2512 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2513 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2514 | |||
| 2515 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c' | ||
| 2516 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2010-08-20 13:27:11 +0000 | ||
| 2517 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2011-04-20 10:00:39 +0000 | ||
| 2518 | @@ -15,5 +15,5 @@ | ||
| 2519 | out_uint32x2_t = vld1_dup_u32 (0); | ||
| 2520 | } | ||
| 2521 | |||
| 2522 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2523 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2524 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2525 | |||
| 2526 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c' | ||
| 2527 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2010-08-20 13:27:11 +0000 | ||
| 2528 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2011-04-20 10:00:39 +0000 | ||
| 2529 | @@ -15,5 +15,5 @@ | ||
| 2530 | out_uint64x1_t = vld1_dup_u64 (0); | ||
| 2531 | } | ||
| 2532 | |||
| 2533 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2534 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2535 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2536 | |||
| 2537 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c' | ||
| 2538 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2010-08-20 13:27:11 +0000 | ||
| 2539 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2011-04-20 10:00:39 +0000 | ||
| 2540 | @@ -15,5 +15,5 @@ | ||
| 2541 | out_uint8x8_t = vld1_dup_u8 (0); | ||
| 2542 | } | ||
| 2543 | |||
| 2544 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2545 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2546 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2547 | |||
| 2548 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c' | ||
| 2549 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 2550 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 2551 | @@ -16,5 +16,5 @@ | ||
| 2552 | out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1); | ||
| 2553 | } | ||
| 2554 | |||
| 2555 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2556 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2557 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2558 | |||
| 2559 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c' | ||
| 2560 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 2561 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 2562 | @@ -16,5 +16,5 @@ | ||
| 2563 | out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1); | ||
| 2564 | } | ||
| 2565 | |||
| 2566 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2567 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2568 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2569 | |||
| 2570 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c' | ||
| 2571 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 2572 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2011-04-20 10:00:39 +0000 | ||
| 2573 | @@ -16,5 +16,5 @@ | ||
| 2574 | out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1); | ||
| 2575 | } | ||
| 2576 | |||
| 2577 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2578 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2579 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2580 | |||
| 2581 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c' | ||
| 2582 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 2583 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 2584 | @@ -16,5 +16,5 @@ | ||
| 2585 | out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1); | ||
| 2586 | } | ||
| 2587 | |||
| 2588 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2589 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2590 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2591 | |||
| 2592 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c' | ||
| 2593 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 2594 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 2595 | @@ -16,5 +16,5 @@ | ||
| 2596 | out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1); | ||
| 2597 | } | ||
| 2598 | |||
| 2599 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2600 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2601 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2602 | |||
| 2603 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c' | ||
| 2604 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2010-08-20 13:27:11 +0000 | ||
| 2605 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2011-04-20 10:00:39 +0000 | ||
| 2606 | @@ -16,5 +16,5 @@ | ||
| 2607 | out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0); | ||
| 2608 | } | ||
| 2609 | |||
| 2610 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2611 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2612 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2613 | |||
| 2614 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c' | ||
| 2615 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 2616 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2011-04-20 10:00:39 +0000 | ||
| 2617 | @@ -16,5 +16,5 @@ | ||
| 2618 | out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1); | ||
| 2619 | } | ||
| 2620 | |||
| 2621 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2622 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2623 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2624 | |||
| 2625 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c' | ||
| 2626 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 2627 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 2628 | @@ -16,5 +16,5 @@ | ||
| 2629 | out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1); | ||
| 2630 | } | ||
| 2631 | |||
| 2632 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2633 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2634 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2635 | |||
| 2636 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c' | ||
| 2637 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 2638 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 2639 | @@ -16,5 +16,5 @@ | ||
| 2640 | out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1); | ||
| 2641 | } | ||
| 2642 | |||
| 2643 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2644 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2645 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2646 | |||
| 2647 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c' | ||
| 2648 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2010-08-20 13:27:11 +0000 | ||
| 2649 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2011-04-20 10:00:39 +0000 | ||
| 2650 | @@ -16,5 +16,5 @@ | ||
| 2651 | out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0); | ||
| 2652 | } | ||
| 2653 | |||
| 2654 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2655 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2656 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2657 | |||
| 2658 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c' | ||
| 2659 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 2660 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2011-04-20 10:00:39 +0000 | ||
| 2661 | @@ -16,5 +16,5 @@ | ||
| 2662 | out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1); | ||
| 2663 | } | ||
| 2664 | |||
| 2665 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2666 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2667 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2668 | |||
| 2669 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1f32.c' | ||
| 2670 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2010-08-20 13:27:11 +0000 | ||
| 2671 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2011-04-20 10:00:39 +0000 | ||
| 2672 | @@ -15,5 +15,5 @@ | ||
| 2673 | out_float32x2_t = vld1_f32 (0); | ||
| 2674 | } | ||
| 2675 | |||
| 2676 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2677 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2678 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2679 | |||
| 2680 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p16.c' | ||
| 2681 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2010-08-20 13:27:11 +0000 | ||
| 2682 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2011-04-20 10:00:39 +0000 | ||
| 2683 | @@ -15,5 +15,5 @@ | ||
| 2684 | out_poly16x4_t = vld1_p16 (0); | ||
| 2685 | } | ||
| 2686 | |||
| 2687 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2688 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2689 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2690 | |||
| 2691 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p8.c' | ||
| 2692 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2010-08-20 13:27:11 +0000 | ||
| 2693 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2011-04-20 10:00:39 +0000 | ||
| 2694 | @@ -15,5 +15,5 @@ | ||
| 2695 | out_poly8x8_t = vld1_p8 (0); | ||
| 2696 | } | ||
| 2697 | |||
| 2698 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2699 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2700 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2701 | |||
| 2702 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s16.c' | ||
| 2703 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2010-08-20 13:27:11 +0000 | ||
| 2704 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2011-04-20 10:00:39 +0000 | ||
| 2705 | @@ -15,5 +15,5 @@ | ||
| 2706 | out_int16x4_t = vld1_s16 (0); | ||
| 2707 | } | ||
| 2708 | |||
| 2709 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2710 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2711 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2712 | |||
| 2713 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s32.c' | ||
| 2714 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2010-08-20 13:27:11 +0000 | ||
| 2715 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2011-04-20 10:00:39 +0000 | ||
| 2716 | @@ -15,5 +15,5 @@ | ||
| 2717 | out_int32x2_t = vld1_s32 (0); | ||
| 2718 | } | ||
| 2719 | |||
| 2720 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2721 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2722 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2723 | |||
| 2724 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s64.c' | ||
| 2725 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2010-08-20 13:27:11 +0000 | ||
| 2726 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2011-04-20 10:00:39 +0000 | ||
| 2727 | @@ -15,5 +15,5 @@ | ||
| 2728 | out_int64x1_t = vld1_s64 (0); | ||
| 2729 | } | ||
| 2730 | |||
| 2731 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2732 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2733 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2734 | |||
| 2735 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s8.c' | ||
| 2736 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2010-08-20 13:27:11 +0000 | ||
| 2737 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2011-04-20 10:00:39 +0000 | ||
| 2738 | @@ -15,5 +15,5 @@ | ||
| 2739 | out_int8x8_t = vld1_s8 (0); | ||
| 2740 | } | ||
| 2741 | |||
| 2742 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2743 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2744 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2745 | |||
| 2746 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u16.c' | ||
| 2747 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2010-08-20 13:27:11 +0000 | ||
| 2748 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2011-04-20 10:00:39 +0000 | ||
| 2749 | @@ -15,5 +15,5 @@ | ||
| 2750 | out_uint16x4_t = vld1_u16 (0); | ||
| 2751 | } | ||
| 2752 | |||
| 2753 | -/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2754 | +/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2755 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2756 | |||
| 2757 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u32.c' | ||
| 2758 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2010-08-20 13:27:11 +0000 | ||
| 2759 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2011-04-20 10:00:39 +0000 | ||
| 2760 | @@ -15,5 +15,5 @@ | ||
| 2761 | out_uint32x2_t = vld1_u32 (0); | ||
| 2762 | } | ||
| 2763 | |||
| 2764 | -/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2765 | +/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2766 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2767 | |||
| 2768 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u64.c' | ||
| 2769 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2010-08-20 13:27:11 +0000 | ||
| 2770 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2011-04-20 10:00:39 +0000 | ||
| 2771 | @@ -15,5 +15,5 @@ | ||
| 2772 | out_uint64x1_t = vld1_u64 (0); | ||
| 2773 | } | ||
| 2774 | |||
| 2775 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2776 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2777 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2778 | |||
| 2779 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u8.c' | ||
| 2780 | --- old/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2010-08-20 13:27:11 +0000 | ||
| 2781 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2011-04-20 10:00:39 +0000 | ||
| 2782 | @@ -15,5 +15,5 @@ | ||
| 2783 | out_uint8x8_t = vld1_u8 (0); | ||
| 2784 | } | ||
| 2785 | |||
| 2786 | -/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2787 | +/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2788 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2789 | |||
| 2790 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c' | ||
| 2791 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 2792 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 2793 | @@ -16,5 +16,5 @@ | ||
| 2794 | out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1); | ||
| 2795 | } | ||
| 2796 | |||
| 2797 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2798 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2799 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2800 | |||
| 2801 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c' | ||
| 2802 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 2803 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 2804 | @@ -16,5 +16,5 @@ | ||
| 2805 | out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1); | ||
| 2806 | } | ||
| 2807 | |||
| 2808 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2809 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2810 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2811 | |||
| 2812 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c' | ||
| 2813 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 2814 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 2815 | @@ -16,5 +16,5 @@ | ||
| 2816 | out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1); | ||
| 2817 | } | ||
| 2818 | |||
| 2819 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2820 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2821 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2822 | |||
| 2823 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c' | ||
| 2824 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 2825 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 2826 | @@ -16,5 +16,5 @@ | ||
| 2827 | out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1); | ||
| 2828 | } | ||
| 2829 | |||
| 2830 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2831 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2832 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2833 | |||
| 2834 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c' | ||
| 2835 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 2836 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 2837 | @@ -16,5 +16,5 @@ | ||
| 2838 | out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1); | ||
| 2839 | } | ||
| 2840 | |||
| 2841 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2842 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2843 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2844 | |||
| 2845 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c' | ||
| 2846 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 2847 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 2848 | @@ -16,5 +16,5 @@ | ||
| 2849 | out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1); | ||
| 2850 | } | ||
| 2851 | |||
| 2852 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2853 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2854 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2855 | |||
| 2856 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c' | ||
| 2857 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 2858 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2011-04-20 10:00:39 +0000 | ||
| 2859 | @@ -15,6 +15,6 @@ | ||
| 2860 | out_float32x4x2_t = vld2q_f32 (0); | ||
| 2861 | } | ||
| 2862 | |||
| 2863 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2864 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2865 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2866 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2867 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2868 | |||
| 2869 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c' | ||
| 2870 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 2871 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2011-04-20 10:00:39 +0000 | ||
| 2872 | @@ -15,6 +15,6 @@ | ||
| 2873 | out_poly16x8x2_t = vld2q_p16 (0); | ||
| 2874 | } | ||
| 2875 | |||
| 2876 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2877 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2878 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2879 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2880 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2881 | |||
| 2882 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c' | ||
| 2883 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 2884 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2011-04-20 10:00:39 +0000 | ||
| 2885 | @@ -15,6 +15,6 @@ | ||
| 2886 | out_poly8x16x2_t = vld2q_p8 (0); | ||
| 2887 | } | ||
| 2888 | |||
| 2889 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2890 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2891 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2892 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2893 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2894 | |||
| 2895 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c' | ||
| 2896 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 2897 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2011-04-20 10:00:39 +0000 | ||
| 2898 | @@ -15,6 +15,6 @@ | ||
| 2899 | out_int16x8x2_t = vld2q_s16 (0); | ||
| 2900 | } | ||
| 2901 | |||
| 2902 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2903 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2904 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2905 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2906 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2907 | |||
| 2908 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c' | ||
| 2909 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 2910 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2011-04-20 10:00:39 +0000 | ||
| 2911 | @@ -15,6 +15,6 @@ | ||
| 2912 | out_int32x4x2_t = vld2q_s32 (0); | ||
| 2913 | } | ||
| 2914 | |||
| 2915 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2916 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2917 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2918 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2919 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2920 | |||
| 2921 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c' | ||
| 2922 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 2923 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2011-04-20 10:00:39 +0000 | ||
| 2924 | @@ -15,6 +15,6 @@ | ||
| 2925 | out_int8x16x2_t = vld2q_s8 (0); | ||
| 2926 | } | ||
| 2927 | |||
| 2928 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2929 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2930 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2931 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2932 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2933 | |||
| 2934 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c' | ||
| 2935 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 2936 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2011-04-20 10:00:39 +0000 | ||
| 2937 | @@ -15,6 +15,6 @@ | ||
| 2938 | out_uint16x8x2_t = vld2q_u16 (0); | ||
| 2939 | } | ||
| 2940 | |||
| 2941 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2942 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2943 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2944 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2945 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2946 | |||
| 2947 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c' | ||
| 2948 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 2949 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2011-04-20 10:00:39 +0000 | ||
| 2950 | @@ -15,6 +15,6 @@ | ||
| 2951 | out_uint32x4x2_t = vld2q_u32 (0); | ||
| 2952 | } | ||
| 2953 | |||
| 2954 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2955 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2956 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2957 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2958 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2959 | |||
| 2960 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c' | ||
| 2961 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 2962 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2011-04-20 10:00:39 +0000 | ||
| 2963 | @@ -15,6 +15,6 @@ | ||
| 2964 | out_uint8x16x2_t = vld2q_u8 (0); | ||
| 2965 | } | ||
| 2966 | |||
| 2967 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2968 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2969 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2970 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2971 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2972 | |||
| 2973 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c' | ||
| 2974 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2010-08-20 13:27:11 +0000 | ||
| 2975 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2011-04-20 10:00:39 +0000 | ||
| 2976 | @@ -15,5 +15,5 @@ | ||
| 2977 | out_float32x2x2_t = vld2_dup_f32 (0); | ||
| 2978 | } | ||
| 2979 | |||
| 2980 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2981 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2982 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2983 | |||
| 2984 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c' | ||
| 2985 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2010-08-20 13:27:11 +0000 | ||
| 2986 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2011-04-20 10:00:39 +0000 | ||
| 2987 | @@ -15,5 +15,5 @@ | ||
| 2988 | out_poly16x4x2_t = vld2_dup_p16 (0); | ||
| 2989 | } | ||
| 2990 | |||
| 2991 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2992 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 2993 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 2994 | |||
| 2995 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c' | ||
| 2996 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2010-08-20 13:27:11 +0000 | ||
| 2997 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2011-04-20 10:00:39 +0000 | ||
| 2998 | @@ -15,5 +15,5 @@ | ||
| 2999 | out_poly8x8x2_t = vld2_dup_p8 (0); | ||
| 3000 | } | ||
| 3001 | |||
| 3002 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3003 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3004 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3005 | |||
| 3006 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c' | ||
| 3007 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2010-08-20 13:27:11 +0000 | ||
| 3008 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2011-04-20 10:00:39 +0000 | ||
| 3009 | @@ -15,5 +15,5 @@ | ||
| 3010 | out_int16x4x2_t = vld2_dup_s16 (0); | ||
| 3011 | } | ||
| 3012 | |||
| 3013 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3014 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3015 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3016 | |||
| 3017 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c' | ||
| 3018 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2010-08-20 13:27:11 +0000 | ||
| 3019 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2011-04-20 10:00:39 +0000 | ||
| 3020 | @@ -15,5 +15,5 @@ | ||
| 3021 | out_int32x2x2_t = vld2_dup_s32 (0); | ||
| 3022 | } | ||
| 3023 | |||
| 3024 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3025 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3026 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3027 | |||
| 3028 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c' | ||
| 3029 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2010-08-20 13:27:11 +0000 | ||
| 3030 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2011-04-20 10:00:39 +0000 | ||
| 3031 | @@ -15,5 +15,5 @@ | ||
| 3032 | out_int64x1x2_t = vld2_dup_s64 (0); | ||
| 3033 | } | ||
| 3034 | |||
| 3035 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3036 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3037 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3038 | |||
| 3039 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c' | ||
| 3040 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2010-08-20 13:27:11 +0000 | ||
| 3041 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2011-04-20 10:00:39 +0000 | ||
| 3042 | @@ -15,5 +15,5 @@ | ||
| 3043 | out_int8x8x2_t = vld2_dup_s8 (0); | ||
| 3044 | } | ||
| 3045 | |||
| 3046 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3047 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3048 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3049 | |||
| 3050 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c' | ||
| 3051 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2010-08-20 13:27:11 +0000 | ||
| 3052 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2011-04-20 10:00:39 +0000 | ||
| 3053 | @@ -15,5 +15,5 @@ | ||
| 3054 | out_uint16x4x2_t = vld2_dup_u16 (0); | ||
| 3055 | } | ||
| 3056 | |||
| 3057 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3058 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3059 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3060 | |||
| 3061 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c' | ||
| 3062 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2010-08-20 13:27:11 +0000 | ||
| 3063 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2011-04-20 10:00:39 +0000 | ||
| 3064 | @@ -15,5 +15,5 @@ | ||
| 3065 | out_uint32x2x2_t = vld2_dup_u32 (0); | ||
| 3066 | } | ||
| 3067 | |||
| 3068 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3069 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3070 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3071 | |||
| 3072 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c' | ||
| 3073 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2010-08-20 13:27:11 +0000 | ||
| 3074 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2011-04-20 10:00:39 +0000 | ||
| 3075 | @@ -15,5 +15,5 @@ | ||
| 3076 | out_uint64x1x2_t = vld2_dup_u64 (0); | ||
| 3077 | } | ||
| 3078 | |||
| 3079 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3080 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3081 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3082 | |||
| 3083 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c' | ||
| 3084 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2010-08-20 13:27:11 +0000 | ||
| 3085 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2011-04-20 10:00:39 +0000 | ||
| 3086 | @@ -15,5 +15,5 @@ | ||
| 3087 | out_uint8x8x2_t = vld2_dup_u8 (0); | ||
| 3088 | } | ||
| 3089 | |||
| 3090 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3091 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3092 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3093 | |||
| 3094 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c' | ||
| 3095 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 3096 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 3097 | @@ -16,5 +16,5 @@ | ||
| 3098 | out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1); | ||
| 3099 | } | ||
| 3100 | |||
| 3101 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3102 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3103 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3104 | |||
| 3105 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c' | ||
| 3106 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 3107 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 3108 | @@ -16,5 +16,5 @@ | ||
| 3109 | out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1); | ||
| 3110 | } | ||
| 3111 | |||
| 3112 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3113 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3114 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3115 | |||
| 3116 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c' | ||
| 3117 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 3118 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2011-04-20 10:00:39 +0000 | ||
| 3119 | @@ -16,5 +16,5 @@ | ||
| 3120 | out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1); | ||
| 3121 | } | ||
| 3122 | |||
| 3123 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3124 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3125 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3126 | |||
| 3127 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c' | ||
| 3128 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 3129 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 3130 | @@ -16,5 +16,5 @@ | ||
| 3131 | out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1); | ||
| 3132 | } | ||
| 3133 | |||
| 3134 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3135 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3136 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3137 | |||
| 3138 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c' | ||
| 3139 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 3140 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 3141 | @@ -16,5 +16,5 @@ | ||
| 3142 | out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1); | ||
| 3143 | } | ||
| 3144 | |||
| 3145 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3146 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3147 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3148 | |||
| 3149 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c' | ||
| 3150 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 3151 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2011-04-20 10:00:39 +0000 | ||
| 3152 | @@ -16,5 +16,5 @@ | ||
| 3153 | out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1); | ||
| 3154 | } | ||
| 3155 | |||
| 3156 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3157 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3158 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3159 | |||
| 3160 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c' | ||
| 3161 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 3162 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 3163 | @@ -16,5 +16,5 @@ | ||
| 3164 | out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1); | ||
| 3165 | } | ||
| 3166 | |||
| 3167 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3168 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3169 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3170 | |||
| 3171 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c' | ||
| 3172 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 3173 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 3174 | @@ -16,5 +16,5 @@ | ||
| 3175 | out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1); | ||
| 3176 | } | ||
| 3177 | |||
| 3178 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3179 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3180 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3181 | |||
| 3182 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c' | ||
| 3183 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 3184 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2011-04-20 10:00:39 +0000 | ||
| 3185 | @@ -16,5 +16,5 @@ | ||
| 3186 | out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1); | ||
| 3187 | } | ||
| 3188 | |||
| 3189 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3190 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3191 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3192 | |||
| 3193 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2f32.c' | ||
| 3194 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2010-08-20 13:27:11 +0000 | ||
| 3195 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2011-04-20 10:00:39 +0000 | ||
| 3196 | @@ -15,5 +15,5 @@ | ||
| 3197 | out_float32x2x2_t = vld2_f32 (0); | ||
| 3198 | } | ||
| 3199 | |||
| 3200 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3201 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3202 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3203 | |||
| 3204 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p16.c' | ||
| 3205 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2010-08-20 13:27:11 +0000 | ||
| 3206 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2011-04-20 10:00:39 +0000 | ||
| 3207 | @@ -15,5 +15,5 @@ | ||
| 3208 | out_poly16x4x2_t = vld2_p16 (0); | ||
| 3209 | } | ||
| 3210 | |||
| 3211 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3212 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3213 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3214 | |||
| 3215 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p8.c' | ||
| 3216 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2010-08-20 13:27:11 +0000 | ||
| 3217 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2011-04-20 10:00:39 +0000 | ||
| 3218 | @@ -15,5 +15,5 @@ | ||
| 3219 | out_poly8x8x2_t = vld2_p8 (0); | ||
| 3220 | } | ||
| 3221 | |||
| 3222 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3223 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3224 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3225 | |||
| 3226 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s16.c' | ||
| 3227 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2010-08-20 13:27:11 +0000 | ||
| 3228 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2011-04-20 10:00:39 +0000 | ||
| 3229 | @@ -15,5 +15,5 @@ | ||
| 3230 | out_int16x4x2_t = vld2_s16 (0); | ||
| 3231 | } | ||
| 3232 | |||
| 3233 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3234 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3235 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3236 | |||
| 3237 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s32.c' | ||
| 3238 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2010-08-20 13:27:11 +0000 | ||
| 3239 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2011-04-20 10:00:39 +0000 | ||
| 3240 | @@ -15,5 +15,5 @@ | ||
| 3241 | out_int32x2x2_t = vld2_s32 (0); | ||
| 3242 | } | ||
| 3243 | |||
| 3244 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3245 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3246 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3247 | |||
| 3248 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s64.c' | ||
| 3249 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2010-08-20 13:27:11 +0000 | ||
| 3250 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2011-04-20 10:00:39 +0000 | ||
| 3251 | @@ -15,5 +15,5 @@ | ||
| 3252 | out_int64x1x2_t = vld2_s64 (0); | ||
| 3253 | } | ||
| 3254 | |||
| 3255 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3256 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3257 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3258 | |||
| 3259 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s8.c' | ||
| 3260 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2010-08-20 13:27:11 +0000 | ||
| 3261 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2011-04-20 10:00:39 +0000 | ||
| 3262 | @@ -15,5 +15,5 @@ | ||
| 3263 | out_int8x8x2_t = vld2_s8 (0); | ||
| 3264 | } | ||
| 3265 | |||
| 3266 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3267 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3268 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3269 | |||
| 3270 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u16.c' | ||
| 3271 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2010-08-20 13:27:11 +0000 | ||
| 3272 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2011-04-20 10:00:39 +0000 | ||
| 3273 | @@ -15,5 +15,5 @@ | ||
| 3274 | out_uint16x4x2_t = vld2_u16 (0); | ||
| 3275 | } | ||
| 3276 | |||
| 3277 | -/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3278 | +/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3279 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3280 | |||
| 3281 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u32.c' | ||
| 3282 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2010-08-20 13:27:11 +0000 | ||
| 3283 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2011-04-20 10:00:39 +0000 | ||
| 3284 | @@ -15,5 +15,5 @@ | ||
| 3285 | out_uint32x2x2_t = vld2_u32 (0); | ||
| 3286 | } | ||
| 3287 | |||
| 3288 | -/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3289 | +/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3290 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3291 | |||
| 3292 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u64.c' | ||
| 3293 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2010-08-20 13:27:11 +0000 | ||
| 3294 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2011-04-20 10:00:39 +0000 | ||
| 3295 | @@ -15,5 +15,5 @@ | ||
| 3296 | out_uint64x1x2_t = vld2_u64 (0); | ||
| 3297 | } | ||
| 3298 | |||
| 3299 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3300 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3301 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3302 | |||
| 3303 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u8.c' | ||
| 3304 | --- old/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2010-08-20 13:27:11 +0000 | ||
| 3305 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2011-04-20 10:00:39 +0000 | ||
| 3306 | @@ -15,5 +15,5 @@ | ||
| 3307 | out_uint8x8x2_t = vld2_u8 (0); | ||
| 3308 | } | ||
| 3309 | |||
| 3310 | -/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3311 | +/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3312 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3313 | |||
| 3314 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c' | ||
| 3315 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 3316 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 3317 | @@ -16,5 +16,5 @@ | ||
| 3318 | out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1); | ||
| 3319 | } | ||
| 3320 | |||
| 3321 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3322 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3323 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3324 | |||
| 3325 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c' | ||
| 3326 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 3327 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 3328 | @@ -16,5 +16,5 @@ | ||
| 3329 | out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1); | ||
| 3330 | } | ||
| 3331 | |||
| 3332 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3333 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3334 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3335 | |||
| 3336 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c' | ||
| 3337 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 3338 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 3339 | @@ -16,5 +16,5 @@ | ||
| 3340 | out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1); | ||
| 3341 | } | ||
| 3342 | |||
| 3343 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3344 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3345 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3346 | |||
| 3347 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c' | ||
| 3348 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 3349 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 3350 | @@ -16,5 +16,5 @@ | ||
| 3351 | out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1); | ||
| 3352 | } | ||
| 3353 | |||
| 3354 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3355 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3356 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3357 | |||
| 3358 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c' | ||
| 3359 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 3360 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 3361 | @@ -16,5 +16,5 @@ | ||
| 3362 | out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1); | ||
| 3363 | } | ||
| 3364 | |||
| 3365 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3366 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3367 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3368 | |||
| 3369 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c' | ||
| 3370 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 3371 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 3372 | @@ -16,5 +16,5 @@ | ||
| 3373 | out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1); | ||
| 3374 | } | ||
| 3375 | |||
| 3376 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3377 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3378 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3379 | |||
| 3380 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c' | ||
| 3381 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 3382 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2011-04-20 10:00:39 +0000 | ||
| 3383 | @@ -15,6 +15,6 @@ | ||
| 3384 | out_float32x4x3_t = vld3q_f32 (0); | ||
| 3385 | } | ||
| 3386 | |||
| 3387 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3388 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3389 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3390 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3391 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3392 | |||
| 3393 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c' | ||
| 3394 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 3395 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2011-04-20 10:00:39 +0000 | ||
| 3396 | @@ -15,6 +15,6 @@ | ||
| 3397 | out_poly16x8x3_t = vld3q_p16 (0); | ||
| 3398 | } | ||
| 3399 | |||
| 3400 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3401 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3402 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3403 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3404 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3405 | |||
| 3406 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c' | ||
| 3407 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 3408 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2011-04-20 10:00:39 +0000 | ||
| 3409 | @@ -15,6 +15,6 @@ | ||
| 3410 | out_poly8x16x3_t = vld3q_p8 (0); | ||
| 3411 | } | ||
| 3412 | |||
| 3413 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3414 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3415 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3416 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3417 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3418 | |||
| 3419 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c' | ||
| 3420 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 3421 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2011-04-20 10:00:39 +0000 | ||
| 3422 | @@ -15,6 +15,6 @@ | ||
| 3423 | out_int16x8x3_t = vld3q_s16 (0); | ||
| 3424 | } | ||
| 3425 | |||
| 3426 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3427 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3428 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3429 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3430 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3431 | |||
| 3432 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c' | ||
| 3433 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 3434 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2011-04-20 10:00:39 +0000 | ||
| 3435 | @@ -15,6 +15,6 @@ | ||
| 3436 | out_int32x4x3_t = vld3q_s32 (0); | ||
| 3437 | } | ||
| 3438 | |||
| 3439 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3440 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3441 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3442 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3443 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3444 | |||
| 3445 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c' | ||
| 3446 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 3447 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2011-04-20 10:00:39 +0000 | ||
| 3448 | @@ -15,6 +15,6 @@ | ||
| 3449 | out_int8x16x3_t = vld3q_s8 (0); | ||
| 3450 | } | ||
| 3451 | |||
| 3452 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3453 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3454 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3455 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3456 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3457 | |||
| 3458 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c' | ||
| 3459 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 3460 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2011-04-20 10:00:39 +0000 | ||
| 3461 | @@ -15,6 +15,6 @@ | ||
| 3462 | out_uint16x8x3_t = vld3q_u16 (0); | ||
| 3463 | } | ||
| 3464 | |||
| 3465 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3466 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3467 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3468 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3469 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3470 | |||
| 3471 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c' | ||
| 3472 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 3473 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2011-04-20 10:00:39 +0000 | ||
| 3474 | @@ -15,6 +15,6 @@ | ||
| 3475 | out_uint32x4x3_t = vld3q_u32 (0); | ||
| 3476 | } | ||
| 3477 | |||
| 3478 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3479 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3480 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3481 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3482 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3483 | |||
| 3484 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c' | ||
| 3485 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 3486 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2011-04-20 10:00:39 +0000 | ||
| 3487 | @@ -15,6 +15,6 @@ | ||
| 3488 | out_uint8x16x3_t = vld3q_u8 (0); | ||
| 3489 | } | ||
| 3490 | |||
| 3491 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3492 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3493 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3494 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3495 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3496 | |||
| 3497 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c' | ||
| 3498 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2010-08-20 13:27:11 +0000 | ||
| 3499 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2011-04-20 10:00:39 +0000 | ||
| 3500 | @@ -15,5 +15,5 @@ | ||
| 3501 | out_float32x2x3_t = vld3_dup_f32 (0); | ||
| 3502 | } | ||
| 3503 | |||
| 3504 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3505 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3506 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3507 | |||
| 3508 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c' | ||
| 3509 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2010-08-20 13:27:11 +0000 | ||
| 3510 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2011-04-20 10:00:39 +0000 | ||
| 3511 | @@ -15,5 +15,5 @@ | ||
| 3512 | out_poly16x4x3_t = vld3_dup_p16 (0); | ||
| 3513 | } | ||
| 3514 | |||
| 3515 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3516 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3517 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3518 | |||
| 3519 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c' | ||
| 3520 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2010-08-20 13:27:11 +0000 | ||
| 3521 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2011-04-20 10:00:39 +0000 | ||
| 3522 | @@ -15,5 +15,5 @@ | ||
| 3523 | out_poly8x8x3_t = vld3_dup_p8 (0); | ||
| 3524 | } | ||
| 3525 | |||
| 3526 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3527 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3528 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3529 | |||
| 3530 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c' | ||
| 3531 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2010-08-20 13:27:11 +0000 | ||
| 3532 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2011-04-20 10:00:39 +0000 | ||
| 3533 | @@ -15,5 +15,5 @@ | ||
| 3534 | out_int16x4x3_t = vld3_dup_s16 (0); | ||
| 3535 | } | ||
| 3536 | |||
| 3537 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3538 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3539 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3540 | |||
| 3541 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c' | ||
| 3542 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2010-08-20 13:27:11 +0000 | ||
| 3543 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2011-04-20 10:00:39 +0000 | ||
| 3544 | @@ -15,5 +15,5 @@ | ||
| 3545 | out_int32x2x3_t = vld3_dup_s32 (0); | ||
| 3546 | } | ||
| 3547 | |||
| 3548 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3549 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3550 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3551 | |||
| 3552 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c' | ||
| 3553 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2010-08-20 13:27:11 +0000 | ||
| 3554 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2011-04-20 10:00:39 +0000 | ||
| 3555 | @@ -15,5 +15,5 @@ | ||
| 3556 | out_int64x1x3_t = vld3_dup_s64 (0); | ||
| 3557 | } | ||
| 3558 | |||
| 3559 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3560 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3561 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3562 | |||
| 3563 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c' | ||
| 3564 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2010-08-20 13:27:11 +0000 | ||
| 3565 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2011-04-20 10:00:39 +0000 | ||
| 3566 | @@ -15,5 +15,5 @@ | ||
| 3567 | out_int8x8x3_t = vld3_dup_s8 (0); | ||
| 3568 | } | ||
| 3569 | |||
| 3570 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3571 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3572 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3573 | |||
| 3574 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c' | ||
| 3575 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2010-08-20 13:27:11 +0000 | ||
| 3576 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2011-04-20 10:00:39 +0000 | ||
| 3577 | @@ -15,5 +15,5 @@ | ||
| 3578 | out_uint16x4x3_t = vld3_dup_u16 (0); | ||
| 3579 | } | ||
| 3580 | |||
| 3581 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3582 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3583 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3584 | |||
| 3585 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c' | ||
| 3586 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2010-08-20 13:27:11 +0000 | ||
| 3587 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2011-04-20 10:00:39 +0000 | ||
| 3588 | @@ -15,5 +15,5 @@ | ||
| 3589 | out_uint32x2x3_t = vld3_dup_u32 (0); | ||
| 3590 | } | ||
| 3591 | |||
| 3592 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3593 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3594 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3595 | |||
| 3596 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c' | ||
| 3597 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2010-08-20 13:27:11 +0000 | ||
| 3598 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2011-04-20 10:00:39 +0000 | ||
| 3599 | @@ -15,5 +15,5 @@ | ||
| 3600 | out_uint64x1x3_t = vld3_dup_u64 (0); | ||
| 3601 | } | ||
| 3602 | |||
| 3603 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3604 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3605 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3606 | |||
| 3607 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c' | ||
| 3608 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2010-08-20 13:27:11 +0000 | ||
| 3609 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2011-04-20 10:00:39 +0000 | ||
| 3610 | @@ -15,5 +15,5 @@ | ||
| 3611 | out_uint8x8x3_t = vld3_dup_u8 (0); | ||
| 3612 | } | ||
| 3613 | |||
| 3614 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3615 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3616 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3617 | |||
| 3618 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c' | ||
| 3619 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 3620 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 3621 | @@ -16,5 +16,5 @@ | ||
| 3622 | out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1); | ||
| 3623 | } | ||
| 3624 | |||
| 3625 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3626 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3627 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3628 | |||
| 3629 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c' | ||
| 3630 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 3631 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 3632 | @@ -16,5 +16,5 @@ | ||
| 3633 | out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1); | ||
| 3634 | } | ||
| 3635 | |||
| 3636 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3637 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3638 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3639 | |||
| 3640 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c' | ||
| 3641 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 3642 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2011-04-20 10:00:39 +0000 | ||
| 3643 | @@ -16,5 +16,5 @@ | ||
| 3644 | out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1); | ||
| 3645 | } | ||
| 3646 | |||
| 3647 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3648 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3649 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3650 | |||
| 3651 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c' | ||
| 3652 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 3653 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 3654 | @@ -16,5 +16,5 @@ | ||
| 3655 | out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1); | ||
| 3656 | } | ||
| 3657 | |||
| 3658 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3659 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3660 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3661 | |||
| 3662 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c' | ||
| 3663 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 3664 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 3665 | @@ -16,5 +16,5 @@ | ||
| 3666 | out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1); | ||
| 3667 | } | ||
| 3668 | |||
| 3669 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3670 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3671 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3672 | |||
| 3673 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c' | ||
| 3674 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 3675 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2011-04-20 10:00:39 +0000 | ||
| 3676 | @@ -16,5 +16,5 @@ | ||
| 3677 | out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1); | ||
| 3678 | } | ||
| 3679 | |||
| 3680 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3681 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3682 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3683 | |||
| 3684 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c' | ||
| 3685 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 3686 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 3687 | @@ -16,5 +16,5 @@ | ||
| 3688 | out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1); | ||
| 3689 | } | ||
| 3690 | |||
| 3691 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3692 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3693 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3694 | |||
| 3695 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c' | ||
| 3696 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 3697 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 3698 | @@ -16,5 +16,5 @@ | ||
| 3699 | out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1); | ||
| 3700 | } | ||
| 3701 | |||
| 3702 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3703 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3704 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3705 | |||
| 3706 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c' | ||
| 3707 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 3708 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2011-04-20 10:00:39 +0000 | ||
| 3709 | @@ -16,5 +16,5 @@ | ||
| 3710 | out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1); | ||
| 3711 | } | ||
| 3712 | |||
| 3713 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3714 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3715 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3716 | |||
| 3717 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3f32.c' | ||
| 3718 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2010-08-20 13:27:11 +0000 | ||
| 3719 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2011-04-20 10:00:39 +0000 | ||
| 3720 | @@ -15,5 +15,5 @@ | ||
| 3721 | out_float32x2x3_t = vld3_f32 (0); | ||
| 3722 | } | ||
| 3723 | |||
| 3724 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3725 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3726 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3727 | |||
| 3728 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p16.c' | ||
| 3729 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2010-08-20 13:27:11 +0000 | ||
| 3730 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2011-04-20 10:00:39 +0000 | ||
| 3731 | @@ -15,5 +15,5 @@ | ||
| 3732 | out_poly16x4x3_t = vld3_p16 (0); | ||
| 3733 | } | ||
| 3734 | |||
| 3735 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3736 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3737 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3738 | |||
| 3739 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p8.c' | ||
| 3740 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2010-08-20 13:27:11 +0000 | ||
| 3741 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2011-04-20 10:00:39 +0000 | ||
| 3742 | @@ -15,5 +15,5 @@ | ||
| 3743 | out_poly8x8x3_t = vld3_p8 (0); | ||
| 3744 | } | ||
| 3745 | |||
| 3746 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3747 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3748 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3749 | |||
| 3750 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s16.c' | ||
| 3751 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2010-08-20 13:27:11 +0000 | ||
| 3752 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2011-04-20 10:00:39 +0000 | ||
| 3753 | @@ -15,5 +15,5 @@ | ||
| 3754 | out_int16x4x3_t = vld3_s16 (0); | ||
| 3755 | } | ||
| 3756 | |||
| 3757 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3758 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3759 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3760 | |||
| 3761 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s32.c' | ||
| 3762 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2010-08-20 13:27:11 +0000 | ||
| 3763 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2011-04-20 10:00:39 +0000 | ||
| 3764 | @@ -15,5 +15,5 @@ | ||
| 3765 | out_int32x2x3_t = vld3_s32 (0); | ||
| 3766 | } | ||
| 3767 | |||
| 3768 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3769 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3770 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3771 | |||
| 3772 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s64.c' | ||
| 3773 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2010-08-20 13:27:11 +0000 | ||
| 3774 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2011-04-20 10:00:39 +0000 | ||
| 3775 | @@ -15,5 +15,5 @@ | ||
| 3776 | out_int64x1x3_t = vld3_s64 (0); | ||
| 3777 | } | ||
| 3778 | |||
| 3779 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3780 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3781 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3782 | |||
| 3783 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s8.c' | ||
| 3784 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2010-08-20 13:27:11 +0000 | ||
| 3785 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2011-04-20 10:00:39 +0000 | ||
| 3786 | @@ -15,5 +15,5 @@ | ||
| 3787 | out_int8x8x3_t = vld3_s8 (0); | ||
| 3788 | } | ||
| 3789 | |||
| 3790 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3791 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3792 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3793 | |||
| 3794 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u16.c' | ||
| 3795 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2010-08-20 13:27:11 +0000 | ||
| 3796 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2011-04-20 10:00:39 +0000 | ||
| 3797 | @@ -15,5 +15,5 @@ | ||
| 3798 | out_uint16x4x3_t = vld3_u16 (0); | ||
| 3799 | } | ||
| 3800 | |||
| 3801 | -/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3802 | +/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3803 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3804 | |||
| 3805 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u32.c' | ||
| 3806 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2010-08-20 13:27:11 +0000 | ||
| 3807 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2011-04-20 10:00:39 +0000 | ||
| 3808 | @@ -15,5 +15,5 @@ | ||
| 3809 | out_uint32x2x3_t = vld3_u32 (0); | ||
| 3810 | } | ||
| 3811 | |||
| 3812 | -/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3813 | +/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3814 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3815 | |||
| 3816 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u64.c' | ||
| 3817 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2010-08-20 13:27:11 +0000 | ||
| 3818 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2011-04-20 10:00:39 +0000 | ||
| 3819 | @@ -15,5 +15,5 @@ | ||
| 3820 | out_uint64x1x3_t = vld3_u64 (0); | ||
| 3821 | } | ||
| 3822 | |||
| 3823 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3824 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3825 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3826 | |||
| 3827 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u8.c' | ||
| 3828 | --- old/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2010-08-20 13:27:11 +0000 | ||
| 3829 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2011-04-20 10:00:39 +0000 | ||
| 3830 | @@ -15,5 +15,5 @@ | ||
| 3831 | out_uint8x8x3_t = vld3_u8 (0); | ||
| 3832 | } | ||
| 3833 | |||
| 3834 | -/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3835 | +/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3836 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3837 | |||
| 3838 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c' | ||
| 3839 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 3840 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 3841 | @@ -16,5 +16,5 @@ | ||
| 3842 | out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1); | ||
| 3843 | } | ||
| 3844 | |||
| 3845 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3846 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3847 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3848 | |||
| 3849 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c' | ||
| 3850 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 3851 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 3852 | @@ -16,5 +16,5 @@ | ||
| 3853 | out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1); | ||
| 3854 | } | ||
| 3855 | |||
| 3856 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3857 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3858 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3859 | |||
| 3860 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c' | ||
| 3861 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 3862 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 3863 | @@ -16,5 +16,5 @@ | ||
| 3864 | out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1); | ||
| 3865 | } | ||
| 3866 | |||
| 3867 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3868 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3869 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3870 | |||
| 3871 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c' | ||
| 3872 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 3873 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 3874 | @@ -16,5 +16,5 @@ | ||
| 3875 | out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1); | ||
| 3876 | } | ||
| 3877 | |||
| 3878 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3879 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3880 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3881 | |||
| 3882 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c' | ||
| 3883 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 3884 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 3885 | @@ -16,5 +16,5 @@ | ||
| 3886 | out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1); | ||
| 3887 | } | ||
| 3888 | |||
| 3889 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3890 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3891 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3892 | |||
| 3893 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c' | ||
| 3894 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 3895 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 3896 | @@ -16,5 +16,5 @@ | ||
| 3897 | out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1); | ||
| 3898 | } | ||
| 3899 | |||
| 3900 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3901 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3902 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3903 | |||
| 3904 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c' | ||
| 3905 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 3906 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2011-04-20 10:00:39 +0000 | ||
| 3907 | @@ -15,6 +15,6 @@ | ||
| 3908 | out_float32x4x4_t = vld4q_f32 (0); | ||
| 3909 | } | ||
| 3910 | |||
| 3911 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3912 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3913 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3914 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3915 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3916 | |||
| 3917 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c' | ||
| 3918 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 3919 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2011-04-20 10:00:39 +0000 | ||
| 3920 | @@ -15,6 +15,6 @@ | ||
| 3921 | out_poly16x8x4_t = vld4q_p16 (0); | ||
| 3922 | } | ||
| 3923 | |||
| 3924 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3925 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3926 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3927 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3928 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3929 | |||
| 3930 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c' | ||
| 3931 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 3932 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2011-04-20 10:00:39 +0000 | ||
| 3933 | @@ -15,6 +15,6 @@ | ||
| 3934 | out_poly8x16x4_t = vld4q_p8 (0); | ||
| 3935 | } | ||
| 3936 | |||
| 3937 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3938 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3939 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3940 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3941 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3942 | |||
| 3943 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c' | ||
| 3944 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 3945 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2011-04-20 10:00:39 +0000 | ||
| 3946 | @@ -15,6 +15,6 @@ | ||
| 3947 | out_int16x8x4_t = vld4q_s16 (0); | ||
| 3948 | } | ||
| 3949 | |||
| 3950 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3951 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3952 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3953 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3954 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3955 | |||
| 3956 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c' | ||
| 3957 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 3958 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2011-04-20 10:00:39 +0000 | ||
| 3959 | @@ -15,6 +15,6 @@ | ||
| 3960 | out_int32x4x4_t = vld4q_s32 (0); | ||
| 3961 | } | ||
| 3962 | |||
| 3963 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3964 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3965 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3966 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3967 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3968 | |||
| 3969 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c' | ||
| 3970 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 3971 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2011-04-20 10:00:39 +0000 | ||
| 3972 | @@ -15,6 +15,6 @@ | ||
| 3973 | out_int8x16x4_t = vld4q_s8 (0); | ||
| 3974 | } | ||
| 3975 | |||
| 3976 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3977 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3978 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3979 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3980 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3981 | |||
| 3982 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c' | ||
| 3983 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 3984 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2011-04-20 10:00:39 +0000 | ||
| 3985 | @@ -15,6 +15,6 @@ | ||
| 3986 | out_uint16x8x4_t = vld4q_u16 (0); | ||
| 3987 | } | ||
| 3988 | |||
| 3989 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3990 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3991 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3992 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 3993 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 3994 | |||
| 3995 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c' | ||
| 3996 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 3997 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2011-04-20 10:00:39 +0000 | ||
| 3998 | @@ -15,6 +15,6 @@ | ||
| 3999 | out_uint32x4x4_t = vld4q_u32 (0); | ||
| 4000 | } | ||
| 4001 | |||
| 4002 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4003 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4004 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4005 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4006 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4007 | |||
| 4008 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c' | ||
| 4009 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 4010 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2011-04-20 10:00:39 +0000 | ||
| 4011 | @@ -15,6 +15,6 @@ | ||
| 4012 | out_uint8x16x4_t = vld4q_u8 (0); | ||
| 4013 | } | ||
| 4014 | |||
| 4015 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4016 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4017 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4018 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4019 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4020 | |||
| 4021 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c' | ||
| 4022 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2010-08-20 13:27:11 +0000 | ||
| 4023 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2011-04-20 10:00:39 +0000 | ||
| 4024 | @@ -15,5 +15,5 @@ | ||
| 4025 | out_float32x2x4_t = vld4_dup_f32 (0); | ||
| 4026 | } | ||
| 4027 | |||
| 4028 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4029 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4030 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4031 | |||
| 4032 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c' | ||
| 4033 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2010-08-20 13:27:11 +0000 | ||
| 4034 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2011-04-20 10:00:39 +0000 | ||
| 4035 | @@ -15,5 +15,5 @@ | ||
| 4036 | out_poly16x4x4_t = vld4_dup_p16 (0); | ||
| 4037 | } | ||
| 4038 | |||
| 4039 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4040 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4041 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4042 | |||
| 4043 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c' | ||
| 4044 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2010-08-20 13:27:11 +0000 | ||
| 4045 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2011-04-20 10:00:39 +0000 | ||
| 4046 | @@ -15,5 +15,5 @@ | ||
| 4047 | out_poly8x8x4_t = vld4_dup_p8 (0); | ||
| 4048 | } | ||
| 4049 | |||
| 4050 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4051 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4052 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4053 | |||
| 4054 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c' | ||
| 4055 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2010-08-20 13:27:11 +0000 | ||
| 4056 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2011-04-20 10:00:39 +0000 | ||
| 4057 | @@ -15,5 +15,5 @@ | ||
| 4058 | out_int16x4x4_t = vld4_dup_s16 (0); | ||
| 4059 | } | ||
| 4060 | |||
| 4061 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4062 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4063 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4064 | |||
| 4065 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c' | ||
| 4066 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2010-08-20 13:27:11 +0000 | ||
| 4067 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2011-04-20 10:00:39 +0000 | ||
| 4068 | @@ -15,5 +15,5 @@ | ||
| 4069 | out_int32x2x4_t = vld4_dup_s32 (0); | ||
| 4070 | } | ||
| 4071 | |||
| 4072 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4073 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4074 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4075 | |||
| 4076 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c' | ||
| 4077 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2010-08-20 13:27:11 +0000 | ||
| 4078 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2011-04-20 10:00:39 +0000 | ||
| 4079 | @@ -15,5 +15,5 @@ | ||
| 4080 | out_int64x1x4_t = vld4_dup_s64 (0); | ||
| 4081 | } | ||
| 4082 | |||
| 4083 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4084 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4085 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4086 | |||
| 4087 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c' | ||
| 4088 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2010-08-20 13:27:11 +0000 | ||
| 4089 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2011-04-20 10:00:39 +0000 | ||
| 4090 | @@ -15,5 +15,5 @@ | ||
| 4091 | out_int8x8x4_t = vld4_dup_s8 (0); | ||
| 4092 | } | ||
| 4093 | |||
| 4094 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4095 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4096 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4097 | |||
| 4098 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c' | ||
| 4099 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2010-08-20 13:27:11 +0000 | ||
| 4100 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2011-04-20 10:00:39 +0000 | ||
| 4101 | @@ -15,5 +15,5 @@ | ||
| 4102 | out_uint16x4x4_t = vld4_dup_u16 (0); | ||
| 4103 | } | ||
| 4104 | |||
| 4105 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4106 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4107 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4108 | |||
| 4109 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c' | ||
| 4110 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2010-08-20 13:27:11 +0000 | ||
| 4111 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2011-04-20 10:00:39 +0000 | ||
| 4112 | @@ -15,5 +15,5 @@ | ||
| 4113 | out_uint32x2x4_t = vld4_dup_u32 (0); | ||
| 4114 | } | ||
| 4115 | |||
| 4116 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4117 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4118 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4119 | |||
| 4120 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c' | ||
| 4121 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2010-08-20 13:27:11 +0000 | ||
| 4122 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2011-04-20 10:00:39 +0000 | ||
| 4123 | @@ -15,5 +15,5 @@ | ||
| 4124 | out_uint64x1x4_t = vld4_dup_u64 (0); | ||
| 4125 | } | ||
| 4126 | |||
| 4127 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4128 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4129 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4130 | |||
| 4131 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c' | ||
| 4132 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2010-08-20 13:27:11 +0000 | ||
| 4133 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2011-04-20 10:00:39 +0000 | ||
| 4134 | @@ -15,5 +15,5 @@ | ||
| 4135 | out_uint8x8x4_t = vld4_dup_u8 (0); | ||
| 4136 | } | ||
| 4137 | |||
| 4138 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4139 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4140 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4141 | |||
| 4142 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c' | ||
| 4143 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 4144 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 4145 | @@ -16,5 +16,5 @@ | ||
| 4146 | out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1); | ||
| 4147 | } | ||
| 4148 | |||
| 4149 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4150 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4151 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4152 | |||
| 4153 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c' | ||
| 4154 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 4155 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 4156 | @@ -16,5 +16,5 @@ | ||
| 4157 | out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1); | ||
| 4158 | } | ||
| 4159 | |||
| 4160 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4161 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4162 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4163 | |||
| 4164 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c' | ||
| 4165 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 4166 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2011-04-20 10:00:39 +0000 | ||
| 4167 | @@ -16,5 +16,5 @@ | ||
| 4168 | out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1); | ||
| 4169 | } | ||
| 4170 | |||
| 4171 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4172 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4173 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4174 | |||
| 4175 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c' | ||
| 4176 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 4177 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 4178 | @@ -16,5 +16,5 @@ | ||
| 4179 | out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1); | ||
| 4180 | } | ||
| 4181 | |||
| 4182 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4183 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4184 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4185 | |||
| 4186 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c' | ||
| 4187 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 4188 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 4189 | @@ -16,5 +16,5 @@ | ||
| 4190 | out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1); | ||
| 4191 | } | ||
| 4192 | |||
| 4193 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4194 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4195 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4196 | |||
| 4197 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c' | ||
| 4198 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 4199 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2011-04-20 10:00:39 +0000 | ||
| 4200 | @@ -16,5 +16,5 @@ | ||
| 4201 | out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1); | ||
| 4202 | } | ||
| 4203 | |||
| 4204 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4205 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4206 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4207 | |||
| 4208 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c' | ||
| 4209 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 4210 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 4211 | @@ -16,5 +16,5 @@ | ||
| 4212 | out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1); | ||
| 4213 | } | ||
| 4214 | |||
| 4215 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4216 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4217 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4218 | |||
| 4219 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c' | ||
| 4220 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 4221 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 4222 | @@ -16,5 +16,5 @@ | ||
| 4223 | out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1); | ||
| 4224 | } | ||
| 4225 | |||
| 4226 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4227 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4228 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4229 | |||
| 4230 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c' | ||
| 4231 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 4232 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2011-04-20 10:00:39 +0000 | ||
| 4233 | @@ -16,5 +16,5 @@ | ||
| 4234 | out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1); | ||
| 4235 | } | ||
| 4236 | |||
| 4237 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4238 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4239 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4240 | |||
| 4241 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4f32.c' | ||
| 4242 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2010-08-20 13:27:11 +0000 | ||
| 4243 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2011-04-20 10:00:39 +0000 | ||
| 4244 | @@ -15,5 +15,5 @@ | ||
| 4245 | out_float32x2x4_t = vld4_f32 (0); | ||
| 4246 | } | ||
| 4247 | |||
| 4248 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4249 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4250 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4251 | |||
| 4252 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p16.c' | ||
| 4253 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2010-08-20 13:27:11 +0000 | ||
| 4254 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2011-04-20 10:00:39 +0000 | ||
| 4255 | @@ -15,5 +15,5 @@ | ||
| 4256 | out_poly16x4x4_t = vld4_p16 (0); | ||
| 4257 | } | ||
| 4258 | |||
| 4259 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4260 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4261 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4262 | |||
| 4263 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p8.c' | ||
| 4264 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2010-08-20 13:27:11 +0000 | ||
| 4265 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2011-04-20 10:00:39 +0000 | ||
| 4266 | @@ -15,5 +15,5 @@ | ||
| 4267 | out_poly8x8x4_t = vld4_p8 (0); | ||
| 4268 | } | ||
| 4269 | |||
| 4270 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4271 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4272 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4273 | |||
| 4274 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s16.c' | ||
| 4275 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2010-08-20 13:27:11 +0000 | ||
| 4276 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2011-04-20 10:00:39 +0000 | ||
| 4277 | @@ -15,5 +15,5 @@ | ||
| 4278 | out_int16x4x4_t = vld4_s16 (0); | ||
| 4279 | } | ||
| 4280 | |||
| 4281 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4282 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4283 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4284 | |||
| 4285 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s32.c' | ||
| 4286 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2010-08-20 13:27:11 +0000 | ||
| 4287 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2011-04-20 10:00:39 +0000 | ||
| 4288 | @@ -15,5 +15,5 @@ | ||
| 4289 | out_int32x2x4_t = vld4_s32 (0); | ||
| 4290 | } | ||
| 4291 | |||
| 4292 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4293 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4294 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4295 | |||
| 4296 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s64.c' | ||
| 4297 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2010-08-20 13:27:11 +0000 | ||
| 4298 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2011-04-20 10:00:39 +0000 | ||
| 4299 | @@ -15,5 +15,5 @@ | ||
| 4300 | out_int64x1x4_t = vld4_s64 (0); | ||
| 4301 | } | ||
| 4302 | |||
| 4303 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4304 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4305 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4306 | |||
| 4307 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s8.c' | ||
| 4308 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2010-08-20 13:27:11 +0000 | ||
| 4309 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2011-04-20 10:00:39 +0000 | ||
| 4310 | @@ -15,5 +15,5 @@ | ||
| 4311 | out_int8x8x4_t = vld4_s8 (0); | ||
| 4312 | } | ||
| 4313 | |||
| 4314 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4315 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4316 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4317 | |||
| 4318 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u16.c' | ||
| 4319 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2010-08-20 13:27:11 +0000 | ||
| 4320 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2011-04-20 10:00:39 +0000 | ||
| 4321 | @@ -15,5 +15,5 @@ | ||
| 4322 | out_uint16x4x4_t = vld4_u16 (0); | ||
| 4323 | } | ||
| 4324 | |||
| 4325 | -/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4326 | +/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4327 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4328 | |||
| 4329 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u32.c' | ||
| 4330 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2010-08-20 13:27:11 +0000 | ||
| 4331 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2011-04-20 10:00:39 +0000 | ||
| 4332 | @@ -15,5 +15,5 @@ | ||
| 4333 | out_uint32x2x4_t = vld4_u32 (0); | ||
| 4334 | } | ||
| 4335 | |||
| 4336 | -/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4337 | +/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4338 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4339 | |||
| 4340 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u64.c' | ||
| 4341 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2010-08-20 13:27:11 +0000 | ||
| 4342 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2011-04-20 10:00:39 +0000 | ||
| 4343 | @@ -15,5 +15,5 @@ | ||
| 4344 | out_uint64x1x4_t = vld4_u64 (0); | ||
| 4345 | } | ||
| 4346 | |||
| 4347 | -/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4348 | +/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4349 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4350 | |||
| 4351 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u8.c' | ||
| 4352 | --- old/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2010-08-20 13:27:11 +0000 | ||
| 4353 | +++ new/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2011-04-20 10:00:39 +0000 | ||
| 4354 | @@ -15,5 +15,5 @@ | ||
| 4355 | out_uint8x8x4_t = vld4_u8 (0); | ||
| 4356 | } | ||
| 4357 | |||
| 4358 | -/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4359 | +/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4360 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4361 | |||
| 4362 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c' | ||
| 4363 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 4364 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 4365 | @@ -16,5 +16,5 @@ | ||
| 4366 | vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); | ||
| 4367 | } | ||
| 4368 | |||
| 4369 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4370 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4371 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4372 | |||
| 4373 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c' | ||
| 4374 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 4375 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 4376 | @@ -16,5 +16,5 @@ | ||
| 4377 | vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); | ||
| 4378 | } | ||
| 4379 | |||
| 4380 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4381 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4382 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4383 | |||
| 4384 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c' | ||
| 4385 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 4386 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2011-04-20 10:00:39 +0000 | ||
| 4387 | @@ -16,5 +16,5 @@ | ||
| 4388 | vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); | ||
| 4389 | } | ||
| 4390 | |||
| 4391 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4392 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4393 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4394 | |||
| 4395 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c' | ||
| 4396 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 4397 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 4398 | @@ -16,5 +16,5 @@ | ||
| 4399 | vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); | ||
| 4400 | } | ||
| 4401 | |||
| 4402 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4403 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4404 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4405 | |||
| 4406 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c' | ||
| 4407 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 4408 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 4409 | @@ -16,5 +16,5 @@ | ||
| 4410 | vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); | ||
| 4411 | } | ||
| 4412 | |||
| 4413 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4414 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4415 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4416 | |||
| 4417 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c' | ||
| 4418 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2010-08-20 13:27:11 +0000 | ||
| 4419 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2011-04-20 10:00:39 +0000 | ||
| 4420 | @@ -16,5 +16,5 @@ | ||
| 4421 | vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1); | ||
| 4422 | } | ||
| 4423 | |||
| 4424 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4425 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4426 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4427 | |||
| 4428 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c' | ||
| 4429 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 4430 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2011-04-20 10:00:39 +0000 | ||
| 4431 | @@ -16,5 +16,5 @@ | ||
| 4432 | vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); | ||
| 4433 | } | ||
| 4434 | |||
| 4435 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4436 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4437 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4438 | |||
| 4439 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c' | ||
| 4440 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 4441 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 4442 | @@ -16,5 +16,5 @@ | ||
| 4443 | vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); | ||
| 4444 | } | ||
| 4445 | |||
| 4446 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4447 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4448 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4449 | |||
| 4450 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c' | ||
| 4451 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 4452 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 4453 | @@ -16,5 +16,5 @@ | ||
| 4454 | vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); | ||
| 4455 | } | ||
| 4456 | |||
| 4457 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4458 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4459 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4460 | |||
| 4461 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c' | ||
| 4462 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2010-08-20 13:27:11 +0000 | ||
| 4463 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2011-04-20 10:00:39 +0000 | ||
| 4464 | @@ -16,5 +16,5 @@ | ||
| 4465 | vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1); | ||
| 4466 | } | ||
| 4467 | |||
| 4468 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4469 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4470 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4471 | |||
| 4472 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c' | ||
| 4473 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 4474 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2011-04-20 10:00:39 +0000 | ||
| 4475 | @@ -16,5 +16,5 @@ | ||
| 4476 | vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); | ||
| 4477 | } | ||
| 4478 | |||
| 4479 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4480 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4481 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4482 | |||
| 4483 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c' | ||
| 4484 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 4485 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2011-04-20 10:00:39 +0000 | ||
| 4486 | @@ -16,5 +16,5 @@ | ||
| 4487 | vst1q_f32 (arg0_float32_t, arg1_float32x4_t); | ||
| 4488 | } | ||
| 4489 | |||
| 4490 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4491 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4492 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4493 | |||
| 4494 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c' | ||
| 4495 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 4496 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2011-04-20 10:00:39 +0000 | ||
| 4497 | @@ -16,5 +16,5 @@ | ||
| 4498 | vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t); | ||
| 4499 | } | ||
| 4500 | |||
| 4501 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4502 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4503 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4504 | |||
| 4505 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c' | ||
| 4506 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 4507 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2011-04-20 10:00:39 +0000 | ||
| 4508 | @@ -16,5 +16,5 @@ | ||
| 4509 | vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t); | ||
| 4510 | } | ||
| 4511 | |||
| 4512 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4513 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4514 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4515 | |||
| 4516 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c' | ||
| 4517 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 4518 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2011-04-20 10:00:39 +0000 | ||
| 4519 | @@ -16,5 +16,5 @@ | ||
| 4520 | vst1q_s16 (arg0_int16_t, arg1_int16x8_t); | ||
| 4521 | } | ||
| 4522 | |||
| 4523 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4524 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4525 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4526 | |||
| 4527 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c' | ||
| 4528 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 4529 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2011-04-20 10:00:39 +0000 | ||
| 4530 | @@ -16,5 +16,5 @@ | ||
| 4531 | vst1q_s32 (arg0_int32_t, arg1_int32x4_t); | ||
| 4532 | } | ||
| 4533 | |||
| 4534 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4535 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4536 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4537 | |||
| 4538 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c' | ||
| 4539 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2010-08-20 13:27:11 +0000 | ||
| 4540 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2011-04-20 10:00:39 +0000 | ||
| 4541 | @@ -16,5 +16,5 @@ | ||
| 4542 | vst1q_s64 (arg0_int64_t, arg1_int64x2_t); | ||
| 4543 | } | ||
| 4544 | |||
| 4545 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4546 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4547 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4548 | |||
| 4549 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c' | ||
| 4550 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 4551 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2011-04-20 10:00:39 +0000 | ||
| 4552 | @@ -16,5 +16,5 @@ | ||
| 4553 | vst1q_s8 (arg0_int8_t, arg1_int8x16_t); | ||
| 4554 | } | ||
| 4555 | |||
| 4556 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4557 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4558 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4559 | |||
| 4560 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c' | ||
| 4561 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 4562 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2011-04-20 10:00:39 +0000 | ||
| 4563 | @@ -16,5 +16,5 @@ | ||
| 4564 | vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t); | ||
| 4565 | } | ||
| 4566 | |||
| 4567 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4568 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4569 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4570 | |||
| 4571 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c' | ||
| 4572 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 4573 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2011-04-20 10:00:39 +0000 | ||
| 4574 | @@ -16,5 +16,5 @@ | ||
| 4575 | vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t); | ||
| 4576 | } | ||
| 4577 | |||
| 4578 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4579 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4580 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4581 | |||
| 4582 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c' | ||
| 4583 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2010-08-20 13:27:11 +0000 | ||
| 4584 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2011-04-20 10:00:39 +0000 | ||
| 4585 | @@ -16,5 +16,5 @@ | ||
| 4586 | vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t); | ||
| 4587 | } | ||
| 4588 | |||
| 4589 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4590 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4591 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4592 | |||
| 4593 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c' | ||
| 4594 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 4595 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2011-04-20 10:00:39 +0000 | ||
| 4596 | @@ -16,5 +16,5 @@ | ||
| 4597 | vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t); | ||
| 4598 | } | ||
| 4599 | |||
| 4600 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4601 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4602 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4603 | |||
| 4604 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c' | ||
| 4605 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 4606 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 4607 | @@ -16,5 +16,5 @@ | ||
| 4608 | vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); | ||
| 4609 | } | ||
| 4610 | |||
| 4611 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4612 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4613 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4614 | |||
| 4615 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c' | ||
| 4616 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 4617 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 4618 | @@ -16,5 +16,5 @@ | ||
| 4619 | vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); | ||
| 4620 | } | ||
| 4621 | |||
| 4622 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4623 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4624 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4625 | |||
| 4626 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c' | ||
| 4627 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 4628 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2011-04-20 10:00:39 +0000 | ||
| 4629 | @@ -16,5 +16,5 @@ | ||
| 4630 | vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); | ||
| 4631 | } | ||
| 4632 | |||
| 4633 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4634 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4635 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4636 | |||
| 4637 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c' | ||
| 4638 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 4639 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 4640 | @@ -16,5 +16,5 @@ | ||
| 4641 | vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); | ||
| 4642 | } | ||
| 4643 | |||
| 4644 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4645 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4646 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4647 | |||
| 4648 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c' | ||
| 4649 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 4650 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 4651 | @@ -16,5 +16,5 @@ | ||
| 4652 | vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); | ||
| 4653 | } | ||
| 4654 | |||
| 4655 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4656 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4657 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4658 | |||
| 4659 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c' | ||
| 4660 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2010-08-20 13:27:11 +0000 | ||
| 4661 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2011-04-20 10:00:39 +0000 | ||
| 4662 | @@ -16,5 +16,5 @@ | ||
| 4663 | vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); | ||
| 4664 | } | ||
| 4665 | |||
| 4666 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4667 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4668 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4669 | |||
| 4670 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c' | ||
| 4671 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 4672 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2011-04-20 10:00:39 +0000 | ||
| 4673 | @@ -16,5 +16,5 @@ | ||
| 4674 | vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); | ||
| 4675 | } | ||
| 4676 | |||
| 4677 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4678 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4679 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4680 | |||
| 4681 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c' | ||
| 4682 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 4683 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 4684 | @@ -16,5 +16,5 @@ | ||
| 4685 | vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); | ||
| 4686 | } | ||
| 4687 | |||
| 4688 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4689 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4690 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4691 | |||
| 4692 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c' | ||
| 4693 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 4694 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 4695 | @@ -16,5 +16,5 @@ | ||
| 4696 | vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); | ||
| 4697 | } | ||
| 4698 | |||
| 4699 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4700 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4701 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4702 | |||
| 4703 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c' | ||
| 4704 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2010-08-20 13:27:11 +0000 | ||
| 4705 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2011-04-20 10:00:39 +0000 | ||
| 4706 | @@ -16,5 +16,5 @@ | ||
| 4707 | vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); | ||
| 4708 | } | ||
| 4709 | |||
| 4710 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4711 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4712 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4713 | |||
| 4714 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c' | ||
| 4715 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 4716 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2011-04-20 10:00:39 +0000 | ||
| 4717 | @@ -16,5 +16,5 @@ | ||
| 4718 | vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); | ||
| 4719 | } | ||
| 4720 | |||
| 4721 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4722 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4723 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4724 | |||
| 4725 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1f32.c' | ||
| 4726 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2010-08-20 13:27:11 +0000 | ||
| 4727 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2011-04-20 10:00:39 +0000 | ||
| 4728 | @@ -16,5 +16,5 @@ | ||
| 4729 | vst1_f32 (arg0_float32_t, arg1_float32x2_t); | ||
| 4730 | } | ||
| 4731 | |||
| 4732 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4733 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4734 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4735 | |||
| 4736 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p16.c' | ||
| 4737 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2010-08-20 13:27:11 +0000 | ||
| 4738 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2011-04-20 10:00:39 +0000 | ||
| 4739 | @@ -16,5 +16,5 @@ | ||
| 4740 | vst1_p16 (arg0_poly16_t, arg1_poly16x4_t); | ||
| 4741 | } | ||
| 4742 | |||
| 4743 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4744 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4745 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4746 | |||
| 4747 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p8.c' | ||
| 4748 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2010-08-20 13:27:11 +0000 | ||
| 4749 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2011-04-20 10:00:39 +0000 | ||
| 4750 | @@ -16,5 +16,5 @@ | ||
| 4751 | vst1_p8 (arg0_poly8_t, arg1_poly8x8_t); | ||
| 4752 | } | ||
| 4753 | |||
| 4754 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4755 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4756 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4757 | |||
| 4758 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s16.c' | ||
| 4759 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2010-08-20 13:27:11 +0000 | ||
| 4760 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2011-04-20 10:00:39 +0000 | ||
| 4761 | @@ -16,5 +16,5 @@ | ||
| 4762 | vst1_s16 (arg0_int16_t, arg1_int16x4_t); | ||
| 4763 | } | ||
| 4764 | |||
| 4765 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4766 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4767 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4768 | |||
| 4769 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s32.c' | ||
| 4770 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2010-08-20 13:27:11 +0000 | ||
| 4771 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2011-04-20 10:00:39 +0000 | ||
| 4772 | @@ -16,5 +16,5 @@ | ||
| 4773 | vst1_s32 (arg0_int32_t, arg1_int32x2_t); | ||
| 4774 | } | ||
| 4775 | |||
| 4776 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4777 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4778 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4779 | |||
| 4780 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s64.c' | ||
| 4781 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2010-08-20 13:27:11 +0000 | ||
| 4782 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2011-04-20 10:00:39 +0000 | ||
| 4783 | @@ -16,5 +16,5 @@ | ||
| 4784 | vst1_s64 (arg0_int64_t, arg1_int64x1_t); | ||
| 4785 | } | ||
| 4786 | |||
| 4787 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4788 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4789 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4790 | |||
| 4791 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s8.c' | ||
| 4792 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2010-08-20 13:27:11 +0000 | ||
| 4793 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2011-04-20 10:00:39 +0000 | ||
| 4794 | @@ -16,5 +16,5 @@ | ||
| 4795 | vst1_s8 (arg0_int8_t, arg1_int8x8_t); | ||
| 4796 | } | ||
| 4797 | |||
| 4798 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4799 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4800 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4801 | |||
| 4802 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u16.c' | ||
| 4803 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2010-08-20 13:27:11 +0000 | ||
| 4804 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2011-04-20 10:00:39 +0000 | ||
| 4805 | @@ -16,5 +16,5 @@ | ||
| 4806 | vst1_u16 (arg0_uint16_t, arg1_uint16x4_t); | ||
| 4807 | } | ||
| 4808 | |||
| 4809 | -/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4810 | +/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4811 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4812 | |||
| 4813 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u32.c' | ||
| 4814 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2010-08-20 13:27:11 +0000 | ||
| 4815 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2011-04-20 10:00:39 +0000 | ||
| 4816 | @@ -16,5 +16,5 @@ | ||
| 4817 | vst1_u32 (arg0_uint32_t, arg1_uint32x2_t); | ||
| 4818 | } | ||
| 4819 | |||
| 4820 | -/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4821 | +/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4822 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4823 | |||
| 4824 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u64.c' | ||
| 4825 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2010-08-20 13:27:11 +0000 | ||
| 4826 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2011-04-20 10:00:39 +0000 | ||
| 4827 | @@ -16,5 +16,5 @@ | ||
| 4828 | vst1_u64 (arg0_uint64_t, arg1_uint64x1_t); | ||
| 4829 | } | ||
| 4830 | |||
| 4831 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4832 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4833 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4834 | |||
| 4835 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u8.c' | ||
| 4836 | --- old/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2010-08-20 13:27:11 +0000 | ||
| 4837 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2011-04-20 10:00:39 +0000 | ||
| 4838 | @@ -16,5 +16,5 @@ | ||
| 4839 | vst1_u8 (arg0_uint8_t, arg1_uint8x8_t); | ||
| 4840 | } | ||
| 4841 | |||
| 4842 | -/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4843 | +/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4844 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4845 | |||
| 4846 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c' | ||
| 4847 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 4848 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 4849 | @@ -16,5 +16,5 @@ | ||
| 4850 | vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1); | ||
| 4851 | } | ||
| 4852 | |||
| 4853 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4854 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4855 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4856 | |||
| 4857 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c' | ||
| 4858 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 4859 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 4860 | @@ -16,5 +16,5 @@ | ||
| 4861 | vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1); | ||
| 4862 | } | ||
| 4863 | |||
| 4864 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4865 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4866 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4867 | |||
| 4868 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c' | ||
| 4869 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 4870 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 4871 | @@ -16,5 +16,5 @@ | ||
| 4872 | vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1); | ||
| 4873 | } | ||
| 4874 | |||
| 4875 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4876 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4877 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4878 | |||
| 4879 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c' | ||
| 4880 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 4881 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 4882 | @@ -16,5 +16,5 @@ | ||
| 4883 | vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1); | ||
| 4884 | } | ||
| 4885 | |||
| 4886 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4887 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4888 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4889 | |||
| 4890 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c' | ||
| 4891 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 4892 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 4893 | @@ -16,5 +16,5 @@ | ||
| 4894 | vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1); | ||
| 4895 | } | ||
| 4896 | |||
| 4897 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4898 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4899 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4900 | |||
| 4901 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c' | ||
| 4902 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 4903 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 4904 | @@ -16,5 +16,5 @@ | ||
| 4905 | vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1); | ||
| 4906 | } | ||
| 4907 | |||
| 4908 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4909 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4910 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4911 | |||
| 4912 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c' | ||
| 4913 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 4914 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2011-04-20 10:00:39 +0000 | ||
| 4915 | @@ -16,6 +16,6 @@ | ||
| 4916 | vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t); | ||
| 4917 | } | ||
| 4918 | |||
| 4919 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4920 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4921 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4922 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4923 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4924 | |||
| 4925 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c' | ||
| 4926 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 4927 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2011-04-20 10:00:39 +0000 | ||
| 4928 | @@ -16,6 +16,6 @@ | ||
| 4929 | vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t); | ||
| 4930 | } | ||
| 4931 | |||
| 4932 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4933 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4934 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4935 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4936 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4937 | |||
| 4938 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c' | ||
| 4939 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 4940 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2011-04-20 10:00:39 +0000 | ||
| 4941 | @@ -16,6 +16,6 @@ | ||
| 4942 | vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t); | ||
| 4943 | } | ||
| 4944 | |||
| 4945 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4946 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4947 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4948 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4949 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4950 | |||
| 4951 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c' | ||
| 4952 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 4953 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2011-04-20 10:00:39 +0000 | ||
| 4954 | @@ -16,6 +16,6 @@ | ||
| 4955 | vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t); | ||
| 4956 | } | ||
| 4957 | |||
| 4958 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4959 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4960 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4961 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4962 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4963 | |||
| 4964 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c' | ||
| 4965 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 4966 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2011-04-20 10:00:39 +0000 | ||
| 4967 | @@ -16,6 +16,6 @@ | ||
| 4968 | vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t); | ||
| 4969 | } | ||
| 4970 | |||
| 4971 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4972 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4973 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4974 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4975 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4976 | |||
| 4977 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c' | ||
| 4978 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 4979 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2011-04-20 10:00:39 +0000 | ||
| 4980 | @@ -16,6 +16,6 @@ | ||
| 4981 | vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t); | ||
| 4982 | } | ||
| 4983 | |||
| 4984 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4985 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4986 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4987 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4988 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 4989 | |||
| 4990 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c' | ||
| 4991 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 4992 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2011-04-20 10:00:39 +0000 | ||
| 4993 | @@ -16,6 +16,6 @@ | ||
| 4994 | vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t); | ||
| 4995 | } | ||
| 4996 | |||
| 4997 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4998 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 4999 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5000 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5001 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5002 | |||
| 5003 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c' | ||
| 5004 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 5005 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2011-04-20 10:00:39 +0000 | ||
| 5006 | @@ -16,6 +16,6 @@ | ||
| 5007 | vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t); | ||
| 5008 | } | ||
| 5009 | |||
| 5010 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5011 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5012 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5013 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5014 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5015 | |||
| 5016 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c' | ||
| 5017 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 5018 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2011-04-20 10:00:39 +0000 | ||
| 5019 | @@ -16,6 +16,6 @@ | ||
| 5020 | vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t); | ||
| 5021 | } | ||
| 5022 | |||
| 5023 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5024 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5025 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5026 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5027 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5028 | |||
| 5029 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c' | ||
| 5030 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 5031 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 5032 | @@ -16,5 +16,5 @@ | ||
| 5033 | vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1); | ||
| 5034 | } | ||
| 5035 | |||
| 5036 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5037 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5038 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5039 | |||
| 5040 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c' | ||
| 5041 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 5042 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 5043 | @@ -16,5 +16,5 @@ | ||
| 5044 | vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1); | ||
| 5045 | } | ||
| 5046 | |||
| 5047 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5048 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5049 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5050 | |||
| 5051 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c' | ||
| 5052 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 5053 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2011-04-20 10:00:39 +0000 | ||
| 5054 | @@ -16,5 +16,5 @@ | ||
| 5055 | vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1); | ||
| 5056 | } | ||
| 5057 | |||
| 5058 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5059 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5060 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5061 | |||
| 5062 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c' | ||
| 5063 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 5064 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 5065 | @@ -16,5 +16,5 @@ | ||
| 5066 | vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1); | ||
| 5067 | } | ||
| 5068 | |||
| 5069 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5070 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5071 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5072 | |||
| 5073 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c' | ||
| 5074 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 5075 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 5076 | @@ -16,5 +16,5 @@ | ||
| 5077 | vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1); | ||
| 5078 | } | ||
| 5079 | |||
| 5080 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5081 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5082 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5083 | |||
| 5084 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c' | ||
| 5085 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 5086 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2011-04-20 10:00:39 +0000 | ||
| 5087 | @@ -16,5 +16,5 @@ | ||
| 5088 | vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1); | ||
| 5089 | } | ||
| 5090 | |||
| 5091 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5092 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5093 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5094 | |||
| 5095 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c' | ||
| 5096 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 5097 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 5098 | @@ -16,5 +16,5 @@ | ||
| 5099 | vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1); | ||
| 5100 | } | ||
| 5101 | |||
| 5102 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5103 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5104 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5105 | |||
| 5106 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c' | ||
| 5107 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 5108 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 5109 | @@ -16,5 +16,5 @@ | ||
| 5110 | vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1); | ||
| 5111 | } | ||
| 5112 | |||
| 5113 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5114 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5115 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5116 | |||
| 5117 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c' | ||
| 5118 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 5119 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2011-04-20 10:00:39 +0000 | ||
| 5120 | @@ -16,5 +16,5 @@ | ||
| 5121 | vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1); | ||
| 5122 | } | ||
| 5123 | |||
| 5124 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5125 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5126 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5127 | |||
| 5128 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2f32.c' | ||
| 5129 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2010-08-20 13:27:11 +0000 | ||
| 5130 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2011-04-20 10:00:39 +0000 | ||
| 5131 | @@ -16,5 +16,5 @@ | ||
| 5132 | vst2_f32 (arg0_float32_t, arg1_float32x2x2_t); | ||
| 5133 | } | ||
| 5134 | |||
| 5135 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5136 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5137 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5138 | |||
| 5139 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p16.c' | ||
| 5140 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2010-08-20 13:27:11 +0000 | ||
| 5141 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2011-04-20 10:00:39 +0000 | ||
| 5142 | @@ -16,5 +16,5 @@ | ||
| 5143 | vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t); | ||
| 5144 | } | ||
| 5145 | |||
| 5146 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5147 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5148 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5149 | |||
| 5150 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p8.c' | ||
| 5151 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2010-08-20 13:27:11 +0000 | ||
| 5152 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2011-04-20 10:00:39 +0000 | ||
| 5153 | @@ -16,5 +16,5 @@ | ||
| 5154 | vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t); | ||
| 5155 | } | ||
| 5156 | |||
| 5157 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5158 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5159 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5160 | |||
| 5161 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s16.c' | ||
| 5162 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2010-08-20 13:27:11 +0000 | ||
| 5163 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2011-04-20 10:00:39 +0000 | ||
| 5164 | @@ -16,5 +16,5 @@ | ||
| 5165 | vst2_s16 (arg0_int16_t, arg1_int16x4x2_t); | ||
| 5166 | } | ||
| 5167 | |||
| 5168 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5169 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5170 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5171 | |||
| 5172 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s32.c' | ||
| 5173 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2010-08-20 13:27:11 +0000 | ||
| 5174 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2011-04-20 10:00:39 +0000 | ||
| 5175 | @@ -16,5 +16,5 @@ | ||
| 5176 | vst2_s32 (arg0_int32_t, arg1_int32x2x2_t); | ||
| 5177 | } | ||
| 5178 | |||
| 5179 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5180 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5181 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5182 | |||
| 5183 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s64.c' | ||
| 5184 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2010-08-20 13:27:11 +0000 | ||
| 5185 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2011-04-20 10:00:39 +0000 | ||
| 5186 | @@ -16,5 +16,5 @@ | ||
| 5187 | vst2_s64 (arg0_int64_t, arg1_int64x1x2_t); | ||
| 5188 | } | ||
| 5189 | |||
| 5190 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5191 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5192 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5193 | |||
| 5194 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s8.c' | ||
| 5195 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2010-08-20 13:27:11 +0000 | ||
| 5196 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2011-04-20 10:00:39 +0000 | ||
| 5197 | @@ -16,5 +16,5 @@ | ||
| 5198 | vst2_s8 (arg0_int8_t, arg1_int8x8x2_t); | ||
| 5199 | } | ||
| 5200 | |||
| 5201 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5202 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5203 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5204 | |||
| 5205 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u16.c' | ||
| 5206 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2010-08-20 13:27:11 +0000 | ||
| 5207 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2011-04-20 10:00:39 +0000 | ||
| 5208 | @@ -16,5 +16,5 @@ | ||
| 5209 | vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t); | ||
| 5210 | } | ||
| 5211 | |||
| 5212 | -/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5213 | +/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5214 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5215 | |||
| 5216 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u32.c' | ||
| 5217 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2010-08-20 13:27:11 +0000 | ||
| 5218 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2011-04-20 10:00:39 +0000 | ||
| 5219 | @@ -16,5 +16,5 @@ | ||
| 5220 | vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t); | ||
| 5221 | } | ||
| 5222 | |||
| 5223 | -/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5224 | +/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5225 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5226 | |||
| 5227 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u64.c' | ||
| 5228 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2010-08-20 13:27:11 +0000 | ||
| 5229 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2011-04-20 10:00:39 +0000 | ||
| 5230 | @@ -16,5 +16,5 @@ | ||
| 5231 | vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t); | ||
| 5232 | } | ||
| 5233 | |||
| 5234 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5235 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5236 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5237 | |||
| 5238 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u8.c' | ||
| 5239 | --- old/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2010-08-20 13:27:11 +0000 | ||
| 5240 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2011-04-20 10:00:39 +0000 | ||
| 5241 | @@ -16,5 +16,5 @@ | ||
| 5242 | vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t); | ||
| 5243 | } | ||
| 5244 | |||
| 5245 | -/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5246 | +/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5247 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5248 | |||
| 5249 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c' | ||
| 5250 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 5251 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 5252 | @@ -16,5 +16,5 @@ | ||
| 5253 | vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1); | ||
| 5254 | } | ||
| 5255 | |||
| 5256 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5257 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5258 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5259 | |||
| 5260 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c' | ||
| 5261 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 5262 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 5263 | @@ -16,5 +16,5 @@ | ||
| 5264 | vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1); | ||
| 5265 | } | ||
| 5266 | |||
| 5267 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5268 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5269 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5270 | |||
| 5271 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c' | ||
| 5272 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 5273 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 5274 | @@ -16,5 +16,5 @@ | ||
| 5275 | vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1); | ||
| 5276 | } | ||
| 5277 | |||
| 5278 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5279 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5280 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5281 | |||
| 5282 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c' | ||
| 5283 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 5284 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 5285 | @@ -16,5 +16,5 @@ | ||
| 5286 | vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1); | ||
| 5287 | } | ||
| 5288 | |||
| 5289 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5290 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5291 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5292 | |||
| 5293 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c' | ||
| 5294 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 5295 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 5296 | @@ -16,5 +16,5 @@ | ||
| 5297 | vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1); | ||
| 5298 | } | ||
| 5299 | |||
| 5300 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5301 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5302 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5303 | |||
| 5304 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c' | ||
| 5305 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 5306 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 5307 | @@ -16,5 +16,5 @@ | ||
| 5308 | vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1); | ||
| 5309 | } | ||
| 5310 | |||
| 5311 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5312 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5313 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5314 | |||
| 5315 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c' | ||
| 5316 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 5317 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2011-04-20 10:00:39 +0000 | ||
| 5318 | @@ -16,6 +16,6 @@ | ||
| 5319 | vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t); | ||
| 5320 | } | ||
| 5321 | |||
| 5322 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5323 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5324 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5325 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5326 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5327 | |||
| 5328 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c' | ||
| 5329 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 5330 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2011-04-20 10:00:39 +0000 | ||
| 5331 | @@ -16,6 +16,6 @@ | ||
| 5332 | vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t); | ||
| 5333 | } | ||
| 5334 | |||
| 5335 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5336 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5337 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5338 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5339 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5340 | |||
| 5341 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c' | ||
| 5342 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 5343 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2011-04-20 10:00:39 +0000 | ||
| 5344 | @@ -16,6 +16,6 @@ | ||
| 5345 | vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t); | ||
| 5346 | } | ||
| 5347 | |||
| 5348 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5349 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5350 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5351 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5352 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5353 | |||
| 5354 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c' | ||
| 5355 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 5356 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2011-04-20 10:00:39 +0000 | ||
| 5357 | @@ -16,6 +16,6 @@ | ||
| 5358 | vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t); | ||
| 5359 | } | ||
| 5360 | |||
| 5361 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5362 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5363 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5364 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5365 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5366 | |||
| 5367 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c' | ||
| 5368 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 5369 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2011-04-20 10:00:39 +0000 | ||
| 5370 | @@ -16,6 +16,6 @@ | ||
| 5371 | vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t); | ||
| 5372 | } | ||
| 5373 | |||
| 5374 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5375 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5376 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5377 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5378 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5379 | |||
| 5380 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c' | ||
| 5381 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 5382 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2011-04-20 10:00:39 +0000 | ||
| 5383 | @@ -16,6 +16,6 @@ | ||
| 5384 | vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t); | ||
| 5385 | } | ||
| 5386 | |||
| 5387 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5388 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5389 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5390 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5391 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5392 | |||
| 5393 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c' | ||
| 5394 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 5395 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2011-04-20 10:00:39 +0000 | ||
| 5396 | @@ -16,6 +16,6 @@ | ||
| 5397 | vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t); | ||
| 5398 | } | ||
| 5399 | |||
| 5400 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5401 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5402 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5403 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5404 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5405 | |||
| 5406 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c' | ||
| 5407 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 5408 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2011-04-20 10:00:39 +0000 | ||
| 5409 | @@ -16,6 +16,6 @@ | ||
| 5410 | vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t); | ||
| 5411 | } | ||
| 5412 | |||
| 5413 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5414 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5415 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5416 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5417 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5418 | |||
| 5419 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c' | ||
| 5420 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 5421 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2011-04-20 10:00:39 +0000 | ||
| 5422 | @@ -16,6 +16,6 @@ | ||
| 5423 | vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t); | ||
| 5424 | } | ||
| 5425 | |||
| 5426 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5427 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5428 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5429 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5430 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5431 | |||
| 5432 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c' | ||
| 5433 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 5434 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 5435 | @@ -16,5 +16,5 @@ | ||
| 5436 | vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1); | ||
| 5437 | } | ||
| 5438 | |||
| 5439 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5440 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5441 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5442 | |||
| 5443 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c' | ||
| 5444 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 5445 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 5446 | @@ -16,5 +16,5 @@ | ||
| 5447 | vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1); | ||
| 5448 | } | ||
| 5449 | |||
| 5450 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5451 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5452 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5453 | |||
| 5454 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c' | ||
| 5455 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 5456 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2011-04-20 10:00:39 +0000 | ||
| 5457 | @@ -16,5 +16,5 @@ | ||
| 5458 | vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1); | ||
| 5459 | } | ||
| 5460 | |||
| 5461 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5462 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5463 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5464 | |||
| 5465 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c' | ||
| 5466 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 5467 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 5468 | @@ -16,5 +16,5 @@ | ||
| 5469 | vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1); | ||
| 5470 | } | ||
| 5471 | |||
| 5472 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5473 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5474 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5475 | |||
| 5476 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c' | ||
| 5477 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 5478 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 5479 | @@ -16,5 +16,5 @@ | ||
| 5480 | vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1); | ||
| 5481 | } | ||
| 5482 | |||
| 5483 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5484 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5485 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5486 | |||
| 5487 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c' | ||
| 5488 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 5489 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2011-04-20 10:00:39 +0000 | ||
| 5490 | @@ -16,5 +16,5 @@ | ||
| 5491 | vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1); | ||
| 5492 | } | ||
| 5493 | |||
| 5494 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5495 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5496 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5497 | |||
| 5498 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c' | ||
| 5499 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 5500 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 5501 | @@ -16,5 +16,5 @@ | ||
| 5502 | vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1); | ||
| 5503 | } | ||
| 5504 | |||
| 5505 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5506 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5507 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5508 | |||
| 5509 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c' | ||
| 5510 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 5511 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 5512 | @@ -16,5 +16,5 @@ | ||
| 5513 | vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1); | ||
| 5514 | } | ||
| 5515 | |||
| 5516 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5517 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5518 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5519 | |||
| 5520 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c' | ||
| 5521 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 5522 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2011-04-20 10:00:39 +0000 | ||
| 5523 | @@ -16,5 +16,5 @@ | ||
| 5524 | vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1); | ||
| 5525 | } | ||
| 5526 | |||
| 5527 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5528 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5529 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5530 | |||
| 5531 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3f32.c' | ||
| 5532 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2010-08-20 13:27:11 +0000 | ||
| 5533 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2011-04-20 10:00:39 +0000 | ||
| 5534 | @@ -16,5 +16,5 @@ | ||
| 5535 | vst3_f32 (arg0_float32_t, arg1_float32x2x3_t); | ||
| 5536 | } | ||
| 5537 | |||
| 5538 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5539 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5540 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5541 | |||
| 5542 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p16.c' | ||
| 5543 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2010-08-20 13:27:11 +0000 | ||
| 5544 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2011-04-20 10:00:39 +0000 | ||
| 5545 | @@ -16,5 +16,5 @@ | ||
| 5546 | vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t); | ||
| 5547 | } | ||
| 5548 | |||
| 5549 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5550 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5551 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5552 | |||
| 5553 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p8.c' | ||
| 5554 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2010-08-20 13:27:11 +0000 | ||
| 5555 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2011-04-20 10:00:39 +0000 | ||
| 5556 | @@ -16,5 +16,5 @@ | ||
| 5557 | vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t); | ||
| 5558 | } | ||
| 5559 | |||
| 5560 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5561 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5562 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5563 | |||
| 5564 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s16.c' | ||
| 5565 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2010-08-20 13:27:11 +0000 | ||
| 5566 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2011-04-20 10:00:39 +0000 | ||
| 5567 | @@ -16,5 +16,5 @@ | ||
| 5568 | vst3_s16 (arg0_int16_t, arg1_int16x4x3_t); | ||
| 5569 | } | ||
| 5570 | |||
| 5571 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5572 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5573 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5574 | |||
| 5575 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s32.c' | ||
| 5576 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2010-08-20 13:27:11 +0000 | ||
| 5577 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2011-04-20 10:00:39 +0000 | ||
| 5578 | @@ -16,5 +16,5 @@ | ||
| 5579 | vst3_s32 (arg0_int32_t, arg1_int32x2x3_t); | ||
| 5580 | } | ||
| 5581 | |||
| 5582 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5583 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5584 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5585 | |||
| 5586 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s64.c' | ||
| 5587 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2010-08-20 13:27:11 +0000 | ||
| 5588 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2011-04-20 10:00:39 +0000 | ||
| 5589 | @@ -16,5 +16,5 @@ | ||
| 5590 | vst3_s64 (arg0_int64_t, arg1_int64x1x3_t); | ||
| 5591 | } | ||
| 5592 | |||
| 5593 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5594 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5595 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5596 | |||
| 5597 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s8.c' | ||
| 5598 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2010-08-20 13:27:11 +0000 | ||
| 5599 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2011-04-20 10:00:39 +0000 | ||
| 5600 | @@ -16,5 +16,5 @@ | ||
| 5601 | vst3_s8 (arg0_int8_t, arg1_int8x8x3_t); | ||
| 5602 | } | ||
| 5603 | |||
| 5604 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5605 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5606 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5607 | |||
| 5608 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u16.c' | ||
| 5609 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2010-08-20 13:27:11 +0000 | ||
| 5610 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2011-04-20 10:00:39 +0000 | ||
| 5611 | @@ -16,5 +16,5 @@ | ||
| 5612 | vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t); | ||
| 5613 | } | ||
| 5614 | |||
| 5615 | -/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5616 | +/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5617 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5618 | |||
| 5619 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u32.c' | ||
| 5620 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2010-08-20 13:27:11 +0000 | ||
| 5621 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2011-04-20 10:00:39 +0000 | ||
| 5622 | @@ -16,5 +16,5 @@ | ||
| 5623 | vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t); | ||
| 5624 | } | ||
| 5625 | |||
| 5626 | -/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5627 | +/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5628 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5629 | |||
| 5630 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u64.c' | ||
| 5631 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2010-08-20 13:27:11 +0000 | ||
| 5632 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2011-04-20 10:00:39 +0000 | ||
| 5633 | @@ -16,5 +16,5 @@ | ||
| 5634 | vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t); | ||
| 5635 | } | ||
| 5636 | |||
| 5637 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5638 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5639 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5640 | |||
| 5641 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u8.c' | ||
| 5642 | --- old/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2010-08-20 13:27:11 +0000 | ||
| 5643 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2011-04-20 10:00:39 +0000 | ||
| 5644 | @@ -16,5 +16,5 @@ | ||
| 5645 | vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t); | ||
| 5646 | } | ||
| 5647 | |||
| 5648 | -/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5649 | +/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5650 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5651 | |||
| 5652 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c' | ||
| 5653 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 5654 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 5655 | @@ -16,5 +16,5 @@ | ||
| 5656 | vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1); | ||
| 5657 | } | ||
| 5658 | |||
| 5659 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5660 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5661 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5662 | |||
| 5663 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c' | ||
| 5664 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 5665 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 5666 | @@ -16,5 +16,5 @@ | ||
| 5667 | vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1); | ||
| 5668 | } | ||
| 5669 | |||
| 5670 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5671 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5672 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5673 | |||
| 5674 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c' | ||
| 5675 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 5676 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 5677 | @@ -16,5 +16,5 @@ | ||
| 5678 | vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1); | ||
| 5679 | } | ||
| 5680 | |||
| 5681 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5682 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5683 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5684 | |||
| 5685 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c' | ||
| 5686 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 5687 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 5688 | @@ -16,5 +16,5 @@ | ||
| 5689 | vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1); | ||
| 5690 | } | ||
| 5691 | |||
| 5692 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5693 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5694 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5695 | |||
| 5696 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c' | ||
| 5697 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 5698 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 5699 | @@ -16,5 +16,5 @@ | ||
| 5700 | vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1); | ||
| 5701 | } | ||
| 5702 | |||
| 5703 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5704 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5705 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5706 | |||
| 5707 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c' | ||
| 5708 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 5709 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 5710 | @@ -16,5 +16,5 @@ | ||
| 5711 | vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1); | ||
| 5712 | } | ||
| 5713 | |||
| 5714 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5715 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5716 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5717 | |||
| 5718 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c' | ||
| 5719 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2010-08-20 13:27:11 +0000 | ||
| 5720 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2011-04-20 10:00:39 +0000 | ||
| 5721 | @@ -16,6 +16,6 @@ | ||
| 5722 | vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t); | ||
| 5723 | } | ||
| 5724 | |||
| 5725 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5726 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5727 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5728 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5729 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5730 | |||
| 5731 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c' | ||
| 5732 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2010-08-20 13:27:11 +0000 | ||
| 5733 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2011-04-20 10:00:39 +0000 | ||
| 5734 | @@ -16,6 +16,6 @@ | ||
| 5735 | vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t); | ||
| 5736 | } | ||
| 5737 | |||
| 5738 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5739 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5740 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5741 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5742 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5743 | |||
| 5744 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c' | ||
| 5745 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2010-08-20 13:27:11 +0000 | ||
| 5746 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2011-04-20 10:00:39 +0000 | ||
| 5747 | @@ -16,6 +16,6 @@ | ||
| 5748 | vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t); | ||
| 5749 | } | ||
| 5750 | |||
| 5751 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5752 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5753 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5754 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5755 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5756 | |||
| 5757 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c' | ||
| 5758 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2010-08-20 13:27:11 +0000 | ||
| 5759 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2011-04-20 10:00:39 +0000 | ||
| 5760 | @@ -16,6 +16,6 @@ | ||
| 5761 | vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t); | ||
| 5762 | } | ||
| 5763 | |||
| 5764 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5765 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5766 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5767 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5768 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5769 | |||
| 5770 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c' | ||
| 5771 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2010-08-20 13:27:11 +0000 | ||
| 5772 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2011-04-20 10:00:39 +0000 | ||
| 5773 | @@ -16,6 +16,6 @@ | ||
| 5774 | vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t); | ||
| 5775 | } | ||
| 5776 | |||
| 5777 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5778 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5779 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5780 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5781 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5782 | |||
| 5783 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c' | ||
| 5784 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2010-08-20 13:27:11 +0000 | ||
| 5785 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2011-04-20 10:00:39 +0000 | ||
| 5786 | @@ -16,6 +16,6 @@ | ||
| 5787 | vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t); | ||
| 5788 | } | ||
| 5789 | |||
| 5790 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5791 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5792 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5793 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5794 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5795 | |||
| 5796 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c' | ||
| 5797 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2010-08-20 13:27:11 +0000 | ||
| 5798 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2011-04-20 10:00:39 +0000 | ||
| 5799 | @@ -16,6 +16,6 @@ | ||
| 5800 | vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t); | ||
| 5801 | } | ||
| 5802 | |||
| 5803 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5804 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5805 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5806 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5807 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5808 | |||
| 5809 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c' | ||
| 5810 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2010-08-20 13:27:11 +0000 | ||
| 5811 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2011-04-20 10:00:39 +0000 | ||
| 5812 | @@ -16,6 +16,6 @@ | ||
| 5813 | vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t); | ||
| 5814 | } | ||
| 5815 | |||
| 5816 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5817 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5818 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5819 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5820 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5821 | |||
| 5822 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c' | ||
| 5823 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2010-08-20 13:27:11 +0000 | ||
| 5824 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2011-04-20 10:00:39 +0000 | ||
| 5825 | @@ -16,6 +16,6 @@ | ||
| 5826 | vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t); | ||
| 5827 | } | ||
| 5828 | |||
| 5829 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5830 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5831 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5832 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5833 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5834 | |||
| 5835 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c' | ||
| 5836 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2010-08-20 13:27:11 +0000 | ||
| 5837 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2011-04-20 10:00:39 +0000 | ||
| 5838 | @@ -16,5 +16,5 @@ | ||
| 5839 | vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1); | ||
| 5840 | } | ||
| 5841 | |||
| 5842 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5843 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5844 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5845 | |||
| 5846 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c' | ||
| 5847 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2010-08-20 13:27:11 +0000 | ||
| 5848 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2011-04-20 10:00:39 +0000 | ||
| 5849 | @@ -16,5 +16,5 @@ | ||
| 5850 | vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1); | ||
| 5851 | } | ||
| 5852 | |||
| 5853 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5854 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5855 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5856 | |||
| 5857 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c' | ||
| 5858 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2010-08-20 13:27:11 +0000 | ||
| 5859 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2011-04-20 10:00:39 +0000 | ||
| 5860 | @@ -16,5 +16,5 @@ | ||
| 5861 | vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1); | ||
| 5862 | } | ||
| 5863 | |||
| 5864 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5865 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5866 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5867 | |||
| 5868 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c' | ||
| 5869 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2010-08-20 13:27:11 +0000 | ||
| 5870 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2011-04-20 10:00:39 +0000 | ||
| 5871 | @@ -16,5 +16,5 @@ | ||
| 5872 | vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1); | ||
| 5873 | } | ||
| 5874 | |||
| 5875 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5876 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5877 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5878 | |||
| 5879 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c' | ||
| 5880 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2010-08-20 13:27:11 +0000 | ||
| 5881 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2011-04-20 10:00:39 +0000 | ||
| 5882 | @@ -16,5 +16,5 @@ | ||
| 5883 | vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1); | ||
| 5884 | } | ||
| 5885 | |||
| 5886 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5887 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5888 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5889 | |||
| 5890 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c' | ||
| 5891 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2010-08-20 13:27:11 +0000 | ||
| 5892 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2011-04-20 10:00:39 +0000 | ||
| 5893 | @@ -16,5 +16,5 @@ | ||
| 5894 | vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1); | ||
| 5895 | } | ||
| 5896 | |||
| 5897 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5898 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5899 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5900 | |||
| 5901 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c' | ||
| 5902 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2010-08-20 13:27:11 +0000 | ||
| 5903 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2011-04-20 10:00:39 +0000 | ||
| 5904 | @@ -16,5 +16,5 @@ | ||
| 5905 | vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1); | ||
| 5906 | } | ||
| 5907 | |||
| 5908 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5909 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5910 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5911 | |||
| 5912 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c' | ||
| 5913 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2010-08-20 13:27:11 +0000 | ||
| 5914 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2011-04-20 10:00:39 +0000 | ||
| 5915 | @@ -16,5 +16,5 @@ | ||
| 5916 | vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1); | ||
| 5917 | } | ||
| 5918 | |||
| 5919 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5920 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5921 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5922 | |||
| 5923 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c' | ||
| 5924 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2010-08-20 13:27:11 +0000 | ||
| 5925 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2011-04-20 10:00:39 +0000 | ||
| 5926 | @@ -16,5 +16,5 @@ | ||
| 5927 | vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1); | ||
| 5928 | } | ||
| 5929 | |||
| 5930 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5931 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5932 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5933 | |||
| 5934 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4f32.c' | ||
| 5935 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2010-08-20 13:27:11 +0000 | ||
| 5936 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2011-04-20 10:00:39 +0000 | ||
| 5937 | @@ -16,5 +16,5 @@ | ||
| 5938 | vst4_f32 (arg0_float32_t, arg1_float32x2x4_t); | ||
| 5939 | } | ||
| 5940 | |||
| 5941 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5942 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5943 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5944 | |||
| 5945 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p16.c' | ||
| 5946 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2010-08-20 13:27:11 +0000 | ||
| 5947 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2011-04-20 10:00:39 +0000 | ||
| 5948 | @@ -16,5 +16,5 @@ | ||
| 5949 | vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t); | ||
| 5950 | } | ||
| 5951 | |||
| 5952 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5953 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5954 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5955 | |||
| 5956 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p8.c' | ||
| 5957 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2010-08-20 13:27:11 +0000 | ||
| 5958 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2011-04-20 10:00:39 +0000 | ||
| 5959 | @@ -16,5 +16,5 @@ | ||
| 5960 | vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t); | ||
| 5961 | } | ||
| 5962 | |||
| 5963 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5964 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5965 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5966 | |||
| 5967 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s16.c' | ||
| 5968 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2010-08-20 13:27:11 +0000 | ||
| 5969 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2011-04-20 10:00:39 +0000 | ||
| 5970 | @@ -16,5 +16,5 @@ | ||
| 5971 | vst4_s16 (arg0_int16_t, arg1_int16x4x4_t); | ||
| 5972 | } | ||
| 5973 | |||
| 5974 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5975 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5976 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5977 | |||
| 5978 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s32.c' | ||
| 5979 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2010-08-20 13:27:11 +0000 | ||
| 5980 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2011-04-20 10:00:39 +0000 | ||
| 5981 | @@ -16,5 +16,5 @@ | ||
| 5982 | vst4_s32 (arg0_int32_t, arg1_int32x2x4_t); | ||
| 5983 | } | ||
| 5984 | |||
| 5985 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5986 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5987 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5988 | |||
| 5989 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s64.c' | ||
| 5990 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2010-08-20 13:27:11 +0000 | ||
| 5991 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2011-04-20 10:00:39 +0000 | ||
| 5992 | @@ -16,5 +16,5 @@ | ||
| 5993 | vst4_s64 (arg0_int64_t, arg1_int64x1x4_t); | ||
| 5994 | } | ||
| 5995 | |||
| 5996 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5997 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 5998 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 5999 | |||
| 6000 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s8.c' | ||
| 6001 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2010-08-20 13:27:11 +0000 | ||
| 6002 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2011-04-20 10:00:39 +0000 | ||
| 6003 | @@ -16,5 +16,5 @@ | ||
| 6004 | vst4_s8 (arg0_int8_t, arg1_int8x8x4_t); | ||
| 6005 | } | ||
| 6006 | |||
| 6007 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6008 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6009 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6010 | |||
| 6011 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u16.c' | ||
| 6012 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2010-08-20 13:27:11 +0000 | ||
| 6013 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2011-04-20 10:00:39 +0000 | ||
| 6014 | @@ -16,5 +16,5 @@ | ||
| 6015 | vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t); | ||
| 6016 | } | ||
| 6017 | |||
| 6018 | -/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6019 | +/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6020 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6021 | |||
| 6022 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u32.c' | ||
| 6023 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2010-08-20 13:27:11 +0000 | ||
| 6024 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2011-04-20 10:00:39 +0000 | ||
| 6025 | @@ -16,5 +16,5 @@ | ||
| 6026 | vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t); | ||
| 6027 | } | ||
| 6028 | |||
| 6029 | -/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6030 | +/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6031 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6032 | |||
| 6033 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u64.c' | ||
| 6034 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2010-08-20 13:27:11 +0000 | ||
| 6035 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2011-04-20 10:00:39 +0000 | ||
| 6036 | @@ -16,5 +16,5 @@ | ||
| 6037 | vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t); | ||
| 6038 | } | ||
| 6039 | |||
| 6040 | -/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6041 | +/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6042 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6043 | |||
| 6044 | === modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u8.c' | ||
| 6045 | --- old/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2010-08-20 13:27:11 +0000 | ||
| 6046 | +++ new/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2011-04-20 10:00:39 +0000 | ||
| 6047 | @@ -16,5 +16,5 @@ | ||
| 6048 | vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t); | ||
| 6049 | } | ||
| 6050 | |||
| 6051 | -/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6052 | +/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@.*\)?\n" } } */ | ||
| 6053 | /* { dg-final { cleanup-saved-temps } } */ | ||
| 6054 | |||
| 6055 | === added file 'gcc/testsuite/gcc.target/arm/pr46329.c' | ||
| 6056 | --- old/gcc/testsuite/gcc.target/arm/pr46329.c 1970-01-01 00:00:00 +0000 | ||
| 6057 | +++ new/gcc/testsuite/gcc.target/arm/pr46329.c 2011-05-03 12:49:58 +0000 | ||
| 6058 | @@ -0,0 +1,11 @@ | ||
| 6059 | +/* { dg-do compile } */ | ||
| 6060 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 6061 | +/* { dg-options "-O2" } */ | ||
| 6062 | +/* { dg-add-options arm_neon } */ | ||
| 6063 | + | ||
| 6064 | +int __attribute__ ((vector_size (32))) x; | ||
| 6065 | +void | ||
| 6066 | +foo (void) | ||
| 6067 | +{ | ||
| 6068 | + x <<= x; | ||
| 6069 | +} | ||
| 6070 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99504.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99504.patch deleted file mode 100644 index b287c4da3..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99504.patch +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | Remove the following | ||
| 2 | |||
| 3 | 2011-04-20 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 4 | |||
| 5 | gcc/testsuite/ | ||
| 6 | From Richard Earnshaw <rearnsha@arm.com> | ||
| 7 | |||
| 8 | PR target/46329 | ||
| 9 | * gcc.target/arm/pr46329.c: New test. | ||
| 10 | |||
| 11 | === removed file 'gcc/testsuite/gcc.target/arm/pr46329.c' | ||
| 12 | --- old/gcc/testsuite/gcc.target/arm/pr46329.c 2011-05-03 12:49:58 +0000 | ||
| 13 | +++ new/gcc/testsuite/gcc.target/arm/pr46329.c 1970-01-01 00:00:00 +0000 | ||
| 14 | @@ -1,11 +0,0 @@ | ||
| 15 | -/* { dg-do compile } */ | ||
| 16 | -/* { dg-require-effective-target arm_neon_ok } */ | ||
| 17 | -/* { dg-options "-O2" } */ | ||
| 18 | -/* { dg-add-options arm_neon } */ | ||
| 19 | - | ||
| 20 | -int __attribute__ ((vector_size (32))) x; | ||
| 21 | -void | ||
| 22 | -foo (void) | ||
| 23 | -{ | ||
| 24 | - x <<= x; | ||
| 25 | -} | ||
| 26 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99506.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99506.patch deleted file mode 100644 index 9432f4c0a..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99506.patch +++ /dev/null | |||
| @@ -1,21 +0,0 @@ | |||
| 1 | 2011-05-06 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | From Sergey Grechanik <mouseentity@ispras.ru>, approved for mainline | ||
| 5 | |||
| 6 | * config/arm/arm.c (coproc_secondary_reload_class): Return NO_REGS | ||
| 7 | for constant vectors. | ||
| 8 | |||
| 9 | === modified file 'gcc/config/arm/arm.c' | ||
| 10 | --- old/gcc/config/arm/arm.c 2011-04-20 10:10:50 +0000 | ||
| 11 | +++ new/gcc/config/arm/arm.c 2011-05-04 15:13:02 +0000 | ||
| 12 | @@ -9353,7 +9353,7 @@ | ||
| 13 | /* The neon move patterns handle all legitimate vector and struct | ||
| 14 | addresses. */ | ||
| 15 | if (TARGET_NEON | ||
| 16 | - && MEM_P (x) | ||
| 17 | + && (MEM_P (x) || GET_CODE (x) == CONST_VECTOR) | ||
| 18 | && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT | ||
| 19 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT | ||
| 20 | || VALID_NEON_STRUCT_MODE (mode))) | ||
| 21 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99507.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99507.patch deleted file mode 100644 index f3d5eee6e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99507.patch +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | 2011-05-03 Tom de Vries <tom@codesourcery.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * stmt.c (set_jump_prob): Make robust against *inv_scale == 0. | ||
| 5 | |||
| 6 | === modified file 'gcc/stmt.c' | ||
| 7 | --- old/gcc/stmt.c 2011-02-07 13:23:30 +0000 | ||
| 8 | +++ new/gcc/stmt.c 2011-05-06 19:17:34 +0000 | ||
| 9 | @@ -2312,7 +2312,9 @@ | ||
| 10 | set_jump_prob (rtx jump, int prob, int *inv_scale) | ||
| 11 | { | ||
| 12 | /* j[i] = p[i] * scale / REG_BR_PROB_BASE. */ | ||
| 13 | - int jump_prob = prob * REG_BR_PROB_BASE / *inv_scale; | ||
| 14 | + int jump_prob = (*inv_scale > 0 | ||
| 15 | + ? prob * REG_BR_PROB_BASE / *inv_scale | ||
| 16 | + : REG_BR_PROB_BASE / 2); | ||
| 17 | /* f[i] = REG_BR_PROB_BASE - j[i]. */ | ||
| 18 | int fallthrough_prob = REG_BR_PROB_BASE - jump_prob; | ||
| 19 | |||
| 20 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99510.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99510.patch deleted file mode 100644 index b4e4e883a..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99510.patch +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | 2011-05-13 Michael Hope <michael.hope@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | Backport from mainline: | ||
| 5 | |||
| 6 | 2011-05-05 Michael Hope <michael.hope@linaro.org> | ||
| 7 | |||
| 8 | PR pch/45979 | ||
| 9 | * config/host-linux.c (TRY_EMPTY_VM_SPACE): Define for | ||
| 10 | __ARM_EABI__ hosts. | ||
| 11 | |||
| 12 | === modified file 'gcc/config/host-linux.c' | ||
| 13 | --- old/gcc/config/host-linux.c 2009-02-20 15:20:38 +0000 | ||
| 14 | +++ new/gcc/config/host-linux.c 2011-05-06 20:16:10 +0000 | ||
| 15 | @@ -86,6 +86,8 @@ | ||
| 16 | # define TRY_EMPTY_VM_SPACE 0x60000000 | ||
| 17 | #elif defined(__mc68000__) | ||
| 18 | # define TRY_EMPTY_VM_SPACE 0x40000000 | ||
| 19 | +#elif defined(__ARM_EABI__) | ||
| 20 | +# define TRY_EMPTY_VM_SPACE 0x60000000 | ||
| 21 | #else | ||
| 22 | # define TRY_EMPTY_VM_SPACE 0 | ||
| 23 | #endif | ||
| 24 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99511.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99511.patch deleted file mode 100644 index 8d096c25d..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99511.patch +++ /dev/null | |||
| @@ -1,582 +0,0 @@ | |||
| 1 | 2011-05-13 Revital Eres <revital.eres@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * loop-doloop.c (doloop_condition_get): Support new form of | ||
| 5 | doloop pattern and use prev_nondebug_insn instead of PREV_INSN. | ||
| 6 | * config/arm/thumb2.md (*thumb2_addsi3_compare0): Remove "*". | ||
| 7 | (doloop_end): New. | ||
| 8 | * config/arm/arm.md (*addsi3_compare0): Remove "*". | ||
| 9 | * params.def (sms-min-sc): New param flag. | ||
| 10 | * doc/invoke.texi (sms-min-sc): Document it. | ||
| 11 | * ddg.c (create_ddg_dep_from_intra_loop_link): If a true dep edge | ||
| 12 | enters the branch create an anti edge in the opposite direction | ||
| 13 | to prevent the creation of reg-moves. | ||
| 14 | (get_node_of_insn_uid, check_closing_branch_deps): Delete | ||
| 15 | functions. | ||
| 16 | (create_ddg): Restore previous definition and implementation. | ||
| 17 | * ddg.h (create_ddg): Restore previous definition. | ||
| 18 | * modulo-sched.c: Adjust comment to reflect the fact we are | ||
| 19 | scheduling closing branch. | ||
| 20 | (PS_STAGE_COUNT): Rename to CALC_STAGE_COUNT and redefine. | ||
| 21 | (stage_count): New field in struct partial_schedule. | ||
| 22 | (calculate_stage_count): New function. | ||
| 23 | (normalize_sched_times): Rename to reset_sched_times and handle | ||
| 24 | incrementing the sched time of the nodes by a constant value | ||
| 25 | passed as parameter. | ||
| 26 | (duplicate_insns_of_cycles): Skip closing branch. | ||
| 27 | (sms_schedule_by_order): Schedule closing branch. | ||
| 28 | (ps_insn_find_column): Handle closing branch. | ||
| 29 | (sms_schedule): Call reset_sched_times and adjust the code to | ||
| 30 | support scheduling of the closing branch. Use sms-min-sc. | ||
| 31 | Support new form of doloop pattern. | ||
| 32 | (ps_insert_empty_row): Update calls to normalize_sched_times | ||
| 33 | and rotate_partial_schedule functions. | ||
| 34 | (mark_doloop_insns): Remove. | ||
| 35 | |||
| 36 | === modified file 'gcc/ddg.c' | ||
| 37 | --- old/gcc/ddg.c 2011-03-24 07:45:38 +0000 | ||
| 38 | +++ new/gcc/ddg.c 2011-05-11 08:00:14 +0000 | ||
| 39 | @@ -60,8 +60,6 @@ | ||
| 40 | static ddg_edge_ptr create_ddg_edge (ddg_node_ptr, ddg_node_ptr, dep_type, | ||
| 41 | dep_data_type, int, int); | ||
| 42 | static void add_edge_to_ddg (ddg_ptr g, ddg_edge_ptr); | ||
| 43 | -static ddg_node_ptr get_node_of_insn_uid (ddg_ptr, int); | ||
| 44 | - | ||
| 45 | |||
| 46 | /* Auxiliary variable for mem_read_insn_p/mem_write_insn_p. */ | ||
| 47 | static bool mem_ref_p; | ||
| 48 | @@ -199,6 +197,11 @@ | ||
| 49 | } | ||
| 50 | } | ||
| 51 | |||
| 52 | + /* If a true dep edge enters the branch create an anti edge in the | ||
| 53 | + opposite direction to prevent the creation of reg-moves. */ | ||
| 54 | + if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn)) | ||
| 55 | + create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1); | ||
| 56 | + | ||
| 57 | latency = dep_cost (link); | ||
| 58 | e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance); | ||
| 59 | add_edge_to_ddg (g, e); | ||
| 60 | @@ -452,65 +455,12 @@ | ||
| 61 | sched_free_deps (head, tail, false); | ||
| 62 | } | ||
| 63 | |||
| 64 | -/* Given DOLOOP_INSNS which holds the instructions that | ||
| 65 | - belong to the do-loop part; mark closing_branch_deps field in ddg G | ||
| 66 | - as TRUE if the do-loop part's instructions are dependent on the other | ||
| 67 | - loop instructions. Otherwise mark it as FALSE. */ | ||
| 68 | -static void | ||
| 69 | -check_closing_branch_deps (ddg_ptr g, sbitmap doloop_insns) | ||
| 70 | -{ | ||
| 71 | - sbitmap_iterator sbi; | ||
| 72 | - unsigned int u = 0; | ||
| 73 | - | ||
| 74 | - EXECUTE_IF_SET_IN_SBITMAP (doloop_insns, 0, u, sbi) | ||
| 75 | - { | ||
| 76 | - ddg_edge_ptr e; | ||
| 77 | - ddg_node_ptr u_node = get_node_of_insn_uid (g, u); | ||
| 78 | - | ||
| 79 | - gcc_assert (u_node); | ||
| 80 | - | ||
| 81 | - for (e = u_node->in; e != 0; e = e->next_in) | ||
| 82 | - { | ||
| 83 | - ddg_node_ptr v_node = e->src; | ||
| 84 | - | ||
| 85 | - if (((unsigned int) INSN_UID (v_node->insn) == u) | ||
| 86 | - || DEBUG_INSN_P (v_node->insn)) | ||
| 87 | - continue; | ||
| 88 | - | ||
| 89 | - /* Ignore dependencies between memory writes and the | ||
| 90 | - jump. */ | ||
| 91 | - if (JUMP_P (u_node->insn) | ||
| 92 | - && e->type == OUTPUT_DEP | ||
| 93 | - && mem_write_insn_p (v_node->insn)) | ||
| 94 | - continue; | ||
| 95 | - if (!TEST_BIT (doloop_insns, INSN_UID (v_node->insn))) | ||
| 96 | - { | ||
| 97 | - g->closing_branch_deps = 1; | ||
| 98 | - return; | ||
| 99 | - } | ||
| 100 | - } | ||
| 101 | - for (e = u_node->out; e != 0; e = e->next_out) | ||
| 102 | - { | ||
| 103 | - ddg_node_ptr v_node = e->dest; | ||
| 104 | - | ||
| 105 | - if (((unsigned int) INSN_UID (v_node->insn) == u) | ||
| 106 | - || DEBUG_INSN_P (v_node->insn)) | ||
| 107 | - continue; | ||
| 108 | - if (!TEST_BIT (doloop_insns, INSN_UID (v_node->insn))) | ||
| 109 | - { | ||
| 110 | - g->closing_branch_deps = 1; | ||
| 111 | - return; | ||
| 112 | - } | ||
| 113 | - } | ||
| 114 | - } | ||
| 115 | - g->closing_branch_deps = 0; | ||
| 116 | -} | ||
| 117 | |||
| 118 | /* Given a basic block, create its DDG and return a pointer to a variable | ||
| 119 | of ddg type that represents it. | ||
| 120 | Initialize the ddg structure fields to the appropriate values. */ | ||
| 121 | ddg_ptr | ||
| 122 | -create_ddg (basic_block bb, sbitmap doloop_insns) | ||
| 123 | +create_ddg (basic_block bb, int closing_branch_deps) | ||
| 124 | { | ||
| 125 | ddg_ptr g; | ||
| 126 | rtx insn, first_note; | ||
| 127 | @@ -520,6 +470,7 @@ | ||
| 128 | g = (ddg_ptr) xcalloc (1, sizeof (struct ddg)); | ||
| 129 | |||
| 130 | g->bb = bb; | ||
| 131 | + g->closing_branch_deps = closing_branch_deps; | ||
| 132 | |||
| 133 | /* Count the number of insns in the BB. */ | ||
| 134 | for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); | ||
| 135 | @@ -592,11 +543,6 @@ | ||
| 136 | /* Build the data dependency graph. */ | ||
| 137 | build_intra_loop_deps (g); | ||
| 138 | build_inter_loop_deps (g); | ||
| 139 | - | ||
| 140 | - /* Check whether the do-loop part is decoupled from the other loop | ||
| 141 | - instructions. */ | ||
| 142 | - check_closing_branch_deps (g, doloop_insns); | ||
| 143 | - | ||
| 144 | return g; | ||
| 145 | } | ||
| 146 | |||
| 147 | @@ -890,18 +836,6 @@ | ||
| 148 | return NULL; | ||
| 149 | } | ||
| 150 | |||
| 151 | -/* Given the uid of an instruction UID return the node that represents it. */ | ||
| 152 | -static ddg_node_ptr | ||
| 153 | -get_node_of_insn_uid (ddg_ptr g, int uid) | ||
| 154 | -{ | ||
| 155 | - int i; | ||
| 156 | - | ||
| 157 | - for (i = 0; i < g->num_nodes; i++) | ||
| 158 | - if (uid == INSN_UID (g->nodes[i].insn)) | ||
| 159 | - return &g->nodes[i]; | ||
| 160 | - return NULL; | ||
| 161 | -} | ||
| 162 | - | ||
| 163 | /* Given a set OPS of nodes in the DDG, find the set of their successors | ||
| 164 | which are not in OPS, and set their bits in SUCC. Bits corresponding to | ||
| 165 | OPS are cleared from SUCC. Leaves the other bits in SUCC unchanged. */ | ||
| 166 | |||
| 167 | === modified file 'gcc/ddg.h' | ||
| 168 | --- old/gcc/ddg.h 2011-03-24 07:45:38 +0000 | ||
| 169 | +++ new/gcc/ddg.h 2011-05-11 08:00:14 +0000 | ||
| 170 | @@ -167,7 +167,7 @@ | ||
| 171 | }; | ||
| 172 | |||
| 173 | |||
| 174 | -ddg_ptr create_ddg (basic_block, sbitmap); | ||
| 175 | +ddg_ptr create_ddg (basic_block, int closing_branch_deps); | ||
| 176 | void free_ddg (ddg_ptr); | ||
| 177 | |||
| 178 | void print_ddg (FILE *, ddg_ptr); | ||
| 179 | |||
| 180 | === modified file 'gcc/doc/invoke.texi' | ||
| 181 | --- old/gcc/doc/invoke.texi 2011-04-17 23:04:58 +0000 | ||
| 182 | +++ new/gcc/doc/invoke.texi 2011-05-11 08:00:14 +0000 | ||
| 183 | @@ -8430,6 +8430,10 @@ | ||
| 184 | The maximum number of best instructions in the ready list that are considered | ||
| 185 | for renaming in the selective scheduler. The default value is 2. | ||
| 186 | |||
| 187 | +@item sms-min-sc | ||
| 188 | +The minimum value of stage count that swing modulo scheduler will | ||
| 189 | +generate. The default value is 2. | ||
| 190 | + | ||
| 191 | @item max-last-value-rtl | ||
| 192 | The maximum size measured as number of RTLs that can be recorded in an expression | ||
| 193 | in combiner for a pseudo register as last known value of that register. The default | ||
| 194 | |||
| 195 | === modified file 'gcc/modulo-sched.c' | ||
| 196 | --- old/gcc/modulo-sched.c 2011-03-24 07:45:38 +0000 | ||
| 197 | +++ new/gcc/modulo-sched.c 2011-05-11 08:00:14 +0000 | ||
| 198 | @@ -84,14 +84,13 @@ | ||
| 199 | II cycles (i.e. use register copies to prevent a def from overwriting | ||
| 200 | itself before reaching the use). | ||
| 201 | |||
| 202 | - SMS works with countable loops (1) whose control part can be easily | ||
| 203 | - decoupled from the rest of the loop and (2) whose loop count can | ||
| 204 | - be easily adjusted. This is because we peel a constant number of | ||
| 205 | - iterations into a prologue and epilogue for which we want to avoid | ||
| 206 | - emitting the control part, and a kernel which is to iterate that | ||
| 207 | - constant number of iterations less than the original loop. So the | ||
| 208 | - control part should be a set of insns clearly identified and having | ||
| 209 | - its own iv, not otherwise used in the loop (at-least for now), which | ||
| 210 | + SMS works with countable loops whose loop count can be easily | ||
| 211 | + adjusted. This is because we peel a constant number of iterations | ||
| 212 | + into a prologue and epilogue for which we want to avoid emitting | ||
| 213 | + the control part, and a kernel which is to iterate that constant | ||
| 214 | + number of iterations less than the original loop. So the control | ||
| 215 | + part should be a set of insns clearly identified and having its | ||
| 216 | + own iv, not otherwise used in the loop (at-least for now), which | ||
| 217 | initializes a register before the loop to the number of iterations. | ||
| 218 | Currently SMS relies on the do-loop pattern to recognize such loops, | ||
| 219 | where (1) the control part comprises of all insns defining and/or | ||
| 220 | @@ -116,7 +115,7 @@ | ||
| 221 | |||
| 222 | /* The number of different iterations the nodes in ps span, assuming | ||
| 223 | the stage boundaries are placed efficiently. */ | ||
| 224 | -#define CALC_STAGE_COUNT(min_cycle,max_cycle,ii) ((max_cycle - min_cycle \ | ||
| 225 | +#define CALC_STAGE_COUNT(max_cycle,min_cycle,ii) ((max_cycle - min_cycle \ | ||
| 226 | + 1 + ii - 1) / ii) | ||
| 227 | /* The stage count of ps. */ | ||
| 228 | #define PS_STAGE_COUNT(ps) (((partial_schedule_ptr)(ps))->stage_count) | ||
| 229 | @@ -200,7 +199,6 @@ | ||
| 230 | static void duplicate_insns_of_cycles (partial_schedule_ptr, | ||
| 231 | int, int, int, rtx); | ||
| 232 | static int calculate_stage_count (partial_schedule_ptr ps); | ||
| 233 | - | ||
| 234 | #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap) | ||
| 235 | #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time) | ||
| 236 | #define SCHED_FIRST_REG_MOVE(x) \ | ||
| 237 | @@ -318,7 +316,7 @@ | ||
| 238 | : prev_nondebug_insn (tail)); | ||
| 239 | |||
| 240 | for (insn = head; insn != first_insn_not_to_check; insn = NEXT_INSN (insn)) | ||
| 241 | - if (reg_mentioned_p (reg, insn) && NONDEBUG_INSN_P (insn)) | ||
| 242 | + if (reg_mentioned_p (reg, insn) && !DEBUG_INSN_P (insn)) | ||
| 243 | { | ||
| 244 | if (dump_file) | ||
| 245 | { | ||
| 246 | @@ -337,24 +335,6 @@ | ||
| 247 | #endif | ||
| 248 | } | ||
| 249 | |||
| 250 | -/* Mark in DOLOOP_INSNS the instructions that belong to the do-loop part. | ||
| 251 | - Use TAIL to recognize that part. */ | ||
| 252 | -static void | ||
| 253 | -mark_doloop_insns (sbitmap doloop_insns, rtx tail) | ||
| 254 | -{ | ||
| 255 | - rtx first_insn_not_to_check, insn; | ||
| 256 | - | ||
| 257 | - /* This is the first instruction which belongs the doloop part. */ | ||
| 258 | - first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail | ||
| 259 | - : prev_nondebug_insn (tail)); | ||
| 260 | - | ||
| 261 | - sbitmap_zero (doloop_insns); | ||
| 262 | - for (insn = first_insn_not_to_check; insn != NEXT_INSN (tail); | ||
| 263 | - insn = NEXT_INSN (insn)) | ||
| 264 | - if (NONDEBUG_INSN_P (insn)) | ||
| 265 | - SET_BIT (doloop_insns, INSN_UID (insn)); | ||
| 266 | -} | ||
| 267 | - | ||
| 268 | /* Check if COUNT_REG is set to a constant in the PRE_HEADER block, so | ||
| 269 | that the number of iterations is a compile-time constant. If so, | ||
| 270 | return the rtx that sets COUNT_REG to a constant, and set COUNT to | ||
| 271 | @@ -607,44 +587,42 @@ | ||
| 272 | ddg_node_ptr u = crr_insn->node; | ||
| 273 | int normalized_time = SCHED_TIME (u) - amount; | ||
| 274 | int new_min_cycle = PS_MIN_CYCLE (ps) - amount; | ||
| 275 | - /* The first cycle in row zero after the rotation. */ | ||
| 276 | - int new_first_cycle_in_row_zero = | ||
| 277 | - new_min_cycle + ii - SMODULO (new_min_cycle, ii); | ||
| 278 | + int sc_until_cycle_zero, stage; | ||
| 279 | |||
| 280 | - if (dump_file) | ||
| 281 | - fprintf (dump_file, "crr_insn->node=%d, crr_insn->cycle=%d,\ | ||
| 282 | - min_cycle=%d\n", crr_insn->node->cuid, SCHED_TIME | ||
| 283 | - (u), ps->min_cycle); | ||
| 284 | + if (dump_file) | ||
| 285 | + { | ||
| 286 | + /* Print the scheduling times after the rotation. */ | ||
| 287 | + fprintf (dump_file, "crr_insn->node=%d (insn id %d), " | ||
| 288 | + "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid, | ||
| 289 | + INSN_UID (crr_insn->node->insn), SCHED_TIME (u), | ||
| 290 | + normalized_time); | ||
| 291 | + if (JUMP_P (crr_insn->node->insn)) | ||
| 292 | + fprintf (dump_file, " (branch)"); | ||
| 293 | + fprintf (dump_file, "\n"); | ||
| 294 | + } | ||
| 295 | + | ||
| 296 | gcc_assert (SCHED_TIME (u) >= ps->min_cycle); | ||
| 297 | gcc_assert (SCHED_TIME (u) <= ps->max_cycle); | ||
| 298 | SCHED_TIME (u) = normalized_time; | ||
| 299 | - crr_insn->cycle = normalized_time; | ||
| 300 | SCHED_ROW (u) = SMODULO (normalized_time, ii); | ||
| 301 | - | ||
| 302 | - /* If min_cycle is in row zero after the rotation then | ||
| 303 | - the stage count can be calculated by dividing the cycle | ||
| 304 | - with ii. Otherwise, the calculation is done by dividing the | ||
| 305 | - SMSed kernel into two intervals: | ||
| 306 | - | ||
| 307 | - 1) min_cycle <= interval 0 < first_cycle_in_row_zero | ||
| 308 | - 2) first_cycle_in_row_zero <= interval 1 < max_cycle | ||
| 309 | - | ||
| 310 | - Cycles in interval 0 are in stage 0. The stage of cycles | ||
| 311 | - in interval 1 should be added by 1 to take interval 0 into | ||
| 312 | - account. */ | ||
| 313 | - if (SMODULO (new_min_cycle, ii) == 0) | ||
| 314 | - SCHED_STAGE (u) = normalized_time / ii; | ||
| 315 | - else | ||
| 316 | - { | ||
| 317 | - if (crr_insn->cycle < new_first_cycle_in_row_zero) | ||
| 318 | - SCHED_STAGE (u) = 0; | ||
| 319 | - else | ||
| 320 | - SCHED_STAGE (u) = | ||
| 321 | - ((SCHED_TIME (u) - new_first_cycle_in_row_zero) / ii) + 1; | ||
| 322 | + | ||
| 323 | + /* The calculation of stage count is done adding the number | ||
| 324 | + of stages before cycle zero and after cycle zero. */ | ||
| 325 | + sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii); | ||
| 326 | + | ||
| 327 | + if (SCHED_TIME (u) < 0) | ||
| 328 | + { | ||
| 329 | + stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii); | ||
| 330 | + SCHED_STAGE (u) = sc_until_cycle_zero - stage; | ||
| 331 | + } | ||
| 332 | + else | ||
| 333 | + { | ||
| 334 | + stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii); | ||
| 335 | + SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1; | ||
| 336 | } | ||
| 337 | } | ||
| 338 | } | ||
| 339 | - | ||
| 340 | + | ||
| 341 | /* Set SCHED_COLUMN of each node according to its position in PS. */ | ||
| 342 | static void | ||
| 343 | set_columns_for_ps (partial_schedule_ptr ps) | ||
| 344 | @@ -694,8 +672,8 @@ | ||
| 345 | |||
| 346 | /* Do not duplicate any insn which refers to count_reg as it | ||
| 347 | belongs to the control part. | ||
| 348 | - If closing_branch_deps is true the closing branch is scheduled | ||
| 349 | - as well and thus should be ignored. | ||
| 350 | + The closing branch is scheduled as well and thus should | ||
| 351 | + be ignored. | ||
| 352 | TODO: This should be done by analyzing the control part of | ||
| 353 | the loop. */ | ||
| 354 | if (reg_mentioned_p (count_reg, u_node->insn) | ||
| 355 | @@ -945,8 +923,7 @@ | ||
| 356 | basic_block condition_bb = NULL; | ||
| 357 | edge latch_edge; | ||
| 358 | gcov_type trip_count = 0; | ||
| 359 | - sbitmap doloop_insns; | ||
| 360 | - | ||
| 361 | + | ||
| 362 | loop_optimizer_init (LOOPS_HAVE_PREHEADERS | ||
| 363 | | LOOPS_HAVE_RECORDED_EXITS); | ||
| 364 | if (number_of_loops () <= 1) | ||
| 365 | @@ -971,7 +948,6 @@ | ||
| 366 | setup_sched_infos (); | ||
| 367 | haifa_sched_init (); | ||
| 368 | |||
| 369 | - doloop_insns = sbitmap_alloc (get_max_uid () + 1); | ||
| 370 | /* Allocate memory to hold the DDG array one entry for each loop. | ||
| 371 | We use loop->num as index into this array. */ | ||
| 372 | g_arr = XCNEWVEC (ddg_ptr, number_of_loops ()); | ||
| 373 | @@ -1104,16 +1080,18 @@ | ||
| 374 | |||
| 375 | continue; | ||
| 376 | } | ||
| 377 | - mark_doloop_insns (doloop_insns, tail); | ||
| 378 | - if (! (g = create_ddg (bb, doloop_insns))) | ||
| 379 | + | ||
| 380 | + /* Always schedule the closing branch with the rest of the | ||
| 381 | + instructions. The branch is rotated to be in row ii-1 at the | ||
| 382 | + end of the scheduling procedure to make sure it's the last | ||
| 383 | + instruction in the iteration. */ | ||
| 384 | + if (! (g = create_ddg (bb, 1))) | ||
| 385 | { | ||
| 386 | if (dump_file) | ||
| 387 | fprintf (dump_file, "SMS create_ddg failed\n"); | ||
| 388 | continue; | ||
| 389 | } | ||
| 390 | - if (dump_file) | ||
| 391 | - fprintf (dump_file, "SMS closing_branch_deps: %d\n", | ||
| 392 | - g->closing_branch_deps); | ||
| 393 | + | ||
| 394 | g_arr[loop->num] = g; | ||
| 395 | if (dump_file) | ||
| 396 | fprintf (dump_file, "...OK\n"); | ||
| 397 | @@ -1215,16 +1193,17 @@ | ||
| 398 | |||
| 399 | ps = sms_schedule_by_order (g, mii, maxii, node_order); | ||
| 400 | |||
| 401 | - if (ps) | ||
| 402 | - { | ||
| 403 | - stage_count = calculate_stage_count (ps); | ||
| 404 | - gcc_assert(stage_count >= 1); | ||
| 405 | - PS_STAGE_COUNT(ps) = stage_count; | ||
| 406 | - } | ||
| 407 | - | ||
| 408 | - /* Stage count of 1 means that there is no interleaving between | ||
| 409 | - iterations, let the scheduling passes do the job. */ | ||
| 410 | - if (stage_count <= 1 | ||
| 411 | + if (ps) | ||
| 412 | + { | ||
| 413 | + stage_count = calculate_stage_count (ps); | ||
| 414 | + gcc_assert(stage_count >= 1); | ||
| 415 | + PS_STAGE_COUNT(ps) = stage_count; | ||
| 416 | + } | ||
| 417 | + | ||
| 418 | + /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of | ||
| 419 | + 1 means that there is no interleaving between iterations thus | ||
| 420 | + we let the scheduling passes do the job in this case. */ | ||
| 421 | + if (stage_count < (unsigned) PARAM_VALUE (PARAM_SMS_MIN_SC) | ||
| 422 | || (count_init && (loop_count <= stage_count)) | ||
| 423 | || (flag_branch_probabilities && (trip_count <= stage_count))) | ||
| 424 | { | ||
| 425 | @@ -1242,21 +1221,12 @@ | ||
| 426 | else | ||
| 427 | { | ||
| 428 | struct undo_replace_buff_elem *reg_move_replaces; | ||
| 429 | - int amount; | ||
| 430 | - | ||
| 431 | - /* Set the stage boundaries. If the DDG is built with closing_branch_deps, | ||
| 432 | - the closing_branch was scheduled and should appear in the last (ii-1) | ||
| 433 | - row. Otherwise, we are free to schedule the branch, and we let nodes | ||
| 434 | - that were scheduled at the first PS_MIN_CYCLE cycle appear in the first | ||
| 435 | - row; this should reduce stage_count to minimum. | ||
| 436 | - TODO: Revisit the issue of scheduling the insns of the | ||
| 437 | - control part relative to the branch when the control part | ||
| 438 | - has more than one insn. */ | ||
| 439 | - amount = (g->closing_branch_deps)? SCHED_TIME (g->closing_branch) + 1: | ||
| 440 | - PS_MIN_CYCLE (ps); | ||
| 441 | + int amount = SCHED_TIME (g->closing_branch) + 1; | ||
| 442 | + | ||
| 443 | + /* Set the stage boundaries. The closing_branch was scheduled | ||
| 444 | + and should appear in the last (ii-1) row. */ | ||
| 445 | reset_sched_times (ps, amount); | ||
| 446 | rotate_partial_schedule (ps, amount); | ||
| 447 | - | ||
| 448 | set_columns_for_ps (ps); | ||
| 449 | |||
| 450 | canon_loop (loop); | ||
| 451 | @@ -1267,13 +1237,8 @@ | ||
| 452 | "SMS succeeded %d %d (with ii, sc)\n", ps->ii, | ||
| 453 | stage_count); | ||
| 454 | print_partial_schedule (ps, dump_file); | ||
| 455 | - if (!g->closing_branch_deps) | ||
| 456 | - fprintf (dump_file, | ||
| 457 | - "SMS Branch (%d) will later be scheduled at \ | ||
| 458 | - cycle %d.\n", | ||
| 459 | - g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1); | ||
| 460 | - } | ||
| 461 | - | ||
| 462 | + } | ||
| 463 | + | ||
| 464 | /* case the BCT count is not known , Do loop-versioning */ | ||
| 465 | if (count_reg && ! count_init) | ||
| 466 | { | ||
| 467 | @@ -1318,7 +1283,6 @@ | ||
| 468 | } | ||
| 469 | |||
| 470 | free (g_arr); | ||
| 471 | - sbitmap_free (doloop_insns); | ||
| 472 | |||
| 473 | /* Release scheduler data, needed until now because of DFA. */ | ||
| 474 | haifa_sched_finish (); | ||
| 475 | @@ -1826,13 +1790,6 @@ | ||
| 476 | RESET_BIT (tobe_scheduled, u); | ||
| 477 | continue; | ||
| 478 | } | ||
| 479 | - /* Closing branch handled later unless closing_branch_deps | ||
| 480 | - is true. */ | ||
| 481 | - if (JUMP_P (insn) && !g->closing_branch_deps) | ||
| 482 | - { | ||
| 483 | - RESET_BIT (tobe_scheduled, u); | ||
| 484 | - continue; | ||
| 485 | - } | ||
| 486 | |||
| 487 | if (TEST_BIT (sched_nodes, u)) | ||
| 488 | continue; | ||
| 489 | @@ -2675,9 +2632,9 @@ | ||
| 490 | last_in_row = next_ps_i; | ||
| 491 | } | ||
| 492 | |||
| 493 | - /* If closing_branch_deps is true we are scheduling the closing | ||
| 494 | - branch as well. Make sure there is no dependent instruction after | ||
| 495 | - it as the branch should be the last instruction. */ | ||
| 496 | + /* The closing branch is scheduled as well. Make sure there is no | ||
| 497 | + dependent instruction after it as the branch should be the last | ||
| 498 | + instruction in the row. */ | ||
| 499 | if (JUMP_P (ps_i->node->insn)) | ||
| 500 | { | ||
| 501 | if (first_must_follow) | ||
| 502 | @@ -2918,51 +2875,21 @@ | ||
| 503 | return ps_i; | ||
| 504 | } | ||
| 505 | |||
| 506 | -/* Calculate the stage count of the partial schedule PS. */ | ||
| 507 | +/* Calculate the stage count of the partial schedule PS. The calculation | ||
| 508 | + takes into account the rotation to bring the closing branch to row | ||
| 509 | + ii-1. */ | ||
| 510 | int | ||
| 511 | calculate_stage_count (partial_schedule_ptr ps) | ||
| 512 | { | ||
| 513 | - int stage_count; | ||
| 514 | - | ||
| 515 | - /* If closing_branch_deps is false then the stage | ||
| 516 | - boundaries are placed efficiently, meaning that min_cycle will be | ||
| 517 | - placed at row 0. Otherwise, the closing branch will be placed in | ||
| 518 | - row ii-1. For the later case we assume the final SMSed kernel can | ||
| 519 | - be divided into two intervals. This assumption is used for the | ||
| 520 | - stage count calculation: | ||
| 521 | - | ||
| 522 | - 1) min_cycle <= interval 0 < first_cycle_in_row_zero | ||
| 523 | - 2) first_cycle_in_row_zero <= interval 1 < max_cycle | ||
| 524 | - */ | ||
| 525 | - stage_count = | ||
| 526 | - CALC_STAGE_COUNT (PS_MIN_CYCLE (ps), PS_MAX_CYCLE (ps), ps->ii); | ||
| 527 | - if (ps->g->closing_branch_deps) | ||
| 528 | - { | ||
| 529 | - int new_min_cycle; | ||
| 530 | - int new_min_cycle_row; | ||
| 531 | - int rotation_amount = SCHED_TIME (ps->g->closing_branch) + 1; | ||
| 532 | - | ||
| 533 | - /* This is the new value of min_cycle after the final rotation to | ||
| 534 | - bring closing branch into row ii-1. */ | ||
| 535 | - new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount; | ||
| 536 | - /* This is the row which the the new min_cycle will be placed in. */ | ||
| 537 | - new_min_cycle_row = SMODULO (new_min_cycle, ps->ii); | ||
| 538 | - /* If the row of min_cycle is zero then interval 0 is empty. | ||
| 539 | - Otherwise, we need to calculate interval 1 and add it by one | ||
| 540 | - to take interval 0 into account. */ | ||
| 541 | - if (new_min_cycle_row != 0) | ||
| 542 | - { | ||
| 543 | - int new_max_cycle, first_cycle_in_row_zero; | ||
| 544 | - | ||
| 545 | - new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount; | ||
| 546 | - first_cycle_in_row_zero = | ||
| 547 | - new_min_cycle + ps->ii - new_min_cycle_row; | ||
| 548 | - | ||
| 549 | - stage_count = | ||
| 550 | - CALC_STAGE_COUNT (first_cycle_in_row_zero, new_max_cycle, | ||
| 551 | - ps->ii) + 1; | ||
| 552 | - } | ||
| 553 | - } | ||
| 554 | + int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1; | ||
| 555 | + int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount; | ||
| 556 | + int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount; | ||
| 557 | + int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii); | ||
| 558 | + | ||
| 559 | + /* The calculation of stage count is done adding the number of stages | ||
| 560 | + before cycle zero and after cycle zero. */ | ||
| 561 | + stage_count += CALC_STAGE_COUNT (new_max_cycle, 0, ps->ii); | ||
| 562 | + | ||
| 563 | return stage_count; | ||
| 564 | } | ||
| 565 | |||
| 566 | |||
| 567 | === modified file 'gcc/params.def' | ||
| 568 | --- old/gcc/params.def 2011-02-01 14:20:13 +0000 | ||
| 569 | +++ new/gcc/params.def 2011-05-11 08:00:14 +0000 | ||
| 570 | @@ -324,6 +324,11 @@ | ||
| 571 | "sms-max-ii-factor", | ||
| 572 | "A factor for tuning the upper bound that swing modulo scheduler uses for scheduling a loop", | ||
| 573 | 100, 0, 0) | ||
| 574 | +/* The minimum value of stage count that swing modulo scheduler will generate. */ | ||
| 575 | +DEFPARAM(PARAM_SMS_MIN_SC, | ||
| 576 | + "sms-min-sc", | ||
| 577 | + "The minimum value of stage count that swing modulo scheduler will generate.", | ||
| 578 | + 2, 1, 1) | ||
| 579 | DEFPARAM(PARAM_SMS_DFA_HISTORY, | ||
| 580 | "sms-dfa-history", | ||
| 581 | "The number of cycles the swing modulo scheduler considers when checking conflicts using DFA", | ||
| 582 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99514.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99514.patch deleted file mode 100644 index 3fe9bbca5..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99514.patch +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | 2011-05-19 Revital Eres <revital.eres@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * ddg.c (free_ddg_all_sccs): Free sccs field in struct | ||
| 5 | ddg_all_sccs. | ||
| 6 | * modulo-sched.c (sms_schedule): Avoid unfreed | ||
| 7 | memory when SMS fails. | ||
| 8 | |||
| 9 | === modified file 'gcc/ddg.c' | ||
| 10 | --- old/gcc/ddg.c 2011-05-11 08:00:14 +0000 | ||
| 11 | +++ new/gcc/ddg.c 2011-05-13 16:16:22 +0000 | ||
| 12 | @@ -978,6 +978,7 @@ | ||
| 13 | for (i = 0; i < all_sccs->num_sccs; i++) | ||
| 14 | free_scc (all_sccs->sccs[i]); | ||
| 15 | |||
| 16 | + free (all_sccs->sccs); | ||
| 17 | free (all_sccs); | ||
| 18 | } | ||
| 19 | |||
| 20 | |||
| 21 | === modified file 'gcc/modulo-sched.c' | ||
| 22 | --- old/gcc/modulo-sched.c 2011-05-11 08:00:14 +0000 | ||
| 23 | +++ new/gcc/modulo-sched.c 2011-05-13 16:16:22 +0000 | ||
| 24 | @@ -1216,7 +1216,6 @@ | ||
| 25 | fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count); | ||
| 26 | fprintf (dump_file, ")\n"); | ||
| 27 | } | ||
| 28 | - continue; | ||
| 29 | } | ||
| 30 | else | ||
| 31 | { | ||
| 32 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99516.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99516.patch deleted file mode 100644 index e058eb15e..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99516.patch +++ /dev/null | |||
| @@ -1,45 +0,0 @@ | |||
| 1 | 2011-06-09 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 2 | |||
| 3 | LP:748138 | ||
| 4 | |||
| 5 | gcc/ | ||
| 6 | * cfgrtl.c (try_redirect_by_replacing_jump): Treat EXIT_BLOCK_PTR case | ||
| 7 | separately before call to redirect_jump(). Add assertion. | ||
| 8 | (patch_jump_insn): Same. | ||
| 9 | |||
| 10 | === modified file 'gcc/cfgrtl.c' | ||
| 11 | --- old/gcc/cfgrtl.c 2011-02-08 10:51:58 +0000 | ||
| 12 | +++ new/gcc/cfgrtl.c 2011-05-12 08:56:07 +0000 | ||
| 13 | @@ -835,11 +835,10 @@ | ||
| 14 | if (dump_file) | ||
| 15 | fprintf (dump_file, "Redirecting jump %i from %i to %i.\n", | ||
| 16 | INSN_UID (insn), e->dest->index, target->index); | ||
| 17 | - if (!redirect_jump (insn, block_label (target), 0)) | ||
| 18 | - { | ||
| 19 | - gcc_assert (target == EXIT_BLOCK_PTR); | ||
| 20 | - return NULL; | ||
| 21 | - } | ||
| 22 | + if (target == EXIT_BLOCK_PTR) | ||
| 23 | + return NULL; | ||
| 24 | + if (! redirect_jump (insn, block_label (target), 0)) | ||
| 25 | + gcc_unreachable (); | ||
| 26 | } | ||
| 27 | |||
| 28 | /* Cannot do anything for target exit block. */ | ||
| 29 | @@ -1019,11 +1018,10 @@ | ||
| 30 | /* If the substitution doesn't succeed, die. This can happen | ||
| 31 | if the back end emitted unrecognizable instructions or if | ||
| 32 | target is exit block on some arches. */ | ||
| 33 | - if (!redirect_jump (insn, block_label (new_bb), 0)) | ||
| 34 | - { | ||
| 35 | - gcc_assert (new_bb == EXIT_BLOCK_PTR); | ||
| 36 | - return false; | ||
| 37 | - } | ||
| 38 | + if (new_bb == EXIT_BLOCK_PTR) | ||
| 39 | + return false; | ||
| 40 | + if (! redirect_jump (insn, block_label (new_bb), 0)) | ||
| 41 | + gcc_unreachable (); | ||
| 42 | } | ||
| 43 | } | ||
| 44 | return true; | ||
| 45 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99519.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99519.patch deleted file mode 100644 index 5337070af..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99519.patch +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | 2011-07-01 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> | ||
| 2 | |||
| 3 | Backport from mainline. | ||
| 4 | LP 744754 | ||
| 5 | 2011-04-17 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 6 | |||
| 7 | * config/arm/arm.c (neon_struct_mem_operand): | ||
| 8 | Support POST_INC/PRE_DEC memory operands. | ||
| 9 | |||
| 10 | === modified file 'gcc/config/arm/arm.c' | ||
| 11 | --- old/gcc/config/arm/arm.c 2011-05-11 14:47:14 +0000 | ||
| 12 | +++ new/gcc/config/arm/arm.c 2011-06-29 10:46:39 +0000 | ||
| 13 | @@ -9322,6 +9322,11 @@ | ||
| 14 | if (GET_CODE (ind) == REG) | ||
| 15 | return arm_address_register_rtx_p (ind, 0); | ||
| 16 | |||
| 17 | + /* vldm/vstm allows POST_INC (ia) and PRE_DEC (db). */ | ||
| 18 | + if (GET_CODE (ind) == POST_INC | ||
| 19 | + || GET_CODE (ind) == PRE_DEC) | ||
| 20 | + return arm_address_register_rtx_p (XEXP (ind, 0), 0); | ||
| 21 | + | ||
| 22 | return FALSE; | ||
| 23 | } | ||
| 24 | |||
| 25 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99521.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99521.patch deleted file mode 100644 index 6d2d75bf9..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99521.patch +++ /dev/null | |||
| @@ -1,166 +0,0 @@ | |||
| 1 | 2011-07-08 Richard Sandiford <rdsandiford@googlemail.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * builtins.c (get_object_alignment): Fix comment. | ||
| 5 | * fold-const.c (get_pointer_modulus_and_residue): Remove | ||
| 6 | allow_func_align. Use get_object_alignment. | ||
| 7 | (fold_binary_loc): Update caller. | ||
| 8 | |||
| 9 | 2011-07-08 Richard Sandiford <rdsandiford@googlemail.com> | ||
| 10 | |||
| 11 | gcc/ | ||
| 12 | Backport from mainline: | ||
| 13 | |||
| 14 | 2011-06-29 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 15 | |||
| 16 | PR tree-optimization/49545 | ||
| 17 | * builtins.c (get_object_alignment_1): Update function comment. | ||
| 18 | Do not use DECL_ALIGN for functions, but test | ||
| 19 | TARGET_PTRMEMFUNC_VBIT_LOCATION instead. | ||
| 20 | * fold-const.c (get_pointer_modulus_and_residue): Don't check | ||
| 21 | for functions here. | ||
| 22 | |||
| 23 | gcc/testsuite/ | ||
| 24 | Backport from mainline: | ||
| 25 | |||
| 26 | 2011-06-29 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 27 | |||
| 28 | * gcc.dg/torture/pr49169.c: Restrict to ARM and MIPS targets. | ||
| 29 | |||
| 30 | 2011-07-08 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 31 | |||
| 32 | gcc/ | ||
| 33 | Backport from mainline: | ||
| 34 | |||
| 35 | 2011-07-27 Richard Guenther <rguenther@suse.de> | ||
| 36 | |||
| 37 | PR tree-optimization/49169 | ||
| 38 | * fold-const.c (get_pointer_modulus_and_residue): Don't rely on | ||
| 39 | the alignment of function decls. | ||
| 40 | |||
| 41 | gcc/testsuite/ | ||
| 42 | Backport from mainline: | ||
| 43 | |||
| 44 | 2011-07-27 Michael Hope <michael.hope@linaro.org> | ||
| 45 | Richard Sandiford <richard.sandiford@linaro.org> | ||
| 46 | |||
| 47 | PR tree-optimization/49169 | ||
| 48 | * gcc.dg/torture/pr49169.c: New test. | ||
| 49 | |||
| 50 | === modified file 'gcc/builtins.c' | ||
| 51 | --- old/gcc/builtins.c 2011-01-06 11:02:44 +0000 | ||
| 52 | +++ new/gcc/builtins.c 2011-06-29 09:59:48 +0000 | ||
| 53 | @@ -263,7 +263,14 @@ | ||
| 54 | |||
| 55 | /* Return the alignment in bits of EXP, an object. | ||
| 56 | Don't return more than MAX_ALIGN no matter what, ALIGN is the inital | ||
| 57 | - guessed alignment e.g. from type alignment. */ | ||
| 58 | + guessed alignment e.g. from type alignment. | ||
| 59 | + | ||
| 60 | + Note that the address (and thus the alignment) computed here is based | ||
| 61 | + on the address to which a symbol resolves, whereas DECL_ALIGN is based | ||
| 62 | + on the address at which an object is actually located. These two | ||
| 63 | + addresses are not always the same. For example, on ARM targets, | ||
| 64 | + the address &foo of a Thumb function foo() has the lowest bit set, | ||
| 65 | + whereas foo() itself starts on an even address. */ | ||
| 66 | |||
| 67 | int | ||
| 68 | get_object_alignment (tree exp, unsigned int align, unsigned int max_align) | ||
| 69 | @@ -327,7 +334,21 @@ | ||
| 70 | exp = DECL_INITIAL (exp); | ||
| 71 | if (DECL_P (exp) | ||
| 72 | && TREE_CODE (exp) != LABEL_DECL) | ||
| 73 | - align = MIN (inner, DECL_ALIGN (exp)); | ||
| 74 | + { | ||
| 75 | + if (TREE_CODE (exp) == FUNCTION_DECL) | ||
| 76 | + { | ||
| 77 | + /* Function addresses can encode extra information besides their | ||
| 78 | + alignment. However, if TARGET_PTRMEMFUNC_VBIT_LOCATION | ||
| 79 | + allows the low bit to be used as a virtual bit, we know | ||
| 80 | + that the address itself must be 2-byte aligned. */ | ||
| 81 | + if (TARGET_PTRMEMFUNC_VBIT_LOCATION == ptrmemfunc_vbit_in_pfn) | ||
| 82 | + align = 2 * BITS_PER_UNIT; | ||
| 83 | + else | ||
| 84 | + align = BITS_PER_UNIT; | ||
| 85 | + } | ||
| 86 | + else | ||
| 87 | + align = MIN (inner, DECL_ALIGN (exp)); | ||
| 88 | + } | ||
| 89 | #ifdef CONSTANT_ALIGNMENT | ||
| 90 | else if (CONSTANT_CLASS_P (exp)) | ||
| 91 | align = MIN (inner, (unsigned)CONSTANT_ALIGNMENT (exp, align)); | ||
| 92 | |||
| 93 | === modified file 'gcc/fold-const.c' | ||
| 94 | --- old/gcc/fold-const.c 2011-05-05 14:28:53 +0000 | ||
| 95 | +++ new/gcc/fold-const.c 2011-07-08 12:54:44 +0000 | ||
| 96 | @@ -10030,15 +10030,10 @@ | ||
| 97 | 0 <= N < M as is common. In general, the precise value of P is unknown. | ||
| 98 | M is chosen as large as possible such that constant N can be determined. | ||
| 99 | |||
| 100 | - Returns M and sets *RESIDUE to N. | ||
| 101 | - | ||
| 102 | - If ALLOW_FUNC_ALIGN is true, do take functions' DECL_ALIGN_UNIT into | ||
| 103 | - account. This is not always possible due to PR 35705. | ||
| 104 | - */ | ||
| 105 | + Returns M and sets *RESIDUE to N. */ | ||
| 106 | |||
| 107 | static unsigned HOST_WIDE_INT | ||
| 108 | -get_pointer_modulus_and_residue (tree expr, unsigned HOST_WIDE_INT *residue, | ||
| 109 | - bool allow_func_align) | ||
| 110 | +get_pointer_modulus_and_residue (tree expr, unsigned HOST_WIDE_INT *residue) | ||
| 111 | { | ||
| 112 | enum tree_code code; | ||
| 113 | |||
| 114 | @@ -10068,9 +10063,8 @@ | ||
| 115 | } | ||
| 116 | } | ||
| 117 | |||
| 118 | - if (DECL_P (expr) | ||
| 119 | - && (allow_func_align || TREE_CODE (expr) != FUNCTION_DECL)) | ||
| 120 | - return DECL_ALIGN_UNIT (expr); | ||
| 121 | + if (DECL_P (expr)) | ||
| 122 | + return get_object_alignment (expr, BITS_PER_UNIT, ~0U) / BITS_PER_UNIT; | ||
| 123 | } | ||
| 124 | else if (code == POINTER_PLUS_EXPR) | ||
| 125 | { | ||
| 126 | @@ -10080,8 +10074,7 @@ | ||
| 127 | |||
| 128 | op0 = TREE_OPERAND (expr, 0); | ||
| 129 | STRIP_NOPS (op0); | ||
| 130 | - modulus = get_pointer_modulus_and_residue (op0, residue, | ||
| 131 | - allow_func_align); | ||
| 132 | + modulus = get_pointer_modulus_and_residue (op0, residue); | ||
| 133 | |||
| 134 | op1 = TREE_OPERAND (expr, 1); | ||
| 135 | STRIP_NOPS (op1); | ||
| 136 | @@ -11801,8 +11794,7 @@ | ||
| 137 | unsigned HOST_WIDE_INT modulus, residue; | ||
| 138 | unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg1); | ||
| 139 | |||
| 140 | - modulus = get_pointer_modulus_and_residue (arg0, &residue, | ||
| 141 | - integer_onep (arg1)); | ||
| 142 | + modulus = get_pointer_modulus_and_residue (arg0, &residue); | ||
| 143 | |||
| 144 | /* This works because modulus is a power of 2. If this weren't the | ||
| 145 | case, we'd have to replace it by its greatest power-of-2 | ||
| 146 | |||
| 147 | === added file 'gcc/testsuite/gcc.dg/torture/pr49169.c' | ||
| 148 | --- old/gcc/testsuite/gcc.dg/torture/pr49169.c 1970-01-01 00:00:00 +0000 | ||
| 149 | +++ new/gcc/testsuite/gcc.dg/torture/pr49169.c 2011-06-29 09:59:48 +0000 | ||
| 150 | @@ -0,0 +1,15 @@ | ||
| 151 | +/* { dg-do compile { target { arm*-*-* || mips*-*-* } } } */ | ||
| 152 | + | ||
| 153 | +#include <stdlib.h> | ||
| 154 | +#include <stdint.h> | ||
| 155 | + | ||
| 156 | +int | ||
| 157 | +main (void) | ||
| 158 | +{ | ||
| 159 | + void *p = main; | ||
| 160 | + if ((intptr_t) p & 1) | ||
| 161 | + abort (); | ||
| 162 | + return 0; | ||
| 163 | +} | ||
| 164 | + | ||
| 165 | +/* { dg-final { scan-assembler "abort" } } */ | ||
| 166 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99522.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99522.patch deleted file mode 100644 index cdf44b118..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99522.patch +++ /dev/null | |||
| @@ -1,210 +0,0 @@ | |||
| 1 | 2011-07-11 Revital Eres <revital.eres@linaro.org> | ||
| 2 | |||
| 3 | Backport from mainline -r175091 | ||
| 4 | gcc/ | ||
| 5 | * modulo-sched.c (struct ps_insn): Remove row_rest_count field. | ||
| 6 | (struct partial_schedule): Add rows_length field. | ||
| 7 | (verify_partial_schedule): Check rows_length. | ||
| 8 | (ps_insert_empty_row): Handle rows_length. | ||
| 9 | (create_partial_schedule): Likewise. | ||
| 10 | (free_partial_schedule): Likewise. | ||
| 11 | (reset_partial_schedule): Likewise. | ||
| 12 | (create_ps_insn): Remove rest_count argument. | ||
| 13 | (remove_node_from_ps): Update rows_length. | ||
| 14 | (add_node_to_ps): Update rows_length and call create_ps_insn | ||
| 15 | without passing row_rest_count. | ||
| 16 | (rotate_partial_schedule): Update rows_length. | ||
| 17 | |||
| 18 | === modified file 'gcc/modulo-sched.c' | ||
| 19 | --- old/gcc/modulo-sched.c 2011-05-13 16:16:22 +0000 | ||
| 20 | +++ new/gcc/modulo-sched.c 2011-07-04 11:39:09 +0000 | ||
| 21 | @@ -134,8 +134,6 @@ | ||
| 22 | ps_insn_ptr next_in_row, | ||
| 23 | prev_in_row; | ||
| 24 | |||
| 25 | - /* The number of nodes in the same row that come after this node. */ | ||
| 26 | - int row_rest_count; | ||
| 27 | }; | ||
| 28 | |||
| 29 | /* Holds the partial schedule as an array of II rows. Each entry of the | ||
| 30 | @@ -149,6 +147,12 @@ | ||
| 31 | /* rows[i] points to linked list of insns scheduled in row i (0<=i<ii). */ | ||
| 32 | ps_insn_ptr *rows; | ||
| 33 | |||
| 34 | + /* rows_length[i] holds the number of instructions in the row. | ||
| 35 | + It is used only (as an optimization) to back off quickly from | ||
| 36 | + trying to schedule a node in a full row; that is, to avoid running | ||
| 37 | + through futile DFA state transitions. */ | ||
| 38 | + int *rows_length; | ||
| 39 | + | ||
| 40 | /* The earliest absolute cycle of an insn in the partial schedule. */ | ||
| 41 | int min_cycle; | ||
| 42 | |||
| 43 | @@ -1907,6 +1911,7 @@ | ||
| 44 | int ii = ps->ii; | ||
| 45 | int new_ii = ii + 1; | ||
| 46 | int row; | ||
| 47 | + int *rows_length_new; | ||
| 48 | |||
| 49 | verify_partial_schedule (ps, sched_nodes); | ||
| 50 | |||
| 51 | @@ -1921,9 +1926,11 @@ | ||
| 52 | rotate_partial_schedule (ps, PS_MIN_CYCLE (ps)); | ||
| 53 | |||
| 54 | rows_new = (ps_insn_ptr *) xcalloc (new_ii, sizeof (ps_insn_ptr)); | ||
| 55 | + rows_length_new = (int *) xcalloc (new_ii, sizeof (int)); | ||
| 56 | for (row = 0; row < split_row; row++) | ||
| 57 | { | ||
| 58 | rows_new[row] = ps->rows[row]; | ||
| 59 | + rows_length_new[row] = ps->rows_length[row]; | ||
| 60 | ps->rows[row] = NULL; | ||
| 61 | for (crr_insn = rows_new[row]; | ||
| 62 | crr_insn; crr_insn = crr_insn->next_in_row) | ||
| 63 | @@ -1944,6 +1951,7 @@ | ||
| 64 | for (row = split_row; row < ii; row++) | ||
| 65 | { | ||
| 66 | rows_new[row + 1] = ps->rows[row]; | ||
| 67 | + rows_length_new[row + 1] = ps->rows_length[row]; | ||
| 68 | ps->rows[row] = NULL; | ||
| 69 | for (crr_insn = rows_new[row + 1]; | ||
| 70 | crr_insn; crr_insn = crr_insn->next_in_row) | ||
| 71 | @@ -1965,6 +1973,8 @@ | ||
| 72 | + (SMODULO (ps->max_cycle, ii) >= split_row ? 1 : 0); | ||
| 73 | free (ps->rows); | ||
| 74 | ps->rows = rows_new; | ||
| 75 | + free (ps->rows_length); | ||
| 76 | + ps->rows_length = rows_length_new; | ||
| 77 | ps->ii = new_ii; | ||
| 78 | gcc_assert (ps->min_cycle >= 0); | ||
| 79 | |||
| 80 | @@ -2040,16 +2050,23 @@ | ||
| 81 | ps_insn_ptr crr_insn; | ||
| 82 | |||
| 83 | for (row = 0; row < ps->ii; row++) | ||
| 84 | - for (crr_insn = ps->rows[row]; crr_insn; crr_insn = crr_insn->next_in_row) | ||
| 85 | - { | ||
| 86 | - ddg_node_ptr u = crr_insn->node; | ||
| 87 | - | ||
| 88 | - gcc_assert (TEST_BIT (sched_nodes, u->cuid)); | ||
| 89 | - /* ??? Test also that all nodes of sched_nodes are in ps, perhaps by | ||
| 90 | - popcount (sched_nodes) == number of insns in ps. */ | ||
| 91 | - gcc_assert (SCHED_TIME (u) >= ps->min_cycle); | ||
| 92 | - gcc_assert (SCHED_TIME (u) <= ps->max_cycle); | ||
| 93 | - } | ||
| 94 | + { | ||
| 95 | + int length = 0; | ||
| 96 | + | ||
| 97 | + for (crr_insn = ps->rows[row]; crr_insn; crr_insn = crr_insn->next_in_row) | ||
| 98 | + { | ||
| 99 | + ddg_node_ptr u = crr_insn->node; | ||
| 100 | + | ||
| 101 | + length++; | ||
| 102 | + gcc_assert (TEST_BIT (sched_nodes, u->cuid)); | ||
| 103 | + /* ??? Test also that all nodes of sched_nodes are in ps, perhaps by | ||
| 104 | + popcount (sched_nodes) == number of insns in ps. */ | ||
| 105 | + gcc_assert (SCHED_TIME (u) >= ps->min_cycle); | ||
| 106 | + gcc_assert (SCHED_TIME (u) <= ps->max_cycle); | ||
| 107 | + } | ||
| 108 | + | ||
| 109 | + gcc_assert (ps->rows_length[row] == length); | ||
| 110 | + } | ||
| 111 | } | ||
| 112 | |||
| 113 | |||
| 114 | @@ -2455,6 +2472,7 @@ | ||
| 115 | { | ||
| 116 | partial_schedule_ptr ps = XNEW (struct partial_schedule); | ||
| 117 | ps->rows = (ps_insn_ptr *) xcalloc (ii, sizeof (ps_insn_ptr)); | ||
| 118 | + ps->rows_length = (int *) xcalloc (ii, sizeof (int)); | ||
| 119 | ps->ii = ii; | ||
| 120 | ps->history = history; | ||
| 121 | ps->min_cycle = INT_MAX; | ||
| 122 | @@ -2493,6 +2511,7 @@ | ||
| 123 | return; | ||
| 124 | free_ps_insns (ps); | ||
| 125 | free (ps->rows); | ||
| 126 | + free (ps->rows_length); | ||
| 127 | free (ps); | ||
| 128 | } | ||
| 129 | |||
| 130 | @@ -2510,6 +2529,8 @@ | ||
| 131 | ps->rows = (ps_insn_ptr *) xrealloc (ps->rows, new_ii | ||
| 132 | * sizeof (ps_insn_ptr)); | ||
| 133 | memset (ps->rows, 0, new_ii * sizeof (ps_insn_ptr)); | ||
| 134 | + ps->rows_length = (int *) xrealloc (ps->rows_length, new_ii * sizeof (int)); | ||
| 135 | + memset (ps->rows_length, 0, new_ii * sizeof (int)); | ||
| 136 | ps->ii = new_ii; | ||
| 137 | ps->min_cycle = INT_MAX; | ||
| 138 | ps->max_cycle = INT_MIN; | ||
| 139 | @@ -2538,14 +2559,13 @@ | ||
| 140 | |||
| 141 | /* Creates an object of PS_INSN and initializes it to the given parameters. */ | ||
| 142 | static ps_insn_ptr | ||
| 143 | -create_ps_insn (ddg_node_ptr node, int rest_count, int cycle) | ||
| 144 | +create_ps_insn (ddg_node_ptr node, int cycle) | ||
| 145 | { | ||
| 146 | ps_insn_ptr ps_i = XNEW (struct ps_insn); | ||
| 147 | |||
| 148 | ps_i->node = node; | ||
| 149 | ps_i->next_in_row = NULL; | ||
| 150 | ps_i->prev_in_row = NULL; | ||
| 151 | - ps_i->row_rest_count = rest_count; | ||
| 152 | ps_i->cycle = cycle; | ||
| 153 | |||
| 154 | return ps_i; | ||
| 155 | @@ -2578,6 +2598,8 @@ | ||
| 156 | if (ps_i->next_in_row) | ||
| 157 | ps_i->next_in_row->prev_in_row = ps_i->prev_in_row; | ||
| 158 | } | ||
| 159 | + | ||
| 160 | + ps->rows_length[row] -= 1; | ||
| 161 | free (ps_i); | ||
| 162 | return true; | ||
| 163 | } | ||
| 164 | @@ -2734,17 +2756,12 @@ | ||
| 165 | sbitmap must_precede, sbitmap must_follow) | ||
| 166 | { | ||
| 167 | ps_insn_ptr ps_i; | ||
| 168 | - int rest_count = 1; | ||
| 169 | int row = SMODULO (cycle, ps->ii); | ||
| 170 | |||
| 171 | - if (ps->rows[row] | ||
| 172 | - && ps->rows[row]->row_rest_count >= issue_rate) | ||
| 173 | + if (ps->rows_length[row] >= issue_rate) | ||
| 174 | return NULL; | ||
| 175 | |||
| 176 | - if (ps->rows[row]) | ||
| 177 | - rest_count += ps->rows[row]->row_rest_count; | ||
| 178 | - | ||
| 179 | - ps_i = create_ps_insn (node, rest_count, cycle); | ||
| 180 | + ps_i = create_ps_insn (node, cycle); | ||
| 181 | |||
| 182 | /* Finds and inserts PS_I according to MUST_FOLLOW and | ||
| 183 | MUST_PRECEDE. */ | ||
| 184 | @@ -2754,6 +2771,7 @@ | ||
| 185 | return NULL; | ||
| 186 | } | ||
| 187 | |||
| 188 | + ps->rows_length[row] += 1; | ||
| 189 | return ps_i; | ||
| 190 | } | ||
| 191 | |||
| 192 | @@ -2909,11 +2927,16 @@ | ||
| 193 | for (i = 0; i < backward_rotates; i++) | ||
| 194 | { | ||
| 195 | ps_insn_ptr first_row = ps->rows[0]; | ||
| 196 | + int first_row_length = ps->rows_length[0]; | ||
| 197 | |||
| 198 | for (row = 0; row < last_row; row++) | ||
| 199 | - ps->rows[row] = ps->rows[row+1]; | ||
| 200 | + { | ||
| 201 | + ps->rows[row] = ps->rows[row + 1]; | ||
| 202 | + ps->rows_length[row] = ps->rows_length[row + 1]; | ||
| 203 | + } | ||
| 204 | |||
| 205 | ps->rows[last_row] = first_row; | ||
| 206 | + ps->rows_length[last_row] = first_row_length; | ||
| 207 | } | ||
| 208 | |||
| 209 | ps->max_cycle -= start_cycle; | ||
| 210 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99523.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99523.patch deleted file mode 100644 index 64eb23777..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99523.patch +++ /dev/null | |||
| @@ -1,119 +0,0 @@ | |||
| 1 | 2011-07-14 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 2 | |||
| 3 | Backport from mainline: | ||
| 4 | gcc/ | ||
| 5 | 2011-07-07 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 6 | |||
| 7 | * reload1.c (choose_reload_regs): Use mode sizes to check whether | ||
| 8 | an old reload register completely defines the required value. | ||
| 9 | |||
| 10 | gcc/testsuite/ | ||
| 11 | 2011-07-07 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 12 | |||
| 13 | * gcc.target/arm/neon-modes-3.c: New test. | ||
| 14 | |||
| 15 | === modified file 'gcc/reload1.c' | ||
| 16 | --- old/gcc/reload1.c 2011-07-01 09:27:50 +0000 | ||
| 17 | +++ new/gcc/reload1.c 2011-07-11 10:05:08 +0000 | ||
| 18 | @@ -6449,6 +6449,8 @@ | ||
| 19 | |||
| 20 | if (regno >= 0 | ||
| 21 | && reg_last_reload_reg[regno] != 0 | ||
| 22 | + && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])) | ||
| 23 | + >= GET_MODE_SIZE (mode) + byte) | ||
| 24 | #ifdef CANNOT_CHANGE_MODE_CLASS | ||
| 25 | /* Verify that the register it's in can be used in | ||
| 26 | mode MODE. */ | ||
| 27 | @@ -6460,24 +6462,12 @@ | ||
| 28 | { | ||
| 29 | enum reg_class rclass = rld[r].rclass, last_class; | ||
| 30 | rtx last_reg = reg_last_reload_reg[regno]; | ||
| 31 | - enum machine_mode need_mode; | ||
| 32 | |||
| 33 | i = REGNO (last_reg); | ||
| 34 | i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode); | ||
| 35 | last_class = REGNO_REG_CLASS (i); | ||
| 36 | |||
| 37 | - if (byte == 0) | ||
| 38 | - need_mode = mode; | ||
| 39 | - else | ||
| 40 | - need_mode | ||
| 41 | - = smallest_mode_for_size | ||
| 42 | - (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT, | ||
| 43 | - GET_MODE_CLASS (mode) == MODE_PARTIAL_INT | ||
| 44 | - ? MODE_INT : GET_MODE_CLASS (mode)); | ||
| 45 | - | ||
| 46 | - if ((GET_MODE_SIZE (GET_MODE (last_reg)) | ||
| 47 | - >= GET_MODE_SIZE (need_mode)) | ||
| 48 | - && reg_reloaded_contents[i] == regno | ||
| 49 | + if (reg_reloaded_contents[i] == regno | ||
| 50 | && TEST_HARD_REG_BIT (reg_reloaded_valid, i) | ||
| 51 | && HARD_REGNO_MODE_OK (i, rld[r].mode) | ||
| 52 | && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i) | ||
| 53 | |||
| 54 | === added file 'gcc/testsuite/gcc.target/arm/neon-modes-3.c' | ||
| 55 | --- old/gcc/testsuite/gcc.target/arm/neon-modes-3.c 1970-01-01 00:00:00 +0000 | ||
| 56 | +++ new/gcc/testsuite/gcc.target/arm/neon-modes-3.c 2011-07-11 10:05:08 +0000 | ||
| 57 | @@ -0,0 +1,61 @@ | ||
| 58 | +/* { dg-do compile } */ | ||
| 59 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 60 | +/* { dg-options "-O" } */ | ||
| 61 | +/* { dg-add-options arm_neon } */ | ||
| 62 | + | ||
| 63 | +#include <arm_neon.h> | ||
| 64 | + | ||
| 65 | +void f1 (volatile float32x4_t *dest, volatile float32x4x4_t *src, int n) | ||
| 66 | +{ | ||
| 67 | + float32x4x4_t a5, a6, a7, a8, a9; | ||
| 68 | + int i; | ||
| 69 | + | ||
| 70 | + a5 = *src; | ||
| 71 | + a6 = *src; | ||
| 72 | + a7 = *src; | ||
| 73 | + a8 = *src; | ||
| 74 | + a9 = *src; | ||
| 75 | + while (n--) | ||
| 76 | + { | ||
| 77 | + for (i = 0; i < 8; i++) | ||
| 78 | + { | ||
| 79 | + float32x4x4_t a0, a1, a2, a3, a4; | ||
| 80 | + | ||
| 81 | + a0 = *src; | ||
| 82 | + a1 = *src; | ||
| 83 | + a2 = *src; | ||
| 84 | + a3 = *src; | ||
| 85 | + a4 = *src; | ||
| 86 | + *src = a0; | ||
| 87 | + *dest = a0.val[0]; | ||
| 88 | + *dest = a0.val[3]; | ||
| 89 | + *src = a1; | ||
| 90 | + *dest = a1.val[0]; | ||
| 91 | + *dest = a1.val[3]; | ||
| 92 | + *src = a2; | ||
| 93 | + *dest = a2.val[0]; | ||
| 94 | + *dest = a2.val[3]; | ||
| 95 | + *src = a3; | ||
| 96 | + *dest = a3.val[0]; | ||
| 97 | + *dest = a3.val[3]; | ||
| 98 | + *src = a4; | ||
| 99 | + *dest = a4.val[0]; | ||
| 100 | + *dest = a4.val[3]; | ||
| 101 | + } | ||
| 102 | + *src = a5; | ||
| 103 | + *dest = a5.val[0]; | ||
| 104 | + *dest = a5.val[3]; | ||
| 105 | + *src = a6; | ||
| 106 | + *dest = a6.val[0]; | ||
| 107 | + *dest = a6.val[3]; | ||
| 108 | + *src = a7; | ||
| 109 | + *dest = a7.val[0]; | ||
| 110 | + *dest = a7.val[3]; | ||
| 111 | + *src = a8; | ||
| 112 | + *dest = a8.val[0]; | ||
| 113 | + *dest = a8.val[3]; | ||
| 114 | + *src = a9; | ||
| 115 | + *dest = a9.val[0]; | ||
| 116 | + *dest = a9.val[3]; | ||
| 117 | + } | ||
| 118 | +} | ||
| 119 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99524.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99524.patch deleted file mode 100644 index 2e8e12d2a..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99524.patch +++ /dev/null | |||
| @@ -1,209 +0,0 @@ | |||
| 1 | 2011-07-14 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * config/arm/arm.h (ARM_LEGITIMIZE_RELOAD_ADDRESS): Apply the | ||
| 5 | arm_legitimize_reload_address changes marked [*] below. | ||
| 6 | |||
| 7 | Backport from mainline: | ||
| 8 | |||
| 9 | 2011-04-20 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 10 | |||
| 11 | [*] config/arm/arm.c (arm_legitimize_reload_address): For NEON | ||
| 12 | quad-word modes, reduce to 9-bit index range when above 1016 | ||
| 13 | limit. | ||
| 14 | |||
| 15 | 2011-04-11 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 16 | Richard Earnshaw <rearnsha@arm.com> | ||
| 17 | |||
| 18 | PR target/48250 | ||
| 19 | [*] config/arm/arm.c (arm_legitimize_reload_address): Update cases | ||
| 20 | to use sign-magnitude offsets. Reject unsupported unaligned | ||
| 21 | cases. Add detailed description in comments. | ||
| 22 | * config/arm/arm.md (reload_outdf): Disable for ARM mode; change | ||
| 23 | condition from TARGET_32BIT to TARGET_ARM. | ||
| 24 | |||
| 25 | === modified file 'gcc/config/arm/arm.h' | ||
| 26 | --- old/gcc/config/arm/arm.h 2011-04-20 10:07:36 +0000 | ||
| 27 | +++ new/gcc/config/arm/arm.h 2011-07-12 16:35:20 +0000 | ||
| 28 | @@ -1399,6 +1399,11 @@ | ||
| 29 | ? GENERAL_REGS : NO_REGS) \ | ||
| 30 | : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) | ||
| 31 | |||
| 32 | +#define SIGN_MAG_LOW_ADDR_BITS(VAL, N) \ | ||
| 33 | + (((VAL) & ((1 << (N)) - 1)) \ | ||
| 34 | + ? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N)) \ | ||
| 35 | + : 0) | ||
| 36 | + | ||
| 37 | /* Try a machine-dependent way of reloading an illegitimate address | ||
| 38 | operand. If we find one, push the reload and jump to WIN. This | ||
| 39 | macro is used in only one place: `find_reloads_address' in reload.c. | ||
| 40 | @@ -1418,26 +1423,135 @@ | ||
| 41 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | ||
| 42 | HOST_WIDE_INT low, high; \ | ||
| 43 | \ | ||
| 44 | - if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \ | ||
| 45 | - low = ((val & 0xf) ^ 0x8) - 0x8; \ | ||
| 46 | - else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \ | ||
| 47 | - /* Need to be careful, -256 is not a valid offset. */ \ | ||
| 48 | - low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ | ||
| 49 | - else if (TARGET_REALLY_IWMMXT && MODE == SImode) \ | ||
| 50 | - /* Need to be careful, -1024 is not a valid offset. */ \ | ||
| 51 | - low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ | ||
| 52 | - else if (MODE == SImode \ | ||
| 53 | - || (MODE == SFmode && TARGET_SOFT_FLOAT) \ | ||
| 54 | - || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ | ||
| 55 | - /* Need to be careful, -4096 is not a valid offset. */ \ | ||
| 56 | - low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ | ||
| 57 | - else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ | ||
| 58 | - /* Need to be careful, -256 is not a valid offset. */ \ | ||
| 59 | - low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ | ||
| 60 | - else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | ||
| 61 | - && TARGET_HARD_FLOAT && TARGET_FPA) \ | ||
| 62 | - /* Need to be careful, -1024 is not a valid offset. */ \ | ||
| 63 | - low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ | ||
| 64 | + /* Detect coprocessor load/stores. */ \ | ||
| 65 | + bool coproc_p = ((TARGET_HARD_FLOAT \ | ||
| 66 | + && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK) \ | ||
| 67 | + && (mode == SFmode || mode == DFmode \ | ||
| 68 | + || (mode == DImode && TARGET_MAVERICK))) \ | ||
| 69 | + || (TARGET_REALLY_IWMMXT \ | ||
| 70 | + && VALID_IWMMXT_REG_MODE (mode)) \ | ||
| 71 | + || (TARGET_NEON \ | ||
| 72 | + && (VALID_NEON_DREG_MODE (mode) \ | ||
| 73 | + || VALID_NEON_QREG_MODE (mode)))); \ | ||
| 74 | + \ | ||
| 75 | + /* For some conditions, bail out when lower two bits are \ | ||
| 76 | + unaligned. */ \ | ||
| 77 | + if ((val & 0x3) != 0 \ | ||
| 78 | + /* Coprocessor load/store indexes are 8-bits + '00' \ | ||
| 79 | + appended. */ \ | ||
| 80 | + && (coproc_p \ | ||
| 81 | + /* For DI, and DF under soft-float: */ \ | ||
| 82 | + || ((mode == DImode || mode == DFmode) \ | ||
| 83 | + /* Without ldrd, we use stm/ldm, which does not \ | ||
| 84 | + fair well with unaligned bits. */ \ | ||
| 85 | + && (! TARGET_LDRD \ | ||
| 86 | + /* Thumb-2 ldrd/strd is [-1020,+1020] in \ | ||
| 87 | + steps of 4. */ \ | ||
| 88 | + || TARGET_THUMB2)))) \ | ||
| 89 | + break; \ | ||
| 90 | + \ | ||
| 91 | + /* When breaking down a [reg+index] reload address into \ | ||
| 92 | + [(reg+high)+low], of which the (reg+high) gets turned into \ | ||
| 93 | + a reload add insn, we try to decompose the index into \ | ||
| 94 | + high/low values that can often also lead to better reload \ | ||
| 95 | + CSE. For example: \ | ||
| 96 | + ldr r0, [r2, #4100] // Offset too large \ | ||
| 97 | + ldr r1, [r2, #4104] // Offset too large \ | ||
| 98 | + \ | ||
| 99 | + is best reloaded as: \ | ||
| 100 | + add t1, r2, #4096 \ | ||
| 101 | + ldr r0, [t1, #4] \ | ||
| 102 | + add t2, r2, #4096 \ | ||
| 103 | + ldr r1, [t2, #8] \ | ||
| 104 | + \ | ||
| 105 | + which post-reload CSE can simplify in most cases to eliminate \ | ||
| 106 | + the second add instruction: \ | ||
| 107 | + add t1, r2, #4096 \ | ||
| 108 | + ldr r0, [t1, #4] \ | ||
| 109 | + ldr r1, [t1, #8] \ | ||
| 110 | + \ | ||
| 111 | + The idea here is that we want to split out the bits of the \ | ||
| 112 | + constant as a mask, rather than as subtracting the maximum \ | ||
| 113 | + offset that the respective type of load/store used can \ | ||
| 114 | + handle. \ | ||
| 115 | + \ | ||
| 116 | + When encountering negative offsets, we can still utilize it \ | ||
| 117 | + even if the overall offset is positive; sometimes this may \ | ||
| 118 | + lead to an immediate that can be constructed with fewer \ | ||
| 119 | + instructions. For example: \ | ||
| 120 | + ldr r0, [r2, #0x3FFFFC] \ | ||
| 121 | + \ | ||
| 122 | + This is best reloaded as: \ | ||
| 123 | + add t1, r2, #0x400000 \ | ||
| 124 | + ldr r0, [t1, #-4] \ | ||
| 125 | + \ | ||
| 126 | + The trick for spotting this for a load insn with N bits of \ | ||
| 127 | + offset (i.e. bits N-1:0) is to look at bit N; if it is set, \ | ||
| 128 | + then chose a negative offset that is going to make bit N and \ | ||
| 129 | + all the bits below it become zero in the remainder part. \ | ||
| 130 | + \ | ||
| 131 | + The SIGN_MAG_LOW_ADDR_BITS macro below implements this, \ | ||
| 132 | + with respect to sign-magnitude addressing (i.e. separate \ | ||
| 133 | + +- bit, or 1's complement), used in most cases of ARM \ | ||
| 134 | + load/store instructions. */ \ | ||
| 135 | + \ | ||
| 136 | + if (coproc_p) \ | ||
| 137 | + { \ | ||
| 138 | + low = SIGN_MAG_LOW_ADDR_BITS (val, 10); \ | ||
| 139 | + \ | ||
| 140 | + /* NEON quad-word load/stores are made of two double-word \ | ||
| 141 | + accesses, so the valid index range is reduced by 8. \ | ||
| 142 | + Treat as 9-bit range if we go over it. */ \ | ||
| 143 | + if (TARGET_NEON && VALID_NEON_QREG_MODE (mode) && low >= 1016) \ | ||
| 144 | + low = SIGN_MAG_LOW_ADDR_BITS (val, 9); \ | ||
| 145 | + } \ | ||
| 146 | + else if (GET_MODE_SIZE (mode) == 8) \ | ||
| 147 | + { \ | ||
| 148 | + if (TARGET_LDRD) \ | ||
| 149 | + low = (TARGET_THUMB2 \ | ||
| 150 | + ? SIGN_MAG_LOW_ADDR_BITS (val, 10) \ | ||
| 151 | + : SIGN_MAG_LOW_ADDR_BITS (val, 8)); \ | ||
| 152 | + else \ | ||
| 153 | + /* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib) \ | ||
| 154 | + to access doublewords. The supported load/store offsets \ | ||
| 155 | + are -8, -4, and 4, which we try to produce here. */ \ | ||
| 156 | + low = ((val & 0xf) ^ 0x8) - 0x8; \ | ||
| 157 | + } \ | ||
| 158 | + else if (GET_MODE_SIZE (mode) < 8) \ | ||
| 159 | + { \ | ||
| 160 | + /* NEON element load/stores do not have an offset. */ \ | ||
| 161 | + if (TARGET_NEON_FP16 && mode == HFmode) \ | ||
| 162 | + break; \ | ||
| 163 | + \ | ||
| 164 | + if (TARGET_THUMB2) \ | ||
| 165 | + { \ | ||
| 166 | + /* Thumb-2 has an asymmetrical index range of (-256,4096). \ | ||
| 167 | + Try the wider 12-bit range first, and re-try if the \ | ||
| 168 | + result is out of range. */ \ | ||
| 169 | + low = SIGN_MAG_LOW_ADDR_BITS (val, 12); \ | ||
| 170 | + if (low < -255) \ | ||
| 171 | + low = SIGN_MAG_LOW_ADDR_BITS (val, 8); \ | ||
| 172 | + } \ | ||
| 173 | + else \ | ||
| 174 | + { \ | ||
| 175 | + if (mode == HImode || mode == HFmode) \ | ||
| 176 | + { \ | ||
| 177 | + if (arm_arch4) \ | ||
| 178 | + low = SIGN_MAG_LOW_ADDR_BITS (val, 8); \ | ||
| 179 | + else \ | ||
| 180 | + { \ | ||
| 181 | + /* The storehi/movhi_bytes fallbacks can use \ | ||
| 182 | + only [-4094,+4094] of the full ldrb/strb \ | ||
| 183 | + index range. */ \ | ||
| 184 | + low = SIGN_MAG_LOW_ADDR_BITS (val, 12); \ | ||
| 185 | + if (low == 4095 || low == -4095) \ | ||
| 186 | + break; \ | ||
| 187 | + } \ | ||
| 188 | + } \ | ||
| 189 | + else \ | ||
| 190 | + low = SIGN_MAG_LOW_ADDR_BITS (val, 12); \ | ||
| 191 | + } \ | ||
| 192 | + } \ | ||
| 193 | else \ | ||
| 194 | break; \ | ||
| 195 | \ | ||
| 196 | |||
| 197 | === modified file 'gcc/config/arm/arm.md' | ||
| 198 | --- old/gcc/config/arm/arm.md 2011-04-28 16:13:24 +0000 | ||
| 199 | +++ new/gcc/config/arm/arm.md 2011-07-12 16:35:20 +0000 | ||
| 200 | @@ -6167,7 +6167,7 @@ | ||
| 201 | [(match_operand:DF 0 "arm_reload_memory_operand" "=o") | ||
| 202 | (match_operand:DF 1 "s_register_operand" "r") | ||
| 203 | (match_operand:SI 2 "s_register_operand" "=&r")] | ||
| 204 | - "TARGET_32BIT" | ||
| 205 | + "TARGET_THUMB2" | ||
| 206 | " | ||
| 207 | { | ||
| 208 | enum rtx_code code = GET_CODE (XEXP (operands[0], 0)); | ||
| 209 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99525.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99525.patch deleted file mode 100644 index 560a830bf..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99525.patch +++ /dev/null | |||
| @@ -1,67 +0,0 @@ | |||
| 1 | 2011-07-15 Michael Hope <michael.hope@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | Backport from mainline: | ||
| 5 | |||
| 6 | 2011-04-05 Eric Botcazou <ebotcazou@adacore.com> | ||
| 7 | |||
| 8 | * ifcvt.c (cond_exec_process_insns): Disallow converting a block | ||
| 9 | that contains the prologue. | ||
| 10 | |||
| 11 | gcc/testsuite/ | ||
| 12 | Backport from mainline: | ||
| 13 | |||
| 14 | 2011-04-01 Bernd Schmidt <bernds@codesourcery.com> | ||
| 15 | |||
| 16 | * gcc.c-torture/compile/20110401-1.c: New test. | ||
| 17 | |||
| 18 | === modified file 'gcc/ifcvt.c' | ||
| 19 | --- old/gcc/ifcvt.c 2011-05-05 14:28:53 +0000 | ||
| 20 | +++ new/gcc/ifcvt.c 2011-07-11 04:08:33 +0000 | ||
| 21 | @@ -1,5 +1,6 @@ | ||
| 22 | /* If-conversion support. | ||
| 23 | - Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010 | ||
| 24 | + Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, | ||
| 25 | + 2011 | ||
| 26 | Free Software Foundation, Inc. | ||
| 27 | |||
| 28 | This file is part of GCC. | ||
| 29 | @@ -311,6 +312,10 @@ | ||
| 30 | |||
| 31 | for (insn = start; ; insn = NEXT_INSN (insn)) | ||
| 32 | { | ||
| 33 | + /* dwarf2out can't cope with conditional prologues. */ | ||
| 34 | + if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_PROLOGUE_END) | ||
| 35 | + return FALSE; | ||
| 36 | + | ||
| 37 | if (NOTE_P (insn) || DEBUG_INSN_P (insn)) | ||
| 38 | goto insn_done; | ||
| 39 | |||
| 40 | |||
| 41 | === added file 'gcc/testsuite/gcc.c-torture/compile/20110401-1.c' | ||
| 42 | --- old/gcc/testsuite/gcc.c-torture/compile/20110401-1.c 1970-01-01 00:00:00 +0000 | ||
| 43 | +++ new/gcc/testsuite/gcc.c-torture/compile/20110401-1.c 2011-07-11 04:08:33 +0000 | ||
| 44 | @@ -0,0 +1,22 @@ | ||
| 45 | +void asn1_length_der (unsigned long int len, unsigned char *ans, int *ans_len) | ||
| 46 | +{ | ||
| 47 | + int k; | ||
| 48 | + unsigned char temp[4]; | ||
| 49 | + if (len < 128) { | ||
| 50 | + if (ans != ((void *) 0)) | ||
| 51 | + ans[0] = (unsigned char) len; | ||
| 52 | + *ans_len = 1; | ||
| 53 | + } else { | ||
| 54 | + k = 0; | ||
| 55 | + while (len) { | ||
| 56 | + temp[k++] = len & 0xFF; | ||
| 57 | + len = len >> 8; | ||
| 58 | + } | ||
| 59 | + *ans_len = k + 1; | ||
| 60 | + if (ans != ((void *) 0)) { | ||
| 61 | + ans[0] = ((unsigned char) k & 0x7F) + 128; | ||
| 62 | + while (k--) | ||
| 63 | + ans[*ans_len - 1 - k] = temp[k]; | ||
| 64 | + } | ||
| 65 | + } | ||
| 66 | +} | ||
| 67 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99528.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99528.patch deleted file mode 100644 index 874358306..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99528.patch +++ /dev/null | |||
| @@ -1,138 +0,0 @@ | |||
| 1 | 2011-07-19 Revital Eres <revital.eres@linaro.org> | ||
| 2 | |||
| 3 | Backport from mainline -r175090 | ||
| 4 | gcc/ | ||
| 5 | * ddg.c (add_intra_loop_mem_dep): New function. | ||
| 6 | (build_intra_loop_deps): Call it. | ||
| 7 | |||
| 8 | gcc/testsuite | ||
| 9 | * gcc.dg/sms-9.c: New file. | ||
| 10 | |||
| 11 | === modified file 'gcc/ddg.c' | ||
| 12 | --- old/gcc/ddg.c 2011-05-13 16:16:22 +0000 | ||
| 13 | +++ new/gcc/ddg.c 2011-07-05 09:02:18 +0000 | ||
| 14 | @@ -352,6 +352,33 @@ | ||
| 15 | } | ||
| 16 | |||
| 17 | |||
| 18 | +/* Given two nodes, analyze their RTL insns and add intra-loop mem deps | ||
| 19 | + to ddg G. */ | ||
| 20 | +static void | ||
| 21 | +add_intra_loop_mem_dep (ddg_ptr g, ddg_node_ptr from, ddg_node_ptr to) | ||
| 22 | +{ | ||
| 23 | + | ||
| 24 | + if ((from->cuid == to->cuid) | ||
| 25 | + || !insn_alias_sets_conflict_p (from->insn, to->insn)) | ||
| 26 | + /* Do not create edge if memory references have disjoint alias sets | ||
| 27 | + or 'to' and 'from' are the same instruction. */ | ||
| 28 | + return; | ||
| 29 | + | ||
| 30 | + if (mem_write_insn_p (from->insn)) | ||
| 31 | + { | ||
| 32 | + if (mem_read_insn_p (to->insn)) | ||
| 33 | + create_ddg_dep_no_link (g, from, to, | ||
| 34 | + DEBUG_INSN_P (to->insn) | ||
| 35 | + ? ANTI_DEP : TRUE_DEP, MEM_DEP, 0); | ||
| 36 | + else | ||
| 37 | + create_ddg_dep_no_link (g, from, to, | ||
| 38 | + DEBUG_INSN_P (to->insn) | ||
| 39 | + ? ANTI_DEP : OUTPUT_DEP, MEM_DEP, 0); | ||
| 40 | + } | ||
| 41 | + else if (!mem_read_insn_p (to->insn)) | ||
| 42 | + create_ddg_dep_no_link (g, from, to, ANTI_DEP, MEM_DEP, 0); | ||
| 43 | +} | ||
| 44 | + | ||
| 45 | /* Given two nodes, analyze their RTL insns and add inter-loop mem deps | ||
| 46 | to ddg G. */ | ||
| 47 | static void | ||
| 48 | @@ -439,10 +466,22 @@ | ||
| 49 | if (DEBUG_INSN_P (j_node->insn)) | ||
| 50 | continue; | ||
| 51 | if (mem_access_insn_p (j_node->insn)) | ||
| 52 | - /* Don't bother calculating inter-loop dep if an intra-loop dep | ||
| 53 | - already exists. */ | ||
| 54 | + { | ||
| 55 | + /* Don't bother calculating inter-loop dep if an intra-loop dep | ||
| 56 | + already exists. */ | ||
| 57 | if (! TEST_BIT (dest_node->successors, j)) | ||
| 58 | add_inter_loop_mem_dep (g, dest_node, j_node); | ||
| 59 | + /* If -fmodulo-sched-allow-regmoves | ||
| 60 | + is set certain anti-dep edges are not created. | ||
| 61 | + It might be that these anti-dep edges are on the | ||
| 62 | + path from one memory instruction to another such that | ||
| 63 | + removing these edges could cause a violation of the | ||
| 64 | + memory dependencies. Thus we add intra edges between | ||
| 65 | + every two memory instructions in this case. */ | ||
| 66 | + if (flag_modulo_sched_allow_regmoves | ||
| 67 | + && !TEST_BIT (dest_node->predecessors, j)) | ||
| 68 | + add_intra_loop_mem_dep (g, j_node, dest_node); | ||
| 69 | + } | ||
| 70 | } | ||
| 71 | } | ||
| 72 | } | ||
| 73 | |||
| 74 | === added file 'gcc/testsuite/gcc.dg/sms-9.c' | ||
| 75 | --- old/gcc/testsuite/gcc.dg/sms-9.c 1970-01-01 00:00:00 +0000 | ||
| 76 | +++ new/gcc/testsuite/gcc.dg/sms-9.c 2011-07-04 11:13:26 +0000 | ||
| 77 | @@ -0,0 +1,60 @@ | ||
| 78 | +/* { dg-do run } */ | ||
| 79 | +/* { dg-options "-O2 -fmodulo-sched -fno-auto-inc-dec -O2 -fmodulo-sched-allow-regmoves" } */ | ||
| 80 | + | ||
| 81 | +#include <stdlib.h> | ||
| 82 | +#include <stdarg.h> | ||
| 83 | + | ||
| 84 | +struct df_ref_info | ||
| 85 | +{ | ||
| 86 | + unsigned int *begin; | ||
| 87 | + unsigned int *count; | ||
| 88 | +}; | ||
| 89 | + | ||
| 90 | +extern void *memset (void *s, int c, __SIZE_TYPE__ n); | ||
| 91 | + | ||
| 92 | + | ||
| 93 | +__attribute__ ((noinline)) | ||
| 94 | + int | ||
| 95 | + df_reorganize_refs_by_reg_by_insn (struct df_ref_info *ref_info, | ||
| 96 | + int num, unsigned int start) | ||
| 97 | +{ | ||
| 98 | + unsigned int m = num; | ||
| 99 | + unsigned int offset = 77; | ||
| 100 | + unsigned int r; | ||
| 101 | + | ||
| 102 | + for (r = start; r < m; r++) | ||
| 103 | + { | ||
| 104 | + ref_info->begin[r] = offset; | ||
| 105 | + offset += ref_info->count[r]; | ||
| 106 | + ref_info->count[r] = 0; | ||
| 107 | + } | ||
| 108 | + | ||
| 109 | + return offset; | ||
| 110 | +} | ||
| 111 | + | ||
| 112 | +int | ||
| 113 | +main () | ||
| 114 | +{ | ||
| 115 | + struct df_ref_info temp; | ||
| 116 | + int num = 100; | ||
| 117 | + unsigned int start = 5; | ||
| 118 | + int i, offset; | ||
| 119 | + | ||
| 120 | + temp.begin = malloc (100 * sizeof (unsigned int)); | ||
| 121 | + temp.count = malloc (100 * sizeof (unsigned int)); | ||
| 122 | + | ||
| 123 | + memset (temp.begin, 0, sizeof (unsigned int) * num); | ||
| 124 | + memset (temp.count, 0, sizeof (unsigned int) * num); | ||
| 125 | + | ||
| 126 | + for (i = 0; i < num; i++) | ||
| 127 | + temp.count[i] = i + 1; | ||
| 128 | + | ||
| 129 | + offset = df_reorganize_refs_by_reg_by_insn (&temp, num, start); | ||
| 130 | + | ||
| 131 | + if (offset != 5112) | ||
| 132 | + abort (); | ||
| 133 | + | ||
| 134 | + free (temp.begin); | ||
| 135 | + free (temp.count); | ||
| 136 | + return 0; | ||
| 137 | +} | ||
| 138 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99529.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99529.patch deleted file mode 100644 index f0f6a9432..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99529.patch +++ /dev/null | |||
| @@ -1,741 +0,0 @@ | |||
| 1 | 2011-07-21 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | PR middle-end/49736 | ||
| 5 | * expr.c (all_zeros_p): Undo bogus part of last change. | ||
| 6 | |||
| 7 | 2011-07-21 Richard Sandiford <rdsandiford@googlemail.com> | ||
| 8 | |||
| 9 | Backport from mainline: | ||
| 10 | gcc/cp/ | ||
| 11 | 2011-07-13 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 12 | |||
| 13 | * typeck2.c (split_nonconstant_init_1): Pass the initializer directly, | ||
| 14 | rather than a pointer to it. Return true if the whole of the value | ||
| 15 | was initialized by the generated statements. Use | ||
| 16 | complete_ctor_at_level_p instead of count_type_elements. | ||
| 17 | |||
| 18 | gcc/ | ||
| 19 | 2011-07-13 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 20 | |||
| 21 | * tree.h (categorize_ctor_elements): Remove comment. Fix long line. | ||
| 22 | (count_type_elements): Delete. | ||
| 23 | (complete_ctor_at_level_p): Declare. | ||
| 24 | * expr.c (flexible_array_member_p): New function, split out from... | ||
| 25 | (count_type_elements): ...here. Make static. Replace allow_flexarr | ||
| 26 | parameter with for_ctor_p. When for_ctor_p is true, return the | ||
| 27 | number of elements that should appear in the top-level constructor, | ||
| 28 | otherwise return an estimate of the number of scalars. | ||
| 29 | (categorize_ctor_elements): Replace p_must_clear with p_complete. | ||
| 30 | (categorize_ctor_elements_1): Likewise. Use complete_ctor_at_level_p. | ||
| 31 | (complete_ctor_at_level_p): New function, borrowing union logic | ||
| 32 | from old categorize_ctor_elements_1. | ||
| 33 | (mostly_zeros_p): Return true if the constructor is not complete. | ||
| 34 | (all_zeros_p): Update call to categorize_ctor_elements. | ||
| 35 | * gimplify.c (gimplify_init_constructor): Update call to | ||
| 36 | categorize_ctor_elements. Don't call count_type_elements. | ||
| 37 | Unconditionally prevent clearing for variable-sized types, | ||
| 38 | otherwise rely on categorize_ctor_elements to detect | ||
| 39 | incomplete initializers. | ||
| 40 | |||
| 41 | gcc/testsuite/ | ||
| 42 | 2011-07-13 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 43 | |||
| 44 | * gcc.target/arm/pr48183.c: New test. | ||
| 45 | |||
| 46 | === modified file 'gcc/cp/typeck2.c' | ||
| 47 | --- old/gcc/cp/typeck2.c 2010-07-30 14:05:57 +0000 | ||
| 48 | +++ new/gcc/cp/typeck2.c 2011-07-13 13:36:36 +0000 | ||
| 49 | @@ -546,18 +546,20 @@ | ||
| 50 | |||
| 51 | |||
| 52 | /* The recursive part of split_nonconstant_init. DEST is an lvalue | ||
| 53 | - expression to which INIT should be assigned. INIT is a CONSTRUCTOR. */ | ||
| 54 | + expression to which INIT should be assigned. INIT is a CONSTRUCTOR. | ||
| 55 | + Return true if the whole of the value was initialized by the | ||
| 56 | + generated statements. */ | ||
| 57 | |||
| 58 | -static void | ||
| 59 | -split_nonconstant_init_1 (tree dest, tree *initp) | ||
| 60 | +static bool | ||
| 61 | +split_nonconstant_init_1 (tree dest, tree init) | ||
| 62 | { | ||
| 63 | unsigned HOST_WIDE_INT idx; | ||
| 64 | - tree init = *initp; | ||
| 65 | tree field_index, value; | ||
| 66 | tree type = TREE_TYPE (dest); | ||
| 67 | tree inner_type = NULL; | ||
| 68 | bool array_type_p = false; | ||
| 69 | - HOST_WIDE_INT num_type_elements, num_initialized_elements; | ||
| 70 | + bool complete_p = true; | ||
| 71 | + HOST_WIDE_INT num_split_elts = 0; | ||
| 72 | |||
| 73 | switch (TREE_CODE (type)) | ||
| 74 | { | ||
| 75 | @@ -569,7 +571,6 @@ | ||
| 76 | case RECORD_TYPE: | ||
| 77 | case UNION_TYPE: | ||
| 78 | case QUAL_UNION_TYPE: | ||
| 79 | - num_initialized_elements = 0; | ||
| 80 | FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (init), idx, | ||
| 81 | field_index, value) | ||
| 82 | { | ||
| 83 | @@ -592,13 +593,14 @@ | ||
| 84 | sub = build3 (COMPONENT_REF, inner_type, dest, field_index, | ||
| 85 | NULL_TREE); | ||
| 86 | |||
| 87 | - split_nonconstant_init_1 (sub, &value); | ||
| 88 | + if (!split_nonconstant_init_1 (sub, value)) | ||
| 89 | + complete_p = false; | ||
| 90 | + num_split_elts++; | ||
| 91 | } | ||
| 92 | else if (!initializer_constant_valid_p (value, inner_type)) | ||
| 93 | { | ||
| 94 | tree code; | ||
| 95 | tree sub; | ||
| 96 | - HOST_WIDE_INT inner_elements; | ||
| 97 | |||
| 98 | /* FIXME: Ordered removal is O(1) so the whole function is | ||
| 99 | worst-case quadratic. This could be fixed using an aside | ||
| 100 | @@ -622,21 +624,9 @@ | ||
| 101 | code = build_stmt (input_location, EXPR_STMT, code); | ||
| 102 | add_stmt (code); | ||
| 103 | |||
| 104 | - inner_elements = count_type_elements (inner_type, true); | ||
| 105 | - if (inner_elements < 0) | ||
| 106 | - num_initialized_elements = -1; | ||
| 107 | - else if (num_initialized_elements >= 0) | ||
| 108 | - num_initialized_elements += inner_elements; | ||
| 109 | - continue; | ||
| 110 | + num_split_elts++; | ||
| 111 | } | ||
| 112 | } | ||
| 113 | - | ||
| 114 | - num_type_elements = count_type_elements (type, true); | ||
| 115 | - /* If all elements of the initializer are non-constant and | ||
| 116 | - have been split out, we don't need the empty CONSTRUCTOR. */ | ||
| 117 | - if (num_type_elements > 0 | ||
| 118 | - && num_type_elements == num_initialized_elements) | ||
| 119 | - *initp = NULL; | ||
| 120 | break; | ||
| 121 | |||
| 122 | case VECTOR_TYPE: | ||
| 123 | @@ -648,6 +638,7 @@ | ||
| 124 | code = build2 (MODIFY_EXPR, type, dest, cons); | ||
| 125 | code = build_stmt (input_location, EXPR_STMT, code); | ||
| 126 | add_stmt (code); | ||
| 127 | + num_split_elts += CONSTRUCTOR_NELTS (init); | ||
| 128 | } | ||
| 129 | break; | ||
| 130 | |||
| 131 | @@ -657,6 +648,8 @@ | ||
| 132 | |||
| 133 | /* The rest of the initializer is now a constant. */ | ||
| 134 | TREE_CONSTANT (init) = 1; | ||
| 135 | + return complete_p && complete_ctor_at_level_p (TREE_TYPE (init), | ||
| 136 | + num_split_elts, inner_type); | ||
| 137 | } | ||
| 138 | |||
| 139 | /* A subroutine of store_init_value. Splits non-constant static | ||
| 140 | @@ -672,7 +665,8 @@ | ||
| 141 | if (TREE_CODE (init) == CONSTRUCTOR) | ||
| 142 | { | ||
| 143 | code = push_stmt_list (); | ||
| 144 | - split_nonconstant_init_1 (dest, &init); | ||
| 145 | + if (split_nonconstant_init_1 (dest, init)) | ||
| 146 | + init = NULL_TREE; | ||
| 147 | code = pop_stmt_list (code); | ||
| 148 | DECL_INITIAL (dest) = init; | ||
| 149 | TREE_READONLY (dest) = 0; | ||
| 150 | |||
| 151 | === modified file 'gcc/expr.c' | ||
| 152 | --- old/gcc/expr.c 2011-04-20 10:07:36 +0000 | ||
| 153 | +++ new/gcc/expr.c 2011-07-14 11:52:06 +0000 | ||
| 154 | @@ -4860,16 +4860,136 @@ | ||
| 155 | return NULL_RTX; | ||
| 156 | } | ||
| 157 | |||
| 158 | +/* Return true if field F of structure TYPE is a flexible array. */ | ||
| 159 | + | ||
| 160 | +static bool | ||
| 161 | +flexible_array_member_p (const_tree f, const_tree type) | ||
| 162 | +{ | ||
| 163 | + const_tree tf; | ||
| 164 | + | ||
| 165 | + tf = TREE_TYPE (f); | ||
| 166 | + return (TREE_CHAIN (f) == NULL | ||
| 167 | + && TREE_CODE (tf) == ARRAY_TYPE | ||
| 168 | + && TYPE_DOMAIN (tf) | ||
| 169 | + && TYPE_MIN_VALUE (TYPE_DOMAIN (tf)) | ||
| 170 | + && integer_zerop (TYPE_MIN_VALUE (TYPE_DOMAIN (tf))) | ||
| 171 | + && !TYPE_MAX_VALUE (TYPE_DOMAIN (tf)) | ||
| 172 | + && int_size_in_bytes (type) >= 0); | ||
| 173 | +} | ||
| 174 | + | ||
| 175 | +/* If FOR_CTOR_P, return the number of top-level elements that a constructor | ||
| 176 | + must have in order for it to completely initialize a value of type TYPE. | ||
| 177 | + Return -1 if the number isn't known. | ||
| 178 | + | ||
| 179 | + If !FOR_CTOR_P, return an estimate of the number of scalars in TYPE. */ | ||
| 180 | + | ||
| 181 | +static HOST_WIDE_INT | ||
| 182 | +count_type_elements (const_tree type, bool for_ctor_p) | ||
| 183 | +{ | ||
| 184 | + switch (TREE_CODE (type)) | ||
| 185 | + { | ||
| 186 | + case ARRAY_TYPE: | ||
| 187 | + { | ||
| 188 | + tree nelts; | ||
| 189 | + | ||
| 190 | + nelts = array_type_nelts (type); | ||
| 191 | + if (nelts && host_integerp (nelts, 1)) | ||
| 192 | + { | ||
| 193 | + unsigned HOST_WIDE_INT n; | ||
| 194 | + | ||
| 195 | + n = tree_low_cst (nelts, 1) + 1; | ||
| 196 | + if (n == 0 || for_ctor_p) | ||
| 197 | + return n; | ||
| 198 | + else | ||
| 199 | + return n * count_type_elements (TREE_TYPE (type), false); | ||
| 200 | + } | ||
| 201 | + return for_ctor_p ? -1 : 1; | ||
| 202 | + } | ||
| 203 | + | ||
| 204 | + case RECORD_TYPE: | ||
| 205 | + { | ||
| 206 | + unsigned HOST_WIDE_INT n; | ||
| 207 | + tree f; | ||
| 208 | + | ||
| 209 | + n = 0; | ||
| 210 | + for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | ||
| 211 | + if (TREE_CODE (f) == FIELD_DECL) | ||
| 212 | + { | ||
| 213 | + if (!for_ctor_p) | ||
| 214 | + n += count_type_elements (TREE_TYPE (f), false); | ||
| 215 | + else if (!flexible_array_member_p (f, type)) | ||
| 216 | + /* Don't count flexible arrays, which are not supposed | ||
| 217 | + to be initialized. */ | ||
| 218 | + n += 1; | ||
| 219 | + } | ||
| 220 | + | ||
| 221 | + return n; | ||
| 222 | + } | ||
| 223 | + | ||
| 224 | + case UNION_TYPE: | ||
| 225 | + case QUAL_UNION_TYPE: | ||
| 226 | + { | ||
| 227 | + tree f; | ||
| 228 | + HOST_WIDE_INT n, m; | ||
| 229 | + | ||
| 230 | + gcc_assert (!for_ctor_p); | ||
| 231 | + /* Estimate the number of scalars in each field and pick the | ||
| 232 | + maximum. Other estimates would do instead; the idea is simply | ||
| 233 | + to make sure that the estimate is not sensitive to the ordering | ||
| 234 | + of the fields. */ | ||
| 235 | + n = 1; | ||
| 236 | + for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | ||
| 237 | + if (TREE_CODE (f) == FIELD_DECL) | ||
| 238 | + { | ||
| 239 | + m = count_type_elements (TREE_TYPE (f), false); | ||
| 240 | + /* If the field doesn't span the whole union, add an extra | ||
| 241 | + scalar for the rest. */ | ||
| 242 | + if (simple_cst_equal (TYPE_SIZE (TREE_TYPE (f)), | ||
| 243 | + TYPE_SIZE (type)) != 1) | ||
| 244 | + m++; | ||
| 245 | + if (n < m) | ||
| 246 | + n = m; | ||
| 247 | + } | ||
| 248 | + return n; | ||
| 249 | + } | ||
| 250 | + | ||
| 251 | + case COMPLEX_TYPE: | ||
| 252 | + return 2; | ||
| 253 | + | ||
| 254 | + case VECTOR_TYPE: | ||
| 255 | + return TYPE_VECTOR_SUBPARTS (type); | ||
| 256 | + | ||
| 257 | + case INTEGER_TYPE: | ||
| 258 | + case REAL_TYPE: | ||
| 259 | + case FIXED_POINT_TYPE: | ||
| 260 | + case ENUMERAL_TYPE: | ||
| 261 | + case BOOLEAN_TYPE: | ||
| 262 | + case POINTER_TYPE: | ||
| 263 | + case OFFSET_TYPE: | ||
| 264 | + case REFERENCE_TYPE: | ||
| 265 | + return 1; | ||
| 266 | + | ||
| 267 | + case ERROR_MARK: | ||
| 268 | + return 0; | ||
| 269 | + | ||
| 270 | + case VOID_TYPE: | ||
| 271 | + case METHOD_TYPE: | ||
| 272 | + case FUNCTION_TYPE: | ||
| 273 | + case LANG_TYPE: | ||
| 274 | + default: | ||
| 275 | + gcc_unreachable (); | ||
| 276 | + } | ||
| 277 | +} | ||
| 278 | + | ||
| 279 | /* Helper for categorize_ctor_elements. Identical interface. */ | ||
| 280 | |||
| 281 | static bool | ||
| 282 | categorize_ctor_elements_1 (const_tree ctor, HOST_WIDE_INT *p_nz_elts, | ||
| 283 | - HOST_WIDE_INT *p_elt_count, | ||
| 284 | - bool *p_must_clear) | ||
| 285 | + HOST_WIDE_INT *p_init_elts, bool *p_complete) | ||
| 286 | { | ||
| 287 | unsigned HOST_WIDE_INT idx; | ||
| 288 | - HOST_WIDE_INT nz_elts, elt_count; | ||
| 289 | - tree value, purpose; | ||
| 290 | + HOST_WIDE_INT nz_elts, init_elts, num_fields; | ||
| 291 | + tree value, purpose, elt_type; | ||
| 292 | |||
| 293 | /* Whether CTOR is a valid constant initializer, in accordance with what | ||
| 294 | initializer_constant_valid_p does. If inferred from the constructor | ||
| 295 | @@ -4878,7 +4998,9 @@ | ||
| 296 | bool const_p = const_from_elts_p ? true : TREE_STATIC (ctor); | ||
| 297 | |||
| 298 | nz_elts = 0; | ||
| 299 | - elt_count = 0; | ||
| 300 | + init_elts = 0; | ||
| 301 | + num_fields = 0; | ||
| 302 | + elt_type = NULL_TREE; | ||
| 303 | |||
| 304 | FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (ctor), idx, purpose, value) | ||
| 305 | { | ||
| 306 | @@ -4894,6 +5016,8 @@ | ||
| 307 | mult = (tree_low_cst (hi_index, 1) | ||
| 308 | - tree_low_cst (lo_index, 1) + 1); | ||
| 309 | } | ||
| 310 | + num_fields += mult; | ||
| 311 | + elt_type = TREE_TYPE (value); | ||
| 312 | |||
| 313 | switch (TREE_CODE (value)) | ||
| 314 | { | ||
| 315 | @@ -4901,11 +5025,11 @@ | ||
| 316 | { | ||
| 317 | HOST_WIDE_INT nz = 0, ic = 0; | ||
| 318 | |||
| 319 | - bool const_elt_p | ||
| 320 | - = categorize_ctor_elements_1 (value, &nz, &ic, p_must_clear); | ||
| 321 | + bool const_elt_p = categorize_ctor_elements_1 (value, &nz, &ic, | ||
| 322 | + p_complete); | ||
| 323 | |||
| 324 | nz_elts += mult * nz; | ||
| 325 | - elt_count += mult * ic; | ||
| 326 | + init_elts += mult * ic; | ||
| 327 | |||
| 328 | if (const_from_elts_p && const_p) | ||
| 329 | const_p = const_elt_p; | ||
| 330 | @@ -4917,12 +5041,12 @@ | ||
| 331 | case FIXED_CST: | ||
| 332 | if (!initializer_zerop (value)) | ||
| 333 | nz_elts += mult; | ||
| 334 | - elt_count += mult; | ||
| 335 | + init_elts += mult; | ||
| 336 | break; | ||
| 337 | |||
| 338 | case STRING_CST: | ||
| 339 | nz_elts += mult * TREE_STRING_LENGTH (value); | ||
| 340 | - elt_count += mult * TREE_STRING_LENGTH (value); | ||
| 341 | + init_elts += mult * TREE_STRING_LENGTH (value); | ||
| 342 | break; | ||
| 343 | |||
| 344 | case COMPLEX_CST: | ||
| 345 | @@ -4930,7 +5054,7 @@ | ||
| 346 | nz_elts += mult; | ||
| 347 | if (!initializer_zerop (TREE_IMAGPART (value))) | ||
| 348 | nz_elts += mult; | ||
| 349 | - elt_count += mult; | ||
| 350 | + init_elts += mult; | ||
| 351 | break; | ||
| 352 | |||
| 353 | case VECTOR_CST: | ||
| 354 | @@ -4940,60 +5064,31 @@ | ||
| 355 | { | ||
| 356 | if (!initializer_zerop (TREE_VALUE (v))) | ||
| 357 | nz_elts += mult; | ||
| 358 | - elt_count += mult; | ||
| 359 | + init_elts += mult; | ||
| 360 | } | ||
| 361 | } | ||
| 362 | break; | ||
| 363 | |||
| 364 | default: | ||
| 365 | - nz_elts += mult; | ||
| 366 | - elt_count += mult; | ||
| 367 | + { | ||
| 368 | + HOST_WIDE_INT tc = count_type_elements (elt_type, false); | ||
| 369 | + nz_elts += mult * tc; | ||
| 370 | + init_elts += mult * tc; | ||
| 371 | |||
| 372 | - if (const_from_elts_p && const_p) | ||
| 373 | - const_p = initializer_constant_valid_p (value, TREE_TYPE (value)) | ||
| 374 | - != NULL_TREE; | ||
| 375 | + if (const_from_elts_p && const_p) | ||
| 376 | + const_p = initializer_constant_valid_p (value, elt_type) | ||
| 377 | + != NULL_TREE; | ||
| 378 | + } | ||
| 379 | break; | ||
| 380 | } | ||
| 381 | } | ||
| 382 | |||
| 383 | - if (!*p_must_clear | ||
| 384 | - && (TREE_CODE (TREE_TYPE (ctor)) == UNION_TYPE | ||
| 385 | - || TREE_CODE (TREE_TYPE (ctor)) == QUAL_UNION_TYPE)) | ||
| 386 | - { | ||
| 387 | - tree init_sub_type; | ||
| 388 | - bool clear_this = true; | ||
| 389 | - | ||
| 390 | - if (!VEC_empty (constructor_elt, CONSTRUCTOR_ELTS (ctor))) | ||
| 391 | - { | ||
| 392 | - /* We don't expect more than one element of the union to be | ||
| 393 | - initialized. Not sure what we should do otherwise... */ | ||
| 394 | - gcc_assert (VEC_length (constructor_elt, CONSTRUCTOR_ELTS (ctor)) | ||
| 395 | - == 1); | ||
| 396 | - | ||
| 397 | - init_sub_type = TREE_TYPE (VEC_index (constructor_elt, | ||
| 398 | - CONSTRUCTOR_ELTS (ctor), | ||
| 399 | - 0)->value); | ||
| 400 | - | ||
| 401 | - /* ??? We could look at each element of the union, and find the | ||
| 402 | - largest element. Which would avoid comparing the size of the | ||
| 403 | - initialized element against any tail padding in the union. | ||
| 404 | - Doesn't seem worth the effort... */ | ||
| 405 | - if (simple_cst_equal (TYPE_SIZE (TREE_TYPE (ctor)), | ||
| 406 | - TYPE_SIZE (init_sub_type)) == 1) | ||
| 407 | - { | ||
| 408 | - /* And now we have to find out if the element itself is fully | ||
| 409 | - constructed. E.g. for union { struct { int a, b; } s; } u | ||
| 410 | - = { .s = { .a = 1 } }. */ | ||
| 411 | - if (elt_count == count_type_elements (init_sub_type, false)) | ||
| 412 | - clear_this = false; | ||
| 413 | - } | ||
| 414 | - } | ||
| 415 | - | ||
| 416 | - *p_must_clear = clear_this; | ||
| 417 | - } | ||
| 418 | + if (*p_complete && !complete_ctor_at_level_p (TREE_TYPE (ctor), | ||
| 419 | + num_fields, elt_type)) | ||
| 420 | + *p_complete = false; | ||
| 421 | |||
| 422 | *p_nz_elts += nz_elts; | ||
| 423 | - *p_elt_count += elt_count; | ||
| 424 | + *p_init_elts += init_elts; | ||
| 425 | |||
| 426 | return const_p; | ||
| 427 | } | ||
| 428 | @@ -5003,111 +5098,50 @@ | ||
| 429 | and place it in *P_NZ_ELTS; | ||
| 430 | * how many scalar fields in total are in CTOR, | ||
| 431 | and place it in *P_ELT_COUNT. | ||
| 432 | - * if a type is a union, and the initializer from the constructor | ||
| 433 | - is not the largest element in the union, then set *p_must_clear. | ||
| 434 | + * whether the constructor is complete -- in the sense that every | ||
| 435 | + meaningful byte is explicitly given a value -- | ||
| 436 | + and place it in *P_COMPLETE. | ||
| 437 | |||
| 438 | Return whether or not CTOR is a valid static constant initializer, the same | ||
| 439 | as "initializer_constant_valid_p (CTOR, TREE_TYPE (CTOR)) != 0". */ | ||
| 440 | |||
| 441 | bool | ||
| 442 | categorize_ctor_elements (const_tree ctor, HOST_WIDE_INT *p_nz_elts, | ||
| 443 | - HOST_WIDE_INT *p_elt_count, | ||
| 444 | - bool *p_must_clear) | ||
| 445 | + HOST_WIDE_INT *p_init_elts, bool *p_complete) | ||
| 446 | { | ||
| 447 | *p_nz_elts = 0; | ||
| 448 | - *p_elt_count = 0; | ||
| 449 | - *p_must_clear = false; | ||
| 450 | + *p_init_elts = 0; | ||
| 451 | + *p_complete = true; | ||
| 452 | |||
| 453 | - return | ||
| 454 | - categorize_ctor_elements_1 (ctor, p_nz_elts, p_elt_count, p_must_clear); | ||
| 455 | + return categorize_ctor_elements_1 (ctor, p_nz_elts, p_init_elts, p_complete); | ||
| 456 | } | ||
| 457 | |||
| 458 | -/* Count the number of scalars in TYPE. Return -1 on overflow or | ||
| 459 | - variable-sized. If ALLOW_FLEXARR is true, don't count flexible | ||
| 460 | - array member at the end of the structure. */ | ||
| 461 | +/* TYPE is initialized by a constructor with NUM_ELTS elements, the last | ||
| 462 | + of which had type LAST_TYPE. Each element was itself a complete | ||
| 463 | + initializer, in the sense that every meaningful byte was explicitly | ||
| 464 | + given a value. Return true if the same is true for the constructor | ||
| 465 | + as a whole. */ | ||
| 466 | |||
| 467 | -HOST_WIDE_INT | ||
| 468 | -count_type_elements (const_tree type, bool allow_flexarr) | ||
| 469 | +bool | ||
| 470 | +complete_ctor_at_level_p (const_tree type, HOST_WIDE_INT num_elts, | ||
| 471 | + const_tree last_type) | ||
| 472 | { | ||
| 473 | - const HOST_WIDE_INT max = ~((HOST_WIDE_INT)1 << (HOST_BITS_PER_WIDE_INT-1)); | ||
| 474 | - switch (TREE_CODE (type)) | ||
| 475 | + if (TREE_CODE (type) == UNION_TYPE | ||
| 476 | + || TREE_CODE (type) == QUAL_UNION_TYPE) | ||
| 477 | { | ||
| 478 | - case ARRAY_TYPE: | ||
| 479 | - { | ||
| 480 | - tree telts = array_type_nelts (type); | ||
| 481 | - if (telts && host_integerp (telts, 1)) | ||
| 482 | - { | ||
| 483 | - HOST_WIDE_INT n = tree_low_cst (telts, 1) + 1; | ||
| 484 | - HOST_WIDE_INT m = count_type_elements (TREE_TYPE (type), false); | ||
| 485 | - if (n == 0) | ||
| 486 | - return 0; | ||
| 487 | - else if (max / n > m) | ||
| 488 | - return n * m; | ||
| 489 | - } | ||
| 490 | - return -1; | ||
| 491 | - } | ||
| 492 | - | ||
| 493 | - case RECORD_TYPE: | ||
| 494 | - { | ||
| 495 | - HOST_WIDE_INT n = 0, t; | ||
| 496 | - tree f; | ||
| 497 | - | ||
| 498 | - for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f)) | ||
| 499 | - if (TREE_CODE (f) == FIELD_DECL) | ||
| 500 | - { | ||
| 501 | - t = count_type_elements (TREE_TYPE (f), false); | ||
| 502 | - if (t < 0) | ||
| 503 | - { | ||
| 504 | - /* Check for structures with flexible array member. */ | ||
| 505 | - tree tf = TREE_TYPE (f); | ||
| 506 | - if (allow_flexarr | ||
| 507 | - && TREE_CHAIN (f) == NULL | ||
| 508 | - && TREE_CODE (tf) == ARRAY_TYPE | ||
| 509 | - && TYPE_DOMAIN (tf) | ||
| 510 | - && TYPE_MIN_VALUE (TYPE_DOMAIN (tf)) | ||
| 511 | - && integer_zerop (TYPE_MIN_VALUE (TYPE_DOMAIN (tf))) | ||
| 512 | - && !TYPE_MAX_VALUE (TYPE_DOMAIN (tf)) | ||
| 513 | - && int_size_in_bytes (type) >= 0) | ||
| 514 | - break; | ||
| 515 | - | ||
| 516 | - return -1; | ||
| 517 | - } | ||
| 518 | - n += t; | ||
| 519 | - } | ||
| 520 | - | ||
| 521 | - return n; | ||
| 522 | - } | ||
| 523 | - | ||
| 524 | - case UNION_TYPE: | ||
| 525 | - case QUAL_UNION_TYPE: | ||
| 526 | - return -1; | ||
| 527 | - | ||
| 528 | - case COMPLEX_TYPE: | ||
| 529 | - return 2; | ||
| 530 | - | ||
| 531 | - case VECTOR_TYPE: | ||
| 532 | - return TYPE_VECTOR_SUBPARTS (type); | ||
| 533 | - | ||
| 534 | - case INTEGER_TYPE: | ||
| 535 | - case REAL_TYPE: | ||
| 536 | - case FIXED_POINT_TYPE: | ||
| 537 | - case ENUMERAL_TYPE: | ||
| 538 | - case BOOLEAN_TYPE: | ||
| 539 | - case POINTER_TYPE: | ||
| 540 | - case OFFSET_TYPE: | ||
| 541 | - case REFERENCE_TYPE: | ||
| 542 | - return 1; | ||
| 543 | - | ||
| 544 | - case ERROR_MARK: | ||
| 545 | - return 0; | ||
| 546 | - | ||
| 547 | - case VOID_TYPE: | ||
| 548 | - case METHOD_TYPE: | ||
| 549 | - case FUNCTION_TYPE: | ||
| 550 | - case LANG_TYPE: | ||
| 551 | - default: | ||
| 552 | - gcc_unreachable (); | ||
| 553 | + if (num_elts == 0) | ||
| 554 | + return false; | ||
| 555 | + | ||
| 556 | + gcc_assert (num_elts == 1 && last_type); | ||
| 557 | + | ||
| 558 | + /* ??? We could look at each element of the union, and find the | ||
| 559 | + largest element. Which would avoid comparing the size of the | ||
| 560 | + initialized element against any tail padding in the union. | ||
| 561 | + Doesn't seem worth the effort... */ | ||
| 562 | + return simple_cst_equal (TYPE_SIZE (type), TYPE_SIZE (last_type)) == 1; | ||
| 563 | } | ||
| 564 | + | ||
| 565 | + return count_type_elements (type, true) == num_elts; | ||
| 566 | } | ||
| 567 | |||
| 568 | /* Return 1 if EXP contains mostly (3/4) zeros. */ | ||
| 569 | @@ -5116,18 +5150,12 @@ | ||
| 570 | mostly_zeros_p (const_tree exp) | ||
| 571 | { | ||
| 572 | if (TREE_CODE (exp) == CONSTRUCTOR) | ||
| 573 | - | ||
| 574 | { | ||
| 575 | - HOST_WIDE_INT nz_elts, count, elts; | ||
| 576 | - bool must_clear; | ||
| 577 | - | ||
| 578 | - categorize_ctor_elements (exp, &nz_elts, &count, &must_clear); | ||
| 579 | - if (must_clear) | ||
| 580 | - return 1; | ||
| 581 | - | ||
| 582 | - elts = count_type_elements (TREE_TYPE (exp), false); | ||
| 583 | - | ||
| 584 | - return nz_elts < elts / 4; | ||
| 585 | + HOST_WIDE_INT nz_elts, init_elts; | ||
| 586 | + bool complete_p; | ||
| 587 | + | ||
| 588 | + categorize_ctor_elements (exp, &nz_elts, &init_elts, &complete_p); | ||
| 589 | + return !complete_p || nz_elts < init_elts / 4; | ||
| 590 | } | ||
| 591 | |||
| 592 | return initializer_zerop (exp); | ||
| 593 | @@ -5139,12 +5167,11 @@ | ||
| 594 | all_zeros_p (const_tree exp) | ||
| 595 | { | ||
| 596 | if (TREE_CODE (exp) == CONSTRUCTOR) | ||
| 597 | - | ||
| 598 | { | ||
| 599 | - HOST_WIDE_INT nz_elts, count; | ||
| 600 | - bool must_clear; | ||
| 601 | + HOST_WIDE_INT nz_elts, init_elts; | ||
| 602 | + bool complete_p; | ||
| 603 | |||
| 604 | - categorize_ctor_elements (exp, &nz_elts, &count, &must_clear); | ||
| 605 | + categorize_ctor_elements (exp, &nz_elts, &init_elts, &complete_p); | ||
| 606 | return nz_elts == 0; | ||
| 607 | } | ||
| 608 | |||
| 609 | |||
| 610 | === modified file 'gcc/gimplify.c' | ||
| 611 | --- old/gcc/gimplify.c 2011-04-07 18:27:20 +0000 | ||
| 612 | +++ new/gcc/gimplify.c 2011-07-13 13:36:36 +0000 | ||
| 613 | @@ -3634,9 +3634,8 @@ | ||
| 614 | case ARRAY_TYPE: | ||
| 615 | { | ||
| 616 | struct gimplify_init_ctor_preeval_data preeval_data; | ||
| 617 | - HOST_WIDE_INT num_type_elements, num_ctor_elements; | ||
| 618 | - HOST_WIDE_INT num_nonzero_elements; | ||
| 619 | - bool cleared, valid_const_initializer; | ||
| 620 | + HOST_WIDE_INT num_ctor_elements, num_nonzero_elements; | ||
| 621 | + bool cleared, complete_p, valid_const_initializer; | ||
| 622 | |||
| 623 | /* Aggregate types must lower constructors to initialization of | ||
| 624 | individual elements. The exception is that a CONSTRUCTOR node | ||
| 625 | @@ -3653,7 +3652,7 @@ | ||
| 626 | can only do so if it known to be a valid constant initializer. */ | ||
| 627 | valid_const_initializer | ||
| 628 | = categorize_ctor_elements (ctor, &num_nonzero_elements, | ||
| 629 | - &num_ctor_elements, &cleared); | ||
| 630 | + &num_ctor_elements, &complete_p); | ||
| 631 | |||
| 632 | /* If a const aggregate variable is being initialized, then it | ||
| 633 | should never be a lose to promote the variable to be static. */ | ||
| 634 | @@ -3691,26 +3690,29 @@ | ||
| 635 | parts in, then generate code for the non-constant parts. */ | ||
| 636 | /* TODO. There's code in cp/typeck.c to do this. */ | ||
| 637 | |||
| 638 | - num_type_elements = count_type_elements (type, true); | ||
| 639 | + if (int_size_in_bytes (TREE_TYPE (ctor)) < 0) | ||
| 640 | + /* store_constructor will ignore the clearing of variable-sized | ||
| 641 | + objects. Initializers for such objects must explicitly set | ||
| 642 | + every field that needs to be set. */ | ||
| 643 | + cleared = false; | ||
| 644 | + else if (!complete_p) | ||
| 645 | + /* If the constructor isn't complete, clear the whole object | ||
| 646 | + beforehand. | ||
| 647 | |||
| 648 | - /* If count_type_elements could not determine number of type elements | ||
| 649 | - for a constant-sized object, assume clearing is needed. | ||
| 650 | - Don't do this for variable-sized objects, as store_constructor | ||
| 651 | - will ignore the clearing of variable-sized objects. */ | ||
| 652 | - if (num_type_elements < 0 && int_size_in_bytes (type) >= 0) | ||
| 653 | + ??? This ought not to be needed. For any element not present | ||
| 654 | + in the initializer, we should simply set them to zero. Except | ||
| 655 | + we'd need to *find* the elements that are not present, and that | ||
| 656 | + requires trickery to avoid quadratic compile-time behavior in | ||
| 657 | + large cases or excessive memory use in small cases. */ | ||
| 658 | cleared = true; | ||
| 659 | - /* If there are "lots" of zeros, then block clear the object first. */ | ||
| 660 | - else if (num_type_elements - num_nonzero_elements | ||
| 661 | + else if (num_ctor_elements - num_nonzero_elements | ||
| 662 | > CLEAR_RATIO (optimize_function_for_speed_p (cfun)) | ||
| 663 | - && num_nonzero_elements < num_type_elements/4) | ||
| 664 | - cleared = true; | ||
| 665 | - /* ??? This bit ought not be needed. For any element not present | ||
| 666 | - in the initializer, we should simply set them to zero. Except | ||
| 667 | - we'd need to *find* the elements that are not present, and that | ||
| 668 | - requires trickery to avoid quadratic compile-time behavior in | ||
| 669 | - large cases or excessive memory use in small cases. */ | ||
| 670 | - else if (num_ctor_elements < num_type_elements) | ||
| 671 | - cleared = true; | ||
| 672 | + && num_nonzero_elements < num_ctor_elements / 4) | ||
| 673 | + /* If there are "lots" of zeros, it's more efficient to clear | ||
| 674 | + the memory and then set the nonzero elements. */ | ||
| 675 | + cleared = true; | ||
| 676 | + else | ||
| 677 | + cleared = false; | ||
| 678 | |||
| 679 | /* If there are "lots" of initialized elements, and all of them | ||
| 680 | are valid address constants, then the entire initializer can | ||
| 681 | |||
| 682 | === added file 'gcc/testsuite/gcc.target/arm/pr48183.c' | ||
| 683 | --- old/gcc/testsuite/gcc.target/arm/pr48183.c 1970-01-01 00:00:00 +0000 | ||
| 684 | +++ new/gcc/testsuite/gcc.target/arm/pr48183.c 2011-07-13 13:36:36 +0000 | ||
| 685 | @@ -0,0 +1,25 @@ | ||
| 686 | +/* testsuite/gcc.target/arm/pr48183.c */ | ||
| 687 | + | ||
| 688 | +/* { dg-do compile } */ | ||
| 689 | +/* { dg-require-effective-target arm_neon_ok } */ | ||
| 690 | +/* { dg-options "-O -g" } */ | ||
| 691 | +/* { dg-add-options arm_neon } */ | ||
| 692 | + | ||
| 693 | +#include <arm_neon.h> | ||
| 694 | + | ||
| 695 | +void move_16bit_to_32bit (int32_t *dst, const short *src, unsigned n) | ||
| 696 | +{ | ||
| 697 | + unsigned i; | ||
| 698 | + int16x4x2_t input; | ||
| 699 | + int32x4x2_t mid; | ||
| 700 | + int32x4x2_t output; | ||
| 701 | + | ||
| 702 | + for (i = 0; i < n/2; i += 8) { | ||
| 703 | + input = vld2_s16(src + i); | ||
| 704 | + mid.val[0] = vmovl_s16(input.val[0]); | ||
| 705 | + mid.val[1] = vmovl_s16(input.val[1]); | ||
| 706 | + output.val[0] = vshlq_n_s32(mid.val[0], 8); | ||
| 707 | + output.val[1] = vshlq_n_s32(mid.val[1], 8); | ||
| 708 | + vst2q_s32((int32_t *)dst + i, output); | ||
| 709 | + } | ||
| 710 | +} | ||
| 711 | |||
| 712 | === modified file 'gcc/tree.h' | ||
| 713 | --- old/gcc/tree.h 2011-04-06 12:29:08 +0000 | ||
| 714 | +++ new/gcc/tree.h 2011-07-13 13:36:36 +0000 | ||
| 715 | @@ -4361,21 +4361,10 @@ | ||
| 716 | |||
| 717 | extern VEC(tree,gc) *ctor_to_vec (tree); | ||
| 718 | |||
| 719 | -/* Examine CTOR to discover: | ||
| 720 | - * how many scalar fields are set to nonzero values, | ||
| 721 | - and place it in *P_NZ_ELTS; | ||
| 722 | - * how many scalar fields in total are in CTOR, | ||
| 723 | - and place it in *P_ELT_COUNT. | ||
| 724 | - * if a type is a union, and the initializer from the constructor | ||
| 725 | - is not the largest element in the union, then set *p_must_clear. | ||
| 726 | - | ||
| 727 | - Return whether or not CTOR is a valid static constant initializer, the same | ||
| 728 | - as "initializer_constant_valid_p (CTOR, TREE_TYPE (CTOR)) != 0". */ | ||
| 729 | - | ||
| 730 | -extern bool categorize_ctor_elements (const_tree, HOST_WIDE_INT *, HOST_WIDE_INT *, | ||
| 731 | - bool *); | ||
| 732 | - | ||
| 733 | -extern HOST_WIDE_INT count_type_elements (const_tree, bool); | ||
| 734 | +extern bool categorize_ctor_elements (const_tree, HOST_WIDE_INT *, | ||
| 735 | + HOST_WIDE_INT *, bool *); | ||
| 736 | + | ||
| 737 | +extern bool complete_ctor_at_level_p (const_tree, HOST_WIDE_INT, const_tree); | ||
| 738 | |||
| 739 | /* integer_zerop (tree x) is nonzero if X is an integer constant of value 0. */ | ||
| 740 | |||
| 741 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99530.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99530.patch deleted file mode 100644 index 64d6262d6..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99530.patch +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | 2011-07-21 Richard Sandiford <rdsandiford@googlemail.com> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | Backport from mainline: | ||
| 5 | |||
| 6 | 2011-07-21 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 7 | |||
| 8 | * regcprop.c (maybe_mode_change): Check HARD_REGNO_MODE_OK. | ||
| 9 | |||
| 10 | === modified file 'gcc/regcprop.c' | ||
| 11 | --- old/gcc/regcprop.c 2010-08-05 15:28:47 +0000 | ||
| 12 | +++ new/gcc/regcprop.c 2011-07-21 12:40:44 +0000 | ||
| 13 | @@ -418,10 +418,9 @@ | ||
| 14 | |||
| 15 | offset = ((WORDS_BIG_ENDIAN ? wordoffset : 0) | ||
| 16 | + (BYTES_BIG_ENDIAN ? byteoffset : 0)); | ||
| 17 | - return gen_rtx_raw_REG (new_mode, | ||
| 18 | - regno + subreg_regno_offset (regno, orig_mode, | ||
| 19 | - offset, | ||
| 20 | - new_mode)); | ||
| 21 | + regno += subreg_regno_offset (regno, orig_mode, offset, new_mode); | ||
| 22 | + if (HARD_REGNO_MODE_OK (regno, new_mode)) | ||
| 23 | + return gen_rtx_raw_REG (new_mode, regno); | ||
| 24 | } | ||
| 25 | return NULL_RTX; | ||
| 26 | } | ||
| 27 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99531.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99531.patch deleted file mode 100644 index 5559dfeda..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99531.patch +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | 2011-07-29 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | Backport only bits marked as [*] from mainline: | ||
| 5 | 2010-12-19 Chung-Lin Tang <cltang@codesourcery.com> | ||
| 6 | |||
| 7 | * config/arm/arm.c ([*]arm_legitimate_index_p): Add VFP load/store | ||
| 8 | index range case. Change to SF/DFmode tests to avoid capturing HFmode. | ||
| 9 | (thumb2_legitimate_index_p): Same. | ||
| 10 | |||
| 11 | === modified file 'gcc/config/arm/arm.c' | ||
| 12 | --- old/gcc/config/arm/arm.c 2011-06-29 10:46:39 +0000 | ||
| 13 | +++ new/gcc/config/arm/arm.c 2011-07-29 15:01:53 +0000 | ||
| 14 | @@ -5643,8 +5643,8 @@ | ||
| 15 | |||
| 16 | /* Standard coprocessor addressing modes. */ | ||
| 17 | if (TARGET_HARD_FLOAT | ||
| 18 | - && (TARGET_FPA || TARGET_MAVERICK) | ||
| 19 | - && (GET_MODE_CLASS (mode) == MODE_FLOAT | ||
| 20 | + && (TARGET_FPA || TARGET_MAVERICK || TARGET_VFP) | ||
| 21 | + && ((mode == SFmode || mode == DFmode) | ||
| 22 | || (TARGET_MAVERICK && mode == DImode))) | ||
| 23 | return (code == CONST_INT && INTVAL (index) < 1024 | ||
| 24 | && INTVAL (index) > -1024 | ||
| 25 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99532.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99532.patch deleted file mode 100644 index 0c2c02b6f..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99532.patch +++ /dev/null | |||
| @@ -1,456 +0,0 @@ | |||
| 1 | 2011-08-03 Revital Eres <revital.eres@linaro.org> | ||
| 2 | |||
| 3 | * modulo-sched.c (calculate_stage_count, | ||
| 4 | calculate_must_precede_follow, get_sched_window, | ||
| 5 | try_scheduling_node_in_cycle, remove_node_from_ps): Add | ||
| 6 | declaration. | ||
| 7 | (update_node_sched_params, set_must_precede_follow, optimize_sc): | ||
| 8 | New functions. | ||
| 9 | (reset_sched_times): Call update_node_sched_params. | ||
| 10 | (sms_schedule): Call optimize_sc. | ||
| 11 | (get_sched_window): Change function arguments. | ||
| 12 | (sms_schedule_by_order): Update call to get_sched_window. | ||
| 13 | Call set_must_precede_follow. | ||
| 14 | (calculate_stage_count): Add function argument. | ||
| 15 | |||
| 16 | === modified file 'gcc/modulo-sched.c' | ||
| 17 | --- old/gcc/modulo-sched.c 2011-07-04 11:39:09 +0000 | ||
| 18 | +++ new/gcc/modulo-sched.c 2011-08-03 12:20:38 +0000 | ||
| 19 | @@ -202,7 +202,16 @@ | ||
| 20 | rtx, rtx); | ||
| 21 | static void duplicate_insns_of_cycles (partial_schedule_ptr, | ||
| 22 | int, int, int, rtx); | ||
| 23 | -static int calculate_stage_count (partial_schedule_ptr ps); | ||
| 24 | +static int calculate_stage_count (partial_schedule_ptr, int); | ||
| 25 | +static void calculate_must_precede_follow (ddg_node_ptr, int, int, | ||
| 26 | + int, int, sbitmap, sbitmap, sbitmap); | ||
| 27 | +static int get_sched_window (partial_schedule_ptr, ddg_node_ptr, | ||
| 28 | + sbitmap, int, int *, int *, int *); | ||
| 29 | +static bool try_scheduling_node_in_cycle (partial_schedule_ptr, ddg_node_ptr, | ||
| 30 | + int, int, sbitmap, int *, sbitmap, | ||
| 31 | + sbitmap); | ||
| 32 | +static bool remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr); | ||
| 33 | + | ||
| 34 | #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap) | ||
| 35 | #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time) | ||
| 36 | #define SCHED_FIRST_REG_MOVE(x) \ | ||
| 37 | @@ -576,6 +585,36 @@ | ||
| 38 | } | ||
| 39 | } | ||
| 40 | |||
| 41 | +/* Update the sched_params (time, row and stage) for node U using the II, | ||
| 42 | + the CYCLE of U and MIN_CYCLE. | ||
| 43 | + We're not simply taking the following | ||
| 44 | + SCHED_STAGE (u) = CALC_STAGE_COUNT (SCHED_TIME (u), min_cycle, ii); | ||
| 45 | + because the stages may not be aligned on cycle 0. */ | ||
| 46 | +static void | ||
| 47 | +update_node_sched_params (ddg_node_ptr u, int ii, int cycle, int min_cycle) | ||
| 48 | +{ | ||
| 49 | + int sc_until_cycle_zero; | ||
| 50 | + int stage; | ||
| 51 | + | ||
| 52 | + SCHED_TIME (u) = cycle; | ||
| 53 | + SCHED_ROW (u) = SMODULO (cycle, ii); | ||
| 54 | + | ||
| 55 | + /* The calculation of stage count is done adding the number | ||
| 56 | + of stages before cycle zero and after cycle zero. */ | ||
| 57 | + sc_until_cycle_zero = CALC_STAGE_COUNT (-1, min_cycle, ii); | ||
| 58 | + | ||
| 59 | + if (SCHED_TIME (u) < 0) | ||
| 60 | + { | ||
| 61 | + stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii); | ||
| 62 | + SCHED_STAGE (u) = sc_until_cycle_zero - stage; | ||
| 63 | + } | ||
| 64 | + else | ||
| 65 | + { | ||
| 66 | + stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii); | ||
| 67 | + SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1; | ||
| 68 | + } | ||
| 69 | +} | ||
| 70 | + | ||
| 71 | /* Bump the SCHED_TIMEs of all nodes by AMOUNT. Set the values of | ||
| 72 | SCHED_ROW and SCHED_STAGE. */ | ||
| 73 | static void | ||
| 74 | @@ -591,7 +630,6 @@ | ||
| 75 | ddg_node_ptr u = crr_insn->node; | ||
| 76 | int normalized_time = SCHED_TIME (u) - amount; | ||
| 77 | int new_min_cycle = PS_MIN_CYCLE (ps) - amount; | ||
| 78 | - int sc_until_cycle_zero, stage; | ||
| 79 | |||
| 80 | if (dump_file) | ||
| 81 | { | ||
| 82 | @@ -607,23 +645,9 @@ | ||
| 83 | |||
| 84 | gcc_assert (SCHED_TIME (u) >= ps->min_cycle); | ||
| 85 | gcc_assert (SCHED_TIME (u) <= ps->max_cycle); | ||
| 86 | - SCHED_TIME (u) = normalized_time; | ||
| 87 | - SCHED_ROW (u) = SMODULO (normalized_time, ii); | ||
| 88 | - | ||
| 89 | - /* The calculation of stage count is done adding the number | ||
| 90 | - of stages before cycle zero and after cycle zero. */ | ||
| 91 | - sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii); | ||
| 92 | - | ||
| 93 | - if (SCHED_TIME (u) < 0) | ||
| 94 | - { | ||
| 95 | - stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii); | ||
| 96 | - SCHED_STAGE (u) = sc_until_cycle_zero - stage; | ||
| 97 | - } | ||
| 98 | - else | ||
| 99 | - { | ||
| 100 | - stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii); | ||
| 101 | - SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1; | ||
| 102 | - } | ||
| 103 | + | ||
| 104 | + crr_insn->cycle = normalized_time; | ||
| 105 | + update_node_sched_params (u, ii, normalized_time, new_min_cycle); | ||
| 106 | } | ||
| 107 | } | ||
| 108 | |||
| 109 | @@ -660,6 +684,206 @@ | ||
| 110 | PREV_INSN (last)); | ||
| 111 | } | ||
| 112 | |||
| 113 | +/* Set bitmaps TMP_FOLLOW and TMP_PRECEDE to MUST_FOLLOW and MUST_PRECEDE | ||
| 114 | + respectively only if cycle C falls on the border of the scheduling | ||
| 115 | + window boundaries marked by START and END cycles. STEP is the | ||
| 116 | + direction of the window. */ | ||
| 117 | +static inline void | ||
| 118 | +set_must_precede_follow (sbitmap *tmp_follow, sbitmap must_follow, | ||
| 119 | + sbitmap *tmp_precede, sbitmap must_precede, int c, | ||
| 120 | + int start, int end, int step) | ||
| 121 | +{ | ||
| 122 | + *tmp_precede = NULL; | ||
| 123 | + *tmp_follow = NULL; | ||
| 124 | + | ||
| 125 | + if (c == start) | ||
| 126 | + { | ||
| 127 | + if (step == 1) | ||
| 128 | + *tmp_precede = must_precede; | ||
| 129 | + else /* step == -1. */ | ||
| 130 | + *tmp_follow = must_follow; | ||
| 131 | + } | ||
| 132 | + if (c == end - step) | ||
| 133 | + { | ||
| 134 | + if (step == 1) | ||
| 135 | + *tmp_follow = must_follow; | ||
| 136 | + else /* step == -1. */ | ||
| 137 | + *tmp_precede = must_precede; | ||
| 138 | + } | ||
| 139 | + | ||
| 140 | +} | ||
| 141 | + | ||
| 142 | +/* Return True if the branch can be moved to row ii-1 while | ||
| 143 | + normalizing the partial schedule PS to start from cycle zero and thus | ||
| 144 | + optimize the SC. Otherwise return False. */ | ||
| 145 | +static bool | ||
| 146 | +optimize_sc (partial_schedule_ptr ps, ddg_ptr g) | ||
| 147 | +{ | ||
| 148 | + int amount = PS_MIN_CYCLE (ps); | ||
| 149 | + sbitmap sched_nodes = sbitmap_alloc (g->num_nodes); | ||
| 150 | + int start, end, step; | ||
| 151 | + int ii = ps->ii; | ||
| 152 | + bool ok = false; | ||
| 153 | + int stage_count, stage_count_curr; | ||
| 154 | + | ||
| 155 | + /* Compare the SC after normalization and SC after bringing the branch | ||
| 156 | + to row ii-1. If they are equal just bail out. */ | ||
| 157 | + stage_count = calculate_stage_count (ps, amount); | ||
| 158 | + stage_count_curr = | ||
| 159 | + calculate_stage_count (ps, SCHED_TIME (g->closing_branch) - (ii - 1)); | ||
| 160 | + | ||
| 161 | + if (stage_count == stage_count_curr) | ||
| 162 | + { | ||
| 163 | + if (dump_file) | ||
| 164 | + fprintf (dump_file, "SMS SC already optimized.\n"); | ||
| 165 | + | ||
| 166 | + ok = false; | ||
| 167 | + goto clear; | ||
| 168 | + } | ||
| 169 | + | ||
| 170 | + if (dump_file) | ||
| 171 | + { | ||
| 172 | + fprintf (dump_file, "SMS Trying to optimize branch location\n"); | ||
| 173 | + fprintf (dump_file, "SMS partial schedule before trial:\n"); | ||
| 174 | + print_partial_schedule (ps, dump_file); | ||
| 175 | + } | ||
| 176 | + | ||
| 177 | + /* First, normalize the partial scheduling. */ | ||
| 178 | + reset_sched_times (ps, amount); | ||
| 179 | + rotate_partial_schedule (ps, amount); | ||
| 180 | + if (dump_file) | ||
| 181 | + { | ||
| 182 | + fprintf (dump_file, | ||
| 183 | + "SMS partial schedule after normalization (ii, %d, SC %d):\n", | ||
| 184 | + ii, stage_count); | ||
| 185 | + print_partial_schedule (ps, dump_file); | ||
| 186 | + } | ||
| 187 | + | ||
| 188 | + if (SMODULO (SCHED_TIME (g->closing_branch), ii) == ii - 1) | ||
| 189 | + { | ||
| 190 | + ok = true; | ||
| 191 | + goto clear; | ||
| 192 | + } | ||
| 193 | + | ||
| 194 | + sbitmap_ones (sched_nodes); | ||
| 195 | + | ||
| 196 | + /* Calculate the new placement of the branch. It should be in row | ||
| 197 | + ii-1 and fall into it's scheduling window. */ | ||
| 198 | + if (get_sched_window (ps, g->closing_branch, sched_nodes, ii, &start, | ||
| 199 | + &step, &end) == 0) | ||
| 200 | + { | ||
| 201 | + bool success; | ||
| 202 | + ps_insn_ptr next_ps_i; | ||
| 203 | + int branch_cycle = SCHED_TIME (g->closing_branch); | ||
| 204 | + int row = SMODULO (branch_cycle, ps->ii); | ||
| 205 | + int num_splits = 0; | ||
| 206 | + sbitmap must_precede, must_follow, tmp_precede, tmp_follow; | ||
| 207 | + int c; | ||
| 208 | + | ||
| 209 | + if (dump_file) | ||
| 210 | + fprintf (dump_file, "\nTrying to schedule node %d " | ||
| 211 | + "INSN = %d in (%d .. %d) step %d\n", | ||
| 212 | + g->closing_branch->cuid, | ||
| 213 | + (INSN_UID (g->closing_branch->insn)), start, end, step); | ||
| 214 | + | ||
| 215 | + gcc_assert ((step > 0 && start < end) || (step < 0 && start > end)); | ||
| 216 | + if (step == 1) | ||
| 217 | + { | ||
| 218 | + c = start + ii - SMODULO (start, ii) - 1; | ||
| 219 | + gcc_assert (c >= start); | ||
| 220 | + if (c >= end) | ||
| 221 | + { | ||
| 222 | + ok = false; | ||
| 223 | + if (dump_file) | ||
| 224 | + fprintf (dump_file, | ||
| 225 | + "SMS failed to schedule branch at cycle: %d\n", c); | ||
| 226 | + goto clear; | ||
| 227 | + } | ||
| 228 | + } | ||
| 229 | + else | ||
| 230 | + { | ||
| 231 | + c = start - SMODULO (start, ii) - 1; | ||
| 232 | + gcc_assert (c <= start); | ||
| 233 | + | ||
| 234 | + if (c <= end) | ||
| 235 | + { | ||
| 236 | + if (dump_file) | ||
| 237 | + fprintf (dump_file, | ||
| 238 | + "SMS failed to schedule branch at cycle: %d\n", c); | ||
| 239 | + ok = false; | ||
| 240 | + goto clear; | ||
| 241 | + } | ||
| 242 | + } | ||
| 243 | + | ||
| 244 | + must_precede = sbitmap_alloc (g->num_nodes); | ||
| 245 | + must_follow = sbitmap_alloc (g->num_nodes); | ||
| 246 | + | ||
| 247 | + /* Try to schedule the branch is it's new cycle. */ | ||
| 248 | + calculate_must_precede_follow (g->closing_branch, start, end, | ||
| 249 | + step, ii, sched_nodes, | ||
| 250 | + must_precede, must_follow); | ||
| 251 | + | ||
| 252 | + set_must_precede_follow (&tmp_follow, must_follow, &tmp_precede, | ||
| 253 | + must_precede, c, start, end, step); | ||
| 254 | + | ||
| 255 | + /* Find the element in the partial schedule related to the closing | ||
| 256 | + branch so we can remove it from it's current cycle. */ | ||
| 257 | + for (next_ps_i = ps->rows[row]; | ||
| 258 | + next_ps_i; next_ps_i = next_ps_i->next_in_row) | ||
| 259 | + if (next_ps_i->node->cuid == g->closing_branch->cuid) | ||
| 260 | + break; | ||
| 261 | + | ||
| 262 | + gcc_assert (next_ps_i); | ||
| 263 | + gcc_assert (remove_node_from_ps (ps, next_ps_i)); | ||
| 264 | + success = | ||
| 265 | + try_scheduling_node_in_cycle (ps, g->closing_branch, | ||
| 266 | + g->closing_branch->cuid, c, | ||
| 267 | + sched_nodes, &num_splits, | ||
| 268 | + tmp_precede, tmp_follow); | ||
| 269 | + gcc_assert (num_splits == 0); | ||
| 270 | + if (!success) | ||
| 271 | + { | ||
| 272 | + if (dump_file) | ||
| 273 | + fprintf (dump_file, | ||
| 274 | + "SMS failed to schedule branch at cycle: %d, " | ||
| 275 | + "bringing it back to cycle %d\n", c, branch_cycle); | ||
| 276 | + | ||
| 277 | + /* The branch was failed to be placed in row ii - 1. | ||
| 278 | + Put it back in it's original place in the partial | ||
| 279 | + schedualing. */ | ||
| 280 | + set_must_precede_follow (&tmp_follow, must_follow, &tmp_precede, | ||
| 281 | + must_precede, branch_cycle, start, end, | ||
| 282 | + step); | ||
| 283 | + success = | ||
| 284 | + try_scheduling_node_in_cycle (ps, g->closing_branch, | ||
| 285 | + g->closing_branch->cuid, | ||
| 286 | + branch_cycle, sched_nodes, | ||
| 287 | + &num_splits, tmp_precede, | ||
| 288 | + tmp_follow); | ||
| 289 | + gcc_assert (success && (num_splits == 0)); | ||
| 290 | + ok = false; | ||
| 291 | + } | ||
| 292 | + else | ||
| 293 | + { | ||
| 294 | + /* The branch is placed in row ii - 1. */ | ||
| 295 | + if (dump_file) | ||
| 296 | + fprintf (dump_file, | ||
| 297 | + "SMS success in moving branch to cycle %d\n", c); | ||
| 298 | + | ||
| 299 | + update_node_sched_params (g->closing_branch, ii, c, | ||
| 300 | + PS_MIN_CYCLE (ps)); | ||
| 301 | + ok = true; | ||
| 302 | + } | ||
| 303 | + | ||
| 304 | + free (must_precede); | ||
| 305 | + free (must_follow); | ||
| 306 | + } | ||
| 307 | + | ||
| 308 | +clear: | ||
| 309 | + free (sched_nodes); | ||
| 310 | + return ok; | ||
| 311 | +} | ||
| 312 | + | ||
| 313 | static void | ||
| 314 | duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage, | ||
| 315 | int to_stage, int for_prolog, rtx count_reg) | ||
| 316 | @@ -1115,6 +1339,7 @@ | ||
| 317 | int mii, rec_mii; | ||
| 318 | unsigned stage_count = 0; | ||
| 319 | HOST_WIDEST_INT loop_count = 0; | ||
| 320 | + bool opt_sc_p = false; | ||
| 321 | |||
| 322 | if (! (g = g_arr[loop->num])) | ||
| 323 | continue; | ||
| 324 | @@ -1196,14 +1421,32 @@ | ||
| 325 | set_node_sched_params (g); | ||
| 326 | |||
| 327 | ps = sms_schedule_by_order (g, mii, maxii, node_order); | ||
| 328 | - | ||
| 329 | - if (ps) | ||
| 330 | - { | ||
| 331 | - stage_count = calculate_stage_count (ps); | ||
| 332 | - gcc_assert(stage_count >= 1); | ||
| 333 | - PS_STAGE_COUNT(ps) = stage_count; | ||
| 334 | - } | ||
| 335 | - | ||
| 336 | + | ||
| 337 | + if (ps) | ||
| 338 | + { | ||
| 339 | + /* Try to achieve optimized SC by normalizing the partial | ||
| 340 | + schedule (having the cycles start from cycle zero). | ||
| 341 | + The branch location must be placed in row ii-1 in the | ||
| 342 | + final scheduling. If failed, shift all instructions to | ||
| 343 | + position the branch in row ii-1. */ | ||
| 344 | + opt_sc_p = optimize_sc (ps, g); | ||
| 345 | + if (opt_sc_p) | ||
| 346 | + stage_count = calculate_stage_count (ps, 0); | ||
| 347 | + else | ||
| 348 | + { | ||
| 349 | + /* Bring the branch to cycle ii-1. */ | ||
| 350 | + int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1); | ||
| 351 | + | ||
| 352 | + if (dump_file) | ||
| 353 | + fprintf (dump_file, "SMS schedule branch at cycle ii-1\n"); | ||
| 354 | + | ||
| 355 | + stage_count = calculate_stage_count (ps, amount); | ||
| 356 | + } | ||
| 357 | + | ||
| 358 | + gcc_assert (stage_count >= 1); | ||
| 359 | + PS_STAGE_COUNT (ps) = stage_count; | ||
| 360 | + } | ||
| 361 | + | ||
| 362 | /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of | ||
| 363 | 1 means that there is no interleaving between iterations thus | ||
| 364 | we let the scheduling passes do the job in this case. */ | ||
| 365 | @@ -1224,12 +1467,16 @@ | ||
| 366 | else | ||
| 367 | { | ||
| 368 | struct undo_replace_buff_elem *reg_move_replaces; | ||
| 369 | - int amount = SCHED_TIME (g->closing_branch) + 1; | ||
| 370 | + | ||
| 371 | + if (!opt_sc_p) | ||
| 372 | + { | ||
| 373 | + /* Rotate the partial schedule to have the branch in row ii-1. */ | ||
| 374 | + int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1); | ||
| 375 | + | ||
| 376 | + reset_sched_times (ps, amount); | ||
| 377 | + rotate_partial_schedule (ps, amount); | ||
| 378 | + } | ||
| 379 | |||
| 380 | - /* Set the stage boundaries. The closing_branch was scheduled | ||
| 381 | - and should appear in the last (ii-1) row. */ | ||
| 382 | - reset_sched_times (ps, amount); | ||
| 383 | - rotate_partial_schedule (ps, amount); | ||
| 384 | set_columns_for_ps (ps); | ||
| 385 | |||
| 386 | canon_loop (loop); | ||
| 387 | @@ -1381,13 +1628,11 @@ | ||
| 388 | scheduling window is empty and zero otherwise. */ | ||
| 389 | |||
| 390 | static int | ||
| 391 | -get_sched_window (partial_schedule_ptr ps, int *nodes_order, int i, | ||
| 392 | +get_sched_window (partial_schedule_ptr ps, ddg_node_ptr u_node, | ||
| 393 | sbitmap sched_nodes, int ii, int *start_p, int *step_p, int *end_p) | ||
| 394 | { | ||
| 395 | int start, step, end; | ||
| 396 | ddg_edge_ptr e; | ||
| 397 | - int u = nodes_order [i]; | ||
| 398 | - ddg_node_ptr u_node = &ps->g->nodes[u]; | ||
| 399 | sbitmap psp = sbitmap_alloc (ps->g->num_nodes); | ||
| 400 | sbitmap pss = sbitmap_alloc (ps->g->num_nodes); | ||
| 401 | sbitmap u_node_preds = NODE_PREDECESSORS (u_node); | ||
| 402 | @@ -1799,7 +2044,7 @@ | ||
| 403 | |||
| 404 | /* Try to get non-empty scheduling window. */ | ||
| 405 | success = 0; | ||
| 406 | - if (get_sched_window (ps, nodes_order, i, sched_nodes, ii, &start, | ||
| 407 | + if (get_sched_window (ps, u_node, sched_nodes, ii, &start, | ||
| 408 | &step, &end) == 0) | ||
| 409 | { | ||
| 410 | if (dump_file) | ||
| 411 | @@ -1816,24 +2061,11 @@ | ||
| 412 | |||
| 413 | for (c = start; c != end; c += step) | ||
| 414 | { | ||
| 415 | - sbitmap tmp_precede = NULL; | ||
| 416 | - sbitmap tmp_follow = NULL; | ||
| 417 | - | ||
| 418 | - if (c == start) | ||
| 419 | - { | ||
| 420 | - if (step == 1) | ||
| 421 | - tmp_precede = must_precede; | ||
| 422 | - else /* step == -1. */ | ||
| 423 | - tmp_follow = must_follow; | ||
| 424 | - } | ||
| 425 | - if (c == end - step) | ||
| 426 | - { | ||
| 427 | - if (step == 1) | ||
| 428 | - tmp_follow = must_follow; | ||
| 429 | - else /* step == -1. */ | ||
| 430 | - tmp_precede = must_precede; | ||
| 431 | - } | ||
| 432 | - | ||
| 433 | + sbitmap tmp_precede, tmp_follow; | ||
| 434 | + | ||
| 435 | + set_must_precede_follow (&tmp_follow, must_follow, | ||
| 436 | + &tmp_precede, must_precede, | ||
| 437 | + c, start, end, step); | ||
| 438 | success = | ||
| 439 | try_scheduling_node_in_cycle (ps, u_node, u, c, | ||
| 440 | sched_nodes, | ||
| 441 | @@ -2893,12 +3125,10 @@ | ||
| 442 | } | ||
| 443 | |||
| 444 | /* Calculate the stage count of the partial schedule PS. The calculation | ||
| 445 | - takes into account the rotation to bring the closing branch to row | ||
| 446 | - ii-1. */ | ||
| 447 | + takes into account the rotation amount passed in ROTATION_AMOUNT. */ | ||
| 448 | int | ||
| 449 | -calculate_stage_count (partial_schedule_ptr ps) | ||
| 450 | +calculate_stage_count (partial_schedule_ptr ps, int rotation_amount) | ||
| 451 | { | ||
| 452 | - int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1; | ||
| 453 | int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount; | ||
| 454 | int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount; | ||
| 455 | int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii); | ||
| 456 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99533.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99533.patch deleted file mode 100644 index 196da9d9d..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99533.patch +++ /dev/null | |||
| @@ -1,63 +0,0 @@ | |||
| 1 | 2011-08-09 Revital Eres <revital.eres@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | Backport from trunk -r176970: | ||
| 5 | |||
| 6 | * modulo-sched.c: Change comment. | ||
| 7 | (reset_sched_times): Fix print message. | ||
| 8 | (print_partial_schedule): Add print | ||
| 9 | info. | ||
| 10 | |||
| 11 | === modified file 'gcc/modulo-sched.c' | ||
| 12 | --- old/gcc/modulo-sched.c 2011-08-03 12:20:38 +0000 | ||
| 13 | +++ new/gcc/modulo-sched.c 2011-08-09 04:31:10 +0000 | ||
| 14 | @@ -84,13 +84,14 @@ | ||
| 15 | II cycles (i.e. use register copies to prevent a def from overwriting | ||
| 16 | itself before reaching the use). | ||
| 17 | |||
| 18 | - SMS works with countable loops whose loop count can be easily | ||
| 19 | - adjusted. This is because we peel a constant number of iterations | ||
| 20 | - into a prologue and epilogue for which we want to avoid emitting | ||
| 21 | - the control part, and a kernel which is to iterate that constant | ||
| 22 | - number of iterations less than the original loop. So the control | ||
| 23 | - part should be a set of insns clearly identified and having its | ||
| 24 | - own iv, not otherwise used in the loop (at-least for now), which | ||
| 25 | + SMS works with countable loops (1) whose control part can be easily | ||
| 26 | + decoupled from the rest of the loop and (2) whose loop count can | ||
| 27 | + be easily adjusted. This is because we peel a constant number of | ||
| 28 | + iterations into a prologue and epilogue for which we want to avoid | ||
| 29 | + emitting the control part, and a kernel which is to iterate that | ||
| 30 | + constant number of iterations less than the original loop. So the | ||
| 31 | + control part should be a set of insns clearly identified and having | ||
| 32 | + its own iv, not otherwise used in the loop (at-least for now), which | ||
| 33 | initializes a register before the loop to the number of iterations. | ||
| 34 | Currently SMS relies on the do-loop pattern to recognize such loops, | ||
| 35 | where (1) the control part comprises of all insns defining and/or | ||
| 36 | @@ -636,8 +637,8 @@ | ||
| 37 | /* Print the scheduling times after the rotation. */ | ||
| 38 | fprintf (dump_file, "crr_insn->node=%d (insn id %d), " | ||
| 39 | "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid, | ||
| 40 | - INSN_UID (crr_insn->node->insn), SCHED_TIME (u), | ||
| 41 | - normalized_time); | ||
| 42 | + INSN_UID (crr_insn->node->insn), normalized_time, | ||
| 43 | + new_min_cycle); | ||
| 44 | if (JUMP_P (crr_insn->node->insn)) | ||
| 45 | fprintf (dump_file, " (branch)"); | ||
| 46 | fprintf (dump_file, "\n"); | ||
| 47 | @@ -2782,8 +2783,13 @@ | ||
| 48 | fprintf (dump, "\n[ROW %d ]: ", i); | ||
| 49 | while (ps_i) | ||
| 50 | { | ||
| 51 | - fprintf (dump, "%d, ", | ||
| 52 | - INSN_UID (ps_i->node->insn)); | ||
| 53 | + if (JUMP_P (ps_i->node->insn)) | ||
| 54 | + fprintf (dump, "%d (branch), ", | ||
| 55 | + INSN_UID (ps_i->node->insn)); | ||
| 56 | + else | ||
| 57 | + fprintf (dump, "%d, ", | ||
| 58 | + INSN_UID (ps_i->node->insn)); | ||
| 59 | + | ||
| 60 | ps_i = ps_i->next_in_row; | ||
| 61 | } | ||
| 62 | } | ||
| 63 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99534.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99534.patch deleted file mode 100644 index 9fa6cf261..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99534.patch +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | 2011-08-09 Revital Eres <revital.eres@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | Backport from trunk -r176972: | ||
| 5 | |||
| 6 | * ddg.c (create_ddg_dep_from_intra_loop_link): Remove | ||
| 7 | the creation of anti-dep edge from a branch. | ||
| 8 | add_cross_iteration_register_deps): | ||
| 9 | Create anti-dep edge from a branch. | ||
| 10 | |||
| 11 | === modified file 'gcc/ddg.c' | ||
| 12 | --- old/gcc/ddg.c 2011-07-05 09:02:18 +0000 | ||
| 13 | +++ new/gcc/ddg.c 2011-07-31 13:13:38 +0000 | ||
| 14 | @@ -197,11 +197,6 @@ | ||
| 15 | } | ||
| 16 | } | ||
| 17 | |||
| 18 | - /* If a true dep edge enters the branch create an anti edge in the | ||
| 19 | - opposite direction to prevent the creation of reg-moves. */ | ||
| 20 | - if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn)) | ||
| 21 | - create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1); | ||
| 22 | - | ||
| 23 | latency = dep_cost (link); | ||
| 24 | e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance); | ||
| 25 | add_edge_to_ddg (g, e); | ||
| 26 | @@ -305,8 +300,11 @@ | ||
| 27 | |||
| 28 | gcc_assert (first_def_node); | ||
| 29 | |||
| 30 | + /* Always create the edge if the use node is a branch in | ||
| 31 | + order to prevent the creation of reg-moves. */ | ||
| 32 | if (DF_REF_ID (last_def) != DF_REF_ID (first_def) | ||
| 33 | - || !flag_modulo_sched_allow_regmoves) | ||
| 34 | + || !flag_modulo_sched_allow_regmoves | ||
| 35 | + || JUMP_P (use_node->insn)) | ||
| 36 | create_ddg_dep_no_link (g, use_node, first_def_node, ANTI_DEP, | ||
| 37 | REG_DEP, 1); | ||
| 38 | |||
| 39 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99536.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99536.patch deleted file mode 100644 index 76798ec1c..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99536.patch +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | 2011-08-15 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | * config/rs6000/rs6000.c (paired_expand_vector_init): Don't create | ||
| 5 | CONST_VECTORs with symbolic elements. | ||
| 6 | (rs6000_expand_vector_init): Likewise. | ||
| 7 | |||
| 8 | === modified file 'gcc/config/rs6000/rs6000.c' | ||
| 9 | --- old/gcc/config/rs6000/rs6000.c 2011-08-11 11:09:07 +0000 | ||
| 10 | +++ new/gcc/config/rs6000/rs6000.c 2011-08-16 12:42:39 +0000 | ||
| 11 | @@ -4129,7 +4129,9 @@ | ||
| 12 | for (i = 0; i < n_elts; ++i) | ||
| 13 | { | ||
| 14 | x = XVECEXP (vals, 0, i); | ||
| 15 | - if (!CONSTANT_P (x)) | ||
| 16 | + if (!(CONST_INT_P (x) | ||
| 17 | + || GET_CODE (x) == CONST_DOUBLE | ||
| 18 | + || GET_CODE (x) == CONST_FIXED)) | ||
| 19 | ++n_var; | ||
| 20 | } | ||
| 21 | if (n_var == 0) | ||
| 22 | @@ -4281,7 +4283,9 @@ | ||
| 23 | for (i = 0; i < n_elts; ++i) | ||
| 24 | { | ||
| 25 | x = XVECEXP (vals, 0, i); | ||
| 26 | - if (!CONSTANT_P (x)) | ||
| 27 | + if (!(CONST_INT_P (x) | ||
| 28 | + || GET_CODE (x) == CONST_DOUBLE | ||
| 29 | + || GET_CODE (x) == CONST_FIXED)) | ||
| 30 | ++n_var, one_var = i; | ||
| 31 | else if (x != CONST0_RTX (inner_mode)) | ||
| 32 | all_const_zero = false; | ||
| 33 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99537.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99537.patch deleted file mode 100644 index b8584334c..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99537.patch +++ /dev/null | |||
| @@ -1,105 +0,0 @@ | |||
| 1 | 2011-08-16 Matthias Klose <doko@ubuntu.com> | ||
| 2 | |||
| 3 | Backport from FSF: | ||
| 4 | |||
| 5 | 2010-12-20 Joseph Myers <joseph@codesourcery.com> | ||
| 6 | |||
| 7 | * config/rs6000/freebsd.h (SVR4_ASM_SPEC): Don't define. | ||
| 8 | (DBX_REGISTER_NUMBER): Define. | ||
| 9 | * config/rs6000/lynx.h (DBX_REGISTER_NUMBER): Define. | ||
| 10 | * config/rs6000/netbsd.h (DBX_REGISTER_NUMBER): Define. | ||
| 11 | * config/rs6000/sysv4.h (SIZE_TYPE): Define. | ||
| 12 | (ASM_SPEC): Define without using SVR4_ASM_SPEC. | ||
| 13 | (DBX_REGISTER_NUMBER): Undefine. | ||
| 14 | * config.gcc (powerpc-*-eabispe*, powerpc-*-eabisimaltivec*, | ||
| 15 | powerpc-*-eabisim*, powerpc-*-elf*, powerpc-*-eabialtivec*, | ||
| 16 | powerpc-xilinx-eabi*, powerpc-*-eabi*, powerpc-*-rtems*, | ||
| 17 | powerpc-*-linux* | powerpc64-*-linux*, powerpc64-*-gnu*, | ||
| 18 | powerpc-*-gnu-gnualtivec*, powerpc-*-gnu*, | ||
| 19 | powerpc-wrs-vxworks|powerpc-wrs-vxworksae, powerpcle-*-elf*, | ||
| 20 | powerpcle-*-eabisim*, powerpcle-*-eabi*): Don't use svr4.h. | ||
| 21 | |||
| 22 | === modified file 'gcc/config.gcc' | ||
| 23 | Index: gcc-4_5-branch/gcc/config.gcc | ||
| 24 | =================================================================== | ||
| 25 | --- gcc-4_5-branch.orig/gcc/config.gcc 2011-09-16 23:01:43.000000000 -0700 | ||
| 26 | +++ gcc-4_5-branch/gcc/config.gcc 2011-09-17 10:54:32.763299018 -0700 | ||
| 27 | @@ -2028,7 +2028,7 @@ powerpc-*-rtems*) | ||
| 28 | tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-rtems t-rtems rs6000/t-ppccomm" | ||
| 29 | ;; | ||
| 30 | powerpc-*-linux* | powerpc64-*-linux*) | ||
| 31 | - tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h" | ||
| 32 | + tm_file="${tm_file} dbxelf.h elfos.h linux.h freebsd-spec.h rs6000/sysv4.h" | ||
| 33 | extra_options="${extra_options} rs6000/sysv4.opt" | ||
| 34 | tmake_file="t-dfprules rs6000/t-fprules rs6000/t-ppcos ${tmake_file} rs6000/t-ppccomm" | ||
| 35 | maybe_biarch=yes | ||
| 36 | Index: gcc-4_5-branch/gcc/config/freebsd-spec.h | ||
| 37 | =================================================================== | ||
| 38 | --- gcc-4_5-branch.orig/gcc/config/freebsd-spec.h 2011-06-16 17:59:03.000000000 -0700 | ||
| 39 | +++ gcc-4_5-branch/gcc/config/freebsd-spec.h 2011-09-17 10:54:32.763299018 -0700 | ||
| 40 | @@ -154,6 +154,7 @@ is built with the --enable-threads confi | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #if defined(HAVE_LD_EH_FRAME_HDR) | ||
| 44 | +#undef LINK_EH_SPEC | ||
| 45 | #define LINK_EH_SPEC "%{!static:--eh-frame-hdr} " | ||
| 46 | #endif | ||
| 47 | |||
| 48 | Index: gcc-4_5-branch/gcc/config/rs6000/linux64.h | ||
| 49 | =================================================================== | ||
| 50 | --- gcc-4_5-branch.orig/gcc/config/rs6000/linux64.h 2011-09-16 23:01:43.000000000 -0700 | ||
| 51 | +++ gcc-4_5-branch/gcc/config/rs6000/linux64.h 2011-09-17 10:56:01.043298999 -0700 | ||
| 52 | @@ -339,6 +339,9 @@ extern int dot_symbols; | ||
| 53 | |||
| 54 | #undef LINK_OS_DEFAULT_SPEC | ||
| 55 | #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)" | ||
| 56 | +#undef LINUX_DYNAMIC_LINKER32 | ||
| 57 | +#undef LINUX_DYNAMIC_LINKER64 | ||
| 58 | +#undef CHOOSE_DYNAMIC_LINKER | ||
| 59 | |||
| 60 | #define GLIBC_DYNAMIC_LINKER32 SYSTEMLIBS_DIR "ld.so.1" | ||
| 61 | #define GLIBC_DYNAMIC_LINKER64 SYSTEMLIBS_DIR "ld64.so.1" | ||
| 62 | Index: gcc-4_5-branch/gcc/config/rs6000/sysv4.h | ||
| 63 | =================================================================== | ||
| 64 | --- gcc-4_5-branch.orig/gcc/config/rs6000/sysv4.h 2011-09-16 23:01:44.000000000 -0700 | ||
| 65 | +++ gcc-4_5-branch/gcc/config/rs6000/sysv4.h 2011-09-17 10:54:32.773299018 -0700 | ||
| 66 | @@ -617,6 +617,7 @@ SVR4_ASM_SPEC \ | ||
| 67 | #define CC1_SECURE_PLT_DEFAULT_SPEC "" | ||
| 68 | #endif | ||
| 69 | |||
| 70 | +#undef CC1_SPEC | ||
| 71 | /* Pass -G xxx to the compiler and set correct endian mode. */ | ||
| 72 | #define CC1_SPEC "%{G*} %(cc1_cpu) \ | ||
| 73 | %{mlittle|mlittle-endian: %(cc1_endian_little); \ | ||
| 74 | @@ -900,22 +901,13 @@ SVR4_ASM_SPEC \ | ||
| 75 | #define LINK_START_LINUX_SPEC "" | ||
| 76 | |||
| 77 | #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" | ||
| 78 | -#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" | ||
| 79 | -#if DEFAULT_LIBC == LIBC_UCLIBC | ||
| 80 | -#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" | ||
| 81 | -#elif DEFAULT_LIBC == LIBC_GLIBC | ||
| 82 | -#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}" | ||
| 83 | -#else | ||
| 84 | -#error "Unsupported DEFAULT_LIBC" | ||
| 85 | -#endif | ||
| 86 | -#define LINUX_DYNAMIC_LINKER \ | ||
| 87 | - CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER) | ||
| 88 | |||
| 89 | #define LINK_OS_LINUX_SPEC "-m elf32ppclinux %{!shared: %{!static: \ | ||
| 90 | %{rdynamic:-export-dynamic} \ | ||
| 91 | %{!dynamic-linker:-dynamic-linker " LINUX_DYNAMIC_LINKER "}}}" | ||
| 92 | |||
| 93 | #if defined(HAVE_LD_EH_FRAME_HDR) | ||
| 94 | +# undef LINK_EH_SPEC | ||
| 95 | # define LINK_EH_SPEC "%{!static:--eh-frame-hdr} " | ||
| 96 | #endif | ||
| 97 | |||
| 98 | @@ -1110,6 +1102,7 @@ ncrtn.o%s" | ||
| 99 | be stacked, so that invocations of #pragma pack(pop)' will return | ||
| 100 | to the previous value. */ | ||
| 101 | |||
| 102 | +#undef HANDLE_PRAGMA_PACK_PUSH_POP | ||
| 103 | #define HANDLE_PRAGMA_PACK_PUSH_POP 1 | ||
| 104 | |||
| 105 | /* Select a format to encode pointers in exception handling data. CODE | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99540.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99540.patch deleted file mode 100644 index b71f6cc5b..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99540.patch +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | 2011-08-26 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | Backport from mainline: | ||
| 5 | |||
| 6 | 2011-08-26 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 7 | |||
| 8 | * df-problems.c (df_note_bb_compute): Pass uses rather than defs | ||
| 9 | to df_set_dead_notes_for_mw. | ||
| 10 | |||
| 11 | === modified file 'gcc/df-problems.c' | ||
| 12 | --- old/gcc/df-problems.c 2011-05-05 14:28:53 +0000 | ||
| 13 | +++ new/gcc/df-problems.c 2011-08-26 14:39:38 +0000 | ||
| 14 | @@ -3562,7 +3562,7 @@ | ||
| 15 | while (*mws_rec) | ||
| 16 | { | ||
| 17 | struct df_mw_hardreg *mws = *mws_rec; | ||
| 18 | - if ((DF_MWS_REG_DEF_P (mws)) | ||
| 19 | + if (DF_MWS_REG_USE_P (mws) | ||
| 20 | && !df_ignore_stack_reg (mws->start_regno)) | ||
| 21 | { | ||
| 22 | bool really_add_notes = debug_insn != 0; | ||
| 23 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99548.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99548.patch deleted file mode 100644 index b78319e8f..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99548.patch +++ /dev/null | |||
| @@ -1,80 +0,0 @@ | |||
| 1 | 2011-09-22 Revital Eres <revital.eres@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | Backport from trunk -r178804: | ||
| 5 | modulo-sched.c (remove_node_from_ps): Return void | ||
| 6 | instead of bool. | ||
| 7 | (optimize_sc): Adjust call to remove_node_from_ps. | ||
| 8 | (sms_schedule): Add print info. | ||
| 9 | |||
| 10 | === modified file 'gcc/modulo-sched.c' | ||
| 11 | --- old/gcc/modulo-sched.c 2011-08-09 04:31:10 +0000 | ||
| 12 | +++ new/gcc/modulo-sched.c 2011-09-22 13:58:43 +0000 | ||
| 13 | @@ -211,7 +211,7 @@ | ||
| 14 | static bool try_scheduling_node_in_cycle (partial_schedule_ptr, ddg_node_ptr, | ||
| 15 | int, int, sbitmap, int *, sbitmap, | ||
| 16 | sbitmap); | ||
| 17 | -static bool remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr); | ||
| 18 | +static void remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr); | ||
| 19 | |||
| 20 | #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap) | ||
| 21 | #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time) | ||
| 22 | @@ -834,8 +834,7 @@ | ||
| 23 | if (next_ps_i->node->cuid == g->closing_branch->cuid) | ||
| 24 | break; | ||
| 25 | |||
| 26 | - gcc_assert (next_ps_i); | ||
| 27 | - gcc_assert (remove_node_from_ps (ps, next_ps_i)); | ||
| 28 | + remove_node_from_ps (ps, next_ps_i); | ||
| 29 | success = | ||
| 30 | try_scheduling_node_in_cycle (ps, g->closing_branch, | ||
| 31 | g->closing_branch->cuid, c, | ||
| 32 | @@ -1485,8 +1484,8 @@ | ||
| 33 | if (dump_file) | ||
| 34 | { | ||
| 35 | fprintf (dump_file, | ||
| 36 | - "SMS succeeded %d %d (with ii, sc)\n", ps->ii, | ||
| 37 | - stage_count); | ||
| 38 | + "%s:%d SMS succeeded %d %d (with ii, sc)\n", | ||
| 39 | + insn_file (tail), insn_line (tail), ps->ii, stage_count); | ||
| 40 | print_partial_schedule (ps, dump_file); | ||
| 41 | } | ||
| 42 | |||
| 43 | @@ -2810,22 +2809,18 @@ | ||
| 44 | } | ||
| 45 | |||
| 46 | |||
| 47 | -/* Removes the given PS_INSN from the partial schedule. Returns false if the | ||
| 48 | - node is not found in the partial schedule, else returns true. */ | ||
| 49 | -static bool | ||
| 50 | +/* Removes the given PS_INSN from the partial schedule. */ | ||
| 51 | +static void | ||
| 52 | remove_node_from_ps (partial_schedule_ptr ps, ps_insn_ptr ps_i) | ||
| 53 | { | ||
| 54 | int row; | ||
| 55 | |||
| 56 | - if (!ps || !ps_i) | ||
| 57 | - return false; | ||
| 58 | - | ||
| 59 | + gcc_assert (ps && ps_i); | ||
| 60 | + | ||
| 61 | row = SMODULO (ps_i->cycle, ps->ii); | ||
| 62 | if (! ps_i->prev_in_row) | ||
| 63 | { | ||
| 64 | - if (ps_i != ps->rows[row]) | ||
| 65 | - return false; | ||
| 66 | - | ||
| 67 | + gcc_assert (ps_i == ps->rows[row]); | ||
| 68 | ps->rows[row] = ps_i->next_in_row; | ||
| 69 | if (ps->rows[row]) | ||
| 70 | ps->rows[row]->prev_in_row = NULL; | ||
| 71 | @@ -2839,7 +2834,7 @@ | ||
| 72 | |||
| 73 | ps->rows_length[row] -= 1; | ||
| 74 | free (ps_i); | ||
| 75 | - return true; | ||
| 76 | + return; | ||
| 77 | } | ||
| 78 | |||
| 79 | /* Unlike what literature describes for modulo scheduling (which focuses | ||
| 80 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch deleted file mode 100644 index 43617024a..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch +++ /dev/null | |||
| @@ -1,460 +0,0 @@ | |||
| 1 | 2011-10-03 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 2 | |||
| 3 | gcc/ | ||
| 4 | Backport from mainline: | ||
| 5 | |||
| 6 | 2010-12-06 Jakub Jelinek <jakub@redhat.com> | ||
| 7 | |||
| 8 | PR debug/46771 | ||
| 9 | * reginfo.c (init_subregs_of_mode): Don't call find_subregs_of_mode | ||
| 10 | on DEBUG_INSNs. | ||
| 11 | |||
| 12 | 2011-10-03 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 13 | |||
| 14 | gcc/ | ||
| 15 | Backport from mainline: | ||
| 16 | |||
| 17 | 2011-09-22 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 18 | |||
| 19 | * config/arm/predicates.md (expandable_comparison_operator): New | ||
| 20 | predicate, extracted from... | ||
| 21 | (arm_comparison_operator): ...here. | ||
| 22 | * config/arm/arm.md (cbranchsi4, cbranchsf4, cbranchdf4, cbranchdi4) | ||
| 23 | (cstoresi4, cstoresf4, cstoredf4, cstoredi4, movsicc, movsfcc) | ||
| 24 | (movdfcc): Use expandable_comparison_operator. | ||
| 25 | |||
| 26 | gcc/testsuite/ | ||
| 27 | Backport from mainline: | ||
| 28 | |||
| 29 | 2011-09-22 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 30 | |||
| 31 | * gcc.target/arm/cmp-1.c: New test. | ||
| 32 | * gcc.target/arm/cmp-2.c: Likewise. | ||
| 33 | |||
| 34 | 2011-10-03 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 35 | |||
| 36 | gcc/ | ||
| 37 | Backport from mainline: | ||
| 38 | |||
| 39 | 2011-09-07 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 40 | |||
| 41 | PR target/49030 | ||
| 42 | * config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare. | ||
| 43 | * config/arm/arm.c (maybe_get_arm_condition_code): New function, | ||
| 44 | reusing the old code from get_arm_condition_code. Return ARM_NV | ||
| 45 | for invalid comparison codes. | ||
| 46 | (get_arm_condition_code): Redefine in terms of | ||
| 47 | maybe_get_arm_condition_code. | ||
| 48 | * config/arm/predicates.md (arm_comparison_operator): Use | ||
| 49 | maybe_get_arm_condition_code. | ||
| 50 | |||
| 51 | gcc/testsuite/ | ||
| 52 | Backport from mainline: | ||
| 53 | |||
| 54 | 2011-09-07 Richard Sandiford <richard.sandiford@linaro.org> | ||
| 55 | |||
| 56 | PR target/49030 | ||
| 57 | * gcc.dg/torture/pr49030.c: New test. | ||
| 58 | |||
| 59 | === modified file 'gcc/config/arm/arm-protos.h' | ||
| 60 | --- old/gcc/config/arm/arm-protos.h 2011-09-15 10:06:35 +0000 | ||
| 61 | +++ new/gcc/config/arm/arm-protos.h 2011-10-03 10:09:06 +0000 | ||
| 62 | @@ -182,6 +182,7 @@ | ||
| 63 | #endif | ||
| 64 | extern int thumb_shiftable_const (unsigned HOST_WIDE_INT); | ||
| 65 | #ifdef RTX_CODE | ||
| 66 | +extern enum arm_cond_code maybe_get_arm_condition_code (rtx); | ||
| 67 | extern void thumb1_final_prescan_insn (rtx); | ||
| 68 | extern void thumb2_final_prescan_insn (rtx); | ||
| 69 | extern const char *thumb_load_double_from_address (rtx *); | ||
| 70 | |||
| 71 | === modified file 'gcc/config/arm/arm.c' | ||
| 72 | --- old/gcc/config/arm/arm.c 2011-09-15 10:06:35 +0000 | ||
| 73 | +++ new/gcc/config/arm/arm.c 2011-10-03 10:09:06 +0000 | ||
| 74 | @@ -17196,10 +17196,10 @@ | ||
| 75 | decremented/zeroed by arm_asm_output_opcode as the insns are output. */ | ||
| 76 | |||
| 77 | /* Returns the index of the ARM condition code string in | ||
| 78 | - `arm_condition_codes'. COMPARISON should be an rtx like | ||
| 79 | - `(eq (...) (...))'. */ | ||
| 80 | -static enum arm_cond_code | ||
| 81 | -get_arm_condition_code (rtx comparison) | ||
| 82 | + `arm_condition_codes', or ARM_NV if the comparison is invalid. | ||
| 83 | + COMPARISON should be an rtx like `(eq (...) (...))'. */ | ||
| 84 | +enum arm_cond_code | ||
| 85 | +maybe_get_arm_condition_code (rtx comparison) | ||
| 86 | { | ||
| 87 | enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); | ||
| 88 | enum arm_cond_code code; | ||
| 89 | @@ -17223,11 +17223,11 @@ | ||
| 90 | case CC_DLTUmode: code = ARM_CC; | ||
| 91 | |||
| 92 | dominance: | ||
| 93 | - gcc_assert (comp_code == EQ || comp_code == NE); | ||
| 94 | - | ||
| 95 | if (comp_code == EQ) | ||
| 96 | return ARM_INVERSE_CONDITION_CODE (code); | ||
| 97 | - return code; | ||
| 98 | + if (comp_code == NE) | ||
| 99 | + return code; | ||
| 100 | + return ARM_NV; | ||
| 101 | |||
| 102 | case CC_NOOVmode: | ||
| 103 | switch (comp_code) | ||
| 104 | @@ -17236,7 +17236,7 @@ | ||
| 105 | case EQ: return ARM_EQ; | ||
| 106 | case GE: return ARM_PL; | ||
| 107 | case LT: return ARM_MI; | ||
| 108 | - default: gcc_unreachable (); | ||
| 109 | + default: return ARM_NV; | ||
| 110 | } | ||
| 111 | |||
| 112 | case CC_Zmode: | ||
| 113 | @@ -17244,7 +17244,7 @@ | ||
| 114 | { | ||
| 115 | case NE: return ARM_NE; | ||
| 116 | case EQ: return ARM_EQ; | ||
| 117 | - default: gcc_unreachable (); | ||
| 118 | + default: return ARM_NV; | ||
| 119 | } | ||
| 120 | |||
| 121 | case CC_Nmode: | ||
| 122 | @@ -17252,7 +17252,7 @@ | ||
| 123 | { | ||
| 124 | case NE: return ARM_MI; | ||
| 125 | case EQ: return ARM_PL; | ||
| 126 | - default: gcc_unreachable (); | ||
| 127 | + default: return ARM_NV; | ||
| 128 | } | ||
| 129 | |||
| 130 | case CCFPEmode: | ||
| 131 | @@ -17277,7 +17277,7 @@ | ||
| 132 | /* UNEQ and LTGT do not have a representation. */ | ||
| 133 | case UNEQ: /* Fall through. */ | ||
| 134 | case LTGT: /* Fall through. */ | ||
| 135 | - default: gcc_unreachable (); | ||
| 136 | + default: return ARM_NV; | ||
| 137 | } | ||
| 138 | |||
| 139 | case CC_SWPmode: | ||
| 140 | @@ -17293,7 +17293,7 @@ | ||
| 141 | case GTU: return ARM_CC; | ||
| 142 | case LEU: return ARM_CS; | ||
| 143 | case LTU: return ARM_HI; | ||
| 144 | - default: gcc_unreachable (); | ||
| 145 | + default: return ARM_NV; | ||
| 146 | } | ||
| 147 | |||
| 148 | case CC_Cmode: | ||
| 149 | @@ -17301,7 +17301,7 @@ | ||
| 150 | { | ||
| 151 | case LTU: return ARM_CS; | ||
| 152 | case GEU: return ARM_CC; | ||
| 153 | - default: gcc_unreachable (); | ||
| 154 | + default: return ARM_NV; | ||
| 155 | } | ||
| 156 | |||
| 157 | case CC_CZmode: | ||
| 158 | @@ -17313,7 +17313,7 @@ | ||
| 159 | case GTU: return ARM_HI; | ||
| 160 | case LEU: return ARM_LS; | ||
| 161 | case LTU: return ARM_CC; | ||
| 162 | - default: gcc_unreachable (); | ||
| 163 | + default: return ARM_NV; | ||
| 164 | } | ||
| 165 | |||
| 166 | case CC_NCVmode: | ||
| 167 | @@ -17323,7 +17323,7 @@ | ||
| 168 | case LT: return ARM_LT; | ||
| 169 | case GEU: return ARM_CS; | ||
| 170 | case LTU: return ARM_CC; | ||
| 171 | - default: gcc_unreachable (); | ||
| 172 | + default: return ARM_NV; | ||
| 173 | } | ||
| 174 | |||
| 175 | case CCmode: | ||
| 176 | @@ -17339,13 +17339,22 @@ | ||
| 177 | case GTU: return ARM_HI; | ||
| 178 | case LEU: return ARM_LS; | ||
| 179 | case LTU: return ARM_CC; | ||
| 180 | - default: gcc_unreachable (); | ||
| 181 | + default: return ARM_NV; | ||
| 182 | } | ||
| 183 | |||
| 184 | default: gcc_unreachable (); | ||
| 185 | } | ||
| 186 | } | ||
| 187 | |||
| 188 | +/* Like maybe_get_arm_condition_code, but never return ARM_NV. */ | ||
| 189 | +static enum arm_cond_code | ||
| 190 | +get_arm_condition_code (rtx comparison) | ||
| 191 | +{ | ||
| 192 | + enum arm_cond_code code = maybe_get_arm_condition_code (comparison); | ||
| 193 | + gcc_assert (code != ARM_NV); | ||
| 194 | + return code; | ||
| 195 | +} | ||
| 196 | + | ||
| 197 | /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed | ||
| 198 | instructions. */ | ||
| 199 | void | ||
| 200 | |||
| 201 | === modified file 'gcc/config/arm/arm.md' | ||
| 202 | --- old/gcc/config/arm/arm.md 2011-07-12 16:35:20 +0000 | ||
| 203 | +++ new/gcc/config/arm/arm.md 2011-10-03 10:09:55 +0000 | ||
| 204 | @@ -6428,7 +6428,7 @@ | ||
| 205 | |||
| 206 | (define_expand "cbranchsi4" | ||
| 207 | [(set (pc) (if_then_else | ||
| 208 | - (match_operator 0 "arm_comparison_operator" | ||
| 209 | + (match_operator 0 "expandable_comparison_operator" | ||
| 210 | [(match_operand:SI 1 "s_register_operand" "") | ||
| 211 | (match_operand:SI 2 "nonmemory_operand" "")]) | ||
| 212 | (label_ref (match_operand 3 "" "")) | ||
| 213 | @@ -6479,7 +6479,7 @@ | ||
| 214 | |||
| 215 | (define_expand "cbranchsf4" | ||
| 216 | [(set (pc) (if_then_else | ||
| 217 | - (match_operator 0 "arm_comparison_operator" | ||
| 218 | + (match_operator 0 "expandable_comparison_operator" | ||
| 219 | [(match_operand:SF 1 "s_register_operand" "") | ||
| 220 | (match_operand:SF 2 "arm_float_compare_operand" "")]) | ||
| 221 | (label_ref (match_operand 3 "" "")) | ||
| 222 | @@ -6491,7 +6491,7 @@ | ||
| 223 | |||
| 224 | (define_expand "cbranchdf4" | ||
| 225 | [(set (pc) (if_then_else | ||
| 226 | - (match_operator 0 "arm_comparison_operator" | ||
| 227 | + (match_operator 0 "expandable_comparison_operator" | ||
| 228 | [(match_operand:DF 1 "s_register_operand" "") | ||
| 229 | (match_operand:DF 2 "arm_float_compare_operand" "")]) | ||
| 230 | (label_ref (match_operand 3 "" "")) | ||
| 231 | @@ -6503,7 +6503,7 @@ | ||
| 232 | |||
| 233 | (define_expand "cbranchdi4" | ||
| 234 | [(set (pc) (if_then_else | ||
| 235 | - (match_operator 0 "arm_comparison_operator" | ||
| 236 | + (match_operator 0 "expandable_comparison_operator" | ||
| 237 | [(match_operand:DI 1 "cmpdi_operand" "") | ||
| 238 | (match_operand:DI 2 "cmpdi_operand" "")]) | ||
| 239 | (label_ref (match_operand 3 "" "")) | ||
| 240 | @@ -7898,7 +7898,7 @@ | ||
| 241 | |||
| 242 | (define_expand "cstoresi4" | ||
| 243 | [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 244 | - (match_operator:SI 1 "arm_comparison_operator" | ||
| 245 | + (match_operator:SI 1 "expandable_comparison_operator" | ||
| 246 | [(match_operand:SI 2 "s_register_operand" "") | ||
| 247 | (match_operand:SI 3 "reg_or_int_operand" "")]))] | ||
| 248 | "TARGET_32BIT || TARGET_THUMB1" | ||
| 249 | @@ -8034,7 +8034,7 @@ | ||
| 250 | |||
| 251 | (define_expand "cstoresf4" | ||
| 252 | [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 253 | - (match_operator:SI 1 "arm_comparison_operator" | ||
| 254 | + (match_operator:SI 1 "expandable_comparison_operator" | ||
| 255 | [(match_operand:SF 2 "s_register_operand" "") | ||
| 256 | (match_operand:SF 3 "arm_float_compare_operand" "")]))] | ||
| 257 | "TARGET_32BIT && TARGET_HARD_FLOAT" | ||
| 258 | @@ -8044,7 +8044,7 @@ | ||
| 259 | |||
| 260 | (define_expand "cstoredf4" | ||
| 261 | [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 262 | - (match_operator:SI 1 "arm_comparison_operator" | ||
| 263 | + (match_operator:SI 1 "expandable_comparison_operator" | ||
| 264 | [(match_operand:DF 2 "s_register_operand" "") | ||
| 265 | (match_operand:DF 3 "arm_float_compare_operand" "")]))] | ||
| 266 | "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" | ||
| 267 | @@ -8054,7 +8054,7 @@ | ||
| 268 | |||
| 269 | (define_expand "cstoredi4" | ||
| 270 | [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 271 | - (match_operator:SI 1 "arm_comparison_operator" | ||
| 272 | + (match_operator:SI 1 "expandable_comparison_operator" | ||
| 273 | [(match_operand:DI 2 "cmpdi_operand" "") | ||
| 274 | (match_operand:DI 3 "cmpdi_operand" "")]))] | ||
| 275 | "TARGET_32BIT" | ||
| 276 | @@ -8174,7 +8174,7 @@ | ||
| 277 | |||
| 278 | (define_expand "movsicc" | ||
| 279 | [(set (match_operand:SI 0 "s_register_operand" "") | ||
| 280 | - (if_then_else:SI (match_operand 1 "arm_comparison_operator" "") | ||
| 281 | + (if_then_else:SI (match_operand 1 "expandable_comparison_operator" "") | ||
| 282 | (match_operand:SI 2 "arm_not_operand" "") | ||
| 283 | (match_operand:SI 3 "arm_not_operand" "")))] | ||
| 284 | "TARGET_32BIT" | ||
| 285 | @@ -8194,7 +8194,7 @@ | ||
| 286 | |||
| 287 | (define_expand "movsfcc" | ||
| 288 | [(set (match_operand:SF 0 "s_register_operand" "") | ||
| 289 | - (if_then_else:SF (match_operand 1 "arm_comparison_operator" "") | ||
| 290 | + (if_then_else:SF (match_operand 1 "expandable_comparison_operator" "") | ||
| 291 | (match_operand:SF 2 "s_register_operand" "") | ||
| 292 | (match_operand:SF 3 "nonmemory_operand" "")))] | ||
| 293 | "TARGET_32BIT && TARGET_HARD_FLOAT" | ||
| 294 | @@ -8220,7 +8220,7 @@ | ||
| 295 | |||
| 296 | (define_expand "movdfcc" | ||
| 297 | [(set (match_operand:DF 0 "s_register_operand" "") | ||
| 298 | - (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") | ||
| 299 | + (if_then_else:DF (match_operand 1 "expandable_comparison_operator" "") | ||
| 300 | (match_operand:DF 2 "s_register_operand" "") | ||
| 301 | (match_operand:DF 3 "arm_float_add_operand" "")))] | ||
| 302 | "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)" | ||
| 303 | |||
| 304 | === modified file 'gcc/config/arm/predicates.md' | ||
| 305 | --- old/gcc/config/arm/predicates.md 2011-09-15 10:06:35 +0000 | ||
| 306 | +++ new/gcc/config/arm/predicates.md 2011-10-03 10:09:55 +0000 | ||
| 307 | @@ -236,11 +236,15 @@ | ||
| 308 | |||
| 309 | ;; True for integer comparisons and, if FP is active, for comparisons | ||
| 310 | ;; other than LTGT or UNEQ. | ||
| 311 | +(define_special_predicate "expandable_comparison_operator" | ||
| 312 | + (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu, | ||
| 313 | + unordered,ordered,unlt,unle,unge,ungt")) | ||
| 314 | + | ||
| 315 | +;; Likewise, but only accept comparisons that are directly supported | ||
| 316 | +;; by ARM condition codes. | ||
| 317 | (define_special_predicate "arm_comparison_operator" | ||
| 318 | - (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu") | ||
| 319 | - (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT | ||
| 320 | - && (TARGET_FPA || TARGET_VFP)") | ||
| 321 | - (match_code "unordered,ordered,unlt,unle,unge,ungt")))) | ||
| 322 | + (and (match_operand 0 "expandable_comparison_operator") | ||
| 323 | + (match_test "maybe_get_arm_condition_code (op) != ARM_NV"))) | ||
| 324 | |||
| 325 | (define_special_predicate "lt_ge_comparison_operator" | ||
| 326 | (match_code "lt,ge")) | ||
| 327 | |||
| 328 | === modified file 'gcc/reginfo.c' | ||
| 329 | --- old/gcc/reginfo.c 2011-09-15 10:06:35 +0000 | ||
| 330 | +++ new/gcc/reginfo.c 2011-10-03 10:10:17 +0000 | ||
| 331 | @@ -1350,7 +1350,7 @@ | ||
| 332 | |||
| 333 | FOR_EACH_BB (bb) | ||
| 334 | FOR_BB_INSNS (bb, insn) | ||
| 335 | - if (INSN_P (insn)) | ||
| 336 | + if (NONDEBUG_INSN_P (insn)) | ||
| 337 | find_subregs_of_mode (PATTERN (insn)); | ||
| 338 | } | ||
| 339 | |||
| 340 | |||
| 341 | === added file 'gcc/testsuite/gcc.dg/torture/pr49030.c' | ||
| 342 | --- old/gcc/testsuite/gcc.dg/torture/pr49030.c 1970-01-01 00:00:00 +0000 | ||
| 343 | +++ new/gcc/testsuite/gcc.dg/torture/pr49030.c 2011-10-03 10:09:06 +0000 | ||
| 344 | @@ -0,0 +1,19 @@ | ||
| 345 | +void | ||
| 346 | +sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples, | ||
| 347 | + unsigned long dst_skip) | ||
| 348 | +{ | ||
| 349 | + long long y; | ||
| 350 | + while (nsamples--) | ||
| 351 | + { | ||
| 352 | + y = (long long) (*src * 8388608.0f) << 8; | ||
| 353 | + if (y > 2147483647) { | ||
| 354 | + *(int *) dst = 2147483647; | ||
| 355 | + } else if (y < -2147483647 - 1) { | ||
| 356 | + *(int *) dst = -2147483647 - 1; | ||
| 357 | + } else { | ||
| 358 | + *(int *) dst = (int) y; | ||
| 359 | + } | ||
| 360 | + dst += dst_skip; | ||
| 361 | + src++; | ||
| 362 | + } | ||
| 363 | +} | ||
| 364 | |||
| 365 | === added file 'gcc/testsuite/gcc.target/arm/cmp-1.c' | ||
| 366 | --- old/gcc/testsuite/gcc.target/arm/cmp-1.c 1970-01-01 00:00:00 +0000 | ||
| 367 | +++ new/gcc/testsuite/gcc.target/arm/cmp-1.c 2011-10-03 10:09:55 +0000 | ||
| 368 | @@ -0,0 +1,37 @@ | ||
| 369 | +/* { dg-do compile } */ | ||
| 370 | +/* { dg-options "-O" } */ | ||
| 371 | +/* { dg-final { scan-assembler-not "\tbl\t" } } */ | ||
| 372 | +/* { dg-final { scan-assembler-not "__aeabi" } } */ | ||
| 373 | +int x, y; | ||
| 374 | + | ||
| 375 | +#define TEST_EXPR(NAME, ARGS, EXPR) \ | ||
| 376 | + int NAME##1 ARGS { return (EXPR); } \ | ||
| 377 | + int NAME##2 ARGS { return !(EXPR); } \ | ||
| 378 | + int NAME##3 ARGS { return (EXPR) ? x : y; } \ | ||
| 379 | + void NAME##4 ARGS { if (EXPR) x++; } \ | ||
| 380 | + void NAME##5 ARGS { if (!(EXPR)) x++; } | ||
| 381 | + | ||
| 382 | +#define TEST(NAME, TYPE, OPERATOR) \ | ||
| 383 | + TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), a1 OPERATOR a2) \ | ||
| 384 | + TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), a1 OPERATOR *a2) \ | ||
| 385 | + TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), *a1 OPERATOR a2) \ | ||
| 386 | + TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), *a1 OPERATOR *a2) \ | ||
| 387 | + TEST_EXPR (NAME##_rc, (TYPE a1), a1 OPERATOR 100) \ | ||
| 388 | + TEST_EXPR (NAME##_cr, (TYPE a1), 100 OPERATOR a1) | ||
| 389 | + | ||
| 390 | +#define TEST_OP(NAME, OPERATOR) \ | ||
| 391 | + TEST (sc_##NAME, signed char, OPERATOR) \ | ||
| 392 | + TEST (uc_##NAME, unsigned char, OPERATOR) \ | ||
| 393 | + TEST (ss_##NAME, short, OPERATOR) \ | ||
| 394 | + TEST (us_##NAME, unsigned short, OPERATOR) \ | ||
| 395 | + TEST (si_##NAME, int, OPERATOR) \ | ||
| 396 | + TEST (ui_##NAME, unsigned int, OPERATOR) \ | ||
| 397 | + TEST (sll_##NAME, long long, OPERATOR) \ | ||
| 398 | + TEST (ull_##NAME, unsigned long long, OPERATOR) | ||
| 399 | + | ||
| 400 | +TEST_OP (eq, ==) | ||
| 401 | +TEST_OP (ne, !=) | ||
| 402 | +TEST_OP (lt, <) | ||
| 403 | +TEST_OP (gt, >) | ||
| 404 | +TEST_OP (le, <=) | ||
| 405 | +TEST_OP (ge, >=) | ||
| 406 | |||
| 407 | === added file 'gcc/testsuite/gcc.target/arm/cmp-2.c' | ||
| 408 | --- old/gcc/testsuite/gcc.target/arm/cmp-2.c 1970-01-01 00:00:00 +0000 | ||
| 409 | +++ new/gcc/testsuite/gcc.target/arm/cmp-2.c 2011-10-03 10:09:55 +0000 | ||
| 410 | @@ -0,0 +1,49 @@ | ||
| 411 | +/* { dg-do compile } */ | ||
| 412 | +/* { dg-require-effective-target arm_vfp_ok } */ | ||
| 413 | +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ | ||
| 414 | +/* { dg-options "-O -mfpu=vfp -mfloat-abi=softfp" } */ | ||
| 415 | +/* { dg-final { scan-assembler-not "\tbl\t" } } */ | ||
| 416 | +/* { dg-final { scan-assembler-not "__aeabi" } } */ | ||
| 417 | +int x, y; | ||
| 418 | + | ||
| 419 | +#define EQ(X, Y) ((X) == (Y)) | ||
| 420 | +#define NE(X, Y) ((X) != (Y)) | ||
| 421 | +#define LT(X, Y) ((X) < (Y)) | ||
| 422 | +#define GT(X, Y) ((X) > (Y)) | ||
| 423 | +#define LE(X, Y) ((X) <= (Y)) | ||
| 424 | +#define GE(X, Y) ((X) >= (Y)) | ||
| 425 | + | ||
| 426 | +#define TEST_EXPR(NAME, ARGS, EXPR) \ | ||
| 427 | + int NAME##1 ARGS { return (EXPR); } \ | ||
| 428 | + int NAME##2 ARGS { return !(EXPR); } \ | ||
| 429 | + int NAME##3 ARGS { return (EXPR) ? x : y; } \ | ||
| 430 | + void NAME##4 ARGS { if (EXPR) x++; } \ | ||
| 431 | + void NAME##5 ARGS { if (!(EXPR)) x++; } | ||
| 432 | + | ||
| 433 | +#define TEST(NAME, TYPE, OPERATOR) \ | ||
| 434 | + TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), OPERATOR (a1, a2)) \ | ||
| 435 | + TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), OPERATOR (a1, *a2)) \ | ||
| 436 | + TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), OPERATOR (*a1, a2)) \ | ||
| 437 | + TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), OPERATOR (*a1, *a2)) \ | ||
| 438 | + TEST_EXPR (NAME##_rc, (TYPE a1), OPERATOR (a1, 100)) \ | ||
| 439 | + TEST_EXPR (NAME##_cr, (TYPE a1), OPERATOR (100, a1)) | ||
| 440 | + | ||
| 441 | +#define TEST_OP(NAME, OPERATOR) \ | ||
| 442 | + TEST (f_##NAME, float, OPERATOR) \ | ||
| 443 | + TEST (d_##NAME, double, OPERATOR) \ | ||
| 444 | + TEST (ld_##NAME, long double, OPERATOR) | ||
| 445 | + | ||
| 446 | +TEST_OP (eq, EQ) | ||
| 447 | +TEST_OP (ne, NE) | ||
| 448 | +TEST_OP (lt, LT) | ||
| 449 | +TEST_OP (gt, GT) | ||
| 450 | +TEST_OP (le, LE) | ||
| 451 | +TEST_OP (ge, GE) | ||
| 452 | +TEST_OP (blt, __builtin_isless) | ||
| 453 | +TEST_OP (bgt, __builtin_isgreater) | ||
| 454 | +TEST_OP (ble, __builtin_islessequal) | ||
| 455 | +TEST_OP (bge, __builtin_isgreaterequal) | ||
| 456 | +/* This one should be expanded into separate ordered and equality | ||
| 457 | + comparisons. */ | ||
| 458 | +TEST_OP (blg, __builtin_islessgreater) | ||
| 459 | +TEST_OP (bun, __builtin_isunordered) | ||
| 460 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/mips64-nomultilib.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/mips64-nomultilib.patch deleted file mode 100644 index 1ef69f899..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/mips64-nomultilib.patch +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | Index: gcc-4.5/gcc/config/mips/linux64.h | ||
| 2 | =================================================================== | ||
| 3 | --- gcc-4.5.orig/gcc/config/mips/linux64.h 2010-09-25 02:05:05.484423095 -0700 | ||
| 4 | +++ gcc-4.5/gcc/config/mips/linux64.h 2010-09-25 02:31:18.524931014 -0700 | ||
| 5 | @@ -26,7 +26,7 @@ | ||
| 6 | BASE_DRIVER_SELF_SPECS, \ | ||
| 7 | LINUX_DRIVER_SELF_SPECS \ | ||
| 8 | " %{!EB:%{!EL:%(endian_spec)}}" \ | ||
| 9 | - " %{!mabi=*: -mabi=n32}" | ||
| 10 | + " %{!mabi=*: -mabi=64}" | ||
| 11 | |||
| 12 | #undef LIB_SPEC | ||
| 13 | #define LIB_SPEC "\ | ||
| 14 | @@ -35,9 +35,9 @@ | ||
| 15 | %{!shared: \ | ||
| 16 | %{profile:-lc_p} %{!profile:-lc}}" | ||
| 17 | |||
| 18 | -#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" | ||
| 19 | -#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld.so.1" | ||
| 20 | -#define GLIBC_DYNAMIC_LINKERN32 "/lib32/ld.so.1" | ||
| 21 | +#define GLIBC_DYNAMIC_LINKER32 "/lib32/ld.so.1" | ||
| 22 | +#define GLIBC_DYNAMIC_LINKER64 "/lib/ld.so.1" | ||
| 23 | +#define GLIBC_DYNAMIC_LINKERN32 "/lib64/ld.so.1" | ||
| 24 | #define UCLIBC_DYNAMIC_LINKERN32 "/lib32/ld-uClibc.so.0" | ||
| 25 | #define LINUX_DYNAMIC_LINKERN32 \ | ||
| 26 | CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32) | ||
| 27 | Index: gcc-4.5/gcc/config.gcc | ||
| 28 | =================================================================== | ||
| 29 | --- gcc-4.5.orig/gcc/config.gcc 2010-07-22 16:37:17.000000000 -0700 | ||
| 30 | +++ gcc-4.5/gcc/config.gcc 2010-09-25 02:25:41.412414136 -0700 | ||
| 31 | @@ -1707,7 +1707,7 @@ | ||
| 32 | *-*-irix6*) | ||
| 33 | tm_file="${tm_file} mips/iris6.h" | ||
| 34 | tmake_file="${tmake_file} mips/t-iris6" | ||
| 35 | - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_N32" | ||
| 36 | + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_64" | ||
| 37 | case ${target} in | ||
| 38 | *-*-irix6.[0-4]*) | ||
| 39 | use_gcc_stdint=provide | ||
| 40 | Index: gcc-4.5/gcc/config/mips/t-linux64 | ||
| 41 | =================================================================== | ||
| 42 | --- gcc-4.5.orig/gcc/config/mips/t-linux64 2010-07-11 16:14:42.000000000 -0700 | ||
| 43 | +++ gcc-4.5/gcc/config/mips/t-linux64 2010-09-25 02:29:52.758708250 -0700 | ||
| 44 | @@ -18,7 +18,7 @@ | ||
| 45 | |||
| 46 | MULTILIB_OPTIONS = mabi=n32/mabi=32/mabi=64 | ||
| 47 | MULTILIB_DIRNAMES = n32 32 64 | ||
| 48 | -MULTILIB_OSDIRNAMES = ../lib32 ../lib ../lib64 | ||
| 49 | +MULTILIB_OSDIRNAMES = ../lib64 ../lib32 ../lib | ||
| 50 | |||
| 51 | EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o | ||
| 52 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/more-epilogues.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/more-epilogues.patch deleted file mode 100644 index 64f1cf375..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/more-epilogues.patch +++ /dev/null | |||
| @@ -1,83 +0,0 @@ | |||
| 1 | Index: a/gcc/cfgcleanup.c | ||
| 2 | =================================================================== | ||
| 3 | --- a/gcc/cfgcleanup.c (revision 315947) | ||
| 4 | +++ b/gcc/cfgcleanup.c (working copy) | ||
| 5 | @@ -1179,13 +1179,19 @@ flow_find_head_matching_sequence (basic_ | ||
| 6 | |||
| 7 | while (true) | ||
| 8 | { | ||
| 9 | - | ||
| 10 | - /* Ignore notes. */ | ||
| 11 | + /* Ignore notes, except NOTE_INSN_EPILOGUE_BEG. */ | ||
| 12 | while (!NONDEBUG_INSN_P (i1) && i1 != BB_END (bb1)) | ||
| 13 | - i1 = NEXT_INSN (i1); | ||
| 14 | - | ||
| 15 | + { | ||
| 16 | + if (NOTE_P (i1) && NOTE_KIND (i1) == NOTE_INSN_EPILOGUE_BEG) | ||
| 17 | + break; | ||
| 18 | + i1 = NEXT_INSN (i1); | ||
| 19 | + } | ||
| 20 | while (!NONDEBUG_INSN_P (i2) && i2 != BB_END (bb2)) | ||
| 21 | - i2 = NEXT_INSN (i2); | ||
| 22 | + { | ||
| 23 | + if (NOTE_P (i2) && NOTE_KIND (i2) == NOTE_INSN_EPILOGUE_BEG) | ||
| 24 | + break; | ||
| 25 | + i2 = NEXT_INSN (i2); | ||
| 26 | + } | ||
| 27 | |||
| 28 | if (NOTE_P (i1) || NOTE_P (i2) | ||
| 29 | || JUMP_P (i1) || JUMP_P (i2)) | ||
| 30 | Index: a/gcc/cfglayout.c | ||
| 31 | =================================================================== | ||
| 32 | --- a/gcc/cfglayout.c (revision 315947) | ||
| 33 | +++ b/gcc/cfglayout.c (working copy) | ||
| 34 | @@ -1295,6 +1295,16 @@ cfg_layout_initialize (unsigned int flag | ||
| 35 | bb->flags |= BB_NON_LOCAL_GOTO_TARGET; | ||
| 36 | } | ||
| 37 | |||
| 38 | + FOR_EACH_BB (bb) | ||
| 39 | + { | ||
| 40 | + rtx insn; | ||
| 41 | + FOR_BB_INSNS (bb, insn) | ||
| 42 | + if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_EPILOGUE_BEG) | ||
| 43 | + { | ||
| 44 | + bb->flags |= BB_EPILOGUE_BEGIN; | ||
| 45 | + break; | ||
| 46 | + } | ||
| 47 | + } | ||
| 48 | cleanup_cfg (CLEANUP_CFGLAYOUT | flags); | ||
| 49 | } | ||
| 50 | |||
| 51 | Index: a/gcc/basic-block.h | ||
| 52 | =================================================================== | ||
| 53 | --- a/gcc/basic-block.h (revision 315947) | ||
| 54 | +++ b/gcc/basic-block.h (working copy) | ||
| 55 | @@ -332,7 +332,11 @@ enum bb_flags | ||
| 56 | |||
| 57 | /* Set on blocks that cannot be threaded through. | ||
| 58 | Only used in cfgcleanup.c. */ | ||
| 59 | - BB_NONTHREADABLE_BLOCK = 1 << 11 | ||
| 60 | + BB_NONTHREADABLE_BLOCK = 1 << 11, | ||
| 61 | + | ||
| 62 | + /* Set on blocks that have a NOTE_INSN_EPILOGUE_BEGIN. | ||
| 63 | + Only used in cfglayout mode. */ | ||
| 64 | + BB_EPILOGUE_BEGIN = 1 << 12 | ||
| 65 | }; | ||
| 66 | |||
| 67 | /* Dummy flag for convenience in the hot/cold partitioning code. */ | ||
| 68 | Index: a/gcc/cfgrtl.c | ||
| 69 | =================================================================== | ||
| 70 | --- a/gcc/cfgrtl.c (revision 315947) | ||
| 71 | +++ b/gcc/cfgrtl.c (working copy) | ||
| 72 | @@ -2707,7 +2707,10 @@ cfg_layout_can_merge_blocks_p (basic_blo | ||
| 73 | not allow us to redirect an edge by replacing a table jump. */ | ||
| 74 | && (!JUMP_P (BB_END (a)) | ||
| 75 | || ((!optimize || reload_completed) | ||
| 76 | - ? simplejump_p (BB_END (a)) : onlyjump_p (BB_END (a))))); | ||
| 77 | + ? simplejump_p (BB_END (a)) : onlyjump_p (BB_END (a)))) | ||
| 78 | + /* Don't separate a NOTE_INSN_EPILOGUE_BEG from its returnjump. */ | ||
| 79 | + && (!(b->flags & BB_EPILOGUE_BEGIN) | ||
| 80 | + || returnjump_p (BB_END (b)))); | ||
| 81 | } | ||
| 82 | |||
| 83 | /* Merge block A and B. The blocks must be mergeable. */ | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/optional_libstdc.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/optional_libstdc.patch deleted file mode 100644 index 0f74353a1..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/optional_libstdc.patch +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | gcc-runtime builds libstdc++ separately from gcc-cross-*. Its configure tests using g++ | ||
| 2 | will not run correctly since my default the linker will try and link against libstdc++ | ||
| 3 | which shouldn't exist yet. We need an option to disable the automatically added -lstdc++ | ||
| 4 | option whilst leaving -lc, -lgcc and other automatic library dependencies. This patch | ||
| 5 | adds such an option which only disables the -lstdc++ linkage. | ||
| 6 | |||
| 7 | A "standard" gcc build uses xgcc and hence avoids this. We should ask upstream how to | ||
| 8 | do this officially, the likely answer is don't build libstdc++ separately. | ||
| 9 | |||
| 10 | RP 29/6/10 | ||
| 11 | |||
| 12 | Index: gcc-4.3.3/gcc/cp/g++spec.c | ||
| 13 | =================================================================== | ||
| 14 | --- gcc-4.3.3.orig/gcc/cp/g++spec.c 2010-06-29 00:06:03.901695025 +0100 | ||
| 15 | +++ gcc-4.3.3/gcc/cp/g++spec.c 2010-06-29 00:06:58.800325439 +0100 | ||
| 16 | @@ -131,6 +131,7 @@ | ||
| 17 | if (argv[i][0] == '-') | ||
| 18 | { | ||
| 19 | if (strcmp (argv[i], "-nostdlib") == 0 | ||
| 20 | + || strcmp (argv[i], "-nostdlib++") == 0 | ||
| 21 | || strcmp (argv[i], "-nodefaultlibs") == 0) | ||
| 22 | { | ||
| 23 | library = -1; | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/pr30961.dpatch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/pr30961.dpatch deleted file mode 100644 index b20fdf5bf..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/pr30961.dpatch +++ /dev/null | |||
| @@ -1,179 +0,0 @@ | |||
| 1 | #! /bin/sh -e | ||
| 2 | |||
| 3 | # DP: <your description> | ||
| 4 | |||
| 5 | dir= | ||
| 6 | if [ $# -eq 3 -a "$2" = '-d' ]; then | ||
| 7 | pdir="-d $3" | ||
| 8 | dir="$3/" | ||
| 9 | elif [ $# -ne 1 ]; then | ||
| 10 | echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" | ||
| 11 | exit 1 | ||
| 12 | fi | ||
| 13 | case "$1" in | ||
| 14 | -patch) | ||
| 15 | patch $pdir -f --no-backup-if-mismatch -p0 < $0 | ||
| 16 | ;; | ||
| 17 | -unpatch) | ||
| 18 | patch $pdir -f --no-backup-if-mismatch -R -p0 < $0 | ||
| 19 | ;; | ||
| 20 | *) | ||
| 21 | echo >&2 "`basename $0`: script expects -patch|-unpatch as argument" | ||
| 22 | exit 1 | ||
| 23 | esac | ||
| 24 | exit 0 | ||
| 25 | |||
| 26 | From: "H.J. Lu" <hjl@lucon.org> | ||
| 27 | Sender: gcc-patches-owner@gcc.gnu.org | ||
| 28 | To: gcc-patches@gcc.gnu.org | ||
| 29 | Subject: PATCH: PR target/30961: [4.1/4.2/4.3 regression] redundant reg/mem stores/moves | ||
| 30 | Date: Mon, 27 Aug 2007 11:34:12 -0700 | ||
| 31 | |||
| 32 | We start with | ||
| 33 | |||
| 34 | (note:HI 3 4 22 2 NOTE_INSN_FUNCTION_BEG) | ||
| 35 | |||
| 36 | (insn:HI 6 3 10 2 c.c:3 (set (reg:DF 58 [ <result> ]) | ||
| 37 | (subreg:DF (reg/v:DI 59 [ in ]) 0)) 102 {*movdf_integer_rex64} (expr_list:REG_DEAD (reg/v:DI 59 [ in ]) | ||
| 38 | (nil))) | ||
| 39 | |||
| 40 | (insn:HI 10 6 16 2 c.c:7 (set (reg/i:DF 21 xmm0 [ <result> ]) | ||
| 41 | (reg:DF 58 [ <result> ])) 102 {*movdf_integer_rex64} (expr_list:REG_DEAD (reg:DF 58 [ <result> ]) | ||
| 42 | (nil))) | ||
| 43 | |||
| 44 | (insn:HI 16 10 0 2 c.c:7 (use (reg/i:DF 21 xmm0 [ <result> ])) -1 (nil)) | ||
| 45 | |||
| 46 | we are trying to allocate registers for insn 6 and we allocate | ||
| 47 | xmm0 for the return value. Reload doesn't check if xmm0 can be used for | ||
| 48 | DF 59, it allocates xmm1 for DF 59 and generates: | ||
| 49 | |||
| 50 | Reloads for insn # 6 | ||
| 51 | Reload 0: reload_in (DF) = (reg:DF 5 di) | ||
| 52 | SSE_REGS, RELOAD_FOR_INPUT (opnum = 1), can't combine | ||
| 53 | reload_in_reg: (subreg:DF (reg/v:DI 5 di [orig:59 in ] [59]) 0) | ||
| 54 | reload_reg_rtx: (reg:DF 22 xmm1) | ||
| 55 | ... | ||
| 56 | |||
| 57 | (note:HI 4 1 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK) | ||
| 58 | |||
| 59 | (note:HI 3 4 22 2 NOTE_INSN_FUNCTION_BEG) | ||
| 60 | |||
| 61 | (insn 22 3 23 2 c.c:3 (set (mem/c:DF (plus:DI (reg/f:DI 7 sp) | ||
| 62 | (const_int -8 [0xfffffffffffffff8])) [0 S8 A8]) | ||
| 63 | (reg:DF 5 di)) 102 {*movdf_integer_rex64} (nil)) | ||
| 64 | |||
| 65 | (insn 23 22 6 2 c.c:3 (set (reg:DF 22 xmm1) | ||
| 66 | (mem/c:DF (plus:DI (reg/f:DI 7 sp) | ||
| 67 | (const_int -8 [0xfffffffffffffff8])) [0 S8 A8])) 102 {*movdf_integer_rex64} (nil)) | ||
| 68 | |||
| 69 | (insn:HI 6 23 16 2 c.c:3 (set (reg:DF 21 xmm0 [orig:58 <result> ] [58]) | ||
| 70 | (reg:DF 22 xmm1)) 102 {*movdf_integer_rex64} (nil)) | ||
| 71 | |||
| 72 | (insn 16 6 21 2 c.c:7 (use (reg/i:DF 21 xmm0 [ <result> ])) -1 (nil)) | ||
| 73 | |||
| 74 | This patch tries to use the destination register when reloading for input. It | ||
| 75 | generates | ||
| 76 | |||
| 77 | Reloads for insn # 6 | ||
| 78 | Reload 0: reload_in (DF) = (reg:DF 5 di) | ||
| 79 | SSE_REGS, RELOAD_FOR_INPUT (opnum = 1), can't combine | ||
| 80 | reload_in_reg: (subreg:DF (reg/v:DI 5 di [orig:59 in ] [59]) 0) | ||
| 81 | reload_reg_rtx: (reg:DF 21 xmm0) | ||
| 82 | ... | ||
| 83 | (note:HI 4 1 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK) | ||
| 84 | |||
| 85 | (note:HI 3 4 22 2 NOTE_INSN_FUNCTION_BEG) | ||
| 86 | |||
| 87 | (insn 22 3 23 2 c.c:3 (set (mem/c:DF (plus:DI (reg/f:DI 7 sp) | ||
| 88 | (const_int -8 [0xfffffffffffffff8])) [0 S8 A8]) | ||
| 89 | (reg:DF 5 di)) 102 {*movdf_integer_rex64} (nil)) | ||
| 90 | |||
| 91 | (insn 23 22 6 2 c.c:3 (set (reg:DF 21 xmm0) | ||
| 92 | (mem/c:DF (plus:DI (reg/f:DI 7 sp) | ||
| 93 | (const_int -8 [0xfffffffffffffff8])) [0 S8 A8])) 102 {*movdf_integer_rex64} (nil)) | ||
| 94 | |||
| 95 | (insn:HI 6 23 10 2 c.c:3 (set (reg:DF 22 xmm1 [orig:58 <result> ] [58]) | ||
| 96 | (reg:DF 21 xmm0)) 102 {*movdf_integer_rex64} (nil)) | ||
| 97 | |||
| 98 | (insn:HI 10 6 16 2 c.c:7 (set (reg/i:DF 21 xmm0 [ <result> ]) | ||
| 99 | (reg:DF 22 xmm1 [orig:58 <result> ] [58])) 102 {*movdf_integer_rex64} (nil)) | ||
| 100 | |||
| 101 | (insn 16 10 21 2 c.c:7 (use (reg/i:DF 21 xmm0 [ <result> ])) -1 (nil)) | ||
| 102 | |||
| 103 | |||
| 104 | H.J. | ||
| 105 | ---- | ||
| 106 | gcc/ | ||
| 107 | |||
| 108 | 2007-08-27 H.J. Lu <hongjiu.lu@intel.com> | ||
| 109 | |||
| 110 | PR target/30961 | ||
| 111 | * reload1.c (find_reg): Favor the hard register in destination | ||
| 112 | if it is usable and a memory location is needed for reload | ||
| 113 | input. | ||
| 114 | |||
| 115 | gcc/testsuite/ | ||
| 116 | |||
| 117 | 2007-08-27 H.J. Lu <hongjiu.lu@intel.com> | ||
| 118 | |||
| 119 | PR target/30961 | ||
| 120 | * gcc.target/i386/pr30961-1.c: New. | ||
| 121 | |||
| 122 | --- gcc/reload1.c.second 2007-08-27 09:35:08.000000000 -0700 | ||
| 123 | +++ gcc/reload1.c 2007-08-27 09:36:33.000000000 -0700 | ||
| 124 | @@ -1781,6 +1781,20 @@ find_reg (struct insn_chain *chain, int | ||
| 125 | HARD_REG_SET not_usable; | ||
| 126 | HARD_REG_SET used_by_other_reload; | ||
| 127 | reg_set_iterator rsi; | ||
| 128 | +#ifdef SECONDARY_MEMORY_NEEDED | ||
| 129 | + rtx body = PATTERN (chain->insn); | ||
| 130 | + unsigned int dest_reg = FIRST_PSEUDO_REGISTER; | ||
| 131 | + | ||
| 132 | + if (GET_CODE (body) == SET) | ||
| 133 | + { | ||
| 134 | + rtx dest = SET_DEST (body); | ||
| 135 | + | ||
| 136 | + if ((REG_P (dest) | ||
| 137 | + || (GET_CODE (dest) == SUBREG | ||
| 138 | + && REG_P (SUBREG_REG (dest))))) | ||
| 139 | + dest_reg = reg_or_subregno (dest); | ||
| 140 | + } | ||
| 141 | +#endif | ||
| 142 | |||
| 143 | COPY_HARD_REG_SET (not_usable, bad_spill_regs); | ||
| 144 | IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); | ||
| 145 | @@ -1821,6 +1835,18 @@ find_reg (struct insn_chain *chain, int | ||
| 146 | this_cost--; | ||
| 147 | if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno) | ||
| 148 | this_cost--; | ||
| 149 | +#ifdef SECONDARY_MEMORY_NEEDED | ||
| 150 | + /* If a memory location is needed for rl->in and dest_reg | ||
| 151 | + is usable, we will favor it. */ | ||
| 152 | + else if (dest_reg == regno | ||
| 153 | + && rl->in | ||
| 154 | + && REG_P (rl->in) | ||
| 155 | + && REGNO (rl->in) < FIRST_PSEUDO_REGISTER | ||
| 156 | + && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (rl->in)), | ||
| 157 | + rl->class, | ||
| 158 | + rl->mode)) | ||
| 159 | + this_cost = 0; | ||
| 160 | +#endif | ||
| 161 | if (this_cost < best_cost | ||
| 162 | /* Among registers with equal cost, prefer caller-saved ones, or | ||
| 163 | use REG_ALLOC_ORDER if it is defined. */ | ||
| 164 | --- gcc/testsuite/gcc.target/i386/pr30961-1.c.second 2007-08-27 11:01:59.000000000 -0700 | ||
| 165 | +++ gcc/testsuite/gcc.target/i386/pr30961-1.c 2007-08-27 11:02:51.000000000 -0700 | ||
| 166 | @@ -0,0 +1,13 @@ | ||
| 167 | +/* { dg-do compile } */ | ||
| 168 | +/* { dg-require-effective-target lp64 } */ | ||
| 169 | +/* { dg-options "-O2" } */ | ||
| 170 | + | ||
| 171 | +double | ||
| 172 | +convert (long long in) | ||
| 173 | +{ | ||
| 174 | + double f; | ||
| 175 | + __builtin_memcpy( &f, &in, sizeof( in ) ); | ||
| 176 | + return f; | ||
| 177 | +} | ||
| 178 | + | ||
| 179 | +/* { dg-final { scan-assembler-not "movapd" } } */ | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/pr35942.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/pr35942.patch deleted file mode 100644 index da610f518..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/pr35942.patch +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | Fix PR 35942: remove -lstdc++ from libtool postdeps for CXX. | ||
| 2 | |||
| 3 | libstdc++-v3/ChangeLog: | ||
| 4 | 2010-01-04 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> | ||
| 5 | |||
| 6 | PR libstdc++/35942 | ||
| 7 | * configure.ac: Remove -lstdc++ from libtool's postdeps_CXX. | ||
| 8 | * configure: Regenerate. | ||
| 9 | |||
| 10 | |||
| 11 | Index: gcc-4.3.3/libstdc++-v3/configure | ||
| 12 | =================================================================== | ||
| 13 | --- gcc-4.3.3.orig/libstdc++-v3/configure 2010-03-26 17:57:51.000000000 +0000 | ||
| 14 | +++ gcc-4.3.3/libstdc++-v3/configure 2010-03-26 17:57:58.000000000 +0000 | ||
| 15 | @@ -13759,6 +13759,9 @@ | ||
| 16 | |||
| 17 | |||
| 18 | |||
| 19 | +# Eliminate -lstdc++ addition to postdeps for cross compiles. | ||
| 20 | +postdeps_CXX=`echo " $postdeps_CXX " | sed 's, -lstdc++ ,,g'` | ||
| 21 | + | ||
| 22 | # Possibly disable most of the library. | ||
| 23 | ## TODO: Consider skipping unncessary tests altogether in this case, rather | ||
| 24 | ## than just ignoring the results. Faster /and/ more correct, win win. | ||
| 25 | Index: gcc-4.3.3/libstdc++-v3/configure.ac | ||
| 26 | =================================================================== | ||
| 27 | --- gcc-4.3.3.orig/libstdc++-v3/configure.ac 2010-03-26 17:57:54.000000000 +0000 | ||
| 28 | +++ gcc-4.3.3/libstdc++-v3/configure.ac 2010-03-26 17:57:58.000000000 +0000 | ||
| 29 | @@ -89,6 +89,9 @@ | ||
| 30 | AC_SUBST(enable_shared) | ||
| 31 | AC_SUBST(enable_static) | ||
| 32 | |||
| 33 | +# Eliminate -lstdc++ addition to postdeps for cross compiles. | ||
| 34 | +postdeps_CXX=`echo " $postdeps_CXX " | sed 's, -lstdc++ ,,g'` | ||
| 35 | + | ||
| 36 | # Possibly disable most of the library. | ||
| 37 | ## TODO: Consider skipping unncessary tests altogether in this case, rather | ||
| 38 | ## than just ignoring the results. Faster /and/ more correct, win win. | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/sh4-multilib.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/sh4-multilib.patch deleted file mode 100644 index c895c95e1..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/sh4-multilib.patch +++ /dev/null | |||
| @@ -1,25 +0,0 @@ | |||
| 1 | # DP: Fix multilib (m4/m4-nofpu) for sh4-linux | ||
| 2 | |||
| 3 | --- | ||
| 4 | a/gcc/config.gcc | 5 +++-- | ||
| 5 | 1 files changed, 3 insertions(+), 2 deletions(-) | ||
| 6 | |||
| 7 | Index: gcc-4_5-branch/gcc/config.gcc | ||
| 8 | =================================================================== | ||
| 9 | --- gcc-4_5-branch.orig/gcc/config.gcc 2010-12-23 00:33:39.000000000 -0800 | ||
| 10 | +++ gcc-4_5-branch/gcc/config.gcc 2011-01-09 02:57:36.608656002 -0800 | ||
| 11 | @@ -2321,11 +2321,12 @@ | ||
| 12 | if test "$sh_multilibs" = "default" ; then | ||
| 13 | case ${target} in | ||
| 14 | sh64-superh-linux* | \ | ||
| 15 | - sh[1234]*) sh_multilibs=${sh_cpu_target} ;; | ||
| 16 | sh64* | sh5*) sh_multilibs=m5-32media,m5-32media-nofpu,m5-compact,m5-compact-nofpu,m5-64media,m5-64media-nofpu ;; | ||
| 17 | - sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; | ||
| 18 | + sh-superh-* | \ | ||
| 19 | + sh4-*-linux*) sh_multilibs=m4,m4-nofpu ;; | ||
| 20 | sh*-*-linux*) sh_multilibs=m1,m3e,m4 ;; | ||
| 21 | sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; | ||
| 22 | + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; | ||
| 23 | *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; | ||
| 24 | esac | ||
| 25 | if test x$with_fp = xno; then | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/use-defaults.h-and-t-oe-in-B.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/use-defaults.h-and-t-oe-in-B.patch deleted file mode 100644 index c93e6caa0..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/use-defaults.h-and-t-oe-in-B.patch +++ /dev/null | |||
| @@ -1,57 +0,0 @@ | |||
| 1 | Upstream-Status: Pending | ||
| 2 | |||
| 3 | Use the defaults.h in ${B} instead of ${S}, and t-oe in ${B}, so that | ||
| 4 | the source can be shared between gcc-cross-initial, | ||
| 5 | gcc-cross-intermediate, gcc-cross, gcc-runtime, and also the sdk build. | ||
| 6 | --- | ||
| 7 | gcc/Makefile.in | 2 +- | ||
| 8 | gcc/configure | 4 ++-- | ||
| 9 | gcc/configure.ac | 4 ++-- | ||
| 10 | 3 files changed, 5 insertions(+), 5 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/gcc/Makefile.in b/gcc/Makefile.in | ||
| 13 | index d91f93a..03ee2bd 100644 | ||
| 14 | --- a/gcc/Makefile.in | ||
| 15 | +++ b/gcc/Makefile.in | ||
| 16 | @@ -461,7 +461,7 @@ LIMITS_H_TEST = [ -f $(SYSTEM_HEADER_DIR)/limits.h ] | ||
| 17 | TARGET_SYSTEM_ROOT = @TARGET_SYSTEM_ROOT@ | ||
| 18 | |||
| 19 | xmake_file=@xmake_file@ | ||
| 20 | -tmake_file=@tmake_file@ | ||
| 21 | +tmake_file=@tmake_file@ ./t-oe | ||
| 22 | TM_ENDIAN_CONFIG=@TM_ENDIAN_CONFIG@ | ||
| 23 | TM_MULTILIB_CONFIG=@TM_MULTILIB_CONFIG@ | ||
| 24 | TM_MULTILIB_EXCEPTIONS_CONFIG=@TM_MULTILIB_EXCEPTIONS_CONFIG@ | ||
| 25 | diff --git a/gcc/configure b/gcc/configure | ||
| 26 | index f440fa2..dafb0c1 100755 | ||
| 27 | --- a/gcc/configure | ||
| 28 | +++ b/gcc/configure | ||
| 29 | @@ -10838,8 +10838,8 @@ for f in $tm_file; do | ||
| 30 | tm_include_list="${tm_include_list} $f" | ||
| 31 | ;; | ||
| 32 | defaults.h ) | ||
| 33 | - tm_file_list="${tm_file_list} \$(srcdir)/$f" | ||
| 34 | - tm_include_list="${tm_include_list} $f" | ||
| 35 | + tm_file_list="${tm_file_list} ./$f" | ||
| 36 | + tm_include_list="${tm_include_list} ./$f" | ||
| 37 | ;; | ||
| 38 | * ) | ||
| 39 | tm_file_list="${tm_file_list} \$(srcdir)/config/$f" | ||
| 40 | diff --git a/gcc/configure.ac b/gcc/configure.ac | ||
| 41 | index d003091..ba422e6 100644 | ||
| 42 | --- a/gcc/configure.ac | ||
| 43 | +++ b/gcc/configure.ac | ||
| 44 | @@ -1652,8 +1652,8 @@ for f in $tm_file; do | ||
| 45 | tm_include_list="${tm_include_list} $f" | ||
| 46 | ;; | ||
| 47 | defaults.h ) | ||
| 48 | - tm_file_list="${tm_file_list} \$(srcdir)/$f" | ||
| 49 | - tm_include_list="${tm_include_list} $f" | ||
| 50 | + tm_file_list="${tm_file_list} ./$f" | ||
| 51 | + tm_include_list="${tm_include_list} ./$f" | ||
| 52 | ;; | ||
| 53 | * ) | ||
| 54 | tm_file_list="${tm_file_list} \$(srcdir)/config/$f" | ||
| 55 | -- | ||
| 56 | 1.7.1 | ||
| 57 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/zecke-no-host-includes.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/zecke-no-host-includes.patch deleted file mode 100644 index 4ccf35f62..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/zecke-no-host-includes.patch +++ /dev/null | |||
| @@ -1,31 +0,0 @@ | |||
| 1 | Index: gcc-4.4+svnr145550/gcc/incpath.c | ||
| 2 | =================================================================== | ||
| 3 | --- gcc-4.4+svnr145550.orig/gcc/incpath.c 2009-04-04 13:48:31.000000000 -0700 | ||
| 4 | +++ gcc-4.4+svnr145550/gcc/incpath.c 2009-04-04 14:49:29.000000000 -0700 | ||
| 5 | @@ -417,6 +417,26 @@ | ||
| 6 | p->construct = 0; | ||
| 7 | p->user_supplied_p = user_supplied_p; | ||
| 8 | |||
| 9 | +#ifdef CROSS_COMPILE | ||
| 10 | + /* A common error when cross compiling is including | ||
| 11 | + host headers. This code below will try to fail fast | ||
| 12 | + for cross compiling. Currently we consider /usr/include, | ||
| 13 | + /opt/include and /sw/include as harmful. */ | ||
| 14 | + { | ||
| 15 | + /* printf("Adding Path: %s\n", p->name ); */ | ||
| 16 | + if( strstr(p->name, "/usr/include" ) == p->name ) { | ||
| 17 | + fprintf(stderr, _("CROSS COMPILE Badness: /usr/include in INCLUDEPATH: %s\n"), p->name); | ||
| 18 | + abort(); | ||
| 19 | + } else if( strstr(p->name, "/sw/include") == p->name ) { | ||
| 20 | + fprintf(stderr, _("CROSS COMPILE Badness: /sw/include in INCLUDEPATH: %s\n"), p->name); | ||
| 21 | + abort(); | ||
| 22 | + } else if( strstr(p->name, "/opt/include") == p->name ) { | ||
| 23 | + fprintf(stderr, _("CROSS COMPILE Badness: /opt/include in INCLUDEPATH: %s\n"), p->name); | ||
| 24 | + abort(); | ||
| 25 | + } | ||
| 26 | + } | ||
| 27 | +#endif | ||
| 28 | + | ||
| 29 | add_cpp_dir_path (p, chain); | ||
| 30 | } | ||
| 31 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/zecke-xgcc-cpp.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/zecke-xgcc-cpp.patch deleted file mode 100644 index a7722cbfc..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/zecke-xgcc-cpp.patch +++ /dev/null | |||
| @@ -1,28 +0,0 @@ | |||
| 1 | upstream: n/a | ||
| 2 | comment: Use the preprocessor we have just compiled instead the one of | ||
| 3 | the system. There might be incompabilities between us and them. | ||
| 4 | |||
| 5 | Index: gcc-4.3.1/Makefile.in | ||
| 6 | =================================================================== | ||
| 7 | --- gcc-4.3.1.orig/Makefile.in 2008-08-19 01:09:56.000000000 -0700 | ||
| 8 | +++ gcc-4.3.1/Makefile.in 2008-08-19 01:13:27.000000000 -0700 | ||
| 9 | @@ -204,6 +204,7 @@ | ||
| 10 | AR="$(AR_FOR_TARGET)"; export AR; \ | ||
| 11 | AS="$(COMPILER_AS_FOR_TARGET)"; export AS; \ | ||
| 12 | CC="$(CC_FOR_TARGET)"; export CC; \ | ||
| 13 | + CPP="$(CC_FOR_TARGET) -E"; export CPP; \ | ||
| 14 | CFLAGS="$(CFLAGS_FOR_TARGET) $(SYSROOT_CFLAGS_FOR_TARGET) $(DEBUG_PREFIX_CFLAGS_FOR_TARGET)"; export CFLAGS; \ | ||
| 15 | CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \ | ||
| 16 | CPPFLAGS="$(CPPFLAGS_FOR_TARGET)"; export CPPFLAGS; \ | ||
| 17 | Index: gcc-4.3.1/Makefile.tpl | ||
| 18 | =================================================================== | ||
| 19 | --- gcc-4.3.1.orig/Makefile.tpl 2008-08-21 00:07:58.000000000 -0700 | ||
| 20 | +++ gcc-4.3.1/Makefile.tpl 2008-08-21 00:09:52.000000000 -0700 | ||
| 21 | @@ -223,6 +223,7 @@ | ||
| 22 | AR="$(AR_FOR_TARGET)"; export AR; \ | ||
| 23 | AS="$(COMPILER_AS_FOR_TARGET)"; export AS; \ | ||
| 24 | CC="$(CC_FOR_TARGET)"; export CC; \ | ||
| 25 | + CPP="$(CC_FOR_TARGET) -E"; export CPP; \ | ||
| 26 | CFLAGS="$(CFLAGS_FOR_TARGET) $(SYSROOT_CFLAGS_FOR_TARGET) $(DEBUG_PREFIX_CFLAGS_FOR_TARGET)"; export CFLAGS; \ | ||
| 27 | CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \ | ||
| 28 | CPPFLAGS="$(CPPFLAGS_FOR_TARGET)"; export CPPFLAGS; \ | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.5.bb deleted file mode 100644 index 0afc90735..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.5.bb +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | inherit cross-canadian | ||
| 2 | |||
| 3 | require recipes-devtools/gcc/gcc-${PV}.inc | ||
| 4 | require recipes-devtools/gcc/gcc-cross-canadian.inc | ||
| 5 | require recipes-devtools/gcc/gcc-configure-sdk.inc | ||
| 6 | require recipes-devtools/gcc/gcc-package-sdk.inc | ||
| 7 | |||
| 8 | |||
| 9 | DEPENDS += "gmp-nativesdk mpfr-nativesdk libmpc-nativesdk elfutils-nativesdk" | ||
| 10 | RDEPENDS_${PN} += "mpfr-nativesdk libmpc-nativesdk elfutils-nativesdk" | ||
| 11 | |||
| 12 | SYSTEMHEADERS = "/usr/include" | ||
| 13 | SYSTEMLIBS = "/lib/" | ||
| 14 | SYSTEMLIBS1 = "/usr/lib/" | ||
| 15 | |||
| 16 | EXTRA_OECONF += "--disable-libunwind-exceptions --disable-libssp \ | ||
| 17 | --disable-libgomp --disable-libmudflap \ | ||
| 18 | --with-mpfr=${STAGING_DIR_HOST}${layout_exec_prefix} \ | ||
| 19 | --with-mpc=${STAGING_DIR_HOST}${layout_exec_prefix}" | ||
| 20 | |||
| 21 | # to find libmpfr | ||
| 22 | # export LD_LIBRARY_PATH = "{STAGING_DIR_HOST}${layout_exec_prefix}" | ||
| 23 | |||
| 24 | PARALLEL_MAKE = "" | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.5.bb deleted file mode 100644 index 65ed3b4ba..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.5.bb +++ /dev/null | |||
| @@ -1,4 +0,0 @@ | |||
| 1 | require recipes-devtools/gcc/gcc-cross_${PV}.bb | ||
| 2 | require recipes-devtools/gcc/gcc-cross-initial.inc | ||
| 3 | |||
| 4 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.5.bb deleted file mode 100644 index 889228838..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.5.bb +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | require recipes-devtools/gcc/gcc-cross_${PV}.bb | ||
| 2 | require recipes-devtools/gcc/gcc-cross-intermediate.inc | ||
| 3 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.5.bb deleted file mode 100644 index fde78981f..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.5.bb +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | |||
| 2 | require recipes-devtools/gcc/gcc-${PV}.inc | ||
| 3 | require recipes-devtools/gcc/gcc-cross4.inc | ||
| 4 | |||
| 5 | EXTRA_OECONF += "--disable-libunwind-exceptions \ | ||
| 6 | --with-mpfr=${STAGING_DIR_NATIVE}${prefix_native} \ | ||
| 7 | --with-system-zlib " | ||
| 8 | |||
| 9 | ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_DIR_TARGET}${target_includedir}" | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.5.bb deleted file mode 100644 index c0b662677..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.5.bb +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | require recipes-devtools/gcc/gcc-cross-initial_${PV}.bb | ||
| 2 | require recipes-devtools/gcc/gcc-crosssdk-initial.inc | ||
| 3 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.5.bb deleted file mode 100644 index 61a0dfbab..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.5.bb +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | require recipes-devtools/gcc/gcc-cross-intermediate_${PV}.bb | ||
| 2 | require recipes-devtools/gcc/gcc-crosssdk-intermediate.inc | ||
| 3 | EXTRA_OECONF += " --with-headers=${STAGING_DIR_TCBOOTSTRAP}${SYSTEMHEADERS} " | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.5.bb deleted file mode 100644 index 40bdbf119..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.5.bb +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | require recipes-devtools/gcc/gcc-cross_${PV}.bb | ||
| 2 | require recipes-devtools/gcc/gcc-crosssdk.inc | ||
| 3 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.5.bb deleted file mode 100644 index e3b2d4ef7..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.5.bb +++ /dev/null | |||
| @@ -1,8 +0,0 @@ | |||
| 1 | |||
| 2 | require recipes-devtools/gcc/gcc-${PV}.inc | ||
| 3 | require recipes-devtools/gcc/gcc-configure-runtime.inc | ||
| 4 | require recipes-devtools/gcc/gcc-package-runtime.inc | ||
| 5 | |||
| 6 | ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_INCDIR}" | ||
| 7 | |||
| 8 | EXTRA_OECONF += "--disable-libunwind-exceptions" | ||
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc_4.5.bb b/toolchain-layer/recipes-devtools/gcc/gcc_4.5.bb deleted file mode 100644 index 19e8a25d0..000000000 --- a/toolchain-layer/recipes-devtools/gcc/gcc_4.5.bb +++ /dev/null | |||
| @@ -1,7 +0,0 @@ | |||
| 1 | |||
| 2 | require recipes-devtools/gcc/gcc-${PV}.inc | ||
| 3 | require recipes-devtools/gcc/gcc-configure-target.inc | ||
| 4 | require recipes-devtools/gcc/gcc-package-target.inc | ||
| 5 | |||
| 6 | ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_INCDIR}" | ||
| 7 | |||
diff --git a/toolchain-layer/recipes-devtools/gcc/libgcc_4.5.bb b/toolchain-layer/recipes-devtools/gcc/libgcc_4.5.bb deleted file mode 100644 index 3f63931d8..000000000 --- a/toolchain-layer/recipes-devtools/gcc/libgcc_4.5.bb +++ /dev/null | |||
| @@ -1,71 +0,0 @@ | |||
| 1 | require recipes-devtools/gcc/gcc-${PV}.inc | ||
| 2 | |||
| 3 | INHIBIT_DEFAULT_DEPS = "1" | ||
| 4 | |||
| 5 | DEPENDS = "virtual/${TARGET_PREFIX}gcc virtual/${TARGET_PREFIX}g++" | ||
| 6 | |||
| 7 | PKGSUFFIX = "" | ||
| 8 | PKGSUFFIX_virtclass-nativesdk = "-nativesdk" | ||
| 9 | |||
| 10 | PACKAGES = "\ | ||
| 11 | ${PN} \ | ||
| 12 | ${PN}-dev \ | ||
| 13 | ${PN}-dbg \ | ||
| 14 | libgcov${PKGSUFFIX}-dev \ | ||
| 15 | " | ||
| 16 | |||
| 17 | FILES_${PN} = "${base_libdir}/libgcc*.so.*" | ||
| 18 | FILES_${PN}-dev = " \ | ||
| 19 | ${base_libdir}/libgcc*.so \ | ||
| 20 | ${libdir}/${TARGET_SYS}/${BINV}/crt* \ | ||
| 21 | ${libdir}/${TARGET_SYS}/${BINV}/libgcc*" | ||
| 22 | FILES_libgcov${PKGSUFFIX}-dev = " \ | ||
| 23 | ${libdir}/${TARGET_SYS}/${BINV}/libgcov.a \ | ||
| 24 | " | ||
| 25 | FILES_${PN}-dbg += "${base_libdir}/.debug/" | ||
| 26 | |||
| 27 | do_configure () { | ||
| 28 | target=`echo ${MULTIMACH_TARGET_SYS} | sed -e s#-nativesdk##` | ||
| 29 | install -d ${D}${base_libdir} ${D}${libdir} | ||
| 30 | cp -fpPR ${STAGING_INCDIR_NATIVE}/gcc-build-internal-$target/* ${B} | ||
| 31 | mkdir -p ${B}/${BPN} | ||
| 32 | cd ${B}/${BPN} | ||
| 33 | chmod a+x ${S}/${BPN}/configure | ||
| 34 | ${S}/${BPN}/configure ${CONFIGUREOPTS} ${EXTRA_OECONF} | ||
| 35 | } | ||
| 36 | |||
| 37 | do_compile () { | ||
| 38 | target=`echo ${TARGET_SYS} | sed -e s#-nativesdk##` | ||
| 39 | cd ${B}/${BPN} | ||
| 40 | oe_runmake MULTIBUILDTOP=${B}/$target/${BPN}/ | ||
| 41 | } | ||
| 42 | |||
| 43 | do_install () { | ||
| 44 | target=`echo ${TARGET_SYS} | sed -e s#-nativesdk##` | ||
| 45 | cd ${B}/${BPN} | ||
| 46 | oe_runmake 'DESTDIR=${D}' MULTIBUILDTOP=${B}/$target/${BPN}/ install | ||
| 47 | |||
| 48 | # Move libgcc_s into /lib | ||
| 49 | mkdir -p ${D}${base_libdir} | ||
| 50 | if [ -f ${D}${libdir}/nof/libgcc_s.so ]; then | ||
| 51 | mv ${D}${libdir}/nof/libgcc* ${D}${base_libdir} | ||
| 52 | else | ||
| 53 | mv ${D}${libdir}/libgcc* ${D}${base_libdir} || true | ||
| 54 | fi | ||
| 55 | |||
| 56 | # install the runtime in /usr/lib/ not in /usr/lib/gcc on target | ||
| 57 | # so that cross-gcc can find it in the sysroot | ||
| 58 | |||
| 59 | mv ${D}${libdir}/gcc/* ${D}${libdir} | ||
| 60 | rm -rf ${D}${libdir}/gcc/ | ||
| 61 | } | ||
| 62 | |||
| 63 | do_package_write_ipk[depends] += "virtual/${MLPREFIX}libc:do_package" | ||
| 64 | do_package_write_deb[depends] += "virtual/${MLPREFIX}libc:do_package" | ||
| 65 | do_package_write_rpm[depends] += "virtual/${MLPREFIX}libc:do_package" | ||
| 66 | |||
| 67 | BBCLASSEXTEND = "nativesdk" | ||
| 68 | |||
| 69 | INSANE_SKIP_${PN}-dev = "staticdev" | ||
| 70 | INSANE_SKIP_libgcov${PKGSUFFIX}-dev = "staticdev" | ||
| 71 | |||