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-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106759.patch545
1 files changed, 0 insertions, 545 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106759.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106759.patch
deleted file mode 100644
index c51576794..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106759.patch
+++ /dev/null
@@ -1,545 +0,0 @@
12011-06-20 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline.
4 2011-06-03 Julian Brown <julian@codesourcery.com>
5
6 * config/arm/arm-cores.def (strongarm, strongarm110, strongarm1100)
7 (strongarm1110): Use strongarm tuning.
8 * config/arm/arm-protos.h (tune_params): Add max_insns_skipped
9 field.
10 * config/arm/arm.c (arm_strongarm_tune): New.
11 (arm_slowmul_tune, arm_fastmul_tune, arm_xscale_tune, arm_9e_tune)
12 (arm_v6t2_tune, arm_cortex_tune, arm_cortex_a5_tune)
13 (arm_cortex_a9_tune, arm_fa726te_tune): Add max_insns_skipped field
14 setting, using previous defaults or 1 for Cortex-A5.
15 (arm_option_override): Set max_insns_skipped from current tuning.
16
172011-06-14 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
18
19 Backport from mainline.
20 2011-06-02 Julian Brown <julian@codesourcery.com>
21
22 * config/arm/arm-cores.def (cortex-a5): Use cortex_a5 tuning.
23 * config/arm/arm.c (arm_cortex_a5_branch_cost): New.
24 (arm_cortex_a5_tune): New.
25
26 2011-06-02 Julian Brown <julian@codesourcery.com>
27
28 * config/arm/arm-protos.h (tune_params): Add branch_cost hook.
29 * config/arm/arm.c (arm_default_branch_cost): New.
30 (arm_slowmul_tune, arm_fastmul_tune, arm_xscale_tune, arm_9e_tune)
31 (arm_v6t2_tune, arm_cortex_tune, arm_cortex_a9_tune)
32 (arm_fa726_tune): Set branch_cost field using
33 arm_default_branch_cost.
34 * config/arm/arm.h (BRANCH_COST): Use branch_cost hook from
35 current_tune structure.
36 * dojump.c (tm_p.h): Include file.
37
38 2011-06-02 Julian Brown <julian@codesourcery.com>
39
40 * config/arm/arm-cores.def (arm1156t2-s, arm1156t2f-s): Use v6t2
41 tuning.
42 (cortex-a5, cortex-a8, cortex-a15, cortex-r4, cortex-r4f, cortex-m4)
43 (cortex-m3, cortex-m1, cortex-m0): Use cortex tuning.
44 * config/arm/arm-protos.h (tune_params): Add prefer_constant_pool
45 field.
46 * config/arm/arm.c (arm_slowmul_tune, arm_fastmul_tune)
47 (arm_xscale_tune, arm_9e_tune, arm_cortex_a9_tune)
48 (arm_fa726te_tune): Add prefer_constant_pool setting.
49 (arm_v6t2_tune, arm_cortex_tune): New.
50 * config/arm/arm.h (TARGET_USE_MOVT): Make dependent on
51 prefer_constant_pool setting.
52
532011-06-14 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
54
55 Backport from mainline
56 2011-06-01 Paul Brook <paul@cpodesourcery.com>
57
58 * config/arm/arm-cores.def: Add cortex-r5. Add DIV flags to
59 Cortex-A15.
60 * config/arm/arm-tune.md: Regenerate.
61 * config/arm/arm.c (FL_DIV): Rename...
62 (FL_THUMB_DIV): ... to this.
63 (FL_ARM_DIV): Define.
64 (FL_FOR_ARCH7R, FL_FOR_ARCH7M): Use FL_THUMB_DIV.
65 (arm_arch_hwdiv): Remove.
66 (arm_arch_thumb_hwdiv, arm_arch_arm_hwdiv): New variables.
67 (arm_issue_rate): Add cortexr5.
68 * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Set
69 __ARM_ARCH_EXT_IDIV__.
70 (TARGET_IDIV): Define.
71 (arm_arch_hwdiv): Remove.
72 (arm_arch_arm_hwdiv, arm_arch_thumb_hwdiv): New prototypes.
73 * config/arm/arm.md (tune_cortexr4): Add cortexr5.
74 (divsi3, udivsi3): New patterns.
75 * config/arm/thumb2.md (divsi3, udivsi3): Remove.
76 * doc/invoke.texi: Document ARM -mcpu=cortex-r5
77
78=== modified file 'gcc/config/arm/arm-cores.def'
79--- old/gcc/config/arm/arm-cores.def 2011-01-03 20:52:22 +0000
80+++ new/gcc/config/arm/arm-cores.def 2011-06-14 16:00:30 +0000
81@@ -70,10 +70,10 @@
82 /* V4 Architecture Processors */
83 ARM_CORE("arm8", arm8, 4, FL_MODE26 | FL_LDSCHED, fastmul)
84 ARM_CORE("arm810", arm810, 4, FL_MODE26 | FL_LDSCHED, fastmul)
85-ARM_CORE("strongarm", strongarm, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
86-ARM_CORE("strongarm110", strongarm110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
87-ARM_CORE("strongarm1100", strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
88-ARM_CORE("strongarm1110", strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
89+ARM_CORE("strongarm", strongarm, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
90+ARM_CORE("strongarm110", strongarm110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
91+ARM_CORE("strongarm1100", strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
92+ARM_CORE("strongarm1110", strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
93 ARM_CORE("fa526", fa526, 4, FL_LDSCHED, fastmul)
94 ARM_CORE("fa626", fa626, 4, FL_LDSCHED, fastmul)
95
96@@ -122,15 +122,16 @@
97 ARM_CORE("arm1176jzf-s", arm1176jzfs, 6ZK, FL_LDSCHED | FL_VFPV2, 9e)
98 ARM_CORE("mpcorenovfp", mpcorenovfp, 6K, FL_LDSCHED, 9e)
99 ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e)
100-ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, 9e)
101-ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, 9e)
102-ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, 9e)
103-ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e)
104+ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, v6t2)
105+ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, v6t2)
106+ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5)
107+ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex)
108 ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9)
109-ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED, 9e)
110-ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e)
111-ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e)
112-ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, 9e)
113-ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e)
114-ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e)
115-ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, 9e)
116+ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
117+ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex)
118+ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex)
119+ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex)
120+ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, cortex)
121+ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, cortex)
122+ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, cortex)
123+ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, cortex)
124
125=== modified file 'gcc/config/arm/arm-protos.h'
126--- old/gcc/config/arm/arm-protos.h 2011-05-03 15:17:25 +0000
127+++ new/gcc/config/arm/arm-protos.h 2011-06-14 16:00:30 +0000
128@@ -219,9 +219,14 @@
129 bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
130 bool (*sched_adjust_cost) (rtx, rtx, rtx, int *);
131 int constant_limit;
132+ /* Maximum number of instructions to conditionalise in
133+ arm_final_prescan_insn. */
134+ int max_insns_skipped;
135 int num_prefetch_slots;
136 int l1_cache_size;
137 int l1_cache_line_size;
138+ bool prefer_constant_pool;
139+ int (*branch_cost) (bool, bool);
140 };
141
142 extern const struct tune_params *current_tune;
143
144=== modified file 'gcc/config/arm/arm-tune.md'
145--- old/gcc/config/arm/arm-tune.md 2010-12-20 17:48:51 +0000
146+++ new/gcc/config/arm/arm-tune.md 2011-06-14 14:37:30 +0000
147@@ -1,5 +1,5 @@
148 ;; -*- buffer-read-only: t -*-
149 ;; Generated automatically by gentune.sh from arm-cores.def
150 (define_attr "tune"
151- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0"
152+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
153 (const (symbol_ref "((enum attr_tune) arm_tune)")))
154
155=== modified file 'gcc/config/arm/arm.c'
156--- old/gcc/config/arm/arm.c 2011-05-11 14:49:48 +0000
157+++ new/gcc/config/arm/arm.c 2011-06-14 16:00:30 +0000
158@@ -255,6 +255,8 @@
159 static void arm_conditional_register_usage (void);
160 static reg_class_t arm_preferred_rename_class (reg_class_t rclass);
161 static unsigned int arm_autovectorize_vector_sizes (void);
162+static int arm_default_branch_cost (bool, bool);
163+static int arm_cortex_a5_branch_cost (bool, bool);
164
165
166 /* Table of machine attributes. */
167@@ -672,12 +674,13 @@
168 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
169 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
170 profile. */
171-#define FL_DIV (1 << 18) /* Hardware divide. */
172+#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */
173 #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
174 #define FL_NEON (1 << 20) /* Neon instructions. */
175 #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
176 architecture. */
177 #define FL_ARCH7 (1 << 22) /* Architecture 7. */
178+#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
179
180 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
181
182@@ -704,8 +707,8 @@
183 #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
184 #define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
185 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
186-#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
187-#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
188+#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
189+#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
190 #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
191
192 /* The bits in this mask specify which
193@@ -791,7 +794,8 @@
194 int arm_arch_thumb2;
195
196 /* Nonzero if chip supports integer division instruction. */
197-int arm_arch_hwdiv;
198+int arm_arch_arm_hwdiv;
199+int arm_arch_thumb_hwdiv;
200
201 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference,
202 we must report the mode of the memory reference from
203@@ -864,48 +868,117 @@
204 {
205 arm_slowmul_rtx_costs,
206 NULL,
207- 3,
208- ARM_PREFETCH_NOT_BENEFICIAL
209+ 3, /* Constant limit. */
210+ 5, /* Max cond insns. */
211+ ARM_PREFETCH_NOT_BENEFICIAL,
212+ true, /* Prefer constant pool. */
213+ arm_default_branch_cost
214 };
215
216 const struct tune_params arm_fastmul_tune =
217 {
218 arm_fastmul_rtx_costs,
219 NULL,
220- 1,
221- ARM_PREFETCH_NOT_BENEFICIAL
222+ 1, /* Constant limit. */
223+ 5, /* Max cond insns. */
224+ ARM_PREFETCH_NOT_BENEFICIAL,
225+ true, /* Prefer constant pool. */
226+ arm_default_branch_cost
227+};
228+
229+/* StrongARM has early execution of branches, so a sequence that is worth
230+ skipping is shorter. Set max_insns_skipped to a lower value. */
231+
232+const struct tune_params arm_strongarm_tune =
233+{
234+ arm_fastmul_rtx_costs,
235+ NULL,
236+ 1, /* Constant limit. */
237+ 3, /* Max cond insns. */
238+ ARM_PREFETCH_NOT_BENEFICIAL,
239+ true, /* Prefer constant pool. */
240+ arm_default_branch_cost
241 };
242
243 const struct tune_params arm_xscale_tune =
244 {
245 arm_xscale_rtx_costs,
246 xscale_sched_adjust_cost,
247- 2,
248- ARM_PREFETCH_NOT_BENEFICIAL
249+ 2, /* Constant limit. */
250+ 3, /* Max cond insns. */
251+ ARM_PREFETCH_NOT_BENEFICIAL,
252+ true, /* Prefer constant pool. */
253+ arm_default_branch_cost
254 };
255
256 const struct tune_params arm_9e_tune =
257 {
258 arm_9e_rtx_costs,
259 NULL,
260- 1,
261- ARM_PREFETCH_NOT_BENEFICIAL
262+ 1, /* Constant limit. */
263+ 5, /* Max cond insns. */
264+ ARM_PREFETCH_NOT_BENEFICIAL,
265+ true, /* Prefer constant pool. */
266+ arm_default_branch_cost
267+};
268+
269+const struct tune_params arm_v6t2_tune =
270+{
271+ arm_9e_rtx_costs,
272+ NULL,
273+ 1, /* Constant limit. */
274+ 5, /* Max cond insns. */
275+ ARM_PREFETCH_NOT_BENEFICIAL,
276+ false, /* Prefer constant pool. */
277+ arm_default_branch_cost
278+};
279+
280+/* Generic Cortex tuning. Use more specific tunings if appropriate. */
281+const struct tune_params arm_cortex_tune =
282+{
283+ arm_9e_rtx_costs,
284+ NULL,
285+ 1, /* Constant limit. */
286+ 5, /* Max cond insns. */
287+ ARM_PREFETCH_NOT_BENEFICIAL,
288+ false, /* Prefer constant pool. */
289+ arm_default_branch_cost
290+};
291+
292+/* Branches can be dual-issued on Cortex-A5, so conditional execution is
293+ less appealing. Set max_insns_skipped to a low value. */
294+
295+const struct tune_params arm_cortex_a5_tune =
296+{
297+ arm_9e_rtx_costs,
298+ NULL,
299+ 1, /* Constant limit. */
300+ 1, /* Max cond insns. */
301+ ARM_PREFETCH_NOT_BENEFICIAL,
302+ false, /* Prefer constant pool. */
303+ arm_cortex_a5_branch_cost
304 };
305
306 const struct tune_params arm_cortex_a9_tune =
307 {
308 arm_9e_rtx_costs,
309 cortex_a9_sched_adjust_cost,
310- 1,
311- ARM_PREFETCH_BENEFICIAL(4,32,32)
312+ 1, /* Constant limit. */
313+ 5, /* Max cond insns. */
314+ ARM_PREFETCH_BENEFICIAL(4,32,32),
315+ false, /* Prefer constant pool. */
316+ arm_default_branch_cost
317 };
318
319 const struct tune_params arm_fa726te_tune =
320 {
321 arm_9e_rtx_costs,
322 fa726te_sched_adjust_cost,
323- 1,
324- ARM_PREFETCH_NOT_BENEFICIAL
325+ 1, /* Constant limit. */
326+ 5, /* Max cond insns. */
327+ ARM_PREFETCH_NOT_BENEFICIAL,
328+ true, /* Prefer constant pool. */
329+ arm_default_branch_cost
330 };
331
332
333@@ -1711,7 +1784,8 @@
334 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
335 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
336 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
337- arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
338+ arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0;
339+ arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0;
340 arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
341
342 /* If we are not using the default (ARM mode) section anchor offset
343@@ -1991,12 +2065,7 @@
344 max_insns_skipped = 6;
345 }
346 else
347- {
348- /* StrongARM has early execution of branches, so a sequence
349- that is worth skipping is shorter. */
350- if (arm_tune_strongarm)
351- max_insns_skipped = 3;
352- }
353+ max_insns_skipped = current_tune->max_insns_skipped;
354
355 /* Hot/Cold partitioning is not currently supported, since we can't
356 handle literal pool placement in that case. */
357@@ -8211,6 +8280,21 @@
358 return cost;
359 }
360
361+static int
362+arm_default_branch_cost (bool speed_p, bool predictable_p ATTRIBUTE_UNUSED)
363+{
364+ if (TARGET_32BIT)
365+ return (TARGET_THUMB2 && !speed_p) ? 1 : 4;
366+ else
367+ return (optimize > 0) ? 2 : 0;
368+}
369+
370+static int
371+arm_cortex_a5_branch_cost (bool speed_p, bool predictable_p)
372+{
373+ return speed_p ? 0 : arm_default_branch_cost (speed_p, predictable_p);
374+}
375+
376 static int fp_consts_inited = 0;
377
378 /* Only zero is valid for VFP. Other values are also valid for FPA. */
379@@ -23123,6 +23207,7 @@
380 {
381 case cortexr4:
382 case cortexr4f:
383+ case cortexr5:
384 case cortexa5:
385 case cortexa8:
386 case cortexa9:
387
388=== modified file 'gcc/config/arm/arm.h'
389--- old/gcc/config/arm/arm.h 2011-06-02 12:12:00 +0000
390+++ new/gcc/config/arm/arm.h 2011-06-14 14:53:07 +0000
391@@ -101,6 +101,8 @@
392 builtin_define ("__ARM_PCS"); \
393 builtin_define ("__ARM_EABI__"); \
394 } \
395+ if (TARGET_IDIV) \
396+ builtin_define ("__ARM_ARCH_EXT_IDIV__"); \
397 } while (0)
398
399 /* The various ARM cores. */
400@@ -282,7 +284,8 @@
401 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
402
403 /* Should MOVW/MOVT be used in preference to a constant pool. */
404-#define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
405+#define TARGET_USE_MOVT \
406+ (arm_arch_thumb2 && !optimize_size && !current_tune->prefer_constant_pool)
407
408 /* We could use unified syntax for arm mode, but for now we just use it
409 for Thumb-2. */
410@@ -303,6 +306,10 @@
411 /* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
412 #define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
413
414+/* Nonzero if integer division instructions supported. */
415+#define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
416+ || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
417+
418 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
419 then TARGET_AAPCS_BASED must be true -- but the converse does not
420 hold. TARGET_BPABI implies the use of the BPABI runtime library,
421@@ -487,8 +494,11 @@
422 /* Nonzero if chip supports Thumb 2. */
423 extern int arm_arch_thumb2;
424
425-/* Nonzero if chip supports integer division instruction. */
426-extern int arm_arch_hwdiv;
427+/* Nonzero if chip supports integer division instruction in ARM mode. */
428+extern int arm_arch_arm_hwdiv;
429+
430+/* Nonzero if chip supports integer division instruction in Thumb mode. */
431+extern int arm_arch_thumb_hwdiv;
432
433 #ifndef TARGET_DEFAULT
434 #define TARGET_DEFAULT (MASK_APCS_FRAME)
435@@ -2018,8 +2028,8 @@
436 /* Try to generate sequences that don't involve branches, we can then use
437 conditional instructions */
438 #define BRANCH_COST(speed_p, predictable_p) \
439- (TARGET_32BIT ? (TARGET_THUMB2 && !speed_p ? 1 : 4) \
440- : (optimize > 0 ? 2 : 0))
441+ (current_tune->branch_cost (speed_p, predictable_p))
442+
443
444 /* Position Independent Code. */
445 /* We decide which register to use based on the compilation options and
446
447=== modified file 'gcc/config/arm/arm.md'
448--- old/gcc/config/arm/arm.md 2011-06-02 15:58:33 +0000
449+++ new/gcc/config/arm/arm.md 2011-06-14 14:37:30 +0000
450@@ -490,7 +490,7 @@
451
452 (define_attr "tune_cortexr4" "yes,no"
453 (const (if_then_else
454- (eq_attr "tune" "cortexr4,cortexr4f")
455+ (eq_attr "tune" "cortexr4,cortexr4f,cortexr5")
456 (const_string "yes")
457 (const_string "no"))))
458
459@@ -3738,6 +3738,28 @@
460 (set_attr "predicable" "yes")]
461 )
462
463+
464+;; Division instructions
465+(define_insn "divsi3"
466+ [(set (match_operand:SI 0 "s_register_operand" "=r")
467+ (div:SI (match_operand:SI 1 "s_register_operand" "r")
468+ (match_operand:SI 2 "s_register_operand" "r")))]
469+ "TARGET_IDIV"
470+ "sdiv%?\t%0, %1, %2"
471+ [(set_attr "predicable" "yes")
472+ (set_attr "insn" "sdiv")]
473+)
474+
475+(define_insn "udivsi3"
476+ [(set (match_operand:SI 0 "s_register_operand" "=r")
477+ (udiv:SI (match_operand:SI 1 "s_register_operand" "r")
478+ (match_operand:SI 2 "s_register_operand" "r")))]
479+ "TARGET_IDIV"
480+ "udiv%?\t%0, %1, %2"
481+ [(set_attr "predicable" "yes")
482+ (set_attr "insn" "udiv")]
483+)
484+
485
486 ;; Unary arithmetic insns
487
488
489=== modified file 'gcc/config/arm/thumb2.md'
490--- old/gcc/config/arm/thumb2.md 2011-05-11 07:15:47 +0000
491+++ new/gcc/config/arm/thumb2.md 2011-06-14 14:37:30 +0000
492@@ -779,26 +779,6 @@
493 (set_attr "length" "2")]
494 )
495
496-(define_insn "divsi3"
497- [(set (match_operand:SI 0 "s_register_operand" "=r")
498- (div:SI (match_operand:SI 1 "s_register_operand" "r")
499- (match_operand:SI 2 "s_register_operand" "r")))]
500- "TARGET_THUMB2 && arm_arch_hwdiv"
501- "sdiv%?\t%0, %1, %2"
502- [(set_attr "predicable" "yes")
503- (set_attr "insn" "sdiv")]
504-)
505-
506-(define_insn "udivsi3"
507- [(set (match_operand:SI 0 "s_register_operand" "=r")
508- (udiv:SI (match_operand:SI 1 "s_register_operand" "r")
509- (match_operand:SI 2 "s_register_operand" "r")))]
510- "TARGET_THUMB2 && arm_arch_hwdiv"
511- "udiv%?\t%0, %1, %2"
512- [(set_attr "predicable" "yes")
513- (set_attr "insn" "udiv")]
514-)
515-
516 (define_insn "*thumb2_subsi_short"
517 [(set (match_operand:SI 0 "low_register_operand" "=l")
518 (minus:SI (match_operand:SI 1 "low_register_operand" "l")
519
520=== modified file 'gcc/doc/invoke.texi'
521--- old/gcc/doc/invoke.texi 2011-05-11 07:15:47 +0000
522+++ new/gcc/doc/invoke.texi 2011-06-14 14:37:30 +0000
523@@ -10208,7 +10208,8 @@
524 @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
525 @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
526 @samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a15},
527-@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3},
528+@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
529+@samp{cortex-m4}, @samp{cortex-m3},
530 @samp{cortex-m1},
531 @samp{cortex-m0},
532 @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
533
534=== modified file 'gcc/dojump.c'
535--- old/gcc/dojump.c 2010-05-19 19:09:57 +0000
536+++ new/gcc/dojump.c 2011-06-14 14:53:07 +0000
537@@ -36,6 +36,7 @@
538 #include "ggc.h"
539 #include "basic-block.h"
540 #include "output.h"
541+#include "tm_p.h"
542
543 static bool prefer_and_bit_test (enum machine_mode, int);
544 static void do_jump_by_parts_greater (tree, tree, int, rtx, rtx, int);
545
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