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-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch360
1 files changed, 360 insertions, 0 deletions
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch
new file mode 100644
index 000000000..60608e481
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99373.patch
@@ -0,0 +1,360 @@
1 Backport from FSF:
2
3 2010-08-25 Julian Brown <julian@codesourcery.com>
4
5 * config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5.
6 * config/arm/arm.md (generic_sched): No for Cortex-A5.
7 (generic_vfp): Likewise.
8 (cortex-a5.md): Include.
9 * config/arm/cortex-a5.md: New.
10
112010-08-25 Andrew Stubbs <ams@codesourcery.com>
12
13 Revert:
14
15 2010-07-26 Julian Brown <julian@codesourcery.com>
16
17=== modified file 'gcc/config/arm/arm.c'
18--- old/gcc/config/arm/arm.c 2010-08-25 16:20:13 +0000
19+++ new/gcc/config/arm/arm.c 2010-08-25 16:22:17 +0000
20@@ -22472,6 +22472,7 @@
21 {
22 case cortexr4:
23 case cortexr4f:
24+ case cortexa5:
25 case cortexa8:
26 case cortexa9:
27 return 2;
28
29=== modified file 'gcc/config/arm/arm.md'
30--- old/gcc/config/arm/arm.md 2010-08-25 16:20:13 +0000
31+++ new/gcc/config/arm/arm.md 2010-08-25 16:22:17 +0000
32@@ -412,7 +412,7 @@
33
34 (define_attr "generic_sched" "yes,no"
35 (const (if_then_else
36- (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9")
37+ (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9")
38 (eq_attr "tune_cortexr4" "yes"))
39 (const_string "no")
40 (const_string "yes"))))
41@@ -420,7 +420,7 @@
42 (define_attr "generic_vfp" "yes,no"
43 (const (if_then_else
44 (and (eq_attr "fpu" "vfp")
45- (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9")
46+ (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9")
47 (eq_attr "tune_cortexr4" "no"))
48 (const_string "yes")
49 (const_string "no"))))
50@@ -444,6 +444,7 @@
51 (include "arm1020e.md")
52 (include "arm1026ejs.md")
53 (include "arm1136jfs.md")
54+(include "cortex-a5.md")
55 (include "cortex-a8.md")
56 (include "cortex-a9.md")
57 (include "cortex-r4.md")
58
59=== added file 'gcc/config/arm/cortex-a5.md'
60--- old/gcc/config/arm/cortex-a5.md 1970-01-01 00:00:00 +0000
61+++ new/gcc/config/arm/cortex-a5.md 2010-08-25 16:22:17 +0000
62@@ -0,0 +1,297 @@
63+;; ARM Cortex-A5 pipeline description
64+;; Copyright (C) 2010 Free Software Foundation, Inc.
65+;; Contributed by CodeSourcery.
66+;;
67+;; This file is part of GCC.
68+;;
69+;; GCC is free software; you can redistribute it and/or modify it
70+;; under the terms of the GNU General Public License as published by
71+;; the Free Software Foundation; either version 3, or (at your option)
72+;; any later version.
73+;;
74+;; GCC is distributed in the hope that it will be useful, but
75+;; WITHOUT ANY WARRANTY; without even the implied warranty of
76+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
77+;; General Public License for more details.
78+;;
79+;; You should have received a copy of the GNU General Public License
80+;; along with GCC; see the file COPYING3. If not see
81+;; <http://www.gnu.org/licenses/>.
82+
83+(define_automaton "cortex_a5")
84+
85+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
86+;; Functional units.
87+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
88+
89+;; The integer (ALU) pipeline. There are five DPU pipeline
90+;; stages. However the decode/issue stages operate the same for all
91+;; instructions, so do not model them. We only need to model the
92+;; first execute stage because instructions always advance one stage
93+;; per cycle in order. Only branch instructions may dual-issue, so a
94+;; single unit covers all of the LS, ALU, MAC and FPU pipelines.
95+
96+(define_cpu_unit "cortex_a5_ex1" "cortex_a5")
97+
98+;; The branch pipeline. Branches can dual-issue with other instructions
99+;; (except when those instructions take multiple cycles to issue).
100+
101+(define_cpu_unit "cortex_a5_branch" "cortex_a5")
102+
103+;; Pseudo-unit for blocking the multiply pipeline when a double-precision
104+;; multiply is in progress.
105+
106+(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5")
107+
108+;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
109+;; of the add pipeline by fmac instructions, etc.
110+
111+(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5")
112+
113+;; Floating-point div/sqrt (long latency, out-of-order completion).
114+
115+(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5")
116+
117+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
118+;; ALU instructions.
119+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
120+
121+(define_insn_reservation "cortex_a5_alu" 2
122+ (and (eq_attr "tune" "cortexa5")
123+ (eq_attr "type" "alu"))
124+ "cortex_a5_ex1")
125+
126+(define_insn_reservation "cortex_a5_alu_shift" 2
127+ (and (eq_attr "tune" "cortexa5")
128+ (eq_attr "type" "alu_shift,alu_shift_reg"))
129+ "cortex_a5_ex1")
130+
131+;; Forwarding path for unshifted operands.
132+
133+(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
134+ "cortex_a5_alu")
135+
136+(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
137+ "cortex_a5_alu_shift"
138+ "arm_no_early_alu_shift_dep")
139+
140+;; The multiplier pipeline can forward results from wr stage only so
141+;; there's no need to specify bypasses).
142+
143+(define_insn_reservation "cortex_a5_mul" 2
144+ (and (eq_attr "tune" "cortexa5")
145+ (eq_attr "type" "mult"))
146+ "cortex_a5_ex1")
147+
148+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
149+;; Load/store instructions.
150+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
151+
152+;; Address-generation happens in the issue stage, which is one stage behind
153+;; the ex1 stage (the first stage we care about for scheduling purposes). The
154+;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr.
155+
156+(define_insn_reservation "cortex_a5_load1" 2
157+ (and (eq_attr "tune" "cortexa5")
158+ (eq_attr "type" "load_byte,load1"))
159+ "cortex_a5_ex1")
160+
161+(define_insn_reservation "cortex_a5_store1" 0
162+ (and (eq_attr "tune" "cortexa5")
163+ (eq_attr "type" "store1"))
164+ "cortex_a5_ex1")
165+
166+(define_insn_reservation "cortex_a5_load2" 3
167+ (and (eq_attr "tune" "cortexa5")
168+ (eq_attr "type" "load2"))
169+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
170+
171+(define_insn_reservation "cortex_a5_store2" 0
172+ (and (eq_attr "tune" "cortexa5")
173+ (eq_attr "type" "store2"))
174+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
175+
176+(define_insn_reservation "cortex_a5_load3" 4
177+ (and (eq_attr "tune" "cortexa5")
178+ (eq_attr "type" "load3"))
179+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
180+ cortex_a5_ex1")
181+
182+(define_insn_reservation "cortex_a5_store3" 0
183+ (and (eq_attr "tune" "cortexa5")
184+ (eq_attr "type" "store3"))
185+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
186+ cortex_a5_ex1")
187+
188+(define_insn_reservation "cortex_a5_load4" 5
189+ (and (eq_attr "tune" "cortexa5")
190+ (eq_attr "type" "load3"))
191+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
192+ cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
193+
194+(define_insn_reservation "cortex_a5_store4" 0
195+ (and (eq_attr "tune" "cortexa5")
196+ (eq_attr "type" "store3"))
197+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
198+ cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
199+
200+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
201+;; Branches.
202+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
203+
204+;; Direct branches are the only instructions we can dual-issue (also IT and
205+;; nop, but those aren't very interesting for scheduling). (The latency here
206+;; is meant to represent when the branch actually takes place, but may not be
207+;; entirely correct.)
208+
209+(define_insn_reservation "cortex_a5_branch" 3
210+ (and (eq_attr "tune" "cortexa5")
211+ (eq_attr "type" "branch,call"))
212+ "cortex_a5_branch")
213+
214+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
215+;; Floating-point arithmetic.
216+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
217+
218+(define_insn_reservation "cortex_a5_fpalu" 4
219+ (and (eq_attr "tune" "cortexa5")
220+ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
221+ fcmps, fcmpd"))
222+ "cortex_a5_ex1+cortex_a5_fpadd_pipe")
223+
224+;; For fconsts and fconstd, 8-bit immediate data is passed directly from
225+;; f1 to f3 (which I think reduces the latency by one cycle).
226+
227+(define_insn_reservation "cortex_a5_fconst" 3
228+ (and (eq_attr "tune" "cortexa5")
229+ (eq_attr "type" "fconsts,fconstd"))
230+ "cortex_a5_ex1+cortex_a5_fpadd_pipe")
231+
232+;; We should try not to attempt to issue a single-precision multiplication in
233+;; the middle of a double-precision multiplication operation (the usage of
234+;; cortex_a5_fpmul_pipe).
235+
236+(define_insn_reservation "cortex_a5_fpmuls" 4
237+ (and (eq_attr "tune" "cortexa5")
238+ (eq_attr "type" "fmuls"))
239+ "cortex_a5_ex1+cortex_a5_fpmul_pipe")
240+
241+;; For single-precision multiply-accumulate, the add (accumulate) is issued
242+;; whilst the multiply is in F4. The multiply result can then be forwarded
243+;; from F5 to F1. The issue unit is only used once (when we first start
244+;; processing the instruction), but the usage of the FP add pipeline could
245+;; block other instructions attempting to use it simultaneously. We try to
246+;; avoid that using cortex_a5_fpadd_pipe.
247+
248+(define_insn_reservation "cortex_a5_fpmacs" 8
249+ (and (eq_attr "tune" "cortexa5")
250+ (eq_attr "type" "fmacs"))
251+ "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
252+
253+;; Non-multiply instructions can issue in the middle two instructions of a
254+;; double-precision multiply. Note that it isn't entirely clear when a branch
255+;; can dual-issue when a multi-cycle multiplication is in progress; we ignore
256+;; that for now though.
257+
258+(define_insn_reservation "cortex_a5_fpmuld" 7
259+ (and (eq_attr "tune" "cortexa5")
260+ (eq_attr "type" "fmuld"))
261+ "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
262+ cortex_a5_ex1+cortex_a5_fpmul_pipe")
263+
264+(define_insn_reservation "cortex_a5_fpmacd" 11
265+ (and (eq_attr "tune" "cortexa5")
266+ (eq_attr "type" "fmacd"))
267+ "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
268+ cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
269+
270+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
271+;; Floating-point divide/square root instructions.
272+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
273+
274+;; ??? Not sure if the 14 cycles taken for single-precision divide to complete
275+;; includes the time taken for the special instruction used to collect the
276+;; result to travel down the multiply pipeline, or not. Assuming so. (If
277+;; that's wrong, the latency should be increased by a few cycles.)
278+
279+;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the
280+;; multiply pipeline to collect the divide/square-root result.
281+
282+(define_insn_reservation "cortex_a5_fdivs" 14
283+ (and (eq_attr "tune" "cortexa5")
284+ (eq_attr "type" "fdivs"))
285+ "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13")
286+
287+;; ??? Similarly for fdivd.
288+
289+(define_insn_reservation "cortex_a5_fdivd" 29
290+ (and (eq_attr "tune" "cortexa5")
291+ (eq_attr "type" "fdivd"))
292+ "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28")
293+
294+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
295+;; VFP to/from core transfers.
296+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
297+
298+;; FP loads take data from wr/rot/f3.
299+
300+;; Core-to-VFP transfers use the multiply pipeline.
301+
302+(define_insn_reservation "cortex_a5_r2f" 4
303+ (and (eq_attr "tune" "cortexa5")
304+ (eq_attr "type" "r_2_f"))
305+ "cortex_a5_ex1")
306+
307+(define_insn_reservation "cortex_a5_f2r" 2
308+ (and (eq_attr "tune" "cortexa5")
309+ (eq_attr "type" "f_2_r"))
310+ "cortex_a5_ex1")
311+
312+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
313+;; VFP flag transfer.
314+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
315+
316+;; ??? The flag forwarding from fmstat to the ex2 stage of the second
317+;; instruction is not modeled at present.
318+
319+(define_insn_reservation "cortex_a5_f_flags" 4
320+ (and (eq_attr "tune" "cortexa5")
321+ (eq_attr "type" "f_flag"))
322+ "cortex_a5_ex1")
323+
324+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
325+;; VFP load/store.
326+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
327+
328+(define_insn_reservation "cortex_a5_f_loads" 4
329+ (and (eq_attr "tune" "cortexa5")
330+ (eq_attr "type" "f_loads"))
331+ "cortex_a5_ex1")
332+
333+(define_insn_reservation "cortex_a5_f_loadd" 5
334+ (and (eq_attr "tune" "cortexa5")
335+ (eq_attr "type" "f_load,f_loadd"))
336+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
337+
338+(define_insn_reservation "cortex_a5_f_stores" 0
339+ (and (eq_attr "tune" "cortexa5")
340+ (eq_attr "type" "f_stores"))
341+ "cortex_a5_ex1")
342+
343+(define_insn_reservation "cortex_a5_f_stored" 0
344+ (and (eq_attr "tune" "cortexa5")
345+ (eq_attr "type" "f_store,f_stored"))
346+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
347+
348+;; Load-to-use for floating-point values has a penalty of one cycle,
349+;; i.e. a latency of two.
350+
351+(define_bypass 2 "cortex_a5_f_loads"
352+ "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
353+ cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
354+ cortex_a5_f2r")
355+
356+(define_bypass 3 "cortex_a5_f_loadd"
357+ "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
358+ cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
359+ cortex_a5_f2r")
360
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