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diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch
new file mode 100644
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+++ b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99372.patch
@@ -0,0 +1,380 @@
12010-08-25 Andrew Stubbs <ams@codesourcery.com>
2
3 Revert:
4
5 2010-07-26 Julian Brown <julian@codesourcery.com>
6
7 Merge from Sourcery G++ 4.4:
8
9 2010-04-11 Julian Brown <julian@codesourcery.com>
10
11 Issue #7326
12
13 gcc/
14 * config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5.
15 * config/arm/arm.md (generic_sched): No for Cortex-A5.
16 (generic_vfp): Likewise.
17 (cortex-a5.md): Include.
18 * config/arm/cortex-a5.md: New.
19
20 2010-08-24 Andrew Stubbs <ams@codesourcery.com>
21
22 Backport from FSF:
23
24=== modified file 'gcc/config/arm/arm.c'
25--- old/gcc/config/arm/arm.c 2010-08-24 13:15:54 +0000
26+++ new/gcc/config/arm/arm.c 2010-08-25 16:20:13 +0000
27@@ -22472,7 +22472,6 @@
28 {
29 case cortexr4:
30 case cortexr4f:
31- case cortexa5:
32 case cortexa8:
33 case cortexa9:
34 return 2;
35
36=== modified file 'gcc/config/arm/arm.md'
37--- old/gcc/config/arm/arm.md 2010-08-24 13:15:54 +0000
38+++ new/gcc/config/arm/arm.md 2010-08-25 16:20:13 +0000
39@@ -412,7 +412,7 @@
40
41 (define_attr "generic_sched" "yes,no"
42 (const (if_then_else
43- (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9")
44+ (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9")
45 (eq_attr "tune_cortexr4" "yes"))
46 (const_string "no")
47 (const_string "yes"))))
48@@ -420,7 +420,7 @@
49 (define_attr "generic_vfp" "yes,no"
50 (const (if_then_else
51 (and (eq_attr "fpu" "vfp")
52- (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9")
53+ (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9")
54 (eq_attr "tune_cortexr4" "no"))
55 (const_string "yes")
56 (const_string "no"))))
57@@ -444,7 +444,6 @@
58 (include "arm1020e.md")
59 (include "arm1026ejs.md")
60 (include "arm1136jfs.md")
61-(include "cortex-a5.md")
62 (include "cortex-a8.md")
63 (include "cortex-a9.md")
64 (include "cortex-r4.md")
65
66=== removed file 'gcc/config/arm/cortex-a5.md'
67--- old/gcc/config/arm/cortex-a5.md 2010-08-13 15:15:12 +0000
68+++ new/gcc/config/arm/cortex-a5.md 1970-01-01 00:00:00 +0000
69@@ -1,310 +0,0 @@
70-;; ARM Cortex-A5 pipeline description
71-;; Copyright (C) 2010 Free Software Foundation, Inc.
72-;; Contributed by CodeSourcery.
73-;;
74-;; This file is part of GCC.
75-;;
76-;; GCC is free software; you can redistribute it and/or modify it
77-;; under the terms of the GNU General Public License as published by
78-;; the Free Software Foundation; either version 3, or (at your option)
79-;; any later version.
80-;;
81-;; GCC is distributed in the hope that it will be useful, but
82-;; WITHOUT ANY WARRANTY; without even the implied warranty of
83-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
84-;; General Public License for more details.
85-;;
86-;; You should have received a copy of the GNU General Public License
87-;; along with GCC; see the file COPYING3. If not see
88-;; <http://www.gnu.org/licenses/>.
89-
90-(define_automaton "cortex_a5")
91-
92-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
93-;; Functional units.
94-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
95-
96-;; The integer (ALU) pipeline. There are five DPU pipeline stages. However the
97-;; decode/issue stages operate the same for all instructions, so do not model
98-;; them. We only need to model the first execute stage because instructions
99-;; always advance one stage per cycle in order. Only branch instructions may
100-;; dual-issue, so a single unit covers all of the LS, ALU, MAC and FPU
101-;; pipelines.
102-
103-(define_cpu_unit "cortex_a5_ex1" "cortex_a5")
104-
105-;; The branch pipeline. Branches can dual-issue with other instructions
106-;; (except when those instructions take multiple cycles to issue).
107-
108-(define_cpu_unit "cortex_a5_branch" "cortex_a5")
109-
110-;; Pseudo-unit for blocking the multiply pipeline when a double-precision
111-;; multiply is in progress.
112-
113-(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5")
114-
115-;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
116-;; of the add pipeline by fmac instructions, etc.
117-
118-(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5")
119-
120-;; Floating-point div/sqrt (long latency, out-of-order completion).
121-
122-(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5")
123-
124-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
125-;; ALU instructions.
126-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
127-
128-(define_insn_reservation "cortex_a5_alu" 2
129- (and (eq_attr "tune" "cortexa5")
130- (eq_attr "type" "alu"))
131- "cortex_a5_ex1")
132-
133-(define_insn_reservation "cortex_a5_alu_shift" 2
134- (and (eq_attr "tune" "cortexa5")
135- (eq_attr "type" "alu_shift,alu_shift_reg"))
136- "cortex_a5_ex1")
137-
138-;; Forwarding path for unshifted operands.
139-
140-(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
141- "cortex_a5_alu")
142-
143-(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
144- "cortex_a5_alu_shift"
145- "arm_no_early_alu_shift_dep")
146-
147-;; The multiplier pipeline can forward results from wr stage only (so I don't
148-;; think there's any need to specify bypasses).
149-
150-(define_insn_reservation "cortex_a5_mul" 2
151- (and (eq_attr "tune" "cortexa5")
152- (eq_attr "type" "mult"))
153- "cortex_a5_ex1")
154-
155-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
156-;; Load/store instructions.
157-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
158-
159-;; Address-generation happens in the issue stage, which is one stage behind
160-;; the ex1 stage (the first stage we care about for scheduling purposes). The
161-;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr.
162-
163-;; FIXME: These might not be entirely accurate for load2, load3, load4. I think
164-;; they make sense since there's a 32-bit interface between the DPU and the DCU,
165-;; so we can't load more than that per cycle. The store2, store3, store4
166-;; reservations are similarly guessed.
167-
168-(define_insn_reservation "cortex_a5_load1" 2
169- (and (eq_attr "tune" "cortexa5")
170- (eq_attr "type" "load_byte,load1"))
171- "cortex_a5_ex1")
172-
173-(define_insn_reservation "cortex_a5_store1" 0
174- (and (eq_attr "tune" "cortexa5")
175- (eq_attr "type" "store1"))
176- "cortex_a5_ex1")
177-
178-(define_insn_reservation "cortex_a5_load2" 3
179- (and (eq_attr "tune" "cortexa5")
180- (eq_attr "type" "load2"))
181- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
182-
183-(define_insn_reservation "cortex_a5_store2" 0
184- (and (eq_attr "tune" "cortexa5")
185- (eq_attr "type" "store2"))
186- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
187-
188-(define_insn_reservation "cortex_a5_load3" 4
189- (and (eq_attr "tune" "cortexa5")
190- (eq_attr "type" "load3"))
191- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
192- cortex_a5_ex1")
193-
194-(define_insn_reservation "cortex_a5_store3" 0
195- (and (eq_attr "tune" "cortexa5")
196- (eq_attr "type" "store3"))
197- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
198- cortex_a5_ex1")
199-
200-(define_insn_reservation "cortex_a5_load4" 5
201- (and (eq_attr "tune" "cortexa5")
202- (eq_attr "type" "load3"))
203- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
204- cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
205-
206-(define_insn_reservation "cortex_a5_store4" 0
207- (and (eq_attr "tune" "cortexa5")
208- (eq_attr "type" "store3"))
209- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
210- cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
211-
212-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
213-;; Branches.
214-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
215-
216-;; Direct branches are the only instructions we can dual-issue (also IT and
217-;; nop, but those aren't very interesting for scheduling). (The latency here
218-;; is meant to represent when the branch actually takes place, but may not be
219-;; entirely correct.)
220-
221-(define_insn_reservation "cortex_a5_branch" 3
222- (and (eq_attr "tune" "cortexa5")
223- (eq_attr "type" "branch,call"))
224- "cortex_a5_branch")
225-
226-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
227-;; Floating-point arithmetic.
228-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
229-
230-(define_insn_reservation "cortex_a5_fpalu" 4
231- (and (eq_attr "tune" "cortexa5")
232- (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
233- fcmps, fcmpd"))
234- "cortex_a5_ex1+cortex_a5_fpadd_pipe")
235-
236-;; For fconsts and fconstd, 8-bit immediate data is passed directly from
237-;; f1 to f3 (which I think reduces the latency by one cycle).
238-
239-(define_insn_reservation "cortex_a5_fconst" 3
240- (and (eq_attr "tune" "cortexa5")
241- (eq_attr "type" "fconsts,fconstd"))
242- "cortex_a5_ex1+cortex_a5_fpadd_pipe")
243-
244-;; We should try not to attempt to issue a single-precision multiplication in
245-;; the middle of a double-precision multiplication operation (the usage of
246-;; cortex_a5_fpmul_pipe).
247-
248-(define_insn_reservation "cortex_a5_fpmuls" 4
249- (and (eq_attr "tune" "cortexa5")
250- (eq_attr "type" "fmuls"))
251- "cortex_a5_ex1+cortex_a5_fpmul_pipe")
252-
253-;; For single-precision multiply-accumulate, the add (accumulate) is issued
254-;; whilst the multiply is in F4. The multiply result can then be forwarded
255-;; from F5 to F1. The issue unit is only used once (when we first start
256-;; processing the instruction), but the usage of the FP add pipeline could
257-;; block other instructions attempting to use it simultaneously. We try to
258-;; avoid that using cortex_a5_fpadd_pipe.
259-
260-(define_insn_reservation "cortex_a5_fpmacs" 8
261- (and (eq_attr "tune" "cortexa5")
262- (eq_attr "type" "fmacs"))
263- "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
264-
265-;; Non-multiply instructions can issue in the middle two instructions of a
266-;; double-precision multiply. Note that it isn't entirely clear when a branch
267-;; can dual-issue when a multi-cycle multiplication is in progress; we ignore
268-;; that for now though.
269-
270-(define_insn_reservation "cortex_a5_fpmuld" 7
271- (and (eq_attr "tune" "cortexa5")
272- (eq_attr "type" "fmuld"))
273- "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
274- cortex_a5_ex1+cortex_a5_fpmul_pipe")
275-
276-(define_insn_reservation "cortex_a5_fpmacd" 11
277- (and (eq_attr "tune" "cortexa5")
278- (eq_attr "type" "fmacd"))
279- "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
280- cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
281-
282-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
283-;; Floating-point divide/square root instructions.
284-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
285-
286-;; ??? Not sure if the 14 cycles taken for single-precision divide to complete
287-;; includes the time taken for the special instruction used to collect the
288-;; result to travel down the multiply pipeline, or not. Assuming so. (If
289-;; that's wrong, the latency should be increased by a few cycles.)
290-
291-;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the
292-;; multiply pipeline to collect the divide/square-root result.
293-
294-(define_insn_reservation "cortex_a5_fdivs" 14
295- (and (eq_attr "tune" "cortexa5")
296- (eq_attr "type" "fdivs"))
297- "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13")
298-
299-;; ??? Similarly for fdivd.
300-
301-(define_insn_reservation "cortex_a5_fdivd" 29
302- (and (eq_attr "tune" "cortexa5")
303- (eq_attr "type" "fdivd"))
304- "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28")
305-
306-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
307-;; VFP to/from core transfers.
308-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
309-
310-;; FP loads take data from wr/rot/f3. Might need to define bypasses to model
311-;; this?
312-
313-;; Core-to-VFP transfers use the multiply pipeline.
314-;; Not sure about this at all... I think we need some bypasses too.
315-
316-(define_insn_reservation "cortex_a5_r2f" 4
317- (and (eq_attr "tune" "cortexa5")
318- (eq_attr "type" "r_2_f"))
319- "cortex_a5_ex1")
320-
321-;; Not sure about this either. 6.8.7 says "Additionally, the store pipe used
322-;; for store and FP->core register transfers can forward into the F2 and F3
323-;; stages."
324-;; This doesn't correspond to what we have though.
325-
326-(define_insn_reservation "cortex_a5_f2r" 2
327- (and (eq_attr "tune" "cortexa5")
328- (eq_attr "type" "f_2_r"))
329- "cortex_a5_ex1")
330-
331-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
332-;; VFP flag transfer.
333-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
334-
335-;; ??? The flag forwarding described in section 6.8.11 of the Cortex-A5 DPU
336-;; specification (from fmstat to the ex2 stage of the second instruction) is
337-;; not modeled at present.
338-
339-(define_insn_reservation "cortex_a5_f_flags" 4
340- (and (eq_attr "tune" "cortexa5")
341- (eq_attr "type" "f_flag"))
342- "cortex_a5_ex1")
343-
344-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
345-;; VFP load/store.
346-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
347-
348-(define_insn_reservation "cortex_a5_f_loads" 4
349- (and (eq_attr "tune" "cortexa5")
350- (eq_attr "type" "f_loads"))
351- "cortex_a5_ex1")
352-
353-(define_insn_reservation "cortex_a5_f_loadd" 5
354- (and (eq_attr "tune" "cortexa5")
355- (eq_attr "type" "f_load,f_loadd"))
356- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
357-
358-(define_insn_reservation "cortex_a5_f_stores" 0
359- (and (eq_attr "tune" "cortexa5")
360- (eq_attr "type" "f_stores"))
361- "cortex_a5_ex1")
362-
363-(define_insn_reservation "cortex_a5_f_stored" 0
364- (and (eq_attr "tune" "cortexa5")
365- (eq_attr "type" "f_store,f_stored"))
366- "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
367-
368-;; Load-to-use for floating-point values has a penalty of one cycle, i.e. a
369-;; latency of two (6.8.3).
370-
371-(define_bypass 2 "cortex_a5_f_loads"
372- "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
373- cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
374- cortex_a5_f2r")
375-
376-(define_bypass 3 "cortex_a5_f_loadd"
377- "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
378- cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
379- cortex_a5_f2r")
380
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