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authorKhem Raj <raj.khem@gmail.com>2012-06-28 12:19:53 -0700
committerKoen Kooi <koen@dominion.thruhere.net>2012-07-09 18:40:21 +0200
commit6b278fbb02d818b54b5a9fa2716fc49e896b72a8 (patch)
tree833783fb738ff7abf3d0e3029c9a468e73b06e28 /toolchain-layer
parent680af24d1ff95533db610176e6b01fcc9dcf6699 (diff)
downloadmeta-openembedded-6b278fbb02d818b54b5a9fa2716fc49e896b72a8.tar.gz
gcc-4.6: Migrate recipes from OE-Core
Remove linaro patches. If one needs to use linaro modified gcc they should use meta-linaro Signed-off-by: Khem Raj <raj.khem@gmail.com>
Diffstat (limited to 'toolchain-layer')
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6.inc119
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/100-uclibc-conf.patch39
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/103-uclibc-conf-noupstream.patch17
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/200-uclibc-locale.patch2842
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/203-uclibc-locale-no__x.patch235
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/204-uclibc-locale-wchar_fix.patch54
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/205-uclibc-locale-update.patch521
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/301-missing-execinfo_h.patch15
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/302-c99-snprintf.patch15
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/303-c99-complex-ugly-hack.patch16
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/304-index_macro.patch30
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/305-libmudflap-susv3-legacy.patch51
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/306-libstdc++-namespace.patch40
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/64bithack.patch68
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/740-sh-pr24836.patch31
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/800-arm-bigendian.patch36
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/904-flatten-switch-stmt-00.patch76
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/COLLECT_GCC_OPTIONS.patch25
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch186
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/arm-nolibfloat.patch26
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/arm-softfloat.patch18
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/cache-amnesia.patch33
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/cpp-honour-sysroot.patch40
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/disable_relax_pic_calls_flag.patch48
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/fix-for-ice-50099.patch49
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/fortran-cross-compile-hack.patch32
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch33
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-4.3.3-SYSROOT_CFLAGS_FOR_TARGET.patch116
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-argument-list-too-long.patch33
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-arm-set-cost.patch35
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-flags-for-build.patch189
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-poison-dir-extend.patch27
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-poison-system-directories.patch223
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-uclibc-locale-ctype_touplow_t.patch72
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-with-linker-hash-style.patch196
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/fix_linaro_106872.patch45
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106720.patch51
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106733.patch653
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106737.patch126
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106738.patch177
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106739.patch140
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106741.patch255
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch6125
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106744.patch21
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106746.patch24
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106747.patch640
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106750.patch30
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106751.patch134
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106753.patch5027
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106754.patch329
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106755.patch120
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106759.patch545
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106762.patch1355
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch24
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106764.patch25
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106766.patch25
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106768.patch182
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106769.patch1281
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106770.patch138
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106771.patch211
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106772.patch350
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106773.patch119
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106775.patch67
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106776.patch46
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106777.patch192
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106778.patch225
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106781.patch741
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106782.patch27
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106783.patch62
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106784.patch458
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106785.patch39
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106786.patch94
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106787.patch30
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106789.patch33
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106792.patch61
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106794.patch2648
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106796.patch1255
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106797.patch23
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106798.patch23
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106799.patch75
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106800.patch1270
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106802.patch948
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106803.patch201
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106804.patch38
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106805.patch47
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106806.patch92
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106807.patch767
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106811.patch203
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106814.patch80
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106815.patch528
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106816.patch387
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106817.patch290
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106818.patch105
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106819.patch436
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106820.patch378
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106821.patch240
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106825.patch124
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106826.patch362
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106827.patch622
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106828.patch1951
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106829.patch147
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106830.patch304
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106831.patch123
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106832.patch24
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106833.patch453
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106834.patch1505
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106836.patch61
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106839.patch23
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106840.patch1400
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106841.patch515
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106842.patch375
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106843.patch805
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106844.patch495
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106845.patch1818
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106846.patch487
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106848.patch276
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106853.patch69
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106855.patch22
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106860.patch104
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106861.patch76
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106862.patch45
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106863.patch47
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106864.patch63
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106865.patch25
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106869.patch2389
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106870.patch28
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106872.patch126
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106873.patch80
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106874.patch46
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106876.patch109
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106877.patch239
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106878.patch69
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106879.patch643
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106882.patch53
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/mips64-default-n64.patch32
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/optional_libstdc.patch86
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/powerpc-e5500.patch465
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr32219.patch72
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr46934.patch393
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr47551.patch64
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/use-defaults.h-and-t-oe-in-B.patch80
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/zecke-xgcc-cpp.patch30
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc101
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.6.bb23
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.6.bbappend3
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.6.bb2
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.6.bbappend3
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-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-cross_4.6.bbappend3
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bb2
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-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.6.bb8
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.6.bbappend3
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc_4.6.bb5
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc_4.6.bbappend3
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-rw-r--r--toolchain-layer/recipes-devtools/gcc/libgcc_4.6.bbappend3
163 files changed, 6935 insertions, 46495 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6.inc b/toolchain-layer/recipes-devtools/gcc/gcc-4.6.inc
new file mode 100644
index 000000000..08590673d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6.inc
@@ -0,0 +1,119 @@
1require recipes-devtools/gcc/gcc-common.inc
2
3PR = "r27"
4
5# Third digit in PV should be incremented after a minor release
6# happens from this branch on gcc e.g. currently its 4.6.0
7# when 4.6.1 is releases and we bump SRCREV beyond the release
8# on branch then PV should be incremented to 4.6.1+svnr${SRCPV}
9# to reflect that change
10
11PV = "4.6.3+svnr${SRCPV}"
12
13# BINV should be incremented after updating to a revision
14# after a minor gcc release (e.g. 4.6.1 or 4.6.2) has been made
15# the value will be minor-release+1 e.g. if current minor release was
16# 4.6.1 then the value below will have 2 which will mean 4.6.2
17# which will be next minor release and so on.
18
19BINV = "4.6.4"
20
21SRCREV = "184847"
22BRANCH = "gcc-4_6-branch"
23FILESPATH = "${@base_set_filespath([ '${FILE_DIRNAME}/gcc-4.6' ], d)}"
24
25DEPENDS =+ "mpfr gmp libmpc"
26NATIVEDEPS = "mpfr-native gmp-native libmpc-native zlib-native"
27
28LICENSE="GPL-3.0-with-GCC-exception & GPLv3"
29
30LIC_FILES_CHKSUM = "file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \
31 file://COPYING3;md5=d32239bcb673463ab874e80d47fae504 \
32 file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6 \
33 file://COPYING.LIB;md5=2d5025d4aa3495befef8f17206a5b0a1 \
34 file://COPYING.RUNTIME;md5=fe60d87048567d4fe8c8a0ed2448bcc8"
35
36SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \
37 file://gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch \
38 file://100-uclibc-conf.patch \
39 file://gcc-uclibc-locale-ctype_touplow_t.patch \
40 file://cache-amnesia.patch \
41 file://gcc-flags-for-build.patch \
42 file://103-uclibc-conf-noupstream.patch \
43 file://200-uclibc-locale.patch \
44 file://203-uclibc-locale-no__x.patch; \
45 file://204-uclibc-locale-wchar_fix.patch; \
46 file://205-uclibc-locale-update.patch; \
47 file://301-missing-execinfo_h.patch \
48 file://302-c99-snprintf.patch \
49 file://303-c99-complex-ugly-hack.patch \
50 file://304-index_macro.patch \
51 file://305-libmudflap-susv3-legacy.patch \
52 file://306-libstdc++-namespace.patch \
53 file://740-sh-pr24836.patch \
54 file://800-arm-bigendian.patch \
55 file://904-flatten-switch-stmt-00.patch \
56 file://arm-nolibfloat.patch \
57 file://arm-softfloat.patch \
58 file://zecke-xgcc-cpp.patch \
59 file://gcc-poison-system-directories.patch \
60 file://gcc-poison-dir-extend.patch \
61 file://gcc-4.3.3-SYSROOT_CFLAGS_FOR_TARGET.patch \
62 file://64bithack.patch \
63 file://optional_libstdc.patch \
64 file://disable_relax_pic_calls_flag.patch \
65 file://COLLECT_GCC_OPTIONS.patch \
66 file://use-defaults.h-and-t-oe-in-B.patch \
67 file://powerpc-e5500.patch \
68 file://fix-for-ice-50099.patch \
69 file://gcc-with-linker-hash-style.patch \
70 file://pr46934.patch \
71 file://pr32219.patch \
72 file://pr47551.patch \
73 file://gcc-arm-set-cost.patch \
74 file://GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch \
75 file://fortran-cross-compile-hack.patch \
76 file://cpp-honour-sysroot.patch \
77 file://mips64-default-n64.patch \
78 file://gcc-argument-list-too-long.patch \
79 "
80
81SRC_URI_append_sh3 = " file://sh3-installfix-fixheaders.patch "
82
83#S = "${WORKDIR}/${BRANCH}"
84S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/${BRANCH}"
85B = "${WORKDIR}/${BRANCH}/build.${HOST_SYS}.${TARGET_SYS}"
86
87# Language Overrides
88FORTRAN = ""
89JAVA = ""
90
91EXTRA_OECONF_BASE = " --enable-lto \
92 --enable-libssp \
93 --disable-bootstrap \
94 --disable-libgomp \
95 --disable-libmudflap \
96 --with-system-zlib \
97 --with-linker-hash-style=${LINKER_HASH_STYLE} \
98 --with-ppl=no \
99 --with-cloog=no \
100 --enable-cheaders=c_global "
101
102EXTRA_OECONF_INITIAL = "--disable-libmudflap \
103 --disable-libgomp \
104 --disable-libssp \
105 --disable-libquadmath \
106 --with-system-zlib \
107 --disable-lto \
108 --disable-plugin \
109 --enable-decimal-float=no"
110
111EXTRA_OECONF_INTERMEDIATE = "--disable-libmudflap \
112 --disable-libgomp \
113 --disable-libquadmath \
114 --with-system-zlib \
115 --disable-lto \
116 --disable-plugin \
117 --disable-libssp"
118
119EXTRA_OECONF_append_libc-uclibc = " --disable-decimal-float "
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/100-uclibc-conf.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/100-uclibc-conf.patch
new file mode 100644
index 000000000..b2981e079
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/100-uclibc-conf.patch
@@ -0,0 +1,39 @@
1Upstream-Status: Pending
2
3Index: gcc-4.6.0/contrib/regression/objs-gcc.sh
4===================================================================
5--- gcc-4.6.0.orig/contrib/regression/objs-gcc.sh
6+++ gcc-4.6.0/contrib/regression/objs-gcc.sh
7@@ -106,6 +106,10 @@ if [ $H_REAL_TARGET = $H_REAL_HOST -a $H
8 then
9 make all-gdb all-dejagnu all-ld || exit 1
10 make install-gdb install-dejagnu install-ld || exit 1
11+elif [ $H_REAL_TARGET = $H_REAL_HOST -a $H_REAL_TARGET = i686-pc-linux-uclibc ]
12+ then
13+ make all-gdb all-dejagnu all-ld || exit 1
14+ make install-gdb install-dejagnu install-ld || exit 1
15 elif [ $H_REAL_TARGET = $H_REAL_HOST ] ; then
16 make bootstrap || exit 1
17 make install || exit 1
18Index: gcc-4.6.0/libjava/classpath/ltconfig
19===================================================================
20--- gcc-4.6.0.orig/libjava/classpath/ltconfig
21+++ gcc-4.6.0/libjava/classpath/ltconfig
22@@ -603,7 +603,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)-
23
24 # Transform linux* to *-*-linux-gnu*, to support old configure scripts.
25 case $host_os in
26-linux-gnu*) ;;
27+linux-gnu*|linux-uclibc*) ;;
28 linux*) host=`echo $host | sed 's/^\(.*-.*-linux\)\(.*\)$/\1-gnu\2/'`
29 esac
30
31@@ -1247,7 +1247,7 @@ linux-gnuoldld* | linux-gnuaout* | linux
32 ;;
33
34 # This must be Linux ELF.
35-linux-gnu*)
36+linux*)
37 version_type=linux
38 need_lib_prefix=no
39 need_version=no
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/103-uclibc-conf-noupstream.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/103-uclibc-conf-noupstream.patch
new file mode 100644
index 000000000..22c65806c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/103-uclibc-conf-noupstream.patch
@@ -0,0 +1,17 @@
1Upstream-Status: Pending
2
3Corrects sub machine arch corectly
4
5Index: gcc-4.6.0/gcc/config.gcc
6===================================================================
7--- gcc-4.6.0.orig/gcc/config.gcc
8+++ gcc-4.6.0/gcc/config.gcc
9@@ -2316,7 +2316,7 @@ score-*-elf)
10 ;;
11 sh-*-elf* | sh[12346l]*-*-elf* | \
12 sh-*-symbianelf* | sh[12346l]*-*-symbianelf* | \
13- sh-*-linux* | sh[2346lbe]*-*-linux* | \
14+ sh*-*-linux* | sh[2346lbe]*-*-linux* | \
15 sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
16 sh64-*-netbsd* | sh64l*-*-netbsd*)
17 tmake_file="${tmake_file} sh/t-sh sh/t-elf"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/200-uclibc-locale.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/200-uclibc-locale.patch
new file mode 100644
index 000000000..b8ea78df5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/200-uclibc-locale.patch
@@ -0,0 +1,2842 @@
1Upstream-Status: Pending
2
3Index: gcc-4.6.0/libstdc++-v3/acinclude.m4
4===================================================================
5--- gcc-4.6.0.orig/libstdc++-v3/acinclude.m4
6+++ gcc-4.6.0/libstdc++-v3/acinclude.m4
7@@ -1753,7 +1753,7 @@ dnl
8 AC_DEFUN([GLIBCXX_ENABLE_CLOCALE], [
9 GLIBCXX_ENABLE(clocale,auto,[[[=MODEL]]],
10 [use MODEL for target locale package],
11- [permit generic|gnu|ieee_1003.1-2001|yes|no|auto])
12+ [permit generic|gnu|ieee_1003.1-2001|uclibc|yes|no|auto])
13
14 # Deal with gettext issues. Default to not using it (=no) until we detect
15 # support for it later. Let the user turn it off via --e/d, but let that
16@@ -1774,6 +1774,9 @@ AC_DEFUN([GLIBCXX_ENABLE_CLOCALE], [
17 # Default to "generic".
18 if test $enable_clocale_flag = auto; then
19 case ${target_os} in
20+ *-uclibc*)
21+ enable_clocale_flag=uclibc
22+ ;;
23 linux* | gnu* | kfreebsd*-gnu | knetbsd*-gnu)
24 enable_clocale_flag=gnu
25 ;;
26@@ -1915,6 +1918,40 @@ AC_DEFUN([GLIBCXX_ENABLE_CLOCALE], [
27 CTIME_CC=config/locale/generic/time_members.cc
28 CLOCALE_INTERNAL_H=config/locale/generic/c++locale_internal.h
29 ;;
30+ uclibc)
31+ AC_MSG_RESULT(uclibc)
32+
33+ # Declare intention to use gettext, and add support for specific
34+ # languages.
35+ # For some reason, ALL_LINGUAS has to be before AM-GNU-GETTEXT
36+ ALL_LINGUAS="de fr"
37+
38+ # Don't call AM-GNU-GETTEXT here. Instead, assume glibc.
39+ AC_CHECK_PROG(check_msgfmt, msgfmt, yes, no)
40+ if test x"$check_msgfmt" = x"yes" && test x"$enable_nls" = x"yes"; then
41+ USE_NLS=yes
42+ fi
43+ # Export the build objects.
44+ for ling in $ALL_LINGUAS; do \
45+ glibcxx_MOFILES="$glibcxx_MOFILES $ling.mo"; \
46+ glibcxx_POFILES="$glibcxx_POFILES $ling.po"; \
47+ done
48+ AC_SUBST(glibcxx_MOFILES)
49+ AC_SUBST(glibcxx_POFILES)
50+
51+ CLOCALE_H=config/locale/uclibc/c_locale.h
52+ CLOCALE_CC=config/locale/uclibc/c_locale.cc
53+ CCODECVT_CC=config/locale/uclibc/codecvt_members.cc
54+ CCOLLATE_CC=config/locale/uclibc/collate_members.cc
55+ CCTYPE_CC=config/locale/uclibc/ctype_members.cc
56+ CMESSAGES_H=config/locale/uclibc/messages_members.h
57+ CMESSAGES_CC=config/locale/uclibc/messages_members.cc
58+ CMONEY_CC=config/locale/uclibc/monetary_members.cc
59+ CNUMERIC_CC=config/locale/uclibc/numeric_members.cc
60+ CTIME_H=config/locale/uclibc/time_members.h
61+ CTIME_CC=config/locale/uclibc/time_members.cc
62+ CLOCALE_INTERNAL_H=config/locale/uclibc/c++locale_internal.h
63+ ;;
64 esac
65
66 # This is where the testsuite looks for locale catalogs, using the
67Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c++locale_internal.h
68===================================================================
69--- /dev/null
70+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c++locale_internal.h
71@@ -0,0 +1,63 @@
72+// Prototypes for GLIBC thread locale __-prefixed functions -*- C++ -*-
73+
74+// Copyright (C) 2002, 2004, 2005 Free Software Foundation, Inc.
75+//
76+// This file is part of the GNU ISO C++ Library. This library is free
77+// software; you can redistribute it and/or modify it under the
78+// terms of the GNU General Public License as published by the
79+// Free Software Foundation; either version 2, or (at your option)
80+// any later version.
81+
82+// This library is distributed in the hope that it will be useful,
83+// but WITHOUT ANY WARRANTY; without even the implied warranty of
84+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
85+// GNU General Public License for more details.
86+
87+// You should have received a copy of the GNU General Public License along
88+// with this library; see the file COPYING. If not, write to the Free
89+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
90+// USA.
91+
92+// As a special exception, you may use this file as part of a free software
93+// library without restriction. Specifically, if other files instantiate
94+// templates or use macros or inline functions from this file, or you compile
95+// this file and link it with other files to produce an executable, this
96+// file does not by itself cause the resulting executable to be covered by
97+// the GNU General Public License. This exception does not however
98+// invalidate any other reasons why the executable file might be covered by
99+// the GNU General Public License.
100+
101+// Written by Jakub Jelinek <jakub@redhat.com>
102+
103+#include <bits/c++config.h>
104+#include <clocale>
105+
106+#ifdef __UCLIBC_MJN3_ONLY__
107+#warning clean this up
108+#endif
109+
110+#ifdef __UCLIBC_HAS_XLOCALE__
111+
112+extern "C" __typeof(nl_langinfo_l) __nl_langinfo_l;
113+extern "C" __typeof(strcoll_l) __strcoll_l;
114+extern "C" __typeof(strftime_l) __strftime_l;
115+extern "C" __typeof(strtod_l) __strtod_l;
116+extern "C" __typeof(strtof_l) __strtof_l;
117+extern "C" __typeof(strtold_l) __strtold_l;
118+extern "C" __typeof(strxfrm_l) __strxfrm_l;
119+extern "C" __typeof(newlocale) __newlocale;
120+extern "C" __typeof(freelocale) __freelocale;
121+extern "C" __typeof(duplocale) __duplocale;
122+extern "C" __typeof(uselocale) __uselocale;
123+
124+#ifdef _GLIBCXX_USE_WCHAR_T
125+extern "C" __typeof(iswctype_l) __iswctype_l;
126+extern "C" __typeof(towlower_l) __towlower_l;
127+extern "C" __typeof(towupper_l) __towupper_l;
128+extern "C" __typeof(wcscoll_l) __wcscoll_l;
129+extern "C" __typeof(wcsftime_l) __wcsftime_l;
130+extern "C" __typeof(wcsxfrm_l) __wcsxfrm_l;
131+extern "C" __typeof(wctype_l) __wctype_l;
132+#endif
133+
134+#endif // GLIBC 2.3 and later
135Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c_locale.cc
136===================================================================
137--- /dev/null
138+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c_locale.cc
139@@ -0,0 +1,160 @@
140+// Wrapper for underlying C-language localization -*- C++ -*-
141+
142+// Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc.
143+//
144+// This file is part of the GNU ISO C++ Library. This library is free
145+// software; you can redistribute it and/or modify it under the
146+// terms of the GNU General Public License as published by the
147+// Free Software Foundation; either version 2, or (at your option)
148+// any later version.
149+
150+// This library is distributed in the hope that it will be useful,
151+// but WITHOUT ANY WARRANTY; without even the implied warranty of
152+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
153+// GNU General Public License for more details.
154+
155+// You should have received a copy of the GNU General Public License along
156+// with this library; see the file COPYING. If not, write to the Free
157+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
158+// USA.
159+
160+// As a special exception, you may use this file as part of a free software
161+// library without restriction. Specifically, if other files instantiate
162+// templates or use macros or inline functions from this file, or you compile
163+// this file and link it with other files to produce an executable, this
164+// file does not by itself cause the resulting executable to be covered by
165+// the GNU General Public License. This exception does not however
166+// invalidate any other reasons why the executable file might be covered by
167+// the GNU General Public License.
168+
169+//
170+// ISO C++ 14882: 22.8 Standard locale categories.
171+//
172+
173+// Written by Benjamin Kosnik <bkoz@redhat.com>
174+
175+#include <cerrno> // For errno
176+#include <locale>
177+#include <stdexcept>
178+#include <langinfo.h>
179+#include <bits/c++locale_internal.h>
180+
181+#ifndef __UCLIBC_HAS_XLOCALE__
182+#define __strtol_l(S, E, B, L) strtol((S), (E), (B))
183+#define __strtoul_l(S, E, B, L) strtoul((S), (E), (B))
184+#define __strtoll_l(S, E, B, L) strtoll((S), (E), (B))
185+#define __strtoull_l(S, E, B, L) strtoull((S), (E), (B))
186+#define __strtof_l(S, E, L) strtof((S), (E))
187+#define __strtod_l(S, E, L) strtod((S), (E))
188+#define __strtold_l(S, E, L) strtold((S), (E))
189+#warning should dummy __newlocale check for C|POSIX ?
190+#define __newlocale(a, b, c) NULL
191+#define __freelocale(a) ((void)0)
192+#define __duplocale(a) __c_locale()
193+#endif
194+
195+namespace std
196+{
197+ template<>
198+ void
199+ __convert_to_v(const char* __s, float& __v, ios_base::iostate& __err,
200+ const __c_locale& __cloc)
201+ {
202+ if (!(__err & ios_base::failbit))
203+ {
204+ char* __sanity;
205+ errno = 0;
206+ float __f = __strtof_l(__s, &__sanity, __cloc);
207+ if (__sanity != __s && errno != ERANGE)
208+ __v = __f;
209+ else
210+ __err |= ios_base::failbit;
211+ }
212+ }
213+
214+ template<>
215+ void
216+ __convert_to_v(const char* __s, double& __v, ios_base::iostate& __err,
217+ const __c_locale& __cloc)
218+ {
219+ if (!(__err & ios_base::failbit))
220+ {
221+ char* __sanity;
222+ errno = 0;
223+ double __d = __strtod_l(__s, &__sanity, __cloc);
224+ if (__sanity != __s && errno != ERANGE)
225+ __v = __d;
226+ else
227+ __err |= ios_base::failbit;
228+ }
229+ }
230+
231+ template<>
232+ void
233+ __convert_to_v(const char* __s, long double& __v, ios_base::iostate& __err,
234+ const __c_locale& __cloc)
235+ {
236+ if (!(__err & ios_base::failbit))
237+ {
238+ char* __sanity;
239+ errno = 0;
240+ long double __ld = __strtold_l(__s, &__sanity, __cloc);
241+ if (__sanity != __s && errno != ERANGE)
242+ __v = __ld;
243+ else
244+ __err |= ios_base::failbit;
245+ }
246+ }
247+
248+ void
249+ locale::facet::_S_create_c_locale(__c_locale& __cloc, const char* __s,
250+ __c_locale __old)
251+ {
252+ __cloc = __newlocale(1 << LC_ALL, __s, __old);
253+#ifdef __UCLIBC_HAS_XLOCALE__
254+ if (!__cloc)
255+ {
256+ // This named locale is not supported by the underlying OS.
257+ __throw_runtime_error(__N("locale::facet::_S_create_c_locale "
258+ "name not valid"));
259+ }
260+#endif
261+ }
262+
263+ void
264+ locale::facet::_S_destroy_c_locale(__c_locale& __cloc)
265+ {
266+ if (_S_get_c_locale() != __cloc)
267+ __freelocale(__cloc);
268+ }
269+
270+ __c_locale
271+ locale::facet::_S_clone_c_locale(__c_locale& __cloc)
272+ { return __duplocale(__cloc); }
273+} // namespace std
274+
275+namespace __gnu_cxx
276+{
277+ const char* const category_names[6 + _GLIBCXX_NUM_CATEGORIES] =
278+ {
279+ "LC_CTYPE",
280+ "LC_NUMERIC",
281+ "LC_TIME",
282+ "LC_COLLATE",
283+ "LC_MONETARY",
284+ "LC_MESSAGES",
285+#if _GLIBCXX_NUM_CATEGORIES != 0
286+ "LC_PAPER",
287+ "LC_NAME",
288+ "LC_ADDRESS",
289+ "LC_TELEPHONE",
290+ "LC_MEASUREMENT",
291+ "LC_IDENTIFICATION"
292+#endif
293+ };
294+}
295+
296+namespace std
297+{
298+ const char* const* const locale::_S_categories = __gnu_cxx::category_names;
299+} // namespace std
300Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c_locale.h
301===================================================================
302--- /dev/null
303+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c_locale.h
304@@ -0,0 +1,117 @@
305+// Wrapper for underlying C-language localization -*- C++ -*-
306+
307+// Copyright (C) 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
308+//
309+// This file is part of the GNU ISO C++ Library. This library is free
310+// software; you can redistribute it and/or modify it under the
311+// terms of the GNU General Public License as published by the
312+// Free Software Foundation; either version 2, or (at your option)
313+// any later version.
314+
315+// This library is distributed in the hope that it will be useful,
316+// but WITHOUT ANY WARRANTY; without even the implied warranty of
317+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
318+// GNU General Public License for more details.
319+
320+// You should have received a copy of the GNU General Public License along
321+// with this library; see the file COPYING. If not, write to the Free
322+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
323+// USA.
324+
325+// As a special exception, you may use this file as part of a free software
326+// library without restriction. Specifically, if other files instantiate
327+// templates or use macros or inline functions from this file, or you compile
328+// this file and link it with other files to produce an executable, this
329+// file does not by itself cause the resulting executable to be covered by
330+// the GNU General Public License. This exception does not however
331+// invalidate any other reasons why the executable file might be covered by
332+// the GNU General Public License.
333+
334+//
335+// ISO C++ 14882: 22.8 Standard locale categories.
336+//
337+
338+// Written by Benjamin Kosnik <bkoz@redhat.com>
339+
340+#ifndef _C_LOCALE_H
341+#define _C_LOCALE_H 1
342+
343+#pragma GCC system_header
344+
345+#include <cstring> // get std::strlen
346+#include <cstdio> // get std::snprintf or std::sprintf
347+#include <clocale>
348+#include <langinfo.h> // For codecvt
349+#ifdef __UCLIBC_MJN3_ONLY__
350+#warning fix this
351+#endif
352+#ifdef __UCLIBC_HAS_LOCALE__
353+#include <iconv.h> // For codecvt using iconv, iconv_t
354+#endif
355+#ifdef __UCLIBC_HAS_GETTEXT_AWARENESS__
356+#include <libintl.h> // For messages
357+#endif
358+
359+#ifdef __UCLIBC_MJN3_ONLY__
360+#warning what is _GLIBCXX_C_LOCALE_GNU for
361+#endif
362+#define _GLIBCXX_C_LOCALE_GNU 1
363+
364+#ifdef __UCLIBC_MJN3_ONLY__
365+#warning fix categories
366+#endif
367+// #define _GLIBCXX_NUM_CATEGORIES 6
368+#define _GLIBCXX_NUM_CATEGORIES 0
369+
370+#ifdef __UCLIBC_HAS_XLOCALE__
371+namespace __gnu_cxx
372+{
373+ extern "C" __typeof(uselocale) __uselocale;
374+}
375+#endif
376+
377+namespace std
378+{
379+#ifdef __UCLIBC_HAS_XLOCALE__
380+ typedef __locale_t __c_locale;
381+#else
382+ typedef int* __c_locale;
383+#endif
384+
385+ // Convert numeric value of type _Tv to string and return length of
386+ // string. If snprintf is available use it, otherwise fall back to
387+ // the unsafe sprintf which, in general, can be dangerous and should
388+ // be avoided.
389+ template<typename _Tv>
390+ int
391+ __convert_from_v(char* __out,
392+ const int __size __attribute__ ((__unused__)),
393+ const char* __fmt,
394+#ifdef __UCLIBC_HAS_XCLOCALE__
395+ _Tv __v, const __c_locale& __cloc, int __prec)
396+ {
397+ __c_locale __old = __gnu_cxx::__uselocale(__cloc);
398+#else
399+ _Tv __v, const __c_locale&, int __prec)
400+ {
401+# ifdef __UCLIBC_HAS_LOCALE__
402+ char* __old = std::setlocale(LC_ALL, NULL);
403+ char* __sav = new char[std::strlen(__old) + 1];
404+ std::strcpy(__sav, __old);
405+ std::setlocale(LC_ALL, "C");
406+# endif
407+#endif
408+
409+ const int __ret = std::snprintf(__out, __size, __fmt, __prec, __v);
410+
411+#ifdef __UCLIBC_HAS_XCLOCALE__
412+ __gnu_cxx::__uselocale(__old);
413+#elif defined __UCLIBC_HAS_LOCALE__
414+ std::setlocale(LC_ALL, __sav);
415+ delete [] __sav;
416+#endif
417+ return __ret;
418+ }
419+}
420+
421+#endif
422Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/codecvt_members.cc
423===================================================================
424--- /dev/null
425+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/codecvt_members.cc
426@@ -0,0 +1,308 @@
427+// std::codecvt implementation details, GNU version -*- C++ -*-
428+
429+// Copyright (C) 2002, 2003 Free Software Foundation, Inc.
430+//
431+// This file is part of the GNU ISO C++ Library. This library is free
432+// software; you can redistribute it and/or modify it under the
433+// terms of the GNU General Public License as published by the
434+// Free Software Foundation; either version 2, or (at your option)
435+// any later version.
436+
437+// This library is distributed in the hope that it will be useful,
438+// but WITHOUT ANY WARRANTY; without even the implied warranty of
439+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
440+// GNU General Public License for more details.
441+
442+// You should have received a copy of the GNU General Public License along
443+// with this library; see the file COPYING. If not, write to the Free
444+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
445+// USA.
446+
447+// As a special exception, you may use this file as part of a free software
448+// library without restriction. Specifically, if other files instantiate
449+// templates or use macros or inline functions from this file, or you compile
450+// this file and link it with other files to produce an executable, this
451+// file does not by itself cause the resulting executable to be covered by
452+// the GNU General Public License. This exception does not however
453+// invalidate any other reasons why the executable file might be covered by
454+// the GNU General Public License.
455+
456+//
457+// ISO C++ 14882: 22.2.1.5 - Template class codecvt
458+//
459+
460+// Written by Benjamin Kosnik <bkoz@redhat.com>
461+
462+#include <locale>
463+#include <cstdlib> // For MB_CUR_MAX
464+#include <climits> // For MB_LEN_MAX
465+#include <bits/c++locale_internal.h>
466+
467+namespace std
468+{
469+ // Specializations.
470+#ifdef _GLIBCXX_USE_WCHAR_T
471+ codecvt_base::result
472+ codecvt<wchar_t, char, mbstate_t>::
473+ do_out(state_type& __state, const intern_type* __from,
474+ const intern_type* __from_end, const intern_type*& __from_next,
475+ extern_type* __to, extern_type* __to_end,
476+ extern_type*& __to_next) const
477+ {
478+ result __ret = ok;
479+ state_type __tmp_state(__state);
480+
481+#ifdef __UCLIBC_HAS_XLOCALE__
482+ __c_locale __old = __uselocale(_M_c_locale_codecvt);
483+#endif
484+
485+ // wcsnrtombs is *very* fast but stops if encounters NUL characters:
486+ // in case we fall back to wcrtomb and then continue, in a loop.
487+ // NB: wcsnrtombs is a GNU extension
488+ for (__from_next = __from, __to_next = __to;
489+ __from_next < __from_end && __to_next < __to_end
490+ && __ret == ok;)
491+ {
492+ const intern_type* __from_chunk_end = wmemchr(__from_next, L'\0',
493+ __from_end - __from_next);
494+ if (!__from_chunk_end)
495+ __from_chunk_end = __from_end;
496+
497+ __from = __from_next;
498+ const size_t __conv = wcsnrtombs(__to_next, &__from_next,
499+ __from_chunk_end - __from_next,
500+ __to_end - __to_next, &__state);
501+ if (__conv == static_cast<size_t>(-1))
502+ {
503+ // In case of error, in order to stop at the exact place we
504+ // have to start again from the beginning with a series of
505+ // wcrtomb.
506+ for (; __from < __from_next; ++__from)
507+ __to_next += wcrtomb(__to_next, *__from, &__tmp_state);
508+ __state = __tmp_state;
509+ __ret = error;
510+ }
511+ else if (__from_next && __from_next < __from_chunk_end)
512+ {
513+ __to_next += __conv;
514+ __ret = partial;
515+ }
516+ else
517+ {
518+ __from_next = __from_chunk_end;
519+ __to_next += __conv;
520+ }
521+
522+ if (__from_next < __from_end && __ret == ok)
523+ {
524+ extern_type __buf[MB_LEN_MAX];
525+ __tmp_state = __state;
526+ const size_t __conv = wcrtomb(__buf, *__from_next, &__tmp_state);
527+ if (__conv > static_cast<size_t>(__to_end - __to_next))
528+ __ret = partial;
529+ else
530+ {
531+ memcpy(__to_next, __buf, __conv);
532+ __state = __tmp_state;
533+ __to_next += __conv;
534+ ++__from_next;
535+ }
536+ }
537+ }
538+
539+#ifdef __UCLIBC_HAS_XLOCALE__
540+ __uselocale(__old);
541+#endif
542+
543+ return __ret;
544+ }
545+
546+ codecvt_base::result
547+ codecvt<wchar_t, char, mbstate_t>::
548+ do_in(state_type& __state, const extern_type* __from,
549+ const extern_type* __from_end, const extern_type*& __from_next,
550+ intern_type* __to, intern_type* __to_end,
551+ intern_type*& __to_next) const
552+ {
553+ result __ret = ok;
554+ state_type __tmp_state(__state);
555+
556+#ifdef __UCLIBC_HAS_XLOCALE__
557+ __c_locale __old = __uselocale(_M_c_locale_codecvt);
558+#endif
559+
560+ // mbsnrtowcs is *very* fast but stops if encounters NUL characters:
561+ // in case we store a L'\0' and then continue, in a loop.
562+ // NB: mbsnrtowcs is a GNU extension
563+ for (__from_next = __from, __to_next = __to;
564+ __from_next < __from_end && __to_next < __to_end
565+ && __ret == ok;)
566+ {
567+ const extern_type* __from_chunk_end;
568+ __from_chunk_end = static_cast<const extern_type*>(memchr(__from_next, '\0',
569+ __from_end
570+ - __from_next));
571+ if (!__from_chunk_end)
572+ __from_chunk_end = __from_end;
573+
574+ __from = __from_next;
575+ size_t __conv = mbsnrtowcs(__to_next, &__from_next,
576+ __from_chunk_end - __from_next,
577+ __to_end - __to_next, &__state);
578+ if (__conv == static_cast<size_t>(-1))
579+ {
580+ // In case of error, in order to stop at the exact place we
581+ // have to start again from the beginning with a series of
582+ // mbrtowc.
583+ for (;; ++__to_next, __from += __conv)
584+ {
585+ __conv = mbrtowc(__to_next, __from, __from_end - __from,
586+ &__tmp_state);
587+ if (__conv == static_cast<size_t>(-1)
588+ || __conv == static_cast<size_t>(-2))
589+ break;
590+ }
591+ __from_next = __from;
592+ __state = __tmp_state;
593+ __ret = error;
594+ }
595+ else if (__from_next && __from_next < __from_chunk_end)
596+ {
597+ // It is unclear what to return in this case (see DR 382).
598+ __to_next += __conv;
599+ __ret = partial;
600+ }
601+ else
602+ {
603+ __from_next = __from_chunk_end;
604+ __to_next += __conv;
605+ }
606+
607+ if (__from_next < __from_end && __ret == ok)
608+ {
609+ if (__to_next < __to_end)
610+ {
611+ // XXX Probably wrong for stateful encodings
612+ __tmp_state = __state;
613+ ++__from_next;
614+ *__to_next++ = L'\0';
615+ }
616+ else
617+ __ret = partial;
618+ }
619+ }
620+
621+#ifdef __UCLIBC_HAS_XLOCALE__
622+ __uselocale(__old);
623+#endif
624+
625+ return __ret;
626+ }
627+
628+ int
629+ codecvt<wchar_t, char, mbstate_t>::
630+ do_encoding() const throw()
631+ {
632+ // XXX This implementation assumes that the encoding is
633+ // stateless and is either single-byte or variable-width.
634+ int __ret = 0;
635+#ifdef __UCLIBC_HAS_XLOCALE__
636+ __c_locale __old = __uselocale(_M_c_locale_codecvt);
637+#endif
638+ if (MB_CUR_MAX == 1)
639+ __ret = 1;
640+#ifdef __UCLIBC_HAS_XLOCALE__
641+ __uselocale(__old);
642+#endif
643+ return __ret;
644+ }
645+
646+ int
647+ codecvt<wchar_t, char, mbstate_t>::
648+ do_max_length() const throw()
649+ {
650+#ifdef __UCLIBC_HAS_XLOCALE__
651+ __c_locale __old = __uselocale(_M_c_locale_codecvt);
652+#endif
653+ // XXX Probably wrong for stateful encodings.
654+ int __ret = MB_CUR_MAX;
655+#ifdef __UCLIBC_HAS_XLOCALE__
656+ __uselocale(__old);
657+#endif
658+ return __ret;
659+ }
660+
661+ int
662+ codecvt<wchar_t, char, mbstate_t>::
663+ do_length(state_type& __state, const extern_type* __from,
664+ const extern_type* __end, size_t __max) const
665+ {
666+ int __ret = 0;
667+ state_type __tmp_state(__state);
668+
669+#ifdef __UCLIBC_HAS_XLOCALE__
670+ __c_locale __old = __uselocale(_M_c_locale_codecvt);
671+#endif
672+
673+ // mbsnrtowcs is *very* fast but stops if encounters NUL characters:
674+ // in case we advance past it and then continue, in a loop.
675+ // NB: mbsnrtowcs is a GNU extension
676+
677+ // A dummy internal buffer is needed in order for mbsnrtocws to consider
678+ // its fourth parameter (it wouldn't with NULL as first parameter).
679+ wchar_t* __to = static_cast<wchar_t*>(__builtin_alloca(sizeof(wchar_t)
680+ * __max));
681+ while (__from < __end && __max)
682+ {
683+ const extern_type* __from_chunk_end;
684+ __from_chunk_end = static_cast<const extern_type*>(memchr(__from, '\0',
685+ __end
686+ - __from));
687+ if (!__from_chunk_end)
688+ __from_chunk_end = __end;
689+
690+ const extern_type* __tmp_from = __from;
691+ size_t __conv = mbsnrtowcs(__to, &__from,
692+ __from_chunk_end - __from,
693+ __max, &__state);
694+ if (__conv == static_cast<size_t>(-1))
695+ {
696+ // In case of error, in order to stop at the exact place we
697+ // have to start again from the beginning with a series of
698+ // mbrtowc.
699+ for (__from = __tmp_from;; __from += __conv)
700+ {
701+ __conv = mbrtowc(NULL, __from, __end - __from,
702+ &__tmp_state);
703+ if (__conv == static_cast<size_t>(-1)
704+ || __conv == static_cast<size_t>(-2))
705+ break;
706+ }
707+ __state = __tmp_state;
708+ __ret += __from - __tmp_from;
709+ break;
710+ }
711+ if (!__from)
712+ __from = __from_chunk_end;
713+
714+ __ret += __from - __tmp_from;
715+ __max -= __conv;
716+
717+ if (__from < __end && __max)
718+ {
719+ // XXX Probably wrong for stateful encodings
720+ __tmp_state = __state;
721+ ++__from;
722+ ++__ret;
723+ --__max;
724+ }
725+ }
726+
727+#ifdef __UCLIBC_HAS_XLOCALE__
728+ __uselocale(__old);
729+#endif
730+
731+ return __ret;
732+ }
733+#endif
734+}
735Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/collate_members.cc
736===================================================================
737--- /dev/null
738+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/collate_members.cc
739@@ -0,0 +1,80 @@
740+// std::collate implementation details, GNU version -*- C++ -*-
741+
742+// Copyright (C) 2001, 2002 Free Software Foundation, Inc.
743+//
744+// This file is part of the GNU ISO C++ Library. This library is free
745+// software; you can redistribute it and/or modify it under the
746+// terms of the GNU General Public License as published by the
747+// Free Software Foundation; either version 2, or (at your option)
748+// any later version.
749+
750+// This library is distributed in the hope that it will be useful,
751+// but WITHOUT ANY WARRANTY; without even the implied warranty of
752+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
753+// GNU General Public License for more details.
754+
755+// You should have received a copy of the GNU General Public License along
756+// with this library; see the file COPYING. If not, write to the Free
757+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
758+// USA.
759+
760+// As a special exception, you may use this file as part of a free software
761+// library without restriction. Specifically, if other files instantiate
762+// templates or use macros or inline functions from this file, or you compile
763+// this file and link it with other files to produce an executable, this
764+// file does not by itself cause the resulting executable to be covered by
765+// the GNU General Public License. This exception does not however
766+// invalidate any other reasons why the executable file might be covered by
767+// the GNU General Public License.
768+
769+//
770+// ISO C++ 14882: 22.2.4.1.2 collate virtual functions
771+//
772+
773+// Written by Benjamin Kosnik <bkoz@redhat.com>
774+
775+#include <locale>
776+#include <bits/c++locale_internal.h>
777+
778+#ifndef __UCLIBC_HAS_XLOCALE__
779+#define __strcoll_l(S1, S2, L) strcoll((S1), (S2))
780+#define __strxfrm_l(S1, S2, N, L) strxfrm((S1), (S2), (N))
781+#define __wcscoll_l(S1, S2, L) wcscoll((S1), (S2))
782+#define __wcsxfrm_l(S1, S2, N, L) wcsxfrm((S1), (S2), (N))
783+#endif
784+
785+namespace std
786+{
787+ // These are basically extensions to char_traits, and perhaps should
788+ // be put there instead of here.
789+ template<>
790+ int
791+ collate<char>::_M_compare(const char* __one, const char* __two) const
792+ {
793+ int __cmp = __strcoll_l(__one, __two, _M_c_locale_collate);
794+ return (__cmp >> (8 * sizeof (int) - 2)) | (__cmp != 0);
795+ }
796+
797+ template<>
798+ size_t
799+ collate<char>::_M_transform(char* __to, const char* __from,
800+ size_t __n) const
801+ { return __strxfrm_l(__to, __from, __n, _M_c_locale_collate); }
802+
803+#ifdef _GLIBCXX_USE_WCHAR_T
804+ template<>
805+ int
806+ collate<wchar_t>::_M_compare(const wchar_t* __one,
807+ const wchar_t* __two) const
808+ {
809+ int __cmp = __wcscoll_l(__one, __two, _M_c_locale_collate);
810+ return (__cmp >> (8 * sizeof (int) - 2)) | (__cmp != 0);
811+ }
812+
813+ template<>
814+ size_t
815+ collate<wchar_t>::_M_transform(wchar_t* __to, const wchar_t* __from,
816+ size_t __n) const
817+ { return __wcsxfrm_l(__to, __from, __n, _M_c_locale_collate); }
818+#endif
819+}
820Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/ctype_members.cc
821===================================================================
822--- /dev/null
823+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/ctype_members.cc
824@@ -0,0 +1,300 @@
825+// std::ctype implementation details, GNU version -*- C++ -*-
826+
827+// Copyright (C) 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
828+//
829+// This file is part of the GNU ISO C++ Library. This library is free
830+// software; you can redistribute it and/or modify it under the
831+// terms of the GNU General Public License as published by the
832+// Free Software Foundation; either version 2, or (at your option)
833+// any later version.
834+
835+// This library is distributed in the hope that it will be useful,
836+// but WITHOUT ANY WARRANTY; without even the implied warranty of
837+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
838+// GNU General Public License for more details.
839+
840+// You should have received a copy of the GNU General Public License along
841+// with this library; see the file COPYING. If not, write to the Free
842+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
843+// USA.
844+
845+// As a special exception, you may use this file as part of a free software
846+// library without restriction. Specifically, if other files instantiate
847+// templates or use macros or inline functions from this file, or you compile
848+// this file and link it with other files to produce an executable, this
849+// file does not by itself cause the resulting executable to be covered by
850+// the GNU General Public License. This exception does not however
851+// invalidate any other reasons why the executable file might be covered by
852+// the GNU General Public License.
853+
854+//
855+// ISO C++ 14882: 22.2.1.1.2 ctype virtual functions.
856+//
857+
858+// Written by Benjamin Kosnik <bkoz@redhat.com>
859+
860+#define _LIBC
861+#include <locale>
862+#undef _LIBC
863+#include <bits/c++locale_internal.h>
864+
865+#ifndef __UCLIBC_HAS_XLOCALE__
866+#define __wctype_l(S, L) wctype((S))
867+#define __towupper_l(C, L) towupper((C))
868+#define __towlower_l(C, L) towlower((C))
869+#define __iswctype_l(C, M, L) iswctype((C), (M))
870+#endif
871+
872+namespace std
873+{
874+ // NB: The other ctype<char> specializations are in src/locale.cc and
875+ // various /config/os/* files.
876+ template<>
877+ ctype_byname<char>::ctype_byname(const char* __s, size_t __refs)
878+ : ctype<char>(0, false, __refs)
879+ {
880+ if (std::strcmp(__s, "C") != 0 && std::strcmp(__s, "POSIX") != 0)
881+ {
882+ this->_S_destroy_c_locale(this->_M_c_locale_ctype);
883+ this->_S_create_c_locale(this->_M_c_locale_ctype, __s);
884+#ifdef __UCLIBC_HAS_XLOCALE__
885+ this->_M_toupper = this->_M_c_locale_ctype->__ctype_toupper;
886+ this->_M_tolower = this->_M_c_locale_ctype->__ctype_tolower;
887+ this->_M_table = this->_M_c_locale_ctype->__ctype_b;
888+#endif
889+ }
890+ }
891+
892+#ifdef _GLIBCXX_USE_WCHAR_T
893+ ctype<wchar_t>::__wmask_type
894+ ctype<wchar_t>::_M_convert_to_wmask(const mask __m) const
895+ {
896+ __wmask_type __ret;
897+ switch (__m)
898+ {
899+ case space:
900+ __ret = __wctype_l("space", _M_c_locale_ctype);
901+ break;
902+ case print:
903+ __ret = __wctype_l("print", _M_c_locale_ctype);
904+ break;
905+ case cntrl:
906+ __ret = __wctype_l("cntrl", _M_c_locale_ctype);
907+ break;
908+ case upper:
909+ __ret = __wctype_l("upper", _M_c_locale_ctype);
910+ break;
911+ case lower:
912+ __ret = __wctype_l("lower", _M_c_locale_ctype);
913+ break;
914+ case alpha:
915+ __ret = __wctype_l("alpha", _M_c_locale_ctype);
916+ break;
917+ case digit:
918+ __ret = __wctype_l("digit", _M_c_locale_ctype);
919+ break;
920+ case punct:
921+ __ret = __wctype_l("punct", _M_c_locale_ctype);
922+ break;
923+ case xdigit:
924+ __ret = __wctype_l("xdigit", _M_c_locale_ctype);
925+ break;
926+ case alnum:
927+ __ret = __wctype_l("alnum", _M_c_locale_ctype);
928+ break;
929+ case graph:
930+ __ret = __wctype_l("graph", _M_c_locale_ctype);
931+ break;
932+ default:
933+ __ret = __wmask_type();
934+ }
935+ return __ret;
936+ }
937+
938+ wchar_t
939+ ctype<wchar_t>::do_toupper(wchar_t __c) const
940+ { return __towupper_l(__c, _M_c_locale_ctype); }
941+
942+ const wchar_t*
943+ ctype<wchar_t>::do_toupper(wchar_t* __lo, const wchar_t* __hi) const
944+ {
945+ while (__lo < __hi)
946+ {
947+ *__lo = __towupper_l(*__lo, _M_c_locale_ctype);
948+ ++__lo;
949+ }
950+ return __hi;
951+ }
952+
953+ wchar_t
954+ ctype<wchar_t>::do_tolower(wchar_t __c) const
955+ { return __towlower_l(__c, _M_c_locale_ctype); }
956+
957+ const wchar_t*
958+ ctype<wchar_t>::do_tolower(wchar_t* __lo, const wchar_t* __hi) const
959+ {
960+ while (__lo < __hi)
961+ {
962+ *__lo = __towlower_l(*__lo, _M_c_locale_ctype);
963+ ++__lo;
964+ }
965+ return __hi;
966+ }
967+
968+ bool
969+ ctype<wchar_t>::
970+ do_is(mask __m, wchar_t __c) const
971+ {
972+ // Highest bitmask in ctype_base == 10, but extra in "C"
973+ // library for blank.
974+ bool __ret = false;
975+ const size_t __bitmasksize = 11;
976+ for (size_t __bitcur = 0; __bitcur <= __bitmasksize; ++__bitcur)
977+ if (__m & _M_bit[__bitcur]
978+ && __iswctype_l(__c, _M_wmask[__bitcur], _M_c_locale_ctype))
979+ {
980+ __ret = true;
981+ break;
982+ }
983+ return __ret;
984+ }
985+
986+ const wchar_t*
987+ ctype<wchar_t>::
988+ do_is(const wchar_t* __lo, const wchar_t* __hi, mask* __vec) const
989+ {
990+ for (; __lo < __hi; ++__vec, ++__lo)
991+ {
992+ // Highest bitmask in ctype_base == 10, but extra in "C"
993+ // library for blank.
994+ const size_t __bitmasksize = 11;
995+ mask __m = 0;
996+ for (size_t __bitcur = 0; __bitcur <= __bitmasksize; ++__bitcur)
997+ if (__iswctype_l(*__lo, _M_wmask[__bitcur], _M_c_locale_ctype))
998+ __m |= _M_bit[__bitcur];
999+ *__vec = __m;
1000+ }
1001+ return __hi;
1002+ }
1003+
1004+ const wchar_t*
1005+ ctype<wchar_t>::
1006+ do_scan_is(mask __m, const wchar_t* __lo, const wchar_t* __hi) const
1007+ {
1008+ while (__lo < __hi && !this->do_is(__m, *__lo))
1009+ ++__lo;
1010+ return __lo;
1011+ }
1012+
1013+ const wchar_t*
1014+ ctype<wchar_t>::
1015+ do_scan_not(mask __m, const char_type* __lo, const char_type* __hi) const
1016+ {
1017+ while (__lo < __hi && this->do_is(__m, *__lo) != 0)
1018+ ++__lo;
1019+ return __lo;
1020+ }
1021+
1022+ wchar_t
1023+ ctype<wchar_t>::
1024+ do_widen(char __c) const
1025+ { return _M_widen[static_cast<unsigned char>(__c)]; }
1026+
1027+ const char*
1028+ ctype<wchar_t>::
1029+ do_widen(const char* __lo, const char* __hi, wchar_t* __dest) const
1030+ {
1031+ while (__lo < __hi)
1032+ {
1033+ *__dest = _M_widen[static_cast<unsigned char>(*__lo)];
1034+ ++__lo;
1035+ ++__dest;
1036+ }
1037+ return __hi;
1038+ }
1039+
1040+ char
1041+ ctype<wchar_t>::
1042+ do_narrow(wchar_t __wc, char __dfault) const
1043+ {
1044+ if (__wc >= 0 && __wc < 128 && _M_narrow_ok)
1045+ return _M_narrow[__wc];
1046+#ifdef __UCLIBC_HAS_XLOCALE__
1047+ __c_locale __old = __uselocale(_M_c_locale_ctype);
1048+#endif
1049+ const int __c = wctob(__wc);
1050+#ifdef __UCLIBC_HAS_XLOCALE__
1051+ __uselocale(__old);
1052+#endif
1053+ return (__c == EOF ? __dfault : static_cast<char>(__c));
1054+ }
1055+
1056+ const wchar_t*
1057+ ctype<wchar_t>::
1058+ do_narrow(const wchar_t* __lo, const wchar_t* __hi, char __dfault,
1059+ char* __dest) const
1060+ {
1061+#ifdef __UCLIBC_HAS_XLOCALE__
1062+ __c_locale __old = __uselocale(_M_c_locale_ctype);
1063+#endif
1064+ if (_M_narrow_ok)
1065+ while (__lo < __hi)
1066+ {
1067+ if (*__lo >= 0 && *__lo < 128)
1068+ *__dest = _M_narrow[*__lo];
1069+ else
1070+ {
1071+ const int __c = wctob(*__lo);
1072+ *__dest = (__c == EOF ? __dfault : static_cast<char>(__c));
1073+ }
1074+ ++__lo;
1075+ ++__dest;
1076+ }
1077+ else
1078+ while (__lo < __hi)
1079+ {
1080+ const int __c = wctob(*__lo);
1081+ *__dest = (__c == EOF ? __dfault : static_cast<char>(__c));
1082+ ++__lo;
1083+ ++__dest;
1084+ }
1085+#ifdef __UCLIBC_HAS_XLOCALE__
1086+ __uselocale(__old);
1087+#endif
1088+ return __hi;
1089+ }
1090+
1091+ void
1092+ ctype<wchar_t>::_M_initialize_ctype()
1093+ {
1094+#ifdef __UCLIBC_HAS_XLOCALE__
1095+ __c_locale __old = __uselocale(_M_c_locale_ctype);
1096+#endif
1097+ wint_t __i;
1098+ for (__i = 0; __i < 128; ++__i)
1099+ {
1100+ const int __c = wctob(__i);
1101+ if (__c == EOF)
1102+ break;
1103+ else
1104+ _M_narrow[__i] = static_cast<char>(__c);
1105+ }
1106+ if (__i == 128)
1107+ _M_narrow_ok = true;
1108+ else
1109+ _M_narrow_ok = false;
1110+ for (size_t __j = 0;
1111+ __j < sizeof(_M_widen) / sizeof(wint_t); ++__j)
1112+ _M_widen[__j] = btowc(__j);
1113+
1114+ for (size_t __k = 0; __k <= 11; ++__k)
1115+ {
1116+ _M_bit[__k] = static_cast<mask>(_ISbit(__k));
1117+ _M_wmask[__k] = _M_convert_to_wmask(_M_bit[__k]);
1118+ }
1119+#ifdef __UCLIBC_HAS_XLOCALE__
1120+ __uselocale(__old);
1121+#endif
1122+ }
1123+#endif // _GLIBCXX_USE_WCHAR_T
1124+}
1125Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/messages_members.cc
1126===================================================================
1127--- /dev/null
1128+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/messages_members.cc
1129@@ -0,0 +1,100 @@
1130+// std::messages implementation details, GNU version -*- C++ -*-
1131+
1132+// Copyright (C) 2001, 2002 Free Software Foundation, Inc.
1133+//
1134+// This file is part of the GNU ISO C++ Library. This library is free
1135+// software; you can redistribute it and/or modify it under the
1136+// terms of the GNU General Public License as published by the
1137+// Free Software Foundation; either version 2, or (at your option)
1138+// any later version.
1139+
1140+// This library is distributed in the hope that it will be useful,
1141+// but WITHOUT ANY WARRANTY; without even the implied warranty of
1142+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1143+// GNU General Public License for more details.
1144+
1145+// You should have received a copy of the GNU General Public License along
1146+// with this library; see the file COPYING. If not, write to the Free
1147+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
1148+// USA.
1149+
1150+// As a special exception, you may use this file as part of a free software
1151+// library without restriction. Specifically, if other files instantiate
1152+// templates or use macros or inline functions from this file, or you compile
1153+// this file and link it with other files to produce an executable, this
1154+// file does not by itself cause the resulting executable to be covered by
1155+// the GNU General Public License. This exception does not however
1156+// invalidate any other reasons why the executable file might be covered by
1157+// the GNU General Public License.
1158+
1159+//
1160+// ISO C++ 14882: 22.2.7.1.2 messages virtual functions
1161+//
1162+
1163+// Written by Benjamin Kosnik <bkoz@redhat.com>
1164+
1165+#include <locale>
1166+#include <bits/c++locale_internal.h>
1167+
1168+#ifdef __UCLIBC_MJN3_ONLY__
1169+#warning fix gettext stuff
1170+#endif
1171+#ifdef __UCLIBC_HAS_GETTEXT_AWARENESS__
1172+extern "C" char *__dcgettext(const char *domainname,
1173+ const char *msgid, int category);
1174+#undef gettext
1175+#define gettext(msgid) __dcgettext(NULL, msgid, LC_MESSAGES)
1176+#else
1177+#undef gettext
1178+#define gettext(msgid) (msgid)
1179+#endif
1180+
1181+namespace std
1182+{
1183+ // Specializations.
1184+ template<>
1185+ string
1186+ messages<char>::do_get(catalog, int, int, const string& __dfault) const
1187+ {
1188+#ifdef __UCLIBC_HAS_XLOCALE__
1189+ __c_locale __old = __uselocale(_M_c_locale_messages);
1190+ const char* __msg = const_cast<const char*>(gettext(__dfault.c_str()));
1191+ __uselocale(__old);
1192+ return string(__msg);
1193+#elif defined __UCLIBC_HAS_LOCALE__
1194+ char* __old = strdup(setlocale(LC_ALL, NULL));
1195+ setlocale(LC_ALL, _M_name_messages);
1196+ const char* __msg = gettext(__dfault.c_str());
1197+ setlocale(LC_ALL, __old);
1198+ free(__old);
1199+ return string(__msg);
1200+#else
1201+ const char* __msg = gettext(__dfault.c_str());
1202+ return string(__msg);
1203+#endif
1204+ }
1205+
1206+#ifdef _GLIBCXX_USE_WCHAR_T
1207+ template<>
1208+ wstring
1209+ messages<wchar_t>::do_get(catalog, int, int, const wstring& __dfault) const
1210+ {
1211+# ifdef __UCLIBC_HAS_XLOCALE__
1212+ __c_locale __old = __uselocale(_M_c_locale_messages);
1213+ char* __msg = gettext(_M_convert_to_char(__dfault));
1214+ __uselocale(__old);
1215+ return _M_convert_from_char(__msg);
1216+# elif defined __UCLIBC_HAS_LOCALE__
1217+ char* __old = strdup(setlocale(LC_ALL, NULL));
1218+ setlocale(LC_ALL, _M_name_messages);
1219+ char* __msg = gettext(_M_convert_to_char(__dfault));
1220+ setlocale(LC_ALL, __old);
1221+ free(__old);
1222+ return _M_convert_from_char(__msg);
1223+# else
1224+ char* __msg = gettext(_M_convert_to_char(__dfault));
1225+ return _M_convert_from_char(__msg);
1226+# endif
1227+ }
1228+#endif
1229+}
1230Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/messages_members.h
1231===================================================================
1232--- /dev/null
1233+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/messages_members.h
1234@@ -0,0 +1,118 @@
1235+// std::messages implementation details, GNU version -*- C++ -*-
1236+
1237+// Copyright (C) 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
1238+//
1239+// This file is part of the GNU ISO C++ Library. This library is free
1240+// software; you can redistribute it and/or modify it under the
1241+// terms of the GNU General Public License as published by the
1242+// Free Software Foundation; either version 2, or (at your option)
1243+// any later version.
1244+
1245+// This library is distributed in the hope that it will be useful,
1246+// but WITHOUT ANY WARRANTY; without even the implied warranty of
1247+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1248+// GNU General Public License for more details.
1249+
1250+// You should have received a copy of the GNU General Public License along
1251+// with this library; see the file COPYING. If not, write to the Free
1252+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
1253+// USA.
1254+
1255+// As a special exception, you may use this file as part of a free software
1256+// library without restriction. Specifically, if other files instantiate
1257+// templates or use macros or inline functions from this file, or you compile
1258+// this file and link it with other files to produce an executable, this
1259+// file does not by itself cause the resulting executable to be covered by
1260+// the GNU General Public License. This exception does not however
1261+// invalidate any other reasons why the executable file might be covered by
1262+// the GNU General Public License.
1263+
1264+//
1265+// ISO C++ 14882: 22.2.7.1.2 messages functions
1266+//
1267+
1268+// Written by Benjamin Kosnik <bkoz@redhat.com>
1269+
1270+#ifdef __UCLIBC_MJN3_ONLY__
1271+#warning fix prototypes for *textdomain funcs
1272+#endif
1273+#ifdef __UCLIBC_HAS_GETTEXT_AWARENESS__
1274+extern "C" char *__textdomain(const char *domainname);
1275+extern "C" char *__bindtextdomain(const char *domainname,
1276+ const char *dirname);
1277+#else
1278+#undef __textdomain
1279+#undef __bindtextdomain
1280+#define __textdomain(D) ((void)0)
1281+#define __bindtextdomain(D,P) ((void)0)
1282+#endif
1283+
1284+ // Non-virtual member functions.
1285+ template<typename _CharT>
1286+ messages<_CharT>::messages(size_t __refs)
1287+ : facet(__refs), _M_c_locale_messages(_S_get_c_locale()),
1288+ _M_name_messages(_S_get_c_name())
1289+ { }
1290+
1291+ template<typename _CharT>
1292+ messages<_CharT>::messages(__c_locale __cloc, const char* __s,
1293+ size_t __refs)
1294+ : facet(__refs), _M_c_locale_messages(_S_clone_c_locale(__cloc)),
1295+ _M_name_messages(__s)
1296+ {
1297+ char* __tmp = new char[std::strlen(__s) + 1];
1298+ std::strcpy(__tmp, __s);
1299+ _M_name_messages = __tmp;
1300+ }
1301+
1302+ template<typename _CharT>
1303+ typename messages<_CharT>::catalog
1304+ messages<_CharT>::open(const basic_string<char>& __s, const locale& __loc,
1305+ const char* __dir) const
1306+ {
1307+ __bindtextdomain(__s.c_str(), __dir);
1308+ return this->do_open(__s, __loc);
1309+ }
1310+
1311+ // Virtual member functions.
1312+ template<typename _CharT>
1313+ messages<_CharT>::~messages()
1314+ {
1315+ if (_M_name_messages != _S_get_c_name())
1316+ delete [] _M_name_messages;
1317+ _S_destroy_c_locale(_M_c_locale_messages);
1318+ }
1319+
1320+ template<typename _CharT>
1321+ typename messages<_CharT>::catalog
1322+ messages<_CharT>::do_open(const basic_string<char>& __s,
1323+ const locale&) const
1324+ {
1325+ // No error checking is done, assume the catalog exists and can
1326+ // be used.
1327+ __textdomain(__s.c_str());
1328+ return 0;
1329+ }
1330+
1331+ template<typename _CharT>
1332+ void
1333+ messages<_CharT>::do_close(catalog) const
1334+ { }
1335+
1336+ // messages_byname
1337+ template<typename _CharT>
1338+ messages_byname<_CharT>::messages_byname(const char* __s, size_t __refs)
1339+ : messages<_CharT>(__refs)
1340+ {
1341+ if (this->_M_name_messages != locale::facet::_S_get_c_name())
1342+ delete [] this->_M_name_messages;
1343+ char* __tmp = new char[std::strlen(__s) + 1];
1344+ std::strcpy(__tmp, __s);
1345+ this->_M_name_messages = __tmp;
1346+
1347+ if (std::strcmp(__s, "C") != 0 && std::strcmp(__s, "POSIX") != 0)
1348+ {
1349+ this->_S_destroy_c_locale(this->_M_c_locale_messages);
1350+ this->_S_create_c_locale(this->_M_c_locale_messages, __s);
1351+ }
1352+ }
1353Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/monetary_members.cc
1354===================================================================
1355--- /dev/null
1356+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/monetary_members.cc
1357@@ -0,0 +1,692 @@
1358+// std::moneypunct implementation details, GNU version -*- C++ -*-
1359+
1360+// Copyright (C) 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
1361+//
1362+// This file is part of the GNU ISO C++ Library. This library is free
1363+// software; you can redistribute it and/or modify it under the
1364+// terms of the GNU General Public License as published by the
1365+// Free Software Foundation; either version 2, or (at your option)
1366+// any later version.
1367+
1368+// This library is distributed in the hope that it will be useful,
1369+// but WITHOUT ANY WARRANTY; without even the implied warranty of
1370+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1371+// GNU General Public License for more details.
1372+
1373+// You should have received a copy of the GNU General Public License along
1374+// with this library; see the file COPYING. If not, write to the Free
1375+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
1376+// USA.
1377+
1378+// As a special exception, you may use this file as part of a free software
1379+// library without restriction. Specifically, if other files instantiate
1380+// templates or use macros or inline functions from this file, or you compile
1381+// this file and link it with other files to produce an executable, this
1382+// file does not by itself cause the resulting executable to be covered by
1383+// the GNU General Public License. This exception does not however
1384+// invalidate any other reasons why the executable file might be covered by
1385+// the GNU General Public License.
1386+
1387+//
1388+// ISO C++ 14882: 22.2.6.3.2 moneypunct virtual functions
1389+//
1390+
1391+// Written by Benjamin Kosnik <bkoz@redhat.com>
1392+
1393+#define _LIBC
1394+#include <locale>
1395+#undef _LIBC
1396+#include <bits/c++locale_internal.h>
1397+
1398+#ifdef __UCLIBC_MJN3_ONLY__
1399+#warning optimize this for uclibc
1400+#warning tailor for stub locale support
1401+#endif
1402+
1403+#ifndef __UCLIBC_HAS_XLOCALE__
1404+#define __nl_langinfo_l(N, L) nl_langinfo((N))
1405+#endif
1406+
1407+namespace std
1408+{
1409+ // Construct and return valid pattern consisting of some combination of:
1410+ // space none symbol sign value
1411+ money_base::pattern
1412+ money_base::_S_construct_pattern(char __precedes, char __space, char __posn)
1413+ {
1414+ pattern __ret;
1415+
1416+ // This insanely complicated routine attempts to construct a valid
1417+ // pattern for use with monyepunct. A couple of invariants:
1418+
1419+ // if (__precedes) symbol -> value
1420+ // else value -> symbol
1421+
1422+ // if (__space) space
1423+ // else none
1424+
1425+ // none == never first
1426+ // space never first or last
1427+
1428+ // Any elegant implementations of this are welcome.
1429+ switch (__posn)
1430+ {
1431+ case 0:
1432+ case 1:
1433+ // 1 The sign precedes the value and symbol.
1434+ __ret.field[0] = sign;
1435+ if (__space)
1436+ {
1437+ // Pattern starts with sign.
1438+ if (__precedes)
1439+ {
1440+ __ret.field[1] = symbol;
1441+ __ret.field[3] = value;
1442+ }
1443+ else
1444+ {
1445+ __ret.field[1] = value;
1446+ __ret.field[3] = symbol;
1447+ }
1448+ __ret.field[2] = space;
1449+ }
1450+ else
1451+ {
1452+ // Pattern starts with sign and ends with none.
1453+ if (__precedes)
1454+ {
1455+ __ret.field[1] = symbol;
1456+ __ret.field[2] = value;
1457+ }
1458+ else
1459+ {
1460+ __ret.field[1] = value;
1461+ __ret.field[2] = symbol;
1462+ }
1463+ __ret.field[3] = none;
1464+ }
1465+ break;
1466+ case 2:
1467+ // 2 The sign follows the value and symbol.
1468+ if (__space)
1469+ {
1470+ // Pattern either ends with sign.
1471+ if (__precedes)
1472+ {
1473+ __ret.field[0] = symbol;
1474+ __ret.field[2] = value;
1475+ }
1476+ else
1477+ {
1478+ __ret.field[0] = value;
1479+ __ret.field[2] = symbol;
1480+ }
1481+ __ret.field[1] = space;
1482+ __ret.field[3] = sign;
1483+ }
1484+ else
1485+ {
1486+ // Pattern ends with sign then none.
1487+ if (__precedes)
1488+ {
1489+ __ret.field[0] = symbol;
1490+ __ret.field[1] = value;
1491+ }
1492+ else
1493+ {
1494+ __ret.field[0] = value;
1495+ __ret.field[1] = symbol;
1496+ }
1497+ __ret.field[2] = sign;
1498+ __ret.field[3] = none;
1499+ }
1500+ break;
1501+ case 3:
1502+ // 3 The sign immediately precedes the symbol.
1503+ if (__precedes)
1504+ {
1505+ __ret.field[0] = sign;
1506+ __ret.field[1] = symbol;
1507+ if (__space)
1508+ {
1509+ __ret.field[2] = space;
1510+ __ret.field[3] = value;
1511+ }
1512+ else
1513+ {
1514+ __ret.field[2] = value;
1515+ __ret.field[3] = none;
1516+ }
1517+ }
1518+ else
1519+ {
1520+ __ret.field[0] = value;
1521+ if (__space)
1522+ {
1523+ __ret.field[1] = space;
1524+ __ret.field[2] = sign;
1525+ __ret.field[3] = symbol;
1526+ }
1527+ else
1528+ {
1529+ __ret.field[1] = sign;
1530+ __ret.field[2] = symbol;
1531+ __ret.field[3] = none;
1532+ }
1533+ }
1534+ break;
1535+ case 4:
1536+ // 4 The sign immediately follows the symbol.
1537+ if (__precedes)
1538+ {
1539+ __ret.field[0] = symbol;
1540+ __ret.field[1] = sign;
1541+ if (__space)
1542+ {
1543+ __ret.field[2] = space;
1544+ __ret.field[3] = value;
1545+ }
1546+ else
1547+ {
1548+ __ret.field[2] = value;
1549+ __ret.field[3] = none;
1550+ }
1551+ }
1552+ else
1553+ {
1554+ __ret.field[0] = value;
1555+ if (__space)
1556+ {
1557+ __ret.field[1] = space;
1558+ __ret.field[2] = symbol;
1559+ __ret.field[3] = sign;
1560+ }
1561+ else
1562+ {
1563+ __ret.field[1] = symbol;
1564+ __ret.field[2] = sign;
1565+ __ret.field[3] = none;
1566+ }
1567+ }
1568+ break;
1569+ default:
1570+ ;
1571+ }
1572+ return __ret;
1573+ }
1574+
1575+ template<>
1576+ void
1577+ moneypunct<char, true>::_M_initialize_moneypunct(__c_locale __cloc,
1578+ const char*)
1579+ {
1580+ if (!_M_data)
1581+ _M_data = new __moneypunct_cache<char, true>;
1582+
1583+ if (!__cloc)
1584+ {
1585+ // "C" locale
1586+ _M_data->_M_decimal_point = '.';
1587+ _M_data->_M_thousands_sep = ',';
1588+ _M_data->_M_grouping = "";
1589+ _M_data->_M_grouping_size = 0;
1590+ _M_data->_M_curr_symbol = "";
1591+ _M_data->_M_curr_symbol_size = 0;
1592+ _M_data->_M_positive_sign = "";
1593+ _M_data->_M_positive_sign_size = 0;
1594+ _M_data->_M_negative_sign = "";
1595+ _M_data->_M_negative_sign_size = 0;
1596+ _M_data->_M_frac_digits = 0;
1597+ _M_data->_M_pos_format = money_base::_S_default_pattern;
1598+ _M_data->_M_neg_format = money_base::_S_default_pattern;
1599+
1600+ for (size_t __i = 0; __i < money_base::_S_end; ++__i)
1601+ _M_data->_M_atoms[__i] = money_base::_S_atoms[__i];
1602+ }
1603+ else
1604+ {
1605+ // Named locale.
1606+ _M_data->_M_decimal_point = *(__nl_langinfo_l(__MON_DECIMAL_POINT,
1607+ __cloc));
1608+ _M_data->_M_thousands_sep = *(__nl_langinfo_l(__MON_THOUSANDS_SEP,
1609+ __cloc));
1610+ _M_data->_M_grouping = __nl_langinfo_l(__MON_GROUPING, __cloc);
1611+ _M_data->_M_grouping_size = strlen(_M_data->_M_grouping);
1612+ _M_data->_M_positive_sign = __nl_langinfo_l(__POSITIVE_SIGN, __cloc);
1613+ _M_data->_M_positive_sign_size = strlen(_M_data->_M_positive_sign);
1614+
1615+ char __nposn = *(__nl_langinfo_l(__INT_N_SIGN_POSN, __cloc));
1616+ if (!__nposn)
1617+ _M_data->_M_negative_sign = "()";
1618+ else
1619+ _M_data->_M_negative_sign = __nl_langinfo_l(__NEGATIVE_SIGN,
1620+ __cloc);
1621+ _M_data->_M_negative_sign_size = strlen(_M_data->_M_negative_sign);
1622+
1623+ // _Intl == true
1624+ _M_data->_M_curr_symbol = __nl_langinfo_l(__INT_CURR_SYMBOL, __cloc);
1625+ _M_data->_M_curr_symbol_size = strlen(_M_data->_M_curr_symbol);
1626+ _M_data->_M_frac_digits = *(__nl_langinfo_l(__INT_FRAC_DIGITS,
1627+ __cloc));
1628+ char __pprecedes = *(__nl_langinfo_l(__INT_P_CS_PRECEDES, __cloc));
1629+ char __pspace = *(__nl_langinfo_l(__INT_P_SEP_BY_SPACE, __cloc));
1630+ char __pposn = *(__nl_langinfo_l(__INT_P_SIGN_POSN, __cloc));
1631+ _M_data->_M_pos_format = _S_construct_pattern(__pprecedes, __pspace,
1632+ __pposn);
1633+ char __nprecedes = *(__nl_langinfo_l(__INT_N_CS_PRECEDES, __cloc));
1634+ char __nspace = *(__nl_langinfo_l(__INT_N_SEP_BY_SPACE, __cloc));
1635+ _M_data->_M_neg_format = _S_construct_pattern(__nprecedes, __nspace,
1636+ __nposn);
1637+ }
1638+ }
1639+
1640+ template<>
1641+ void
1642+ moneypunct<char, false>::_M_initialize_moneypunct(__c_locale __cloc,
1643+ const char*)
1644+ {
1645+ if (!_M_data)
1646+ _M_data = new __moneypunct_cache<char, false>;
1647+
1648+ if (!__cloc)
1649+ {
1650+ // "C" locale
1651+ _M_data->_M_decimal_point = '.';
1652+ _M_data->_M_thousands_sep = ',';
1653+ _M_data->_M_grouping = "";
1654+ _M_data->_M_grouping_size = 0;
1655+ _M_data->_M_curr_symbol = "";
1656+ _M_data->_M_curr_symbol_size = 0;
1657+ _M_data->_M_positive_sign = "";
1658+ _M_data->_M_positive_sign_size = 0;
1659+ _M_data->_M_negative_sign = "";
1660+ _M_data->_M_negative_sign_size = 0;
1661+ _M_data->_M_frac_digits = 0;
1662+ _M_data->_M_pos_format = money_base::_S_default_pattern;
1663+ _M_data->_M_neg_format = money_base::_S_default_pattern;
1664+
1665+ for (size_t __i = 0; __i < money_base::_S_end; ++__i)
1666+ _M_data->_M_atoms[__i] = money_base::_S_atoms[__i];
1667+ }
1668+ else
1669+ {
1670+ // Named locale.
1671+ _M_data->_M_decimal_point = *(__nl_langinfo_l(__MON_DECIMAL_POINT,
1672+ __cloc));
1673+ _M_data->_M_thousands_sep = *(__nl_langinfo_l(__MON_THOUSANDS_SEP,
1674+ __cloc));
1675+ _M_data->_M_grouping = __nl_langinfo_l(__MON_GROUPING, __cloc);
1676+ _M_data->_M_grouping_size = strlen(_M_data->_M_grouping);
1677+ _M_data->_M_positive_sign = __nl_langinfo_l(__POSITIVE_SIGN, __cloc);
1678+ _M_data->_M_positive_sign_size = strlen(_M_data->_M_positive_sign);
1679+
1680+ char __nposn = *(__nl_langinfo_l(__N_SIGN_POSN, __cloc));
1681+ if (!__nposn)
1682+ _M_data->_M_negative_sign = "()";
1683+ else
1684+ _M_data->_M_negative_sign = __nl_langinfo_l(__NEGATIVE_SIGN,
1685+ __cloc);
1686+ _M_data->_M_negative_sign_size = strlen(_M_data->_M_negative_sign);
1687+
1688+ // _Intl == false
1689+ _M_data->_M_curr_symbol = __nl_langinfo_l(__CURRENCY_SYMBOL, __cloc);
1690+ _M_data->_M_curr_symbol_size = strlen(_M_data->_M_curr_symbol);
1691+ _M_data->_M_frac_digits = *(__nl_langinfo_l(__FRAC_DIGITS, __cloc));
1692+ char __pprecedes = *(__nl_langinfo_l(__P_CS_PRECEDES, __cloc));
1693+ char __pspace = *(__nl_langinfo_l(__P_SEP_BY_SPACE, __cloc));
1694+ char __pposn = *(__nl_langinfo_l(__P_SIGN_POSN, __cloc));
1695+ _M_data->_M_pos_format = _S_construct_pattern(__pprecedes, __pspace,
1696+ __pposn);
1697+ char __nprecedes = *(__nl_langinfo_l(__N_CS_PRECEDES, __cloc));
1698+ char __nspace = *(__nl_langinfo_l(__N_SEP_BY_SPACE, __cloc));
1699+ _M_data->_M_neg_format = _S_construct_pattern(__nprecedes, __nspace,
1700+ __nposn);
1701+ }
1702+ }
1703+
1704+ template<>
1705+ moneypunct<char, true>::~moneypunct()
1706+ { delete _M_data; }
1707+
1708+ template<>
1709+ moneypunct<char, false>::~moneypunct()
1710+ { delete _M_data; }
1711+
1712+#ifdef _GLIBCXX_USE_WCHAR_T
1713+ template<>
1714+ void
1715+ moneypunct<wchar_t, true>::_M_initialize_moneypunct(__c_locale __cloc,
1716+#ifdef __UCLIBC_HAS_XLOCALE__
1717+ const char*)
1718+#else
1719+ const char* __name)
1720+#endif
1721+ {
1722+ if (!_M_data)
1723+ _M_data = new __moneypunct_cache<wchar_t, true>;
1724+
1725+ if (!__cloc)
1726+ {
1727+ // "C" locale
1728+ _M_data->_M_decimal_point = L'.';
1729+ _M_data->_M_thousands_sep = L',';
1730+ _M_data->_M_grouping = "";
1731+ _M_data->_M_grouping_size = 0;
1732+ _M_data->_M_curr_symbol = L"";
1733+ _M_data->_M_curr_symbol_size = 0;
1734+ _M_data->_M_positive_sign = L"";
1735+ _M_data->_M_positive_sign_size = 0;
1736+ _M_data->_M_negative_sign = L"";
1737+ _M_data->_M_negative_sign_size = 0;
1738+ _M_data->_M_frac_digits = 0;
1739+ _M_data->_M_pos_format = money_base::_S_default_pattern;
1740+ _M_data->_M_neg_format = money_base::_S_default_pattern;
1741+
1742+ // Use ctype::widen code without the facet...
1743+ for (size_t __i = 0; __i < money_base::_S_end; ++__i)
1744+ _M_data->_M_atoms[__i] =
1745+ static_cast<wchar_t>(money_base::_S_atoms[__i]);
1746+ }
1747+ else
1748+ {
1749+ // Named locale.
1750+#ifdef __UCLIBC_HAS_XLOCALE__
1751+ __c_locale __old = __uselocale(__cloc);
1752+#else
1753+ // Switch to named locale so that mbsrtowcs will work.
1754+ char* __old = strdup(setlocale(LC_ALL, NULL));
1755+ setlocale(LC_ALL, __name);
1756+#endif
1757+
1758+#ifdef __UCLIBC_MJN3_ONLY__
1759+#warning fix this... should be monetary
1760+#endif
1761+#ifdef __UCLIBC__
1762+# ifdef __UCLIBC_HAS_XLOCALE__
1763+ _M_data->_M_decimal_point = __cloc->decimal_point_wc;
1764+ _M_data->_M_thousands_sep = __cloc->thousands_sep_wc;
1765+# else
1766+ _M_data->_M_decimal_point = __global_locale->decimal_point_wc;
1767+ _M_data->_M_thousands_sep = __global_locale->thousands_sep_wc;
1768+# endif
1769+#else
1770+ union { char *__s; wchar_t __w; } __u;
1771+ __u.__s = __nl_langinfo_l(_NL_MONETARY_DECIMAL_POINT_WC, __cloc);
1772+ _M_data->_M_decimal_point = __u.__w;
1773+
1774+ __u.__s = __nl_langinfo_l(_NL_MONETARY_THOUSANDS_SEP_WC, __cloc);
1775+ _M_data->_M_thousands_sep = __u.__w;
1776+#endif
1777+ _M_data->_M_grouping = __nl_langinfo_l(__MON_GROUPING, __cloc);
1778+ _M_data->_M_grouping_size = strlen(_M_data->_M_grouping);
1779+
1780+ const char* __cpossign = __nl_langinfo_l(__POSITIVE_SIGN, __cloc);
1781+ const char* __cnegsign = __nl_langinfo_l(__NEGATIVE_SIGN, __cloc);
1782+ const char* __ccurr = __nl_langinfo_l(__INT_CURR_SYMBOL, __cloc);
1783+
1784+ wchar_t* __wcs_ps = 0;
1785+ wchar_t* __wcs_ns = 0;
1786+ const char __nposn = *(__nl_langinfo_l(__INT_N_SIGN_POSN, __cloc));
1787+ try
1788+ {
1789+ mbstate_t __state;
1790+ size_t __len = strlen(__cpossign);
1791+ if (__len)
1792+ {
1793+ ++__len;
1794+ memset(&__state, 0, sizeof(mbstate_t));
1795+ __wcs_ps = new wchar_t[__len];
1796+ mbsrtowcs(__wcs_ps, &__cpossign, __len, &__state);
1797+ _M_data->_M_positive_sign = __wcs_ps;
1798+ }
1799+ else
1800+ _M_data->_M_positive_sign = L"";
1801+ _M_data->_M_positive_sign_size = wcslen(_M_data->_M_positive_sign);
1802+
1803+ __len = strlen(__cnegsign);
1804+ if (!__nposn)
1805+ _M_data->_M_negative_sign = L"()";
1806+ else if (__len)
1807+ {
1808+ ++__len;
1809+ memset(&__state, 0, sizeof(mbstate_t));
1810+ __wcs_ns = new wchar_t[__len];
1811+ mbsrtowcs(__wcs_ns, &__cnegsign, __len, &__state);
1812+ _M_data->_M_negative_sign = __wcs_ns;
1813+ }
1814+ else
1815+ _M_data->_M_negative_sign = L"";
1816+ _M_data->_M_negative_sign_size = wcslen(_M_data->_M_negative_sign);
1817+
1818+ // _Intl == true.
1819+ __len = strlen(__ccurr);
1820+ if (__len)
1821+ {
1822+ ++__len;
1823+ memset(&__state, 0, sizeof(mbstate_t));
1824+ wchar_t* __wcs = new wchar_t[__len];
1825+ mbsrtowcs(__wcs, &__ccurr, __len, &__state);
1826+ _M_data->_M_curr_symbol = __wcs;
1827+ }
1828+ else
1829+ _M_data->_M_curr_symbol = L"";
1830+ _M_data->_M_curr_symbol_size = wcslen(_M_data->_M_curr_symbol);
1831+ }
1832+ catch (...)
1833+ {
1834+ delete _M_data;
1835+ _M_data = 0;
1836+ delete __wcs_ps;
1837+ delete __wcs_ns;
1838+#ifdef __UCLIBC_HAS_XLOCALE__
1839+ __uselocale(__old);
1840+#else
1841+ setlocale(LC_ALL, __old);
1842+ free(__old);
1843+#endif
1844+ __throw_exception_again;
1845+ }
1846+
1847+ _M_data->_M_frac_digits = *(__nl_langinfo_l(__INT_FRAC_DIGITS,
1848+ __cloc));
1849+ char __pprecedes = *(__nl_langinfo_l(__INT_P_CS_PRECEDES, __cloc));
1850+ char __pspace = *(__nl_langinfo_l(__INT_P_SEP_BY_SPACE, __cloc));
1851+ char __pposn = *(__nl_langinfo_l(__INT_P_SIGN_POSN, __cloc));
1852+ _M_data->_M_pos_format = _S_construct_pattern(__pprecedes, __pspace,
1853+ __pposn);
1854+ char __nprecedes = *(__nl_langinfo_l(__INT_N_CS_PRECEDES, __cloc));
1855+ char __nspace = *(__nl_langinfo_l(__INT_N_SEP_BY_SPACE, __cloc));
1856+ _M_data->_M_neg_format = _S_construct_pattern(__nprecedes, __nspace,
1857+ __nposn);
1858+
1859+#ifdef __UCLIBC_HAS_XLOCALE__
1860+ __uselocale(__old);
1861+#else
1862+ setlocale(LC_ALL, __old);
1863+ free(__old);
1864+#endif
1865+ }
1866+ }
1867+
1868+ template<>
1869+ void
1870+ moneypunct<wchar_t, false>::_M_initialize_moneypunct(__c_locale __cloc,
1871+#ifdef __UCLIBC_HAS_XLOCALE__
1872+ const char*)
1873+#else
1874+ const char* __name)
1875+#endif
1876+ {
1877+ if (!_M_data)
1878+ _M_data = new __moneypunct_cache<wchar_t, false>;
1879+
1880+ if (!__cloc)
1881+ {
1882+ // "C" locale
1883+ _M_data->_M_decimal_point = L'.';
1884+ _M_data->_M_thousands_sep = L',';
1885+ _M_data->_M_grouping = "";
1886+ _M_data->_M_grouping_size = 0;
1887+ _M_data->_M_curr_symbol = L"";
1888+ _M_data->_M_curr_symbol_size = 0;
1889+ _M_data->_M_positive_sign = L"";
1890+ _M_data->_M_positive_sign_size = 0;
1891+ _M_data->_M_negative_sign = L"";
1892+ _M_data->_M_negative_sign_size = 0;
1893+ _M_data->_M_frac_digits = 0;
1894+ _M_data->_M_pos_format = money_base::_S_default_pattern;
1895+ _M_data->_M_neg_format = money_base::_S_default_pattern;
1896+
1897+ // Use ctype::widen code without the facet...
1898+ for (size_t __i = 0; __i < money_base::_S_end; ++__i)
1899+ _M_data->_M_atoms[__i] =
1900+ static_cast<wchar_t>(money_base::_S_atoms[__i]);
1901+ }
1902+ else
1903+ {
1904+ // Named locale.
1905+#ifdef __UCLIBC_HAS_XLOCALE__
1906+ __c_locale __old = __uselocale(__cloc);
1907+#else
1908+ // Switch to named locale so that mbsrtowcs will work.
1909+ char* __old = strdup(setlocale(LC_ALL, NULL));
1910+ setlocale(LC_ALL, __name);
1911+#endif
1912+
1913+#ifdef __UCLIBC_MJN3_ONLY__
1914+#warning fix this... should be monetary
1915+#endif
1916+#ifdef __UCLIBC__
1917+# ifdef __UCLIBC_HAS_XLOCALE__
1918+ _M_data->_M_decimal_point = __cloc->decimal_point_wc;
1919+ _M_data->_M_thousands_sep = __cloc->thousands_sep_wc;
1920+# else
1921+ _M_data->_M_decimal_point = __global_locale->decimal_point_wc;
1922+ _M_data->_M_thousands_sep = __global_locale->thousands_sep_wc;
1923+# endif
1924+#else
1925+ union { char *__s; wchar_t __w; } __u;
1926+ __u.__s = __nl_langinfo_l(_NL_MONETARY_DECIMAL_POINT_WC, __cloc);
1927+ _M_data->_M_decimal_point = __u.__w;
1928+
1929+ __u.__s = __nl_langinfo_l(_NL_MONETARY_THOUSANDS_SEP_WC, __cloc);
1930+ _M_data->_M_thousands_sep = __u.__w;
1931+#endif
1932+ _M_data->_M_grouping = __nl_langinfo_l(__MON_GROUPING, __cloc);
1933+ _M_data->_M_grouping_size = strlen(_M_data->_M_grouping);
1934+
1935+ const char* __cpossign = __nl_langinfo_l(__POSITIVE_SIGN, __cloc);
1936+ const char* __cnegsign = __nl_langinfo_l(__NEGATIVE_SIGN, __cloc);
1937+ const char* __ccurr = __nl_langinfo_l(__CURRENCY_SYMBOL, __cloc);
1938+
1939+ wchar_t* __wcs_ps = 0;
1940+ wchar_t* __wcs_ns = 0;
1941+ const char __nposn = *(__nl_langinfo_l(__N_SIGN_POSN, __cloc));
1942+ try
1943+ {
1944+ mbstate_t __state;
1945+ size_t __len;
1946+ __len = strlen(__cpossign);
1947+ if (__len)
1948+ {
1949+ ++__len;
1950+ memset(&__state, 0, sizeof(mbstate_t));
1951+ __wcs_ps = new wchar_t[__len];
1952+ mbsrtowcs(__wcs_ps, &__cpossign, __len, &__state);
1953+ _M_data->_M_positive_sign = __wcs_ps;
1954+ }
1955+ else
1956+ _M_data->_M_positive_sign = L"";
1957+ _M_data->_M_positive_sign_size = wcslen(_M_data->_M_positive_sign);
1958+
1959+ __len = strlen(__cnegsign);
1960+ if (!__nposn)
1961+ _M_data->_M_negative_sign = L"()";
1962+ else if (__len)
1963+ {
1964+ ++__len;
1965+ memset(&__state, 0, sizeof(mbstate_t));
1966+ __wcs_ns = new wchar_t[__len];
1967+ mbsrtowcs(__wcs_ns, &__cnegsign, __len, &__state);
1968+ _M_data->_M_negative_sign = __wcs_ns;
1969+ }
1970+ else
1971+ _M_data->_M_negative_sign = L"";
1972+ _M_data->_M_negative_sign_size = wcslen(_M_data->_M_negative_sign);
1973+
1974+ // _Intl == true.
1975+ __len = strlen(__ccurr);
1976+ if (__len)
1977+ {
1978+ ++__len;
1979+ memset(&__state, 0, sizeof(mbstate_t));
1980+ wchar_t* __wcs = new wchar_t[__len];
1981+ mbsrtowcs(__wcs, &__ccurr, __len, &__state);
1982+ _M_data->_M_curr_symbol = __wcs;
1983+ }
1984+ else
1985+ _M_data->_M_curr_symbol = L"";
1986+ _M_data->_M_curr_symbol_size = wcslen(_M_data->_M_curr_symbol);
1987+ }
1988+ catch (...)
1989+ {
1990+ delete _M_data;
1991+ _M_data = 0;
1992+ delete __wcs_ps;
1993+ delete __wcs_ns;
1994+#ifdef __UCLIBC_HAS_XLOCALE__
1995+ __uselocale(__old);
1996+#else
1997+ setlocale(LC_ALL, __old);
1998+ free(__old);
1999+#endif
2000+ __throw_exception_again;
2001+ }
2002+
2003+ _M_data->_M_frac_digits = *(__nl_langinfo_l(__FRAC_DIGITS, __cloc));
2004+ char __pprecedes = *(__nl_langinfo_l(__P_CS_PRECEDES, __cloc));
2005+ char __pspace = *(__nl_langinfo_l(__P_SEP_BY_SPACE, __cloc));
2006+ char __pposn = *(__nl_langinfo_l(__P_SIGN_POSN, __cloc));
2007+ _M_data->_M_pos_format = _S_construct_pattern(__pprecedes, __pspace,
2008+ __pposn);
2009+ char __nprecedes = *(__nl_langinfo_l(__N_CS_PRECEDES, __cloc));
2010+ char __nspace = *(__nl_langinfo_l(__N_SEP_BY_SPACE, __cloc));
2011+ _M_data->_M_neg_format = _S_construct_pattern(__nprecedes, __nspace,
2012+ __nposn);
2013+
2014+#ifdef __UCLIBC_HAS_XLOCALE__
2015+ __uselocale(__old);
2016+#else
2017+ setlocale(LC_ALL, __old);
2018+ free(__old);
2019+#endif
2020+ }
2021+ }
2022+
2023+ template<>
2024+ moneypunct<wchar_t, true>::~moneypunct()
2025+ {
2026+ if (_M_data->_M_positive_sign_size)
2027+ delete [] _M_data->_M_positive_sign;
2028+ if (_M_data->_M_negative_sign_size
2029+ && wcscmp(_M_data->_M_negative_sign, L"()") != 0)
2030+ delete [] _M_data->_M_negative_sign;
2031+ if (_M_data->_M_curr_symbol_size)
2032+ delete [] _M_data->_M_curr_symbol;
2033+ delete _M_data;
2034+ }
2035+
2036+ template<>
2037+ moneypunct<wchar_t, false>::~moneypunct()
2038+ {
2039+ if (_M_data->_M_positive_sign_size)
2040+ delete [] _M_data->_M_positive_sign;
2041+ if (_M_data->_M_negative_sign_size
2042+ && wcscmp(_M_data->_M_negative_sign, L"()") != 0)
2043+ delete [] _M_data->_M_negative_sign;
2044+ if (_M_data->_M_curr_symbol_size)
2045+ delete [] _M_data->_M_curr_symbol;
2046+ delete _M_data;
2047+ }
2048+#endif
2049+}
2050Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/numeric_members.cc
2051===================================================================
2052--- /dev/null
2053+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/numeric_members.cc
2054@@ -0,0 +1,160 @@
2055+// std::numpunct implementation details, GNU version -*- C++ -*-
2056+
2057+// Copyright (C) 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
2058+//
2059+// This file is part of the GNU ISO C++ Library. This library is free
2060+// software; you can redistribute it and/or modify it under the
2061+// terms of the GNU General Public License as published by the
2062+// Free Software Foundation; either version 2, or (at your option)
2063+// any later version.
2064+
2065+// This library is distributed in the hope that it will be useful,
2066+// but WITHOUT ANY WARRANTY; without even the implied warranty of
2067+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2068+// GNU General Public License for more details.
2069+
2070+// You should have received a copy of the GNU General Public License along
2071+// with this library; see the file COPYING. If not, write to the Free
2072+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
2073+// USA.
2074+
2075+// As a special exception, you may use this file as part of a free software
2076+// library without restriction. Specifically, if other files instantiate
2077+// templates or use macros or inline functions from this file, or you compile
2078+// this file and link it with other files to produce an executable, this
2079+// file does not by itself cause the resulting executable to be covered by
2080+// the GNU General Public License. This exception does not however
2081+// invalidate any other reasons why the executable file might be covered by
2082+// the GNU General Public License.
2083+
2084+//
2085+// ISO C++ 14882: 22.2.3.1.2 numpunct virtual functions
2086+//
2087+
2088+// Written by Benjamin Kosnik <bkoz@redhat.com>
2089+
2090+#define _LIBC
2091+#include <locale>
2092+#undef _LIBC
2093+#include <bits/c++locale_internal.h>
2094+
2095+#ifdef __UCLIBC_MJN3_ONLY__
2096+#warning tailor for stub locale support
2097+#endif
2098+#ifndef __UCLIBC_HAS_XLOCALE__
2099+#define __nl_langinfo_l(N, L) nl_langinfo((N))
2100+#endif
2101+
2102+namespace std
2103+{
2104+ template<>
2105+ void
2106+ numpunct<char>::_M_initialize_numpunct(__c_locale __cloc)
2107+ {
2108+ if (!_M_data)
2109+ _M_data = new __numpunct_cache<char>;
2110+
2111+ if (!__cloc)
2112+ {
2113+ // "C" locale
2114+ _M_data->_M_grouping = "";
2115+ _M_data->_M_grouping_size = 0;
2116+ _M_data->_M_use_grouping = false;
2117+
2118+ _M_data->_M_decimal_point = '.';
2119+ _M_data->_M_thousands_sep = ',';
2120+
2121+ for (size_t __i = 0; __i < __num_base::_S_oend; ++__i)
2122+ _M_data->_M_atoms_out[__i] = __num_base::_S_atoms_out[__i];
2123+
2124+ for (size_t __j = 0; __j < __num_base::_S_iend; ++__j)
2125+ _M_data->_M_atoms_in[__j] = __num_base::_S_atoms_in[__j];
2126+ }
2127+ else
2128+ {
2129+ // Named locale.
2130+ _M_data->_M_decimal_point = *(__nl_langinfo_l(DECIMAL_POINT,
2131+ __cloc));
2132+ _M_data->_M_thousands_sep = *(__nl_langinfo_l(THOUSANDS_SEP,
2133+ __cloc));
2134+
2135+ // Check for NULL, which implies no grouping.
2136+ if (_M_data->_M_thousands_sep == '\0')
2137+ _M_data->_M_grouping = "";
2138+ else
2139+ _M_data->_M_grouping = __nl_langinfo_l(GROUPING, __cloc);
2140+ _M_data->_M_grouping_size = strlen(_M_data->_M_grouping);
2141+ }
2142+
2143+ // NB: There is no way to extact this info from posix locales.
2144+ // _M_truename = __nl_langinfo_l(YESSTR, __cloc);
2145+ _M_data->_M_truename = "true";
2146+ _M_data->_M_truename_size = 4;
2147+ // _M_falsename = __nl_langinfo_l(NOSTR, __cloc);
2148+ _M_data->_M_falsename = "false";
2149+ _M_data->_M_falsename_size = 5;
2150+ }
2151+
2152+ template<>
2153+ numpunct<char>::~numpunct()
2154+ { delete _M_data; }
2155+
2156+#ifdef _GLIBCXX_USE_WCHAR_T
2157+ template<>
2158+ void
2159+ numpunct<wchar_t>::_M_initialize_numpunct(__c_locale __cloc)
2160+ {
2161+ if (!_M_data)
2162+ _M_data = new __numpunct_cache<wchar_t>;
2163+
2164+ if (!__cloc)
2165+ {
2166+ // "C" locale
2167+ _M_data->_M_grouping = "";
2168+ _M_data->_M_grouping_size = 0;
2169+ _M_data->_M_use_grouping = false;
2170+
2171+ _M_data->_M_decimal_point = L'.';
2172+ _M_data->_M_thousands_sep = L',';
2173+
2174+ // Use ctype::widen code without the facet...
2175+ for (size_t __i = 0; __i < __num_base::_S_oend; ++__i)
2176+ _M_data->_M_atoms_out[__i] =
2177+ static_cast<wchar_t>(__num_base::_S_atoms_out[__i]);
2178+
2179+ for (size_t __j = 0; __j < __num_base::_S_iend; ++__j)
2180+ _M_data->_M_atoms_in[__j] =
2181+ static_cast<wchar_t>(__num_base::_S_atoms_in[__j]);
2182+ }
2183+ else
2184+ {
2185+ // Named locale.
2186+ // NB: In the GNU model wchar_t is always 32 bit wide.
2187+ union { char *__s; wchar_t __w; } __u;
2188+ __u.__s = __nl_langinfo_l(_NL_NUMERIC_DECIMAL_POINT_WC, __cloc);
2189+ _M_data->_M_decimal_point = __u.__w;
2190+
2191+ __u.__s = __nl_langinfo_l(_NL_NUMERIC_THOUSANDS_SEP_WC, __cloc);
2192+ _M_data->_M_thousands_sep = __u.__w;
2193+
2194+ if (_M_data->_M_thousands_sep == L'\0')
2195+ _M_data->_M_grouping = "";
2196+ else
2197+ _M_data->_M_grouping = __nl_langinfo_l(GROUPING, __cloc);
2198+ _M_data->_M_grouping_size = strlen(_M_data->_M_grouping);
2199+ }
2200+
2201+ // NB: There is no way to extact this info from posix locales.
2202+ // _M_truename = __nl_langinfo_l(YESSTR, __cloc);
2203+ _M_data->_M_truename = L"true";
2204+ _M_data->_M_truename_size = 4;
2205+ // _M_falsename = __nl_langinfo_l(NOSTR, __cloc);
2206+ _M_data->_M_falsename = L"false";
2207+ _M_data->_M_falsename_size = 5;
2208+ }
2209+
2210+ template<>
2211+ numpunct<wchar_t>::~numpunct()
2212+ { delete _M_data; }
2213+ #endif
2214+}
2215Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/time_members.cc
2216===================================================================
2217--- /dev/null
2218+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/time_members.cc
2219@@ -0,0 +1,406 @@
2220+// std::time_get, std::time_put implementation, GNU version -*- C++ -*-
2221+
2222+// Copyright (C) 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
2223+//
2224+// This file is part of the GNU ISO C++ Library. This library is free
2225+// software; you can redistribute it and/or modify it under the
2226+// terms of the GNU General Public License as published by the
2227+// Free Software Foundation; either version 2, or (at your option)
2228+// any later version.
2229+
2230+// This library is distributed in the hope that it will be useful,
2231+// but WITHOUT ANY WARRANTY; without even the implied warranty of
2232+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2233+// GNU General Public License for more details.
2234+
2235+// You should have received a copy of the GNU General Public License along
2236+// with this library; see the file COPYING. If not, write to the Free
2237+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
2238+// USA.
2239+
2240+// As a special exception, you may use this file as part of a free software
2241+// library without restriction. Specifically, if other files instantiate
2242+// templates or use macros or inline functions from this file, or you compile
2243+// this file and link it with other files to produce an executable, this
2244+// file does not by itself cause the resulting executable to be covered by
2245+// the GNU General Public License. This exception does not however
2246+// invalidate any other reasons why the executable file might be covered by
2247+// the GNU General Public License.
2248+
2249+//
2250+// ISO C++ 14882: 22.2.5.1.2 - time_get virtual functions
2251+// ISO C++ 14882: 22.2.5.3.2 - time_put virtual functions
2252+//
2253+
2254+// Written by Benjamin Kosnik <bkoz@redhat.com>
2255+
2256+#include <locale>
2257+#include <bits/c++locale_internal.h>
2258+
2259+#ifdef __UCLIBC_MJN3_ONLY__
2260+#warning tailor for stub locale support
2261+#endif
2262+#ifndef __UCLIBC_HAS_XLOCALE__
2263+#define __nl_langinfo_l(N, L) nl_langinfo((N))
2264+#endif
2265+
2266+namespace std
2267+{
2268+ template<>
2269+ void
2270+ __timepunct<char>::
2271+ _M_put(char* __s, size_t __maxlen, const char* __format,
2272+ const tm* __tm) const
2273+ {
2274+#ifdef __UCLIBC_HAS_XLOCALE__
2275+ const size_t __len = __strftime_l(__s, __maxlen, __format, __tm,
2276+ _M_c_locale_timepunct);
2277+#else
2278+ char* __old = strdup(setlocale(LC_ALL, NULL));
2279+ setlocale(LC_ALL, _M_name_timepunct);
2280+ const size_t __len = strftime(__s, __maxlen, __format, __tm);
2281+ setlocale(LC_ALL, __old);
2282+ free(__old);
2283+#endif
2284+ // Make sure __s is null terminated.
2285+ if (__len == 0)
2286+ __s[0] = '\0';
2287+ }
2288+
2289+ template<>
2290+ void
2291+ __timepunct<char>::_M_initialize_timepunct(__c_locale __cloc)
2292+ {
2293+ if (!_M_data)
2294+ _M_data = new __timepunct_cache<char>;
2295+
2296+ if (!__cloc)
2297+ {
2298+ // "C" locale
2299+ _M_c_locale_timepunct = _S_get_c_locale();
2300+
2301+ _M_data->_M_date_format = "%m/%d/%y";
2302+ _M_data->_M_date_era_format = "%m/%d/%y";
2303+ _M_data->_M_time_format = "%H:%M:%S";
2304+ _M_data->_M_time_era_format = "%H:%M:%S";
2305+ _M_data->_M_date_time_format = "";
2306+ _M_data->_M_date_time_era_format = "";
2307+ _M_data->_M_am = "AM";
2308+ _M_data->_M_pm = "PM";
2309+ _M_data->_M_am_pm_format = "";
2310+
2311+ // Day names, starting with "C"'s Sunday.
2312+ _M_data->_M_day1 = "Sunday";
2313+ _M_data->_M_day2 = "Monday";
2314+ _M_data->_M_day3 = "Tuesday";
2315+ _M_data->_M_day4 = "Wednesday";
2316+ _M_data->_M_day5 = "Thursday";
2317+ _M_data->_M_day6 = "Friday";
2318+ _M_data->_M_day7 = "Saturday";
2319+
2320+ // Abbreviated day names, starting with "C"'s Sun.
2321+ _M_data->_M_aday1 = "Sun";
2322+ _M_data->_M_aday2 = "Mon";
2323+ _M_data->_M_aday3 = "Tue";
2324+ _M_data->_M_aday4 = "Wed";
2325+ _M_data->_M_aday5 = "Thu";
2326+ _M_data->_M_aday6 = "Fri";
2327+ _M_data->_M_aday7 = "Sat";
2328+
2329+ // Month names, starting with "C"'s January.
2330+ _M_data->_M_month01 = "January";
2331+ _M_data->_M_month02 = "February";
2332+ _M_data->_M_month03 = "March";
2333+ _M_data->_M_month04 = "April";
2334+ _M_data->_M_month05 = "May";
2335+ _M_data->_M_month06 = "June";
2336+ _M_data->_M_month07 = "July";
2337+ _M_data->_M_month08 = "August";
2338+ _M_data->_M_month09 = "September";
2339+ _M_data->_M_month10 = "October";
2340+ _M_data->_M_month11 = "November";
2341+ _M_data->_M_month12 = "December";
2342+
2343+ // Abbreviated month names, starting with "C"'s Jan.
2344+ _M_data->_M_amonth01 = "Jan";
2345+ _M_data->_M_amonth02 = "Feb";
2346+ _M_data->_M_amonth03 = "Mar";
2347+ _M_data->_M_amonth04 = "Apr";
2348+ _M_data->_M_amonth05 = "May";
2349+ _M_data->_M_amonth06 = "Jun";
2350+ _M_data->_M_amonth07 = "Jul";
2351+ _M_data->_M_amonth08 = "Aug";
2352+ _M_data->_M_amonth09 = "Sep";
2353+ _M_data->_M_amonth10 = "Oct";
2354+ _M_data->_M_amonth11 = "Nov";
2355+ _M_data->_M_amonth12 = "Dec";
2356+ }
2357+ else
2358+ {
2359+ _M_c_locale_timepunct = _S_clone_c_locale(__cloc);
2360+
2361+ _M_data->_M_date_format = __nl_langinfo_l(D_FMT, __cloc);
2362+ _M_data->_M_date_era_format = __nl_langinfo_l(ERA_D_FMT, __cloc);
2363+ _M_data->_M_time_format = __nl_langinfo_l(T_FMT, __cloc);
2364+ _M_data->_M_time_era_format = __nl_langinfo_l(ERA_T_FMT, __cloc);
2365+ _M_data->_M_date_time_format = __nl_langinfo_l(D_T_FMT, __cloc);
2366+ _M_data->_M_date_time_era_format = __nl_langinfo_l(ERA_D_T_FMT,
2367+ __cloc);
2368+ _M_data->_M_am = __nl_langinfo_l(AM_STR, __cloc);
2369+ _M_data->_M_pm = __nl_langinfo_l(PM_STR, __cloc);
2370+ _M_data->_M_am_pm_format = __nl_langinfo_l(T_FMT_AMPM, __cloc);
2371+
2372+ // Day names, starting with "C"'s Sunday.
2373+ _M_data->_M_day1 = __nl_langinfo_l(DAY_1, __cloc);
2374+ _M_data->_M_day2 = __nl_langinfo_l(DAY_2, __cloc);
2375+ _M_data->_M_day3 = __nl_langinfo_l(DAY_3, __cloc);
2376+ _M_data->_M_day4 = __nl_langinfo_l(DAY_4, __cloc);
2377+ _M_data->_M_day5 = __nl_langinfo_l(DAY_5, __cloc);
2378+ _M_data->_M_day6 = __nl_langinfo_l(DAY_6, __cloc);
2379+ _M_data->_M_day7 = __nl_langinfo_l(DAY_7, __cloc);
2380+
2381+ // Abbreviated day names, starting with "C"'s Sun.
2382+ _M_data->_M_aday1 = __nl_langinfo_l(ABDAY_1, __cloc);
2383+ _M_data->_M_aday2 = __nl_langinfo_l(ABDAY_2, __cloc);
2384+ _M_data->_M_aday3 = __nl_langinfo_l(ABDAY_3, __cloc);
2385+ _M_data->_M_aday4 = __nl_langinfo_l(ABDAY_4, __cloc);
2386+ _M_data->_M_aday5 = __nl_langinfo_l(ABDAY_5, __cloc);
2387+ _M_data->_M_aday6 = __nl_langinfo_l(ABDAY_6, __cloc);
2388+ _M_data->_M_aday7 = __nl_langinfo_l(ABDAY_7, __cloc);
2389+
2390+ // Month names, starting with "C"'s January.
2391+ _M_data->_M_month01 = __nl_langinfo_l(MON_1, __cloc);
2392+ _M_data->_M_month02 = __nl_langinfo_l(MON_2, __cloc);
2393+ _M_data->_M_month03 = __nl_langinfo_l(MON_3, __cloc);
2394+ _M_data->_M_month04 = __nl_langinfo_l(MON_4, __cloc);
2395+ _M_data->_M_month05 = __nl_langinfo_l(MON_5, __cloc);
2396+ _M_data->_M_month06 = __nl_langinfo_l(MON_6, __cloc);
2397+ _M_data->_M_month07 = __nl_langinfo_l(MON_7, __cloc);
2398+ _M_data->_M_month08 = __nl_langinfo_l(MON_8, __cloc);
2399+ _M_data->_M_month09 = __nl_langinfo_l(MON_9, __cloc);
2400+ _M_data->_M_month10 = __nl_langinfo_l(MON_10, __cloc);
2401+ _M_data->_M_month11 = __nl_langinfo_l(MON_11, __cloc);
2402+ _M_data->_M_month12 = __nl_langinfo_l(MON_12, __cloc);
2403+
2404+ // Abbreviated month names, starting with "C"'s Jan.
2405+ _M_data->_M_amonth01 = __nl_langinfo_l(ABMON_1, __cloc);
2406+ _M_data->_M_amonth02 = __nl_langinfo_l(ABMON_2, __cloc);
2407+ _M_data->_M_amonth03 = __nl_langinfo_l(ABMON_3, __cloc);
2408+ _M_data->_M_amonth04 = __nl_langinfo_l(ABMON_4, __cloc);
2409+ _M_data->_M_amonth05 = __nl_langinfo_l(ABMON_5, __cloc);
2410+ _M_data->_M_amonth06 = __nl_langinfo_l(ABMON_6, __cloc);
2411+ _M_data->_M_amonth07 = __nl_langinfo_l(ABMON_7, __cloc);
2412+ _M_data->_M_amonth08 = __nl_langinfo_l(ABMON_8, __cloc);
2413+ _M_data->_M_amonth09 = __nl_langinfo_l(ABMON_9, __cloc);
2414+ _M_data->_M_amonth10 = __nl_langinfo_l(ABMON_10, __cloc);
2415+ _M_data->_M_amonth11 = __nl_langinfo_l(ABMON_11, __cloc);
2416+ _M_data->_M_amonth12 = __nl_langinfo_l(ABMON_12, __cloc);
2417+ }
2418+ }
2419+
2420+#ifdef _GLIBCXX_USE_WCHAR_T
2421+ template<>
2422+ void
2423+ __timepunct<wchar_t>::
2424+ _M_put(wchar_t* __s, size_t __maxlen, const wchar_t* __format,
2425+ const tm* __tm) const
2426+ {
2427+#ifdef __UCLIBC_HAS_XLOCALE__
2428+ __wcsftime_l(__s, __maxlen, __format, __tm, _M_c_locale_timepunct);
2429+ const size_t __len = __wcsftime_l(__s, __maxlen, __format, __tm,
2430+ _M_c_locale_timepunct);
2431+#else
2432+ char* __old = strdup(setlocale(LC_ALL, NULL));
2433+ setlocale(LC_ALL, _M_name_timepunct);
2434+ const size_t __len = wcsftime(__s, __maxlen, __format, __tm);
2435+ setlocale(LC_ALL, __old);
2436+ free(__old);
2437+#endif
2438+ // Make sure __s is null terminated.
2439+ if (__len == 0)
2440+ __s[0] = L'\0';
2441+ }
2442+
2443+ template<>
2444+ void
2445+ __timepunct<wchar_t>::_M_initialize_timepunct(__c_locale __cloc)
2446+ {
2447+ if (!_M_data)
2448+ _M_data = new __timepunct_cache<wchar_t>;
2449+
2450+#warning wide time stuff
2451+// if (!__cloc)
2452+ {
2453+ // "C" locale
2454+ _M_c_locale_timepunct = _S_get_c_locale();
2455+
2456+ _M_data->_M_date_format = L"%m/%d/%y";
2457+ _M_data->_M_date_era_format = L"%m/%d/%y";
2458+ _M_data->_M_time_format = L"%H:%M:%S";
2459+ _M_data->_M_time_era_format = L"%H:%M:%S";
2460+ _M_data->_M_date_time_format = L"";
2461+ _M_data->_M_date_time_era_format = L"";
2462+ _M_data->_M_am = L"AM";
2463+ _M_data->_M_pm = L"PM";
2464+ _M_data->_M_am_pm_format = L"";
2465+
2466+ // Day names, starting with "C"'s Sunday.
2467+ _M_data->_M_day1 = L"Sunday";
2468+ _M_data->_M_day2 = L"Monday";
2469+ _M_data->_M_day3 = L"Tuesday";
2470+ _M_data->_M_day4 = L"Wednesday";
2471+ _M_data->_M_day5 = L"Thursday";
2472+ _M_data->_M_day6 = L"Friday";
2473+ _M_data->_M_day7 = L"Saturday";
2474+
2475+ // Abbreviated day names, starting with "C"'s Sun.
2476+ _M_data->_M_aday1 = L"Sun";
2477+ _M_data->_M_aday2 = L"Mon";
2478+ _M_data->_M_aday3 = L"Tue";
2479+ _M_data->_M_aday4 = L"Wed";
2480+ _M_data->_M_aday5 = L"Thu";
2481+ _M_data->_M_aday6 = L"Fri";
2482+ _M_data->_M_aday7 = L"Sat";
2483+
2484+ // Month names, starting with "C"'s January.
2485+ _M_data->_M_month01 = L"January";
2486+ _M_data->_M_month02 = L"February";
2487+ _M_data->_M_month03 = L"March";
2488+ _M_data->_M_month04 = L"April";
2489+ _M_data->_M_month05 = L"May";
2490+ _M_data->_M_month06 = L"June";
2491+ _M_data->_M_month07 = L"July";
2492+ _M_data->_M_month08 = L"August";
2493+ _M_data->_M_month09 = L"September";
2494+ _M_data->_M_month10 = L"October";
2495+ _M_data->_M_month11 = L"November";
2496+ _M_data->_M_month12 = L"December";
2497+
2498+ // Abbreviated month names, starting with "C"'s Jan.
2499+ _M_data->_M_amonth01 = L"Jan";
2500+ _M_data->_M_amonth02 = L"Feb";
2501+ _M_data->_M_amonth03 = L"Mar";
2502+ _M_data->_M_amonth04 = L"Apr";
2503+ _M_data->_M_amonth05 = L"May";
2504+ _M_data->_M_amonth06 = L"Jun";
2505+ _M_data->_M_amonth07 = L"Jul";
2506+ _M_data->_M_amonth08 = L"Aug";
2507+ _M_data->_M_amonth09 = L"Sep";
2508+ _M_data->_M_amonth10 = L"Oct";
2509+ _M_data->_M_amonth11 = L"Nov";
2510+ _M_data->_M_amonth12 = L"Dec";
2511+ }
2512+#if 0
2513+ else
2514+ {
2515+ _M_c_locale_timepunct = _S_clone_c_locale(__cloc);
2516+
2517+ union { char *__s; wchar_t *__w; } __u;
2518+
2519+ __u.__s = __nl_langinfo_l(_NL_WD_FMT, __cloc);
2520+ _M_data->_M_date_format = __u.__w;
2521+ __u.__s = __nl_langinfo_l(_NL_WERA_D_FMT, __cloc);
2522+ _M_data->_M_date_era_format = __u.__w;
2523+ __u.__s = __nl_langinfo_l(_NL_WT_FMT, __cloc);
2524+ _M_data->_M_time_format = __u.__w;
2525+ __u.__s = __nl_langinfo_l(_NL_WERA_T_FMT, __cloc);
2526+ _M_data->_M_time_era_format = __u.__w;
2527+ __u.__s = __nl_langinfo_l(_NL_WD_T_FMT, __cloc);
2528+ _M_data->_M_date_time_format = __u.__w;
2529+ __u.__s = __nl_langinfo_l(_NL_WERA_D_T_FMT, __cloc);
2530+ _M_data->_M_date_time_era_format = __u.__w;
2531+ __u.__s = __nl_langinfo_l(_NL_WAM_STR, __cloc);
2532+ _M_data->_M_am = __u.__w;
2533+ __u.__s = __nl_langinfo_l(_NL_WPM_STR, __cloc);
2534+ _M_data->_M_pm = __u.__w;
2535+ __u.__s = __nl_langinfo_l(_NL_WT_FMT_AMPM, __cloc);
2536+ _M_data->_M_am_pm_format = __u.__w;
2537+
2538+ // Day names, starting with "C"'s Sunday.
2539+ __u.__s = __nl_langinfo_l(_NL_WDAY_1, __cloc);
2540+ _M_data->_M_day1 = __u.__w;
2541+ __u.__s = __nl_langinfo_l(_NL_WDAY_2, __cloc);
2542+ _M_data->_M_day2 = __u.__w;
2543+ __u.__s = __nl_langinfo_l(_NL_WDAY_3, __cloc);
2544+ _M_data->_M_day3 = __u.__w;
2545+ __u.__s = __nl_langinfo_l(_NL_WDAY_4, __cloc);
2546+ _M_data->_M_day4 = __u.__w;
2547+ __u.__s = __nl_langinfo_l(_NL_WDAY_5, __cloc);
2548+ _M_data->_M_day5 = __u.__w;
2549+ __u.__s = __nl_langinfo_l(_NL_WDAY_6, __cloc);
2550+ _M_data->_M_day6 = __u.__w;
2551+ __u.__s = __nl_langinfo_l(_NL_WDAY_7, __cloc);
2552+ _M_data->_M_day7 = __u.__w;
2553+
2554+ // Abbreviated day names, starting with "C"'s Sun.
2555+ __u.__s = __nl_langinfo_l(_NL_WABDAY_1, __cloc);
2556+ _M_data->_M_aday1 = __u.__w;
2557+ __u.__s = __nl_langinfo_l(_NL_WABDAY_2, __cloc);
2558+ _M_data->_M_aday2 = __u.__w;
2559+ __u.__s = __nl_langinfo_l(_NL_WABDAY_3, __cloc);
2560+ _M_data->_M_aday3 = __u.__w;
2561+ __u.__s = __nl_langinfo_l(_NL_WABDAY_4, __cloc);
2562+ _M_data->_M_aday4 = __u.__w;
2563+ __u.__s = __nl_langinfo_l(_NL_WABDAY_5, __cloc);
2564+ _M_data->_M_aday5 = __u.__w;
2565+ __u.__s = __nl_langinfo_l(_NL_WABDAY_6, __cloc);
2566+ _M_data->_M_aday6 = __u.__w;
2567+ __u.__s = __nl_langinfo_l(_NL_WABDAY_7, __cloc);
2568+ _M_data->_M_aday7 = __u.__w;
2569+
2570+ // Month names, starting with "C"'s January.
2571+ __u.__s = __nl_langinfo_l(_NL_WMON_1, __cloc);
2572+ _M_data->_M_month01 = __u.__w;
2573+ __u.__s = __nl_langinfo_l(_NL_WMON_2, __cloc);
2574+ _M_data->_M_month02 = __u.__w;
2575+ __u.__s = __nl_langinfo_l(_NL_WMON_3, __cloc);
2576+ _M_data->_M_month03 = __u.__w;
2577+ __u.__s = __nl_langinfo_l(_NL_WMON_4, __cloc);
2578+ _M_data->_M_month04 = __u.__w;
2579+ __u.__s = __nl_langinfo_l(_NL_WMON_5, __cloc);
2580+ _M_data->_M_month05 = __u.__w;
2581+ __u.__s = __nl_langinfo_l(_NL_WMON_6, __cloc);
2582+ _M_data->_M_month06 = __u.__w;
2583+ __u.__s = __nl_langinfo_l(_NL_WMON_7, __cloc);
2584+ _M_data->_M_month07 = __u.__w;
2585+ __u.__s = __nl_langinfo_l(_NL_WMON_8, __cloc);
2586+ _M_data->_M_month08 = __u.__w;
2587+ __u.__s = __nl_langinfo_l(_NL_WMON_9, __cloc);
2588+ _M_data->_M_month09 = __u.__w;
2589+ __u.__s = __nl_langinfo_l(_NL_WMON_10, __cloc);
2590+ _M_data->_M_month10 = __u.__w;
2591+ __u.__s = __nl_langinfo_l(_NL_WMON_11, __cloc);
2592+ _M_data->_M_month11 = __u.__w;
2593+ __u.__s = __nl_langinfo_l(_NL_WMON_12, __cloc);
2594+ _M_data->_M_month12 = __u.__w;
2595+
2596+ // Abbreviated month names, starting with "C"'s Jan.
2597+ __u.__s = __nl_langinfo_l(_NL_WABMON_1, __cloc);
2598+ _M_data->_M_amonth01 = __u.__w;
2599+ __u.__s = __nl_langinfo_l(_NL_WABMON_2, __cloc);
2600+ _M_data->_M_amonth02 = __u.__w;
2601+ __u.__s = __nl_langinfo_l(_NL_WABMON_3, __cloc);
2602+ _M_data->_M_amonth03 = __u.__w;
2603+ __u.__s = __nl_langinfo_l(_NL_WABMON_4, __cloc);
2604+ _M_data->_M_amonth04 = __u.__w;
2605+ __u.__s = __nl_langinfo_l(_NL_WABMON_5, __cloc);
2606+ _M_data->_M_amonth05 = __u.__w;
2607+ __u.__s = __nl_langinfo_l(_NL_WABMON_6, __cloc);
2608+ _M_data->_M_amonth06 = __u.__w;
2609+ __u.__s = __nl_langinfo_l(_NL_WABMON_7, __cloc);
2610+ _M_data->_M_amonth07 = __u.__w;
2611+ __u.__s = __nl_langinfo_l(_NL_WABMON_8, __cloc);
2612+ _M_data->_M_amonth08 = __u.__w;
2613+ __u.__s = __nl_langinfo_l(_NL_WABMON_9, __cloc);
2614+ _M_data->_M_amonth09 = __u.__w;
2615+ __u.__s = __nl_langinfo_l(_NL_WABMON_10, __cloc);
2616+ _M_data->_M_amonth10 = __u.__w;
2617+ __u.__s = __nl_langinfo_l(_NL_WABMON_11, __cloc);
2618+ _M_data->_M_amonth11 = __u.__w;
2619+ __u.__s = __nl_langinfo_l(_NL_WABMON_12, __cloc);
2620+ _M_data->_M_amonth12 = __u.__w;
2621+ }
2622+#endif // 0
2623+ }
2624+#endif
2625+}
2626Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/time_members.h
2627===================================================================
2628--- /dev/null
2629+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/time_members.h
2630@@ -0,0 +1,68 @@
2631+// std::time_get, std::time_put implementation, GNU version -*- C++ -*-
2632+
2633+// Copyright (C) 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
2634+//
2635+// This file is part of the GNU ISO C++ Library. This library is free
2636+// software; you can redistribute it and/or modify it under the
2637+// terms of the GNU General Public License as published by the
2638+// Free Software Foundation; either version 2, or (at your option)
2639+// any later version.
2640+
2641+// This library is distributed in the hope that it will be useful,
2642+// but WITHOUT ANY WARRANTY; without even the implied warranty of
2643+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2644+// GNU General Public License for more details.
2645+
2646+// You should have received a copy of the GNU General Public License along
2647+// with this library; see the file COPYING. If not, write to the Free
2648+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
2649+// USA.
2650+
2651+// As a special exception, you may use this file as part of a free software
2652+// library without restriction. Specifically, if other files instantiate
2653+// templates or use macros or inline functions from this file, or you compile
2654+// this file and link it with other files to produce an executable, this
2655+// file does not by itself cause the resulting executable to be covered by
2656+// the GNU General Public License. This exception does not however
2657+// invalidate any other reasons why the executable file might be covered by
2658+// the GNU General Public License.
2659+
2660+//
2661+// ISO C++ 14882: 22.2.5.1.2 - time_get functions
2662+// ISO C++ 14882: 22.2.5.3.2 - time_put functions
2663+//
2664+
2665+// Written by Benjamin Kosnik <bkoz@redhat.com>
2666+
2667+ template<typename _CharT>
2668+ __timepunct<_CharT>::__timepunct(size_t __refs)
2669+ : facet(__refs), _M_data(NULL), _M_c_locale_timepunct(NULL),
2670+ _M_name_timepunct(_S_get_c_name())
2671+ { _M_initialize_timepunct(); }
2672+
2673+ template<typename _CharT>
2674+ __timepunct<_CharT>::__timepunct(__cache_type* __cache, size_t __refs)
2675+ : facet(__refs), _M_data(__cache), _M_c_locale_timepunct(NULL),
2676+ _M_name_timepunct(_S_get_c_name())
2677+ { _M_initialize_timepunct(); }
2678+
2679+ template<typename _CharT>
2680+ __timepunct<_CharT>::__timepunct(__c_locale __cloc, const char* __s,
2681+ size_t __refs)
2682+ : facet(__refs), _M_data(NULL), _M_c_locale_timepunct(NULL),
2683+ _M_name_timepunct(__s)
2684+ {
2685+ char* __tmp = new char[std::strlen(__s) + 1];
2686+ std::strcpy(__tmp, __s);
2687+ _M_name_timepunct = __tmp;
2688+ _M_initialize_timepunct(__cloc);
2689+ }
2690+
2691+ template<typename _CharT>
2692+ __timepunct<_CharT>::~__timepunct()
2693+ {
2694+ if (_M_name_timepunct != _S_get_c_name())
2695+ delete [] _M_name_timepunct;
2696+ delete _M_data;
2697+ _S_destroy_c_locale(_M_c_locale_timepunct);
2698+ }
2699Index: gcc-4.6.0/libstdc++-v3/configure
2700===================================================================
2701--- gcc-4.6.0.orig/libstdc++-v3/configure
2702+++ gcc-4.6.0/libstdc++-v3/configure
2703@@ -15642,7 +15642,7 @@ $as_echo "stdio" >&6; }
2704 if test "${enable_clocale+set}" = set; then :
2705 enableval=$enable_clocale;
2706 case "$enableval" in
2707- generic|gnu|ieee_1003.1-2001|yes|no|auto) ;;
2708+ generic|gnu|ieee_1003.1-2001|uclibc|yes|no|auto) ;;
2709 *) as_fn_error "Unknown argument to enable/disable clocale" "$LINENO" 5 ;;
2710 esac
2711
2712@@ -15674,6 +15674,9 @@ fi
2713 # Default to "generic".
2714 if test $enable_clocale_flag = auto; then
2715 case ${target_os} in
2716+ *-uclibc*)
2717+ enable_clocale_flag=uclibc
2718+ ;;
2719 linux* | gnu* | kfreebsd*-gnu | knetbsd*-gnu)
2720 enable_clocale_flag=gnu
2721 ;;
2722@@ -15907,6 +15910,76 @@ $as_echo "IEEE 1003.1" >&6; }
2723 CTIME_CC=config/locale/generic/time_members.cc
2724 CLOCALE_INTERNAL_H=config/locale/generic/c++locale_internal.h
2725 ;;
2726+ uclibc)
2727+ echo "$as_me:$LINENO: result: uclibc" >&5
2728+echo "${ECHO_T}uclibc" >&6
2729+
2730+ # Declare intention to use gettext, and add support for specific
2731+ # languages.
2732+ # For some reason, ALL_LINGUAS has to be before AM-GNU-GETTEXT
2733+ ALL_LINGUAS="de fr"
2734+
2735+ # Don't call AM-GNU-GETTEXT here. Instead, assume glibc.
2736+ # Extract the first word of "msgfmt", so it can be a program name with args.
2737+set dummy msgfmt; ac_word=$2
2738+echo "$as_me:$LINENO: checking for $ac_word" >&5
2739+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
2740+if test "${ac_cv_prog_check_msgfmt+set}" = set; then
2741+ echo $ECHO_N "(cached) $ECHO_C" >&6
2742+else
2743+ if test -n "$check_msgfmt"; then
2744+ ac_cv_prog_check_msgfmt="$check_msgfmt" # Let the user override the test.
2745+else
2746+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
2747+for as_dir in $PATH
2748+do
2749+ IFS=$as_save_IFS
2750+ test -z "$as_dir" && as_dir=.
2751+ for ac_exec_ext in '' $ac_executable_extensions; do
2752+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
2753+ ac_cv_prog_check_msgfmt="yes"
2754+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
2755+ break 2
2756+ fi
2757+done
2758+done
2759+
2760+ test -z "$ac_cv_prog_check_msgfmt" && ac_cv_prog_check_msgfmt="no"
2761+fi
2762+fi
2763+check_msgfmt=$ac_cv_prog_check_msgfmt
2764+if test -n "$check_msgfmt"; then
2765+ echo "$as_me:$LINENO: result: $check_msgfmt" >&5
2766+echo "${ECHO_T}$check_msgfmt" >&6
2767+else
2768+ echo "$as_me:$LINENO: result: no" >&5
2769+echo "${ECHO_T}no" >&6
2770+fi
2771+
2772+ if test x"$check_msgfmt" = x"yes" && test x"$enable_nls" = x"yes"; then
2773+ USE_NLS=yes
2774+ fi
2775+ # Export the build objects.
2776+ for ling in $ALL_LINGUAS; do \
2777+ glibcxx_MOFILES="$glibcxx_MOFILES $ling.mo"; \
2778+ glibcxx_POFILES="$glibcxx_POFILES $ling.po"; \
2779+ done
2780+
2781+
2782+
2783+ CLOCALE_H=config/locale/uclibc/c_locale.h
2784+ CLOCALE_CC=config/locale/uclibc/c_locale.cc
2785+ CCODECVT_CC=config/locale/uclibc/codecvt_members.cc
2786+ CCOLLATE_CC=config/locale/uclibc/collate_members.cc
2787+ CCTYPE_CC=config/locale/uclibc/ctype_members.cc
2788+ CMESSAGES_H=config/locale/uclibc/messages_members.h
2789+ CMESSAGES_CC=config/locale/uclibc/messages_members.cc
2790+ CMONEY_CC=config/locale/uclibc/monetary_members.cc
2791+ CNUMERIC_CC=config/locale/uclibc/numeric_members.cc
2792+ CTIME_H=config/locale/uclibc/time_members.h
2793+ CTIME_CC=config/locale/uclibc/time_members.cc
2794+ CLOCALE_INTERNAL_H=config/locale/uclibc/c++locale_internal.h
2795+ ;;
2796 esac
2797
2798 # This is where the testsuite looks for locale catalogs, using the
2799@@ -16957,6 +17030,7 @@ rm -f core conftest.err conftest.$ac_obj
2800
2801 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
2802 /* end confdefs.h. */
2803+#line 17016 "configure"
2804 #include <wctype.h>
2805 int
2806 main ()
2807@@ -64172,7 +64246,6 @@ $as_echo_n "checking for shared libgcc..
2808 fi
2809 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
2810 /* end confdefs.h. */
2811-
2812 int
2813 main ()
2814 {
2815Index: gcc-4.6.0/libstdc++-v3/include/c_compatibility/wchar.h
2816===================================================================
2817--- gcc-4.6.0.orig/libstdc++-v3/include/c_compatibility/wchar.h
2818+++ gcc-4.6.0/libstdc++-v3/include/c_compatibility/wchar.h
2819@@ -101,7 +101,9 @@ using std::wmemcmp;
2820 using std::wmemcpy;
2821 using std::wmemmove;
2822 using std::wmemset;
2823+#if _GLIBCXX_HAVE_WCSFTIME
2824 using std::wcsftime;
2825+#endif
2826
2827 #if _GLIBCXX_USE_C99
2828 using std::wcstold;
2829Index: gcc-4.6.0/libstdc++-v3/include/c_std/cwchar
2830===================================================================
2831--- gcc-4.6.0.orig/libstdc++-v3/include/c_std/cwchar
2832+++ gcc-4.6.0/libstdc++-v3/include/c_std/cwchar
2833@@ -177,7 +177,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
2834 using ::wcscoll;
2835 using ::wcscpy;
2836 using ::wcscspn;
2837+#if _GLIBCXX_HAVE_WCSFTIME
2838 using ::wcsftime;
2839+#endif
2840 using ::wcslen;
2841 using ::wcsncat;
2842 using ::wcsncmp;
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/203-uclibc-locale-no__x.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/203-uclibc-locale-no__x.patch
new file mode 100644
index 000000000..c602e913e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/203-uclibc-locale-no__x.patch
@@ -0,0 +1,235 @@
1Upstream-Status: Pending
2
3Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c++locale_internal.h
4===================================================================
5--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/c++locale_internal.h
6+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c++locale_internal.h
7@@ -60,4 +60,49 @@ extern "C" __typeof(wcsxfrm_l) __wcsxfrm
8 extern "C" __typeof(wctype_l) __wctype_l;
9 #endif
10
11+# define __nl_langinfo_l nl_langinfo_l
12+# define __strcoll_l strcoll_l
13+# define __strftime_l strftime_l
14+# define __strtod_l strtod_l
15+# define __strtof_l strtof_l
16+# define __strtold_l strtold_l
17+# define __strxfrm_l strxfrm_l
18+# define __newlocale newlocale
19+# define __freelocale freelocale
20+# define __duplocale duplocale
21+# define __uselocale uselocale
22+
23+# ifdef _GLIBCXX_USE_WCHAR_T
24+# define __iswctype_l iswctype_l
25+# define __towlower_l towlower_l
26+# define __towupper_l towupper_l
27+# define __wcscoll_l wcscoll_l
28+# define __wcsftime_l wcsftime_l
29+# define __wcsxfrm_l wcsxfrm_l
30+# define __wctype_l wctype_l
31+# endif
32+
33+#else
34+# define __nl_langinfo_l(N, L) nl_langinfo((N))
35+# define __strcoll_l(S1, S2, L) strcoll((S1), (S2))
36+# define __strtod_l(S, E, L) strtod((S), (E))
37+# define __strtof_l(S, E, L) strtof((S), (E))
38+# define __strtold_l(S, E, L) strtold((S), (E))
39+# define __strxfrm_l(S1, S2, N, L) strxfrm((S1), (S2), (N))
40+# warning should dummy __newlocale check for C|POSIX ?
41+# define __newlocale(a, b, c) NULL
42+# define __freelocale(a) ((void)0)
43+# define __duplocale(a) __c_locale()
44+//# define __uselocale ?
45+//
46+# ifdef _GLIBCXX_USE_WCHAR_T
47+# define __iswctype_l(C, M, L) iswctype((C), (M))
48+# define __towlower_l(C, L) towlower((C))
49+# define __towupper_l(C, L) towupper((C))
50+# define __wcscoll_l(S1, S2, L) wcscoll((S1), (S2))
51+//# define __wcsftime_l(S, M, F, T, L) wcsftime((S), (M), (F), (T))
52+# define __wcsxfrm_l(S1, S2, N, L) wcsxfrm((S1), (S2), (N))
53+# define __wctype_l(S, L) wctype((S))
54+# endif
55+
56 #endif // GLIBC 2.3 and later
57Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c_locale.cc
58===================================================================
59--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/c_locale.cc
60+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c_locale.cc
61@@ -39,20 +39,6 @@
62 #include <langinfo.h>
63 #include <bits/c++locale_internal.h>
64
65-#ifndef __UCLIBC_HAS_XLOCALE__
66-#define __strtol_l(S, E, B, L) strtol((S), (E), (B))
67-#define __strtoul_l(S, E, B, L) strtoul((S), (E), (B))
68-#define __strtoll_l(S, E, B, L) strtoll((S), (E), (B))
69-#define __strtoull_l(S, E, B, L) strtoull((S), (E), (B))
70-#define __strtof_l(S, E, L) strtof((S), (E))
71-#define __strtod_l(S, E, L) strtod((S), (E))
72-#define __strtold_l(S, E, L) strtold((S), (E))
73-#warning should dummy __newlocale check for C|POSIX ?
74-#define __newlocale(a, b, c) NULL
75-#define __freelocale(a) ((void)0)
76-#define __duplocale(a) __c_locale()
77-#endif
78-
79 namespace std
80 {
81 template<>
82Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/collate_members.cc
83===================================================================
84--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/collate_members.cc
85+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/collate_members.cc
86@@ -36,13 +36,6 @@
87 #include <locale>
88 #include <bits/c++locale_internal.h>
89
90-#ifndef __UCLIBC_HAS_XLOCALE__
91-#define __strcoll_l(S1, S2, L) strcoll((S1), (S2))
92-#define __strxfrm_l(S1, S2, N, L) strxfrm((S1), (S2), (N))
93-#define __wcscoll_l(S1, S2, L) wcscoll((S1), (S2))
94-#define __wcsxfrm_l(S1, S2, N, L) wcsxfrm((S1), (S2), (N))
95-#endif
96-
97 namespace std
98 {
99 // These are basically extensions to char_traits, and perhaps should
100Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/monetary_members.cc
101===================================================================
102--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/monetary_members.cc
103+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/monetary_members.cc
104@@ -43,10 +43,6 @@
105 #warning tailor for stub locale support
106 #endif
107
108-#ifndef __UCLIBC_HAS_XLOCALE__
109-#define __nl_langinfo_l(N, L) nl_langinfo((N))
110-#endif
111-
112 namespace std
113 {
114 // Construct and return valid pattern consisting of some combination of:
115Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/numeric_members.cc
116===================================================================
117--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/numeric_members.cc
118+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/numeric_members.cc
119@@ -41,9 +41,6 @@
120 #ifdef __UCLIBC_MJN3_ONLY__
121 #warning tailor for stub locale support
122 #endif
123-#ifndef __UCLIBC_HAS_XLOCALE__
124-#define __nl_langinfo_l(N, L) nl_langinfo((N))
125-#endif
126
127 namespace std
128 {
129Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/time_members.cc
130===================================================================
131--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/time_members.cc
132+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/time_members.cc
133@@ -40,9 +40,6 @@
134 #ifdef __UCLIBC_MJN3_ONLY__
135 #warning tailor for stub locale support
136 #endif
137-#ifndef __UCLIBC_HAS_XLOCALE__
138-#define __nl_langinfo_l(N, L) nl_langinfo((N))
139-#endif
140
141 namespace std
142 {
143Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/ctype_members.cc
144===================================================================
145--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/ctype_members.cc
146+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/ctype_members.cc
147@@ -38,13 +38,6 @@
148 #undef _LIBC
149 #include <bits/c++locale_internal.h>
150
151-#ifndef __UCLIBC_HAS_XLOCALE__
152-#define __wctype_l(S, L) wctype((S))
153-#define __towupper_l(C, L) towupper((C))
154-#define __towlower_l(C, L) towlower((C))
155-#define __iswctype_l(C, M, L) iswctype((C), (M))
156-#endif
157-
158 namespace std
159 {
160 // NB: The other ctype<char> specializations are in src/locale.cc and
161Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/messages_members.cc
162===================================================================
163--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/messages_members.cc
164+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/messages_members.cc
165@@ -39,13 +39,10 @@
166 #ifdef __UCLIBC_MJN3_ONLY__
167 #warning fix gettext stuff
168 #endif
169-#ifdef __UCLIBC_HAS_GETTEXT_AWARENESS__
170-extern "C" char *__dcgettext(const char *domainname,
171- const char *msgid, int category);
172 #undef gettext
173-#define gettext(msgid) __dcgettext(NULL, msgid, LC_MESSAGES)
174+#ifdef __UCLIBC_HAS_GETTEXT_AWARENESS__
175+#define gettext(msgid) dcgettext(NULL, msgid, LC_MESSAGES)
176 #else
177-#undef gettext
178 #define gettext(msgid) (msgid)
179 #endif
180
181Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/messages_members.h
182===================================================================
183--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/messages_members.h
184+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/messages_members.h
185@@ -36,15 +36,11 @@
186 #ifdef __UCLIBC_MJN3_ONLY__
187 #warning fix prototypes for *textdomain funcs
188 #endif
189-#ifdef __UCLIBC_HAS_GETTEXT_AWARENESS__
190-extern "C" char *__textdomain(const char *domainname);
191-extern "C" char *__bindtextdomain(const char *domainname,
192- const char *dirname);
193-#else
194-#undef __textdomain
195-#undef __bindtextdomain
196-#define __textdomain(D) ((void)0)
197-#define __bindtextdomain(D,P) ((void)0)
198+#ifndef __UCLIBC_HAS_GETTEXT_AWARENESS__
199+#undef textdomain
200+#undef bindtextdomain
201+#define textdomain(D) ((void)0)
202+#define bindtextdomain(D,P) ((void)0)
203 #endif
204
205 // Non-virtual member functions.
206@@ -70,7 +66,7 @@ extern "C" char *__bindtextdomain(const
207 messages<_CharT>::open(const basic_string<char>& __s, const locale& __loc,
208 const char* __dir) const
209 {
210- __bindtextdomain(__s.c_str(), __dir);
211+ bindtextdomain(__s.c_str(), __dir);
212 return this->do_open(__s, __loc);
213 }
214
215@@ -90,7 +86,7 @@ extern "C" char *__bindtextdomain(const
216 {
217 // No error checking is done, assume the catalog exists and can
218 // be used.
219- __textdomain(__s.c_str());
220+ textdomain(__s.c_str());
221 return 0;
222 }
223
224Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c_locale.h
225===================================================================
226--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/c_locale.h
227+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c_locale.h
228@@ -68,6 +68,7 @@ namespace __gnu_cxx
229 {
230 extern "C" __typeof(uselocale) __uselocale;
231 }
232+#define __uselocale uselocale
233 #endif
234
235 namespace std
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/204-uclibc-locale-wchar_fix.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/204-uclibc-locale-wchar_fix.patch
new file mode 100644
index 000000000..896d2a57c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/204-uclibc-locale-wchar_fix.patch
@@ -0,0 +1,54 @@
1Upstream-Status: Pending
2
3Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/monetary_members.cc
4===================================================================
5--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/monetary_members.cc
6+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/monetary_members.cc
7@@ -401,7 +401,7 @@ namespace std
8 # ifdef __UCLIBC_HAS_XLOCALE__
9 _M_data->_M_decimal_point = __cloc->decimal_point_wc;
10 _M_data->_M_thousands_sep = __cloc->thousands_sep_wc;
11-# else
12+# elif defined __UCLIBC_HAS_LOCALE__
13 _M_data->_M_decimal_point = __global_locale->decimal_point_wc;
14 _M_data->_M_thousands_sep = __global_locale->thousands_sep_wc;
15 # endif
16@@ -556,7 +556,7 @@ namespace std
17 # ifdef __UCLIBC_HAS_XLOCALE__
18 _M_data->_M_decimal_point = __cloc->decimal_point_wc;
19 _M_data->_M_thousands_sep = __cloc->thousands_sep_wc;
20-# else
21+# elif defined __UCLIBC_HAS_LOCALE__
22 _M_data->_M_decimal_point = __global_locale->decimal_point_wc;
23 _M_data->_M_thousands_sep = __global_locale->thousands_sep_wc;
24 # endif
25Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/numeric_members.cc
26===================================================================
27--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/numeric_members.cc
28+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/numeric_members.cc
29@@ -127,12 +127,25 @@ namespace std
30 {
31 // Named locale.
32 // NB: In the GNU model wchar_t is always 32 bit wide.
33+#ifdef __UCLIBC_MJN3_ONLY__
34+#warning fix this... should be numeric
35+#endif
36+#ifdef __UCLIBC__
37+# ifdef __UCLIBC_HAS_XLOCALE__
38+ _M_data->_M_decimal_point = __cloc->decimal_point_wc;
39+ _M_data->_M_thousands_sep = __cloc->thousands_sep_wc;
40+# elif defined __UCLIBC_HAS_LOCALE__
41+ _M_data->_M_decimal_point = __global_locale->decimal_point_wc;
42+ _M_data->_M_thousands_sep = __global_locale->thousands_sep_wc;
43+# endif
44+#else
45 union { char *__s; wchar_t __w; } __u;
46 __u.__s = __nl_langinfo_l(_NL_NUMERIC_DECIMAL_POINT_WC, __cloc);
47 _M_data->_M_decimal_point = __u.__w;
48
49 __u.__s = __nl_langinfo_l(_NL_NUMERIC_THOUSANDS_SEP_WC, __cloc);
50 _M_data->_M_thousands_sep = __u.__w;
51+#endif
52
53 if (_M_data->_M_thousands_sep == L'\0')
54 _M_data->_M_grouping = "";
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/205-uclibc-locale-update.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/205-uclibc-locale-update.patch
new file mode 100644
index 000000000..743017b4d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/205-uclibc-locale-update.patch
@@ -0,0 +1,521 @@
1Upstream-Status: Pending
2
3Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c_locale.cc
4===================================================================
5--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/c_locale.cc
6+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c_locale.cc
7@@ -39,23 +39,20 @@
8 #include <langinfo.h>
9 #include <bits/c++locale_internal.h>
10
11-namespace std
12-{
13+_GLIBCXX_BEGIN_NAMESPACE(std)
14+
15 template<>
16 void
17 __convert_to_v(const char* __s, float& __v, ios_base::iostate& __err,
18 const __c_locale& __cloc)
19 {
20- if (!(__err & ios_base::failbit))
21- {
22- char* __sanity;
23- errno = 0;
24- float __f = __strtof_l(__s, &__sanity, __cloc);
25- if (__sanity != __s && errno != ERANGE)
26- __v = __f;
27- else
28- __err |= ios_base::failbit;
29- }
30+ char* __sanity;
31+ errno = 0;
32+ float __f = __strtof_l(__s, &__sanity, __cloc);
33+ if (__sanity != __s && errno != ERANGE)
34+ __v = __f;
35+ else
36+ __err |= ios_base::failbit;
37 }
38
39 template<>
40@@ -63,16 +60,13 @@ namespace std
41 __convert_to_v(const char* __s, double& __v, ios_base::iostate& __err,
42 const __c_locale& __cloc)
43 {
44- if (!(__err & ios_base::failbit))
45- {
46- char* __sanity;
47- errno = 0;
48- double __d = __strtod_l(__s, &__sanity, __cloc);
49- if (__sanity != __s && errno != ERANGE)
50- __v = __d;
51- else
52- __err |= ios_base::failbit;
53- }
54+ char* __sanity;
55+ errno = 0;
56+ double __d = __strtod_l(__s, &__sanity, __cloc);
57+ if (__sanity != __s && errno != ERANGE)
58+ __v = __d;
59+ else
60+ __err |= ios_base::failbit;
61 }
62
63 template<>
64@@ -80,16 +74,13 @@ namespace std
65 __convert_to_v(const char* __s, long double& __v, ios_base::iostate& __err,
66 const __c_locale& __cloc)
67 {
68- if (!(__err & ios_base::failbit))
69- {
70- char* __sanity;
71- errno = 0;
72- long double __ld = __strtold_l(__s, &__sanity, __cloc);
73- if (__sanity != __s && errno != ERANGE)
74- __v = __ld;
75- else
76- __err |= ios_base::failbit;
77- }
78+ char* __sanity;
79+ errno = 0;
80+ long double __ld = __strtold_l(__s, &__sanity, __cloc);
81+ if (__sanity != __s && errno != ERANGE)
82+ __v = __ld;
83+ else
84+ __err |= ios_base::failbit;
85 }
86
87 void
88@@ -110,17 +101,18 @@ namespace std
89 void
90 locale::facet::_S_destroy_c_locale(__c_locale& __cloc)
91 {
92- if (_S_get_c_locale() != __cloc)
93+ if (__cloc && _S_get_c_locale() != __cloc)
94 __freelocale(__cloc);
95 }
96
97 __c_locale
98 locale::facet::_S_clone_c_locale(__c_locale& __cloc)
99 { return __duplocale(__cloc); }
100-} // namespace std
101
102-namespace __gnu_cxx
103-{
104+_GLIBCXX_END_NAMESPACE
105+
106+_GLIBCXX_BEGIN_NAMESPACE(__gnu_cxx)
107+
108 const char* const category_names[6 + _GLIBCXX_NUM_CATEGORIES] =
109 {
110 "LC_CTYPE",
111@@ -138,9 +130,11 @@ namespace __gnu_cxx
112 "LC_IDENTIFICATION"
113 #endif
114 };
115-}
116
117-namespace std
118-{
119+_GLIBCXX_END_NAMESPACE
120+
121+_GLIBCXX_BEGIN_NAMESPACE(std)
122+
123 const char* const* const locale::_S_categories = __gnu_cxx::category_names;
124-} // namespace std
125+
126+_GLIBCXX_END_NAMESPACE
127Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/ctype_members.cc
128===================================================================
129--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/ctype_members.cc
130+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/ctype_members.cc
131@@ -33,16 +33,20 @@
132
133 // Written by Benjamin Kosnik <bkoz@redhat.com>
134
135+#include <features.h>
136+#ifdef __UCLIBC_HAS_LOCALE__
137 #define _LIBC
138 #include <locale>
139 #undef _LIBC
140+#else
141+#include <locale>
142+#endif
143 #include <bits/c++locale_internal.h>
144
145-namespace std
146-{
147+_GLIBCXX_BEGIN_NAMESPACE(std)
148+
149 // NB: The other ctype<char> specializations are in src/locale.cc and
150 // various /config/os/* files.
151- template<>
152 ctype_byname<char>::ctype_byname(const char* __s, size_t __refs)
153 : ctype<char>(0, false, __refs)
154 {
155@@ -57,6 +61,8 @@ namespace std
156 #endif
157 }
158 }
159+ ctype_byname<char>::~ctype_byname()
160+ { }
161
162 #ifdef _GLIBCXX_USE_WCHAR_T
163 ctype<wchar_t>::__wmask_type
164@@ -138,17 +144,33 @@ namespace std
165 ctype<wchar_t>::
166 do_is(mask __m, wchar_t __c) const
167 {
168- // Highest bitmask in ctype_base == 10, but extra in "C"
169- // library for blank.
170+ // The case of __m == ctype_base::space is particularly important,
171+ // due to its use in many istream functions. Therefore we deal with
172+ // it first, exploiting the knowledge that on GNU systems _M_bit[5]
173+ // is the mask corresponding to ctype_base::space. NB: an encoding
174+ // change would not affect correctness!
175+
176 bool __ret = false;
177- const size_t __bitmasksize = 11;
178- for (size_t __bitcur = 0; __bitcur <= __bitmasksize; ++__bitcur)
179- if (__m & _M_bit[__bitcur]
180- && __iswctype_l(__c, _M_wmask[__bitcur], _M_c_locale_ctype))
181- {
182- __ret = true;
183- break;
184- }
185+ if (__m == _M_bit[5])
186+ __ret = __iswctype_l(__c, _M_wmask[5], _M_c_locale_ctype);
187+ else
188+ {
189+ // Highest bitmask in ctype_base == 10, but extra in "C"
190+ // library for blank.
191+ const size_t __bitmasksize = 11;
192+ for (size_t __bitcur = 0; __bitcur <= __bitmasksize; ++__bitcur)
193+ if (__m & _M_bit[__bitcur])
194+ {
195+ if (__iswctype_l(__c, _M_wmask[__bitcur], _M_c_locale_ctype))
196+ {
197+ __ret = true;
198+ break;
199+ }
200+ else if (__m == _M_bit[__bitcur])
201+ break;
202+ }
203+ }
204+
205 return __ret;
206 }
207
208@@ -290,4 +312,5 @@ namespace std
209 #endif
210 }
211 #endif // _GLIBCXX_USE_WCHAR_T
212-}
213+
214+_GLIBCXX_END_NAMESPACE
215Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/messages_members.h
216===================================================================
217--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/messages_members.h
218+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/messages_members.h
219@@ -53,12 +53,16 @@
220 template<typename _CharT>
221 messages<_CharT>::messages(__c_locale __cloc, const char* __s,
222 size_t __refs)
223- : facet(__refs), _M_c_locale_messages(_S_clone_c_locale(__cloc)),
224- _M_name_messages(__s)
225+ : facet(__refs), _M_c_locale_messages(NULL),
226+ _M_name_messages(NULL)
227 {
228- char* __tmp = new char[std::strlen(__s) + 1];
229- std::strcpy(__tmp, __s);
230+ const size_t __len = std::strlen(__s) + 1;
231+ char* __tmp = new char[__len];
232+ std::memcpy(__tmp, __s, __len);
233 _M_name_messages = __tmp;
234+
235+ // Last to avoid leaking memory if new throws.
236+ _M_c_locale_messages = _S_clone_c_locale(__cloc);
237 }
238
239 template<typename _CharT>
240Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/monetary_members.cc
241===================================================================
242--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/monetary_members.cc
243+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/monetary_members.cc
244@@ -33,9 +33,14 @@
245
246 // Written by Benjamin Kosnik <bkoz@redhat.com>
247
248+#include <features.h>
249+#ifdef __UCLIBC_HAS_LOCALE__
250 #define _LIBC
251 #include <locale>
252 #undef _LIBC
253+#else
254+#include <locale>
255+#endif
256 #include <bits/c++locale_internal.h>
257
258 #ifdef __UCLIBC_MJN3_ONLY__
259@@ -206,7 +211,7 @@ namespace std
260 }
261 break;
262 default:
263- ;
264+ __ret = pattern();
265 }
266 return __ret;
267 }
268@@ -390,7 +395,9 @@ namespace std
269 __c_locale __old = __uselocale(__cloc);
270 #else
271 // Switch to named locale so that mbsrtowcs will work.
272- char* __old = strdup(setlocale(LC_ALL, NULL));
273+ char* __old = setlocale(LC_ALL, NULL);
274+ const size_t __llen = strlen(__old) + 1;
275+ char* __sav = new char[__llen];
276 setlocale(LC_ALL, __name);
277 #endif
278
279@@ -477,8 +484,8 @@ namespace std
280 #ifdef __UCLIBC_HAS_XLOCALE__
281 __uselocale(__old);
282 #else
283- setlocale(LC_ALL, __old);
284- free(__old);
285+ setlocale(LC_ALL, __sav);
286+ delete [] __sav;
287 #endif
288 __throw_exception_again;
289 }
290@@ -498,8 +505,8 @@ namespace std
291 #ifdef __UCLIBC_HAS_XLOCALE__
292 __uselocale(__old);
293 #else
294- setlocale(LC_ALL, __old);
295- free(__old);
296+ setlocale(LC_ALL, __sav);
297+ delete [] __sav;
298 #endif
299 }
300 }
301@@ -545,8 +552,11 @@ namespace std
302 __c_locale __old = __uselocale(__cloc);
303 #else
304 // Switch to named locale so that mbsrtowcs will work.
305- char* __old = strdup(setlocale(LC_ALL, NULL));
306- setlocale(LC_ALL, __name);
307+ char* __old = setlocale(LC_ALL, NULL);
308+ const size_t __llen = strlen(__old) + 1;
309+ char* __sav = new char[__llen];
310+ memcpy(__sav, __old, __llen);
311+ setlocale(LC_ALL, __name);
312 #endif
313
314 #ifdef __UCLIBC_MJN3_ONLY__
315@@ -633,8 +643,8 @@ namespace std
316 #ifdef __UCLIBC_HAS_XLOCALE__
317 __uselocale(__old);
318 #else
319- setlocale(LC_ALL, __old);
320- free(__old);
321+ setlocale(LC_ALL, __sav);
322+ delete [] __sav;
323 #endif
324 __throw_exception_again;
325 }
326@@ -653,8 +663,8 @@ namespace std
327 #ifdef __UCLIBC_HAS_XLOCALE__
328 __uselocale(__old);
329 #else
330- setlocale(LC_ALL, __old);
331- free(__old);
332+ setlocale(LC_ALL, __sav);
333+ delete [] __sav;
334 #endif
335 }
336 }
337Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/numeric_members.cc
338===================================================================
339--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/numeric_members.cc
340+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/numeric_members.cc
341@@ -33,9 +33,14 @@
342
343 // Written by Benjamin Kosnik <bkoz@redhat.com>
344
345+#include <features.h>
346+#ifdef __UCLIBC_HAS_LOCALE__
347 #define _LIBC
348 #include <locale>
349 #undef _LIBC
350+#else
351+#include <locale>
352+#endif
353 #include <bits/c++locale_internal.h>
354
355 #ifdef __UCLIBC_MJN3_ONLY__
356Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/time_members.h
357===================================================================
358--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/time_members.h
359+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/time_members.h
360@@ -50,12 +50,21 @@
361 __timepunct<_CharT>::__timepunct(__c_locale __cloc, const char* __s,
362 size_t __refs)
363 : facet(__refs), _M_data(NULL), _M_c_locale_timepunct(NULL),
364- _M_name_timepunct(__s)
365+ _M_name_timepunct(NULL)
366 {
367- char* __tmp = new char[std::strlen(__s) + 1];
368- std::strcpy(__tmp, __s);
369+ const size_t __len = std::strlen(__s) + 1;
370+ char* __tmp = new char[__len];
371+ std::memcpy(__tmp, __s, __len);
372 _M_name_timepunct = __tmp;
373- _M_initialize_timepunct(__cloc);
374+
375+ try
376+ { _M_initialize_timepunct(__cloc); }
377+ catch(...)
378+ {
379+ delete [] _M_name_timepunct;
380+ __throw_exception_again;
381+ }
382+
383 }
384
385 template<typename _CharT>
386Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c_locale.h
387===================================================================
388--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/c_locale.h
389+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c_locale.h
390@@ -39,21 +39,23 @@
391 #pragma GCC system_header
392
393 #include <cstring> // get std::strlen
394-#include <cstdio> // get std::snprintf or std::sprintf
395+#include <cstdio> // get std::vsnprintf or std::vsprintf
396 #include <clocale>
397 #include <langinfo.h> // For codecvt
398 #ifdef __UCLIBC_MJN3_ONLY__
399 #warning fix this
400 #endif
401-#ifdef __UCLIBC_HAS_LOCALE__
402+#ifdef _GLIBCXX_USE_ICONV
403 #include <iconv.h> // For codecvt using iconv, iconv_t
404 #endif
405-#ifdef __UCLIBC_HAS_GETTEXT_AWARENESS__
406-#include <libintl.h> // For messages
407+#ifdef HAVE_LIBINTL_H
408+#include <libintl.h> // For messages
409 #endif
410+#include <cstdarg>
411
412 #ifdef __UCLIBC_MJN3_ONLY__
413 #warning what is _GLIBCXX_C_LOCALE_GNU for
414+// psm: used in os/gnu-linux/ctype_noninline.h
415 #endif
416 #define _GLIBCXX_C_LOCALE_GNU 1
417
418@@ -78,23 +80,25 @@ namespace std
419 #else
420 typedef int* __c_locale;
421 #endif
422-
423- // Convert numeric value of type _Tv to string and return length of
424- // string. If snprintf is available use it, otherwise fall back to
425- // the unsafe sprintf which, in general, can be dangerous and should
426+ // Convert numeric value of type double to string and return length of
427+ // string. If vsnprintf is available use it, otherwise fall back to
428+ // the unsafe vsprintf which, in general, can be dangerous and should
429 // be avoided.
430- template<typename _Tv>
431- int
432- __convert_from_v(char* __out,
433- const int __size __attribute__ ((__unused__)),
434- const char* __fmt,
435-#ifdef __UCLIBC_HAS_XCLOCALE__
436- _Tv __v, const __c_locale& __cloc, int __prec)
437+ inline int
438+ __convert_from_v(const __c_locale&
439+#ifndef __UCLIBC_HAS_XCLOCALE__
440+ __cloc __attribute__ ((__unused__))
441+#endif
442+ ,
443+ char* __out,
444+ const int __size,
445+ const char* __fmt, ...)
446 {
447+ va_list __args;
448+#ifdef __UCLIBC_HAS_XCLOCALE__
449+
450 __c_locale __old = __gnu_cxx::__uselocale(__cloc);
451 #else
452- _Tv __v, const __c_locale&, int __prec)
453- {
454 # ifdef __UCLIBC_HAS_LOCALE__
455 char* __old = std::setlocale(LC_ALL, NULL);
456 char* __sav = new char[std::strlen(__old) + 1];
457@@ -103,7 +107,9 @@ namespace std
458 # endif
459 #endif
460
461- const int __ret = std::snprintf(__out, __size, __fmt, __prec, __v);
462+ va_start(__args, __fmt);
463+ const int __ret = std::vsnprintf(__out, __size, __fmt, __args);
464+ va_end(__args);
465
466 #ifdef __UCLIBC_HAS_XCLOCALE__
467 __gnu_cxx::__uselocale(__old);
468Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/time_members.cc
469===================================================================
470--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/time_members.cc
471+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/time_members.cc
472@@ -53,11 +53,14 @@ namespace std
473 const size_t __len = __strftime_l(__s, __maxlen, __format, __tm,
474 _M_c_locale_timepunct);
475 #else
476- char* __old = strdup(setlocale(LC_ALL, NULL));
477+ char* __old = setlocale(LC_ALL, NULL);
478+ const size_t __llen = strlen(__old) + 1;
479+ char* __sav = new char[__llen];
480+ memcpy(__sav, __old, __llen);
481 setlocale(LC_ALL, _M_name_timepunct);
482 const size_t __len = strftime(__s, __maxlen, __format, __tm);
483- setlocale(LC_ALL, __old);
484- free(__old);
485+ setlocale(LC_ALL, __sav);
486+ delete [] __sav;
487 #endif
488 // Make sure __s is null terminated.
489 if (__len == 0)
490@@ -207,11 +210,14 @@ namespace std
491 const size_t __len = __wcsftime_l(__s, __maxlen, __format, __tm,
492 _M_c_locale_timepunct);
493 #else
494- char* __old = strdup(setlocale(LC_ALL, NULL));
495+ char* __old = setlocale(LC_ALL, NULL);
496+ const size_t __llen = strlen(__old) + 1;
497+ char* __sav = new char[__llen];
498+ memcpy(__sav, __old, __llen);
499 setlocale(LC_ALL, _M_name_timepunct);
500 const size_t __len = wcsftime(__s, __maxlen, __format, __tm);
501- setlocale(LC_ALL, __old);
502- free(__old);
503+ setlocale(LC_ALL, __sav);
504+ delete [] __sav;
505 #endif
506 // Make sure __s is null terminated.
507 if (__len == 0)
508Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c++locale_internal.h
509===================================================================
510--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/c++locale_internal.h
511+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/c++locale_internal.h
512@@ -31,6 +31,9 @@
513
514 #include <bits/c++config.h>
515 #include <clocale>
516+#include <cstdlib>
517+#include <cstring>
518+#include <cstddef>
519
520 #ifdef __UCLIBC_MJN3_ONLY__
521 #warning clean this up
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/301-missing-execinfo_h.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/301-missing-execinfo_h.patch
new file mode 100644
index 000000000..9589822b8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/301-missing-execinfo_h.patch
@@ -0,0 +1,15 @@
1Upstream-Status: Pending
2
3Index: gcc-4.6.0/boehm-gc/include/gc.h
4===================================================================
5--- gcc-4.6.0.orig/boehm-gc/include/gc.h
6+++ gcc-4.6.0/boehm-gc/include/gc.h
7@@ -503,7 +503,7 @@ GC_API GC_PTR GC_malloc_atomic_ignore_of
8 #if defined(__linux__) || defined(__GLIBC__)
9 # include <features.h>
10 # if (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 1 || __GLIBC__ > 2) \
11- && !defined(__ia64__)
12+ && !defined(__ia64__) && !defined(__UCLIBC__)
13 # ifndef GC_HAVE_BUILTIN_BACKTRACE
14 # define GC_HAVE_BUILTIN_BACKTRACE
15 # endif
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/302-c99-snprintf.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/302-c99-snprintf.patch
new file mode 100644
index 000000000..f02c98dec
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/302-c99-snprintf.patch
@@ -0,0 +1,15 @@
1Upstream-Status: Pending
2
3Index: gcc-4.6.0/libstdc++-v3/include/c_std/cstdio
4===================================================================
5--- gcc-4.6.0.orig/libstdc++-v3/include/c_std/cstdio
6+++ gcc-4.6.0/libstdc++-v3/include/c_std/cstdio
7@@ -136,7 +136,7 @@ namespace std
8 using ::vsprintf;
9 } // namespace std
10
11-#if _GLIBCXX_USE_C99
12+#if _GLIBCXX_USE_C99 || defined(__UCLIBC__)
13
14 #undef snprintf
15 #undef vfscanf
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/303-c99-complex-ugly-hack.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/303-c99-complex-ugly-hack.patch
new file mode 100644
index 000000000..db594cbb1
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/303-c99-complex-ugly-hack.patch
@@ -0,0 +1,16 @@
1Upstream-Status: Inappropriate [embedded specific]
2
3Index: gcc-4.6.0/libstdc++-v3/configure
4===================================================================
5--- gcc-4.6.0.orig/libstdc++-v3/configure
6+++ gcc-4.6.0/libstdc++-v3/configure
7@@ -18302,6 +18302,9 @@ $as_echo_n "checking for ISO C99 support
8 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
9 /* end confdefs.h. */
10 #include <complex.h>
11+#ifdef __UCLIBC__
12+#error ugly hack to make sure configure test fails here for cross until uClibc supports the complex funcs
13+#endif
14 int
15 main ()
16 {
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/304-index_macro.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/304-index_macro.patch
new file mode 100644
index 000000000..f10376523
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/304-index_macro.patch
@@ -0,0 +1,30 @@
1Upstream-Status: Pending
2
3Index: gcc-4.6.0/libstdc++-v3/include/ext/rope
4===================================================================
5--- gcc-4.6.0.orig/libstdc++-v3/include/ext/rope
6+++ gcc-4.6.0/libstdc++-v3/include/ext/rope
7@@ -54,6 +54,9 @@
8 #include <bits/gthr.h>
9 #include <tr1/functional>
10
11+/* cope w/ index defined as macro, SuSv3 proposal */
12+#undef index
13+
14 # ifdef __GC
15 # define __GC_CONST const
16 # else
17Index: gcc-4.6.0/libstdc++-v3/include/ext/ropeimpl.h
18===================================================================
19--- gcc-4.6.0.orig/libstdc++-v3/include/ext/ropeimpl.h
20+++ gcc-4.6.0/libstdc++-v3/include/ext/ropeimpl.h
21@@ -49,6 +49,9 @@
22 #include <ext/memory> // For uninitialized_copy_n
23 #include <ext/numeric> // For power
24
25+/* cope w/ index defined as macro, SuSv3 proposal */
26+#undef index
27+
28 namespace __gnu_cxx _GLIBCXX_VISIBILITY(default)
29 {
30 _GLIBCXX_BEGIN_NAMESPACE_VERSION
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/305-libmudflap-susv3-legacy.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/305-libmudflap-susv3-legacy.patch
new file mode 100644
index 000000000..8d9a4d870
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/305-libmudflap-susv3-legacy.patch
@@ -0,0 +1,51 @@
1Upstream-Status: Inappropriate [embedded specific]
2
3Index: gcc-4.6.0/libmudflap/mf-hooks2.c
4===================================================================
5--- gcc-4.6.0.orig/libmudflap/mf-hooks2.c
6+++ gcc-4.6.0/libmudflap/mf-hooks2.c
7@@ -421,7 +421,7 @@ WRAPPER2(void, bzero, void *s, size_t n)
8 {
9 TRACE ("%s\n", __PRETTY_FUNCTION__);
10 MF_VALIDATE_EXTENT(s, n, __MF_CHECK_WRITE, "bzero region");
11- bzero (s, n);
12+ memset (s, 0, n);
13 }
14
15
16@@ -431,7 +431,7 @@ WRAPPER2(void, bcopy, const void *src, v
17 TRACE ("%s\n", __PRETTY_FUNCTION__);
18 MF_VALIDATE_EXTENT(src, n, __MF_CHECK_READ, "bcopy src");
19 MF_VALIDATE_EXTENT(dest, n, __MF_CHECK_WRITE, "bcopy dest");
20- bcopy (src, dest, n);
21+ memmove (dest, src, n);
22 }
23
24
25@@ -441,7 +441,7 @@ WRAPPER2(int, bcmp, const void *s1, cons
26 TRACE ("%s\n", __PRETTY_FUNCTION__);
27 MF_VALIDATE_EXTENT(s1, n, __MF_CHECK_READ, "bcmp 1st arg");
28 MF_VALIDATE_EXTENT(s2, n, __MF_CHECK_READ, "bcmp 2nd arg");
29- return bcmp (s1, s2, n);
30+ return n == 0 ? 0 : memcmp (s1, s2, n);
31 }
32
33
34@@ -450,7 +450,7 @@ WRAPPER2(char *, index, const char *s, i
35 size_t n = strlen (s);
36 TRACE ("%s\n", __PRETTY_FUNCTION__);
37 MF_VALIDATE_EXTENT(s, CLAMPADD(n, 1), __MF_CHECK_READ, "index region");
38- return index (s, c);
39+ return strchr (s, c);
40 }
41
42
43@@ -459,7 +459,7 @@ WRAPPER2(char *, rindex, const char *s,
44 size_t n = strlen (s);
45 TRACE ("%s\n", __PRETTY_FUNCTION__);
46 MF_VALIDATE_EXTENT(s, CLAMPADD(n, 1), __MF_CHECK_READ, "rindex region");
47- return rindex (s, c);
48+ return strrchr (s, c);
49 }
50
51 /* XXX: stpcpy, memccpy */
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/306-libstdc++-namespace.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/306-libstdc++-namespace.patch
new file mode 100644
index 000000000..e99bf9602
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/306-libstdc++-namespace.patch
@@ -0,0 +1,40 @@
1Upstream-Status: Pending
2
3Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/messages_members.h
4===================================================================
5--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/messages_members.h
6+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/messages_members.h
7@@ -32,7 +32,8 @@
8 //
9
10 // Written by Benjamin Kosnik <bkoz@redhat.com>
11-
12+namespace std
13+{
14 #ifdef __UCLIBC_MJN3_ONLY__
15 #warning fix prototypes for *textdomain funcs
16 #endif
17@@ -116,3 +117,4 @@
18 this->_S_create_c_locale(this->_M_c_locale_messages, __s);
19 }
20 }
21+}
22Index: gcc-4.6.0/libstdc++-v3/config/locale/uclibc/time_members.h
23===================================================================
24--- gcc-4.6.0.orig/libstdc++-v3/config/locale/uclibc/time_members.h
25+++ gcc-4.6.0/libstdc++-v3/config/locale/uclibc/time_members.h
26@@ -33,7 +33,8 @@
27 //
28
29 // Written by Benjamin Kosnik <bkoz@redhat.com>
30-
31+namespace std
32+{
33 template<typename _CharT>
34 __timepunct<_CharT>::__timepunct(size_t __refs)
35 : facet(__refs), _M_data(NULL), _M_c_locale_timepunct(NULL),
36@@ -75,3 +76,4 @@
37 delete _M_data;
38 _S_destroy_c_locale(_M_c_locale_timepunct);
39 }
40+}
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/64bithack.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/64bithack.patch
new file mode 100644
index 000000000..d35753a06
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/64bithack.patch
@@ -0,0 +1,68 @@
1Upstream-Status: Inappropriate [embedded specific]
2
3GCC has internal multilib handling code but it assumes a very specific rigid directory
4layout. The build system implementation of multilib layout is very generic and allows
5complete customisation of the library directories.
6
7This patch is a partial solution to allow any custom directories to be passed into gcc
8and handled correctly. It forces gcc to use the base_libdir (which is the current
9directory, "."). We need to do this for each multilib that is configured as we don't
10know which compiler options may be being passed into the compiler. Since we have a compiler
11per mulitlib at this point that isn't an issue.
12
13The one problem is the target compiler is only going to work for the default multlilib at
14this point. Ideally we'd figure out which multilibs were being enabled with which paths
15and be able to patch these entries with a complete set of correct paths but this we
16don't have such code at this point. This is something the target gcc recipe should do
17and override these platform defaults in its build config.
18
19RP 15/8/11
20
21Index: gcc-4_6-branch/gcc/config/i386/t-linux64
22===================================================================
23--- gcc-4_6-branch.orig/gcc/config/i386/t-linux64 2011-06-23 15:15:29.000000000 +0100
24+++ gcc-4_6-branch/gcc/config/i386/t-linux64 2011-08-15 13:09:03.772415848 +0100
25@@ -24,8 +24,8 @@
26 # MULTILIB_OSDIRNAMES according to what is found on the target.
27
28 MULTILIB_OPTIONS = m64/m32
29-MULTILIB_DIRNAMES = 64 32
30-MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)
31+MULTILIB_DIRNAMES = . .
32+MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir))
33
34 LIBGCC = stmp-multilib
35 INSTALL_LIBGCC = install-multilib
36Index: gcc-4_6-branch/gcc/config/mips/t-linux64
37===================================================================
38--- gcc-4_6-branch.orig/gcc/config/mips/t-linux64 2011-08-15 13:06:13.732415763 +0100
39+++ gcc-4_6-branch/gcc/config/mips/t-linux64 2011-08-15 13:09:11.452419446 +0100
40@@ -17,8 +17,8 @@
41 # <http://www.gnu.org/licenses/>.
42
43 MULTILIB_OPTIONS = mabi=n32/mabi=32/mabi=64
44-MULTILIB_DIRNAMES = n32 32 64
45-MULTILIB_OSDIRNAMES = ../lib32 ../lib ../lib64
46+MULTILIB_DIRNAMES = . . .
47+MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir))
48
49 EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o
50
51Index: gcc-4_6-branch/gcc/config/rs6000/t-linux64
52===================================================================
53--- gcc-4_6-branch.orig/gcc/config/rs6000/t-linux64 2011-08-15 13:06:25.272415822 +0100
54+++ gcc-4_6-branch/gcc/config/rs6000/t-linux64 2011-08-15 13:09:21.062415878 +0100
55@@ -32,11 +32,11 @@
56 # MULTILIB_OSDIRNAMES according to what is found on the target.
57
58 MULTILIB_OPTIONS = m64/m32 msoft-float
59-MULTILIB_DIRNAMES = 64 32 nof
60+MULTILIB_DIRNAMES = . . .
61 MULTILIB_EXTRA_OPTS = fPIC mstrict-align
62 MULTILIB_EXCEPTIONS = m64/msoft-float
63 MULTILIB_EXCLUSIONS = m64/!m32/msoft-float
64-MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) nof
65+MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir))
66 MULTILIB_MATCHES = $(MULTILIB_MATCHES_FLOAT)
67
68 softfp_wrap_start := '\#ifndef __powerpc64__'
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/740-sh-pr24836.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/740-sh-pr24836.patch
new file mode 100644
index 000000000..bc4ea5d86
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/740-sh-pr24836.patch
@@ -0,0 +1,31 @@
1Upstream-Status: Pending
2
3http://sourceforge.net/mailarchive/forum.php?thread_id=8959304&forum_id=5348
4http://gcc.gnu.org/bugzilla/show_bug.cgi?id=24836
5
6Index: gcc-4.6.0/gcc/configure.ac
7===================================================================
8--- gcc-4.6.0.orig/gcc/configure.ac
9+++ gcc-4.6.0/gcc/configure.ac
10@@ -2926,7 +2926,7 @@ foo: .long 25
11 tls_first_minor=14
12 tls_as_opt="-m64 -Aesame --fatal-warnings"
13 ;;
14- sh-*-* | sh[34]-*-*)
15+ sh-*-* | sh[34]*-*-*)
16 conftest_s='
17 .section ".tdata","awT",@progbits
18 foo: .long 25
19Index: gcc-4.6.0/gcc/configure
20===================================================================
21--- gcc-4.6.0.orig/gcc/configure
22+++ gcc-4.6.0/gcc/configure
23@@ -22756,7 +22756,7 @@ foo: .long 25
24 tls_first_minor=14
25 tls_as_opt="-m64 -Aesame --fatal-warnings"
26 ;;
27- sh-*-* | sh[34]-*-*)
28+ sh-*-* | sh[34]*-*-*)
29 conftest_s='
30 .section ".tdata","awT",@progbits
31 foo: .long 25
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/800-arm-bigendian.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/800-arm-bigendian.patch
new file mode 100644
index 000000000..8c8046d4c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/800-arm-bigendian.patch
@@ -0,0 +1,36 @@
1Upstream-Status: Pending
2
3By Lennert Buytenhek <buytenh@wantstofly.org>
4Adds support for arm*b-linux* big-endian ARM targets
5
6See http://gcc.gnu.org/PR16350
7
8Index: gcc-4.6.0/gcc/config/arm/linux-elf.h
9===================================================================
10--- gcc-4.6.0.orig/gcc/config/arm/linux-elf.h
11+++ gcc-4.6.0/gcc/config/arm/linux-elf.h
12@@ -51,7 +51,7 @@
13
14 #undef MULTILIB_DEFAULTS
15 #define MULTILIB_DEFAULTS \
16- { "marm", "mlittle-endian", "mhard-float", "mno-thumb-interwork" }
17+ { "marm", TARGET_ENDIAN_OPTION, "mhard-float", "mno-thumb-interwork" }
18
19 /* Now we define the strings used to build the spec file. */
20 #undef LIB_SPEC
21Index: gcc-4.6.0/gcc/config.gcc
22===================================================================
23--- gcc-4.6.0.orig/gcc/config.gcc
24+++ gcc-4.6.0/gcc/config.gcc
25@@ -822,6 +822,11 @@ arm*-*-linux*) # ARM GNU/Linux with EL
26 esac
27 tmake_file="${tmake_file} t-linux arm/t-arm"
28 case ${target} in
29+ arm*b-*)
30+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
31+ ;;
32+ esac
33+ case ${target} in
34 arm*-*-linux-*eabi)
35 tm_file="$tm_file arm/bpabi.h arm/linux-eabi.h"
36 tm_file="$tm_file ../../libgcc/config/arm/bpabi-lib.h"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/904-flatten-switch-stmt-00.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/904-flatten-switch-stmt-00.patch
new file mode 100644
index 000000000..ce3e6b584
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/904-flatten-switch-stmt-00.patch
@@ -0,0 +1,76 @@
1Upstream-Status: Pending
2
3Hi,
4
5The attached patch makes sure that we create smaller object code for
6simple switch statements. We just make sure to flatten the switch
7statement into an if-else chain, basically.
8
9This fixes a size-regression as compared to gcc-3.4, as can be seen
10below.
11
122007-04-15 Bernhard Fischer <..>
13
14 * stmt.c (expand_case): Do not create a complex binary tree when
15 optimizing for size but rather use the simple ordered list.
16 (emit_case_nodes): do not emit jumps to the default_label when
17 optimizing for size.
18
19Not regtested so far.
20Comments?
21
22Attached is the test switch.c mentioned below.
23
24$ for i in 2.95 3.3 3.4 4.0 4.1 4.2.orig-HEAD 4.3.orig-HEAD 4.3-HEAD;do
25gcc-$i -DCHAIN -Os -o switch-CHAIN-$i.o -c switch.c ;done
26$ for i in 2.95 3.3 3.4 4.0 4.1 4.2.orig-HEAD 4.3.orig-HEAD 4.3-HEAD;do
27gcc-$i -UCHAIN -Os -o switch-$i.o -c switch.c ;done
28
29$ size switch-*.o
30 text data bss dec hex filename
31 169 0 0 169 a9 switch-2.95.o
32 115 0 0 115 73 switch-3.3.o
33 103 0 0 103 67 switch-3.4.o
34 124 0 0 124 7c switch-4.0.o
35 124 0 0 124 7c switch-4.1.o
36 124 0 0 124 7c switch-4.2.orig-HEAD.o
37 95 0 0 95 5f switch-4.3-HEAD.o
38 124 0 0 124 7c switch-4.3.orig-HEAD.o
39 166 0 0 166 a6 switch-CHAIN-2.95.o
40 111 0 0 111 6f switch-CHAIN-3.3.o
41 95 0 0 95 5f switch-CHAIN-3.4.o
42 95 0 0 95 5f switch-CHAIN-4.0.o
43 95 0 0 95 5f switch-CHAIN-4.1.o
44 95 0 0 95 5f switch-CHAIN-4.2.orig-HEAD.o
45 95 0 0 95 5f switch-CHAIN-4.3-HEAD.o
46 95 0 0 95 5f switch-CHAIN-4.3.orig-HEAD.o
47
48
49Content-Type: text/x-diff; charset=us-ascii
50Content-Disposition: attachment; filename="gcc-4.3.gcc-flatten-switch-stmt.00.diff"
51
52Index: gcc-4.6.0/gcc/stmt.c
53===================================================================
54--- gcc-4.6.0.orig/gcc/stmt.c
55+++ gcc-4.6.0/gcc/stmt.c
56@@ -2478,7 +2478,11 @@ expand_case (gimple stmt)
57 default code is emitted. */
58
59 use_cost_table = estimate_case_costs (case_list);
60- balance_case_nodes (&case_list, NULL);
61+ /* When optimizing for size, we want a straight list to avoid
62+ jumps as much as possible. This basically creates an if-else
63+ chain. */
64+ if (!optimize_size)
65+ balance_case_nodes (&case_list, NULL);
66 emit_case_nodes (index, case_list, default_label, index_type);
67 if (default_label)
68 emit_jump (default_label);
69@@ -3046,6 +3050,7 @@ emit_case_nodes (rtx index, case_node_pt
70 {
71 if (!node_has_low_bound (node, index_type))
72 {
73+ if (!optimize_size) /* don't jl to the .default_label. */
74 emit_cmp_and_jump_insns (index,
75 convert_modes
76 (mode, imode,
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/COLLECT_GCC_OPTIONS.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/COLLECT_GCC_OPTIONS.patch
new file mode 100644
index 000000000..38856c2d8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/COLLECT_GCC_OPTIONS.patch
@@ -0,0 +1,25 @@
1Upstream-Status: Pending
2
3#This patck added --sysroot into COLLECT_GCC_OPTIONS which is used to
4#invoke collect2.
5
6Index: gcc-4.6.0/gcc/gcc.c
7===================================================================
8--- gcc-4.6.0.orig/gcc/gcc.c
9+++ gcc-4.6.0/gcc/gcc.c
10@@ -3948,6 +3948,15 @@ set_collect_gcc_options (void)
11 sizeof ("COLLECT_GCC_OPTIONS=") - 1);
12
13 first_time = TRUE;
14+#ifdef HAVE_LD_SYSROOT
15+ if (target_system_root_changed && target_system_root)
16+ {
17+ obstack_grow (&collect_obstack, "'--sysroot=", sizeof("'--sysroot=")-1);
18+ obstack_grow (&collect_obstack, target_system_root,strlen(target_system_root));
19+ obstack_grow (&collect_obstack, "'", 1);
20+ first_time = FALSE;
21+ }
22+#endif
23 for (i = 0; (int) i < n_switches; i++)
24 {
25 const char *const *args;
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch
new file mode 100644
index 000000000..575e0e4b4
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch
@@ -0,0 +1,186 @@
1source: http://patchwork.ozlabs.org/patch/129800/
2Upstream-Status: Submitted
3
4ChangeLog
5 * Makefile.in (gcc_gxx_include_dir_add_sysroot): New.
6 (PREPROCESSOR_DEFINES): Define GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT.
7
8 * cppdefault.c (cpp_include_defaults): replace hard coded "1" with
9 GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT for "add_sysroot" field.
10
11 * configure.ac (AC_SUBST): Add gcc_gxx_include_dir_add_sysroot to
12 control whether sysroot should be prepended to gxx include dir.
13
14 * configure: Regenerate.
15
16Hi, this is a follow up for issue "http://codereview.appspot.com/4641076".
17
18The rationale for the patch copied from previous thread:
19=======================================
20The setup:
21
22Configuring a toolchain targeting x86-64 GNU Linux (Ubuntu Lucid), as a
23cross-compiler. Using a sysroot to provide the Lucid headers+libraries,
24with the sysroot path being within the GCC install tree. Want to use the
25Lucid system libstdc++ and headers, which means that I'm not
26building/installing libstdc++-v3.
27
28So, configuring with:
29 --with-sysroot="$SYSROOT"
30 --disable-libstdc++-v3 \
31 --with-gxx-include-dir="$SYSROOT/usr/include/c++/4.4" \
32(among other options).
33
34Hoping to support two usage models with this configuration, w.r.t. use of
35the sysroot:
36
37(1) somebody installs the sysroot in the normal location relative to the
38GCC install, and relocates the whole bundle (sysroot+GCC). This works
39great AFAICT, GCC finds its includes (including the C++ includes) thanks
40to the add_standard_paths iprefix handling.
41
42(2) somebody installs the sysroot in a non-standard location, and uses
43--sysroot to try to access it. This works fine for the C headers, but
44doesn't work.
45
46For the C headers, add_standard_paths prepends the sysroot location to
47the /usr/include path (since that's what's specified in cppdefault.c for
48that path). It doesn't do the same for the C++ include path, though
49(again, as specified in cppdefault.c).
50
51add_standard_paths doesn't attempt to relocate built-in include paths that
52start with the compiled-in sysroot location (e.g., the g++ include dir, in
53this case). This isn't surprising really: normally you either prepend the
54sysroot location or you don't (as specified by cppdefault.c); none of the
55built-in paths normally *start* with the sysroot location and need to be
56relocated. However, in this odd-ball case of trying to use the C++ headers
57from the sysroot, one of the paths *does* need to be relocated in this way.
58===========================
59Index: gcc-4_6-branch/gcc/Makefile.in
60===================================================================
61--- gcc-4_6-branch.orig/gcc/Makefile.in 2012-03-04 09:33:36.000000000 -0800
62+++ gcc-4_6-branch/gcc/Makefile.in 2012-03-04 09:41:06.858672113 -0800
63@@ -587,6 +587,7 @@
64 build_tooldir = $(exec_prefix)/$(target_noncanonical)
65 # Directory in which the compiler finds target-independent g++ includes.
66 gcc_gxx_include_dir = @gcc_gxx_include_dir@
67+gcc_gxx_include_dir_add_sysroot = @gcc_gxx_include_dir_add_sysroot@
68 # Directory to search for site-specific includes.
69 local_includedir = $(local_prefix)/include
70 includedir = $(prefix)/include
71@@ -3964,6 +3965,7 @@
72 -DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \
73 -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \
74 -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \
75+ -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \
76 -DGPLUSPLUS_TOOL_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/$(target_noncanonical)\" \
77 -DGPLUSPLUS_BACKWARD_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/backward\" \
78 -DLOCAL_INCLUDE_DIR=\"$(local_includedir)\" \
79Index: gcc-4_6-branch/gcc/configure.ac
80===================================================================
81--- gcc-4_6-branch.orig/gcc/configure.ac 2012-03-04 09:33:36.000000000 -0800
82+++ gcc-4_6-branch/gcc/configure.ac 2012-03-04 09:41:06.862671939 -0800
83@@ -144,6 +144,15 @@
84 fi
85 fi
86
87+gcc_gxx_include_dir_add_sysroot=0
88+if test "${with_sysroot+set}" = set; then :
89+ gcc_gxx_without_sysroot=`expr "${gcc_gxx_include_dir}" : "${with_sysroot}"'\(.*\)'`
90+ if test "${gcc_gxx_without_sysroot}"; then :
91+ gcc_gxx_include_dir="${gcc_gxx_without_sysroot}"
92+ gcc_gxx_include_dir_add_sysroot=1
93+ fi
94+fi
95+
96 AC_ARG_WITH(cpp_install_dir,
97 [ --with-cpp-install-dir=DIR
98 install the user visible C preprocessor in DIR
99@@ -4727,6 +4736,7 @@
100 AC_SUBST(float_h_file)
101 AC_SUBST(gcc_config_arguments)
102 AC_SUBST(gcc_gxx_include_dir)
103+AC_SUBST(gcc_gxx_include_dir_add_sysroot)
104 AC_SUBST(host_exeext)
105 AC_SUBST(host_xm_file_list)
106 AC_SUBST(host_xm_include_list)
107Index: gcc-4_6-branch/gcc/cppdefault.c
108===================================================================
109--- gcc-4_6-branch.orig/gcc/cppdefault.c 2012-03-03 01:03:17.000000000 -0800
110+++ gcc-4_6-branch/gcc/cppdefault.c 2012-03-04 09:41:06.862671939 -0800
111@@ -48,15 +48,18 @@
112 = {
113 #ifdef GPLUSPLUS_INCLUDE_DIR
114 /* Pick up GNU C++ generic include files. */
115- { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, 0, 0 },
116+ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1,
117+ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
118 #endif
119 #ifdef GPLUSPLUS_TOOL_INCLUDE_DIR
120 /* Pick up GNU C++ target-dependent include files. */
121- { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, 0, 1 },
122+ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1,
123+ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 },
124 #endif
125 #ifdef GPLUSPLUS_BACKWARD_INCLUDE_DIR
126 /* Pick up GNU C++ backward and deprecated include files. */
127- { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, 0, 0 },
128+ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1,
129+ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
130 #endif
131 #ifdef GCC_INCLUDE_DIR
132 /* This is the dir for gcc's private headers. */
133Index: gcc-4_6-branch/gcc/configure
134===================================================================
135--- gcc-4_6-branch.orig/gcc/configure 2012-03-04 09:33:36.000000000 -0800
136+++ gcc-4_6-branch/gcc/configure 2012-03-04 09:41:12.462671816 -0800
137@@ -636,6 +636,7 @@
138 host_xm_include_list
139 host_xm_file_list
140 host_exeext
141+gcc_gxx_include_dir_add_sysroot
142 gcc_gxx_include_dir
143 gcc_config_arguments
144 float_h_file
145@@ -3313,6 +3314,15 @@
146 fi
147 fi
148
149+gcc_gxx_include_dir_add_sysroot=0
150+if test "${with_sysroot+set}" = set; then :
151+ gcc_gxx_without_sysroot=`expr "${gcc_gxx_include_dir}" : "${with_sysroot}"'\(.*\)'`
152+ if test "${gcc_gxx_without_sysroot}"; then :
153+ gcc_gxx_include_dir="${gcc_gxx_without_sysroot}"
154+ gcc_gxx_include_dir_add_sysroot=1
155+ fi
156+fi
157+
158
159 # Check whether --with-cpp_install_dir was given.
160 if test "${with_cpp_install_dir+set}" = set; then :
161@@ -17504,7 +17514,7 @@
162 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
163 lt_status=$lt_dlunknown
164 cat > conftest.$ac_ext <<_LT_EOF
165-#line 17507 "configure"
166+#line 17517 "configure"
167 #include "confdefs.h"
168
169 #if HAVE_DLFCN_H
170@@ -17610,7 +17620,7 @@
171 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
172 lt_status=$lt_dlunknown
173 cat > conftest.$ac_ext <<_LT_EOF
174-#line 17613 "configure"
175+#line 17623 "configure"
176 #include "confdefs.h"
177
178 #if HAVE_DLFCN_H
179@@ -26141,6 +26151,7 @@
180
181
182
183+
184
185
186
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/arm-nolibfloat.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/arm-nolibfloat.patch
new file mode 100644
index 000000000..59a9ec33c
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/arm-nolibfloat.patch
@@ -0,0 +1,26 @@
1Upstream-Status: Pending
2
3# Dimitry Andric <dimitry@andric.com>, 2004-05-01
4#
5# * Removed the extra -lfloat option from LIBGCC_SPEC, since it isn't needed
6# anymore. (The required functions are now in libgcc.)
7#
8# Fixes errors like
9# arm-softfloat-linux-gnu/3.4.0/../../../../arm-softfloat-linux-gnu/bin/ld: cannot find -lfloat
10# collect2: ld returned 1 exit status
11# make[2]: *** [arm-softfloat-linux-gnu/gcc-3.4.0-glibc-2.3.2/build-glibc/iconvdata/ISO8859-1.so] Error 1
12# when building glibc-2.3.3 with gcc-3.4.0 for arm-softfloat
13
14Index: gcc-4.6.0/gcc/config/arm/linux-elf.h
15===================================================================
16--- gcc-4.6.0.orig/gcc/config/arm/linux-elf.h
17+++ gcc-4.6.0/gcc/config/arm/linux-elf.h
18@@ -60,7 +60,7 @@
19 %{shared:-lc} \
20 %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
21
22-#define LIBGCC_SPEC "%{msoft-float:-lfloat} %{mfloat-abi=soft*:-lfloat} -lgcc"
23+#define LIBGCC_SPEC "-lgcc"
24
25 #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
26
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/arm-softfloat.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/arm-softfloat.patch
new file mode 100644
index 000000000..01bf80d0f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/arm-softfloat.patch
@@ -0,0 +1,18 @@
1Upstream-Status: Pending
2
3Index: gcc-4.6.0/gcc/config/arm/t-linux
4===================================================================
5--- gcc-4.6.0.orig/gcc/config/arm/t-linux
6+++ gcc-4.6.0/gcc/config/arm/t-linux
7@@ -23,7 +23,10 @@ TARGET_LIBGCC2_CFLAGS = -fomit-frame-poi
8
9 LIB1ASMSRC = arm/lib1funcs.asm
10 LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \
11- _arm_addsubdf3 _arm_addsubsf3
12+ _negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \
13+ _truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \
14+ _fixsfsi _fixunssfsi _floatdidf _floatdisf _floatundisf _floatundidf
15+# _arm_addsubdf3 _arm_addsubsf3
16
17 # MULTILIB_OPTIONS = mhard-float/msoft-float
18 # MULTILIB_DIRNAMES = hard-float soft-float
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/cache-amnesia.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/cache-amnesia.patch
new file mode 100644
index 000000000..72ead3118
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/cache-amnesia.patch
@@ -0,0 +1,33 @@
1Upstream-Status: Inappropriate [embedded specific]
2
3---
4 gcc/configure | 2 +-
5 gcc/configure.ac | 2 +-
6 2 files changed, 2 insertions(+), 2 deletions(-)
7
8Index: gcc-4.6.0/gcc/configure
9===================================================================
10--- gcc-4.6.0.orig/gcc/configure
11+++ gcc-4.6.0/gcc/configure
12@@ -10898,7 +10898,7 @@ else
13 saved_CFLAGS="${CFLAGS}"
14 CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
15 LDFLAGS="${LDFLAGS_FOR_BUILD}" \
16- ${realsrcdir}/configure \
17+ CONFIG_SITE= ${realsrcdir}/configure --cache-file=./other.cache \
18 --enable-languages=${enable_languages-all} \
19 --target=$target_alias --host=$build_alias --build=$build_alias
20 CFLAGS="${saved_CFLAGS}"
21Index: gcc-4.6.0/gcc/configure.ac
22===================================================================
23--- gcc-4.6.0.orig/gcc/configure.ac
24+++ gcc-4.6.0/gcc/configure.ac
25@@ -1435,7 +1435,7 @@ else
26 saved_CFLAGS="${CFLAGS}"
27 CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
28 LDFLAGS="${LDFLAGS_FOR_BUILD}" \
29- ${realsrcdir}/configure \
30+ CONFIG_SITE= ${realsrcdir}/configure --cache-file=./other.cache \
31 --enable-languages=${enable_languages-all} \
32 --target=$target_alias --host=$build_alias --build=$build_alias
33 CFLAGS="${saved_CFLAGS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/cpp-honour-sysroot.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/cpp-honour-sysroot.patch
new file mode 100644
index 000000000..731067741
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/cpp-honour-sysroot.patch
@@ -0,0 +1,40 @@
1Currently, if the gcc toolchain is relocated and installed from sstate, then you try and compile
2preprocessed source (.i or .ii files), the compiler will try and access the builtin sysroot location
3rather than the --sysroot option specified on the commandline. If access to that directory is
4permission denied (unreadable), gcc will error.
5
6This happens when ccache is in use due to the fact it uses preprocessed source files.
7
8The fix below adds %I to the cpp-output spec macro so the default substitutions for -iprefix,
9-isystem, -isysroot happen and the correct sysroot is used.
10
11[YOCTO #2074]
12
13Upstream-Status: Pending
14
15RP 2012/04/13
16
17Index: gcc-4_6-branch/gcc/gcc.c
18===================================================================
19--- gcc-4_6-branch.orig/gcc/gcc.c 2012-04-13 12:24:37.939671140 +0000
20+++ gcc-4_6-branch/gcc/gcc.c 2012-04-13 12:24:54.439670688 +0000
21@@ -953,7 +953,7 @@
22 %W{o*:--output-pch=%*}}%V}}}}}}", 0, 0, 0},
23 {".i", "@cpp-output", 0, 0, 0},
24 {"@cpp-output",
25- "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %(cc1_options) %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
26+ "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %I %(cc1_options) %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
27 {".s", "@assembler", 0, 0, 0},
28 {"@assembler",
29 "%{!M:%{!MM:%{!E:%{!S:as %(asm_debug) %(asm_options) %i %A }}}}", 0, 0, 0},
30Index: gcc-4_6-branch/gcc/cp/lang-specs.h
31===================================================================
32--- gcc-4_6-branch.orig/gcc/cp/lang-specs.h 2012-04-13 12:25:01.019670594 +0000
33+++ gcc-4_6-branch/gcc/cp/lang-specs.h 2012-04-13 12:25:07.567670180 +0000
34@@ -64,5 +64,5 @@
35 {".ii", "@c++-cpp-output", 0, 0, 0},
36 {"@c++-cpp-output",
37 "%{!M:%{!MM:%{!E:\
38- cc1plus -fpreprocessed %i %(cc1_options) %2\
39+ cc1plus -fpreprocessed %i %I %(cc1_options) %2\
40 %{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/disable_relax_pic_calls_flag.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/disable_relax_pic_calls_flag.patch
new file mode 100644
index 000000000..22c106d25
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/disable_relax_pic_calls_flag.patch
@@ -0,0 +1,48 @@
1Upstream-Status: Inappropriate [configuration]
2
3GCC: disable MASK_RELAX_PIC_CALLS bit
4
5The new feature added after 4.3.3
6"http://www.pubbs.net/200909/gcc/94048-patch-add-support-for-rmipsjalr.html"
7will cause cc1plus eat up all the system memory when build webkit-gtk.
8The function mips_get_pic_call_symbol keeps on recursively calling itself.
9Disable this feature to walk aside the bug.
10
11Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
12
13Index: gcc-4.6.0/gcc/configure
14===================================================================
15--- gcc-4.6.0.orig/gcc/configure
16+++ gcc-4.6.0/gcc/configure
17@@ -24887,13 +24887,6 @@ $as_echo_n "checking assembler and linke
18 rm -f conftest.*
19 fi
20 fi
21- if test $gcc_cv_as_ld_jalr_reloc = yes; then
22- if test x$target_cpu_default = x; then
23- target_cpu_default=MASK_RELAX_PIC_CALLS
24- else
25- target_cpu_default="($target_cpu_default)|MASK_RELAX_PIC_CALLS"
26- fi
27- fi
28 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_ld_jalr_reloc" >&5
29 $as_echo "$gcc_cv_as_ld_jalr_reloc" >&6; }
30
31Index: gcc-4.6.0/gcc/configure.ac
32===================================================================
33--- gcc-4.6.0.orig/gcc/configure.ac
34+++ gcc-4.6.0/gcc/configure.ac
35@@ -3764,13 +3764,6 @@ x:
36 rm -f conftest.*
37 fi
38 fi
39- if test $gcc_cv_as_ld_jalr_reloc = yes; then
40- if test x$target_cpu_default = x; then
41- target_cpu_default=MASK_RELAX_PIC_CALLS
42- else
43- target_cpu_default="($target_cpu_default)|MASK_RELAX_PIC_CALLS"
44- fi
45- fi
46 AC_MSG_RESULT($gcc_cv_as_ld_jalr_reloc)
47
48 AC_CACHE_CHECK([linker for .eh_frame personality relaxation],
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/fix-for-ice-50099.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/fix-for-ice-50099.patch
new file mode 100644
index 000000000..57b03d2bf
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/fix-for-ice-50099.patch
@@ -0,0 +1,49 @@
1
2This patch address an issue with the compiler generating an ICE
3during compliation of lttng-ust.
4
5http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50099
6
7Upstream-Status: Pending
8
9Signed-off-by: Khem Raj <khem.raj@gmail.com>
10Signed-off-by: Saul Wold <sgw@linux.intel.com>
11
12Index: gcc/config/arm/arm.md
13===================================================================
14--- gcc-4.6.0/gcc/config/arm/arm.md (revision 178135)
15+++ gcc-4.6.0/gcc/config/arm/arm.md (working copy)
16@@ -4217,6 +4217,7 @@ (define_split
17 "TARGET_32BIT"
18 [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
19 {
20+ rtx srcop = operands[1];
21 rtx lo_part = gen_lowpart (SImode, operands[0]);
22 enum machine_mode src_mode = GET_MODE (operands[1]);
23
24@@ -4224,14 +4225,21 @@ (define_split
25 && !reg_overlap_mentioned_p (operands[0], operands[1]))
26 emit_clobber (operands[0]);
27
28+ if (TARGET_ARM && src_mode == QImode
29+ && !arm_reg_or_extendqisi_mem_op (srcop, QImode))
30+ {
31+ rtx dest = gen_lowpart (QImode, lo_part);
32+ emit_move_insn (dest, srcop);
33+ srcop = dest;
34+ }
35 if (!REG_P (lo_part) || src_mode != SImode
36- || !rtx_equal_p (lo_part, operands[1]))
37+ || !rtx_equal_p (lo_part, srcop))
38 {
39 if (src_mode == SImode)
40- emit_move_insn (lo_part, operands[1]);
41+ emit_move_insn (lo_part, srcop);
42 else
43 emit_insn (gen_rtx_SET (VOIDmode, lo_part,
44- gen_rtx_SIGN_EXTEND (SImode, operands[1])));
45+ gen_rtx_SIGN_EXTEND (SImode, srcop)));
46 operands[1] = lo_part;
47 }
48 operands[0] = gen_highpart (SImode, operands[0]);
49
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/fortran-cross-compile-hack.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/fortran-cross-compile-hack.patch
new file mode 100644
index 000000000..5a895596f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/fortran-cross-compile-hack.patch
@@ -0,0 +1,32 @@
1Upstream-Status: Inappropriate [embedded specific]
2
3* Fortran would have searched for arm-angstrom-gnueabi-gfortran but would have used
4 used gfortan. For gcc_4.2.2.bb we want to use the gfortran compiler from our cross
5 directory.
6
7Index: gcc-4.5+svnr155514/libgfortran/configure
8===================================================================
9--- gcc-4.5+svnr155514.orig/libgfortran/configure 2009-12-29 22:02:01.000000000 -0800
10+++ gcc-4.5+svnr155514/libgfortran/configure 2009-12-30 08:12:40.889091657 -0800
11@@ -11655,7 +11655,7 @@ CC="$lt_save_CC"
12
13 # We need gfortran to compile parts of the library
14 #AC_PROG_FC(gfortran)
15-FC="$GFORTRAN"
16+#FC="$GFORTRAN"
17 ac_ext=${ac_fc_srcext-f}
18 ac_compile='$FC -c $FCFLAGS $ac_fcflags_srcext conftest.$ac_ext >&5'
19 ac_link='$FC -o conftest$ac_exeext $FCFLAGS $LDFLAGS $ac_fcflags_srcext conftest.$ac_ext $LIBS >&5'
20Index: gcc-4.5+svnr155514/libgfortran/configure.ac
21===================================================================
22--- gcc-4.5+svnr155514.orig/libgfortran/configure.ac 2009-12-29 22:02:01.000000000 -0800
23+++ gcc-4.5+svnr155514/libgfortran/configure.ac 2009-12-30 08:12:13.453094218 -0800
24@@ -187,7 +187,7 @@ AC_SUBST(enable_static)
25
26 # We need gfortran to compile parts of the library
27 #AC_PROG_FC(gfortran)
28-FC="$GFORTRAN"
29+#FC="$GFORTRAN"
30 AC_PROG_FC(gfortran)
31
32 # extra LD Flags which are required for targets
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch
new file mode 100644
index 000000000..ce8274004
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch
@@ -0,0 +1,33 @@
1Upstream-Status: Inappropriate [embedded specific]
2
3---
4 configure | 2 +-
5 configure.ac | 2 +-
6 2 files changed, 2 insertions(+), 2 deletions(-)
7
8Index: gcc-4.6.0/configure.ac
9===================================================================
10--- gcc-4.6.0.orig/configure.ac
11+++ gcc-4.6.0/configure.ac
12@@ -3073,7 +3073,7 @@ fi
13 # for target_alias and gcc doesn't manage it consistently.
14 target_configargs="--cache-file=./config.cache ${target_configargs}"
15
16-FLAGS_FOR_TARGET=
17+FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET"
18 case " $target_configdirs " in
19 *" newlib "*)
20 case " $target_configargs " in
21Index: gcc-4.6.0/configure
22===================================================================
23--- gcc-4.6.0.orig/configure
24+++ gcc-4.6.0/configure
25@@ -7594,7 +7594,7 @@ fi
26 # for target_alias and gcc doesn't manage it consistently.
27 target_configargs="--cache-file=./config.cache ${target_configargs}"
28
29-FLAGS_FOR_TARGET=
30+FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET"
31 case " $target_configdirs " in
32 *" newlib "*)
33 case " $target_configargs " in
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-4.3.3-SYSROOT_CFLAGS_FOR_TARGET.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-4.3.3-SYSROOT_CFLAGS_FOR_TARGET.patch
new file mode 100644
index 000000000..6d02f7177
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-4.3.3-SYSROOT_CFLAGS_FOR_TARGET.patch
@@ -0,0 +1,116 @@
1Upstream-Status: Pending
2
3Before committing, I noticed that PR/32161 was marked as a dup of PR/32009, but my previous patch did not fix it.
4
5This alternative patch is better because it lets you just use CFLAGS_FOR_TARGET to set the compilation flags for libgcc. Since bootstrapped target libraries are never compiled with the native compiler, it makes little sense to use different flags for stage1 and later stages. And it also makes little sense to use a different variable than CFLAGS_FOR_TARGET.
6
7Other changes I had to do include:
8
9- moving the creation of default CFLAGS_FOR_TARGET from Makefile.am to configure.ac, because otherwise the BOOT_CFLAGS are substituted into CFLAGS_FOR_TARGET (which is "-O2 -g $(CFLAGS)") via $(CFLAGS). It is also cleaner this way though.
10
11- passing the right CFLAGS to configure scripts as exported environment variables
12
13I also stopped passing LIBCFLAGS to configure scripts since they are unused in the whole src tree. And I updated the documentation as H-P reminded me to do.
14
15Bootstrapped/regtested i686-pc-linux-gnu, will commit to 4.4 shortly. Ok for 4.3?
16
17Paolo
18
192008-02-19 Paolo Bonzini <bonzini@gnu.org>
20
21 PR bootstrap/32009
22 PR bootstrap/32161
23
24 * configure.ac (CFLAGS_FOR_TARGET, CXXFLAGS_FOR_TARGET): Compute here.
25 * configure: Regenerate.
26
27 * Makefile.def: Define stage_libcflags for all bootstrap stages.
28 * Makefile.tpl (BOOT_LIBCFLAGS, STAGE2_LIBCFLAGS, STAGE3_LIBCFLAGS,
29 STAGE4_LIBCFLAGS): New.
30 (CFLAGS_FOR_TARGET, CXXFLAGS_FOR_TARGET): Subst from autoconf, without
31 $(SYSROOT_CFLAGS_FOR_TARGET) and $(DEBUG_PREFIX_CFLAGS_FOR_TARGET).
32 (BASE_TARGET_EXPORTS): Append them here to C{,XX}FLAGS.
33 (EXTRA_TARGET_FLAGS): Append them here to {LIB,}C{,XX}FLAGS.
34 (configure-stage[+id+]-[+prefix+][+module+]): Pass stage_libcflags
35 for target modules. Don't export LIBCFLAGS.
36 (all-stage[+id+]-[+prefix+][+module+]): Pass stage_libcflags; pass
37 $(BASE_FLAGS_TO_PASS) where [+args+] was passed, and [+args+] after
38 the overridden CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET.
39 (invocations of `all'): Replace $(TARGET_FLAGS_TO_PASS) with
40 $(EXTRA_TARGET_FLAGS), $(FLAGS_TO_PASS) with $(EXTRA_HOST_FLAGS).
41 * Makefile.in: Regenerate.
42
43config:
442008-02-19 Paolo Bonzini <bonzini@gnu.org>
45
46 PR bootstrap/32009
47 * mh-ppc-darwin (BOOT_CFLAGS): Reenable.
48
49gcc:
502008-02-19 Paolo Bonzini <bonzini@gnu.org>
51
52 PR bootstrap/32009
53 * doc/install.texi: Correct references to CFLAGS, replacing them
54 with BOOT_CFLAGS. Document flags used during bootstrap for
55 target libraries.
56
57
58---
59 Makefile.def | 25
60 Makefile.in | 1845 ++++++++++++++++++++++++++++++-------------------
61 Makefile.tpl | 91 +-
62 config/mh-ppc-darwin | 3
63 configure | 36
64 configure.ac | 32
65 gcc/Makefile.in | 2
66 gcc/configure | 6
67 gcc/configure.ac | 3
68 gcc/doc/install.texi | 56 -
69 libiberty/Makefile.in | 162 ++--
70 libiberty/configure | 46 -
71 libiberty/configure.ac | 43 -
72 13 files changed, 1454 insertions(+), 896 deletions(-)
73
74Index: gcc-4.6.0/configure
75===================================================================
76--- gcc-4.6.0.orig/configure
77+++ gcc-4.6.0/configure
78@@ -6785,6 +6785,38 @@ if test "x$CXXFLAGS_FOR_TARGET" = x; the
79 fi
80
81
82+# During gcc bootstrap, if we use some random cc for stage1 then CFLAGS
83+# might be empty or "-g". We don't require a C++ compiler, so CXXFLAGS
84+# might also be empty (or "-g", if a non-GCC C++ compiler is in the path).
85+# We want to ensure that TARGET libraries (which we know are built with
86+# gcc) are built with "-O2 -g", so include those options when setting
87+# CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET.
88+if test "x$CFLAGS_FOR_TARGET" = x; then
89+ CFLAGS_FOR_TARGET=$CFLAGS
90+ case " $CFLAGS " in
91+ *" -O2 "*) ;;
92+ *) CFLAGS_FOR_TARGET="-O2 $CFLAGS" ;;
93+ esac
94+ case " $CFLAGS " in
95+ *" -g "* | *" -g3 "*) ;;
96+ *) CFLAGS_FOR_TARGET="-g $CFLAGS" ;;
97+ esac
98+fi
99+
100+
101+if test "x$CXXFLAGS_FOR_TARGET" = x; then
102+ CXXFLAGS_FOR_TARGET=$CXXFLAGS
103+ case " $CXXFLAGS " in
104+ *" -O2 "*) ;;
105+ *) CXXFLAGS_FOR_TARGET="-O2 $CXXFLAGS" ;;
106+ esac
107+ case " $CXXFLAGS " in
108+ *" -g "* | *" -g3 "*) ;;
109+ *) CXXFLAGS_FOR_TARGET="-g $CXXFLAGS" ;;
110+ esac
111+fi
112+
113+
114 # Handle --with-headers=XXX. If the value is not "yes", the contents of
115 # the named directory are copied to $(tooldir)/sys-include.
116 if test x"${with_headers}" != x && test x"${with_headers}" != xno ; then
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-argument-list-too-long.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-argument-list-too-long.patch
new file mode 100644
index 000000000..70d3c53a8
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-argument-list-too-long.patch
@@ -0,0 +1,33 @@
1There would be an "Argument list too long" error when the
2build directory is longer than 200, this is caused by:
3
4headers=`echo $(PLUGIN_HEADERS) | tr ' ' '\012' | sort -u`
5
6The PLUGIN_HEADERS is too long before sort, so the "echo" can't handle
7it, use the $(sort list) of GNU make which can handle the too long list
8would fix the problem, the header would be short enough after sorted.
9The "tr ' ' '\012'" was used for translating the space to "\n", the
10$(sort list) doesn't need this.
11
12Signed-off-by: Robert Yang <liezhi.yang@windriver.com>
13
14Upstream-Status: Pending
15---
16 gcc/Makefile.in | 2 +-
17 1 file changed, 1 insertion(+), 1 deletion(-)
18
19diff --git a/gcc/Makefile.in b/gcc/Makefile.in
20--- a/gcc/Makefile.in
21+++ b/gcc/Makefile.in
22@@ -4553,7 +4553,7 @@ install-plugin: installdirs lang.install-plugin s-header-vars install-gengtype
23 # We keep the directory structure for files in config or c-family and .def
24 # files. All other files are flattened to a single directory.
25 $(mkinstalldirs) $(DESTDIR)$(plugin_includedir)
26- headers=`echo $(PLUGIN_HEADERS) | tr ' ' '\012' | sort -u`; \
27+ headers="$(sort $(PLUGIN_HEADERS))"; \
28 srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'`; \
29 for file in $$headers; do \
30 if [ -f $$file ] ; then \
31--
321.7.10.2
33
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-arm-set-cost.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-arm-set-cost.patch
new file mode 100644
index 000000000..4419a2017
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-arm-set-cost.patch
@@ -0,0 +1,35 @@
1Upstream-Status:Backport
22011-08-18 Richard Sandiford <richard.sandiford@linaro.org>
3
4 gcc/
5 Backport from mainline:
6
7 2011-08-18 Richard Sandiford <richard.sandiford@linaro.org>
8
9 * config/arm/arm.c (arm_rtx_costs_1): Don't modify the costs of SET.
10 (arm_size_rtx_costs): Likewise.
11
12=== modified file 'gcc/config/arm/arm.c'
13--- old/gcc/config/arm/arm.c 2011-08-12 08:08:31 +0000
14+++ new/gcc/config/arm/arm.c 2011-08-18 13:53:37 +0000
15@@ -7464,6 +7464,9 @@
16 *total = COSTS_N_INSNS (4);
17 return true;
18
19+ case SET:
20+ return false;
21+
22 default:
23 *total = COSTS_N_INSNS (4);
24 return false;
25@@ -7811,6 +7814,9 @@
26 *total = COSTS_N_INSNS (1) + 1;
27 return true;
28
29+ case SET:
30+ return false;
31+
32 default:
33 if (mode != VOIDmode)
34 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
35
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-flags-for-build.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-flags-for-build.patch
new file mode 100644
index 000000000..5eaeb0508
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-flags-for-build.patch
@@ -0,0 +1,189 @@
1Upstream-Status: Pending
2
3Index: gcc-4_6-branch/Makefile.def
4===================================================================
5--- gcc-4_6-branch.orig/Makefile.def 2012-03-03 01:08:03.000000000 -0800
6+++ gcc-4_6-branch/Makefile.def 2012-03-04 09:19:02.430607447 -0800
7@@ -242,6 +242,7 @@
8 flags_to_pass = { flag= BISON ; };
9 flags_to_pass = { flag= CC_FOR_BUILD ; };
10 flags_to_pass = { flag= CFLAGS_FOR_BUILD ; };
11+flags_to_pass = { flag= CPPFLAGS_FOR_BUILD ; };
12 flags_to_pass = { flag= CXX_FOR_BUILD ; };
13 flags_to_pass = { flag= EXPECT ; };
14 flags_to_pass = { flag= FLEX ; };
15Index: gcc-4_6-branch/gcc/Makefile.in
16===================================================================
17--- gcc-4_6-branch.orig/gcc/Makefile.in 2012-03-03 01:03:17.000000000 -0800
18+++ gcc-4_6-branch/gcc/Makefile.in 2012-03-04 09:19:02.430607447 -0800
19@@ -770,7 +770,7 @@
20
21 # Native linker and preprocessor flags. For x-fragment overrides.
22 BUILD_LDFLAGS=@BUILD_LDFLAGS@
23-BUILD_CPPFLAGS=$(ALL_CPPFLAGS)
24+BUILD_CPPFLAGS=$(INCLUDES) @BUILD_CPPFLAGS@ $(X_CPPFLAGS)
25
26 # Actual name to use when installing a native compiler.
27 GCC_INSTALL_NAME := $(shell echo gcc|sed '$(program_transform_name)')
28Index: gcc-4_6-branch/gcc/configure.ac
29===================================================================
30--- gcc-4_6-branch.orig/gcc/configure.ac 2012-03-03 01:17:45.000000000 -0800
31+++ gcc-4_6-branch/gcc/configure.ac 2012-03-04 09:19:02.430607447 -0800
32@@ -1774,16 +1774,18 @@
33 # Also, we cannot run fixincludes.
34
35 # These are the normal (build=host) settings:
36-CC_FOR_BUILD='$(CC)' AC_SUBST(CC_FOR_BUILD)
37-BUILD_CFLAGS='$(ALL_CFLAGS)' AC_SUBST(BUILD_CFLAGS)
38-BUILD_LDFLAGS='$(LDFLAGS)' AC_SUBST(BUILD_LDFLAGS)
39-STMP_FIXINC=stmp-fixinc AC_SUBST(STMP_FIXINC)
40+CC_FOR_BUILD='$(CC)' AC_SUBST(CC_FOR_BUILD)
41+BUILD_CFLAGS='$(ALL_CFLAGS)' AC_SUBST(BUILD_CFLAGS)
42+BUILD_LDFLAGS='$(LDFLAGS)' AC_SUBST(BUILD_LDFLAGS)
43+BUILD_CPPFLAGS='$(ALL_CPPFLAGS)' AC_SUBST(BUILD_CPPFLAGS)
44+STMP_FIXINC=stmp-fixinc AC_SUBST(STMP_FIXINC)
45
46 # And these apply if build != host, or we are generating coverage data
47 if test x$build != x$host || test "x$coverage_flags" != x
48 then
49 BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)'
50 BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)'
51+ BUILD_CPPFLAGS='$(CPPFLAGS_FOR_BUILD)'
52 fi
53
54 # Expand extra_headers to include complete path.
55Index: gcc-4_6-branch/Makefile.in
56===================================================================
57--- gcc-4_6-branch.orig/Makefile.in 2012-03-03 01:08:03.000000000 -0800
58+++ gcc-4_6-branch/Makefile.in 2012-03-04 09:19:02.446607448 -0800
59@@ -338,6 +338,7 @@
60 AS_FOR_BUILD = @AS_FOR_BUILD@
61 CC_FOR_BUILD = @CC_FOR_BUILD@
62 CFLAGS_FOR_BUILD = @CFLAGS_FOR_BUILD@
63+CPPFLAGS_FOR_BUILD = @CPPFLAGS_FOR_BUILD@
64 CXXFLAGS_FOR_BUILD = @CXXFLAGS_FOR_BUILD@
65 CXX_FOR_BUILD = @CXX_FOR_BUILD@
66 DLLTOOL_FOR_BUILD = @DLLTOOL_FOR_BUILD@
67@@ -691,6 +692,7 @@
68 "BISON=$(BISON)" \
69 "CC_FOR_BUILD=$(CC_FOR_BUILD)" \
70 "CFLAGS_FOR_BUILD=$(CFLAGS_FOR_BUILD)" \
71+ "CPPFLAGS_FOR_BUILD=$(CPPFLAGS_FOR_BUILD)" \
72 "CXX_FOR_BUILD=$(CXX_FOR_BUILD)" \
73 "EXPECT=$(EXPECT)" \
74 "FLEX=$(FLEX)" \
75Index: gcc-4_6-branch/gcc/configure
76===================================================================
77--- gcc-4_6-branch.orig/gcc/configure 2012-03-03 01:17:45.000000000 -0800
78+++ gcc-4_6-branch/gcc/configure 2012-03-04 09:19:15.638608087 -0800
79@@ -703,6 +703,7 @@
80 LIBTOOL
81 collect2
82 STMP_FIXINC
83+BUILD_CPPFLAGS
84 BUILD_LDFLAGS
85 BUILD_CFLAGS
86 CC_FOR_BUILD
87@@ -4842,7 +4843,7 @@
88 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $acx_cv_cc_gcc_supports_ada" >&5
89 $as_echo "$acx_cv_cc_gcc_supports_ada" >&6; }
90
91-if test x$GNATBIND != xno && test x$GNATMAKE != xno && test x$acx_cv_cc_gcc_supports_ada != xno; then
92+if test "x$GNATBIND" != xno && test "x$GNATMAKE" != xno && test x$acx_cv_cc_gcc_supports_ada != xno; then
93 have_gnat=yes
94 else
95 have_gnat=no
96@@ -11372,6 +11373,7 @@
97 CC_FOR_BUILD='$(CC)'
98 BUILD_CFLAGS='$(ALL_CFLAGS)'
99 BUILD_LDFLAGS='$(LDFLAGS)'
100+BUILD_CPPFLAGS='$(ALL_CPPFLAGS)'
101 STMP_FIXINC=stmp-fixinc
102
103 # And these apply if build != host, or we are generating coverage data
104@@ -11379,6 +11381,7 @@
105 then
106 BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)'
107 BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)'
108+ BUILD_CPPFLAGS='$(CPPFLAGS_FOR_BUILD)'
109 fi
110
111 # Expand extra_headers to include complete path.
112@@ -17495,7 +17498,7 @@
113 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
114 lt_status=$lt_dlunknown
115 cat > conftest.$ac_ext <<_LT_EOF
116-#line 17498 "configure"
117+#line 17501 "configure"
118 #include "confdefs.h"
119
120 #if HAVE_DLFCN_H
121@@ -17601,7 +17604,7 @@
122 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
123 lt_status=$lt_dlunknown
124 cat > conftest.$ac_ext <<_LT_EOF
125-#line 17604 "configure"
126+#line 17607 "configure"
127 #include "confdefs.h"
128
129 #if HAVE_DLFCN_H
130Index: gcc-4_6-branch/Makefile.tpl
131===================================================================
132--- gcc-4_6-branch.orig/Makefile.tpl 2012-03-03 01:08:03.000000000 -0800
133+++ gcc-4_6-branch/Makefile.tpl 2012-03-04 09:19:02.454607448 -0800
134@@ -341,6 +341,7 @@
135 AS_FOR_BUILD = @AS_FOR_BUILD@
136 CC_FOR_BUILD = @CC_FOR_BUILD@
137 CFLAGS_FOR_BUILD = @CFLAGS_FOR_BUILD@
138+CPPFLAGS_FOR_BUILD = @CPPFLAGS_FOR_BUILD@
139 CXXFLAGS_FOR_BUILD = @CXXFLAGS_FOR_BUILD@
140 CXX_FOR_BUILD = @CXX_FOR_BUILD@
141 DLLTOOL_FOR_BUILD = @DLLTOOL_FOR_BUILD@
142Index: gcc-4_6-branch/configure.ac
143===================================================================
144--- gcc-4_6-branch.orig/configure.ac 2012-03-03 01:17:45.000000000 -0800
145+++ gcc-4_6-branch/configure.ac 2012-03-04 09:19:02.454607448 -0800
146@@ -3123,6 +3123,7 @@
147 # our build compiler if desired.
148 if test x"${build}" = x"${host}" ; then
149 CFLAGS_FOR_BUILD=${CFLAGS_FOR_BUILD-${CFLAGS}}
150+ CPPFLAGS_FOR_BUILD=${CPPFLAGS_FOR_BUILD-${CPPFLAGS}}
151 CXXFLAGS_FOR_BUILD=${CXXFLAGS_FOR_BUILD-${CXXFLAGS}}
152 LDFLAGS_FOR_BUILD=${LDFLAGS_FOR_BUILD-${LDFLAGS}}
153 fi
154@@ -3189,6 +3190,7 @@
155 AC_SUBST(AS_FOR_BUILD)
156 AC_SUBST(CC_FOR_BUILD)
157 AC_SUBST(CFLAGS_FOR_BUILD)
158+AC_SUBST(CPPFLAGS_FOR_BUILD)
159 AC_SUBST(CXXFLAGS_FOR_BUILD)
160 AC_SUBST(CXX_FOR_BUILD)
161 AC_SUBST(DLLTOOL_FOR_BUILD)
162Index: gcc-4_6-branch/configure
163===================================================================
164--- gcc-4_6-branch.orig/configure 2012-03-03 01:17:45.000000000 -0800
165+++ gcc-4_6-branch/configure 2012-03-04 09:19:02.458607448 -0800
166@@ -617,6 +617,7 @@
167 DLLTOOL_FOR_BUILD
168 CXX_FOR_BUILD
169 CXXFLAGS_FOR_BUILD
170+CPPFLAGS_FOR_BUILD
171 CFLAGS_FOR_BUILD
172 CC_FOR_BUILD
173 AS_FOR_BUILD
174@@ -7644,6 +7645,7 @@
175 # our build compiler if desired.
176 if test x"${build}" = x"${host}" ; then
177 CFLAGS_FOR_BUILD=${CFLAGS_FOR_BUILD-${CFLAGS}}
178+ CPPFLAGS_FOR_BUILD=${CPPFLAGS_FOR_BUILD-${CPPFLAGS}}
179 CXXFLAGS_FOR_BUILD=${CXXFLAGS_FOR_BUILD-${CXXFLAGS}}
180 LDFLAGS_FOR_BUILD=${LDFLAGS_FOR_BUILD-${LDFLAGS}}
181 fi
182@@ -7709,6 +7711,7 @@
183
184
185
186+
187
188
189
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-poison-dir-extend.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-poison-dir-extend.patch
new file mode 100644
index 000000000..35170e262
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-poison-dir-extend.patch
@@ -0,0 +1,27 @@
1Upstream-Status: Pending
2
3Add /sw/include and /opt/include based on the original
4zecke-no-host-includes.patch patch. The original patch checked for
5/usr/include, /sw/include and /opt/include and then triggered a failure and
6aborted.
7
8Instead, we add the two missing items to the current scan. If the user
9wants this to be a failure, they can add "-Werror=poison-system-directories".
10
11Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
12
13Index: gcc-4.6.0/gcc/incpath.c
14===================================================================
15--- gcc-4.6.0.orig/gcc/incpath.c
16+++ gcc-4.6.0/gcc/incpath.c
17@@ -363,7 +363,9 @@ merge_include_chains (const char *sysroo
18 {
19 if ((!strncmp (p->name, "/usr/include", 12))
20 || (!strncmp (p->name, "/usr/local/include", 18))
21- || (!strncmp (p->name, "/usr/X11R6/include", 18)))
22+ || (!strncmp (p->name, "/usr/X11R6/include", 18))
23+ || (!strncmp (p->name, "/sw/include", 11))
24+ || (!strncmp (p->name, "/opt/include", 12)))
25 warning (OPT_Wpoison_system_directories,
26 "include location \"%s\" is unsafe for "
27 "cross-compilation",
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-poison-system-directories.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-poison-system-directories.patch
new file mode 100644
index 000000000..a44e86ca4
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-poison-system-directories.patch
@@ -0,0 +1,223 @@
1Upstream-Status: Inappropriate [distribution: codesourcery]
2
3 gcc/
4 2008-07-02 Joseph Myers <joseph@codesourcery.com>
5 * c-incpath.c: Include toplev.h.
6 (merge_include_chains): Use warning instead of cpp_error for
7 system directory poisoning diagnostic.
8 * Makefile.in (c-incpath.o): Depend on toplev.h.
9 * gcc.c (LINK_COMMAND_SPEC): Pass
10 --error-poison-system-directories if
11 -Werror=poison-system-directories.
12
13 2007-06-13 Joseph Myers <joseph@codesourcery.com>
14 * common.opt (--Wno-poison-system-directories): New.
15 * doc/invoke.texi (-Wno-poison-system-directories): Document.
16 * c-incpath.c: Include flags.h.
17 (merge_include_chains): Check flag_poison_system_directories.
18 * gcc.c (LINK_COMMAND_SPEC): Pass --no-poison-system-directories
19 to linker if -Wno-poison-system-directories.
20 * Makefile.in (c-incpath.o): Depend on $(FLAGS_H).
21
22 2007-03-20 Daniel Jacobowitz <dan@codesourcery.com>
23 Joseph Myers <joseph@codesourcery.com>
24 * configure.ac (--enable-poison-system-directories): New option.
25 * configure, config.in: Regenerate.
26 * c-incpath.c (merge_include_chains): If
27 ENABLE_POISON_SYSTEM_DIRECTORIES defined, warn for use of
28 /usr/include, /usr/local/include or /usr/X11R6/include.
29
30Index: gcc-4_6-branch/gcc/common.opt
31===================================================================
32--- gcc-4_6-branch.orig/gcc/common.opt 2012-03-03 01:03:17.000000000 -0800
33+++ gcc-4_6-branch/gcc/common.opt 2012-03-04 09:24:54.410624483 -0800
34@@ -567,6 +567,10 @@
35 Common Var(warn_padded) Warning
36 Warn when padding is required to align structure members
37
38+Wpoison-system-directories
39+Common Var(flag_poison_system_directories) Init(1) Warning
40+Warn for -I and -L options using system directories if cross compiling
41+
42 Wshadow
43 Common Var(warn_shadow) Warning
44 Warn when one local variable shadows another
45Index: gcc-4_6-branch/gcc/config.in
46===================================================================
47--- gcc-4_6-branch.orig/gcc/config.in 2012-03-03 01:03:17.000000000 -0800
48+++ gcc-4_6-branch/gcc/config.in 2012-03-04 09:24:54.410624483 -0800
49@@ -144,6 +144,12 @@
50 #endif
51
52
53+/* Define to warn for use of native system header directories */
54+#ifndef USED_FOR_TARGET
55+#undef ENABLE_POISON_SYSTEM_DIRECTORIES
56+#endif
57+
58+
59 /* Define if you want all operations on RTL (the basic data structure of the
60 optimizer and back end) to be checked for dynamic type safety at runtime.
61 This is quite expensive. */
62Index: gcc-4_6-branch/gcc/configure.ac
63===================================================================
64--- gcc-4_6-branch.orig/gcc/configure.ac 2012-03-04 09:22:07.000000000 -0800
65+++ gcc-4_6-branch/gcc/configure.ac 2012-03-04 09:24:54.410624483 -0800
66@@ -4692,6 +4692,16 @@
67 fi)
68 AC_SUBST(slibdir)
69
70+AC_ARG_ENABLE([poison-system-directories],
71+ AS_HELP_STRING([--enable-poison-system-directories],
72+ [warn for use of native system header directories]),,
73+ [enable_poison_system_directories=no])
74+if test "x${enable_poison_system_directories}" = "xyes"; then
75+ AC_DEFINE([ENABLE_POISON_SYSTEM_DIRECTORIES],
76+ [1],
77+ [Define to warn for use of native system header directories])
78+fi
79+
80 # Substitute configuration variables
81 AC_SUBST(subdirs)
82 AC_SUBST(srcdir)
83Index: gcc-4_6-branch/gcc/doc/invoke.texi
84===================================================================
85--- gcc-4_6-branch.orig/gcc/doc/invoke.texi 2012-03-03 00:46:39.000000000 -0800
86+++ gcc-4_6-branch/gcc/doc/invoke.texi 2012-03-04 09:24:54.414624482 -0800
87@@ -257,6 +257,7 @@
88 -Woverlength-strings -Wpacked -Wpacked-bitfield-compat -Wpadded @gol
89 -Wparentheses -Wpedantic-ms-format -Wno-pedantic-ms-format @gol
90 -Wpointer-arith -Wno-pointer-to-int-cast @gol
91+-Wno-poison-system-directories @gol
92 -Wredundant-decls @gol
93 -Wreturn-type -Wsequence-point -Wshadow @gol
94 -Wsign-compare -Wsign-conversion -Wstack-protector @gol
95@@ -3782,6 +3783,14 @@
96 for most targets, it is made up of code and thus requires the stack
97 to be made executable in order for the program to work properly.
98
99+@item -Wno-poison-system-directories
100+@opindex Wno-poison-system-directories
101+Do not warn for @option{-I} or @option{-L} options using system
102+directories such as @file{/usr/include} when cross compiling. This
103+option is intended for use in chroot environments when such
104+directories contain the correct headers and libraries for the target
105+system rather than the host.
106+
107 @item -Wfloat-equal
108 @opindex Wfloat-equal
109 @opindex Wno-float-equal
110Index: gcc-4_6-branch/gcc/gcc.c
111===================================================================
112--- gcc-4_6-branch.orig/gcc/gcc.c 2012-03-03 01:03:17.000000000 -0800
113+++ gcc-4_6-branch/gcc/gcc.c 2012-03-04 09:24:54.418624482 -0800
114@@ -659,6 +659,8 @@
115 %{flto} %{flto=*} %l " LINK_PIE_SPEC \
116 "%X %{o*} %{e*} %{N} %{n} %{r}\
117 %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!nostartfiles:%S}}\
118+ %{Wno-poison-system-directories:--no-poison-system-directories}\
119+ %{Werror=poison-system-directories:--error-poison-system-directories}\
120 %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\
121 %{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)}\
122 %(mflib) " STACK_SPLIT_SPEC "\
123Index: gcc-4_6-branch/gcc/incpath.c
124===================================================================
125--- gcc-4_6-branch.orig/gcc/incpath.c 2012-03-03 01:03:17.000000000 -0800
126+++ gcc-4_6-branch/gcc/incpath.c 2012-03-04 09:24:54.418624482 -0800
127@@ -353,6 +353,24 @@
128 }
129 fprintf (stderr, _("End of search list.\n"));
130 }
131+
132+#ifdef ENABLE_POISON_SYSTEM_DIRECTORIES
133+ if (flag_poison_system_directories)
134+ {
135+ struct cpp_dir *p;
136+
137+ for (p = heads[QUOTE]; p; p = p->next)
138+ {
139+ if ((!strncmp (p->name, "/usr/include", 12))
140+ || (!strncmp (p->name, "/usr/local/include", 18))
141+ || (!strncmp (p->name, "/usr/X11R6/include", 18)))
142+ warning (OPT_Wpoison_system_directories,
143+ "include location \"%s\" is unsafe for "
144+ "cross-compilation",
145+ p->name);
146+ }
147+ }
148+#endif
149 }
150
151 /* Use given -I paths for #include "..." but not #include <...>, and
152Index: gcc-4_6-branch/gcc/Makefile.in
153===================================================================
154--- gcc-4_6-branch.orig/gcc/Makefile.in 2012-03-04 09:22:05.000000000 -0800
155+++ gcc-4_6-branch/gcc/Makefile.in 2012-03-04 09:24:54.418624482 -0800
156@@ -2179,7 +2179,7 @@
157
158 incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \
159 intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \
160- $(MACHMODE_H)
161+ $(MACHMODE_H) $(FLAGS_H) toplev.h
162
163 prefix.o: prefix.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) prefix.h \
164 Makefile $(BASEVER)
165Index: gcc-4_6-branch/gcc/configure
166===================================================================
167--- gcc-4_6-branch.orig/gcc/configure 2012-03-04 09:22:07.000000000 -0800
168+++ gcc-4_6-branch/gcc/configure 2012-03-04 09:25:31.502626277 -0800
169@@ -912,6 +912,7 @@
170 enable_maintainer_mode
171 enable_version_specific_runtime_libs
172 with_slibdir
173+enable_poison_system_directories
174 enable_plugin
175 enable_libquadmath_support
176 '
177@@ -1623,6 +1624,8 @@
178 --enable-version-specific-runtime-libs
179 specify that runtime libraries should be
180 installed in a compiler-specific directory
181+ --enable-poison-system-directories
182+ warn for use of native system header directories
183 --enable-plugin enable plugin support
184 --disable-libquadmath-support
185 disable libquadmath support for Fortran
186@@ -17498,7 +17501,7 @@
187 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
188 lt_status=$lt_dlunknown
189 cat > conftest.$ac_ext <<_LT_EOF
190-#line 17501 "configure"
191+#line 17504 "configure"
192 #include "confdefs.h"
193
194 #if HAVE_DLFCN_H
195@@ -17604,7 +17607,7 @@
196 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
197 lt_status=$lt_dlunknown
198 cat > conftest.$ac_ext <<_LT_EOF
199-#line 17607 "configure"
200+#line 17610 "configure"
201 #include "confdefs.h"
202
203 #if HAVE_DLFCN_H
204@@ -26125,6 +26128,19 @@
205
206
207
208+# Check whether --enable-poison-system-directories was given.
209+if test "${enable_poison_system_directories+set}" = set; then :
210+ enableval=$enable_poison_system_directories;
211+else
212+ enable_poison_system_directories=no
213+fi
214+
215+if test "x${enable_poison_system_directories}" = "xyes"; then
216+
217+$as_echo "#define ENABLE_POISON_SYSTEM_DIRECTORIES 1" >>confdefs.h
218+
219+fi
220+
221 # Substitute configuration variables
222
223
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-uclibc-locale-ctype_touplow_t.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-uclibc-locale-ctype_touplow_t.patch
new file mode 100644
index 000000000..1648b3b98
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-uclibc-locale-ctype_touplow_t.patch
@@ -0,0 +1,72 @@
1Upstream-Status: Pending
2
3Index: gcc-4.6.0/libstdc++-v3/config/locale/generic/c_locale.h
4===================================================================
5--- gcc-4.6.0.orig/libstdc++-v3/config/locale/generic/c_locale.h
6+++ gcc-4.6.0/libstdc++-v3/config/locale/generic/c_locale.h
7@@ -41,13 +41,22 @@
8
9 #include <clocale>
10
11+#ifdef __UCLIBC__
12+#include <features.h>
13+#include <ctype.h>
14+#endif
15+
16 #define _GLIBCXX_NUM_CATEGORIES 0
17
18 namespace std _GLIBCXX_VISIBILITY(default)
19 {
20 _GLIBCXX_BEGIN_NAMESPACE_VERSION
21
22+#ifdef __UCLIBC__
23+ typedef __ctype_touplow_t* __c_locale;
24+#else
25 typedef int* __c_locale;
26+#endif
27
28 // Convert numeric value of type double and long double to string and
29 // return length of string. If vsnprintf is available use it, otherwise
30Index: gcc-4.6.0/libstdc++-v3/config/os/gnu-linux/ctype_base.h
31===================================================================
32--- gcc-4.6.0.orig/libstdc++-v3/config/os/gnu-linux/ctype_base.h
33+++ gcc-4.6.0/libstdc++-v3/config/os/gnu-linux/ctype_base.h
34@@ -34,6 +34,11 @@
35
36 // Information as gleaned from /usr/include/ctype.h
37
38+#ifdef __UCLIBC__
39+#include <features.h>
40+#include <ctype.h>
41+#endif
42+
43 namespace std _GLIBCXX_VISIBILITY(default)
44 {
45 _GLIBCXX_BEGIN_NAMESPACE_VERSION
46@@ -42,7 +47,11 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
47 struct ctype_base
48 {
49 // Non-standard typedefs.
50+#ifdef __UCLIBC__
51+ typedef const __ctype_touplow_t* __to_type;
52+#else
53 typedef const int* __to_type;
54+#endif
55
56 // NB: Offsets into ctype<char>::_M_table force a particular size
57 // on the mask type. Because of this, we don't use an enum.
58Index: gcc-4.6.0/libstdc++-v3/config/locale/generic/c_locale.cc
59===================================================================
60--- gcc-4.6.0.orig/libstdc++-v3/config/locale/generic/c_locale.cc
61+++ gcc-4.6.0/libstdc++-v3/config/locale/generic/c_locale.cc
62@@ -264,5 +264,10 @@ _GLIBCXX_END_NAMESPACE_VERSION
63 #ifdef _GLIBCXX_LONG_DOUBLE_COMPAT
64 #define _GLIBCXX_LDBL_COMPAT(dbl, ldbl) \
65 extern "C" void ldbl (void) __attribute__ ((alias (#dbl)))
66+#ifdef __UCLIBC__
67+// This is because __c_locale is of type __ctype_touplow_t* which is short on uclibc. for glibc its int*
68+_GLIBCXX_LDBL_COMPAT(_ZSt14__convert_to_vIdEvPKcRT_RSt12_Ios_IostateRKPs, _ZSt14__convert_to_vIeEvPKcRT_RSt12_Ios_IostateRKPs);
69+#else
70 _GLIBCXX_LDBL_COMPAT(_ZSt14__convert_to_vIdEvPKcRT_RSt12_Ios_IostateRKPi, _ZSt14__convert_to_vIeEvPKcRT_RSt12_Ios_IostateRKPi);
71+#endif
72 #endif // _GLIBCXX_LONG_DOUBLE_COMPAT
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-with-linker-hash-style.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-with-linker-hash-style.patch
new file mode 100644
index 000000000..94b61cdcc
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/gcc-with-linker-hash-style.patch
@@ -0,0 +1,196 @@
1Upstream-Status: Backport
2Signed-off-by: Khem Raj <raj.khem@gmail.com>
3
4commit 3cb9bbfa927aa187048534f9069202c017a78e38
5Author: ppluzhnikov <ppluzhnikov@138bc75d-0d04-0410-961f-82ee72b054a4>
6Date: Wed May 11 18:28:14 2011 +0000
7
8 2011-05-11 Satoru Takabayashi <satorux@google.com>
9 Paul Pluzhnikov <ppluzhnikov@google.com>
10
11 * gcc/doc/install.texi (Configuration): Document
12 --with-linker-hash-style.
13 * gcc/gcc.c (init_spec): Handle LINKER_HASH_STYLE.
14 * gcc/config.in: Add LINKER_HASH_STYLE.
15 * gcc/configure.ac: Add --with-linker-hash-style.
16 * gcc/configure: Regenerate.
17
18
19
20 git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@173668 138bc75d-0d04-0410-961f-82ee72b054a4
21
22Index: gcc-4_6-branch/gcc/config.in
23===================================================================
24--- gcc-4_6-branch.orig/gcc/config.in 2012-03-04 09:30:04.000000000 -0800
25+++ gcc-4_6-branch/gcc/config.in 2012-03-04 09:32:30.878646575 -0800
26@@ -1583,6 +1583,12 @@
27 #endif
28
29
30+/* The linker hash style */
31+#ifndef USED_FOR_TARGET
32+#undef LINKER_HASH_STYLE
33+#endif
34+
35+
36 /* Define to the name of the LTO plugin DSO that must be passed to the
37 linker's -plugin=LIB option. */
38 #ifndef USED_FOR_TARGET
39Index: gcc-4_6-branch/gcc/configure
40===================================================================
41--- gcc-4_6-branch.orig/gcc/configure 2012-03-04 09:30:05.000000000 -0800
42+++ gcc-4_6-branch/gcc/configure 2012-03-04 09:32:39.918647011 -0800
43@@ -915,6 +915,7 @@
44 enable_poison_system_directories
45 enable_plugin
46 enable_libquadmath_support
47+with_linker_hash_style
48 '
49 ac_precious_vars='build_alias
50 host_alias
51@@ -1667,6 +1668,8 @@
52 with the compiler
53 --with-system-zlib use installed libz
54 --with-slibdir=DIR shared libraries in DIR [LIBDIR]
55+ --with-linker-hash-style={sysv,gnu,both}
56+ specify the linker hash style
57
58 Some influential environment variables:
59 CC C compiler command
60@@ -17501,7 +17504,7 @@
61 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
62 lt_status=$lt_dlunknown
63 cat > conftest.$ac_ext <<_LT_EOF
64-#line 17504 "configure"
65+#line 17507 "configure"
66 #include "confdefs.h"
67
68 #if HAVE_DLFCN_H
69@@ -17607,7 +17610,7 @@
70 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
71 lt_status=$lt_dlunknown
72 cat > conftest.$ac_ext <<_LT_EOF
73-#line 17610 "configure"
74+#line 17613 "configure"
75 #include "confdefs.h"
76
77 #if HAVE_DLFCN_H
78@@ -26432,6 +26435,36 @@
79 fi
80
81
82+# Specify what hash style to use by default.
83+
84+# Check whether --with-linker-hash-style was given.
85+if test "${with_linker_hash_style+set}" = set; then :
86+ withval=$with_linker_hash_style; case x"$withval" in
87+ xsysv)
88+ LINKER_HASH_STYLE=sysv
89+ ;;
90+ xgnu)
91+ LINKER_HASH_STYLE=gnu
92+ ;;
93+ xboth)
94+ LINKER_HASH_STYLE=both
95+ ;;
96+ *)
97+ as_fn_error "$withval is an invalid option to --with-linker-hash-style" "$LINENO" 5
98+ ;;
99+ esac
100+else
101+ LINKER_HASH_STYLE=''
102+fi
103+
104+if test x"${LINKER_HASH_STYLE}" != x; then
105+
106+cat >>confdefs.h <<_ACEOF
107+#define LINKER_HASH_STYLE "$LINKER_HASH_STYLE"
108+_ACEOF
109+
110+fi
111+
112 # Configure the subdirectories
113 # AC_CONFIG_SUBDIRS($subdirs)
114
115Index: gcc-4_6-branch/gcc/configure.ac
116===================================================================
117--- gcc-4_6-branch.orig/gcc/configure.ac 2012-03-04 09:30:05.000000000 -0800
118+++ gcc-4_6-branch/gcc/configure.ac 2012-03-04 09:32:30.890646574 -0800
119@@ -4905,6 +4905,30 @@
120 fi
121
122
123+# Specify what hash style to use by default.
124+AC_ARG_WITH([linker-hash-style],
125+[AC_HELP_STRING([--with-linker-hash-style={sysv,gnu,both}],
126+ [specify the linker hash style])],
127+[case x"$withval" in
128+ xsysv)
129+ LINKER_HASH_STYLE=sysv
130+ ;;
131+ xgnu)
132+ LINKER_HASH_STYLE=gnu
133+ ;;
134+ xboth)
135+ LINKER_HASH_STYLE=both
136+ ;;
137+ *)
138+ AC_MSG_ERROR([$withval is an invalid option to --with-linker-hash-style])
139+ ;;
140+ esac],
141+[LINKER_HASH_STYLE=''])
142+if test x"${LINKER_HASH_STYLE}" != x; then
143+ AC_DEFINE_UNQUOTED(LINKER_HASH_STYLE, "$LINKER_HASH_STYLE",
144+ [The linker hash style])
145+fi
146+
147 # Configure the subdirectories
148 # AC_CONFIG_SUBDIRS($subdirs)
149
150Index: gcc-4_6-branch/gcc/doc/install.texi
151===================================================================
152--- gcc-4_6-branch.orig/gcc/doc/install.texi 2012-03-03 00:46:39.000000000 -0800
153+++ gcc-4_6-branch/gcc/doc/install.texi 2012-03-04 09:32:30.894646574 -0800
154@@ -1665,6 +1665,11 @@
155 support @option{--build-id} option, a warning is issued and the
156 @option{--enable-linker-build-id} option is ignored. The default is off.
157
158+@item --with-linker-hash-style=@var{choice}
159+Tells GCC to pass @option{--hash-style=@var{choice}} option to the
160+linker for all final links. @var{choice} can be one of
161+@samp{sysv}, @samp{gnu}, and @samp{both} where @samp{sysv} is the default.
162+
163 @item --enable-gnu-unique-object
164 @itemx --disable-gnu-unique-object
165 Tells GCC to use the gnu_unique_object relocation for C++ template
166Index: gcc-4_6-branch/gcc/gcc.c
167===================================================================
168--- gcc-4_6-branch.orig/gcc/gcc.c 2012-03-04 09:30:04.000000000 -0800
169+++ gcc-4_6-branch/gcc/gcc.c 2012-03-04 09:32:30.894646574 -0800
170@@ -1427,7 +1427,8 @@
171 }
172 #endif
173
174-#if defined LINK_EH_SPEC || defined LINK_BUILDID_SPEC
175+#if defined LINK_EH_SPEC || defined LINK_BUILDID_SPEC || \
176+ defined LINKER_HASH_STYLE
177 # ifdef LINK_BUILDID_SPEC
178 /* Prepend LINK_BUILDID_SPEC to whatever link_spec we had before. */
179 obstack_grow (&obstack, LINK_BUILDID_SPEC, sizeof(LINK_BUILDID_SPEC) - 1);
180@@ -1436,6 +1437,16 @@
181 /* Prepend LINK_EH_SPEC to whatever link_spec we had before. */
182 obstack_grow (&obstack, LINK_EH_SPEC, sizeof(LINK_EH_SPEC) - 1);
183 # endif
184+# ifdef LINKER_HASH_STYLE
185+ /* Prepend --hash-style=LINKER_HASH_STYLE to whatever link_spec we had
186+ before. */
187+ {
188+ static const char hash_style[] = "--hash-style=";
189+ obstack_grow (&obstack, hash_style, sizeof(hash_style) - 1);
190+ obstack_grow (&obstack, LINKER_HASH_STYLE, sizeof(LINKER_HASH_STYLE) - 1);
191+ obstack_1grow (&obstack, ' ');
192+ }
193+# endif
194 obstack_grow0 (&obstack, link_spec, strlen (link_spec));
195 link_spec = XOBFINISH (&obstack, const char *);
196 #endif
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/fix_linaro_106872.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/fix_linaro_106872.patch
deleted file mode 100644
index ef33afff7..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/fix_linaro_106872.patch
+++ /dev/null
@@ -1,45 +0,0 @@
1Index: gcc-4_6-branch/gcc/config/arm/arm.c
2===================================================================
3--- gcc-4_6-branch.orig/gcc/config/arm/arm.c 2012-03-05 17:14:09.901129286 -0800
4+++ gcc-4_6-branch/gcc/config/arm/arm.c 2012-03-05 17:18:23.061141606 -0800
5@@ -17525,6 +17525,13 @@
6 }
7 return;
8
9+ case 'v':
10+ {
11+ gcc_assert (GET_CODE (x) == CONST_DOUBLE);
12+ fprintf (stream, "#%d", vfp3_const_double_for_fract_bits (x));
13+ return;
14+ }
15+
16 /* Register specifier for vld1.16/vst1.16. Translate the S register
17 number into a D register number and element index. */
18 case 'z':
19@@ -24925,4 +24932,26 @@
20 return 4;
21 }
22
23+int
24+vfp3_const_double_for_fract_bits (rtx operand)
25+{
26+ REAL_VALUE_TYPE r0;
27+
28+ if (GET_CODE (operand) != CONST_DOUBLE)
29+ return 0;
30+
31+ REAL_VALUE_FROM_CONST_DOUBLE (r0, operand);
32+ if (exact_real_inverse (DFmode, &r0))
33+ {
34+ if (exact_real_truncate (DFmode, &r0))
35+ {
36+ HOST_WIDE_INT value = real_to_integer (&r0);
37+ value = value & 0xffffffff;
38+ if ((value != 0) && ( (value & (value - 1)) == 0))
39+ return int_log2 (value);
40+ }
41+ }
42+ return 0;
43+}
44+
45 #include "gt-arm.h"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106720.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106720.patch
deleted file mode 100644
index 4c573f401..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106720.patch
+++ /dev/null
@@ -1,51 +0,0 @@
12011-02-21 Andrew Stubbs <ams@codesourcery.com>
2 Julian Brown <julian@codesourcery.com>
3 Mark Shinwell <shinwell@codesourcery.com>
4
5 Forward-ported from Linaro GCC 4.5 (bzr99324).
6
7 gcc/
8 * config/arm/arm.h (arm_class_likely_spilled_p): Check against
9 LO_REGS only for Thumb-1.
10 (MODE_BASE_REG_CLASS): Restrict base registers to those which can
11 be used in short instructions when optimising for size on Thumb-2.
12
13=== modified file 'gcc/config/arm/arm.c'
14--- old/gcc/config/arm/arm.c 2011-01-29 03:20:57 +0000
15+++ new/gcc/config/arm/arm.c 2011-02-21 14:04:51 +0000
16@@ -22304,14 +22304,16 @@
17
18 /* Implement TARGET_CLASS_LIKELY_SPILLED_P.
19
20- We need to define this for LO_REGS on thumb. Otherwise we can end up
21- using r0-r4 for function arguments, r7 for the stack frame and don't
22- have enough left over to do doubleword arithmetic. */
23-
24+ We need to define this for LO_REGS on Thumb-1. Otherwise we can end up
25+ using r0-r4 for function arguments, r7 for the stack frame and don't have
26+ enough left over to do doubleword arithmetic. For Thumb-2 all the
27+ potentially problematic instructions accept high registers so this is not
28+ necessary. Care needs to be taken to avoid adding new Thumb-2 patterns
29+ that require many low registers. */
30 static bool
31 arm_class_likely_spilled_p (reg_class_t rclass)
32 {
33- if ((TARGET_THUMB && rclass == LO_REGS)
34+ if ((TARGET_THUMB1 && rclass == LO_REGS)
35 || rclass == CC_REG)
36 return true;
37
38
39=== modified file 'gcc/config/arm/arm.h'
40--- old/gcc/config/arm/arm.h 2011-01-29 03:20:57 +0000
41+++ new/gcc/config/arm/arm.h 2011-02-21 14:04:51 +0000
42@@ -1185,7 +1185,7 @@
43 when addressing quantities in QI or HI mode; if we don't know the
44 mode, then we must be conservative. */
45 #define MODE_BASE_REG_CLASS(MODE) \
46- (TARGET_32BIT ? CORE_REGS : \
47+ (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \
48 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
49
50 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
51
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106733.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106733.patch
deleted file mode 100644
index 4b0079e1d..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106733.patch
+++ /dev/null
@@ -1,653 +0,0 @@
12011-03-27 Ira Rosen <ira.rosen@linaro.org>
2
3 gcc/
4 * doc/invoke.texi (max-stores-to-sink): Document.
5 * params.h (MAX_STORES_TO_SINK): Define.
6 * opts.c (finish_options): Set MAX_STORES_TO_SINK to 0
7 if either vectorization or if-conversion is disabled.
8 * tree-data-ref.c (dr_equal_offsets_p1): Moved and renamed from
9 tree-vect-data-refs.c vect_equal_offsets.
10 (dr_equal_offsets_p): New function.
11 (find_data_references_in_bb): Remove static.
12 * tree-data-ref.h (find_data_references_in_bb): Declare.
13 (dr_equal_offsets_p): Likewise.
14 * tree-vect-data-refs.c (vect_equal_offsets): Move to tree-data-ref.c.
15 (vect_drs_dependent_in_basic_block): Update calls to
16 vect_equal_offsets.
17 (vect_check_interleaving): Likewise.
18 * tree-ssa-phiopt.c: Include cfgloop.h and tree-data-ref.h.
19 (cond_if_else_store_replacement): Rename to...
20 (cond_if_else_store_replacement_1): ... this. Change arguments and
21 documentation.
22 (cond_if_else_store_replacement): New function.
23 * Makefile.in (tree-ssa-phiopt.o): Adjust dependencies.
24 * params.def (PARAM_MAX_STORES_TO_SINK): Define.
25
26 gcc/testsuite/
27 * gcc.dg/vect/vect-cselim-1.c: New test.
28 * gcc.dg/vect/vect-cselim-2.c: New test.
29
30=== modified file 'gcc/Makefile.in'
31--- old/gcc/Makefile.in 2011-03-26 09:20:34 +0000
32+++ new/gcc/Makefile.in 2011-04-18 11:31:29 +0000
33@@ -2422,7 +2422,8 @@
34 tree-ssa-phiopt.o : tree-ssa-phiopt.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
35 $(TM_H) $(GGC_H) $(TREE_H) $(TM_P_H) $(BASIC_BLOCK_H) \
36 $(TREE_FLOW_H) $(TREE_PASS_H) $(TREE_DUMP_H) langhooks.h $(FLAGS_H) \
37- $(DIAGNOSTIC_H) $(TIMEVAR_H) pointer-set.h domwalk.h
38+ $(DIAGNOSTIC_H) $(TIMEVAR_H) pointer-set.h domwalk.h $(CFGLOOP_H) \
39+ $(TREE_DATA_REF_H)
40 tree-nrv.o : tree-nrv.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
41 $(TM_H) $(TREE_H) $(FUNCTION_H) $(BASIC_BLOCK_H) $(FLAGS_H) \
42 $(DIAGNOSTIC_H) $(TREE_FLOW_H) $(TIMEVAR_H) $(TREE_DUMP_H) $(TREE_PASS_H) \
43
44=== modified file 'gcc/doc/invoke.texi'
45--- old/gcc/doc/invoke.texi 2011-03-29 14:24:42 +0000
46+++ new/gcc/doc/invoke.texi 2011-04-18 11:31:29 +0000
47@@ -8909,6 +8909,11 @@
48 The maximum number of namespaces to consult for suggestions when C++
49 name lookup fails for an identifier. The default is 1000.
50
51+@item max-stores-to-sink
52+The maximum number of conditional stores paires that can be sunk. Set to 0
53+if either vectorization (@option{-ftree-vectorize}) or if-conversion
54+(@option{-ftree-loop-if-convert}) is disabled. The default is 2.
55+
56 @end table
57 @end table
58
59
60=== modified file 'gcc/opts.c'
61--- old/gcc/opts.c 2011-02-17 22:51:57 +0000
62+++ new/gcc/opts.c 2011-03-27 09:38:18 +0000
63@@ -823,6 +823,12 @@
64 opts->x_flag_split_stack = 0;
65 }
66 }
67+
68+ /* Set PARAM_MAX_STORES_TO_SINK to 0 if either vectorization or if-conversion
69+ is disabled. */
70+ if (!opts->x_flag_tree_vectorize || !opts->x_flag_tree_loop_if_convert)
71+ maybe_set_param_value (PARAM_MAX_STORES_TO_SINK, 0,
72+ opts->x_param_values, opts_set->x_param_values);
73 }
74
75 #define LEFT_COLUMN 27
76
77=== modified file 'gcc/params.def'
78--- old/gcc/params.def 2011-03-26 09:20:34 +0000
79+++ new/gcc/params.def 2011-04-18 11:31:29 +0000
80@@ -883,6 +883,13 @@
81 "name lookup fails",
82 1000, 0, 0)
83
84+/* Maximum number of conditional store pairs that can be sunk. */
85+DEFPARAM (PARAM_MAX_STORES_TO_SINK,
86+ "max-stores-to-sink",
87+ "Maximum number of conditional store pairs that can be sunk",
88+ 2, 0, 0)
89+
90+
91 /*
92 Local variables:
93 mode:c
94
95=== modified file 'gcc/params.h'
96--- old/gcc/params.h 2011-01-13 13:41:03 +0000
97+++ new/gcc/params.h 2011-03-27 09:38:18 +0000
98@@ -206,4 +206,6 @@
99 PARAM_VALUE (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO)
100 #define MIN_NONDEBUG_INSN_UID \
101 PARAM_VALUE (PARAM_MIN_NONDEBUG_INSN_UID)
102+#define MAX_STORES_TO_SINK \
103+ PARAM_VALUE (PARAM_MAX_STORES_TO_SINK)
104 #endif /* ! GCC_PARAMS_H */
105
106=== added file 'gcc/testsuite/gcc.dg/vect/vect-cselim-1.c'
107--- old/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 1970-01-01 00:00:00 +0000
108+++ new/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 2011-03-27 09:38:18 +0000
109@@ -0,0 +1,86 @@
110+/* { dg-require-effective-target vect_int } */
111+
112+#include <stdarg.h>
113+#include "tree-vect.h"
114+
115+#define N 50
116+
117+typedef struct {
118+ short a;
119+ short b;
120+} data;
121+
122+data in1[N], in2[N], out[N];
123+short result[N*2] = {7,-7,9,-6,11,-5,13,-4,15,-3,17,-2,19,-1,21,0,23,1,25,2,27,3,29,4,31,5,33,6,35,7,37,8,39,9,41,10,43,11,45,12,47,13,49,14,51,15,53,16,55,17,57,18,59,19,61,20,63,21,65,22,67,23,69,24,71,25,73,26,75,27,77,28,79,29,81,30,83,31,85,32,87,33,89,34,91,35,93,36,95,37,97,38,99,39,101,40,103,41,105,42};
124+short out1[N], out2[N];
125+
126+__attribute__ ((noinline)) void
127+foo ()
128+{
129+ int i;
130+ short c, d;
131+
132+ /* Vectorizable with conditional store sinking. */
133+ for (i = 0; i < N; i++)
134+ {
135+ c = in1[i].b;
136+ d = in2[i].b;
137+
138+ if (c >= d)
139+ {
140+ out[i].b = c;
141+ out[i].a = d + 5;
142+ }
143+ else
144+ {
145+ out[i].b = d - 12;
146+ out[i].a = c + d;
147+ }
148+ }
149+
150+ /* Not vectorizable. */
151+ for (i = 0; i < N; i++)
152+ {
153+ c = in1[i].b;
154+ d = in2[i].b;
155+
156+ if (c >= d)
157+ {
158+ out1[i] = c;
159+ }
160+ else
161+ {
162+ out2[i] = c + d;
163+ }
164+ }
165+}
166+
167+int
168+main (void)
169+{
170+ int i;
171+
172+ check_vect ();
173+
174+ for (i = 0; i < N; i++)
175+ {
176+ in1[i].a = i;
177+ in1[i].b = i + 2;
178+ in2[i].a = 5;
179+ in2[i].b = i + 5;
180+ __asm__ volatile ("");
181+ }
182+
183+ foo ();
184+
185+ for (i = 0; i < N; i++)
186+ {
187+ if (out[i].a != result[2*i] || out[i].b != result[2*i+1])
188+ abort ();
189+ }
190+
191+ return 0;
192+}
193+
194+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || {! vect_strided } } } } } */
195+/* { dg-final { cleanup-tree-dump "vect" } } */
196
197=== added file 'gcc/testsuite/gcc.dg/vect/vect-cselim-2.c'
198--- old/gcc/testsuite/gcc.dg/vect/vect-cselim-2.c 1970-01-01 00:00:00 +0000
199+++ new/gcc/testsuite/gcc.dg/vect/vect-cselim-2.c 2011-03-27 09:38:18 +0000
200@@ -0,0 +1,65 @@
201+/* { dg-require-effective-target vect_int } */
202+
203+#include <stdarg.h>
204+#include "tree-vect.h"
205+
206+#define N 50
207+
208+int a[N], b[N], in1[N], in2[N];
209+int result[2*N] = {5,-7,7,-6,9,-5,11,-4,13,-3,15,-2,17,-1,19,0,21,1,23,2,25,3,27,4,29,5,31,6,33,7,35,8,37,9,39,10,41,11,43,12,45,13,47,14,49,15,51,16,53,17,55,18,57,19,59,20,61,21,63,22,65,23,67,24,69,25,71,26,73,27,75,28,77,29,79,30,81,31,83,32,85,33,87,34,89,35,91,36,93,37,95,38,97,39,99,40,101,41,103,42};
210+
211+__attribute__ ((noinline)) void
212+foo (int *pa, int *pb)
213+{
214+ int i;
215+ int c, d;
216+
217+ /* Store sinking should not work here since the pointers may alias. */
218+ for (i = 0; i < N; i++)
219+ {
220+ c = in1[i];
221+ d = in2[i];
222+
223+ if (c >= d)
224+ {
225+ *pa = c;
226+ *pb = d + 5;
227+ }
228+ else
229+ {
230+ *pb = d - 12;
231+ *pa = c + d;
232+ }
233+
234+ pa++;
235+ pb++;
236+ }
237+}
238+
239+int
240+main (void)
241+{
242+ int i;
243+
244+ check_vect ();
245+
246+ for (i = 0; i < N; i++)
247+ {
248+ in1[i] = i;
249+ in2[i] = i + 5;
250+ __asm__ volatile ("");
251+ }
252+
253+ foo (a, b);
254+
255+ for (i = 0; i < N; i++)
256+ {
257+ if (a[i] != result[2*i] || b[i] != result[2*i+1])
258+ abort ();
259+ }
260+
261+ return 0;
262+}
263+
264+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } } */
265+/* { dg-final { cleanup-tree-dump "vect" } } */
266
267=== modified file 'gcc/tree-data-ref.c'
268--- old/gcc/tree-data-ref.c 2011-02-05 01:39:20 +0000
269+++ new/gcc/tree-data-ref.c 2011-03-27 09:38:18 +0000
270@@ -991,6 +991,48 @@
271 return dr;
272 }
273
274+/* Check if OFFSET1 and OFFSET2 (DR_OFFSETs of some data-refs) are identical
275+ expressions. */
276+static bool
277+dr_equal_offsets_p1 (tree offset1, tree offset2)
278+{
279+ bool res;
280+
281+ STRIP_NOPS (offset1);
282+ STRIP_NOPS (offset2);
283+
284+ if (offset1 == offset2)
285+ return true;
286+
287+ if (TREE_CODE (offset1) != TREE_CODE (offset2)
288+ || (!BINARY_CLASS_P (offset1) && !UNARY_CLASS_P (offset1)))
289+ return false;
290+
291+ res = dr_equal_offsets_p1 (TREE_OPERAND (offset1, 0),
292+ TREE_OPERAND (offset2, 0));
293+
294+ if (!res || !BINARY_CLASS_P (offset1))
295+ return res;
296+
297+ res = dr_equal_offsets_p1 (TREE_OPERAND (offset1, 1),
298+ TREE_OPERAND (offset2, 1));
299+
300+ return res;
301+}
302+
303+/* Check if DRA and DRB have equal offsets. */
304+bool
305+dr_equal_offsets_p (struct data_reference *dra,
306+ struct data_reference *drb)
307+{
308+ tree offset1, offset2;
309+
310+ offset1 = DR_OFFSET (dra);
311+ offset2 = DR_OFFSET (drb);
312+
313+ return dr_equal_offsets_p1 (offset1, offset2);
314+}
315+
316 /* Returns true if FNA == FNB. */
317
318 static bool
319@@ -4294,7 +4336,7 @@
320 DATAREFS. Returns chrec_dont_know when failing to analyze a
321 difficult case, returns NULL_TREE otherwise. */
322
323-static tree
324+tree
325 find_data_references_in_bb (struct loop *loop, basic_block bb,
326 VEC (data_reference_p, heap) **datarefs)
327 {
328
329=== modified file 'gcc/tree-data-ref.h'
330--- old/gcc/tree-data-ref.h 2011-01-25 21:24:23 +0000
331+++ new/gcc/tree-data-ref.h 2011-03-27 09:38:18 +0000
332@@ -426,10 +426,14 @@
333 extern void compute_all_dependences (VEC (data_reference_p, heap) *,
334 VEC (ddr_p, heap) **, VEC (loop_p, heap) *,
335 bool);
336+extern tree find_data_references_in_bb (struct loop *, basic_block,
337+ VEC (data_reference_p, heap) **);
338
339 extern void create_rdg_vertices (struct graph *, VEC (gimple, heap) *);
340 extern bool dr_may_alias_p (const struct data_reference *,
341 const struct data_reference *);
342+extern bool dr_equal_offsets_p (struct data_reference *,
343+ struct data_reference *);
344
345
346 /* Return true when the base objects of data references A and B are
347
348=== modified file 'gcc/tree-ssa-phiopt.c'
349--- old/gcc/tree-ssa-phiopt.c 2010-11-03 15:18:50 +0000
350+++ new/gcc/tree-ssa-phiopt.c 2011-03-27 09:38:18 +0000
351@@ -34,6 +34,8 @@
352 #include "langhooks.h"
353 #include "pointer-set.h"
354 #include "domwalk.h"
355+#include "cfgloop.h"
356+#include "tree-data-ref.h"
357
358 static unsigned int tree_ssa_phiopt (void);
359 static unsigned int tree_ssa_phiopt_worker (bool);
360@@ -1292,35 +1294,18 @@
361 return true;
362 }
363
364-/* Do the main work of conditional store replacement. We already know
365- that the recognized pattern looks like so:
366-
367- split:
368- if (cond) goto THEN_BB; else goto ELSE_BB (edge E1)
369- THEN_BB:
370- X = Y;
371- goto JOIN_BB;
372- ELSE_BB:
373- X = Z;
374- fallthrough (edge E0)
375- JOIN_BB:
376- some more
377-
378- We check that THEN_BB and ELSE_BB contain only one store
379- that the stores have a "simple" RHS. */
380+/* Do the main work of conditional store replacement. */
381
382 static bool
383-cond_if_else_store_replacement (basic_block then_bb, basic_block else_bb,
384- basic_block join_bb)
385+cond_if_else_store_replacement_1 (basic_block then_bb, basic_block else_bb,
386+ basic_block join_bb, gimple then_assign,
387+ gimple else_assign)
388 {
389- gimple then_assign = last_and_only_stmt (then_bb);
390- gimple else_assign = last_and_only_stmt (else_bb);
391 tree lhs_base, lhs, then_rhs, else_rhs;
392 source_location then_locus, else_locus;
393 gimple_stmt_iterator gsi;
394 gimple newphi, new_stmt;
395
396- /* Check if then_bb and else_bb contain only one store each. */
397 if (then_assign == NULL
398 || !gimple_assign_single_p (then_assign)
399 || else_assign == NULL
400@@ -1385,6 +1370,190 @@
401 return true;
402 }
403
404+/* Conditional store replacement. We already know
405+ that the recognized pattern looks like so:
406+
407+ split:
408+ if (cond) goto THEN_BB; else goto ELSE_BB (edge E1)
409+ THEN_BB:
410+ ...
411+ X = Y;
412+ ...
413+ goto JOIN_BB;
414+ ELSE_BB:
415+ ...
416+ X = Z;
417+ ...
418+ fallthrough (edge E0)
419+ JOIN_BB:
420+ some more
421+
422+ We check that it is safe to sink the store to JOIN_BB by verifying that
423+ there are no read-after-write or write-after-write dependencies in
424+ THEN_BB and ELSE_BB. */
425+
426+static bool
427+cond_if_else_store_replacement (basic_block then_bb, basic_block else_bb,
428+ basic_block join_bb)
429+{
430+ gimple then_assign = last_and_only_stmt (then_bb);
431+ gimple else_assign = last_and_only_stmt (else_bb);
432+ VEC (data_reference_p, heap) *then_datarefs, *else_datarefs;
433+ VEC (ddr_p, heap) *then_ddrs, *else_ddrs;
434+ gimple then_store, else_store;
435+ bool found, ok = false, res;
436+ struct data_dependence_relation *ddr;
437+ data_reference_p then_dr, else_dr;
438+ int i, j;
439+ tree then_lhs, else_lhs;
440+ VEC (gimple, heap) *then_stores, *else_stores;
441+ basic_block blocks[3];
442+
443+ if (MAX_STORES_TO_SINK == 0)
444+ return false;
445+
446+ /* Handle the case with single statement in THEN_BB and ELSE_BB. */
447+ if (then_assign && else_assign)
448+ return cond_if_else_store_replacement_1 (then_bb, else_bb, join_bb,
449+ then_assign, else_assign);
450+
451+ /* Find data references. */
452+ then_datarefs = VEC_alloc (data_reference_p, heap, 1);
453+ else_datarefs = VEC_alloc (data_reference_p, heap, 1);
454+ if ((find_data_references_in_bb (NULL, then_bb, &then_datarefs)
455+ == chrec_dont_know)
456+ || !VEC_length (data_reference_p, then_datarefs)
457+ || (find_data_references_in_bb (NULL, else_bb, &else_datarefs)
458+ == chrec_dont_know)
459+ || !VEC_length (data_reference_p, else_datarefs))
460+ {
461+ free_data_refs (then_datarefs);
462+ free_data_refs (else_datarefs);
463+ return false;
464+ }
465+
466+ /* Find pairs of stores with equal LHS. */
467+ then_stores = VEC_alloc (gimple, heap, 1);
468+ else_stores = VEC_alloc (gimple, heap, 1);
469+ FOR_EACH_VEC_ELT (data_reference_p, then_datarefs, i, then_dr)
470+ {
471+ if (DR_IS_READ (then_dr))
472+ continue;
473+
474+ then_store = DR_STMT (then_dr);
475+ then_lhs = gimple_assign_lhs (then_store);
476+ found = false;
477+
478+ FOR_EACH_VEC_ELT (data_reference_p, else_datarefs, j, else_dr)
479+ {
480+ if (DR_IS_READ (else_dr))
481+ continue;
482+
483+ else_store = DR_STMT (else_dr);
484+ else_lhs = gimple_assign_lhs (else_store);
485+
486+ if (operand_equal_p (then_lhs, else_lhs, 0))
487+ {
488+ found = true;
489+ break;
490+ }
491+ }
492+
493+ if (!found)
494+ continue;
495+
496+ VEC_safe_push (gimple, heap, then_stores, then_store);
497+ VEC_safe_push (gimple, heap, else_stores, else_store);
498+ }
499+
500+ /* No pairs of stores found. */
501+ if (!VEC_length (gimple, then_stores)
502+ || VEC_length (gimple, then_stores) > (unsigned) MAX_STORES_TO_SINK)
503+ {
504+ free_data_refs (then_datarefs);
505+ free_data_refs (else_datarefs);
506+ VEC_free (gimple, heap, then_stores);
507+ VEC_free (gimple, heap, else_stores);
508+ return false;
509+ }
510+
511+ /* Compute and check data dependencies in both basic blocks. */
512+ then_ddrs = VEC_alloc (ddr_p, heap, 1);
513+ else_ddrs = VEC_alloc (ddr_p, heap, 1);
514+ compute_all_dependences (then_datarefs, &then_ddrs, NULL, false);
515+ compute_all_dependences (else_datarefs, &else_ddrs, NULL, false);
516+ blocks[0] = then_bb;
517+ blocks[1] = else_bb;
518+ blocks[2] = join_bb;
519+ renumber_gimple_stmt_uids_in_blocks (blocks, 3);
520+
521+ /* Check that there are no read-after-write or write-after-write dependencies
522+ in THEN_BB. */
523+ FOR_EACH_VEC_ELT (ddr_p, then_ddrs, i, ddr)
524+ {
525+ struct data_reference *dra = DDR_A (ddr);
526+ struct data_reference *drb = DDR_B (ddr);
527+
528+ if (DDR_ARE_DEPENDENT (ddr) != chrec_known
529+ && ((DR_IS_READ (dra) && DR_IS_WRITE (drb)
530+ && gimple_uid (DR_STMT (dra)) > gimple_uid (DR_STMT (drb)))
531+ || (DR_IS_READ (drb) && DR_IS_WRITE (dra)
532+ && gimple_uid (DR_STMT (drb)) > gimple_uid (DR_STMT (dra)))
533+ || (DR_IS_WRITE (dra) && DR_IS_WRITE (drb))))
534+ {
535+ free_dependence_relations (then_ddrs);
536+ free_dependence_relations (else_ddrs);
537+ free_data_refs (then_datarefs);
538+ free_data_refs (else_datarefs);
539+ VEC_free (gimple, heap, then_stores);
540+ VEC_free (gimple, heap, else_stores);
541+ return false;
542+ }
543+ }
544+
545+ /* Check that there are no read-after-write or write-after-write dependencies
546+ in ELSE_BB. */
547+ FOR_EACH_VEC_ELT (ddr_p, else_ddrs, i, ddr)
548+ {
549+ struct data_reference *dra = DDR_A (ddr);
550+ struct data_reference *drb = DDR_B (ddr);
551+
552+ if (DDR_ARE_DEPENDENT (ddr) != chrec_known
553+ && ((DR_IS_READ (dra) && DR_IS_WRITE (drb)
554+ && gimple_uid (DR_STMT (dra)) > gimple_uid (DR_STMT (drb)))
555+ || (DR_IS_READ (drb) && DR_IS_WRITE (dra)
556+ && gimple_uid (DR_STMT (drb)) > gimple_uid (DR_STMT (dra)))
557+ || (DR_IS_WRITE (dra) && DR_IS_WRITE (drb))))
558+ {
559+ free_dependence_relations (then_ddrs);
560+ free_dependence_relations (else_ddrs);
561+ free_data_refs (then_datarefs);
562+ free_data_refs (else_datarefs);
563+ VEC_free (gimple, heap, then_stores);
564+ VEC_free (gimple, heap, else_stores);
565+ return false;
566+ }
567+ }
568+
569+ /* Sink stores with same LHS. */
570+ FOR_EACH_VEC_ELT (gimple, then_stores, i, then_store)
571+ {
572+ else_store = VEC_index (gimple, else_stores, i);
573+ res = cond_if_else_store_replacement_1 (then_bb, else_bb, join_bb,
574+ then_store, else_store);
575+ ok = ok || res;
576+ }
577+
578+ free_dependence_relations (then_ddrs);
579+ free_dependence_relations (else_ddrs);
580+ free_data_refs (then_datarefs);
581+ free_data_refs (else_datarefs);
582+ VEC_free (gimple, heap, then_stores);
583+ VEC_free (gimple, heap, else_stores);
584+
585+ return ok;
586+}
587+
588 /* Always do these optimizations if we have SSA
589 trees to work on. */
590 static bool
591
592=== modified file 'gcc/tree-vect-data-refs.c'
593--- old/gcc/tree-vect-data-refs.c 2011-02-25 11:18:14 +0000
594+++ new/gcc/tree-vect-data-refs.c 2011-03-27 09:38:18 +0000
595@@ -289,39 +289,6 @@
596 }
597 }
598
599-
600-/* Function vect_equal_offsets.
601-
602- Check if OFFSET1 and OFFSET2 are identical expressions. */
603-
604-static bool
605-vect_equal_offsets (tree offset1, tree offset2)
606-{
607- bool res;
608-
609- STRIP_NOPS (offset1);
610- STRIP_NOPS (offset2);
611-
612- if (offset1 == offset2)
613- return true;
614-
615- if (TREE_CODE (offset1) != TREE_CODE (offset2)
616- || (!BINARY_CLASS_P (offset1) && !UNARY_CLASS_P (offset1)))
617- return false;
618-
619- res = vect_equal_offsets (TREE_OPERAND (offset1, 0),
620- TREE_OPERAND (offset2, 0));
621-
622- if (!res || !BINARY_CLASS_P (offset1))
623- return res;
624-
625- res = vect_equal_offsets (TREE_OPERAND (offset1, 1),
626- TREE_OPERAND (offset2, 1));
627-
628- return res;
629-}
630-
631-
632 /* Check dependence between DRA and DRB for basic block vectorization.
633 If the accesses share same bases and offsets, we can compare their initial
634 constant offsets to decide whether they differ or not. In case of a read-
635@@ -352,7 +319,7 @@
636 || TREE_CODE (DR_BASE_ADDRESS (drb)) != ADDR_EXPR
637 || TREE_OPERAND (DR_BASE_ADDRESS (dra), 0)
638 != TREE_OPERAND (DR_BASE_ADDRESS (drb),0)))
639- || !vect_equal_offsets (DR_OFFSET (dra), DR_OFFSET (drb)))
640+ || !dr_equal_offsets_p (dra, drb))
641 return true;
642
643 /* Check the types. */
644@@ -402,7 +369,7 @@
645 || TREE_CODE (DR_BASE_ADDRESS (drb)) != ADDR_EXPR
646 || TREE_OPERAND (DR_BASE_ADDRESS (dra), 0)
647 != TREE_OPERAND (DR_BASE_ADDRESS (drb),0)))
648- || !vect_equal_offsets (DR_OFFSET (dra), DR_OFFSET (drb))
649+ || !dr_equal_offsets_p (dra, drb)
650 || !tree_int_cst_compare (DR_INIT (dra), DR_INIT (drb))
651 || DR_IS_READ (dra) != DR_IS_READ (drb))
652 return false;
653
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106737.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106737.patch
deleted file mode 100644
index 017b1df7e..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106737.patch
+++ /dev/null
@@ -1,126 +0,0 @@
12011-04-21 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF:
4
5 2008-12-03 Daniel Jacobowitz <dan@codesourcery.com>
6
7 gcc/testsuite/
8 * gcc.dg/vect/vect-shift-3.c, gcc.dg/vect/vect-shift-4.c: New.
9 * lib/target-supports.exp (check_effective_target_vect_shift_char): New
10 function.
11
12=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-3.c'
13--- old/gcc/testsuite/gcc.dg/vect/vect-shift-3.c 1970-01-01 00:00:00 +0000
14+++ new/gcc/testsuite/gcc.dg/vect/vect-shift-3.c 2011-04-21 13:51:06 +0000
15@@ -0,0 +1,37 @@
16+/* { dg-require-effective-target vect_shift } */
17+/* { dg-require-effective-target vect_int } */
18+
19+#include "tree-vect.h"
20+
21+#define N 32
22+
23+unsigned short dst[N] __attribute__((aligned(N)));
24+unsigned short src[N] __attribute__((aligned(N)));
25+
26+__attribute__ ((noinline))
27+void array_shift(void)
28+{
29+ int i;
30+ for (i = 0; i < N; i++)
31+ dst[i] = src[i] >> 3;
32+}
33+
34+int main()
35+{
36+ volatile int i;
37+ check_vect ();
38+
39+ for (i = 0; i < N; i++)
40+ src[i] = i << 3;
41+
42+ array_shift ();
43+
44+ for (i = 0; i < N; i++)
45+ if (dst[i] != i)
46+ abort ();
47+
48+ return 0;
49+}
50+
51+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
52+/* { dg-final { cleanup-tree-dump "vect" } } */
53
54=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-4.c'
55--- old/gcc/testsuite/gcc.dg/vect/vect-shift-4.c 1970-01-01 00:00:00 +0000
56+++ new/gcc/testsuite/gcc.dg/vect/vect-shift-4.c 2011-04-21 13:51:06 +0000
57@@ -0,0 +1,37 @@
58+/* { dg-require-effective-target vect_shift_char } */
59+/* { dg-require-effective-target vect_int } */
60+
61+#include "tree-vect.h"
62+
63+#define N 32
64+
65+unsigned char dst[N] __attribute__((aligned(N)));
66+unsigned char src[N] __attribute__((aligned(N)));
67+
68+__attribute__ ((noinline))
69+void array_shift(void)
70+{
71+ int i;
72+ for (i = 0; i < N; i++)
73+ dst[i] = src[i] >> 3;
74+}
75+
76+int main()
77+{
78+ volatile int i;
79+ check_vect ();
80+
81+ for (i = 0; i < N; i++)
82+ src[i] = i << 3;
83+
84+ array_shift ();
85+
86+ for (i = 0; i < N; i++)
87+ if (dst[i] != i)
88+ abort ();
89+
90+ return 0;
91+}
92+
93+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
94+/* { dg-final { cleanup-tree-dump "vect" } } */
95
96=== modified file 'gcc/testsuite/lib/target-supports.exp'
97--- old/gcc/testsuite/lib/target-supports.exp 2011-02-19 15:31:15 +0000
98+++ new/gcc/testsuite/lib/target-supports.exp 2011-04-21 13:51:06 +0000
99@@ -2308,6 +2308,26 @@
100 }
101
102
103+# Return 1 if the target supports hardware vector shift operation for char.
104+
105+proc check_effective_target_vect_shift_char { } {
106+ global et_vect_shift_char_saved
107+
108+ if [info exists et_vect_shift_char_saved] {
109+ verbose "check_effective_target_vect_shift_char: using cached result" 2
110+ } else {
111+ set et_vect_shift_char_saved 0
112+ if { ([istarget powerpc*-*-*]
113+ && ![istarget powerpc-*-linux*paired*])
114+ || [check_effective_target_arm32] } {
115+ set et_vect_shift_char_saved 1
116+ }
117+ }
118+
119+ verbose "check_effective_target_vect_shift_char: returning $et_vect_shift_char_saved" 2
120+ return $et_vect_shift_char_saved
121+}
122+
123 # Return 1 if the target supports hardware vectors of long, 0 otherwise.
124 #
125 # This can change for different subtargets so do not cache the result.
126
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106738.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106738.patch
deleted file mode 100644
index 3dde3b29a..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106738.patch
+++ /dev/null
@@ -1,177 +0,0 @@
12011-04-27 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from FSF:
4
5 2011-04-03 Richard Guenther <rguenther@suse.de>
6 Ira Rosen <ira.rosen@linaro.org>
7
8 gcc/
9 * tree-if-conv.c (memrefs_read_or_written_unconditionally): Strip all
10 non-variable offsets and compare the remaining bases of the two
11 accesses instead of looking for exact same data-ref.
12
13 gcc/testsuite/
14 * gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c: New test.
15 * gcc.dg/vect/vect.exp: Run if-cvt-stores-vect* tests with
16 -ftree-loop-if-convert-stores.
17
18=== added file 'gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c'
19--- old/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c 1970-01-01 00:00:00 +0000
20+++ new/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c 2011-04-24 07:45:49 +0000
21@@ -0,0 +1,69 @@
22+/* { dg-require-effective-target vect_int } */
23+
24+#include <stdarg.h>
25+#include "tree-vect.h"
26+
27+#define N 50
28+
29+typedef struct {
30+ short a;
31+ short b;
32+} data;
33+
34+data in1[N], in2[N], out[N];
35+short result[N*2] = {10,-7,11,-6,12,-5,13,-4,14,-3,15,-2,16,-1,17,0,18,1,19,2,20,3,21,4,22,5,23,6,24,7,25,8,26,9,27,10,28,11,29,12,30,13,31,14,32,15,33,16,34,17,35,18,36,19,37,20,38,21,39,22,40,23,41,24,42,25,43,26,44,27,45,28,46,29,47,30,48,31,49,32,50,33,51,34,52,35,53,36,54,37,55,38,56,39,57,40,58,41,59,42};
36+short out1[N], out2[N];
37+
38+__attribute__ ((noinline)) void
39+foo ()
40+{
41+ int i;
42+ short c, d;
43+
44+ for (i = 0; i < N; i++)
45+ {
46+ c = in1[i].b;
47+ d = in2[i].b;
48+
49+ if (c >= d)
50+ {
51+ out[i].b = in1[i].a;
52+ out[i].a = d + 5;
53+ }
54+ else
55+ {
56+ out[i].b = d - 12;
57+ out[i].a = in2[i].a + d;
58+ }
59+ }
60+}
61+
62+int
63+main (void)
64+{
65+ int i;
66+
67+ check_vect ();
68+
69+ for (i = 0; i < N; i++)
70+ {
71+ in1[i].a = i;
72+ in1[i].b = i + 2;
73+ in2[i].a = 5;
74+ in2[i].b = i + 5;
75+ __asm__ volatile ("");
76+ }
77+
78+ foo ();
79+
80+ for (i = 0; i < N; i++)
81+ {
82+ if (out[i].a != result[2*i] || out[i].b != result[2*i+1])
83+ abort ();
84+ }
85+
86+ return 0;
87+}
88+
89+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || {! vect_strided } } } } } */
90+/* { dg-final { cleanup-tree-dump "vect" } } */
91
92=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp'
93--- old/gcc/testsuite/gcc.dg/vect/vect.exp 2010-11-22 21:49:19 +0000
94+++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2011-04-24 07:45:49 +0000
95@@ -210,6 +210,12 @@
96 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/ggc-*.\[cS\]]] \
97 "" $DEFAULT_VECTCFLAGS
98
99+# -ftree-loop-if-convert-stores
100+set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
101+lappend DEFAULT_VECTCFLAGS "-ftree-loop-if-convert-stores"
102+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/if-cvt-stores-vect-*.\[cS\]]] \
103+ "" $DEFAULT_VECTCFLAGS
104+
105 # With -O3.
106 # Don't allow IPA cloning, because it throws our counts out of whack.
107 set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
108
109=== modified file 'gcc/tree-if-conv.c'
110--- old/gcc/tree-if-conv.c 2011-02-23 16:49:52 +0000
111+++ new/gcc/tree-if-conv.c 2011-04-24 07:45:49 +0000
112@@ -464,8 +464,8 @@
113 /* Returns true when the memory references of STMT are read or written
114 unconditionally. In other words, this function returns true when
115 for every data reference A in STMT there exist other accesses to
116- the same data reference with predicates that add up (OR-up) to the
117- true predicate: this ensures that the data reference A is touched
118+ a data reference with the same base with predicates that add up (OR-up) to
119+ the true predicate: this ensures that the data reference A is touched
120 (read or written) on every iteration of the if-converted loop. */
121
122 static bool
123@@ -489,21 +489,38 @@
124 continue;
125
126 for (j = 0; VEC_iterate (data_reference_p, drs, j, b); j++)
127- if (DR_STMT (b) != stmt
128- && same_data_refs (a, b))
129- {
130- tree cb = bb_predicate (gimple_bb (DR_STMT (b)));
131-
132- if (DR_RW_UNCONDITIONALLY (b) == 1
133- || is_true_predicate (cb)
134- || is_true_predicate (ca = fold_or_predicates (EXPR_LOCATION (cb),
135- ca, cb)))
136- {
137- DR_RW_UNCONDITIONALLY (a) = 1;
138- DR_RW_UNCONDITIONALLY (b) = 1;
139- found = true;
140- break;
141- }
142+ {
143+ tree ref_base_a = DR_REF (a);
144+ tree ref_base_b = DR_REF (b);
145+
146+ if (DR_STMT (b) == stmt)
147+ continue;
148+
149+ while (TREE_CODE (ref_base_a) == COMPONENT_REF
150+ || TREE_CODE (ref_base_a) == IMAGPART_EXPR
151+ || TREE_CODE (ref_base_a) == REALPART_EXPR)
152+ ref_base_a = TREE_OPERAND (ref_base_a, 0);
153+
154+ while (TREE_CODE (ref_base_b) == COMPONENT_REF
155+ || TREE_CODE (ref_base_b) == IMAGPART_EXPR
156+ || TREE_CODE (ref_base_b) == REALPART_EXPR)
157+ ref_base_b = TREE_OPERAND (ref_base_b, 0);
158+
159+ if (!operand_equal_p (ref_base_a, ref_base_b, 0))
160+ {
161+ tree cb = bb_predicate (gimple_bb (DR_STMT (b)));
162+
163+ if (DR_RW_UNCONDITIONALLY (b) == 1
164+ || is_true_predicate (cb)
165+ || is_true_predicate (ca
166+ = fold_or_predicates (EXPR_LOCATION (cb), ca, cb)))
167+ {
168+ DR_RW_UNCONDITIONALLY (a) = 1;
169+ DR_RW_UNCONDITIONALLY (b) = 1;
170+ found = true;
171+ break;
172+ }
173+ }
174 }
175
176 if (!found)
177
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106739.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106739.patch
deleted file mode 100644
index 2c14ceb8c..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106739.patch
+++ /dev/null
@@ -1,140 +0,0 @@
12011-05-02 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from FSF:
4
5 2011-03-27 Ira Rosen <ira.rosen@linaro.org>
6
7 gcc/
8 * config/arm/arm.c (arm_autovectorize_vector_sizes): New function.
9 (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Define.
10
11 gcc/testsuite/
12 * gcc.dg/vect/vect-outer-5.c: Reduce the distance between data
13 accesses to preserve the meaning of the test for doubleword vectors.
14 * gcc.dg/vect/no-vfa-pr29145.c: Likewise.
15 * gcc.dg/vect/slp-3.c: Reduce the loop bound for the same reason.
16
17=== modified file 'gcc/config/arm/arm.c'
18--- old/gcc/config/arm/arm.c 2011-03-02 11:38:43 +0000
19+++ new/gcc/config/arm/arm.c 2011-04-28 11:46:58 +0000
20@@ -250,6 +250,7 @@
21 bool is_packed);
22 static void arm_conditional_register_usage (void);
23 static reg_class_t arm_preferred_rename_class (reg_class_t rclass);
24+static unsigned int arm_autovectorize_vector_sizes (void);
25
26
27 /* Table of machine attributes. */
28@@ -395,6 +396,9 @@
29 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
30 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
31 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
32+#undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
33+#define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
34+ arm_autovectorize_vector_sizes
35
36 #undef TARGET_MACHINE_DEPENDENT_REORG
37 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
38@@ -23511,6 +23515,12 @@
39 }
40 }
41
42+static unsigned int
43+arm_autovectorize_vector_sizes (void)
44+{
45+ return TARGET_NEON_VECTORIZE_QUAD ? 16 | 8 : 0;
46+}
47+
48 static bool
49 arm_vector_alignment_reachable (const_tree type, bool is_packed)
50 {
51
52=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c'
53--- old/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c 2010-10-04 14:59:30 +0000
54+++ new/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c 2011-04-28 11:46:58 +0000
55@@ -8,7 +8,7 @@
56 void with_restrict(int * __restrict p)
57 {
58 int i;
59- int *q = p - 2;
60+ int *q = p - 1;
61
62 for (i = 0; i < 1000; ++i) {
63 p[i] = q[i];
64@@ -19,7 +19,7 @@
65 void without_restrict(int * p)
66 {
67 int i;
68- int *q = p - 2;
69+ int *q = p - 1;
70
71 for (i = 0; i < 1000; ++i) {
72 p[i] = q[i];
73@@ -38,8 +38,8 @@
74 a[i] = b[i] = i;
75 }
76
77- with_restrict(a + 2);
78- without_restrict(b + 2);
79+ with_restrict(a + 1);
80+ without_restrict(b + 1);
81
82 for (i = 0; i < 1002; ++i) {
83 if (a[i] != b[i])
84
85=== modified file 'gcc/testsuite/gcc.dg/vect/slp-3.c'
86--- old/gcc/testsuite/gcc.dg/vect/slp-3.c 2010-11-22 12:16:52 +0000
87+++ new/gcc/testsuite/gcc.dg/vect/slp-3.c 2011-04-28 11:46:58 +0000
88@@ -4,9 +4,9 @@
89 #include <stdarg.h>
90 #include "tree-vect.h"
91
92-#define N 8
93+#define N 12
94
95-unsigned short in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
96+unsigned short in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};
97
98 int
99 main1 ()
100@@ -101,7 +101,7 @@
101 }
102
103 /* SLP with unrolling by 8. */
104- for (i = 0; i < N/2; i++)
105+ for (i = 0; i < N/4; i++)
106 {
107 out[i*9] = in[i*9];
108 out[i*9 + 1] = in[i*9 + 1];
109@@ -115,7 +115,7 @@
110 }
111
112 /* check results: */
113- for (i = 0; i < N/2; i++)
114+ for (i = 0; i < N/4; i++)
115 {
116 if (out[i*9] != in[i*9]
117 || out[i*9 + 1] != in[i*9 + 1]
118
119=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-5.c'
120--- old/gcc/testsuite/gcc.dg/vect/vect-outer-5.c 2010-11-22 12:16:52 +0000
121+++ new/gcc/testsuite/gcc.dg/vect/vect-outer-5.c 2011-04-28 11:46:58 +0000
122@@ -17,7 +17,7 @@
123 float B[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
124 float C[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
125 float D[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
126- float E[4] = {0,1,2,480};
127+ float E[4] = {0,480,960,1440};
128 float s;
129
130 int i, j;
131@@ -55,7 +55,7 @@
132 s = 0;
133 for (j=0; j<N; j+=4)
134 s += C[j];
135- B[i+3] = B[i] + s;
136+ B[i+1] = B[i] + s;
137 }
138
139 /* check results: */
140
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106741.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106741.patch
deleted file mode 100644
index 6e76c2127..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106741.patch
+++ /dev/null
@@ -1,255 +0,0 @@
12011-04-26 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF:
4
5 2011-04-15 Maxim Kuvyrkov <maxim@codesourcery.com>
6
7 gcc/
8 * combine.c (subst, combine_simlify_rtx): Add new argument, use it
9 to track processing of conditionals. Update all callers.
10 (try_combine, simplify_if_then_else): Update.
11
12 2011-04-25 Maxim Kuvyrkov <maxim@codesourcery.com>
13 Eric Botcazou <ebotcazou@adacore.com>
14
15 gcc/
16 * combine.c (combine_simplify_rtx): Avoid mis-simplifying conditionals
17 for STORE_FLAG_VALUE==-1 case.
18
19=== modified file 'gcc/combine.c'
20Index: gcc-4_6-branch/gcc/combine.c
21===================================================================
22--- gcc-4_6-branch.orig/gcc/combine.c 2012-03-05 00:16:20.000000000 -0800
23+++ gcc-4_6-branch/gcc/combine.c 2012-03-05 16:05:01.212928507 -0800
24@@ -391,8 +391,8 @@
25 static void undo_all (void);
26 static void undo_commit (void);
27 static rtx *find_split_point (rtx *, rtx, bool);
28-static rtx subst (rtx, rtx, rtx, int, int);
29-static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
30+static rtx subst (rtx, rtx, rtx, int, int, int);
31+static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
32 static rtx simplify_if_then_else (rtx);
33 static rtx simplify_set (rtx);
34 static rtx simplify_logical (rtx);
35@@ -3119,12 +3119,12 @@
36 if (i1)
37 {
38 subst_low_luid = DF_INSN_LUID (i1);
39- i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
40+ i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
41 }
42 else
43 {
44 subst_low_luid = DF_INSN_LUID (i2);
45- i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
46+ i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
47 }
48 }
49
50@@ -3136,7 +3136,7 @@
51 self-referential RTL when we will be substituting I1SRC for I1DEST
52 later. Likewise if I0 feeds into I2, either directly or indirectly
53 through I1, and I0DEST is in I0SRC. */
54- newpat = subst (PATTERN (i3), i2dest, i2src, 0,
55+ newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
56 (i1_feeds_i2_n && i1dest_in_i1src)
57 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
58 && i0dest_in_i0src));
59@@ -3180,7 +3180,7 @@
60 copy of I1SRC each time we substitute it, in order to avoid creating
61 self-referential RTL when we will be substituting I0SRC for I0DEST
62 later. */
63- newpat = subst (newpat, i1dest, i1src, 0,
64+ newpat = subst (newpat, i1dest, i1src, 0, 0,
65 i0_feeds_i1_n && i0dest_in_i0src);
66 substed_i1 = 1;
67
68@@ -3214,7 +3214,7 @@
69
70 n_occurrences = 0;
71 subst_low_luid = DF_INSN_LUID (i0);
72- newpat = subst (newpat, i0dest, i0src, 0, 0);
73+ newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
74 substed_i0 = 1;
75 }
76
77@@ -3276,7 +3276,7 @@
78 {
79 rtx t = i1pat;
80 if (i0_feeds_i1_n)
81- t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0);
82+ t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
83
84 XVECEXP (newpat, 0, --total_sets) = t;
85 }
86@@ -3284,10 +3284,10 @@
87 {
88 rtx t = i2pat;
89 if (i1_feeds_i2_n)
90- t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0,
91+ t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
92 i0_feeds_i1_n && i0dest_in_i0src);
93 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
94- t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0);
95+ t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
96
97 XVECEXP (newpat, 0, --total_sets) = t;
98 }
99@@ -4959,11 +4959,13 @@
100
101 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
102
103+ IN_COND is nonzero if we are on top level of the condition.
104+
105 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
106 by copying if `n_occurrences' is nonzero. */
107
108 static rtx
109-subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
110+subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
111 {
112 enum rtx_code code = GET_CODE (x);
113 enum machine_mode op0_mode = VOIDmode;
114@@ -5024,7 +5026,7 @@
115 && GET_CODE (XVECEXP (x, 0, 0)) == SET
116 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
117 {
118- new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
119+ new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
120
121 /* If this substitution failed, this whole thing fails. */
122 if (GET_CODE (new_rtx) == CLOBBER
123@@ -5041,7 +5043,7 @@
124 && GET_CODE (dest) != CC0
125 && GET_CODE (dest) != PC)
126 {
127- new_rtx = subst (dest, from, to, 0, unique_copy);
128+ new_rtx = subst (dest, from, to, 0, 0, unique_copy);
129
130 /* If this substitution failed, this whole thing fails. */
131 if (GET_CODE (new_rtx) == CLOBBER
132@@ -5087,8 +5089,8 @@
133 }
134 else
135 {
136- new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
137- unique_copy);
138+ new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
139+ unique_copy);
140
141 /* If this substitution failed, this whole thing
142 fails. */
143@@ -5165,7 +5167,9 @@
144 && (code == SUBREG || code == STRICT_LOW_PART
145 || code == ZERO_EXTRACT))
146 || code == SET)
147- && i == 0), unique_copy);
148+ && i == 0),
149+ code == IF_THEN_ELSE && i == 0,
150+ unique_copy);
151
152 /* If we found that we will have to reject this combination,
153 indicate that by returning the CLOBBER ourselves, rather than
154@@ -5222,7 +5226,7 @@
155 /* If X is sufficiently simple, don't bother trying to do anything
156 with it. */
157 if (code != CONST_INT && code != REG && code != CLOBBER)
158- x = combine_simplify_rtx (x, op0_mode, in_dest);
159+ x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
160
161 if (GET_CODE (x) == code)
162 break;
163@@ -5242,10 +5246,12 @@
164 expression.
165
166 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
167- if we are inside a SET_DEST. */
168+ if we are inside a SET_DEST. IN_COND is nonzero if we are on the top level
169+ of a condition. */
170
171 static rtx
172-combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
173+combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
174+ int in_cond)
175 {
176 enum rtx_code code = GET_CODE (x);
177 enum machine_mode mode = GET_MODE (x);
178@@ -5300,8 +5306,8 @@
179 false arms to store-flag values. Be careful to use copy_rtx
180 here since true_rtx or false_rtx might share RTL with x as a
181 result of the if_then_else_cond call above. */
182- true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
183- false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
184+ true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
185+ false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
186
187 /* If true_rtx and false_rtx are not general_operands, an if_then_else
188 is unlikely to be simpler. */
189@@ -5645,7 +5651,7 @@
190 {
191 /* Try to simplify the expression further. */
192 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
193- temp = combine_simplify_rtx (tor, VOIDmode, in_dest);
194+ temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
195
196 /* If we could, great. If not, do not go ahead with the IOR
197 replacement, since PLUS appears in many special purpose
198@@ -5738,7 +5744,16 @@
199 ZERO_EXTRACT is indeed appropriate, it will be placed back by
200 the call to make_compound_operation in the SET case. */
201
202- if (STORE_FLAG_VALUE == 1
203+ if (in_cond)
204+ /* Don't apply below optimizations if the caller would
205+ prefer a comparison rather than a value.
206+ E.g., for the condition in an IF_THEN_ELSE most targets need
207+ an explicit comparison. */
208+ {
209+ ;
210+ }
211+
212+ else if (STORE_FLAG_VALUE == 1
213 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
214 && op1 == const0_rtx
215 && mode == GET_MODE (op0)
216@@ -5784,7 +5799,10 @@
217
218 /* If STORE_FLAG_VALUE is -1, we have cases similar to
219 those above. */
220- if (STORE_FLAG_VALUE == -1
221+ if (in_cond)
222+ ;
223+
224+ else if (STORE_FLAG_VALUE == -1
225 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
226 && op1 == const0_rtx
227 && (num_sign_bit_copies (op0, mode)
228@@ -5982,11 +6000,11 @@
229 if (reg_mentioned_p (from, true_rtx))
230 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
231 from, true_val),
232- pc_rtx, pc_rtx, 0, 0);
233+ pc_rtx, pc_rtx, 0, 0, 0);
234 if (reg_mentioned_p (from, false_rtx))
235 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
236 from, false_val),
237- pc_rtx, pc_rtx, 0, 0);
238+ pc_rtx, pc_rtx, 0, 0, 0);
239
240 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
241 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
242@@ -6203,11 +6221,11 @@
243 {
244 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
245 cond_op0, cond_op1),
246- pc_rtx, pc_rtx, 0, 0);
247+ pc_rtx, pc_rtx, 0, 0, 0);
248 temp = simplify_gen_binary (MULT, m, temp,
249 simplify_gen_binary (MULT, m, c1,
250 const_true_rtx));
251- temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
252+ temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
253 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
254
255 if (extend_op != UNKNOWN)
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch
deleted file mode 100644
index 395c08cab..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch
+++ /dev/null
@@ -1,6125 +0,0 @@
12011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/testsuite/
4 From Richard Earnshaw <rearnsha@arm.com>
5
6 PR target/46329
7 * gcc.target/arm/pr46329.c: New test.
8
9 gcc/
10 PR target/46329
11 * config/arm/arm.c (arm_legitimate_constant_p_1): Return false
12 for all Neon struct constants.
13
142011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
15
16 gcc/
17 * targhooks.h (default_legitimate_constant_p); Declare.
18 * targhooks.c (default_legitimate_constant_p): New function.
19
20 Backport from mainline:
21 2011-04-21 Richard Sandiford <richard.sandiford@linaro.org>
22
23 * target.def (legitimate_constant_p): New hook.
24 * doc/tm.texi.in (LEGITIMATE_CONSTANT_P): Replace with...
25 (TARGET_LEGITIMATE_CONSTANT_P): ...this.
26 * doc/tm.texi: Regenerate.
27 * calls.c (precompute_register_parameters): Replace uses of
28 LEGITIMATE_CONSTANT_P with targetm.legitimate_constant_p.
29 (emit_library_call_value_1): Likewise.
30 * expr.c (move_block_to_reg, can_store_by_pieces, emit_move_insn)
31 (compress_float_constant, emit_push_insn, expand_expr_real_1): Likewise.
32 * recog.c (general_operand, immediate_operand): Likewise.
33 * reload.c (find_reloads_toplev, find_reloads_address_part): Likewise.
34 * reload1.c (init_eliminable_invariants): Likewise.
35
36 * config/arm/arm-protos.h (arm_cannot_force_const_mem): Delete.
37 * config/arm/arm.h (ARM_LEGITIMATE_CONSTANT_P): Likewise.
38 (THUMB_LEGITIMATE_CONSTANT_P, LEGITIMATE_CONSTANT_P): Likewise.
39 * config/arm/arm.c (TARGET_LEGITIMATE_CONSTANT_P): Define.
40 (arm_legitimate_constant_p_1, thumb_legitimate_constant_p)
41 (arm_legitimate_constant_p): New functions.
42 (arm_cannot_force_const_mem): Make static.
43
442011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
45
46 gcc/
47 Backport from mainline:
48
49 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
50
51 * hooks.h (hook_bool_mode_uhwi_false): Declare.
52 * hooks.c (hook_bool_mode_uhwi_false): New function.
53 * target.def (array_mode_supported_p): New hook.
54 * doc/tm.texi.in (TARGET_ARRAY_MODE_SUPPORTED_P): Add @hook.
55 * doc/tm.texi: Regenerate.
56 * stor-layout.c (mode_for_array): New function.
57 (layout_type): Use it.
58 * config/arm/arm.c (arm_array_mode_supported_p): New function.
59 (TARGET_ARRAY_MODE_SUPPORTED_P): Define.
60
612011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
62
63 gcc/
64 Backport from mainline:
65
66 2011-04-12 Richard Sandiford <richard.sandiford@linaro.org>
67
68 * config/arm/arm.c (arm_print_operand): Use MEM_SIZE to get the
69 size of a '%A' memory reference.
70 (T_DREG, T_QREG): New neon_builtin_type_bits.
71 (arm_init_neon_builtins): Assert that the load and store operands
72 are neon_struct_operands.
73 (locate_neon_builtin_icode): Provide the neon_builtin_type_bits.
74 (NEON_ARG_MEMORY): New builtin_arg.
75 (neon_dereference_pointer): New function.
76 (arm_expand_neon_args): Add a neon_builtin_type_bits argument.
77 Handle NEON_ARG_MEMORY.
78 (arm_expand_neon_builtin): Update after above interface changes.
79 Use NEON_ARG_MEMORY for loads and stores.
80 * config/arm/predicates.md (neon_struct_operand): New predicate.
81 * config/arm/iterators.md (V_two_elem): Tweak formatting.
82 (V_three_elem): Use BLKmode for accesses that have no associated mode.
83 (V_four_elem): Tweak formatting.
84 * config/arm/neon.md (neon_vld1<mode>, neon_vld1_dup<mode>)
85 (neon_vst1_lane<mode>, neon_vst1<mode>, neon_vld2<mode>)
86 (neon_vld2_lane<mode>, neon_vld2_dup<mode>, neon_vst2<mode>)
87 (neon_vst2_lane<mode>, neon_vld3<mode>, neon_vld3_lane<mode>)
88 (neon_vld3_dup<mode>, neon_vst3<mode>, neon_vst3_lane<mode>)
89 (neon_vld4<mode>, neon_vld4_lane<mode>, neon_vld4_dup<mode>)
90 (neon_vst4<mode>): Replace pointer operand with a memory operand.
91 Use %A in the output template.
92 (neon_vld3qa<mode>, neon_vld3qb<mode>, neon_vst3qa<mode>)
93 (neon_vst3qb<mode>, neon_vld4qa<mode>, neon_vld4qb<mode>)
94 (neon_vst4qa<mode>, neon_vst4qb<mode>): Likewise, but halve
95 the width of the memory access. Remove post-increment.
96 * config/arm/neon-testgen.ml: Allow addresses to have an alignment.
97
98 gcc/testsuite/
99 Backport from mainline:
100
101 2011-04-12 Richard Sandiford <richard.sandiford@linaro.org>
102
103 * gcc.target/arm/neon-vld3-1.c: New test.
104 * gcc.target/arm/neon-vst3-1.c: New test.
105 * gcc.target/arm/neon/v*.c: Regenerate.
106
1072011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
108
109 gcc/
110 Backport from mainline:
111
112 2011-03-30 Richard Sandiford <richard.sandiford@linaro.org>
113 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
114
115 PR target/43590
116 * config/arm/neon.md (neon_vld3qa<mode>, neon_vld4qa<mode>): Remove
117 operand 1 and reshuffle the operands to match.
118 (neon_vld3<mode>, neon_vld4<mode>): Update accordingly.
119
120=== modified file 'gcc/calls.c'
121Index: gcc-4_6-branch/gcc/calls.c
122===================================================================
123--- gcc-4_6-branch.orig/gcc/calls.c 2011-06-24 08:33:49.000000000 -0700
124+++ gcc-4_6-branch/gcc/calls.c 2011-09-16 20:16:00.217564705 -0700
125@@ -686,7 +686,7 @@
126 /* If the value is a non-legitimate constant, force it into a
127 pseudo now. TLS symbols sometimes need a call to resolve. */
128 if (CONSTANT_P (args[i].value)
129- && !LEGITIMATE_CONSTANT_P (args[i].value))
130+ && !targetm.legitimate_constant_p (args[i].mode, args[i].value))
131 args[i].value = force_reg (args[i].mode, args[i].value);
132
133 /* If we are to promote the function arg to a wider mode,
134@@ -3449,7 +3449,8 @@
135
136 /* Make sure it is a reasonable operand for a move or push insn. */
137 if (!REG_P (addr) && !MEM_P (addr)
138- && ! (CONSTANT_P (addr) && LEGITIMATE_CONSTANT_P (addr)))
139+ && !(CONSTANT_P (addr)
140+ && targetm.legitimate_constant_p (Pmode, addr)))
141 addr = force_operand (addr, NULL_RTX);
142
143 argvec[count].value = addr;
144@@ -3490,7 +3491,7 @@
145
146 /* Make sure it is a reasonable operand for a move or push insn. */
147 if (!REG_P (val) && !MEM_P (val)
148- && ! (CONSTANT_P (val) && LEGITIMATE_CONSTANT_P (val)))
149+ && !(CONSTANT_P (val) && targetm.legitimate_constant_p (mode, val)))
150 val = force_operand (val, NULL_RTX);
151
152 if (pass_by_reference (&args_so_far, mode, NULL_TREE, 1))
153Index: gcc-4_6-branch/gcc/config/arm/arm-protos.h
154===================================================================
155--- gcc-4_6-branch.orig/gcc/config/arm/arm-protos.h 2011-06-24 08:33:37.000000000 -0700
156+++ gcc-4_6-branch/gcc/config/arm/arm-protos.h 2011-09-16 20:16:00.217564705 -0700
157@@ -81,7 +81,6 @@
158 extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx,
159 bool);
160 extern bool arm_tls_referenced_p (rtx);
161-extern bool arm_cannot_force_const_mem (rtx);
162
163 extern int cirrus_memory_offset (rtx);
164 extern int arm_coproc_mem_operand (rtx, bool);
165Index: gcc-4_6-branch/gcc/config/arm/arm.c
166===================================================================
167--- gcc-4_6-branch.orig/gcc/config/arm/arm.c 2011-09-16 20:14:34.000000000 -0700
168+++ gcc-4_6-branch/gcc/config/arm/arm.c 2011-09-16 20:16:00.237564275 -0700
169@@ -143,6 +143,8 @@
170 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
171 tree);
172 static bool arm_have_conditional_execution (void);
173+static bool arm_cannot_force_const_mem (rtx);
174+static bool arm_legitimate_constant_p (enum machine_mode, rtx);
175 static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);
176 static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
177 static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
178@@ -241,6 +243,8 @@
179 static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *);
180 static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *);
181 static bool fa726te_sched_adjust_cost (rtx, rtx, rtx, int *);
182+static bool arm_array_mode_supported_p (enum machine_mode,
183+ unsigned HOST_WIDE_INT);
184 static enum machine_mode arm_preferred_simd_mode (enum machine_mode);
185 static bool arm_class_likely_spilled_p (reg_class_t);
186 static bool arm_vector_alignment_reachable (const_tree type, bool is_packed);
187@@ -394,6 +398,8 @@
188 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
189 #undef TARGET_VECTOR_MODE_SUPPORTED_P
190 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
191+#undef TARGET_ARRAY_MODE_SUPPORTED_P
192+#define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p
193 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
194 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
195 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
196@@ -523,6 +529,9 @@
197 #undef TARGET_HAVE_CONDITIONAL_EXECUTION
198 #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution
199
200+#undef TARGET_LEGITIMATE_CONSTANT_P
201+#define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p
202+
203 #undef TARGET_CANNOT_FORCE_CONST_MEM
204 #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
205
206@@ -6539,9 +6548,47 @@
207 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
208 }
209
210+/* Implement TARGET_LEGITIMATE_CONSTANT_P.
211+
212+ On the ARM, allow any integer (invalid ones are removed later by insn
213+ patterns), nice doubles and symbol_refs which refer to the function's
214+ constant pool XXX.
215+
216+ When generating pic allow anything. */
217+
218+static bool
219+arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x)
220+{
221+ /* At present, we have no support for Neon structure constants, so forbid
222+ them here. It might be possible to handle simple cases like 0 and -1
223+ in future. */
224+ if (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))
225+ return false;
226+
227+ return flag_pic || !label_mentioned_p (x);
228+}
229+
230+static bool
231+thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
232+{
233+ return (GET_CODE (x) == CONST_INT
234+ || GET_CODE (x) == CONST_DOUBLE
235+ || CONSTANT_ADDRESS_P (x)
236+ || flag_pic);
237+}
238+
239+static bool
240+arm_legitimate_constant_p (enum machine_mode mode, rtx x)
241+{
242+ return (!arm_cannot_force_const_mem (x)
243+ && (TARGET_32BIT
244+ ? arm_legitimate_constant_p_1 (mode, x)
245+ : thumb_legitimate_constant_p (mode, x)));
246+}
247+
248 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
249
250-bool
251+static bool
252 arm_cannot_force_const_mem (rtx x)
253 {
254 rtx base, offset;
255@@ -16598,7 +16645,7 @@
256 {
257 rtx addr;
258 bool postinc = FALSE;
259- unsigned align, modesize, align_bits;
260+ unsigned align, memsize, align_bits;
261
262 gcc_assert (GET_CODE (x) == MEM);
263 addr = XEXP (x, 0);
264@@ -16613,12 +16660,12 @@
265 instruction (for some alignments) as an aid to the memory subsystem
266 of the target. */
267 align = MEM_ALIGN (x) >> 3;
268- modesize = GET_MODE_SIZE (GET_MODE (x));
269+ memsize = INTVAL (MEM_SIZE (x));
270
271 /* Only certain alignment specifiers are supported by the hardware. */
272- if (modesize == 16 && (align % 32) == 0)
273+ if (memsize == 16 && (align % 32) == 0)
274 align_bits = 256;
275- else if ((modesize == 8 || modesize == 16) && (align % 16) == 0)
276+ else if ((memsize == 8 || memsize == 16) && (align % 16) == 0)
277 align_bits = 128;
278 else if ((align % 8) == 0)
279 align_bits = 64;
280@@ -18278,12 +18325,14 @@
281 T_V2SI = 0x0004,
282 T_V2SF = 0x0008,
283 T_DI = 0x0010,
284+ T_DREG = 0x001F,
285 T_V16QI = 0x0020,
286 T_V8HI = 0x0040,
287 T_V4SI = 0x0080,
288 T_V4SF = 0x0100,
289 T_V2DI = 0x0200,
290 T_TI = 0x0400,
291+ T_QREG = 0x07E0,
292 T_EI = 0x0800,
293 T_OI = 0x1000
294 };
295@@ -18929,10 +18978,9 @@
296 if (is_load && k == 1)
297 {
298 /* Neon load patterns always have the memory operand
299- (a SImode pointer) in the operand 1 position. We
300- want a const pointer to the element type in that
301- position. */
302- gcc_assert (insn_data[icode].operand[k].mode == SImode);
303+ in the operand 1 position. */
304+ gcc_assert (insn_data[icode].operand[k].predicate
305+ == neon_struct_operand);
306
307 switch (1 << j)
308 {
309@@ -18967,10 +19015,9 @@
310 else if (is_store && k == 0)
311 {
312 /* Similarly, Neon store patterns use operand 0 as
313- the memory location to store to (a SImode pointer).
314- Use a pointer to the element type of the store in
315- that position. */
316- gcc_assert (insn_data[icode].operand[k].mode == SImode);
317+ the memory location to store to. */
318+ gcc_assert (insn_data[icode].operand[k].predicate
319+ == neon_struct_operand);
320
321 switch (1 << j)
322 {
323@@ -19290,12 +19337,13 @@
324 }
325
326 static enum insn_code
327-locate_neon_builtin_icode (int fcode, neon_itype *itype)
328+locate_neon_builtin_icode (int fcode, neon_itype *itype,
329+ enum neon_builtin_type_bits *type_bit)
330 {
331 neon_builtin_datum key
332 = { NULL, (neon_itype) 0, 0, { CODE_FOR_nothing }, 0, 0 };
333 neon_builtin_datum *found;
334- int idx;
335+ int idx, type, ntypes;
336
337 key.base_fcode = fcode;
338 found = (neon_builtin_datum *)
339@@ -19308,20 +19356,84 @@
340 if (itype)
341 *itype = found->itype;
342
343+ if (type_bit)
344+ {
345+ ntypes = 0;
346+ for (type = 0; type < T_MAX; type++)
347+ if (found->bits & (1 << type))
348+ {
349+ if (ntypes == idx)
350+ break;
351+ ntypes++;
352+ }
353+ gcc_assert (type < T_MAX);
354+ *type_bit = (enum neon_builtin_type_bits) (1 << type);
355+ }
356 return found->codes[idx];
357 }
358
359 typedef enum {
360 NEON_ARG_COPY_TO_REG,
361 NEON_ARG_CONSTANT,
362+ NEON_ARG_MEMORY,
363 NEON_ARG_STOP
364 } builtin_arg;
365
366 #define NEON_MAX_BUILTIN_ARGS 5
367
368+/* EXP is a pointer argument to a Neon load or store intrinsic. Derive
369+ and return an expression for the accessed memory.
370+
371+ The intrinsic function operates on a block of registers that has
372+ mode REG_MODE. This block contains vectors of type TYPE_BIT.
373+ The function references the memory at EXP in mode MEM_MODE;
374+ this mode may be BLKmode if no more suitable mode is available. */
375+
376+static tree
377+neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
378+ enum machine_mode reg_mode,
379+ enum neon_builtin_type_bits type_bit)
380+{
381+ HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
382+ tree elem_type, upper_bound, array_type;
383+
384+ /* Work out the size of the register block in bytes. */
385+ reg_size = GET_MODE_SIZE (reg_mode);
386+
387+ /* Work out the size of each vector in bytes. */
388+ gcc_assert (type_bit & (T_DREG | T_QREG));
389+ vector_size = (type_bit & T_QREG ? 16 : 8);
390+
391+ /* Work out how many vectors there are. */
392+ gcc_assert (reg_size % vector_size == 0);
393+ nvectors = reg_size / vector_size;
394+
395+ /* Work out how many elements are being loaded or stored.
396+ MEM_MODE == REG_MODE implies a one-to-one mapping between register
397+ and memory elements; anything else implies a lane load or store. */
398+ if (mem_mode == reg_mode)
399+ nelems = vector_size * nvectors;
400+ else
401+ nelems = nvectors;
402+
403+ /* Work out the type of each element. */
404+ gcc_assert (POINTER_TYPE_P (TREE_TYPE (exp)));
405+ elem_type = TREE_TYPE (TREE_TYPE (exp));
406+
407+ /* Create a type that describes the full access. */
408+ upper_bound = build_int_cst (size_type_node, nelems - 1);
409+ array_type = build_array_type (elem_type, build_index_type (upper_bound));
410+
411+ /* Dereference EXP using that type. */
412+ exp = convert (build_pointer_type (array_type), exp);
413+ return fold_build2 (MEM_REF, array_type, exp,
414+ build_int_cst (TREE_TYPE (exp), 0));
415+}
416+
417 /* Expand a Neon builtin. */
418 static rtx
419 arm_expand_neon_args (rtx target, int icode, int have_retval,
420+ enum neon_builtin_type_bits type_bit,
421 tree exp, ...)
422 {
423 va_list ap;
424@@ -19330,7 +19442,9 @@
425 rtx op[NEON_MAX_BUILTIN_ARGS];
426 enum machine_mode tmode = insn_data[icode].operand[0].mode;
427 enum machine_mode mode[NEON_MAX_BUILTIN_ARGS];
428+ enum machine_mode other_mode;
429 int argc = 0;
430+ int opno;
431
432 if (have_retval
433 && (!target
434@@ -19348,26 +19462,46 @@
435 break;
436 else
437 {
438+ opno = argc + have_retval;
439+ mode[argc] = insn_data[icode].operand[opno].mode;
440 arg[argc] = CALL_EXPR_ARG (exp, argc);
441+ if (thisarg == NEON_ARG_MEMORY)
442+ {
443+ other_mode = insn_data[icode].operand[1 - opno].mode;
444+ arg[argc] = neon_dereference_pointer (arg[argc], mode[argc],
445+ other_mode, type_bit);
446+ }
447 op[argc] = expand_normal (arg[argc]);
448- mode[argc] = insn_data[icode].operand[argc + have_retval].mode;
449
450 switch (thisarg)
451 {
452 case NEON_ARG_COPY_TO_REG:
453 /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
454- if (!(*insn_data[icode].operand[argc + have_retval].predicate)
455+ if (!(*insn_data[icode].operand[opno].predicate)
456 (op[argc], mode[argc]))
457 op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
458 break;
459
460 case NEON_ARG_CONSTANT:
461 /* FIXME: This error message is somewhat unhelpful. */
462- if (!(*insn_data[icode].operand[argc + have_retval].predicate)
463+ if (!(*insn_data[icode].operand[opno].predicate)
464 (op[argc], mode[argc]))
465 error ("argument must be a constant");
466 break;
467
468+ case NEON_ARG_MEMORY:
469+ gcc_assert (MEM_P (op[argc]));
470+ PUT_MODE (op[argc], mode[argc]);
471+ /* ??? arm_neon.h uses the same built-in functions for signed
472+ and unsigned accesses, casting where necessary. This isn't
473+ alias safe. */
474+ set_mem_alias_set (op[argc], 0);
475+ if (!(*insn_data[icode].operand[opno].predicate)
476+ (op[argc], mode[argc]))
477+ op[argc] = (replace_equiv_address
478+ (op[argc], force_reg (Pmode, XEXP (op[argc], 0))));
479+ break;
480+
481 case NEON_ARG_STOP:
482 gcc_unreachable ();
483 }
484@@ -19446,14 +19580,15 @@
485 arm_expand_neon_builtin (int fcode, tree exp, rtx target)
486 {
487 neon_itype itype;
488- enum insn_code icode = locate_neon_builtin_icode (fcode, &itype);
489+ enum neon_builtin_type_bits type_bit;
490+ enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, &type_bit);
491
492 switch (itype)
493 {
494 case NEON_UNOP:
495 case NEON_CONVERT:
496 case NEON_DUPLANE:
497- return arm_expand_neon_args (target, icode, 1, exp,
498+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
499 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
500
501 case NEON_BINOP:
502@@ -19463,90 +19598,90 @@
503 case NEON_SCALARMULH:
504 case NEON_SHIFTINSERT:
505 case NEON_LOGICBINOP:
506- return arm_expand_neon_args (target, icode, 1, exp,
507+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
508 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
509 NEON_ARG_STOP);
510
511 case NEON_TERNOP:
512- return arm_expand_neon_args (target, icode, 1, exp,
513+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
514 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
515 NEON_ARG_CONSTANT, NEON_ARG_STOP);
516
517 case NEON_GETLANE:
518 case NEON_FIXCONV:
519 case NEON_SHIFTIMM:
520- return arm_expand_neon_args (target, icode, 1, exp,
521+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
522 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
523 NEON_ARG_STOP);
524
525 case NEON_CREATE:
526- return arm_expand_neon_args (target, icode, 1, exp,
527+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
528 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
529
530 case NEON_DUP:
531 case NEON_SPLIT:
532 case NEON_REINTERP:
533- return arm_expand_neon_args (target, icode, 1, exp,
534+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
535 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
536
537 case NEON_COMBINE:
538 case NEON_VTBL:
539- return arm_expand_neon_args (target, icode, 1, exp,
540+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
541 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
542
543 case NEON_RESULTPAIR:
544- return arm_expand_neon_args (target, icode, 0, exp,
545+ return arm_expand_neon_args (target, icode, 0, type_bit, exp,
546 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
547 NEON_ARG_STOP);
548
549 case NEON_LANEMUL:
550 case NEON_LANEMULL:
551 case NEON_LANEMULH:
552- return arm_expand_neon_args (target, icode, 1, exp,
553+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
554 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
555 NEON_ARG_CONSTANT, NEON_ARG_STOP);
556
557 case NEON_LANEMAC:
558- return arm_expand_neon_args (target, icode, 1, exp,
559+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
560 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
561 NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
562
563 case NEON_SHIFTACC:
564- return arm_expand_neon_args (target, icode, 1, exp,
565+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
566 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
567 NEON_ARG_CONSTANT, NEON_ARG_STOP);
568
569 case NEON_SCALARMAC:
570- return arm_expand_neon_args (target, icode, 1, exp,
571+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
572 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
573 NEON_ARG_CONSTANT, NEON_ARG_STOP);
574
575 case NEON_SELECT:
576 case NEON_VTBX:
577- return arm_expand_neon_args (target, icode, 1, exp,
578+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
579 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
580 NEON_ARG_STOP);
581
582 case NEON_LOAD1:
583 case NEON_LOADSTRUCT:
584- return arm_expand_neon_args (target, icode, 1, exp,
585- NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
586+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
587+ NEON_ARG_MEMORY, NEON_ARG_STOP);
588
589 case NEON_LOAD1LANE:
590 case NEON_LOADSTRUCTLANE:
591- return arm_expand_neon_args (target, icode, 1, exp,
592- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
593+ return arm_expand_neon_args (target, icode, 1, type_bit, exp,
594+ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
595 NEON_ARG_STOP);
596
597 case NEON_STORE1:
598 case NEON_STORESTRUCT:
599- return arm_expand_neon_args (target, icode, 0, exp,
600- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
601+ return arm_expand_neon_args (target, icode, 0, type_bit, exp,
602+ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
603
604 case NEON_STORE1LANE:
605 case NEON_STORESTRUCTLANE:
606- return arm_expand_neon_args (target, icode, 0, exp,
607- NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
608+ return arm_expand_neon_args (target, icode, 0, type_bit, exp,
609+ NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
610 NEON_ARG_STOP);
611 }
612
613@@ -22265,6 +22400,20 @@
614 return true;
615
616 return false;
617+}
618+
619+/* Implements target hook array_mode_supported_p. */
620+
621+static bool
622+arm_array_mode_supported_p (enum machine_mode mode,
623+ unsigned HOST_WIDE_INT nelems)
624+{
625+ if (TARGET_NEON
626+ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
627+ && (nelems >= 2 && nelems <= 4))
628+ return true;
629+
630+ return false;
631 }
632
633 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
634Index: gcc-4_6-branch/gcc/config/arm/arm.h
635===================================================================
636--- gcc-4_6-branch.orig/gcc/config/arm/arm.h 2011-09-16 20:14:33.000000000 -0700
637+++ gcc-4_6-branch/gcc/config/arm/arm.h 2011-09-16 20:16:00.237564275 -0700
638@@ -1777,27 +1777,6 @@
639 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
640 #endif
641
642-/* Nonzero if the constant value X is a legitimate general operand.
643- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
644-
645- On the ARM, allow any integer (invalid ones are removed later by insn
646- patterns), nice doubles and symbol_refs which refer to the function's
647- constant pool XXX.
648-
649- When generating pic allow anything. */
650-#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
651-
652-#define THUMB_LEGITIMATE_CONSTANT_P(X) \
653- ( GET_CODE (X) == CONST_INT \
654- || GET_CODE (X) == CONST_DOUBLE \
655- || CONSTANT_ADDRESS_P (X) \
656- || flag_pic)
657-
658-#define LEGITIMATE_CONSTANT_P(X) \
659- (!arm_cannot_force_const_mem (X) \
660- && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
661- : THUMB_LEGITIMATE_CONSTANT_P (X)))
662-
663 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
664 #define SUBTARGET_NAME_ENCODING_LENGTHS
665 #endif
666Index: gcc-4_6-branch/gcc/config/arm/iterators.md
667===================================================================
668--- gcc-4_6-branch.orig/gcc/config/arm/iterators.md 2011-06-24 08:33:37.000000000 -0700
669+++ gcc-4_6-branch/gcc/config/arm/iterators.md 2011-09-16 20:16:00.237564275 -0700
670@@ -194,24 +194,22 @@
671
672 ;; Mode of pair of elements for each vector mode, to define transfer
673 ;; size for structure lane/dup loads and stores.
674-(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
675- (V4HI "SI") (V8HI "SI")
676+(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
677+ (V4HI "SI") (V8HI "SI")
678 (V2SI "V2SI") (V4SI "V2SI")
679 (V2SF "V2SF") (V4SF "V2SF")
680 (DI "V2DI") (V2DI "V2DI")])
681
682 ;; Similar, for three elements.
683-;; ??? Should we define extra modes so that sizes of all three-element
684-;; accesses can be accurately represented?
685-(define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI")
686- (V4HI "V4HI") (V8HI "V4HI")
687- (V2SI "V4SI") (V4SI "V4SI")
688- (V2SF "V4SF") (V4SF "V4SF")
689- (DI "EI") (V2DI "EI")])
690+(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
691+ (V4HI "BLK") (V8HI "BLK")
692+ (V2SI "BLK") (V4SI "BLK")
693+ (V2SF "BLK") (V4SF "BLK")
694+ (DI "EI") (V2DI "EI")])
695
696 ;; Similar, for four elements.
697 (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI")
698- (V4HI "V4HI") (V8HI "V4HI")
699+ (V4HI "V4HI") (V8HI "V4HI")
700 (V2SI "V4SI") (V4SI "V4SI")
701 (V2SF "V4SF") (V4SF "V4SF")
702 (DI "OI") (V2DI "OI")])
703Index: gcc-4_6-branch/gcc/config/arm/neon-testgen.ml
704===================================================================
705--- gcc-4_6-branch.orig/gcc/config/arm/neon-testgen.ml 2011-06-24 08:33:37.000000000 -0700
706+++ gcc-4_6-branch/gcc/config/arm/neon-testgen.ml 2011-09-16 20:16:00.237564275 -0700
707@@ -177,7 +177,7 @@
708 let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in
709 "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}"
710 | (PtrTo elt | CstPtrTo elt) ->
711- "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\\\\\]"
712+ "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]"
713 | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
714 | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
715 | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"
716Index: gcc-4_6-branch/gcc/config/arm/neon.md
717===================================================================
718--- gcc-4_6-branch.orig/gcc/config/arm/neon.md 2011-07-19 21:50:44.000000000 -0700
719+++ gcc-4_6-branch/gcc/config/arm/neon.md 2011-09-16 20:16:00.247564269 -0700
720@@ -4250,16 +4250,16 @@
721
722 (define_insn "neon_vld1<mode>"
723 [(set (match_operand:VDQX 0 "s_register_operand" "=w")
724- (unspec:VDQX [(mem:VDQX (match_operand:SI 1 "s_register_operand" "r"))]
725+ (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")]
726 UNSPEC_VLD1))]
727 "TARGET_NEON"
728- "vld1.<V_sz_elem>\t%h0, [%1]"
729+ "vld1.<V_sz_elem>\t%h0, %A1"
730 [(set_attr "neon_type" "neon_vld1_1_2_regs")]
731 )
732
733 (define_insn "neon_vld1_lane<mode>"
734 [(set (match_operand:VDX 0 "s_register_operand" "=w")
735- (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
736+ (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
737 (match_operand:VDX 2 "s_register_operand" "0")
738 (match_operand:SI 3 "immediate_operand" "i")]
739 UNSPEC_VLD1_LANE))]
740@@ -4270,9 +4270,9 @@
741 if (lane < 0 || lane >= max)
742 error ("lane out of range");
743 if (max == 1)
744- return "vld1.<V_sz_elem>\t%P0, [%1]";
745+ return "vld1.<V_sz_elem>\t%P0, %A1";
746 else
747- return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
748+ return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
749 }
750 [(set (attr "neon_type")
751 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
752@@ -4282,7 +4282,7 @@
753
754 (define_insn "neon_vld1_lane<mode>"
755 [(set (match_operand:VQX 0 "s_register_operand" "=w")
756- (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))
757+ (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")
758 (match_operand:VQX 2 "s_register_operand" "0")
759 (match_operand:SI 3 "immediate_operand" "i")]
760 UNSPEC_VLD1_LANE))]
761@@ -4301,9 +4301,9 @@
762 }
763 operands[0] = gen_rtx_REG (<V_HALF>mode, regno);
764 if (max == 2)
765- return "vld1.<V_sz_elem>\t%P0, [%1]";
766+ return "vld1.<V_sz_elem>\t%P0, %A1";
767 else
768- return "vld1.<V_sz_elem>\t{%P0[%c3]}, [%1]";
769+ return "vld1.<V_sz_elem>\t{%P0[%c3]}, %A1";
770 }
771 [(set (attr "neon_type")
772 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
773@@ -4313,14 +4313,14 @@
774
775 (define_insn "neon_vld1_dup<mode>"
776 [(set (match_operand:VDX 0 "s_register_operand" "=w")
777- (unspec:VDX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
778+ (unspec:VDX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
779 UNSPEC_VLD1_DUP))]
780 "TARGET_NEON"
781 {
782 if (GET_MODE_NUNITS (<MODE>mode) > 1)
783- return "vld1.<V_sz_elem>\t{%P0[]}, [%1]";
784+ return "vld1.<V_sz_elem>\t{%P0[]}, %A1";
785 else
786- return "vld1.<V_sz_elem>\t%h0, [%1]";
787+ return "vld1.<V_sz_elem>\t%h0, %A1";
788 }
789 [(set (attr "neon_type")
790 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
791@@ -4330,14 +4330,14 @@
792
793 (define_insn "neon_vld1_dup<mode>"
794 [(set (match_operand:VQX 0 "s_register_operand" "=w")
795- (unspec:VQX [(mem:<V_elem> (match_operand:SI 1 "s_register_operand" "r"))]
796+ (unspec:VQX [(match_operand:<V_elem> 1 "neon_struct_operand" "Um")]
797 UNSPEC_VLD1_DUP))]
798 "TARGET_NEON"
799 {
800 if (GET_MODE_NUNITS (<MODE>mode) > 2)
801- return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
802+ return "vld1.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
803 else
804- return "vld1.<V_sz_elem>\t%h0, [%1]";
805+ return "vld1.<V_sz_elem>\t%h0, %A1";
806 }
807 [(set (attr "neon_type")
808 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
809@@ -4346,15 +4346,15 @@
810 )
811
812 (define_insn "neon_vst1<mode>"
813- [(set (mem:VDQX (match_operand:SI 0 "s_register_operand" "r"))
814+ [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
815 (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
816 UNSPEC_VST1))]
817 "TARGET_NEON"
818- "vst1.<V_sz_elem>\t%h1, [%0]"
819+ "vst1.<V_sz_elem>\t%h1, %A0"
820 [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
821
822 (define_insn "neon_vst1_lane<mode>"
823- [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
824+ [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
825 (vec_select:<V_elem>
826 (match_operand:VDX 1 "s_register_operand" "w")
827 (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
828@@ -4365,9 +4365,9 @@
829 if (lane < 0 || lane >= max)
830 error ("lane out of range");
831 if (max == 1)
832- return "vst1.<V_sz_elem>\t{%P1}, [%0]";
833+ return "vst1.<V_sz_elem>\t{%P1}, %A0";
834 else
835- return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
836+ return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
837 }
838 [(set (attr "neon_type")
839 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1))
840@@ -4375,7 +4375,7 @@
841 (const_string "neon_vst1_vst2_lane")))])
842
843 (define_insn "neon_vst1_lane<mode>"
844- [(set (mem:<V_elem> (match_operand:SI 0 "s_register_operand" "r"))
845+ [(set (match_operand:<V_elem> 0 "neon_struct_operand" "=Um")
846 (vec_select:<V_elem>
847 (match_operand:VQX 1 "s_register_operand" "w")
848 (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
849@@ -4394,24 +4394,24 @@
850 }
851 operands[1] = gen_rtx_REG (<V_HALF>mode, regno);
852 if (max == 2)
853- return "vst1.<V_sz_elem>\t{%P1}, [%0]";
854+ return "vst1.<V_sz_elem>\t{%P1}, %A0";
855 else
856- return "vst1.<V_sz_elem>\t{%P1[%c2]}, [%0]";
857+ return "vst1.<V_sz_elem>\t{%P1[%c2]}, %A0";
858 }
859 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
860 )
861
862 (define_insn "neon_vld2<mode>"
863 [(set (match_operand:TI 0 "s_register_operand" "=w")
864- (unspec:TI [(mem:TI (match_operand:SI 1 "s_register_operand" "r"))
865+ (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um")
866 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
867 UNSPEC_VLD2))]
868 "TARGET_NEON"
869 {
870 if (<V_sz_elem> == 64)
871- return "vld1.64\t%h0, [%1]";
872+ return "vld1.64\t%h0, %A1";
873 else
874- return "vld2.<V_sz_elem>\t%h0, [%1]";
875+ return "vld2.<V_sz_elem>\t%h0, %A1";
876 }
877 [(set (attr "neon_type")
878 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
879@@ -4421,16 +4421,16 @@
880
881 (define_insn "neon_vld2<mode>"
882 [(set (match_operand:OI 0 "s_register_operand" "=w")
883- (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
884+ (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
885 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
886 UNSPEC_VLD2))]
887 "TARGET_NEON"
888- "vld2.<V_sz_elem>\t%h0, [%1]"
889+ "vld2.<V_sz_elem>\t%h0, %A1"
890 [(set_attr "neon_type" "neon_vld2_2_regs_vld1_vld2_all_lanes")])
891
892 (define_insn "neon_vld2_lane<mode>"
893 [(set (match_operand:TI 0 "s_register_operand" "=w")
894- (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
895+ (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
896 (match_operand:TI 2 "s_register_operand" "0")
897 (match_operand:SI 3 "immediate_operand" "i")
898 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
899@@ -4447,7 +4447,7 @@
900 ops[1] = gen_rtx_REG (DImode, regno + 2);
901 ops[2] = operands[1];
902 ops[3] = operands[3];
903- output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
904+ output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
905 return "";
906 }
907 [(set_attr "neon_type" "neon_vld1_vld2_lane")]
908@@ -4455,7 +4455,7 @@
909
910 (define_insn "neon_vld2_lane<mode>"
911 [(set (match_operand:OI 0 "s_register_operand" "=w")
912- (unspec:OI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
913+ (unspec:OI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
914 (match_operand:OI 2 "s_register_operand" "0")
915 (match_operand:SI 3 "immediate_operand" "i")
916 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
917@@ -4477,7 +4477,7 @@
918 ops[1] = gen_rtx_REG (DImode, regno + 4);
919 ops[2] = operands[1];
920 ops[3] = GEN_INT (lane);
921- output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, [%2]", ops);
922+ output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
923 return "";
924 }
925 [(set_attr "neon_type" "neon_vld1_vld2_lane")]
926@@ -4485,15 +4485,15 @@
927
928 (define_insn "neon_vld2_dup<mode>"
929 [(set (match_operand:TI 0 "s_register_operand" "=w")
930- (unspec:TI [(mem:<V_two_elem> (match_operand:SI 1 "s_register_operand" "r"))
931+ (unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
932 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
933 UNSPEC_VLD2_DUP))]
934 "TARGET_NEON"
935 {
936 if (GET_MODE_NUNITS (<MODE>mode) > 1)
937- return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, [%1]";
938+ return "vld2.<V_sz_elem>\t{%e0[], %f0[]}, %A1";
939 else
940- return "vld1.<V_sz_elem>\t%h0, [%1]";
941+ return "vld1.<V_sz_elem>\t%h0, %A1";
942 }
943 [(set (attr "neon_type")
944 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
945@@ -4502,16 +4502,16 @@
946 )
947
948 (define_insn "neon_vst2<mode>"
949- [(set (mem:TI (match_operand:SI 0 "s_register_operand" "r"))
950+ [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
951 (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
952 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
953 UNSPEC_VST2))]
954 "TARGET_NEON"
955 {
956 if (<V_sz_elem> == 64)
957- return "vst1.64\t%h1, [%0]";
958+ return "vst1.64\t%h1, %A0";
959 else
960- return "vst2.<V_sz_elem>\t%h1, [%0]";
961+ return "vst2.<V_sz_elem>\t%h1, %A0";
962 }
963 [(set (attr "neon_type")
964 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
965@@ -4520,17 +4520,17 @@
966 )
967
968 (define_insn "neon_vst2<mode>"
969- [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
970+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
971 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
972 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
973 UNSPEC_VST2))]
974 "TARGET_NEON"
975- "vst2.<V_sz_elem>\t%h1, [%0]"
976+ "vst2.<V_sz_elem>\t%h1, %A0"
977 [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")]
978 )
979
980 (define_insn "neon_vst2_lane<mode>"
981- [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
982+ [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
983 (unspec:<V_two_elem>
984 [(match_operand:TI 1 "s_register_operand" "w")
985 (match_operand:SI 2 "immediate_operand" "i")
986@@ -4548,14 +4548,14 @@
987 ops[1] = gen_rtx_REG (DImode, regno);
988 ops[2] = gen_rtx_REG (DImode, regno + 2);
989 ops[3] = operands[2];
990- output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
991+ output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
992 return "";
993 }
994 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
995 )
996
997 (define_insn "neon_vst2_lane<mode>"
998- [(set (mem:<V_two_elem> (match_operand:SI 0 "s_register_operand" "r"))
999+ [(set (match_operand:<V_two_elem> 0 "neon_struct_operand" "=Um")
1000 (unspec:<V_two_elem>
1001 [(match_operand:OI 1 "s_register_operand" "w")
1002 (match_operand:SI 2 "immediate_operand" "i")
1003@@ -4578,7 +4578,7 @@
1004 ops[1] = gen_rtx_REG (DImode, regno);
1005 ops[2] = gen_rtx_REG (DImode, regno + 4);
1006 ops[3] = GEN_INT (lane);
1007- output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, [%0]", ops);
1008+ output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
1009 return "";
1010 }
1011 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
1012@@ -4586,15 +4586,15 @@
1013
1014 (define_insn "neon_vld3<mode>"
1015 [(set (match_operand:EI 0 "s_register_operand" "=w")
1016- (unspec:EI [(mem:EI (match_operand:SI 1 "s_register_operand" "r"))
1017+ (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um")
1018 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1019 UNSPEC_VLD3))]
1020 "TARGET_NEON"
1021 {
1022 if (<V_sz_elem> == 64)
1023- return "vld1.64\t%h0, [%1]";
1024+ return "vld1.64\t%h0, %A1";
1025 else
1026- return "vld3.<V_sz_elem>\t%h0, [%1]";
1027+ return "vld3.<V_sz_elem>\t%h0, %A1";
1028 }
1029 [(set (attr "neon_type")
1030 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
1031@@ -4603,27 +4603,25 @@
1032 )
1033
1034 (define_expand "neon_vld3<mode>"
1035- [(match_operand:CI 0 "s_register_operand" "=w")
1036- (match_operand:SI 1 "s_register_operand" "+r")
1037+ [(match_operand:CI 0 "s_register_operand")
1038+ (match_operand:CI 1 "neon_struct_operand")
1039 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1040 "TARGET_NEON"
1041 {
1042- emit_insn (gen_neon_vld3qa<mode> (operands[0], operands[0],
1043- operands[1], operands[1]));
1044- emit_insn (gen_neon_vld3qb<mode> (operands[0], operands[0],
1045- operands[1], operands[1]));
1046+ rtx mem;
1047+
1048+ mem = adjust_address (operands[1], EImode, 0);
1049+ emit_insn (gen_neon_vld3qa<mode> (operands[0], mem));
1050+ mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
1051+ emit_insn (gen_neon_vld3qb<mode> (operands[0], mem, operands[0]));
1052 DONE;
1053 })
1054
1055 (define_insn "neon_vld3qa<mode>"
1056 [(set (match_operand:CI 0 "s_register_operand" "=w")
1057- (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
1058- (match_operand:CI 1 "s_register_operand" "0")
1059+ (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
1060 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1061- UNSPEC_VLD3A))
1062- (set (match_operand:SI 2 "s_register_operand" "=r")
1063- (plus:SI (match_dup 3)
1064- (const_int 24)))]
1065+ UNSPEC_VLD3A))]
1066 "TARGET_NEON"
1067 {
1068 int regno = REGNO (operands[0]);
1069@@ -4631,8 +4629,8 @@
1070 ops[0] = gen_rtx_REG (DImode, regno);
1071 ops[1] = gen_rtx_REG (DImode, regno + 4);
1072 ops[2] = gen_rtx_REG (DImode, regno + 8);
1073- ops[3] = operands[2];
1074- output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
1075+ ops[3] = operands[1];
1076+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
1077 return "";
1078 }
1079 [(set_attr "neon_type" "neon_vld3_vld4")]
1080@@ -4640,13 +4638,10 @@
1081
1082 (define_insn "neon_vld3qb<mode>"
1083 [(set (match_operand:CI 0 "s_register_operand" "=w")
1084- (unspec:CI [(mem:CI (match_operand:SI 3 "s_register_operand" "2"))
1085- (match_operand:CI 1 "s_register_operand" "0")
1086+ (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
1087+ (match_operand:CI 2 "s_register_operand" "0")
1088 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1089- UNSPEC_VLD3B))
1090- (set (match_operand:SI 2 "s_register_operand" "=r")
1091- (plus:SI (match_dup 3)
1092- (const_int 24)))]
1093+ UNSPEC_VLD3B))]
1094 "TARGET_NEON"
1095 {
1096 int regno = REGNO (operands[0]);
1097@@ -4654,8 +4649,8 @@
1098 ops[0] = gen_rtx_REG (DImode, regno + 2);
1099 ops[1] = gen_rtx_REG (DImode, regno + 6);
1100 ops[2] = gen_rtx_REG (DImode, regno + 10);
1101- ops[3] = operands[2];
1102- output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, [%3]!", ops);
1103+ ops[3] = operands[1];
1104+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0, %P1, %P2}, %A3", ops);
1105 return "";
1106 }
1107 [(set_attr "neon_type" "neon_vld3_vld4")]
1108@@ -4663,7 +4658,7 @@
1109
1110 (define_insn "neon_vld3_lane<mode>"
1111 [(set (match_operand:EI 0 "s_register_operand" "=w")
1112- (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
1113+ (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
1114 (match_operand:EI 2 "s_register_operand" "0")
1115 (match_operand:SI 3 "immediate_operand" "i")
1116 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1117@@ -4681,7 +4676,7 @@
1118 ops[2] = gen_rtx_REG (DImode, regno + 4);
1119 ops[3] = operands[1];
1120 ops[4] = operands[3];
1121- output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
1122+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
1123 ops);
1124 return "";
1125 }
1126@@ -4690,7 +4685,7 @@
1127
1128 (define_insn "neon_vld3_lane<mode>"
1129 [(set (match_operand:CI 0 "s_register_operand" "=w")
1130- (unspec:CI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
1131+ (unspec:CI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
1132 (match_operand:CI 2 "s_register_operand" "0")
1133 (match_operand:SI 3 "immediate_operand" "i")
1134 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1135@@ -4713,7 +4708,7 @@
1136 ops[2] = gen_rtx_REG (DImode, regno + 8);
1137 ops[3] = operands[1];
1138 ops[4] = GEN_INT (lane);
1139- output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, [%3]",
1140+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3",
1141 ops);
1142 return "";
1143 }
1144@@ -4722,7 +4717,7 @@
1145
1146 (define_insn "neon_vld3_dup<mode>"
1147 [(set (match_operand:EI 0 "s_register_operand" "=w")
1148- (unspec:EI [(mem:<V_three_elem> (match_operand:SI 1 "s_register_operand" "r"))
1149+ (unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
1150 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1151 UNSPEC_VLD3_DUP))]
1152 "TARGET_NEON"
1153@@ -4735,11 +4730,11 @@
1154 ops[1] = gen_rtx_REG (DImode, regno + 2);
1155 ops[2] = gen_rtx_REG (DImode, regno + 4);
1156 ops[3] = operands[1];
1157- output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, [%3]", ops);
1158+ output_asm_insn ("vld3.<V_sz_elem>\t{%P0[], %P1[], %P2[]}, %A3", ops);
1159 return "";
1160 }
1161 else
1162- return "vld1.<V_sz_elem>\t%h0, [%1]";
1163+ return "vld1.<V_sz_elem>\t%h0, %A1";
1164 }
1165 [(set (attr "neon_type")
1166 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
1167@@ -4747,16 +4742,16 @@
1168 (const_string "neon_vld1_1_2_regs")))])
1169
1170 (define_insn "neon_vst3<mode>"
1171- [(set (mem:EI (match_operand:SI 0 "s_register_operand" "r"))
1172+ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
1173 (unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
1174 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1175 UNSPEC_VST3))]
1176 "TARGET_NEON"
1177 {
1178 if (<V_sz_elem> == 64)
1179- return "vst1.64\t%h1, [%0]";
1180+ return "vst1.64\t%h1, %A0";
1181 else
1182- return "vst3.<V_sz_elem>\t%h1, [%0]";
1183+ return "vst3.<V_sz_elem>\t%h1, %A0";
1184 }
1185 [(set (attr "neon_type")
1186 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
1187@@ -4764,62 +4759,60 @@
1188 (const_string "neon_vst2_4_regs_vst3_vst4")))])
1189
1190 (define_expand "neon_vst3<mode>"
1191- [(match_operand:SI 0 "s_register_operand" "+r")
1192- (match_operand:CI 1 "s_register_operand" "w")
1193+ [(match_operand:CI 0 "neon_struct_operand")
1194+ (match_operand:CI 1 "s_register_operand")
1195 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1196 "TARGET_NEON"
1197 {
1198- emit_insn (gen_neon_vst3qa<mode> (operands[0], operands[0], operands[1]));
1199- emit_insn (gen_neon_vst3qb<mode> (operands[0], operands[0], operands[1]));
1200+ rtx mem;
1201+
1202+ mem = adjust_address (operands[0], EImode, 0);
1203+ emit_insn (gen_neon_vst3qa<mode> (mem, operands[1]));
1204+ mem = adjust_address (mem, EImode, GET_MODE_SIZE (EImode));
1205+ emit_insn (gen_neon_vst3qb<mode> (mem, operands[1]));
1206 DONE;
1207 })
1208
1209 (define_insn "neon_vst3qa<mode>"
1210- [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
1211- (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
1212+ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
1213+ (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
1214 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1215- UNSPEC_VST3A))
1216- (set (match_operand:SI 0 "s_register_operand" "=r")
1217- (plus:SI (match_dup 1)
1218- (const_int 24)))]
1219+ UNSPEC_VST3A))]
1220 "TARGET_NEON"
1221 {
1222- int regno = REGNO (operands[2]);
1223+ int regno = REGNO (operands[1]);
1224 rtx ops[4];
1225 ops[0] = operands[0];
1226 ops[1] = gen_rtx_REG (DImode, regno);
1227 ops[2] = gen_rtx_REG (DImode, regno + 4);
1228 ops[3] = gen_rtx_REG (DImode, regno + 8);
1229- output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
1230+ output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
1231 return "";
1232 }
1233 [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
1234 )
1235
1236 (define_insn "neon_vst3qb<mode>"
1237- [(set (mem:EI (match_operand:SI 1 "s_register_operand" "0"))
1238- (unspec:EI [(match_operand:CI 2 "s_register_operand" "w")
1239+ [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
1240+ (unspec:EI [(match_operand:CI 1 "s_register_operand" "w")
1241 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1242- UNSPEC_VST3B))
1243- (set (match_operand:SI 0 "s_register_operand" "=r")
1244- (plus:SI (match_dup 1)
1245- (const_int 24)))]
1246+ UNSPEC_VST3B))]
1247 "TARGET_NEON"
1248 {
1249- int regno = REGNO (operands[2]);
1250+ int regno = REGNO (operands[1]);
1251 rtx ops[4];
1252 ops[0] = operands[0];
1253 ops[1] = gen_rtx_REG (DImode, regno + 2);
1254 ops[2] = gen_rtx_REG (DImode, regno + 6);
1255 ops[3] = gen_rtx_REG (DImode, regno + 10);
1256- output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, [%0]!", ops);
1257+ output_asm_insn ("vst3.<V_sz_elem>\t{%P1, %P2, %P3}, %A0", ops);
1258 return "";
1259 }
1260 [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
1261 )
1262
1263 (define_insn "neon_vst3_lane<mode>"
1264- [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
1265+ [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
1266 (unspec:<V_three_elem>
1267 [(match_operand:EI 1 "s_register_operand" "w")
1268 (match_operand:SI 2 "immediate_operand" "i")
1269@@ -4838,7 +4831,7 @@
1270 ops[2] = gen_rtx_REG (DImode, regno + 2);
1271 ops[3] = gen_rtx_REG (DImode, regno + 4);
1272 ops[4] = operands[2];
1273- output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
1274+ output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
1275 ops);
1276 return "";
1277 }
1278@@ -4846,7 +4839,7 @@
1279 )
1280
1281 (define_insn "neon_vst3_lane<mode>"
1282- [(set (mem:<V_three_elem> (match_operand:SI 0 "s_register_operand" "r"))
1283+ [(set (match_operand:<V_three_elem> 0 "neon_struct_operand" "=Um")
1284 (unspec:<V_three_elem>
1285 [(match_operand:CI 1 "s_register_operand" "w")
1286 (match_operand:SI 2 "immediate_operand" "i")
1287@@ -4870,7 +4863,7 @@
1288 ops[2] = gen_rtx_REG (DImode, regno + 4);
1289 ops[3] = gen_rtx_REG (DImode, regno + 8);
1290 ops[4] = GEN_INT (lane);
1291- output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, [%0]",
1292+ output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0",
1293 ops);
1294 return "";
1295 }
1296@@ -4878,15 +4871,15 @@
1297
1298 (define_insn "neon_vld4<mode>"
1299 [(set (match_operand:OI 0 "s_register_operand" "=w")
1300- (unspec:OI [(mem:OI (match_operand:SI 1 "s_register_operand" "r"))
1301+ (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
1302 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1303 UNSPEC_VLD4))]
1304 "TARGET_NEON"
1305 {
1306 if (<V_sz_elem> == 64)
1307- return "vld1.64\t%h0, [%1]";
1308+ return "vld1.64\t%h0, %A1";
1309 else
1310- return "vld4.<V_sz_elem>\t%h0, [%1]";
1311+ return "vld4.<V_sz_elem>\t%h0, %A1";
1312 }
1313 [(set (attr "neon_type")
1314 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
1315@@ -4895,27 +4888,25 @@
1316 )
1317
1318 (define_expand "neon_vld4<mode>"
1319- [(match_operand:XI 0 "s_register_operand" "=w")
1320- (match_operand:SI 1 "s_register_operand" "+r")
1321+ [(match_operand:XI 0 "s_register_operand")
1322+ (match_operand:XI 1 "neon_struct_operand")
1323 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1324 "TARGET_NEON"
1325 {
1326- emit_insn (gen_neon_vld4qa<mode> (operands[0], operands[0],
1327- operands[1], operands[1]));
1328- emit_insn (gen_neon_vld4qb<mode> (operands[0], operands[0],
1329- operands[1], operands[1]));
1330+ rtx mem;
1331+
1332+ mem = adjust_address (operands[1], OImode, 0);
1333+ emit_insn (gen_neon_vld4qa<mode> (operands[0], mem));
1334+ mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
1335+ emit_insn (gen_neon_vld4qb<mode> (operands[0], mem, operands[0]));
1336 DONE;
1337 })
1338
1339 (define_insn "neon_vld4qa<mode>"
1340 [(set (match_operand:XI 0 "s_register_operand" "=w")
1341- (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
1342- (match_operand:XI 1 "s_register_operand" "0")
1343+ (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
1344 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1345- UNSPEC_VLD4A))
1346- (set (match_operand:SI 2 "s_register_operand" "=r")
1347- (plus:SI (match_dup 3)
1348- (const_int 32)))]
1349+ UNSPEC_VLD4A))]
1350 "TARGET_NEON"
1351 {
1352 int regno = REGNO (operands[0]);
1353@@ -4924,8 +4915,8 @@
1354 ops[1] = gen_rtx_REG (DImode, regno + 4);
1355 ops[2] = gen_rtx_REG (DImode, regno + 8);
1356 ops[3] = gen_rtx_REG (DImode, regno + 12);
1357- ops[4] = operands[2];
1358- output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
1359+ ops[4] = operands[1];
1360+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
1361 return "";
1362 }
1363 [(set_attr "neon_type" "neon_vld3_vld4")]
1364@@ -4933,13 +4924,10 @@
1365
1366 (define_insn "neon_vld4qb<mode>"
1367 [(set (match_operand:XI 0 "s_register_operand" "=w")
1368- (unspec:XI [(mem:XI (match_operand:SI 3 "s_register_operand" "2"))
1369- (match_operand:XI 1 "s_register_operand" "0")
1370+ (unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
1371+ (match_operand:XI 2 "s_register_operand" "0")
1372 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1373- UNSPEC_VLD4B))
1374- (set (match_operand:SI 2 "s_register_operand" "=r")
1375- (plus:SI (match_dup 3)
1376- (const_int 32)))]
1377+ UNSPEC_VLD4B))]
1378 "TARGET_NEON"
1379 {
1380 int regno = REGNO (operands[0]);
1381@@ -4948,8 +4936,8 @@
1382 ops[1] = gen_rtx_REG (DImode, regno + 6);
1383 ops[2] = gen_rtx_REG (DImode, regno + 10);
1384 ops[3] = gen_rtx_REG (DImode, regno + 14);
1385- ops[4] = operands[2];
1386- output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, [%4]!", ops);
1387+ ops[4] = operands[1];
1388+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0, %P1, %P2, %P3}, %A4", ops);
1389 return "";
1390 }
1391 [(set_attr "neon_type" "neon_vld3_vld4")]
1392@@ -4957,7 +4945,7 @@
1393
1394 (define_insn "neon_vld4_lane<mode>"
1395 [(set (match_operand:OI 0 "s_register_operand" "=w")
1396- (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
1397+ (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
1398 (match_operand:OI 2 "s_register_operand" "0")
1399 (match_operand:SI 3 "immediate_operand" "i")
1400 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1401@@ -4976,7 +4964,7 @@
1402 ops[3] = gen_rtx_REG (DImode, regno + 6);
1403 ops[4] = operands[1];
1404 ops[5] = operands[3];
1405- output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
1406+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
1407 ops);
1408 return "";
1409 }
1410@@ -4985,7 +4973,7 @@
1411
1412 (define_insn "neon_vld4_lane<mode>"
1413 [(set (match_operand:XI 0 "s_register_operand" "=w")
1414- (unspec:XI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
1415+ (unspec:XI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
1416 (match_operand:XI 2 "s_register_operand" "0")
1417 (match_operand:SI 3 "immediate_operand" "i")
1418 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1419@@ -5009,7 +4997,7 @@
1420 ops[3] = gen_rtx_REG (DImode, regno + 12);
1421 ops[4] = operands[1];
1422 ops[5] = GEN_INT (lane);
1423- output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, [%4]",
1424+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
1425 ops);
1426 return "";
1427 }
1428@@ -5018,7 +5006,7 @@
1429
1430 (define_insn "neon_vld4_dup<mode>"
1431 [(set (match_operand:OI 0 "s_register_operand" "=w")
1432- (unspec:OI [(mem:<V_four_elem> (match_operand:SI 1 "s_register_operand" "r"))
1433+ (unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
1434 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1435 UNSPEC_VLD4_DUP))]
1436 "TARGET_NEON"
1437@@ -5032,12 +5020,12 @@
1438 ops[2] = gen_rtx_REG (DImode, regno + 4);
1439 ops[3] = gen_rtx_REG (DImode, regno + 6);
1440 ops[4] = operands[1];
1441- output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, [%4]",
1442+ output_asm_insn ("vld4.<V_sz_elem>\t{%P0[], %P1[], %P2[], %P3[]}, %A4",
1443 ops);
1444 return "";
1445 }
1446 else
1447- return "vld1.<V_sz_elem>\t%h0, [%1]";
1448+ return "vld1.<V_sz_elem>\t%h0, %A1";
1449 }
1450 [(set (attr "neon_type")
1451 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
1452@@ -5046,16 +5034,16 @@
1453 )
1454
1455 (define_insn "neon_vst4<mode>"
1456- [(set (mem:OI (match_operand:SI 0 "s_register_operand" "r"))
1457+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
1458 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
1459 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1460 UNSPEC_VST4))]
1461 "TARGET_NEON"
1462 {
1463 if (<V_sz_elem> == 64)
1464- return "vst1.64\t%h1, [%0]";
1465+ return "vst1.64\t%h1, %A0";
1466 else
1467- return "vst4.<V_sz_elem>\t%h1, [%0]";
1468+ return "vst4.<V_sz_elem>\t%h1, %A0";
1469 }
1470 [(set (attr "neon_type")
1471 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
1472@@ -5064,64 +5052,62 @@
1473 )
1474
1475 (define_expand "neon_vst4<mode>"
1476- [(match_operand:SI 0 "s_register_operand" "+r")
1477- (match_operand:XI 1 "s_register_operand" "w")
1478+ [(match_operand:XI 0 "neon_struct_operand")
1479+ (match_operand:XI 1 "s_register_operand")
1480 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1481 "TARGET_NEON"
1482 {
1483- emit_insn (gen_neon_vst4qa<mode> (operands[0], operands[0], operands[1]));
1484- emit_insn (gen_neon_vst4qb<mode> (operands[0], operands[0], operands[1]));
1485+ rtx mem;
1486+
1487+ mem = adjust_address (operands[0], OImode, 0);
1488+ emit_insn (gen_neon_vst4qa<mode> (mem, operands[1]));
1489+ mem = adjust_address (mem, OImode, GET_MODE_SIZE (OImode));
1490+ emit_insn (gen_neon_vst4qb<mode> (mem, operands[1]));
1491 DONE;
1492 })
1493
1494 (define_insn "neon_vst4qa<mode>"
1495- [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
1496- (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
1497+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
1498+ (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
1499 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1500- UNSPEC_VST4A))
1501- (set (match_operand:SI 0 "s_register_operand" "=r")
1502- (plus:SI (match_dup 1)
1503- (const_int 32)))]
1504+ UNSPEC_VST4A))]
1505 "TARGET_NEON"
1506 {
1507- int regno = REGNO (operands[2]);
1508+ int regno = REGNO (operands[1]);
1509 rtx ops[5];
1510 ops[0] = operands[0];
1511 ops[1] = gen_rtx_REG (DImode, regno);
1512 ops[2] = gen_rtx_REG (DImode, regno + 4);
1513 ops[3] = gen_rtx_REG (DImode, regno + 8);
1514 ops[4] = gen_rtx_REG (DImode, regno + 12);
1515- output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
1516+ output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
1517 return "";
1518 }
1519 [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
1520 )
1521
1522 (define_insn "neon_vst4qb<mode>"
1523- [(set (mem:OI (match_operand:SI 1 "s_register_operand" "0"))
1524- (unspec:OI [(match_operand:XI 2 "s_register_operand" "w")
1525+ [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
1526+ (unspec:OI [(match_operand:XI 1 "s_register_operand" "w")
1527 (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1528- UNSPEC_VST4B))
1529- (set (match_operand:SI 0 "s_register_operand" "=r")
1530- (plus:SI (match_dup 1)
1531- (const_int 32)))]
1532+ UNSPEC_VST4B))]
1533 "TARGET_NEON"
1534 {
1535- int regno = REGNO (operands[2]);
1536+ int regno = REGNO (operands[1]);
1537 rtx ops[5];
1538 ops[0] = operands[0];
1539 ops[1] = gen_rtx_REG (DImode, regno + 2);
1540 ops[2] = gen_rtx_REG (DImode, regno + 6);
1541 ops[3] = gen_rtx_REG (DImode, regno + 10);
1542 ops[4] = gen_rtx_REG (DImode, regno + 14);
1543- output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, [%0]!", ops);
1544+ output_asm_insn ("vst4.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
1545 return "";
1546 }
1547 [(set_attr "neon_type" "neon_vst2_4_regs_vst3_vst4")]
1548 )
1549
1550 (define_insn "neon_vst4_lane<mode>"
1551- [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
1552+ [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
1553 (unspec:<V_four_elem>
1554 [(match_operand:OI 1 "s_register_operand" "w")
1555 (match_operand:SI 2 "immediate_operand" "i")
1556@@ -5141,7 +5127,7 @@
1557 ops[3] = gen_rtx_REG (DImode, regno + 4);
1558 ops[4] = gen_rtx_REG (DImode, regno + 6);
1559 ops[5] = operands[2];
1560- output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
1561+ output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
1562 ops);
1563 return "";
1564 }
1565@@ -5149,7 +5135,7 @@
1566 )
1567
1568 (define_insn "neon_vst4_lane<mode>"
1569- [(set (mem:<V_four_elem> (match_operand:SI 0 "s_register_operand" "r"))
1570+ [(set (match_operand:<V_four_elem> 0 "neon_struct_operand" "=Um")
1571 (unspec:<V_four_elem>
1572 [(match_operand:XI 1 "s_register_operand" "w")
1573 (match_operand:SI 2 "immediate_operand" "i")
1574@@ -5174,7 +5160,7 @@
1575 ops[3] = gen_rtx_REG (DImode, regno + 8);
1576 ops[4] = gen_rtx_REG (DImode, regno + 12);
1577 ops[5] = GEN_INT (lane);
1578- output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, [%0]",
1579+ output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
1580 ops);
1581 return "";
1582 }
1583Index: gcc-4_6-branch/gcc/config/arm/predicates.md
1584===================================================================
1585--- gcc-4_6-branch.orig/gcc/config/arm/predicates.md 2011-09-16 19:58:21.000000000 -0700
1586+++ gcc-4_6-branch/gcc/config/arm/predicates.md 2011-09-16 20:19:03.967834108 -0700
1587@@ -686,3 +686,8 @@
1588
1589 (define_special_predicate "add_operator"
1590 (match_code "plus"))
1591+
1592+(define_special_predicate "neon_struct_operand"
1593+ (and (match_code "mem")
1594+ (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
1595+
1596Index: gcc-4_6-branch/gcc/doc/tm.texi
1597===================================================================
1598--- gcc-4_6-branch.orig/gcc/doc/tm.texi 2011-06-24 08:13:00.000000000 -0700
1599+++ gcc-4_6-branch/gcc/doc/tm.texi 2011-09-16 20:16:00.257564628 -0700
1600@@ -2533,7 +2533,7 @@
1601 register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
1602 @var{x} is a floating-point constant. If the constant can't be loaded
1603 into any kind of register, code generation will be better if
1604-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1605+@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1606 of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
1607
1608 If an insn has pseudos in it after register allocation, reload will go
1609@@ -2570,8 +2570,8 @@
1610 register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
1611 @var{x} is a floating-point constant. If the constant can't be loaded
1612 into any kind of register, code generation will be better if
1613-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1614-of using @code{PREFERRED_RELOAD_CLASS}.
1615+@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1616+of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
1617
1618 If an insn has pseudos in it after register allocation, reload will go
1619 through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS}
1620@@ -4319,6 +4319,34 @@
1621 must have move patterns for this mode.
1622 @end deftypefn
1623
1624+@deftypefn {Target Hook} bool TARGET_ARRAY_MODE_SUPPORTED_P (enum machine_mode @var{mode}, unsigned HOST_WIDE_INT @var{nelems})
1625+Return true if GCC should try to use a scalar mode to store an array
1626+of @var{nelems} elements, given that each element has mode @var{mode}.
1627+Returning true here overrides the usual @code{MAX_FIXED_MODE} limit
1628+and allows GCC to use any defined integer mode.
1629+
1630+One use of this hook is to support vector load and store operations
1631+that operate on several homogeneous vectors. For example, ARM NEON
1632+has operations like:
1633+
1634+@smallexample
1635+int8x8x3_t vld3_s8 (const int8_t *)
1636+@end smallexample
1637+
1638+where the return type is defined as:
1639+
1640+@smallexample
1641+typedef struct int8x8x3_t
1642+@{
1643+ int8x8_t val[3];
1644+@} int8x8x3_t;
1645+@end smallexample
1646+
1647+If this hook allows @code{val} to have a scalar mode, then
1648+@code{int8x8x3_t} can have the same mode. GCC can then store
1649+@code{int8x8x3_t}s in registers rather than forcing them onto the stack.
1650+@end deftypefn
1651+
1652 @deftypefn {Target Hook} bool TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P (enum machine_mode @var{mode})
1653 Define this to return nonzero for machine modes for which the port has
1654 small register classes. If this target hook returns nonzero for a given
1655@@ -5577,13 +5605,13 @@
1656 @code{TARGET_MODE_DEPENDENT_ADDRESS_P} target hook.
1657 @end defmac
1658
1659-@defmac LEGITIMATE_CONSTANT_P (@var{x})
1660-A C expression that is nonzero if @var{x} is a legitimate constant for
1661-an immediate operand on the target machine. You can assume that
1662-@var{x} satisfies @code{CONSTANT_P}, so you need not check this. In fact,
1663-@samp{1} is a suitable definition for this macro on machines where
1664-anything @code{CONSTANT_P} is valid.
1665-@end defmac
1666+@deftypefn {Target Hook} bool TARGET_LEGITIMATE_CONSTANT_P (enum machine_mode @var{mode}, rtx @var{x})
1667+This hook returns true if @var{x} is a legitimate constant for a
1668+@var{mode}-mode immediate operand on the target machine. You can assume that
1669+@var{x} satisfies @code{CONSTANT_P}, so you need not check this.
1670+
1671+The default definition returns true.
1672+@end deftypefn
1673
1674 @deftypefn {Target Hook} rtx TARGET_DELEGITIMIZE_ADDRESS (rtx @var{x})
1675 This hook is used to undo the possibly obfuscating effects of the
1676Index: gcc-4_6-branch/gcc/doc/tm.texi.in
1677===================================================================
1678--- gcc-4_6-branch.orig/gcc/doc/tm.texi.in 2011-06-24 08:13:00.000000000 -0700
1679+++ gcc-4_6-branch/gcc/doc/tm.texi.in 2011-09-16 20:16:00.257564628 -0700
1680@@ -2521,7 +2521,7 @@
1681 register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
1682 @var{x} is a floating-point constant. If the constant can't be loaded
1683 into any kind of register, code generation will be better if
1684-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1685+@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1686 of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
1687
1688 If an insn has pseudos in it after register allocation, reload will go
1689@@ -2558,8 +2558,8 @@
1690 register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
1691 @var{x} is a floating-point constant. If the constant can't be loaded
1692 into any kind of register, code generation will be better if
1693-@code{LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1694-of using @code{PREFERRED_RELOAD_CLASS}.
1695+@code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead
1696+of using @code{TARGET_PREFERRED_RELOAD_CLASS}.
1697
1698 If an insn has pseudos in it after register allocation, reload will go
1699 through the alternatives and call repeatedly @code{PREFERRED_RELOAD_CLASS}
1700@@ -4305,6 +4305,8 @@
1701 must have move patterns for this mode.
1702 @end deftypefn
1703
1704+@hook TARGET_ARRAY_MODE_SUPPORTED_P
1705+
1706 @hook TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
1707 Define this to return nonzero for machine modes for which the port has
1708 small register classes. If this target hook returns nonzero for a given
1709@@ -5555,13 +5557,13 @@
1710 @code{TARGET_MODE_DEPENDENT_ADDRESS_P} target hook.
1711 @end defmac
1712
1713-@defmac LEGITIMATE_CONSTANT_P (@var{x})
1714-A C expression that is nonzero if @var{x} is a legitimate constant for
1715-an immediate operand on the target machine. You can assume that
1716-@var{x} satisfies @code{CONSTANT_P}, so you need not check this. In fact,
1717-@samp{1} is a suitable definition for this macro on machines where
1718-anything @code{CONSTANT_P} is valid.
1719-@end defmac
1720+@hook TARGET_LEGITIMATE_CONSTANT_P
1721+This hook returns true if @var{x} is a legitimate constant for a
1722+@var{mode}-mode immediate operand on the target machine. You can assume that
1723+@var{x} satisfies @code{CONSTANT_P}, so you need not check this.
1724+
1725+The default definition returns true.
1726+@end deftypefn
1727
1728 @hook TARGET_DELEGITIMIZE_ADDRESS
1729 This hook is used to undo the possibly obfuscating effects of the
1730Index: gcc-4_6-branch/gcc/expr.c
1731===================================================================
1732--- gcc-4_6-branch.orig/gcc/expr.c 2011-09-16 20:14:32.000000000 -0700
1733+++ gcc-4_6-branch/gcc/expr.c 2011-09-16 20:16:00.267564792 -0700
1734@@ -1497,7 +1497,7 @@
1735 if (nregs == 0)
1736 return;
1737
1738- if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x))
1739+ if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
1740 x = validize_mem (force_const_mem (mode, x));
1741
1742 /* See if the machine can do this with a load multiple insn. */
1743@@ -2308,7 +2308,7 @@
1744 offset -= size;
1745
1746 cst = (*constfun) (constfundata, offset, mode);
1747- if (!LEGITIMATE_CONSTANT_P (cst))
1748+ if (!targetm.legitimate_constant_p (mode, cst))
1749 return 0;
1750
1751 if (!reverse)
1752@@ -3363,7 +3363,7 @@
1753
1754 y_cst = y;
1755
1756- if (!LEGITIMATE_CONSTANT_P (y))
1757+ if (!targetm.legitimate_constant_p (mode, y))
1758 {
1759 y = force_const_mem (mode, y);
1760
1761@@ -3419,7 +3419,7 @@
1762
1763 REAL_VALUE_FROM_CONST_DOUBLE (r, y);
1764
1765- if (LEGITIMATE_CONSTANT_P (y))
1766+ if (targetm.legitimate_constant_p (dstmode, y))
1767 oldcost = rtx_cost (y, SET, speed);
1768 else
1769 oldcost = rtx_cost (force_const_mem (dstmode, y), SET, speed);
1770@@ -3442,7 +3442,7 @@
1771
1772 trunc_y = CONST_DOUBLE_FROM_REAL_VALUE (r, srcmode);
1773
1774- if (LEGITIMATE_CONSTANT_P (trunc_y))
1775+ if (targetm.legitimate_constant_p (srcmode, trunc_y))
1776 {
1777 /* Skip if the target needs extra instructions to perform
1778 the extension. */
1779@@ -3855,7 +3855,7 @@
1780 by setting SKIP to 0. */
1781 skip = (reg_parm_stack_space == 0) ? 0 : not_stack;
1782
1783- if (CONSTANT_P (x) && ! LEGITIMATE_CONSTANT_P (x))
1784+ if (CONSTANT_P (x) && !targetm.legitimate_constant_p (mode, x))
1785 x = validize_mem (force_const_mem (mode, x));
1786
1787 /* If X is a hard register in a non-integer mode, copy it into a pseudo;
1788@@ -9108,7 +9108,7 @@
1789 constant and we don't need a memory reference. */
1790 if (CONSTANT_P (op0)
1791 && mode2 != BLKmode
1792- && LEGITIMATE_CONSTANT_P (op0)
1793+ && targetm.legitimate_constant_p (mode2, op0)
1794 && !must_force_mem)
1795 op0 = force_reg (mode2, op0);
1796
1797Index: gcc-4_6-branch/gcc/hooks.c
1798===================================================================
1799--- gcc-4_6-branch.orig/gcc/hooks.c 2011-06-24 08:33:48.000000000 -0700
1800+++ gcc-4_6-branch/gcc/hooks.c 2011-09-16 20:16:00.267564792 -0700
1801@@ -101,6 +101,15 @@
1802 return true;
1803 }
1804
1805+/* Generic hook that takes (enum machine_mode, unsigned HOST_WIDE_INT)
1806+ and returns false. */
1807+bool
1808+hook_bool_mode_uhwi_false (enum machine_mode mode ATTRIBUTE_UNUSED,
1809+ unsigned HOST_WIDE_INT value ATTRIBUTE_UNUSED)
1810+{
1811+ return false;
1812+}
1813+
1814 /* Generic hook that takes (FILE *, const char *) and does nothing. */
1815 void
1816 hook_void_FILEptr_constcharptr (FILE *a ATTRIBUTE_UNUSED, const char *b ATTRIBUTE_UNUSED)
1817Index: gcc-4_6-branch/gcc/hooks.h
1818===================================================================
1819--- gcc-4_6-branch.orig/gcc/hooks.h 2011-06-24 08:33:48.000000000 -0700
1820+++ gcc-4_6-branch/gcc/hooks.h 2011-09-16 20:16:00.267564792 -0700
1821@@ -34,6 +34,8 @@
1822 extern bool hook_bool_mode_true (enum machine_mode);
1823 extern bool hook_bool_mode_const_rtx_false (enum machine_mode, const_rtx);
1824 extern bool hook_bool_mode_const_rtx_true (enum machine_mode, const_rtx);
1825+extern bool hook_bool_mode_uhwi_false (enum machine_mode,
1826+ unsigned HOST_WIDE_INT);
1827 extern bool hook_bool_tree_false (tree);
1828 extern bool hook_bool_const_tree_false (const_tree);
1829 extern bool hook_bool_tree_true (tree);
1830Index: gcc-4_6-branch/gcc/recog.c
1831===================================================================
1832--- gcc-4_6-branch.orig/gcc/recog.c 2011-06-24 08:33:49.000000000 -0700
1833+++ gcc-4_6-branch/gcc/recog.c 2011-09-16 20:16:00.277564886 -0700
1834@@ -930,7 +930,9 @@
1835 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
1836 || mode == VOIDmode)
1837 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1838- && LEGITIMATE_CONSTANT_P (op));
1839+ && targetm.legitimate_constant_p (mode == VOIDmode
1840+ ? GET_MODE (op)
1841+ : mode, op));
1842
1843 /* Except for certain constants with VOIDmode, already checked for,
1844 OP's mode must match MODE if MODE specifies a mode. */
1845@@ -1107,7 +1109,9 @@
1846 && (GET_MODE (op) == mode || mode == VOIDmode
1847 || GET_MODE (op) == VOIDmode)
1848 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1849- && LEGITIMATE_CONSTANT_P (op));
1850+ && targetm.legitimate_constant_p (mode == VOIDmode
1851+ ? GET_MODE (op)
1852+ : mode, op));
1853 }
1854
1855 /* Returns 1 if OP is an operand that is a CONST_INT. */
1856Index: gcc-4_6-branch/gcc/reload.c
1857===================================================================
1858--- gcc-4_6-branch.orig/gcc/reload.c 2011-06-24 08:33:49.000000000 -0700
1859+++ gcc-4_6-branch/gcc/reload.c 2011-09-16 20:16:00.277564886 -0700
1860@@ -4721,7 +4721,8 @@
1861 simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno],
1862 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
1863 gcc_assert (tem);
1864- if (CONSTANT_P (tem) && !LEGITIMATE_CONSTANT_P (tem))
1865+ if (CONSTANT_P (tem)
1866+ && !targetm.legitimate_constant_p (GET_MODE (x), tem))
1867 {
1868 tem = force_const_mem (GET_MODE (x), tem);
1869 i = find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0),
1870@@ -6049,7 +6050,7 @@
1871 enum reload_type type, int ind_levels)
1872 {
1873 if (CONSTANT_P (x)
1874- && (! LEGITIMATE_CONSTANT_P (x)
1875+ && (!targetm.legitimate_constant_p (mode, x)
1876 || targetm.preferred_reload_class (x, rclass) == NO_REGS))
1877 {
1878 x = force_const_mem (mode, x);
1879@@ -6059,7 +6060,7 @@
1880
1881 else if (GET_CODE (x) == PLUS
1882 && CONSTANT_P (XEXP (x, 1))
1883- && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1))
1884+ && (!targetm.legitimate_constant_p (GET_MODE (x), XEXP (x, 1))
1885 || targetm.preferred_reload_class (XEXP (x, 1), rclass)
1886 == NO_REGS))
1887 {
1888Index: gcc-4_6-branch/gcc/reload1.c
1889===================================================================
1890--- gcc-4_6-branch.orig/gcc/reload1.c 2011-06-24 08:33:49.000000000 -0700
1891+++ gcc-4_6-branch/gcc/reload1.c 2011-09-16 20:16:00.277564886 -0700
1892@@ -4155,6 +4155,9 @@
1893 }
1894 else if (function_invariant_p (x))
1895 {
1896+ enum machine_mode mode;
1897+
1898+ mode = GET_MODE (SET_DEST (set));
1899 if (GET_CODE (x) == PLUS)
1900 {
1901 /* This is PLUS of frame pointer and a constant,
1902@@ -4167,12 +4170,11 @@
1903 reg_equiv_invariant[i] = x;
1904 num_eliminable_invariants++;
1905 }
1906- else if (LEGITIMATE_CONSTANT_P (x))
1907+ else if (targetm.legitimate_constant_p (mode, x))
1908 reg_equiv_constant[i] = x;
1909 else
1910 {
1911- reg_equiv_memory_loc[i]
1912- = force_const_mem (GET_MODE (SET_DEST (set)), x);
1913+ reg_equiv_memory_loc[i] = force_const_mem (mode, x);
1914 if (! reg_equiv_memory_loc[i])
1915 reg_equiv_init[i] = NULL_RTX;
1916 }
1917Index: gcc-4_6-branch/gcc/stor-layout.c
1918===================================================================
1919--- gcc-4_6-branch.orig/gcc/stor-layout.c 2011-06-24 08:33:49.000000000 -0700
1920+++ gcc-4_6-branch/gcc/stor-layout.c 2011-09-16 20:16:00.287564867 -0700
1921@@ -546,6 +546,34 @@
1922 return MIN (BIGGEST_ALIGNMENT, MAX (1, mode_base_align[mode]*BITS_PER_UNIT));
1923 }
1924
1925+/* Return the natural mode of an array, given that it is SIZE bytes in
1926+ total and has elements of type ELEM_TYPE. */
1927+
1928+static enum machine_mode
1929+mode_for_array (tree elem_type, tree size)
1930+{
1931+ tree elem_size;
1932+ unsigned HOST_WIDE_INT int_size, int_elem_size;
1933+ bool limit_p;
1934+
1935+ /* One-element arrays get the component type's mode. */
1936+ elem_size = TYPE_SIZE (elem_type);
1937+ if (simple_cst_equal (size, elem_size))
1938+ return TYPE_MODE (elem_type);
1939+
1940+ limit_p = true;
1941+ if (host_integerp (size, 1) && host_integerp (elem_size, 1))
1942+ {
1943+ int_size = tree_low_cst (size, 1);
1944+ int_elem_size = tree_low_cst (elem_size, 1);
1945+ if (int_elem_size > 0
1946+ && int_size % int_elem_size == 0
1947+ && targetm.array_mode_supported_p (TYPE_MODE (elem_type),
1948+ int_size / int_elem_size))
1949+ limit_p = false;
1950+ }
1951+ return mode_for_size_tree (size, MODE_INT, limit_p);
1952+}
1953
1954 /* Subroutine of layout_decl: Force alignment required for the data type.
1955 But if the decl itself wants greater alignment, don't override that. */
1956@@ -2039,14 +2067,8 @@
1957 && (TYPE_MODE (TREE_TYPE (type)) != BLKmode
1958 || TYPE_NO_FORCE_BLK (TREE_TYPE (type))))
1959 {
1960- /* One-element arrays get the component type's mode. */
1961- if (simple_cst_equal (TYPE_SIZE (type),
1962- TYPE_SIZE (TREE_TYPE (type))))
1963- SET_TYPE_MODE (type, TYPE_MODE (TREE_TYPE (type)));
1964- else
1965- SET_TYPE_MODE (type, mode_for_size_tree (TYPE_SIZE (type),
1966- MODE_INT, 1));
1967-
1968+ SET_TYPE_MODE (type, mode_for_array (TREE_TYPE (type),
1969+ TYPE_SIZE (type)));
1970 if (TYPE_MODE (type) != BLKmode
1971 && STRICT_ALIGNMENT && TYPE_ALIGN (type) < BIGGEST_ALIGNMENT
1972 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (TYPE_MODE (type)))
1973Index: gcc-4_6-branch/gcc/target.def
1974===================================================================
1975--- gcc-4_6-branch.orig/gcc/target.def 2011-06-24 08:33:48.000000000 -0700
1976+++ gcc-4_6-branch/gcc/target.def 2011-09-16 20:16:00.287564867 -0700
1977@@ -1344,6 +1344,13 @@
1978 unsigned, (unsigned nunroll, struct loop *loop),
1979 NULL)
1980
1981+/* True if X is a legitimate MODE-mode immediate operand. */
1982+DEFHOOK
1983+(legitimate_constant_p,
1984+ "",
1985+ bool, (enum machine_mode mode, rtx x),
1986+ default_legitimate_constant_p)
1987+
1988 /* True if the constant X cannot be placed in the constant pool. */
1989 DEFHOOK
1990 (cannot_force_const_mem,
1991@@ -1611,6 +1618,38 @@
1992 bool, (enum machine_mode mode),
1993 hook_bool_mode_false)
1994
1995+/* True if we should try to use a scalar mode to represent an array,
1996+ overriding the usual MAX_FIXED_MODE limit. */
1997+DEFHOOK
1998+(array_mode_supported_p,
1999+ "Return true if GCC should try to use a scalar mode to store an array\n\
2000+of @var{nelems} elements, given that each element has mode @var{mode}.\n\
2001+Returning true here overrides the usual @code{MAX_FIXED_MODE} limit\n\
2002+and allows GCC to use any defined integer mode.\n\
2003+\n\
2004+One use of this hook is to support vector load and store operations\n\
2005+that operate on several homogeneous vectors. For example, ARM NEON\n\
2006+has operations like:\n\
2007+\n\
2008+@smallexample\n\
2009+int8x8x3_t vld3_s8 (const int8_t *)\n\
2010+@end smallexample\n\
2011+\n\
2012+where the return type is defined as:\n\
2013+\n\
2014+@smallexample\n\
2015+typedef struct int8x8x3_t\n\
2016+@{\n\
2017+ int8x8_t val[3];\n\
2018+@} int8x8x3_t;\n\
2019+@end smallexample\n\
2020+\n\
2021+If this hook allows @code{val} to have a scalar mode, then\n\
2022+@code{int8x8x3_t} can have the same mode. GCC can then store\n\
2023+@code{int8x8x3_t}s in registers rather than forcing them onto the stack.",
2024+ bool, (enum machine_mode mode, unsigned HOST_WIDE_INT nelems),
2025+ hook_bool_mode_uhwi_false)
2026+
2027 /* Compute cost of moving data from a register of class FROM to one of
2028 TO, using MODE. */
2029 DEFHOOK
2030Index: gcc-4_6-branch/gcc/targhooks.c
2031===================================================================
2032--- gcc-4_6-branch.orig/gcc/targhooks.c 2011-06-24 08:33:48.000000000 -0700
2033+++ gcc-4_6-branch/gcc/targhooks.c 2011-09-16 20:16:00.287564867 -0700
2034@@ -1519,4 +1519,15 @@
2035 { OPT_LEVELS_NONE, 0, NULL, 0 }
2036 };
2037
2038+bool
2039+default_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2040+ rtx x ATTRIBUTE_UNUSED)
2041+{
2042+#ifdef LEGITIMATE_CONSTANT_P
2043+ return LEGITIMATE_CONSTANT_P (x);
2044+#else
2045+ return true;
2046+#endif
2047+}
2048+
2049 #include "gt-targhooks.h"
2050Index: gcc-4_6-branch/gcc/targhooks.h
2051===================================================================
2052--- gcc-4_6-branch.orig/gcc/targhooks.h 2011-06-24 08:33:48.000000000 -0700
2053+++ gcc-4_6-branch/gcc/targhooks.h 2011-09-16 20:16:00.287564867 -0700
2054@@ -183,3 +183,4 @@
2055
2056 extern void *default_get_pch_validity (size_t *);
2057 extern const char *default_pch_valid_p (const void *, size_t);
2058+extern bool default_legitimate_constant_p (enum machine_mode, rtx);
2059Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vld3-1.c
2060===================================================================
2061--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2062+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vld3-1.c 2011-09-16 20:16:00.287564867 -0700
2063@@ -0,0 +1,27 @@
2064+/* { dg-do run } */
2065+/* { dg-require-effective-target arm_neon_hw } */
2066+/* { dg-options "-O2" } */
2067+/* { dg-add-options arm_neon } */
2068+
2069+#include "arm_neon.h"
2070+
2071+uint32_t buffer[12];
2072+
2073+void __attribute__((noinline))
2074+foo (uint32_t *a)
2075+{
2076+ uint32x4x3_t x;
2077+
2078+ x = vld3q_u32 (a);
2079+ x.val[0] = vaddq_u32 (x.val[0], x.val[1]);
2080+ vst3q_u32 (a, x);
2081+}
2082+
2083+int
2084+main (void)
2085+{
2086+ buffer[0] = 1;
2087+ buffer[1] = 2;
2088+ foo (buffer);
2089+ return buffer[0] != 3;
2090+}
2091Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vst3-1.c
2092===================================================================
2093--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2094+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vst3-1.c 2011-09-16 20:16:00.287564867 -0700
2095@@ -0,0 +1,25 @@
2096+/* { dg-do run } */
2097+/* { dg-require-effective-target arm_neon_hw } */
2098+/* { dg-options "-O2" } */
2099+/* { dg-add-options arm_neon } */
2100+
2101+#include "arm_neon.h"
2102+
2103+uint32_t buffer[64];
2104+
2105+void __attribute__((noinline))
2106+foo (uint32_t *a)
2107+{
2108+ uint32x4x3_t x;
2109+
2110+ x = vld3q_u32 (a);
2111+ a[35] = 1;
2112+ vst3q_lane_u32 (a + 32, x, 1);
2113+}
2114+
2115+int
2116+main (void)
2117+{
2118+ foo (buffer);
2119+ return buffer[35] != 1;
2120+}
2121Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
2122===================================================================
2123--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2011-06-24 08:13:40.000000000 -0700
2124+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2011-09-16 20:16:00.297564810 -0700
2125@@ -15,5 +15,5 @@
2126 out_float32x4_t = vld1q_dup_f32 (0);
2127 }
2128
2129-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2130+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2131 /* { dg-final { cleanup-saved-temps } } */
2132Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
2133===================================================================
2134--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2011-06-24 08:13:40.000000000 -0700
2135+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2011-09-16 20:16:00.297564810 -0700
2136@@ -15,5 +15,5 @@
2137 out_poly16x8_t = vld1q_dup_p16 (0);
2138 }
2139
2140-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2141+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2142 /* { dg-final { cleanup-saved-temps } } */
2143Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
2144===================================================================
2145--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2011-06-24 08:13:40.000000000 -0700
2146+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2011-09-16 20:16:00.297564810 -0700
2147@@ -15,5 +15,5 @@
2148 out_poly8x16_t = vld1q_dup_p8 (0);
2149 }
2150
2151-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2152+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2153 /* { dg-final { cleanup-saved-temps } } */
2154Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
2155===================================================================
2156--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2011-06-24 08:13:40.000000000 -0700
2157+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2011-09-16 20:16:00.297564810 -0700
2158@@ -15,5 +15,5 @@
2159 out_int16x8_t = vld1q_dup_s16 (0);
2160 }
2161
2162-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2163+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2164 /* { dg-final { cleanup-saved-temps } } */
2165Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
2166===================================================================
2167--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2011-06-24 08:13:40.000000000 -0700
2168+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2011-09-16 20:16:00.297564810 -0700
2169@@ -15,5 +15,5 @@
2170 out_int32x4_t = vld1q_dup_s32 (0);
2171 }
2172
2173-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2174+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2175 /* { dg-final { cleanup-saved-temps } } */
2176Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
2177===================================================================
2178--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2011-06-24 08:13:40.000000000 -0700
2179+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2011-09-16 20:16:00.347564808 -0700
2180@@ -15,5 +15,5 @@
2181 out_int64x2_t = vld1q_dup_s64 (0);
2182 }
2183
2184-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2185+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2186 /* { dg-final { cleanup-saved-temps } } */
2187Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
2188===================================================================
2189--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2011-06-24 08:13:40.000000000 -0700
2190+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2011-09-16 20:16:00.347564808 -0700
2191@@ -15,5 +15,5 @@
2192 out_int8x16_t = vld1q_dup_s8 (0);
2193 }
2194
2195-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2196+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2197 /* { dg-final { cleanup-saved-temps } } */
2198Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
2199===================================================================
2200--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2011-06-24 08:13:40.000000000 -0700
2201+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2011-09-16 20:16:00.347564808 -0700
2202@@ -15,5 +15,5 @@
2203 out_uint16x8_t = vld1q_dup_u16 (0);
2204 }
2205
2206-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2207+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2208 /* { dg-final { cleanup-saved-temps } } */
2209Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
2210===================================================================
2211--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2011-06-24 08:13:40.000000000 -0700
2212+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2011-09-16 20:16:00.347564808 -0700
2213@@ -15,5 +15,5 @@
2214 out_uint32x4_t = vld1q_dup_u32 (0);
2215 }
2216
2217-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2218+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2219 /* { dg-final { cleanup-saved-temps } } */
2220Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
2221===================================================================
2222--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2011-06-24 08:13:40.000000000 -0700
2223+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2011-09-16 20:16:00.347564808 -0700
2224@@ -15,5 +15,5 @@
2225 out_uint64x2_t = vld1q_dup_u64 (0);
2226 }
2227
2228-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2229+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2230 /* { dg-final { cleanup-saved-temps } } */
2231Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
2232===================================================================
2233--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2011-06-24 08:13:40.000000000 -0700
2234+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2011-09-16 20:16:00.347564808 -0700
2235@@ -15,5 +15,5 @@
2236 out_uint8x16_t = vld1q_dup_u8 (0);
2237 }
2238
2239-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2240+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2241 /* { dg-final { cleanup-saved-temps } } */
2242Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
2243===================================================================
2244--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
2245+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2011-09-16 20:16:00.347564808 -0700
2246@@ -16,5 +16,5 @@
2247 out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
2248 }
2249
2250-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2251+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2252 /* { dg-final { cleanup-saved-temps } } */
2253Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
2254===================================================================
2255--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
2256+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2011-09-16 20:16:00.347564808 -0700
2257@@ -16,5 +16,5 @@
2258 out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
2259 }
2260
2261-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2262+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2263 /* { dg-final { cleanup-saved-temps } } */
2264Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
2265===================================================================
2266--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2011-06-24 08:13:40.000000000 -0700
2267+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2011-09-16 20:16:00.347564808 -0700
2268@@ -16,5 +16,5 @@
2269 out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
2270 }
2271
2272-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2273+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2274 /* { dg-final { cleanup-saved-temps } } */
2275Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
2276===================================================================
2277--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
2278+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2011-09-16 20:16:00.347564808 -0700
2279@@ -16,5 +16,5 @@
2280 out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
2281 }
2282
2283-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2284+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2285 /* { dg-final { cleanup-saved-temps } } */
2286Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
2287===================================================================
2288--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
2289+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2011-09-16 20:16:00.347564808 -0700
2290@@ -16,5 +16,5 @@
2291 out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
2292 }
2293
2294-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2295+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2296 /* { dg-final { cleanup-saved-temps } } */
2297Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
2298===================================================================
2299--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2011-06-24 08:13:40.000000000 -0700
2300+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2011-09-16 20:16:00.347564808 -0700
2301@@ -16,5 +16,5 @@
2302 out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
2303 }
2304
2305-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2306+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2307 /* { dg-final { cleanup-saved-temps } } */
2308Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
2309===================================================================
2310--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2011-06-24 08:13:40.000000000 -0700
2311+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2011-09-16 20:16:00.347564808 -0700
2312@@ -16,5 +16,5 @@
2313 out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
2314 }
2315
2316-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2317+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2318 /* { dg-final { cleanup-saved-temps } } */
2319Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
2320===================================================================
2321--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
2322+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2011-09-16 20:16:00.347564808 -0700
2323@@ -16,5 +16,5 @@
2324 out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
2325 }
2326
2327-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2328+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2329 /* { dg-final { cleanup-saved-temps } } */
2330Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
2331===================================================================
2332--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
2333+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2011-09-16 20:16:00.347564808 -0700
2334@@ -16,5 +16,5 @@
2335 out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
2336 }
2337
2338-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2339+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2340 /* { dg-final { cleanup-saved-temps } } */
2341Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
2342===================================================================
2343--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2011-06-24 08:13:40.000000000 -0700
2344+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2011-09-16 20:16:00.347564808 -0700
2345@@ -16,5 +16,5 @@
2346 out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
2347 }
2348
2349-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2350+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2351 /* { dg-final { cleanup-saved-temps } } */
2352Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
2353===================================================================
2354--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2011-06-24 08:13:40.000000000 -0700
2355+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2011-09-16 20:16:00.347564808 -0700
2356@@ -16,5 +16,5 @@
2357 out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
2358 }
2359
2360-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2361+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2362 /* { dg-final { cleanup-saved-temps } } */
2363Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
2364===================================================================
2365--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2011-06-24 08:13:40.000000000 -0700
2366+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2011-09-16 20:16:00.357564842 -0700
2367@@ -15,5 +15,5 @@
2368 out_float32x4_t = vld1q_f32 (0);
2369 }
2370
2371-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2372+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2373 /* { dg-final { cleanup-saved-temps } } */
2374Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
2375===================================================================
2376--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2011-06-24 08:13:40.000000000 -0700
2377+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2011-09-16 20:16:00.357564842 -0700
2378@@ -15,5 +15,5 @@
2379 out_poly16x8_t = vld1q_p16 (0);
2380 }
2381
2382-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2383+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2384 /* { dg-final { cleanup-saved-temps } } */
2385Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
2386===================================================================
2387--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2011-06-24 08:13:40.000000000 -0700
2388+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2011-09-16 20:16:00.357564842 -0700
2389@@ -15,5 +15,5 @@
2390 out_poly8x16_t = vld1q_p8 (0);
2391 }
2392
2393-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2394+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2395 /* { dg-final { cleanup-saved-temps } } */
2396Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
2397===================================================================
2398--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2011-06-24 08:13:40.000000000 -0700
2399+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2011-09-16 20:16:00.357564842 -0700
2400@@ -15,5 +15,5 @@
2401 out_int16x8_t = vld1q_s16 (0);
2402 }
2403
2404-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2405+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2406 /* { dg-final { cleanup-saved-temps } } */
2407Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
2408===================================================================
2409--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2011-06-24 08:13:40.000000000 -0700
2410+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2011-09-16 20:16:00.357564842 -0700
2411@@ -15,5 +15,5 @@
2412 out_int32x4_t = vld1q_s32 (0);
2413 }
2414
2415-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2416+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2417 /* { dg-final { cleanup-saved-temps } } */
2418Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
2419===================================================================
2420--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2011-06-24 08:13:40.000000000 -0700
2421+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2011-09-16 20:16:00.357564842 -0700
2422@@ -15,5 +15,5 @@
2423 out_int64x2_t = vld1q_s64 (0);
2424 }
2425
2426-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2427+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2428 /* { dg-final { cleanup-saved-temps } } */
2429Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
2430===================================================================
2431--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2011-06-24 08:13:40.000000000 -0700
2432+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2011-09-16 20:16:00.357564842 -0700
2433@@ -15,5 +15,5 @@
2434 out_int8x16_t = vld1q_s8 (0);
2435 }
2436
2437-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2438+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2439 /* { dg-final { cleanup-saved-temps } } */
2440Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
2441===================================================================
2442--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2011-06-24 08:13:40.000000000 -0700
2443+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2011-09-16 20:16:00.357564842 -0700
2444@@ -15,5 +15,5 @@
2445 out_uint16x8_t = vld1q_u16 (0);
2446 }
2447
2448-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2449+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2450 /* { dg-final { cleanup-saved-temps } } */
2451Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
2452===================================================================
2453--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2011-06-24 08:13:40.000000000 -0700
2454+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2011-09-16 20:16:00.357564842 -0700
2455@@ -15,5 +15,5 @@
2456 out_uint32x4_t = vld1q_u32 (0);
2457 }
2458
2459-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2460+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2461 /* { dg-final { cleanup-saved-temps } } */
2462Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
2463===================================================================
2464--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2011-06-24 08:13:40.000000000 -0700
2465+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2011-09-16 20:16:00.357564842 -0700
2466@@ -15,5 +15,5 @@
2467 out_uint64x2_t = vld1q_u64 (0);
2468 }
2469
2470-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2471+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2472 /* { dg-final { cleanup-saved-temps } } */
2473Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
2474===================================================================
2475--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2011-06-24 08:13:40.000000000 -0700
2476+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2011-09-16 20:16:00.357564842 -0700
2477@@ -15,5 +15,5 @@
2478 out_uint8x16_t = vld1q_u8 (0);
2479 }
2480
2481-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2482+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2483 /* { dg-final { cleanup-saved-temps } } */
2484Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
2485===================================================================
2486--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2011-06-24 08:13:40.000000000 -0700
2487+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2011-09-16 20:16:00.357564842 -0700
2488@@ -15,5 +15,5 @@
2489 out_float32x2_t = vld1_dup_f32 (0);
2490 }
2491
2492-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2493+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2494 /* { dg-final { cleanup-saved-temps } } */
2495Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
2496===================================================================
2497--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2011-06-24 08:13:40.000000000 -0700
2498+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2011-09-16 20:16:00.357564842 -0700
2499@@ -15,5 +15,5 @@
2500 out_poly16x4_t = vld1_dup_p16 (0);
2501 }
2502
2503-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2504+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2505 /* { dg-final { cleanup-saved-temps } } */
2506Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
2507===================================================================
2508--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2011-06-24 08:13:40.000000000 -0700
2509+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2011-09-16 20:16:00.357564842 -0700
2510@@ -15,5 +15,5 @@
2511 out_poly8x8_t = vld1_dup_p8 (0);
2512 }
2513
2514-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2515+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2516 /* { dg-final { cleanup-saved-temps } } */
2517Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
2518===================================================================
2519--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2011-06-24 08:13:40.000000000 -0700
2520+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2011-09-16 20:16:00.357564842 -0700
2521@@ -15,5 +15,5 @@
2522 out_int16x4_t = vld1_dup_s16 (0);
2523 }
2524
2525-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2526+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2527 /* { dg-final { cleanup-saved-temps } } */
2528Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
2529===================================================================
2530--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2011-06-24 08:13:40.000000000 -0700
2531+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2011-09-16 20:16:00.357564842 -0700
2532@@ -15,5 +15,5 @@
2533 out_int32x2_t = vld1_dup_s32 (0);
2534 }
2535
2536-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2537+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2538 /* { dg-final { cleanup-saved-temps } } */
2539Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
2540===================================================================
2541--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2011-06-24 08:13:40.000000000 -0700
2542+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2011-09-16 20:16:00.357564842 -0700
2543@@ -15,5 +15,5 @@
2544 out_int64x1_t = vld1_dup_s64 (0);
2545 }
2546
2547-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2548+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2549 /* { dg-final { cleanup-saved-temps } } */
2550Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
2551===================================================================
2552--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2011-06-24 08:13:40.000000000 -0700
2553+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2011-09-16 20:16:00.357564842 -0700
2554@@ -15,5 +15,5 @@
2555 out_int8x8_t = vld1_dup_s8 (0);
2556 }
2557
2558-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2559+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2560 /* { dg-final { cleanup-saved-temps } } */
2561Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
2562===================================================================
2563--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2011-06-24 08:13:40.000000000 -0700
2564+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2011-09-16 20:16:00.357564842 -0700
2565@@ -15,5 +15,5 @@
2566 out_uint16x4_t = vld1_dup_u16 (0);
2567 }
2568
2569-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2570+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2571 /* { dg-final { cleanup-saved-temps } } */
2572Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
2573===================================================================
2574--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2011-06-24 08:13:40.000000000 -0700
2575+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2011-09-16 20:16:00.357564842 -0700
2576@@ -15,5 +15,5 @@
2577 out_uint32x2_t = vld1_dup_u32 (0);
2578 }
2579
2580-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2581+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2582 /* { dg-final { cleanup-saved-temps } } */
2583Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
2584===================================================================
2585--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2011-06-24 08:13:40.000000000 -0700
2586+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2011-09-16 20:16:00.367564848 -0700
2587@@ -15,5 +15,5 @@
2588 out_uint64x1_t = vld1_dup_u64 (0);
2589 }
2590
2591-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2592+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2593 /* { dg-final { cleanup-saved-temps } } */
2594Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
2595===================================================================
2596--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2011-06-24 08:13:40.000000000 -0700
2597+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2011-09-16 20:16:00.367564848 -0700
2598@@ -15,5 +15,5 @@
2599 out_uint8x8_t = vld1_dup_u8 (0);
2600 }
2601
2602-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2603+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2604 /* { dg-final { cleanup-saved-temps } } */
2605Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
2606===================================================================
2607--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2011-06-24 08:13:40.000000000 -0700
2608+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2011-09-16 20:16:00.367564848 -0700
2609@@ -16,5 +16,5 @@
2610 out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
2611 }
2612
2613-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2614+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2615 /* { dg-final { cleanup-saved-temps } } */
2616Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
2617===================================================================
2618--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2011-06-24 08:13:40.000000000 -0700
2619+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2011-09-16 20:16:00.367564848 -0700
2620@@ -16,5 +16,5 @@
2621 out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
2622 }
2623
2624-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2625+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2626 /* { dg-final { cleanup-saved-temps } } */
2627Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
2628===================================================================
2629--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2011-06-24 08:13:40.000000000 -0700
2630+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2011-09-16 20:16:00.367564848 -0700
2631@@ -16,5 +16,5 @@
2632 out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
2633 }
2634
2635-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2636+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2637 /* { dg-final { cleanup-saved-temps } } */
2638Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
2639===================================================================
2640--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2011-06-24 08:13:40.000000000 -0700
2641+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2011-09-16 20:16:00.367564848 -0700
2642@@ -16,5 +16,5 @@
2643 out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
2644 }
2645
2646-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2647+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2648 /* { dg-final { cleanup-saved-temps } } */
2649Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
2650===================================================================
2651--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2011-06-24 08:13:40.000000000 -0700
2652+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2011-09-16 20:16:00.367564848 -0700
2653@@ -16,5 +16,5 @@
2654 out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
2655 }
2656
2657-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2658+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2659 /* { dg-final { cleanup-saved-temps } } */
2660Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
2661===================================================================
2662--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2011-06-24 08:13:40.000000000 -0700
2663+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2011-09-16 20:16:00.367564848 -0700
2664@@ -16,5 +16,5 @@
2665 out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
2666 }
2667
2668-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2669+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2670 /* { dg-final { cleanup-saved-temps } } */
2671Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
2672===================================================================
2673--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2011-06-24 08:13:40.000000000 -0700
2674+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2011-09-16 20:16:00.367564848 -0700
2675@@ -16,5 +16,5 @@
2676 out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
2677 }
2678
2679-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2680+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2681 /* { dg-final { cleanup-saved-temps } } */
2682Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
2683===================================================================
2684--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2011-06-24 08:13:40.000000000 -0700
2685+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2011-09-16 20:16:00.367564848 -0700
2686@@ -16,5 +16,5 @@
2687 out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
2688 }
2689
2690-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2691+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2692 /* { dg-final { cleanup-saved-temps } } */
2693Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
2694===================================================================
2695--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2011-06-24 08:13:40.000000000 -0700
2696+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2011-09-16 20:16:00.367564848 -0700
2697@@ -16,5 +16,5 @@
2698 out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
2699 }
2700
2701-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2702+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2703 /* { dg-final { cleanup-saved-temps } } */
2704Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
2705===================================================================
2706--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2011-06-24 08:13:40.000000000 -0700
2707+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2011-09-16 20:16:00.367564848 -0700
2708@@ -16,5 +16,5 @@
2709 out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
2710 }
2711
2712-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2713+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2714 /* { dg-final { cleanup-saved-temps } } */
2715Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
2716===================================================================
2717--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2011-06-24 08:13:40.000000000 -0700
2718+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2011-09-16 20:16:00.367564848 -0700
2719@@ -16,5 +16,5 @@
2720 out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
2721 }
2722
2723-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2724+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2725 /* { dg-final { cleanup-saved-temps } } */
2726Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
2727===================================================================
2728--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2011-06-24 08:13:40.000000000 -0700
2729+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2011-09-16 20:16:00.367564848 -0700
2730@@ -15,5 +15,5 @@
2731 out_float32x2_t = vld1_f32 (0);
2732 }
2733
2734-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2735+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2736 /* { dg-final { cleanup-saved-temps } } */
2737Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
2738===================================================================
2739--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2011-06-24 08:13:40.000000000 -0700
2740+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2011-09-16 20:16:00.377564842 -0700
2741@@ -15,5 +15,5 @@
2742 out_poly16x4_t = vld1_p16 (0);
2743 }
2744
2745-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2746+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2747 /* { dg-final { cleanup-saved-temps } } */
2748Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
2749===================================================================
2750--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2011-06-24 08:13:40.000000000 -0700
2751+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2011-09-16 20:16:00.377564842 -0700
2752@@ -15,5 +15,5 @@
2753 out_poly8x8_t = vld1_p8 (0);
2754 }
2755
2756-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2757+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2758 /* { dg-final { cleanup-saved-temps } } */
2759Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
2760===================================================================
2761--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2011-06-24 08:13:40.000000000 -0700
2762+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2011-09-16 20:16:00.377564842 -0700
2763@@ -15,5 +15,5 @@
2764 out_int16x4_t = vld1_s16 (0);
2765 }
2766
2767-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2768+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2769 /* { dg-final { cleanup-saved-temps } } */
2770Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
2771===================================================================
2772--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2011-06-24 08:13:40.000000000 -0700
2773+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2011-09-16 20:16:00.377564842 -0700
2774@@ -15,5 +15,5 @@
2775 out_int32x2_t = vld1_s32 (0);
2776 }
2777
2778-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2779+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2780 /* { dg-final { cleanup-saved-temps } } */
2781Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
2782===================================================================
2783--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2011-06-24 08:13:40.000000000 -0700
2784+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2011-09-16 20:16:00.377564842 -0700
2785@@ -15,5 +15,5 @@
2786 out_int64x1_t = vld1_s64 (0);
2787 }
2788
2789-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2790+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2791 /* { dg-final { cleanup-saved-temps } } */
2792Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
2793===================================================================
2794--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2011-06-24 08:13:40.000000000 -0700
2795+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2011-09-16 20:16:00.377564842 -0700
2796@@ -15,5 +15,5 @@
2797 out_int8x8_t = vld1_s8 (0);
2798 }
2799
2800-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2801+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2802 /* { dg-final { cleanup-saved-temps } } */
2803Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
2804===================================================================
2805--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2011-06-24 08:13:40.000000000 -0700
2806+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2011-09-16 20:16:00.377564842 -0700
2807@@ -15,5 +15,5 @@
2808 out_uint16x4_t = vld1_u16 (0);
2809 }
2810
2811-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2812+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2813 /* { dg-final { cleanup-saved-temps } } */
2814Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
2815===================================================================
2816--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2011-06-24 08:13:40.000000000 -0700
2817+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2011-09-16 20:16:00.377564842 -0700
2818@@ -15,5 +15,5 @@
2819 out_uint32x2_t = vld1_u32 (0);
2820 }
2821
2822-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2823+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2824 /* { dg-final { cleanup-saved-temps } } */
2825Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
2826===================================================================
2827--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2011-06-24 08:13:40.000000000 -0700
2828+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2011-09-16 20:16:00.377564842 -0700
2829@@ -15,5 +15,5 @@
2830 out_uint64x1_t = vld1_u64 (0);
2831 }
2832
2833-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2834+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2835 /* { dg-final { cleanup-saved-temps } } */
2836Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
2837===================================================================
2838--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2011-06-24 08:13:40.000000000 -0700
2839+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2011-09-16 20:16:00.387564830 -0700
2840@@ -15,5 +15,5 @@
2841 out_uint8x8_t = vld1_u8 (0);
2842 }
2843
2844-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2845+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2846 /* { dg-final { cleanup-saved-temps } } */
2847Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
2848===================================================================
2849--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
2850+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2011-09-16 20:16:00.387564830 -0700
2851@@ -16,5 +16,5 @@
2852 out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
2853 }
2854
2855-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2856+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2857 /* { dg-final { cleanup-saved-temps } } */
2858Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
2859===================================================================
2860--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
2861+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2011-09-16 20:16:00.387564830 -0700
2862@@ -16,5 +16,5 @@
2863 out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
2864 }
2865
2866-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2867+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2868 /* { dg-final { cleanup-saved-temps } } */
2869Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
2870===================================================================
2871--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
2872+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2011-09-16 20:16:00.387564830 -0700
2873@@ -16,5 +16,5 @@
2874 out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
2875 }
2876
2877-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2878+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2879 /* { dg-final { cleanup-saved-temps } } */
2880Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
2881===================================================================
2882--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
2883+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2011-09-16 20:16:00.387564830 -0700
2884@@ -16,5 +16,5 @@
2885 out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
2886 }
2887
2888-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2889+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2890 /* { dg-final { cleanup-saved-temps } } */
2891Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
2892===================================================================
2893--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
2894+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2011-09-16 20:16:00.397564843 -0700
2895@@ -16,5 +16,5 @@
2896 out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
2897 }
2898
2899-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2900+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2901 /* { dg-final { cleanup-saved-temps } } */
2902Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
2903===================================================================
2904--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
2905+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2011-09-16 20:16:00.397564843 -0700
2906@@ -16,5 +16,5 @@
2907 out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
2908 }
2909
2910-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2911+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2912 /* { dg-final { cleanup-saved-temps } } */
2913Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
2914===================================================================
2915--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2011-06-24 08:13:40.000000000 -0700
2916+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2011-09-16 20:16:00.397564843 -0700
2917@@ -15,6 +15,6 @@
2918 out_float32x4x2_t = vld2q_f32 (0);
2919 }
2920
2921-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2922-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2923+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2924+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2925 /* { dg-final { cleanup-saved-temps } } */
2926Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
2927===================================================================
2928--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2011-06-24 08:13:40.000000000 -0700
2929+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2011-09-16 20:16:00.397564843 -0700
2930@@ -15,6 +15,6 @@
2931 out_poly16x8x2_t = vld2q_p16 (0);
2932 }
2933
2934-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2935-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2936+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2937+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2938 /* { dg-final { cleanup-saved-temps } } */
2939Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
2940===================================================================
2941--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2011-06-24 08:13:40.000000000 -0700
2942+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2011-09-16 20:16:00.397564843 -0700
2943@@ -15,6 +15,6 @@
2944 out_poly8x16x2_t = vld2q_p8 (0);
2945 }
2946
2947-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2948-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2949+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2950+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2951 /* { dg-final { cleanup-saved-temps } } */
2952Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
2953===================================================================
2954--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2011-06-24 08:13:40.000000000 -0700
2955+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2011-09-16 20:16:00.397564843 -0700
2956@@ -15,6 +15,6 @@
2957 out_int16x8x2_t = vld2q_s16 (0);
2958 }
2959
2960-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2961-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2962+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2963+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2964 /* { dg-final { cleanup-saved-temps } } */
2965Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
2966===================================================================
2967--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2011-06-24 08:13:40.000000000 -0700
2968+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2011-09-16 20:16:00.397564843 -0700
2969@@ -15,6 +15,6 @@
2970 out_int32x4x2_t = vld2q_s32 (0);
2971 }
2972
2973-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2974-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2975+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2976+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2977 /* { dg-final { cleanup-saved-temps } } */
2978Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
2979===================================================================
2980--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2011-06-24 08:13:40.000000000 -0700
2981+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2011-09-16 20:16:00.397564843 -0700
2982@@ -15,6 +15,6 @@
2983 out_int8x16x2_t = vld2q_s8 (0);
2984 }
2985
2986-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2987-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2988+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2989+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2990 /* { dg-final { cleanup-saved-temps } } */
2991Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
2992===================================================================
2993--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2011-06-24 08:13:40.000000000 -0700
2994+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2011-09-16 20:16:00.397564843 -0700
2995@@ -15,6 +15,6 @@
2996 out_uint16x8x2_t = vld2q_u16 (0);
2997 }
2998
2999-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3000-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3001+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3002+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3003 /* { dg-final { cleanup-saved-temps } } */
3004Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
3005===================================================================
3006--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2011-06-24 08:13:40.000000000 -0700
3007+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2011-09-16 20:16:00.407564879 -0700
3008@@ -15,6 +15,6 @@
3009 out_uint32x4x2_t = vld2q_u32 (0);
3010 }
3011
3012-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3013-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3014+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3015+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3016 /* { dg-final { cleanup-saved-temps } } */
3017Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
3018===================================================================
3019--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2011-06-24 08:13:40.000000000 -0700
3020+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2011-09-16 20:16:00.407564879 -0700
3021@@ -15,6 +15,6 @@
3022 out_uint8x16x2_t = vld2q_u8 (0);
3023 }
3024
3025-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3026-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3027+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3028+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3029 /* { dg-final { cleanup-saved-temps } } */
3030Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
3031===================================================================
3032--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2011-06-24 08:13:40.000000000 -0700
3033+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2011-09-16 20:16:00.407564879 -0700
3034@@ -15,5 +15,5 @@
3035 out_float32x2x2_t = vld2_dup_f32 (0);
3036 }
3037
3038-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3039+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3040 /* { dg-final { cleanup-saved-temps } } */
3041Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
3042===================================================================
3043--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2011-06-24 08:13:40.000000000 -0700
3044+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2011-09-16 20:16:00.407564879 -0700
3045@@ -15,5 +15,5 @@
3046 out_poly16x4x2_t = vld2_dup_p16 (0);
3047 }
3048
3049-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3050+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3051 /* { dg-final { cleanup-saved-temps } } */
3052Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
3053===================================================================
3054--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2011-06-24 08:13:40.000000000 -0700
3055+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2011-09-16 20:16:00.407564879 -0700
3056@@ -15,5 +15,5 @@
3057 out_poly8x8x2_t = vld2_dup_p8 (0);
3058 }
3059
3060-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3061+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3062 /* { dg-final { cleanup-saved-temps } } */
3063Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
3064===================================================================
3065--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2011-06-24 08:13:40.000000000 -0700
3066+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2011-09-16 20:16:00.407564879 -0700
3067@@ -15,5 +15,5 @@
3068 out_int16x4x2_t = vld2_dup_s16 (0);
3069 }
3070
3071-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3072+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3073 /* { dg-final { cleanup-saved-temps } } */
3074Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
3075===================================================================
3076--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2011-06-24 08:13:40.000000000 -0700
3077+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2011-09-16 20:16:00.407564879 -0700
3078@@ -15,5 +15,5 @@
3079 out_int32x2x2_t = vld2_dup_s32 (0);
3080 }
3081
3082-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3083+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3084 /* { dg-final { cleanup-saved-temps } } */
3085Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
3086===================================================================
3087--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2011-06-24 08:13:40.000000000 -0700
3088+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2011-09-16 20:16:00.407564879 -0700
3089@@ -15,5 +15,5 @@
3090 out_int64x1x2_t = vld2_dup_s64 (0);
3091 }
3092
3093-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3094+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3095 /* { dg-final { cleanup-saved-temps } } */
3096Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
3097===================================================================
3098--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2011-06-24 08:13:40.000000000 -0700
3099+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2011-09-16 20:16:00.417564906 -0700
3100@@ -15,5 +15,5 @@
3101 out_int8x8x2_t = vld2_dup_s8 (0);
3102 }
3103
3104-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3105+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3106 /* { dg-final { cleanup-saved-temps } } */
3107Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
3108===================================================================
3109--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2011-06-24 08:13:40.000000000 -0700
3110+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2011-09-16 20:16:00.417564906 -0700
3111@@ -15,5 +15,5 @@
3112 out_uint16x4x2_t = vld2_dup_u16 (0);
3113 }
3114
3115-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3116+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3117 /* { dg-final { cleanup-saved-temps } } */
3118Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
3119===================================================================
3120--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2011-06-24 08:13:40.000000000 -0700
3121+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2011-09-16 20:16:00.417564906 -0700
3122@@ -15,5 +15,5 @@
3123 out_uint32x2x2_t = vld2_dup_u32 (0);
3124 }
3125
3126-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3127+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3128 /* { dg-final { cleanup-saved-temps } } */
3129Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
3130===================================================================
3131--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2011-06-24 08:13:40.000000000 -0700
3132+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2011-09-16 20:16:00.417564906 -0700
3133@@ -15,5 +15,5 @@
3134 out_uint64x1x2_t = vld2_dup_u64 (0);
3135 }
3136
3137-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3138+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3139 /* { dg-final { cleanup-saved-temps } } */
3140Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
3141===================================================================
3142--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2011-06-24 08:13:40.000000000 -0700
3143+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2011-09-16 20:16:00.417564906 -0700
3144@@ -15,5 +15,5 @@
3145 out_uint8x8x2_t = vld2_dup_u8 (0);
3146 }
3147
3148-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3149+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3150 /* { dg-final { cleanup-saved-temps } } */
3151Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
3152===================================================================
3153--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2011-06-24 08:13:40.000000000 -0700
3154+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2011-09-16 20:16:00.417564906 -0700
3155@@ -16,5 +16,5 @@
3156 out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
3157 }
3158
3159-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3160+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3161 /* { dg-final { cleanup-saved-temps } } */
3162Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
3163===================================================================
3164--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2011-06-24 08:13:40.000000000 -0700
3165+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2011-09-16 20:16:00.417564906 -0700
3166@@ -16,5 +16,5 @@
3167 out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
3168 }
3169
3170-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3171+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3172 /* { dg-final { cleanup-saved-temps } } */
3173Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
3174===================================================================
3175--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2011-06-24 08:13:40.000000000 -0700
3176+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2011-09-16 20:16:00.417564906 -0700
3177@@ -16,5 +16,5 @@
3178 out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
3179 }
3180
3181-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3182+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3183 /* { dg-final { cleanup-saved-temps } } */
3184Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
3185===================================================================
3186--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2011-06-24 08:13:40.000000000 -0700
3187+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2011-09-16 20:16:00.417564906 -0700
3188@@ -16,5 +16,5 @@
3189 out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
3190 }
3191
3192-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3193+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3194 /* { dg-final { cleanup-saved-temps } } */
3195Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
3196===================================================================
3197--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2011-06-24 08:13:40.000000000 -0700
3198+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2011-09-16 20:16:00.417564906 -0700
3199@@ -16,5 +16,5 @@
3200 out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
3201 }
3202
3203-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3204+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3205 /* { dg-final { cleanup-saved-temps } } */
3206Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
3207===================================================================
3208--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2011-06-24 08:13:40.000000000 -0700
3209+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2011-09-16 20:16:00.417564906 -0700
3210@@ -16,5 +16,5 @@
3211 out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
3212 }
3213
3214-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3215+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3216 /* { dg-final { cleanup-saved-temps } } */
3217Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
3218===================================================================
3219--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2011-06-24 08:13:40.000000000 -0700
3220+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2011-09-16 20:16:00.417564906 -0700
3221@@ -16,5 +16,5 @@
3222 out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
3223 }
3224
3225-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3226+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3227 /* { dg-final { cleanup-saved-temps } } */
3228Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
3229===================================================================
3230--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2011-06-24 08:13:40.000000000 -0700
3231+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2011-09-16 20:16:00.417564906 -0700
3232@@ -16,5 +16,5 @@
3233 out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
3234 }
3235
3236-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3237+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3238 /* { dg-final { cleanup-saved-temps } } */
3239Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
3240===================================================================
3241--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2011-06-24 08:13:40.000000000 -0700
3242+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2011-09-16 20:16:00.417564906 -0700
3243@@ -16,5 +16,5 @@
3244 out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
3245 }
3246
3247-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3248+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3249 /* { dg-final { cleanup-saved-temps } } */
3250Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
3251===================================================================
3252--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2011-06-24 08:13:40.000000000 -0700
3253+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2011-09-16 20:16:00.427564921 -0700
3254@@ -15,5 +15,5 @@
3255 out_float32x2x2_t = vld2_f32 (0);
3256 }
3257
3258-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3259+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3260 /* { dg-final { cleanup-saved-temps } } */
3261Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
3262===================================================================
3263--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2011-06-24 08:13:40.000000000 -0700
3264+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2011-09-16 20:16:00.427564921 -0700
3265@@ -15,5 +15,5 @@
3266 out_poly16x4x2_t = vld2_p16 (0);
3267 }
3268
3269-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3270+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3271 /* { dg-final { cleanup-saved-temps } } */
3272Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
3273===================================================================
3274--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2011-06-24 08:13:40.000000000 -0700
3275+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2011-09-16 20:16:00.427564921 -0700
3276@@ -15,5 +15,5 @@
3277 out_poly8x8x2_t = vld2_p8 (0);
3278 }
3279
3280-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3281+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3282 /* { dg-final { cleanup-saved-temps } } */
3283Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
3284===================================================================
3285--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2011-06-24 08:13:40.000000000 -0700
3286+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2011-09-16 20:16:00.427564921 -0700
3287@@ -15,5 +15,5 @@
3288 out_int16x4x2_t = vld2_s16 (0);
3289 }
3290
3291-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3292+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3293 /* { dg-final { cleanup-saved-temps } } */
3294Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
3295===================================================================
3296--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2011-06-24 08:13:40.000000000 -0700
3297+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2011-09-16 20:16:00.427564921 -0700
3298@@ -15,5 +15,5 @@
3299 out_int32x2x2_t = vld2_s32 (0);
3300 }
3301
3302-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3303+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3304 /* { dg-final { cleanup-saved-temps } } */
3305Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
3306===================================================================
3307--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2011-06-24 08:13:40.000000000 -0700
3308+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2011-09-16 20:16:00.427564921 -0700
3309@@ -15,5 +15,5 @@
3310 out_int64x1x2_t = vld2_s64 (0);
3311 }
3312
3313-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3314+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3315 /* { dg-final { cleanup-saved-temps } } */
3316Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
3317===================================================================
3318--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2011-06-24 08:13:40.000000000 -0700
3319+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2011-09-16 20:16:00.437564924 -0700
3320@@ -15,5 +15,5 @@
3321 out_int8x8x2_t = vld2_s8 (0);
3322 }
3323
3324-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3325+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3326 /* { dg-final { cleanup-saved-temps } } */
3327Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
3328===================================================================
3329--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2011-06-24 08:13:40.000000000 -0700
3330+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2011-09-16 20:16:00.437564924 -0700
3331@@ -15,5 +15,5 @@
3332 out_uint16x4x2_t = vld2_u16 (0);
3333 }
3334
3335-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3336+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3337 /* { dg-final { cleanup-saved-temps } } */
3338Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
3339===================================================================
3340--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2011-06-24 08:13:40.000000000 -0700
3341+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2011-09-16 20:16:00.437564924 -0700
3342@@ -15,5 +15,5 @@
3343 out_uint32x2x2_t = vld2_u32 (0);
3344 }
3345
3346-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3347+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3348 /* { dg-final { cleanup-saved-temps } } */
3349Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
3350===================================================================
3351--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2011-06-24 08:13:40.000000000 -0700
3352+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2011-09-16 20:16:00.437564924 -0700
3353@@ -15,5 +15,5 @@
3354 out_uint64x1x2_t = vld2_u64 (0);
3355 }
3356
3357-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3358+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3359 /* { dg-final { cleanup-saved-temps } } */
3360Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
3361===================================================================
3362--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2011-06-24 08:13:40.000000000 -0700
3363+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2011-09-16 20:16:00.437564924 -0700
3364@@ -15,5 +15,5 @@
3365 out_uint8x8x2_t = vld2_u8 (0);
3366 }
3367
3368-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3369+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3370 /* { dg-final { cleanup-saved-temps } } */
3371Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
3372===================================================================
3373--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
3374+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2011-09-16 20:16:00.437564924 -0700
3375@@ -16,5 +16,5 @@
3376 out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
3377 }
3378
3379-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3380+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3381 /* { dg-final { cleanup-saved-temps } } */
3382Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
3383===================================================================
3384--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
3385+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2011-09-16 20:16:00.437564924 -0700
3386@@ -16,5 +16,5 @@
3387 out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
3388 }
3389
3390-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3391+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3392 /* { dg-final { cleanup-saved-temps } } */
3393Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
3394===================================================================
3395--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
3396+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2011-09-16 20:16:00.447564932 -0700
3397@@ -16,5 +16,5 @@
3398 out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
3399 }
3400
3401-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3402+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3403 /* { dg-final { cleanup-saved-temps } } */
3404Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
3405===================================================================
3406--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
3407+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2011-09-16 20:16:00.447564932 -0700
3408@@ -16,5 +16,5 @@
3409 out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
3410 }
3411
3412-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3413+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3414 /* { dg-final { cleanup-saved-temps } } */
3415Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
3416===================================================================
3417--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
3418+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2011-09-16 20:16:00.447564932 -0700
3419@@ -16,5 +16,5 @@
3420 out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
3421 }
3422
3423-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3424+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3425 /* { dg-final { cleanup-saved-temps } } */
3426Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
3427===================================================================
3428--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
3429+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2011-09-16 20:16:00.447564932 -0700
3430@@ -16,5 +16,5 @@
3431 out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
3432 }
3433
3434-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3435+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3436 /* { dg-final { cleanup-saved-temps } } */
3437Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
3438===================================================================
3439--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2011-06-24 08:13:40.000000000 -0700
3440+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2011-09-16 20:16:00.447564932 -0700
3441@@ -15,6 +15,6 @@
3442 out_float32x4x3_t = vld3q_f32 (0);
3443 }
3444
3445-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3446-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3447+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3448+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3449 /* { dg-final { cleanup-saved-temps } } */
3450Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
3451===================================================================
3452--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2011-06-24 08:13:40.000000000 -0700
3453+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2011-09-16 20:16:00.447564932 -0700
3454@@ -15,6 +15,6 @@
3455 out_poly16x8x3_t = vld3q_p16 (0);
3456 }
3457
3458-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3459-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3460+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3461+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3462 /* { dg-final { cleanup-saved-temps } } */
3463Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
3464===================================================================
3465--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2011-06-24 08:13:40.000000000 -0700
3466+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2011-09-16 20:16:00.447564932 -0700
3467@@ -15,6 +15,6 @@
3468 out_poly8x16x3_t = vld3q_p8 (0);
3469 }
3470
3471-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3472-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3473+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3474+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3475 /* { dg-final { cleanup-saved-temps } } */
3476Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
3477===================================================================
3478--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2011-06-24 08:13:40.000000000 -0700
3479+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2011-09-16 20:16:00.447564932 -0700
3480@@ -15,6 +15,6 @@
3481 out_int16x8x3_t = vld3q_s16 (0);
3482 }
3483
3484-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3485-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3486+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3487+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3488 /* { dg-final { cleanup-saved-temps } } */
3489Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
3490===================================================================
3491--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2011-06-24 08:13:40.000000000 -0700
3492+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2011-09-16 20:16:00.447564932 -0700
3493@@ -15,6 +15,6 @@
3494 out_int32x4x3_t = vld3q_s32 (0);
3495 }
3496
3497-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3498-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3499+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3500+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3501 /* { dg-final { cleanup-saved-temps } } */
3502Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
3503===================================================================
3504--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2011-06-24 08:13:40.000000000 -0700
3505+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2011-09-16 20:16:00.447564932 -0700
3506@@ -15,6 +15,6 @@
3507 out_int8x16x3_t = vld3q_s8 (0);
3508 }
3509
3510-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3511-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3512+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3513+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3514 /* { dg-final { cleanup-saved-temps } } */
3515Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
3516===================================================================
3517--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2011-06-24 08:13:40.000000000 -0700
3518+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2011-09-16 20:16:00.447564932 -0700
3519@@ -15,6 +15,6 @@
3520 out_uint16x8x3_t = vld3q_u16 (0);
3521 }
3522
3523-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3524-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3525+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3526+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3527 /* { dg-final { cleanup-saved-temps } } */
3528Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
3529===================================================================
3530--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2011-06-24 08:13:40.000000000 -0700
3531+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2011-09-16 20:16:00.447564932 -0700
3532@@ -15,6 +15,6 @@
3533 out_uint32x4x3_t = vld3q_u32 (0);
3534 }
3535
3536-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3537-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3538+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3539+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3540 /* { dg-final { cleanup-saved-temps } } */
3541Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
3542===================================================================
3543--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2011-06-24 08:13:40.000000000 -0700
3544+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2011-09-16 20:16:00.457564944 -0700
3545@@ -15,6 +15,6 @@
3546 out_uint8x16x3_t = vld3q_u8 (0);
3547 }
3548
3549-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3550-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3551+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3552+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3553 /* { dg-final { cleanup-saved-temps } } */
3554Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
3555===================================================================
3556--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2011-06-24 08:13:40.000000000 -0700
3557+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2011-09-16 20:16:00.457564944 -0700
3558@@ -15,5 +15,5 @@
3559 out_float32x2x3_t = vld3_dup_f32 (0);
3560 }
3561
3562-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3563+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3564 /* { dg-final { cleanup-saved-temps } } */
3565Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
3566===================================================================
3567--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2011-06-24 08:13:40.000000000 -0700
3568+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2011-09-16 20:16:00.457564944 -0700
3569@@ -15,5 +15,5 @@
3570 out_poly16x4x3_t = vld3_dup_p16 (0);
3571 }
3572
3573-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3574+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3575 /* { dg-final { cleanup-saved-temps } } */
3576Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
3577===================================================================
3578--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2011-06-24 08:13:40.000000000 -0700
3579+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2011-09-16 20:16:00.457564944 -0700
3580@@ -15,5 +15,5 @@
3581 out_poly8x8x3_t = vld3_dup_p8 (0);
3582 }
3583
3584-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3585+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3586 /* { dg-final { cleanup-saved-temps } } */
3587Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
3588===================================================================
3589--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2011-06-24 08:13:40.000000000 -0700
3590+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2011-09-16 20:16:00.457564944 -0700
3591@@ -15,5 +15,5 @@
3592 out_int16x4x3_t = vld3_dup_s16 (0);
3593 }
3594
3595-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3596+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3597 /* { dg-final { cleanup-saved-temps } } */
3598Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
3599===================================================================
3600--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2011-06-24 08:13:40.000000000 -0700
3601+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2011-09-16 20:16:00.457564944 -0700
3602@@ -15,5 +15,5 @@
3603 out_int32x2x3_t = vld3_dup_s32 (0);
3604 }
3605
3606-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3607+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3608 /* { dg-final { cleanup-saved-temps } } */
3609Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
3610===================================================================
3611--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2011-06-24 08:13:40.000000000 -0700
3612+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2011-09-16 20:16:00.457564944 -0700
3613@@ -15,5 +15,5 @@
3614 out_int64x1x3_t = vld3_dup_s64 (0);
3615 }
3616
3617-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3618+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3619 /* { dg-final { cleanup-saved-temps } } */
3620Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
3621===================================================================
3622--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2011-06-24 08:13:40.000000000 -0700
3623+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2011-09-16 20:16:00.457564944 -0700
3624@@ -15,5 +15,5 @@
3625 out_int8x8x3_t = vld3_dup_s8 (0);
3626 }
3627
3628-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3629+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3630 /* { dg-final { cleanup-saved-temps } } */
3631Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
3632===================================================================
3633--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2011-06-24 08:13:40.000000000 -0700
3634+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2011-09-16 20:16:00.457564944 -0700
3635@@ -15,5 +15,5 @@
3636 out_uint16x4x3_t = vld3_dup_u16 (0);
3637 }
3638
3639-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3640+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3641 /* { dg-final { cleanup-saved-temps } } */
3642Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
3643===================================================================
3644--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2011-06-24 08:13:40.000000000 -0700
3645+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2011-09-16 20:16:00.457564944 -0700
3646@@ -15,5 +15,5 @@
3647 out_uint32x2x3_t = vld3_dup_u32 (0);
3648 }
3649
3650-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3651+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3652 /* { dg-final { cleanup-saved-temps } } */
3653Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
3654===================================================================
3655--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2011-06-24 08:13:40.000000000 -0700
3656+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2011-09-16 20:16:00.457564944 -0700
3657@@ -15,5 +15,5 @@
3658 out_uint64x1x3_t = vld3_dup_u64 (0);
3659 }
3660
3661-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3662+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3663 /* { dg-final { cleanup-saved-temps } } */
3664Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
3665===================================================================
3666--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2011-06-24 08:13:40.000000000 -0700
3667+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2011-09-16 20:16:00.457564944 -0700
3668@@ -15,5 +15,5 @@
3669 out_uint8x8x3_t = vld3_dup_u8 (0);
3670 }
3671
3672-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3673+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3674 /* { dg-final { cleanup-saved-temps } } */
3675Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
3676===================================================================
3677--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2011-06-24 08:13:40.000000000 -0700
3678+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2011-09-16 20:16:00.457564944 -0700
3679@@ -16,5 +16,5 @@
3680 out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
3681 }
3682
3683-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3684+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3685 /* { dg-final { cleanup-saved-temps } } */
3686Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
3687===================================================================
3688--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2011-06-24 08:13:40.000000000 -0700
3689+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2011-09-16 20:16:00.457564944 -0700
3690@@ -16,5 +16,5 @@
3691 out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
3692 }
3693
3694-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3695+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3696 /* { dg-final { cleanup-saved-temps } } */
3697Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
3698===================================================================
3699--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2011-06-24 08:13:40.000000000 -0700
3700+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2011-09-16 20:16:00.457564944 -0700
3701@@ -16,5 +16,5 @@
3702 out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
3703 }
3704
3705-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3706+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3707 /* { dg-final { cleanup-saved-temps } } */
3708Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
3709===================================================================
3710--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2011-06-24 08:13:40.000000000 -0700
3711+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2011-09-16 20:16:00.457564944 -0700
3712@@ -16,5 +16,5 @@
3713 out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
3714 }
3715
3716-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3717+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3718 /* { dg-final { cleanup-saved-temps } } */
3719Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
3720===================================================================
3721--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2011-06-24 08:13:40.000000000 -0700
3722+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2011-09-16 20:16:00.457564944 -0700
3723@@ -16,5 +16,5 @@
3724 out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
3725 }
3726
3727-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3728+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3729 /* { dg-final { cleanup-saved-temps } } */
3730Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
3731===================================================================
3732--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2011-06-24 08:13:40.000000000 -0700
3733+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2011-09-16 20:16:00.457564944 -0700
3734@@ -16,5 +16,5 @@
3735 out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
3736 }
3737
3738-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3739+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3740 /* { dg-final { cleanup-saved-temps } } */
3741Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
3742===================================================================
3743--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2011-06-24 08:13:40.000000000 -0700
3744+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2011-09-16 20:16:00.457564944 -0700
3745@@ -16,5 +16,5 @@
3746 out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
3747 }
3748
3749-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3750+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3751 /* { dg-final { cleanup-saved-temps } } */
3752Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
3753===================================================================
3754--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2011-06-24 08:13:40.000000000 -0700
3755+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2011-09-16 20:16:00.457564944 -0700
3756@@ -16,5 +16,5 @@
3757 out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
3758 }
3759
3760-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3761+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3762 /* { dg-final { cleanup-saved-temps } } */
3763Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
3764===================================================================
3765--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2011-06-24 08:13:40.000000000 -0700
3766+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2011-09-16 20:16:00.457564944 -0700
3767@@ -16,5 +16,5 @@
3768 out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
3769 }
3770
3771-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3772+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3773 /* { dg-final { cleanup-saved-temps } } */
3774Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
3775===================================================================
3776--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2011-06-24 08:13:40.000000000 -0700
3777+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2011-09-16 20:16:00.457564944 -0700
3778@@ -15,5 +15,5 @@
3779 out_float32x2x3_t = vld3_f32 (0);
3780 }
3781
3782-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3783+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3784 /* { dg-final { cleanup-saved-temps } } */
3785Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
3786===================================================================
3787--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2011-06-24 08:13:40.000000000 -0700
3788+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2011-09-16 20:16:00.457564944 -0700
3789@@ -15,5 +15,5 @@
3790 out_poly16x4x3_t = vld3_p16 (0);
3791 }
3792
3793-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3794+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3795 /* { dg-final { cleanup-saved-temps } } */
3796Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
3797===================================================================
3798--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2011-06-24 08:13:40.000000000 -0700
3799+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2011-09-16 20:16:00.457564944 -0700
3800@@ -15,5 +15,5 @@
3801 out_poly8x8x3_t = vld3_p8 (0);
3802 }
3803
3804-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3805+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3806 /* { dg-final { cleanup-saved-temps } } */
3807Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
3808===================================================================
3809--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2011-06-24 08:13:40.000000000 -0700
3810+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2011-09-16 20:16:00.457564944 -0700
3811@@ -15,5 +15,5 @@
3812 out_int16x4x3_t = vld3_s16 (0);
3813 }
3814
3815-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3816+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3817 /* { dg-final { cleanup-saved-temps } } */
3818Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
3819===================================================================
3820--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2011-06-24 08:13:40.000000000 -0700
3821+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2011-09-16 20:16:00.457564944 -0700
3822@@ -15,5 +15,5 @@
3823 out_int32x2x3_t = vld3_s32 (0);
3824 }
3825
3826-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3827+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3828 /* { dg-final { cleanup-saved-temps } } */
3829Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
3830===================================================================
3831--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2011-06-24 08:13:40.000000000 -0700
3832+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2011-09-16 20:16:00.457564944 -0700
3833@@ -15,5 +15,5 @@
3834 out_int64x1x3_t = vld3_s64 (0);
3835 }
3836
3837-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3838+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3839 /* { dg-final { cleanup-saved-temps } } */
3840Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
3841===================================================================
3842--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2011-06-24 08:13:40.000000000 -0700
3843+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2011-09-16 20:16:00.467564964 -0700
3844@@ -15,5 +15,5 @@
3845 out_int8x8x3_t = vld3_s8 (0);
3846 }
3847
3848-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3849+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3850 /* { dg-final { cleanup-saved-temps } } */
3851Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
3852===================================================================
3853--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2011-06-24 08:13:40.000000000 -0700
3854+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2011-09-16 20:16:00.467564964 -0700
3855@@ -15,5 +15,5 @@
3856 out_uint16x4x3_t = vld3_u16 (0);
3857 }
3858
3859-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3860+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3861 /* { dg-final { cleanup-saved-temps } } */
3862Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
3863===================================================================
3864--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2011-06-24 08:13:40.000000000 -0700
3865+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2011-09-16 20:16:00.467564964 -0700
3866@@ -15,5 +15,5 @@
3867 out_uint32x2x3_t = vld3_u32 (0);
3868 }
3869
3870-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3871+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3872 /* { dg-final { cleanup-saved-temps } } */
3873Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
3874===================================================================
3875--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2011-06-24 08:13:40.000000000 -0700
3876+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2011-09-16 20:16:00.467564964 -0700
3877@@ -15,5 +15,5 @@
3878 out_uint64x1x3_t = vld3_u64 (0);
3879 }
3880
3881-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3882+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3883 /* { dg-final { cleanup-saved-temps } } */
3884Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
3885===================================================================
3886--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2011-06-24 08:13:40.000000000 -0700
3887+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2011-09-16 20:16:00.467564964 -0700
3888@@ -15,5 +15,5 @@
3889 out_uint8x8x3_t = vld3_u8 (0);
3890 }
3891
3892-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3893+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3894 /* { dg-final { cleanup-saved-temps } } */
3895Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
3896===================================================================
3897--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
3898+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2011-09-16 20:16:00.467564964 -0700
3899@@ -16,5 +16,5 @@
3900 out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
3901 }
3902
3903-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3904+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3905 /* { dg-final { cleanup-saved-temps } } */
3906Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
3907===================================================================
3908--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
3909+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2011-09-16 20:16:00.467564964 -0700
3910@@ -16,5 +16,5 @@
3911 out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
3912 }
3913
3914-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3915+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3916 /* { dg-final { cleanup-saved-temps } } */
3917Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
3918===================================================================
3919--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
3920+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2011-09-16 20:16:00.467564964 -0700
3921@@ -16,5 +16,5 @@
3922 out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
3923 }
3924
3925-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3926+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3927 /* { dg-final { cleanup-saved-temps } } */
3928Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
3929===================================================================
3930--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
3931+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2011-09-16 20:16:00.467564964 -0700
3932@@ -16,5 +16,5 @@
3933 out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
3934 }
3935
3936-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3937+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3938 /* { dg-final { cleanup-saved-temps } } */
3939Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
3940===================================================================
3941--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
3942+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2011-09-16 20:16:00.467564964 -0700
3943@@ -16,5 +16,5 @@
3944 out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
3945 }
3946
3947-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3948+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3949 /* { dg-final { cleanup-saved-temps } } */
3950Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
3951===================================================================
3952--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
3953+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2011-09-16 20:16:00.467564964 -0700
3954@@ -16,5 +16,5 @@
3955 out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
3956 }
3957
3958-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3959+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3960 /* { dg-final { cleanup-saved-temps } } */
3961Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
3962===================================================================
3963--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2011-06-24 08:13:40.000000000 -0700
3964+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2011-09-16 20:16:00.467564964 -0700
3965@@ -15,6 +15,6 @@
3966 out_float32x4x4_t = vld4q_f32 (0);
3967 }
3968
3969-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3970-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3971+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3972+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3973 /* { dg-final { cleanup-saved-temps } } */
3974Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
3975===================================================================
3976--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2011-06-24 08:13:40.000000000 -0700
3977+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2011-09-16 20:16:00.467564964 -0700
3978@@ -15,6 +15,6 @@
3979 out_poly16x8x4_t = vld4q_p16 (0);
3980 }
3981
3982-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3983-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3984+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3985+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3986 /* { dg-final { cleanup-saved-temps } } */
3987Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
3988===================================================================
3989--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2011-06-24 08:13:40.000000000 -0700
3990+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2011-09-16 20:16:00.467564964 -0700
3991@@ -15,6 +15,6 @@
3992 out_poly8x16x4_t = vld4q_p8 (0);
3993 }
3994
3995-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3996-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3997+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3998+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3999 /* { dg-final { cleanup-saved-temps } } */
4000Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
4001===================================================================
4002--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2011-06-24 08:13:40.000000000 -0700
4003+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2011-09-16 20:16:00.477564991 -0700
4004@@ -15,6 +15,6 @@
4005 out_int16x8x4_t = vld4q_s16 (0);
4006 }
4007
4008-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4009-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4010+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4011+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4012 /* { dg-final { cleanup-saved-temps } } */
4013Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
4014===================================================================
4015--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2011-06-24 08:13:40.000000000 -0700
4016+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2011-09-16 20:16:00.477564991 -0700
4017@@ -15,6 +15,6 @@
4018 out_int32x4x4_t = vld4q_s32 (0);
4019 }
4020
4021-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4022-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4023+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4024+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4025 /* { dg-final { cleanup-saved-temps } } */
4026Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
4027===================================================================
4028--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2011-06-24 08:13:40.000000000 -0700
4029+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2011-09-16 20:16:00.477564991 -0700
4030@@ -15,6 +15,6 @@
4031 out_int8x16x4_t = vld4q_s8 (0);
4032 }
4033
4034-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4035-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4036+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4037+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4038 /* { dg-final { cleanup-saved-temps } } */
4039Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
4040===================================================================
4041--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2011-06-24 08:13:40.000000000 -0700
4042+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2011-09-16 20:16:00.477564991 -0700
4043@@ -15,6 +15,6 @@
4044 out_uint16x8x4_t = vld4q_u16 (0);
4045 }
4046
4047-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4048-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4049+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4050+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4051 /* { dg-final { cleanup-saved-temps } } */
4052Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
4053===================================================================
4054--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2011-06-24 08:13:40.000000000 -0700
4055+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2011-09-16 20:16:00.477564991 -0700
4056@@ -15,6 +15,6 @@
4057 out_uint32x4x4_t = vld4q_u32 (0);
4058 }
4059
4060-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4061-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4062+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4063+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4064 /* { dg-final { cleanup-saved-temps } } */
4065Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
4066===================================================================
4067--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2011-06-24 08:13:40.000000000 -0700
4068+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2011-09-16 20:16:00.477564991 -0700
4069@@ -15,6 +15,6 @@
4070 out_uint8x16x4_t = vld4q_u8 (0);
4071 }
4072
4073-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4074-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4075+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4076+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4077 /* { dg-final { cleanup-saved-temps } } */
4078Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
4079===================================================================
4080--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2011-06-24 08:13:40.000000000 -0700
4081+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2011-09-16 20:16:00.477564991 -0700
4082@@ -15,5 +15,5 @@
4083 out_float32x2x4_t = vld4_dup_f32 (0);
4084 }
4085
4086-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4087+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4088 /* { dg-final { cleanup-saved-temps } } */
4089Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
4090===================================================================
4091--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2011-06-24 08:13:40.000000000 -0700
4092+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2011-09-16 20:16:00.477564991 -0700
4093@@ -15,5 +15,5 @@
4094 out_poly16x4x4_t = vld4_dup_p16 (0);
4095 }
4096
4097-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4098+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4099 /* { dg-final { cleanup-saved-temps } } */
4100Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
4101===================================================================
4102--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2011-06-24 08:13:40.000000000 -0700
4103+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2011-09-16 20:16:00.477564991 -0700
4104@@ -15,5 +15,5 @@
4105 out_poly8x8x4_t = vld4_dup_p8 (0);
4106 }
4107
4108-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4109+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4110 /* { dg-final { cleanup-saved-temps } } */
4111Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
4112===================================================================
4113--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2011-06-24 08:13:40.000000000 -0700
4114+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2011-09-16 20:16:00.477564991 -0700
4115@@ -15,5 +15,5 @@
4116 out_int16x4x4_t = vld4_dup_s16 (0);
4117 }
4118
4119-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4120+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4121 /* { dg-final { cleanup-saved-temps } } */
4122Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
4123===================================================================
4124--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2011-06-24 08:13:40.000000000 -0700
4125+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2011-09-16 20:16:00.477564991 -0700
4126@@ -15,5 +15,5 @@
4127 out_int32x2x4_t = vld4_dup_s32 (0);
4128 }
4129
4130-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4131+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4132 /* { dg-final { cleanup-saved-temps } } */
4133Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
4134===================================================================
4135--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2011-06-24 08:13:40.000000000 -0700
4136+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2011-09-16 20:16:00.487565006 -0700
4137@@ -15,5 +15,5 @@
4138 out_int64x1x4_t = vld4_dup_s64 (0);
4139 }
4140
4141-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4142+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4143 /* { dg-final { cleanup-saved-temps } } */
4144Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
4145===================================================================
4146--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2011-06-24 08:13:40.000000000 -0700
4147+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2011-09-16 20:16:00.487565006 -0700
4148@@ -15,5 +15,5 @@
4149 out_int8x8x4_t = vld4_dup_s8 (0);
4150 }
4151
4152-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4153+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4154 /* { dg-final { cleanup-saved-temps } } */
4155Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
4156===================================================================
4157--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2011-06-24 08:13:40.000000000 -0700
4158+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2011-09-16 20:16:00.487565006 -0700
4159@@ -15,5 +15,5 @@
4160 out_uint16x4x4_t = vld4_dup_u16 (0);
4161 }
4162
4163-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4164+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4165 /* { dg-final { cleanup-saved-temps } } */
4166Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
4167===================================================================
4168--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2011-06-24 08:13:40.000000000 -0700
4169+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2011-09-16 20:16:00.487565006 -0700
4170@@ -15,5 +15,5 @@
4171 out_uint32x2x4_t = vld4_dup_u32 (0);
4172 }
4173
4174-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4175+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4176 /* { dg-final { cleanup-saved-temps } } */
4177Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
4178===================================================================
4179--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2011-06-24 08:13:40.000000000 -0700
4180+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2011-09-16 20:16:00.487565006 -0700
4181@@ -15,5 +15,5 @@
4182 out_uint64x1x4_t = vld4_dup_u64 (0);
4183 }
4184
4185-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4186+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4187 /* { dg-final { cleanup-saved-temps } } */
4188Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
4189===================================================================
4190--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2011-06-24 08:13:40.000000000 -0700
4191+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2011-09-16 20:16:00.487565006 -0700
4192@@ -15,5 +15,5 @@
4193 out_uint8x8x4_t = vld4_dup_u8 (0);
4194 }
4195
4196-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4197+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4198 /* { dg-final { cleanup-saved-temps } } */
4199Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
4200===================================================================
4201--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2011-06-24 08:13:40.000000000 -0700
4202+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2011-09-16 20:16:00.487565006 -0700
4203@@ -16,5 +16,5 @@
4204 out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
4205 }
4206
4207-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4208+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4209 /* { dg-final { cleanup-saved-temps } } */
4210Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
4211===================================================================
4212--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2011-06-24 08:13:40.000000000 -0700
4213+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2011-09-16 20:16:00.487565006 -0700
4214@@ -16,5 +16,5 @@
4215 out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
4216 }
4217
4218-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4219+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4220 /* { dg-final { cleanup-saved-temps } } */
4221Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
4222===================================================================
4223--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2011-06-24 08:13:40.000000000 -0700
4224+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2011-09-16 20:16:00.487565006 -0700
4225@@ -16,5 +16,5 @@
4226 out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
4227 }
4228
4229-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4230+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4231 /* { dg-final { cleanup-saved-temps } } */
4232Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
4233===================================================================
4234--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2011-06-24 08:13:40.000000000 -0700
4235+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2011-09-16 20:16:00.497565009 -0700
4236@@ -16,5 +16,5 @@
4237 out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
4238 }
4239
4240-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4241+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4242 /* { dg-final { cleanup-saved-temps } } */
4243Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
4244===================================================================
4245--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2011-06-24 08:13:40.000000000 -0700
4246+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2011-09-16 20:16:00.497565009 -0700
4247@@ -16,5 +16,5 @@
4248 out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
4249 }
4250
4251-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4252+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4253 /* { dg-final { cleanup-saved-temps } } */
4254Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
4255===================================================================
4256--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2011-06-24 08:13:40.000000000 -0700
4257+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2011-09-16 20:16:00.497565009 -0700
4258@@ -16,5 +16,5 @@
4259 out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
4260 }
4261
4262-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4263+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4264 /* { dg-final { cleanup-saved-temps } } */
4265Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
4266===================================================================
4267--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2011-06-24 08:13:40.000000000 -0700
4268+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2011-09-16 20:16:00.497565009 -0700
4269@@ -16,5 +16,5 @@
4270 out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
4271 }
4272
4273-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4274+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4275 /* { dg-final { cleanup-saved-temps } } */
4276Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
4277===================================================================
4278--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2011-06-24 08:13:40.000000000 -0700
4279+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2011-09-16 20:16:00.497565009 -0700
4280@@ -16,5 +16,5 @@
4281 out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
4282 }
4283
4284-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4285+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4286 /* { dg-final { cleanup-saved-temps } } */
4287Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
4288===================================================================
4289--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2011-06-24 08:13:40.000000000 -0700
4290+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2011-09-16 20:16:00.497565009 -0700
4291@@ -16,5 +16,5 @@
4292 out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
4293 }
4294
4295-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4296+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4297 /* { dg-final { cleanup-saved-temps } } */
4298Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
4299===================================================================
4300--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2011-06-24 08:13:40.000000000 -0700
4301+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2011-09-16 20:16:00.497565009 -0700
4302@@ -15,5 +15,5 @@
4303 out_float32x2x4_t = vld4_f32 (0);
4304 }
4305
4306-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4307+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4308 /* { dg-final { cleanup-saved-temps } } */
4309Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
4310===================================================================
4311--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2011-06-24 08:13:40.000000000 -0700
4312+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2011-09-16 20:16:00.497565009 -0700
4313@@ -15,5 +15,5 @@
4314 out_poly16x4x4_t = vld4_p16 (0);
4315 }
4316
4317-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4318+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4319 /* { dg-final { cleanup-saved-temps } } */
4320Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
4321===================================================================
4322--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2011-06-24 08:13:40.000000000 -0700
4323+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2011-09-16 20:16:00.497565009 -0700
4324@@ -15,5 +15,5 @@
4325 out_poly8x8x4_t = vld4_p8 (0);
4326 }
4327
4328-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4329+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4330 /* { dg-final { cleanup-saved-temps } } */
4331Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
4332===================================================================
4333--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2011-06-24 08:13:40.000000000 -0700
4334+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2011-09-16 20:16:00.497565009 -0700
4335@@ -15,5 +15,5 @@
4336 out_int16x4x4_t = vld4_s16 (0);
4337 }
4338
4339-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4340+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4341 /* { dg-final { cleanup-saved-temps } } */
4342Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
4343===================================================================
4344--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2011-06-24 08:13:40.000000000 -0700
4345+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2011-09-16 20:16:00.497565009 -0700
4346@@ -15,5 +15,5 @@
4347 out_int32x2x4_t = vld4_s32 (0);
4348 }
4349
4350-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4351+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4352 /* { dg-final { cleanup-saved-temps } } */
4353Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
4354===================================================================
4355--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2011-06-24 08:13:40.000000000 -0700
4356+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2011-09-16 20:16:00.497565009 -0700
4357@@ -15,5 +15,5 @@
4358 out_int64x1x4_t = vld4_s64 (0);
4359 }
4360
4361-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4362+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4363 /* { dg-final { cleanup-saved-temps } } */
4364Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
4365===================================================================
4366--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2011-06-24 08:13:40.000000000 -0700
4367+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2011-09-16 20:16:00.497565009 -0700
4368@@ -15,5 +15,5 @@
4369 out_int8x8x4_t = vld4_s8 (0);
4370 }
4371
4372-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4373+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4374 /* { dg-final { cleanup-saved-temps } } */
4375Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
4376===================================================================
4377--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2011-06-24 08:13:40.000000000 -0700
4378+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2011-09-16 20:16:00.497565009 -0700
4379@@ -15,5 +15,5 @@
4380 out_uint16x4x4_t = vld4_u16 (0);
4381 }
4382
4383-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4384+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4385 /* { dg-final { cleanup-saved-temps } } */
4386Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
4387===================================================================
4388--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2011-06-24 08:13:40.000000000 -0700
4389+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2011-09-16 20:16:00.507565013 -0700
4390@@ -15,5 +15,5 @@
4391 out_uint32x2x4_t = vld4_u32 (0);
4392 }
4393
4394-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4395+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4396 /* { dg-final { cleanup-saved-temps } } */
4397Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
4398===================================================================
4399--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2011-06-24 08:13:40.000000000 -0700
4400+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2011-09-16 20:16:00.507565013 -0700
4401@@ -15,5 +15,5 @@
4402 out_uint64x1x4_t = vld4_u64 (0);
4403 }
4404
4405-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4406+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4407 /* { dg-final { cleanup-saved-temps } } */
4408Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
4409===================================================================
4410--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2011-06-24 08:13:40.000000000 -0700
4411+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2011-09-16 20:16:00.507565013 -0700
4412@@ -15,5 +15,5 @@
4413 out_uint8x8x4_t = vld4_u8 (0);
4414 }
4415
4416-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4417+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4418 /* { dg-final { cleanup-saved-temps } } */
4419Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
4420===================================================================
4421--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
4422+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2011-09-16 20:16:00.507565013 -0700
4423@@ -16,5 +16,5 @@
4424 vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
4425 }
4426
4427-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4428+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4429 /* { dg-final { cleanup-saved-temps } } */
4430Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
4431===================================================================
4432--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
4433+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2011-09-16 20:16:00.507565013 -0700
4434@@ -16,5 +16,5 @@
4435 vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
4436 }
4437
4438-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4439+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4440 /* { dg-final { cleanup-saved-temps } } */
4441Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
4442===================================================================
4443--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2011-06-24 08:13:40.000000000 -0700
4444+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2011-09-16 20:16:00.507565013 -0700
4445@@ -16,5 +16,5 @@
4446 vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
4447 }
4448
4449-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4450+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4451 /* { dg-final { cleanup-saved-temps } } */
4452Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
4453===================================================================
4454--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
4455+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2011-09-16 20:16:00.507565013 -0700
4456@@ -16,5 +16,5 @@
4457 vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
4458 }
4459
4460-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4461+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4462 /* { dg-final { cleanup-saved-temps } } */
4463Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
4464===================================================================
4465--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
4466+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2011-09-16 20:16:00.507565013 -0700
4467@@ -16,5 +16,5 @@
4468 vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
4469 }
4470
4471-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4472+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4473 /* { dg-final { cleanup-saved-temps } } */
4474Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
4475===================================================================
4476--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2011-06-24 08:13:40.000000000 -0700
4477+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2011-09-16 20:16:00.507565013 -0700
4478@@ -16,5 +16,5 @@
4479 vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
4480 }
4481
4482-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4483+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4484 /* { dg-final { cleanup-saved-temps } } */
4485Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
4486===================================================================
4487--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2011-06-24 08:13:40.000000000 -0700
4488+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2011-09-16 20:16:00.507565013 -0700
4489@@ -16,5 +16,5 @@
4490 vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
4491 }
4492
4493-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4494+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4495 /* { dg-final { cleanup-saved-temps } } */
4496Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
4497===================================================================
4498--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
4499+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2011-09-16 20:16:00.507565013 -0700
4500@@ -16,5 +16,5 @@
4501 vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
4502 }
4503
4504-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4505+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4506 /* { dg-final { cleanup-saved-temps } } */
4507Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
4508===================================================================
4509--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
4510+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2011-09-16 20:16:00.507565013 -0700
4511@@ -16,5 +16,5 @@
4512 vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
4513 }
4514
4515-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4516+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4517 /* { dg-final { cleanup-saved-temps } } */
4518Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
4519===================================================================
4520--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2011-06-24 08:13:40.000000000 -0700
4521+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2011-09-16 20:16:00.507565013 -0700
4522@@ -16,5 +16,5 @@
4523 vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
4524 }
4525
4526-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4527+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4528 /* { dg-final { cleanup-saved-temps } } */
4529Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
4530===================================================================
4531--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2011-06-24 08:13:40.000000000 -0700
4532+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2011-09-16 20:16:00.507565013 -0700
4533@@ -16,5 +16,5 @@
4534 vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
4535 }
4536
4537-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4538+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4539 /* { dg-final { cleanup-saved-temps } } */
4540Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
4541===================================================================
4542--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2011-06-24 08:13:40.000000000 -0700
4543+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2011-09-16 20:16:00.507565013 -0700
4544@@ -16,5 +16,5 @@
4545 vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
4546 }
4547
4548-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4549+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4550 /* { dg-final { cleanup-saved-temps } } */
4551Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
4552===================================================================
4553--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2011-06-24 08:13:40.000000000 -0700
4554+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2011-09-16 20:16:00.507565013 -0700
4555@@ -16,5 +16,5 @@
4556 vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
4557 }
4558
4559-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4560+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4561 /* { dg-final { cleanup-saved-temps } } */
4562Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
4563===================================================================
4564--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2011-06-24 08:13:40.000000000 -0700
4565+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2011-09-16 20:16:00.507565013 -0700
4566@@ -16,5 +16,5 @@
4567 vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
4568 }
4569
4570-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4571+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4572 /* { dg-final { cleanup-saved-temps } } */
4573Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
4574===================================================================
4575--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2011-06-24 08:13:40.000000000 -0700
4576+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2011-09-16 20:16:00.507565013 -0700
4577@@ -16,5 +16,5 @@
4578 vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
4579 }
4580
4581-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4582+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4583 /* { dg-final { cleanup-saved-temps } } */
4584Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
4585===================================================================
4586--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2011-06-24 08:13:40.000000000 -0700
4587+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2011-09-16 20:16:00.517565031 -0700
4588@@ -16,5 +16,5 @@
4589 vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
4590 }
4591
4592-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4593+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4594 /* { dg-final { cleanup-saved-temps } } */
4595Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
4596===================================================================
4597--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2011-06-24 08:13:40.000000000 -0700
4598+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2011-09-16 20:16:00.517565031 -0700
4599@@ -16,5 +16,5 @@
4600 vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
4601 }
4602
4603-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4604+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4605 /* { dg-final { cleanup-saved-temps } } */
4606Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
4607===================================================================
4608--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2011-06-24 08:13:40.000000000 -0700
4609+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2011-09-16 20:16:00.517565031 -0700
4610@@ -16,5 +16,5 @@
4611 vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
4612 }
4613
4614-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4615+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4616 /* { dg-final { cleanup-saved-temps } } */
4617Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
4618===================================================================
4619--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2011-06-24 08:13:40.000000000 -0700
4620+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2011-09-16 20:16:00.517565031 -0700
4621@@ -16,5 +16,5 @@
4622 vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
4623 }
4624
4625-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4626+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4627 /* { dg-final { cleanup-saved-temps } } */
4628Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
4629===================================================================
4630--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2011-06-24 08:13:40.000000000 -0700
4631+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2011-09-16 20:16:00.517565031 -0700
4632@@ -16,5 +16,5 @@
4633 vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
4634 }
4635
4636-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4637+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4638 /* { dg-final { cleanup-saved-temps } } */
4639Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
4640===================================================================
4641--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2011-06-24 08:13:40.000000000 -0700
4642+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2011-09-16 20:16:00.517565031 -0700
4643@@ -16,5 +16,5 @@
4644 vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
4645 }
4646
4647-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4648+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4649 /* { dg-final { cleanup-saved-temps } } */
4650Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
4651===================================================================
4652--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2011-06-24 08:13:40.000000000 -0700
4653+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2011-09-16 20:16:00.517565031 -0700
4654@@ -16,5 +16,5 @@
4655 vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
4656 }
4657
4658-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4659+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4660 /* { dg-final { cleanup-saved-temps } } */
4661Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
4662===================================================================
4663--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2011-06-24 08:13:40.000000000 -0700
4664+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2011-09-16 20:16:00.517565031 -0700
4665@@ -16,5 +16,5 @@
4666 vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
4667 }
4668
4669-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4670+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4671 /* { dg-final { cleanup-saved-temps } } */
4672Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
4673===================================================================
4674--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2011-06-24 08:13:40.000000000 -0700
4675+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2011-09-16 20:16:00.517565031 -0700
4676@@ -16,5 +16,5 @@
4677 vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
4678 }
4679
4680-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4681+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4682 /* { dg-final { cleanup-saved-temps } } */
4683Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
4684===================================================================
4685--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2011-06-24 08:13:40.000000000 -0700
4686+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2011-09-16 20:16:00.517565031 -0700
4687@@ -16,5 +16,5 @@
4688 vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
4689 }
4690
4691-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4692+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4693 /* { dg-final { cleanup-saved-temps } } */
4694Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
4695===================================================================
4696--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2011-06-24 08:13:40.000000000 -0700
4697+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2011-09-16 20:16:00.517565031 -0700
4698@@ -16,5 +16,5 @@
4699 vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
4700 }
4701
4702-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4703+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4704 /* { dg-final { cleanup-saved-temps } } */
4705Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
4706===================================================================
4707--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2011-06-24 08:13:40.000000000 -0700
4708+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2011-09-16 20:16:00.517565031 -0700
4709@@ -16,5 +16,5 @@
4710 vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
4711 }
4712
4713-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4714+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4715 /* { dg-final { cleanup-saved-temps } } */
4716Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
4717===================================================================
4718--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2011-06-24 08:13:40.000000000 -0700
4719+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2011-09-16 20:16:00.517565031 -0700
4720@@ -16,5 +16,5 @@
4721 vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
4722 }
4723
4724-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4725+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4726 /* { dg-final { cleanup-saved-temps } } */
4727Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
4728===================================================================
4729--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2011-06-24 08:13:40.000000000 -0700
4730+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2011-09-16 20:16:00.517565031 -0700
4731@@ -16,5 +16,5 @@
4732 vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
4733 }
4734
4735-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4736+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4737 /* { dg-final { cleanup-saved-temps } } */
4738Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
4739===================================================================
4740--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2011-06-24 08:13:40.000000000 -0700
4741+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2011-09-16 20:16:00.517565031 -0700
4742@@ -16,5 +16,5 @@
4743 vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
4744 }
4745
4746-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4747+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4748 /* { dg-final { cleanup-saved-temps } } */
4749Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
4750===================================================================
4751--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2011-06-24 08:13:40.000000000 -0700
4752+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2011-09-16 20:16:00.517565031 -0700
4753@@ -16,5 +16,5 @@
4754 vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
4755 }
4756
4757-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4758+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4759 /* { dg-final { cleanup-saved-temps } } */
4760Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
4761===================================================================
4762--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2011-06-24 08:13:40.000000000 -0700
4763+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2011-09-16 20:16:00.517565031 -0700
4764@@ -16,5 +16,5 @@
4765 vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
4766 }
4767
4768-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4769+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4770 /* { dg-final { cleanup-saved-temps } } */
4771Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
4772===================================================================
4773--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2011-06-24 08:13:40.000000000 -0700
4774+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2011-09-16 20:16:00.517565031 -0700
4775@@ -16,5 +16,5 @@
4776 vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
4777 }
4778
4779-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4780+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4781 /* { dg-final { cleanup-saved-temps } } */
4782Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
4783===================================================================
4784--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2011-06-24 08:13:40.000000000 -0700
4785+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2011-09-16 20:16:00.517565031 -0700
4786@@ -16,5 +16,5 @@
4787 vst1_f32 (arg0_float32_t, arg1_float32x2_t);
4788 }
4789
4790-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4791+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4792 /* { dg-final { cleanup-saved-temps } } */
4793Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
4794===================================================================
4795--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2011-06-24 08:13:40.000000000 -0700
4796+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2011-09-16 20:16:00.517565031 -0700
4797@@ -16,5 +16,5 @@
4798 vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
4799 }
4800
4801-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4802+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4803 /* { dg-final { cleanup-saved-temps } } */
4804Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
4805===================================================================
4806--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2011-06-24 08:13:40.000000000 -0700
4807+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2011-09-16 20:16:00.517565031 -0700
4808@@ -16,5 +16,5 @@
4809 vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
4810 }
4811
4812-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4813+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4814 /* { dg-final { cleanup-saved-temps } } */
4815Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
4816===================================================================
4817--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2011-06-24 08:13:40.000000000 -0700
4818+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2011-09-16 20:16:00.527565060 -0700
4819@@ -16,5 +16,5 @@
4820 vst1_s16 (arg0_int16_t, arg1_int16x4_t);
4821 }
4822
4823-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4824+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4825 /* { dg-final { cleanup-saved-temps } } */
4826Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
4827===================================================================
4828--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2011-06-24 08:13:40.000000000 -0700
4829+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2011-09-16 20:16:00.527565060 -0700
4830@@ -16,5 +16,5 @@
4831 vst1_s32 (arg0_int32_t, arg1_int32x2_t);
4832 }
4833
4834-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4835+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4836 /* { dg-final { cleanup-saved-temps } } */
4837Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
4838===================================================================
4839--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2011-06-24 08:13:40.000000000 -0700
4840+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2011-09-16 20:16:00.527565060 -0700
4841@@ -16,5 +16,5 @@
4842 vst1_s64 (arg0_int64_t, arg1_int64x1_t);
4843 }
4844
4845-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4846+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4847 /* { dg-final { cleanup-saved-temps } } */
4848Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
4849===================================================================
4850--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2011-06-24 08:13:40.000000000 -0700
4851+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2011-09-16 20:16:00.527565060 -0700
4852@@ -16,5 +16,5 @@
4853 vst1_s8 (arg0_int8_t, arg1_int8x8_t);
4854 }
4855
4856-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4857+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4858 /* { dg-final { cleanup-saved-temps } } */
4859Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
4860===================================================================
4861--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2011-06-24 08:13:40.000000000 -0700
4862+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2011-09-16 20:16:00.527565060 -0700
4863@@ -16,5 +16,5 @@
4864 vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
4865 }
4866
4867-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4868+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4869 /* { dg-final { cleanup-saved-temps } } */
4870Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
4871===================================================================
4872--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2011-06-24 08:13:40.000000000 -0700
4873+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2011-09-16 20:16:00.527565060 -0700
4874@@ -16,5 +16,5 @@
4875 vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
4876 }
4877
4878-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4879+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4880 /* { dg-final { cleanup-saved-temps } } */
4881Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
4882===================================================================
4883--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2011-06-24 08:13:40.000000000 -0700
4884+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2011-09-16 20:16:00.527565060 -0700
4885@@ -16,5 +16,5 @@
4886 vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
4887 }
4888
4889-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4890+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4891 /* { dg-final { cleanup-saved-temps } } */
4892Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
4893===================================================================
4894--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2011-06-24 08:13:40.000000000 -0700
4895+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2011-09-16 20:16:00.527565060 -0700
4896@@ -16,5 +16,5 @@
4897 vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
4898 }
4899
4900-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4901+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4902 /* { dg-final { cleanup-saved-temps } } */
4903Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
4904===================================================================
4905--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
4906+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2011-09-16 20:16:00.527565060 -0700
4907@@ -16,5 +16,5 @@
4908 vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
4909 }
4910
4911-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4912+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4913 /* { dg-final { cleanup-saved-temps } } */
4914Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
4915===================================================================
4916--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
4917+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2011-09-16 20:16:00.527565060 -0700
4918@@ -16,5 +16,5 @@
4919 vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
4920 }
4921
4922-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4923+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4924 /* { dg-final { cleanup-saved-temps } } */
4925Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
4926===================================================================
4927--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
4928+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2011-09-16 20:16:00.527565060 -0700
4929@@ -16,5 +16,5 @@
4930 vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
4931 }
4932
4933-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4934+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4935 /* { dg-final { cleanup-saved-temps } } */
4936Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
4937===================================================================
4938--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
4939+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2011-09-16 20:16:00.527565060 -0700
4940@@ -16,5 +16,5 @@
4941 vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
4942 }
4943
4944-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4945+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4946 /* { dg-final { cleanup-saved-temps } } */
4947Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
4948===================================================================
4949--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
4950+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2011-09-16 20:16:00.527565060 -0700
4951@@ -16,5 +16,5 @@
4952 vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
4953 }
4954
4955-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4956+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4957 /* { dg-final { cleanup-saved-temps } } */
4958Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
4959===================================================================
4960--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
4961+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2011-09-16 20:16:00.527565060 -0700
4962@@ -16,5 +16,5 @@
4963 vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
4964 }
4965
4966-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4967+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4968 /* { dg-final { cleanup-saved-temps } } */
4969Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
4970===================================================================
4971--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2011-06-24 08:13:40.000000000 -0700
4972+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2011-09-16 20:16:00.527565060 -0700
4973@@ -16,6 +16,6 @@
4974 vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
4975 }
4976
4977-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4978-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4979+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4980+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4981 /* { dg-final { cleanup-saved-temps } } */
4982Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
4983===================================================================
4984--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2011-06-24 08:13:40.000000000 -0700
4985+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2011-09-16 20:16:00.527565060 -0700
4986@@ -16,6 +16,6 @@
4987 vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
4988 }
4989
4990-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4991-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4992+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4993+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4994 /* { dg-final { cleanup-saved-temps } } */
4995Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
4996===================================================================
4997--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2011-06-24 08:13:40.000000000 -0700
4998+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2011-09-16 20:16:00.527565060 -0700
4999@@ -16,6 +16,6 @@
5000 vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
5001 }
5002
5003-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5004-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5005+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5006+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5007 /* { dg-final { cleanup-saved-temps } } */
5008Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
5009===================================================================
5010--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2011-06-24 08:13:40.000000000 -0700
5011+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2011-09-16 20:16:00.527565060 -0700
5012@@ -16,6 +16,6 @@
5013 vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
5014 }
5015
5016-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5017-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5018+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5019+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5020 /* { dg-final { cleanup-saved-temps } } */
5021Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
5022===================================================================
5023--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2011-06-24 08:13:40.000000000 -0700
5024+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2011-09-16 20:16:00.527565060 -0700
5025@@ -16,6 +16,6 @@
5026 vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
5027 }
5028
5029-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5030-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5031+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5032+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5033 /* { dg-final { cleanup-saved-temps } } */
5034Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
5035===================================================================
5036--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2011-06-24 08:13:40.000000000 -0700
5037+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2011-09-16 20:16:00.527565060 -0700
5038@@ -16,6 +16,6 @@
5039 vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
5040 }
5041
5042-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5043-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5044+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5045+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5046 /* { dg-final { cleanup-saved-temps } } */
5047Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
5048===================================================================
5049--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2011-06-24 08:13:40.000000000 -0700
5050+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2011-09-16 20:16:00.527565060 -0700
5051@@ -16,6 +16,6 @@
5052 vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
5053 }
5054
5055-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5056-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5057+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5058+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5059 /* { dg-final { cleanup-saved-temps } } */
5060Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
5061===================================================================
5062--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2011-06-24 08:13:40.000000000 -0700
5063+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2011-09-16 20:16:00.527565060 -0700
5064@@ -16,6 +16,6 @@
5065 vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
5066 }
5067
5068-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5069-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5070+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5071+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5072 /* { dg-final { cleanup-saved-temps } } */
5073Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
5074===================================================================
5075--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2011-06-24 08:13:40.000000000 -0700
5076+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2011-09-16 20:16:00.537565077 -0700
5077@@ -16,6 +16,6 @@
5078 vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
5079 }
5080
5081-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5082-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5083+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5084+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5085 /* { dg-final { cleanup-saved-temps } } */
5086Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
5087===================================================================
5088--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2011-06-24 08:13:40.000000000 -0700
5089+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2011-09-16 20:16:00.537565077 -0700
5090@@ -16,5 +16,5 @@
5091 vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
5092 }
5093
5094-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5095+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5096 /* { dg-final { cleanup-saved-temps } } */
5097Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
5098===================================================================
5099--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2011-06-24 08:13:40.000000000 -0700
5100+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2011-09-16 20:16:00.537565077 -0700
5101@@ -16,5 +16,5 @@
5102 vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
5103 }
5104
5105-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5106+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5107 /* { dg-final { cleanup-saved-temps } } */
5108Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
5109===================================================================
5110--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2011-06-24 08:13:40.000000000 -0700
5111+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2011-09-16 20:16:00.537565077 -0700
5112@@ -16,5 +16,5 @@
5113 vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
5114 }
5115
5116-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5117+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5118 /* { dg-final { cleanup-saved-temps } } */
5119Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
5120===================================================================
5121--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2011-06-24 08:13:40.000000000 -0700
5122+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2011-09-16 20:16:00.537565077 -0700
5123@@ -16,5 +16,5 @@
5124 vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
5125 }
5126
5127-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5128+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5129 /* { dg-final { cleanup-saved-temps } } */
5130Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
5131===================================================================
5132--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2011-06-24 08:13:40.000000000 -0700
5133+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2011-09-16 20:16:00.537565077 -0700
5134@@ -16,5 +16,5 @@
5135 vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
5136 }
5137
5138-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5139+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5140 /* { dg-final { cleanup-saved-temps } } */
5141Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
5142===================================================================
5143--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2011-06-24 08:13:40.000000000 -0700
5144+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2011-09-16 20:16:00.537565077 -0700
5145@@ -16,5 +16,5 @@
5146 vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
5147 }
5148
5149-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5150+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5151 /* { dg-final { cleanup-saved-temps } } */
5152Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
5153===================================================================
5154--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2011-06-24 08:13:40.000000000 -0700
5155+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2011-09-16 20:16:00.537565077 -0700
5156@@ -16,5 +16,5 @@
5157 vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
5158 }
5159
5160-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5161+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5162 /* { dg-final { cleanup-saved-temps } } */
5163Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
5164===================================================================
5165--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2011-06-24 08:13:40.000000000 -0700
5166+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2011-09-16 20:16:00.537565077 -0700
5167@@ -16,5 +16,5 @@
5168 vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
5169 }
5170
5171-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5172+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5173 /* { dg-final { cleanup-saved-temps } } */
5174Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
5175===================================================================
5176--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2011-06-24 08:13:40.000000000 -0700
5177+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2011-09-16 20:16:00.537565077 -0700
5178@@ -16,5 +16,5 @@
5179 vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
5180 }
5181
5182-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5183+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5184 /* { dg-final { cleanup-saved-temps } } */
5185Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
5186===================================================================
5187--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2011-06-24 08:13:40.000000000 -0700
5188+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2011-09-16 20:16:00.537565077 -0700
5189@@ -16,5 +16,5 @@
5190 vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
5191 }
5192
5193-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5194+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5195 /* { dg-final { cleanup-saved-temps } } */
5196Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
5197===================================================================
5198--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2011-06-24 08:13:40.000000000 -0700
5199+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2011-09-16 20:16:00.537565077 -0700
5200@@ -16,5 +16,5 @@
5201 vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
5202 }
5203
5204-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5205+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5206 /* { dg-final { cleanup-saved-temps } } */
5207Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
5208===================================================================
5209--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2011-06-24 08:13:40.000000000 -0700
5210+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2011-09-16 20:16:00.547565082 -0700
5211@@ -16,5 +16,5 @@
5212 vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
5213 }
5214
5215-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5216+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5217 /* { dg-final { cleanup-saved-temps } } */
5218Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
5219===================================================================
5220--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2011-06-24 08:13:40.000000000 -0700
5221+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2011-09-16 20:16:00.547565082 -0700
5222@@ -16,5 +16,5 @@
5223 vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
5224 }
5225
5226-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5227+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5228 /* { dg-final { cleanup-saved-temps } } */
5229Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
5230===================================================================
5231--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2011-06-24 08:13:40.000000000 -0700
5232+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2011-09-16 20:16:00.547565082 -0700
5233@@ -16,5 +16,5 @@
5234 vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
5235 }
5236
5237-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5238+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5239 /* { dg-final { cleanup-saved-temps } } */
5240Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
5241===================================================================
5242--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2011-06-24 08:13:40.000000000 -0700
5243+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2011-09-16 20:16:00.547565082 -0700
5244@@ -16,5 +16,5 @@
5245 vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
5246 }
5247
5248-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5249+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5250 /* { dg-final { cleanup-saved-temps } } */
5251Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
5252===================================================================
5253--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2011-06-24 08:13:40.000000000 -0700
5254+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2011-09-16 20:16:00.547565082 -0700
5255@@ -16,5 +16,5 @@
5256 vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
5257 }
5258
5259-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5260+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5261 /* { dg-final { cleanup-saved-temps } } */
5262Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
5263===================================================================
5264--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2011-06-24 08:13:40.000000000 -0700
5265+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2011-09-16 20:16:00.547565082 -0700
5266@@ -16,5 +16,5 @@
5267 vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
5268 }
5269
5270-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5271+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5272 /* { dg-final { cleanup-saved-temps } } */
5273Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
5274===================================================================
5275--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2011-06-24 08:13:40.000000000 -0700
5276+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2011-09-16 20:16:00.547565082 -0700
5277@@ -16,5 +16,5 @@
5278 vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
5279 }
5280
5281-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5282+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5283 /* { dg-final { cleanup-saved-temps } } */
5284Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
5285===================================================================
5286--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2011-06-24 08:13:40.000000000 -0700
5287+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2011-09-16 20:16:00.557565092 -0700
5288@@ -16,5 +16,5 @@
5289 vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
5290 }
5291
5292-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5293+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5294 /* { dg-final { cleanup-saved-temps } } */
5295Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
5296===================================================================
5297--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2011-06-24 08:13:40.000000000 -0700
5298+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2011-09-16 20:16:00.557565092 -0700
5299@@ -16,5 +16,5 @@
5300 vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
5301 }
5302
5303-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5304+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5305 /* { dg-final { cleanup-saved-temps } } */
5306Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
5307===================================================================
5308--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
5309+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2011-09-16 20:16:00.557565092 -0700
5310@@ -16,5 +16,5 @@
5311 vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
5312 }
5313
5314-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5315+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5316 /* { dg-final { cleanup-saved-temps } } */
5317Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
5318===================================================================
5319--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
5320+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2011-09-16 20:16:00.557565092 -0700
5321@@ -16,5 +16,5 @@
5322 vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
5323 }
5324
5325-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5326+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5327 /* { dg-final { cleanup-saved-temps } } */
5328Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
5329===================================================================
5330--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
5331+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2011-09-16 20:16:00.557565092 -0700
5332@@ -16,5 +16,5 @@
5333 vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
5334 }
5335
5336-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5337+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5338 /* { dg-final { cleanup-saved-temps } } */
5339Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
5340===================================================================
5341--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
5342+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2011-09-16 20:16:00.557565092 -0700
5343@@ -16,5 +16,5 @@
5344 vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
5345 }
5346
5347-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5348+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5349 /* { dg-final { cleanup-saved-temps } } */
5350Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
5351===================================================================
5352--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
5353+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2011-09-16 20:16:00.557565092 -0700
5354@@ -16,5 +16,5 @@
5355 vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
5356 }
5357
5358-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5359+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5360 /* { dg-final { cleanup-saved-temps } } */
5361Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
5362===================================================================
5363--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
5364+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2011-09-16 20:16:00.557565092 -0700
5365@@ -16,5 +16,5 @@
5366 vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
5367 }
5368
5369-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5370+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5371 /* { dg-final { cleanup-saved-temps } } */
5372Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
5373===================================================================
5374--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2011-06-24 08:13:40.000000000 -0700
5375+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2011-09-16 20:16:00.557565092 -0700
5376@@ -16,6 +16,6 @@
5377 vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
5378 }
5379
5380-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5381-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5382+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5383+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5384 /* { dg-final { cleanup-saved-temps } } */
5385Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
5386===================================================================
5387--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2011-06-24 08:13:40.000000000 -0700
5388+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2011-09-16 20:16:00.567565108 -0700
5389@@ -16,6 +16,6 @@
5390 vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
5391 }
5392
5393-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5394-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5395+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5396+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5397 /* { dg-final { cleanup-saved-temps } } */
5398Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
5399===================================================================
5400--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2011-06-24 08:13:40.000000000 -0700
5401+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2011-09-16 20:16:00.567565108 -0700
5402@@ -16,6 +16,6 @@
5403 vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
5404 }
5405
5406-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5407-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5408+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5409+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5410 /* { dg-final { cleanup-saved-temps } } */
5411Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
5412===================================================================
5413--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2011-06-24 08:13:40.000000000 -0700
5414+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2011-09-16 20:16:00.567565108 -0700
5415@@ -16,6 +16,6 @@
5416 vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
5417 }
5418
5419-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5420-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5421+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5422+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5423 /* { dg-final { cleanup-saved-temps } } */
5424Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
5425===================================================================
5426--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2011-06-24 08:13:40.000000000 -0700
5427+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2011-09-16 20:16:00.567565108 -0700
5428@@ -16,6 +16,6 @@
5429 vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
5430 }
5431
5432-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5433-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5434+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5435+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5436 /* { dg-final { cleanup-saved-temps } } */
5437Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
5438===================================================================
5439--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2011-06-24 08:13:40.000000000 -0700
5440+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2011-09-16 20:16:00.567565108 -0700
5441@@ -16,6 +16,6 @@
5442 vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
5443 }
5444
5445-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5446-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5447+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5448+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5449 /* { dg-final { cleanup-saved-temps } } */
5450Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
5451===================================================================
5452--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2011-06-24 08:13:40.000000000 -0700
5453+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2011-09-16 20:16:00.567565108 -0700
5454@@ -16,6 +16,6 @@
5455 vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
5456 }
5457
5458-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5459-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5460+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5461+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5462 /* { dg-final { cleanup-saved-temps } } */
5463Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
5464===================================================================
5465--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2011-06-24 08:13:40.000000000 -0700
5466+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2011-09-16 20:16:00.567565108 -0700
5467@@ -16,6 +16,6 @@
5468 vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
5469 }
5470
5471-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5472-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5473+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5474+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5475 /* { dg-final { cleanup-saved-temps } } */
5476Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
5477===================================================================
5478--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2011-06-24 08:13:40.000000000 -0700
5479+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2011-09-16 20:16:00.567565108 -0700
5480@@ -16,6 +16,6 @@
5481 vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
5482 }
5483
5484-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5485-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5486+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5487+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5488 /* { dg-final { cleanup-saved-temps } } */
5489Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
5490===================================================================
5491--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2011-06-24 08:13:40.000000000 -0700
5492+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2011-09-16 20:16:00.567565108 -0700
5493@@ -16,5 +16,5 @@
5494 vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
5495 }
5496
5497-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5498+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5499 /* { dg-final { cleanup-saved-temps } } */
5500Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
5501===================================================================
5502--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2011-06-24 08:13:40.000000000 -0700
5503+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2011-09-16 20:16:00.577565135 -0700
5504@@ -16,5 +16,5 @@
5505 vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
5506 }
5507
5508-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5509+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5510 /* { dg-final { cleanup-saved-temps } } */
5511Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
5512===================================================================
5513--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2011-06-24 08:13:40.000000000 -0700
5514+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2011-09-16 20:16:00.577565135 -0700
5515@@ -16,5 +16,5 @@
5516 vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
5517 }
5518
5519-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5520+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5521 /* { dg-final { cleanup-saved-temps } } */
5522Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
5523===================================================================
5524--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2011-06-24 08:13:40.000000000 -0700
5525+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2011-09-16 20:16:00.577565135 -0700
5526@@ -16,5 +16,5 @@
5527 vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
5528 }
5529
5530-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5531+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5532 /* { dg-final { cleanup-saved-temps } } */
5533Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
5534===================================================================
5535--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2011-06-24 08:13:40.000000000 -0700
5536+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2011-09-16 20:16:00.577565135 -0700
5537@@ -16,5 +16,5 @@
5538 vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
5539 }
5540
5541-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5542+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5543 /* { dg-final { cleanup-saved-temps } } */
5544Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
5545===================================================================
5546--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2011-06-24 08:13:40.000000000 -0700
5547+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2011-09-16 20:16:00.577565135 -0700
5548@@ -16,5 +16,5 @@
5549 vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
5550 }
5551
5552-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5553+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5554 /* { dg-final { cleanup-saved-temps } } */
5555Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
5556===================================================================
5557--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2011-06-24 08:13:40.000000000 -0700
5558+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2011-09-16 20:16:00.577565135 -0700
5559@@ -16,5 +16,5 @@
5560 vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
5561 }
5562
5563-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5564+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5565 /* { dg-final { cleanup-saved-temps } } */
5566Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
5567===================================================================
5568--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2011-06-24 08:13:40.000000000 -0700
5569+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2011-09-16 20:16:00.577565135 -0700
5570@@ -16,5 +16,5 @@
5571 vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
5572 }
5573
5574-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5575+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5576 /* { dg-final { cleanup-saved-temps } } */
5577Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
5578===================================================================
5579--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2011-06-24 08:13:40.000000000 -0700
5580+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2011-09-16 20:16:00.587565144 -0700
5581@@ -16,5 +16,5 @@
5582 vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
5583 }
5584
5585-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5586+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5587 /* { dg-final { cleanup-saved-temps } } */
5588Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
5589===================================================================
5590--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2011-06-24 08:13:40.000000000 -0700
5591+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2011-09-16 20:16:00.587565144 -0700
5592@@ -16,5 +16,5 @@
5593 vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
5594 }
5595
5596-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5597+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5598 /* { dg-final { cleanup-saved-temps } } */
5599Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
5600===================================================================
5601--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2011-06-24 08:13:40.000000000 -0700
5602+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2011-09-16 20:16:00.587565144 -0700
5603@@ -16,5 +16,5 @@
5604 vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
5605 }
5606
5607-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5608+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5609 /* { dg-final { cleanup-saved-temps } } */
5610Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
5611===================================================================
5612--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2011-06-24 08:13:40.000000000 -0700
5613+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2011-09-16 20:16:00.587565144 -0700
5614@@ -16,5 +16,5 @@
5615 vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
5616 }
5617
5618-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5619+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5620 /* { dg-final { cleanup-saved-temps } } */
5621Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
5622===================================================================
5623--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2011-06-24 08:13:40.000000000 -0700
5624+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2011-09-16 20:16:00.587565144 -0700
5625@@ -16,5 +16,5 @@
5626 vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
5627 }
5628
5629-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5630+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5631 /* { dg-final { cleanup-saved-temps } } */
5632Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
5633===================================================================
5634--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2011-06-24 08:13:40.000000000 -0700
5635+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2011-09-16 20:16:00.587565144 -0700
5636@@ -16,5 +16,5 @@
5637 vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
5638 }
5639
5640-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5641+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5642 /* { dg-final { cleanup-saved-temps } } */
5643Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
5644===================================================================
5645--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2011-06-24 08:13:40.000000000 -0700
5646+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2011-09-16 20:16:00.587565144 -0700
5647@@ -16,5 +16,5 @@
5648 vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
5649 }
5650
5651-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5652+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5653 /* { dg-final { cleanup-saved-temps } } */
5654Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
5655===================================================================
5656--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2011-06-24 08:13:40.000000000 -0700
5657+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2011-09-16 20:16:00.587565144 -0700
5658@@ -16,5 +16,5 @@
5659 vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
5660 }
5661
5662-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5663+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5664 /* { dg-final { cleanup-saved-temps } } */
5665Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
5666===================================================================
5667--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2011-06-24 08:13:40.000000000 -0700
5668+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2011-09-16 20:16:00.587565144 -0700
5669@@ -16,5 +16,5 @@
5670 vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
5671 }
5672
5673-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5674+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5675 /* { dg-final { cleanup-saved-temps } } */
5676Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
5677===================================================================
5678--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2011-06-24 08:13:40.000000000 -0700
5679+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2011-09-16 20:16:00.587565144 -0700
5680@@ -16,5 +16,5 @@
5681 vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
5682 }
5683
5684-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5685+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5686 /* { dg-final { cleanup-saved-temps } } */
5687Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
5688===================================================================
5689--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2011-06-24 08:13:40.000000000 -0700
5690+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2011-09-16 20:16:00.587565144 -0700
5691@@ -16,5 +16,5 @@
5692 vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
5693 }
5694
5695-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5696+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5697 /* { dg-final { cleanup-saved-temps } } */
5698Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
5699===================================================================
5700--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2011-06-24 08:13:40.000000000 -0700
5701+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2011-09-16 20:16:00.587565144 -0700
5702@@ -16,5 +16,5 @@
5703 vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
5704 }
5705
5706-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5707+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5708 /* { dg-final { cleanup-saved-temps } } */
5709Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
5710===================================================================
5711--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
5712+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2011-09-16 20:16:00.597565156 -0700
5713@@ -16,5 +16,5 @@
5714 vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
5715 }
5716
5717-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5718+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5719 /* { dg-final { cleanup-saved-temps } } */
5720Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
5721===================================================================
5722--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
5723+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2011-09-16 20:16:00.597565156 -0700
5724@@ -16,5 +16,5 @@
5725 vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
5726 }
5727
5728-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5729+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5730 /* { dg-final { cleanup-saved-temps } } */
5731Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
5732===================================================================
5733--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
5734+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2011-09-16 20:16:00.597565156 -0700
5735@@ -16,5 +16,5 @@
5736 vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
5737 }
5738
5739-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5740+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5741 /* { dg-final { cleanup-saved-temps } } */
5742Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
5743===================================================================
5744--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
5745+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2011-09-16 20:16:00.597565156 -0700
5746@@ -16,5 +16,5 @@
5747 vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
5748 }
5749
5750-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5751+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5752 /* { dg-final { cleanup-saved-temps } } */
5753Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
5754===================================================================
5755--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
5756+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2011-09-16 20:16:00.597565156 -0700
5757@@ -16,5 +16,5 @@
5758 vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
5759 }
5760
5761-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5762+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5763 /* { dg-final { cleanup-saved-temps } } */
5764Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
5765===================================================================
5766--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
5767+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2011-09-16 20:16:00.597565156 -0700
5768@@ -16,5 +16,5 @@
5769 vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
5770 }
5771
5772-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5773+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5774 /* { dg-final { cleanup-saved-temps } } */
5775Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
5776===================================================================
5777--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2011-06-24 08:13:40.000000000 -0700
5778+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2011-09-16 20:16:00.597565156 -0700
5779@@ -16,6 +16,6 @@
5780 vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
5781 }
5782
5783-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5784-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5785+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5786+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5787 /* { dg-final { cleanup-saved-temps } } */
5788Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
5789===================================================================
5790--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2011-06-24 08:13:40.000000000 -0700
5791+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2011-09-16 20:16:00.597565156 -0700
5792@@ -16,6 +16,6 @@
5793 vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
5794 }
5795
5796-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5797-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5798+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5799+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5800 /* { dg-final { cleanup-saved-temps } } */
5801Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
5802===================================================================
5803--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2011-06-24 08:13:40.000000000 -0700
5804+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2011-09-16 20:16:00.597565156 -0700
5805@@ -16,6 +16,6 @@
5806 vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
5807 }
5808
5809-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5810-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5811+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5812+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5813 /* { dg-final { cleanup-saved-temps } } */
5814Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
5815===================================================================
5816--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2011-06-24 08:13:40.000000000 -0700
5817+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2011-09-16 20:16:00.597565156 -0700
5818@@ -16,6 +16,6 @@
5819 vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
5820 }
5821
5822-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5823-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5824+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5825+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5826 /* { dg-final { cleanup-saved-temps } } */
5827Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
5828===================================================================
5829--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2011-06-24 08:13:40.000000000 -0700
5830+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2011-09-16 20:16:00.597565156 -0700
5831@@ -16,6 +16,6 @@
5832 vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
5833 }
5834
5835-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5836-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5837+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5838+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5839 /* { dg-final { cleanup-saved-temps } } */
5840Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
5841===================================================================
5842--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2011-06-24 08:13:40.000000000 -0700
5843+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2011-09-16 20:16:00.607565171 -0700
5844@@ -16,6 +16,6 @@
5845 vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
5846 }
5847
5848-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5849-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5850+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5851+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5852 /* { dg-final { cleanup-saved-temps } } */
5853Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
5854===================================================================
5855--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2011-06-24 08:13:40.000000000 -0700
5856+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2011-09-16 20:16:00.607565171 -0700
5857@@ -16,6 +16,6 @@
5858 vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
5859 }
5860
5861-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5862-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5863+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5864+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5865 /* { dg-final { cleanup-saved-temps } } */
5866Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
5867===================================================================
5868--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2011-06-24 08:13:40.000000000 -0700
5869+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2011-09-16 20:16:00.607565171 -0700
5870@@ -16,6 +16,6 @@
5871 vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
5872 }
5873
5874-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5875-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5876+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5877+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5878 /* { dg-final { cleanup-saved-temps } } */
5879Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
5880===================================================================
5881--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2011-06-24 08:13:40.000000000 -0700
5882+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2011-09-16 20:16:00.607565171 -0700
5883@@ -16,6 +16,6 @@
5884 vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
5885 }
5886
5887-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5888-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5889+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5890+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5891 /* { dg-final { cleanup-saved-temps } } */
5892Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
5893===================================================================
5894--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2011-06-24 08:13:40.000000000 -0700
5895+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2011-09-16 20:16:00.607565171 -0700
5896@@ -16,5 +16,5 @@
5897 vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
5898 }
5899
5900-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5901+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5902 /* { dg-final { cleanup-saved-temps } } */
5903Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
5904===================================================================
5905--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2011-06-24 08:13:40.000000000 -0700
5906+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2011-09-16 20:16:00.607565171 -0700
5907@@ -16,5 +16,5 @@
5908 vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
5909 }
5910
5911-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5912+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5913 /* { dg-final { cleanup-saved-temps } } */
5914Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
5915===================================================================
5916--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2011-06-24 08:13:40.000000000 -0700
5917+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2011-09-16 20:16:00.607565171 -0700
5918@@ -16,5 +16,5 @@
5919 vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
5920 }
5921
5922-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5923+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5924 /* { dg-final { cleanup-saved-temps } } */
5925Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
5926===================================================================
5927--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2011-06-24 08:13:40.000000000 -0700
5928+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2011-09-16 20:16:00.607565171 -0700
5929@@ -16,5 +16,5 @@
5930 vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
5931 }
5932
5933-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5934+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5935 /* { dg-final { cleanup-saved-temps } } */
5936Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
5937===================================================================
5938--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2011-06-24 08:13:40.000000000 -0700
5939+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2011-09-16 20:16:00.607565171 -0700
5940@@ -16,5 +16,5 @@
5941 vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
5942 }
5943
5944-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5945+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5946 /* { dg-final { cleanup-saved-temps } } */
5947Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
5948===================================================================
5949--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2011-06-24 08:13:40.000000000 -0700
5950+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2011-09-16 20:16:00.607565171 -0700
5951@@ -16,5 +16,5 @@
5952 vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
5953 }
5954
5955-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5956+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5957 /* { dg-final { cleanup-saved-temps } } */
5958Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
5959===================================================================
5960--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2011-06-24 08:13:40.000000000 -0700
5961+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2011-09-16 20:16:00.607565171 -0700
5962@@ -16,5 +16,5 @@
5963 vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
5964 }
5965
5966-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5967+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5968 /* { dg-final { cleanup-saved-temps } } */
5969Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
5970===================================================================
5971--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2011-06-24 08:13:40.000000000 -0700
5972+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2011-09-16 20:16:00.607565171 -0700
5973@@ -16,5 +16,5 @@
5974 vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
5975 }
5976
5977-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5978+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5979 /* { dg-final { cleanup-saved-temps } } */
5980Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
5981===================================================================
5982--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2011-06-24 08:13:40.000000000 -0700
5983+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2011-09-16 20:16:00.607565171 -0700
5984@@ -16,5 +16,5 @@
5985 vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
5986 }
5987
5988-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5989+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5990 /* { dg-final { cleanup-saved-temps } } */
5991Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
5992===================================================================
5993--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2011-06-24 08:13:40.000000000 -0700
5994+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2011-09-16 20:16:00.607565171 -0700
5995@@ -16,5 +16,5 @@
5996 vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
5997 }
5998
5999-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6000+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6001 /* { dg-final { cleanup-saved-temps } } */
6002Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
6003===================================================================
6004--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2011-06-24 08:13:40.000000000 -0700
6005+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2011-09-16 20:16:00.607565171 -0700
6006@@ -16,5 +16,5 @@
6007 vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
6008 }
6009
6010-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6011+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6012 /* { dg-final { cleanup-saved-temps } } */
6013Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
6014===================================================================
6015--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2011-06-24 08:13:40.000000000 -0700
6016+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2011-09-16 20:16:00.607565171 -0700
6017@@ -16,5 +16,5 @@
6018 vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
6019 }
6020
6021-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6022+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6023 /* { dg-final { cleanup-saved-temps } } */
6024Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
6025===================================================================
6026--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2011-06-24 08:13:40.000000000 -0700
6027+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2011-09-16 20:16:00.607565171 -0700
6028@@ -16,5 +16,5 @@
6029 vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
6030 }
6031
6032-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6033+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6034 /* { dg-final { cleanup-saved-temps } } */
6035Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
6036===================================================================
6037--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2011-06-24 08:13:40.000000000 -0700
6038+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2011-09-16 20:16:00.607565171 -0700
6039@@ -16,5 +16,5 @@
6040 vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
6041 }
6042
6043-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6044+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6045 /* { dg-final { cleanup-saved-temps } } */
6046Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
6047===================================================================
6048--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2011-06-24 08:13:40.000000000 -0700
6049+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2011-09-16 20:16:00.607565171 -0700
6050@@ -16,5 +16,5 @@
6051 vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
6052 }
6053
6054-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6055+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6056 /* { dg-final { cleanup-saved-temps } } */
6057Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
6058===================================================================
6059--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2011-06-24 08:13:40.000000000 -0700
6060+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2011-09-16 20:16:00.607565171 -0700
6061@@ -16,5 +16,5 @@
6062 vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
6063 }
6064
6065-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6066+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6067 /* { dg-final { cleanup-saved-temps } } */
6068Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
6069===================================================================
6070--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2011-06-24 08:13:40.000000000 -0700
6071+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2011-09-16 20:16:00.607565171 -0700
6072@@ -16,5 +16,5 @@
6073 vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
6074 }
6075
6076-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6077+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6078 /* { dg-final { cleanup-saved-temps } } */
6079Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
6080===================================================================
6081--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2011-06-24 08:13:40.000000000 -0700
6082+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2011-09-16 20:16:00.607565171 -0700
6083@@ -16,5 +16,5 @@
6084 vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
6085 }
6086
6087-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6088+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6089 /* { dg-final { cleanup-saved-temps } } */
6090Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
6091===================================================================
6092--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2011-06-24 08:13:40.000000000 -0700
6093+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2011-09-16 20:16:00.607565171 -0700
6094@@ -16,5 +16,5 @@
6095 vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
6096 }
6097
6098-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6099+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6100 /* { dg-final { cleanup-saved-temps } } */
6101Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
6102===================================================================
6103--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2011-06-24 08:13:40.000000000 -0700
6104+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2011-09-16 20:16:00.607565171 -0700
6105@@ -16,5 +16,5 @@
6106 vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
6107 }
6108
6109-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6110+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6111 /* { dg-final { cleanup-saved-temps } } */
6112Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr46329.c
6113===================================================================
6114--- /dev/null 1970-01-01 00:00:00.000000000 +0000
6115+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr46329.c 2011-09-16 20:16:00.617565191 -0700
6116@@ -0,0 +1,9 @@
6117+/* { dg-options "-O2" } */
6118+/* { dg-add-options arm_neon } */
6119+
6120+int __attribute__ ((vector_size (32))) x;
6121+void
6122+foo (void)
6123+{
6124+ x <<= x;
6125+}
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106744.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106744.patch
deleted file mode 100644
index 004f0131c..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106744.patch
+++ /dev/null
@@ -1,21 +0,0 @@
12011-05-06 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 From Sergey Grechanik <mouseentity@ispras.ru>, approved for mainline
5
6 * config/arm/arm.c (coproc_secondary_reload_class): Return NO_REGS
7 for constant vectors.
8
9=== modified file 'gcc/config/arm/arm.c'
10--- old/gcc/config/arm/arm.c 2011-05-03 15:18:07 +0000
11+++ new/gcc/config/arm/arm.c 2011-05-06 11:33:02 +0000
12@@ -9193,7 +9193,7 @@
13 /* The neon move patterns handle all legitimate vector and struct
14 addresses. */
15 if (TARGET_NEON
16- && MEM_P (x)
17+ && (MEM_P (x) || GET_CODE (x) == CONST_VECTOR)
18 && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
19 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
20 || VALID_NEON_STRUCT_MODE (mode)))
21
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106746.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106746.patch
deleted file mode 100644
index ce0272431..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106746.patch
+++ /dev/null
@@ -1,24 +0,0 @@
12011-05-12 Michael Hope <michael.hope@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-05-05 Michael Hope <michael.hope@linaro.org>
7
8 PR pch/45979
9 * config/host-linux.c (TRY_EMPTY_VM_SPACE): Define for
10 __ARM_EABI__ hosts.
11
12=== modified file 'gcc/config/host-linux.c'
13--- old/gcc/config/host-linux.c 2010-11-29 14:09:41 +0000
14+++ new/gcc/config/host-linux.c 2011-05-06 20:19:30 +0000
15@@ -84,6 +84,8 @@
16 # define TRY_EMPTY_VM_SPACE 0x60000000
17 #elif defined(__mc68000__)
18 # define TRY_EMPTY_VM_SPACE 0x40000000
19+#elif defined(__ARM_EABI__)
20+# define TRY_EMPTY_VM_SPACE 0x60000000
21 #else
22 # define TRY_EMPTY_VM_SPACE 0
23 #endif
24
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106747.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106747.patch
deleted file mode 100644
index 7885b7af4..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106747.patch
+++ /dev/null
@@ -1,640 +0,0 @@
12011-05-13 Revital Eres <revital.eres@linaro.org>
2
3 gcc/
4 * loop-doloop.c (doloop_condition_get): Support new form of
5 doloop pattern and use prev_nondebug_insn instead of PREV_INSN.
6 * config/arm/thumb2.md (*thumb2_addsi3_compare0): Remove "*".
7 (doloop_end): New.
8 * config/arm/arm.md (*addsi3_compare0): Remove "*".
9 * params.def (sms-min-sc): New param flag.
10 * doc/invoke.texi (sms-min-sc): Document it.
11 * ddg.c (create_ddg_dep_from_intra_loop_link): If a true dep edge
12 enters the branch create an anti edge in the opposite direction
13 to prevent the creation of reg-moves.
14 * modulo-sched.c: Adjust comment to reflect the fact we are
15 scheduling closing branch.
16 (PS_STAGE_COUNT): Rename to CALC_STAGE_COUNT and redefine.
17 (stage_count): New field in struct partial_schedule.
18 (calculate_stage_count): New function.
19 (normalize_sched_times): Rename to reset_sched_times and handle
20 incrementing the sched time of the nodes by a constant value
21 passed as parameter.
22 (duplicate_insns_of_cycles): Skip closing branch.
23 (sms_schedule_by_order): Schedule closing branch.
24 (ps_insn_find_column): Handle closing branch.
25 (sms_schedule): Call reset_sched_times and adjust the code to
26 support scheduling of the closing branch. Use sms-min-sc.
27 Support new form of doloop pattern.
28 (ps_insert_empty_row): Update calls to normalize_sched_times
29 and rotate_partial_schedule functions.
30
31=== modified file 'gcc/config/arm/arm.md'
32--- old/gcc/config/arm/arm.md 2011-05-06 11:28:27 +0000
33+++ new/gcc/config/arm/arm.md 2011-05-13 13:42:39 +0000
34@@ -791,7 +791,7 @@
35 ""
36 )
37
38-(define_insn "*addsi3_compare0"
39+(define_insn "addsi3_compare0"
40 [(set (reg:CC_NOOV CC_REGNUM)
41 (compare:CC_NOOV
42 (plus:SI (match_operand:SI 1 "s_register_operand" "r, r")
43
44=== modified file 'gcc/config/arm/thumb2.md'
45--- old/gcc/config/arm/thumb2.md 2011-01-03 20:52:22 +0000
46+++ new/gcc/config/arm/thumb2.md 2011-05-11 07:15:47 +0000
47@@ -836,7 +836,7 @@
48 "operands[4] = GEN_INT (- INTVAL (operands[2]));"
49 )
50
51-(define_insn "*thumb2_addsi3_compare0"
52+(define_insn "thumb2_addsi3_compare0"
53 [(set (reg:CC_NOOV CC_REGNUM)
54 (compare:CC_NOOV
55 (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
56@@ -1118,3 +1118,54 @@
57 "
58 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
59 ")
60+
61+;; Define the subtract-one-and-jump insns so loop.c
62+;; knows what to generate.
63+(define_expand "doloop_end"
64+ [(use (match_operand 0 "" "")) ; loop pseudo
65+ (use (match_operand 1 "" "")) ; iterations; zero if unknown
66+ (use (match_operand 2 "" "")) ; max iterations
67+ (use (match_operand 3 "" "")) ; loop level
68+ (use (match_operand 4 "" ""))] ; label
69+ "TARGET_32BIT"
70+ "
71+ {
72+ /* Currently SMS relies on the do-loop pattern to recognize loops
73+ where (1) the control part consists of all insns defining and/or
74+ using a certain 'count' register and (2) the loop count can be
75+ adjusted by modifying this register prior to the loop.
76+ ??? The possible introduction of a new block to initialize the
77+ new IV can potentially affect branch optimizations. */
78+ if (optimize > 0 && flag_modulo_sched)
79+ {
80+ rtx s0;
81+ rtx bcomp;
82+ rtx loc_ref;
83+ rtx cc_reg;
84+ rtx insn;
85+ rtx cmp;
86+
87+ /* Only use this on innermost loops. */
88+ if (INTVAL (operands[3]) > 1)
89+ FAIL;
90+ if (GET_MODE (operands[0]) != SImode)
91+ FAIL;
92+
93+ s0 = operands [0];
94+ if (TARGET_THUMB2)
95+ insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
96+ else
97+ insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
98+
99+ cmp = XVECEXP (PATTERN (insn), 0, 0);
100+ cc_reg = SET_DEST (cmp);
101+ bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
102+ loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]);
103+ emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
104+ gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
105+ loc_ref, pc_rtx)));
106+ DONE;
107+ }else
108+ FAIL;
109+}")
110+
111
112=== modified file 'gcc/ddg.c'
113--- old/gcc/ddg.c 2010-11-30 11:41:24 +0000
114+++ new/gcc/ddg.c 2011-05-11 07:15:47 +0000
115@@ -197,6 +197,11 @@
116 }
117 }
118
119+ /* If a true dep edge enters the branch create an anti edge in the
120+ opposite direction to prevent the creation of reg-moves. */
121+ if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn))
122+ create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1);
123+
124 latency = dep_cost (link);
125 e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
126 add_edge_to_ddg (g, e);
127
128=== modified file 'gcc/doc/invoke.texi'
129--- old/gcc/doc/invoke.texi 2011-04-18 11:31:29 +0000
130+++ new/gcc/doc/invoke.texi 2011-05-11 07:15:47 +0000
131@@ -8730,6 +8730,10 @@
132 The maximum number of best instructions in the ready list that are considered
133 for renaming in the selective scheduler. The default value is 2.
134
135+@item sms-min-sc
136+The minimum value of stage count that swing modulo scheduler will
137+generate. The default value is 2.
138+
139 @item max-last-value-rtl
140 The maximum size measured as number of RTLs that can be recorded in an expression
141 in combiner for a pseudo register as last known value of that register. The default
142
143=== modified file 'gcc/loop-doloop.c'
144--- old/gcc/loop-doloop.c 2010-11-30 11:41:24 +0000
145+++ new/gcc/loop-doloop.c 2011-05-11 07:15:47 +0000
146@@ -78,6 +78,8 @@
147 rtx inc_src;
148 rtx condition;
149 rtx pattern;
150+ rtx cc_reg = NULL_RTX;
151+ rtx reg_orig = NULL_RTX;
152
153 /* The canonical doloop pattern we expect has one of the following
154 forms:
155@@ -96,7 +98,16 @@
156 2) (set (reg) (plus (reg) (const_int -1))
157 (set (pc) (if_then_else (reg != 0)
158 (label_ref (label))
159- (pc))). */
160+ (pc))).
161+
162+ Some targets (ARM) do the comparison before the branch, as in the
163+ following form:
164+
165+ 3) (parallel [(set (cc) (compare ((plus (reg) (const_int -1), 0)))
166+ (set (reg) (plus (reg) (const_int -1)))])
167+ (set (pc) (if_then_else (cc == NE)
168+ (label_ref (label))
169+ (pc))) */
170
171 pattern = PATTERN (doloop_pat);
172
173@@ -104,19 +115,47 @@
174 {
175 rtx cond;
176 rtx prev_insn = prev_nondebug_insn (doloop_pat);
177+ rtx cmp_arg1, cmp_arg2;
178+ rtx cmp_orig;
179
180- /* We expect the decrement to immediately precede the branch. */
181+ /* In case the pattern is not PARALLEL we expect two forms
182+ of doloop which are cases 2) and 3) above: in case 2) the
183+ decrement immediately precedes the branch, while in case 3)
184+ the compare and decrement instructions immediately precede
185+ the branch. */
186
187 if (prev_insn == NULL_RTX || !INSN_P (prev_insn))
188 return 0;
189
190 cmp = pattern;
191- inc = PATTERN (PREV_INSN (doloop_pat));
192+ if (GET_CODE (PATTERN (prev_insn)) == PARALLEL)
193+ {
194+ /* The third case: the compare and decrement instructions
195+ immediately precede the branch. */
196+ cmp_orig = XVECEXP (PATTERN (prev_insn), 0, 0);
197+ if (GET_CODE (cmp_orig) != SET)
198+ return 0;
199+ if (GET_CODE (SET_SRC (cmp_orig)) != COMPARE)
200+ return 0;
201+ cmp_arg1 = XEXP (SET_SRC (cmp_orig), 0);
202+ cmp_arg2 = XEXP (SET_SRC (cmp_orig), 1);
203+ if (cmp_arg2 != const0_rtx
204+ || GET_CODE (cmp_arg1) != PLUS)
205+ return 0;
206+ reg_orig = XEXP (cmp_arg1, 0);
207+ if (XEXP (cmp_arg1, 1) != GEN_INT (-1)
208+ || !REG_P (reg_orig))
209+ return 0;
210+ cc_reg = SET_DEST (cmp_orig);
211+
212+ inc = XVECEXP (PATTERN (prev_insn), 0, 1);
213+ }
214+ else
215+ inc = PATTERN (prev_insn);
216 /* We expect the condition to be of the form (reg != 0) */
217 cond = XEXP (SET_SRC (cmp), 0);
218 if (GET_CODE (cond) != NE || XEXP (cond, 1) != const0_rtx)
219 return 0;
220-
221 }
222 else
223 {
224@@ -162,11 +201,15 @@
225 return 0;
226
227 if ((XEXP (condition, 0) == reg)
228+ /* For the third case: */
229+ || ((cc_reg != NULL_RTX)
230+ && (XEXP (condition, 0) == cc_reg)
231+ && (reg_orig == reg))
232 || (GET_CODE (XEXP (condition, 0)) == PLUS
233- && XEXP (XEXP (condition, 0), 0) == reg))
234+ && XEXP (XEXP (condition, 0), 0) == reg))
235 {
236 if (GET_CODE (pattern) != PARALLEL)
237- /* The second form we expect:
238+ /* For the second form we expect:
239
240 (set (reg) (plus (reg) (const_int -1))
241 (set (pc) (if_then_else (reg != 0)
242@@ -181,7 +224,24 @@
243 (set (reg) (plus (reg) (const_int -1)))
244 (additional clobbers and uses)])
245
246- So we return that form instead.
247+ For the third form we expect:
248+
249+ (parallel [(set (cc) (compare ((plus (reg) (const_int -1)), 0))
250+ (set (reg) (plus (reg) (const_int -1)))])
251+ (set (pc) (if_then_else (cc == NE)
252+ (label_ref (label))
253+ (pc)))
254+
255+ which is equivalent to the following:
256+
257+ (parallel [(set (cc) (compare (reg, 1))
258+ (set (reg) (plus (reg) (const_int -1)))
259+ (set (pc) (if_then_else (NE == cc)
260+ (label_ref (label))
261+ (pc))))])
262+
263+ So we return the second form instead for the two cases.
264+
265 */
266 condition = gen_rtx_fmt_ee (NE, VOIDmode, inc_src, const1_rtx);
267
268
269=== modified file 'gcc/modulo-sched.c'
270--- old/gcc/modulo-sched.c 2011-02-14 17:59:10 +0000
271+++ new/gcc/modulo-sched.c 2011-05-11 07:15:47 +0000
272@@ -84,14 +84,13 @@
273 II cycles (i.e. use register copies to prevent a def from overwriting
274 itself before reaching the use).
275
276- SMS works with countable loops (1) whose control part can be easily
277- decoupled from the rest of the loop and (2) whose loop count can
278- be easily adjusted. This is because we peel a constant number of
279- iterations into a prologue and epilogue for which we want to avoid
280- emitting the control part, and a kernel which is to iterate that
281- constant number of iterations less than the original loop. So the
282- control part should be a set of insns clearly identified and having
283- its own iv, not otherwise used in the loop (at-least for now), which
284+ SMS works with countable loops whose loop count can be easily
285+ adjusted. This is because we peel a constant number of iterations
286+ into a prologue and epilogue for which we want to avoid emitting
287+ the control part, and a kernel which is to iterate that constant
288+ number of iterations less than the original loop. So the control
289+ part should be a set of insns clearly identified and having its
290+ own iv, not otherwise used in the loop (at-least for now), which
291 initializes a register before the loop to the number of iterations.
292 Currently SMS relies on the do-loop pattern to recognize such loops,
293 where (1) the control part comprises of all insns defining and/or
294@@ -116,8 +115,10 @@
295
296 /* The number of different iterations the nodes in ps span, assuming
297 the stage boundaries are placed efficiently. */
298-#define PS_STAGE_COUNT(ps) ((PS_MAX_CYCLE (ps) - PS_MIN_CYCLE (ps) \
299- + 1 + (ps)->ii - 1) / (ps)->ii)
300+#define CALC_STAGE_COUNT(max_cycle,min_cycle,ii) ((max_cycle - min_cycle \
301+ + 1 + ii - 1) / ii)
302+/* The stage count of ps. */
303+#define PS_STAGE_COUNT(ps) (((partial_schedule_ptr)(ps))->stage_count)
304
305 /* A single instruction in the partial schedule. */
306 struct ps_insn
307@@ -155,6 +156,8 @@
308 int max_cycle;
309
310 ddg_ptr g; /* The DDG of the insns in the partial schedule. */
311+
312+ int stage_count; /* The stage count of the partial schedule. */
313 };
314
315 /* We use this to record all the register replacements we do in
316@@ -195,7 +198,7 @@
317 rtx, rtx);
318 static void duplicate_insns_of_cycles (partial_schedule_ptr,
319 int, int, int, rtx);
320-
321+static int calculate_stage_count (partial_schedule_ptr ps);
322 #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
323 #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
324 #define SCHED_FIRST_REG_MOVE(x) \
325@@ -310,10 +313,10 @@
326 either a single (parallel) branch-on-count or a (non-parallel)
327 branch immediately preceded by a single (decrement) insn. */
328 first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail
329- : PREV_INSN (tail));
330+ : prev_nondebug_insn (tail));
331
332 for (insn = head; insn != first_insn_not_to_check; insn = NEXT_INSN (insn))
333- if (reg_mentioned_p (reg, insn))
334+ if (reg_mentioned_p (reg, insn) && !DEBUG_INSN_P (insn))
335 {
336 if (dump_file)
337 {
338@@ -569,13 +572,12 @@
339 }
340 }
341
342-/* Bump the SCHED_TIMEs of all nodes to start from zero. Set the values
343- of SCHED_ROW and SCHED_STAGE. */
344+/* Bump the SCHED_TIMEs of all nodes by AMOUNT. Set the values of
345+ SCHED_ROW and SCHED_STAGE. */
346 static void
347-normalize_sched_times (partial_schedule_ptr ps)
348+reset_sched_times (partial_schedule_ptr ps, int amount)
349 {
350 int row;
351- int amount = PS_MIN_CYCLE (ps);
352 int ii = ps->ii;
353 ps_insn_ptr crr_insn;
354
355@@ -584,19 +586,43 @@
356 {
357 ddg_node_ptr u = crr_insn->node;
358 int normalized_time = SCHED_TIME (u) - amount;
359+ int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
360+ int sc_until_cycle_zero, stage;
361
362- if (dump_file)
363- fprintf (dump_file, "crr_insn->node=%d, crr_insn->cycle=%d,\
364- min_cycle=%d\n", crr_insn->node->cuid, SCHED_TIME
365- (u), ps->min_cycle);
366+ if (dump_file)
367+ {
368+ /* Print the scheduling times after the rotation. */
369+ fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
370+ "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
371+ INSN_UID (crr_insn->node->insn), SCHED_TIME (u),
372+ normalized_time);
373+ if (JUMP_P (crr_insn->node->insn))
374+ fprintf (dump_file, " (branch)");
375+ fprintf (dump_file, "\n");
376+ }
377+
378 gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
379 gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
380 SCHED_TIME (u) = normalized_time;
381- SCHED_ROW (u) = normalized_time % ii;
382- SCHED_STAGE (u) = normalized_time / ii;
383+ SCHED_ROW (u) = SMODULO (normalized_time, ii);
384+
385+ /* The calculation of stage count is done adding the number
386+ of stages before cycle zero and after cycle zero. */
387+ sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii);
388+
389+ if (SCHED_TIME (u) < 0)
390+ {
391+ stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
392+ SCHED_STAGE (u) = sc_until_cycle_zero - stage;
393+ }
394+ else
395+ {
396+ stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
397+ SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
398+ }
399 }
400 }
401-
402+
403 /* Set SCHED_COLUMN of each node according to its position in PS. */
404 static void
405 set_columns_for_ps (partial_schedule_ptr ps)
406@@ -646,9 +672,12 @@
407
408 /* Do not duplicate any insn which refers to count_reg as it
409 belongs to the control part.
410+ The closing branch is scheduled as well and thus should
411+ be ignored.
412 TODO: This should be done by analyzing the control part of
413 the loop. */
414- if (reg_mentioned_p (count_reg, u_node->insn))
415+ if (reg_mentioned_p (count_reg, u_node->insn)
416+ || JUMP_P (ps_ij->node->insn))
417 continue;
418
419 if (for_prolog)
420@@ -1009,9 +1038,11 @@
421 continue;
422 }
423
424- /* Don't handle BBs with calls or barriers, or !single_set insns,
425- or auto-increment insns (to avoid creating invalid reg-moves
426- for the auto-increment insns).
427+ /* Don't handle BBs with calls or barriers or auto-increment insns
428+ (to avoid creating invalid reg-moves for the auto-increment insns),
429+ or !single_set with the exception of instructions that include
430+ count_reg---these instructions are part of the control part
431+ that do-loop recognizes.
432 ??? Should handle auto-increment insns.
433 ??? Should handle insns defining subregs. */
434 for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn))
435@@ -1021,7 +1052,8 @@
436 if (CALL_P (insn)
437 || BARRIER_P (insn)
438 || (NONDEBUG_INSN_P (insn) && !JUMP_P (insn)
439- && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE)
440+ && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE
441+ && !reg_mentioned_p (count_reg, insn))
442 || (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0)
443 || (INSN_P (insn) && (set = single_set (insn))
444 && GET_CODE (SET_DEST (set)) == SUBREG))
445@@ -1049,7 +1081,11 @@
446 continue;
447 }
448
449- if (! (g = create_ddg (bb, 0)))
450+ /* Always schedule the closing branch with the rest of the
451+ instructions. The branch is rotated to be in row ii-1 at the
452+ end of the scheduling procedure to make sure it's the last
453+ instruction in the iteration. */
454+ if (! (g = create_ddg (bb, 1)))
455 {
456 if (dump_file)
457 fprintf (dump_file, "SMS create_ddg failed\n");
458@@ -1157,14 +1193,17 @@
459
460 ps = sms_schedule_by_order (g, mii, maxii, node_order);
461
462- if (ps){
463- stage_count = PS_STAGE_COUNT (ps);
464- gcc_assert(stage_count >= 1);
465- }
466+ if (ps)
467+ {
468+ stage_count = calculate_stage_count (ps);
469+ gcc_assert(stage_count >= 1);
470+ PS_STAGE_COUNT(ps) = stage_count;
471+ }
472
473- /* Stage count of 1 means that there is no interleaving between
474- iterations, let the scheduling passes do the job. */
475- if (stage_count <= 1
476+ /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
477+ 1 means that there is no interleaving between iterations thus
478+ we let the scheduling passes do the job in this case. */
479+ if (stage_count < (unsigned) PARAM_VALUE (PARAM_SMS_MIN_SC)
480 || (count_init && (loop_count <= stage_count))
481 || (flag_branch_probabilities && (trip_count <= stage_count)))
482 {
483@@ -1182,32 +1221,24 @@
484 else
485 {
486 struct undo_replace_buff_elem *reg_move_replaces;
487-
488- if (dump_file)
489- {
490+ int amount = SCHED_TIME (g->closing_branch) + 1;
491+
492+ /* Set the stage boundaries. The closing_branch was scheduled
493+ and should appear in the last (ii-1) row. */
494+ reset_sched_times (ps, amount);
495+ rotate_partial_schedule (ps, amount);
496+ set_columns_for_ps (ps);
497+
498+ canon_loop (loop);
499+
500+ if (dump_file)
501+ {
502 fprintf (dump_file,
503 "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
504 stage_count);
505 print_partial_schedule (ps, dump_file);
506- fprintf (dump_file,
507- "SMS Branch (%d) will later be scheduled at cycle %d.\n",
508- g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1);
509 }
510-
511- /* Set the stage boundaries. If the DDG is built with closing_branch_deps,
512- the closing_branch was scheduled and should appear in the last (ii-1)
513- row. Otherwise, we are free to schedule the branch, and we let nodes
514- that were scheduled at the first PS_MIN_CYCLE cycle appear in the first
515- row; this should reduce stage_count to minimum.
516- TODO: Revisit the issue of scheduling the insns of the
517- control part relative to the branch when the control part
518- has more than one insn. */
519- normalize_sched_times (ps);
520- rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
521- set_columns_for_ps (ps);
522-
523- canon_loop (loop);
524-
525+
526 /* case the BCT count is not known , Do loop-versioning */
527 if (count_reg && ! count_init)
528 {
529@@ -1760,12 +1791,6 @@
530 continue;
531 }
532
533- if (JUMP_P (insn)) /* Closing branch handled later. */
534- {
535- RESET_BIT (tobe_scheduled, u);
536- continue;
537- }
538-
539 if (TEST_BIT (sched_nodes, u))
540 continue;
541
542@@ -1893,8 +1918,8 @@
543 if (dump_file)
544 fprintf (dump_file, "split_row=%d\n", split_row);
545
546- normalize_sched_times (ps);
547- rotate_partial_schedule (ps, ps->min_cycle);
548+ reset_sched_times (ps, PS_MIN_CYCLE (ps));
549+ rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
550
551 rows_new = (ps_insn_ptr *) xcalloc (new_ii, sizeof (ps_insn_ptr));
552 for (row = 0; row < split_row; row++)
553@@ -2571,6 +2596,7 @@
554 ps_insn_ptr next_ps_i;
555 ps_insn_ptr first_must_follow = NULL;
556 ps_insn_ptr last_must_precede = NULL;
557+ ps_insn_ptr last_in_row = NULL;
558 int row;
559
560 if (! ps_i)
561@@ -2597,8 +2623,37 @@
562 else
563 last_must_precede = next_ps_i;
564 }
565+ /* The closing branch must be the last in the row. */
566+ if (must_precede
567+ && TEST_BIT (must_precede, next_ps_i->node->cuid)
568+ && JUMP_P (next_ps_i->node->insn))
569+ return false;
570+
571+ last_in_row = next_ps_i;
572 }
573
574+ /* The closing branch is scheduled as well. Make sure there is no
575+ dependent instruction after it as the branch should be the last
576+ instruction in the row. */
577+ if (JUMP_P (ps_i->node->insn))
578+ {
579+ if (first_must_follow)
580+ return false;
581+ if (last_in_row)
582+ {
583+ /* Make the branch the last in the row. New instructions
584+ will be inserted at the beginning of the row or after the
585+ last must_precede instruction thus the branch is guaranteed
586+ to remain the last instruction in the row. */
587+ last_in_row->next_in_row = ps_i;
588+ ps_i->prev_in_row = last_in_row;
589+ ps_i->next_in_row = NULL;
590+ }
591+ else
592+ ps->rows[row] = ps_i;
593+ return true;
594+ }
595+
596 /* Now insert the node after INSERT_AFTER_PSI. */
597
598 if (! last_must_precede)
599@@ -2820,6 +2875,24 @@
600 return ps_i;
601 }
602
603+/* Calculate the stage count of the partial schedule PS. The calculation
604+ takes into account the rotation to bring the closing branch to row
605+ ii-1. */
606+int
607+calculate_stage_count (partial_schedule_ptr ps)
608+{
609+ int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1;
610+ int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
611+ int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
612+ int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii);
613+
614+ /* The calculation of stage count is done adding the number of stages
615+ before cycle zero and after cycle zero. */
616+ stage_count += CALC_STAGE_COUNT (new_max_cycle, 0, ps->ii);
617+
618+ return stage_count;
619+}
620+
621 /* Rotate the rows of PS such that insns scheduled at time
622 START_CYCLE will appear in row 0. Updates max/min_cycles. */
623 void
624
625=== modified file 'gcc/params.def'
626--- old/gcc/params.def 2011-04-18 11:31:29 +0000
627+++ new/gcc/params.def 2011-05-11 07:15:47 +0000
628@@ -344,6 +344,11 @@
629 "sms-max-ii-factor",
630 "A factor for tuning the upper bound that swing modulo scheduler uses for scheduling a loop",
631 100, 0, 0)
632+/* The minimum value of stage count that swing modulo scheduler will generate. */
633+DEFPARAM(PARAM_SMS_MIN_SC,
634+ "sms-min-sc",
635+ "The minimum value of stage count that swing modulo scheduler will generate.",
636+ 2, 1, 1)
637 DEFPARAM(PARAM_SMS_DFA_HISTORY,
638 "sms-dfa-history",
639 "The number of cycles the swing modulo scheduler considers when checking conflicts using DFA",
640
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106750.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106750.patch
deleted file mode 100644
index 9c62102db..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106750.patch
+++ /dev/null
@@ -1,30 +0,0 @@
1 2011-05-13 Revital Eres <revital.eres@linaro.org>
2
3 gcc/
4 * ddg.c (free_ddg_all_sccs): Free sccs field in struct ddg_all_sccs.
5 * modulo-sched.c (sms_schedule): Avoid unfreed memory when SMS fails.
6
7=== modified file 'gcc/ddg.c'
8--- old/gcc/ddg.c 2011-05-11 07:15:47 +0000
9+++ new/gcc/ddg.c 2011-05-13 16:03:40 +0000
10@@ -1016,6 +1016,7 @@
11 for (i = 0; i < all_sccs->num_sccs; i++)
12 free_scc (all_sccs->sccs[i]);
13
14+ free (all_sccs->sccs);
15 free (all_sccs);
16 }
17
18
19=== modified file 'gcc/modulo-sched.c'
20--- old/gcc/modulo-sched.c 2011-05-11 07:15:47 +0000
21+++ new/gcc/modulo-sched.c 2011-05-13 16:03:40 +0000
22@@ -1216,7 +1216,6 @@
23 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count);
24 fprintf (dump_file, ")\n");
25 }
26- continue;
27 }
28 else
29 {
30
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106751.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106751.patch
deleted file mode 100644
index c26ee5bde..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106751.patch
+++ /dev/null
@@ -1,134 +0,0 @@
12011-06-02 Chung-Lin Tang <cltang@codesourcery.com>
2
3 Backport from mainline:
4
5 2011-03-21 Chung-Lin Tang <cltang@codesourcery.com>
6
7 gcc/
8 * simplify-rtx.c (simplify_binary_operation_1): Handle
9 (xor (and A B) C) case when B and C are both constants.
10
11 gcc/testsuite/
12 * gcc.target/arm/xor-and.c: New.
13
14 2011-03-18 Chung-Lin Tang <cltang@codesourcery.com>
15
16 gcc/
17 * combine.c (try_combine): Do simplification only call of
18 subst() on i2 even when i1 is present. Update comments.
19
20 gcc/testsuite/
21 * gcc.target/arm/unsigned-extend-1.c: New.
22
23=== modified file 'gcc/combine.c'
24--- old/gcc/combine.c 2011-05-06 11:28:27 +0000
25+++ new/gcc/combine.c 2011-05-27 14:31:18 +0000
26@@ -3089,7 +3089,7 @@
27 /* It is possible that the source of I2 or I1 may be performing
28 an unneeded operation, such as a ZERO_EXTEND of something
29 that is known to have the high part zero. Handle that case
30- by letting subst look at the innermost one of them.
31+ by letting subst look at the inner insns.
32
33 Another way to do this would be to have a function that tries
34 to simplify a single insn instead of merging two or more
35@@ -3114,11 +3114,9 @@
36 subst_low_luid = DF_INSN_LUID (i1);
37 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
38 }
39- else
40- {
41- subst_low_luid = DF_INSN_LUID (i2);
42- i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
43- }
44+
45+ subst_low_luid = DF_INSN_LUID (i2);
46+ i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
47 }
48
49 n_occurrences = 0; /* `subst' counts here */
50
51=== modified file 'gcc/simplify-rtx.c'
52--- old/gcc/simplify-rtx.c 2011-03-26 09:24:06 +0000
53+++ new/gcc/simplify-rtx.c 2011-05-27 14:31:18 +0000
54@@ -2484,6 +2484,46 @@
55 XEXP (op0, 1), mode),
56 op1);
57
58+ /* Given (xor (and A B) C), using P^Q == (~P&Q) | (~Q&P),
59+ we can transform like this:
60+ (A&B)^C == ~(A&B)&C | ~C&(A&B)
61+ == (~A|~B)&C | ~C&(A&B) * DeMorgan's Law
62+ == ~A&C | ~B&C | A&(~C&B) * Distribute and re-order
63+ Attempt a few simplifications when B and C are both constants. */
64+ if (GET_CODE (op0) == AND
65+ && CONST_INT_P (op1)
66+ && CONST_INT_P (XEXP (op0, 1)))
67+ {
68+ rtx a = XEXP (op0, 0);
69+ rtx b = XEXP (op0, 1);
70+ rtx c = op1;
71+ HOST_WIDE_INT bval = INTVAL (b);
72+ HOST_WIDE_INT cval = INTVAL (c);
73+
74+ rtx na_c
75+ = simplify_binary_operation (AND, mode,
76+ simplify_gen_unary (NOT, mode, a, mode),
77+ c);
78+ if ((~cval & bval) == 0)
79+ {
80+ /* Try to simplify ~A&C | ~B&C. */
81+ if (na_c != NULL_RTX)
82+ return simplify_gen_binary (IOR, mode, na_c,
83+ GEN_INT (~bval & cval));
84+ }
85+ else
86+ {
87+ /* If ~A&C is zero, simplify A&(~C&B) | ~B&C. */
88+ if (na_c == const0_rtx)
89+ {
90+ rtx a_nc_b = simplify_gen_binary (AND, mode, a,
91+ GEN_INT (~cval & bval));
92+ return simplify_gen_binary (IOR, mode, a_nc_b,
93+ GEN_INT (~bval & cval));
94+ }
95+ }
96+ }
97+
98 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
99 comparison if STORE_FLAG_VALUE is 1. */
100 if (STORE_FLAG_VALUE == 1
101
102=== added file 'gcc/testsuite/gcc.target/arm/unsigned-extend-1.c'
103--- old/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c 1970-01-01 00:00:00 +0000
104+++ new/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c 2011-05-27 14:31:18 +0000
105@@ -0,0 +1,9 @@
106+/* { dg-do compile } */
107+/* { dg-options "-O2 -march=armv6" } */
108+
109+unsigned char foo (unsigned char c)
110+{
111+ return (c >= '0') && (c <= '9');
112+}
113+
114+/* { dg-final { scan-assembler-not "uxtb" } } */
115
116=== added file 'gcc/testsuite/gcc.target/arm/xor-and.c'
117--- old/gcc/testsuite/gcc.target/arm/xor-and.c 1970-01-01 00:00:00 +0000
118+++ new/gcc/testsuite/gcc.target/arm/xor-and.c 2011-05-27 14:31:18 +0000
119@@ -0,0 +1,14 @@
120+/* { dg-do compile } */
121+/* { dg-options "-O -march=armv6" } */
122+
123+unsigned short foo (unsigned short x)
124+{
125+ x ^= 0x4002;
126+ x >>= 1;
127+ x |= 0x8000;
128+ return x;
129+}
130+
131+/* { dg-final { scan-assembler "orr" } } */
132+/* { dg-final { scan-assembler-not "mvn" } } */
133+/* { dg-final { scan-assembler-not "uxth" } } */
134
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106753.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106753.patch
deleted file mode 100644
index bda39e8fa..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106753.patch
+++ /dev/null
@@ -1,5027 +0,0 @@
12001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 * gimple.c (gimple_build_call_internal_1): Add missing call to
5 gimple_call_reset_alias_info.
6
72001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
8
9 gcc/testsuite/
10 Backport from mainline:
11
12 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
13
14 * gcc.dg/vect/vect-strided-u16-i3.c: New test.
15
162001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
17
18 gcc/testsuite/
19 Backport from mainline:
20
21 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
22
23 * lib/target-supports.exp (check_effective_target_vect_strided):
24 Replace with...
25 (check_effective_target_vect_strided2)
26 (check_effective_target_vect_strided3)
27 (check_effective_target_vect_strided4)
28 (check_effective_target_vect_strided8): ...these new functions.
29
30 * gcc.dg/vect/O3-pr39675-2.c: Update accordingly.
31 * gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c: Likewise.
32 * gcc.dg/vect/fast-math-slp-27.c: Likewise.
33 * gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c: Likewise.
34 * gcc.dg/vect/pr37539.c: Likewise.
35 * gcc.dg/vect/slp-11a.c: Likewise.
36 * gcc.dg/vect/slp-11b.c: Likewise.
37 * gcc.dg/vect/slp-11c.c: Likewise.
38 * gcc.dg/vect/slp-12a.c: Likewise.
39 * gcc.dg/vect/slp-12b.c: Likewise.
40 * gcc.dg/vect/slp-18.c: Likewise.
41 * gcc.dg/vect/slp-19a.c: Likewise.
42 * gcc.dg/vect/slp-19b.c: Likewise.
43 * gcc.dg/vect/slp-21.c: Likewise.
44 * gcc.dg/vect/slp-23.c: Likewise.
45 * gcc.dg/vect/vect-cselim-1.c: Likewise.
46
47 * gcc.dg/vect/fast-math-vect-complex-3.c: Use vect_stridedN
48 instead of vect_interleave && vect_extract_even_odd.
49 * gcc.dg/vect/no-scevccp-outer-10a.c: Likewise.
50 * gcc.dg/vect/no-scevccp-outer-10b.c: Likewise.
51 * gcc.dg/vect/no-scevccp-outer-20.c: Likewise.
52 * gcc.dg/vect/vect-1.c: Likewise.
53 * gcc.dg/vect/vect-10.c: Likewise.
54 * gcc.dg/vect/vect-98.c: Likewise.
55 * gcc.dg/vect/vect-107.c: Likewise.
56 * gcc.dg/vect/vect-strided-a-mult.c: Likewise.
57 * gcc.dg/vect/vect-strided-a-u16-i2.c: Likewise.
58 * gcc.dg/vect/vect-strided-a-u16-i4.c: Likewise.
59 * gcc.dg/vect/vect-strided-a-u16-mult.c: Likewise.
60 * gcc.dg/vect/vect-strided-a-u32-mult.c: Likewise.
61 * gcc.dg/vect/vect-strided-a-u8-i2-gap.c: Likewise.
62 * gcc.dg/vect/vect-strided-a-u8-i8-gap2.c: Likewise.
63 * gcc.dg/vect/vect-strided-a-u8-i8-gap7.c: Likewise.
64 * gcc.dg/vect/vect-strided-float.c: Likewise.
65 * gcc.dg/vect/vect-strided-mult-char-ls.c: Likewise.
66 * gcc.dg/vect/vect-strided-mult.c: Likewise.
67 * gcc.dg/vect/vect-strided-same-dr.c: Likewise.
68 * gcc.dg/vect/vect-strided-u16-i2.c: Likewise.
69 * gcc.dg/vect/vect-strided-u16-i4.c: Likewise.
70 * gcc.dg/vect/vect-strided-u32-i4.c: Likewise.
71 * gcc.dg/vect/vect-strided-u32-i8.c: Likewise.
72 * gcc.dg/vect/vect-strided-u32-mult.c: Likewise.
73 * gcc.dg/vect/vect-strided-u8-i2-gap.c: Likewise.
74 * gcc.dg/vect/vect-strided-u8-i2.c: Likewise.
75 * gcc.dg/vect/vect-strided-u8-i8-gap2.c: Likewise.
76 * gcc.dg/vect/vect-strided-u8-i8-gap4.c: Likewise.
77 * gcc.dg/vect/vect-strided-u8-i8-gap7.c: Likewise.
78 * gcc.dg/vect/vect-strided-u8-i8.c: Likewise.
79 * gcc.dg/vect/vect-vfa-03.c: Likewise.
80
81 * gcc.dg/vect/no-scevccp-outer-18.c: Add vect_stridedN to the
82 target condition.
83 * gcc.dg/vect/pr30843.c: Likewise.
84 * gcc.dg/vect/pr33866.c: Likewise.
85 * gcc.dg/vect/slp-reduc-6.c: Likewise.
86 * gcc.dg/vect/vect-strided-store-a-u8-i2.c: Likewise.
87 * gcc.dg/vect/vect-strided-store-u16-i4.c: Likewise.
88 * gcc.dg/vect/vect-strided-store-u32-i2.c: Likewise.
89
902001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
91
92 gcc/testsuite/
93 Backport from mainline:
94
95 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
96
97 * gcc.dg/vect/slp-11.c: Split into...
98 * gcc.dg/vect/slp-11a.c, gcc.dg/vect/slp-11b.c,
99 gcc.dg/vect/slp-11c.c: ...these tests.
100 * gcc.dg/vect/slp-12a.c: Split 4-stride loop into...
101 * gcc.dg/vect/slp-12c.c: ...this new test.
102 * gcc.dg/vect/slp-19.c: Split into...
103 * gcc.dg/vect/slp-19a.c, gcc.dg/vect/slp-19b.c,
104 gcc.dg/vect/slp-19c.c: ...these new tests.
105
1062001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
107
108 gcc/testsuite/
109 Backport from mainline:
110
111 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
112
113 * lib/target-supports.exp
114 (check_effective_target_vect_extract_even_odd_wide): Delete.
115 (check_effective_target_vect_strided_wide): Likewise.
116 * gcc.dg/vect/O3-pr39675-2.c: Use the non-wide versions instead.
117 * gcc.dg/vect/fast-math-pr35982.c: Likewise.
118 * gcc.dg/vect/fast-math-vect-complex-3.c: Likewise.
119 * gcc.dg/vect/pr37539.c: Likewise.
120 * gcc.dg/vect/slp-11.c: Likewise.
121 * gcc.dg/vect/slp-12a.c: Likewise.
122 * gcc.dg/vect/slp-12b.c: Likewise.
123 * gcc.dg/vect/slp-19.c: Likewise.
124 * gcc.dg/vect/slp-23.c: Likewise.
125 * gcc.dg/vect/vect-1.c: Likewise.
126 * gcc.dg/vect/vect-98.c: Likewise.
127 * gcc.dg/vect/vect-107.c: Likewise.
128 * gcc.dg/vect/vect-strided-float.c: Likewise.
129
1302001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
131
132 gcc/testsuite/
133 Backport from mainline:
134
135 2011-04-21 Richard Sandiford <richard.sandiford@linaro.org>
136
137 * gcc.dg/vect/vect.exp: Run the main tests twice, one with -flto
138 and once without.
139
1402001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
141
142 gcc/
143 Backport from mainlie:
144
145 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
146
147 * config/arm/neon.md (vec_load_lanes<mode><mode>): New expanders,
148 (vec_store_lanes<mode><mode>): Likewise.
149
1502001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
151
152 gcc/
153 Backport from mainline:
154
155 2011-05-03 Richard Sandiford <richard.sandiford@linaro.org>
156
157 * doc/md.texi (vec_load_lanes, vec_store_lanes): Document.
158 * optabs.h (COI_vec_load_lanes, COI_vec_store_lanes): New
159 convert_optab_index values.
160 (vec_load_lanes_optab, vec_store_lanes_optab): New convert optabs.
161 * genopinit.c (optabs): Initialize the new optabs.
162 * internal-fn.def (LOAD_LANES, STORE_LANES): New internal functions.
163 * internal-fn.c (get_multi_vector_move, expand_LOAD_LANES)
164 (expand_STORE_LANES): New functions.
165 * tree.h (build_array_type_nelts): Declare.
166 * tree.c (build_array_type_nelts): New function.
167 * tree-vectorizer.h (vect_model_store_cost): Add a bool argument.
168 (vect_model_load_cost): Likewise.
169 (vect_store_lanes_supported, vect_load_lanes_supported)
170 (vect_record_strided_load_vectors): Declare.
171 * tree-vect-data-refs.c (vect_lanes_optab_supported_p)
172 (vect_store_lanes_supported, vect_load_lanes_supported): New functions.
173 (vect_transform_strided_load): Split out statement recording into...
174 (vect_record_strided_load_vectors): ...this new function.
175 * tree-vect-stmts.c (create_vector_array, read_vector_array)
176 (write_vector_array, create_array_ref): New functions.
177 (vect_model_store_cost): Add store_lanes_p argument.
178 (vect_model_load_cost): Add load_lanes_p argument.
179 (vectorizable_store): Try to use store-lanes functions for
180 interleaved stores.
181 (vectorizable_load): Likewise load-lanes and loads.
182 * tree-vect-slp.c (vect_get_and_check_slp_defs): Update call
183 to vect_model_store_cost.
184 (vect_build_slp_tree): Likewise vect_model_load_cost.
185
1862001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
187
188 gcc/
189 Backport from mainline:
190
191 2011-04-20 Richard Sandiford <richard.sandiford@linaro.org>
192
193 * tree-vect-stmts.c (vectorizable_store): Only chain one related
194 statement per copy.
195
1962001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
197
198 gcc/
199 * tree-inline.c (estimate_num_insns): Likewise.
200
201 Backport from mainline:
202
203 2011-04-20 Richard Sandiford <richard.sandiford@linaro.org>
204
205 * Makefile.in (INTERNAL_FN_DEF, INTERNAL_FN_H): Define.
206 (GIMPLE_H): Include $(INTERNAL_FN_H).
207 (OBJS-common): Add internal-fn.o.
208 (internal-fn.o): New rule.
209 * internal-fn.def: New file.
210 * internal-fn.h: Likewise.
211 * internal-fn.c: Likewise.
212 * gimple.h: Include internal-fn.h.
213 (GF_CALL_INTERNAL): New gf_mask.
214 (gimple_statement_call): Put fntype into a union with a new
215 internal_fn field.
216 (gimple_build_call_internal): Declare.
217 (gimple_build_call_internal_vec): Likewise.
218 (gimple_call_same_target_p): Likewise.
219 (gimple_call_internal_p): New function.
220 (gimple_call_internal_fn): Likewise.
221 (gimple_call_set_fn): Assert that the function is not internal.
222 (gimple_call_set_fndecl): Likewise.
223 (gimple_call_set_internal_fn): New function.
224 (gimple_call_addr_fndecl): Handle null functions.
225 (gimple_call_return_type): Likewise.
226 [---- Plus backport adjustments:
227 (GF_CALL_INTERNAL_FN_SHIFT): New macro.
228 (GF_CALL_INTERNAL_FN): New gf_mask.
229 ----]
230 * gimple.c (gimple_build_call_internal_1): New function.
231 (gimple_build_call_internal): Likewise.
232 (gimple_build_call_internal_vec): Likewise.
233 (gimple_call_same_target_p): Likewise.
234 (gimple_call_flags): Handle calls to internal functions.
235 (gimple_call_fnspec): New function.
236 (gimple_call_arg_flags, gimple_call_return_flags): Use it.
237 (gimple_has_side_effects): Handle null functions.
238 (gimple_rhs_has_side_effects): Likewise.
239 (gimple_call_copy_skip_args): Handle calls to internal functions.
240 * cfgexpand.c (expand_call_stmt): Likewise.
241 * expr.c (expand_expr_real_1): Assert that the call isn't internal.
242 * gimple-low.c (gimple_check_call_args): Handle calls to internal
243 functions.
244 * gimple-pretty-print.c (dump_gimple_call): Likewise.
245 * ipa-prop.c (ipa_analyze_call_uses): Handle null functions.
246 * tree-cfg.c (verify_gimple_call): Handle calls to internal functions.
247 (do_warn_unused_result): Likewise.
248 [---- Plus backport adjustments:
249 (verify_stmt): Likewise.
250 ----]
251 * tree-eh.c (same_handler_p): Use gimple_call_same_target_p.
252 * tree-ssa-ccp.c (ccp_fold_stmt): Handle calls to internal functions.
253 [---- Plus backport adjustments:
254 (fold_gimple_call): Likewise.
255 ----]
256 * tree-ssa-dom.c (hashable_expr): Use the gimple statement to record
257 the target of a call.
258 (initialize_hash_element): Update accordingly.
259 (hashable_expr_equal_p): Use gimple_call_same_target_p.
260 (iterative_hash_hashable_expr): Handle calls to internal functions.
261 (print_expr_hash_elt): Likewise.
262 * tree-ssa-pre.c (can_value_number_call): Likewise.
263 (eliminate): Handle null functions.
264 * tree-ssa-sccvn.c (visit_use): Handle calls to internal functions.
265 * tree-ssa-structalias.c (find_func_aliases): Likewise.
266 * value-prof.c (gimple_ic_transform): Likewise.
267 (gimple_indirect_call_to_profile): Likewise.
268
2692001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
270
271 gcc/
272 Backport from mainline:
273
274 2011-04-14 Richard Sandiford <richard.sandiford@linaro.org>
275
276 * tree-vectorizer.h (vect_strided_store_supported): Add a
277 HOST_WIDE_INT argument.
278 (vect_strided_load_supported): Likewise.
279 (vect_permute_store_chain): Return void.
280 (vect_transform_strided_load): Likewise.
281 (vect_permute_load_chain): Delete.
282 * tree-vect-data-refs.c (vect_strided_store_supported): Take a
283 count argument. Check that the count is a power of two.
284 (vect_strided_load_supported): Likewise.
285 (vect_permute_store_chain): Return void. Update after above changes.
286 Assert that the access is supported.
287 (vect_permute_load_chain): Likewise.
288 (vect_transform_strided_load): Return void.
289 * tree-vect-stmts.c (vectorizable_store): Update calls after
290 above interface changes.
291 (vectorizable_load): Likewise.
292 (vect_analyze_stmt): Don't check for strided powers of two here.
293
2942001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
295
296 gcc/
297 Backport from mainline:
298
299 2011-04-14 Richard Sandiford <richard.sandiford@linaro.org>
300
301 * tree-vectorizer.h (vect_create_data_ref_ptr): Add an extra
302 type parameter.
303 * tree-vect-data-refs.c (vect_create_data_ref_ptr): Add an aggr_type
304 parameter. Generalise code to handle arrays as well as vectors.
305 (vect_setup_realignment): Update accordingly.
306 * tree-vect-stmts.c (vectorizable_store): Likewise.
307 (vectorizable_load): Likewise.
308
3092001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
310
311 gcc/
312 Backport from mainline:
313
314 2011-04-14 Richard Sandiford <richard.sandiford@linaro.org>
315
316 * tree-vect-stmts.c (vectorizable_load): Allocate and free dr_chain
317 within the per-copy loop.
318
3192001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
320
321 gcc/
322 Backport from mainline:
323
324 2011-04-14 Richard Sandiford <richard.sandiford@linaro.org>
325
326 * tree-vect-stmts.c (vectorizable_load): Print the number of copies
327 in the dump file.
328
3292001-06-02 Richard Sandiford <richard.sandiford@linaro.org>
330
331 gcc/
332 Backport from mainline:
333
334 2011-03-25 Richard Sandiford <richard.sandiford@linaro.org>
335
336 * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Restrict FPA_REGS
337 case to VFPv1.
338
339=== modified file 'gcc/Makefile.in'
340--- old/gcc/Makefile.in 2011-05-26 14:27:33 +0000
341+++ new/gcc/Makefile.in 2011-06-02 12:12:00 +0000
342@@ -888,6 +888,8 @@
343 READ_MD_H = $(OBSTACK_H) $(HASHTAB_H) read-md.h
344 PARAMS_H = params.h params.def
345 BUILTINS_DEF = builtins.def sync-builtins.def omp-builtins.def
346+INTERNAL_FN_DEF = internal-fn.def
347+INTERNAL_FN_H = internal-fn.h $(INTERNAL_FN_DEF)
348 TREE_H = tree.h all-tree.def tree.def c-family/c-common.def \
349 $(lang_tree_files) $(MACHMODE_H) tree-check.h $(BUILTINS_DEF) \
350 $(INPUT_H) statistics.h $(VEC_H) treestruct.def $(HASHTAB_H) \
351@@ -897,7 +899,7 @@
352 BASIC_BLOCK_H = basic-block.h $(PREDICT_H) $(VEC_H) $(FUNCTION_H) cfghooks.h
353 GIMPLE_H = gimple.h gimple.def gsstruct.def pointer-set.h $(VEC_H) \
354 $(GGC_H) $(BASIC_BLOCK_H) $(TARGET_H) tree-ssa-operands.h \
355- tree-ssa-alias.h vecir.h
356+ tree-ssa-alias.h vecir.h $(INTERNAL_FN_H)
357 GCOV_IO_H = gcov-io.h gcov-iov.h auto-host.h
358 COVERAGE_H = coverage.h $(GCOV_IO_H)
359 DEMANGLE_H = $(srcdir)/../include/demangle.h
360@@ -1269,6 +1271,7 @@
361 init-regs.o \
362 input.o \
363 integrate.o \
364+ internal-fn.o \
365 intl.o \
366 ira.o \
367 ira-build.o \
368@@ -2751,6 +2754,8 @@
369 $(TM_H) $(TREE_H) $(DIAGNOSTIC_CORE_H) $(DIAGNOSTIC_H) $(TREE_FLOW_H) \
370 $(TREE_PASS_H) tree-ssa-propagate.h tree-pretty-print.h \
371 gimple-pretty-print.h
372+internal-fn.o : internal-fn.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
373+ $(GIMPLE_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) $(RECOG_H)
374 gimple.o : gimple.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TREE_H) \
375 $(GGC_H) $(GIMPLE_H) $(DIAGNOSTIC_CORE_H) $(DIAGNOSTIC_H) gt-gimple.h \
376 $(TREE_FLOW_H) value-prof.h $(FLAGS_H) $(DEMANGLE_H) \
377
378=== modified file 'gcc/cfgexpand.c'
379--- old/gcc/cfgexpand.c 2011-04-20 11:18:50 +0000
380+++ new/gcc/cfgexpand.c 2011-06-02 12:12:00 +0000
381@@ -1839,12 +1839,17 @@
382 static void
383 expand_call_stmt (gimple stmt)
384 {
385- tree exp;
386- tree lhs = gimple_call_lhs (stmt);
387+ tree exp, lhs;
388 size_t i;
389 bool builtin_p;
390 tree decl;
391
392+ if (gimple_call_internal_p (stmt))
393+ {
394+ expand_internal_call (stmt);
395+ return;
396+ }
397+
398 exp = build_vl_exp (CALL_EXPR, gimple_call_num_args (stmt) + 3);
399
400 CALL_EXPR_FN (exp) = gimple_call_fn (stmt);
401@@ -1882,6 +1887,7 @@
402 SET_EXPR_LOCATION (exp, gimple_location (stmt));
403 TREE_BLOCK (exp) = gimple_block (stmt);
404
405+ lhs = gimple_call_lhs (stmt);
406 if (lhs)
407 expand_assignment (lhs, exp, false);
408 else
409
410=== modified file 'gcc/config/arm/arm.h'
411--- old/gcc/config/arm/arm.h 2011-04-26 14:42:21 +0000
412+++ new/gcc/config/arm/arm.h 2011-06-02 12:12:00 +0000
413@@ -1169,12 +1169,12 @@
414 }
415
416 /* FPA registers can't do subreg as all values are reformatted to internal
417- precision. VFP registers may only be accessed in the mode they
418- were set. */
419-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
420- (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
421- ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
422- || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
423+ precision. In VFPv1, VFP registers could only be accessed in the mode
424+ they were set, so subregs would be invalid there too. However, we don't
425+ support VFPv1 at the moment, and the restriction was lifted in VFPv2. */
426+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
427+ (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
428+ ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
429 : 0)
430
431 /* The class value for index registers, and the one for base regs. */
432
433=== modified file 'gcc/config/arm/neon.md'
434--- old/gcc/config/arm/neon.md 2011-05-06 11:28:27 +0000
435+++ new/gcc/config/arm/neon.md 2011-06-02 12:12:00 +0000
436@@ -4248,6 +4248,12 @@
437 DONE;
438 })
439
440+(define_expand "vec_load_lanes<mode><mode>"
441+ [(set (match_operand:VDQX 0 "s_register_operand")
442+ (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand")]
443+ UNSPEC_VLD1))]
444+ "TARGET_NEON")
445+
446 (define_insn "neon_vld1<mode>"
447 [(set (match_operand:VDQX 0 "s_register_operand" "=w")
448 (unspec:VDQX [(match_operand:VDQX 1 "neon_struct_operand" "Um")]
449@@ -4345,6 +4351,12 @@
450 (const_string "neon_vld1_1_2_regs")))]
451 )
452
453+(define_expand "vec_store_lanes<mode><mode>"
454+ [(set (match_operand:VDQX 0 "neon_struct_operand")
455+ (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand")]
456+ UNSPEC_VST1))]
457+ "TARGET_NEON")
458+
459 (define_insn "neon_vst1<mode>"
460 [(set (match_operand:VDQX 0 "neon_struct_operand" "=Um")
461 (unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" "w")]
462@@ -4401,6 +4413,13 @@
463 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
464 )
465
466+(define_expand "vec_load_lanesti<mode>"
467+ [(set (match_operand:TI 0 "s_register_operand")
468+ (unspec:TI [(match_operand:TI 1 "neon_struct_operand")
469+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
470+ UNSPEC_VLD2))]
471+ "TARGET_NEON")
472+
473 (define_insn "neon_vld2<mode>"
474 [(set (match_operand:TI 0 "s_register_operand" "=w")
475 (unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um")
476@@ -4419,6 +4438,13 @@
477 (const_string "neon_vld2_2_regs_vld1_vld2_all_lanes")))]
478 )
479
480+(define_expand "vec_load_lanesoi<mode>"
481+ [(set (match_operand:OI 0 "s_register_operand")
482+ (unspec:OI [(match_operand:OI 1 "neon_struct_operand")
483+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
484+ UNSPEC_VLD2))]
485+ "TARGET_NEON")
486+
487 (define_insn "neon_vld2<mode>"
488 [(set (match_operand:OI 0 "s_register_operand" "=w")
489 (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
490@@ -4501,6 +4527,13 @@
491 (const_string "neon_vld1_1_2_regs")))]
492 )
493
494+(define_expand "vec_store_lanesti<mode>"
495+ [(set (match_operand:TI 0 "neon_struct_operand")
496+ (unspec:TI [(match_operand:TI 1 "s_register_operand")
497+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
498+ UNSPEC_VST2))]
499+ "TARGET_NEON")
500+
501 (define_insn "neon_vst2<mode>"
502 [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
503 (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
504@@ -4519,6 +4552,13 @@
505 (const_string "neon_vst1_1_2_regs_vst2_2_regs")))]
506 )
507
508+(define_expand "vec_store_lanesoi<mode>"
509+ [(set (match_operand:OI 0 "neon_struct_operand")
510+ (unspec:OI [(match_operand:OI 1 "s_register_operand")
511+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
512+ UNSPEC_VST2))]
513+ "TARGET_NEON")
514+
515 (define_insn "neon_vst2<mode>"
516 [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
517 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
518@@ -4584,6 +4624,13 @@
519 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
520 )
521
522+(define_expand "vec_load_lanesei<mode>"
523+ [(set (match_operand:EI 0 "s_register_operand")
524+ (unspec:EI [(match_operand:EI 1 "neon_struct_operand")
525+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
526+ UNSPEC_VLD3))]
527+ "TARGET_NEON")
528+
529 (define_insn "neon_vld3<mode>"
530 [(set (match_operand:EI 0 "s_register_operand" "=w")
531 (unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um")
532@@ -4602,6 +4649,16 @@
533 (const_string "neon_vld3_vld4")))]
534 )
535
536+(define_expand "vec_load_lanesci<mode>"
537+ [(match_operand:CI 0 "s_register_operand")
538+ (match_operand:CI 1 "neon_struct_operand")
539+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
540+ "TARGET_NEON"
541+{
542+ emit_insn (gen_neon_vld3<mode> (operands[0], operands[1]));
543+ DONE;
544+})
545+
546 (define_expand "neon_vld3<mode>"
547 [(match_operand:CI 0 "s_register_operand")
548 (match_operand:CI 1 "neon_struct_operand")
549@@ -4741,6 +4798,13 @@
550 (const_string "neon_vld3_vld4_all_lanes")
551 (const_string "neon_vld1_1_2_regs")))])
552
553+(define_expand "vec_store_lanesei<mode>"
554+ [(set (match_operand:EI 0 "neon_struct_operand")
555+ (unspec:EI [(match_operand:EI 1 "s_register_operand")
556+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
557+ UNSPEC_VST3))]
558+ "TARGET_NEON")
559+
560 (define_insn "neon_vst3<mode>"
561 [(set (match_operand:EI 0 "neon_struct_operand" "=Um")
562 (unspec:EI [(match_operand:EI 1 "s_register_operand" "w")
563@@ -4758,6 +4822,16 @@
564 (const_string "neon_vst1_1_2_regs_vst2_2_regs")
565 (const_string "neon_vst2_4_regs_vst3_vst4")))])
566
567+(define_expand "vec_store_lanesci<mode>"
568+ [(match_operand:CI 0 "neon_struct_operand")
569+ (match_operand:CI 1 "s_register_operand")
570+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
571+ "TARGET_NEON"
572+{
573+ emit_insn (gen_neon_vst3<mode> (operands[0], operands[1]));
574+ DONE;
575+})
576+
577 (define_expand "neon_vst3<mode>"
578 [(match_operand:CI 0 "neon_struct_operand")
579 (match_operand:CI 1 "s_register_operand")
580@@ -4869,6 +4943,13 @@
581 }
582 [(set_attr "neon_type" "neon_vst3_vst4_lane")])
583
584+(define_expand "vec_load_lanesoi<mode>"
585+ [(set (match_operand:OI 0 "s_register_operand")
586+ (unspec:OI [(match_operand:OI 1 "neon_struct_operand")
587+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
588+ UNSPEC_VLD4))]
589+ "TARGET_NEON")
590+
591 (define_insn "neon_vld4<mode>"
592 [(set (match_operand:OI 0 "s_register_operand" "=w")
593 (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
594@@ -4887,6 +4968,16 @@
595 (const_string "neon_vld3_vld4")))]
596 )
597
598+(define_expand "vec_load_lanesxi<mode>"
599+ [(match_operand:XI 0 "s_register_operand")
600+ (match_operand:XI 1 "neon_struct_operand")
601+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
602+ "TARGET_NEON"
603+{
604+ emit_insn (gen_neon_vld4<mode> (operands[0], operands[1]));
605+ DONE;
606+})
607+
608 (define_expand "neon_vld4<mode>"
609 [(match_operand:XI 0 "s_register_operand")
610 (match_operand:XI 1 "neon_struct_operand")
611@@ -5033,6 +5124,13 @@
612 (const_string "neon_vld1_1_2_regs")))]
613 )
614
615+(define_expand "vec_store_lanesoi<mode>"
616+ [(set (match_operand:OI 0 "neon_struct_operand")
617+ (unspec:OI [(match_operand:OI 1 "s_register_operand")
618+ (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
619+ UNSPEC_VST4))]
620+ "TARGET_NEON")
621+
622 (define_insn "neon_vst4<mode>"
623 [(set (match_operand:OI 0 "neon_struct_operand" "=Um")
624 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
625@@ -5051,6 +5149,16 @@
626 (const_string "neon_vst2_4_regs_vst3_vst4")))]
627 )
628
629+(define_expand "vec_store_lanesxi<mode>"
630+ [(match_operand:XI 0 "neon_struct_operand")
631+ (match_operand:XI 1 "s_register_operand")
632+ (unspec:VQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
633+ "TARGET_NEON"
634+{
635+ emit_insn (gen_neon_vst4<mode> (operands[0], operands[1]));
636+ DONE;
637+})
638+
639 (define_expand "neon_vst4<mode>"
640 [(match_operand:XI 0 "neon_struct_operand")
641 (match_operand:XI 1 "s_register_operand")
642
643=== modified file 'gcc/doc/md.texi'
644--- old/gcc/doc/md.texi 2011-01-03 20:52:22 +0000
645+++ new/gcc/doc/md.texi 2011-05-05 15:43:06 +0000
646@@ -3935,6 +3935,48 @@
647 consecutive memory locations, operand 1 is the first register, and
648 operand 2 is a constant: the number of consecutive registers.
649
650+@cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
651+@item @samp{vec_load_lanes@var{m}@var{n}}
652+Perform an interleaved load of several vectors from memory operand 1
653+into register operand 0. Both operands have mode @var{m}. The register
654+operand is viewed as holding consecutive vectors of mode @var{n},
655+while the memory operand is a flat array that contains the same number
656+of elements. The operation is equivalent to:
657+
658+@smallexample
659+int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
660+for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
661+ for (i = 0; i < c; i++)
662+ operand0[i][j] = operand1[j * c + i];
663+@end smallexample
664+
665+For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
666+from memory into a register of mode @samp{TI}@. The register
667+contains two consecutive vectors of mode @samp{V4HI}@.
668+
669+This pattern can only be used if:
670+@smallexample
671+TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
672+@end smallexample
673+is true. GCC assumes that, if a target supports this kind of
674+instruction for some mode @var{n}, it also supports unaligned
675+loads for vectors of mode @var{n}.
676+
677+@cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
678+@item @samp{vec_store_lanes@var{m}@var{n}}
679+Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
680+and register operands reversed. That is, the instruction is
681+equivalent to:
682+
683+@smallexample
684+int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
685+for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
686+ for (i = 0; i < c; i++)
687+ operand0[j * c + i] = operand1[i][j];
688+@end smallexample
689+
690+for a memory operand 0 and register operand 1.
691+
692 @cindex @code{vec_set@var{m}} instruction pattern
693 @item @samp{vec_set@var{m}}
694 Set given field in the vector value. Operand 0 is the vector to modify,
695
696=== modified file 'gcc/expr.c'
697--- old/gcc/expr.c 2011-05-26 14:27:33 +0000
698+++ new/gcc/expr.c 2011-06-02 12:12:00 +0000
699@@ -8537,10 +8537,13 @@
700 if (code == SSA_NAME
701 && (g = SSA_NAME_DEF_STMT (ssa_name))
702 && gimple_code (g) == GIMPLE_CALL)
703- pmode = promote_function_mode (type, mode, &unsignedp,
704- TREE_TYPE
705- (TREE_TYPE (gimple_call_fn (g))),
706- 2);
707+ {
708+ gcc_assert (!gimple_call_internal_p (g));
709+ pmode = promote_function_mode (type, mode, &unsignedp,
710+ TREE_TYPE
711+ (TREE_TYPE (gimple_call_fn (g))),
712+ 2);
713+ }
714 else
715 pmode = promote_decl_mode (exp, &unsignedp);
716 gcc_assert (GET_MODE (decl_rtl) == pmode);
717
718=== modified file 'gcc/genopinit.c'
719--- old/gcc/genopinit.c 2011-01-03 20:52:22 +0000
720+++ new/gcc/genopinit.c 2011-05-05 15:43:06 +0000
721@@ -74,6 +74,8 @@
722 "set_convert_optab_handler (fractuns_optab, $B, $A, CODE_FOR_$(fractuns$Q$a$I$b2$))",
723 "set_convert_optab_handler (satfract_optab, $B, $A, CODE_FOR_$(satfract$a$Q$b2$))",
724 "set_convert_optab_handler (satfractuns_optab, $B, $A, CODE_FOR_$(satfractuns$I$a$Q$b2$))",
725+ "set_convert_optab_handler (vec_load_lanes_optab, $A, $B, CODE_FOR_$(vec_load_lanes$a$b$))",
726+ "set_convert_optab_handler (vec_store_lanes_optab, $A, $B, CODE_FOR_$(vec_store_lanes$a$b$))",
727 "set_optab_handler (add_optab, $A, CODE_FOR_$(add$P$a3$))",
728 "set_optab_handler (addv_optab, $A, CODE_FOR_$(add$F$a3$)),\n\
729 set_optab_handler (add_optab, $A, CODE_FOR_$(add$F$a3$))",
730
731=== modified file 'gcc/gimple-low.c'
732--- old/gcc/gimple-low.c 2011-02-08 11:15:53 +0000
733+++ new/gcc/gimple-low.c 2011-05-05 15:42:22 +0000
734@@ -218,6 +218,10 @@
735 tree fndecl, parms, p;
736 unsigned int i, nargs;
737
738+ /* Calls to internal functions always match their signature. */
739+ if (gimple_call_internal_p (stmt))
740+ return true;
741+
742 nargs = gimple_call_num_args (stmt);
743
744 /* Get argument types for verification. */
745
746=== modified file 'gcc/gimple-pretty-print.c'
747--- old/gcc/gimple-pretty-print.c 2011-02-15 18:36:16 +0000
748+++ new/gcc/gimple-pretty-print.c 2011-05-05 15:42:22 +0000
749@@ -596,8 +596,12 @@
750
751 if (flags & TDF_RAW)
752 {
753- dump_gimple_fmt (buffer, spc, flags, "%G <%T, %T",
754- gs, gimple_call_fn (gs), lhs);
755+ if (gimple_call_internal_p (gs))
756+ dump_gimple_fmt (buffer, spc, flags, "%G <%s, %T", gs,
757+ internal_fn_name (gimple_call_internal_fn (gs)), lhs);
758+ else
759+ dump_gimple_fmt (buffer, spc, flags, "%G <%T, %T",
760+ gs, gimple_call_fn (gs), lhs);
761 if (gimple_call_num_args (gs) > 0)
762 {
763 pp_string (buffer, ", ");
764@@ -617,7 +621,10 @@
765
766 pp_space (buffer);
767 }
768- print_call_name (buffer, gimple_call_fn (gs), flags);
769+ if (gimple_call_internal_p (gs))
770+ pp_string (buffer, internal_fn_name (gimple_call_internal_fn (gs)));
771+ else
772+ print_call_name (buffer, gimple_call_fn (gs), flags);
773 pp_string (buffer, " (");
774 dump_gimple_call_args (buffer, gs, flags);
775 pp_character (buffer, ')');
776
777=== modified file 'gcc/gimple.c'
778--- old/gcc/gimple.c 2011-05-18 13:33:53 +0000
779+++ new/gcc/gimple.c 2011-06-02 12:12:00 +0000
780@@ -276,6 +276,59 @@
781 }
782
783
784+/* Helper for gimple_build_call_internal and gimple_build_call_internal_vec.
785+ Build the basic components of a GIMPLE_CALL statement to internal
786+ function FN with NARGS arguments. */
787+
788+static inline gimple
789+gimple_build_call_internal_1 (enum internal_fn fn, unsigned nargs)
790+{
791+ gimple s = gimple_build_with_ops (GIMPLE_CALL, ERROR_MARK, nargs + 3);
792+ s->gsbase.subcode |= GF_CALL_INTERNAL;
793+ gimple_call_set_internal_fn (s, fn);
794+ gimple_call_reset_alias_info (s);
795+ return s;
796+}
797+
798+
799+/* Build a GIMPLE_CALL statement to internal function FN. NARGS is
800+ the number of arguments. The ... are the arguments. */
801+
802+gimple
803+gimple_build_call_internal (enum internal_fn fn, unsigned nargs, ...)
804+{
805+ va_list ap;
806+ gimple call;
807+ unsigned i;
808+
809+ call = gimple_build_call_internal_1 (fn, nargs);
810+ va_start (ap, nargs);
811+ for (i = 0; i < nargs; i++)
812+ gimple_call_set_arg (call, i, va_arg (ap, tree));
813+ va_end (ap);
814+
815+ return call;
816+}
817+
818+
819+/* Build a GIMPLE_CALL statement to internal function FN with the arguments
820+ specified in vector ARGS. */
821+
822+gimple
823+gimple_build_call_internal_vec (enum internal_fn fn, VEC(tree, heap) *args)
824+{
825+ unsigned i, nargs;
826+ gimple call;
827+
828+ nargs = VEC_length (tree, args);
829+ call = gimple_build_call_internal_1 (fn, nargs);
830+ for (i = 0; i < nargs; i++)
831+ gimple_call_set_arg (call, i, VEC_index (tree, args, i));
832+
833+ return call;
834+}
835+
836+
837 /* Build a GIMPLE_CALL statement from CALL_EXPR T. Note that T is
838 assumed to be in GIMPLE form already. Minimal checking is done of
839 this fact. */
840@@ -1774,6 +1827,20 @@
841 return (gimple_body (fndecl) || (fn && fn->cfg));
842 }
843
844+/* Return true if calls C1 and C2 are known to go to the same function. */
845+
846+bool
847+gimple_call_same_target_p (const_gimple c1, const_gimple c2)
848+{
849+ if (gimple_call_internal_p (c1))
850+ return (gimple_call_internal_p (c2)
851+ && gimple_call_internal_fn (c1) == gimple_call_internal_fn (c2));
852+ else
853+ return (gimple_call_fn (c1) == gimple_call_fn (c2)
854+ || (gimple_call_fndecl (c1)
855+ && gimple_call_fndecl (c1) == gimple_call_fndecl (c2)));
856+}
857+
858 /* Detect flags from a GIMPLE_CALL. This is just like
859 call_expr_flags, but for gimple tuples. */
860
861@@ -1786,6 +1853,8 @@
862
863 if (decl)
864 flags = flags_from_decl_or_type (decl);
865+ else if (gimple_call_internal_p (stmt))
866+ flags = internal_fn_flags (gimple_call_internal_fn (stmt));
867 else
868 {
869 t = TREE_TYPE (gimple_call_fn (stmt));
870@@ -1801,18 +1870,35 @@
871 return flags;
872 }
873
874+/* Return the "fn spec" string for call STMT. */
875+
876+static tree
877+gimple_call_fnspec (const_gimple stmt)
878+{
879+ tree fn, type, attr;
880+
881+ fn = gimple_call_fn (stmt);
882+ if (!fn)
883+ return NULL_TREE;
884+
885+ type = TREE_TYPE (TREE_TYPE (fn));
886+ if (!type)
887+ return NULL_TREE;
888+
889+ attr = lookup_attribute ("fn spec", TYPE_ATTRIBUTES (type));
890+ if (!attr)
891+ return NULL_TREE;
892+
893+ return TREE_VALUE (TREE_VALUE (attr));
894+}
895+
896 /* Detects argument flags for argument number ARG on call STMT. */
897
898 int
899 gimple_call_arg_flags (const_gimple stmt, unsigned arg)
900 {
901- tree type = TREE_TYPE (TREE_TYPE (gimple_call_fn (stmt)));
902- tree attr = lookup_attribute ("fn spec", TYPE_ATTRIBUTES (type));
903- if (!attr)
904- return 0;
905-
906- attr = TREE_VALUE (TREE_VALUE (attr));
907- if (1 + arg >= (unsigned) TREE_STRING_LENGTH (attr))
908+ tree attr = gimple_call_fnspec (stmt);
909+ if (!attr || 1 + arg >= (unsigned) TREE_STRING_LENGTH (attr))
910 return 0;
911
912 switch (TREE_STRING_POINTER (attr)[1 + arg])
913@@ -1850,13 +1936,8 @@
914 if (gimple_call_flags (stmt) & ECF_MALLOC)
915 return ERF_NOALIAS;
916
917- type = TREE_TYPE (TREE_TYPE (gimple_call_fn (stmt)));
918- attr = lookup_attribute ("fn spec", TYPE_ATTRIBUTES (type));
919- if (!attr)
920- return 0;
921-
922- attr = TREE_VALUE (TREE_VALUE (attr));
923- if (TREE_STRING_LENGTH (attr) < 1)
924+ attr = gimple_call_fnspec (stmt);
925+ if (!attr || TREE_STRING_LENGTH (attr) < 1)
926 return 0;
927
928 switch (TREE_STRING_POINTER (attr)[0])
929@@ -2293,6 +2374,7 @@
930 if (is_gimple_call (s))
931 {
932 unsigned nargs = gimple_call_num_args (s);
933+ tree fn;
934
935 if (!(gimple_call_flags (s) & (ECF_CONST | ECF_PURE)))
936 return true;
937@@ -2307,7 +2389,8 @@
938 return true;
939 }
940
941- if (TREE_SIDE_EFFECTS (gimple_call_fn (s)))
942+ fn = gimple_call_fn (s);
943+ if (fn && TREE_SIDE_EFFECTS (fn))
944 return true;
945
946 for (i = 0; i < nargs; i++)
947@@ -2349,14 +2432,15 @@
948 if (is_gimple_call (s))
949 {
950 unsigned nargs = gimple_call_num_args (s);
951+ tree fn;
952
953 if (!(gimple_call_flags (s) & (ECF_CONST | ECF_PURE)))
954 return true;
955
956 /* We cannot use gimple_has_volatile_ops here,
957 because we must ignore a volatile LHS. */
958- if (TREE_SIDE_EFFECTS (gimple_call_fn (s))
959- || TREE_THIS_VOLATILE (gimple_call_fn (s)))
960+ fn = gimple_call_fn (s);
961+ if (fn && (TREE_SIDE_EFFECTS (fn) || TREE_THIS_VOLATILE (fn)))
962 {
963 gcc_assert (gimple_has_volatile_ops (s));
964 return true;
965@@ -3113,7 +3197,6 @@
966 gimple_call_copy_skip_args (gimple stmt, bitmap args_to_skip)
967 {
968 int i;
969- tree fn = gimple_call_fn (stmt);
970 int nargs = gimple_call_num_args (stmt);
971 VEC(tree, heap) *vargs = VEC_alloc (tree, heap, nargs);
972 gimple new_stmt;
973@@ -3122,7 +3205,11 @@
974 if (!bitmap_bit_p (args_to_skip, i))
975 VEC_quick_push (tree, vargs, gimple_call_arg (stmt, i));
976
977- new_stmt = gimple_build_call_vec (fn, vargs);
978+ if (gimple_call_internal_p (stmt))
979+ new_stmt = gimple_build_call_internal_vec (gimple_call_internal_fn (stmt),
980+ vargs);
981+ else
982+ new_stmt = gimple_build_call_vec (gimple_call_fn (stmt), vargs);
983 VEC_free (tree, heap, vargs);
984 if (gimple_call_lhs (stmt))
985 gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt));
986
987=== modified file 'gcc/gimple.h'
988--- old/gcc/gimple.h 2011-04-18 21:58:03 +0000
989+++ new/gcc/gimple.h 2011-06-02 12:12:00 +0000
990@@ -30,6 +30,7 @@
991 #include "basic-block.h"
992 #include "tree-ssa-operands.h"
993 #include "tree-ssa-alias.h"
994+#include "internal-fn.h"
995
996 struct gimple_seq_node_d;
997 typedef struct gimple_seq_node_d *gimple_seq_node;
998@@ -82,6 +83,8 @@
999 name, a _DECL, a _REF, etc. */
1000 };
1001
1002+#define GF_CALL_INTERNAL_FN_SHIFT 8
1003+
1004 /* Specific flags for individual GIMPLE statements. These flags are
1005 always stored in gimple_statement_base.subcode and they may only be
1006 defined for statement codes that do not use sub-codes.
1007@@ -102,6 +105,8 @@
1008 GF_CALL_TAILCALL = 1 << 3,
1009 GF_CALL_VA_ARG_PACK = 1 << 4,
1010 GF_CALL_NOTHROW = 1 << 5,
1011+ GF_CALL_INTERNAL = 1 << 6,
1012+ GF_CALL_INTERNAL_FN = 0xff << GF_CALL_INTERNAL_FN_SHIFT,
1013 GF_OMP_PARALLEL_COMBINED = 1 << 0,
1014
1015 /* True on an GIMPLE_OMP_RETURN statement if the return does not require
1016@@ -817,6 +822,8 @@
1017
1018 gimple gimple_build_call_vec (tree, VEC(tree, heap) *);
1019 gimple gimple_build_call (tree, unsigned, ...);
1020+gimple gimple_build_call_internal (enum internal_fn, unsigned, ...);
1021+gimple gimple_build_call_internal_vec (enum internal_fn, VEC(tree, heap) *);
1022 gimple gimple_build_call_from_tree (tree);
1023 gimple gimplify_assign (tree, tree, gimple_seq *);
1024 gimple gimple_build_cond (enum tree_code, tree, tree, tree, tree);
1025@@ -861,6 +868,7 @@
1026 void gimple_seq_free (gimple_seq);
1027 void gimple_seq_add_seq (gimple_seq *, gimple_seq);
1028 gimple_seq gimple_seq_copy (gimple_seq);
1029+bool gimple_call_same_target_p (const_gimple, const_gimple);
1030 int gimple_call_flags (const_gimple);
1031 int gimple_call_return_flags (const_gimple);
1032 int gimple_call_arg_flags (const_gimple, unsigned);
1033@@ -2012,6 +2020,27 @@
1034 }
1035
1036
1037+/* Return true if call GS calls an internal-only function, as enumerated
1038+ by internal_fn. */
1039+
1040+static inline bool
1041+gimple_call_internal_p (const_gimple gs)
1042+{
1043+ GIMPLE_CHECK (gs, GIMPLE_CALL);
1044+ return (gs->gsbase.subcode & GF_CALL_INTERNAL) != 0;
1045+}
1046+
1047+
1048+/* Return the target of internal call GS. */
1049+
1050+static inline enum internal_fn
1051+gimple_call_internal_fn (const_gimple gs)
1052+{
1053+ gcc_assert (gimple_call_internal_p (gs));
1054+ return (enum internal_fn) (gs->gsbase.subcode >> GF_CALL_INTERNAL_FN_SHIFT);
1055+}
1056+
1057+
1058 /* Return a pointer to the tree node representing the function called by call
1059 statement GS. */
1060
1061@@ -2029,6 +2058,7 @@
1062 gimple_call_set_fn (gimple gs, tree fn)
1063 {
1064 GIMPLE_CHECK (gs, GIMPLE_CALL);
1065+ gcc_assert (!gimple_call_internal_p (gs));
1066 gimple_set_op (gs, 1, fn);
1067 }
1068
1069@@ -2039,10 +2069,23 @@
1070 gimple_call_set_fndecl (gimple gs, tree decl)
1071 {
1072 GIMPLE_CHECK (gs, GIMPLE_CALL);
1073+ gcc_assert (!gimple_call_internal_p (gs));
1074 gimple_set_op (gs, 1, build_fold_addr_expr_loc (gimple_location (gs), decl));
1075 }
1076
1077
1078+/* Set internal function FN to be the function called by call statement GS. */
1079+
1080+static inline void
1081+gimple_call_set_internal_fn (gimple gs, enum internal_fn fn)
1082+{
1083+ GIMPLE_CHECK (gs, GIMPLE_CALL);
1084+ gcc_assert (gimple_call_internal_p (gs));
1085+ gs->gsbase.subcode &= ~GF_CALL_INTERNAL_FN;
1086+ gs->gsbase.subcode |= (int) fn << GF_CALL_INTERNAL_FN_SHIFT;
1087+}
1088+
1089+
1090 /* If a given GIMPLE_CALL's callee is a FUNCTION_DECL, return it.
1091 Otherwise return NULL. This function is analogous to
1092 get_callee_fndecl in tree land. */
1093@@ -2051,7 +2094,7 @@
1094 gimple_call_fndecl (const_gimple gs)
1095 {
1096 tree addr = gimple_call_fn (gs);
1097- if (TREE_CODE (addr) == ADDR_EXPR)
1098+ if (addr && TREE_CODE (addr) == ADDR_EXPR)
1099 {
1100 tree fndecl = TREE_OPERAND (addr, 0);
1101 if (TREE_CODE (fndecl) == MEM_REF)
1102@@ -2073,8 +2116,13 @@
1103 static inline tree
1104 gimple_call_return_type (const_gimple gs)
1105 {
1106- tree fn = gimple_call_fn (gs);
1107- tree type = TREE_TYPE (fn);
1108+ tree fn, type;
1109+
1110+ fn = gimple_call_fn (gs);
1111+ if (fn == NULL_TREE)
1112+ return TREE_TYPE (gimple_call_lhs (gs));
1113+
1114+ type = TREE_TYPE (fn);
1115
1116 /* See through the pointer. */
1117 type = TREE_TYPE (type);
1118
1119=== added file 'gcc/internal-fn.c'
1120--- old/gcc/internal-fn.c 1970-01-01 00:00:00 +0000
1121+++ new/gcc/internal-fn.c 2011-05-05 15:43:06 +0000
1122@@ -0,0 +1,147 @@
1123+/* Internal functions.
1124+ Copyright (C) 2011 Free Software Foundation, Inc.
1125+
1126+This file is part of GCC.
1127+
1128+GCC is free software; you can redistribute it and/or modify it under
1129+the terms of the GNU General Public License as published by the Free
1130+Software Foundation; either version 3, or (at your option) any later
1131+version.
1132+
1133+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
1134+WARRANTY; without even the implied warranty of MERCHANTABILITY or
1135+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1136+for more details.
1137+
1138+You should have received a copy of the GNU General Public License
1139+along with GCC; see the file COPYING3. If not see
1140+<http://www.gnu.org/licenses/>. */
1141+
1142+#include "config.h"
1143+#include "system.h"
1144+#include "coretypes.h"
1145+#include "gimple.h"
1146+#include "tree.h"
1147+#include "expr.h"
1148+#include "optabs.h"
1149+#include "recog.h"
1150+
1151+/* The names of each internal function, indexed by function number. */
1152+const char *const internal_fn_name_array[] = {
1153+#define DEF_INTERNAL_FN(CODE, FLAGS) #CODE,
1154+#include "internal-fn.def"
1155+#undef DEF_INTERNAL_FN
1156+ "<invalid-fn>"
1157+};
1158+
1159+/* The ECF_* flags of each internal function, indexed by function number. */
1160+const int internal_fn_flags_array[] = {
1161+#define DEF_INTERNAL_FN(CODE, FLAGS) FLAGS,
1162+#include "internal-fn.def"
1163+#undef DEF_INTERNAL_FN
1164+ 0
1165+};
1166+
1167+/* ARRAY_TYPE is an array of vector modes. Return the associated insn
1168+ for load-lanes-style optab OPTAB. The insn must exist. */
1169+
1170+static enum insn_code
1171+get_multi_vector_move (tree array_type, convert_optab optab)
1172+{
1173+ enum insn_code icode;
1174+ enum machine_mode imode;
1175+ enum machine_mode vmode;
1176+
1177+ gcc_assert (TREE_CODE (array_type) == ARRAY_TYPE);
1178+ imode = TYPE_MODE (array_type);
1179+ vmode = TYPE_MODE (TREE_TYPE (array_type));
1180+
1181+ icode = convert_optab_handler (optab, imode, vmode);
1182+ gcc_assert (icode != CODE_FOR_nothing);
1183+ return icode;
1184+}
1185+
1186+/* Expand LOAD_LANES call STMT. */
1187+
1188+static void
1189+expand_LOAD_LANES (gimple stmt)
1190+{
1191+ tree type, lhs, rhs;
1192+ rtx target, mem;
1193+ enum insn_code icode;
1194+ const struct insn_operand_data *operand;
1195+
1196+ lhs = gimple_call_lhs (stmt);
1197+ rhs = gimple_call_arg (stmt, 0);
1198+ type = TREE_TYPE (lhs);
1199+
1200+ target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);
1201+ mem = expand_normal (rhs);
1202+
1203+ gcc_assert (REG_P (target));
1204+ gcc_assert (MEM_P (mem));
1205+ PUT_MODE (mem, TYPE_MODE (type));
1206+
1207+ icode = get_multi_vector_move (type, vec_load_lanes_optab);
1208+
1209+ operand = &insn_data[(int) icode].operand[1];
1210+ if (operand->predicate && !operand->predicate (mem, operand->mode))
1211+ mem = replace_equiv_address (mem, force_reg (Pmode, XEXP (mem, 0)));
1212+
1213+ emit_insn (GEN_FCN (icode) (target, mem));
1214+}
1215+
1216+/* Expand STORE_LANES call STMT. */
1217+
1218+static void
1219+expand_STORE_LANES (gimple stmt)
1220+{
1221+ tree type, lhs, rhs;
1222+ rtx target, reg;
1223+ enum insn_code icode;
1224+ const struct insn_operand_data *operand;
1225+
1226+ lhs = gimple_call_lhs (stmt);
1227+ rhs = gimple_call_arg (stmt, 0);
1228+ type = TREE_TYPE (rhs);
1229+
1230+ target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);
1231+ reg = expand_normal (rhs);
1232+
1233+ gcc_assert (MEM_P (target));
1234+ PUT_MODE (target, TYPE_MODE (type));
1235+
1236+ icode = get_multi_vector_move (type, vec_store_lanes_optab);
1237+
1238+ operand = &insn_data[(int) icode].operand[0];
1239+ if (operand->predicate && !operand->predicate (target, operand->mode))
1240+ target = replace_equiv_address (target,
1241+ force_reg (Pmode, XEXP (target, 0)));
1242+
1243+ operand = &insn_data[(int) icode].operand[1];
1244+ if (operand->predicate && !operand->predicate (reg, operand->mode))
1245+ reg = force_reg (TYPE_MODE (type), reg);
1246+
1247+ emit_insn (GEN_FCN (icode) (target, reg));
1248+}
1249+
1250+/* Routines to expand each internal function, indexed by function number.
1251+ Each routine has the prototype:
1252+
1253+ expand_<NAME> (gimple stmt)
1254+
1255+ where STMT is the statement that performs the call. */
1256+static void (*const internal_fn_expanders[]) (gimple) = {
1257+#define DEF_INTERNAL_FN(CODE, FLAGS) expand_##CODE,
1258+#include "internal-fn.def"
1259+#undef DEF_INTERNAL_FN
1260+ 0
1261+};
1262+
1263+/* Expand STMT, which is a call to internal function FN. */
1264+
1265+void
1266+expand_internal_call (gimple stmt)
1267+{
1268+ internal_fn_expanders[(int) gimple_call_internal_fn (stmt)] (stmt);
1269+}
1270
1271=== added file 'gcc/internal-fn.def'
1272--- old/gcc/internal-fn.def 1970-01-01 00:00:00 +0000
1273+++ new/gcc/internal-fn.def 2011-05-05 15:43:06 +0000
1274@@ -0,0 +1,42 @@
1275+/* Internal functions.
1276+ Copyright (C) 2011 Free Software Foundation, Inc.
1277+
1278+This file is part of GCC.
1279+
1280+GCC is free software; you can redistribute it and/or modify it under
1281+the terms of the GNU General Public License as published by the Free
1282+Software Foundation; either version 3, or (at your option) any later
1283+version.
1284+
1285+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
1286+WARRANTY; without even the implied warranty of MERCHANTABILITY or
1287+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1288+for more details.
1289+
1290+You should have received a copy of the GNU General Public License
1291+along with GCC; see the file COPYING3. If not see
1292+<http://www.gnu.org/licenses/>. */
1293+
1294+/* This file specifies a list of internal "functions". These functions
1295+ differ from built-in functions in that they have no linkage and cannot
1296+ be called directly by the user. They represent operations that are only
1297+ synthesised by GCC itself.
1298+
1299+ Internal functions are used instead of tree codes if the operation
1300+ and its operands are more naturally represented as a GIMPLE_CALL
1301+ than a GIMPLE_ASSIGN.
1302+
1303+ Each entry in this file has the form:
1304+
1305+ DEF_INTERNAL_FN (NAME, FLAGS)
1306+
1307+ where NAME is the name of the function and FLAGS is a set of
1308+ ECF_* flags. Each entry must have a corresponding expander
1309+ of the form:
1310+
1311+ void expand_NAME (gimple stmt)
1312+
1313+ where STMT is the statement that performs the call. */
1314+
1315+DEF_INTERNAL_FN (LOAD_LANES, ECF_CONST | ECF_LEAF)
1316+DEF_INTERNAL_FN (STORE_LANES, ECF_CONST | ECF_LEAF)
1317
1318=== added file 'gcc/internal-fn.h'
1319--- old/gcc/internal-fn.h 1970-01-01 00:00:00 +0000
1320+++ new/gcc/internal-fn.h 2011-05-05 15:42:22 +0000
1321@@ -0,0 +1,52 @@
1322+/* Internal functions.
1323+ Copyright (C) 2011 Free Software Foundation, Inc.
1324+
1325+This file is part of GCC.
1326+
1327+GCC is free software; you can redistribute it and/or modify it under
1328+the terms of the GNU General Public License as published by the Free
1329+Software Foundation; either version 3, or (at your option) any later
1330+version.
1331+
1332+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
1333+WARRANTY; without even the implied warranty of MERCHANTABILITY or
1334+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1335+for more details.
1336+
1337+You should have received a copy of the GNU General Public License
1338+along with GCC; see the file COPYING3. If not see
1339+<http://www.gnu.org/licenses/>. */
1340+
1341+#ifndef GCC_INTERNAL_FN_H
1342+#define GCC_INTERNAL_FN_H
1343+
1344+enum internal_fn {
1345+#define DEF_INTERNAL_FN(CODE, FLAGS) IFN_##CODE,
1346+#include "internal-fn.def"
1347+#undef DEF_INTERNAL_FN
1348+ IFN_LAST
1349+};
1350+
1351+extern const char *const internal_fn_name_array[];
1352+extern const int internal_fn_flags_array[];
1353+
1354+/* Return the name of internal function FN. The name is only meaningful
1355+ for dumps; it has no linkage. */
1356+
1357+static inline const char *
1358+internal_fn_name (enum internal_fn fn)
1359+{
1360+ return internal_fn_name_array[(int) fn];
1361+}
1362+
1363+/* Return the ECF_* flags for function FN. */
1364+
1365+static inline int
1366+internal_fn_flags (enum internal_fn fn)
1367+{
1368+ return internal_fn_flags_array[(int) fn];
1369+}
1370+
1371+extern void expand_internal_call (gimple);
1372+
1373+#endif
1374
1375=== modified file 'gcc/ipa-prop.c'
1376--- old/gcc/ipa-prop.c 2011-04-18 21:58:03 +0000
1377+++ new/gcc/ipa-prop.c 2011-06-02 12:12:00 +0000
1378@@ -1418,6 +1418,8 @@
1379 {
1380 tree target = gimple_call_fn (call);
1381
1382+ if (!target)
1383+ return;
1384 if (TREE_CODE (target) == SSA_NAME)
1385 ipa_analyze_indirect_call_uses (node, info, parms_info, call, target);
1386 else if (TREE_CODE (target) == OBJ_TYPE_REF)
1387
1388=== modified file 'gcc/optabs.h'
1389--- old/gcc/optabs.h 2011-01-03 20:52:22 +0000
1390+++ new/gcc/optabs.h 2011-05-05 15:43:06 +0000
1391@@ -578,6 +578,9 @@
1392 COI_satfract,
1393 COI_satfractuns,
1394
1395+ COI_vec_load_lanes,
1396+ COI_vec_store_lanes,
1397+
1398 COI_MAX
1399 };
1400
1401@@ -598,6 +601,8 @@
1402 #define fractuns_optab (&convert_optab_table[COI_fractuns])
1403 #define satfract_optab (&convert_optab_table[COI_satfract])
1404 #define satfractuns_optab (&convert_optab_table[COI_satfractuns])
1405+#define vec_load_lanes_optab (&convert_optab_table[COI_vec_load_lanes])
1406+#define vec_store_lanes_optab (&convert_optab_table[COI_vec_store_lanes])
1407
1408 /* Contains the optab used for each rtx code. */
1409 extern optab code_to_optab[NUM_RTX_CODE + 1];
1410
1411=== modified file 'gcc/testsuite/gcc.dg/vect/O3-pr39675-2.c'
1412--- old/gcc/testsuite/gcc.dg/vect/O3-pr39675-2.c 2009-04-20 10:26:18 +0000
1413+++ new/gcc/testsuite/gcc.dg/vect/O3-pr39675-2.c 2011-05-05 15:46:10 +0000
1414@@ -26,7 +26,7 @@
1415 }
1416 }
1417
1418-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided_wide } } } */
1419-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided_wide } } } */
1420+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
1421+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided4 } } } */
1422 /* { dg-final { cleanup-tree-dump "vect" } } */
1423
1424
1425=== modified file 'gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c'
1426--- old/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c 2010-11-22 12:16:52 +0000
1427+++ new/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-12.c 2011-05-05 15:46:10 +0000
1428@@ -113,7 +113,7 @@
1429 return 0;
1430 }
1431
1432-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" {target { vect_strided && vect_int_mult } } } } */
1433-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" {target { vect_strided && vect_int_mult } } } } */
1434+/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" {target { vect_strided8 && vect_int_mult } } } } */
1435+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" {target { vect_strided8 && vect_int_mult } } } } */
1436 /* { dg-final { cleanup-tree-dump "vect" } } */
1437
1438
1439=== modified file 'gcc/testsuite/gcc.dg/vect/fast-math-pr35982.c'
1440--- old/gcc/testsuite/gcc.dg/vect/fast-math-pr35982.c 2008-08-26 08:14:37 +0000
1441+++ new/gcc/testsuite/gcc.dg/vect/fast-math-pr35982.c 2011-05-05 15:44:00 +0000
1442@@ -20,7 +20,7 @@
1443 return avg;
1444 }
1445
1446-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */
1447-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */
1448+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd } } } */
1449+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd } } } */
1450 /* { dg-final { cleanup-tree-dump "vect" } } */
1451
1452
1453=== modified file 'gcc/testsuite/gcc.dg/vect/fast-math-slp-27.c'
1454--- old/gcc/testsuite/gcc.dg/vect/fast-math-slp-27.c 2010-08-26 11:13:58 +0000
1455+++ new/gcc/testsuite/gcc.dg/vect/fast-math-slp-27.c 2011-05-05 15:46:10 +0000
1456@@ -13,5 +13,5 @@
1457 }
1458 }
1459
1460-/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" { target vect_strided } } } */
1461+/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" { target vect_strided2 } } } */
1462 /* { dg-final { cleanup-tree-dump "vect" } } */
1463
1464=== modified file 'gcc/testsuite/gcc.dg/vect/fast-math-vect-complex-3.c'
1465--- old/gcc/testsuite/gcc.dg/vect/fast-math-vect-complex-3.c 2010-11-22 12:16:52 +0000
1466+++ new/gcc/testsuite/gcc.dg/vect/fast-math-vect-complex-3.c 2011-05-05 15:46:10 +0000
1467@@ -56,5 +56,5 @@
1468 return 0;
1469 }
1470
1471-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */
1472+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
1473 /* { dg-final { cleanup-tree-dump "vect" } } */
1474
1475=== modified file 'gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c'
1476--- old/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c 2011-04-24 07:45:49 +0000
1477+++ new/gcc/testsuite/gcc.dg/vect/if-cvt-stores-vect-ifcvt-18.c 2011-05-05 15:46:10 +0000
1478@@ -65,5 +65,5 @@
1479 return 0;
1480 }
1481
1482-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || {! vect_strided } } } } } */
1483+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || { ! vect_strided2 } } } } } */
1484 /* { dg-final { cleanup-tree-dump "vect" } } */
1485
1486=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10a.c'
1487--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10a.c 2007-09-04 12:05:19 +0000
1488+++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10a.c 2011-05-05 15:46:10 +0000
1489@@ -54,5 +54,5 @@
1490 return 0;
1491 }
1492
1493-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
1494+/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_strided2 } } } */
1495 /* { dg-final { cleanup-tree-dump "vect" } } */
1496
1497=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10b.c'
1498--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10b.c 2007-09-04 12:05:19 +0000
1499+++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-10b.c 2011-05-05 15:46:10 +0000
1500@@ -53,5 +53,5 @@
1501 return 0;
1502 }
1503
1504-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
1505+/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_strided2 } } } */
1506 /* { dg-final { cleanup-tree-dump "vect" } } */
1507
1508=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-18.c'
1509--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-18.c 2007-10-21 09:01:16 +0000
1510+++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-18.c 2011-05-05 15:46:10 +0000
1511@@ -47,5 +47,5 @@
1512 return 0;
1513 }
1514
1515-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_interleave } } } */
1516+/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave || vect_strided2 } } } } */
1517 /* { dg-final { cleanup-tree-dump "vect" } } */
1518
1519=== modified file 'gcc/testsuite/gcc.dg/vect/no-scevccp-outer-20.c'
1520--- old/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-20.c 2007-09-04 12:05:19 +0000
1521+++ new/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-20.c 2011-05-05 15:46:10 +0000
1522@@ -50,5 +50,5 @@
1523 return 0;
1524 }
1525
1526-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
1527+/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { target vect_strided2 } } } */
1528 /* { dg-final { cleanup-tree-dump "vect" } } */
1529
1530=== modified file 'gcc/testsuite/gcc.dg/vect/pr30843.c'
1531--- old/gcc/testsuite/gcc.dg/vect/pr30843.c 2007-02-22 12:30:12 +0000
1532+++ new/gcc/testsuite/gcc.dg/vect/pr30843.c 2011-05-05 15:46:10 +0000
1533@@ -20,6 +20,6 @@
1534 }
1535 }
1536
1537-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */
1538+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided4 } } } } */
1539 /* { dg-final { cleanup-tree-dump "vect" } } */
1540
1541
1542=== modified file 'gcc/testsuite/gcc.dg/vect/pr33866.c'
1543--- old/gcc/testsuite/gcc.dg/vect/pr33866.c 2007-10-30 08:26:14 +0000
1544+++ new/gcc/testsuite/gcc.dg/vect/pr33866.c 2011-05-05 15:46:10 +0000
1545@@ -27,6 +27,6 @@
1546 }
1547
1548 /* Needs interleaving support. */
1549-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */
1550+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided2 } } } } */
1551 /* { dg-final { cleanup-tree-dump "vect" } } */
1552
1553
1554=== modified file 'gcc/testsuite/gcc.dg/vect/pr37539.c'
1555--- old/gcc/testsuite/gcc.dg/vect/pr37539.c 2009-11-26 02:03:50 +0000
1556+++ new/gcc/testsuite/gcc.dg/vect/pr37539.c 2011-05-05 15:46:10 +0000
1557@@ -40,7 +40,7 @@
1558 return 0;
1559 }
1560
1561-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_strided_wide } } } */
1562+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { vect_strided4 && vect_strided2 } } } } */
1563 /* { dg-final { cleanup-tree-dump "vect" } } */
1564
1565
1566
1567=== removed file 'gcc/testsuite/gcc.dg/vect/slp-11.c'
1568--- old/gcc/testsuite/gcc.dg/vect/slp-11.c 2010-11-22 12:16:52 +0000
1569+++ new/gcc/testsuite/gcc.dg/vect/slp-11.c 1970-01-01 00:00:00 +0000
1570@@ -1,113 +0,0 @@
1571-/* { dg-require-effective-target vect_int } */
1572-
1573-#include <stdarg.h>
1574-#include "tree-vect.h"
1575-
1576-#define N 8
1577-
1578-int
1579-main1 ()
1580-{
1581- int i;
1582- unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
1583- unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
1584- float out2[N*8];
1585-
1586- /* Different operations - not SLPable. */
1587- for (i = 0; i < N; i++)
1588- {
1589- a0 = in[i*8] + 5;
1590- a1 = in[i*8 + 1] * 6;
1591- a2 = in[i*8 + 2] + 7;
1592- a3 = in[i*8 + 3] + 8;
1593- a4 = in[i*8 + 4] + 9;
1594- a5 = in[i*8 + 5] + 10;
1595- a6 = in[i*8 + 6] + 11;
1596- a7 = in[i*8 + 7] + 12;
1597-
1598- b0 = a0 * 3;
1599- b1 = a1 * 2;
1600- b2 = a2 * 12;
1601- b3 = a3 * 5;
1602- b4 = a4 * 8;
1603- b5 = a5 * 4;
1604- b6 = a6 * 3;
1605- b7 = a7 * 2;
1606-
1607- out[i*8] = b0 - 2;
1608- out[i*8 + 1] = b1 - 3;
1609- out[i*8 + 2] = b2 - 2;
1610- out[i*8 + 3] = b3 - 1;
1611- out[i*8 + 4] = b4 - 8;
1612- out[i*8 + 5] = b5 - 7;
1613- out[i*8 + 6] = b6 - 3;
1614- out[i*8 + 7] = b7 - 7;
1615- }
1616-
1617- /* check results: */
1618- for (i = 0; i < N; i++)
1619- {
1620- if (out[i*8] != (in[i*8] + 5) * 3 - 2
1621- || out[i*8 + 1] != (in[i*8 + 1] * 6) * 2 - 3
1622- || out[i*8 + 2] != (in[i*8 + 2] + 7) * 12 - 2
1623- || out[i*8 + 3] != (in[i*8 + 3] + 8) * 5 - 1
1624- || out[i*8 + 4] != (in[i*8 + 4] + 9) * 8 - 8
1625- || out[i*8 + 5] != (in[i*8 + 5] + 10) * 4 - 7
1626- || out[i*8 + 6] != (in[i*8 + 6] + 11) * 3 - 3
1627- || out[i*8 + 7] != (in[i*8 + 7] + 12) * 2 - 7)
1628- abort ();
1629- }
1630-
1631- /* Requires permutation - not SLPable. */
1632- for (i = 0; i < N*2; i++)
1633- {
1634- out[i*4] = (in[i*4] + 2) * 3;
1635- out[i*4 + 1] = (in[i*4 + 2] + 2) * 7;
1636- out[i*4 + 2] = (in[i*4 + 1] + 7) * 3;
1637- out[i*4 + 3] = (in[i*4 + 3] + 3) * 4;
1638- }
1639-
1640- /* check results: */
1641- for (i = 0; i < N*2; i++)
1642- {
1643- if (out[i*4] != (in[i*4] + 2) * 3
1644- || out[i*4 + 1] != (in[i*4 + 2] + 2) * 7
1645- || out[i*4 + 2] != (in[i*4 + 1] + 7) * 3
1646- || out[i*4 + 3] != (in[i*4 + 3] + 3) * 4)
1647- abort ();
1648- }
1649-
1650- /* Different operations - not SLPable. */
1651- for (i = 0; i < N*4; i++)
1652- {
1653- out2[i*2] = ((float) in[i*2] * 2 + 6) ;
1654- out2[i*2 + 1] = (float) (in[i*2 + 1] * 3 + 7);
1655- }
1656-
1657- /* check results: */
1658- for (i = 0; i < N*4; i++)
1659- {
1660- if (out2[i*2] != ((float) in[i*2] * 2 + 6)
1661- || out2[i*2 + 1] != (float) (in[i*2 + 1] * 3 + 7))
1662- abort ();
1663- }
1664-
1665-
1666- return 0;
1667-}
1668-
1669-int main (void)
1670-{
1671- check_vect ();
1672-
1673- main1 ();
1674-
1675- return 0;
1676-}
1677-
1678-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target { { vect_uintfloat_cvt && vect_strided_wide } && vect_int_mult } } } } */
1679-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { { { ! vect_uintfloat_cvt } && vect_strided_wide } && vect_int_mult } } } } */
1680-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { ! { vect_int_mult && vect_strided_wide } } } } } */
1681-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
1682-/* { dg-final { cleanup-tree-dump "vect" } } */
1683-
1684
1685=== added file 'gcc/testsuite/gcc.dg/vect/slp-11a.c'
1686--- old/gcc/testsuite/gcc.dg/vect/slp-11a.c 1970-01-01 00:00:00 +0000
1687+++ new/gcc/testsuite/gcc.dg/vect/slp-11a.c 2011-05-05 15:46:10 +0000
1688@@ -0,0 +1,75 @@
1689+/* { dg-require-effective-target vect_int } */
1690+
1691+#include <stdarg.h>
1692+#include "tree-vect.h"
1693+
1694+#define N 8
1695+
1696+int
1697+main1 ()
1698+{
1699+ int i;
1700+ unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
1701+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
1702+
1703+ /* Different operations - not SLPable. */
1704+ for (i = 0; i < N; i++)
1705+ {
1706+ a0 = in[i*8] + 5;
1707+ a1 = in[i*8 + 1] * 6;
1708+ a2 = in[i*8 + 2] + 7;
1709+ a3 = in[i*8 + 3] + 8;
1710+ a4 = in[i*8 + 4] + 9;
1711+ a5 = in[i*8 + 5] + 10;
1712+ a6 = in[i*8 + 6] + 11;
1713+ a7 = in[i*8 + 7] + 12;
1714+
1715+ b0 = a0 * 3;
1716+ b1 = a1 * 2;
1717+ b2 = a2 * 12;
1718+ b3 = a3 * 5;
1719+ b4 = a4 * 8;
1720+ b5 = a5 * 4;
1721+ b6 = a6 * 3;
1722+ b7 = a7 * 2;
1723+
1724+ out[i*8] = b0 - 2;
1725+ out[i*8 + 1] = b1 - 3;
1726+ out[i*8 + 2] = b2 - 2;
1727+ out[i*8 + 3] = b3 - 1;
1728+ out[i*8 + 4] = b4 - 8;
1729+ out[i*8 + 5] = b5 - 7;
1730+ out[i*8 + 6] = b6 - 3;
1731+ out[i*8 + 7] = b7 - 7;
1732+ }
1733+
1734+ /* check results: */
1735+ for (i = 0; i < N; i++)
1736+ {
1737+ if (out[i*8] != (in[i*8] + 5) * 3 - 2
1738+ || out[i*8 + 1] != (in[i*8 + 1] * 6) * 2 - 3
1739+ || out[i*8 + 2] != (in[i*8 + 2] + 7) * 12 - 2
1740+ || out[i*8 + 3] != (in[i*8 + 3] + 8) * 5 - 1
1741+ || out[i*8 + 4] != (in[i*8 + 4] + 9) * 8 - 8
1742+ || out[i*8 + 5] != (in[i*8 + 5] + 10) * 4 - 7
1743+ || out[i*8 + 6] != (in[i*8 + 6] + 11) * 3 - 3
1744+ || out[i*8 + 7] != (in[i*8 + 7] + 12) * 2 - 7)
1745+ abort ();
1746+ }
1747+
1748+ return 0;
1749+}
1750+
1751+int main (void)
1752+{
1753+ check_vect ();
1754+
1755+ main1 ();
1756+
1757+ return 0;
1758+}
1759+
1760+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided8 && vect_int_mult } } } } */
1761+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided8 && vect_int_mult } } } } } */
1762+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
1763+/* { dg-final { cleanup-tree-dump "vect" } } */
1764
1765=== added file 'gcc/testsuite/gcc.dg/vect/slp-11b.c'
1766--- old/gcc/testsuite/gcc.dg/vect/slp-11b.c 1970-01-01 00:00:00 +0000
1767+++ new/gcc/testsuite/gcc.dg/vect/slp-11b.c 2011-05-05 15:46:10 +0000
1768@@ -0,0 +1,49 @@
1769+/* { dg-require-effective-target vect_int } */
1770+
1771+#include <stdarg.h>
1772+#include "tree-vect.h"
1773+
1774+#define N 8
1775+
1776+int
1777+main1 ()
1778+{
1779+ int i;
1780+ unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
1781+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
1782+
1783+ /* Requires permutation - not SLPable. */
1784+ for (i = 0; i < N*2; i++)
1785+ {
1786+ out[i*4] = (in[i*4] + 2) * 3;
1787+ out[i*4 + 1] = (in[i*4 + 2] + 2) * 7;
1788+ out[i*4 + 2] = (in[i*4 + 1] + 7) * 3;
1789+ out[i*4 + 3] = (in[i*4 + 3] + 3) * 4;
1790+ }
1791+
1792+ /* check results: */
1793+ for (i = 0; i < N*2; i++)
1794+ {
1795+ if (out[i*4] != (in[i*4] + 2) * 3
1796+ || out[i*4 + 1] != (in[i*4 + 2] + 2) * 7
1797+ || out[i*4 + 2] != (in[i*4 + 1] + 7) * 3
1798+ || out[i*4 + 3] != (in[i*4 + 3] + 3) * 4)
1799+ abort ();
1800+ }
1801+
1802+ return 0;
1803+}
1804+
1805+int main (void)
1806+{
1807+ check_vect ();
1808+
1809+ main1 ();
1810+
1811+ return 0;
1812+}
1813+
1814+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided4 && vect_int_mult } } } } */
1815+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided4 && vect_int_mult } } } } } */
1816+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
1817+/* { dg-final { cleanup-tree-dump "vect" } } */
1818
1819=== added file 'gcc/testsuite/gcc.dg/vect/slp-11c.c'
1820--- old/gcc/testsuite/gcc.dg/vect/slp-11c.c 1970-01-01 00:00:00 +0000
1821+++ new/gcc/testsuite/gcc.dg/vect/slp-11c.c 2011-05-05 15:46:10 +0000
1822@@ -0,0 +1,46 @@
1823+/* { dg-require-effective-target vect_int } */
1824+
1825+#include <stdarg.h>
1826+#include "tree-vect.h"
1827+
1828+#define N 8
1829+
1830+int
1831+main1 ()
1832+{
1833+ int i;
1834+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
1835+ float out[N*8];
1836+
1837+ /* Different operations - not SLPable. */
1838+ for (i = 0; i < N*4; i++)
1839+ {
1840+ out[i*2] = ((float) in[i*2] * 2 + 6) ;
1841+ out[i*2 + 1] = (float) (in[i*2 + 1] * 3 + 7);
1842+ }
1843+
1844+ /* check results: */
1845+ for (i = 0; i < N*4; i++)
1846+ {
1847+ if (out[i*2] != ((float) in[i*2] * 2 + 6)
1848+ || out[i*2 + 1] != (float) (in[i*2 + 1] * 3 + 7))
1849+ abort ();
1850+ }
1851+
1852+
1853+ return 0;
1854+}
1855+
1856+int main (void)
1857+{
1858+ check_vect ();
1859+
1860+ main1 ();
1861+
1862+ return 0;
1863+}
1864+
1865+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { vect_uintfloat_cvt && vect_strided2 } && vect_int_mult } } } } */
1866+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { { vect_uintfloat_cvt && vect_strided2 } && vect_int_mult } } } } } */
1867+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
1868+/* { dg-final { cleanup-tree-dump "vect" } } */
1869
1870=== modified file 'gcc/testsuite/gcc.dg/vect/slp-12a.c'
1871--- old/gcc/testsuite/gcc.dg/vect/slp-12a.c 2010-11-22 12:16:52 +0000
1872+++ new/gcc/testsuite/gcc.dg/vect/slp-12a.c 2011-05-05 15:46:10 +0000
1873@@ -11,7 +11,7 @@
1874 int i;
1875 unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
1876 unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
1877- unsigned int ia[N], ib[N*2];
1878+ unsigned int ia[N];
1879
1880 for (i = 0; i < N; i++)
1881 {
1882@@ -61,27 +61,6 @@
1883 abort ();
1884 }
1885
1886- for (i = 0; i < N*2; i++)
1887- {
1888- out[i*4] = (in[i*4] + 2) * 3;
1889- out[i*4 + 1] = (in[i*4 + 1] + 2) * 7;
1890- out[i*4 + 2] = (in[i*4 + 2] + 7) * 3;
1891- out[i*4 + 3] = (in[i*4 + 3] + 7) * 7;
1892-
1893- ib[i] = 7;
1894- }
1895-
1896- /* check results: */
1897- for (i = 0; i < N*2; i++)
1898- {
1899- if (out[i*4] != (in[i*4] + 2) * 3
1900- || out[i*4 + 1] != (in[i*4 + 1] + 2) * 7
1901- || out[i*4 + 2] != (in[i*4 + 2] + 7) * 3
1902- || out[i*4 + 3] != (in[i*4 + 3] + 7) * 7
1903- || ib[i] != 7)
1904- abort ();
1905- }
1906-
1907 return 0;
1908 }
1909
1910@@ -94,11 +73,8 @@
1911 return 0;
1912 }
1913
1914-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" {target { vect_strided_wide && vect_int_mult} } } } */
1915-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {target { {! {vect_strided_wide}} && vect_int_mult } } } } */
1916-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { ! vect_int_mult } } } } */
1917-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" {target { vect_strided_wide && vect_int_mult } } } } */
1918-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" {target { {! {vect_strided_wide}} && vect_int_mult } } } } */
1919-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" {target { ! vect_int_mult } } } } */
1920+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided8 && vect_int_mult } } } } */
1921+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided8 && vect_int_mult } } } } } */
1922+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { vect_strided8 && vect_int_mult } } } } */
1923+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided8 && vect_int_mult } } } } } */
1924 /* { dg-final { cleanup-tree-dump "vect" } } */
1925-
1926
1927=== modified file 'gcc/testsuite/gcc.dg/vect/slp-12b.c'
1928--- old/gcc/testsuite/gcc.dg/vect/slp-12b.c 2010-11-22 12:16:52 +0000
1929+++ new/gcc/testsuite/gcc.dg/vect/slp-12b.c 2011-05-05 15:46:10 +0000
1930@@ -43,9 +43,9 @@
1931 return 0;
1932 }
1933
1934-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" {target { vect_strided_wide && vect_int_mult } } } } */
1935-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" {target { { ! { vect_int_mult }} || { ! {vect_strided_wide}}} } } } */
1936-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" {target { vect_strided_wide && vect_int_mult } } } } */
1937-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" {target { { ! { vect_int_mult }} || { ! {vect_strided_wide}}} } } } */
1938+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided2 && vect_int_mult } } } } */
1939+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { vect_strided2 && vect_int_mult } } } } } */
1940+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { vect_strided2 && vect_int_mult } } } } */
1941+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided2 && vect_int_mult } } } } } */
1942 /* { dg-final { cleanup-tree-dump "vect" } } */
1943
1944
1945=== added file 'gcc/testsuite/gcc.dg/vect/slp-12c.c'
1946--- old/gcc/testsuite/gcc.dg/vect/slp-12c.c 1970-01-01 00:00:00 +0000
1947+++ new/gcc/testsuite/gcc.dg/vect/slp-12c.c 2011-05-05 15:44:41 +0000
1948@@ -0,0 +1,53 @@
1949+/* { dg-require-effective-target vect_int } */
1950+
1951+#include <stdarg.h>
1952+#include "tree-vect.h"
1953+
1954+#define N 8
1955+
1956+int
1957+main1 ()
1958+{
1959+ int i;
1960+ unsigned int out[N*8], a0, a1, a2, a3, a4, a5, a6, a7, b1, b0, b2, b3, b4, b5, b6, b7;
1961+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
1962+ unsigned int ia[N*2];
1963+
1964+ for (i = 0; i < N*2; i++)
1965+ {
1966+ out[i*4] = (in[i*4] + 2) * 3;
1967+ out[i*4 + 1] = (in[i*4 + 1] + 2) * 7;
1968+ out[i*4 + 2] = (in[i*4 + 2] + 7) * 3;
1969+ out[i*4 + 3] = (in[i*4 + 3] + 7) * 7;
1970+
1971+ ia[i] = 7;
1972+ }
1973+
1974+ /* check results: */
1975+ for (i = 0; i < N*2; i++)
1976+ {
1977+ if (out[i*4] != (in[i*4] + 2) * 3
1978+ || out[i*4 + 1] != (in[i*4 + 1] + 2) * 7
1979+ || out[i*4 + 2] != (in[i*4 + 2] + 7) * 3
1980+ || out[i*4 + 3] != (in[i*4 + 3] + 7) * 7
1981+ || ia[i] != 7)
1982+ abort ();
1983+ }
1984+
1985+ return 0;
1986+}
1987+
1988+int main (void)
1989+{
1990+ check_vect ();
1991+
1992+ main1 ();
1993+
1994+ return 0;
1995+}
1996+
1997+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_int_mult } } } } */
1998+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_int_mult } } } } */
1999+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_int_mult } } } */
2000+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! vect_int_mult } } } } */
2001+/* { dg-final { cleanup-tree-dump "vect" } } */
2002
2003=== modified file 'gcc/testsuite/gcc.dg/vect/slp-18.c'
2004--- old/gcc/testsuite/gcc.dg/vect/slp-18.c 2010-11-22 12:16:52 +0000
2005+++ new/gcc/testsuite/gcc.dg/vect/slp-18.c 2011-05-05 15:46:10 +0000
2006@@ -91,7 +91,7 @@
2007 return 0;
2008 }
2009
2010-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_strided } } } } */
2011-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_strided } } } } */
2012+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2013+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_strided8 } } } */
2014 /* { dg-final { cleanup-tree-dump "vect" } } */
2015
2016
2017=== removed file 'gcc/testsuite/gcc.dg/vect/slp-19.c'
2018--- old/gcc/testsuite/gcc.dg/vect/slp-19.c 2010-11-22 12:16:52 +0000
2019+++ new/gcc/testsuite/gcc.dg/vect/slp-19.c 1970-01-01 00:00:00 +0000
2020@@ -1,154 +0,0 @@
2021-/* { dg-require-effective-target vect_int } */
2022-
2023-#include <stdarg.h>
2024-#include "tree-vect.h"
2025-
2026-#define N 16
2027-
2028-int
2029-main1 ()
2030-{
2031- unsigned int i;
2032- unsigned int out[N*8];
2033- unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
2034- unsigned int ia[N*2], a0, a1, a2, a3;
2035-
2036- for (i = 0; i < N; i++)
2037- {
2038- out[i*8] = in[i*8];
2039- out[i*8 + 1] = in[i*8 + 1];
2040- out[i*8 + 2] = in[i*8 + 2];
2041- out[i*8 + 3] = in[i*8 + 3];
2042- out[i*8 + 4] = in[i*8 + 4];
2043- out[i*8 + 5] = in[i*8 + 5];
2044- out[i*8 + 6] = in[i*8 + 6];
2045- out[i*8 + 7] = in[i*8 + 7];
2046-
2047- ia[i] = in[i*8 + 2];
2048- }
2049-
2050- /* check results: */
2051- for (i = 0; i < N; i++)
2052- {
2053- if (out[i*8] != in[i*8]
2054- || out[i*8 + 1] != in[i*8 + 1]
2055- || out[i*8 + 2] != in[i*8 + 2]
2056- || out[i*8 + 3] != in[i*8 + 3]
2057- || out[i*8 + 4] != in[i*8 + 4]
2058- || out[i*8 + 5] != in[i*8 + 5]
2059- || out[i*8 + 6] != in[i*8 + 6]
2060- || out[i*8 + 7] != in[i*8 + 7]
2061- || ia[i] != in[i*8 + 2])
2062- abort ();
2063- }
2064-
2065- for (i = 0; i < N*2; i++)
2066- {
2067- a0 = in[i*4] + 1;
2068- a1 = in[i*4 + 1] + 2;
2069- a2 = in[i*4 + 2] + 3;
2070- a3 = in[i*4 + 3] + 4;
2071-
2072- out[i*4] = a0;
2073- out[i*4 + 1] = a1;
2074- out[i*4 + 2] = a2;
2075- out[i*4 + 3] = a3;
2076-
2077- ia[i] = a2;
2078- }
2079-
2080- /* check results: */
2081- for (i = 0; i < N*2; i++)
2082- {
2083- if (out[i*4] != in[i*4] + 1
2084- || out[i*4 + 1] != in[i*4 + 1] + 2
2085- || out[i*4 + 2] != in[i*4 + 2] + 3
2086- || out[i*4 + 3] != in[i*4 + 3] + 4
2087- || ia[i] != in[i*4 + 2] + 3)
2088- abort ();
2089- }
2090-
2091- /* The last stmt requires interleaving of not power of 2 size - not
2092- vectorizable. */
2093- for (i = 0; i < N/2; i++)
2094- {
2095- out[i*12] = in[i*12];
2096- out[i*12 + 1] = in[i*12 + 1];
2097- out[i*12 + 2] = in[i*12 + 2];
2098- out[i*12 + 3] = in[i*12 + 3];
2099- out[i*12 + 4] = in[i*12 + 4];
2100- out[i*12 + 5] = in[i*12 + 5];
2101- out[i*12 + 6] = in[i*12 + 6];
2102- out[i*12 + 7] = in[i*12 + 7];
2103- out[i*12 + 8] = in[i*12 + 8];
2104- out[i*12 + 9] = in[i*12 + 9];
2105- out[i*12 + 10] = in[i*12 + 10];
2106- out[i*12 + 11] = in[i*12 + 11];
2107-
2108- ia[i] = in[i*12 + 7];
2109- }
2110-
2111- /* check results: */
2112- for (i = 0; i < N/2; i++)
2113- {
2114- if (out[i*12] != in[i*12]
2115- || out[i*12 + 1] != in[i*12 + 1]
2116- || out[i*12 + 2] != in[i*12 + 2]
2117- || out[i*12 + 3] != in[i*12 + 3]
2118- || out[i*12 + 4] != in[i*12 + 4]
2119- || out[i*12 + 5] != in[i*12 + 5]
2120- || out[i*12 + 6] != in[i*12 + 6]
2121- || out[i*12 + 7] != in[i*12 + 7]
2122- || out[i*12 + 8] != in[i*12 + 8]
2123- || out[i*12 + 9] != in[i*12 + 9]
2124- || out[i*12 + 10] != in[i*12 + 10]
2125- || out[i*12 + 11] != in[i*12 + 11]
2126- || ia[i] != in[i*12 + 7])
2127- abort ();
2128- }
2129-
2130- /* Hybrid SLP with unrolling by 2. */
2131- for (i = 0; i < N; i++)
2132- {
2133- out[i*6] = in[i*6];
2134- out[i*6 + 1] = in[i*6 + 1];
2135- out[i*6 + 2] = in[i*6 + 2];
2136- out[i*6 + 3] = in[i*6 + 3];
2137- out[i*6 + 4] = in[i*6 + 4];
2138- out[i*6 + 5] = in[i*6 + 5];
2139-
2140- ia[i] = i;
2141- }
2142-
2143- /* check results: */
2144- for (i = 0; i < N/2; i++)
2145- {
2146- if (out[i*6] != in[i*6]
2147- || out[i*6 + 1] != in[i*6 + 1]
2148- || out[i*6 + 2] != in[i*6 + 2]
2149- || out[i*6 + 3] != in[i*6 + 3]
2150- || out[i*6 + 4] != in[i*6 + 4]
2151- || out[i*6 + 5] != in[i*6 + 5]
2152- || ia[i] != i)
2153- abort ();
2154- }
2155-
2156-
2157- return 0;
2158-}
2159-
2160-int main (void)
2161-{
2162- check_vect ();
2163-
2164- main1 ();
2165-
2166- return 0;
2167-}
2168-
2169-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { target vect_strided_wide } } } */
2170-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided_wide } } } } } */
2171-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" { target vect_strided_wide } } } */
2172-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! { vect_strided_wide } } } } } */
2173-/* { dg-final { cleanup-tree-dump "vect" } } */
2174-
2175
2176=== added file 'gcc/testsuite/gcc.dg/vect/slp-19a.c'
2177--- old/gcc/testsuite/gcc.dg/vect/slp-19a.c 1970-01-01 00:00:00 +0000
2178+++ new/gcc/testsuite/gcc.dg/vect/slp-19a.c 2011-05-05 15:46:10 +0000
2179@@ -0,0 +1,61 @@
2180+/* { dg-require-effective-target vect_int } */
2181+
2182+#include <stdarg.h>
2183+#include "tree-vect.h"
2184+
2185+#define N 16
2186+
2187+int
2188+main1 ()
2189+{
2190+ unsigned int i;
2191+ unsigned int out[N*8];
2192+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
2193+ unsigned int ia[N*2];
2194+
2195+ for (i = 0; i < N; i++)
2196+ {
2197+ out[i*8] = in[i*8];
2198+ out[i*8 + 1] = in[i*8 + 1];
2199+ out[i*8 + 2] = in[i*8 + 2];
2200+ out[i*8 + 3] = in[i*8 + 3];
2201+ out[i*8 + 4] = in[i*8 + 4];
2202+ out[i*8 + 5] = in[i*8 + 5];
2203+ out[i*8 + 6] = in[i*8 + 6];
2204+ out[i*8 + 7] = in[i*8 + 7];
2205+
2206+ ia[i] = in[i*8 + 2];
2207+ }
2208+
2209+ /* check results: */
2210+ for (i = 0; i < N; i++)
2211+ {
2212+ if (out[i*8] != in[i*8]
2213+ || out[i*8 + 1] != in[i*8 + 1]
2214+ || out[i*8 + 2] != in[i*8 + 2]
2215+ || out[i*8 + 3] != in[i*8 + 3]
2216+ || out[i*8 + 4] != in[i*8 + 4]
2217+ || out[i*8 + 5] != in[i*8 + 5]
2218+ || out[i*8 + 6] != in[i*8 + 6]
2219+ || out[i*8 + 7] != in[i*8 + 7]
2220+ || ia[i] != in[i*8 + 2])
2221+ abort ();
2222+ }
2223+
2224+ return 0;
2225+}
2226+
2227+int main (void)
2228+{
2229+ check_vect ();
2230+
2231+ main1 ();
2232+
2233+ return 0;
2234+}
2235+
2236+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2237+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_strided8 } } } } */
2238+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided8 } } } */
2239+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! vect_strided8} } } } */
2240+/* { dg-final { cleanup-tree-dump "vect" } } */
2241
2242=== added file 'gcc/testsuite/gcc.dg/vect/slp-19b.c'
2243--- old/gcc/testsuite/gcc.dg/vect/slp-19b.c 1970-01-01 00:00:00 +0000
2244+++ new/gcc/testsuite/gcc.dg/vect/slp-19b.c 2011-05-05 15:46:10 +0000
2245@@ -0,0 +1,58 @@
2246+/* { dg-require-effective-target vect_int } */
2247+
2248+#include <stdarg.h>
2249+#include "tree-vect.h"
2250+
2251+#define N 16
2252+
2253+int
2254+main1 ()
2255+{
2256+ unsigned int i;
2257+ unsigned int out[N*8];
2258+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
2259+ unsigned int ia[N*2], a0, a1, a2, a3;
2260+
2261+ for (i = 0; i < N*2; i++)
2262+ {
2263+ a0 = in[i*4] + 1;
2264+ a1 = in[i*4 + 1] + 2;
2265+ a2 = in[i*4 + 2] + 3;
2266+ a3 = in[i*4 + 3] + 4;
2267+
2268+ out[i*4] = a0;
2269+ out[i*4 + 1] = a1;
2270+ out[i*4 + 2] = a2;
2271+ out[i*4 + 3] = a3;
2272+
2273+ ia[i] = a2;
2274+ }
2275+
2276+ /* check results: */
2277+ for (i = 0; i < N*2; i++)
2278+ {
2279+ if (out[i*4] != in[i*4] + 1
2280+ || out[i*4 + 1] != in[i*4 + 1] + 2
2281+ || out[i*4 + 2] != in[i*4 + 2] + 3
2282+ || out[i*4 + 3] != in[i*4 + 3] + 4
2283+ || ia[i] != in[i*4 + 2] + 3)
2284+ abort ();
2285+ }
2286+
2287+ return 0;
2288+}
2289+
2290+int main (void)
2291+{
2292+ check_vect ();
2293+
2294+ main1 ();
2295+
2296+ return 0;
2297+}
2298+
2299+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
2300+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! vect_strided4 } } } } */
2301+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_strided4 } } } */
2302+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! vect_strided4 } } } } */
2303+/* { dg-final { cleanup-tree-dump "vect" } } */
2304
2305=== added file 'gcc/testsuite/gcc.dg/vect/slp-19c.c'
2306--- old/gcc/testsuite/gcc.dg/vect/slp-19c.c 1970-01-01 00:00:00 +0000
2307+++ new/gcc/testsuite/gcc.dg/vect/slp-19c.c 2011-05-05 15:44:41 +0000
2308@@ -0,0 +1,95 @@
2309+/* { dg-require-effective-target vect_int } */
2310+
2311+#include <stdarg.h>
2312+#include "tree-vect.h"
2313+
2314+#define N 16
2315+
2316+int
2317+main1 ()
2318+{
2319+ unsigned int i;
2320+ unsigned int out[N*8];
2321+ unsigned int in[N*8] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63};
2322+ unsigned int ia[N*2], a0, a1, a2, a3;
2323+
2324+ /* The last stmt requires interleaving of not power of 2 size - not
2325+ vectorizable. */
2326+ for (i = 0; i < N/2; i++)
2327+ {
2328+ out[i*12] = in[i*12];
2329+ out[i*12 + 1] = in[i*12 + 1];
2330+ out[i*12 + 2] = in[i*12 + 2];
2331+ out[i*12 + 3] = in[i*12 + 3];
2332+ out[i*12 + 4] = in[i*12 + 4];
2333+ out[i*12 + 5] = in[i*12 + 5];
2334+ out[i*12 + 6] = in[i*12 + 6];
2335+ out[i*12 + 7] = in[i*12 + 7];
2336+ out[i*12 + 8] = in[i*12 + 8];
2337+ out[i*12 + 9] = in[i*12 + 9];
2338+ out[i*12 + 10] = in[i*12 + 10];
2339+ out[i*12 + 11] = in[i*12 + 11];
2340+
2341+ ia[i] = in[i*12 + 7];
2342+ }
2343+
2344+ /* check results: */
2345+ for (i = 0; i < N/2; i++)
2346+ {
2347+ if (out[i*12] != in[i*12]
2348+ || out[i*12 + 1] != in[i*12 + 1]
2349+ || out[i*12 + 2] != in[i*12 + 2]
2350+ || out[i*12 + 3] != in[i*12 + 3]
2351+ || out[i*12 + 4] != in[i*12 + 4]
2352+ || out[i*12 + 5] != in[i*12 + 5]
2353+ || out[i*12 + 6] != in[i*12 + 6]
2354+ || out[i*12 + 7] != in[i*12 + 7]
2355+ || out[i*12 + 8] != in[i*12 + 8]
2356+ || out[i*12 + 9] != in[i*12 + 9]
2357+ || out[i*12 + 10] != in[i*12 + 10]
2358+ || out[i*12 + 11] != in[i*12 + 11]
2359+ || ia[i] != in[i*12 + 7])
2360+ abort ();
2361+ }
2362+
2363+ /* Hybrid SLP with unrolling by 2. */
2364+ for (i = 0; i < N; i++)
2365+ {
2366+ out[i*6] = in[i*6];
2367+ out[i*6 + 1] = in[i*6 + 1];
2368+ out[i*6 + 2] = in[i*6 + 2];
2369+ out[i*6 + 3] = in[i*6 + 3];
2370+ out[i*6 + 4] = in[i*6 + 4];
2371+ out[i*6 + 5] = in[i*6 + 5];
2372+
2373+ ia[i] = i;
2374+ }
2375+
2376+ /* check results: */
2377+ for (i = 0; i < N/2; i++)
2378+ {
2379+ if (out[i*6] != in[i*6]
2380+ || out[i*6 + 1] != in[i*6 + 1]
2381+ || out[i*6 + 2] != in[i*6 + 2]
2382+ || out[i*6 + 3] != in[i*6 + 3]
2383+ || out[i*6 + 4] != in[i*6 + 4]
2384+ || out[i*6 + 5] != in[i*6 + 5]
2385+ || ia[i] != i)
2386+ abort ();
2387+ }
2388+
2389+ return 0;
2390+}
2391+
2392+int main (void)
2393+{
2394+ check_vect ();
2395+
2396+ main1 ();
2397+
2398+ return 0;
2399+}
2400+
2401+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
2402+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" } } */
2403+/* { dg-final { cleanup-tree-dump "vect" } } */
2404
2405=== modified file 'gcc/testsuite/gcc.dg/vect/slp-21.c'
2406--- old/gcc/testsuite/gcc.dg/vect/slp-21.c 2010-11-22 12:16:52 +0000
2407+++ new/gcc/testsuite/gcc.dg/vect/slp-21.c 2011-05-05 15:46:10 +0000
2408@@ -199,9 +199,9 @@
2409 return 0;
2410 }
2411
2412-/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" { target { vect_strided || vect_extract_even_odd } } } } */
2413-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided || vect_extract_even_odd } } } } } */
2414-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_strided } } } */
2415-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided } } } } } */
2416+/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" { target { vect_strided4 || vect_extract_even_odd } } } } */
2417+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided4 || vect_extract_even_odd } } } } } */
2418+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_strided4 } } } */
2419+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { vect_strided4 } } } } } */
2420 /* { dg-final { cleanup-tree-dump "vect" } } */
2421
2422
2423=== modified file 'gcc/testsuite/gcc.dg/vect/slp-23.c'
2424--- old/gcc/testsuite/gcc.dg/vect/slp-23.c 2011-01-10 12:51:00 +0000
2425+++ new/gcc/testsuite/gcc.dg/vect/slp-23.c 2011-05-05 15:46:10 +0000
2426@@ -106,8 +106,8 @@
2427 return 0;
2428 }
2429
2430-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided_wide } && {! { vect_no_align} } } } } */
2431-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided_wide || vect_no_align} } } } } */
2432+/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_strided8 && { ! { vect_no_align} } } } } } */
2433+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! { vect_strided8 || vect_no_align } } } } } */
2434 /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" } } */
2435 /* { dg-final { cleanup-tree-dump "vect" } } */
2436
2437
2438=== modified file 'gcc/testsuite/gcc.dg/vect/slp-reduc-6.c'
2439--- old/gcc/testsuite/gcc.dg/vect/slp-reduc-6.c 2010-11-22 12:16:52 +0000
2440+++ new/gcc/testsuite/gcc.dg/vect/slp-reduc-6.c 2011-05-05 15:46:10 +0000
2441@@ -42,7 +42,7 @@
2442 return 0;
2443 }
2444
2445-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail { vect_no_int_add || { ! vect_unpack } } } } } */
2446+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail { vect_no_int_add || { ! { vect_unpack || vect_strided2 } } } } } } */
2447 /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" } } */
2448 /* { dg-final { scan-tree-dump-times "different interleaving chains in one node" 1 "vect" { target { ! vect_no_int_add } } } } */
2449 /* { dg-final { cleanup-tree-dump "vect" } } */
2450
2451=== modified file 'gcc/testsuite/gcc.dg/vect/vect-1.c'
2452--- old/gcc/testsuite/gcc.dg/vect/vect-1.c 2010-08-19 10:23:50 +0000
2453+++ new/gcc/testsuite/gcc.dg/vect/vect-1.c 2011-05-05 15:46:10 +0000
2454@@ -85,6 +85,6 @@
2455 fbar (a);
2456 }
2457
2458-/* { dg-final { scan-tree-dump-times "vectorized 6 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */
2459-/* { dg-final { scan-tree-dump-times "vectorized 5 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */
2460+/* { dg-final { scan-tree-dump-times "vectorized 6 loops" 1 "vect" { target vect_strided2 } } } */
2461+/* { dg-final { scan-tree-dump-times "vectorized 5 loops" 1 "vect" { xfail vect_strided2 } } } */
2462 /* { dg-final { cleanup-tree-dump "vect" } } */
2463
2464=== modified file 'gcc/testsuite/gcc.dg/vect/vect-10.c'
2465--- old/gcc/testsuite/gcc.dg/vect/vect-10.c 2010-05-27 12:23:45 +0000
2466+++ new/gcc/testsuite/gcc.dg/vect/vect-10.c 2011-05-05 15:46:10 +0000
2467@@ -22,5 +22,5 @@
2468 return 0;
2469 }
2470
2471-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { ! vect_extract_even_odd } } } } */
2472+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { ! vect_strided2 } } } } */
2473 /* { dg-final { cleanup-tree-dump "vect" } } */
2474
2475=== modified file 'gcc/testsuite/gcc.dg/vect/vect-107.c'
2476--- old/gcc/testsuite/gcc.dg/vect/vect-107.c 2008-08-19 08:06:54 +0000
2477+++ new/gcc/testsuite/gcc.dg/vect/vect-107.c 2011-05-05 15:46:10 +0000
2478@@ -40,6 +40,6 @@
2479 return main1 ();
2480 }
2481
2482-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_extract_even_odd_wide } } } */
2483-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_extract_even_odd_wide } } } */
2484+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2485+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_strided2 } } } */
2486 /* { dg-final { cleanup-tree-dump "vect" } } */
2487
2488=== modified file 'gcc/testsuite/gcc.dg/vect/vect-98.c'
2489--- old/gcc/testsuite/gcc.dg/vect/vect-98.c 2008-08-02 11:05:47 +0000
2490+++ new/gcc/testsuite/gcc.dg/vect/vect-98.c 2011-05-05 15:46:10 +0000
2491@@ -38,6 +38,6 @@
2492 }
2493
2494 /* Needs interleaving support. */
2495-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */
2496-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail { vect_interleave && vect_extract_even_odd_wide } } } } */
2497+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
2498+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail vect_strided4 } } } */
2499 /* { dg-final { cleanup-tree-dump "vect" } } */
2500
2501=== modified file 'gcc/testsuite/gcc.dg/vect/vect-cselim-1.c'
2502--- old/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 2011-03-27 09:38:18 +0000
2503+++ new/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c 2011-05-05 15:46:10 +0000
2504@@ -82,5 +82,5 @@
2505 return 0;
2506 }
2507
2508-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || {! vect_strided } } } } } */
2509+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || { ! vect_strided2 } } } } } */
2510 /* { dg-final { cleanup-tree-dump "vect" } } */
2511
2512=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-mult.c'
2513--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-mult.c 2007-09-04 12:05:19 +0000
2514+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-mult.c 2011-05-05 15:46:10 +0000
2515@@ -71,6 +71,6 @@
2516 return 0;
2517 }
2518
2519-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2520+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2521 /* { dg-final { cleanup-tree-dump "vect" } } */
2522
2523
2524=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i2.c'
2525--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i2.c 2007-09-04 12:05:19 +0000
2526+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i2.c 2011-05-05 15:46:10 +0000
2527@@ -55,6 +55,6 @@
2528 return 0;
2529 }
2530
2531-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2532+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2533 /* { dg-final { cleanup-tree-dump "vect" } } */
2534
2535
2536=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i4.c'
2537--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i4.c 2007-09-04 12:05:19 +0000
2538+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-i4.c 2011-05-05 15:46:10 +0000
2539@@ -68,6 +68,6 @@
2540 return 0;
2541 }
2542
2543-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2544+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
2545 /* { dg-final { cleanup-tree-dump "vect" } } */
2546
2547
2548=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-mult.c'
2549--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-mult.c 2007-09-04 12:05:19 +0000
2550+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u16-mult.c 2011-05-05 15:46:10 +0000
2551@@ -62,6 +62,6 @@
2552 return 0;
2553 }
2554
2555-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2556+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2557 /* { dg-final { cleanup-tree-dump "vect" } } */
2558
2559
2560=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u32-mult.c'
2561--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u32-mult.c 2010-05-27 12:23:45 +0000
2562+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u32-mult.c 2011-05-05 15:46:10 +0000
2563@@ -61,6 +61,6 @@
2564 return 0;
2565 }
2566
2567-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2568+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2569 /* { dg-final { cleanup-tree-dump "vect" } } */
2570
2571
2572=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i2-gap.c'
2573--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i2-gap.c 2007-09-04 12:05:19 +0000
2574+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i2-gap.c 2011-05-05 15:46:10 +0000
2575@@ -69,6 +69,6 @@
2576 return 0;
2577 }
2578
2579-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2580+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2581 /* { dg-final { cleanup-tree-dump "vect" } } */
2582
2583
2584=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap2.c'
2585--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap2.c 2010-11-22 12:16:52 +0000
2586+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap2.c 2011-05-05 15:46:10 +0000
2587@@ -76,6 +76,6 @@
2588 return 0;
2589 }
2590
2591-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2592+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2593 /* { dg-final { cleanup-tree-dump "vect" } } */
2594
2595
2596=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap7.c'
2597--- old/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap7.c 2007-09-04 12:05:19 +0000
2598+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-a-u8-i8-gap7.c 2011-05-05 15:46:10 +0000
2599@@ -81,6 +81,6 @@
2600 return 0;
2601 }
2602
2603-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2604+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2605 /* { dg-final { cleanup-tree-dump "vect" } } */
2606
2607
2608=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-float.c'
2609--- old/gcc/testsuite/gcc.dg/vect/vect-strided-float.c 2008-08-19 08:06:54 +0000
2610+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-float.c 2011-05-05 15:46:10 +0000
2611@@ -39,7 +39,7 @@
2612 }
2613
2614 /* Needs interleaving support. */
2615-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd_wide } } } } */
2616-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave && vect_extract_even_odd_wide } } } } */
2617+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2618+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail vect_strided2 } } } */
2619 /* { dg-final { cleanup-tree-dump "vect" } } */
2620
2621
2622=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-mult-char-ls.c'
2623--- old/gcc/testsuite/gcc.dg/vect/vect-strided-mult-char-ls.c 2007-09-04 12:05:19 +0000
2624+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-mult-char-ls.c 2011-05-05 15:46:10 +0000
2625@@ -71,6 +71,6 @@
2626 return 0;
2627 }
2628
2629-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2630+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2631 /* { dg-final { cleanup-tree-dump "vect" } } */
2632
2633
2634=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-mult.c'
2635--- old/gcc/testsuite/gcc.dg/vect/vect-strided-mult.c 2007-09-04 12:05:19 +0000
2636+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-mult.c 2011-05-05 15:46:10 +0000
2637@@ -71,6 +71,6 @@
2638 return 0;
2639 }
2640
2641-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2642+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2643 /* { dg-final { cleanup-tree-dump "vect" } } */
2644
2645
2646=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-same-dr.c'
2647--- old/gcc/testsuite/gcc.dg/vect/vect-strided-same-dr.c 2007-09-04 12:05:19 +0000
2648+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-same-dr.c 2011-05-05 15:46:10 +0000
2649@@ -72,5 +72,5 @@
2650 return 0;
2651 }
2652
2653-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2654+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2655 /* { dg-final { cleanup-tree-dump "vect" } } */
2656
2657=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-store-a-u8-i2.c'
2658--- old/gcc/testsuite/gcc.dg/vect/vect-strided-store-a-u8-i2.c 2008-08-12 05:31:57 +0000
2659+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-store-a-u8-i2.c 2011-05-05 15:46:10 +0000
2660@@ -55,6 +55,6 @@
2661 return 0;
2662 }
2663
2664-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */
2665+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided2 } } } } */
2666 /* { dg-final { cleanup-tree-dump "vect" } } */
2667
2668
2669=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-store-u16-i4.c'
2670--- old/gcc/testsuite/gcc.dg/vect/vect-strided-store-u16-i4.c 2007-10-21 09:01:16 +0000
2671+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-store-u16-i4.c 2011-05-05 15:46:10 +0000
2672@@ -65,8 +65,8 @@
2673 return 0;
2674 }
2675
2676-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { vect_interleave && vect_pack_trunc } } } } */
2677-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { ! { vect_interleave } } && { vect_pack_trunc } } } } } */
2678+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { { vect_interleave || vect_strided4 } && vect_pack_trunc } } } } */
2679+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { ! { vect_interleave || vect_strided4 } } && { vect_pack_trunc } } } } } */
2680 /* { dg-final { cleanup-tree-dump "vect" } } */
2681
2682
2683
2684=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-store-u32-i2.c'
2685--- old/gcc/testsuite/gcc.dg/vect/vect-strided-store-u32-i2.c 2010-11-22 12:16:52 +0000
2686+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-store-u32-i2.c 2011-05-05 15:46:10 +0000
2687@@ -39,7 +39,7 @@
2688 }
2689
2690 /* Needs interleaving support. */
2691-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave } } } } */
2692-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave } } } } */
2693+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided2 } } } } */
2694+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave || vect_strided2 } } } } */
2695 /* { dg-final { cleanup-tree-dump "vect" } } */
2696
2697
2698=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u16-i2.c'
2699--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i2.c 2007-09-04 12:05:19 +0000
2700+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i2.c 2011-05-05 15:46:10 +0000
2701@@ -55,6 +55,6 @@
2702 return 0;
2703 }
2704
2705-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2706+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2707 /* { dg-final { cleanup-tree-dump "vect" } } */
2708
2709
2710=== added file 'gcc/testsuite/gcc.dg/vect/vect-strided-u16-i3.c'
2711--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i3.c 1970-01-01 00:00:00 +0000
2712+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i3.c 2011-05-05 15:46:25 +0000
2713@@ -0,0 +1,112 @@
2714+#include <stdarg.h>
2715+#include "tree-vect.h"
2716+
2717+#define N 128
2718+
2719+typedef struct {
2720+ unsigned short a;
2721+ unsigned short b;
2722+ unsigned short c;
2723+} s;
2724+
2725+#define A(I) (I)
2726+#define B(I) ((I) * 2)
2727+#define C(I) ((unsigned short) ~((I) ^ 0x18))
2728+
2729+void __attribute__ ((noinline))
2730+check1 (s *res)
2731+{
2732+ int i;
2733+
2734+ for (i = 0; i < N; i++)
2735+ if (res[i].a != C (i)
2736+ || res[i].b != A (i)
2737+ || res[i].c != B (i))
2738+ abort ();
2739+}
2740+
2741+void __attribute__ ((noinline))
2742+check2 (unsigned short *res)
2743+{
2744+ int i;
2745+
2746+ for (i = 0; i < N; i++)
2747+ if (res[i] != (unsigned short) (A (i) + B (i) + C (i)))
2748+ abort ();
2749+}
2750+
2751+void __attribute__ ((noinline))
2752+check3 (s *res)
2753+{
2754+ int i;
2755+
2756+ for (i = 0; i < N; i++)
2757+ if (res[i].a != i
2758+ || res[i].b != i
2759+ || res[i].c != i)
2760+ abort ();
2761+}
2762+
2763+void __attribute__ ((noinline))
2764+check4 (unsigned short *res)
2765+{
2766+ int i;
2767+
2768+ for (i = 0; i < N; i++)
2769+ if (res[i] != (unsigned short) (A (i) + B (i)))
2770+ abort ();
2771+}
2772+
2773+void __attribute__ ((noinline))
2774+main1 (s *arr)
2775+{
2776+ int i;
2777+ s *ptr = arr;
2778+ s res1[N];
2779+ unsigned short res2[N];
2780+
2781+ for (i = 0; i < N; i++)
2782+ {
2783+ res1[i].a = arr[i].c;
2784+ res1[i].b = arr[i].a;
2785+ res1[i].c = arr[i].b;
2786+ }
2787+ check1 (res1);
2788+
2789+ for (i = 0; i < N; i++)
2790+ res2[i] = arr[i].a + arr[i].b + arr[i].c;
2791+ check2 (res2);
2792+
2793+ for (i = 0; i < N; i++)
2794+ {
2795+ res1[i].a = i;
2796+ res1[i].b = i;
2797+ res1[i].c = i;
2798+ }
2799+ check3 (res1);
2800+
2801+ for (i = 0; i < N; i++)
2802+ res2[i] = arr[i].a + arr[i].b;
2803+ check4 (res2);
2804+}
2805+
2806+int main (void)
2807+{
2808+ int i;
2809+ s arr[N];
2810+
2811+ check_vect ();
2812+
2813+ for (i = 0; i < N; i++)
2814+ {
2815+ arr[i].a = A (i);
2816+ arr[i].b = B (i);
2817+ arr[i].c = C (i);
2818+ }
2819+ main1 (arr);
2820+
2821+ return 0;
2822+}
2823+
2824+/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" { target vect_strided3 } } } */
2825+/* { dg-final { cleanup-tree-dump "vect" } } */
2826
2827=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u16-i4.c'
2828--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i4.c 2007-09-04 12:05:19 +0000
2829+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u16-i4.c 2011-05-05 15:46:10 +0000
2830@@ -68,6 +68,6 @@
2831 return 0;
2832 }
2833
2834-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2835+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
2836 /* { dg-final { cleanup-tree-dump "vect" } } */
2837
2838
2839=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u32-i4.c'
2840--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i4.c 2007-09-04 12:05:19 +0000
2841+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i4.c 2011-05-05 15:46:10 +0000
2842@@ -63,6 +63,6 @@
2843 return 0;
2844 }
2845
2846-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2847+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided4 } } } */
2848 /* { dg-final { cleanup-tree-dump "vect" } } */
2849
2850
2851=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u32-i8.c'
2852--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i8.c 2007-09-04 12:05:19 +0000
2853+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u32-i8.c 2011-05-05 15:46:10 +0000
2854@@ -77,6 +77,6 @@
2855 return 0;
2856 }
2857
2858-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2859+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2860 /* { dg-final { cleanup-tree-dump "vect" } } */
2861
2862
2863=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u32-mult.c'
2864--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u32-mult.c 2010-05-27 12:23:45 +0000
2865+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u32-mult.c 2011-05-05 15:46:10 +0000
2866@@ -60,6 +60,6 @@
2867 return 0;
2868 }
2869
2870-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2871+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2872 /* { dg-final { cleanup-tree-dump "vect" } } */
2873
2874
2875=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2-gap.c'
2876--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2-gap.c 2007-09-04 12:05:19 +0000
2877+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2-gap.c 2011-05-05 15:46:10 +0000
2878@@ -71,6 +71,6 @@
2879 return 0;
2880 }
2881
2882-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2883+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2884 /* { dg-final { cleanup-tree-dump "vect" } } */
2885
2886
2887=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2.c'
2888--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2.c 2007-09-04 12:05:19 +0000
2889+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i2.c 2011-05-05 15:46:10 +0000
2890@@ -54,6 +54,6 @@
2891 return 0;
2892 }
2893
2894-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2895+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2896 /* { dg-final { cleanup-tree-dump "vect" } } */
2897
2898
2899=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap2.c'
2900--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap2.c 2010-11-22 12:16:52 +0000
2901+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap2.c 2011-05-05 15:46:10 +0000
2902@@ -78,6 +78,6 @@
2903 return 0;
2904 }
2905
2906-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2907+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2908 /* { dg-final { cleanup-tree-dump "vect" } } */
2909
2910
2911=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap4.c'
2912--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap4.c 2007-09-04 12:05:19 +0000
2913+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap4.c 2011-05-05 15:46:10 +0000
2914@@ -98,6 +98,6 @@
2915 return 0;
2916 }
2917
2918-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2919+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2920 /* { dg-final { cleanup-tree-dump "vect" } } */
2921
2922
2923=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap7.c'
2924--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap7.c 2007-09-04 12:05:19 +0000
2925+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8-gap7.c 2011-05-05 15:46:10 +0000
2926@@ -83,6 +83,6 @@
2927 return 0;
2928 }
2929
2930-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2931+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2932 /* { dg-final { cleanup-tree-dump "vect" } } */
2933
2934
2935=== modified file 'gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8.c'
2936--- old/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8.c 2010-11-22 12:16:52 +0000
2937+++ new/gcc/testsuite/gcc.dg/vect/vect-strided-u8-i8.c 2011-05-05 15:46:10 +0000
2938@@ -85,6 +85,6 @@
2939 return 0;
2940 }
2941
2942-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2943+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided8 } } } */
2944 /* { dg-final { cleanup-tree-dump "vect" } } */
2945
2946
2947=== modified file 'gcc/testsuite/gcc.dg/vect/vect-vfa-03.c'
2948--- old/gcc/testsuite/gcc.dg/vect/vect-vfa-03.c 2007-09-09 07:46:12 +0000
2949+++ new/gcc/testsuite/gcc.dg/vect/vect-vfa-03.c 2011-05-05 15:46:10 +0000
2950@@ -53,6 +53,6 @@
2951 }
2952
2953 /* Needs interleaving support. */
2954-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave && vect_extract_even_odd } } } } */
2955-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail { vect_interleave && vect_extract_even_odd } } } } */
2956+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_strided2 } } } */
2957+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { xfail vect_strided2 } } } */
2958 /* { dg-final { cleanup-tree-dump "vect" } } */
2959
2960=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp'
2961--- old/gcc/testsuite/gcc.dg/vect/vect.exp 2011-04-24 07:45:49 +0000
2962+++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2011-05-05 15:43:31 +0000
2963@@ -75,15 +75,20 @@
2964 lappend VECT_SLP_CFLAGS "-fdump-tree-slp-details"
2965
2966 # Main loop.
2967-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/pr*.\[cS\]]] \
2968- "" $DEFAULT_VECTCFLAGS
2969-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vect-*.\[cS\]]] \
2970- "" $DEFAULT_VECTCFLAGS
2971-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/slp-*.\[cS\]]] \
2972- "" $DEFAULT_VECTCFLAGS
2973-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/bb-slp*.\[cS\]]] \
2974- "" $VECT_SLP_CFLAGS
2975-
2976+set VECT_ADDITIONAL_FLAGS [list ""]
2977+if { [check_effective_target_lto] } {
2978+ lappend VECT_ADDITIONAL_FLAGS "-flto"
2979+}
2980+foreach flags $VECT_ADDITIONAL_FLAGS {
2981+ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/pr*.\[cS\]]] \
2982+ $flags $DEFAULT_VECTCFLAGS
2983+ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vect-*.\[cS\]]] \
2984+ $flags $DEFAULT_VECTCFLAGS
2985+ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/slp-*.\[cS\]]] \
2986+ $flags $DEFAULT_VECTCFLAGS
2987+ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/bb-slp*.\[cS\]]] \
2988+ $flags $VECT_SLP_CFLAGS
2989+}
2990
2991 #### Tests with special options
2992 global SAVED_DEFAULT_VECTCFLAGS
2993
2994=== modified file 'gcc/testsuite/lib/target-supports.exp'
2995--- old/gcc/testsuite/lib/target-supports.exp 2011-05-06 11:28:27 +0000
2996+++ new/gcc/testsuite/lib/target-supports.exp 2011-06-02 12:12:00 +0000
2997@@ -3139,29 +3139,6 @@
2998 return $et_vect_extract_even_odd_saved
2999 }
3000
3001-# Return 1 if the target supports vector even/odd elements extraction of
3002-# vectors with SImode elements or larger, 0 otherwise.
3003-
3004-proc check_effective_target_vect_extract_even_odd_wide { } {
3005- global et_vect_extract_even_odd_wide_saved
3006-
3007- if [info exists et_vect_extract_even_odd_wide_saved] {
3008- verbose "check_effective_target_vect_extract_even_odd_wide: using cached result" 2
3009- } else {
3010- set et_vect_extract_even_odd_wide_saved 0
3011- if { [istarget powerpc*-*-*]
3012- || [istarget i?86-*-*]
3013- || [istarget x86_64-*-*]
3014- || [istarget ia64-*-*]
3015- || [istarget spu-*-*] } {
3016- set et_vect_extract_even_odd_wide_saved 1
3017- }
3018- }
3019-
3020- verbose "check_effective_target_vect_extract_even_wide_odd: returning $et_vect_extract_even_odd_wide_saved" 2
3021- return $et_vect_extract_even_odd_wide_saved
3022-}
3023-
3024 # Return 1 if the target supports vector interleaving, 0 otherwise.
3025
3026 proc check_effective_target_vect_interleave { } {
3027@@ -3184,41 +3161,30 @@
3028 return $et_vect_interleave_saved
3029 }
3030
3031-# Return 1 if the target supports vector interleaving and extract even/odd, 0 otherwise.
3032-proc check_effective_target_vect_strided { } {
3033- global et_vect_strided_saved
3034-
3035- if [info exists et_vect_strided_saved] {
3036- verbose "check_effective_target_vect_strided: using cached result" 2
3037- } else {
3038- set et_vect_strided_saved 0
3039- if { [check_effective_target_vect_interleave]
3040- && [check_effective_target_vect_extract_even_odd] } {
3041- set et_vect_strided_saved 1
3042- }
3043- }
3044-
3045- verbose "check_effective_target_vect_strided: returning $et_vect_strided_saved" 2
3046- return $et_vect_strided_saved
3047-}
3048-
3049-# Return 1 if the target supports vector interleaving and extract even/odd
3050-# for wide element types, 0 otherwise.
3051-proc check_effective_target_vect_strided_wide { } {
3052- global et_vect_strided_wide_saved
3053-
3054- if [info exists et_vect_strided_wide_saved] {
3055- verbose "check_effective_target_vect_strided_wide: using cached result" 2
3056- } else {
3057- set et_vect_strided_wide_saved 0
3058- if { [check_effective_target_vect_interleave]
3059- && [check_effective_target_vect_extract_even_odd_wide] } {
3060- set et_vect_strided_wide_saved 1
3061- }
3062- }
3063-
3064- verbose "check_effective_target_vect_strided_wide: returning $et_vect_strided_wide_saved" 2
3065- return $et_vect_strided_wide_saved
3066+foreach N {2 3 4 8} {
3067+ eval [string map [list N $N] {
3068+ # Return 1 if the target supports 2-vector interleaving
3069+ proc check_effective_target_vect_stridedN { } {
3070+ global et_vect_stridedN_saved
3071+
3072+ if [info exists et_vect_stridedN_saved] {
3073+ verbose "check_effective_target_vect_stridedN: using cached result" 2
3074+ } else {
3075+ set et_vect_stridedN_saved 0
3076+ if { (N & -N) == N
3077+ && [check_effective_target_vect_interleave]
3078+ && [check_effective_target_vect_extract_even_odd] } {
3079+ set et_vect_stridedN_saved 1
3080+ }
3081+ if { [istarget arm*-*-*] && N >= 2 && N <= 4 } {
3082+ set et_vect_stridedN_saved 1
3083+ }
3084+ }
3085+
3086+ verbose "check_effective_target_vect_stridedN: returning $et_vect_stridedN_saved" 2
3087+ return $et_vect_stridedN_saved
3088+ }
3089+ }]
3090 }
3091
3092 # Return 1 if the target supports section-anchors
3093
3094=== modified file 'gcc/tree-cfg.c'
3095--- old/gcc/tree-cfg.c 2011-02-12 21:11:33 +0000
3096+++ new/gcc/tree-cfg.c 2011-05-05 15:42:22 +0000
3097@@ -3046,7 +3046,26 @@
3098 tree fntype;
3099 unsigned i;
3100
3101- if (TREE_CODE (fn) != OBJ_TYPE_REF
3102+ if (gimple_call_internal_p (stmt))
3103+ {
3104+ if (fn)
3105+ {
3106+ error ("gimple call has two targets");
3107+ debug_generic_stmt (fn);
3108+ return true;
3109+ }
3110+ }
3111+ else
3112+ {
3113+ if (!fn)
3114+ {
3115+ error ("gimple call has no target");
3116+ return true;
3117+ }
3118+ }
3119+
3120+ if (fn
3121+ && TREE_CODE (fn) != OBJ_TYPE_REF
3122 && !is_gimple_val (fn))
3123 {
3124 error ("invalid function in gimple call");
3125@@ -3054,9 +3073,10 @@
3126 return true;
3127 }
3128
3129- if (!POINTER_TYPE_P (TREE_TYPE (fn))
3130- || (TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != FUNCTION_TYPE
3131- && TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != METHOD_TYPE))
3132+ if (fn
3133+ && (!POINTER_TYPE_P (TREE_TYPE (fn))
3134+ || (TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != FUNCTION_TYPE
3135+ && TREE_CODE (TREE_TYPE (TREE_TYPE (fn))) != METHOD_TYPE)))
3136 {
3137 error ("non-function in gimple call");
3138 return true;
3139@@ -3076,8 +3096,12 @@
3140 return true;
3141 }
3142
3143- fntype = TREE_TYPE (TREE_TYPE (fn));
3144- if (gimple_call_lhs (stmt)
3145+ if (fn)
3146+ fntype = TREE_TYPE (TREE_TYPE (fn));
3147+ else
3148+ fntype = NULL_TREE;
3149+ if (fntype
3150+ && gimple_call_lhs (stmt)
3151 && !useless_type_conversion_p (TREE_TYPE (gimple_call_lhs (stmt)),
3152 TREE_TYPE (fntype))
3153 /* ??? At least C++ misses conversions at assignments from
3154@@ -4130,9 +4154,10 @@
3155 didn't see a function declaration before the call. */
3156 if (is_gimple_call (stmt))
3157 {
3158- tree decl;
3159+ tree fn, decl;
3160
3161- if (!is_gimple_call_addr (gimple_call_fn (stmt)))
3162+ fn = gimple_call_fn (stmt);
3163+ if (fn && !is_gimple_call_addr (fn))
3164 {
3165 error ("invalid function in call statement");
3166 return true;
3167@@ -7484,6 +7509,8 @@
3168 case GIMPLE_CALL:
3169 if (gimple_call_lhs (g))
3170 break;
3171+ if (gimple_call_internal_p (g))
3172+ break;
3173
3174 /* This is a naked call, as opposed to a GIMPLE_CALL with an
3175 LHS. All calls whose value is ignored should be
3176
3177=== modified file 'gcc/tree-eh.c'
3178--- old/gcc/tree-eh.c 2011-05-10 06:31:59 +0000
3179+++ new/gcc/tree-eh.c 2011-06-02 12:12:00 +0000
3180@@ -2745,7 +2745,7 @@
3181 || gimple_call_lhs (twos)
3182 || gimple_call_chain (ones)
3183 || gimple_call_chain (twos)
3184- || !operand_equal_p (gimple_call_fn (ones), gimple_call_fn (twos), 0)
3185+ || !gimple_call_same_target_p (ones, twos)
3186 || gimple_call_num_args (ones) != gimple_call_num_args (twos))
3187 return false;
3188
3189
3190=== modified file 'gcc/tree-inline.c'
3191--- old/gcc/tree-inline.c 2011-05-05 21:02:06 +0000
3192+++ new/gcc/tree-inline.c 2011-06-02 12:12:00 +0000
3193@@ -3471,10 +3471,13 @@
3194 {
3195 tree decl = gimple_call_fndecl (stmt);
3196 tree addr = gimple_call_fn (stmt);
3197- tree funtype = TREE_TYPE (addr);
3198+ tree funtype = NULL_TREE;
3199 bool stdarg = false;
3200
3201- if (POINTER_TYPE_P (funtype))
3202+ if (addr)
3203+ funtype = TREE_TYPE (addr);
3204+
3205+ if (funtype && POINTER_TYPE_P (funtype))
3206 funtype = TREE_TYPE (funtype);
3207
3208 /* Do not special case builtins where we see the body.
3209@@ -3514,7 +3517,7 @@
3210 if (decl)
3211 funtype = TREE_TYPE (decl);
3212
3213- if (!VOID_TYPE_P (TREE_TYPE (funtype)))
3214+ if (funtype && !VOID_TYPE_P (TREE_TYPE (funtype)))
3215 cost += estimate_move_cost (TREE_TYPE (funtype));
3216
3217 if (funtype)
3218
3219=== modified file 'gcc/tree-ssa-ccp.c'
3220--- old/gcc/tree-ssa-ccp.c 2011-01-31 16:52:22 +0000
3221+++ new/gcc/tree-ssa-ccp.c 2011-05-05 15:42:22 +0000
3222@@ -1279,7 +1279,10 @@
3223
3224 case GIMPLE_CALL:
3225 {
3226- tree fn = valueize_op (gimple_call_fn (stmt));
3227+ tree fn = gimple_call_fn (stmt);
3228+ if (!fn)
3229+ return NULL_TREE;
3230+ fn = valueize_op (fn);
3231 if (TREE_CODE (fn) == ADDR_EXPR
3232 && TREE_CODE (TREE_OPERAND (fn, 0)) == FUNCTION_DECL
3233 && DECL_BUILT_IN (TREE_OPERAND (fn, 0)))
3234@@ -2310,6 +2313,11 @@
3235 return true;
3236 }
3237
3238+ /* Internal calls provide no argument types, so the extra laxity
3239+ for normal calls does not apply. */
3240+ if (gimple_call_internal_p (stmt))
3241+ return false;
3242+
3243 /* Propagate into the call arguments. Compared to replace_uses_in
3244 this can use the argument slot types for type verification
3245 instead of the current argument type. We also can safely
3246
3247=== modified file 'gcc/tree-ssa-dom.c'
3248--- old/gcc/tree-ssa-dom.c 2011-02-14 17:59:10 +0000
3249+++ new/gcc/tree-ssa-dom.c 2011-05-05 15:42:22 +0000
3250@@ -64,7 +64,7 @@
3251 struct { enum tree_code op; tree opnd; } unary;
3252 struct { enum tree_code op; tree opnd0, opnd1; } binary;
3253 struct { enum tree_code op; tree opnd0, opnd1, opnd2; } ternary;
3254- struct { tree fn; bool pure; size_t nargs; tree *args; } call;
3255+ struct { gimple fn_from; bool pure; size_t nargs; tree *args; } call;
3256 } ops;
3257 };
3258
3259@@ -258,7 +258,7 @@
3260
3261 expr->type = TREE_TYPE (gimple_call_lhs (stmt));
3262 expr->kind = EXPR_CALL;
3263- expr->ops.call.fn = gimple_call_fn (stmt);
3264+ expr->ops.call.fn_from = stmt;
3265
3266 if (gimple_call_flags (stmt) & (ECF_CONST | ECF_PURE))
3267 expr->ops.call.pure = true;
3268@@ -422,8 +422,8 @@
3269
3270 /* If the calls are to different functions, then they
3271 clearly cannot be equal. */
3272- if (! operand_equal_p (expr0->ops.call.fn,
3273- expr1->ops.call.fn, 0))
3274+ if (!gimple_call_same_target_p (expr0->ops.call.fn_from,
3275+ expr1->ops.call.fn_from))
3276 return false;
3277
3278 if (! expr0->ops.call.pure)
3279@@ -503,9 +503,15 @@
3280 {
3281 size_t i;
3282 enum tree_code code = CALL_EXPR;
3283+ gimple fn_from;
3284
3285 val = iterative_hash_object (code, val);
3286- val = iterative_hash_expr (expr->ops.call.fn, val);
3287+ fn_from = expr->ops.call.fn_from;
3288+ if (gimple_call_internal_p (fn_from))
3289+ val = iterative_hash_hashval_t
3290+ ((hashval_t) gimple_call_internal_fn (fn_from), val);
3291+ else
3292+ val = iterative_hash_expr (gimple_call_fn (fn_from), val);
3293 for (i = 0; i < expr->ops.call.nargs; i++)
3294 val = iterative_hash_expr (expr->ops.call.args[i], val);
3295 }
3296@@ -565,8 +571,14 @@
3297 {
3298 size_t i;
3299 size_t nargs = element->expr.ops.call.nargs;
3300+ gimple fn_from;
3301
3302- print_generic_expr (stream, element->expr.ops.call.fn, 0);
3303+ fn_from = element->expr.ops.call.fn_from;
3304+ if (gimple_call_internal_p (fn_from))
3305+ fputs (internal_fn_name (gimple_call_internal_fn (fn_from)),
3306+ stream);
3307+ else
3308+ print_generic_expr (stream, gimple_call_fn (fn_from), 0);
3309 fprintf (stream, " (");
3310 for (i = 0; i < nargs; i++)
3311 {
3312
3313=== modified file 'gcc/tree-ssa-pre.c'
3314--- old/gcc/tree-ssa-pre.c 2011-02-15 13:04:47 +0000
3315+++ new/gcc/tree-ssa-pre.c 2011-05-05 15:42:22 +0000
3316@@ -2657,11 +2657,13 @@
3317 }
3318
3319 /* Return true if we can value number the call in STMT. This is true
3320- if we have a pure or constant call. */
3321+ if we have a pure or constant call to a real function. */
3322
3323 static bool
3324 can_value_number_call (gimple stmt)
3325 {
3326+ if (gimple_call_internal_p (stmt))
3327+ return false;
3328 if (gimple_call_flags (stmt) & (ECF_PURE | ECF_CONST))
3329 return true;
3330 return false;
3331@@ -4187,6 +4189,7 @@
3332 gimple_stmt_iterator gsi;
3333 gimple stmt;
3334 unsigned i;
3335+ tree fn;
3336
3337 FOR_EACH_BB (b)
3338 {
3339@@ -4378,9 +4381,10 @@
3340 /* Visit indirect calls and turn them into direct calls if
3341 possible. */
3342 if (is_gimple_call (stmt)
3343- && TREE_CODE (gimple_call_fn (stmt)) == SSA_NAME)
3344+ && (fn = gimple_call_fn (stmt))
3345+ && TREE_CODE (fn) == SSA_NAME)
3346 {
3347- tree fn = VN_INFO (gimple_call_fn (stmt))->valnum;
3348+ fn = VN_INFO (fn)->valnum;
3349 if (TREE_CODE (fn) == ADDR_EXPR
3350 && TREE_CODE (TREE_OPERAND (fn, 0)) == FUNCTION_DECL)
3351 {
3352
3353=== modified file 'gcc/tree-ssa-sccvn.c'
3354--- old/gcc/tree-ssa-sccvn.c 2011-05-12 14:08:00 +0000
3355+++ new/gcc/tree-ssa-sccvn.c 2011-06-02 12:12:00 +0000
3356@@ -2982,7 +2982,8 @@
3357 /* ??? We should handle stores from calls. */
3358 else if (TREE_CODE (lhs) == SSA_NAME)
3359 {
3360- if (gimple_call_flags (stmt) & (ECF_PURE | ECF_CONST))
3361+ if (!gimple_call_internal_p (stmt)
3362+ && gimple_call_flags (stmt) & (ECF_PURE | ECF_CONST))
3363 changed = visit_reference_op_call (lhs, stmt);
3364 else
3365 changed = defs_to_varying (stmt);
3366
3367=== modified file 'gcc/tree-ssa-structalias.c'
3368--- old/gcc/tree-ssa-structalias.c 2011-02-10 15:29:52 +0000
3369+++ new/gcc/tree-ssa-structalias.c 2011-05-05 15:42:22 +0000
3370@@ -4319,6 +4319,7 @@
3371 /* Fallthru to general call handling. */;
3372 }
3373 if (!in_ipa_mode
3374+ || gimple_call_internal_p (t)
3375 || (fndecl
3376 && (!(fi = lookup_vi_for_tree (fndecl))
3377 || !fi->is_fn_info)))
3378
3379=== modified file 'gcc/tree-vect-data-refs.c'
3380--- old/gcc/tree-vect-data-refs.c 2011-05-06 11:28:27 +0000
3381+++ new/gcc/tree-vect-data-refs.c 2011-06-02 12:12:00 +0000
3382@@ -43,6 +43,45 @@
3383 #include "expr.h"
3384 #include "optabs.h"
3385
3386+/* Return true if load- or store-lanes optab OPTAB is implemented for
3387+ COUNT vectors of type VECTYPE. NAME is the name of OPTAB. */
3388+
3389+static bool
3390+vect_lanes_optab_supported_p (const char *name, convert_optab optab,
3391+ tree vectype, unsigned HOST_WIDE_INT count)
3392+{
3393+ enum machine_mode mode, array_mode;
3394+ bool limit_p;
3395+
3396+ mode = TYPE_MODE (vectype);
3397+ limit_p = !targetm.array_mode_supported_p (mode, count);
3398+ array_mode = mode_for_size (count * GET_MODE_BITSIZE (mode),
3399+ MODE_INT, limit_p);
3400+
3401+ if (array_mode == BLKmode)
3402+ {
3403+ if (vect_print_dump_info (REPORT_DETAILS))
3404+ fprintf (vect_dump, "no array mode for %s[" HOST_WIDE_INT_PRINT_DEC "]",
3405+ GET_MODE_NAME (mode), count);
3406+ return false;
3407+ }
3408+
3409+ if (convert_optab_handler (optab, array_mode, mode) == CODE_FOR_nothing)
3410+ {
3411+ if (vect_print_dump_info (REPORT_DETAILS))
3412+ fprintf (vect_dump, "cannot use %s<%s><%s>",
3413+ name, GET_MODE_NAME (array_mode), GET_MODE_NAME (mode));
3414+ return false;
3415+ }
3416+
3417+ if (vect_print_dump_info (REPORT_DETAILS))
3418+ fprintf (vect_dump, "can use %s<%s><%s>",
3419+ name, GET_MODE_NAME (array_mode), GET_MODE_NAME (mode));
3420+
3421+ return true;
3422+}
3423+
3424+
3425 /* Return the smallest scalar part of STMT.
3426 This is used to determine the vectype of the stmt. We generally set the
3427 vectype according to the type of the result (lhs). For stmts whose
3428@@ -2196,19 +2235,6 @@
3429 return false;
3430 }
3431
3432- /* FORNOW: we handle only interleaving that is a power of 2.
3433- We don't fail here if it may be still possible to vectorize the
3434- group using SLP. If not, the size of the group will be checked in
3435- vect_analyze_operations, and the vectorization will fail. */
3436- if (exact_log2 (stride) == -1)
3437- {
3438- if (vect_print_dump_info (REPORT_DETAILS))
3439- fprintf (vect_dump, "interleaving is not a power of 2");
3440-
3441- if (slp_impossible)
3442- return false;
3443- }
3444-
3445 if (stride == 0)
3446 stride = count;
3447
3448@@ -2911,31 +2937,33 @@
3449
3450 /* Function vect_create_data_ref_ptr.
3451
3452- Create a new pointer to vector type (vp), that points to the first location
3453- accessed in the loop by STMT, along with the def-use update chain to
3454- appropriately advance the pointer through the loop iterations. Also set
3455- aliasing information for the pointer. This vector pointer is used by the
3456- callers to this function to create a memory reference expression for vector
3457- load/store access.
3458+ Create a new pointer-to-AGGR_TYPE variable (ap), that points to the first
3459+ location accessed in the loop by STMT, along with the def-use update
3460+ chain to appropriately advance the pointer through the loop iterations.
3461+ Also set aliasing information for the pointer. This pointer is used by
3462+ the callers to this function to create a memory reference expression for
3463+ vector load/store access.
3464
3465 Input:
3466 1. STMT: a stmt that references memory. Expected to be of the form
3467 GIMPLE_ASSIGN <name, data-ref> or
3468 GIMPLE_ASSIGN <data-ref, name>.
3469- 2. AT_LOOP: the loop where the vector memref is to be created.
3470- 3. OFFSET (optional): an offset to be added to the initial address accessed
3471+ 2. AGGR_TYPE: the type of the reference, which should be either a vector
3472+ or an array.
3473+ 3. AT_LOOP: the loop where the vector memref is to be created.
3474+ 4. OFFSET (optional): an offset to be added to the initial address accessed
3475 by the data-ref in STMT.
3476- 4. ONLY_INIT: indicate if vp is to be updated in the loop, or remain
3477+ 5. ONLY_INIT: indicate if vp is to be updated in the loop, or remain
3478 pointing to the initial address.
3479- 5. TYPE: if not NULL indicates the required type of the data-ref.
3480+ 6. TYPE: if not NULL indicates the required type of the data-ref.
3481
3482 Output:
3483 1. Declare a new ptr to vector_type, and have it point to the base of the
3484 data reference (initial addressed accessed by the data reference).
3485 For example, for vector of type V8HI, the following code is generated:
3486
3487- v8hi *vp;
3488- vp = (v8hi *)initial_address;
3489+ v8hi *ap;
3490+ ap = (v8hi *)initial_address;
3491
3492 if OFFSET is not supplied:
3493 initial_address = &a[init];
3494@@ -2955,7 +2983,7 @@
3495 4. Return the pointer. */
3496
3497 tree
3498-vect_create_data_ref_ptr (gimple stmt, struct loop *at_loop,
3499+vect_create_data_ref_ptr (gimple stmt, tree aggr_type, struct loop *at_loop,
3500 tree offset, tree *initial_address, gimple *ptr_incr,
3501 bool only_init, bool *inv_p)
3502 {
3503@@ -2965,17 +2993,16 @@
3504 struct loop *loop = NULL;
3505 bool nested_in_vect_loop = false;
3506 struct loop *containing_loop = NULL;
3507- tree vectype = STMT_VINFO_VECTYPE (stmt_info);
3508- tree vect_ptr_type;
3509- tree vect_ptr;
3510+ tree aggr_ptr_type;
3511+ tree aggr_ptr;
3512 tree new_temp;
3513 gimple vec_stmt;
3514 gimple_seq new_stmt_list = NULL;
3515 edge pe = NULL;
3516 basic_block new_bb;
3517- tree vect_ptr_init;
3518+ tree aggr_ptr_init;
3519 struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info);
3520- tree vptr;
3521+ tree aptr;
3522 gimple_stmt_iterator incr_gsi;
3523 bool insert_after;
3524 bool negative;
3525@@ -2986,6 +3013,9 @@
3526 gimple_stmt_iterator gsi = gsi_for_stmt (stmt);
3527 tree base;
3528
3529+ gcc_assert (TREE_CODE (aggr_type) == ARRAY_TYPE
3530+ || TREE_CODE (aggr_type) == VECTOR_TYPE);
3531+
3532 if (loop_vinfo)
3533 {
3534 loop = LOOP_VINFO_LOOP (loop_vinfo);
3535@@ -3020,8 +3050,9 @@
3536 if (vect_print_dump_info (REPORT_DETAILS))
3537 {
3538 tree data_ref_base = base_name;
3539- fprintf (vect_dump, "create vector-pointer variable to type: ");
3540- print_generic_expr (vect_dump, vectype, TDF_SLIM);
3541+ fprintf (vect_dump, "create %s-pointer variable to type: ",
3542+ tree_code_name[(int) TREE_CODE (aggr_type)]);
3543+ print_generic_expr (vect_dump, aggr_type, TDF_SLIM);
3544 if (TREE_CODE (data_ref_base) == VAR_DECL
3545 || TREE_CODE (data_ref_base) == ARRAY_REF)
3546 fprintf (vect_dump, " vectorizing an array ref: ");
3547@@ -3032,27 +3063,28 @@
3548 print_generic_expr (vect_dump, base_name, TDF_SLIM);
3549 }
3550
3551- /* (1) Create the new vector-pointer variable. */
3552- vect_ptr_type = build_pointer_type (vectype);
3553+ /* (1) Create the new aggregate-pointer variable. */
3554+ aggr_ptr_type = build_pointer_type (aggr_type);
3555 base = get_base_address (DR_REF (dr));
3556 if (base
3557 && TREE_CODE (base) == MEM_REF)
3558- vect_ptr_type
3559- = build_qualified_type (vect_ptr_type,
3560+ aggr_ptr_type
3561+ = build_qualified_type (aggr_ptr_type,
3562 TYPE_QUALS (TREE_TYPE (TREE_OPERAND (base, 0))));
3563- vect_ptr = vect_get_new_vect_var (vect_ptr_type, vect_pointer_var,
3564+ aggr_ptr = vect_get_new_vect_var (aggr_ptr_type, vect_pointer_var,
3565 get_name (base_name));
3566
3567- /* Vector types inherit the alias set of their component type by default so
3568- we need to use a ref-all pointer if the data reference does not conflict
3569- with the created vector data reference because it is not addressable. */
3570- if (!alias_sets_conflict_p (get_deref_alias_set (vect_ptr),
3571+ /* Vector and array types inherit the alias set of their component
3572+ type by default so we need to use a ref-all pointer if the data
3573+ reference does not conflict with the created aggregated data
3574+ reference because it is not addressable. */
3575+ if (!alias_sets_conflict_p (get_deref_alias_set (aggr_ptr),
3576 get_alias_set (DR_REF (dr))))
3577 {
3578- vect_ptr_type
3579- = build_pointer_type_for_mode (vectype,
3580- TYPE_MODE (vect_ptr_type), true);
3581- vect_ptr = vect_get_new_vect_var (vect_ptr_type, vect_pointer_var,
3582+ aggr_ptr_type
3583+ = build_pointer_type_for_mode (aggr_type,
3584+ TYPE_MODE (aggr_ptr_type), true);
3585+ aggr_ptr = vect_get_new_vect_var (aggr_ptr_type, vect_pointer_var,
3586 get_name (base_name));
3587 }
3588
3589@@ -3063,14 +3095,14 @@
3590 do
3591 {
3592 tree lhs = gimple_assign_lhs (orig_stmt);
3593- if (!alias_sets_conflict_p (get_deref_alias_set (vect_ptr),
3594+ if (!alias_sets_conflict_p (get_deref_alias_set (aggr_ptr),
3595 get_alias_set (lhs)))
3596 {
3597- vect_ptr_type
3598- = build_pointer_type_for_mode (vectype,
3599- TYPE_MODE (vect_ptr_type), true);
3600- vect_ptr
3601- = vect_get_new_vect_var (vect_ptr_type, vect_pointer_var,
3602+ aggr_ptr_type
3603+ = build_pointer_type_for_mode (aggr_type,
3604+ TYPE_MODE (aggr_ptr_type), true);
3605+ aggr_ptr
3606+ = vect_get_new_vect_var (aggr_ptr_type, vect_pointer_var,
3607 get_name (base_name));
3608 break;
3609 }
3610@@ -3080,7 +3112,7 @@
3611 while (orig_stmt);
3612 }
3613
3614- add_referenced_var (vect_ptr);
3615+ add_referenced_var (aggr_ptr);
3616
3617 /* Note: If the dataref is in an inner-loop nested in LOOP, and we are
3618 vectorizing LOOP (i.e., outer-loop vectorization), we need to create two
3619@@ -3113,8 +3145,8 @@
3620 vp2 = vp1 + step
3621 if () goto LOOP */
3622
3623- /* (2) Calculate the initial address the vector-pointer, and set
3624- the vector-pointer to point to it before the loop. */
3625+ /* (2) Calculate the initial address of the aggregate-pointer, and set
3626+ the aggregate-pointer to point to it before the loop. */
3627
3628 /* Create: (&(base[init_val+offset]) in the loop preheader. */
3629
3630@@ -3133,17 +3165,17 @@
3631
3632 *initial_address = new_temp;
3633
3634- /* Create: p = (vectype *) initial_base */
3635+ /* Create: p = (aggr_type *) initial_base */
3636 if (TREE_CODE (new_temp) != SSA_NAME
3637- || !useless_type_conversion_p (vect_ptr_type, TREE_TYPE (new_temp)))
3638+ || !useless_type_conversion_p (aggr_ptr_type, TREE_TYPE (new_temp)))
3639 {
3640- vec_stmt = gimple_build_assign (vect_ptr,
3641- fold_convert (vect_ptr_type, new_temp));
3642- vect_ptr_init = make_ssa_name (vect_ptr, vec_stmt);
3643+ vec_stmt = gimple_build_assign (aggr_ptr,
3644+ fold_convert (aggr_ptr_type, new_temp));
3645+ aggr_ptr_init = make_ssa_name (aggr_ptr, vec_stmt);
3646 /* Copy the points-to information if it exists. */
3647 if (DR_PTR_INFO (dr))
3648- duplicate_ssa_name_ptr_info (vect_ptr_init, DR_PTR_INFO (dr));
3649- gimple_assign_set_lhs (vec_stmt, vect_ptr_init);
3650+ duplicate_ssa_name_ptr_info (aggr_ptr_init, DR_PTR_INFO (dr));
3651+ gimple_assign_set_lhs (vec_stmt, aggr_ptr_init);
3652 if (pe)
3653 {
3654 new_bb = gsi_insert_on_edge_immediate (pe, vec_stmt);
3655@@ -3153,19 +3185,19 @@
3656 gsi_insert_before (&gsi, vec_stmt, GSI_SAME_STMT);
3657 }
3658 else
3659- vect_ptr_init = new_temp;
3660+ aggr_ptr_init = new_temp;
3661
3662- /* (3) Handle the updating of the vector-pointer inside the loop.
3663+ /* (3) Handle the updating of the aggregate-pointer inside the loop.
3664 This is needed when ONLY_INIT is false, and also when AT_LOOP is the
3665 inner-loop nested in LOOP (during outer-loop vectorization). */
3666
3667 /* No update in loop is required. */
3668 if (only_init && (!loop_vinfo || at_loop == loop))
3669- vptr = vect_ptr_init;
3670+ aptr = aggr_ptr_init;
3671 else
3672 {
3673- /* The step of the vector pointer is the Vector Size. */
3674- tree step = TYPE_SIZE_UNIT (vectype);
3675+ /* The step of the aggregate pointer is the type size. */
3676+ tree step = TYPE_SIZE_UNIT (aggr_type);
3677 /* One exception to the above is when the scalar step of the load in
3678 LOOP is zero. In this case the step here is also zero. */
3679 if (*inv_p)
3680@@ -3175,9 +3207,9 @@
3681
3682 standard_iv_increment_position (loop, &incr_gsi, &insert_after);
3683
3684- create_iv (vect_ptr_init,
3685- fold_convert (vect_ptr_type, step),
3686- vect_ptr, loop, &incr_gsi, insert_after,
3687+ create_iv (aggr_ptr_init,
3688+ fold_convert (aggr_ptr_type, step),
3689+ aggr_ptr, loop, &incr_gsi, insert_after,
3690 &indx_before_incr, &indx_after_incr);
3691 incr = gsi_stmt (incr_gsi);
3692 set_vinfo_for_stmt (incr, new_stmt_vec_info (incr, loop_vinfo, NULL));
3693@@ -3191,14 +3223,14 @@
3694 if (ptr_incr)
3695 *ptr_incr = incr;
3696
3697- vptr = indx_before_incr;
3698+ aptr = indx_before_incr;
3699 }
3700
3701 if (!nested_in_vect_loop || only_init)
3702- return vptr;
3703-
3704-
3705- /* (4) Handle the updating of the vector-pointer inside the inner-loop
3706+ return aptr;
3707+
3708+
3709+ /* (4) Handle the updating of the aggregate-pointer inside the inner-loop
3710 nested in LOOP, if exists. */
3711
3712 gcc_assert (nested_in_vect_loop);
3713@@ -3206,7 +3238,7 @@
3714 {
3715 standard_iv_increment_position (containing_loop, &incr_gsi,
3716 &insert_after);
3717- create_iv (vptr, fold_convert (vect_ptr_type, DR_STEP (dr)), vect_ptr,
3718+ create_iv (aptr, fold_convert (aggr_ptr_type, DR_STEP (dr)), aggr_ptr,
3719 containing_loop, &incr_gsi, insert_after, &indx_before_incr,
3720 &indx_after_incr);
3721 incr = gsi_stmt (incr_gsi);
3722@@ -3343,13 +3375,22 @@
3723 and FALSE otherwise. */
3724
3725 bool
3726-vect_strided_store_supported (tree vectype)
3727+vect_strided_store_supported (tree vectype, unsigned HOST_WIDE_INT count)
3728 {
3729 optab interleave_high_optab, interleave_low_optab;
3730 enum machine_mode mode;
3731
3732 mode = TYPE_MODE (vectype);
3733
3734+ /* vect_permute_store_chain requires the group size to be a power of two. */
3735+ if (exact_log2 (count) == -1)
3736+ {
3737+ if (vect_print_dump_info (REPORT_DETAILS))
3738+ fprintf (vect_dump, "the size of the group of strided accesses"
3739+ " is not a power of 2");
3740+ return false;
3741+ }
3742+
3743 /* Check that the operation is supported. */
3744 interleave_high_optab = optab_for_tree_code (VEC_INTERLEAVE_HIGH_EXPR,
3745 vectype, optab_default);
3746@@ -3374,6 +3415,18 @@
3747 }
3748
3749
3750+/* Return TRUE if vec_store_lanes is available for COUNT vectors of
3751+ type VECTYPE. */
3752+
3753+bool
3754+vect_store_lanes_supported (tree vectype, unsigned HOST_WIDE_INT count)
3755+{
3756+ return vect_lanes_optab_supported_p ("vec_store_lanes",
3757+ vec_store_lanes_optab,
3758+ vectype, count);
3759+}
3760+
3761+
3762 /* Function vect_permute_store_chain.
3763
3764 Given a chain of interleaved stores in DR_CHAIN of LENGTH that must be
3765@@ -3435,7 +3488,7 @@
3766 I3: 4 12 20 28 5 13 21 30
3767 I4: 6 14 22 30 7 15 23 31. */
3768
3769-bool
3770+void
3771 vect_permute_store_chain (VEC(tree,heap) *dr_chain,
3772 unsigned int length,
3773 gimple stmt,
3774@@ -3449,9 +3502,7 @@
3775 unsigned int j;
3776 enum tree_code high_code, low_code;
3777
3778- /* Check that the operation is supported. */
3779- if (!vect_strided_store_supported (vectype))
3780- return false;
3781+ gcc_assert (vect_strided_store_supported (vectype, length));
3782
3783 *result_chain = VEC_copy (tree, heap, dr_chain);
3784
3785@@ -3504,7 +3555,6 @@
3786 }
3787 dr_chain = VEC_copy (tree, heap, *result_chain);
3788 }
3789- return true;
3790 }
3791
3792 /* Function vect_setup_realignment
3793@@ -3674,8 +3724,9 @@
3794
3795 gcc_assert (!compute_in_loop);
3796 vec_dest = vect_create_destination_var (scalar_dest, vectype);
3797- ptr = vect_create_data_ref_ptr (stmt, loop_for_initial_load, NULL_TREE,
3798- &init_addr, &inc, true, &inv_p);
3799+ ptr = vect_create_data_ref_ptr (stmt, vectype, loop_for_initial_load,
3800+ NULL_TREE, &init_addr, &inc,
3801+ true, &inv_p);
3802 new_stmt = gimple_build_assign_with_ops
3803 (BIT_AND_EXPR, NULL_TREE, ptr,
3804 build_int_cst (TREE_TYPE (ptr),
3805@@ -3780,13 +3831,22 @@
3806 and FALSE otherwise. */
3807
3808 bool
3809-vect_strided_load_supported (tree vectype)
3810+vect_strided_load_supported (tree vectype, unsigned HOST_WIDE_INT count)
3811 {
3812 optab perm_even_optab, perm_odd_optab;
3813 enum machine_mode mode;
3814
3815 mode = TYPE_MODE (vectype);
3816
3817+ /* vect_permute_load_chain requires the group size to be a power of two. */
3818+ if (exact_log2 (count) == -1)
3819+ {
3820+ if (vect_print_dump_info (REPORT_DETAILS))
3821+ fprintf (vect_dump, "the size of the group of strided accesses"
3822+ " is not a power of 2");
3823+ return false;
3824+ }
3825+
3826 perm_even_optab = optab_for_tree_code (VEC_EXTRACT_EVEN_EXPR, vectype,
3827 optab_default);
3828 if (!perm_even_optab)
3829@@ -3821,6 +3881,16 @@
3830 return true;
3831 }
3832
3833+/* Return TRUE if vec_load_lanes is available for COUNT vectors of
3834+ type VECTYPE. */
3835+
3836+bool
3837+vect_load_lanes_supported (tree vectype, unsigned HOST_WIDE_INT count)
3838+{
3839+ return vect_lanes_optab_supported_p ("vec_load_lanes",
3840+ vec_load_lanes_optab,
3841+ vectype, count);
3842+}
3843
3844 /* Function vect_permute_load_chain.
3845
3846@@ -3898,7 +3968,7 @@
3847 3rd vec (E2): 2 6 10 14 18 22 26 30
3848 4th vec (E4): 3 7 11 15 19 23 27 31. */
3849
3850-bool
3851+static void
3852 vect_permute_load_chain (VEC(tree,heap) *dr_chain,
3853 unsigned int length,
3854 gimple stmt,
3855@@ -3911,9 +3981,7 @@
3856 int i;
3857 unsigned int j;
3858
3859- /* Check that the operation is supported. */
3860- if (!vect_strided_load_supported (vectype))
3861- return false;
3862+ gcc_assert (vect_strided_load_supported (vectype, length));
3863
3864 *result_chain = VEC_copy (tree, heap, dr_chain);
3865 for (i = 0; i < exact_log2 (length); i++)
3866@@ -3956,7 +4024,6 @@
3867 }
3868 dr_chain = VEC_copy (tree, heap, *result_chain);
3869 }
3870- return true;
3871 }
3872
3873
3874@@ -3967,24 +4034,32 @@
3875 the scalar statements.
3876 */
3877
3878-bool
3879+void
3880 vect_transform_strided_load (gimple stmt, VEC(tree,heap) *dr_chain, int size,
3881 gimple_stmt_iterator *gsi)
3882 {
3883- stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
3884- gimple first_stmt = DR_GROUP_FIRST_DR (stmt_info);
3885- gimple next_stmt, new_stmt;
3886 VEC(tree,heap) *result_chain = NULL;
3887- unsigned int i, gap_count;
3888- tree tmp_data_ref;
3889
3890 /* DR_CHAIN contains input data-refs that are a part of the interleaving.
3891 RESULT_CHAIN is the output of vect_permute_load_chain, it contains permuted
3892 vectors, that are ready for vector computation. */
3893 result_chain = VEC_alloc (tree, heap, size);
3894- /* Permute. */
3895- if (!vect_permute_load_chain (dr_chain, size, stmt, gsi, &result_chain))
3896- return false;
3897+ vect_permute_load_chain (dr_chain, size, stmt, gsi, &result_chain);
3898+ vect_record_strided_load_vectors (stmt, result_chain);
3899+ VEC_free (tree, heap, result_chain);
3900+}
3901+
3902+/* RESULT_CHAIN contains the output of a group of strided loads that were
3903+ generated as part of the vectorization of STMT. Assign the statement
3904+ for each vector to the associated scalar statement. */
3905+
3906+void
3907+vect_record_strided_load_vectors (gimple stmt, VEC(tree,heap) *result_chain)
3908+{
3909+ gimple first_stmt = DR_GROUP_FIRST_DR (vinfo_for_stmt (stmt));
3910+ gimple next_stmt, new_stmt;
3911+ unsigned int i, gap_count;
3912+ tree tmp_data_ref;
3913
3914 /* Put a permuted data-ref in the VECTORIZED_STMT field.
3915 Since we scan the chain starting from it's first node, their order
3916@@ -4046,9 +4121,6 @@
3917 break;
3918 }
3919 }
3920-
3921- VEC_free (tree, heap, result_chain);
3922- return true;
3923 }
3924
3925 /* Function vect_force_dr_alignment_p.
3926
3927=== modified file 'gcc/tree-vect-slp.c'
3928--- old/gcc/tree-vect-slp.c 2010-12-23 16:25:52 +0000
3929+++ new/gcc/tree-vect-slp.c 2011-05-05 15:43:06 +0000
3930@@ -215,7 +215,8 @@
3931 vect_model_simple_cost (stmt_info, ncopies_for_cost, dt, slp_node);
3932 else
3933 /* Store. */
3934- vect_model_store_cost (stmt_info, ncopies_for_cost, dt[0], slp_node);
3935+ vect_model_store_cost (stmt_info, ncopies_for_cost, false,
3936+ dt[0], slp_node);
3937 }
3938
3939 else
3940@@ -579,7 +580,7 @@
3941
3942 /* Analyze costs (for the first stmt in the group). */
3943 vect_model_load_cost (vinfo_for_stmt (stmt),
3944- ncopies_for_cost, *node);
3945+ ncopies_for_cost, false, *node);
3946 }
3947
3948 /* Store the place of this load in the interleaving chain. In
3949
3950=== modified file 'gcc/tree-vect-stmts.c'
3951--- old/gcc/tree-vect-stmts.c 2011-04-18 07:38:11 +0000
3952+++ new/gcc/tree-vect-stmts.c 2011-06-02 12:12:00 +0000
3953@@ -42,6 +42,82 @@
3954 #include "langhooks.h"
3955
3956
3957+/* Return a variable of type ELEM_TYPE[NELEMS]. */
3958+
3959+static tree
3960+create_vector_array (tree elem_type, unsigned HOST_WIDE_INT nelems)
3961+{
3962+ return create_tmp_var (build_array_type_nelts (elem_type, nelems),
3963+ "vect_array");
3964+}
3965+
3966+/* ARRAY is an array of vectors created by create_vector_array.
3967+ Return an SSA_NAME for the vector in index N. The reference
3968+ is part of the vectorization of STMT and the vector is associated
3969+ with scalar destination SCALAR_DEST. */
3970+
3971+static tree
3972+read_vector_array (gimple stmt, gimple_stmt_iterator *gsi, tree scalar_dest,
3973+ tree array, unsigned HOST_WIDE_INT n)
3974+{
3975+ tree vect_type, vect, vect_name, array_ref;
3976+ gimple new_stmt;
3977+
3978+ gcc_assert (TREE_CODE (TREE_TYPE (array)) == ARRAY_TYPE);
3979+ vect_type = TREE_TYPE (TREE_TYPE (array));
3980+ vect = vect_create_destination_var (scalar_dest, vect_type);
3981+ array_ref = build4 (ARRAY_REF, vect_type, array,
3982+ build_int_cst (size_type_node, n),
3983+ NULL_TREE, NULL_TREE);
3984+
3985+ new_stmt = gimple_build_assign (vect, array_ref);
3986+ vect_name = make_ssa_name (vect, new_stmt);
3987+ gimple_assign_set_lhs (new_stmt, vect_name);
3988+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
3989+ mark_symbols_for_renaming (new_stmt);
3990+
3991+ return vect_name;
3992+}
3993+
3994+/* ARRAY is an array of vectors created by create_vector_array.
3995+ Emit code to store SSA_NAME VECT in index N of the array.
3996+ The store is part of the vectorization of STMT. */
3997+
3998+static void
3999+write_vector_array (gimple stmt, gimple_stmt_iterator *gsi, tree vect,
4000+ tree array, unsigned HOST_WIDE_INT n)
4001+{
4002+ tree array_ref;
4003+ gimple new_stmt;
4004+
4005+ array_ref = build4 (ARRAY_REF, TREE_TYPE (vect), array,
4006+ build_int_cst (size_type_node, n),
4007+ NULL_TREE, NULL_TREE);
4008+
4009+ new_stmt = gimple_build_assign (array_ref, vect);
4010+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4011+ mark_symbols_for_renaming (new_stmt);
4012+}
4013+
4014+/* PTR is a pointer to an array of type TYPE. Return a representation
4015+ of *PTR. The memory reference replaces those in FIRST_DR
4016+ (and its group). */
4017+
4018+static tree
4019+create_array_ref (tree type, tree ptr, struct data_reference *first_dr)
4020+{
4021+ struct ptr_info_def *pi;
4022+ tree mem_ref, alias_ptr_type;
4023+
4024+ alias_ptr_type = reference_alias_ptr_type (DR_REF (first_dr));
4025+ mem_ref = build2 (MEM_REF, type, ptr, build_int_cst (alias_ptr_type, 0));
4026+ /* Arrays have the same alignment as their type. */
4027+ pi = get_ptr_info (ptr);
4028+ pi->align = TYPE_ALIGN_UNIT (type);
4029+ pi->misalign = 0;
4030+ return mem_ref;
4031+}
4032+
4033 /* Utility functions used by vect_mark_stmts_to_be_vectorized. */
4034
4035 /* Function vect_mark_relevant.
4036@@ -648,7 +724,8 @@
4037
4038 void
4039 vect_model_store_cost (stmt_vec_info stmt_info, int ncopies,
4040- enum vect_def_type dt, slp_tree slp_node)
4041+ bool store_lanes_p, enum vect_def_type dt,
4042+ slp_tree slp_node)
4043 {
4044 int group_size;
4045 unsigned int inside_cost = 0, outside_cost = 0;
4046@@ -685,9 +762,11 @@
4047 first_dr = STMT_VINFO_DATA_REF (stmt_info);
4048 }
4049
4050- /* Is this an access in a group of stores, which provide strided access?
4051- If so, add in the cost of the permutes. */
4052- if (group_size > 1)
4053+ /* We assume that the cost of a single store-lanes instruction is
4054+ equivalent to the cost of GROUP_SIZE separate stores. If a strided
4055+ access is instead being provided by a permute-and-store operation,
4056+ include the cost of the permutes. */
4057+ if (!store_lanes_p && group_size > 1)
4058 {
4059 /* Uses a high and low interleave operation for each needed permute. */
4060 inside_cost = ncopies * exact_log2(group_size) * group_size
4061@@ -763,8 +842,8 @@
4062 access scheme chosen. */
4063
4064 void
4065-vect_model_load_cost (stmt_vec_info stmt_info, int ncopies, slp_tree slp_node)
4066-
4067+vect_model_load_cost (stmt_vec_info stmt_info, int ncopies, bool load_lanes_p,
4068+ slp_tree slp_node)
4069 {
4070 int group_size;
4071 gimple first_stmt;
4072@@ -789,9 +868,11 @@
4073 first_dr = dr;
4074 }
4075
4076- /* Is this an access in a group of loads providing strided access?
4077- If so, add in the cost of the permutes. */
4078- if (group_size > 1)
4079+ /* We assume that the cost of a single load-lanes instruction is
4080+ equivalent to the cost of GROUP_SIZE separate loads. If a strided
4081+ access is instead being provided by a load-and-permute operation,
4082+ include the cost of the permutes. */
4083+ if (!load_lanes_p && group_size > 1)
4084 {
4085 /* Uses an even and odd extract operations for each needed permute. */
4086 inside_cost = ncopies * exact_log2(group_size) * group_size
4087@@ -3329,6 +3410,7 @@
4088 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
4089 struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info), *first_dr = NULL;
4090 tree vectype = STMT_VINFO_VECTYPE (stmt_info);
4091+ tree elem_type;
4092 loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info);
4093 struct loop *loop = NULL;
4094 enum machine_mode vec_mode;
4095@@ -3344,6 +3426,7 @@
4096 int j;
4097 gimple next_stmt, first_stmt = NULL;
4098 bool strided_store = false;
4099+ bool store_lanes_p = false;
4100 unsigned int group_size, i;
4101 VEC(tree,heap) *dr_chain = NULL, *oprnds = NULL, *result_chain = NULL;
4102 bool inv_p;
4103@@ -3351,6 +3434,7 @@
4104 bool slp = (slp_node != NULL);
4105 unsigned int vec_num;
4106 bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
4107+ tree aggr_type;
4108
4109 if (loop_vinfo)
4110 loop = LOOP_VINFO_LOOP (loop_vinfo);
4111@@ -3404,7 +3488,8 @@
4112
4113 /* The scalar rhs type needs to be trivially convertible to the vector
4114 component type. This should always be the case. */
4115- if (!useless_type_conversion_p (TREE_TYPE (vectype), TREE_TYPE (op)))
4116+ elem_type = TREE_TYPE (vectype);
4117+ if (!useless_type_conversion_p (elem_type, TREE_TYPE (op)))
4118 {
4119 if (vect_print_dump_info (REPORT_DETAILS))
4120 fprintf (vect_dump, "??? operands of different types");
4121@@ -3431,9 +3516,14 @@
4122 {
4123 strided_store = true;
4124 first_stmt = DR_GROUP_FIRST_DR (stmt_info);
4125- if (!vect_strided_store_supported (vectype)
4126- && !PURE_SLP_STMT (stmt_info) && !slp)
4127- return false;
4128+ if (!slp && !PURE_SLP_STMT (stmt_info))
4129+ {
4130+ group_size = DR_GROUP_SIZE (vinfo_for_stmt (first_stmt));
4131+ if (vect_store_lanes_supported (vectype, group_size))
4132+ store_lanes_p = true;
4133+ else if (!vect_strided_store_supported (vectype, group_size))
4134+ return false;
4135+ }
4136
4137 if (first_stmt == stmt)
4138 {
4139@@ -3459,7 +3549,7 @@
4140 if (!vec_stmt) /* transformation not required. */
4141 {
4142 STMT_VINFO_TYPE (stmt_info) = store_vec_info_type;
4143- vect_model_store_cost (stmt_info, ncopies, dt, NULL);
4144+ vect_model_store_cost (stmt_info, ncopies, store_lanes_p, dt, NULL);
4145 return true;
4146 }
4147
4148@@ -3514,6 +3604,16 @@
4149
4150 alignment_support_scheme = vect_supportable_dr_alignment (first_dr, false);
4151 gcc_assert (alignment_support_scheme);
4152+ /* Targets with store-lane instructions must not require explicit
4153+ realignment. */
4154+ gcc_assert (!store_lanes_p
4155+ || alignment_support_scheme == dr_aligned
4156+ || alignment_support_scheme == dr_unaligned_supported);
4157+
4158+ if (store_lanes_p)
4159+ aggr_type = build_array_type_nelts (elem_type, vec_num * nunits);
4160+ else
4161+ aggr_type = vectype;
4162
4163 /* In case the vectorization factor (VF) is bigger than the number
4164 of elements that we can fit in a vectype (nunits), we have to generate
4165@@ -3602,9 +3702,9 @@
4166 /* We should have catched mismatched types earlier. */
4167 gcc_assert (useless_type_conversion_p (vectype,
4168 TREE_TYPE (vec_oprnd)));
4169- dataref_ptr = vect_create_data_ref_ptr (first_stmt, NULL, NULL_TREE,
4170- &dummy, &ptr_incr, false,
4171- &inv_p);
4172+ dataref_ptr = vect_create_data_ref_ptr (first_stmt, aggr_type, NULL,
4173+ NULL_TREE, &dummy,
4174+ &ptr_incr, false, &inv_p);
4175 gcc_assert (bb_vinfo || !inv_p);
4176 }
4177 else
4178@@ -3625,76 +3725,101 @@
4179 VEC_replace(tree, dr_chain, i, vec_oprnd);
4180 VEC_replace(tree, oprnds, i, vec_oprnd);
4181 }
4182- dataref_ptr =
4183- bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, NULL_TREE);
4184- }
4185-
4186- if (strided_store)
4187- {
4188- result_chain = VEC_alloc (tree, heap, group_size);
4189- /* Permute. */
4190- if (!vect_permute_store_chain (dr_chain, group_size, stmt, gsi,
4191- &result_chain))
4192- return false;
4193- }
4194-
4195- next_stmt = first_stmt;
4196- for (i = 0; i < vec_num; i++)
4197- {
4198- struct ptr_info_def *pi;
4199-
4200- if (i > 0)
4201- /* Bump the vector pointer. */
4202- dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
4203- NULL_TREE);
4204-
4205- if (slp)
4206- vec_oprnd = VEC_index (tree, vec_oprnds, i);
4207- else if (strided_store)
4208- /* For strided stores vectorized defs are interleaved in
4209- vect_permute_store_chain(). */
4210- vec_oprnd = VEC_index (tree, result_chain, i);
4211-
4212- data_ref = build2 (MEM_REF, TREE_TYPE (vec_oprnd), dataref_ptr,
4213- build_int_cst (reference_alias_ptr_type
4214- (DR_REF (first_dr)), 0));
4215- pi = get_ptr_info (dataref_ptr);
4216- pi->align = TYPE_ALIGN_UNIT (vectype);
4217- if (aligned_access_p (first_dr))
4218- pi->misalign = 0;
4219- else if (DR_MISALIGNMENT (first_dr) == -1)
4220- {
4221- TREE_TYPE (data_ref)
4222- = build_aligned_type (TREE_TYPE (data_ref),
4223- TYPE_ALIGN (TREE_TYPE (vectype)));
4224- pi->align = TYPE_ALIGN_UNIT (TREE_TYPE (vectype));
4225- pi->misalign = 0;
4226- }
4227- else
4228- {
4229- TREE_TYPE (data_ref)
4230- = build_aligned_type (TREE_TYPE (data_ref),
4231- TYPE_ALIGN (TREE_TYPE (vectype)));
4232- pi->misalign = DR_MISALIGNMENT (first_dr);
4233- }
4234-
4235- /* Arguments are ready. Create the new vector stmt. */
4236- new_stmt = gimple_build_assign (data_ref, vec_oprnd);
4237+ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
4238+ TYPE_SIZE_UNIT (aggr_type));
4239+ }
4240+
4241+ if (store_lanes_p)
4242+ {
4243+ tree vec_array;
4244+
4245+ /* Combine all the vectors into an array. */
4246+ vec_array = create_vector_array (vectype, vec_num);
4247+ for (i = 0; i < vec_num; i++)
4248+ {
4249+ vec_oprnd = VEC_index (tree, dr_chain, i);
4250+ write_vector_array (stmt, gsi, vec_oprnd, vec_array, i);
4251+ }
4252+
4253+ /* Emit:
4254+ MEM_REF[...all elements...] = STORE_LANES (VEC_ARRAY). */
4255+ data_ref = create_array_ref (aggr_type, dataref_ptr, first_dr);
4256+ new_stmt = gimple_build_call_internal (IFN_STORE_LANES, 1, vec_array);
4257+ gimple_call_set_lhs (new_stmt, data_ref);
4258 vect_finish_stmt_generation (stmt, new_stmt, gsi);
4259 mark_symbols_for_renaming (new_stmt);
4260-
4261- if (slp)
4262- continue;
4263-
4264- if (j == 0)
4265- STMT_VINFO_VEC_STMT (stmt_info) = *vec_stmt = new_stmt;
4266+ }
4267+ else
4268+ {
4269+ new_stmt = NULL;
4270+ if (strided_store)
4271+ {
4272+ result_chain = VEC_alloc (tree, heap, group_size);
4273+ /* Permute. */
4274+ vect_permute_store_chain (dr_chain, group_size, stmt, gsi,
4275+ &result_chain);
4276+ }
4277+
4278+ next_stmt = first_stmt;
4279+ for (i = 0; i < vec_num; i++)
4280+ {
4281+ struct ptr_info_def *pi;
4282+
4283+ if (i > 0)
4284+ /* Bump the vector pointer. */
4285+ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi,
4286+ stmt, NULL_TREE);
4287+
4288+ if (slp)
4289+ vec_oprnd = VEC_index (tree, vec_oprnds, i);
4290+ else if (strided_store)
4291+ /* For strided stores vectorized defs are interleaved in
4292+ vect_permute_store_chain(). */
4293+ vec_oprnd = VEC_index (tree, result_chain, i);
4294+
4295+ data_ref = build2 (MEM_REF, TREE_TYPE (vec_oprnd), dataref_ptr,
4296+ build_int_cst (reference_alias_ptr_type
4297+ (DR_REF (first_dr)), 0));
4298+ pi = get_ptr_info (dataref_ptr);
4299+ pi->align = TYPE_ALIGN_UNIT (vectype);
4300+ if (aligned_access_p (first_dr))
4301+ pi->misalign = 0;
4302+ else if (DR_MISALIGNMENT (first_dr) == -1)
4303+ {
4304+ TREE_TYPE (data_ref)
4305+ = build_aligned_type (TREE_TYPE (data_ref),
4306+ TYPE_ALIGN (elem_type));
4307+ pi->align = TYPE_ALIGN_UNIT (elem_type);
4308+ pi->misalign = 0;
4309+ }
4310+ else
4311+ {
4312+ TREE_TYPE (data_ref)
4313+ = build_aligned_type (TREE_TYPE (data_ref),
4314+ TYPE_ALIGN (elem_type));
4315+ pi->misalign = DR_MISALIGNMENT (first_dr);
4316+ }
4317+
4318+ /* Arguments are ready. Create the new vector stmt. */
4319+ new_stmt = gimple_build_assign (data_ref, vec_oprnd);
4320+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4321+ mark_symbols_for_renaming (new_stmt);
4322+
4323+ if (slp)
4324+ continue;
4325+
4326+ next_stmt = DR_GROUP_NEXT_DR (vinfo_for_stmt (next_stmt));
4327+ if (!next_stmt)
4328+ break;
4329+ }
4330+ }
4331+ if (!slp)
4332+ {
4333+ if (j == 0)
4334+ STMT_VINFO_VEC_STMT (stmt_info) = *vec_stmt = new_stmt;
4335 else
4336 STMT_VINFO_RELATED_STMT (prev_stmt_info) = new_stmt;
4337-
4338 prev_stmt_info = vinfo_for_stmt (new_stmt);
4339- next_stmt = DR_GROUP_NEXT_DR (vinfo_for_stmt (next_stmt));
4340- if (!next_stmt)
4341- break;
4342 }
4343 }
4344
4345@@ -3805,6 +3930,7 @@
4346 bool nested_in_vect_loop = false;
4347 struct data_reference *dr = STMT_VINFO_DATA_REF (stmt_info), *first_dr;
4348 tree vectype = STMT_VINFO_VECTYPE (stmt_info);
4349+ tree elem_type;
4350 tree new_temp;
4351 enum machine_mode mode;
4352 gimple new_stmt = NULL;
4353@@ -3821,6 +3947,7 @@
4354 gimple phi = NULL;
4355 VEC(tree,heap) *dr_chain = NULL;
4356 bool strided_load = false;
4357+ bool load_lanes_p = false;
4358 gimple first_stmt;
4359 tree scalar_type;
4360 bool inv_p;
4361@@ -3833,6 +3960,7 @@
4362 enum tree_code code;
4363 bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
4364 int vf;
4365+ tree aggr_type;
4366
4367 if (loop_vinfo)
4368 {
4369@@ -3909,7 +4037,8 @@
4370
4371 /* The vector component type needs to be trivially convertible to the
4372 scalar lhs. This should always be the case. */
4373- if (!useless_type_conversion_p (TREE_TYPE (scalar_dest), TREE_TYPE (vectype)))
4374+ elem_type = TREE_TYPE (vectype);
4375+ if (!useless_type_conversion_p (TREE_TYPE (scalar_dest), elem_type))
4376 {
4377 if (vect_print_dump_info (REPORT_DETAILS))
4378 fprintf (vect_dump, "??? operands of different types");
4379@@ -3923,10 +4052,15 @@
4380 /* FORNOW */
4381 gcc_assert (! nested_in_vect_loop);
4382
4383- /* Check if interleaving is supported. */
4384- if (!vect_strided_load_supported (vectype)
4385- && !PURE_SLP_STMT (stmt_info) && !slp)
4386- return false;
4387+ first_stmt = DR_GROUP_FIRST_DR (stmt_info);
4388+ if (!slp && !PURE_SLP_STMT (stmt_info))
4389+ {
4390+ group_size = DR_GROUP_SIZE (vinfo_for_stmt (first_stmt));
4391+ if (vect_load_lanes_supported (vectype, group_size))
4392+ load_lanes_p = true;
4393+ else if (!vect_strided_load_supported (vectype, group_size))
4394+ return false;
4395+ }
4396 }
4397
4398 if (negative)
4399@@ -3951,12 +4085,12 @@
4400 if (!vec_stmt) /* transformation not required. */
4401 {
4402 STMT_VINFO_TYPE (stmt_info) = load_vec_info_type;
4403- vect_model_load_cost (stmt_info, ncopies, NULL);
4404+ vect_model_load_cost (stmt_info, ncopies, load_lanes_p, NULL);
4405 return true;
4406 }
4407
4408 if (vect_print_dump_info (REPORT_DETAILS))
4409- fprintf (vect_dump, "transform load.");
4410+ fprintf (vect_dump, "transform load. ncopies = %d", ncopies);
4411
4412 /** Transform. **/
4413
4414@@ -3982,8 +4116,6 @@
4415 }
4416 else
4417 vec_num = group_size;
4418-
4419- dr_chain = VEC_alloc (tree, heap, vec_num);
4420 }
4421 else
4422 {
4423@@ -3994,6 +4126,11 @@
4424
4425 alignment_support_scheme = vect_supportable_dr_alignment (first_dr, false);
4426 gcc_assert (alignment_support_scheme);
4427+ /* Targets with load-lane instructions must not require explicit
4428+ realignment. */
4429+ gcc_assert (!load_lanes_p
4430+ || alignment_support_scheme == dr_aligned
4431+ || alignment_support_scheme == dr_unaligned_supported);
4432
4433 /* In case the vectorization factor (VF) is bigger than the number
4434 of elements that we can fit in a vectype (nunits), we have to generate
4435@@ -4125,208 +4262,252 @@
4436 if (negative)
4437 offset = size_int (-TYPE_VECTOR_SUBPARTS (vectype) + 1);
4438
4439+ if (load_lanes_p)
4440+ aggr_type = build_array_type_nelts (elem_type, vec_num * nunits);
4441+ else
4442+ aggr_type = vectype;
4443+
4444 prev_stmt_info = NULL;
4445 for (j = 0; j < ncopies; j++)
4446 {
4447 /* 1. Create the vector pointer update chain. */
4448 if (j == 0)
4449- dataref_ptr = vect_create_data_ref_ptr (first_stmt,
4450+ dataref_ptr = vect_create_data_ref_ptr (first_stmt, aggr_type,
4451 at_loop, offset,
4452 &dummy, &ptr_incr, false,
4453 &inv_p);
4454 else
4455- dataref_ptr =
4456- bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt, NULL_TREE);
4457-
4458- for (i = 0; i < vec_num; i++)
4459+ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
4460+ TYPE_SIZE_UNIT (aggr_type));
4461+
4462+ if (strided_load || slp_perm)
4463+ dr_chain = VEC_alloc (tree, heap, vec_num);
4464+
4465+ if (load_lanes_p)
4466 {
4467- if (i > 0)
4468- dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi, stmt,
4469- NULL_TREE);
4470-
4471- /* 2. Create the vector-load in the loop. */
4472- switch (alignment_support_scheme)
4473- {
4474- case dr_aligned:
4475- case dr_unaligned_supported:
4476- {
4477- struct ptr_info_def *pi;
4478- data_ref
4479- = build2 (MEM_REF, vectype, dataref_ptr,
4480- build_int_cst (reference_alias_ptr_type
4481- (DR_REF (first_dr)), 0));
4482- pi = get_ptr_info (dataref_ptr);
4483- pi->align = TYPE_ALIGN_UNIT (vectype);
4484- if (alignment_support_scheme == dr_aligned)
4485- {
4486- gcc_assert (aligned_access_p (first_dr));
4487- pi->misalign = 0;
4488- }
4489- else if (DR_MISALIGNMENT (first_dr) == -1)
4490- {
4491- TREE_TYPE (data_ref)
4492- = build_aligned_type (TREE_TYPE (data_ref),
4493- TYPE_ALIGN (TREE_TYPE (vectype)));
4494- pi->align = TYPE_ALIGN_UNIT (TREE_TYPE (vectype));
4495- pi->misalign = 0;
4496- }
4497- else
4498- {
4499- TREE_TYPE (data_ref)
4500- = build_aligned_type (TREE_TYPE (data_ref),
4501- TYPE_ALIGN (TREE_TYPE (vectype)));
4502- pi->misalign = DR_MISALIGNMENT (first_dr);
4503- }
4504- break;
4505- }
4506- case dr_explicit_realign:
4507- {
4508- tree ptr, bump;
4509- tree vs_minus_1 = size_int (TYPE_VECTOR_SUBPARTS (vectype) - 1);
4510-
4511- if (compute_in_loop)
4512- msq = vect_setup_realignment (first_stmt, gsi,
4513- &realignment_token,
4514- dr_explicit_realign,
4515- dataref_ptr, NULL);
4516-
4517- new_stmt = gimple_build_assign_with_ops
4518- (BIT_AND_EXPR, NULL_TREE, dataref_ptr,
4519- build_int_cst
4520- (TREE_TYPE (dataref_ptr),
4521- -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype)));
4522- ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
4523- gimple_assign_set_lhs (new_stmt, ptr);
4524- vect_finish_stmt_generation (stmt, new_stmt, gsi);
4525- data_ref
4526- = build2 (MEM_REF, vectype, ptr,
4527- build_int_cst (reference_alias_ptr_type
4528- (DR_REF (first_dr)), 0));
4529- vec_dest = vect_create_destination_var (scalar_dest, vectype);
4530- new_stmt = gimple_build_assign (vec_dest, data_ref);
4531- new_temp = make_ssa_name (vec_dest, new_stmt);
4532- gimple_assign_set_lhs (new_stmt, new_temp);
4533- gimple_set_vdef (new_stmt, gimple_vdef (stmt));
4534- gimple_set_vuse (new_stmt, gimple_vuse (stmt));
4535- vect_finish_stmt_generation (stmt, new_stmt, gsi);
4536- msq = new_temp;
4537-
4538- bump = size_binop (MULT_EXPR, vs_minus_1,
4539- TYPE_SIZE_UNIT (scalar_type));
4540- ptr = bump_vector_ptr (dataref_ptr, NULL, gsi, stmt, bump);
4541- new_stmt = gimple_build_assign_with_ops
4542- (BIT_AND_EXPR, NULL_TREE, ptr,
4543- build_int_cst
4544- (TREE_TYPE (ptr),
4545- -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype)));
4546- ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
4547- gimple_assign_set_lhs (new_stmt, ptr);
4548- vect_finish_stmt_generation (stmt, new_stmt, gsi);
4549- data_ref
4550- = build2 (MEM_REF, vectype, ptr,
4551- build_int_cst (reference_alias_ptr_type
4552- (DR_REF (first_dr)), 0));
4553- break;
4554- }
4555- case dr_explicit_realign_optimized:
4556- new_stmt = gimple_build_assign_with_ops
4557- (BIT_AND_EXPR, NULL_TREE, dataref_ptr,
4558- build_int_cst
4559- (TREE_TYPE (dataref_ptr),
4560- -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype)));
4561- new_temp = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
4562- gimple_assign_set_lhs (new_stmt, new_temp);
4563- vect_finish_stmt_generation (stmt, new_stmt, gsi);
4564- data_ref
4565- = build2 (MEM_REF, vectype, new_temp,
4566- build_int_cst (reference_alias_ptr_type
4567- (DR_REF (first_dr)), 0));
4568- break;
4569- default:
4570- gcc_unreachable ();
4571- }
4572- vec_dest = vect_create_destination_var (scalar_dest, vectype);
4573- new_stmt = gimple_build_assign (vec_dest, data_ref);
4574- new_temp = make_ssa_name (vec_dest, new_stmt);
4575- gimple_assign_set_lhs (new_stmt, new_temp);
4576+ tree vec_array;
4577+
4578+ vec_array = create_vector_array (vectype, vec_num);
4579+
4580+ /* Emit:
4581+ VEC_ARRAY = LOAD_LANES (MEM_REF[...all elements...]). */
4582+ data_ref = create_array_ref (aggr_type, dataref_ptr, first_dr);
4583+ new_stmt = gimple_build_call_internal (IFN_LOAD_LANES, 1, data_ref);
4584+ gimple_call_set_lhs (new_stmt, vec_array);
4585 vect_finish_stmt_generation (stmt, new_stmt, gsi);
4586 mark_symbols_for_renaming (new_stmt);
4587
4588- /* 3. Handle explicit realignment if necessary/supported. Create in
4589- loop: vec_dest = realign_load (msq, lsq, realignment_token) */
4590- if (alignment_support_scheme == dr_explicit_realign_optimized
4591- || alignment_support_scheme == dr_explicit_realign)
4592- {
4593- tree tmp;
4594-
4595- lsq = gimple_assign_lhs (new_stmt);
4596- if (!realignment_token)
4597- realignment_token = dataref_ptr;
4598+ /* Extract each vector into an SSA_NAME. */
4599+ for (i = 0; i < vec_num; i++)
4600+ {
4601+ new_temp = read_vector_array (stmt, gsi, scalar_dest,
4602+ vec_array, i);
4603+ VEC_quick_push (tree, dr_chain, new_temp);
4604+ }
4605+
4606+ /* Record the mapping between SSA_NAMEs and statements. */
4607+ vect_record_strided_load_vectors (stmt, dr_chain);
4608+ }
4609+ else
4610+ {
4611+ for (i = 0; i < vec_num; i++)
4612+ {
4613+ if (i > 0)
4614+ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi,
4615+ stmt, NULL_TREE);
4616+
4617+ /* 2. Create the vector-load in the loop. */
4618+ switch (alignment_support_scheme)
4619+ {
4620+ case dr_aligned:
4621+ case dr_unaligned_supported:
4622+ {
4623+ struct ptr_info_def *pi;
4624+ data_ref
4625+ = build2 (MEM_REF, vectype, dataref_ptr,
4626+ build_int_cst (reference_alias_ptr_type
4627+ (DR_REF (first_dr)), 0));
4628+ pi = get_ptr_info (dataref_ptr);
4629+ pi->align = TYPE_ALIGN_UNIT (vectype);
4630+ if (alignment_support_scheme == dr_aligned)
4631+ {
4632+ gcc_assert (aligned_access_p (first_dr));
4633+ pi->misalign = 0;
4634+ }
4635+ else if (DR_MISALIGNMENT (first_dr) == -1)
4636+ {
4637+ TREE_TYPE (data_ref)
4638+ = build_aligned_type (TREE_TYPE (data_ref),
4639+ TYPE_ALIGN (elem_type));
4640+ pi->align = TYPE_ALIGN_UNIT (elem_type);
4641+ pi->misalign = 0;
4642+ }
4643+ else
4644+ {
4645+ TREE_TYPE (data_ref)
4646+ = build_aligned_type (TREE_TYPE (data_ref),
4647+ TYPE_ALIGN (elem_type));
4648+ pi->misalign = DR_MISALIGNMENT (first_dr);
4649+ }
4650+ break;
4651+ }
4652+ case dr_explicit_realign:
4653+ {
4654+ tree ptr, bump;
4655+ tree vs_minus_1
4656+ = size_int (TYPE_VECTOR_SUBPARTS (vectype) - 1);
4657+
4658+ if (compute_in_loop)
4659+ msq = vect_setup_realignment (first_stmt, gsi,
4660+ &realignment_token,
4661+ dr_explicit_realign,
4662+ dataref_ptr, NULL);
4663+
4664+ new_stmt = gimple_build_assign_with_ops
4665+ (BIT_AND_EXPR, NULL_TREE, dataref_ptr,
4666+ build_int_cst
4667+ (TREE_TYPE (dataref_ptr),
4668+ -(HOST_WIDE_INT)
4669+ TYPE_ALIGN_UNIT (vectype)));
4670+ ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
4671+ gimple_assign_set_lhs (new_stmt, ptr);
4672+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4673+ data_ref
4674+ = build2 (MEM_REF, vectype, ptr,
4675+ build_int_cst (reference_alias_ptr_type
4676+ (DR_REF (first_dr)), 0));
4677+ vec_dest = vect_create_destination_var (scalar_dest,
4678+ vectype);
4679+ new_stmt = gimple_build_assign (vec_dest, data_ref);
4680+ new_temp = make_ssa_name (vec_dest, new_stmt);
4681+ gimple_assign_set_lhs (new_stmt, new_temp);
4682+ gimple_set_vdef (new_stmt, gimple_vdef (stmt));
4683+ gimple_set_vuse (new_stmt, gimple_vuse (stmt));
4684+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4685+ msq = new_temp;
4686+
4687+ bump = size_binop (MULT_EXPR, vs_minus_1,
4688+ TYPE_SIZE_UNIT (scalar_type));
4689+ ptr = bump_vector_ptr (dataref_ptr, NULL, gsi, stmt, bump);
4690+ new_stmt = gimple_build_assign_with_ops
4691+ (BIT_AND_EXPR, NULL_TREE, ptr,
4692+ build_int_cst
4693+ (TREE_TYPE (ptr),
4694+ -(HOST_WIDE_INT)
4695+ TYPE_ALIGN_UNIT (vectype)));
4696+ ptr = make_ssa_name (SSA_NAME_VAR (dataref_ptr), new_stmt);
4697+ gimple_assign_set_lhs (new_stmt, ptr);
4698+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4699+ data_ref
4700+ = build2 (MEM_REF, vectype, ptr,
4701+ build_int_cst (reference_alias_ptr_type
4702+ (DR_REF (first_dr)), 0));
4703+ break;
4704+ }
4705+ case dr_explicit_realign_optimized:
4706+ new_stmt = gimple_build_assign_with_ops
4707+ (BIT_AND_EXPR, NULL_TREE, dataref_ptr,
4708+ build_int_cst
4709+ (TREE_TYPE (dataref_ptr),
4710+ -(HOST_WIDE_INT)TYPE_ALIGN_UNIT (vectype)));
4711+ new_temp = make_ssa_name (SSA_NAME_VAR (dataref_ptr),
4712+ new_stmt);
4713+ gimple_assign_set_lhs (new_stmt, new_temp);
4714+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4715+ data_ref
4716+ = build2 (MEM_REF, vectype, new_temp,
4717+ build_int_cst (reference_alias_ptr_type
4718+ (DR_REF (first_dr)), 0));
4719+ break;
4720+ default:
4721+ gcc_unreachable ();
4722+ }
4723 vec_dest = vect_create_destination_var (scalar_dest, vectype);
4724- tmp = build3 (REALIGN_LOAD_EXPR, vectype, msq, lsq,
4725- realignment_token);
4726- new_stmt = gimple_build_assign (vec_dest, tmp);
4727+ new_stmt = gimple_build_assign (vec_dest, data_ref);
4728 new_temp = make_ssa_name (vec_dest, new_stmt);
4729 gimple_assign_set_lhs (new_stmt, new_temp);
4730 vect_finish_stmt_generation (stmt, new_stmt, gsi);
4731-
4732- if (alignment_support_scheme == dr_explicit_realign_optimized)
4733- {
4734- gcc_assert (phi);
4735- if (i == vec_num - 1 && j == ncopies - 1)
4736- add_phi_arg (phi, lsq, loop_latch_edge (containing_loop),
4737- UNKNOWN_LOCATION);
4738- msq = lsq;
4739- }
4740- }
4741-
4742- /* 4. Handle invariant-load. */
4743- if (inv_p && !bb_vinfo)
4744- {
4745- gcc_assert (!strided_load);
4746- gcc_assert (nested_in_vect_loop_p (loop, stmt));
4747- if (j == 0)
4748- {
4749- int k;
4750- tree t = NULL_TREE;
4751- tree vec_inv, bitpos, bitsize = TYPE_SIZE (scalar_type);
4752-
4753- /* CHECKME: bitpos depends on endianess? */
4754- bitpos = bitsize_zero_node;
4755- vec_inv = build3 (BIT_FIELD_REF, scalar_type, new_temp,
4756- bitsize, bitpos);
4757- vec_dest =
4758- vect_create_destination_var (scalar_dest, NULL_TREE);
4759- new_stmt = gimple_build_assign (vec_dest, vec_inv);
4760- new_temp = make_ssa_name (vec_dest, new_stmt);
4761+ mark_symbols_for_renaming (new_stmt);
4762+
4763+ /* 3. Handle explicit realignment if necessary/supported.
4764+ Create in loop:
4765+ vec_dest = realign_load (msq, lsq, realignment_token) */
4766+ if (alignment_support_scheme == dr_explicit_realign_optimized
4767+ || alignment_support_scheme == dr_explicit_realign)
4768+ {
4769+ tree tmp;
4770+
4771+ lsq = gimple_assign_lhs (new_stmt);
4772+ if (!realignment_token)
4773+ realignment_token = dataref_ptr;
4774+ vec_dest = vect_create_destination_var (scalar_dest, vectype);
4775+ tmp = build3 (REALIGN_LOAD_EXPR, vectype, msq, lsq,
4776+ realignment_token);
4777+ new_stmt = gimple_build_assign (vec_dest, tmp);
4778+ new_temp = make_ssa_name (vec_dest, new_stmt);
4779 gimple_assign_set_lhs (new_stmt, new_temp);
4780 vect_finish_stmt_generation (stmt, new_stmt, gsi);
4781
4782- for (k = nunits - 1; k >= 0; --k)
4783- t = tree_cons (NULL_TREE, new_temp, t);
4784- /* FIXME: use build_constructor directly. */
4785- vec_inv = build_constructor_from_list (vectype, t);
4786- new_temp = vect_init_vector (stmt, vec_inv, vectype, gsi);
4787+ if (alignment_support_scheme == dr_explicit_realign_optimized)
4788+ {
4789+ gcc_assert (phi);
4790+ if (i == vec_num - 1 && j == ncopies - 1)
4791+ add_phi_arg (phi, lsq,
4792+ loop_latch_edge (containing_loop),
4793+ UNKNOWN_LOCATION);
4794+ msq = lsq;
4795+ }
4796+ }
4797+
4798+ /* 4. Handle invariant-load. */
4799+ if (inv_p && !bb_vinfo)
4800+ {
4801+ gcc_assert (!strided_load);
4802+ gcc_assert (nested_in_vect_loop_p (loop, stmt));
4803+ if (j == 0)
4804+ {
4805+ int k;
4806+ tree t = NULL_TREE;
4807+ tree vec_inv, bitpos, bitsize = TYPE_SIZE (scalar_type);
4808+
4809+ /* CHECKME: bitpos depends on endianess? */
4810+ bitpos = bitsize_zero_node;
4811+ vec_inv = build3 (BIT_FIELD_REF, scalar_type, new_temp,
4812+ bitsize, bitpos);
4813+ vec_dest = vect_create_destination_var (scalar_dest,
4814+ NULL_TREE);
4815+ new_stmt = gimple_build_assign (vec_dest, vec_inv);
4816+ new_temp = make_ssa_name (vec_dest, new_stmt);
4817+ gimple_assign_set_lhs (new_stmt, new_temp);
4818+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
4819+
4820+ for (k = nunits - 1; k >= 0; --k)
4821+ t = tree_cons (NULL_TREE, new_temp, t);
4822+ /* FIXME: use build_constructor directly. */
4823+ vec_inv = build_constructor_from_list (vectype, t);
4824+ new_temp = vect_init_vector (stmt, vec_inv, vectype, gsi);
4825+ new_stmt = SSA_NAME_DEF_STMT (new_temp);
4826+ }
4827+ else
4828+ gcc_unreachable (); /* FORNOW. */
4829+ }
4830+
4831+ if (negative)
4832+ {
4833+ new_temp = reverse_vec_elements (new_temp, stmt, gsi);
4834 new_stmt = SSA_NAME_DEF_STMT (new_temp);
4835 }
4836- else
4837- gcc_unreachable (); /* FORNOW. */
4838- }
4839-
4840- if (negative)
4841- {
4842- new_temp = reverse_vec_elements (new_temp, stmt, gsi);
4843- new_stmt = SSA_NAME_DEF_STMT (new_temp);
4844- }
4845-
4846- /* Collect vector loads and later create their permutation in
4847- vect_transform_strided_load (). */
4848- if (strided_load || slp_perm)
4849- VEC_quick_push (tree, dr_chain, new_temp);
4850-
4851- /* Store vector loads in the corresponding SLP_NODE. */
4852- if (slp && !slp_perm)
4853- VEC_quick_push (gimple, SLP_TREE_VEC_STMTS (slp_node), new_stmt);
4854+
4855+ /* Collect vector loads and later create their permutation in
4856+ vect_transform_strided_load (). */
4857+ if (strided_load || slp_perm)
4858+ VEC_quick_push (tree, dr_chain, new_temp);
4859+
4860+ /* Store vector loads in the corresponding SLP_NODE. */
4861+ if (slp && !slp_perm)
4862+ VEC_quick_push (gimple, SLP_TREE_VEC_STMTS (slp_node),
4863+ new_stmt);
4864+ }
4865 }
4866
4867 if (slp && !slp_perm)
4868@@ -4345,12 +4526,9 @@
4869 {
4870 if (strided_load)
4871 {
4872- if (!vect_transform_strided_load (stmt, dr_chain, group_size, gsi))
4873- return false;
4874-
4875+ if (!load_lanes_p)
4876+ vect_transform_strided_load (stmt, dr_chain, group_size, gsi);
4877 *vec_stmt = STMT_VINFO_VEC_STMT (stmt_info);
4878- VEC_free (tree, heap, dr_chain);
4879- dr_chain = VEC_alloc (tree, heap, group_size);
4880 }
4881 else
4882 {
4883@@ -4361,11 +4539,10 @@
4884 prev_stmt_info = vinfo_for_stmt (new_stmt);
4885 }
4886 }
4887+ if (dr_chain)
4888+ VEC_free (tree, heap, dr_chain);
4889 }
4890
4891- if (dr_chain)
4892- VEC_free (tree, heap, dr_chain);
4893-
4894 return true;
4895 }
4896
4897@@ -4769,27 +4946,6 @@
4898 return false;
4899 }
4900
4901- if (!PURE_SLP_STMT (stmt_info))
4902- {
4903- /* Groups of strided accesses whose size is not a power of 2 are not
4904- vectorizable yet using loop-vectorization. Therefore, if this stmt
4905- feeds non-SLP-able stmts (i.e., this stmt has to be both SLPed and
4906- loop-based vectorized), the loop cannot be vectorized. */
4907- if (STMT_VINFO_STRIDED_ACCESS (stmt_info)
4908- && exact_log2 (DR_GROUP_SIZE (vinfo_for_stmt (
4909- DR_GROUP_FIRST_DR (stmt_info)))) == -1)
4910- {
4911- if (vect_print_dump_info (REPORT_DETAILS))
4912- {
4913- fprintf (vect_dump, "not vectorized: the size of group "
4914- "of strided accesses is not a power of 2");
4915- print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
4916- }
4917-
4918- return false;
4919- }
4920- }
4921-
4922 return true;
4923 }
4924
4925
4926=== modified file 'gcc/tree-vectorizer.h'
4927--- old/gcc/tree-vectorizer.h 2010-12-23 16:25:52 +0000
4928+++ new/gcc/tree-vectorizer.h 2011-05-05 15:43:06 +0000
4929@@ -788,9 +788,9 @@
4930 extern tree vectorizable_function (gimple, tree, tree);
4931 extern void vect_model_simple_cost (stmt_vec_info, int, enum vect_def_type *,
4932 slp_tree);
4933-extern void vect_model_store_cost (stmt_vec_info, int, enum vect_def_type,
4934- slp_tree);
4935-extern void vect_model_load_cost (stmt_vec_info, int, slp_tree);
4936+extern void vect_model_store_cost (stmt_vec_info, int, bool,
4937+ enum vect_def_type, slp_tree);
4938+extern void vect_model_load_cost (stmt_vec_info, int, bool, slp_tree);
4939 extern void vect_finish_stmt_generation (gimple, gimple,
4940 gimple_stmt_iterator *);
4941 extern bool vect_mark_stmts_to_be_vectorized (loop_vec_info);
4942@@ -823,21 +823,22 @@
4943 extern bool vect_analyze_data_ref_accesses (loop_vec_info, bb_vec_info);
4944 extern bool vect_prune_runtime_alias_test_list (loop_vec_info);
4945 extern bool vect_analyze_data_refs (loop_vec_info, bb_vec_info, int *);
4946-extern tree vect_create_data_ref_ptr (gimple, struct loop *, tree, tree *,
4947- gimple *, bool, bool *);
4948+extern tree vect_create_data_ref_ptr (gimple, tree, struct loop *, tree,
4949+ tree *, gimple *, bool, bool *);
4950 extern tree bump_vector_ptr (tree, gimple, gimple_stmt_iterator *, gimple, tree);
4951 extern tree vect_create_destination_var (tree, tree);
4952-extern bool vect_strided_store_supported (tree);
4953-extern bool vect_strided_load_supported (tree);
4954-extern bool vect_permute_store_chain (VEC(tree,heap) *,unsigned int, gimple,
4955+extern bool vect_strided_store_supported (tree, unsigned HOST_WIDE_INT);
4956+extern bool vect_store_lanes_supported (tree, unsigned HOST_WIDE_INT);
4957+extern bool vect_strided_load_supported (tree, unsigned HOST_WIDE_INT);
4958+extern bool vect_load_lanes_supported (tree, unsigned HOST_WIDE_INT);
4959+extern void vect_permute_store_chain (VEC(tree,heap) *,unsigned int, gimple,
4960 gimple_stmt_iterator *, VEC(tree,heap) **);
4961 extern tree vect_setup_realignment (gimple, gimple_stmt_iterator *, tree *,
4962 enum dr_alignment_support, tree,
4963 struct loop **);
4964-extern bool vect_permute_load_chain (VEC(tree,heap) *,unsigned int, gimple,
4965- gimple_stmt_iterator *, VEC(tree,heap) **);
4966-extern bool vect_transform_strided_load (gimple, VEC(tree,heap) *, int,
4967+extern void vect_transform_strided_load (gimple, VEC(tree,heap) *, int,
4968 gimple_stmt_iterator *);
4969+extern void vect_record_strided_load_vectors (gimple, VEC(tree,heap) *);
4970 extern int vect_get_place_in_interleaving_chain (gimple, gimple);
4971 extern tree vect_get_new_vect_var (tree, enum vect_var_kind, const char *);
4972 extern tree vect_create_addr_base_for_vector_ref (gimple, gimple_seq *,
4973
4974=== modified file 'gcc/tree.c'
4975--- old/gcc/tree.c 2011-05-18 13:29:24 +0000
4976+++ new/gcc/tree.c 2011-06-02 12:12:00 +0000
4977@@ -7321,6 +7321,15 @@
4978 return build_array_type_1 (elt_type, index_type, false);
4979 }
4980
4981+/* Return a representation of ELT_TYPE[NELTS], using indices of type
4982+ sizetype. */
4983+
4984+tree
4985+build_array_type_nelts (tree elt_type, unsigned HOST_WIDE_INT nelts)
4986+{
4987+ return build_array_type (elt_type, build_index_type (size_int (nelts - 1)));
4988+}
4989+
4990 /* Recursively examines the array elements of TYPE, until a non-array
4991 element type is found. */
4992
4993
4994=== modified file 'gcc/tree.h'
4995--- old/gcc/tree.h 2011-03-11 22:38:58 +0000
4996+++ new/gcc/tree.h 2011-05-05 15:43:06 +0000
4997@@ -4192,6 +4192,7 @@
4998 extern tree build_index_type (tree);
4999 extern tree build_array_type (tree, tree);
5000 extern tree build_nonshared_array_type (tree, tree);
5001+extern tree build_array_type_nelts (tree, unsigned HOST_WIDE_INT);
5002 extern tree build_function_type (tree, tree);
5003 extern tree build_function_type_list (tree, ...);
5004 extern tree build_function_type_skip_args (tree, bitmap);
5005
5006=== modified file 'gcc/value-prof.c'
5007--- old/gcc/value-prof.c 2011-01-29 03:54:56 +0000
5008+++ new/gcc/value-prof.c 2011-05-05 15:42:22 +0000
5009@@ -1242,6 +1242,9 @@
5010 if (TREE_CODE (callee) == FUNCTION_DECL)
5011 return false;
5012
5013+ if (gimple_call_internal_p (stmt))
5014+ return false;
5015+
5016 histogram = gimple_histogram_value_of_type (cfun, stmt, HIST_TYPE_INDIR_CALL);
5017 if (!histogram)
5018 return false;
5019@@ -1630,6 +1633,7 @@
5020 tree callee;
5021
5022 if (gimple_code (stmt) != GIMPLE_CALL
5023+ || gimple_call_internal_p (stmt)
5024 || gimple_call_fndecl (stmt) != NULL_TREE)
5025 return;
5026
5027
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106754.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106754.patch
deleted file mode 100644
index b64991836..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106754.patch
+++ /dev/null
@@ -1,329 +0,0 @@
12011-06-07 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF:
4
5 2011-06-07 Andrew Stubbs <ams@codesourcery.com>
6
7 gcc/
8 * config/arm/arm.md (*maddhidi4tb, *maddhidi4tt): New define_insns.
9 (*maddhisi4tb, *maddhisi4tt): New define_insns.
10
11 gcc/testsuite/
12 * gcc.target/arm/smlatb-1.c: New file.
13 * gcc.target/arm/smlatt-1.c: New file.
14 * gcc.target/arm/smlaltb-1.c: New file.
15 * gcc.target/arm/smlaltt-1.c: New file.
16
172011-06-07 Andrew Stubbs <ams@codesourcery.com>
18
19 Backport from FSF:
20
21 2011-06-07 Bernd Schmidt <bernds@codesourcery.com>
22 Andrew Stubbs <ams@codesourcery.com>
23
24 gcc/
25 * simplify-rtx.c (simplify_unary_operation_1): Canonicalize widening
26 multiplies.
27 * doc/md.texi (Canonicalization of Instructions): Document widening
28 multiply canonicalization.
29
30 gcc/testsuite/
31 * gcc.target/arm/mla-2.c: New test.
32
33=== modified file 'gcc/config/arm/arm.md'
34--- old/gcc/config/arm/arm.md 2011-05-13 13:42:39 +0000
35+++ new/gcc/config/arm/arm.md 2011-06-02 15:58:33 +0000
36@@ -1809,6 +1809,36 @@
37 (set_attr "predicable" "yes")]
38 )
39
40+;; Note: there is no maddhisi4ibt because this one is canonical form
41+(define_insn "*maddhisi4tb"
42+ [(set (match_operand:SI 0 "s_register_operand" "=r")
43+ (plus:SI (mult:SI (ashiftrt:SI
44+ (match_operand:SI 1 "s_register_operand" "r")
45+ (const_int 16))
46+ (sign_extend:SI
47+ (match_operand:HI 2 "s_register_operand" "r")))
48+ (match_operand:SI 3 "s_register_operand" "r")))]
49+ "TARGET_DSP_MULTIPLY"
50+ "smlatb%?\\t%0, %1, %2, %3"
51+ [(set_attr "insn" "smlaxy")
52+ (set_attr "predicable" "yes")]
53+)
54+
55+(define_insn "*maddhisi4tt"
56+ [(set (match_operand:SI 0 "s_register_operand" "=r")
57+ (plus:SI (mult:SI (ashiftrt:SI
58+ (match_operand:SI 1 "s_register_operand" "r")
59+ (const_int 16))
60+ (ashiftrt:SI
61+ (match_operand:SI 2 "s_register_operand" "r")
62+ (const_int 16)))
63+ (match_operand:SI 3 "s_register_operand" "r")))]
64+ "TARGET_DSP_MULTIPLY"
65+ "smlatt%?\\t%0, %1, %2, %3"
66+ [(set_attr "insn" "smlaxy")
67+ (set_attr "predicable" "yes")]
68+)
69+
70 (define_insn "*maddhidi4"
71 [(set (match_operand:DI 0 "s_register_operand" "=r")
72 (plus:DI
73@@ -1822,6 +1852,39 @@
74 [(set_attr "insn" "smlalxy")
75 (set_attr "predicable" "yes")])
76
77+;; Note: there is no maddhidi4ibt because this one is canonical form
78+(define_insn "*maddhidi4tb"
79+ [(set (match_operand:DI 0 "s_register_operand" "=r")
80+ (plus:DI
81+ (mult:DI (sign_extend:DI
82+ (ashiftrt:SI
83+ (match_operand:SI 1 "s_register_operand" "r")
84+ (const_int 16)))
85+ (sign_extend:DI
86+ (match_operand:HI 2 "s_register_operand" "r")))
87+ (match_operand:DI 3 "s_register_operand" "0")))]
88+ "TARGET_DSP_MULTIPLY"
89+ "smlaltb%?\\t%Q0, %R0, %1, %2"
90+ [(set_attr "insn" "smlalxy")
91+ (set_attr "predicable" "yes")])
92+
93+(define_insn "*maddhidi4tt"
94+ [(set (match_operand:DI 0 "s_register_operand" "=r")
95+ (plus:DI
96+ (mult:DI (sign_extend:DI
97+ (ashiftrt:SI
98+ (match_operand:SI 1 "s_register_operand" "r")
99+ (const_int 16)))
100+ (sign_extend:DI
101+ (ashiftrt:SI
102+ (match_operand:SI 2 "s_register_operand" "r")
103+ (const_int 16))))
104+ (match_operand:DI 3 "s_register_operand" "0")))]
105+ "TARGET_DSP_MULTIPLY"
106+ "smlaltt%?\\t%Q0, %R0, %1, %2"
107+ [(set_attr "insn" "smlalxy")
108+ (set_attr "predicable" "yes")])
109+
110 (define_expand "mulsf3"
111 [(set (match_operand:SF 0 "s_register_operand" "")
112 (mult:SF (match_operand:SF 1 "s_register_operand" "")
113
114=== modified file 'gcc/doc/md.texi'
115--- old/gcc/doc/md.texi 2011-05-05 15:43:06 +0000
116+++ new/gcc/doc/md.texi 2011-06-07 11:18:20 +0000
117@@ -5929,6 +5929,23 @@
118 will be written using @code{zero_extract} rather than the equivalent
119 @code{and} or @code{sign_extract} operations.
120
121+@cindex @code{mult}, canonicalization of
122+@item
123+@code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
124+(sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
125+(sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
126+for @code{zero_extend}.
127+
128+@item
129+@code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
130+@var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
131+to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
132+@var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
133+patterns using @code{zero_extend} and @code{lshiftrt}. If the second
134+operand of @code{mult} is also a shift, then that is extended also.
135+This transformation is only applied when it can be proven that the
136+original operation had sufficient precision to prevent overflow.
137+
138 @end itemize
139
140 Further canonicalization rules are defined in the function
141
142=== modified file 'gcc/simplify-rtx.c'
143--- old/gcc/simplify-rtx.c 2011-05-27 14:31:18 +0000
144+++ new/gcc/simplify-rtx.c 2011-06-02 12:32:16 +0000
145@@ -1000,6 +1000,48 @@
146 && GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF)
147 return XEXP (op, 0);
148
149+ /* Extending a widening multiplication should be canonicalized to
150+ a wider widening multiplication. */
151+ if (GET_CODE (op) == MULT)
152+ {
153+ rtx lhs = XEXP (op, 0);
154+ rtx rhs = XEXP (op, 1);
155+ enum rtx_code lcode = GET_CODE (lhs);
156+ enum rtx_code rcode = GET_CODE (rhs);
157+
158+ /* Widening multiplies usually extend both operands, but sometimes
159+ they use a shift to extract a portion of a register. */
160+ if ((lcode == SIGN_EXTEND
161+ || (lcode == ASHIFTRT && CONST_INT_P (XEXP (lhs, 1))))
162+ && (rcode == SIGN_EXTEND
163+ || (rcode == ASHIFTRT && CONST_INT_P (XEXP (rhs, 1)))))
164+ {
165+ enum machine_mode lmode = GET_MODE (lhs);
166+ enum machine_mode rmode = GET_MODE (rhs);
167+ int bits;
168+
169+ if (lcode == ASHIFTRT)
170+ /* Number of bits not shifted off the end. */
171+ bits = GET_MODE_PRECISION (lmode) - INTVAL (XEXP (lhs, 1));
172+ else /* lcode == SIGN_EXTEND */
173+ /* Size of inner mode. */
174+ bits = GET_MODE_PRECISION (GET_MODE (XEXP (lhs, 0)));
175+
176+ if (rcode == ASHIFTRT)
177+ bits += GET_MODE_PRECISION (rmode) - INTVAL (XEXP (rhs, 1));
178+ else /* rcode == SIGN_EXTEND */
179+ bits += GET_MODE_PRECISION (GET_MODE (XEXP (rhs, 0)));
180+
181+ /* We can only widen multiplies if the result is mathematiclly
182+ equivalent. I.e. if overflow was impossible. */
183+ if (bits <= GET_MODE_PRECISION (GET_MODE (op)))
184+ return simplify_gen_binary
185+ (MULT, mode,
186+ simplify_gen_unary (SIGN_EXTEND, mode, lhs, lmode),
187+ simplify_gen_unary (SIGN_EXTEND, mode, rhs, rmode));
188+ }
189+ }
190+
191 /* Check for a sign extension of a subreg of a promoted
192 variable, where the promotion is sign-extended, and the
193 target mode is the same as the variable's promotion. */
194@@ -1071,6 +1113,48 @@
195 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
196 return rtl_hooks.gen_lowpart_no_emit (mode, op);
197
198+ /* Extending a widening multiplication should be canonicalized to
199+ a wider widening multiplication. */
200+ if (GET_CODE (op) == MULT)
201+ {
202+ rtx lhs = XEXP (op, 0);
203+ rtx rhs = XEXP (op, 1);
204+ enum rtx_code lcode = GET_CODE (lhs);
205+ enum rtx_code rcode = GET_CODE (rhs);
206+
207+ /* Widening multiplies usually extend both operands, but sometimes
208+ they use a shift to extract a portion of a register. */
209+ if ((lcode == ZERO_EXTEND
210+ || (lcode == LSHIFTRT && CONST_INT_P (XEXP (lhs, 1))))
211+ && (rcode == ZERO_EXTEND
212+ || (rcode == LSHIFTRT && CONST_INT_P (XEXP (rhs, 1)))))
213+ {
214+ enum machine_mode lmode = GET_MODE (lhs);
215+ enum machine_mode rmode = GET_MODE (rhs);
216+ int bits;
217+
218+ if (lcode == LSHIFTRT)
219+ /* Number of bits not shifted off the end. */
220+ bits = GET_MODE_PRECISION (lmode) - INTVAL (XEXP (lhs, 1));
221+ else /* lcode == ZERO_EXTEND */
222+ /* Size of inner mode. */
223+ bits = GET_MODE_PRECISION (GET_MODE (XEXP (lhs, 0)));
224+
225+ if (rcode == LSHIFTRT)
226+ bits += GET_MODE_PRECISION (rmode) - INTVAL (XEXP (rhs, 1));
227+ else /* rcode == ZERO_EXTEND */
228+ bits += GET_MODE_PRECISION (GET_MODE (XEXP (rhs, 0)));
229+
230+ /* We can only widen multiplies if the result is mathematiclly
231+ equivalent. I.e. if overflow was impossible. */
232+ if (bits <= GET_MODE_PRECISION (GET_MODE (op)))
233+ return simplify_gen_binary
234+ (MULT, mode,
235+ simplify_gen_unary (ZERO_EXTEND, mode, lhs, lmode),
236+ simplify_gen_unary (ZERO_EXTEND, mode, rhs, rmode));
237+ }
238+ }
239+
240 /* (zero_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
241 if (GET_CODE (op) == ZERO_EXTEND)
242 return simplify_gen_unary (ZERO_EXTEND, mode, XEXP (op, 0),
243
244=== added file 'gcc/testsuite/gcc.target/arm/mla-2.c'
245--- old/gcc/testsuite/gcc.target/arm/mla-2.c 1970-01-01 00:00:00 +0000
246+++ new/gcc/testsuite/gcc.target/arm/mla-2.c 2011-06-02 12:32:16 +0000
247@@ -0,0 +1,9 @@
248+/* { dg-do compile } */
249+/* { dg-options "-O2 -march=armv7-a" } */
250+
251+long long foolong (long long x, short *a, short *b)
252+{
253+ return x + *a * *b;
254+}
255+
256+/* { dg-final { scan-assembler "smlalbb" } } */
257
258=== added file 'gcc/testsuite/gcc.target/arm/smlaltb-1.c'
259--- old/gcc/testsuite/gcc.target/arm/smlaltb-1.c 1970-01-01 00:00:00 +0000
260+++ new/gcc/testsuite/gcc.target/arm/smlaltb-1.c 2011-06-02 15:58:33 +0000
261@@ -0,0 +1,13 @@
262+/* { dg-do compile } */
263+/* { dg-options "-O2 -march=armv7-a" } */
264+
265+long long int
266+foo (long long x, int in)
267+{
268+ short a = in & 0xffff;
269+ short b = (in & 0xffff0000) >> 16;
270+
271+ return x + b * a;
272+}
273+
274+/* { dg-final { scan-assembler "smlaltb" } } */
275
276=== added file 'gcc/testsuite/gcc.target/arm/smlaltt-1.c'
277--- old/gcc/testsuite/gcc.target/arm/smlaltt-1.c 1970-01-01 00:00:00 +0000
278+++ new/gcc/testsuite/gcc.target/arm/smlaltt-1.c 2011-06-02 15:58:33 +0000
279@@ -0,0 +1,13 @@
280+/* { dg-do compile } */
281+/* { dg-options "-O2 -march=armv7-a" } */
282+
283+long long int
284+foo (long long x, int in1, int in2)
285+{
286+ short a = (in1 & 0xffff0000) >> 16;
287+ short b = (in2 & 0xffff0000) >> 16;
288+
289+ return x + b * a;
290+}
291+
292+/* { dg-final { scan-assembler "smlaltt" } } */
293
294=== added file 'gcc/testsuite/gcc.target/arm/smlatb-1.c'
295--- old/gcc/testsuite/gcc.target/arm/smlatb-1.c 1970-01-01 00:00:00 +0000
296+++ new/gcc/testsuite/gcc.target/arm/smlatb-1.c 2011-06-02 15:58:33 +0000
297@@ -0,0 +1,13 @@
298+/* { dg-do compile } */
299+/* { dg-options "-O2 -march=armv7-a" } */
300+
301+int
302+foo (int x, int in)
303+{
304+ short a = in & 0xffff;
305+ short b = (in & 0xffff0000) >> 16;
306+
307+ return x + b * a;
308+}
309+
310+/* { dg-final { scan-assembler "smlatb" } } */
311
312=== added file 'gcc/testsuite/gcc.target/arm/smlatt-1.c'
313--- old/gcc/testsuite/gcc.target/arm/smlatt-1.c 1970-01-01 00:00:00 +0000
314+++ new/gcc/testsuite/gcc.target/arm/smlatt-1.c 2011-06-02 15:58:33 +0000
315@@ -0,0 +1,13 @@
316+/* { dg-do compile } */
317+/* { dg-options "-O2 -march=armv7-a" } */
318+
319+int
320+foo (int x, int in1, int in2)
321+{
322+ short a = (in1 & 0xffff0000) >> 16;
323+ short b = (in2 & 0xffff0000) >> 16;
324+
325+ return x + b * a;
326+}
327+
328+/* { dg-final { scan-assembler "smlatt" } } */
329
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106755.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106755.patch
deleted file mode 100644
index b8f587c9f..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106755.patch
+++ /dev/null
@@ -1,120 +0,0 @@
12011-06-10 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline:
4 gcc/
5 2011-06-02 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
6 * config/arm/neon.md (orndi3_neon): Actually split it.
7
8
92011-06-10 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
10
11 Backport from mainline.
12 gcc/
13 2011-05-26 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
14
15 * config/arm/neon.md ("orn<mode>3_neon"): Canonicalize not.
16 ("orndi3_neon"): Likewise.
17 ("bic<mode>3_neon"): Likewise.
18
19 gcc/testsuite
20 2011-05-26 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
21
22 * gcc.target/arm/neon-vorn-vbic.c: New test.
23
24=== modified file 'gcc/config/arm/neon.md'
25--- old/gcc/config/arm/neon.md 2011-06-02 12:12:00 +0000
26+++ new/gcc/config/arm/neon.md 2011-06-04 00:04:47 +0000
27@@ -783,30 +783,57 @@
28
29 (define_insn "orn<mode>3_neon"
30 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
31- (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
32- (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))))]
33+ (ior:VDQ (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))
34+ (match_operand:VDQ 1 "s_register_operand" "w")))]
35 "TARGET_NEON"
36 "vorn\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
37 [(set_attr "neon_type" "neon_int_1")]
38 )
39
40-(define_insn "orndi3_neon"
41- [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r")
42- (ior:DI (match_operand:DI 1 "s_register_operand" "w,r,0")
43- (not:DI (match_operand:DI 2 "s_register_operand" "w,0,r"))))]
44+;; TODO: investigate whether we should disable
45+;; this and bicdi3_neon for the A8 in line with the other
46+;; changes above.
47+(define_insn_and_split "orndi3_neon"
48+ [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r")
49+ (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,0,0,r"))
50+ (match_operand:DI 1 "s_register_operand" "w,r,r,0")))]
51 "TARGET_NEON"
52 "@
53 vorn\t%P0, %P1, %P2
54 #
55+ #
56 #"
57- [(set_attr "neon_type" "neon_int_1,*,*")
58- (set_attr "length" "*,8,8")]
59+ "reload_completed &&
60+ (TARGET_NEON && !(IS_VFP_REGNUM (REGNO (operands[0]))))"
61+ [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
62+ (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
63+ "
64+ {
65+ if (TARGET_THUMB2)
66+ {
67+ operands[3] = gen_highpart (SImode, operands[0]);
68+ operands[0] = gen_lowpart (SImode, operands[0]);
69+ operands[4] = gen_highpart (SImode, operands[2]);
70+ operands[2] = gen_lowpart (SImode, operands[2]);
71+ operands[5] = gen_highpart (SImode, operands[1]);
72+ operands[1] = gen_lowpart (SImode, operands[1]);
73+ }
74+ else
75+ {
76+ emit_insn (gen_one_cmpldi2 (operands[0], operands[2]));
77+ emit_insn (gen_iordi3 (operands[0], operands[1], operands[0]));
78+ DONE;
79+ }
80+ }"
81+ [(set_attr "neon_type" "neon_int_1,*,*,*")
82+ (set_attr "length" "*,16,8,8")
83+ (set_attr "arch" "any,a,t2,t2")]
84 )
85
86 (define_insn "bic<mode>3_neon"
87 [(set (match_operand:VDQ 0 "s_register_operand" "=w")
88- (and:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
89- (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))))]
90+ (and:VDQ (not:VDQ (match_operand:VDQ 2 "s_register_operand" "w"))
91+ (match_operand:VDQ 1 "s_register_operand" "w")))]
92 "TARGET_NEON"
93 "vbic\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
94 [(set_attr "neon_type" "neon_int_1")]
95
96=== added file 'gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c'
97--- old/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c 1970-01-01 00:00:00 +0000
98+++ new/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c 2011-06-03 23:50:02 +0000
99@@ -0,0 +1,20 @@
100+/* { dg-do compile } */
101+/* { dg-require-effective-target arm_neon_ok } */
102+/* { dg-options "-O2 -ftree-vectorize" } */
103+/* { dg-add-options arm_neon } */
104+
105+void bor (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b)
106+{
107+ int i;
108+ for (i = 0; i < 9; i++)
109+ c[i] = b[i] | (~a[i]);
110+}
111+void bic (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b)
112+{
113+ int i;
114+ for (i = 0; i < 9; i++)
115+ c[i] = b[i] & (~a[i]);
116+}
117+
118+/* { dg-final { scan-assembler "vorn\\t" } } */
119+/* { dg-final { scan-assembler "vbic\\t" } } */
120
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106759.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106759.patch
deleted file mode 100644
index c51576794..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106759.patch
+++ /dev/null
@@ -1,545 +0,0 @@
12011-06-20 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline.
4 2011-06-03 Julian Brown <julian@codesourcery.com>
5
6 * config/arm/arm-cores.def (strongarm, strongarm110, strongarm1100)
7 (strongarm1110): Use strongarm tuning.
8 * config/arm/arm-protos.h (tune_params): Add max_insns_skipped
9 field.
10 * config/arm/arm.c (arm_strongarm_tune): New.
11 (arm_slowmul_tune, arm_fastmul_tune, arm_xscale_tune, arm_9e_tune)
12 (arm_v6t2_tune, arm_cortex_tune, arm_cortex_a5_tune)
13 (arm_cortex_a9_tune, arm_fa726te_tune): Add max_insns_skipped field
14 setting, using previous defaults or 1 for Cortex-A5.
15 (arm_option_override): Set max_insns_skipped from current tuning.
16
172011-06-14 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
18
19 Backport from mainline.
20 2011-06-02 Julian Brown <julian@codesourcery.com>
21
22 * config/arm/arm-cores.def (cortex-a5): Use cortex_a5 tuning.
23 * config/arm/arm.c (arm_cortex_a5_branch_cost): New.
24 (arm_cortex_a5_tune): New.
25
26 2011-06-02 Julian Brown <julian@codesourcery.com>
27
28 * config/arm/arm-protos.h (tune_params): Add branch_cost hook.
29 * config/arm/arm.c (arm_default_branch_cost): New.
30 (arm_slowmul_tune, arm_fastmul_tune, arm_xscale_tune, arm_9e_tune)
31 (arm_v6t2_tune, arm_cortex_tune, arm_cortex_a9_tune)
32 (arm_fa726_tune): Set branch_cost field using
33 arm_default_branch_cost.
34 * config/arm/arm.h (BRANCH_COST): Use branch_cost hook from
35 current_tune structure.
36 * dojump.c (tm_p.h): Include file.
37
38 2011-06-02 Julian Brown <julian@codesourcery.com>
39
40 * config/arm/arm-cores.def (arm1156t2-s, arm1156t2f-s): Use v6t2
41 tuning.
42 (cortex-a5, cortex-a8, cortex-a15, cortex-r4, cortex-r4f, cortex-m4)
43 (cortex-m3, cortex-m1, cortex-m0): Use cortex tuning.
44 * config/arm/arm-protos.h (tune_params): Add prefer_constant_pool
45 field.
46 * config/arm/arm.c (arm_slowmul_tune, arm_fastmul_tune)
47 (arm_xscale_tune, arm_9e_tune, arm_cortex_a9_tune)
48 (arm_fa726te_tune): Add prefer_constant_pool setting.
49 (arm_v6t2_tune, arm_cortex_tune): New.
50 * config/arm/arm.h (TARGET_USE_MOVT): Make dependent on
51 prefer_constant_pool setting.
52
532011-06-14 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
54
55 Backport from mainline
56 2011-06-01 Paul Brook <paul@cpodesourcery.com>
57
58 * config/arm/arm-cores.def: Add cortex-r5. Add DIV flags to
59 Cortex-A15.
60 * config/arm/arm-tune.md: Regenerate.
61 * config/arm/arm.c (FL_DIV): Rename...
62 (FL_THUMB_DIV): ... to this.
63 (FL_ARM_DIV): Define.
64 (FL_FOR_ARCH7R, FL_FOR_ARCH7M): Use FL_THUMB_DIV.
65 (arm_arch_hwdiv): Remove.
66 (arm_arch_thumb_hwdiv, arm_arch_arm_hwdiv): New variables.
67 (arm_issue_rate): Add cortexr5.
68 * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Set
69 __ARM_ARCH_EXT_IDIV__.
70 (TARGET_IDIV): Define.
71 (arm_arch_hwdiv): Remove.
72 (arm_arch_arm_hwdiv, arm_arch_thumb_hwdiv): New prototypes.
73 * config/arm/arm.md (tune_cortexr4): Add cortexr5.
74 (divsi3, udivsi3): New patterns.
75 * config/arm/thumb2.md (divsi3, udivsi3): Remove.
76 * doc/invoke.texi: Document ARM -mcpu=cortex-r5
77
78=== modified file 'gcc/config/arm/arm-cores.def'
79--- old/gcc/config/arm/arm-cores.def 2011-01-03 20:52:22 +0000
80+++ new/gcc/config/arm/arm-cores.def 2011-06-14 16:00:30 +0000
81@@ -70,10 +70,10 @@
82 /* V4 Architecture Processors */
83 ARM_CORE("arm8", arm8, 4, FL_MODE26 | FL_LDSCHED, fastmul)
84 ARM_CORE("arm810", arm810, 4, FL_MODE26 | FL_LDSCHED, fastmul)
85-ARM_CORE("strongarm", strongarm, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
86-ARM_CORE("strongarm110", strongarm110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
87-ARM_CORE("strongarm1100", strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
88-ARM_CORE("strongarm1110", strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, fastmul)
89+ARM_CORE("strongarm", strongarm, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
90+ARM_CORE("strongarm110", strongarm110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
91+ARM_CORE("strongarm1100", strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
92+ARM_CORE("strongarm1110", strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
93 ARM_CORE("fa526", fa526, 4, FL_LDSCHED, fastmul)
94 ARM_CORE("fa626", fa626, 4, FL_LDSCHED, fastmul)
95
96@@ -122,15 +122,16 @@
97 ARM_CORE("arm1176jzf-s", arm1176jzfs, 6ZK, FL_LDSCHED | FL_VFPV2, 9e)
98 ARM_CORE("mpcorenovfp", mpcorenovfp, 6K, FL_LDSCHED, 9e)
99 ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e)
100-ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, 9e)
101-ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, 9e)
102-ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, 9e)
103-ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e)
104+ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, v6t2)
105+ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, v6t2)
106+ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5)
107+ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex)
108 ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9)
109-ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED, 9e)
110-ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e)
111-ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e)
112-ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, 9e)
113-ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e)
114-ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e)
115-ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, 9e)
116+ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
117+ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex)
118+ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex)
119+ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex)
120+ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, cortex)
121+ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, cortex)
122+ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, cortex)
123+ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, cortex)
124
125=== modified file 'gcc/config/arm/arm-protos.h'
126--- old/gcc/config/arm/arm-protos.h 2011-05-03 15:17:25 +0000
127+++ new/gcc/config/arm/arm-protos.h 2011-06-14 16:00:30 +0000
128@@ -219,9 +219,14 @@
129 bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
130 bool (*sched_adjust_cost) (rtx, rtx, rtx, int *);
131 int constant_limit;
132+ /* Maximum number of instructions to conditionalise in
133+ arm_final_prescan_insn. */
134+ int max_insns_skipped;
135 int num_prefetch_slots;
136 int l1_cache_size;
137 int l1_cache_line_size;
138+ bool prefer_constant_pool;
139+ int (*branch_cost) (bool, bool);
140 };
141
142 extern const struct tune_params *current_tune;
143
144=== modified file 'gcc/config/arm/arm-tune.md'
145--- old/gcc/config/arm/arm-tune.md 2010-12-20 17:48:51 +0000
146+++ new/gcc/config/arm/arm-tune.md 2011-06-14 14:37:30 +0000
147@@ -1,5 +1,5 @@
148 ;; -*- buffer-read-only: t -*-
149 ;; Generated automatically by gentune.sh from arm-cores.def
150 (define_attr "tune"
151- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0"
152+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
153 (const (symbol_ref "((enum attr_tune) arm_tune)")))
154
155=== modified file 'gcc/config/arm/arm.c'
156--- old/gcc/config/arm/arm.c 2011-05-11 14:49:48 +0000
157+++ new/gcc/config/arm/arm.c 2011-06-14 16:00:30 +0000
158@@ -255,6 +255,8 @@
159 static void arm_conditional_register_usage (void);
160 static reg_class_t arm_preferred_rename_class (reg_class_t rclass);
161 static unsigned int arm_autovectorize_vector_sizes (void);
162+static int arm_default_branch_cost (bool, bool);
163+static int arm_cortex_a5_branch_cost (bool, bool);
164
165
166 /* Table of machine attributes. */
167@@ -672,12 +674,13 @@
168 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
169 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
170 profile. */
171-#define FL_DIV (1 << 18) /* Hardware divide. */
172+#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */
173 #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
174 #define FL_NEON (1 << 20) /* Neon instructions. */
175 #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
176 architecture. */
177 #define FL_ARCH7 (1 << 22) /* Architecture 7. */
178+#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
179
180 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
181
182@@ -704,8 +707,8 @@
183 #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
184 #define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
185 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
186-#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
187-#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
188+#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
189+#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
190 #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
191
192 /* The bits in this mask specify which
193@@ -791,7 +794,8 @@
194 int arm_arch_thumb2;
195
196 /* Nonzero if chip supports integer division instruction. */
197-int arm_arch_hwdiv;
198+int arm_arch_arm_hwdiv;
199+int arm_arch_thumb_hwdiv;
200
201 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference,
202 we must report the mode of the memory reference from
203@@ -864,48 +868,117 @@
204 {
205 arm_slowmul_rtx_costs,
206 NULL,
207- 3,
208- ARM_PREFETCH_NOT_BENEFICIAL
209+ 3, /* Constant limit. */
210+ 5, /* Max cond insns. */
211+ ARM_PREFETCH_NOT_BENEFICIAL,
212+ true, /* Prefer constant pool. */
213+ arm_default_branch_cost
214 };
215
216 const struct tune_params arm_fastmul_tune =
217 {
218 arm_fastmul_rtx_costs,
219 NULL,
220- 1,
221- ARM_PREFETCH_NOT_BENEFICIAL
222+ 1, /* Constant limit. */
223+ 5, /* Max cond insns. */
224+ ARM_PREFETCH_NOT_BENEFICIAL,
225+ true, /* Prefer constant pool. */
226+ arm_default_branch_cost
227+};
228+
229+/* StrongARM has early execution of branches, so a sequence that is worth
230+ skipping is shorter. Set max_insns_skipped to a lower value. */
231+
232+const struct tune_params arm_strongarm_tune =
233+{
234+ arm_fastmul_rtx_costs,
235+ NULL,
236+ 1, /* Constant limit. */
237+ 3, /* Max cond insns. */
238+ ARM_PREFETCH_NOT_BENEFICIAL,
239+ true, /* Prefer constant pool. */
240+ arm_default_branch_cost
241 };
242
243 const struct tune_params arm_xscale_tune =
244 {
245 arm_xscale_rtx_costs,
246 xscale_sched_adjust_cost,
247- 2,
248- ARM_PREFETCH_NOT_BENEFICIAL
249+ 2, /* Constant limit. */
250+ 3, /* Max cond insns. */
251+ ARM_PREFETCH_NOT_BENEFICIAL,
252+ true, /* Prefer constant pool. */
253+ arm_default_branch_cost
254 };
255
256 const struct tune_params arm_9e_tune =
257 {
258 arm_9e_rtx_costs,
259 NULL,
260- 1,
261- ARM_PREFETCH_NOT_BENEFICIAL
262+ 1, /* Constant limit. */
263+ 5, /* Max cond insns. */
264+ ARM_PREFETCH_NOT_BENEFICIAL,
265+ true, /* Prefer constant pool. */
266+ arm_default_branch_cost
267+};
268+
269+const struct tune_params arm_v6t2_tune =
270+{
271+ arm_9e_rtx_costs,
272+ NULL,
273+ 1, /* Constant limit. */
274+ 5, /* Max cond insns. */
275+ ARM_PREFETCH_NOT_BENEFICIAL,
276+ false, /* Prefer constant pool. */
277+ arm_default_branch_cost
278+};
279+
280+/* Generic Cortex tuning. Use more specific tunings if appropriate. */
281+const struct tune_params arm_cortex_tune =
282+{
283+ arm_9e_rtx_costs,
284+ NULL,
285+ 1, /* Constant limit. */
286+ 5, /* Max cond insns. */
287+ ARM_PREFETCH_NOT_BENEFICIAL,
288+ false, /* Prefer constant pool. */
289+ arm_default_branch_cost
290+};
291+
292+/* Branches can be dual-issued on Cortex-A5, so conditional execution is
293+ less appealing. Set max_insns_skipped to a low value. */
294+
295+const struct tune_params arm_cortex_a5_tune =
296+{
297+ arm_9e_rtx_costs,
298+ NULL,
299+ 1, /* Constant limit. */
300+ 1, /* Max cond insns. */
301+ ARM_PREFETCH_NOT_BENEFICIAL,
302+ false, /* Prefer constant pool. */
303+ arm_cortex_a5_branch_cost
304 };
305
306 const struct tune_params arm_cortex_a9_tune =
307 {
308 arm_9e_rtx_costs,
309 cortex_a9_sched_adjust_cost,
310- 1,
311- ARM_PREFETCH_BENEFICIAL(4,32,32)
312+ 1, /* Constant limit. */
313+ 5, /* Max cond insns. */
314+ ARM_PREFETCH_BENEFICIAL(4,32,32),
315+ false, /* Prefer constant pool. */
316+ arm_default_branch_cost
317 };
318
319 const struct tune_params arm_fa726te_tune =
320 {
321 arm_9e_rtx_costs,
322 fa726te_sched_adjust_cost,
323- 1,
324- ARM_PREFETCH_NOT_BENEFICIAL
325+ 1, /* Constant limit. */
326+ 5, /* Max cond insns. */
327+ ARM_PREFETCH_NOT_BENEFICIAL,
328+ true, /* Prefer constant pool. */
329+ arm_default_branch_cost
330 };
331
332
333@@ -1711,7 +1784,8 @@
334 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
335 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
336 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
337- arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
338+ arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0;
339+ arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0;
340 arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
341
342 /* If we are not using the default (ARM mode) section anchor offset
343@@ -1991,12 +2065,7 @@
344 max_insns_skipped = 6;
345 }
346 else
347- {
348- /* StrongARM has early execution of branches, so a sequence
349- that is worth skipping is shorter. */
350- if (arm_tune_strongarm)
351- max_insns_skipped = 3;
352- }
353+ max_insns_skipped = current_tune->max_insns_skipped;
354
355 /* Hot/Cold partitioning is not currently supported, since we can't
356 handle literal pool placement in that case. */
357@@ -8211,6 +8280,21 @@
358 return cost;
359 }
360
361+static int
362+arm_default_branch_cost (bool speed_p, bool predictable_p ATTRIBUTE_UNUSED)
363+{
364+ if (TARGET_32BIT)
365+ return (TARGET_THUMB2 && !speed_p) ? 1 : 4;
366+ else
367+ return (optimize > 0) ? 2 : 0;
368+}
369+
370+static int
371+arm_cortex_a5_branch_cost (bool speed_p, bool predictable_p)
372+{
373+ return speed_p ? 0 : arm_default_branch_cost (speed_p, predictable_p);
374+}
375+
376 static int fp_consts_inited = 0;
377
378 /* Only zero is valid for VFP. Other values are also valid for FPA. */
379@@ -23123,6 +23207,7 @@
380 {
381 case cortexr4:
382 case cortexr4f:
383+ case cortexr5:
384 case cortexa5:
385 case cortexa8:
386 case cortexa9:
387
388=== modified file 'gcc/config/arm/arm.h'
389--- old/gcc/config/arm/arm.h 2011-06-02 12:12:00 +0000
390+++ new/gcc/config/arm/arm.h 2011-06-14 14:53:07 +0000
391@@ -101,6 +101,8 @@
392 builtin_define ("__ARM_PCS"); \
393 builtin_define ("__ARM_EABI__"); \
394 } \
395+ if (TARGET_IDIV) \
396+ builtin_define ("__ARM_ARCH_EXT_IDIV__"); \
397 } while (0)
398
399 /* The various ARM cores. */
400@@ -282,7 +284,8 @@
401 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
402
403 /* Should MOVW/MOVT be used in preference to a constant pool. */
404-#define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
405+#define TARGET_USE_MOVT \
406+ (arm_arch_thumb2 && !optimize_size && !current_tune->prefer_constant_pool)
407
408 /* We could use unified syntax for arm mode, but for now we just use it
409 for Thumb-2. */
410@@ -303,6 +306,10 @@
411 /* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
412 #define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
413
414+/* Nonzero if integer division instructions supported. */
415+#define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
416+ || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
417+
418 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
419 then TARGET_AAPCS_BASED must be true -- but the converse does not
420 hold. TARGET_BPABI implies the use of the BPABI runtime library,
421@@ -487,8 +494,11 @@
422 /* Nonzero if chip supports Thumb 2. */
423 extern int arm_arch_thumb2;
424
425-/* Nonzero if chip supports integer division instruction. */
426-extern int arm_arch_hwdiv;
427+/* Nonzero if chip supports integer division instruction in ARM mode. */
428+extern int arm_arch_arm_hwdiv;
429+
430+/* Nonzero if chip supports integer division instruction in Thumb mode. */
431+extern int arm_arch_thumb_hwdiv;
432
433 #ifndef TARGET_DEFAULT
434 #define TARGET_DEFAULT (MASK_APCS_FRAME)
435@@ -2018,8 +2028,8 @@
436 /* Try to generate sequences that don't involve branches, we can then use
437 conditional instructions */
438 #define BRANCH_COST(speed_p, predictable_p) \
439- (TARGET_32BIT ? (TARGET_THUMB2 && !speed_p ? 1 : 4) \
440- : (optimize > 0 ? 2 : 0))
441+ (current_tune->branch_cost (speed_p, predictable_p))
442+
443
444 /* Position Independent Code. */
445 /* We decide which register to use based on the compilation options and
446
447=== modified file 'gcc/config/arm/arm.md'
448--- old/gcc/config/arm/arm.md 2011-06-02 15:58:33 +0000
449+++ new/gcc/config/arm/arm.md 2011-06-14 14:37:30 +0000
450@@ -490,7 +490,7 @@
451
452 (define_attr "tune_cortexr4" "yes,no"
453 (const (if_then_else
454- (eq_attr "tune" "cortexr4,cortexr4f")
455+ (eq_attr "tune" "cortexr4,cortexr4f,cortexr5")
456 (const_string "yes")
457 (const_string "no"))))
458
459@@ -3738,6 +3738,28 @@
460 (set_attr "predicable" "yes")]
461 )
462
463+
464+;; Division instructions
465+(define_insn "divsi3"
466+ [(set (match_operand:SI 0 "s_register_operand" "=r")
467+ (div:SI (match_operand:SI 1 "s_register_operand" "r")
468+ (match_operand:SI 2 "s_register_operand" "r")))]
469+ "TARGET_IDIV"
470+ "sdiv%?\t%0, %1, %2"
471+ [(set_attr "predicable" "yes")
472+ (set_attr "insn" "sdiv")]
473+)
474+
475+(define_insn "udivsi3"
476+ [(set (match_operand:SI 0 "s_register_operand" "=r")
477+ (udiv:SI (match_operand:SI 1 "s_register_operand" "r")
478+ (match_operand:SI 2 "s_register_operand" "r")))]
479+ "TARGET_IDIV"
480+ "udiv%?\t%0, %1, %2"
481+ [(set_attr "predicable" "yes")
482+ (set_attr "insn" "udiv")]
483+)
484+
485
486 ;; Unary arithmetic insns
487
488
489=== modified file 'gcc/config/arm/thumb2.md'
490--- old/gcc/config/arm/thumb2.md 2011-05-11 07:15:47 +0000
491+++ new/gcc/config/arm/thumb2.md 2011-06-14 14:37:30 +0000
492@@ -779,26 +779,6 @@
493 (set_attr "length" "2")]
494 )
495
496-(define_insn "divsi3"
497- [(set (match_operand:SI 0 "s_register_operand" "=r")
498- (div:SI (match_operand:SI 1 "s_register_operand" "r")
499- (match_operand:SI 2 "s_register_operand" "r")))]
500- "TARGET_THUMB2 && arm_arch_hwdiv"
501- "sdiv%?\t%0, %1, %2"
502- [(set_attr "predicable" "yes")
503- (set_attr "insn" "sdiv")]
504-)
505-
506-(define_insn "udivsi3"
507- [(set (match_operand:SI 0 "s_register_operand" "=r")
508- (udiv:SI (match_operand:SI 1 "s_register_operand" "r")
509- (match_operand:SI 2 "s_register_operand" "r")))]
510- "TARGET_THUMB2 && arm_arch_hwdiv"
511- "udiv%?\t%0, %1, %2"
512- [(set_attr "predicable" "yes")
513- (set_attr "insn" "udiv")]
514-)
515-
516 (define_insn "*thumb2_subsi_short"
517 [(set (match_operand:SI 0 "low_register_operand" "=l")
518 (minus:SI (match_operand:SI 1 "low_register_operand" "l")
519
520=== modified file 'gcc/doc/invoke.texi'
521--- old/gcc/doc/invoke.texi 2011-05-11 07:15:47 +0000
522+++ new/gcc/doc/invoke.texi 2011-06-14 14:37:30 +0000
523@@ -10208,7 +10208,8 @@
524 @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
525 @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
526 @samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a15},
527-@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3},
528+@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
529+@samp{cortex-m4}, @samp{cortex-m3},
530 @samp{cortex-m1},
531 @samp{cortex-m0},
532 @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
533
534=== modified file 'gcc/dojump.c'
535--- old/gcc/dojump.c 2010-05-19 19:09:57 +0000
536+++ new/gcc/dojump.c 2011-06-14 14:53:07 +0000
537@@ -36,6 +36,7 @@
538 #include "ggc.h"
539 #include "basic-block.h"
540 #include "output.h"
541+#include "tm_p.h"
542
543 static bool prefer_and_bit_test (enum machine_mode, int);
544 static void do_jump_by_parts_greater (tree, tree, int, rtx, rtx, int);
545
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106762.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106762.patch
deleted file mode 100644
index bbf9819ec..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106762.patch
+++ /dev/null
@@ -1,1355 +0,0 @@
12011-06-28 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from FSF:
4
5 2011-06-07 Ira Rosen <ira.rosen@linaro.org>
6
7 gcc/
8 * tree-vectorizer.h (vect_recog_func_ptr): Make last argument to be
9 a pointer.
10 * tree-vect-patterns.c (vect_recog_widen_sum_pattern,
11 vect_recog_widen_mult_pattern, vect_recog_dot_prod_pattern,
12 vect_recog_pow_pattern): Likewise.
13 (vect_pattern_recog_1): Remove declaration.
14 (widened_name_p): Remove declaration. Add new argument to specify
15 whether to check that both types are either signed or unsigned.
16 (vect_recog_widen_mult_pattern): Update documentation. Handle
17 unsigned patterns and multiplication by constants.
18 (vect_pattern_recog_1): Update vect_recog_func references. Use
19 statement information from the statement returned from pattern
20 detection functions.
21 (vect_pattern_recog): Update vect_recog_func reference.
22 * tree-vect-stmts.c (vectorizable_type_promotion): For widening
23 multiplication by a constant use the type of the other operand.
24
25 gcc/testsuite
26 * lib/target-supports.exp
27 (check_effective_target_vect_widen_mult_qi_to_hi):
28 Add NEON as supporting target.
29 (check_effective_target_vect_widen_mult_hi_to_si): Likewise.
30 (check_effective_target_vect_widen_mult_qi_to_hi_pattern): New.
31 (check_effective_target_vect_widen_mult_hi_to_si_pattern): New.
32 * gcc.dg/vect/vect-widen-mult-u8.c: Expect to be vectorized
33 using widening multiplication on targets that support it.
34 * gcc.dg/vect/vect-widen-mult-u16.c: Likewise.
35 * gcc.dg/vect/vect-widen-mult-const-s16.c: New test.
36 * gcc.dg/vect/vect-widen-mult-const-u16.c: New test.
37
38 and
39
40 2011-06-15 Ira Rosen <ira.rosen@linaro.org>
41
42 gcc/
43 * tree-vect-loop-manip.c (remove_dead_stmts_from_loop): Remove.
44 (slpeel_tree_peel_loop_to_edge): Don't call
45 remove_dead_stmts_from_loop.
46 * tree-vect-loop.c (vect_determine_vectorization_factor): Don't
47 remove irrelevant pattern statements. For irrelevant statements
48 check if it is the last statement of a detected pattern, use
49 corresponding pattern statement instead.
50 (destroy_loop_vec_info): No need to remove pattern statements,
51 only free stmt_vec_info.
52 (vect_transform_loop): For irrelevant statements check if it is
53 the last statement of a detected pattern, use corresponding
54 pattern statement instead.
55 * tree-vect-patterns.c (vect_pattern_recog_1): Don't insert
56 pattern statements. Set basic block for the new statement.
57 (vect_pattern_recog): Update documentation.
58 * tree-vect-stmts.c (vect_mark_stmts_to_be_vectorized): Scan
59 operands of pattern statements.
60 (vectorizable_call): Fix printing. In case of a pattern statement
61 use the lhs of the original statement when creating a dummy
62 statement to replace the original call.
63 (vect_analyze_stmt): For irrelevant statements check if it is
64 the last statement of a detected pattern, use corresponding
65 pattern statement instead.
66 * tree-vect-slp.c (vect_schedule_slp_instance): For pattern
67 statements use gsi of the original statement.
68
69 and
70 2011-06-21 Ira Rosen <ira.rosen@linaro.org>
71
72 PR tree-optimization/49478
73 gcc/
74
75 * tree-vect-loop.c (vectorizable_reduction): Handle DOT_PROD_EXPR
76 with constant operand.
77
78=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c'
79--- old/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c 1970-01-01 00:00:00 +0000
80+++ new/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-s16.c 2011-06-19 10:59:13 +0000
81@@ -0,0 +1,60 @@
82+/* { dg-require-effective-target vect_int } */
83+
84+#include "tree-vect.h"
85+#include <stdlib.h>
86+
87+#define N 32
88+
89+__attribute__ ((noinline)) void
90+foo (int *__restrict a,
91+ short *__restrict b,
92+ int n)
93+{
94+ int i;
95+
96+ for (i = 0; i < n; i++)
97+ a[i] = b[i] * 2333;
98+
99+ for (i = 0; i < n; i++)
100+ if (a[i] != b[i] * 2333)
101+ abort ();
102+}
103+
104+__attribute__ ((noinline)) void
105+bar (int *__restrict a,
106+ short *__restrict b,
107+ int n)
108+{
109+ int i;
110+
111+ for (i = 0; i < n; i++)
112+ a[i] = b[i] * (short) 2333;
113+
114+ for (i = 0; i < n; i++)
115+ if (a[i] != b[i] * (short) 2333)
116+ abort ();
117+}
118+
119+int main (void)
120+{
121+ int i;
122+ int a[N];
123+ short b[N];
124+
125+ for (i = 0; i < N; i++)
126+ {
127+ a[i] = 0;
128+ b[i] = i;
129+ __asm__ volatile ("");
130+ }
131+
132+ foo (a, b, N);
133+ bar (a, b, N);
134+ return 0;
135+}
136+
137+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_widen_mult_hi_to_si } } } */
138+/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
139+/* { dg-final { scan-tree-dump-times "pattern recognized" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
140+/* { dg-final { cleanup-tree-dump "vect" } } */
141+
142
143=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c'
144--- old/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c 1970-01-01 00:00:00 +0000
145+++ new/gcc/testsuite/gcc.dg/vect/vect-widen-mult-const-u16.c 2011-06-19 10:59:13 +0000
146@@ -0,0 +1,77 @@
147+/* { dg-require-effective-target vect_int } */
148+
149+#include "tree-vect.h"
150+#include <stdlib.h>
151+
152+#define N 32
153+
154+__attribute__ ((noinline)) void
155+foo (unsigned int *__restrict a,
156+ unsigned short *__restrict b,
157+ int n)
158+{
159+ int i;
160+
161+ for (i = 0; i < n; i++)
162+ a[i] = b[i] * 2333;
163+
164+ for (i = 0; i < n; i++)
165+ if (a[i] != b[i] * 2333)
166+ abort ();
167+}
168+
169+__attribute__ ((noinline)) void
170+bar (unsigned int *__restrict a,
171+ unsigned short *__restrict b,
172+ int n)
173+{
174+ int i;
175+
176+ for (i = 0; i < n; i++)
177+ a[i] = (unsigned short) 2333 * b[i];
178+
179+ for (i = 0; i < n; i++)
180+ if (a[i] != b[i] * (unsigned short) 2333)
181+ abort ();
182+}
183+
184+__attribute__ ((noinline)) void
185+baz (unsigned int *__restrict a,
186+ unsigned short *__restrict b,
187+ int n)
188+{
189+ int i;
190+
191+ for (i = 0; i < n; i++)
192+ a[i] = b[i] * 233333333;
193+
194+ for (i = 0; i < n; i++)
195+ if (a[i] != b[i] * 233333333)
196+ abort ();
197+}
198+
199+
200+int main (void)
201+{
202+ int i;
203+ unsigned int a[N];
204+ unsigned short b[N];
205+
206+ for (i = 0; i < N; i++)
207+ {
208+ a[i] = 0;
209+ b[i] = i;
210+ __asm__ volatile ("");
211+ }
212+
213+ foo (a, b, N);
214+ bar (a, b, N);
215+ baz (a, b, N);
216+ return 0;
217+}
218+
219+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 3 "vect" { target vect_widen_mult_hi_to_si } } } */
220+/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
221+/* { dg-final { scan-tree-dump-times "pattern recognized" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
222+/* { dg-final { cleanup-tree-dump "vect" } } */
223+
224
225=== modified file 'gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c'
226--- old/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c 2010-05-27 12:23:45 +0000
227+++ new/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u16.c 2011-06-19 10:59:13 +0000
228@@ -9,13 +9,11 @@
229 unsigned short Y[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
230 unsigned int result[N];
231
232-/* short->int widening-mult */
233+/* unsigned short->unsigned int widening-mult. */
234 __attribute__ ((noinline)) int
235 foo1(int len) {
236 int i;
237
238- /* Not vectorized because X[i] and Y[i] are casted to 'int'
239- so the widening multiplication pattern is not recognized. */
240 for (i=0; i<len; i++) {
241 result[i] = (unsigned int)(X[i] * Y[i]);
242 }
243@@ -43,8 +41,8 @@
244 return 0;
245 }
246
247-/*The induction loop is vectorized */
248-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail *-*-* } } } */
249-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_pack_trunc } } } */
250+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_widen_mult_hi_to_si || vect_unpack } } } } */
251+/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 1 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
252+/* { dg-final { scan-tree-dump-times "pattern recognized" 1 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
253 /* { dg-final { cleanup-tree-dump "vect" } } */
254
255
256=== modified file 'gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c'
257--- old/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c 2009-05-08 12:39:01 +0000
258+++ new/gcc/testsuite/gcc.dg/vect/vect-widen-mult-u8.c 2011-06-19 10:59:13 +0000
259@@ -9,7 +9,7 @@
260 unsigned char Y[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
261 unsigned short result[N];
262
263-/* char->short widening-mult */
264+/* unsigned char-> unsigned short widening-mult. */
265 __attribute__ ((noinline)) int
266 foo1(int len) {
267 int i;
268@@ -28,8 +28,7 @@
269 for (i=0; i<N; i++) {
270 X[i] = i;
271 Y[i] = 64-i;
272- if (i%4 == 0)
273- X[i] = 5;
274+ __asm__ volatile ("");
275 }
276
277 foo1 (N);
278@@ -43,5 +42,7 @@
279 }
280
281 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_widen_mult_qi_to_hi || vect_unpack } } } } */
282+/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 1 "vect" { target vect_widen_mult_qi_to_hi_pattern } } } */
283+/* { dg-final { scan-tree-dump-times "pattern recognized" 1 "vect" { target vect_widen_mult_qi_to_hi_pattern } } } */
284 /* { dg-final { cleanup-tree-dump "vect" } } */
285
286
287=== modified file 'gcc/testsuite/lib/target-supports.exp'
288--- old/gcc/testsuite/lib/target-supports.exp 2011-06-02 12:12:00 +0000
289+++ new/gcc/testsuite/lib/target-supports.exp 2011-06-19 10:59:13 +0000
290@@ -2663,7 +2663,8 @@
291 } else {
292 set et_vect_widen_mult_qi_to_hi_saved 0
293 }
294- if { [istarget powerpc*-*-*] } {
295+ if { [istarget powerpc*-*-*]
296+ || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
297 set et_vect_widen_mult_qi_to_hi_saved 1
298 }
299 }
300@@ -2696,7 +2697,8 @@
301 || [istarget spu-*-*]
302 || [istarget ia64-*-*]
303 || [istarget i?86-*-*]
304- || [istarget x86_64-*-*] } {
305+ || [istarget x86_64-*-*]
306+ || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
307 set et_vect_widen_mult_hi_to_si_saved 1
308 }
309 }
310@@ -2705,6 +2707,52 @@
311 }
312
313 # Return 1 if the target plus current options supports a vector
314+# widening multiplication of *char* args into *short* result, 0 otherwise.
315+#
316+# This won't change for different subtargets so cache the result.
317+
318+proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } {
319+ global et_vect_widen_mult_qi_to_hi_pattern
320+
321+ if [info exists et_vect_widen_mult_qi_to_hi_pattern_saved] {
322+ verbose "check_effective_target_vect_widen_mult_qi_to_hi_pattern: using cached result" 2
323+ } else {
324+ set et_vect_widen_mult_qi_to_hi_pattern_saved 0
325+ if { [istarget powerpc*-*-*]
326+ || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
327+ set et_vect_widen_mult_qi_to_hi_pattern_saved 1
328+ }
329+ }
330+ verbose "check_effective_target_vect_widen_mult_qi_to_hi_pattern: returning $et_vect_widen_mult_qi_to_hi_pattern_saved" 2
331+ return $et_vect_widen_mult_qi_to_hi_pattern_saved
332+}
333+
334+# Return 1 if the target plus current options supports a vector
335+# widening multiplication of *short* args into *int* result, 0 otherwise.
336+#
337+# This won't change for different subtargets so cache the result.
338+
339+proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } {
340+ global et_vect_widen_mult_hi_to_si_pattern
341+
342+ if [info exists et_vect_widen_mult_hi_to_si_pattern_saved] {
343+ verbose "check_effective_target_vect_widen_mult_hi_to_si_pattern: using cached result" 2
344+ } else {
345+ set et_vect_widen_mult_hi_to_si_pattern_saved 0
346+ if { [istarget powerpc*-*-*]
347+ || [istarget spu-*-*]
348+ || [istarget ia64-*-*]
349+ || [istarget i?86-*-*]
350+ || [istarget x86_64-*-*]
351+ || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) } {
352+ set et_vect_widen_mult_hi_to_si_pattern_saved 1
353+ }
354+ }
355+ verbose "check_effective_target_vect_widen_mult_hi_to_si_pattern: returning $et_vect_widen_mult_hi_to_si_pattern_saved" 2
356+ return $et_vect_widen_mult_hi_to_si_pattern_saved
357+}
358+
359+# Return 1 if the target plus current options supports a vector
360 # dot-product of signed chars, 0 otherwise.
361 #
362 # This won't change for different subtargets so cache the result.
363
364=== modified file 'gcc/tree-vect-loop-manip.c'
365--- old/gcc/tree-vect-loop-manip.c 2011-05-18 13:24:05 +0000
366+++ new/gcc/tree-vect-loop-manip.c 2011-06-19 10:59:13 +0000
367@@ -1105,35 +1105,6 @@
368 first_niters = PHI_RESULT (newphi);
369 }
370
371-
372-/* Remove dead assignments from loop NEW_LOOP. */
373-
374-static void
375-remove_dead_stmts_from_loop (struct loop *new_loop)
376-{
377- basic_block *bbs = get_loop_body (new_loop);
378- unsigned i;
379- for (i = 0; i < new_loop->num_nodes; ++i)
380- {
381- gimple_stmt_iterator gsi;
382- for (gsi = gsi_start_bb (bbs[i]); !gsi_end_p (gsi);)
383- {
384- gimple stmt = gsi_stmt (gsi);
385- if (is_gimple_assign (stmt)
386- && TREE_CODE (gimple_assign_lhs (stmt)) == SSA_NAME
387- && has_zero_uses (gimple_assign_lhs (stmt)))
388- {
389- gsi_remove (&gsi, true);
390- release_defs (stmt);
391- }
392- else
393- gsi_next (&gsi);
394- }
395- }
396- free (bbs);
397-}
398-
399-
400 /* Function slpeel_tree_peel_loop_to_edge.
401
402 Peel the first (last) iterations of LOOP into a new prolog (epilog) loop
403@@ -1445,13 +1416,6 @@
404 BITMAP_FREE (definitions);
405 delete_update_ssa ();
406
407- /* Remove all pattern statements from the loop copy. They will confuse
408- the expander if DCE is disabled.
409- ??? The pattern recognizer should be split into an analysis and
410- a transformation phase that is then run only on the loop that is
411- going to be transformed. */
412- remove_dead_stmts_from_loop (new_loop);
413-
414 adjust_vec_debug_stmts ();
415
416 return new_loop;
417
418=== modified file 'gcc/tree-vect-loop.c'
419--- old/gcc/tree-vect-loop.c 2011-03-01 13:18:25 +0000
420+++ new/gcc/tree-vect-loop.c 2011-06-22 06:21:13 +0000
421@@ -244,7 +244,7 @@
422 for (si = gsi_start_bb (bb); !gsi_end_p (si); gsi_next (&si))
423 {
424 tree vf_vectype;
425- gimple stmt = gsi_stmt (si);
426+ gimple stmt = gsi_stmt (si), pattern_stmt;
427 stmt_info = vinfo_for_stmt (stmt);
428
429 if (vect_print_dump_info (REPORT_DETAILS))
430@@ -259,9 +259,25 @@
431 if (!STMT_VINFO_RELEVANT_P (stmt_info)
432 && !STMT_VINFO_LIVE_P (stmt_info))
433 {
434- if (vect_print_dump_info (REPORT_DETAILS))
435- fprintf (vect_dump, "skip.");
436- continue;
437+ if (STMT_VINFO_IN_PATTERN_P (stmt_info)
438+ && (pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info))
439+ && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
440+ || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
441+ {
442+ stmt = pattern_stmt;
443+ stmt_info = vinfo_for_stmt (pattern_stmt);
444+ if (vect_print_dump_info (REPORT_DETAILS))
445+ {
446+ fprintf (vect_dump, "==> examining pattern statement: ");
447+ print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
448+ }
449+ }
450+ else
451+ {
452+ if (vect_print_dump_info (REPORT_DETAILS))
453+ fprintf (vect_dump, "skip.");
454+ continue;
455+ }
456 }
457
458 if (gimple_get_lhs (stmt) == NULL_TREE)
459@@ -816,25 +832,17 @@
460
461 if (stmt_info)
462 {
463- /* Check if this is a "pattern stmt" (introduced by the
464- vectorizer during the pattern recognition pass). */
465- bool remove_stmt_p = false;
466- gimple orig_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
467- if (orig_stmt)
468- {
469- stmt_vec_info orig_stmt_info = vinfo_for_stmt (orig_stmt);
470- if (orig_stmt_info
471- && STMT_VINFO_IN_PATTERN_P (orig_stmt_info))
472- remove_stmt_p = true;
473- }
474+ /* Check if this statement has a related "pattern stmt"
475+ (introduced by the vectorizer during the pattern recognition
476+ pass). Free pattern's stmt_vec_info. */
477+ if (STMT_VINFO_IN_PATTERN_P (stmt_info)
478+ && vinfo_for_stmt (STMT_VINFO_RELATED_STMT (stmt_info)))
479+ free_stmt_vec_info (STMT_VINFO_RELATED_STMT (stmt_info));
480
481 /* Free stmt_vec_info. */
482 free_stmt_vec_info (stmt);
483+ }
484
485- /* Remove dead "pattern stmts". */
486- if (remove_stmt_p)
487- gsi_remove (&si, true);
488- }
489 gsi_next (&si);
490 }
491 }
492@@ -4262,6 +4270,25 @@
493 return false;
494 }
495
496+ /* In case of widenning multiplication by a constant, we update the type
497+ of the constant to be the type of the other operand. We check that the
498+ constant fits the type in the pattern recognition pass. */
499+ if (code == DOT_PROD_EXPR
500+ && !types_compatible_p (TREE_TYPE (ops[0]), TREE_TYPE (ops[1])))
501+ {
502+ if (TREE_CODE (ops[0]) == INTEGER_CST)
503+ ops[0] = fold_convert (TREE_TYPE (ops[1]), ops[0]);
504+ else if (TREE_CODE (ops[1]) == INTEGER_CST)
505+ ops[1] = fold_convert (TREE_TYPE (ops[0]), ops[1]);
506+ else
507+ {
508+ if (vect_print_dump_info (REPORT_DETAILS))
509+ fprintf (vect_dump, "invalid types in dot-prod");
510+
511+ return false;
512+ }
513+ }
514+
515 if (!vec_stmt) /* transformation not required. */
516 {
517 STMT_VINFO_TYPE (stmt_info) = reduc_vec_info_type;
518@@ -4796,7 +4823,7 @@
519
520 for (si = gsi_start_bb (bb); !gsi_end_p (si);)
521 {
522- gimple stmt = gsi_stmt (si);
523+ gimple stmt = gsi_stmt (si), pattern_stmt;
524 bool is_store;
525
526 if (vect_print_dump_info (REPORT_DETAILS))
527@@ -4821,14 +4848,25 @@
528
529 if (!STMT_VINFO_RELEVANT_P (stmt_info)
530 && !STMT_VINFO_LIVE_P (stmt_info))
531- {
532- gsi_next (&si);
533- continue;
534+ {
535+ if (STMT_VINFO_IN_PATTERN_P (stmt_info)
536+ && (pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info))
537+ && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
538+ || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
539+ {
540+ stmt = pattern_stmt;
541+ stmt_info = vinfo_for_stmt (stmt);
542+ }
543+ else
544+ {
545+ gsi_next (&si);
546+ continue;
547+ }
548 }
549
550 gcc_assert (STMT_VINFO_VECTYPE (stmt_info));
551- nunits =
552- (unsigned int) TYPE_VECTOR_SUBPARTS (STMT_VINFO_VECTYPE (stmt_info));
553+ nunits = (unsigned int) TYPE_VECTOR_SUBPARTS (
554+ STMT_VINFO_VECTYPE (stmt_info));
555 if (!STMT_SLP_TYPE (stmt_info)
556 && nunits != (unsigned int) vectorization_factor
557 && vect_print_dump_info (REPORT_DETAILS))
558
559=== modified file 'gcc/tree-vect-patterns.c'
560--- old/gcc/tree-vect-patterns.c 2010-12-02 11:47:12 +0000
561+++ new/gcc/tree-vect-patterns.c 2011-06-22 12:10:44 +0000
562@@ -38,16 +38,11 @@
563 #include "recog.h"
564 #include "diagnostic-core.h"
565
566-/* Function prototypes */
567-static void vect_pattern_recog_1
568- (gimple (* ) (gimple, tree *, tree *), gimple_stmt_iterator);
569-static bool widened_name_p (tree, gimple, tree *, gimple *);
570-
571 /* Pattern recognition functions */
572-static gimple vect_recog_widen_sum_pattern (gimple, tree *, tree *);
573-static gimple vect_recog_widen_mult_pattern (gimple, tree *, tree *);
574-static gimple vect_recog_dot_prod_pattern (gimple, tree *, tree *);
575-static gimple vect_recog_pow_pattern (gimple, tree *, tree *);
576+static gimple vect_recog_widen_sum_pattern (gimple *, tree *, tree *);
577+static gimple vect_recog_widen_mult_pattern (gimple *, tree *, tree *);
578+static gimple vect_recog_dot_prod_pattern (gimple *, tree *, tree *);
579+static gimple vect_recog_pow_pattern (gimple *, tree *, tree *);
580 static vect_recog_func_ptr vect_vect_recog_func_ptrs[NUM_PATTERNS] = {
581 vect_recog_widen_mult_pattern,
582 vect_recog_widen_sum_pattern,
583@@ -61,10 +56,12 @@
584 is a result of a type-promotion, such that:
585 DEF_STMT: NAME = NOP (name0)
586 where the type of name0 (HALF_TYPE) is smaller than the type of NAME.
587-*/
588+ If CHECK_SIGN is TRUE, check that either both types are signed or both are
589+ unsigned. */
590
591 static bool
592-widened_name_p (tree name, gimple use_stmt, tree *half_type, gimple *def_stmt)
593+widened_name_p (tree name, gimple use_stmt, tree *half_type, gimple *def_stmt,
594+ bool check_sign)
595 {
596 tree dummy;
597 gimple dummy_gimple;
598@@ -98,7 +95,7 @@
599
600 *half_type = TREE_TYPE (oprnd0);
601 if (!INTEGRAL_TYPE_P (type) || !INTEGRAL_TYPE_P (*half_type)
602- || (TYPE_UNSIGNED (type) != TYPE_UNSIGNED (*half_type))
603+ || ((TYPE_UNSIGNED (type) != TYPE_UNSIGNED (*half_type)) && check_sign)
604 || (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 2)))
605 return false;
606
607@@ -168,12 +165,12 @@
608 inner-loop nested in an outer-loop that us being vectorized). */
609
610 static gimple
611-vect_recog_dot_prod_pattern (gimple last_stmt, tree *type_in, tree *type_out)
612+vect_recog_dot_prod_pattern (gimple *last_stmt, tree *type_in, tree *type_out)
613 {
614 gimple stmt;
615 tree oprnd0, oprnd1;
616 tree oprnd00, oprnd01;
617- stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt);
618+ stmt_vec_info stmt_vinfo = vinfo_for_stmt (*last_stmt);
619 tree type, half_type;
620 gimple pattern_stmt;
621 tree prod_type;
622@@ -181,10 +178,10 @@
623 struct loop *loop = LOOP_VINFO_LOOP (loop_info);
624 tree var, rhs;
625
626- if (!is_gimple_assign (last_stmt))
627+ if (!is_gimple_assign (*last_stmt))
628 return NULL;
629
630- type = gimple_expr_type (last_stmt);
631+ type = gimple_expr_type (*last_stmt);
632
633 /* Look for the following pattern
634 DX = (TYPE1) X;
635@@ -210,7 +207,7 @@
636 /* Starting from LAST_STMT, follow the defs of its uses in search
637 of the above pattern. */
638
639- if (gimple_assign_rhs_code (last_stmt) != PLUS_EXPR)
640+ if (gimple_assign_rhs_code (*last_stmt) != PLUS_EXPR)
641 return NULL;
642
643 if (STMT_VINFO_IN_PATTERN_P (stmt_vinfo))
644@@ -231,14 +228,14 @@
645
646 if (STMT_VINFO_DEF_TYPE (stmt_vinfo) != vect_reduction_def)
647 return NULL;
648- oprnd0 = gimple_assign_rhs1 (last_stmt);
649- oprnd1 = gimple_assign_rhs2 (last_stmt);
650+ oprnd0 = gimple_assign_rhs1 (*last_stmt);
651+ oprnd1 = gimple_assign_rhs2 (*last_stmt);
652 if (!types_compatible_p (TREE_TYPE (oprnd0), type)
653 || !types_compatible_p (TREE_TYPE (oprnd1), type))
654 return NULL;
655- stmt = last_stmt;
656+ stmt = *last_stmt;
657
658- if (widened_name_p (oprnd0, stmt, &half_type, &def_stmt))
659+ if (widened_name_p (oprnd0, stmt, &half_type, &def_stmt, true))
660 {
661 stmt = def_stmt;
662 oprnd0 = gimple_assign_rhs1 (stmt);
663@@ -293,10 +290,10 @@
664 if (!types_compatible_p (TREE_TYPE (oprnd0), prod_type)
665 || !types_compatible_p (TREE_TYPE (oprnd1), prod_type))
666 return NULL;
667- if (!widened_name_p (oprnd0, stmt, &half_type0, &def_stmt))
668+ if (!widened_name_p (oprnd0, stmt, &half_type0, &def_stmt, true))
669 return NULL;
670 oprnd00 = gimple_assign_rhs1 (def_stmt);
671- if (!widened_name_p (oprnd1, stmt, &half_type1, &def_stmt))
672+ if (!widened_name_p (oprnd1, stmt, &half_type1, &def_stmt, true))
673 return NULL;
674 oprnd01 = gimple_assign_rhs1 (def_stmt);
675 if (!types_compatible_p (half_type0, half_type1))
676@@ -322,7 +319,7 @@
677
678 /* We don't allow changing the order of the computation in the inner-loop
679 when doing outer-loop vectorization. */
680- gcc_assert (!nested_in_vect_loop_p (loop, last_stmt));
681+ gcc_assert (!nested_in_vect_loop_p (loop, *last_stmt));
682
683 return pattern_stmt;
684 }
685@@ -342,24 +339,47 @@
686
687 where type 'TYPE' is at least double the size of type 'type'.
688
689- Input:
690-
691- * LAST_STMT: A stmt from which the pattern search begins. In the example,
692- when this function is called with S5, the pattern {S3,S4,S5} is be detected.
693-
694- Output:
695-
696- * TYPE_IN: The type of the input arguments to the pattern.
697-
698- * TYPE_OUT: The type of the output of this pattern.
699-
700- * Return value: A new stmt that will be used to replace the sequence of
701- stmts that constitute the pattern. In this case it will be:
702- WIDEN_MULT <a_t, b_t>
703-*/
704+ Also detect unsgigned cases:
705+
706+ unsigned type a_t, b_t;
707+ unsigned TYPE u_prod_T;
708+ TYPE a_T, b_T, prod_T;
709+
710+ S1 a_t = ;
711+ S2 b_t = ;
712+ S3 a_T = (TYPE) a_t;
713+ S4 b_T = (TYPE) b_t;
714+ S5 prod_T = a_T * b_T;
715+ S6 u_prod_T = (unsigned TYPE) prod_T;
716+
717+ and multiplication by constants:
718+
719+ type a_t;
720+ TYPE a_T, prod_T;
721+
722+ S1 a_t = ;
723+ S3 a_T = (TYPE) a_t;
724+ S5 prod_T = a_T * CONST;
725+
726+ Input:
727+
728+ * LAST_STMT: A stmt from which the pattern search begins. In the example,
729+ when this function is called with S5, the pattern {S3,S4,S5,(S6)} is
730+ detected.
731+
732+ Output:
733+
734+ * TYPE_IN: The type of the input arguments to the pattern.
735+
736+ * TYPE_OUT: The type of the output of this pattern.
737+
738+ * Return value: A new stmt that will be used to replace the sequence of
739+ stmts that constitute the pattern. In this case it will be:
740+ WIDEN_MULT <a_t, b_t>
741+ */
742
743 static gimple
744-vect_recog_widen_mult_pattern (gimple last_stmt,
745+vect_recog_widen_mult_pattern (gimple *last_stmt,
746 tree *type_in,
747 tree *type_out)
748 {
749@@ -367,39 +387,112 @@
750 tree oprnd0, oprnd1;
751 tree type, half_type0, half_type1;
752 gimple pattern_stmt;
753- tree vectype, vectype_out;
754+ tree vectype, vectype_out = NULL_TREE;
755 tree dummy;
756 tree var;
757 enum tree_code dummy_code;
758 int dummy_int;
759 VEC (tree, heap) *dummy_vec;
760+ bool op0_ok, op1_ok;
761
762- if (!is_gimple_assign (last_stmt))
763+ if (!is_gimple_assign (*last_stmt))
764 return NULL;
765
766- type = gimple_expr_type (last_stmt);
767+ type = gimple_expr_type (*last_stmt);
768
769 /* Starting from LAST_STMT, follow the defs of its uses in search
770 of the above pattern. */
771
772- if (gimple_assign_rhs_code (last_stmt) != MULT_EXPR)
773+ if (gimple_assign_rhs_code (*last_stmt) != MULT_EXPR)
774 return NULL;
775
776- oprnd0 = gimple_assign_rhs1 (last_stmt);
777- oprnd1 = gimple_assign_rhs2 (last_stmt);
778+ oprnd0 = gimple_assign_rhs1 (*last_stmt);
779+ oprnd1 = gimple_assign_rhs2 (*last_stmt);
780 if (!types_compatible_p (TREE_TYPE (oprnd0), type)
781 || !types_compatible_p (TREE_TYPE (oprnd1), type))
782 return NULL;
783
784- /* Check argument 0 */
785- if (!widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0))
786- return NULL;
787- oprnd0 = gimple_assign_rhs1 (def_stmt0);
788-
789- /* Check argument 1 */
790- if (!widened_name_p (oprnd1, last_stmt, &half_type1, &def_stmt1))
791- return NULL;
792- oprnd1 = gimple_assign_rhs1 (def_stmt1);
793+ /* Check argument 0. */
794+ op0_ok = widened_name_p (oprnd0, *last_stmt, &half_type0, &def_stmt0, false);
795+ /* Check argument 1. */
796+ op1_ok = widened_name_p (oprnd1, *last_stmt, &half_type1, &def_stmt1, false);
797+
798+ /* In case of multiplication by a constant one of the operands may not match
799+ the pattern, but not both. */
800+ if (!op0_ok && !op1_ok)
801+ return NULL;
802+
803+ if (op0_ok && op1_ok)
804+ {
805+ oprnd0 = gimple_assign_rhs1 (def_stmt0);
806+ oprnd1 = gimple_assign_rhs1 (def_stmt1);
807+ }
808+ else if (!op0_ok)
809+ {
810+ if (CONSTANT_CLASS_P (oprnd0)
811+ && TREE_CODE (half_type1) == INTEGER_TYPE
812+ && tree_int_cst_lt (oprnd0, TYPE_MAXVAL (half_type1))
813+ && tree_int_cst_lt (TYPE_MINVAL (half_type1), oprnd0))
814+ {
815+ /* OPRND0 is a constant of HALF_TYPE1. */
816+ half_type0 = half_type1;
817+ oprnd1 = gimple_assign_rhs1 (def_stmt1);
818+ }
819+ else
820+ return NULL;
821+ }
822+ else if (!op1_ok)
823+ {
824+ if (CONSTANT_CLASS_P (oprnd1)
825+ && TREE_CODE (half_type0) == INTEGER_TYPE
826+ && tree_int_cst_lt (oprnd1, TYPE_MAXVAL (half_type0))
827+ && tree_int_cst_lt (TYPE_MINVAL (half_type0), oprnd1))
828+ {
829+ /* OPRND1 is a constant of HALF_TYPE0. */
830+ half_type1 = half_type0;
831+ oprnd0 = gimple_assign_rhs1 (def_stmt0);
832+ }
833+ else
834+ return NULL;
835+ }
836+
837+ /* Handle unsigned case. Look for
838+ S6 u_prod_T = (unsigned TYPE) prod_T;
839+ Use unsigned TYPE as the type for WIDEN_MULT_EXPR. */
840+ if (TYPE_UNSIGNED (type) != TYPE_UNSIGNED (half_type0))
841+ {
842+ tree lhs = gimple_assign_lhs (*last_stmt), use_lhs;
843+ imm_use_iterator imm_iter;
844+ use_operand_p use_p;
845+ int nuses = 0;
846+ gimple use_stmt = NULL;
847+ tree use_type;
848+
849+ if (TYPE_UNSIGNED (type) == TYPE_UNSIGNED (half_type1))
850+ return NULL;
851+
852+ FOR_EACH_IMM_USE_FAST (use_p, imm_iter, lhs)
853+ {
854+ if (is_gimple_debug (USE_STMT (use_p)))
855+ continue;
856+ use_stmt = USE_STMT (use_p);
857+ nuses++;
858+ }
859+
860+ if (nuses != 1 || !is_gimple_assign (use_stmt)
861+ || gimple_assign_rhs_code (use_stmt) != NOP_EXPR)
862+ return NULL;
863+
864+ use_lhs = gimple_assign_lhs (use_stmt);
865+ use_type = TREE_TYPE (use_lhs);
866+ if (!INTEGRAL_TYPE_P (use_type)
867+ || (TYPE_UNSIGNED (type) == TYPE_UNSIGNED (use_type))
868+ || (TYPE_PRECISION (type) != TYPE_PRECISION (use_type)))
869+ return NULL;
870+
871+ type = use_type;
872+ *last_stmt = use_stmt;
873+ }
874
875 if (!types_compatible_p (half_type0, half_type1))
876 return NULL;
877@@ -413,7 +506,7 @@
878 vectype_out = get_vectype_for_scalar_type (type);
879 if (!vectype
880 || !vectype_out
881- || !supportable_widening_operation (WIDEN_MULT_EXPR, last_stmt,
882+ || !supportable_widening_operation (WIDEN_MULT_EXPR, *last_stmt,
883 vectype_out, vectype,
884 &dummy, &dummy, &dummy_code,
885 &dummy_code, &dummy_int, &dummy_vec))
886@@ -462,16 +555,16 @@
887 */
888
889 static gimple
890-vect_recog_pow_pattern (gimple last_stmt, tree *type_in, tree *type_out)
891+vect_recog_pow_pattern (gimple *last_stmt, tree *type_in, tree *type_out)
892 {
893 tree fn, base, exp = NULL;
894 gimple stmt;
895 tree var;
896
897- if (!is_gimple_call (last_stmt) || gimple_call_lhs (last_stmt) == NULL)
898+ if (!is_gimple_call (*last_stmt) || gimple_call_lhs (*last_stmt) == NULL)
899 return NULL;
900
901- fn = gimple_call_fndecl (last_stmt);
902+ fn = gimple_call_fndecl (*last_stmt);
903 if (fn == NULL_TREE || DECL_BUILT_IN_CLASS (fn) != BUILT_IN_NORMAL)
904 return NULL;
905
906@@ -481,8 +574,8 @@
907 case BUILT_IN_POWI:
908 case BUILT_IN_POWF:
909 case BUILT_IN_POW:
910- base = gimple_call_arg (last_stmt, 0);
911- exp = gimple_call_arg (last_stmt, 1);
912+ base = gimple_call_arg (*last_stmt, 0);
913+ exp = gimple_call_arg (*last_stmt, 1);
914 if (TREE_CODE (exp) != REAL_CST
915 && TREE_CODE (exp) != INTEGER_CST)
916 return NULL;
917@@ -574,21 +667,21 @@
918 inner-loop nested in an outer-loop that us being vectorized). */
919
920 static gimple
921-vect_recog_widen_sum_pattern (gimple last_stmt, tree *type_in, tree *type_out)
922+vect_recog_widen_sum_pattern (gimple *last_stmt, tree *type_in, tree *type_out)
923 {
924 gimple stmt;
925 tree oprnd0, oprnd1;
926- stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt);
927+ stmt_vec_info stmt_vinfo = vinfo_for_stmt (*last_stmt);
928 tree type, half_type;
929 gimple pattern_stmt;
930 loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
931 struct loop *loop = LOOP_VINFO_LOOP (loop_info);
932 tree var;
933
934- if (!is_gimple_assign (last_stmt))
935+ if (!is_gimple_assign (*last_stmt))
936 return NULL;
937
938- type = gimple_expr_type (last_stmt);
939+ type = gimple_expr_type (*last_stmt);
940
941 /* Look for the following pattern
942 DX = (TYPE) X;
943@@ -600,25 +693,25 @@
944 /* Starting from LAST_STMT, follow the defs of its uses in search
945 of the above pattern. */
946
947- if (gimple_assign_rhs_code (last_stmt) != PLUS_EXPR)
948+ if (gimple_assign_rhs_code (*last_stmt) != PLUS_EXPR)
949 return NULL;
950
951 if (STMT_VINFO_DEF_TYPE (stmt_vinfo) != vect_reduction_def)
952 return NULL;
953
954- oprnd0 = gimple_assign_rhs1 (last_stmt);
955- oprnd1 = gimple_assign_rhs2 (last_stmt);
956+ oprnd0 = gimple_assign_rhs1 (*last_stmt);
957+ oprnd1 = gimple_assign_rhs2 (*last_stmt);
958 if (!types_compatible_p (TREE_TYPE (oprnd0), type)
959 || !types_compatible_p (TREE_TYPE (oprnd1), type))
960 return NULL;
961
962- /* So far so good. Since last_stmt was detected as a (summation) reduction,
963+ /* So far so good. Since *last_stmt was detected as a (summation) reduction,
964 we know that oprnd1 is the reduction variable (defined by a loop-header
965 phi), and oprnd0 is an ssa-name defined by a stmt in the loop body.
966 Left to check that oprnd0 is defined by a cast from type 'type' to type
967 'TYPE'. */
968
969- if (!widened_name_p (oprnd0, last_stmt, &half_type, &stmt))
970+ if (!widened_name_p (oprnd0, *last_stmt, &half_type, &stmt, true))
971 return NULL;
972
973 oprnd0 = gimple_assign_rhs1 (stmt);
974@@ -639,7 +732,7 @@
975
976 /* We don't allow changing the order of the computation in the inner-loop
977 when doing outer-loop vectorization. */
978- gcc_assert (!nested_in_vect_loop_p (loop, last_stmt));
979+ gcc_assert (!nested_in_vect_loop_p (loop, *last_stmt));
980
981 return pattern_stmt;
982 }
983@@ -669,23 +762,27 @@
984
985 static void
986 vect_pattern_recog_1 (
987- gimple (* vect_recog_func) (gimple, tree *, tree *),
988+ gimple (* vect_recog_func) (gimple *, tree *, tree *),
989 gimple_stmt_iterator si)
990 {
991 gimple stmt = gsi_stmt (si), pattern_stmt;
992- stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
993+ stmt_vec_info stmt_info;
994 stmt_vec_info pattern_stmt_info;
995- loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info);
996+ loop_vec_info loop_vinfo;
997 tree pattern_vectype;
998 tree type_in, type_out;
999 enum tree_code code;
1000 int i;
1001 gimple next;
1002
1003- pattern_stmt = (* vect_recog_func) (stmt, &type_in, &type_out);
1004+ pattern_stmt = (* vect_recog_func) (&stmt, &type_in, &type_out);
1005 if (!pattern_stmt)
1006 return;
1007
1008+ si = gsi_for_stmt (stmt);
1009+ stmt_info = vinfo_for_stmt (stmt);
1010+ loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info);
1011+
1012 if (VECTOR_MODE_P (TYPE_MODE (type_in)))
1013 {
1014 /* No need to check target support (already checked by the pattern
1015@@ -736,9 +833,9 @@
1016 }
1017
1018 /* Mark the stmts that are involved in the pattern. */
1019- gsi_insert_before (&si, pattern_stmt, GSI_SAME_STMT);
1020 set_vinfo_for_stmt (pattern_stmt,
1021 new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
1022+ gimple_set_bb (pattern_stmt, gimple_bb (stmt));
1023 pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
1024
1025 STMT_VINFO_RELATED_STMT (pattern_stmt_info) = stmt;
1026@@ -761,8 +858,8 @@
1027 LOOP_VINFO - a struct_loop_info of a loop in which we want to look for
1028 computation idioms.
1029
1030- Output - for each computation idiom that is detected we insert a new stmt
1031- that provides the same functionality and that can be vectorized. We
1032+ Output - for each computation idiom that is detected we create a new stmt
1033+ that provides the same functionality and that can be vectorized. We
1034 also record some information in the struct_stmt_info of the relevant
1035 stmts, as explained below:
1036
1037@@ -777,52 +874,48 @@
1038 S5: ... = ..use(a_0).. - - -
1039
1040 Say the sequence {S1,S2,S3,S4} was detected as a pattern that can be
1041- represented by a single stmt. We then:
1042- - create a new stmt S6 that will replace the pattern.
1043- - insert the new stmt S6 before the last stmt in the pattern
1044+ represented by a single stmt. We then:
1045+ - create a new stmt S6 equivalent to the pattern (the stmt is not
1046+ inserted into the code)
1047 - fill in the STMT_VINFO fields as follows:
1048
1049 in_pattern_p related_stmt vec_stmt
1050 S1: a_i = .... - - -
1051 S2: a_2 = ..use(a_i).. - - -
1052 S3: a_1 = ..use(a_2).. - - -
1053- > S6: a_new = .... - S4 -
1054 S4: a_0 = ..use(a_1).. true S6 -
1055+ '---> S6: a_new = .... - S4 -
1056 S5: ... = ..use(a_0).. - - -
1057
1058 (the last stmt in the pattern (S4) and the new pattern stmt (S6) point
1059- to each other through the RELATED_STMT field).
1060+ to each other through the RELATED_STMT field).
1061
1062 S6 will be marked as relevant in vect_mark_stmts_to_be_vectorized instead
1063 of S4 because it will replace all its uses. Stmts {S1,S2,S3} will
1064 remain irrelevant unless used by stmts other than S4.
1065
1066 If vectorization succeeds, vect_transform_stmt will skip over {S1,S2,S3}
1067- (because they are marked as irrelevant). It will vectorize S6, and record
1068+ (because they are marked as irrelevant). It will vectorize S6, and record
1069 a pointer to the new vector stmt VS6 both from S6 (as usual), and also
1070- from S4. We do that so that when we get to vectorizing stmts that use the
1071+ from S4. We do that so that when we get to vectorizing stmts that use the
1072 def of S4 (like S5 that uses a_0), we'll know where to take the relevant
1073- vector-def from. S4 will be skipped, and S5 will be vectorized as usual:
1074+ vector-def from. S4 will be skipped, and S5 will be vectorized as usual:
1075
1076 in_pattern_p related_stmt vec_stmt
1077 S1: a_i = .... - - -
1078 S2: a_2 = ..use(a_i).. - - -
1079 S3: a_1 = ..use(a_2).. - - -
1080 > VS6: va_new = .... - - -
1081- S6: a_new = .... - S4 VS6
1082 S4: a_0 = ..use(a_1).. true S6 VS6
1083+ '---> S6: a_new = .... - S4 VS6
1084 > VS5: ... = ..vuse(va_new).. - - -
1085 S5: ... = ..use(a_0).. - - -
1086
1087- DCE could then get rid of {S1,S2,S3,S4,S5,S6} (if their defs are not used
1088+ DCE could then get rid of {S1,S2,S3,S4,S5} (if their defs are not used
1089 elsewhere), and we'll end up with:
1090
1091 VS6: va_new = ....
1092- VS5: ... = ..vuse(va_new)..
1093-
1094- If vectorization does not succeed, DCE will clean S6 away (its def is
1095- not used), and we'll end up with the original sequence.
1096-*/
1097+ VS5: ... = ..vuse(va_new).. */
1098
1099 void
1100 vect_pattern_recog (loop_vec_info loop_vinfo)
1101@@ -832,7 +925,7 @@
1102 unsigned int nbbs = loop->num_nodes;
1103 gimple_stmt_iterator si;
1104 unsigned int i, j;
1105- gimple (* vect_recog_func_ptr) (gimple, tree *, tree *);
1106+ gimple (* vect_recog_func_ptr) (gimple *, tree *, tree *);
1107
1108 if (vect_print_dump_info (REPORT_DETAILS))
1109 fprintf (vect_dump, "=== vect_pattern_recog ===");
1110
1111=== modified file 'gcc/tree-vect-slp.c'
1112--- old/gcc/tree-vect-slp.c 2011-05-05 15:43:06 +0000
1113+++ new/gcc/tree-vect-slp.c 2011-06-19 10:59:13 +0000
1114@@ -2510,6 +2510,8 @@
1115 && STMT_VINFO_STRIDED_ACCESS (stmt_info)
1116 && !REFERENCE_CLASS_P (gimple_get_lhs (stmt)))
1117 si = gsi_for_stmt (SLP_INSTANCE_FIRST_LOAD_STMT (instance));
1118+ else if (is_pattern_stmt_p (stmt_info))
1119+ si = gsi_for_stmt (STMT_VINFO_RELATED_STMT (stmt_info));
1120 else
1121 si = gsi_for_stmt (stmt);
1122
1123
1124=== modified file 'gcc/tree-vect-stmts.c'
1125--- old/gcc/tree-vect-stmts.c 2011-06-02 12:12:00 +0000
1126+++ new/gcc/tree-vect-stmts.c 2011-06-22 06:21:13 +0000
1127@@ -605,15 +605,76 @@
1128 break;
1129 }
1130
1131- FOR_EACH_PHI_OR_STMT_USE (use_p, stmt, iter, SSA_OP_USE)
1132- {
1133- tree op = USE_FROM_PTR (use_p);
1134- if (!process_use (stmt, op, loop_vinfo, live_p, relevant, &worklist))
1135- {
1136- VEC_free (gimple, heap, worklist);
1137- return false;
1138- }
1139- }
1140+ if (is_pattern_stmt_p (vinfo_for_stmt (stmt)))
1141+ {
1142+ /* Pattern statements are not inserted into the code, so
1143+ FOR_EACH_PHI_OR_STMT_USE optimizes their operands out, and we
1144+ have to scan the RHS or function arguments instead. */
1145+ if (is_gimple_assign (stmt))
1146+ {
1147+ tree rhs = gimple_assign_rhs1 (stmt);
1148+ if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt))
1149+ == GIMPLE_SINGLE_RHS)
1150+ {
1151+ unsigned int op_num = TREE_OPERAND_LENGTH (gimple_assign_rhs1
1152+ (stmt));
1153+ for (i = 0; i < op_num; i++)
1154+ {
1155+ tree op = TREE_OPERAND (rhs, i);
1156+ if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
1157+ &worklist))
1158+ {
1159+ VEC_free (gimple, heap, worklist);
1160+ return false;
1161+ }
1162+ }
1163+ }
1164+ else if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt))
1165+ == GIMPLE_BINARY_RHS)
1166+ {
1167+ tree op = gimple_assign_rhs1 (stmt);
1168+ if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
1169+ &worklist))
1170+ {
1171+ VEC_free (gimple, heap, worklist);
1172+ return false;
1173+ }
1174+ op = gimple_assign_rhs2 (stmt);
1175+ if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
1176+ &worklist))
1177+ {
1178+ VEC_free (gimple, heap, worklist);
1179+ return false;
1180+ }
1181+ }
1182+ else
1183+ return false;
1184+ }
1185+ else if (is_gimple_call (stmt))
1186+ {
1187+ for (i = 0; i < gimple_call_num_args (stmt); i++)
1188+ {
1189+ tree arg = gimple_call_arg (stmt, i);
1190+ if (!process_use (stmt, arg, loop_vinfo, live_p, relevant,
1191+ &worklist))
1192+ {
1193+ VEC_free (gimple, heap, worklist);
1194+ return false;
1195+ }
1196+ }
1197+ }
1198+ }
1199+ else
1200+ FOR_EACH_PHI_OR_STMT_USE (use_p, stmt, iter, SSA_OP_USE)
1201+ {
1202+ tree op = USE_FROM_PTR (use_p);
1203+ if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
1204+ &worklist))
1205+ {
1206+ VEC_free (gimple, heap, worklist);
1207+ return false;
1208+ }
1209+ }
1210 } /* while worklist */
1211
1212 VEC_free (gimple, heap, worklist);
1213@@ -1405,6 +1466,7 @@
1214 VEC(tree, heap) *vargs = NULL;
1215 enum { NARROW, NONE, WIDEN } modifier;
1216 size_t i, nargs;
1217+ tree lhs;
1218
1219 /* FORNOW: unsupported in basic block SLP. */
1220 gcc_assert (loop_vinfo);
1221@@ -1542,7 +1604,7 @@
1222 /** Transform. **/
1223
1224 if (vect_print_dump_info (REPORT_DETAILS))
1225- fprintf (vect_dump, "transform operation.");
1226+ fprintf (vect_dump, "transform call.");
1227
1228 /* Handle def. */
1229 scalar_dest = gimple_call_lhs (stmt);
1230@@ -1661,8 +1723,11 @@
1231 rhs of the statement with something harmless. */
1232
1233 type = TREE_TYPE (scalar_dest);
1234- new_stmt = gimple_build_assign (gimple_call_lhs (stmt),
1235- build_zero_cst (type));
1236+ if (is_pattern_stmt_p (stmt_info))
1237+ lhs = gimple_call_lhs (STMT_VINFO_RELATED_STMT (stmt_info));
1238+ else
1239+ lhs = gimple_call_lhs (stmt);
1240+ new_stmt = gimple_build_assign (lhs, build_zero_cst (type));
1241 set_vinfo_for_stmt (new_stmt, stmt_info);
1242 set_vinfo_for_stmt (stmt, NULL);
1243 STMT_VINFO_STMT (stmt_info) = new_stmt;
1244@@ -3231,6 +3296,33 @@
1245 fprintf (vect_dump, "use not simple.");
1246 return false;
1247 }
1248+
1249+ op_type = TREE_CODE_LENGTH (code);
1250+ if (op_type == binary_op)
1251+ {
1252+ bool ok;
1253+
1254+ op1 = gimple_assign_rhs2 (stmt);
1255+ if (code == WIDEN_MULT_EXPR)
1256+ {
1257+ /* For WIDEN_MULT_EXPR, if OP0 is a constant, use the type of
1258+ OP1. */
1259+ if (CONSTANT_CLASS_P (op0))
1260+ ok = vect_is_simple_use_1 (op1, loop_vinfo, NULL,
1261+ &def_stmt, &def, &dt[1], &vectype_in);
1262+ else
1263+ ok = vect_is_simple_use (op1, loop_vinfo, NULL, &def_stmt, &def,
1264+ &dt[1]);
1265+
1266+ if (!ok)
1267+ {
1268+ if (vect_print_dump_info (REPORT_DETAILS))
1269+ fprintf (vect_dump, "use not simple.");
1270+ return false;
1271+ }
1272+ }
1273+ }
1274+
1275 /* If op0 is an external or constant def use a vector type with
1276 the same size as the output vector type. */
1277 if (!vectype_in)
1278@@ -3263,18 +3355,6 @@
1279
1280 gcc_assert (ncopies >= 1);
1281
1282- op_type = TREE_CODE_LENGTH (code);
1283- if (op_type == binary_op)
1284- {
1285- op1 = gimple_assign_rhs2 (stmt);
1286- if (!vect_is_simple_use (op1, loop_vinfo, NULL, &def_stmt, &def, &dt[1]))
1287- {
1288- if (vect_print_dump_info (REPORT_DETAILS))
1289- fprintf (vect_dump, "use not simple.");
1290- return false;
1291- }
1292- }
1293-
1294 /* Supportable by target? */
1295 if (!supportable_widening_operation (code, stmt, vectype_out, vectype_in,
1296 &decl1, &decl2, &code1, &code2,
1297@@ -3300,6 +3380,14 @@
1298 fprintf (vect_dump, "transform type promotion operation. ncopies = %d.",
1299 ncopies);
1300
1301+ if (code == WIDEN_MULT_EXPR)
1302+ {
1303+ if (CONSTANT_CLASS_P (op0))
1304+ op0 = fold_convert (TREE_TYPE (op1), op0);
1305+ else if (CONSTANT_CLASS_P (op1))
1306+ op1 = fold_convert (TREE_TYPE (op0), op1);
1307+ }
1308+
1309 /* Handle def. */
1310 /* In case of multi-step promotion, we first generate promotion operations
1311 to the intermediate types, and then from that types to the final one.
1312@@ -4824,10 +4912,26 @@
1313 if (!STMT_VINFO_RELEVANT_P (stmt_info)
1314 && !STMT_VINFO_LIVE_P (stmt_info))
1315 {
1316- if (vect_print_dump_info (REPORT_DETAILS))
1317- fprintf (vect_dump, "irrelevant.");
1318+ gimple pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
1319+ if (STMT_VINFO_IN_PATTERN_P (stmt_info)
1320+ && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
1321+ || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
1322+ {
1323+ stmt = pattern_stmt;
1324+ stmt_info = vinfo_for_stmt (pattern_stmt);
1325+ if (vect_print_dump_info (REPORT_DETAILS))
1326+ {
1327+ fprintf (vect_dump, "==> examining pattern statement: ");
1328+ print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
1329+ }
1330+ }
1331+ else
1332+ {
1333+ if (vect_print_dump_info (REPORT_DETAILS))
1334+ fprintf (vect_dump, "irrelevant.");
1335
1336- return true;
1337+ return true;
1338+ }
1339 }
1340
1341 switch (STMT_VINFO_DEF_TYPE (stmt_info))
1342
1343=== modified file 'gcc/tree-vectorizer.h'
1344--- old/gcc/tree-vectorizer.h 2011-05-05 15:43:06 +0000
1345+++ new/gcc/tree-vectorizer.h 2011-06-19 10:59:13 +0000
1346@@ -884,7 +884,7 @@
1347 /* Pattern recognition functions.
1348 Additional pattern recognition functions can (and will) be added
1349 in the future. */
1350-typedef gimple (* vect_recog_func_ptr) (gimple, tree *, tree *);
1351+typedef gimple (* vect_recog_func_ptr) (gimple *, tree *, tree *);
1352 #define NUM_PATTERNS 4
1353 void vect_pattern_recog (loop_vec_info);
1354
1355
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch
deleted file mode 100644
index 4abfa02a7..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch
+++ /dev/null
@@ -1,24 +0,0 @@
12011-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline.
4 gcc/
5 2011-06-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
6
7 PR target/49385
8 * config/arm/thumb2.md (*thumb2_movhi_insn): Make sure atleast
9 one of the operands is a register.
10Index: gcc-4_6-branch/gcc/config/arm/thumb2.md
11===================================================================
12--- gcc-4_6-branch.orig/gcc/config/arm/thumb2.md 2011-09-16 20:22:40.000000000 -0700
13+++ gcc-4_6-branch/gcc/config/arm/thumb2.md 2011-09-16 20:28:47.648690433 -0700
14@@ -207,7 +207,9 @@
15 (define_insn "*thumb2_movhi_insn"
16 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
17 (match_operand:HI 1 "general_operand" "rI,n,r,m"))]
18- "TARGET_THUMB2"
19+ "TARGET_THUMB2
20+ && (register_operand (operands[0], HImode)
21+ || register_operand (operands[1], HImode))"
22 "@
23 mov%?\\t%0, %1\\t%@ movhi
24 movw%?\\t%0, %L1\\t%@ movhi
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106764.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106764.patch
deleted file mode 100644
index a548b1b68..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106764.patch
+++ /dev/null
@@ -1,25 +0,0 @@
12011-06-30 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline.
4 LP 744754
5 2011-04-17 Chung-Lin Tang <cltang@codesourcery.com>
6
7 * config/arm/arm.c (neon_struct_mem_operand):
8 Support POST_INC/PRE_DEC memory operands.
9
10=== modified file 'gcc/config/arm/arm.c'
11--- old/gcc/config/arm/arm.c 2011-06-27 22:14:07 +0000
12+++ new/gcc/config/arm/arm.c 2011-06-29 09:13:17 +0000
13@@ -9357,6 +9357,11 @@
14 if (GET_CODE (ind) == REG)
15 return arm_address_register_rtx_p (ind, 0);
16
17+ /* vldm/vstm allows POST_INC (ia) and PRE_DEC (db). */
18+ if (GET_CODE (ind) == POST_INC
19+ || GET_CODE (ind) == PRE_DEC)
20+ return arm_address_register_rtx_p (XEXP (ind, 0), 0);
21+
22 return FALSE;
23 }
24
25
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106766.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106766.patch
deleted file mode 100644
index 15046a766..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106766.patch
+++ /dev/null
@@ -1,25 +0,0 @@
12011-07-03 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from FSF:
4 2011-06-12 Ira Rosen <ira.rosen@linaro.org>
5
6 gcc/
7 * tree-vect-data-refs.c (vect_peeling_hash_get_most_frequent):
8 Take number of iterations to peel into account for equally frequent
9 misalignment values.
10
11=== modified file 'gcc/tree-vect-data-refs.c'
12--- old/gcc/tree-vect-data-refs.c 2011-06-02 12:12:00 +0000
13+++ new/gcc/tree-vect-data-refs.c 2011-06-29 11:20:24 +0000
14@@ -1256,7 +1256,9 @@
15 vect_peel_info elem = (vect_peel_info) *slot;
16 vect_peel_extended_info max = (vect_peel_extended_info) data;
17
18- if (elem->count > max->peel_info.count)
19+ if (elem->count > max->peel_info.count
20+ || (elem->count == max->peel_info.count
21+ && max->peel_info.npeel > elem->npeel))
22 {
23 max->peel_info.npeel = elem->npeel;
24 max->peel_info.count = elem->count;
25
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106768.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106768.patch
deleted file mode 100644
index f1f7718eb..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106768.patch
+++ /dev/null
@@ -1,182 +0,0 @@
12011-07-07 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 * builtins.c (get_object_alignment): Fix comment.
5 * fold-const.c (get_pointer_modulus_and_residue): Remove
6 allow_func_align. Use get_object_alignment.
7 (fold_binary_loc): Update caller.
8
92011-07-07 Richard Sandiford <richard.sandiford@linaro.org>
10
11 gcc/
12 Backport from mainline:
13
14 2011-06-29 Richard Sandiford <richard.sandiford@linaro.org>
15
16 PR tree-optimization/49545
17 * builtins.c (get_object_alignment_1): Update function comment.
18 Do not use DECL_ALIGN for functions, but test
19 TARGET_PTRMEMFUNC_VBIT_LOCATION instead.
20 * fold-const.c (get_pointer_modulus_and_residue): Don't check
21 for functions here.
22 * tree-ssa-ccp.c (get_value_from_alignment): Likewise.
23
24 gcc/testsuite/
25 Backport from mainline:
26
27 2011-06-29 Richard Sandiford <richard.sandiford@linaro.org>
28
29 * gcc.dg/torture/pr49169.c: Restrict to ARM and MIPS targets.
30
312011-07-07 Richard Sandiford <richard.sandiford@linaro.org>
32
33 gcc/
34 Backport from mainline:
35
36 2011-07-27 Richard Guenther <rguenther@suse.de>
37
38 PR tree-optimization/49169
39 * fold-const.c (get_pointer_modulus_and_residue): Don't rely on
40 the alignment of function decls.
41
42 gcc/testsuite/
43 Backport from mainline:
44
45 2011-07-27 Michael Hope <michael.hope@linaro.org>
46 Richard Sandiford <richard.sandiford@linaro.org>
47
48 PR tree-optimization/49169
49 * gcc.dg/torture/pr49169.c: New test.
50
51=== modified file 'gcc/builtins.c'
52--- old/gcc/builtins.c 2011-03-03 21:56:58 +0000
53+++ new/gcc/builtins.c 2011-07-04 09:52:27 +0000
54@@ -264,7 +264,14 @@
55 }
56
57 /* Return the alignment in bits of EXP, an object.
58- Don't return more than MAX_ALIGN no matter what. */
59+ Don't return more than MAX_ALIGN no matter what.
60+
61+ Note that the address (and thus the alignment) computed here is based
62+ on the address to which a symbol resolves, whereas DECL_ALIGN is based
63+ on the address at which an object is actually located. These two
64+ addresses are not always the same. For example, on ARM targets,
65+ the address &foo of a Thumb function foo() has the lowest bit set,
66+ whereas foo() itself starts on an even address. */
67
68 unsigned int
69 get_object_alignment (tree exp, unsigned int max_align)
70@@ -286,7 +293,21 @@
71 exp = DECL_INITIAL (exp);
72 if (DECL_P (exp)
73 && TREE_CODE (exp) != LABEL_DECL)
74- align = DECL_ALIGN (exp);
75+ {
76+ if (TREE_CODE (exp) == FUNCTION_DECL)
77+ {
78+ /* Function addresses can encode extra information besides their
79+ alignment. However, if TARGET_PTRMEMFUNC_VBIT_LOCATION
80+ allows the low bit to be used as a virtual bit, we know
81+ that the address itself must be 2-byte aligned. */
82+ if (TARGET_PTRMEMFUNC_VBIT_LOCATION == ptrmemfunc_vbit_in_pfn)
83+ align = 2 * BITS_PER_UNIT;
84+ else
85+ align = BITS_PER_UNIT;
86+ }
87+ else
88+ align = DECL_ALIGN (exp);
89+ }
90 else if (CONSTANT_CLASS_P (exp))
91 {
92 align = TYPE_ALIGN (TREE_TYPE (exp));
93
94=== modified file 'gcc/fold-const.c'
95--- old/gcc/fold-const.c 2011-05-23 20:37:18 +0000
96+++ new/gcc/fold-const.c 2011-07-04 09:52:27 +0000
97@@ -9232,15 +9232,10 @@
98 0 <= N < M as is common. In general, the precise value of P is unknown.
99 M is chosen as large as possible such that constant N can be determined.
100
101- Returns M and sets *RESIDUE to N.
102-
103- If ALLOW_FUNC_ALIGN is true, do take functions' DECL_ALIGN_UNIT into
104- account. This is not always possible due to PR 35705.
105- */
106+ Returns M and sets *RESIDUE to N. */
107
108 static unsigned HOST_WIDE_INT
109-get_pointer_modulus_and_residue (tree expr, unsigned HOST_WIDE_INT *residue,
110- bool allow_func_align)
111+get_pointer_modulus_and_residue (tree expr, unsigned HOST_WIDE_INT *residue)
112 {
113 enum tree_code code;
114
115@@ -9270,9 +9265,8 @@
116 }
117 }
118
119- if (DECL_P (expr)
120- && (allow_func_align || TREE_CODE (expr) != FUNCTION_DECL))
121- return DECL_ALIGN_UNIT (expr);
122+ if (DECL_P (expr))
123+ return get_object_alignment (expr, ~0U) / BITS_PER_UNIT;
124 }
125 else if (code == POINTER_PLUS_EXPR)
126 {
127@@ -9282,8 +9276,7 @@
128
129 op0 = TREE_OPERAND (expr, 0);
130 STRIP_NOPS (op0);
131- modulus = get_pointer_modulus_and_residue (op0, residue,
132- allow_func_align);
133+ modulus = get_pointer_modulus_and_residue (op0, residue);
134
135 op1 = TREE_OPERAND (expr, 1);
136 STRIP_NOPS (op1);
137@@ -11163,8 +11156,7 @@
138 unsigned HOST_WIDE_INT modulus, residue;
139 unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg1);
140
141- modulus = get_pointer_modulus_and_residue (arg0, &residue,
142- integer_onep (arg1));
143+ modulus = get_pointer_modulus_and_residue (arg0, &residue);
144
145 /* This works because modulus is a power of 2. If this weren't the
146 case, we'd have to replace it by its greatest power-of-2
147
148=== added file 'gcc/testsuite/gcc.dg/torture/pr49169.c'
149--- old/gcc/testsuite/gcc.dg/torture/pr49169.c 1970-01-01 00:00:00 +0000
150+++ new/gcc/testsuite/gcc.dg/torture/pr49169.c 2011-06-29 09:46:06 +0000
151@@ -0,0 +1,15 @@
152+/* { dg-do compile { target { arm*-*-* || mips*-*-* } } } */
153+
154+#include <stdlib.h>
155+#include <stdint.h>
156+
157+int
158+main (void)
159+{
160+ void *p = main;
161+ if ((intptr_t) p & 1)
162+ abort ();
163+ return 0;
164+}
165+
166+/* { dg-final { scan-assembler "abort" } } */
167
168=== modified file 'gcc/tree-ssa-ccp.c'
169--- old/gcc/tree-ssa-ccp.c 2011-05-05 15:42:22 +0000
170+++ new/gcc/tree-ssa-ccp.c 2011-06-29 09:46:06 +0000
171@@ -522,10 +522,6 @@
172 val = bit_value_binop (PLUS_EXPR, TREE_TYPE (expr),
173 TREE_OPERAND (base, 0), TREE_OPERAND (base, 1));
174 else if (base
175- /* ??? While function decls have DECL_ALIGN their addresses
176- may encode extra information in the lower bits on some
177- targets (PR47239). Simply punt for function decls for now. */
178- && TREE_CODE (base) != FUNCTION_DECL
179 && ((align = get_object_alignment (base, BIGGEST_ALIGNMENT))
180 > BITS_PER_UNIT))
181 {
182
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106769.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106769.patch
deleted file mode 100644
index 3a149231f..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106769.patch
+++ /dev/null
@@ -1,1281 +0,0 @@
12011-07-11 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from FSF:
4 2011-06-16 Ira Rosen <ira.rosen@linaro.org>
5
6 gcc/
7 * tree-vectorizer.h (vect_recog_func_ptr): Change the first
8 argument to be a VEC of statements.
9 * tree-vect-loop.c (vect_determine_vectorization_factor): Remove the
10 assert that pattern statements have to have their vector type set.
11 * tree-vect-patterns.c (vect_recog_widen_sum_pattern):
12 Change the first argument to be a VEC of statements. Update
13 documentation.
14 (vect_recog_dot_prod_pattern, vect_recog_pow_pattern): Likewise.
15 (vect_handle_widen_mult_by_const): New function.
16 (vect_recog_widen_mult_pattern): Change the first argument to be a
17 VEC of statements. Update documentation. Check that the constant is
18 INTEGER_CST. Support multiplication by a constant that fits an
19 intermediate type - call vect_handle_widen_mult_by_const.
20 (vect_pattern_recog_1): Update vect_recog_func_ptr and its
21 call. Handle additional pattern statements if necessary.
22
23 gcc/testsuite/
24 * gcc.dg/vect/vect-widen-mult-half-u8.c: New test.
25
26 and
27 2011-06-30 Ira Rosen <ira.rosen@linaro.org>
28
29 gcc/
30 * tree-vect-loop.c (vect_determine_vectorization_factor): Handle
31 both pattern and original statements if necessary.
32 (vect_transform_loop): Likewise.
33 * tree-vect-patterns.c (vect_pattern_recog): Update documentation.
34 * tree-vect-stmts.c (vect_mark_relevant): Add new argument.
35 Mark the pattern statement only if the original statement doesn't
36 have its own uses.
37 (process_use): Call vect_mark_relevant with additional parameter.
38 (vect_mark_stmts_to_be_vectorized): Likewise.
39 (vect_get_vec_def_for_operand): Use vectorized pattern statement.
40 (vect_analyze_stmt): Handle both pattern and original statements
41 if necessary.
42 (vect_transform_stmt): Don't store vectorized pattern statement
43 in the original statement.
44 (vect_is_simple_use_1): Use related pattern statement only if the
45 original statement is irrelevant.
46 * tree-vect-slp.c (vect_get_and_check_slp_defs): Likewise.
47
48 gcc/testsuite/
49 * gcc.dg/vect/slp-widen-mult-half.c: New test.
50 * gcc.dg/vect/vect-widen-mult-half.c: New test.
51
52=== added file 'gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c'
53Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c
54===================================================================
55--- /dev/null 1970-01-01 00:00:00.000000000 +0000
56+++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c 2012-01-09 15:03:29.156918805 -0800
57@@ -0,0 +1,52 @@
58+/* { dg-require-effective-target vect_int } */
59+
60+#include "tree-vect.h"
61+#include <stdlib.h>
62+
63+#define N 32
64+#define COEF 32470
65+#define COEF2 324700
66+
67+unsigned char in[N];
68+int out[N];
69+int out2[N];
70+
71+__attribute__ ((noinline)) void
72+foo ()
73+{
74+ int i;
75+
76+ for (i = 0; i < N/2; i++)
77+ {
78+ out[2*i] = in[2*i] * COEF;
79+ out2[2*i] = in[2*i] + COEF2;
80+ out[2*i+1] = in[2*i+1] * COEF;
81+ out2[2*i+1] = in[2*i+1] + COEF2;
82+ }
83+}
84+
85+int main (void)
86+{
87+ int i;
88+
89+ for (i = 0; i < N; i++)
90+ {
91+ in[i] = i;
92+ __asm__ volatile ("");
93+ }
94+
95+ foo ();
96+
97+ for (i = 0; i < N; i++)
98+ if (out[i] != in[i] * COEF || out2[i] != in[i] + COEF2)
99+ abort ();
100+
101+ return 0;
102+}
103+
104+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_widen_mult_hi_to_si } } } */
105+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_widen_mult_hi_to_si } } } */
106+/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
107+/* { dg-final { scan-tree-dump-times "pattern recognized" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
108+/* { dg-final { cleanup-tree-dump "vect" } } */
109+
110Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c
111===================================================================
112--- /dev/null 1970-01-01 00:00:00.000000000 +0000
113+++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c 2012-01-09 15:03:29.156918805 -0800
114@@ -0,0 +1,59 @@
115+/* { dg-require-effective-target vect_int } */
116+
117+#include "tree-vect.h"
118+#include <stdlib.h>
119+
120+#define N 32
121+#define COEF 32470
122+
123+unsigned char in[N];
124+int out[N];
125+
126+__attribute__ ((noinline)) void
127+foo ()
128+{
129+ int i;
130+
131+ for (i = 0; i < N; i++)
132+ out[i] = in[i] * COEF;
133+}
134+
135+__attribute__ ((noinline)) void
136+bar ()
137+{
138+ int i;
139+
140+ for (i = 0; i < N; i++)
141+ out[i] = COEF * in[i];
142+}
143+
144+int main (void)
145+{
146+ int i;
147+
148+ for (i = 0; i < N; i++)
149+ {
150+ in[i] = i;
151+ __asm__ volatile ("");
152+ }
153+
154+ foo ();
155+
156+ for (i = 0; i < N; i++)
157+ if (out[i] != in[i] * COEF)
158+ abort ();
159+
160+ bar ();
161+
162+ for (i = 0; i < N; i++)
163+ if (out[i] != in[i] * COEF)
164+ abort ();
165+
166+ return 0;
167+}
168+
169+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_widen_mult_hi_to_si } } } */
170+/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
171+/* { dg-final { scan-tree-dump-times "pattern recognized" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
172+/* { dg-final { cleanup-tree-dump "vect" } } */
173+
174Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c
175===================================================================
176--- /dev/null 1970-01-01 00:00:00.000000000 +0000
177+++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c 2012-01-09 15:03:29.160918806 -0800
178@@ -0,0 +1,49 @@
179+/* { dg-require-effective-target vect_int } */
180+
181+#include "tree-vect.h"
182+#include <stdlib.h>
183+
184+#define N 32
185+#define COEF 32470
186+#define COEF2 324700
187+
188+unsigned char in[N];
189+int out[N];
190+int out2[N];
191+
192+__attribute__ ((noinline)) void
193+foo (int a)
194+{
195+ int i;
196+
197+ for (i = 0; i < N; i++)
198+ {
199+ out[i] = in[i] * COEF;
200+ out2[i] = in[i] + a;
201+ }
202+}
203+
204+int main (void)
205+{
206+ int i;
207+
208+ for (i = 0; i < N; i++)
209+ {
210+ in[i] = i;
211+ __asm__ volatile ("");
212+ }
213+
214+ foo (COEF2);
215+
216+ for (i = 0; i < N; i++)
217+ if (out[i] != in[i] * COEF || out2[i] != in[i] + COEF2)
218+ abort ();
219+
220+ return 0;
221+}
222+
223+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_widen_mult_hi_to_si } } } */
224+/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 1 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
225+/* { dg-final { scan-tree-dump-times "pattern recognized" 1 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
226+/* { dg-final { cleanup-tree-dump "vect" } } */
227+
228Index: gcc-4_6-branch/gcc/tree-vect-loop.c
229===================================================================
230--- gcc-4_6-branch.orig/gcc/tree-vect-loop.c 2012-01-09 15:02:15.000000000 -0800
231+++ gcc-4_6-branch/gcc/tree-vect-loop.c 2012-01-09 15:03:29.160918806 -0800
232@@ -181,6 +181,8 @@
233 stmt_vec_info stmt_info;
234 int i;
235 HOST_WIDE_INT dummy;
236+ gimple stmt, pattern_stmt = NULL;
237+ bool analyze_pattern_stmt = false;
238
239 if (vect_print_dump_info (REPORT_DETAILS))
240 fprintf (vect_dump, "=== vect_determine_vectorization_factor ===");
241@@ -241,12 +243,20 @@
242 }
243 }
244
245- for (si = gsi_start_bb (bb); !gsi_end_p (si); gsi_next (&si))
246+ for (si = gsi_start_bb (bb); !gsi_end_p (si) || analyze_pattern_stmt;)
247 {
248- tree vf_vectype;
249- gimple stmt = gsi_stmt (si), pattern_stmt;
250- stmt_info = vinfo_for_stmt (stmt);
251+ tree vf_vectype;
252+
253+ if (analyze_pattern_stmt)
254+ {
255+ stmt = pattern_stmt;
256+ analyze_pattern_stmt = false;
257+ }
258+ else
259+ stmt = gsi_stmt (si);
260
261+ stmt_info = vinfo_for_stmt (stmt);
262+
263 if (vect_print_dump_info (REPORT_DETAILS))
264 {
265 fprintf (vect_dump, "==> examining statement: ");
266@@ -276,10 +286,17 @@
267 {
268 if (vect_print_dump_info (REPORT_DETAILS))
269 fprintf (vect_dump, "skip.");
270+ gsi_next (&si);
271 continue;
272 }
273 }
274
275+ else if (STMT_VINFO_IN_PATTERN_P (stmt_info)
276+ && (pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info))
277+ && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
278+ || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
279+ analyze_pattern_stmt = true;
280+
281 if (gimple_get_lhs (stmt) == NULL_TREE)
282 {
283 if (vect_print_dump_info (REPORT_UNVECTORIZED_LOCATIONS))
284@@ -311,9 +328,7 @@
285 }
286 else
287 {
288- gcc_assert (!STMT_VINFO_DATA_REF (stmt_info)
289- && !is_pattern_stmt_p (stmt_info));
290-
291+ gcc_assert (!STMT_VINFO_DATA_REF (stmt_info));
292 scalar_type = TREE_TYPE (gimple_get_lhs (stmt));
293 if (vect_print_dump_info (REPORT_DETAILS))
294 {
295@@ -385,6 +400,9 @@
296 if (!vectorization_factor
297 || (nunits > vectorization_factor))
298 vectorization_factor = nunits;
299+
300+ if (!analyze_pattern_stmt)
301+ gsi_next (&si);
302 }
303 }
304
305@@ -4740,6 +4758,8 @@
306 tree cond_expr = NULL_TREE;
307 gimple_seq cond_expr_stmt_list = NULL;
308 bool do_peeling_for_loop_bound;
309+ gimple stmt, pattern_stmt;
310+ bool transform_pattern_stmt = false;
311
312 if (vect_print_dump_info (REPORT_DETAILS))
313 fprintf (vect_dump, "=== vec_transform_loop ===");
314@@ -4827,11 +4847,19 @@
315 }
316 }
317
318- for (si = gsi_start_bb (bb); !gsi_end_p (si);)
319+ pattern_stmt = NULL;
320+ for (si = gsi_start_bb (bb); !gsi_end_p (si) || transform_pattern_stmt;)
321 {
322- gimple stmt = gsi_stmt (si), pattern_stmt;
323 bool is_store;
324
325+ if (transform_pattern_stmt)
326+ {
327+ stmt = pattern_stmt;
328+ transform_pattern_stmt = false;
329+ }
330+ else
331+ stmt = gsi_stmt (si);
332+
333 if (vect_print_dump_info (REPORT_DETAILS))
334 {
335 fprintf (vect_dump, "------>vectorizing statement: ");
336@@ -4869,6 +4897,11 @@
337 continue;
338 }
339 }
340+ else if (STMT_VINFO_IN_PATTERN_P (stmt_info)
341+ && (pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info))
342+ && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
343+ || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
344+ transform_pattern_stmt = true;
345
346 gcc_assert (STMT_VINFO_VECTYPE (stmt_info));
347 nunits = (unsigned int) TYPE_VECTOR_SUBPARTS (
348@@ -4897,8 +4930,9 @@
349 /* Hybrid SLP stmts must be vectorized in addition to SLP. */
350 if (!vinfo_for_stmt (stmt) || PURE_SLP_STMT (stmt_info))
351 {
352- gsi_next (&si);
353- continue;
354+ if (!transform_pattern_stmt)
355+ gsi_next (&si);
356+ continue;
357 }
358 }
359
360@@ -4917,7 +4951,7 @@
361 the chain. */
362 vect_remove_stores (DR_GROUP_FIRST_DR (stmt_info));
363 gsi_remove (&si, true);
364- continue;
365+ continue;
366 }
367 else
368 {
369@@ -4927,7 +4961,9 @@
370 continue;
371 }
372 }
373- gsi_next (&si);
374+
375+ if (!transform_pattern_stmt)
376+ gsi_next (&si);
377 } /* stmts in BB */
378 } /* BBs in loop */
379
380Index: gcc-4_6-branch/gcc/tree-vect-patterns.c
381===================================================================
382--- gcc-4_6-branch.orig/gcc/tree-vect-patterns.c 2012-01-09 15:02:15.000000000 -0800
383+++ gcc-4_6-branch/gcc/tree-vect-patterns.c 2012-01-09 15:03:29.160918806 -0800
384@@ -39,10 +39,13 @@
385 #include "diagnostic-core.h"
386
387 /* Pattern recognition functions */
388-static gimple vect_recog_widen_sum_pattern (gimple *, tree *, tree *);
389-static gimple vect_recog_widen_mult_pattern (gimple *, tree *, tree *);
390-static gimple vect_recog_dot_prod_pattern (gimple *, tree *, tree *);
391-static gimple vect_recog_pow_pattern (gimple *, tree *, tree *);
392+static gimple vect_recog_widen_sum_pattern (VEC (gimple, heap) **, tree *,
393+ tree *);
394+static gimple vect_recog_widen_mult_pattern (VEC (gimple, heap) **, tree *,
395+ tree *);
396+static gimple vect_recog_dot_prod_pattern (VEC (gimple, heap) **, tree *,
397+ tree *);
398+static gimple vect_recog_pow_pattern (VEC (gimple, heap) **, tree *, tree *);
399 static vect_recog_func_ptr vect_vect_recog_func_ptrs[NUM_PATTERNS] = {
400 vect_recog_widen_mult_pattern,
401 vect_recog_widen_sum_pattern,
402@@ -142,9 +145,9 @@
403
404 Input:
405
406- * LAST_STMT: A stmt from which the pattern search begins. In the example,
407- when this function is called with S7, the pattern {S3,S4,S5,S6,S7} will be
408- detected.
409+ * STMTS: Contains a stmt from which the pattern search begins. In the
410+ example, when this function is called with S7, the pattern {S3,S4,S5,S6,S7}
411+ will be detected.
412
413 Output:
414
415@@ -165,12 +168,13 @@
416 inner-loop nested in an outer-loop that us being vectorized). */
417
418 static gimple
419-vect_recog_dot_prod_pattern (gimple *last_stmt, tree *type_in, tree *type_out)
420+vect_recog_dot_prod_pattern (VEC (gimple, heap) **stmts, tree *type_in,
421+ tree *type_out)
422 {
423- gimple stmt;
424+ gimple stmt, last_stmt = VEC_index (gimple, *stmts, 0);
425 tree oprnd0, oprnd1;
426 tree oprnd00, oprnd01;
427- stmt_vec_info stmt_vinfo = vinfo_for_stmt (*last_stmt);
428+ stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt);
429 tree type, half_type;
430 gimple pattern_stmt;
431 tree prod_type;
432@@ -178,10 +182,10 @@
433 struct loop *loop = LOOP_VINFO_LOOP (loop_info);
434 tree var, rhs;
435
436- if (!is_gimple_assign (*last_stmt))
437+ if (!is_gimple_assign (last_stmt))
438 return NULL;
439
440- type = gimple_expr_type (*last_stmt);
441+ type = gimple_expr_type (last_stmt);
442
443 /* Look for the following pattern
444 DX = (TYPE1) X;
445@@ -207,7 +211,7 @@
446 /* Starting from LAST_STMT, follow the defs of its uses in search
447 of the above pattern. */
448
449- if (gimple_assign_rhs_code (*last_stmt) != PLUS_EXPR)
450+ if (gimple_assign_rhs_code (last_stmt) != PLUS_EXPR)
451 return NULL;
452
453 if (STMT_VINFO_IN_PATTERN_P (stmt_vinfo))
454@@ -228,12 +232,12 @@
455
456 if (STMT_VINFO_DEF_TYPE (stmt_vinfo) != vect_reduction_def)
457 return NULL;
458- oprnd0 = gimple_assign_rhs1 (*last_stmt);
459- oprnd1 = gimple_assign_rhs2 (*last_stmt);
460+ oprnd0 = gimple_assign_rhs1 (last_stmt);
461+ oprnd1 = gimple_assign_rhs2 (last_stmt);
462 if (!types_compatible_p (TREE_TYPE (oprnd0), type)
463 || !types_compatible_p (TREE_TYPE (oprnd1), type))
464 return NULL;
465- stmt = *last_stmt;
466+ stmt = last_stmt;
467
468 if (widened_name_p (oprnd0, stmt, &half_type, &def_stmt, true))
469 {
470@@ -319,11 +323,79 @@
471
472 /* We don't allow changing the order of the computation in the inner-loop
473 when doing outer-loop vectorization. */
474- gcc_assert (!nested_in_vect_loop_p (loop, *last_stmt));
475+ gcc_assert (!nested_in_vect_loop_p (loop, last_stmt));
476
477 return pattern_stmt;
478 }
479
480+/* Handle two cases of multiplication by a constant. The first one is when
481+ the constant, CONST_OPRND, fits the type (HALF_TYPE) of the second
482+ operand (OPRND). In that case, we can peform widen-mult from HALF_TYPE to
483+ TYPE.
484+
485+ Otherwise, if the type of the result (TYPE) is at least 4 times bigger than
486+ HALF_TYPE, and CONST_OPRND fits an intermediate type (2 times smaller than
487+ TYPE), we can perform widen-mult from the intermediate type to TYPE and
488+ replace a_T = (TYPE) a_t; with a_it - (interm_type) a_t; */
489+
490+static bool
491+vect_handle_widen_mult_by_const (tree const_oprnd, tree *oprnd,
492+ VEC (gimple, heap) **stmts, tree type,
493+ tree *half_type, gimple def_stmt)
494+{
495+ tree new_type, new_oprnd, tmp;
496+ gimple new_stmt;
497+
498+ if (int_fits_type_p (const_oprnd, *half_type))
499+ {
500+ /* CONST_OPRND is a constant of HALF_TYPE. */
501+ *oprnd = gimple_assign_rhs1 (def_stmt);
502+ return true;
503+ }
504+
505+ if (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 4)
506+ || !vinfo_for_stmt (def_stmt))
507+ return false;
508+
509+ /* TYPE is 4 times bigger than HALF_TYPE, try widen-mult for
510+ a type 2 times bigger than HALF_TYPE. */
511+ new_type = build_nonstandard_integer_type (TYPE_PRECISION (type) / 2,
512+ TYPE_UNSIGNED (type));
513+ if (!int_fits_type_p (const_oprnd, new_type))
514+ return false;
515+
516+ /* Use NEW_TYPE for widen_mult. */
517+ if (STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)))
518+ {
519+ new_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt));
520+ /* Check if the already created pattern stmt is what we need. */
521+ if (!is_gimple_assign (new_stmt)
522+ || gimple_assign_rhs_code (new_stmt) != NOP_EXPR
523+ || TREE_TYPE (gimple_assign_lhs (new_stmt)) != new_type)
524+ return false;
525+
526+ *oprnd = gimple_assign_lhs (new_stmt);
527+ }
528+ else
529+ {
530+ /* Create a_T = (NEW_TYPE) a_t; */
531+ *oprnd = gimple_assign_rhs1 (def_stmt);
532+ tmp = create_tmp_var (new_type, NULL);
533+ add_referenced_var (tmp);
534+ new_oprnd = make_ssa_name (tmp, NULL);
535+ new_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd, *oprnd,
536+ NULL_TREE);
537+ SSA_NAME_DEF_STMT (new_oprnd) = new_stmt;
538+ STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)) = new_stmt;
539+ VEC_safe_push (gimple, heap, *stmts, def_stmt);
540+ *oprnd = new_oprnd;
541+ }
542+
543+ *half_type = new_type;
544+ return true;
545+}
546+
547+
548 /* Function vect_recog_widen_mult_pattern
549
550 Try to find the following pattern:
551@@ -361,28 +433,47 @@
552 S3 a_T = (TYPE) a_t;
553 S5 prod_T = a_T * CONST;
554
555- Input:
556+ A special case of multiplication by constants is when 'TYPE' is 4 times
557+ bigger than 'type', but CONST fits an intermediate type 2 times smaller
558+ than 'TYPE'. In that case we create an additional pattern stmt for S3
559+ to create a variable of the intermediate type, and perform widen-mult
560+ on the intermediate type as well:
561+
562+ type a_t;
563+ interm_type a_it;
564+ TYPE a_T, prod_T, prod_T';
565+
566+ S1 a_t = ;
567+ S3 a_T = (TYPE) a_t;
568+ '--> a_it = (interm_type) a_t;
569+ S5 prod_T = a_T * CONST;
570+ '--> prod_T' = a_it w* CONST;
571+
572+ Input/Output:
573
574- * LAST_STMT: A stmt from which the pattern search begins. In the example,
575- when this function is called with S5, the pattern {S3,S4,S5,(S6)} is
576- detected.
577+ * STMTS: Contains a stmt from which the pattern search begins. In the
578+ example, when this function is called with S5, the pattern {S3,S4,S5,(S6)}
579+ is detected. In case of unsigned widen-mult, the original stmt (S5) is
580+ replaced with S6 in STMTS. In case of multiplication by a constant
581+ of an intermediate type (the last case above), STMTS also contains S3
582+ (inserted before S5).
583
584- Output:
585+ Output:
586
587- * TYPE_IN: The type of the input arguments to the pattern.
588+ * TYPE_IN: The type of the input arguments to the pattern.
589
590- * TYPE_OUT: The type of the output of this pattern.
591+ * TYPE_OUT: The type of the output of this pattern.
592
593- * Return value: A new stmt that will be used to replace the sequence of
594- stmts that constitute the pattern. In this case it will be:
595- WIDEN_MULT <a_t, b_t>
596- */
597+ * Return value: A new stmt that will be used to replace the sequence of
598+ stmts that constitute the pattern. In this case it will be:
599+ WIDEN_MULT <a_t, b_t>
600+*/
601
602 static gimple
603-vect_recog_widen_mult_pattern (gimple *last_stmt,
604- tree *type_in,
605- tree *type_out)
606+vect_recog_widen_mult_pattern (VEC (gimple, heap) **stmts,
607+ tree *type_in, tree *type_out)
608 {
609+ gimple last_stmt = VEC_pop (gimple, *stmts);
610 gimple def_stmt0, def_stmt1;
611 tree oprnd0, oprnd1;
612 tree type, half_type0, half_type1;
613@@ -395,27 +486,27 @@
614 VEC (tree, heap) *dummy_vec;
615 bool op0_ok, op1_ok;
616
617- if (!is_gimple_assign (*last_stmt))
618+ if (!is_gimple_assign (last_stmt))
619 return NULL;
620
621- type = gimple_expr_type (*last_stmt);
622+ type = gimple_expr_type (last_stmt);
623
624 /* Starting from LAST_STMT, follow the defs of its uses in search
625 of the above pattern. */
626
627- if (gimple_assign_rhs_code (*last_stmt) != MULT_EXPR)
628+ if (gimple_assign_rhs_code (last_stmt) != MULT_EXPR)
629 return NULL;
630
631- oprnd0 = gimple_assign_rhs1 (*last_stmt);
632- oprnd1 = gimple_assign_rhs2 (*last_stmt);
633+ oprnd0 = gimple_assign_rhs1 (last_stmt);
634+ oprnd1 = gimple_assign_rhs2 (last_stmt);
635 if (!types_compatible_p (TREE_TYPE (oprnd0), type)
636 || !types_compatible_p (TREE_TYPE (oprnd1), type))
637 return NULL;
638
639 /* Check argument 0. */
640- op0_ok = widened_name_p (oprnd0, *last_stmt, &half_type0, &def_stmt0, false);
641+ op0_ok = widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0, false);
642 /* Check argument 1. */
643- op1_ok = widened_name_p (oprnd1, *last_stmt, &half_type1, &def_stmt1, false);
644+ op1_ok = widened_name_p (oprnd1, last_stmt, &half_type1, &def_stmt1, false);
645
646 /* In case of multiplication by a constant one of the operands may not match
647 the pattern, but not both. */
648@@ -429,29 +520,21 @@
649 }
650 else if (!op0_ok)
651 {
652- if (CONSTANT_CLASS_P (oprnd0)
653- && TREE_CODE (half_type1) == INTEGER_TYPE
654- && tree_int_cst_lt (oprnd0, TYPE_MAXVAL (half_type1))
655- && tree_int_cst_lt (TYPE_MINVAL (half_type1), oprnd0))
656- {
657- /* OPRND0 is a constant of HALF_TYPE1. */
658- half_type0 = half_type1;
659- oprnd1 = gimple_assign_rhs1 (def_stmt1);
660- }
661+ if (TREE_CODE (oprnd0) == INTEGER_CST
662+ && TREE_CODE (half_type1) == INTEGER_TYPE
663+ && vect_handle_widen_mult_by_const (oprnd0, &oprnd1, stmts, type,
664+ &half_type1, def_stmt1))
665+ half_type0 = half_type1;
666 else
667 return NULL;
668 }
669 else if (!op1_ok)
670 {
671- if (CONSTANT_CLASS_P (oprnd1)
672+ if (TREE_CODE (oprnd1) == INTEGER_CST
673 && TREE_CODE (half_type0) == INTEGER_TYPE
674- && tree_int_cst_lt (oprnd1, TYPE_MAXVAL (half_type0))
675- && tree_int_cst_lt (TYPE_MINVAL (half_type0), oprnd1))
676- {
677- /* OPRND1 is a constant of HALF_TYPE0. */
678- half_type1 = half_type0;
679- oprnd0 = gimple_assign_rhs1 (def_stmt0);
680- }
681+ && vect_handle_widen_mult_by_const (oprnd1, &oprnd0, stmts, type,
682+ &half_type0, def_stmt0))
683+ half_type1 = half_type0;
684 else
685 return NULL;
686 }
687@@ -461,7 +544,7 @@
688 Use unsigned TYPE as the type for WIDEN_MULT_EXPR. */
689 if (TYPE_UNSIGNED (type) != TYPE_UNSIGNED (half_type0))
690 {
691- tree lhs = gimple_assign_lhs (*last_stmt), use_lhs;
692+ tree lhs = gimple_assign_lhs (last_stmt), use_lhs;
693 imm_use_iterator imm_iter;
694 use_operand_p use_p;
695 int nuses = 0;
696@@ -491,7 +574,7 @@
697 return NULL;
698
699 type = use_type;
700- *last_stmt = use_stmt;
701+ last_stmt = use_stmt;
702 }
703
704 if (!types_compatible_p (half_type0, half_type1))
705@@ -506,7 +589,7 @@
706 vectype_out = get_vectype_for_scalar_type (type);
707 if (!vectype
708 || !vectype_out
709- || !supportable_widening_operation (WIDEN_MULT_EXPR, *last_stmt,
710+ || !supportable_widening_operation (WIDEN_MULT_EXPR, last_stmt,
711 vectype_out, vectype,
712 &dummy, &dummy, &dummy_code,
713 &dummy_code, &dummy_int, &dummy_vec))
714@@ -524,6 +607,7 @@
715 if (vect_print_dump_info (REPORT_DETAILS))
716 print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
717
718+ VEC_safe_push (gimple, heap, *stmts, last_stmt);
719 return pattern_stmt;
720 }
721
722@@ -555,16 +639,17 @@
723 */
724
725 static gimple
726-vect_recog_pow_pattern (gimple *last_stmt, tree *type_in, tree *type_out)
727+vect_recog_pow_pattern (VEC (gimple, heap) **stmts, tree *type_in, tree *type_out)
728 {
729+ gimple last_stmt = VEC_index (gimple, *stmts, 0);
730 tree fn, base, exp = NULL;
731 gimple stmt;
732 tree var;
733
734- if (!is_gimple_call (*last_stmt) || gimple_call_lhs (*last_stmt) == NULL)
735+ if (!is_gimple_call (last_stmt) || gimple_call_lhs (last_stmt) == NULL)
736 return NULL;
737
738- fn = gimple_call_fndecl (*last_stmt);
739+ fn = gimple_call_fndecl (last_stmt);
740 if (fn == NULL_TREE || DECL_BUILT_IN_CLASS (fn) != BUILT_IN_NORMAL)
741 return NULL;
742
743@@ -574,8 +659,8 @@
744 case BUILT_IN_POWI:
745 case BUILT_IN_POWF:
746 case BUILT_IN_POW:
747- base = gimple_call_arg (*last_stmt, 0);
748- exp = gimple_call_arg (*last_stmt, 1);
749+ base = gimple_call_arg (last_stmt, 0);
750+ exp = gimple_call_arg (last_stmt, 1);
751 if (TREE_CODE (exp) != REAL_CST
752 && TREE_CODE (exp) != INTEGER_CST)
753 return NULL;
754@@ -667,21 +752,23 @@
755 inner-loop nested in an outer-loop that us being vectorized). */
756
757 static gimple
758-vect_recog_widen_sum_pattern (gimple *last_stmt, tree *type_in, tree *type_out)
759+vect_recog_widen_sum_pattern (VEC (gimple, heap) **stmts, tree *type_in,
760+ tree *type_out)
761 {
762+ gimple last_stmt = VEC_index (gimple, *stmts, 0);
763 gimple stmt;
764 tree oprnd0, oprnd1;
765- stmt_vec_info stmt_vinfo = vinfo_for_stmt (*last_stmt);
766+ stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt);
767 tree type, half_type;
768 gimple pattern_stmt;
769 loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
770 struct loop *loop = LOOP_VINFO_LOOP (loop_info);
771 tree var;
772
773- if (!is_gimple_assign (*last_stmt))
774+ if (!is_gimple_assign (last_stmt))
775 return NULL;
776
777- type = gimple_expr_type (*last_stmt);
778+ type = gimple_expr_type (last_stmt);
779
780 /* Look for the following pattern
781 DX = (TYPE) X;
782@@ -693,25 +780,25 @@
783 /* Starting from LAST_STMT, follow the defs of its uses in search
784 of the above pattern. */
785
786- if (gimple_assign_rhs_code (*last_stmt) != PLUS_EXPR)
787+ if (gimple_assign_rhs_code (last_stmt) != PLUS_EXPR)
788 return NULL;
789
790 if (STMT_VINFO_DEF_TYPE (stmt_vinfo) != vect_reduction_def)
791 return NULL;
792
793- oprnd0 = gimple_assign_rhs1 (*last_stmt);
794- oprnd1 = gimple_assign_rhs2 (*last_stmt);
795+ oprnd0 = gimple_assign_rhs1 (last_stmt);
796+ oprnd1 = gimple_assign_rhs2 (last_stmt);
797 if (!types_compatible_p (TREE_TYPE (oprnd0), type)
798 || !types_compatible_p (TREE_TYPE (oprnd1), type))
799 return NULL;
800
801- /* So far so good. Since *last_stmt was detected as a (summation) reduction,
802+ /* So far so good. Since last_stmt was detected as a (summation) reduction,
803 we know that oprnd1 is the reduction variable (defined by a loop-header
804 phi), and oprnd0 is an ssa-name defined by a stmt in the loop body.
805 Left to check that oprnd0 is defined by a cast from type 'type' to type
806 'TYPE'. */
807
808- if (!widened_name_p (oprnd0, *last_stmt, &half_type, &stmt, true))
809+ if (!widened_name_p (oprnd0, last_stmt, &half_type, &stmt, true))
810 return NULL;
811
812 oprnd0 = gimple_assign_rhs1 (stmt);
813@@ -732,8 +819,9 @@
814
815 /* We don't allow changing the order of the computation in the inner-loop
816 when doing outer-loop vectorization. */
817- gcc_assert (!nested_in_vect_loop_p (loop, *last_stmt));
818+ gcc_assert (!nested_in_vect_loop_p (loop, last_stmt));
819
820+ VEC_safe_push (gimple, heap, *stmts, last_stmt);
821 return pattern_stmt;
822 }
823
824@@ -762,7 +850,7 @@
825
826 static void
827 vect_pattern_recog_1 (
828- gimple (* vect_recog_func) (gimple *, tree *, tree *),
829+ gimple (* vect_recog_func) (VEC (gimple, heap) **, tree *, tree *),
830 gimple_stmt_iterator si)
831 {
832 gimple stmt = gsi_stmt (si), pattern_stmt;
833@@ -774,12 +862,14 @@
834 enum tree_code code;
835 int i;
836 gimple next;
837+ VEC (gimple, heap) *stmts_to_replace = VEC_alloc (gimple, heap, 1);
838
839- pattern_stmt = (* vect_recog_func) (&stmt, &type_in, &type_out);
840+ VEC_quick_push (gimple, stmts_to_replace, stmt);
841+ pattern_stmt = (* vect_recog_func) (&stmts_to_replace, &type_in, &type_out);
842 if (!pattern_stmt)
843 return;
844
845- si = gsi_for_stmt (stmt);
846+ stmt = VEC_last (gimple, stmts_to_replace);
847 stmt_info = vinfo_for_stmt (stmt);
848 loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info);
849
850@@ -849,6 +939,35 @@
851 FOR_EACH_VEC_ELT (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i, next)
852 if (next == stmt)
853 VEC_ordered_remove (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i);
854+
855+ /* In case of widen-mult by a constant, it is possible that an additional
856+ pattern stmt is created and inserted in STMTS_TO_REPLACE. We create a
857+ stmt_info for it, and mark the relevant statements. */
858+ for (i = 0; VEC_iterate (gimple, stmts_to_replace, i, stmt)
859+ && (unsigned) i < (VEC_length (gimple, stmts_to_replace) - 1);
860+ i++)
861+ {
862+ stmt_info = vinfo_for_stmt (stmt);
863+ pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
864+ if (vect_print_dump_info (REPORT_DETAILS))
865+ {
866+ fprintf (vect_dump, "additional pattern stmt: ");
867+ print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
868+ }
869+
870+ set_vinfo_for_stmt (pattern_stmt,
871+ new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
872+ gimple_set_bb (pattern_stmt, gimple_bb (stmt));
873+ pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
874+
875+ STMT_VINFO_RELATED_STMT (pattern_stmt_info) = stmt;
876+ STMT_VINFO_DEF_TYPE (pattern_stmt_info)
877+ = STMT_VINFO_DEF_TYPE (stmt_info);
878+ STMT_VINFO_VECTYPE (pattern_stmt_info) = STMT_VINFO_VECTYPE (stmt_info);
879+ STMT_VINFO_IN_PATTERN_P (stmt_info) = true;
880+ }
881+
882+ VEC_free (gimple, heap, stmts_to_replace);
883 }
884
885
886@@ -896,10 +1015,8 @@
887
888 If vectorization succeeds, vect_transform_stmt will skip over {S1,S2,S3}
889 (because they are marked as irrelevant). It will vectorize S6, and record
890- a pointer to the new vector stmt VS6 both from S6 (as usual), and also
891- from S4. We do that so that when we get to vectorizing stmts that use the
892- def of S4 (like S5 that uses a_0), we'll know where to take the relevant
893- vector-def from. S4 will be skipped, and S5 will be vectorized as usual:
894+ a pointer to the new vector stmt VS6 from S6 (as usual).
895+ S4 will be skipped, and S5 will be vectorized as usual:
896
897 in_pattern_p related_stmt vec_stmt
898 S1: a_i = .... - - -
899@@ -915,7 +1032,21 @@
900 elsewhere), and we'll end up with:
901
902 VS6: va_new = ....
903- VS5: ... = ..vuse(va_new).. */
904+ VS5: ... = ..vuse(va_new)..
905+
906+ In case of more than one pattern statements, e.g., widen-mult with
907+ intermediate type:
908+
909+ S1 a_t = ;
910+ S2 a_T = (TYPE) a_t;
911+ '--> S3: a_it = (interm_type) a_t;
912+ S4 prod_T = a_T * CONST;
913+ '--> S5: prod_T' = a_it w* CONST;
914+
915+ there may be other users of a_T outside the pattern. In that case S2 will
916+ be marked as relevant (as well as S3), and both S2 and S3 will be analyzed
917+ and vectorized. The vector stmt VS2 will be recorded in S2, and VS3 will
918+ be recorded in S3. */
919
920 void
921 vect_pattern_recog (loop_vec_info loop_vinfo)
922@@ -925,7 +1056,7 @@
923 unsigned int nbbs = loop->num_nodes;
924 gimple_stmt_iterator si;
925 unsigned int i, j;
926- gimple (* vect_recog_func_ptr) (gimple *, tree *, tree *);
927+ gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
928
929 if (vect_print_dump_info (REPORT_DETAILS))
930 fprintf (vect_dump, "=== vect_pattern_recog ===");
931Index: gcc-4_6-branch/gcc/tree-vect-slp.c
932===================================================================
933--- gcc-4_6-branch.orig/gcc/tree-vect-slp.c 2012-01-09 15:02:15.000000000 -0800
934+++ gcc-4_6-branch/gcc/tree-vect-slp.c 2012-01-09 15:03:29.160918806 -0800
935@@ -152,7 +152,9 @@
936 if (loop && def_stmt && gimple_bb (def_stmt)
937 && flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
938 && vinfo_for_stmt (def_stmt)
939- && STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (def_stmt)))
940+ && STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (def_stmt))
941+ && !STMT_VINFO_RELEVANT (vinfo_for_stmt (def_stmt))
942+ && !STMT_VINFO_LIVE_P (vinfo_for_stmt (def_stmt)))
943 {
944 if (!*first_stmt_dt0)
945 *pattern0 = true;
946Index: gcc-4_6-branch/gcc/tree-vect-stmts.c
947===================================================================
948--- gcc-4_6-branch.orig/gcc/tree-vect-stmts.c 2012-01-09 15:02:15.000000000 -0800
949+++ gcc-4_6-branch/gcc/tree-vect-stmts.c 2012-01-09 15:06:23.636927250 -0800
950@@ -126,33 +126,72 @@
951
952 static void
953 vect_mark_relevant (VEC(gimple,heap) **worklist, gimple stmt,
954- enum vect_relevant relevant, bool live_p)
955+ enum vect_relevant relevant, bool live_p,
956+ bool used_in_pattern)
957 {
958 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
959 enum vect_relevant save_relevant = STMT_VINFO_RELEVANT (stmt_info);
960 bool save_live_p = STMT_VINFO_LIVE_P (stmt_info);
961+ gimple pattern_stmt;
962
963 if (vect_print_dump_info (REPORT_DETAILS))
964 fprintf (vect_dump, "mark relevant %d, live %d.", relevant, live_p);
965
966+ /* If this stmt is an original stmt in a pattern, we might need to mark its
967+ related pattern stmt instead of the original stmt. However, such stmts
968+ may have their own uses that are not in any pattern, in such cases the
969+ stmt itself should be marked. */
970 if (STMT_VINFO_IN_PATTERN_P (stmt_info))
971 {
972- gimple pattern_stmt;
973+ bool found = false;
974+ if (!used_in_pattern)
975+ {
976+ imm_use_iterator imm_iter;
977+ use_operand_p use_p;
978+ gimple use_stmt;
979+ tree lhs;
980+
981+ if (is_gimple_assign (stmt))
982+ lhs = gimple_assign_lhs (stmt);
983+ else
984+ lhs = gimple_call_lhs (stmt);
985+
986+ /* This use is out of pattern use, if LHS has other uses that are
987+ pattern uses, we should mark the stmt itself, and not the pattern
988+ stmt. */
989+ FOR_EACH_IMM_USE_FAST (use_p, imm_iter, lhs)
990+ {
991+ if (is_gimple_debug (USE_STMT (use_p)))
992+ continue;
993+ use_stmt = USE_STMT (use_p);
994+
995+ if (vinfo_for_stmt (use_stmt)
996+ && STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (use_stmt)))
997+ {
998+ found = true;
999+ break;
1000+ }
1001+ }
1002+ }
1003+
1004+ if (!found)
1005+ {
1006+ /* This is the last stmt in a sequence that was detected as a
1007+ pattern that can potentially be vectorized. Don't mark the stmt
1008+ as relevant/live because it's not going to be vectorized.
1009+ Instead mark the pattern-stmt that replaces it. */
1010+
1011+ pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
1012
1013- /* This is the last stmt in a sequence that was detected as a
1014- pattern that can potentially be vectorized. Don't mark the stmt
1015- as relevant/live because it's not going to be vectorized.
1016- Instead mark the pattern-stmt that replaces it. */
1017-
1018- pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
1019-
1020- if (vect_print_dump_info (REPORT_DETAILS))
1021- fprintf (vect_dump, "last stmt in pattern. don't mark relevant/live.");
1022- stmt_info = vinfo_for_stmt (pattern_stmt);
1023- gcc_assert (STMT_VINFO_RELATED_STMT (stmt_info) == stmt);
1024- save_relevant = STMT_VINFO_RELEVANT (stmt_info);
1025- save_live_p = STMT_VINFO_LIVE_P (stmt_info);
1026- stmt = pattern_stmt;
1027+ if (vect_print_dump_info (REPORT_DETAILS))
1028+ fprintf (vect_dump, "last stmt in pattern. don't mark"
1029+ " relevant/live.");
1030+ stmt_info = vinfo_for_stmt (pattern_stmt);
1031+ gcc_assert (STMT_VINFO_RELATED_STMT (stmt_info) == stmt);
1032+ save_relevant = STMT_VINFO_RELEVANT (stmt_info);
1033+ save_live_p = STMT_VINFO_LIVE_P (stmt_info);
1034+ stmt = pattern_stmt;
1035+ }
1036 }
1037
1038 STMT_VINFO_LIVE_P (stmt_info) |= live_p;
1039@@ -437,7 +476,8 @@
1040 }
1041 }
1042
1043- vect_mark_relevant (worklist, def_stmt, relevant, live_p);
1044+ vect_mark_relevant (worklist, def_stmt, relevant, live_p,
1045+ is_pattern_stmt_p (stmt_vinfo));
1046 return true;
1047 }
1048
1049@@ -494,7 +534,7 @@
1050 }
1051
1052 if (vect_stmt_relevant_p (phi, loop_vinfo, &relevant, &live_p))
1053- vect_mark_relevant (&worklist, phi, relevant, live_p);
1054+ vect_mark_relevant (&worklist, phi, relevant, live_p, false);
1055 }
1056 for (si = gsi_start_bb (bb); !gsi_end_p (si); gsi_next (&si))
1057 {
1058@@ -506,7 +546,7 @@
1059 }
1060
1061 if (vect_stmt_relevant_p (stmt, loop_vinfo, &relevant, &live_p))
1062- vect_mark_relevant (&worklist, stmt, relevant, live_p);
1063+ vect_mark_relevant (&worklist, stmt, relevant, live_p, false);
1064 }
1065 }
1066
1067@@ -613,42 +653,55 @@
1068 if (is_gimple_assign (stmt))
1069 {
1070 tree rhs = gimple_assign_rhs1 (stmt);
1071- if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt))
1072- == GIMPLE_SINGLE_RHS)
1073+ unsigned int op_num;
1074+ tree op;
1075+ switch (get_gimple_rhs_class (gimple_assign_rhs_code (stmt)))
1076 {
1077- unsigned int op_num = TREE_OPERAND_LENGTH (gimple_assign_rhs1
1078- (stmt));
1079- for (i = 0; i < op_num; i++)
1080- {
1081- tree op = TREE_OPERAND (rhs, i);
1082- if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
1083- &worklist))
1084+ case GIMPLE_SINGLE_RHS:
1085+ op_num = TREE_OPERAND_LENGTH (gimple_assign_rhs1 (stmt));
1086+ for (i = 0; i < op_num; i++)
1087 {
1088- VEC_free (gimple, heap, worklist);
1089- return false;
1090+ op = TREE_OPERAND (rhs, i);
1091+ if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
1092+ &worklist))
1093+ {
1094+ VEC_free (gimple, heap, worklist);
1095+ return false;
1096+ }
1097 }
1098- }
1099- }
1100- else if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt))
1101- == GIMPLE_BINARY_RHS)
1102- {
1103- tree op = gimple_assign_rhs1 (stmt);
1104- if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
1105- &worklist))
1106- {
1107- VEC_free (gimple, heap, worklist);
1108- return false;
1109- }
1110- op = gimple_assign_rhs2 (stmt);
1111- if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
1112- &worklist))
1113- {
1114- VEC_free (gimple, heap, worklist);
1115- return false;
1116- }
1117+ break;
1118+
1119+ case GIMPLE_BINARY_RHS:
1120+ op = gimple_assign_rhs1 (stmt);
1121+ if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
1122+ &worklist))
1123+ {
1124+ VEC_free (gimple, heap, worklist);
1125+ return false;
1126+ }
1127+ op = gimple_assign_rhs2 (stmt);
1128+ if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
1129+ &worklist))
1130+ {
1131+ VEC_free (gimple, heap, worklist);
1132+ return false;
1133+ }
1134+ break;
1135+
1136+ case GIMPLE_UNARY_RHS:
1137+ op = gimple_assign_rhs1 (stmt);
1138+ if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
1139+ &worklist))
1140+ {
1141+ VEC_free (gimple, heap, worklist);
1142+ return false;
1143+ }
1144+
1145+ break;
1146+
1147+ default:
1148+ return false;
1149 }
1150- else
1151- return false;
1152 }
1153 else if (is_gimple_call (stmt))
1154 {
1155@@ -1210,7 +1263,14 @@
1156
1157 /* Get the def from the vectorized stmt. */
1158 def_stmt_info = vinfo_for_stmt (def_stmt);
1159+
1160 vec_stmt = STMT_VINFO_VEC_STMT (def_stmt_info);
1161+ /* Get vectorized pattern statement. */
1162+ if (!vec_stmt
1163+ && STMT_VINFO_IN_PATTERN_P (def_stmt_info)
1164+ && !STMT_VINFO_RELEVANT (def_stmt_info))
1165+ vec_stmt = STMT_VINFO_VEC_STMT (vinfo_for_stmt (
1166+ STMT_VINFO_RELATED_STMT (def_stmt_info)));
1167 gcc_assert (vec_stmt);
1168 if (gimple_code (vec_stmt) == GIMPLE_PHI)
1169 vec_oprnd = PHI_RESULT (vec_stmt);
1170@@ -4894,6 +4954,7 @@
1171 enum vect_relevant relevance = STMT_VINFO_RELEVANT (stmt_info);
1172 bool ok;
1173 tree scalar_type, vectype;
1174+ gimple pattern_stmt;
1175
1176 if (vect_print_dump_info (REPORT_DETAILS))
1177 {
1178@@ -4915,16 +4976,22 @@
1179 - any LABEL_EXPRs in the loop
1180 - computations that are used only for array indexing or loop control.
1181 In basic blocks we only analyze statements that are a part of some SLP
1182- instance, therefore, all the statements are relevant. */
1183+ instance, therefore, all the statements are relevant.
1184+
1185+ Pattern statement need to be analyzed instead of the original statement
1186+ if the original statement is not relevant. Otherwise, we analyze both
1187+ statements. */
1188
1189+ pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
1190 if (!STMT_VINFO_RELEVANT_P (stmt_info)
1191 && !STMT_VINFO_LIVE_P (stmt_info))
1192 {
1193- gimple pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
1194 if (STMT_VINFO_IN_PATTERN_P (stmt_info)
1195+ && pattern_stmt
1196 && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
1197 || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
1198 {
1199+ /* Analyze PATTERN_STMT instead of the original stmt. */
1200 stmt = pattern_stmt;
1201 stmt_info = vinfo_for_stmt (pattern_stmt);
1202 if (vect_print_dump_info (REPORT_DETAILS))
1203@@ -4941,6 +5008,21 @@
1204 return true;
1205 }
1206 }
1207+ else if (STMT_VINFO_IN_PATTERN_P (stmt_info)
1208+ && pattern_stmt
1209+ && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_stmt))
1210+ || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
1211+ {
1212+ /* Analyze PATTERN_STMT too. */
1213+ if (vect_print_dump_info (REPORT_DETAILS))
1214+ {
1215+ fprintf (vect_dump, "==> examining pattern statement: ");
1216+ print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
1217+ }
1218+
1219+ if (!vect_analyze_stmt (pattern_stmt, need_to_vectorize, node))
1220+ return false;
1221+ }
1222
1223 switch (STMT_VINFO_DEF_TYPE (stmt_info))
1224 {
1225@@ -5074,7 +5156,6 @@
1226 bool is_store = false;
1227 gimple vec_stmt = NULL;
1228 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
1229- gimple orig_stmt_in_pattern;
1230 bool done;
1231
1232 switch (STMT_VINFO_TYPE (stmt_info))
1233@@ -5213,21 +5294,7 @@
1234 }
1235
1236 if (vec_stmt)
1237- {
1238 STMT_VINFO_VEC_STMT (stmt_info) = vec_stmt;
1239- orig_stmt_in_pattern = STMT_VINFO_RELATED_STMT (stmt_info);
1240- if (orig_stmt_in_pattern)
1241- {
1242- stmt_vec_info stmt_vinfo = vinfo_for_stmt (orig_stmt_in_pattern);
1243- /* STMT was inserted by the vectorizer to replace a computation idiom.
1244- ORIG_STMT_IN_PATTERN is a stmt in the original sequence that
1245- computed this idiom. We need to record a pointer to VEC_STMT in
1246- the stmt_info of ORIG_STMT_IN_PATTERN. See more details in the
1247- documentation of vect_pattern_recog. */
1248- if (STMT_VINFO_IN_PATTERN_P (stmt_vinfo))
1249- STMT_VINFO_VEC_STMT (stmt_vinfo) = vec_stmt;
1250- }
1251- }
1252
1253 return is_store;
1254 }
1255@@ -5605,8 +5672,12 @@
1256 || *dt == vect_nested_cycle)
1257 {
1258 stmt_vec_info stmt_info = vinfo_for_stmt (*def_stmt);
1259- if (STMT_VINFO_IN_PATTERN_P (stmt_info))
1260+
1261+ if (STMT_VINFO_IN_PATTERN_P (stmt_info)
1262+ && !STMT_VINFO_RELEVANT (stmt_info)
1263+ && !STMT_VINFO_LIVE_P (stmt_info))
1264 stmt_info = vinfo_for_stmt (STMT_VINFO_RELATED_STMT (stmt_info));
1265+
1266 *vectype = STMT_VINFO_VECTYPE (stmt_info);
1267 gcc_assert (*vectype != NULL_TREE);
1268 }
1269Index: gcc-4_6-branch/gcc/tree-vectorizer.h
1270===================================================================
1271--- gcc-4_6-branch.orig/gcc/tree-vectorizer.h 2012-01-09 15:02:15.000000000 -0800
1272+++ gcc-4_6-branch/gcc/tree-vectorizer.h 2012-01-09 15:03:29.164918806 -0800
1273@@ -890,7 +890,7 @@
1274 /* Pattern recognition functions.
1275 Additional pattern recognition functions can (and will) be added
1276 in the future. */
1277-typedef gimple (* vect_recog_func_ptr) (gimple *, tree *, tree *);
1278+typedef gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
1279 #define NUM_PATTERNS 4
1280 void vect_pattern_recog (loop_vec_info);
1281
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106770.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106770.patch
deleted file mode 100644
index 82ae3a132..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106770.patch
+++ /dev/null
@@ -1,138 +0,0 @@
12011-07-11 Revital Eres <revital.eres@linaro.org>
2
3 Backport from mainline -r175090.
4 gcc/
5 * ddg.c (add_intra_loop_mem_dep): New function.
6 (build_intra_loop_deps): Call it.
7
8 gcc/testsuite
9 * gcc.dg/sms-9.c: New file.
10
11=== modified file 'gcc/ddg.c'
12--- old/gcc/ddg.c 2011-05-13 16:03:40 +0000
13+++ new/gcc/ddg.c 2011-07-04 11:00:06 +0000
14@@ -390,6 +390,33 @@
15 &PATTERN (insn2));
16 }
17
18+/* Given two nodes, analyze their RTL insns and add intra-loop mem deps
19+ to ddg G. */
20+static void
21+add_intra_loop_mem_dep (ddg_ptr g, ddg_node_ptr from, ddg_node_ptr to)
22+{
23+
24+ if ((from->cuid == to->cuid)
25+ || !insns_may_alias_p (from->insn, to->insn))
26+ /* Do not create edge if memory references have disjoint alias sets
27+ or 'to' and 'from' are the same instruction. */
28+ return;
29+
30+ if (mem_write_insn_p (from->insn))
31+ {
32+ if (mem_read_insn_p (to->insn))
33+ create_ddg_dep_no_link (g, from, to,
34+ DEBUG_INSN_P (to->insn)
35+ ? ANTI_DEP : TRUE_DEP, MEM_DEP, 0);
36+ else
37+ create_ddg_dep_no_link (g, from, to,
38+ DEBUG_INSN_P (to->insn)
39+ ? ANTI_DEP : OUTPUT_DEP, MEM_DEP, 0);
40+ }
41+ else if (!mem_read_insn_p (to->insn))
42+ create_ddg_dep_no_link (g, from, to, ANTI_DEP, MEM_DEP, 0);
43+}
44+
45 /* Given two nodes, analyze their RTL insns and add inter-loop mem deps
46 to ddg G. */
47 static void
48@@ -477,10 +504,22 @@
49 if (DEBUG_INSN_P (j_node->insn))
50 continue;
51 if (mem_access_insn_p (j_node->insn))
52- /* Don't bother calculating inter-loop dep if an intra-loop dep
53- already exists. */
54+ {
55+ /* Don't bother calculating inter-loop dep if an intra-loop dep
56+ already exists. */
57 if (! TEST_BIT (dest_node->successors, j))
58 add_inter_loop_mem_dep (g, dest_node, j_node);
59+ /* If -fmodulo-sched-allow-regmoves
60+ is set certain anti-dep edges are not created.
61+ It might be that these anti-dep edges are on the
62+ path from one memory instruction to another such that
63+ removing these edges could cause a violation of the
64+ memory dependencies. Thus we add intra edges between
65+ every two memory instructions in this case. */
66+ if (flag_modulo_sched_allow_regmoves
67+ && !TEST_BIT (dest_node->predecessors, j))
68+ add_intra_loop_mem_dep (g, j_node, dest_node);
69+ }
70 }
71 }
72 }
73
74=== added file 'gcc/testsuite/gcc.dg/sms-9.c'
75--- old/gcc/testsuite/gcc.dg/sms-9.c 1970-01-01 00:00:00 +0000
76+++ new/gcc/testsuite/gcc.dg/sms-9.c 2011-07-04 11:00:06 +0000
77@@ -0,0 +1,60 @@
78+/* { dg-do run } */
79+/* { dg-options "-O2 -fmodulo-sched -fno-auto-inc-dec -O2 -fmodulo-sched-allow-regmoves" } */
80+
81+#include <stdlib.h>
82+#include <stdarg.h>
83+
84+struct df_ref_info
85+{
86+ unsigned int *begin;
87+ unsigned int *count;
88+};
89+
90+extern void *memset (void *s, int c, __SIZE_TYPE__ n);
91+
92+
93+__attribute__ ((noinline))
94+ int
95+ df_reorganize_refs_by_reg_by_insn (struct df_ref_info *ref_info,
96+ int num, unsigned int start)
97+{
98+ unsigned int m = num;
99+ unsigned int offset = 77;
100+ unsigned int r;
101+
102+ for (r = start; r < m; r++)
103+ {
104+ ref_info->begin[r] = offset;
105+ offset += ref_info->count[r];
106+ ref_info->count[r] = 0;
107+ }
108+
109+ return offset;
110+}
111+
112+int
113+main ()
114+{
115+ struct df_ref_info temp;
116+ int num = 100;
117+ unsigned int start = 5;
118+ int i, offset;
119+
120+ temp.begin = malloc (100 * sizeof (unsigned int));
121+ temp.count = malloc (100 * sizeof (unsigned int));
122+
123+ memset (temp.begin, 0, sizeof (unsigned int) * num);
124+ memset (temp.count, 0, sizeof (unsigned int) * num);
125+
126+ for (i = 0; i < num; i++)
127+ temp.count[i] = i + 1;
128+
129+ offset = df_reorganize_refs_by_reg_by_insn (&temp, num, start);
130+
131+ if (offset != 5112)
132+ abort ();
133+
134+ free (temp.begin);
135+ free (temp.count);
136+ return 0;
137+}
138
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106771.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106771.patch
deleted file mode 100644
index 70c8638cd..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106771.patch
+++ /dev/null
@@ -1,211 +0,0 @@
12011-07-11 Revital Eres <revital.eres@linaro.org>
2
3 Backport from mainline -r175091
4 gcc/
5 * modulo-sched.c (struct ps_insn): Remove row_rest_count
6 field.
7 (struct partial_schedule): Add rows_length field.
8 (verify_partial_schedule): Check rows_length.
9 (ps_insert_empty_row): Handle rows_length.
10 (create_partial_schedule): Likewise.
11 (free_partial_schedule): Likewise.
12 (reset_partial_schedule): Likewise.
13 (create_ps_insn): Remove rest_count argument.
14 (remove_node_from_ps): Update rows_length.
15 (add_node_to_ps): Update rows_length and call create_ps_insn without
16 passing row_rest_count.
17 (rotate_partial_schedule): Update rows_length.
18
19=== modified file 'gcc/modulo-sched.c'
20--- old/gcc/modulo-sched.c 2011-05-13 16:03:40 +0000
21+++ new/gcc/modulo-sched.c 2011-07-04 12:01:34 +0000
22@@ -134,8 +134,6 @@
23 ps_insn_ptr next_in_row,
24 prev_in_row;
25
26- /* The number of nodes in the same row that come after this node. */
27- int row_rest_count;
28 };
29
30 /* Holds the partial schedule as an array of II rows. Each entry of the
31@@ -149,6 +147,12 @@
32 /* rows[i] points to linked list of insns scheduled in row i (0<=i<ii). */
33 ps_insn_ptr *rows;
34
35+ /* rows_length[i] holds the number of instructions in the row.
36+ It is used only (as an optimization) to back off quickly from
37+ trying to schedule a node in a full row; that is, to avoid running
38+ through futile DFA state transitions. */
39+ int *rows_length;
40+
41 /* The earliest absolute cycle of an insn in the partial schedule. */
42 int min_cycle;
43
44@@ -1907,6 +1911,7 @@
45 int ii = ps->ii;
46 int new_ii = ii + 1;
47 int row;
48+ int *rows_length_new;
49
50 verify_partial_schedule (ps, sched_nodes);
51
52@@ -1921,9 +1926,11 @@
53 rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
54
55 rows_new = (ps_insn_ptr *) xcalloc (new_ii, sizeof (ps_insn_ptr));
56+ rows_length_new = (int *) xcalloc (new_ii, sizeof (int));
57 for (row = 0; row < split_row; row++)
58 {
59 rows_new[row] = ps->rows[row];
60+ rows_length_new[row] = ps->rows_length[row];
61 ps->rows[row] = NULL;
62 for (crr_insn = rows_new[row];
63 crr_insn; crr_insn = crr_insn->next_in_row)
64@@ -1944,6 +1951,7 @@
65 for (row = split_row; row < ii; row++)
66 {
67 rows_new[row + 1] = ps->rows[row];
68+ rows_length_new[row + 1] = ps->rows_length[row];
69 ps->rows[row] = NULL;
70 for (crr_insn = rows_new[row + 1];
71 crr_insn; crr_insn = crr_insn->next_in_row)
72@@ -1965,6 +1973,8 @@
73 + (SMODULO (ps->max_cycle, ii) >= split_row ? 1 : 0);
74 free (ps->rows);
75 ps->rows = rows_new;
76+ free (ps->rows_length);
77+ ps->rows_length = rows_length_new;
78 ps->ii = new_ii;
79 gcc_assert (ps->min_cycle >= 0);
80
81@@ -2040,16 +2050,23 @@
82 ps_insn_ptr crr_insn;
83
84 for (row = 0; row < ps->ii; row++)
85- for (crr_insn = ps->rows[row]; crr_insn; crr_insn = crr_insn->next_in_row)
86- {
87- ddg_node_ptr u = crr_insn->node;
88-
89- gcc_assert (TEST_BIT (sched_nodes, u->cuid));
90- /* ??? Test also that all nodes of sched_nodes are in ps, perhaps by
91- popcount (sched_nodes) == number of insns in ps. */
92- gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
93- gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
94- }
95+ {
96+ int length = 0;
97+
98+ for (crr_insn = ps->rows[row]; crr_insn; crr_insn = crr_insn->next_in_row)
99+ {
100+ ddg_node_ptr u = crr_insn->node;
101+
102+ length++;
103+ gcc_assert (TEST_BIT (sched_nodes, u->cuid));
104+ /* ??? Test also that all nodes of sched_nodes are in ps, perhaps by
105+ popcount (sched_nodes) == number of insns in ps. */
106+ gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
107+ gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
108+ }
109+
110+ gcc_assert (ps->rows_length[row] == length);
111+ }
112 }
113
114
115@@ -2455,6 +2472,7 @@
116 {
117 partial_schedule_ptr ps = XNEW (struct partial_schedule);
118 ps->rows = (ps_insn_ptr *) xcalloc (ii, sizeof (ps_insn_ptr));
119+ ps->rows_length = (int *) xcalloc (ii, sizeof (int));
120 ps->ii = ii;
121 ps->history = history;
122 ps->min_cycle = INT_MAX;
123@@ -2493,6 +2511,7 @@
124 return;
125 free_ps_insns (ps);
126 free (ps->rows);
127+ free (ps->rows_length);
128 free (ps);
129 }
130
131@@ -2510,6 +2529,8 @@
132 ps->rows = (ps_insn_ptr *) xrealloc (ps->rows, new_ii
133 * sizeof (ps_insn_ptr));
134 memset (ps->rows, 0, new_ii * sizeof (ps_insn_ptr));
135+ ps->rows_length = (int *) xrealloc (ps->rows_length, new_ii * sizeof (int));
136+ memset (ps->rows_length, 0, new_ii * sizeof (int));
137 ps->ii = new_ii;
138 ps->min_cycle = INT_MAX;
139 ps->max_cycle = INT_MIN;
140@@ -2538,14 +2559,13 @@
141
142 /* Creates an object of PS_INSN and initializes it to the given parameters. */
143 static ps_insn_ptr
144-create_ps_insn (ddg_node_ptr node, int rest_count, int cycle)
145+create_ps_insn (ddg_node_ptr node, int cycle)
146 {
147 ps_insn_ptr ps_i = XNEW (struct ps_insn);
148
149 ps_i->node = node;
150 ps_i->next_in_row = NULL;
151 ps_i->prev_in_row = NULL;
152- ps_i->row_rest_count = rest_count;
153 ps_i->cycle = cycle;
154
155 return ps_i;
156@@ -2578,6 +2598,8 @@
157 if (ps_i->next_in_row)
158 ps_i->next_in_row->prev_in_row = ps_i->prev_in_row;
159 }
160+
161+ ps->rows_length[row] -= 1;
162 free (ps_i);
163 return true;
164 }
165@@ -2734,17 +2756,12 @@
166 sbitmap must_precede, sbitmap must_follow)
167 {
168 ps_insn_ptr ps_i;
169- int rest_count = 1;
170 int row = SMODULO (cycle, ps->ii);
171
172- if (ps->rows[row]
173- && ps->rows[row]->row_rest_count >= issue_rate)
174+ if (ps->rows_length[row] >= issue_rate)
175 return NULL;
176
177- if (ps->rows[row])
178- rest_count += ps->rows[row]->row_rest_count;
179-
180- ps_i = create_ps_insn (node, rest_count, cycle);
181+ ps_i = create_ps_insn (node, cycle);
182
183 /* Finds and inserts PS_I according to MUST_FOLLOW and
184 MUST_PRECEDE. */
185@@ -2754,6 +2771,7 @@
186 return NULL;
187 }
188
189+ ps->rows_length[row] += 1;
190 return ps_i;
191 }
192
193@@ -2909,11 +2927,16 @@
194 for (i = 0; i < backward_rotates; i++)
195 {
196 ps_insn_ptr first_row = ps->rows[0];
197+ int first_row_length = ps->rows_length[0];
198
199 for (row = 0; row < last_row; row++)
200- ps->rows[row] = ps->rows[row+1];
201+ {
202+ ps->rows[row] = ps->rows[row + 1];
203+ ps->rows_length[row] = ps->rows_length[row + 1];
204+ }
205
206 ps->rows[last_row] = first_row;
207+ ps->rows_length[last_row] = first_row_length;
208 }
209
210 ps->max_cycle -= start_cycle;
211
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106772.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106772.patch
deleted file mode 100644
index d918f9c58..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106772.patch
+++ /dev/null
@@ -1,350 +0,0 @@
12011-07-11 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 gcc/
4 2011-06-22 Dmitry Plotnikov <dplotnikov@ispras.ru>
5 Dmitry Melnik <dm@ispras.ru>
6
7 * config/arm/arm.c (neon_immediate_valid_for_shift): New function.
8 (neon_output_shift_immediate): Ditto.
9 * config/arm/arm-protos.h (neon_immediate_valid_for_shift): New
10 prototype.
11 (neon_output_shift_immediate): Ditto.
12 * config/arm/neon.md (vashl<mode>3): Modified constraint.
13 (vashr<mode>3_imm): New insn pattern.
14 (vlshr<mode>3_imm): Ditto.
15 (vashr<mode>3): Modified constraint.
16 (vlshr<mode>3): Ditto.
17 * config/arm/predicates.md (imm_for_neon_lshift_operand): New
18 predicate.
19 (imm_for_neon_rshift_operand): Ditto.
20 (imm_lshift_or_reg_neon): Ditto.
21 (imm_rshift_or_reg_neon): Ditto.
22
23 * optabs.c (init_optabs): Init optab codes for vashl, vashr, vlshr.
24
25=== modified file 'gcc/config/arm/arm-protos.h'
26--- old/gcc/config/arm/arm-protos.h 2011-06-14 16:00:30 +0000
27+++ new/gcc/config/arm/arm-protos.h 2011-07-04 14:03:49 +0000
28@@ -64,8 +64,12 @@
29 extern int neon_immediate_valid_for_move (rtx, enum machine_mode, rtx *, int *);
30 extern int neon_immediate_valid_for_logic (rtx, enum machine_mode, int, rtx *,
31 int *);
32+extern int neon_immediate_valid_for_shift (rtx, enum machine_mode, rtx *,
33+ int *, bool);
34 extern char *neon_output_logic_immediate (const char *, rtx *,
35 enum machine_mode, int, int);
36+extern char *neon_output_shift_immediate (const char *, char, rtx *,
37+ enum machine_mode, int, bool);
38 extern void neon_pairwise_reduce (rtx, rtx, enum machine_mode,
39 rtx (*) (rtx, rtx, rtx));
40 extern rtx neon_make_constant (rtx);
41
42=== modified file 'gcc/config/arm/arm.c'
43--- old/gcc/config/arm/arm.c 2011-06-29 09:13:17 +0000
44+++ new/gcc/config/arm/arm.c 2011-07-04 14:03:49 +0000
45@@ -8863,6 +8863,66 @@
46 return 1;
47 }
48
49+/* Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction. If
50+ the immediate is valid, write a constant suitable for using as an operand
51+ to VSHR/VSHL to *MODCONST and the corresponding element width to
52+ *ELEMENTWIDTH. ISLEFTSHIFT is for determine left or right shift,
53+ because they have different limitations. */
54+
55+int
56+neon_immediate_valid_for_shift (rtx op, enum machine_mode mode,
57+ rtx *modconst, int *elementwidth,
58+ bool isleftshift)
59+{
60+ unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
61+ unsigned int n_elts = CONST_VECTOR_NUNITS (op), i;
62+ unsigned HOST_WIDE_INT last_elt = 0;
63+ unsigned HOST_WIDE_INT maxshift;
64+
65+ /* Split vector constant out into a byte vector. */
66+ for (i = 0; i < n_elts; i++)
67+ {
68+ rtx el = CONST_VECTOR_ELT (op, i);
69+ unsigned HOST_WIDE_INT elpart;
70+
71+ if (GET_CODE (el) == CONST_INT)
72+ elpart = INTVAL (el);
73+ else if (GET_CODE (el) == CONST_DOUBLE)
74+ return 0;
75+ else
76+ gcc_unreachable ();
77+
78+ if (i != 0 && elpart != last_elt)
79+ return 0;
80+
81+ last_elt = elpart;
82+ }
83+
84+ /* Shift less than element size. */
85+ maxshift = innersize * 8;
86+
87+ if (isleftshift)
88+ {
89+ /* Left shift immediate value can be from 0 to <size>-1. */
90+ if (last_elt >= maxshift)
91+ return 0;
92+ }
93+ else
94+ {
95+ /* Right shift immediate value can be from 1 to <size>. */
96+ if (last_elt == 0 || last_elt > maxshift)
97+ return 0;
98+ }
99+
100+ if (elementwidth)
101+ *elementwidth = innersize * 8;
102+
103+ if (modconst)
104+ *modconst = CONST_VECTOR_ELT (op, 0);
105+
106+ return 1;
107+}
108+
109 /* Return a string suitable for output of Neon immediate logic operation
110 MNEM. */
111
112@@ -8885,6 +8945,28 @@
113 return templ;
114 }
115
116+/* Return a string suitable for output of Neon immediate shift operation
117+ (VSHR or VSHL) MNEM. */
118+
119+char *
120+neon_output_shift_immediate (const char *mnem, char sign, rtx *op2,
121+ enum machine_mode mode, int quad,
122+ bool isleftshift)
123+{
124+ int width, is_valid;
125+ static char templ[40];
126+
127+ is_valid = neon_immediate_valid_for_shift (*op2, mode, op2, &width, isleftshift);
128+ gcc_assert (is_valid != 0);
129+
130+ if (quad)
131+ sprintf (templ, "%s.%c%d\t%%q0, %%q1, %%2", mnem, sign, width);
132+ else
133+ sprintf (templ, "%s.%c%d\t%%P0, %%P1, %%2", mnem, sign, width);
134+
135+ return templ;
136+}
137+
138 /* Output a sequence of pairwise operations to implement a reduction.
139 NOTE: We do "too much work" here, because pairwise operations work on two
140 registers-worth of operands in one go. Unfortunately we can't exploit those
141
142=== modified file 'gcc/config/arm/neon.md'
143--- old/gcc/config/arm/neon.md 2011-07-01 09:19:21 +0000
144+++ new/gcc/config/arm/neon.md 2011-07-04 14:03:49 +0000
145@@ -956,15 +956,57 @@
146 ; SImode elements.
147
148 (define_insn "vashl<mode>3"
149- [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
150- (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
151- (match_operand:VDQIW 2 "s_register_operand" "w")))]
152- "TARGET_NEON"
153- "vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
154- [(set (attr "neon_type")
155- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
156- (const_string "neon_vshl_ddd")
157- (const_string "neon_shift_3")))]
158+ [(set (match_operand:VDQIW 0 "s_register_operand" "=w,w")
159+ (ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w,w")
160+ (match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dn")))]
161+ "TARGET_NEON"
162+ {
163+ switch (which_alternative)
164+ {
165+ case 0: return "vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2";
166+ case 1: return neon_output_shift_immediate ("vshl", 'i', &operands[2],
167+ <MODE>mode,
168+ VALID_NEON_QREG_MODE (<MODE>mode),
169+ true);
170+ default: gcc_unreachable ();
171+ }
172+ }
173+ [(set (attr "neon_type")
174+ (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
175+ (const_string "neon_vshl_ddd")
176+ (const_string "neon_shift_3")))]
177+)
178+
179+(define_insn "vashr<mode>3_imm"
180+ [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
181+ (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
182+ (match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dn")))]
183+ "TARGET_NEON"
184+ {
185+ return neon_output_shift_immediate ("vshr", 's', &operands[2],
186+ <MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode),
187+ false);
188+ }
189+ [(set (attr "neon_type")
190+ (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
191+ (const_string "neon_vshl_ddd")
192+ (const_string "neon_shift_3")))]
193+)
194+
195+(define_insn "vlshr<mode>3_imm"
196+ [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
197+ (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
198+ (match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dn")))]
199+ "TARGET_NEON"
200+ {
201+ return neon_output_shift_immediate ("vshr", 'u', &operands[2],
202+ <MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode),
203+ false);
204+ }
205+ [(set (attr "neon_type")
206+ (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
207+ (const_string "neon_vshl_ddd")
208+ (const_string "neon_shift_3")))]
209 )
210
211 ; Used for implementing logical shift-right, which is a left-shift by a negative
212@@ -1004,28 +1046,34 @@
213 (define_expand "vashr<mode>3"
214 [(set (match_operand:VDQIW 0 "s_register_operand" "")
215 (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
216- (match_operand:VDQIW 2 "s_register_operand" "")))]
217+ (match_operand:VDQIW 2 "imm_rshift_or_reg_neon" "")))]
218 "TARGET_NEON"
219 {
220 rtx neg = gen_reg_rtx (<MODE>mode);
221-
222- emit_insn (gen_neg<mode>2 (neg, operands[2]));
223- emit_insn (gen_ashl<mode>3_signed (operands[0], operands[1], neg));
224-
225+ if (REG_P (operands[2]))
226+ {
227+ emit_insn (gen_neg<mode>2 (neg, operands[2]));
228+ emit_insn (gen_ashl<mode>3_signed (operands[0], operands[1], neg));
229+ }
230+ else
231+ emit_insn (gen_vashr<mode>3_imm (operands[0], operands[1], operands[2]));
232 DONE;
233 })
234
235 (define_expand "vlshr<mode>3"
236 [(set (match_operand:VDQIW 0 "s_register_operand" "")
237 (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "")
238- (match_operand:VDQIW 2 "s_register_operand" "")))]
239+ (match_operand:VDQIW 2 "imm_rshift_or_reg_neon" "")))]
240 "TARGET_NEON"
241 {
242 rtx neg = gen_reg_rtx (<MODE>mode);
243-
244- emit_insn (gen_neg<mode>2 (neg, operands[2]));
245- emit_insn (gen_ashl<mode>3_unsigned (operands[0], operands[1], neg));
246-
247+ if (REG_P (operands[2]))
248+ {
249+ emit_insn (gen_neg<mode>2 (neg, operands[2]));
250+ emit_insn (gen_ashl<mode>3_unsigned (operands[0], operands[1], neg));
251+ }
252+ else
253+ emit_insn (gen_vlshr<mode>3_imm (operands[0], operands[1], operands[2]));
254 DONE;
255 })
256
257
258=== modified file 'gcc/config/arm/predicates.md'
259--- old/gcc/config/arm/predicates.md 2011-06-22 15:50:23 +0000
260+++ new/gcc/config/arm/predicates.md 2011-07-04 14:03:49 +0000
261@@ -585,6 +585,26 @@
262 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
263 })
264
265+(define_predicate "imm_for_neon_lshift_operand"
266+ (match_code "const_vector")
267+{
268+ return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
269+})
270+
271+(define_predicate "imm_for_neon_rshift_operand"
272+ (match_code "const_vector")
273+{
274+ return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
275+})
276+
277+(define_predicate "imm_lshift_or_reg_neon"
278+ (ior (match_operand 0 "s_register_operand")
279+ (match_operand 0 "imm_for_neon_lshift_operand")))
280+
281+(define_predicate "imm_rshift_or_reg_neon"
282+ (ior (match_operand 0 "s_register_operand")
283+ (match_operand 0 "imm_for_neon_rshift_operand")))
284+
285 (define_predicate "imm_for_neon_logic_operand"
286 (match_code "const_vector")
287 {
288
289=== modified file 'gcc/optabs.c'
290--- old/gcc/optabs.c 2011-03-04 10:27:10 +0000
291+++ new/gcc/optabs.c 2011-07-04 14:03:49 +0000
292@@ -6171,6 +6171,9 @@
293 init_optab (usashl_optab, US_ASHIFT);
294 init_optab (ashr_optab, ASHIFTRT);
295 init_optab (lshr_optab, LSHIFTRT);
296+ init_optabv (vashl_optab, ASHIFT);
297+ init_optabv (vashr_optab, ASHIFTRT);
298+ init_optabv (vlshr_optab, LSHIFTRT);
299 init_optab (rotl_optab, ROTATE);
300 init_optab (rotr_optab, ROTATERT);
301 init_optab (smin_optab, SMIN);
302
303=== added file 'gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c'
304--- old/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c 1970-01-01 00:00:00 +0000
305+++ new/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c 2011-07-04 14:03:49 +0000
306@@ -0,0 +1,11 @@
307+/* { dg-do compile } */
308+/* { dg-require-effective-target arm_neon_ok } */
309+/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
310+/* { dg-final { scan-assembler "vshr\.u32.*#3" } } */
311+
312+/* Verify that VSHR immediate is used. */
313+void f1(int n, unsigned int x[], unsigned int y[]) {
314+ int i;
315+ for (i = 0; i < n; ++i)
316+ y[i] = x[i] >> 3;
317+}
318
319=== added file 'gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c'
320--- old/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c 1970-01-01 00:00:00 +0000
321+++ new/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c 2011-07-04 14:03:49 +0000
322@@ -0,0 +1,11 @@
323+/* { dg-do compile } */
324+/* { dg-require-effective-target arm_neon_ok } */
325+/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
326+/* { dg-final { scan-assembler "vshl\.i32.*#3" } } */
327+
328+/* Verify that VSHR immediate is used. */
329+void f1(int n, int x[], int y[]) {
330+ int i;
331+ for (i = 0; i < n; ++i)
332+ y[i] = x[i] << 3;
333+}
334
335=== added file 'gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c'
336--- old/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c 1970-01-01 00:00:00 +0000
337+++ new/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c 2011-07-04 14:03:49 +0000
338@@ -0,0 +1,11 @@
339+/* { dg-do compile } */
340+/* { dg-require-effective-target arm_neon_ok } */
341+/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
342+/* { dg-final { scan-assembler "vshr\.s32.*#3" } } */
343+
344+/* Verify that VSHR immediate is used. */
345+void f1(int n, int x[], int y[]) {
346+ int i;
347+ for (i = 0; i < n; ++i)
348+ y[i] = x[i] >> 3;
349+}
350
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106773.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106773.patch
deleted file mode 100644
index de3f29e19..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106773.patch
+++ /dev/null
@@ -1,119 +0,0 @@
12011-07-13 Richard Sandiford <richard.sandiford@linaro.org>
2
3 Backport from mainline:
4 gcc/
5 2011-07-07 Richard Sandiford <richard.sandiford@linaro.org>
6
7 * reload1.c (choose_reload_regs): Use mode sizes to check whether
8 an old reload register completely defines the required value.
9
10 gcc/testsuite/
11 2011-07-07 Richard Sandiford <richard.sandiford@linaro.org>
12
13 * gcc.target/arm/neon-modes-3.c: New test.
14
15=== modified file 'gcc/reload1.c'
16--- old/gcc/reload1.c 2011-07-01 09:19:21 +0000
17+++ new/gcc/reload1.c 2011-07-11 10:06:50 +0000
18@@ -6451,6 +6451,8 @@
19
20 if (regno >= 0
21 && reg_last_reload_reg[regno] != 0
22+ && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
23+ >= GET_MODE_SIZE (mode) + byte)
24 #ifdef CANNOT_CHANGE_MODE_CLASS
25 /* Verify that the register it's in can be used in
26 mode MODE. */
27@@ -6462,24 +6464,12 @@
28 {
29 enum reg_class rclass = rld[r].rclass, last_class;
30 rtx last_reg = reg_last_reload_reg[regno];
31- enum machine_mode need_mode;
32
33 i = REGNO (last_reg);
34 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
35 last_class = REGNO_REG_CLASS (i);
36
37- if (byte == 0)
38- need_mode = mode;
39- else
40- need_mode
41- = smallest_mode_for_size
42- (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
43- GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
44- ? MODE_INT : GET_MODE_CLASS (mode));
45-
46- if ((GET_MODE_SIZE (GET_MODE (last_reg))
47- >= GET_MODE_SIZE (need_mode))
48- && reg_reloaded_contents[i] == regno
49+ if (reg_reloaded_contents[i] == regno
50 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
51 && HARD_REGNO_MODE_OK (i, rld[r].mode)
52 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
53
54=== added file 'gcc/testsuite/gcc.target/arm/neon-modes-3.c'
55--- old/gcc/testsuite/gcc.target/arm/neon-modes-3.c 1970-01-01 00:00:00 +0000
56+++ new/gcc/testsuite/gcc.target/arm/neon-modes-3.c 2011-07-11 10:06:50 +0000
57@@ -0,0 +1,61 @@
58+/* { dg-do compile } */
59+/* { dg-require-effective-target arm_neon_ok } */
60+/* { dg-options "-O" } */
61+/* { dg-add-options arm_neon } */
62+
63+#include <arm_neon.h>
64+
65+void f1 (volatile float32x4_t *dest, volatile float32x4x4_t *src, int n)
66+{
67+ float32x4x4_t a5, a6, a7, a8, a9;
68+ int i;
69+
70+ a5 = *src;
71+ a6 = *src;
72+ a7 = *src;
73+ a8 = *src;
74+ a9 = *src;
75+ while (n--)
76+ {
77+ for (i = 0; i < 8; i++)
78+ {
79+ float32x4x4_t a0, a1, a2, a3, a4;
80+
81+ a0 = *src;
82+ a1 = *src;
83+ a2 = *src;
84+ a3 = *src;
85+ a4 = *src;
86+ *src = a0;
87+ *dest = a0.val[0];
88+ *dest = a0.val[3];
89+ *src = a1;
90+ *dest = a1.val[0];
91+ *dest = a1.val[3];
92+ *src = a2;
93+ *dest = a2.val[0];
94+ *dest = a2.val[3];
95+ *src = a3;
96+ *dest = a3.val[0];
97+ *dest = a3.val[3];
98+ *src = a4;
99+ *dest = a4.val[0];
100+ *dest = a4.val[3];
101+ }
102+ *src = a5;
103+ *dest = a5.val[0];
104+ *dest = a5.val[3];
105+ *src = a6;
106+ *dest = a6.val[0];
107+ *dest = a6.val[3];
108+ *src = a7;
109+ *dest = a7.val[0];
110+ *dest = a7.val[3];
111+ *src = a8;
112+ *dest = a8.val[0];
113+ *dest = a8.val[3];
114+ *src = a9;
115+ *dest = a9.val[0];
116+ *dest = a9.val[3];
117+ }
118+}
119
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106775.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106775.patch
deleted file mode 100644
index 0b05c3824..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106775.patch
+++ /dev/null
@@ -1,67 +0,0 @@
12011-07-15 Michael Hope <michael.hope@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-04-05 Eric Botcazou <ebotcazou@adacore.com>
7
8 * ifcvt.c (cond_exec_process_insns): Disallow converting a block
9 that contains the prologue.
10
11 gcc/testsuite/
12 Backport from mainline:
13
14 2011-04-01 Bernd Schmidt <bernds@codesourcery.com>
15
16 * gcc.c-torture/compile/20110401-1.c: New test.
17
18=== modified file 'gcc/ifcvt.c'
19--- old/gcc/ifcvt.c 2010-12-14 00:23:40 +0000
20+++ new/gcc/ifcvt.c 2011-07-11 04:02:28 +0000
21@@ -1,5 +1,6 @@
22 /* If-conversion support.
23- Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
24+ Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010,
25+ 2011
26 Free Software Foundation, Inc.
27
28 This file is part of GCC.
29@@ -304,6 +305,10 @@
30
31 for (insn = start; ; insn = NEXT_INSN (insn))
32 {
33+ /* dwarf2out can't cope with conditional prologues. */
34+ if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_PROLOGUE_END)
35+ return FALSE;
36+
37 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
38 goto insn_done;
39
40
41=== added file 'gcc/testsuite/gcc.c-torture/compile/20110401-1.c'
42--- old/gcc/testsuite/gcc.c-torture/compile/20110401-1.c 1970-01-01 00:00:00 +0000
43+++ new/gcc/testsuite/gcc.c-torture/compile/20110401-1.c 2011-07-11 04:02:28 +0000
44@@ -0,0 +1,22 @@
45+void asn1_length_der (unsigned long int len, unsigned char *ans, int *ans_len)
46+{
47+ int k;
48+ unsigned char temp[4];
49+ if (len < 128) {
50+ if (ans != ((void *) 0))
51+ ans[0] = (unsigned char) len;
52+ *ans_len = 1;
53+ } else {
54+ k = 0;
55+ while (len) {
56+ temp[k++] = len & 0xFF;
57+ len = len >> 8;
58+ }
59+ *ans_len = k + 1;
60+ if (ans != ((void *) 0)) {
61+ ans[0] = ((unsigned char) k & 0x7F) + 128;
62+ while (k--)
63+ ans[*ans_len - 1 - k] = temp[k];
64+ }
65+ }
66+}
67
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106776.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106776.patch
deleted file mode 100644
index 3d4d5c504..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106776.patch
+++ /dev/null
@@ -1,46 +0,0 @@
12011-07-15 Michael Hope <michael.hope@linaro.org>
2
3 gcc/
4 Backport from mainline:
5 2011-03-22 Eric Botcazou <ebotcazou@adacore.com>
6
7 * combine.c (simplify_set): Try harder to find the best CC mode when
8 simplifying a nested COMPARE on the RHS.
9
10=== modified file 'gcc/combine.c'
11--- old/gcc/combine.c 2011-05-27 14:31:18 +0000
12+++ new/gcc/combine.c 2011-07-11 03:52:31 +0000
13@@ -6287,10 +6287,18 @@
14 enum rtx_code new_code;
15 rtx op0, op1, tmp;
16 int other_changed = 0;
17+ rtx inner_compare = NULL_RTX;
18 enum machine_mode compare_mode = GET_MODE (dest);
19
20 if (GET_CODE (src) == COMPARE)
21- op0 = XEXP (src, 0), op1 = XEXP (src, 1);
22+ {
23+ op0 = XEXP (src, 0), op1 = XEXP (src, 1);
24+ if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
25+ {
26+ inner_compare = op0;
27+ op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
28+ }
29+ }
30 else
31 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
32
33@@ -6332,6 +6340,12 @@
34 need to use a different CC mode here. */
35 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
36 compare_mode = GET_MODE (op0);
37+ else if (inner_compare
38+ && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
39+ && new_code == old_code
40+ && op0 == XEXP (inner_compare, 0)
41+ && op1 == XEXP (inner_compare, 1))
42+ compare_mode = GET_MODE (inner_compare);
43 else
44 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
45
46
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106777.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106777.patch
deleted file mode 100644
index 68b682b3c..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106777.patch
+++ /dev/null
@@ -1,192 +0,0 @@
12011-07-15 Michael Hope <michael.hope@linaro.org>
2
3 gcc/
4 Backport from mainline:
5 2011-06-29 Nathan Sidwell <nathan@codesourcery.com>
6
7 * config/arm/unwind-arm.c (enum __cxa_type_match_result): New.
8 (cxa_type_match): Correct declaration.
9 (__gnu_unwind_pr_common): Reconstruct
10 additional indirection when __cxa_type_match returns
11 succeeded_with_ptr_to_base.
12
13 libstdc++-v3/
14 Backport from mainline:
15
16 2011-06-29 Nathan Sidwell <nathan@codesourcery.com>
17
18 * libsupc++/eh_arm.c (__cxa_type_match): Construct address of
19 thrown object here. Return succeded_with_ptr_to_base for all
20 pointer cases.
21
22=== modified file 'gcc/config/arm/unwind-arm.c'
23--- old/gcc/config/arm/unwind-arm.c 2011-03-22 10:59:10 +0000
24+++ new/gcc/config/arm/unwind-arm.c 2011-07-11 03:35:44 +0000
25@@ -32,13 +32,18 @@
26 typedef unsigned char bool;
27
28 typedef struct _ZSt9type_info type_info; /* This names C++ type_info type */
29+enum __cxa_type_match_result
30+ {
31+ ctm_failed = 0,
32+ ctm_succeeded = 1,
33+ ctm_succeeded_with_ptr_to_base = 2
34+ };
35
36 void __attribute__((weak)) __cxa_call_unexpected(_Unwind_Control_Block *ucbp);
37 bool __attribute__((weak)) __cxa_begin_cleanup(_Unwind_Control_Block *ucbp);
38-bool __attribute__((weak)) __cxa_type_match(_Unwind_Control_Block *ucbp,
39- const type_info *rttip,
40- bool is_reference,
41- void **matched_object);
42+enum __cxa_type_match_result __attribute__((weak)) __cxa_type_match
43+ (_Unwind_Control_Block *ucbp, const type_info *rttip,
44+ bool is_reference, void **matched_object);
45
46 _Unwind_Ptr __attribute__((weak))
47 __gnu_Unwind_Find_exidx (_Unwind_Ptr, int *);
48@@ -1107,6 +1112,7 @@
49 _uw rtti;
50 bool is_reference = (data[0] & uint32_highbit) != 0;
51 void *matched;
52+ enum __cxa_type_match_result match_type;
53
54 /* Check for no-throw areas. */
55 if (data[1] == (_uw) -2)
56@@ -1118,17 +1124,31 @@
57 {
58 /* Match a catch specification. */
59 rtti = _Unwind_decode_target2 ((_uw) &data[1]);
60- if (!__cxa_type_match (ucbp, (type_info *) rtti,
61- is_reference,
62- &matched))
63- matched = (void *)0;
64+ match_type = __cxa_type_match (ucbp,
65+ (type_info *) rtti,
66+ is_reference,
67+ &matched);
68 }
69+ else
70+ match_type = ctm_succeeded;
71
72- if (matched)
73+ if (match_type)
74 {
75 ucbp->barrier_cache.sp =
76 _Unwind_GetGR (context, R_SP);
77- ucbp->barrier_cache.bitpattern[0] = (_uw) matched;
78+ // ctm_succeeded_with_ptr_to_base really
79+ // means _c_t_m indirected the pointer
80+ // object. We have to reconstruct the
81+ // additional pointer layer by using a temporary.
82+ if (match_type == ctm_succeeded_with_ptr_to_base)
83+ {
84+ ucbp->barrier_cache.bitpattern[2]
85+ = (_uw) matched;
86+ ucbp->barrier_cache.bitpattern[0]
87+ = (_uw) &ucbp->barrier_cache.bitpattern[2];
88+ }
89+ else
90+ ucbp->barrier_cache.bitpattern[0] = (_uw) matched;
91 ucbp->barrier_cache.bitpattern[1] = (_uw) data;
92 return _URC_HANDLER_FOUND;
93 }
94
95=== modified file 'libstdc++-v3/libsupc++/eh_arm.cc'
96--- old/libstdc++-v3/libsupc++/eh_arm.cc 2011-01-03 20:52:22 +0000
97+++ new/libstdc++-v3/libsupc++/eh_arm.cc 2011-07-11 03:35:44 +0000
98@@ -30,10 +30,11 @@
99 using namespace __cxxabiv1;
100
101
102-// Given the thrown type THROW_TYPE, pointer to a variable containing a
103-// pointer to the exception object THROWN_PTR_P and a type CATCH_TYPE to
104-// compare against, return whether or not there is a match and if so,
105-// update *THROWN_PTR_P.
106+// Given the thrown type THROW_TYPE, exception object UE_HEADER and a
107+// type CATCH_TYPE to compare against, return whether or not there is
108+// a match and if so, update *THROWN_PTR_P to point to either the
109+// type-matched object, or in the case of a pointer type, the object
110+// pointed to by the pointer.
111
112 extern "C" __cxa_type_match_result
113 __cxa_type_match(_Unwind_Exception* ue_header,
114@@ -41,51 +42,51 @@
115 bool is_reference __attribute__((__unused__)),
116 void** thrown_ptr_p)
117 {
118- bool forced_unwind = __is_gxx_forced_unwind_class(ue_header->exception_class);
119- bool foreign_exception = !forced_unwind && !__is_gxx_exception_class(ue_header->exception_class);
120- bool dependent_exception =
121- __is_dependent_exception(ue_header->exception_class);
122+ bool forced_unwind
123+ = __is_gxx_forced_unwind_class(ue_header->exception_class);
124+ bool foreign_exception
125+ = !forced_unwind && !__is_gxx_exception_class(ue_header->exception_class);
126+ bool dependent_exception
127+ = __is_dependent_exception(ue_header->exception_class);
128 __cxa_exception* xh = __get_exception_header_from_ue(ue_header);
129 __cxa_dependent_exception *dx = __get_dependent_exception_from_ue(ue_header);
130 const std::type_info* throw_type;
131+ void *thrown_ptr = 0;
132
133 if (forced_unwind)
134 throw_type = &typeid(abi::__forced_unwind);
135 else if (foreign_exception)
136 throw_type = &typeid(abi::__foreign_exception);
137- else if (dependent_exception)
138- throw_type = __get_exception_header_from_obj
139- (dx->primaryException)->exceptionType;
140 else
141- throw_type = xh->exceptionType;
142-
143- void* thrown_ptr = *thrown_ptr_p;
144+ {
145+ if (dependent_exception)
146+ xh = __get_exception_header_from_obj (dx->primaryException);
147+ throw_type = xh->exceptionType;
148+ // We used to require the caller set the target of thrown_ptr_p,
149+ // but that's incorrect -- the EHABI makes no such requirement
150+ // -- and not all callers will set it. Fortunately callers that
151+ // do initialize will always pass us the value we calculate
152+ // here, so there's no backwards compatibility problem.
153+ thrown_ptr = __get_object_from_ue (ue_header);
154+ }
155+
156+ __cxa_type_match_result result = ctm_succeeded;
157
158 // Pointer types need to adjust the actual pointer, not
159 // the pointer to pointer that is the exception object.
160 // This also has the effect of passing pointer types
161 // "by value" through the __cxa_begin_catch return value.
162 if (throw_type->__is_pointer_p())
163- thrown_ptr = *(void**) thrown_ptr;
164+ {
165+ thrown_ptr = *(void**) thrown_ptr;
166+ // We need to indicate the indirection to our caller.
167+ result = ctm_succeeded_with_ptr_to_base;
168+ }
169
170 if (catch_type->__do_catch(throw_type, &thrown_ptr, 1))
171 {
172 *thrown_ptr_p = thrown_ptr;
173-
174- if (typeid(*catch_type) == typeid (typeid(void*)))
175- {
176- const __pointer_type_info *catch_pointer_type =
177- static_cast<const __pointer_type_info *> (catch_type);
178- const __pointer_type_info *throw_pointer_type =
179- static_cast<const __pointer_type_info *> (throw_type);
180-
181- if (typeid (*catch_pointer_type->__pointee) != typeid (void)
182- && (*catch_pointer_type->__pointee !=
183- *throw_pointer_type->__pointee))
184- return ctm_succeeded_with_ptr_to_base;
185- }
186-
187- return ctm_succeeded;
188+ return result;
189 }
190
191 return ctm_failed;
192
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106778.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106778.patch
deleted file mode 100644
index b42b425dc..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106778.patch
+++ /dev/null
@@ -1,225 +0,0 @@
12011-07-15 Michael Hope <michael.hope@linaro.org>
2
3 Backport from mainline r174540
4 LP: #807573
5
6 gcc/
7 2011-06-01 Richard Sandiford <rdsandiford@googlemail.com>
8
9 PR rtl-optimization/48830
10 PR rtl-optimization/48808
11 PR rtl-optimization/48792
12 * reload.c (push_reload): Check contains_reg_of_mode.
13 * reload1.c (strip_paradoxical_subreg): New function.
14 (gen_reload_chain_without_interm_reg_p): Use it to handle
15 paradoxical subregs.
16 (emit_output_reload_insns, gen_reload): Likewise.
17
18 gcc/testsuite/
19 2011-06-01 Eric Botcazou <ebotcazou@adacore.com>
20 Hans-Peter Nilsson <hp@axis.com>
21
22 PR rtl-optimization/48830
23 * gcc.target/sparc/ultrasp12.c: New test.
24
25=== modified file 'gcc/reload.c'
26--- old/gcc/reload.c 2011-07-01 09:19:21 +0000
27+++ new/gcc/reload.c 2011-07-13 02:09:08 +0000
28@@ -1017,6 +1017,7 @@
29 #ifdef CANNOT_CHANGE_MODE_CLASS
30 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (in)), inmode, rclass)
31 #endif
32+ && contains_reg_of_mode[(int) rclass][(int) GET_MODE (SUBREG_REG (in))]
33 && (CONSTANT_P (SUBREG_REG (in))
34 || GET_CODE (SUBREG_REG (in)) == PLUS
35 || strict_low
36@@ -1123,6 +1124,7 @@
37 #ifdef CANNOT_CHANGE_MODE_CLASS
38 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SUBREG_REG (out)), outmode, rclass)
39 #endif
40+ && contains_reg_of_mode[(int) rclass][(int) GET_MODE (SUBREG_REG (out))]
41 && (CONSTANT_P (SUBREG_REG (out))
42 || strict_low
43 || (((REG_P (SUBREG_REG (out))
44
45=== modified file 'gcc/reload1.c'
46--- old/gcc/reload1.c 2011-07-11 10:06:50 +0000
47+++ new/gcc/reload1.c 2011-07-14 22:14:45 +0000
48@@ -4476,6 +4476,43 @@
49 }
50 }
51 }
52+
53+/* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
54+ If *OP_PTR is a paradoxical subreg, try to remove that subreg
55+ and apply the corresponding narrowing subreg to *OTHER_PTR.
56+ Return true if the operands were changed, false otherwise. */
57+
58+static bool
59+strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
60+{
61+ rtx op, inner, other, tem;
62+
63+ op = *op_ptr;
64+ if (GET_CODE (op) != SUBREG)
65+ return false;
66+
67+ inner = SUBREG_REG (op);
68+ if (GET_MODE_SIZE (GET_MODE (op)) <= GET_MODE_SIZE (GET_MODE (inner)))
69+ return false;
70+
71+ other = *other_ptr;
72+ tem = gen_lowpart_common (GET_MODE (inner), other);
73+ if (!tem)
74+ return false;
75+
76+ /* If the lowpart operation turned a hard register into a subreg,
77+ rather than simplifying it to another hard register, then the
78+ mode change cannot be properly represented. For example, OTHER
79+ might be valid in its current mode, but not in the new one. */
80+ if (GET_CODE (tem) == SUBREG
81+ && REG_P (other)
82+ && HARD_REGISTER_P (other))
83+ return false;
84+
85+ *op_ptr = inner;
86+ *other_ptr = tem;
87+ return true;
88+}
89
90 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
91 examine all of the reload insns between PREV and NEXT exclusive, and
92@@ -5556,7 +5593,7 @@
93 chain reloads or do need an intermediate hard registers. */
94 bool result = true;
95 int regno, n, code;
96- rtx out, in, tem, insn;
97+ rtx out, in, insn;
98 rtx last = get_last_insn ();
99
100 /* Make r2 a component of r1. */
101@@ -5575,11 +5612,7 @@
102
103 /* If IN is a paradoxical SUBREG, remove it and try to put the
104 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
105- if (GET_CODE (in) == SUBREG
106- && (GET_MODE_SIZE (GET_MODE (in))
107- > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
108- && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
109- in = SUBREG_REG (in), out = tem;
110+ strip_paradoxical_subreg (&in, &out);
111
112 if (GET_CODE (in) == PLUS
113 && (REG_P (XEXP (in, 0))
114@@ -7571,7 +7604,6 @@
115 if (tertiary_icode != CODE_FOR_nothing)
116 {
117 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
118- rtx tem;
119
120 /* Copy primary reload reg to secondary reload reg.
121 (Note that these have been swapped above, then
122@@ -7580,13 +7612,7 @@
123 /* If REAL_OLD is a paradoxical SUBREG, remove it
124 and try to put the opposite SUBREG on
125 RELOADREG. */
126- if (GET_CODE (real_old) == SUBREG
127- && (GET_MODE_SIZE (GET_MODE (real_old))
128- > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
129- && 0 != (tem = gen_lowpart_common
130- (GET_MODE (SUBREG_REG (real_old)),
131- reloadreg)))
132- real_old = SUBREG_REG (real_old), reloadreg = tem;
133+ strip_paradoxical_subreg (&real_old, &reloadreg);
134
135 gen_reload (reloadreg, second_reloadreg,
136 rl->opnum, rl->when_needed);
137@@ -8402,16 +8428,8 @@
138
139 /* If IN is a paradoxical SUBREG, remove it and try to put the
140 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
141- if (GET_CODE (in) == SUBREG
142- && (GET_MODE_SIZE (GET_MODE (in))
143- > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
144- && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
145- in = SUBREG_REG (in), out = tem;
146- else if (GET_CODE (out) == SUBREG
147- && (GET_MODE_SIZE (GET_MODE (out))
148- > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
149- && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
150- out = SUBREG_REG (out), in = tem;
151+ if (!strip_paradoxical_subreg (&in, &out))
152+ strip_paradoxical_subreg (&out, &in);
153
154 /* How to do this reload can get quite tricky. Normally, we are being
155 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
156
157=== added file 'gcc/testsuite/gcc.target/sparc/ultrasp12.c'
158--- old/gcc/testsuite/gcc.target/sparc/ultrasp12.c 1970-01-01 00:00:00 +0000
159+++ new/gcc/testsuite/gcc.target/sparc/ultrasp12.c 2011-07-13 02:09:08 +0000
160@@ -0,0 +1,64 @@
161+/* PR rtl-optimization/48830 */
162+/* Testcase by Hans-Peter Nilsson <hp@gcc.gnu.org> */
163+
164+/* { dg-do compile } */
165+/* { dg-require-effective-target lp64 } */
166+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
167+
168+typedef unsigned char uint8_t;
169+typedef unsigned int uint32_t;
170+typedef unsigned long int uint64_t;
171+typedef unsigned long int uintmax_t;
172+typedef unsigned char rc_vec_t __attribute__((__vector_size__(8)));
173+typedef short rc_svec_type_ __attribute__((__vector_size__(8)));
174+typedef unsigned char rc_vec4_type_ __attribute__((__vector_size__(4)));
175+
176+void
177+rc_stat_xsum_acc(const uint8_t *__restrict src1, int src1_dim,
178+ const uint8_t *__restrict src2, int src2_dim,
179+ int len, int height, uintmax_t sum[5])
180+{
181+ uint32_t s1 = 0;
182+ uint32_t s2 = 0;
183+ uintmax_t s11 = 0;
184+ uintmax_t s22 = 0;
185+ uintmax_t s12 = 0;
186+ int full = len / ((1024) < (1024) ? (1024) : (1024));
187+ int rem = len % ((1024) < (1024) ? (1024) : (1024));
188+ int rem1 = rem / 1;
189+ int y;
190+ unsigned int rc_gsr_scale_ __attribute__ ((__unused__)) = 7; unsigned int rc_gsr_align_ __attribute__ ((__unused__)) = 4; unsigned int rc_gsr_set_ __attribute__ ((__unused__)) = 0; register unsigned int rc_gsr_fakedep_ __attribute__ ((__unused__)) = 0; unsigned int rc_gsr_ldinit_ __attribute__ ((__unused__)) = 0;
191+ for (y = 0; y < height; y++) {
192+ rc_vec_t a1, a2, a11, a22, a12;
193+ int i1 = (y)*(src1_dim);
194+ int i2 = (y)*(src2_dim);
195+ int x;
196+ ((a1) = ((rc_vec_t) {0}));
197+ ((a2) = ((rc_vec_t) {0}));
198+ ((a11) = ((rc_vec_t) {0}));
199+ ((a22) = ((rc_vec_t) {0}));
200+ ((a12) = ((rc_vec_t) {0}));
201+ for (x = 0; x < full; x++) {
202+ int k;
203+ for (k = 0; k < ((1024) < (1024) ? (1024) : (1024)) /
204+ 1; k++)
205+ {
206+ do { rc_vec_t v1, v2; ((v1) = *(const rc_vec_t*)(&(src1)[i1])); ((v2) = *(const rc_vec_t*)(&(src2)[i2])); ((a1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v1, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)))).v)); ((a2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v2, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)))).v)); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v1); rc_vec_t accvin_ = (a11); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a11) = accvout_; } while (0); do { rc_vec_t s1_ = (v2); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a22); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a22) = accvout_; } while (0); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a12); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a12) = accvout_; } while (0); (i1) += 8; (i2) += 8; } while (0);
207+
208+ }
209+ do { uint32_t t1, t2, t11, t22, t12; ((t1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)); ((t2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a11); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t11) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a22); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t22) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a12); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t12) = maclo_ + machi_ * 256; } while (0); ((a1) = ((rc_vec_t) {0})); ((a2) = ((rc_vec_t) {0})); ((a11) = ((rc_vec_t) {0})); ((a22) = ((rc_vec_t) {0})); ((a12) = ((rc_vec_t) {0})); (s1) += t1; (s2) += t2; (s11) += t11; (s22) += t22; (s12) += t12; } while (0);
210+ }
211+ for (x = 0; x < rem1; x++) {
212+ do { rc_vec_t v1, v2; ((v1) = *(const rc_vec_t*)(&(src1)[i1])); ((v2) = *(const rc_vec_t*)(&(src2)[i2])); ((a1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v1, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)))).v)); ((a2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v2, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)))).v)); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v1); rc_vec_t accvin_ = (a11); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a11) = accvout_; } while (0); do { rc_vec_t s1_ = (v2); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a22); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a22) = accvout_; } while (0); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a12); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a12) = accvout_; } while (0); (i1) += 8; (i2) += 8; } while (0);
213+ }
214+ do { uint32_t t1, t2, t11, t22, t12; ((t1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)); ((t2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a11); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t11) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a22); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t22) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a12); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t12) = maclo_ + machi_ * 256; } while (0); ((a1) = ((rc_vec_t) {0})); ((a2) = ((rc_vec_t) {0})); ((a11) = ((rc_vec_t) {0})); ((a22) = ((rc_vec_t) {0})); ((a12) = ((rc_vec_t) {0})); (s1) += t1; (s2) += t2; (s11) += t11; (s22) += t22; (s12) += t12; } while (0);
215+
216+ do { uint32_t t1, t2, t11, t22, t12; ((t1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)); ((t2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a11); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t11) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a22); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t22) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a12); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t12) = maclo_ + machi_ * 256; } while (0); ((a1) = ((rc_vec_t) {0})); ((a2) = ((rc_vec_t) {0})); ((a11) = ((rc_vec_t) {0})); ((a22) = ((rc_vec_t) {0})); ((a12) = ((rc_vec_t) {0})); (s1) += t1; (s2) += t2; (s11) += t11; (s22) += t22; (s12) += t12; } while (0);
217+ }
218+ sum[0] = s1;
219+ sum[1] = s2;
220+ sum[2] = s11;
221+ sum[3] = s22;
222+ sum[4] = s12;
223+ ;
224+}
225
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106781.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106781.patch
deleted file mode 100644
index a86ddfdec..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106781.patch
+++ /dev/null
@@ -1,741 +0,0 @@
12011-07-21 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 PR middle-end/49736
5 * expr.c (all_zeros_p): Undo bogus part of last change.
6
72011-07-21 Richard Sandiford <richard.sandiford@linaro.org>
8
9 Backport from mainline:
10 gcc/cp/
11 2011-07-13 Richard Sandiford <richard.sandiford@linaro.org>
12
13 * typeck2.c (split_nonconstant_init_1): Pass the initializer directly,
14 rather than a pointer to it. Return true if the whole of the value
15 was initialized by the generated statements. Use
16 complete_ctor_at_level_p instead of count_type_elements.
17
18 gcc/
19 2011-07-13 Richard Sandiford <richard.sandiford@linaro.org>
20
21 * tree.h (categorize_ctor_elements): Remove comment. Fix long line.
22 (count_type_elements): Delete.
23 (complete_ctor_at_level_p): Declare.
24 * expr.c (flexible_array_member_p): New function, split out from...
25 (count_type_elements): ...here. Make static. Replace allow_flexarr
26 parameter with for_ctor_p. When for_ctor_p is true, return the
27 number of elements that should appear in the top-level constructor,
28 otherwise return an estimate of the number of scalars.
29 (categorize_ctor_elements): Replace p_must_clear with p_complete.
30 (categorize_ctor_elements_1): Likewise. Use complete_ctor_at_level_p.
31 (complete_ctor_at_level_p): New function, borrowing union logic
32 from old categorize_ctor_elements_1.
33 (mostly_zeros_p): Return true if the constructor is not complete.
34 (all_zeros_p): Update call to categorize_ctor_elements.
35 * gimplify.c (gimplify_init_constructor): Update call to
36 categorize_ctor_elements. Don't call count_type_elements.
37 Unconditionally prevent clearing for variable-sized types,
38 otherwise rely on categorize_ctor_elements to detect
39 incomplete initializers.
40
41 gcc/testsuite/
42 2011-07-13 Chung-Lin Tang <cltang@codesourcery.com>
43
44 * gcc.target/arm/pr48183.c: New test.
45
46=== modified file 'gcc/cp/typeck2.c'
47--- old/gcc/cp/typeck2.c 2011-05-20 21:29:14 +0000
48+++ new/gcc/cp/typeck2.c 2011-07-13 13:17:31 +0000
49@@ -473,18 +473,20 @@
50
51
52 /* The recursive part of split_nonconstant_init. DEST is an lvalue
53- expression to which INIT should be assigned. INIT is a CONSTRUCTOR. */
54+ expression to which INIT should be assigned. INIT is a CONSTRUCTOR.
55+ Return true if the whole of the value was initialized by the
56+ generated statements. */
57
58-static void
59-split_nonconstant_init_1 (tree dest, tree *initp)
60+static bool
61+split_nonconstant_init_1 (tree dest, tree init)
62 {
63 unsigned HOST_WIDE_INT idx;
64- tree init = *initp;
65 tree field_index, value;
66 tree type = TREE_TYPE (dest);
67 tree inner_type = NULL;
68 bool array_type_p = false;
69- HOST_WIDE_INT num_type_elements, num_initialized_elements;
70+ bool complete_p = true;
71+ HOST_WIDE_INT num_split_elts = 0;
72
73 switch (TREE_CODE (type))
74 {
75@@ -496,7 +498,6 @@
76 case RECORD_TYPE:
77 case UNION_TYPE:
78 case QUAL_UNION_TYPE:
79- num_initialized_elements = 0;
80 FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (init), idx,
81 field_index, value)
82 {
83@@ -519,13 +520,14 @@
84 sub = build3 (COMPONENT_REF, inner_type, dest, field_index,
85 NULL_TREE);
86
87- split_nonconstant_init_1 (sub, &value);
88+ if (!split_nonconstant_init_1 (sub, value))
89+ complete_p = false;
90+ num_split_elts++;
91 }
92 else if (!initializer_constant_valid_p (value, inner_type))
93 {
94 tree code;
95 tree sub;
96- HOST_WIDE_INT inner_elements;
97
98 /* FIXME: Ordered removal is O(1) so the whole function is
99 worst-case quadratic. This could be fixed using an aside
100@@ -549,21 +551,9 @@
101 code = build_stmt (input_location, EXPR_STMT, code);
102 add_stmt (code);
103
104- inner_elements = count_type_elements (inner_type, true);
105- if (inner_elements < 0)
106- num_initialized_elements = -1;
107- else if (num_initialized_elements >= 0)
108- num_initialized_elements += inner_elements;
109- continue;
110+ num_split_elts++;
111 }
112 }
113-
114- num_type_elements = count_type_elements (type, true);
115- /* If all elements of the initializer are non-constant and
116- have been split out, we don't need the empty CONSTRUCTOR. */
117- if (num_type_elements > 0
118- && num_type_elements == num_initialized_elements)
119- *initp = NULL;
120 break;
121
122 case VECTOR_TYPE:
123@@ -575,6 +565,7 @@
124 code = build2 (MODIFY_EXPR, type, dest, cons);
125 code = build_stmt (input_location, EXPR_STMT, code);
126 add_stmt (code);
127+ num_split_elts += CONSTRUCTOR_NELTS (init);
128 }
129 break;
130
131@@ -584,6 +575,8 @@
132
133 /* The rest of the initializer is now a constant. */
134 TREE_CONSTANT (init) = 1;
135+ return complete_p && complete_ctor_at_level_p (TREE_TYPE (init),
136+ num_split_elts, inner_type);
137 }
138
139 /* A subroutine of store_init_value. Splits non-constant static
140@@ -599,7 +592,8 @@
141 if (TREE_CODE (init) == CONSTRUCTOR)
142 {
143 code = push_stmt_list ();
144- split_nonconstant_init_1 (dest, &init);
145+ if (split_nonconstant_init_1 (dest, init))
146+ init = NULL_TREE;
147 code = pop_stmt_list (code);
148 DECL_INITIAL (dest) = init;
149 TREE_READONLY (dest) = 0;
150
151=== modified file 'gcc/expr.c'
152--- old/gcc/expr.c 2011-06-02 12:12:00 +0000
153+++ new/gcc/expr.c 2011-07-14 11:52:32 +0000
154@@ -4866,16 +4866,136 @@
155 return NULL_RTX;
156 }
157
158+/* Return true if field F of structure TYPE is a flexible array. */
159+
160+static bool
161+flexible_array_member_p (const_tree f, const_tree type)
162+{
163+ const_tree tf;
164+
165+ tf = TREE_TYPE (f);
166+ return (DECL_CHAIN (f) == NULL
167+ && TREE_CODE (tf) == ARRAY_TYPE
168+ && TYPE_DOMAIN (tf)
169+ && TYPE_MIN_VALUE (TYPE_DOMAIN (tf))
170+ && integer_zerop (TYPE_MIN_VALUE (TYPE_DOMAIN (tf)))
171+ && !TYPE_MAX_VALUE (TYPE_DOMAIN (tf))
172+ && int_size_in_bytes (type) >= 0);
173+}
174+
175+/* If FOR_CTOR_P, return the number of top-level elements that a constructor
176+ must have in order for it to completely initialize a value of type TYPE.
177+ Return -1 if the number isn't known.
178+
179+ If !FOR_CTOR_P, return an estimate of the number of scalars in TYPE. */
180+
181+static HOST_WIDE_INT
182+count_type_elements (const_tree type, bool for_ctor_p)
183+{
184+ switch (TREE_CODE (type))
185+ {
186+ case ARRAY_TYPE:
187+ {
188+ tree nelts;
189+
190+ nelts = array_type_nelts (type);
191+ if (nelts && host_integerp (nelts, 1))
192+ {
193+ unsigned HOST_WIDE_INT n;
194+
195+ n = tree_low_cst (nelts, 1) + 1;
196+ if (n == 0 || for_ctor_p)
197+ return n;
198+ else
199+ return n * count_type_elements (TREE_TYPE (type), false);
200+ }
201+ return for_ctor_p ? -1 : 1;
202+ }
203+
204+ case RECORD_TYPE:
205+ {
206+ unsigned HOST_WIDE_INT n;
207+ tree f;
208+
209+ n = 0;
210+ for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
211+ if (TREE_CODE (f) == FIELD_DECL)
212+ {
213+ if (!for_ctor_p)
214+ n += count_type_elements (TREE_TYPE (f), false);
215+ else if (!flexible_array_member_p (f, type))
216+ /* Don't count flexible arrays, which are not supposed
217+ to be initialized. */
218+ n += 1;
219+ }
220+
221+ return n;
222+ }
223+
224+ case UNION_TYPE:
225+ case QUAL_UNION_TYPE:
226+ {
227+ tree f;
228+ HOST_WIDE_INT n, m;
229+
230+ gcc_assert (!for_ctor_p);
231+ /* Estimate the number of scalars in each field and pick the
232+ maximum. Other estimates would do instead; the idea is simply
233+ to make sure that the estimate is not sensitive to the ordering
234+ of the fields. */
235+ n = 1;
236+ for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
237+ if (TREE_CODE (f) == FIELD_DECL)
238+ {
239+ m = count_type_elements (TREE_TYPE (f), false);
240+ /* If the field doesn't span the whole union, add an extra
241+ scalar for the rest. */
242+ if (simple_cst_equal (TYPE_SIZE (TREE_TYPE (f)),
243+ TYPE_SIZE (type)) != 1)
244+ m++;
245+ if (n < m)
246+ n = m;
247+ }
248+ return n;
249+ }
250+
251+ case COMPLEX_TYPE:
252+ return 2;
253+
254+ case VECTOR_TYPE:
255+ return TYPE_VECTOR_SUBPARTS (type);
256+
257+ case INTEGER_TYPE:
258+ case REAL_TYPE:
259+ case FIXED_POINT_TYPE:
260+ case ENUMERAL_TYPE:
261+ case BOOLEAN_TYPE:
262+ case POINTER_TYPE:
263+ case OFFSET_TYPE:
264+ case REFERENCE_TYPE:
265+ return 1;
266+
267+ case ERROR_MARK:
268+ return 0;
269+
270+ case VOID_TYPE:
271+ case METHOD_TYPE:
272+ case FUNCTION_TYPE:
273+ case LANG_TYPE:
274+ default:
275+ gcc_unreachable ();
276+ }
277+}
278+
279 /* Helper for categorize_ctor_elements. Identical interface. */
280
281 static bool
282 categorize_ctor_elements_1 (const_tree ctor, HOST_WIDE_INT *p_nz_elts,
283- HOST_WIDE_INT *p_elt_count,
284- bool *p_must_clear)
285+ HOST_WIDE_INT *p_init_elts, bool *p_complete)
286 {
287 unsigned HOST_WIDE_INT idx;
288- HOST_WIDE_INT nz_elts, elt_count;
289- tree value, purpose;
290+ HOST_WIDE_INT nz_elts, init_elts, num_fields;
291+ tree value, purpose, elt_type;
292
293 /* Whether CTOR is a valid constant initializer, in accordance with what
294 initializer_constant_valid_p does. If inferred from the constructor
295@@ -4884,7 +5004,9 @@
296 bool const_p = const_from_elts_p ? true : TREE_STATIC (ctor);
297
298 nz_elts = 0;
299- elt_count = 0;
300+ init_elts = 0;
301+ num_fields = 0;
302+ elt_type = NULL_TREE;
303
304 FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (ctor), idx, purpose, value)
305 {
306@@ -4899,6 +5021,8 @@
307 mult = (tree_low_cst (hi_index, 1)
308 - tree_low_cst (lo_index, 1) + 1);
309 }
310+ num_fields += mult;
311+ elt_type = TREE_TYPE (value);
312
313 switch (TREE_CODE (value))
314 {
315@@ -4906,11 +5030,11 @@
316 {
317 HOST_WIDE_INT nz = 0, ic = 0;
318
319- bool const_elt_p
320- = categorize_ctor_elements_1 (value, &nz, &ic, p_must_clear);
321+ bool const_elt_p = categorize_ctor_elements_1 (value, &nz, &ic,
322+ p_complete);
323
324 nz_elts += mult * nz;
325- elt_count += mult * ic;
326+ init_elts += mult * ic;
327
328 if (const_from_elts_p && const_p)
329 const_p = const_elt_p;
330@@ -4922,12 +5046,12 @@
331 case FIXED_CST:
332 if (!initializer_zerop (value))
333 nz_elts += mult;
334- elt_count += mult;
335+ init_elts += mult;
336 break;
337
338 case STRING_CST:
339 nz_elts += mult * TREE_STRING_LENGTH (value);
340- elt_count += mult * TREE_STRING_LENGTH (value);
341+ init_elts += mult * TREE_STRING_LENGTH (value);
342 break;
343
344 case COMPLEX_CST:
345@@ -4935,7 +5059,7 @@
346 nz_elts += mult;
347 if (!initializer_zerop (TREE_IMAGPART (value)))
348 nz_elts += mult;
349- elt_count += mult;
350+ init_elts += mult;
351 break;
352
353 case VECTOR_CST:
354@@ -4945,65 +5069,31 @@
355 {
356 if (!initializer_zerop (TREE_VALUE (v)))
357 nz_elts += mult;
358- elt_count += mult;
359+ init_elts += mult;
360 }
361 }
362 break;
363
364 default:
365 {
366- HOST_WIDE_INT tc = count_type_elements (TREE_TYPE (value), true);
367- if (tc < 1)
368- tc = 1;
369+ HOST_WIDE_INT tc = count_type_elements (elt_type, false);
370 nz_elts += mult * tc;
371- elt_count += mult * tc;
372+ init_elts += mult * tc;
373
374 if (const_from_elts_p && const_p)
375- const_p = initializer_constant_valid_p (value, TREE_TYPE (value))
376+ const_p = initializer_constant_valid_p (value, elt_type)
377 != NULL_TREE;
378 }
379 break;
380 }
381 }
382
383- if (!*p_must_clear
384- && (TREE_CODE (TREE_TYPE (ctor)) == UNION_TYPE
385- || TREE_CODE (TREE_TYPE (ctor)) == QUAL_UNION_TYPE))
386- {
387- tree init_sub_type;
388- bool clear_this = true;
389-
390- if (!VEC_empty (constructor_elt, CONSTRUCTOR_ELTS (ctor)))
391- {
392- /* We don't expect more than one element of the union to be
393- initialized. Not sure what we should do otherwise... */
394- gcc_assert (VEC_length (constructor_elt, CONSTRUCTOR_ELTS (ctor))
395- == 1);
396-
397- init_sub_type = TREE_TYPE (VEC_index (constructor_elt,
398- CONSTRUCTOR_ELTS (ctor),
399- 0)->value);
400-
401- /* ??? We could look at each element of the union, and find the
402- largest element. Which would avoid comparing the size of the
403- initialized element against any tail padding in the union.
404- Doesn't seem worth the effort... */
405- if (simple_cst_equal (TYPE_SIZE (TREE_TYPE (ctor)),
406- TYPE_SIZE (init_sub_type)) == 1)
407- {
408- /* And now we have to find out if the element itself is fully
409- constructed. E.g. for union { struct { int a, b; } s; } u
410- = { .s = { .a = 1 } }. */
411- if (elt_count == count_type_elements (init_sub_type, false))
412- clear_this = false;
413- }
414- }
415-
416- *p_must_clear = clear_this;
417- }
418+ if (*p_complete && !complete_ctor_at_level_p (TREE_TYPE (ctor),
419+ num_fields, elt_type))
420+ *p_complete = false;
421
422 *p_nz_elts += nz_elts;
423- *p_elt_count += elt_count;
424+ *p_init_elts += init_elts;
425
426 return const_p;
427 }
428@@ -5013,111 +5103,50 @@
429 and place it in *P_NZ_ELTS;
430 * how many scalar fields in total are in CTOR,
431 and place it in *P_ELT_COUNT.
432- * if a type is a union, and the initializer from the constructor
433- is not the largest element in the union, then set *p_must_clear.
434+ * whether the constructor is complete -- in the sense that every
435+ meaningful byte is explicitly given a value --
436+ and place it in *P_COMPLETE.
437
438 Return whether or not CTOR is a valid static constant initializer, the same
439 as "initializer_constant_valid_p (CTOR, TREE_TYPE (CTOR)) != 0". */
440
441 bool
442 categorize_ctor_elements (const_tree ctor, HOST_WIDE_INT *p_nz_elts,
443- HOST_WIDE_INT *p_elt_count,
444- bool *p_must_clear)
445+ HOST_WIDE_INT *p_init_elts, bool *p_complete)
446 {
447 *p_nz_elts = 0;
448- *p_elt_count = 0;
449- *p_must_clear = false;
450+ *p_init_elts = 0;
451+ *p_complete = true;
452
453- return
454- categorize_ctor_elements_1 (ctor, p_nz_elts, p_elt_count, p_must_clear);
455+ return categorize_ctor_elements_1 (ctor, p_nz_elts, p_init_elts, p_complete);
456 }
457
458-/* Count the number of scalars in TYPE. Return -1 on overflow or
459- variable-sized. If ALLOW_FLEXARR is true, don't count flexible
460- array member at the end of the structure. */
461+/* TYPE is initialized by a constructor with NUM_ELTS elements, the last
462+ of which had type LAST_TYPE. Each element was itself a complete
463+ initializer, in the sense that every meaningful byte was explicitly
464+ given a value. Return true if the same is true for the constructor
465+ as a whole. */
466
467-HOST_WIDE_INT
468-count_type_elements (const_tree type, bool allow_flexarr)
469+bool
470+complete_ctor_at_level_p (const_tree type, HOST_WIDE_INT num_elts,
471+ const_tree last_type)
472 {
473- const HOST_WIDE_INT max = ~((HOST_WIDE_INT)1 << (HOST_BITS_PER_WIDE_INT-1));
474- switch (TREE_CODE (type))
475+ if (TREE_CODE (type) == UNION_TYPE
476+ || TREE_CODE (type) == QUAL_UNION_TYPE)
477 {
478- case ARRAY_TYPE:
479- {
480- tree telts = array_type_nelts (type);
481- if (telts && host_integerp (telts, 1))
482- {
483- HOST_WIDE_INT n = tree_low_cst (telts, 1) + 1;
484- HOST_WIDE_INT m = count_type_elements (TREE_TYPE (type), false);
485- if (n == 0)
486- return 0;
487- else if (max / n > m)
488- return n * m;
489- }
490- return -1;
491- }
492-
493- case RECORD_TYPE:
494- {
495- HOST_WIDE_INT n = 0, t;
496- tree f;
497-
498- for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
499- if (TREE_CODE (f) == FIELD_DECL)
500- {
501- t = count_type_elements (TREE_TYPE (f), false);
502- if (t < 0)
503- {
504- /* Check for structures with flexible array member. */
505- tree tf = TREE_TYPE (f);
506- if (allow_flexarr
507- && DECL_CHAIN (f) == NULL
508- && TREE_CODE (tf) == ARRAY_TYPE
509- && TYPE_DOMAIN (tf)
510- && TYPE_MIN_VALUE (TYPE_DOMAIN (tf))
511- && integer_zerop (TYPE_MIN_VALUE (TYPE_DOMAIN (tf)))
512- && !TYPE_MAX_VALUE (TYPE_DOMAIN (tf))
513- && int_size_in_bytes (type) >= 0)
514- break;
515-
516- return -1;
517- }
518- n += t;
519- }
520-
521- return n;
522- }
523-
524- case UNION_TYPE:
525- case QUAL_UNION_TYPE:
526- return -1;
527-
528- case COMPLEX_TYPE:
529- return 2;
530-
531- case VECTOR_TYPE:
532- return TYPE_VECTOR_SUBPARTS (type);
533-
534- case INTEGER_TYPE:
535- case REAL_TYPE:
536- case FIXED_POINT_TYPE:
537- case ENUMERAL_TYPE:
538- case BOOLEAN_TYPE:
539- case POINTER_TYPE:
540- case OFFSET_TYPE:
541- case REFERENCE_TYPE:
542- return 1;
543-
544- case ERROR_MARK:
545- return 0;
546-
547- case VOID_TYPE:
548- case METHOD_TYPE:
549- case FUNCTION_TYPE:
550- case LANG_TYPE:
551- default:
552- gcc_unreachable ();
553+ if (num_elts == 0)
554+ return false;
555+
556+ gcc_assert (num_elts == 1 && last_type);
557+
558+ /* ??? We could look at each element of the union, and find the
559+ largest element. Which would avoid comparing the size of the
560+ initialized element against any tail padding in the union.
561+ Doesn't seem worth the effort... */
562+ return simple_cst_equal (TYPE_SIZE (type), TYPE_SIZE (last_type)) == 1;
563 }
564+
565+ return count_type_elements (type, true) == num_elts;
566 }
567
568 /* Return 1 if EXP contains mostly (3/4) zeros. */
569@@ -5126,18 +5155,12 @@
570 mostly_zeros_p (const_tree exp)
571 {
572 if (TREE_CODE (exp) == CONSTRUCTOR)
573-
574 {
575- HOST_WIDE_INT nz_elts, count, elts;
576- bool must_clear;
577-
578- categorize_ctor_elements (exp, &nz_elts, &count, &must_clear);
579- if (must_clear)
580- return 1;
581-
582- elts = count_type_elements (TREE_TYPE (exp), false);
583-
584- return nz_elts < elts / 4;
585+ HOST_WIDE_INT nz_elts, init_elts;
586+ bool complete_p;
587+
588+ categorize_ctor_elements (exp, &nz_elts, &init_elts, &complete_p);
589+ return !complete_p || nz_elts < init_elts / 4;
590 }
591
592 return initializer_zerop (exp);
593@@ -5149,12 +5172,11 @@
594 all_zeros_p (const_tree exp)
595 {
596 if (TREE_CODE (exp) == CONSTRUCTOR)
597-
598 {
599- HOST_WIDE_INT nz_elts, count;
600- bool must_clear;
601+ HOST_WIDE_INT nz_elts, init_elts;
602+ bool complete_p;
603
604- categorize_ctor_elements (exp, &nz_elts, &count, &must_clear);
605+ categorize_ctor_elements (exp, &nz_elts, &init_elts, &complete_p);
606 return nz_elts == 0;
607 }
608
609
610=== modified file 'gcc/gimplify.c'
611--- old/gcc/gimplify.c 2011-05-26 10:27:57 +0000
612+++ new/gcc/gimplify.c 2011-07-13 13:17:31 +0000
613@@ -3693,9 +3693,8 @@
614 case ARRAY_TYPE:
615 {
616 struct gimplify_init_ctor_preeval_data preeval_data;
617- HOST_WIDE_INT num_type_elements, num_ctor_elements;
618- HOST_WIDE_INT num_nonzero_elements;
619- bool cleared, valid_const_initializer;
620+ HOST_WIDE_INT num_ctor_elements, num_nonzero_elements;
621+ bool cleared, complete_p, valid_const_initializer;
622
623 /* Aggregate types must lower constructors to initialization of
624 individual elements. The exception is that a CONSTRUCTOR node
625@@ -3712,7 +3711,7 @@
626 can only do so if it known to be a valid constant initializer. */
627 valid_const_initializer
628 = categorize_ctor_elements (ctor, &num_nonzero_elements,
629- &num_ctor_elements, &cleared);
630+ &num_ctor_elements, &complete_p);
631
632 /* If a const aggregate variable is being initialized, then it
633 should never be a lose to promote the variable to be static. */
634@@ -3750,26 +3749,29 @@
635 parts in, then generate code for the non-constant parts. */
636 /* TODO. There's code in cp/typeck.c to do this. */
637
638- num_type_elements = count_type_elements (type, true);
639+ if (int_size_in_bytes (TREE_TYPE (ctor)) < 0)
640+ /* store_constructor will ignore the clearing of variable-sized
641+ objects. Initializers for such objects must explicitly set
642+ every field that needs to be set. */
643+ cleared = false;
644+ else if (!complete_p)
645+ /* If the constructor isn't complete, clear the whole object
646+ beforehand.
647
648- /* If count_type_elements could not determine number of type elements
649- for a constant-sized object, assume clearing is needed.
650- Don't do this for variable-sized objects, as store_constructor
651- will ignore the clearing of variable-sized objects. */
652- if (num_type_elements < 0 && int_size_in_bytes (type) >= 0)
653+ ??? This ought not to be needed. For any element not present
654+ in the initializer, we should simply set them to zero. Except
655+ we'd need to *find* the elements that are not present, and that
656+ requires trickery to avoid quadratic compile-time behavior in
657+ large cases or excessive memory use in small cases. */
658 cleared = true;
659- /* If there are "lots" of zeros, then block clear the object first. */
660- else if (num_type_elements - num_nonzero_elements
661+ else if (num_ctor_elements - num_nonzero_elements
662 > CLEAR_RATIO (optimize_function_for_speed_p (cfun))
663- && num_nonzero_elements < num_type_elements/4)
664- cleared = true;
665- /* ??? This bit ought not be needed. For any element not present
666- in the initializer, we should simply set them to zero. Except
667- we'd need to *find* the elements that are not present, and that
668- requires trickery to avoid quadratic compile-time behavior in
669- large cases or excessive memory use in small cases. */
670- else if (num_ctor_elements < num_type_elements)
671- cleared = true;
672+ && num_nonzero_elements < num_ctor_elements / 4)
673+ /* If there are "lots" of zeros, it's more efficient to clear
674+ the memory and then set the nonzero elements. */
675+ cleared = true;
676+ else
677+ cleared = false;
678
679 /* If there are "lots" of initialized elements, and all of them
680 are valid address constants, then the entire initializer can
681
682=== added file 'gcc/testsuite/gcc.target/arm/pr48183.c'
683--- old/gcc/testsuite/gcc.target/arm/pr48183.c 1970-01-01 00:00:00 +0000
684+++ new/gcc/testsuite/gcc.target/arm/pr48183.c 2011-07-13 13:17:31 +0000
685@@ -0,0 +1,25 @@
686+/* testsuite/gcc.target/arm/pr48183.c */
687+
688+/* { dg-do compile } */
689+/* { dg-require-effective-target arm_neon_ok } */
690+/* { dg-options "-O -g" } */
691+/* { dg-add-options arm_neon } */
692+
693+#include <arm_neon.h>
694+
695+void move_16bit_to_32bit (int32_t *dst, const short *src, unsigned n)
696+{
697+ unsigned i;
698+ int16x4x2_t input;
699+ int32x4x2_t mid;
700+ int32x4x2_t output;
701+
702+ for (i = 0; i < n/2; i += 8) {
703+ input = vld2_s16(src + i);
704+ mid.val[0] = vmovl_s16(input.val[0]);
705+ mid.val[1] = vmovl_s16(input.val[1]);
706+ output.val[0] = vshlq_n_s32(mid.val[0], 8);
707+ output.val[1] = vshlq_n_s32(mid.val[1], 8);
708+ vst2q_s32((int32_t *)dst + i, output);
709+ }
710+}
711
712=== modified file 'gcc/tree.h'
713--- old/gcc/tree.h 2011-07-01 09:19:21 +0000
714+++ new/gcc/tree.h 2011-07-13 13:17:31 +0000
715@@ -4627,21 +4627,10 @@
716
717 extern VEC(tree,gc) *ctor_to_vec (tree);
718
719-/* Examine CTOR to discover:
720- * how many scalar fields are set to nonzero values,
721- and place it in *P_NZ_ELTS;
722- * how many scalar fields in total are in CTOR,
723- and place it in *P_ELT_COUNT.
724- * if a type is a union, and the initializer from the constructor
725- is not the largest element in the union, then set *p_must_clear.
726-
727- Return whether or not CTOR is a valid static constant initializer, the same
728- as "initializer_constant_valid_p (CTOR, TREE_TYPE (CTOR)) != 0". */
729-
730-extern bool categorize_ctor_elements (const_tree, HOST_WIDE_INT *, HOST_WIDE_INT *,
731- bool *);
732-
733-extern HOST_WIDE_INT count_type_elements (const_tree, bool);
734+extern bool categorize_ctor_elements (const_tree, HOST_WIDE_INT *,
735+ HOST_WIDE_INT *, bool *);
736+
737+extern bool complete_ctor_at_level_p (const_tree, HOST_WIDE_INT, const_tree);
738
739 /* integer_zerop (tree x) is nonzero if X is an integer constant of value 0. */
740
741
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106782.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106782.patch
deleted file mode 100644
index 5335a9e37..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106782.patch
+++ /dev/null
@@ -1,27 +0,0 @@
12011-07-21 Richard Sandiford <rdsandiford@googlemail.com>
2
3 gcc/
4 Backport from mainline:
5
6 2011-07-21 Richard Sandiford <richard.sandiford@linaro.org>
7
8 * regcprop.c (maybe_mode_change): Check HARD_REGNO_MODE_OK.
9
10=== modified file 'gcc/regcprop.c'
11--- old/gcc/regcprop.c 2010-12-17 22:51:25 +0000
12+++ new/gcc/regcprop.c 2011-07-21 11:30:53 +0000
13@@ -418,10 +418,9 @@
14
15 offset = ((WORDS_BIG_ENDIAN ? wordoffset : 0)
16 + (BYTES_BIG_ENDIAN ? byteoffset : 0));
17- return gen_rtx_raw_REG (new_mode,
18- regno + subreg_regno_offset (regno, orig_mode,
19- offset,
20- new_mode));
21+ regno += subreg_regno_offset (regno, orig_mode, offset, new_mode);
22+ if (HARD_REGNO_MODE_OK (regno, new_mode))
23+ return gen_rtx_raw_REG (new_mode, regno);
24 }
25 return NULL_RTX;
26 }
27
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106783.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106783.patch
deleted file mode 100644
index 61e391637..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106783.patch
+++ /dev/null
@@ -1,62 +0,0 @@
12011-07-31 Revital Eres <revital.eres@linaro.org>
2
3 gcc/
4 Backport from trunk -r176970:
5
6 * modulo-sched.c: Change comment.
7 (reset_sched_times): Fix print message.
8 (print_partial_schedule): Add print info.
9
10=== modified file 'gcc/modulo-sched.c'
11--- old/gcc/modulo-sched.c 2011-07-04 12:01:34 +0000
12+++ new/gcc/modulo-sched.c 2011-07-31 10:58:46 +0000
13@@ -84,13 +84,14 @@
14 II cycles (i.e. use register copies to prevent a def from overwriting
15 itself before reaching the use).
16
17- SMS works with countable loops whose loop count can be easily
18- adjusted. This is because we peel a constant number of iterations
19- into a prologue and epilogue for which we want to avoid emitting
20- the control part, and a kernel which is to iterate that constant
21- number of iterations less than the original loop. So the control
22- part should be a set of insns clearly identified and having its
23- own iv, not otherwise used in the loop (at-least for now), which
24+ SMS works with countable loops (1) whose control part can be easily
25+ decoupled from the rest of the loop and (2) whose loop count can
26+ be easily adjusted. This is because we peel a constant number of
27+ iterations into a prologue and epilogue for which we want to avoid
28+ emitting the control part, and a kernel which is to iterate that
29+ constant number of iterations less than the original loop. So the
30+ control part should be a set of insns clearly identified and having
31+ its own iv, not otherwise used in the loop (at-least for now), which
32 initializes a register before the loop to the number of iterations.
33 Currently SMS relies on the do-loop pattern to recognize such loops,
34 where (1) the control part comprises of all insns defining and/or
35@@ -598,8 +599,8 @@
36 /* Print the scheduling times after the rotation. */
37 fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
38 "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
39- INSN_UID (crr_insn->node->insn), SCHED_TIME (u),
40- normalized_time);
41+ INSN_UID (crr_insn->node->insn), normalized_time,
42+ new_min_cycle);
43 if (JUMP_P (crr_insn->node->insn))
44 fprintf (dump_file, " (branch)");
45 fprintf (dump_file, "\n");
46@@ -2550,8 +2551,13 @@
47 fprintf (dump, "\n[ROW %d ]: ", i);
48 while (ps_i)
49 {
50- fprintf (dump, "%d, ",
51- INSN_UID (ps_i->node->insn));
52+ if (JUMP_P (ps_i->node->insn))
53+ fprintf (dump, "%d (branch), ",
54+ INSN_UID (ps_i->node->insn));
55+ else
56+ fprintf (dump, "%d, ",
57+ INSN_UID (ps_i->node->insn));
58+
59 ps_i = ps_i->next_in_row;
60 }
61 }
62
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106784.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106784.patch
deleted file mode 100644
index b82fe76d4..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106784.patch
+++ /dev/null
@@ -1,458 +0,0 @@
12011-08-09 Revital Eres <revital.eres@linaro.org>
2
3 gcc/
4 Backport from trunk -r177235.
5 * modulo-sched.c (calculate_stage_count,
6 calculate_must_precede_follow, get_sched_window,
7 try_scheduling_node_in_cycle, remove_node_from_ps):
8 Add declaration.
9 (update_node_sched_params, set_must_precede_follow, optimize_sc):
10 New functions.
11 (reset_sched_times): Call update_node_sched_params.
12 (sms_schedule): Call optimize_sc.
13 (get_sched_window): Change function arguments.
14 (sms_schedule_by_order): Update call to get_sched_window.
15 Call set_must_precede_follow.
16 (calculate_stage_count): Add function argument.
17
18=== modified file 'gcc/modulo-sched.c'
19--- old/gcc/modulo-sched.c 2011-07-31 10:58:46 +0000
20+++ new/gcc/modulo-sched.c 2011-08-09 04:51:48 +0000
21@@ -203,7 +203,16 @@
22 rtx, rtx);
23 static void duplicate_insns_of_cycles (partial_schedule_ptr,
24 int, int, int, rtx);
25-static int calculate_stage_count (partial_schedule_ptr ps);
26+static int calculate_stage_count (partial_schedule_ptr, int);
27+static void calculate_must_precede_follow (ddg_node_ptr, int, int,
28+ int, int, sbitmap, sbitmap, sbitmap);
29+static int get_sched_window (partial_schedule_ptr, ddg_node_ptr,
30+ sbitmap, int, int *, int *, int *);
31+static bool try_scheduling_node_in_cycle (partial_schedule_ptr, ddg_node_ptr,
32+ int, int, sbitmap, int *, sbitmap,
33+ sbitmap);
34+static bool remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
35+
36 #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
37 #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
38 #define SCHED_FIRST_REG_MOVE(x) \
39@@ -577,6 +586,36 @@
40 }
41 }
42
43+/* Update the sched_params (time, row and stage) for node U using the II,
44+ the CYCLE of U and MIN_CYCLE.
45+ We're not simply taking the following
46+ SCHED_STAGE (u) = CALC_STAGE_COUNT (SCHED_TIME (u), min_cycle, ii);
47+ because the stages may not be aligned on cycle 0. */
48+static void
49+update_node_sched_params (ddg_node_ptr u, int ii, int cycle, int min_cycle)
50+{
51+ int sc_until_cycle_zero;
52+ int stage;
53+
54+ SCHED_TIME (u) = cycle;
55+ SCHED_ROW (u) = SMODULO (cycle, ii);
56+
57+ /* The calculation of stage count is done adding the number
58+ of stages before cycle zero and after cycle zero. */
59+ sc_until_cycle_zero = CALC_STAGE_COUNT (-1, min_cycle, ii);
60+
61+ if (SCHED_TIME (u) < 0)
62+ {
63+ stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
64+ SCHED_STAGE (u) = sc_until_cycle_zero - stage;
65+ }
66+ else
67+ {
68+ stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
69+ SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
70+ }
71+}
72+
73 /* Bump the SCHED_TIMEs of all nodes by AMOUNT. Set the values of
74 SCHED_ROW and SCHED_STAGE. */
75 static void
76@@ -592,7 +631,6 @@
77 ddg_node_ptr u = crr_insn->node;
78 int normalized_time = SCHED_TIME (u) - amount;
79 int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
80- int sc_until_cycle_zero, stage;
81
82 if (dump_file)
83 {
84@@ -608,23 +646,9 @@
85
86 gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
87 gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
88- SCHED_TIME (u) = normalized_time;
89- SCHED_ROW (u) = SMODULO (normalized_time, ii);
90-
91- /* The calculation of stage count is done adding the number
92- of stages before cycle zero and after cycle zero. */
93- sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii);
94-
95- if (SCHED_TIME (u) < 0)
96- {
97- stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
98- SCHED_STAGE (u) = sc_until_cycle_zero - stage;
99- }
100- else
101- {
102- stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
103- SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
104- }
105+
106+ crr_insn->cycle = normalized_time;
107+ update_node_sched_params (u, ii, normalized_time, new_min_cycle);
108 }
109 }
110
111@@ -661,6 +685,206 @@
112 PREV_INSN (last));
113 }
114
115+/* Set bitmaps TMP_FOLLOW and TMP_PRECEDE to MUST_FOLLOW and MUST_PRECEDE
116+ respectively only if cycle C falls on the border of the scheduling
117+ window boundaries marked by START and END cycles. STEP is the
118+ direction of the window. */
119+static inline void
120+set_must_precede_follow (sbitmap *tmp_follow, sbitmap must_follow,
121+ sbitmap *tmp_precede, sbitmap must_precede, int c,
122+ int start, int end, int step)
123+{
124+ *tmp_precede = NULL;
125+ *tmp_follow = NULL;
126+
127+ if (c == start)
128+ {
129+ if (step == 1)
130+ *tmp_precede = must_precede;
131+ else /* step == -1. */
132+ *tmp_follow = must_follow;
133+ }
134+ if (c == end - step)
135+ {
136+ if (step == 1)
137+ *tmp_follow = must_follow;
138+ else /* step == -1. */
139+ *tmp_precede = must_precede;
140+ }
141+
142+}
143+
144+/* Return True if the branch can be moved to row ii-1 while
145+ normalizing the partial schedule PS to start from cycle zero and thus
146+ optimize the SC. Otherwise return False. */
147+static bool
148+optimize_sc (partial_schedule_ptr ps, ddg_ptr g)
149+{
150+ int amount = PS_MIN_CYCLE (ps);
151+ sbitmap sched_nodes = sbitmap_alloc (g->num_nodes);
152+ int start, end, step;
153+ int ii = ps->ii;
154+ bool ok = false;
155+ int stage_count, stage_count_curr;
156+
157+ /* Compare the SC after normalization and SC after bringing the branch
158+ to row ii-1. If they are equal just bail out. */
159+ stage_count = calculate_stage_count (ps, amount);
160+ stage_count_curr =
161+ calculate_stage_count (ps, SCHED_TIME (g->closing_branch) - (ii - 1));
162+
163+ if (stage_count == stage_count_curr)
164+ {
165+ if (dump_file)
166+ fprintf (dump_file, "SMS SC already optimized.\n");
167+
168+ ok = false;
169+ goto clear;
170+ }
171+
172+ if (dump_file)
173+ {
174+ fprintf (dump_file, "SMS Trying to optimize branch location\n");
175+ fprintf (dump_file, "SMS partial schedule before trial:\n");
176+ print_partial_schedule (ps, dump_file);
177+ }
178+
179+ /* First, normalize the partial scheduling. */
180+ reset_sched_times (ps, amount);
181+ rotate_partial_schedule (ps, amount);
182+ if (dump_file)
183+ {
184+ fprintf (dump_file,
185+ "SMS partial schedule after normalization (ii, %d, SC %d):\n",
186+ ii, stage_count);
187+ print_partial_schedule (ps, dump_file);
188+ }
189+
190+ if (SMODULO (SCHED_TIME (g->closing_branch), ii) == ii - 1)
191+ {
192+ ok = true;
193+ goto clear;
194+ }
195+
196+ sbitmap_ones (sched_nodes);
197+
198+ /* Calculate the new placement of the branch. It should be in row
199+ ii-1 and fall into it's scheduling window. */
200+ if (get_sched_window (ps, g->closing_branch, sched_nodes, ii, &start,
201+ &step, &end) == 0)
202+ {
203+ bool success;
204+ ps_insn_ptr next_ps_i;
205+ int branch_cycle = SCHED_TIME (g->closing_branch);
206+ int row = SMODULO (branch_cycle, ps->ii);
207+ int num_splits = 0;
208+ sbitmap must_precede, must_follow, tmp_precede, tmp_follow;
209+ int c;
210+
211+ if (dump_file)
212+ fprintf (dump_file, "\nTrying to schedule node %d "
213+ "INSN = %d in (%d .. %d) step %d\n",
214+ g->closing_branch->cuid,
215+ (INSN_UID (g->closing_branch->insn)), start, end, step);
216+
217+ gcc_assert ((step > 0 && start < end) || (step < 0 && start > end));
218+ if (step == 1)
219+ {
220+ c = start + ii - SMODULO (start, ii) - 1;
221+ gcc_assert (c >= start);
222+ if (c >= end)
223+ {
224+ ok = false;
225+ if (dump_file)
226+ fprintf (dump_file,
227+ "SMS failed to schedule branch at cycle: %d\n", c);
228+ goto clear;
229+ }
230+ }
231+ else
232+ {
233+ c = start - SMODULO (start, ii) - 1;
234+ gcc_assert (c <= start);
235+
236+ if (c <= end)
237+ {
238+ if (dump_file)
239+ fprintf (dump_file,
240+ "SMS failed to schedule branch at cycle: %d\n", c);
241+ ok = false;
242+ goto clear;
243+ }
244+ }
245+
246+ must_precede = sbitmap_alloc (g->num_nodes);
247+ must_follow = sbitmap_alloc (g->num_nodes);
248+
249+ /* Try to schedule the branch is it's new cycle. */
250+ calculate_must_precede_follow (g->closing_branch, start, end,
251+ step, ii, sched_nodes,
252+ must_precede, must_follow);
253+
254+ set_must_precede_follow (&tmp_follow, must_follow, &tmp_precede,
255+ must_precede, c, start, end, step);
256+
257+ /* Find the element in the partial schedule related to the closing
258+ branch so we can remove it from it's current cycle. */
259+ for (next_ps_i = ps->rows[row];
260+ next_ps_i; next_ps_i = next_ps_i->next_in_row)
261+ if (next_ps_i->node->cuid == g->closing_branch->cuid)
262+ break;
263+
264+ gcc_assert (next_ps_i);
265+ gcc_assert (remove_node_from_ps (ps, next_ps_i));
266+ success =
267+ try_scheduling_node_in_cycle (ps, g->closing_branch,
268+ g->closing_branch->cuid, c,
269+ sched_nodes, &num_splits,
270+ tmp_precede, tmp_follow);
271+ gcc_assert (num_splits == 0);
272+ if (!success)
273+ {
274+ if (dump_file)
275+ fprintf (dump_file,
276+ "SMS failed to schedule branch at cycle: %d, "
277+ "bringing it back to cycle %d\n", c, branch_cycle);
278+
279+ /* The branch was failed to be placed in row ii - 1.
280+ Put it back in it's original place in the partial
281+ schedualing. */
282+ set_must_precede_follow (&tmp_follow, must_follow, &tmp_precede,
283+ must_precede, branch_cycle, start, end,
284+ step);
285+ success =
286+ try_scheduling_node_in_cycle (ps, g->closing_branch,
287+ g->closing_branch->cuid,
288+ branch_cycle, sched_nodes,
289+ &num_splits, tmp_precede,
290+ tmp_follow);
291+ gcc_assert (success && (num_splits == 0));
292+ ok = false;
293+ }
294+ else
295+ {
296+ /* The branch is placed in row ii - 1. */
297+ if (dump_file)
298+ fprintf (dump_file,
299+ "SMS success in moving branch to cycle %d\n", c);
300+
301+ update_node_sched_params (g->closing_branch, ii, c,
302+ PS_MIN_CYCLE (ps));
303+ ok = true;
304+ }
305+
306+ free (must_precede);
307+ free (must_follow);
308+ }
309+
310+clear:
311+ free (sched_nodes);
312+ return ok;
313+}
314+
315 static void
316 duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage,
317 int to_stage, int for_prolog, rtx count_reg)
318@@ -1116,6 +1340,7 @@
319 int mii, rec_mii;
320 unsigned stage_count = 0;
321 HOST_WIDEST_INT loop_count = 0;
322+ bool opt_sc_p = false;
323
324 if (! (g = g_arr[loop->num]))
325 continue;
326@@ -1197,14 +1422,32 @@
327 set_node_sched_params (g);
328
329 ps = sms_schedule_by_order (g, mii, maxii, node_order);
330-
331- if (ps)
332- {
333- stage_count = calculate_stage_count (ps);
334- gcc_assert(stage_count >= 1);
335- PS_STAGE_COUNT(ps) = stage_count;
336- }
337-
338+
339+ if (ps)
340+ {
341+ /* Try to achieve optimized SC by normalizing the partial
342+ schedule (having the cycles start from cycle zero).
343+ The branch location must be placed in row ii-1 in the
344+ final scheduling. If failed, shift all instructions to
345+ position the branch in row ii-1. */
346+ opt_sc_p = optimize_sc (ps, g);
347+ if (opt_sc_p)
348+ stage_count = calculate_stage_count (ps, 0);
349+ else
350+ {
351+ /* Bring the branch to cycle ii-1. */
352+ int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1);
353+
354+ if (dump_file)
355+ fprintf (dump_file, "SMS schedule branch at cycle ii-1\n");
356+
357+ stage_count = calculate_stage_count (ps, amount);
358+ }
359+
360+ gcc_assert (stage_count >= 1);
361+ PS_STAGE_COUNT (ps) = stage_count;
362+ }
363+
364 /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
365 1 means that there is no interleaving between iterations thus
366 we let the scheduling passes do the job in this case. */
367@@ -1225,12 +1468,16 @@
368 else
369 {
370 struct undo_replace_buff_elem *reg_move_replaces;
371- int amount = SCHED_TIME (g->closing_branch) + 1;
372+
373+ if (!opt_sc_p)
374+ {
375+ /* Rotate the partial schedule to have the branch in row ii-1. */
376+ int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1);
377+
378+ reset_sched_times (ps, amount);
379+ rotate_partial_schedule (ps, amount);
380+ }
381
382- /* Set the stage boundaries. The closing_branch was scheduled
383- and should appear in the last (ii-1) row. */
384- reset_sched_times (ps, amount);
385- rotate_partial_schedule (ps, amount);
386 set_columns_for_ps (ps);
387
388 canon_loop (loop);
389@@ -1382,13 +1629,11 @@
390 scheduling window is empty and zero otherwise. */
391
392 static int
393-get_sched_window (partial_schedule_ptr ps, int *nodes_order, int i,
394+get_sched_window (partial_schedule_ptr ps, ddg_node_ptr u_node,
395 sbitmap sched_nodes, int ii, int *start_p, int *step_p, int *end_p)
396 {
397 int start, step, end;
398 ddg_edge_ptr e;
399- int u = nodes_order [i];
400- ddg_node_ptr u_node = &ps->g->nodes[u];
401 sbitmap psp = sbitmap_alloc (ps->g->num_nodes);
402 sbitmap pss = sbitmap_alloc (ps->g->num_nodes);
403 sbitmap u_node_preds = NODE_PREDECESSORS (u_node);
404@@ -1800,7 +2045,7 @@
405
406 /* Try to get non-empty scheduling window. */
407 success = 0;
408- if (get_sched_window (ps, nodes_order, i, sched_nodes, ii, &start,
409+ if (get_sched_window (ps, u_node, sched_nodes, ii, &start,
410 &step, &end) == 0)
411 {
412 if (dump_file)
413@@ -1817,24 +2062,11 @@
414
415 for (c = start; c != end; c += step)
416 {
417- sbitmap tmp_precede = NULL;
418- sbitmap tmp_follow = NULL;
419-
420- if (c == start)
421- {
422- if (step == 1)
423- tmp_precede = must_precede;
424- else /* step == -1. */
425- tmp_follow = must_follow;
426- }
427- if (c == end - step)
428- {
429- if (step == 1)
430- tmp_follow = must_follow;
431- else /* step == -1. */
432- tmp_precede = must_precede;
433- }
434-
435+ sbitmap tmp_precede, tmp_follow;
436+
437+ set_must_precede_follow (&tmp_follow, must_follow,
438+ &tmp_precede, must_precede,
439+ c, start, end, step);
440 success =
441 try_scheduling_node_in_cycle (ps, u_node, u, c,
442 sched_nodes,
443@@ -2899,12 +3131,10 @@
444 }
445
446 /* Calculate the stage count of the partial schedule PS. The calculation
447- takes into account the rotation to bring the closing branch to row
448- ii-1. */
449+ takes into account the rotation amount passed in ROTATION_AMOUNT. */
450 int
451-calculate_stage_count (partial_schedule_ptr ps)
452+calculate_stage_count (partial_schedule_ptr ps, int rotation_amount)
453 {
454- int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1;
455 int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
456 int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
457 int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii);
458
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106785.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106785.patch
deleted file mode 100644
index 608dd1833..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106785.patch
+++ /dev/null
@@ -1,39 +0,0 @@
1 2011-08-09 Revital Eres <revital.eres@linaro.org>
2
3 gcc/
4 Backport from trunk -r176972:
5
6 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove
7 the creation of anti-dep edge from a branch.
8 (add_cross_iteration_register_deps):
9 Create anti-dep edge from a branch.
10
11=== modified file 'gcc/ddg.c'
12--- old/gcc/ddg.c 2011-07-04 11:00:06 +0000
13+++ new/gcc/ddg.c 2011-07-31 11:29:10 +0000
14@@ -197,11 +197,6 @@
15 }
16 }
17
18- /* If a true dep edge enters the branch create an anti edge in the
19- opposite direction to prevent the creation of reg-moves. */
20- if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn))
21- create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1);
22-
23 latency = dep_cost (link);
24 e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
25 add_edge_to_ddg (g, e);
26@@ -306,8 +301,11 @@
27
28 gcc_assert (first_def_node);
29
30+ /* Always create the edge if the use node is a branch in
31+ order to prevent the creation of reg-moves. */
32 if (DF_REF_ID (last_def) != DF_REF_ID (first_def)
33- || !flag_modulo_sched_allow_regmoves)
34+ || !flag_modulo_sched_allow_regmoves
35+ || JUMP_P (use_node->insn))
36 create_ddg_dep_no_link (g, use_node, first_def_node, ANTI_DEP,
37 REG_DEP, 1);
38
39
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106786.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106786.patch
deleted file mode 100644
index 55b7cc107..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106786.patch
+++ /dev/null
@@ -1,94 +0,0 @@
12011-08-11 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-07-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
7
8 * config/arm/vfp.md ("*movdf_vfp"): Handle the VFP constraints
9 before the core constraints. Adjust attributes.
10 (*thumb2_movdf_vfp"): Likewise.
11
12=== modified file 'gcc/config/arm/vfp.md'
13--- old/gcc/config/arm/vfp.md 2011-01-20 22:03:29 +0000
14+++ new/gcc/config/arm/vfp.md 2011-07-27 12:59:19 +0000
15@@ -401,8 +401,8 @@
16 ;; DFmode moves
17
18 (define_insn "*movdf_vfp"
19- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
20- (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
21+ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r, m,w,r")
22+ (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
23 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
24 && ( register_operand (operands[0], DFmode)
25 || register_operand (operands[1], DFmode))"
26@@ -418,9 +418,9 @@
27 gcc_assert (TARGET_VFP_DOUBLE);
28 return \"fconstd%?\\t%P0, #%G1\";
29 case 3: case 4:
30+ return output_move_vfp (operands);
31+ case 5: case 6:
32 return output_move_double (operands);
33- case 5: case 6:
34- return output_move_vfp (operands);
35 case 7:
36 if (TARGET_VFP_SINGLE)
37 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
38@@ -435,7 +435,7 @@
39 "
40 [(set_attr "type"
41 "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
42- (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
43+ (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
44 (eq_attr "alternative" "7")
45 (if_then_else
46 (eq (symbol_ref "TARGET_VFP_SINGLE")
47@@ -449,8 +449,8 @@
48 )
49
50 (define_insn "*thumb2_movdf_vfp"
51- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
52- (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
53+ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r ,m,w,r")
54+ (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w, mF,r, w,r"))]
55 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
56 "*
57 {
58@@ -463,10 +463,10 @@
59 case 2:
60 gcc_assert (TARGET_VFP_DOUBLE);
61 return \"fconstd%?\\t%P0, #%G1\";
62- case 3: case 4: case 8:
63+ case 3: case 4:
64+ return output_move_vfp (operands);
65+ case 5: case 6: case 8:
66 return output_move_double (operands);
67- case 5: case 6:
68- return output_move_vfp (operands);
69 case 7:
70 if (TARGET_VFP_SINGLE)
71 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
72@@ -478,8 +478,8 @@
73 }
74 "
75 [(set_attr "type"
76- "r_2_f,f_2_r,fconstd,load2,store2,f_loadd,f_stored,ffarithd,*")
77- (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
78+ "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
79+ (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
80 (eq_attr "alternative" "7")
81 (if_then_else
82 (eq (symbol_ref "TARGET_VFP_SINGLE")
83@@ -487,8 +487,8 @@
84 (const_int 8)
85 (const_int 4))]
86 (const_int 4)))
87- (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
88- (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
89+ (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
90+ (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
91 )
92
93
94
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106787.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106787.patch
deleted file mode 100644
index bdb48ad1e..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106787.patch
+++ /dev/null
@@ -1,30 +0,0 @@
12011-08-15 Michael Hope <michael.hope@linaro.org>
2
3 Backport from mainline r177357
4
5 gcc/testsuite/
6 2011-08-04 Ian Bolton <ian.bolton@arm.com>
7
8 * gcc.target/arm/vfp-1.c: no large negative offsets on Thumb2.
9
10=== modified file 'gcc/testsuite/gcc.target/arm/vfp-1.c'
11--- old/gcc/testsuite/gcc.target/arm/vfp-1.c 2011-01-01 08:52:03 +0000
12+++ new/gcc/testsuite/gcc.target/arm/vfp-1.c 2011-08-09 23:22:51 +0000
13@@ -127,13 +127,13 @@
14
15 void test_ldst (float f[], double d[]) {
16 /* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */
17- /* { dg-final { scan-assembler "flds.+ \\\[r0, #-1020\\\]" } } */
18+ /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
19 /* { dg-final { scan-assembler "add.+ r0, #1024" } } */
20- /* { dg-final { scan-assembler "fsts.+ \\\[r0, #0\\\]\n" } } */
21+ /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\], #0\\\]\n" } } */
22 f[256] = f[255] + f[-255];
23
24 /* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */
25- /* { dg-final { scan-assembler "fldd.+ \\\[r1, #-1016\\\]" } } */
26+ /* { dg-final { scan-assembler "fldd.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
27 /* { dg-final { scan-assembler "fstd.+ \\\[r1, #256\\\]" } } */
28 d[32] = d[127] + d[-127];
29 }
30
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106789.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106789.patch
deleted file mode 100644
index a384ce7a1..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106789.patch
+++ /dev/null
@@ -1,33 +0,0 @@
12011-08-15 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 * config/rs6000/rs6000.c (paired_expand_vector_init): Don't create
5 CONST_VECTORs with symbolic elements.
6 (rs6000_expand_vector_init): Likewise.
7
8=== modified file 'gcc/config/rs6000/rs6000.c'
9--- old/gcc/config/rs6000/rs6000.c 2011-07-27 18:17:15 +0000
10+++ new/gcc/config/rs6000/rs6000.c 2011-08-16 08:59:36 +0000
11@@ -5134,7 +5134,9 @@
12 for (i = 0; i < n_elts; ++i)
13 {
14 x = XVECEXP (vals, 0, i);
15- if (!CONSTANT_P (x))
16+ if (!(CONST_INT_P (x)
17+ || GET_CODE (x) == CONST_DOUBLE
18+ || GET_CODE (x) == CONST_FIXED))
19 ++n_var;
20 }
21 if (n_var == 0)
22@@ -5286,7 +5288,9 @@
23 for (i = 0; i < n_elts; ++i)
24 {
25 x = XVECEXP (vals, 0, i);
26- if (!CONSTANT_P (x))
27+ if (!(CONST_INT_P (x)
28+ || GET_CODE (x) == CONST_DOUBLE
29+ || GET_CODE (x) == CONST_FIXED))
30 ++n_var, one_var = i;
31 else if (x != CONST0_RTX (inner_mode))
32 all_const_zero = false;
33
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106792.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106792.patch
deleted file mode 100644
index 12c578c2b..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106792.patch
+++ /dev/null
@@ -1,61 +0,0 @@
12011-08-18 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-08-12 Richard Sandiford <rdsandiford@googlemail.com>
7
8 * config/arm/arm.c (get_label_padding): New function.
9 (create_fix_barrier, arm_reorg): Use it.
10
11=== modified file 'gcc/config/arm/arm.c'
12--- old/gcc/config/arm/arm.c 2011-07-04 14:03:49 +0000
13+++ new/gcc/config/arm/arm.c 2011-08-12 08:08:31 +0000
14@@ -11769,6 +11769,19 @@
15 return 0;
16 }
17
18+/* Return the maximum amount of padding that will be inserted before
19+ label LABEL. */
20+
21+static HOST_WIDE_INT
22+get_label_padding (rtx label)
23+{
24+ HOST_WIDE_INT align, min_insn_size;
25+
26+ align = 1 << label_to_alignment (label);
27+ min_insn_size = TARGET_THUMB ? 2 : 4;
28+ return align > min_insn_size ? align - min_insn_size : 0;
29+}
30+
31 /* Move a minipool fix MP from its current location to before MAX_MP.
32 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
33 constraints may need updating. */
34@@ -12315,8 +12328,12 @@
35 within range. */
36 gcc_assert (GET_CODE (from) != BARRIER);
37
38- /* Count the length of this insn. */
39- count += get_attr_length (from);
40+ /* Count the length of this insn. This must stay in sync with the
41+ code that pushes minipool fixes. */
42+ if (LABEL_P (from))
43+ count += get_label_padding (from);
44+ else
45+ count += get_attr_length (from);
46
47 /* If there is a jump table, add its length. */
48 tmp = is_jump_table (from);
49@@ -12736,6 +12753,11 @@
50 insn = table;
51 }
52 }
53+ else if (LABEL_P (insn))
54+ /* Add the worst-case padding due to alignment. We don't add
55+ the _current_ padding because the minipool insertions
56+ themselves might change it. */
57+ address += get_label_padding (insn);
58 }
59
60 fix = minipool_fix_head;
61
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106794.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106794.patch
deleted file mode 100644
index 29663c64a..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106794.patch
+++ /dev/null
@@ -1,2648 +0,0 @@
12011-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 gcc/
4 * config/arm/arm.c (arm_init_neon_builtins): Use
5 n_operands instead of n_generator_args.
6
72011-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
8
9 Backport from mainline
10 2011-04-18 Jie Zhang <jie@codesourcery.com>
11 Richard Earnshaw <rearnsha@arm.com>
12
13 * arm.c (neon_builtin_type_bits): Remove.
14 (typedef enum neon_builtin_mode): New.
15 (T_MAX): Don't define.
16 (typedef enum neon_builtin_datum): Remove bits, codes[],
17 num_vars and base_fcode. Add mode, code and fcode.
18 (VAR1, VAR2, VAR3, VAR4, VAR5, VAR6, VAR7, VAR8, VAR9
19 VAR10): Change accordingly.
20 (neon_builtin_data[]): Change accordingly
21 (arm_init_neon_builtins): Change accordingly.
22 (neon_builtin_compare): Remove.
23 (locate_neon_builtin_icode): Remove.
24 (arm_expand_neon_builtin): Change accordingly.
25
26 * arm.h (enum arm_builtins): Move to ...
27 * arm.c (enum arm_builtins): ... here; and rearrange builtin code.
28
29 * arm.c (arm_builtin_decl): Declare.
30 (TARGET_BUILTIN_DECL): Define.
31 (enum arm_builtins): Correct ARM_BUILTIN_MAX.
32 (arm_builtin_decls[]): New.
33 (arm_init_neon_builtins): Store builtin declarations in
34 arm_builtin_decls[].
35 (arm_init_tls_builtins): Likewise.
36 (arm_init_iwmmxt_builtins): Likewise. Refactor initialization code.
37 (arm_builtin_decl): New.
38
39=== modified file 'gcc/config/arm/arm.c'
40--- old/gcc/config/arm/arm.c 2011-08-18 13:53:37 +0000
41+++ new/gcc/config/arm/arm.c 2011-08-24 17:35:16 +0000
42@@ -162,6 +162,7 @@
43 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
44 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
45 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
46+static tree arm_builtin_decl (unsigned, bool);
47 static void emit_constant_insn (rtx cond, rtx pattern);
48 static rtx emit_set_insn (rtx, rtx);
49 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
50@@ -415,6 +416,8 @@
51 #define TARGET_INIT_BUILTINS arm_init_builtins
52 #undef TARGET_EXPAND_BUILTIN
53 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
54+#undef TARGET_BUILTIN_DECL
55+#define TARGET_BUILTIN_DECL arm_builtin_decl
56
57 #undef TARGET_INIT_LIBFUNCS
58 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
59@@ -18147,505 +18150,31 @@
60 return value;
61 }
62
63-#define def_mbuiltin(MASK, NAME, TYPE, CODE) \
64- do \
65- { \
66- if ((MASK) & insn_flags) \
67- add_builtin_function ((NAME), (TYPE), (CODE), \
68- BUILT_IN_MD, NULL, NULL_TREE); \
69- } \
70- while (0)
71-
72-struct builtin_description
73-{
74- const unsigned int mask;
75- const enum insn_code icode;
76- const char * const name;
77- const enum arm_builtins code;
78- const enum rtx_code comparison;
79- const unsigned int flag;
80-};
81-
82-static const struct builtin_description bdesc_2arg[] =
83-{
84-#define IWMMXT_BUILTIN(code, string, builtin) \
85- { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
86- ARM_BUILTIN_##builtin, UNKNOWN, 0 },
87-
88- IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
89- IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
90- IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
91- IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
92- IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
93- IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
94- IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
95- IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
96- IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
97- IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
98- IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
99- IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
100- IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
101- IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
102- IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
103- IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
104- IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
105- IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
106- IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
107- IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
108- IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
109- IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
110- IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
111- IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
112- IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
113- IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
114- IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
115- IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
116- IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
117- IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
118- IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
119- IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
120- IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
121- IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
122- IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
123- IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
124- IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
125- IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
126- IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
127- IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
128- IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
129- IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
130- IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
131- IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
132- IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
133- IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
134- IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
135- IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
136- IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
137- IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
138- IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
139- IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
140- IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
141- IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
142- IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
143- IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
144- IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
145- IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
146-
147-#define IWMMXT_BUILTIN2(code, builtin) \
148- { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
149-
150- IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
151- IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
152- IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
153- IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
154- IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
155- IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
156- IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
157- IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI)
158- IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
159- IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI)
160- IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
161- IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
162- IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
163- IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI)
164- IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
165- IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI)
166- IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
167- IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
168- IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
169- IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI)
170- IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
171- IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI)
172- IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
173- IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
174- IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
175- IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
176- IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
177- IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
178- IWMMXT_BUILTIN2 (rordi3_di, WRORD)
179- IWMMXT_BUILTIN2 (rordi3, WRORDI)
180- IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
181- IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
182-};
183-
184-static const struct builtin_description bdesc_1arg[] =
185-{
186- IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
187- IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
188- IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
189- IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
190- IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
191- IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
192- IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
193- IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
194- IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
195- IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
196- IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
197- IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
198- IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
199- IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
200- IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
201- IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
202- IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
203- IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
204-};
205-
206-/* Set up all the iWMMXt builtins. This is
207- not called if TARGET_IWMMXT is zero. */
208-
209-static void
210-arm_init_iwmmxt_builtins (void)
211-{
212- const struct builtin_description * d;
213- size_t i;
214- tree endlink = void_list_node;
215-
216- tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
217- tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
218- tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
219-
220- tree int_ftype_int
221- = build_function_type (integer_type_node,
222- tree_cons (NULL_TREE, integer_type_node, endlink));
223- tree v8qi_ftype_v8qi_v8qi_int
224- = build_function_type (V8QI_type_node,
225- tree_cons (NULL_TREE, V8QI_type_node,
226- tree_cons (NULL_TREE, V8QI_type_node,
227- tree_cons (NULL_TREE,
228- integer_type_node,
229- endlink))));
230- tree v4hi_ftype_v4hi_int
231- = build_function_type (V4HI_type_node,
232- tree_cons (NULL_TREE, V4HI_type_node,
233- tree_cons (NULL_TREE, integer_type_node,
234- endlink)));
235- tree v2si_ftype_v2si_int
236- = build_function_type (V2SI_type_node,
237- tree_cons (NULL_TREE, V2SI_type_node,
238- tree_cons (NULL_TREE, integer_type_node,
239- endlink)));
240- tree v2si_ftype_di_di
241- = build_function_type (V2SI_type_node,
242- tree_cons (NULL_TREE, long_long_integer_type_node,
243- tree_cons (NULL_TREE, long_long_integer_type_node,
244- endlink)));
245- tree di_ftype_di_int
246- = build_function_type (long_long_integer_type_node,
247- tree_cons (NULL_TREE, long_long_integer_type_node,
248- tree_cons (NULL_TREE, integer_type_node,
249- endlink)));
250- tree di_ftype_di_int_int
251- = build_function_type (long_long_integer_type_node,
252- tree_cons (NULL_TREE, long_long_integer_type_node,
253- tree_cons (NULL_TREE, integer_type_node,
254- tree_cons (NULL_TREE,
255- integer_type_node,
256- endlink))));
257- tree int_ftype_v8qi
258- = build_function_type (integer_type_node,
259- tree_cons (NULL_TREE, V8QI_type_node,
260- endlink));
261- tree int_ftype_v4hi
262- = build_function_type (integer_type_node,
263- tree_cons (NULL_TREE, V4HI_type_node,
264- endlink));
265- tree int_ftype_v2si
266- = build_function_type (integer_type_node,
267- tree_cons (NULL_TREE, V2SI_type_node,
268- endlink));
269- tree int_ftype_v8qi_int
270- = build_function_type (integer_type_node,
271- tree_cons (NULL_TREE, V8QI_type_node,
272- tree_cons (NULL_TREE, integer_type_node,
273- endlink)));
274- tree int_ftype_v4hi_int
275- = build_function_type (integer_type_node,
276- tree_cons (NULL_TREE, V4HI_type_node,
277- tree_cons (NULL_TREE, integer_type_node,
278- endlink)));
279- tree int_ftype_v2si_int
280- = build_function_type (integer_type_node,
281- tree_cons (NULL_TREE, V2SI_type_node,
282- tree_cons (NULL_TREE, integer_type_node,
283- endlink)));
284- tree v8qi_ftype_v8qi_int_int
285- = build_function_type (V8QI_type_node,
286- tree_cons (NULL_TREE, V8QI_type_node,
287- tree_cons (NULL_TREE, integer_type_node,
288- tree_cons (NULL_TREE,
289- integer_type_node,
290- endlink))));
291- tree v4hi_ftype_v4hi_int_int
292- = build_function_type (V4HI_type_node,
293- tree_cons (NULL_TREE, V4HI_type_node,
294- tree_cons (NULL_TREE, integer_type_node,
295- tree_cons (NULL_TREE,
296- integer_type_node,
297- endlink))));
298- tree v2si_ftype_v2si_int_int
299- = build_function_type (V2SI_type_node,
300- tree_cons (NULL_TREE, V2SI_type_node,
301- tree_cons (NULL_TREE, integer_type_node,
302- tree_cons (NULL_TREE,
303- integer_type_node,
304- endlink))));
305- /* Miscellaneous. */
306- tree v8qi_ftype_v4hi_v4hi
307- = build_function_type (V8QI_type_node,
308- tree_cons (NULL_TREE, V4HI_type_node,
309- tree_cons (NULL_TREE, V4HI_type_node,
310- endlink)));
311- tree v4hi_ftype_v2si_v2si
312- = build_function_type (V4HI_type_node,
313- tree_cons (NULL_TREE, V2SI_type_node,
314- tree_cons (NULL_TREE, V2SI_type_node,
315- endlink)));
316- tree v2si_ftype_v4hi_v4hi
317- = build_function_type (V2SI_type_node,
318- tree_cons (NULL_TREE, V4HI_type_node,
319- tree_cons (NULL_TREE, V4HI_type_node,
320- endlink)));
321- tree v2si_ftype_v8qi_v8qi
322- = build_function_type (V2SI_type_node,
323- tree_cons (NULL_TREE, V8QI_type_node,
324- tree_cons (NULL_TREE, V8QI_type_node,
325- endlink)));
326- tree v4hi_ftype_v4hi_di
327- = build_function_type (V4HI_type_node,
328- tree_cons (NULL_TREE, V4HI_type_node,
329- tree_cons (NULL_TREE,
330- long_long_integer_type_node,
331- endlink)));
332- tree v2si_ftype_v2si_di
333- = build_function_type (V2SI_type_node,
334- tree_cons (NULL_TREE, V2SI_type_node,
335- tree_cons (NULL_TREE,
336- long_long_integer_type_node,
337- endlink)));
338- tree void_ftype_int_int
339- = build_function_type (void_type_node,
340- tree_cons (NULL_TREE, integer_type_node,
341- tree_cons (NULL_TREE, integer_type_node,
342- endlink)));
343- tree di_ftype_void
344- = build_function_type (long_long_unsigned_type_node, endlink);
345- tree di_ftype_v8qi
346- = build_function_type (long_long_integer_type_node,
347- tree_cons (NULL_TREE, V8QI_type_node,
348- endlink));
349- tree di_ftype_v4hi
350- = build_function_type (long_long_integer_type_node,
351- tree_cons (NULL_TREE, V4HI_type_node,
352- endlink));
353- tree di_ftype_v2si
354- = build_function_type (long_long_integer_type_node,
355- tree_cons (NULL_TREE, V2SI_type_node,
356- endlink));
357- tree v2si_ftype_v4hi
358- = build_function_type (V2SI_type_node,
359- tree_cons (NULL_TREE, V4HI_type_node,
360- endlink));
361- tree v4hi_ftype_v8qi
362- = build_function_type (V4HI_type_node,
363- tree_cons (NULL_TREE, V8QI_type_node,
364- endlink));
365-
366- tree di_ftype_di_v4hi_v4hi
367- = build_function_type (long_long_unsigned_type_node,
368- tree_cons (NULL_TREE,
369- long_long_unsigned_type_node,
370- tree_cons (NULL_TREE, V4HI_type_node,
371- tree_cons (NULL_TREE,
372- V4HI_type_node,
373- endlink))));
374-
375- tree di_ftype_v4hi_v4hi
376- = build_function_type (long_long_unsigned_type_node,
377- tree_cons (NULL_TREE, V4HI_type_node,
378- tree_cons (NULL_TREE, V4HI_type_node,
379- endlink)));
380-
381- /* Normal vector binops. */
382- tree v8qi_ftype_v8qi_v8qi
383- = build_function_type (V8QI_type_node,
384- tree_cons (NULL_TREE, V8QI_type_node,
385- tree_cons (NULL_TREE, V8QI_type_node,
386- endlink)));
387- tree v4hi_ftype_v4hi_v4hi
388- = build_function_type (V4HI_type_node,
389- tree_cons (NULL_TREE, V4HI_type_node,
390- tree_cons (NULL_TREE, V4HI_type_node,
391- endlink)));
392- tree v2si_ftype_v2si_v2si
393- = build_function_type (V2SI_type_node,
394- tree_cons (NULL_TREE, V2SI_type_node,
395- tree_cons (NULL_TREE, V2SI_type_node,
396- endlink)));
397- tree di_ftype_di_di
398- = build_function_type (long_long_unsigned_type_node,
399- tree_cons (NULL_TREE, long_long_unsigned_type_node,
400- tree_cons (NULL_TREE,
401- long_long_unsigned_type_node,
402- endlink)));
403-
404- /* Add all builtins that are more or less simple operations on two
405- operands. */
406- for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
407- {
408- /* Use one of the operands; the target can have a different mode for
409- mask-generating compares. */
410- enum machine_mode mode;
411- tree type;
412-
413- if (d->name == 0)
414- continue;
415-
416- mode = insn_data[d->icode].operand[1].mode;
417-
418- switch (mode)
419- {
420- case V8QImode:
421- type = v8qi_ftype_v8qi_v8qi;
422- break;
423- case V4HImode:
424- type = v4hi_ftype_v4hi_v4hi;
425- break;
426- case V2SImode:
427- type = v2si_ftype_v2si_v2si;
428- break;
429- case DImode:
430- type = di_ftype_di_di;
431- break;
432-
433- default:
434- gcc_unreachable ();
435- }
436-
437- def_mbuiltin (d->mask, d->name, type, d->code);
438- }
439-
440- /* Add the remaining MMX insns with somewhat more complicated types. */
441- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
442- def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
443- def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
444-
445- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
446- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
447- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
448- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
449- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
450- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
451-
452- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
453- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
454- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
455- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
456- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
457- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
458-
459- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
460- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
461- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
462- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
463- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
464- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
465-
466- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
467- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
468- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
469- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
470- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
471- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
472-
473- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
474-
475- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
476- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
477- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
478- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
479-
480- def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
481- def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
482- def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
483- def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
484- def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
485- def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
486- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
487- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
488- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
489-
490- def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
491- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
492- def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
493-
494- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
495- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
496- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
497-
498- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
499- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
500- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
501- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
502- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
503- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
504-
505- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
506- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
507- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
508- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
509- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
510- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
511- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
512- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
513- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
514- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
515- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
516- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
517-
518- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
519- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
520- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
521- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
522-
523- def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
524- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
525- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
526- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
527- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
528- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
529- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
530-}
531-
532-static void
533-arm_init_tls_builtins (void)
534-{
535- tree ftype, decl;
536-
537- ftype = build_function_type (ptr_type_node, void_list_node);
538- decl = add_builtin_function ("__builtin_thread_pointer", ftype,
539- ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
540- NULL, NULL_TREE);
541- TREE_NOTHROW (decl) = 1;
542- TREE_READONLY (decl) = 1;
543-}
544-
545-enum neon_builtin_type_bits {
546- T_V8QI = 0x0001,
547- T_V4HI = 0x0002,
548- T_V2SI = 0x0004,
549- T_V2SF = 0x0008,
550- T_DI = 0x0010,
551- T_DREG = 0x001F,
552- T_V16QI = 0x0020,
553- T_V8HI = 0x0040,
554- T_V4SI = 0x0080,
555- T_V4SF = 0x0100,
556- T_V2DI = 0x0200,
557- T_TI = 0x0400,
558- T_QREG = 0x07E0,
559- T_EI = 0x0800,
560- T_OI = 0x1000
561-};
562+typedef enum {
563+ T_V8QI,
564+ T_V4HI,
565+ T_V2SI,
566+ T_V2SF,
567+ T_DI,
568+ T_V16QI,
569+ T_V8HI,
570+ T_V4SI,
571+ T_V4SF,
572+ T_V2DI,
573+ T_TI,
574+ T_EI,
575+ T_OI,
576+ T_MAX /* Size of enum. Keep last. */
577+} neon_builtin_type_mode;
578+
579+#define TYPE_MODE_BIT(X) (1 << (X))
580+
581+#define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI) \
582+ | TYPE_MODE_BIT (T_V2SI) | TYPE_MODE_BIT (T_V2SF) \
583+ | TYPE_MODE_BIT (T_DI))
584+#define TB_QREG (TYPE_MODE_BIT (T_V16QI) | TYPE_MODE_BIT (T_V8HI) \
585+ | TYPE_MODE_BIT (T_V4SI) | TYPE_MODE_BIT (T_V4SF) \
586+ | TYPE_MODE_BIT (T_V2DI) | TYPE_MODE_BIT (T_TI))
587
588 #define v8qi_UP T_V8QI
589 #define v4hi_UP T_V4HI
590@@ -18663,8 +18192,6 @@
591
592 #define UP(X) X##_UP
593
594-#define T_MAX 13
595-
596 typedef enum {
597 NEON_BINOP,
598 NEON_TERNOP,
599@@ -18708,49 +18235,42 @@
600 typedef struct {
601 const char *name;
602 const neon_itype itype;
603- const int bits;
604- const enum insn_code codes[T_MAX];
605- const unsigned int num_vars;
606- unsigned int base_fcode;
607+ const neon_builtin_type_mode mode;
608+ const enum insn_code code;
609+ unsigned int fcode;
610 } neon_builtin_datum;
611
612 #define CF(N,X) CODE_FOR_neon_##N##X
613
614 #define VAR1(T, N, A) \
615- #N, NEON_##T, UP (A), { CF (N, A) }, 1, 0
616+ {#N, NEON_##T, UP (A), CF (N, A), 0}
617 #define VAR2(T, N, A, B) \
618- #N, NEON_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0
619+ VAR1 (T, N, A), \
620+ {#N, NEON_##T, UP (B), CF (N, B), 0}
621 #define VAR3(T, N, A, B, C) \
622- #N, NEON_##T, UP (A) | UP (B) | UP (C), \
623- { CF (N, A), CF (N, B), CF (N, C) }, 3, 0
624+ VAR2 (T, N, A, B), \
625+ {#N, NEON_##T, UP (C), CF (N, C), 0}
626 #define VAR4(T, N, A, B, C, D) \
627- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D), \
628- { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0
629+ VAR3 (T, N, A, B, C), \
630+ {#N, NEON_##T, UP (D), CF (N, D), 0}
631 #define VAR5(T, N, A, B, C, D, E) \
632- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \
633- { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0
634+ VAR4 (T, N, A, B, C, D), \
635+ {#N, NEON_##T, UP (E), CF (N, E), 0}
636 #define VAR6(T, N, A, B, C, D, E, F) \
637- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \
638- { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0
639+ VAR5 (T, N, A, B, C, D, E), \
640+ {#N, NEON_##T, UP (F), CF (N, F), 0}
641 #define VAR7(T, N, A, B, C, D, E, F, G) \
642- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G), \
643- { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
644- CF (N, G) }, 7, 0
645+ VAR6 (T, N, A, B, C, D, E, F), \
646+ {#N, NEON_##T, UP (G), CF (N, G), 0}
647 #define VAR8(T, N, A, B, C, D, E, F, G, H) \
648- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
649- | UP (H), \
650- { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
651- CF (N, G), CF (N, H) }, 8, 0
652+ VAR7 (T, N, A, B, C, D, E, F, G), \
653+ {#N, NEON_##T, UP (H), CF (N, H), 0}
654 #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
655- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
656- | UP (H) | UP (I), \
657- { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
658- CF (N, G), CF (N, H), CF (N, I) }, 9, 0
659+ VAR8 (T, N, A, B, C, D, E, F, G, H), \
660+ {#N, NEON_##T, UP (I), CF (N, I), 0}
661 #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
662- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
663- | UP (H) | UP (I) | UP (J), \
664- { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
665- CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0
666+ VAR9 (T, N, A, B, C, D, E, F, G, H, I), \
667+ {#N, NEON_##T, UP (J), CF (N, J), 0}
668
669 /* The mode entries in the following table correspond to the "key" type of the
670 instruction variant, i.e. equivalent to that which would be specified after
671@@ -18758,192 +18278,190 @@
672 (Signed/unsigned/polynomial types are not differentiated between though, and
673 are all mapped onto the same mode for a given element size.) The modes
674 listed per instruction should be the same as those defined for that
675- instruction's pattern in neon.md.
676- WARNING: Variants should be listed in the same increasing order as
677- neon_builtin_type_bits. */
678+ instruction's pattern in neon.md. */
679
680 static neon_builtin_datum neon_builtin_data[] =
681 {
682- { VAR10 (BINOP, vadd,
683- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
684- { VAR3 (BINOP, vaddl, v8qi, v4hi, v2si) },
685- { VAR3 (BINOP, vaddw, v8qi, v4hi, v2si) },
686- { VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
687- { VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
688- { VAR3 (BINOP, vaddhn, v8hi, v4si, v2di) },
689- { VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
690- { VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
691- { VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si) },
692- { VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
693- { VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si) },
694- { VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si) },
695- { VAR2 (TERNOP, vqdmlal, v4hi, v2si) },
696- { VAR2 (TERNOP, vqdmlsl, v4hi, v2si) },
697- { VAR3 (BINOP, vmull, v8qi, v4hi, v2si) },
698- { VAR2 (SCALARMULL, vmull_n, v4hi, v2si) },
699- { VAR2 (LANEMULL, vmull_lane, v4hi, v2si) },
700- { VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si) },
701- { VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si) },
702- { VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si) },
703- { VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si) },
704- { VAR2 (BINOP, vqdmull, v4hi, v2si) },
705- { VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
706- { VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
707- { VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
708- { VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di) },
709- { VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di) },
710- { VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di) },
711- { VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
712- { VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
713- { VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
714- { VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si) },
715- { VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
716- { VAR10 (BINOP, vsub,
717- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
718- { VAR3 (BINOP, vsubl, v8qi, v4hi, v2si) },
719- { VAR3 (BINOP, vsubw, v8qi, v4hi, v2si) },
720- { VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
721- { VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
722- { VAR3 (BINOP, vsubhn, v8hi, v4si, v2di) },
723- { VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
724- { VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
725- { VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
726- { VAR2 (BINOP, vcage, v2sf, v4sf) },
727- { VAR2 (BINOP, vcagt, v2sf, v4sf) },
728- { VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
729- { VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
730- { VAR3 (BINOP, vabdl, v8qi, v4hi, v2si) },
731- { VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
732- { VAR3 (TERNOP, vabal, v8qi, v4hi, v2si) },
733- { VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
734- { VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
735- { VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf) },
736- { VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
737- { VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
738- { VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf) },
739- { VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf) },
740- { VAR2 (BINOP, vrecps, v2sf, v4sf) },
741- { VAR2 (BINOP, vrsqrts, v2sf, v4sf) },
742- { VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
743- { VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
744- { VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
745- { VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
746- { VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
747- { VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
748- { VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
749- { VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
750- { VAR2 (UNOP, vcnt, v8qi, v16qi) },
751- { VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf) },
752- { VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf) },
753- { VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
754+ VAR10 (BINOP, vadd,
755+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
756+ VAR3 (BINOP, vaddl, v8qi, v4hi, v2si),
757+ VAR3 (BINOP, vaddw, v8qi, v4hi, v2si),
758+ VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
759+ VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
760+ VAR3 (BINOP, vaddhn, v8hi, v4si, v2di),
761+ VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
762+ VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
763+ VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si),
764+ VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
765+ VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si),
766+ VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si),
767+ VAR2 (TERNOP, vqdmlal, v4hi, v2si),
768+ VAR2 (TERNOP, vqdmlsl, v4hi, v2si),
769+ VAR3 (BINOP, vmull, v8qi, v4hi, v2si),
770+ VAR2 (SCALARMULL, vmull_n, v4hi, v2si),
771+ VAR2 (LANEMULL, vmull_lane, v4hi, v2si),
772+ VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si),
773+ VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si),
774+ VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si),
775+ VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si),
776+ VAR2 (BINOP, vqdmull, v4hi, v2si),
777+ VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
778+ VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
779+ VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
780+ VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di),
781+ VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di),
782+ VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di),
783+ VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
784+ VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
785+ VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
786+ VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si),
787+ VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
788+ VAR10 (BINOP, vsub,
789+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
790+ VAR3 (BINOP, vsubl, v8qi, v4hi, v2si),
791+ VAR3 (BINOP, vsubw, v8qi, v4hi, v2si),
792+ VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
793+ VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
794+ VAR3 (BINOP, vsubhn, v8hi, v4si, v2di),
795+ VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
796+ VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
797+ VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
798+ VAR2 (BINOP, vcage, v2sf, v4sf),
799+ VAR2 (BINOP, vcagt, v2sf, v4sf),
800+ VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
801+ VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
802+ VAR3 (BINOP, vabdl, v8qi, v4hi, v2si),
803+ VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
804+ VAR3 (TERNOP, vabal, v8qi, v4hi, v2si),
805+ VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
806+ VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
807+ VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf),
808+ VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
809+ VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
810+ VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf),
811+ VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf),
812+ VAR2 (BINOP, vrecps, v2sf, v4sf),
813+ VAR2 (BINOP, vrsqrts, v2sf, v4sf),
814+ VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
815+ VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
816+ VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
817+ VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
818+ VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
819+ VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
820+ VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
821+ VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
822+ VAR2 (UNOP, vcnt, v8qi, v16qi),
823+ VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf),
824+ VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf),
825+ VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
826 /* FIXME: vget_lane supports more variants than this! */
827- { VAR10 (GETLANE, vget_lane,
828- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
829- { VAR10 (SETLANE, vset_lane,
830- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
831- { VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di) },
832- { VAR10 (DUP, vdup_n,
833- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
834- { VAR10 (DUPLANE, vdup_lane,
835- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
836- { VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di) },
837- { VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di) },
838- { VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di) },
839- { VAR3 (UNOP, vmovn, v8hi, v4si, v2di) },
840- { VAR3 (UNOP, vqmovn, v8hi, v4si, v2di) },
841- { VAR3 (UNOP, vqmovun, v8hi, v4si, v2di) },
842- { VAR3 (UNOP, vmovl, v8qi, v4hi, v2si) },
843- { VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
844- { VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
845- { VAR2 (LANEMAC, vmlal_lane, v4hi, v2si) },
846- { VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si) },
847- { VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
848- { VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si) },
849- { VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si) },
850- { VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
851- { VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
852- { VAR2 (SCALARMAC, vmlal_n, v4hi, v2si) },
853- { VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si) },
854- { VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
855- { VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si) },
856- { VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si) },
857- { VAR10 (BINOP, vext,
858- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
859- { VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
860- { VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi) },
861- { VAR2 (UNOP, vrev16, v8qi, v16qi) },
862- { VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf) },
863- { VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf) },
864- { VAR10 (SELECT, vbsl,
865- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
866- { VAR1 (VTBL, vtbl1, v8qi) },
867- { VAR1 (VTBL, vtbl2, v8qi) },
868- { VAR1 (VTBL, vtbl3, v8qi) },
869- { VAR1 (VTBL, vtbl4, v8qi) },
870- { VAR1 (VTBX, vtbx1, v8qi) },
871- { VAR1 (VTBX, vtbx2, v8qi) },
872- { VAR1 (VTBX, vtbx3, v8qi) },
873- { VAR1 (VTBX, vtbx4, v8qi) },
874- { VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
875- { VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
876- { VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
877- { VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di) },
878- { VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di) },
879- { VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di) },
880- { VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di) },
881- { VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di) },
882- { VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di) },
883- { VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di) },
884- { VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di) },
885- { VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di) },
886- { VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di) },
887- { VAR10 (LOAD1, vld1,
888- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
889- { VAR10 (LOAD1LANE, vld1_lane,
890- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
891- { VAR10 (LOAD1, vld1_dup,
892- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
893- { VAR10 (STORE1, vst1,
894- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
895- { VAR10 (STORE1LANE, vst1_lane,
896- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
897- { VAR9 (LOADSTRUCT,
898- vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
899- { VAR7 (LOADSTRUCTLANE, vld2_lane,
900- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
901- { VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di) },
902- { VAR9 (STORESTRUCT, vst2,
903- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
904- { VAR7 (STORESTRUCTLANE, vst2_lane,
905- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
906- { VAR9 (LOADSTRUCT,
907- vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
908- { VAR7 (LOADSTRUCTLANE, vld3_lane,
909- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
910- { VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di) },
911- { VAR9 (STORESTRUCT, vst3,
912- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
913- { VAR7 (STORESTRUCTLANE, vst3_lane,
914- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
915- { VAR9 (LOADSTRUCT, vld4,
916- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
917- { VAR7 (LOADSTRUCTLANE, vld4_lane,
918- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
919- { VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di) },
920- { VAR9 (STORESTRUCT, vst4,
921- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
922- { VAR7 (STORESTRUCTLANE, vst4_lane,
923- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
924- { VAR10 (LOGICBINOP, vand,
925- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
926- { VAR10 (LOGICBINOP, vorr,
927- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
928- { VAR10 (BINOP, veor,
929- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
930- { VAR10 (LOGICBINOP, vbic,
931- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
932- { VAR10 (LOGICBINOP, vorn,
933- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }
934+ VAR10 (GETLANE, vget_lane,
935+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
936+ VAR10 (SETLANE, vset_lane,
937+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
938+ VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di),
939+ VAR10 (DUP, vdup_n,
940+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
941+ VAR10 (DUPLANE, vdup_lane,
942+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
943+ VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di),
944+ VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di),
945+ VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di),
946+ VAR3 (UNOP, vmovn, v8hi, v4si, v2di),
947+ VAR3 (UNOP, vqmovn, v8hi, v4si, v2di),
948+ VAR3 (UNOP, vqmovun, v8hi, v4si, v2di),
949+ VAR3 (UNOP, vmovl, v8qi, v4hi, v2si),
950+ VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
951+ VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
952+ VAR2 (LANEMAC, vmlal_lane, v4hi, v2si),
953+ VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si),
954+ VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
955+ VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si),
956+ VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si),
957+ VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
958+ VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
959+ VAR2 (SCALARMAC, vmlal_n, v4hi, v2si),
960+ VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si),
961+ VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
962+ VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si),
963+ VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si),
964+ VAR10 (BINOP, vext,
965+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
966+ VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
967+ VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi),
968+ VAR2 (UNOP, vrev16, v8qi, v16qi),
969+ VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf),
970+ VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf),
971+ VAR10 (SELECT, vbsl,
972+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
973+ VAR1 (VTBL, vtbl1, v8qi),
974+ VAR1 (VTBL, vtbl2, v8qi),
975+ VAR1 (VTBL, vtbl3, v8qi),
976+ VAR1 (VTBL, vtbl4, v8qi),
977+ VAR1 (VTBX, vtbx1, v8qi),
978+ VAR1 (VTBX, vtbx2, v8qi),
979+ VAR1 (VTBX, vtbx3, v8qi),
980+ VAR1 (VTBX, vtbx4, v8qi),
981+ VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
982+ VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
983+ VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
984+ VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di),
985+ VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di),
986+ VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di),
987+ VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di),
988+ VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di),
989+ VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di),
990+ VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di),
991+ VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di),
992+ VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di),
993+ VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di),
994+ VAR10 (LOAD1, vld1,
995+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
996+ VAR10 (LOAD1LANE, vld1_lane,
997+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
998+ VAR10 (LOAD1, vld1_dup,
999+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1000+ VAR10 (STORE1, vst1,
1001+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1002+ VAR10 (STORE1LANE, vst1_lane,
1003+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1004+ VAR9 (LOADSTRUCT,
1005+ vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
1006+ VAR7 (LOADSTRUCTLANE, vld2_lane,
1007+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
1008+ VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di),
1009+ VAR9 (STORESTRUCT, vst2,
1010+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
1011+ VAR7 (STORESTRUCTLANE, vst2_lane,
1012+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
1013+ VAR9 (LOADSTRUCT,
1014+ vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
1015+ VAR7 (LOADSTRUCTLANE, vld3_lane,
1016+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
1017+ VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di),
1018+ VAR9 (STORESTRUCT, vst3,
1019+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
1020+ VAR7 (STORESTRUCTLANE, vst3_lane,
1021+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
1022+ VAR9 (LOADSTRUCT, vld4,
1023+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
1024+ VAR7 (LOADSTRUCTLANE, vld4_lane,
1025+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
1026+ VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di),
1027+ VAR9 (STORESTRUCT, vst4,
1028+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
1029+ VAR7 (STORESTRUCTLANE, vst4_lane,
1030+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
1031+ VAR10 (LOGICBINOP, vand,
1032+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1033+ VAR10 (LOGICBINOP, vorr,
1034+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1035+ VAR10 (BINOP, veor,
1036+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1037+ VAR10 (LOGICBINOP, vbic,
1038+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1039+ VAR10 (LOGICBINOP, vorn,
1040+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
1041 };
1042
1043 #undef CF
1044@@ -18958,10 +18476,185 @@
1045 #undef VAR9
1046 #undef VAR10
1047
1048+/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
1049+ symbolic names defined here (which would require too much duplication).
1050+ FIXME? */
1051+enum arm_builtins
1052+{
1053+ ARM_BUILTIN_GETWCX,
1054+ ARM_BUILTIN_SETWCX,
1055+
1056+ ARM_BUILTIN_WZERO,
1057+
1058+ ARM_BUILTIN_WAVG2BR,
1059+ ARM_BUILTIN_WAVG2HR,
1060+ ARM_BUILTIN_WAVG2B,
1061+ ARM_BUILTIN_WAVG2H,
1062+
1063+ ARM_BUILTIN_WACCB,
1064+ ARM_BUILTIN_WACCH,
1065+ ARM_BUILTIN_WACCW,
1066+
1067+ ARM_BUILTIN_WMACS,
1068+ ARM_BUILTIN_WMACSZ,
1069+ ARM_BUILTIN_WMACU,
1070+ ARM_BUILTIN_WMACUZ,
1071+
1072+ ARM_BUILTIN_WSADB,
1073+ ARM_BUILTIN_WSADBZ,
1074+ ARM_BUILTIN_WSADH,
1075+ ARM_BUILTIN_WSADHZ,
1076+
1077+ ARM_BUILTIN_WALIGN,
1078+
1079+ ARM_BUILTIN_TMIA,
1080+ ARM_BUILTIN_TMIAPH,
1081+ ARM_BUILTIN_TMIABB,
1082+ ARM_BUILTIN_TMIABT,
1083+ ARM_BUILTIN_TMIATB,
1084+ ARM_BUILTIN_TMIATT,
1085+
1086+ ARM_BUILTIN_TMOVMSKB,
1087+ ARM_BUILTIN_TMOVMSKH,
1088+ ARM_BUILTIN_TMOVMSKW,
1089+
1090+ ARM_BUILTIN_TBCSTB,
1091+ ARM_BUILTIN_TBCSTH,
1092+ ARM_BUILTIN_TBCSTW,
1093+
1094+ ARM_BUILTIN_WMADDS,
1095+ ARM_BUILTIN_WMADDU,
1096+
1097+ ARM_BUILTIN_WPACKHSS,
1098+ ARM_BUILTIN_WPACKWSS,
1099+ ARM_BUILTIN_WPACKDSS,
1100+ ARM_BUILTIN_WPACKHUS,
1101+ ARM_BUILTIN_WPACKWUS,
1102+ ARM_BUILTIN_WPACKDUS,
1103+
1104+ ARM_BUILTIN_WADDB,
1105+ ARM_BUILTIN_WADDH,
1106+ ARM_BUILTIN_WADDW,
1107+ ARM_BUILTIN_WADDSSB,
1108+ ARM_BUILTIN_WADDSSH,
1109+ ARM_BUILTIN_WADDSSW,
1110+ ARM_BUILTIN_WADDUSB,
1111+ ARM_BUILTIN_WADDUSH,
1112+ ARM_BUILTIN_WADDUSW,
1113+ ARM_BUILTIN_WSUBB,
1114+ ARM_BUILTIN_WSUBH,
1115+ ARM_BUILTIN_WSUBW,
1116+ ARM_BUILTIN_WSUBSSB,
1117+ ARM_BUILTIN_WSUBSSH,
1118+ ARM_BUILTIN_WSUBSSW,
1119+ ARM_BUILTIN_WSUBUSB,
1120+ ARM_BUILTIN_WSUBUSH,
1121+ ARM_BUILTIN_WSUBUSW,
1122+
1123+ ARM_BUILTIN_WAND,
1124+ ARM_BUILTIN_WANDN,
1125+ ARM_BUILTIN_WOR,
1126+ ARM_BUILTIN_WXOR,
1127+
1128+ ARM_BUILTIN_WCMPEQB,
1129+ ARM_BUILTIN_WCMPEQH,
1130+ ARM_BUILTIN_WCMPEQW,
1131+ ARM_BUILTIN_WCMPGTUB,
1132+ ARM_BUILTIN_WCMPGTUH,
1133+ ARM_BUILTIN_WCMPGTUW,
1134+ ARM_BUILTIN_WCMPGTSB,
1135+ ARM_BUILTIN_WCMPGTSH,
1136+ ARM_BUILTIN_WCMPGTSW,
1137+
1138+ ARM_BUILTIN_TEXTRMSB,
1139+ ARM_BUILTIN_TEXTRMSH,
1140+ ARM_BUILTIN_TEXTRMSW,
1141+ ARM_BUILTIN_TEXTRMUB,
1142+ ARM_BUILTIN_TEXTRMUH,
1143+ ARM_BUILTIN_TEXTRMUW,
1144+ ARM_BUILTIN_TINSRB,
1145+ ARM_BUILTIN_TINSRH,
1146+ ARM_BUILTIN_TINSRW,
1147+
1148+ ARM_BUILTIN_WMAXSW,
1149+ ARM_BUILTIN_WMAXSH,
1150+ ARM_BUILTIN_WMAXSB,
1151+ ARM_BUILTIN_WMAXUW,
1152+ ARM_BUILTIN_WMAXUH,
1153+ ARM_BUILTIN_WMAXUB,
1154+ ARM_BUILTIN_WMINSW,
1155+ ARM_BUILTIN_WMINSH,
1156+ ARM_BUILTIN_WMINSB,
1157+ ARM_BUILTIN_WMINUW,
1158+ ARM_BUILTIN_WMINUH,
1159+ ARM_BUILTIN_WMINUB,
1160+
1161+ ARM_BUILTIN_WMULUM,
1162+ ARM_BUILTIN_WMULSM,
1163+ ARM_BUILTIN_WMULUL,
1164+
1165+ ARM_BUILTIN_PSADBH,
1166+ ARM_BUILTIN_WSHUFH,
1167+
1168+ ARM_BUILTIN_WSLLH,
1169+ ARM_BUILTIN_WSLLW,
1170+ ARM_BUILTIN_WSLLD,
1171+ ARM_BUILTIN_WSRAH,
1172+ ARM_BUILTIN_WSRAW,
1173+ ARM_BUILTIN_WSRAD,
1174+ ARM_BUILTIN_WSRLH,
1175+ ARM_BUILTIN_WSRLW,
1176+ ARM_BUILTIN_WSRLD,
1177+ ARM_BUILTIN_WRORH,
1178+ ARM_BUILTIN_WRORW,
1179+ ARM_BUILTIN_WRORD,
1180+ ARM_BUILTIN_WSLLHI,
1181+ ARM_BUILTIN_WSLLWI,
1182+ ARM_BUILTIN_WSLLDI,
1183+ ARM_BUILTIN_WSRAHI,
1184+ ARM_BUILTIN_WSRAWI,
1185+ ARM_BUILTIN_WSRADI,
1186+ ARM_BUILTIN_WSRLHI,
1187+ ARM_BUILTIN_WSRLWI,
1188+ ARM_BUILTIN_WSRLDI,
1189+ ARM_BUILTIN_WRORHI,
1190+ ARM_BUILTIN_WRORWI,
1191+ ARM_BUILTIN_WRORDI,
1192+
1193+ ARM_BUILTIN_WUNPCKIHB,
1194+ ARM_BUILTIN_WUNPCKIHH,
1195+ ARM_BUILTIN_WUNPCKIHW,
1196+ ARM_BUILTIN_WUNPCKILB,
1197+ ARM_BUILTIN_WUNPCKILH,
1198+ ARM_BUILTIN_WUNPCKILW,
1199+
1200+ ARM_BUILTIN_WUNPCKEHSB,
1201+ ARM_BUILTIN_WUNPCKEHSH,
1202+ ARM_BUILTIN_WUNPCKEHSW,
1203+ ARM_BUILTIN_WUNPCKEHUB,
1204+ ARM_BUILTIN_WUNPCKEHUH,
1205+ ARM_BUILTIN_WUNPCKEHUW,
1206+ ARM_BUILTIN_WUNPCKELSB,
1207+ ARM_BUILTIN_WUNPCKELSH,
1208+ ARM_BUILTIN_WUNPCKELSW,
1209+ ARM_BUILTIN_WUNPCKELUB,
1210+ ARM_BUILTIN_WUNPCKELUH,
1211+ ARM_BUILTIN_WUNPCKELUW,
1212+
1213+ ARM_BUILTIN_THREAD_POINTER,
1214+
1215+ ARM_BUILTIN_NEON_BASE,
1216+
1217+ ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE + ARRAY_SIZE (neon_builtin_data)
1218+};
1219+
1220+static GTY(()) tree arm_builtin_decls[ARM_BUILTIN_MAX];
1221+
1222 static void
1223 arm_init_neon_builtins (void)
1224 {
1225- unsigned int i, fcode = ARM_BUILTIN_NEON_BASE;
1226+ unsigned int i, fcode;
1227+ tree decl;
1228
1229 tree neon_intQI_type_node;
1230 tree neon_intHI_type_node;
1231@@ -19209,250 +18902,740 @@
1232 }
1233 }
1234
1235- for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++)
1236+ for (i = 0, fcode = ARM_BUILTIN_NEON_BASE;
1237+ i < ARRAY_SIZE (neon_builtin_data);
1238+ i++, fcode++)
1239 {
1240 neon_builtin_datum *d = &neon_builtin_data[i];
1241- unsigned int j, codeidx = 0;
1242-
1243- d->base_fcode = fcode;
1244-
1245- for (j = 0; j < T_MAX; j++)
1246- {
1247- const char* const modenames[] = {
1248- "v8qi", "v4hi", "v2si", "v2sf", "di",
1249- "v16qi", "v8hi", "v4si", "v4sf", "v2di"
1250- };
1251- char namebuf[60];
1252- tree ftype = NULL;
1253- enum insn_code icode;
1254- int is_load = 0, is_store = 0;
1255-
1256- if ((d->bits & (1 << j)) == 0)
1257- continue;
1258-
1259- icode = d->codes[codeidx++];
1260-
1261- switch (d->itype)
1262- {
1263- case NEON_LOAD1:
1264- case NEON_LOAD1LANE:
1265- case NEON_LOADSTRUCT:
1266- case NEON_LOADSTRUCTLANE:
1267- is_load = 1;
1268- /* Fall through. */
1269- case NEON_STORE1:
1270- case NEON_STORE1LANE:
1271- case NEON_STORESTRUCT:
1272- case NEON_STORESTRUCTLANE:
1273- if (!is_load)
1274- is_store = 1;
1275- /* Fall through. */
1276- case NEON_UNOP:
1277- case NEON_BINOP:
1278- case NEON_LOGICBINOP:
1279- case NEON_SHIFTINSERT:
1280- case NEON_TERNOP:
1281- case NEON_GETLANE:
1282- case NEON_SETLANE:
1283- case NEON_CREATE:
1284- case NEON_DUP:
1285- case NEON_DUPLANE:
1286- case NEON_SHIFTIMM:
1287- case NEON_SHIFTACC:
1288- case NEON_COMBINE:
1289- case NEON_SPLIT:
1290- case NEON_CONVERT:
1291- case NEON_FIXCONV:
1292- case NEON_LANEMUL:
1293- case NEON_LANEMULL:
1294- case NEON_LANEMULH:
1295- case NEON_LANEMAC:
1296- case NEON_SCALARMUL:
1297- case NEON_SCALARMULL:
1298- case NEON_SCALARMULH:
1299- case NEON_SCALARMAC:
1300- case NEON_SELECT:
1301- case NEON_VTBL:
1302- case NEON_VTBX:
1303- {
1304- int k;
1305- tree return_type = void_type_node, args = void_list_node;
1306-
1307- /* Build a function type directly from the insn_data for this
1308- builtin. The build_function_type() function takes care of
1309- removing duplicates for us. */
1310- for (k = insn_data[icode].n_operands - 1; k >= 0; k--)
1311- {
1312- tree eltype;
1313-
1314- if (is_load && k == 1)
1315- {
1316- /* Neon load patterns always have the memory operand
1317- in the operand 1 position. */
1318- gcc_assert (insn_data[icode].operand[k].predicate
1319- == neon_struct_operand);
1320-
1321- switch (1 << j)
1322- {
1323- case T_V8QI:
1324- case T_V16QI:
1325- eltype = const_intQI_pointer_node;
1326- break;
1327-
1328- case T_V4HI:
1329- case T_V8HI:
1330- eltype = const_intHI_pointer_node;
1331- break;
1332-
1333- case T_V2SI:
1334- case T_V4SI:
1335- eltype = const_intSI_pointer_node;
1336- break;
1337-
1338- case T_V2SF:
1339- case T_V4SF:
1340- eltype = const_float_pointer_node;
1341- break;
1342-
1343- case T_DI:
1344- case T_V2DI:
1345- eltype = const_intDI_pointer_node;
1346- break;
1347-
1348- default: gcc_unreachable ();
1349- }
1350- }
1351- else if (is_store && k == 0)
1352- {
1353- /* Similarly, Neon store patterns use operand 0 as
1354- the memory location to store to. */
1355- gcc_assert (insn_data[icode].operand[k].predicate
1356- == neon_struct_operand);
1357-
1358- switch (1 << j)
1359- {
1360- case T_V8QI:
1361- case T_V16QI:
1362- eltype = intQI_pointer_node;
1363- break;
1364-
1365- case T_V4HI:
1366- case T_V8HI:
1367- eltype = intHI_pointer_node;
1368- break;
1369-
1370- case T_V2SI:
1371- case T_V4SI:
1372- eltype = intSI_pointer_node;
1373- break;
1374-
1375- case T_V2SF:
1376- case T_V4SF:
1377- eltype = float_pointer_node;
1378- break;
1379-
1380- case T_DI:
1381- case T_V2DI:
1382- eltype = intDI_pointer_node;
1383- break;
1384-
1385- default: gcc_unreachable ();
1386- }
1387- }
1388- else
1389- {
1390- switch (insn_data[icode].operand[k].mode)
1391- {
1392- case VOIDmode: eltype = void_type_node; break;
1393- /* Scalars. */
1394- case QImode: eltype = neon_intQI_type_node; break;
1395- case HImode: eltype = neon_intHI_type_node; break;
1396- case SImode: eltype = neon_intSI_type_node; break;
1397- case SFmode: eltype = neon_float_type_node; break;
1398- case DImode: eltype = neon_intDI_type_node; break;
1399- case TImode: eltype = intTI_type_node; break;
1400- case EImode: eltype = intEI_type_node; break;
1401- case OImode: eltype = intOI_type_node; break;
1402- case CImode: eltype = intCI_type_node; break;
1403- case XImode: eltype = intXI_type_node; break;
1404- /* 64-bit vectors. */
1405- case V8QImode: eltype = V8QI_type_node; break;
1406- case V4HImode: eltype = V4HI_type_node; break;
1407- case V2SImode: eltype = V2SI_type_node; break;
1408- case V2SFmode: eltype = V2SF_type_node; break;
1409- /* 128-bit vectors. */
1410- case V16QImode: eltype = V16QI_type_node; break;
1411- case V8HImode: eltype = V8HI_type_node; break;
1412- case V4SImode: eltype = V4SI_type_node; break;
1413- case V4SFmode: eltype = V4SF_type_node; break;
1414- case V2DImode: eltype = V2DI_type_node; break;
1415- default: gcc_unreachable ();
1416- }
1417- }
1418-
1419- if (k == 0 && !is_store)
1420- return_type = eltype;
1421- else
1422- args = tree_cons (NULL_TREE, eltype, args);
1423- }
1424-
1425- ftype = build_function_type (return_type, args);
1426- }
1427- break;
1428-
1429- case NEON_RESULTPAIR:
1430- {
1431- switch (insn_data[icode].operand[1].mode)
1432- {
1433- case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break;
1434- case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break;
1435- case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break;
1436- case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break;
1437- case DImode: ftype = void_ftype_pdi_di_di; break;
1438- case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break;
1439- case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break;
1440- case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break;
1441- case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break;
1442- case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break;
1443- default: gcc_unreachable ();
1444- }
1445- }
1446- break;
1447-
1448- case NEON_REINTERP:
1449- {
1450- /* We iterate over 5 doubleword types, then 5 quadword
1451- types. */
1452- int rhs = j % 5;
1453- switch (insn_data[icode].operand[0].mode)
1454- {
1455- case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break;
1456- case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break;
1457- case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break;
1458- case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break;
1459- case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break;
1460- case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break;
1461- case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break;
1462- case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break;
1463- case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break;
1464- case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break;
1465- default: gcc_unreachable ();
1466- }
1467- }
1468- break;
1469-
1470- default:
1471- gcc_unreachable ();
1472- }
1473-
1474- gcc_assert (ftype != NULL);
1475-
1476- sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[j]);
1477-
1478- add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL,
1479- NULL_TREE);
1480- }
1481- }
1482+
1483+ const char* const modenames[] = {
1484+ "v8qi", "v4hi", "v2si", "v2sf", "di",
1485+ "v16qi", "v8hi", "v4si", "v4sf", "v2di",
1486+ "ti", "ei", "oi"
1487+ };
1488+ char namebuf[60];
1489+ tree ftype = NULL;
1490+ int is_load = 0, is_store = 0;
1491+
1492+ gcc_assert (ARRAY_SIZE (modenames) == T_MAX);
1493+
1494+ d->fcode = fcode;
1495+
1496+ switch (d->itype)
1497+ {
1498+ case NEON_LOAD1:
1499+ case NEON_LOAD1LANE:
1500+ case NEON_LOADSTRUCT:
1501+ case NEON_LOADSTRUCTLANE:
1502+ is_load = 1;
1503+ /* Fall through. */
1504+ case NEON_STORE1:
1505+ case NEON_STORE1LANE:
1506+ case NEON_STORESTRUCT:
1507+ case NEON_STORESTRUCTLANE:
1508+ if (!is_load)
1509+ is_store = 1;
1510+ /* Fall through. */
1511+ case NEON_UNOP:
1512+ case NEON_BINOP:
1513+ case NEON_LOGICBINOP:
1514+ case NEON_SHIFTINSERT:
1515+ case NEON_TERNOP:
1516+ case NEON_GETLANE:
1517+ case NEON_SETLANE:
1518+ case NEON_CREATE:
1519+ case NEON_DUP:
1520+ case NEON_DUPLANE:
1521+ case NEON_SHIFTIMM:
1522+ case NEON_SHIFTACC:
1523+ case NEON_COMBINE:
1524+ case NEON_SPLIT:
1525+ case NEON_CONVERT:
1526+ case NEON_FIXCONV:
1527+ case NEON_LANEMUL:
1528+ case NEON_LANEMULL:
1529+ case NEON_LANEMULH:
1530+ case NEON_LANEMAC:
1531+ case NEON_SCALARMUL:
1532+ case NEON_SCALARMULL:
1533+ case NEON_SCALARMULH:
1534+ case NEON_SCALARMAC:
1535+ case NEON_SELECT:
1536+ case NEON_VTBL:
1537+ case NEON_VTBX:
1538+ {
1539+ int k;
1540+ tree return_type = void_type_node, args = void_list_node;
1541+
1542+ /* Build a function type directly from the insn_data for
1543+ this builtin. The build_function_type() function takes
1544+ care of removing duplicates for us. */
1545+ for (k = insn_data[d->code].n_operands - 1; k >= 0; k--)
1546+ {
1547+ tree eltype;
1548+
1549+ if (is_load && k == 1)
1550+ {
1551+ /* Neon load patterns always have the memory
1552+ operand in the operand 1 position. */
1553+ gcc_assert (insn_data[d->code].operand[k].predicate
1554+ == neon_struct_operand);
1555+
1556+ switch (d->mode)
1557+ {
1558+ case T_V8QI:
1559+ case T_V16QI:
1560+ eltype = const_intQI_pointer_node;
1561+ break;
1562+
1563+ case T_V4HI:
1564+ case T_V8HI:
1565+ eltype = const_intHI_pointer_node;
1566+ break;
1567+
1568+ case T_V2SI:
1569+ case T_V4SI:
1570+ eltype = const_intSI_pointer_node;
1571+ break;
1572+
1573+ case T_V2SF:
1574+ case T_V4SF:
1575+ eltype = const_float_pointer_node;
1576+ break;
1577+
1578+ case T_DI:
1579+ case T_V2DI:
1580+ eltype = const_intDI_pointer_node;
1581+ break;
1582+
1583+ default: gcc_unreachable ();
1584+ }
1585+ }
1586+ else if (is_store && k == 0)
1587+ {
1588+ /* Similarly, Neon store patterns use operand 0 as
1589+ the memory location to store to. */
1590+ gcc_assert (insn_data[d->code].operand[k].predicate
1591+ == neon_struct_operand);
1592+
1593+ switch (d->mode)
1594+ {
1595+ case T_V8QI:
1596+ case T_V16QI:
1597+ eltype = intQI_pointer_node;
1598+ break;
1599+
1600+ case T_V4HI:
1601+ case T_V8HI:
1602+ eltype = intHI_pointer_node;
1603+ break;
1604+
1605+ case T_V2SI:
1606+ case T_V4SI:
1607+ eltype = intSI_pointer_node;
1608+ break;
1609+
1610+ case T_V2SF:
1611+ case T_V4SF:
1612+ eltype = float_pointer_node;
1613+ break;
1614+
1615+ case T_DI:
1616+ case T_V2DI:
1617+ eltype = intDI_pointer_node;
1618+ break;
1619+
1620+ default: gcc_unreachable ();
1621+ }
1622+ }
1623+ else
1624+ {
1625+ switch (insn_data[d->code].operand[k].mode)
1626+ {
1627+ case VOIDmode: eltype = void_type_node; break;
1628+ /* Scalars. */
1629+ case QImode: eltype = neon_intQI_type_node; break;
1630+ case HImode: eltype = neon_intHI_type_node; break;
1631+ case SImode: eltype = neon_intSI_type_node; break;
1632+ case SFmode: eltype = neon_float_type_node; break;
1633+ case DImode: eltype = neon_intDI_type_node; break;
1634+ case TImode: eltype = intTI_type_node; break;
1635+ case EImode: eltype = intEI_type_node; break;
1636+ case OImode: eltype = intOI_type_node; break;
1637+ case CImode: eltype = intCI_type_node; break;
1638+ case XImode: eltype = intXI_type_node; break;
1639+ /* 64-bit vectors. */
1640+ case V8QImode: eltype = V8QI_type_node; break;
1641+ case V4HImode: eltype = V4HI_type_node; break;
1642+ case V2SImode: eltype = V2SI_type_node; break;
1643+ case V2SFmode: eltype = V2SF_type_node; break;
1644+ /* 128-bit vectors. */
1645+ case V16QImode: eltype = V16QI_type_node; break;
1646+ case V8HImode: eltype = V8HI_type_node; break;
1647+ case V4SImode: eltype = V4SI_type_node; break;
1648+ case V4SFmode: eltype = V4SF_type_node; break;
1649+ case V2DImode: eltype = V2DI_type_node; break;
1650+ default: gcc_unreachable ();
1651+ }
1652+ }
1653+
1654+ if (k == 0 && !is_store)
1655+ return_type = eltype;
1656+ else
1657+ args = tree_cons (NULL_TREE, eltype, args);
1658+ }
1659+
1660+ ftype = build_function_type (return_type, args);
1661+ }
1662+ break;
1663+
1664+ case NEON_RESULTPAIR:
1665+ {
1666+ switch (insn_data[d->code].operand[1].mode)
1667+ {
1668+ case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break;
1669+ case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break;
1670+ case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break;
1671+ case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break;
1672+ case DImode: ftype = void_ftype_pdi_di_di; break;
1673+ case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break;
1674+ case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break;
1675+ case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break;
1676+ case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break;
1677+ case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break;
1678+ default: gcc_unreachable ();
1679+ }
1680+ }
1681+ break;
1682+
1683+ case NEON_REINTERP:
1684+ {
1685+ /* We iterate over 5 doubleword types, then 5 quadword
1686+ types. */
1687+ int rhs = d->mode % 5;
1688+ switch (insn_data[d->code].operand[0].mode)
1689+ {
1690+ case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break;
1691+ case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break;
1692+ case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break;
1693+ case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break;
1694+ case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break;
1695+ case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break;
1696+ case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break;
1697+ case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break;
1698+ case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break;
1699+ case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break;
1700+ default: gcc_unreachable ();
1701+ }
1702+ }
1703+ break;
1704+
1705+ default:
1706+ gcc_unreachable ();
1707+ }
1708+
1709+ gcc_assert (ftype != NULL);
1710+
1711+ sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[d->mode]);
1712+
1713+ decl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD, NULL,
1714+ NULL_TREE);
1715+ arm_builtin_decls[fcode] = decl;
1716+ }
1717+}
1718+
1719+#define def_mbuiltin(MASK, NAME, TYPE, CODE) \
1720+ do \
1721+ { \
1722+ if ((MASK) & insn_flags) \
1723+ { \
1724+ tree bdecl; \
1725+ bdecl = add_builtin_function ((NAME), (TYPE), (CODE), \
1726+ BUILT_IN_MD, NULL, NULL_TREE); \
1727+ arm_builtin_decls[CODE] = bdecl; \
1728+ } \
1729+ } \
1730+ while (0)
1731+
1732+struct builtin_description
1733+{
1734+ const unsigned int mask;
1735+ const enum insn_code icode;
1736+ const char * const name;
1737+ const enum arm_builtins code;
1738+ const enum rtx_code comparison;
1739+ const unsigned int flag;
1740+};
1741+
1742+static const struct builtin_description bdesc_2arg[] =
1743+{
1744+#define IWMMXT_BUILTIN(code, string, builtin) \
1745+ { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
1746+ ARM_BUILTIN_##builtin, UNKNOWN, 0 },
1747+
1748+ IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
1749+ IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
1750+ IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
1751+ IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
1752+ IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
1753+ IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
1754+ IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
1755+ IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
1756+ IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
1757+ IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
1758+ IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
1759+ IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
1760+ IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
1761+ IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
1762+ IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
1763+ IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
1764+ IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
1765+ IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
1766+ IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
1767+ IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
1768+ IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
1769+ IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
1770+ IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
1771+ IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
1772+ IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
1773+ IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
1774+ IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
1775+ IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
1776+ IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
1777+ IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
1778+ IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
1779+ IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
1780+ IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
1781+ IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
1782+ IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
1783+ IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
1784+ IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
1785+ IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
1786+ IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
1787+ IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
1788+ IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
1789+ IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
1790+ IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
1791+ IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
1792+ IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
1793+ IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
1794+ IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
1795+ IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
1796+ IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
1797+ IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
1798+ IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
1799+ IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
1800+ IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
1801+ IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
1802+ IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
1803+ IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
1804+ IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
1805+ IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
1806+
1807+#define IWMMXT_BUILTIN2(code, builtin) \
1808+ { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
1809+
1810+ IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
1811+ IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
1812+ IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
1813+ IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
1814+ IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
1815+ IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
1816+ IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
1817+ IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI)
1818+ IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
1819+ IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI)
1820+ IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
1821+ IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
1822+ IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
1823+ IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI)
1824+ IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
1825+ IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI)
1826+ IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
1827+ IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
1828+ IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
1829+ IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI)
1830+ IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
1831+ IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI)
1832+ IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
1833+ IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
1834+ IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
1835+ IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
1836+ IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
1837+ IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
1838+ IWMMXT_BUILTIN2 (rordi3_di, WRORD)
1839+ IWMMXT_BUILTIN2 (rordi3, WRORDI)
1840+ IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
1841+ IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
1842+};
1843+
1844+static const struct builtin_description bdesc_1arg[] =
1845+{
1846+ IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
1847+ IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
1848+ IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
1849+ IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
1850+ IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
1851+ IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
1852+ IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
1853+ IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
1854+ IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
1855+ IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
1856+ IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
1857+ IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
1858+ IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
1859+ IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
1860+ IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
1861+ IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
1862+ IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
1863+ IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
1864+};
1865+
1866+/* Set up all the iWMMXt builtins. This is not called if
1867+ TARGET_IWMMXT is zero. */
1868+
1869+static void
1870+arm_init_iwmmxt_builtins (void)
1871+{
1872+ const struct builtin_description * d;
1873+ size_t i;
1874+ tree endlink = void_list_node;
1875+
1876+ tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
1877+ tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
1878+ tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
1879+
1880+ tree int_ftype_int
1881+ = build_function_type (integer_type_node,
1882+ tree_cons (NULL_TREE, integer_type_node, endlink));
1883+ tree v8qi_ftype_v8qi_v8qi_int
1884+ = build_function_type (V8QI_type_node,
1885+ tree_cons (NULL_TREE, V8QI_type_node,
1886+ tree_cons (NULL_TREE, V8QI_type_node,
1887+ tree_cons (NULL_TREE,
1888+ integer_type_node,
1889+ endlink))));
1890+ tree v4hi_ftype_v4hi_int
1891+ = build_function_type (V4HI_type_node,
1892+ tree_cons (NULL_TREE, V4HI_type_node,
1893+ tree_cons (NULL_TREE, integer_type_node,
1894+ endlink)));
1895+ tree v2si_ftype_v2si_int
1896+ = build_function_type (V2SI_type_node,
1897+ tree_cons (NULL_TREE, V2SI_type_node,
1898+ tree_cons (NULL_TREE, integer_type_node,
1899+ endlink)));
1900+ tree v2si_ftype_di_di
1901+ = build_function_type (V2SI_type_node,
1902+ tree_cons (NULL_TREE, long_long_integer_type_node,
1903+ tree_cons (NULL_TREE,
1904+ long_long_integer_type_node,
1905+ endlink)));
1906+ tree di_ftype_di_int
1907+ = build_function_type (long_long_integer_type_node,
1908+ tree_cons (NULL_TREE, long_long_integer_type_node,
1909+ tree_cons (NULL_TREE, integer_type_node,
1910+ endlink)));
1911+ tree di_ftype_di_int_int
1912+ = build_function_type (long_long_integer_type_node,
1913+ tree_cons (NULL_TREE, long_long_integer_type_node,
1914+ tree_cons (NULL_TREE, integer_type_node,
1915+ tree_cons (NULL_TREE,
1916+ integer_type_node,
1917+ endlink))));
1918+ tree int_ftype_v8qi
1919+ = build_function_type (integer_type_node,
1920+ tree_cons (NULL_TREE, V8QI_type_node,
1921+ endlink));
1922+ tree int_ftype_v4hi
1923+ = build_function_type (integer_type_node,
1924+ tree_cons (NULL_TREE, V4HI_type_node,
1925+ endlink));
1926+ tree int_ftype_v2si
1927+ = build_function_type (integer_type_node,
1928+ tree_cons (NULL_TREE, V2SI_type_node,
1929+ endlink));
1930+ tree int_ftype_v8qi_int
1931+ = build_function_type (integer_type_node,
1932+ tree_cons (NULL_TREE, V8QI_type_node,
1933+ tree_cons (NULL_TREE, integer_type_node,
1934+ endlink)));
1935+ tree int_ftype_v4hi_int
1936+ = build_function_type (integer_type_node,
1937+ tree_cons (NULL_TREE, V4HI_type_node,
1938+ tree_cons (NULL_TREE, integer_type_node,
1939+ endlink)));
1940+ tree int_ftype_v2si_int
1941+ = build_function_type (integer_type_node,
1942+ tree_cons (NULL_TREE, V2SI_type_node,
1943+ tree_cons (NULL_TREE, integer_type_node,
1944+ endlink)));
1945+ tree v8qi_ftype_v8qi_int_int
1946+ = build_function_type (V8QI_type_node,
1947+ tree_cons (NULL_TREE, V8QI_type_node,
1948+ tree_cons (NULL_TREE, integer_type_node,
1949+ tree_cons (NULL_TREE,
1950+ integer_type_node,
1951+ endlink))));
1952+ tree v4hi_ftype_v4hi_int_int
1953+ = build_function_type (V4HI_type_node,
1954+ tree_cons (NULL_TREE, V4HI_type_node,
1955+ tree_cons (NULL_TREE, integer_type_node,
1956+ tree_cons (NULL_TREE,
1957+ integer_type_node,
1958+ endlink))));
1959+ tree v2si_ftype_v2si_int_int
1960+ = build_function_type (V2SI_type_node,
1961+ tree_cons (NULL_TREE, V2SI_type_node,
1962+ tree_cons (NULL_TREE, integer_type_node,
1963+ tree_cons (NULL_TREE,
1964+ integer_type_node,
1965+ endlink))));
1966+ /* Miscellaneous. */
1967+ tree v8qi_ftype_v4hi_v4hi
1968+ = build_function_type (V8QI_type_node,
1969+ tree_cons (NULL_TREE, V4HI_type_node,
1970+ tree_cons (NULL_TREE, V4HI_type_node,
1971+ endlink)));
1972+ tree v4hi_ftype_v2si_v2si
1973+ = build_function_type (V4HI_type_node,
1974+ tree_cons (NULL_TREE, V2SI_type_node,
1975+ tree_cons (NULL_TREE, V2SI_type_node,
1976+ endlink)));
1977+ tree v2si_ftype_v4hi_v4hi
1978+ = build_function_type (V2SI_type_node,
1979+ tree_cons (NULL_TREE, V4HI_type_node,
1980+ tree_cons (NULL_TREE, V4HI_type_node,
1981+ endlink)));
1982+ tree v2si_ftype_v8qi_v8qi
1983+ = build_function_type (V2SI_type_node,
1984+ tree_cons (NULL_TREE, V8QI_type_node,
1985+ tree_cons (NULL_TREE, V8QI_type_node,
1986+ endlink)));
1987+ tree v4hi_ftype_v4hi_di
1988+ = build_function_type (V4HI_type_node,
1989+ tree_cons (NULL_TREE, V4HI_type_node,
1990+ tree_cons (NULL_TREE,
1991+ long_long_integer_type_node,
1992+ endlink)));
1993+ tree v2si_ftype_v2si_di
1994+ = build_function_type (V2SI_type_node,
1995+ tree_cons (NULL_TREE, V2SI_type_node,
1996+ tree_cons (NULL_TREE,
1997+ long_long_integer_type_node,
1998+ endlink)));
1999+ tree void_ftype_int_int
2000+ = build_function_type (void_type_node,
2001+ tree_cons (NULL_TREE, integer_type_node,
2002+ tree_cons (NULL_TREE, integer_type_node,
2003+ endlink)));
2004+ tree di_ftype_void
2005+ = build_function_type (long_long_unsigned_type_node, endlink);
2006+ tree di_ftype_v8qi
2007+ = build_function_type (long_long_integer_type_node,
2008+ tree_cons (NULL_TREE, V8QI_type_node,
2009+ endlink));
2010+ tree di_ftype_v4hi
2011+ = build_function_type (long_long_integer_type_node,
2012+ tree_cons (NULL_TREE, V4HI_type_node,
2013+ endlink));
2014+ tree di_ftype_v2si
2015+ = build_function_type (long_long_integer_type_node,
2016+ tree_cons (NULL_TREE, V2SI_type_node,
2017+ endlink));
2018+ tree v2si_ftype_v4hi
2019+ = build_function_type (V2SI_type_node,
2020+ tree_cons (NULL_TREE, V4HI_type_node,
2021+ endlink));
2022+ tree v4hi_ftype_v8qi
2023+ = build_function_type (V4HI_type_node,
2024+ tree_cons (NULL_TREE, V8QI_type_node,
2025+ endlink));
2026+
2027+ tree di_ftype_di_v4hi_v4hi
2028+ = build_function_type (long_long_unsigned_type_node,
2029+ tree_cons (NULL_TREE,
2030+ long_long_unsigned_type_node,
2031+ tree_cons (NULL_TREE, V4HI_type_node,
2032+ tree_cons (NULL_TREE,
2033+ V4HI_type_node,
2034+ endlink))));
2035+
2036+ tree di_ftype_v4hi_v4hi
2037+ = build_function_type (long_long_unsigned_type_node,
2038+ tree_cons (NULL_TREE, V4HI_type_node,
2039+ tree_cons (NULL_TREE, V4HI_type_node,
2040+ endlink)));
2041+
2042+ /* Normal vector binops. */
2043+ tree v8qi_ftype_v8qi_v8qi
2044+ = build_function_type (V8QI_type_node,
2045+ tree_cons (NULL_TREE, V8QI_type_node,
2046+ tree_cons (NULL_TREE, V8QI_type_node,
2047+ endlink)));
2048+ tree v4hi_ftype_v4hi_v4hi
2049+ = build_function_type (V4HI_type_node,
2050+ tree_cons (NULL_TREE, V4HI_type_node,
2051+ tree_cons (NULL_TREE, V4HI_type_node,
2052+ endlink)));
2053+ tree v2si_ftype_v2si_v2si
2054+ = build_function_type (V2SI_type_node,
2055+ tree_cons (NULL_TREE, V2SI_type_node,
2056+ tree_cons (NULL_TREE, V2SI_type_node,
2057+ endlink)));
2058+ tree di_ftype_di_di
2059+ = build_function_type (long_long_unsigned_type_node,
2060+ tree_cons (NULL_TREE, long_long_unsigned_type_node,
2061+ tree_cons (NULL_TREE,
2062+ long_long_unsigned_type_node,
2063+ endlink)));
2064+
2065+ /* Add all builtins that are more or less simple operations on two
2066+ operands. */
2067+ for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
2068+ {
2069+ /* Use one of the operands; the target can have a different mode for
2070+ mask-generating compares. */
2071+ enum machine_mode mode;
2072+ tree type;
2073+
2074+ if (d->name == 0)
2075+ continue;
2076+
2077+ mode = insn_data[d->icode].operand[1].mode;
2078+
2079+ switch (mode)
2080+ {
2081+ case V8QImode:
2082+ type = v8qi_ftype_v8qi_v8qi;
2083+ break;
2084+ case V4HImode:
2085+ type = v4hi_ftype_v4hi_v4hi;
2086+ break;
2087+ case V2SImode:
2088+ type = v2si_ftype_v2si_v2si;
2089+ break;
2090+ case DImode:
2091+ type = di_ftype_di_di;
2092+ break;
2093+
2094+ default:
2095+ gcc_unreachable ();
2096+ }
2097+
2098+ def_mbuiltin (d->mask, d->name, type, d->code);
2099+ }
2100+
2101+ /* Add the remaining MMX insns with somewhat more complicated types. */
2102+#define iwmmx_mbuiltin(NAME, TYPE, CODE) \
2103+ def_mbuiltin (FL_IWMMXT, "__builtin_arm_" NAME, (TYPE), \
2104+ ARM_BUILTIN_ ## CODE)
2105+
2106+ iwmmx_mbuiltin ("wzero", di_ftype_void, WZERO);
2107+ iwmmx_mbuiltin ("setwcx", void_ftype_int_int, SETWCX);
2108+ iwmmx_mbuiltin ("getwcx", int_ftype_int, GETWCX);
2109+
2110+ iwmmx_mbuiltin ("wsllh", v4hi_ftype_v4hi_di, WSLLH);
2111+ iwmmx_mbuiltin ("wsllw", v2si_ftype_v2si_di, WSLLW);
2112+ iwmmx_mbuiltin ("wslld", di_ftype_di_di, WSLLD);
2113+ iwmmx_mbuiltin ("wsllhi", v4hi_ftype_v4hi_int, WSLLHI);
2114+ iwmmx_mbuiltin ("wsllwi", v2si_ftype_v2si_int, WSLLWI);
2115+ iwmmx_mbuiltin ("wslldi", di_ftype_di_int, WSLLDI);
2116+
2117+ iwmmx_mbuiltin ("wsrlh", v4hi_ftype_v4hi_di, WSRLH);
2118+ iwmmx_mbuiltin ("wsrlw", v2si_ftype_v2si_di, WSRLW);
2119+ iwmmx_mbuiltin ("wsrld", di_ftype_di_di, WSRLD);
2120+ iwmmx_mbuiltin ("wsrlhi", v4hi_ftype_v4hi_int, WSRLHI);
2121+ iwmmx_mbuiltin ("wsrlwi", v2si_ftype_v2si_int, WSRLWI);
2122+ iwmmx_mbuiltin ("wsrldi", di_ftype_di_int, WSRLDI);
2123+
2124+ iwmmx_mbuiltin ("wsrah", v4hi_ftype_v4hi_di, WSRAH);
2125+ iwmmx_mbuiltin ("wsraw", v2si_ftype_v2si_di, WSRAW);
2126+ iwmmx_mbuiltin ("wsrad", di_ftype_di_di, WSRAD);
2127+ iwmmx_mbuiltin ("wsrahi", v4hi_ftype_v4hi_int, WSRAHI);
2128+ iwmmx_mbuiltin ("wsrawi", v2si_ftype_v2si_int, WSRAWI);
2129+ iwmmx_mbuiltin ("wsradi", di_ftype_di_int, WSRADI);
2130+
2131+ iwmmx_mbuiltin ("wrorh", v4hi_ftype_v4hi_di, WRORH);
2132+ iwmmx_mbuiltin ("wrorw", v2si_ftype_v2si_di, WRORW);
2133+ iwmmx_mbuiltin ("wrord", di_ftype_di_di, WRORD);
2134+ iwmmx_mbuiltin ("wrorhi", v4hi_ftype_v4hi_int, WRORHI);
2135+ iwmmx_mbuiltin ("wrorwi", v2si_ftype_v2si_int, WRORWI);
2136+ iwmmx_mbuiltin ("wrordi", di_ftype_di_int, WRORDI);
2137+
2138+ iwmmx_mbuiltin ("wshufh", v4hi_ftype_v4hi_int, WSHUFH);
2139+
2140+ iwmmx_mbuiltin ("wsadb", v2si_ftype_v8qi_v8qi, WSADB);
2141+ iwmmx_mbuiltin ("wsadh", v2si_ftype_v4hi_v4hi, WSADH);
2142+ iwmmx_mbuiltin ("wsadbz", v2si_ftype_v8qi_v8qi, WSADBZ);
2143+ iwmmx_mbuiltin ("wsadhz", v2si_ftype_v4hi_v4hi, WSADHZ);
2144+
2145+ iwmmx_mbuiltin ("textrmsb", int_ftype_v8qi_int, TEXTRMSB);
2146+ iwmmx_mbuiltin ("textrmsh", int_ftype_v4hi_int, TEXTRMSH);
2147+ iwmmx_mbuiltin ("textrmsw", int_ftype_v2si_int, TEXTRMSW);
2148+ iwmmx_mbuiltin ("textrmub", int_ftype_v8qi_int, TEXTRMUB);
2149+ iwmmx_mbuiltin ("textrmuh", int_ftype_v4hi_int, TEXTRMUH);
2150+ iwmmx_mbuiltin ("textrmuw", int_ftype_v2si_int, TEXTRMUW);
2151+ iwmmx_mbuiltin ("tinsrb", v8qi_ftype_v8qi_int_int, TINSRB);
2152+ iwmmx_mbuiltin ("tinsrh", v4hi_ftype_v4hi_int_int, TINSRH);
2153+ iwmmx_mbuiltin ("tinsrw", v2si_ftype_v2si_int_int, TINSRW);
2154+
2155+ iwmmx_mbuiltin ("waccb", di_ftype_v8qi, WACCB);
2156+ iwmmx_mbuiltin ("wacch", di_ftype_v4hi, WACCH);
2157+ iwmmx_mbuiltin ("waccw", di_ftype_v2si, WACCW);
2158+
2159+ iwmmx_mbuiltin ("tmovmskb", int_ftype_v8qi, TMOVMSKB);
2160+ iwmmx_mbuiltin ("tmovmskh", int_ftype_v4hi, TMOVMSKH);
2161+ iwmmx_mbuiltin ("tmovmskw", int_ftype_v2si, TMOVMSKW);
2162+
2163+ iwmmx_mbuiltin ("wpackhss", v8qi_ftype_v4hi_v4hi, WPACKHSS);
2164+ iwmmx_mbuiltin ("wpackhus", v8qi_ftype_v4hi_v4hi, WPACKHUS);
2165+ iwmmx_mbuiltin ("wpackwus", v4hi_ftype_v2si_v2si, WPACKWUS);
2166+ iwmmx_mbuiltin ("wpackwss", v4hi_ftype_v2si_v2si, WPACKWSS);
2167+ iwmmx_mbuiltin ("wpackdus", v2si_ftype_di_di, WPACKDUS);
2168+ iwmmx_mbuiltin ("wpackdss", v2si_ftype_di_di, WPACKDSS);
2169+
2170+ iwmmx_mbuiltin ("wunpckehub", v4hi_ftype_v8qi, WUNPCKEHUB);
2171+ iwmmx_mbuiltin ("wunpckehuh", v2si_ftype_v4hi, WUNPCKEHUH);
2172+ iwmmx_mbuiltin ("wunpckehuw", di_ftype_v2si, WUNPCKEHUW);
2173+ iwmmx_mbuiltin ("wunpckehsb", v4hi_ftype_v8qi, WUNPCKEHSB);
2174+ iwmmx_mbuiltin ("wunpckehsh", v2si_ftype_v4hi, WUNPCKEHSH);
2175+ iwmmx_mbuiltin ("wunpckehsw", di_ftype_v2si, WUNPCKEHSW);
2176+ iwmmx_mbuiltin ("wunpckelub", v4hi_ftype_v8qi, WUNPCKELUB);
2177+ iwmmx_mbuiltin ("wunpckeluh", v2si_ftype_v4hi, WUNPCKELUH);
2178+ iwmmx_mbuiltin ("wunpckeluw", di_ftype_v2si, WUNPCKELUW);
2179+ iwmmx_mbuiltin ("wunpckelsb", v4hi_ftype_v8qi, WUNPCKELSB);
2180+ iwmmx_mbuiltin ("wunpckelsh", v2si_ftype_v4hi, WUNPCKELSH);
2181+ iwmmx_mbuiltin ("wunpckelsw", di_ftype_v2si, WUNPCKELSW);
2182+
2183+ iwmmx_mbuiltin ("wmacs", di_ftype_di_v4hi_v4hi, WMACS);
2184+ iwmmx_mbuiltin ("wmacsz", di_ftype_v4hi_v4hi, WMACSZ);
2185+ iwmmx_mbuiltin ("wmacu", di_ftype_di_v4hi_v4hi, WMACU);
2186+ iwmmx_mbuiltin ("wmacuz", di_ftype_v4hi_v4hi, WMACUZ);
2187+
2188+ iwmmx_mbuiltin ("walign", v8qi_ftype_v8qi_v8qi_int, WALIGN);
2189+ iwmmx_mbuiltin ("tmia", di_ftype_di_int_int, TMIA);
2190+ iwmmx_mbuiltin ("tmiaph", di_ftype_di_int_int, TMIAPH);
2191+ iwmmx_mbuiltin ("tmiabb", di_ftype_di_int_int, TMIABB);
2192+ iwmmx_mbuiltin ("tmiabt", di_ftype_di_int_int, TMIABT);
2193+ iwmmx_mbuiltin ("tmiatb", di_ftype_di_int_int, TMIATB);
2194+ iwmmx_mbuiltin ("tmiatt", di_ftype_di_int_int, TMIATT);
2195+
2196+#undef iwmmx_mbuiltin
2197+}
2198+
2199+static void
2200+arm_init_tls_builtins (void)
2201+{
2202+ tree ftype, decl;
2203+
2204+ ftype = build_function_type (ptr_type_node, void_list_node);
2205+ decl = add_builtin_function ("__builtin_thread_pointer", ftype,
2206+ ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
2207+ NULL, NULL_TREE);
2208+ TREE_NOTHROW (decl) = 1;
2209+ TREE_READONLY (decl) = 1;
2210+ arm_builtin_decls[ARM_BUILTIN_THREAD_POINTER] = decl;
2211 }
2212
2213 static void
2214@@ -19479,6 +19662,17 @@
2215 arm_init_fp16_builtins ();
2216 }
2217
2218+/* Return the ARM builtin for CODE. */
2219+
2220+static tree
2221+arm_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
2222+{
2223+ if (code >= ARM_BUILTIN_MAX)
2224+ return error_mark_node;
2225+
2226+ return arm_builtin_decls[code];
2227+}
2228+
2229 /* Implement TARGET_INVALID_PARAMETER_TYPE. */
2230
2231 static const char *
2232@@ -19630,58 +19824,6 @@
2233 return target;
2234 }
2235
2236-static int
2237-neon_builtin_compare (const void *a, const void *b)
2238-{
2239- const neon_builtin_datum *const key = (const neon_builtin_datum *) a;
2240- const neon_builtin_datum *const memb = (const neon_builtin_datum *) b;
2241- unsigned int soughtcode = key->base_fcode;
2242-
2243- if (soughtcode >= memb->base_fcode
2244- && soughtcode < memb->base_fcode + memb->num_vars)
2245- return 0;
2246- else if (soughtcode < memb->base_fcode)
2247- return -1;
2248- else
2249- return 1;
2250-}
2251-
2252-static enum insn_code
2253-locate_neon_builtin_icode (int fcode, neon_itype *itype,
2254- enum neon_builtin_type_bits *type_bit)
2255-{
2256- neon_builtin_datum key
2257- = { NULL, (neon_itype) 0, 0, { CODE_FOR_nothing }, 0, 0 };
2258- neon_builtin_datum *found;
2259- int idx, type, ntypes;
2260-
2261- key.base_fcode = fcode;
2262- found = (neon_builtin_datum *)
2263- bsearch (&key, &neon_builtin_data[0], ARRAY_SIZE (neon_builtin_data),
2264- sizeof (neon_builtin_data[0]), neon_builtin_compare);
2265- gcc_assert (found);
2266- idx = fcode - (int) found->base_fcode;
2267- gcc_assert (idx >= 0 && idx < T_MAX && idx < (int)found->num_vars);
2268-
2269- if (itype)
2270- *itype = found->itype;
2271-
2272- if (type_bit)
2273- {
2274- ntypes = 0;
2275- for (type = 0; type < T_MAX; type++)
2276- if (found->bits & (1 << type))
2277- {
2278- if (ntypes == idx)
2279- break;
2280- ntypes++;
2281- }
2282- gcc_assert (type < T_MAX);
2283- *type_bit = (enum neon_builtin_type_bits) (1 << type);
2284- }
2285- return found->codes[idx];
2286-}
2287-
2288 typedef enum {
2289 NEON_ARG_COPY_TO_REG,
2290 NEON_ARG_CONSTANT,
2291@@ -19695,14 +19837,14 @@
2292 and return an expression for the accessed memory.
2293
2294 The intrinsic function operates on a block of registers that has
2295- mode REG_MODE. This block contains vectors of type TYPE_BIT.
2296+ mode REG_MODE. This block contains vectors of type TYPE_MODE.
2297 The function references the memory at EXP in mode MEM_MODE;
2298 this mode may be BLKmode if no more suitable mode is available. */
2299
2300 static tree
2301 neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
2302 enum machine_mode reg_mode,
2303- enum neon_builtin_type_bits type_bit)
2304+ neon_builtin_type_mode type_mode)
2305 {
2306 HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
2307 tree elem_type, upper_bound, array_type;
2308@@ -19711,8 +19853,8 @@
2309 reg_size = GET_MODE_SIZE (reg_mode);
2310
2311 /* Work out the size of each vector in bytes. */
2312- gcc_assert (type_bit & (T_DREG | T_QREG));
2313- vector_size = (type_bit & T_QREG ? 16 : 8);
2314+ gcc_assert (TYPE_MODE_BIT (type_mode) & (TB_DREG | TB_QREG));
2315+ vector_size = (TYPE_MODE_BIT (type_mode) & TB_QREG ? 16 : 8);
2316
2317 /* Work out how many vectors there are. */
2318 gcc_assert (reg_size % vector_size == 0);
2319@@ -19743,7 +19885,7 @@
2320 /* Expand a Neon builtin. */
2321 static rtx
2322 arm_expand_neon_args (rtx target, int icode, int have_retval,
2323- enum neon_builtin_type_bits type_bit,
2324+ neon_builtin_type_mode type_mode,
2325 tree exp, ...)
2326 {
2327 va_list ap;
2328@@ -19779,7 +19921,7 @@
2329 {
2330 other_mode = insn_data[icode].operand[1 - opno].mode;
2331 arg[argc] = neon_dereference_pointer (arg[argc], mode[argc],
2332- other_mode, type_bit);
2333+ other_mode, type_mode);
2334 }
2335 op[argc] = expand_normal (arg[argc]);
2336
2337@@ -19889,16 +20031,17 @@
2338 static rtx
2339 arm_expand_neon_builtin (int fcode, tree exp, rtx target)
2340 {
2341- neon_itype itype;
2342- enum neon_builtin_type_bits type_bit;
2343- enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, &type_bit);
2344+ neon_builtin_datum *d = &neon_builtin_data[fcode - ARM_BUILTIN_NEON_BASE];
2345+ neon_itype itype = d->itype;
2346+ enum insn_code icode = d->code;
2347+ neon_builtin_type_mode type_mode = d->mode;
2348
2349 switch (itype)
2350 {
2351 case NEON_UNOP:
2352 case NEON_CONVERT:
2353 case NEON_DUPLANE:
2354- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2355+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2356 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
2357
2358 case NEON_BINOP:
2359@@ -19908,89 +20051,89 @@
2360 case NEON_SCALARMULH:
2361 case NEON_SHIFTINSERT:
2362 case NEON_LOGICBINOP:
2363- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2364+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2365 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
2366 NEON_ARG_STOP);
2367
2368 case NEON_TERNOP:
2369- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2370+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2371 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
2372 NEON_ARG_CONSTANT, NEON_ARG_STOP);
2373
2374 case NEON_GETLANE:
2375 case NEON_FIXCONV:
2376 case NEON_SHIFTIMM:
2377- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2378+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2379 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
2380 NEON_ARG_STOP);
2381
2382 case NEON_CREATE:
2383- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2384+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2385 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
2386
2387 case NEON_DUP:
2388 case NEON_SPLIT:
2389 case NEON_REINTERP:
2390- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2391+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2392 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
2393
2394 case NEON_COMBINE:
2395 case NEON_VTBL:
2396- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2397+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2398 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
2399
2400 case NEON_RESULTPAIR:
2401- return arm_expand_neon_args (target, icode, 0, type_bit, exp,
2402+ return arm_expand_neon_args (target, icode, 0, type_mode, exp,
2403 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
2404 NEON_ARG_STOP);
2405
2406 case NEON_LANEMUL:
2407 case NEON_LANEMULL:
2408 case NEON_LANEMULH:
2409- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2410+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2411 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
2412 NEON_ARG_CONSTANT, NEON_ARG_STOP);
2413
2414 case NEON_LANEMAC:
2415- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2416+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2417 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
2418 NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
2419
2420 case NEON_SHIFTACC:
2421- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2422+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2423 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
2424 NEON_ARG_CONSTANT, NEON_ARG_STOP);
2425
2426 case NEON_SCALARMAC:
2427- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2428+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2429 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
2430 NEON_ARG_CONSTANT, NEON_ARG_STOP);
2431
2432 case NEON_SELECT:
2433 case NEON_VTBX:
2434- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2435+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2436 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
2437 NEON_ARG_STOP);
2438
2439 case NEON_LOAD1:
2440 case NEON_LOADSTRUCT:
2441- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2442+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2443 NEON_ARG_MEMORY, NEON_ARG_STOP);
2444
2445 case NEON_LOAD1LANE:
2446 case NEON_LOADSTRUCTLANE:
2447- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2448+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2449 NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
2450 NEON_ARG_STOP);
2451
2452 case NEON_STORE1:
2453 case NEON_STORESTRUCT:
2454- return arm_expand_neon_args (target, icode, 0, type_bit, exp,
2455+ return arm_expand_neon_args (target, icode, 0, type_mode, exp,
2456 NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
2457
2458 case NEON_STORE1LANE:
2459 case NEON_STORESTRUCTLANE:
2460- return arm_expand_neon_args (target, icode, 0, type_bit, exp,
2461+ return arm_expand_neon_args (target, icode, 0, type_mode, exp,
2462 NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
2463 NEON_ARG_STOP);
2464 }
2465
2466=== modified file 'gcc/config/arm/arm.h'
2467--- old/gcc/config/arm/arm.h 2011-08-13 08:32:32 +0000
2468+++ new/gcc/config/arm/arm.h 2011-08-24 17:35:16 +0000
2469@@ -2269,178 +2269,6 @@
2470 : arm_gen_return_addr_mask ())
2471
2472
2473-/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2474- symbolic names defined here (which would require too much duplication).
2475- FIXME? */
2476-enum arm_builtins
2477-{
2478- ARM_BUILTIN_GETWCX,
2479- ARM_BUILTIN_SETWCX,
2480-
2481- ARM_BUILTIN_WZERO,
2482-
2483- ARM_BUILTIN_WAVG2BR,
2484- ARM_BUILTIN_WAVG2HR,
2485- ARM_BUILTIN_WAVG2B,
2486- ARM_BUILTIN_WAVG2H,
2487-
2488- ARM_BUILTIN_WACCB,
2489- ARM_BUILTIN_WACCH,
2490- ARM_BUILTIN_WACCW,
2491-
2492- ARM_BUILTIN_WMACS,
2493- ARM_BUILTIN_WMACSZ,
2494- ARM_BUILTIN_WMACU,
2495- ARM_BUILTIN_WMACUZ,
2496-
2497- ARM_BUILTIN_WSADB,
2498- ARM_BUILTIN_WSADBZ,
2499- ARM_BUILTIN_WSADH,
2500- ARM_BUILTIN_WSADHZ,
2501-
2502- ARM_BUILTIN_WALIGN,
2503-
2504- ARM_BUILTIN_TMIA,
2505- ARM_BUILTIN_TMIAPH,
2506- ARM_BUILTIN_TMIABB,
2507- ARM_BUILTIN_TMIABT,
2508- ARM_BUILTIN_TMIATB,
2509- ARM_BUILTIN_TMIATT,
2510-
2511- ARM_BUILTIN_TMOVMSKB,
2512- ARM_BUILTIN_TMOVMSKH,
2513- ARM_BUILTIN_TMOVMSKW,
2514-
2515- ARM_BUILTIN_TBCSTB,
2516- ARM_BUILTIN_TBCSTH,
2517- ARM_BUILTIN_TBCSTW,
2518-
2519- ARM_BUILTIN_WMADDS,
2520- ARM_BUILTIN_WMADDU,
2521-
2522- ARM_BUILTIN_WPACKHSS,
2523- ARM_BUILTIN_WPACKWSS,
2524- ARM_BUILTIN_WPACKDSS,
2525- ARM_BUILTIN_WPACKHUS,
2526- ARM_BUILTIN_WPACKWUS,
2527- ARM_BUILTIN_WPACKDUS,
2528-
2529- ARM_BUILTIN_WADDB,
2530- ARM_BUILTIN_WADDH,
2531- ARM_BUILTIN_WADDW,
2532- ARM_BUILTIN_WADDSSB,
2533- ARM_BUILTIN_WADDSSH,
2534- ARM_BUILTIN_WADDSSW,
2535- ARM_BUILTIN_WADDUSB,
2536- ARM_BUILTIN_WADDUSH,
2537- ARM_BUILTIN_WADDUSW,
2538- ARM_BUILTIN_WSUBB,
2539- ARM_BUILTIN_WSUBH,
2540- ARM_BUILTIN_WSUBW,
2541- ARM_BUILTIN_WSUBSSB,
2542- ARM_BUILTIN_WSUBSSH,
2543- ARM_BUILTIN_WSUBSSW,
2544- ARM_BUILTIN_WSUBUSB,
2545- ARM_BUILTIN_WSUBUSH,
2546- ARM_BUILTIN_WSUBUSW,
2547-
2548- ARM_BUILTIN_WAND,
2549- ARM_BUILTIN_WANDN,
2550- ARM_BUILTIN_WOR,
2551- ARM_BUILTIN_WXOR,
2552-
2553- ARM_BUILTIN_WCMPEQB,
2554- ARM_BUILTIN_WCMPEQH,
2555- ARM_BUILTIN_WCMPEQW,
2556- ARM_BUILTIN_WCMPGTUB,
2557- ARM_BUILTIN_WCMPGTUH,
2558- ARM_BUILTIN_WCMPGTUW,
2559- ARM_BUILTIN_WCMPGTSB,
2560- ARM_BUILTIN_WCMPGTSH,
2561- ARM_BUILTIN_WCMPGTSW,
2562-
2563- ARM_BUILTIN_TEXTRMSB,
2564- ARM_BUILTIN_TEXTRMSH,
2565- ARM_BUILTIN_TEXTRMSW,
2566- ARM_BUILTIN_TEXTRMUB,
2567- ARM_BUILTIN_TEXTRMUH,
2568- ARM_BUILTIN_TEXTRMUW,
2569- ARM_BUILTIN_TINSRB,
2570- ARM_BUILTIN_TINSRH,
2571- ARM_BUILTIN_TINSRW,
2572-
2573- ARM_BUILTIN_WMAXSW,
2574- ARM_BUILTIN_WMAXSH,
2575- ARM_BUILTIN_WMAXSB,
2576- ARM_BUILTIN_WMAXUW,
2577- ARM_BUILTIN_WMAXUH,
2578- ARM_BUILTIN_WMAXUB,
2579- ARM_BUILTIN_WMINSW,
2580- ARM_BUILTIN_WMINSH,
2581- ARM_BUILTIN_WMINSB,
2582- ARM_BUILTIN_WMINUW,
2583- ARM_BUILTIN_WMINUH,
2584- ARM_BUILTIN_WMINUB,
2585-
2586- ARM_BUILTIN_WMULUM,
2587- ARM_BUILTIN_WMULSM,
2588- ARM_BUILTIN_WMULUL,
2589-
2590- ARM_BUILTIN_PSADBH,
2591- ARM_BUILTIN_WSHUFH,
2592-
2593- ARM_BUILTIN_WSLLH,
2594- ARM_BUILTIN_WSLLW,
2595- ARM_BUILTIN_WSLLD,
2596- ARM_BUILTIN_WSRAH,
2597- ARM_BUILTIN_WSRAW,
2598- ARM_BUILTIN_WSRAD,
2599- ARM_BUILTIN_WSRLH,
2600- ARM_BUILTIN_WSRLW,
2601- ARM_BUILTIN_WSRLD,
2602- ARM_BUILTIN_WRORH,
2603- ARM_BUILTIN_WRORW,
2604- ARM_BUILTIN_WRORD,
2605- ARM_BUILTIN_WSLLHI,
2606- ARM_BUILTIN_WSLLWI,
2607- ARM_BUILTIN_WSLLDI,
2608- ARM_BUILTIN_WSRAHI,
2609- ARM_BUILTIN_WSRAWI,
2610- ARM_BUILTIN_WSRADI,
2611- ARM_BUILTIN_WSRLHI,
2612- ARM_BUILTIN_WSRLWI,
2613- ARM_BUILTIN_WSRLDI,
2614- ARM_BUILTIN_WRORHI,
2615- ARM_BUILTIN_WRORWI,
2616- ARM_BUILTIN_WRORDI,
2617-
2618- ARM_BUILTIN_WUNPCKIHB,
2619- ARM_BUILTIN_WUNPCKIHH,
2620- ARM_BUILTIN_WUNPCKIHW,
2621- ARM_BUILTIN_WUNPCKILB,
2622- ARM_BUILTIN_WUNPCKILH,
2623- ARM_BUILTIN_WUNPCKILW,
2624-
2625- ARM_BUILTIN_WUNPCKEHSB,
2626- ARM_BUILTIN_WUNPCKEHSH,
2627- ARM_BUILTIN_WUNPCKEHSW,
2628- ARM_BUILTIN_WUNPCKEHUB,
2629- ARM_BUILTIN_WUNPCKEHUH,
2630- ARM_BUILTIN_WUNPCKEHUW,
2631- ARM_BUILTIN_WUNPCKELSB,
2632- ARM_BUILTIN_WUNPCKELSH,
2633- ARM_BUILTIN_WUNPCKELSW,
2634- ARM_BUILTIN_WUNPCKELUB,
2635- ARM_BUILTIN_WUNPCKELUH,
2636- ARM_BUILTIN_WUNPCKELUW,
2637-
2638- ARM_BUILTIN_THREAD_POINTER,
2639-
2640- ARM_BUILTIN_NEON_BASE,
2641-
2642- ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2643-};
2644-
2645 /* Do not emit .note.GNU-stack by default. */
2646 #ifndef NEED_INDICATE_EXEC_STACK
2647 #define NEED_INDICATE_EXEC_STACK 0
2648
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106796.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106796.patch
deleted file mode 100644
index 1a940975f..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106796.patch
+++ /dev/null
@@ -1,1255 +0,0 @@
12011-08-25 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF mainline:
4
5 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
6
7 gcc/
8 * tree-ssa-math-opts.c (is_widening_mult_rhs_p): Handle constants
9 beyond conversions.
10 (convert_mult_to_widen): Convert constant inputs to the right type.
11 (convert_plusminus_to_widen): Don't automatically reject inputs that
12 are not an SSA_NAME.
13 Convert constant inputs to the right type.
14
15 gcc/testsuite/
16 * gcc.target/arm/wmul-11.c: New file.
17 * gcc.target/arm/wmul-12.c: New file.
18 * gcc.target/arm/wmul-13.c: New file.
19
20 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
21
22 gcc/
23 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Convert add_rhs
24 to the correct type.
25
26 gcc/testsuite/
27 * gcc.target/arm/wmul-10.c: New file.
28
29 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
30
31 gcc/
32 * tree-ssa-math-opts.c (convert_mult_to_widen): Better handle
33 unsigned inputs of different modes.
34 (convert_plusminus_to_widen): Likewise.
35
36 gcc/testsuite/
37 * gcc.target/arm/wmul-9.c: New file.
38 * gcc.target/arm/wmul-bitfield-2.c: New file.
39
40 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
41
42 gcc/
43 * tree-ssa-math-opts.c (is_widening_mult_rhs_p): Add new argument
44 'type'.
45 Use 'type' from caller, not inferred from 'rhs'.
46 Don't reject non-conversion statements. Do return lhs in this case.
47 (is_widening_mult_p): Add new argument 'type'.
48 Use 'type' from caller, not inferred from 'stmt'.
49 Pass type to is_widening_mult_rhs_p.
50 (convert_mult_to_widen): Pass type to is_widening_mult_p.
51 (convert_plusminus_to_widen): Likewise.
52
53 gcc/testsuite/
54 * gcc.target/arm/wmul-8.c: New file.
55
56 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
57
58 gcc/
59 * tree-ssa-math-opts.c (is_widening_mult_p): Remove FIXME.
60 Ensure the the larger type is the first operand.
61
62 gcc/testsuite/
63 * gcc.target/arm/wmul-7.c: New file.
64
65 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
66
67 gcc/
68 * tree-ssa-math-opts.c (convert_mult_to_widen): Convert
69 unsupported unsigned multiplies to signed.
70 (convert_plusminus_to_widen): Likewise.
71
72 gcc/testsuite/
73 * gcc.target/arm/wmul-6.c: New file.
74
75 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
76
77 gcc/
78 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Permit a single
79 conversion statement separating multiply-and-accumulate.
80
81 gcc/testsuite/
82 * gcc.target/arm/wmul-5.c: New file.
83 * gcc.target/arm/no-wmla-1.c: New file.
84
85 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
86
87 gcc/
88 * config/arm/arm.md (maddhidi4): Remove '*' from name.
89 * expr.c (expand_expr_real_2): Use find_widening_optab_handler.
90 * optabs.c (find_widening_optab_handler_and_mode): New function.
91 (expand_widen_pattern_expr): Use find_widening_optab_handler.
92 (expand_binop_directly): Likewise.
93 (expand_binop): Likewise.
94 * optabs.h (find_widening_optab_handler): New macro define.
95 (find_widening_optab_handler_and_mode): New prototype.
96 * tree-cfg.c (verify_gimple_assign_binary): Adjust WIDEN_MULT_EXPR
97 type precision rules.
98 (verify_gimple_assign_ternary): Likewise for WIDEN_MULT_PLUS_EXPR.
99 * tree-ssa-math-opts.c (build_and_insert_cast): New function.
100 (is_widening_mult_rhs_p): Allow widening by more than one mode.
101 Explicitly disallow mis-matched input types.
102 (convert_mult_to_widen): Use find_widening_optab_handler, and cast
103 input types to fit the new handler.
104 (convert_plusminus_to_widen): Likewise.
105
106 gcc/testsuite/
107 * gcc.target/arm/wmul-bitfield-1.c: New file.
108
109 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
110
111 gcc/
112 * expr.c (expand_expr_real_2): Use widening_optab_handler.
113 * genopinit.c (optabs): Use set_widening_optab_handler for $N.
114 (gen_insn): $N now means $a must be wider than $b, not consecutive.
115 * optabs.c (widened_mode): New function.
116 (expand_widen_pattern_expr): Use widening_optab_handler.
117 (expand_binop_directly): Likewise.
118 (expand_binop): Likewise.
119 * optabs.h (widening_optab_handlers): New struct.
120 (optab_d): New member, 'widening'.
121 (widening_optab_handler): New function.
122 (set_widening_optab_handler): New function.
123 * tree-ssa-math-opts.c (convert_mult_to_widen): Use
124 widening_optab_handler.
125 (convert_plusminus_to_widen): Likewise.
126
127=== modified file 'gcc/config/arm/arm.md'
128--- old/gcc/config/arm/arm.md 2011-08-13 08:32:32 +0000
129+++ new/gcc/config/arm/arm.md 2011-08-25 11:42:09 +0000
130@@ -1839,7 +1839,7 @@
131 (set_attr "predicable" "yes")]
132 )
133
134-(define_insn "*maddhidi4"
135+(define_insn "maddhidi4"
136 [(set (match_operand:DI 0 "s_register_operand" "=r")
137 (plus:DI
138 (mult:DI (sign_extend:DI
139
140=== modified file 'gcc/expr.c'
141--- old/gcc/expr.c 2011-08-13 08:32:32 +0000
142+++ new/gcc/expr.c 2011-08-25 11:42:09 +0000
143@@ -7688,18 +7688,16 @@
144 {
145 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (treeop0));
146 this_optab = usmul_widen_optab;
147- if (mode == GET_MODE_2XWIDER_MODE (innermode))
148+ if (find_widening_optab_handler (this_optab, mode, innermode, 0)
149+ != CODE_FOR_nothing)
150 {
151- if (optab_handler (this_optab, mode) != CODE_FOR_nothing)
152- {
153- if (TYPE_UNSIGNED (TREE_TYPE (treeop0)))
154- expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1,
155- EXPAND_NORMAL);
156- else
157- expand_operands (treeop0, treeop1, NULL_RTX, &op1, &op0,
158- EXPAND_NORMAL);
159- goto binop3;
160- }
161+ if (TYPE_UNSIGNED (TREE_TYPE (treeop0)))
162+ expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1,
163+ EXPAND_NORMAL);
164+ else
165+ expand_operands (treeop0, treeop1, NULL_RTX, &op1, &op0,
166+ EXPAND_NORMAL);
167+ goto binop3;
168 }
169 }
170 /* Check for a multiplication with matching signedness. */
171@@ -7714,10 +7712,10 @@
172 optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab;
173 this_optab = zextend_p ? umul_widen_optab : smul_widen_optab;
174
175- if (mode == GET_MODE_2XWIDER_MODE (innermode)
176- && TREE_CODE (treeop0) != INTEGER_CST)
177+ if (TREE_CODE (treeop0) != INTEGER_CST)
178 {
179- if (optab_handler (this_optab, mode) != CODE_FOR_nothing)
180+ if (find_widening_optab_handler (this_optab, mode, innermode, 0)
181+ != CODE_FOR_nothing)
182 {
183 expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1,
184 EXPAND_NORMAL);
185@@ -7725,7 +7723,8 @@
186 unsignedp, this_optab);
187 return REDUCE_BIT_FIELD (temp);
188 }
189- if (optab_handler (other_optab, mode) != CODE_FOR_nothing
190+ if (find_widening_optab_handler (other_optab, mode, innermode, 0)
191+ != CODE_FOR_nothing
192 && innermode == word_mode)
193 {
194 rtx htem, hipart;
195
196=== modified file 'gcc/genopinit.c'
197--- old/gcc/genopinit.c 2011-05-05 15:43:06 +0000
198+++ new/gcc/genopinit.c 2011-07-15 13:06:31 +0000
199@@ -46,10 +46,12 @@
200 used. $A and $B are replaced with the full name of the mode; $a and $b
201 are replaced with the short form of the name, as above.
202
203- If $N is present in the pattern, it means the two modes must be consecutive
204- widths in the same mode class (e.g, QImode and HImode). $I means that
205- only full integer modes should be considered for the next mode, and $F
206- means that only float modes should be considered.
207+ If $N is present in the pattern, it means the two modes must be in
208+ the same mode class, and $b must be greater than $a (e.g, QImode
209+ and HImode).
210+
211+ $I means that only full integer modes should be considered for the
212+ next mode, and $F means that only float modes should be considered.
213 $P means that both full and partial integer modes should be considered.
214 $Q means that only fixed-point modes should be considered.
215
216@@ -99,17 +101,17 @@
217 "set_optab_handler (smulv_optab, $A, CODE_FOR_$(mulv$I$a3$))",
218 "set_optab_handler (umul_highpart_optab, $A, CODE_FOR_$(umul$a3_highpart$))",
219 "set_optab_handler (smul_highpart_optab, $A, CODE_FOR_$(smul$a3_highpart$))",
220- "set_optab_handler (smul_widen_optab, $B, CODE_FOR_$(mul$a$b3$)$N)",
221- "set_optab_handler (umul_widen_optab, $B, CODE_FOR_$(umul$a$b3$)$N)",
222- "set_optab_handler (usmul_widen_optab, $B, CODE_FOR_$(usmul$a$b3$)$N)",
223- "set_optab_handler (smadd_widen_optab, $B, CODE_FOR_$(madd$a$b4$)$N)",
224- "set_optab_handler (umadd_widen_optab, $B, CODE_FOR_$(umadd$a$b4$)$N)",
225- "set_optab_handler (ssmadd_widen_optab, $B, CODE_FOR_$(ssmadd$a$b4$)$N)",
226- "set_optab_handler (usmadd_widen_optab, $B, CODE_FOR_$(usmadd$a$b4$)$N)",
227- "set_optab_handler (smsub_widen_optab, $B, CODE_FOR_$(msub$a$b4$)$N)",
228- "set_optab_handler (umsub_widen_optab, $B, CODE_FOR_$(umsub$a$b4$)$N)",
229- "set_optab_handler (ssmsub_widen_optab, $B, CODE_FOR_$(ssmsub$a$b4$)$N)",
230- "set_optab_handler (usmsub_widen_optab, $B, CODE_FOR_$(usmsub$a$b4$)$N)",
231+ "set_widening_optab_handler (smul_widen_optab, $B, $A, CODE_FOR_$(mul$a$b3$)$N)",
232+ "set_widening_optab_handler (umul_widen_optab, $B, $A, CODE_FOR_$(umul$a$b3$)$N)",
233+ "set_widening_optab_handler (usmul_widen_optab, $B, $A, CODE_FOR_$(usmul$a$b3$)$N)",
234+ "set_widening_optab_handler (smadd_widen_optab, $B, $A, CODE_FOR_$(madd$a$b4$)$N)",
235+ "set_widening_optab_handler (umadd_widen_optab, $B, $A, CODE_FOR_$(umadd$a$b4$)$N)",
236+ "set_widening_optab_handler (ssmadd_widen_optab, $B, $A, CODE_FOR_$(ssmadd$a$b4$)$N)",
237+ "set_widening_optab_handler (usmadd_widen_optab, $B, $A, CODE_FOR_$(usmadd$a$b4$)$N)",
238+ "set_widening_optab_handler (smsub_widen_optab, $B, $A, CODE_FOR_$(msub$a$b4$)$N)",
239+ "set_widening_optab_handler (umsub_widen_optab, $B, $A, CODE_FOR_$(umsub$a$b4$)$N)",
240+ "set_widening_optab_handler (ssmsub_widen_optab, $B, $A, CODE_FOR_$(ssmsub$a$b4$)$N)",
241+ "set_widening_optab_handler (usmsub_widen_optab, $B, $A, CODE_FOR_$(usmsub$a$b4$)$N)",
242 "set_optab_handler (sdiv_optab, $A, CODE_FOR_$(div$a3$))",
243 "set_optab_handler (ssdiv_optab, $A, CODE_FOR_$(ssdiv$Q$a3$))",
244 "set_optab_handler (sdivv_optab, $A, CODE_FOR_$(div$V$I$a3$))",
245@@ -304,7 +306,7 @@
246 {
247 int force_float = 0, force_int = 0, force_partial_int = 0;
248 int force_fixed = 0;
249- int force_consec = 0;
250+ int force_wider = 0;
251 int matches = 1;
252
253 for (pp = optabs[pindex]; pp[0] != '$' || pp[1] != '('; pp++)
254@@ -322,7 +324,7 @@
255 switch (*++pp)
256 {
257 case 'N':
258- force_consec = 1;
259+ force_wider = 1;
260 break;
261 case 'I':
262 force_int = 1;
263@@ -391,7 +393,10 @@
264 || mode_class[i] == MODE_VECTOR_FRACT
265 || mode_class[i] == MODE_VECTOR_UFRACT
266 || mode_class[i] == MODE_VECTOR_ACCUM
267- || mode_class[i] == MODE_VECTOR_UACCUM))
268+ || mode_class[i] == MODE_VECTOR_UACCUM)
269+ && (! force_wider
270+ || *pp == 'a'
271+ || m1 < i))
272 break;
273 }
274
275@@ -411,8 +416,7 @@
276 }
277
278 if (matches && pp[0] == '$' && pp[1] == ')'
279- && *np == 0
280- && (! force_consec || (int) GET_MODE_WIDER_MODE(m1) == m2))
281+ && *np == 0)
282 break;
283 }
284
285
286=== modified file 'gcc/optabs.c'
287--- old/gcc/optabs.c 2011-07-04 14:03:49 +0000
288+++ new/gcc/optabs.c 2011-08-11 15:46:01 +0000
289@@ -225,6 +225,61 @@
290 return 1;
291 }
292
293+/* Given two input operands, OP0 and OP1, determine what the correct from_mode
294+ for a widening operation would be. In most cases this would be OP0, but if
295+ that's a constant it'll be VOIDmode, which isn't useful. */
296+
297+static enum machine_mode
298+widened_mode (enum machine_mode to_mode, rtx op0, rtx op1)
299+{
300+ enum machine_mode m0 = GET_MODE (op0);
301+ enum machine_mode m1 = GET_MODE (op1);
302+ enum machine_mode result;
303+
304+ if (m0 == VOIDmode && m1 == VOIDmode)
305+ return to_mode;
306+ else if (m0 == VOIDmode || GET_MODE_SIZE (m0) < GET_MODE_SIZE (m1))
307+ result = m1;
308+ else
309+ result = m0;
310+
311+ if (GET_MODE_SIZE (result) > GET_MODE_SIZE (to_mode))
312+ return to_mode;
313+
314+ return result;
315+}
316+
317+/* Find a widening optab even if it doesn't widen as much as we want.
318+ E.g. if from_mode is HImode, and to_mode is DImode, and there is no
319+ direct HI->SI insn, then return SI->DI, if that exists.
320+ If PERMIT_NON_WIDENING is non-zero then this can be used with
321+ non-widening optabs also. */
322+
323+enum insn_code
324+find_widening_optab_handler_and_mode (optab op, enum machine_mode to_mode,
325+ enum machine_mode from_mode,
326+ int permit_non_widening,
327+ enum machine_mode *found_mode)
328+{
329+ for (; (permit_non_widening || from_mode != to_mode)
330+ && GET_MODE_SIZE (from_mode) <= GET_MODE_SIZE (to_mode)
331+ && from_mode != VOIDmode;
332+ from_mode = GET_MODE_WIDER_MODE (from_mode))
333+ {
334+ enum insn_code handler = widening_optab_handler (op, to_mode,
335+ from_mode);
336+
337+ if (handler != CODE_FOR_nothing)
338+ {
339+ if (found_mode)
340+ *found_mode = from_mode;
341+ return handler;
342+ }
343+ }
344+
345+ return CODE_FOR_nothing;
346+}
347+
348 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
349 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
350 not actually do a sign-extend or zero-extend, but can leave the
351@@ -517,8 +572,9 @@
352 optab_for_tree_code (ops->code, TREE_TYPE (oprnd0), optab_default);
353 if (ops->code == WIDEN_MULT_PLUS_EXPR
354 || ops->code == WIDEN_MULT_MINUS_EXPR)
355- icode = (int) optab_handler (widen_pattern_optab,
356- TYPE_MODE (TREE_TYPE (ops->op2)));
357+ icode = (int) find_widening_optab_handler (widen_pattern_optab,
358+ TYPE_MODE (TREE_TYPE (ops->op2)),
359+ tmode0, 0);
360 else
361 icode = (int) optab_handler (widen_pattern_optab, tmode0);
362 gcc_assert (icode != CODE_FOR_nothing);
363@@ -1389,7 +1445,9 @@
364 rtx target, int unsignedp, enum optab_methods methods,
365 rtx last)
366 {
367- int icode = (int) optab_handler (binoptab, mode);
368+ enum machine_mode from_mode = widened_mode (mode, op0, op1);
369+ int icode = (int) find_widening_optab_handler (binoptab, mode,
370+ from_mode, 1);
371 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
372 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
373 enum machine_mode tmp_mode;
374@@ -1546,7 +1604,9 @@
375 /* If we can do it with a three-operand insn, do so. */
376
377 if (methods != OPTAB_MUST_WIDEN
378- && optab_handler (binoptab, mode) != CODE_FOR_nothing)
379+ && find_widening_optab_handler (binoptab, mode,
380+ widened_mode (mode, op0, op1), 1)
381+ != CODE_FOR_nothing)
382 {
383 temp = expand_binop_directly (mode, binoptab, op0, op1, target,
384 unsignedp, methods, last);
385@@ -1586,8 +1646,9 @@
386
387 if (binoptab == smul_optab
388 && GET_MODE_WIDER_MODE (mode) != VOIDmode
389- && (optab_handler ((unsignedp ? umul_widen_optab : smul_widen_optab),
390- GET_MODE_WIDER_MODE (mode))
391+ && (widening_optab_handler ((unsignedp ? umul_widen_optab
392+ : smul_widen_optab),
393+ GET_MODE_WIDER_MODE (mode), mode)
394 != CODE_FOR_nothing))
395 {
396 temp = expand_binop (GET_MODE_WIDER_MODE (mode),
397@@ -1618,9 +1679,11 @@
398 if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing
399 || (binoptab == smul_optab
400 && GET_MODE_WIDER_MODE (wider_mode) != VOIDmode
401- && (optab_handler ((unsignedp ? umul_widen_optab
402- : smul_widen_optab),
403- GET_MODE_WIDER_MODE (wider_mode))
404+ && (find_widening_optab_handler ((unsignedp
405+ ? umul_widen_optab
406+ : smul_widen_optab),
407+ GET_MODE_WIDER_MODE (wider_mode),
408+ mode, 0)
409 != CODE_FOR_nothing)))
410 {
411 rtx xop0 = op0, xop1 = op1;
412@@ -2043,8 +2106,8 @@
413 && optab_handler (add_optab, word_mode) != CODE_FOR_nothing)
414 {
415 rtx product = NULL_RTX;
416-
417- if (optab_handler (umul_widen_optab, mode) != CODE_FOR_nothing)
418+ if (widening_optab_handler (umul_widen_optab, mode, word_mode)
419+ != CODE_FOR_nothing)
420 {
421 product = expand_doubleword_mult (mode, op0, op1, target,
422 true, methods);
423@@ -2053,7 +2116,8 @@
424 }
425
426 if (product == NULL_RTX
427- && optab_handler (smul_widen_optab, mode) != CODE_FOR_nothing)
428+ && widening_optab_handler (smul_widen_optab, mode, word_mode)
429+ != CODE_FOR_nothing)
430 {
431 product = expand_doubleword_mult (mode, op0, op1, target,
432 false, methods);
433@@ -2144,7 +2208,8 @@
434 wider_mode != VOIDmode;
435 wider_mode = GET_MODE_WIDER_MODE (wider_mode))
436 {
437- if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing
438+ if (find_widening_optab_handler (binoptab, wider_mode, mode, 1)
439+ != CODE_FOR_nothing
440 || (methods == OPTAB_LIB
441 && optab_libfunc (binoptab, wider_mode)))
442 {
443
444=== modified file 'gcc/optabs.h'
445--- old/gcc/optabs.h 2011-05-05 15:43:06 +0000
446+++ new/gcc/optabs.h 2011-07-27 14:12:45 +0000
447@@ -42,6 +42,11 @@
448 int insn_code;
449 };
450
451+struct widening_optab_handlers
452+{
453+ struct optab_handlers handlers[NUM_MACHINE_MODES][NUM_MACHINE_MODES];
454+};
455+
456 struct optab_d
457 {
458 enum rtx_code code;
459@@ -50,6 +55,7 @@
460 void (*libcall_gen)(struct optab_d *, const char *name, char suffix,
461 enum machine_mode);
462 struct optab_handlers handlers[NUM_MACHINE_MODES];
463+ struct widening_optab_handlers *widening;
464 };
465 typedef struct optab_d * optab;
466
467@@ -799,6 +805,15 @@
468 extern void emit_unop_insn (int, rtx, rtx, enum rtx_code);
469 extern bool maybe_emit_unop_insn (int, rtx, rtx, enum rtx_code);
470
471+/* Find a widening optab even if it doesn't widen as much as we want. */
472+#define find_widening_optab_handler(A,B,C,D) \
473+ find_widening_optab_handler_and_mode (A, B, C, D, NULL)
474+extern enum insn_code find_widening_optab_handler_and_mode (optab,
475+ enum machine_mode,
476+ enum machine_mode,
477+ int,
478+ enum machine_mode *);
479+
480 /* An extra flag to control optab_for_tree_code's behavior. This is needed to
481 distinguish between machines with a vector shift that takes a scalar for the
482 shift amount vs. machines that take a vector for the shift amount. */
483@@ -874,6 +889,23 @@
484 + (int) CODE_FOR_nothing);
485 }
486
487+/* Like optab_handler, but for widening_operations that have a TO_MODE and
488+ a FROM_MODE. */
489+
490+static inline enum insn_code
491+widening_optab_handler (optab op, enum machine_mode to_mode,
492+ enum machine_mode from_mode)
493+{
494+ if (to_mode == from_mode || from_mode == VOIDmode)
495+ return optab_handler (op, to_mode);
496+
497+ if (op->widening)
498+ return (enum insn_code) (op->widening->handlers[(int) to_mode][(int) from_mode].insn_code
499+ + (int) CODE_FOR_nothing);
500+
501+ return CODE_FOR_nothing;
502+}
503+
504 /* Record that insn CODE should be used to implement mode MODE of OP. */
505
506 static inline void
507@@ -882,6 +914,26 @@
508 op->handlers[(int) mode].insn_code = (int) code - (int) CODE_FOR_nothing;
509 }
510
511+/* Like set_optab_handler, but for widening operations that have a TO_MODE
512+ and a FROM_MODE. */
513+
514+static inline void
515+set_widening_optab_handler (optab op, enum machine_mode to_mode,
516+ enum machine_mode from_mode, enum insn_code code)
517+{
518+ if (to_mode == from_mode)
519+ set_optab_handler (op, to_mode, code);
520+ else
521+ {
522+ if (op->widening == NULL)
523+ op->widening = (struct widening_optab_handlers *)
524+ xcalloc (1, sizeof (struct widening_optab_handlers));
525+
526+ op->widening->handlers[(int) to_mode][(int) from_mode].insn_code
527+ = (int) code - (int) CODE_FOR_nothing;
528+ }
529+}
530+
531 /* Return the insn used to perform conversion OP from mode FROM_MODE
532 to mode TO_MODE; return CODE_FOR_nothing if the target does not have
533 such an insn. */
534
535=== added file 'gcc/testsuite/gcc.target/arm/no-wmla-1.c'
536--- old/gcc/testsuite/gcc.target/arm/no-wmla-1.c 1970-01-01 00:00:00 +0000
537+++ new/gcc/testsuite/gcc.target/arm/no-wmla-1.c 2011-07-15 13:52:38 +0000
538@@ -0,0 +1,11 @@
539+/* { dg-do compile } */
540+/* { dg-options "-O2 -march=armv7-a" } */
541+
542+int
543+foo (int a, short b, short c)
544+{
545+ int bc = b * c;
546+ return a + (short)bc;
547+}
548+
549+/* { dg-final { scan-assembler "mul" } } */
550
551=== added file 'gcc/testsuite/gcc.target/arm/wmul-10.c'
552--- old/gcc/testsuite/gcc.target/arm/wmul-10.c 1970-01-01 00:00:00 +0000
553+++ new/gcc/testsuite/gcc.target/arm/wmul-10.c 2011-07-18 12:56:20 +0000
554@@ -0,0 +1,10 @@
555+/* { dg-do compile } */
556+/* { dg-options "-O2 -march=armv7-a" } */
557+
558+unsigned long long
559+foo (unsigned short a, unsigned short *b, unsigned short *c)
560+{
561+ return (unsigned)a + (unsigned long long)*b * (unsigned long long)*c;
562+}
563+
564+/* { dg-final { scan-assembler "umlal" } } */
565
566=== added file 'gcc/testsuite/gcc.target/arm/wmul-11.c'
567--- old/gcc/testsuite/gcc.target/arm/wmul-11.c 1970-01-01 00:00:00 +0000
568+++ new/gcc/testsuite/gcc.target/arm/wmul-11.c 2011-07-22 15:46:42 +0000
569@@ -0,0 +1,10 @@
570+/* { dg-do compile } */
571+/* { dg-options "-O2 -march=armv7-a" } */
572+
573+long long
574+foo (int *b)
575+{
576+ return 10 * (long long)*b;
577+}
578+
579+/* { dg-final { scan-assembler "smull" } } */
580
581=== added file 'gcc/testsuite/gcc.target/arm/wmul-12.c'
582--- old/gcc/testsuite/gcc.target/arm/wmul-12.c 1970-01-01 00:00:00 +0000
583+++ new/gcc/testsuite/gcc.target/arm/wmul-12.c 2011-07-22 15:46:42 +0000
584@@ -0,0 +1,11 @@
585+/* { dg-do compile } */
586+/* { dg-options "-O2 -march=armv7-a" } */
587+
588+long long
589+foo (int *b, int *c)
590+{
591+ int tmp = *b * *c;
592+ return 10 + (long long)tmp;
593+}
594+
595+/* { dg-final { scan-assembler "smlal" } } */
596
597=== added file 'gcc/testsuite/gcc.target/arm/wmul-13.c'
598--- old/gcc/testsuite/gcc.target/arm/wmul-13.c 1970-01-01 00:00:00 +0000
599+++ new/gcc/testsuite/gcc.target/arm/wmul-13.c 2011-07-22 15:46:42 +0000
600@@ -0,0 +1,10 @@
601+/* { dg-do compile } */
602+/* { dg-options "-O2 -march=armv7-a" } */
603+
604+long long
605+foo (int *a, int *b)
606+{
607+ return *a + (long long)*b * 10;
608+}
609+
610+/* { dg-final { scan-assembler "smlal" } } */
611
612=== added file 'gcc/testsuite/gcc.target/arm/wmul-5.c'
613--- old/gcc/testsuite/gcc.target/arm/wmul-5.c 1970-01-01 00:00:00 +0000
614+++ new/gcc/testsuite/gcc.target/arm/wmul-5.c 2011-07-15 13:52:38 +0000
615@@ -0,0 +1,10 @@
616+/* { dg-do compile } */
617+/* { dg-options "-O2 -march=armv7-a" } */
618+
619+long long
620+foo (long long a, char *b, char *c)
621+{
622+ return a + *b * *c;
623+}
624+
625+/* { dg-final { scan-assembler "umlal" } } */
626
627=== added file 'gcc/testsuite/gcc.target/arm/wmul-6.c'
628--- old/gcc/testsuite/gcc.target/arm/wmul-6.c 1970-01-01 00:00:00 +0000
629+++ new/gcc/testsuite/gcc.target/arm/wmul-6.c 2011-07-15 13:59:11 +0000
630@@ -0,0 +1,10 @@
631+/* { dg-do compile } */
632+/* { dg-options "-O2 -march=armv7-a" } */
633+
634+long long
635+foo (long long a, unsigned char *b, signed char *c)
636+{
637+ return a + (long long)*b * (long long)*c;
638+}
639+
640+/* { dg-final { scan-assembler "smlal" } } */
641
642=== added file 'gcc/testsuite/gcc.target/arm/wmul-7.c'
643--- old/gcc/testsuite/gcc.target/arm/wmul-7.c 1970-01-01 00:00:00 +0000
644+++ new/gcc/testsuite/gcc.target/arm/wmul-7.c 2011-07-15 14:11:23 +0000
645@@ -0,0 +1,10 @@
646+/* { dg-do compile } */
647+/* { dg-options "-O2 -march=armv7-a" } */
648+
649+unsigned long long
650+foo (unsigned long long a, unsigned char *b, unsigned short *c)
651+{
652+ return a + *b * *c;
653+}
654+
655+/* { dg-final { scan-assembler "umlal" } } */
656
657=== added file 'gcc/testsuite/gcc.target/arm/wmul-8.c'
658--- old/gcc/testsuite/gcc.target/arm/wmul-8.c 1970-01-01 00:00:00 +0000
659+++ new/gcc/testsuite/gcc.target/arm/wmul-8.c 2011-07-15 14:16:54 +0000
660@@ -0,0 +1,10 @@
661+/* { dg-do compile } */
662+/* { dg-options "-O2 -march=armv7-a" } */
663+
664+long long
665+foo (long long a, int *b, int *c)
666+{
667+ return a + *b * *c;
668+}
669+
670+/* { dg-final { scan-assembler "smlal" } } */
671
672=== added file 'gcc/testsuite/gcc.target/arm/wmul-9.c'
673--- old/gcc/testsuite/gcc.target/arm/wmul-9.c 1970-01-01 00:00:00 +0000
674+++ new/gcc/testsuite/gcc.target/arm/wmul-9.c 2011-07-15 14:22:39 +0000
675@@ -0,0 +1,10 @@
676+/* { dg-do compile } */
677+/* { dg-options "-O2 -march=armv7-a" } */
678+
679+long long
680+foo (long long a, short *b, char *c)
681+{
682+ return a + *b * *c;
683+}
684+
685+/* { dg-final { scan-assembler "smlalbb" } } */
686
687=== added file 'gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c'
688--- old/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c 1970-01-01 00:00:00 +0000
689+++ new/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c 2011-07-15 13:44:50 +0000
690@@ -0,0 +1,17 @@
691+/* { dg-do compile } */
692+/* { dg-options "-O2 -march=armv7-a" } */
693+
694+struct bf
695+{
696+ int a : 3;
697+ int b : 15;
698+ int c : 3;
699+};
700+
701+long long
702+foo (long long a, struct bf b, struct bf c)
703+{
704+ return a + b.b * c.b;
705+}
706+
707+/* { dg-final { scan-assembler "smlalbb" } } */
708
709=== added file 'gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c'
710--- old/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c 1970-01-01 00:00:00 +0000
711+++ new/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c 2011-07-15 14:22:39 +0000
712@@ -0,0 +1,17 @@
713+/* { dg-do compile } */
714+/* { dg-options "-O2 -march=armv7-a" } */
715+
716+struct bf
717+{
718+ int a : 3;
719+ unsigned int b : 15;
720+ int c : 3;
721+};
722+
723+long long
724+foo (long long a, struct bf b, struct bf c)
725+{
726+ return a + b.b * c.c;
727+}
728+
729+/* { dg-final { scan-assembler "smlalbb" } } */
730
731=== modified file 'gcc/tree-cfg.c'
732--- old/gcc/tree-cfg.c 2011-07-01 09:19:21 +0000
733+++ new/gcc/tree-cfg.c 2011-07-15 13:44:50 +0000
734@@ -3574,7 +3574,7 @@
735 case WIDEN_MULT_EXPR:
736 if (TREE_CODE (lhs_type) != INTEGER_TYPE)
737 return true;
738- return ((2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type))
739+ return ((2 * TYPE_PRECISION (rhs1_type) > TYPE_PRECISION (lhs_type))
740 || (TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type)));
741
742 case WIDEN_SUM_EXPR:
743@@ -3667,7 +3667,7 @@
744 && !FIXED_POINT_TYPE_P (rhs1_type))
745 || !useless_type_conversion_p (rhs1_type, rhs2_type)
746 || !useless_type_conversion_p (lhs_type, rhs3_type)
747- || 2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type)
748+ || 2 * TYPE_PRECISION (rhs1_type) > TYPE_PRECISION (lhs_type)
749 || TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type))
750 {
751 error ("type mismatch in widening multiply-accumulate expression");
752
753=== modified file 'gcc/tree-ssa-math-opts.c'
754--- old/gcc/tree-ssa-math-opts.c 2011-03-11 16:36:16 +0000
755+++ new/gcc/tree-ssa-math-opts.c 2011-08-09 10:26:48 +0000
756@@ -1266,39 +1266,67 @@
757 }
758 };
759
760-/* Return true if RHS is a suitable operand for a widening multiplication.
761+/* Build a gimple assignment to cast VAL to TARGET. Insert the statement
762+ prior to GSI's current position, and return the fresh SSA name. */
763+
764+static tree
765+build_and_insert_cast (gimple_stmt_iterator *gsi, location_t loc,
766+ tree target, tree val)
767+{
768+ tree result = make_ssa_name (target, NULL);
769+ gimple stmt = gimple_build_assign_with_ops (CONVERT_EXPR, result, val, NULL);
770+ gimple_set_location (stmt, loc);
771+ gsi_insert_before (gsi, stmt, GSI_SAME_STMT);
772+ return result;
773+}
774+
775+/* Return true if RHS is a suitable operand for a widening multiplication,
776+ assuming a target type of TYPE.
777 There are two cases:
778
779- - RHS makes some value twice as wide. Store that value in *NEW_RHS_OUT
780- if so, and store its type in *TYPE_OUT.
781+ - RHS makes some value at least twice as wide. Store that value
782+ in *NEW_RHS_OUT if so, and store its type in *TYPE_OUT.
783
784 - RHS is an integer constant. Store that value in *NEW_RHS_OUT if so,
785 but leave *TYPE_OUT untouched. */
786
787 static bool
788-is_widening_mult_rhs_p (tree rhs, tree *type_out, tree *new_rhs_out)
789+is_widening_mult_rhs_p (tree type, tree rhs, tree *type_out,
790+ tree *new_rhs_out)
791 {
792 gimple stmt;
793- tree type, type1, rhs1;
794+ tree type1, rhs1;
795 enum tree_code rhs_code;
796
797 if (TREE_CODE (rhs) == SSA_NAME)
798 {
799- type = TREE_TYPE (rhs);
800 stmt = SSA_NAME_DEF_STMT (rhs);
801- if (!is_gimple_assign (stmt))
802- return false;
803-
804- rhs_code = gimple_assign_rhs_code (stmt);
805- if (TREE_CODE (type) == INTEGER_TYPE
806- ? !CONVERT_EXPR_CODE_P (rhs_code)
807- : rhs_code != FIXED_CONVERT_EXPR)
808- return false;
809-
810- rhs1 = gimple_assign_rhs1 (stmt);
811+ if (is_gimple_assign (stmt))
812+ {
813+ rhs_code = gimple_assign_rhs_code (stmt);
814+ if (TREE_CODE (type) == INTEGER_TYPE
815+ ? !CONVERT_EXPR_CODE_P (rhs_code)
816+ : rhs_code != FIXED_CONVERT_EXPR)
817+ rhs1 = rhs;
818+ else
819+ {
820+ rhs1 = gimple_assign_rhs1 (stmt);
821+
822+ if (TREE_CODE (rhs1) == INTEGER_CST)
823+ {
824+ *new_rhs_out = rhs1;
825+ *type_out = NULL;
826+ return true;
827+ }
828+ }
829+ }
830+ else
831+ rhs1 = rhs;
832+
833 type1 = TREE_TYPE (rhs1);
834+
835 if (TREE_CODE (type1) != TREE_CODE (type)
836- || TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type))
837+ || TYPE_PRECISION (type1) * 2 > TYPE_PRECISION (type))
838 return false;
839
840 *new_rhs_out = rhs1;
841@@ -1316,28 +1344,27 @@
842 return false;
843 }
844
845-/* Return true if STMT performs a widening multiplication. If so,
846- store the unwidened types of the operands in *TYPE1_OUT and *TYPE2_OUT
847- respectively. Also fill *RHS1_OUT and *RHS2_OUT such that converting
848- those operands to types *TYPE1_OUT and *TYPE2_OUT would give the
849- operands of the multiplication. */
850+/* Return true if STMT performs a widening multiplication, assuming the
851+ output type is TYPE. If so, store the unwidened types of the operands
852+ in *TYPE1_OUT and *TYPE2_OUT respectively. Also fill *RHS1_OUT and
853+ *RHS2_OUT such that converting those operands to types *TYPE1_OUT
854+ and *TYPE2_OUT would give the operands of the multiplication. */
855
856 static bool
857-is_widening_mult_p (gimple stmt,
858+is_widening_mult_p (tree type, gimple stmt,
859 tree *type1_out, tree *rhs1_out,
860 tree *type2_out, tree *rhs2_out)
861 {
862- tree type;
863-
864- type = TREE_TYPE (gimple_assign_lhs (stmt));
865 if (TREE_CODE (type) != INTEGER_TYPE
866 && TREE_CODE (type) != FIXED_POINT_TYPE)
867 return false;
868
869- if (!is_widening_mult_rhs_p (gimple_assign_rhs1 (stmt), type1_out, rhs1_out))
870+ if (!is_widening_mult_rhs_p (type, gimple_assign_rhs1 (stmt), type1_out,
871+ rhs1_out))
872 return false;
873
874- if (!is_widening_mult_rhs_p (gimple_assign_rhs2 (stmt), type2_out, rhs2_out))
875+ if (!is_widening_mult_rhs_p (type, gimple_assign_rhs2 (stmt), type2_out,
876+ rhs2_out))
877 return false;
878
879 if (*type1_out == NULL)
880@@ -1354,6 +1381,18 @@
881 *type2_out = *type1_out;
882 }
883
884+ /* Ensure that the larger of the two operands comes first. */
885+ if (TYPE_PRECISION (*type1_out) < TYPE_PRECISION (*type2_out))
886+ {
887+ tree tmp;
888+ tmp = *type1_out;
889+ *type1_out = *type2_out;
890+ *type2_out = tmp;
891+ tmp = *rhs1_out;
892+ *rhs1_out = *rhs2_out;
893+ *rhs2_out = tmp;
894+ }
895+
896 return true;
897 }
898
899@@ -1362,31 +1401,100 @@
900 value is true iff we converted the statement. */
901
902 static bool
903-convert_mult_to_widen (gimple stmt)
904+convert_mult_to_widen (gimple stmt, gimple_stmt_iterator *gsi)
905 {
906- tree lhs, rhs1, rhs2, type, type1, type2;
907+ tree lhs, rhs1, rhs2, type, type1, type2, tmp = NULL;
908 enum insn_code handler;
909+ enum machine_mode to_mode, from_mode, actual_mode;
910+ optab op;
911+ int actual_precision;
912+ location_t loc = gimple_location (stmt);
913+ bool from_unsigned1, from_unsigned2;
914
915 lhs = gimple_assign_lhs (stmt);
916 type = TREE_TYPE (lhs);
917 if (TREE_CODE (type) != INTEGER_TYPE)
918 return false;
919
920- if (!is_widening_mult_p (stmt, &type1, &rhs1, &type2, &rhs2))
921+ if (!is_widening_mult_p (type, stmt, &type1, &rhs1, &type2, &rhs2))
922 return false;
923
924- if (TYPE_UNSIGNED (type1) && TYPE_UNSIGNED (type2))
925- handler = optab_handler (umul_widen_optab, TYPE_MODE (type));
926- else if (!TYPE_UNSIGNED (type1) && !TYPE_UNSIGNED (type2))
927- handler = optab_handler (smul_widen_optab, TYPE_MODE (type));
928+ to_mode = TYPE_MODE (type);
929+ from_mode = TYPE_MODE (type1);
930+ from_unsigned1 = TYPE_UNSIGNED (type1);
931+ from_unsigned2 = TYPE_UNSIGNED (type2);
932+
933+ if (from_unsigned1 && from_unsigned2)
934+ op = umul_widen_optab;
935+ else if (!from_unsigned1 && !from_unsigned2)
936+ op = smul_widen_optab;
937 else
938- handler = optab_handler (usmul_widen_optab, TYPE_MODE (type));
939+ op = usmul_widen_optab;
940+
941+ handler = find_widening_optab_handler_and_mode (op, to_mode, from_mode,
942+ 0, &actual_mode);
943
944 if (handler == CODE_FOR_nothing)
945- return false;
946-
947- gimple_assign_set_rhs1 (stmt, fold_convert (type1, rhs1));
948- gimple_assign_set_rhs2 (stmt, fold_convert (type2, rhs2));
949+ {
950+ if (op != smul_widen_optab)
951+ {
952+ /* We can use a signed multiply with unsigned types as long as
953+ there is a wider mode to use, or it is the smaller of the two
954+ types that is unsigned. Note that type1 >= type2, always. */
955+ if ((TYPE_UNSIGNED (type1)
956+ && TYPE_PRECISION (type1) == GET_MODE_PRECISION (from_mode))
957+ || (TYPE_UNSIGNED (type2)
958+ && TYPE_PRECISION (type2) == GET_MODE_PRECISION (from_mode)))
959+ {
960+ from_mode = GET_MODE_WIDER_MODE (from_mode);
961+ if (GET_MODE_SIZE (to_mode) <= GET_MODE_SIZE (from_mode))
962+ return false;
963+ }
964+
965+ op = smul_widen_optab;
966+ handler = find_widening_optab_handler_and_mode (op, to_mode,
967+ from_mode, 0,
968+ &actual_mode);
969+
970+ if (handler == CODE_FOR_nothing)
971+ return false;
972+
973+ from_unsigned1 = from_unsigned2 = false;
974+ }
975+ else
976+ return false;
977+ }
978+
979+ /* Ensure that the inputs to the handler are in the correct precison
980+ for the opcode. This will be the full mode size. */
981+ actual_precision = GET_MODE_PRECISION (actual_mode);
982+ if (actual_precision != TYPE_PRECISION (type1)
983+ || from_unsigned1 != TYPE_UNSIGNED (type1))
984+ {
985+ tmp = create_tmp_var (build_nonstandard_integer_type
986+ (actual_precision, from_unsigned1),
987+ NULL);
988+ rhs1 = build_and_insert_cast (gsi, loc, tmp, rhs1);
989+ }
990+ if (actual_precision != TYPE_PRECISION (type2)
991+ || from_unsigned2 != TYPE_UNSIGNED (type2))
992+ {
993+ /* Reuse the same type info, if possible. */
994+ if (!tmp || from_unsigned1 != from_unsigned2)
995+ tmp = create_tmp_var (build_nonstandard_integer_type
996+ (actual_precision, from_unsigned2),
997+ NULL);
998+ rhs2 = build_and_insert_cast (gsi, loc, tmp, rhs2);
999+ }
1000+
1001+ /* Handle constants. */
1002+ if (TREE_CODE (rhs1) == INTEGER_CST)
1003+ rhs1 = fold_convert (type1, rhs1);
1004+ if (TREE_CODE (rhs2) == INTEGER_CST)
1005+ rhs2 = fold_convert (type2, rhs2);
1006+
1007+ gimple_assign_set_rhs1 (stmt, rhs1);
1008+ gimple_assign_set_rhs2 (stmt, rhs2);
1009 gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR);
1010 update_stmt (stmt);
1011 return true;
1012@@ -1403,11 +1511,17 @@
1013 enum tree_code code)
1014 {
1015 gimple rhs1_stmt = NULL, rhs2_stmt = NULL;
1016- tree type, type1, type2;
1017+ gimple conv1_stmt = NULL, conv2_stmt = NULL, conv_stmt;
1018+ tree type, type1, type2, optype, tmp = NULL;
1019 tree lhs, rhs1, rhs2, mult_rhs1, mult_rhs2, add_rhs;
1020 enum tree_code rhs1_code = ERROR_MARK, rhs2_code = ERROR_MARK;
1021 optab this_optab;
1022 enum tree_code wmult_code;
1023+ enum insn_code handler;
1024+ enum machine_mode to_mode, from_mode, actual_mode;
1025+ location_t loc = gimple_location (stmt);
1026+ int actual_precision;
1027+ bool from_unsigned1, from_unsigned2;
1028
1029 lhs = gimple_assign_lhs (stmt);
1030 type = TREE_TYPE (lhs);
1031@@ -1429,8 +1543,6 @@
1032 if (is_gimple_assign (rhs1_stmt))
1033 rhs1_code = gimple_assign_rhs_code (rhs1_stmt);
1034 }
1035- else
1036- return false;
1037
1038 if (TREE_CODE (rhs2) == SSA_NAME)
1039 {
1040@@ -1438,57 +1550,160 @@
1041 if (is_gimple_assign (rhs2_stmt))
1042 rhs2_code = gimple_assign_rhs_code (rhs2_stmt);
1043 }
1044- else
1045- return false;
1046-
1047- if (code == PLUS_EXPR && rhs1_code == MULT_EXPR)
1048- {
1049- if (!is_widening_mult_p (rhs1_stmt, &type1, &mult_rhs1,
1050- &type2, &mult_rhs2))
1051- return false;
1052- add_rhs = rhs2;
1053- }
1054- else if (rhs2_code == MULT_EXPR)
1055- {
1056- if (!is_widening_mult_p (rhs2_stmt, &type1, &mult_rhs1,
1057- &type2, &mult_rhs2))
1058- return false;
1059- add_rhs = rhs1;
1060- }
1061- else if (code == PLUS_EXPR && rhs1_code == WIDEN_MULT_EXPR)
1062- {
1063- mult_rhs1 = gimple_assign_rhs1 (rhs1_stmt);
1064- mult_rhs2 = gimple_assign_rhs2 (rhs1_stmt);
1065- type1 = TREE_TYPE (mult_rhs1);
1066- type2 = TREE_TYPE (mult_rhs2);
1067- add_rhs = rhs2;
1068- }
1069- else if (rhs2_code == WIDEN_MULT_EXPR)
1070- {
1071- mult_rhs1 = gimple_assign_rhs1 (rhs2_stmt);
1072- mult_rhs2 = gimple_assign_rhs2 (rhs2_stmt);
1073- type1 = TREE_TYPE (mult_rhs1);
1074- type2 = TREE_TYPE (mult_rhs2);
1075- add_rhs = rhs1;
1076- }
1077- else
1078- return false;
1079-
1080- if (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2))
1081- return false;
1082+
1083+ /* Allow for one conversion statement between the multiply
1084+ and addition/subtraction statement. If there are more than
1085+ one conversions then we assume they would invalidate this
1086+ transformation. If that's not the case then they should have
1087+ been folded before now. */
1088+ if (CONVERT_EXPR_CODE_P (rhs1_code))
1089+ {
1090+ conv1_stmt = rhs1_stmt;
1091+ rhs1 = gimple_assign_rhs1 (rhs1_stmt);
1092+ if (TREE_CODE (rhs1) == SSA_NAME)
1093+ {
1094+ rhs1_stmt = SSA_NAME_DEF_STMT (rhs1);
1095+ if (is_gimple_assign (rhs1_stmt))
1096+ rhs1_code = gimple_assign_rhs_code (rhs1_stmt);
1097+ }
1098+ else
1099+ return false;
1100+ }
1101+ if (CONVERT_EXPR_CODE_P (rhs2_code))
1102+ {
1103+ conv2_stmt = rhs2_stmt;
1104+ rhs2 = gimple_assign_rhs1 (rhs2_stmt);
1105+ if (TREE_CODE (rhs2) == SSA_NAME)
1106+ {
1107+ rhs2_stmt = SSA_NAME_DEF_STMT (rhs2);
1108+ if (is_gimple_assign (rhs2_stmt))
1109+ rhs2_code = gimple_assign_rhs_code (rhs2_stmt);
1110+ }
1111+ else
1112+ return false;
1113+ }
1114+
1115+ /* If code is WIDEN_MULT_EXPR then it would seem unnecessary to call
1116+ is_widening_mult_p, but we still need the rhs returns.
1117+
1118+ It might also appear that it would be sufficient to use the existing
1119+ operands of the widening multiply, but that would limit the choice of
1120+ multiply-and-accumulate instructions. */
1121+ if (code == PLUS_EXPR
1122+ && (rhs1_code == MULT_EXPR || rhs1_code == WIDEN_MULT_EXPR))
1123+ {
1124+ if (!is_widening_mult_p (type, rhs1_stmt, &type1, &mult_rhs1,
1125+ &type2, &mult_rhs2))
1126+ return false;
1127+ add_rhs = rhs2;
1128+ conv_stmt = conv1_stmt;
1129+ }
1130+ else if (rhs2_code == MULT_EXPR || rhs2_code == WIDEN_MULT_EXPR)
1131+ {
1132+ if (!is_widening_mult_p (type, rhs2_stmt, &type1, &mult_rhs1,
1133+ &type2, &mult_rhs2))
1134+ return false;
1135+ add_rhs = rhs1;
1136+ conv_stmt = conv2_stmt;
1137+ }
1138+ else
1139+ return false;
1140+
1141+ to_mode = TYPE_MODE (type);
1142+ from_mode = TYPE_MODE (type1);
1143+ from_unsigned1 = TYPE_UNSIGNED (type1);
1144+ from_unsigned2 = TYPE_UNSIGNED (type2);
1145+
1146+ /* There's no such thing as a mixed sign madd yet, so use a wider mode. */
1147+ if (from_unsigned1 != from_unsigned2)
1148+ {
1149+ /* We can use a signed multiply with unsigned types as long as
1150+ there is a wider mode to use, or it is the smaller of the two
1151+ types that is unsigned. Note that type1 >= type2, always. */
1152+ if ((from_unsigned1
1153+ && TYPE_PRECISION (type1) == GET_MODE_PRECISION (from_mode))
1154+ || (from_unsigned2
1155+ && TYPE_PRECISION (type2) == GET_MODE_PRECISION (from_mode)))
1156+ {
1157+ from_mode = GET_MODE_WIDER_MODE (from_mode);
1158+ if (GET_MODE_SIZE (from_mode) >= GET_MODE_SIZE (to_mode))
1159+ return false;
1160+ }
1161+
1162+ from_unsigned1 = from_unsigned2 = false;
1163+ }
1164+
1165+ /* If there was a conversion between the multiply and addition
1166+ then we need to make sure it fits a multiply-and-accumulate.
1167+ The should be a single mode change which does not change the
1168+ value. */
1169+ if (conv_stmt)
1170+ {
1171+ /* We use the original, unmodified data types for this. */
1172+ tree from_type = TREE_TYPE (gimple_assign_rhs1 (conv_stmt));
1173+ tree to_type = TREE_TYPE (gimple_assign_lhs (conv_stmt));
1174+ int data_size = TYPE_PRECISION (type1) + TYPE_PRECISION (type2);
1175+ bool is_unsigned = TYPE_UNSIGNED (type1) && TYPE_UNSIGNED (type2);
1176+
1177+ if (TYPE_PRECISION (from_type) > TYPE_PRECISION (to_type))
1178+ {
1179+ /* Conversion is a truncate. */
1180+ if (TYPE_PRECISION (to_type) < data_size)
1181+ return false;
1182+ }
1183+ else if (TYPE_PRECISION (from_type) < TYPE_PRECISION (to_type))
1184+ {
1185+ /* Conversion is an extend. Check it's the right sort. */
1186+ if (TYPE_UNSIGNED (from_type) != is_unsigned
1187+ && !(is_unsigned && TYPE_PRECISION (from_type) > data_size))
1188+ return false;
1189+ }
1190+ /* else convert is a no-op for our purposes. */
1191+ }
1192
1193 /* Verify that the machine can perform a widening multiply
1194 accumulate in this mode/signedness combination, otherwise
1195 this transformation is likely to pessimize code. */
1196- this_optab = optab_for_tree_code (wmult_code, type1, optab_default);
1197- if (optab_handler (this_optab, TYPE_MODE (type)) == CODE_FOR_nothing)
1198+ optype = build_nonstandard_integer_type (from_mode, from_unsigned1);
1199+ this_optab = optab_for_tree_code (wmult_code, optype, optab_default);
1200+ handler = find_widening_optab_handler_and_mode (this_optab, to_mode,
1201+ from_mode, 0, &actual_mode);
1202+
1203+ if (handler == CODE_FOR_nothing)
1204 return false;
1205
1206- /* ??? May need some type verification here? */
1207-
1208- gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code,
1209- fold_convert (type1, mult_rhs1),
1210- fold_convert (type2, mult_rhs2),
1211+ /* Ensure that the inputs to the handler are in the correct precison
1212+ for the opcode. This will be the full mode size. */
1213+ actual_precision = GET_MODE_PRECISION (actual_mode);
1214+ if (actual_precision != TYPE_PRECISION (type1)
1215+ || from_unsigned1 != TYPE_UNSIGNED (type1))
1216+ {
1217+ tmp = create_tmp_var (build_nonstandard_integer_type
1218+ (actual_precision, from_unsigned1),
1219+ NULL);
1220+ mult_rhs1 = build_and_insert_cast (gsi, loc, tmp, mult_rhs1);
1221+ }
1222+ if (actual_precision != TYPE_PRECISION (type2)
1223+ || from_unsigned2 != TYPE_UNSIGNED (type2))
1224+ {
1225+ if (!tmp || from_unsigned1 != from_unsigned2)
1226+ tmp = create_tmp_var (build_nonstandard_integer_type
1227+ (actual_precision, from_unsigned2),
1228+ NULL);
1229+ mult_rhs2 = build_and_insert_cast (gsi, loc, tmp, mult_rhs2);
1230+ }
1231+
1232+ if (!useless_type_conversion_p (type, TREE_TYPE (add_rhs)))
1233+ add_rhs = build_and_insert_cast (gsi, loc, create_tmp_var (type, NULL),
1234+ add_rhs);
1235+
1236+ /* Handle constants. */
1237+ if (TREE_CODE (mult_rhs1) == INTEGER_CST)
1238+ rhs1 = fold_convert (type1, mult_rhs1);
1239+ if (TREE_CODE (mult_rhs2) == INTEGER_CST)
1240+ rhs2 = fold_convert (type2, mult_rhs2);
1241+
1242+ gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code, mult_rhs1, mult_rhs2,
1243 add_rhs);
1244 update_stmt (gsi_stmt (*gsi));
1245 return true;
1246@@ -1696,7 +1911,7 @@
1247 switch (code)
1248 {
1249 case MULT_EXPR:
1250- if (!convert_mult_to_widen (stmt)
1251+ if (!convert_mult_to_widen (stmt, &gsi)
1252 && convert_mult_to_fma (stmt,
1253 gimple_assign_rhs1 (stmt),
1254 gimple_assign_rhs2 (stmt)))
1255
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106797.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106797.patch
deleted file mode 100644
index 8230beb91..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106797.patch
+++ /dev/null
@@ -1,23 +0,0 @@
12011-08-26 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-08-26 Richard Sandiford <richard.sandiford@linaro.org>
7
8 * df-problems.c (df_note_bb_compute): Pass uses rather than defs
9 to df_set_dead_notes_for_mw.
10
11=== modified file 'gcc/df-problems.c'
12--- old/gcc/df-problems.c 2011-07-07 19:10:01 +0000
13+++ new/gcc/df-problems.c 2011-08-26 14:32:47 +0000
14@@ -3375,7 +3375,7 @@
15 while (*mws_rec)
16 {
17 struct df_mw_hardreg *mws = *mws_rec;
18- if ((DF_MWS_REG_DEF_P (mws))
19+ if (DF_MWS_REG_USE_P (mws)
20 && !df_ignore_stack_reg (mws->start_regno))
21 {
22 bool really_add_notes = debug_insn != 0;
23
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106798.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106798.patch
deleted file mode 100644
index aa067b711..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106798.patch
+++ /dev/null
@@ -1,23 +0,0 @@
12011-09-05 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 gcc/
4
5 2011-08-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
6
7 PR target/48328
8 * config/arm/arm.h (CASE_VECTOR_SHORTEN_MODE): Fix distance
9 for tbh instructions.
10
11=== modified file 'gcc/config/arm/arm.h'
12--- old/gcc/config/arm/arm.h 2011-08-24 17:35:16 +0000
13+++ new/gcc/config/arm/arm.h 2011-09-05 14:32:11 +0000
14@@ -1961,7 +1961,7 @@
15 : min >= -4096 && max < 4096 \
16 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
17 : SImode) \
18- : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
19+ : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \
20 : (max >= 0x200) ? HImode \
21 : QImode))
22
23
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106799.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106799.patch
deleted file mode 100644
index c440db91e..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106799.patch
+++ /dev/null
@@ -1,75 +0,0 @@
1 2011-09-05 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline.
4 2011-08-26 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
5
6 * config/arm/cortex-a9.md ("cortex_a9_mult_long"): New.
7 ("cortex_a9_multiply_long"): New and use above. Handle all
8 long multiply cases.
9 ("cortex_a9_multiply"): Handle smmul and smmulr.
10 ("cortex_a9_mac"): Handle smmla.
11
12=== modified file 'gcc/config/arm/cortex-a9.md'
13--- old/gcc/config/arm/cortex-a9.md 2011-01-18 15:28:08 +0000
14+++ new/gcc/config/arm/cortex-a9.md 2011-08-26 08:52:15 +0000
15@@ -68,7 +68,8 @@
16 "cortex_a9_mac_m1*2, cortex_a9_mac_m2, cortex_a9_p0_wb")
17 (define_reservation "cortex_a9_mac"
18 "cortex_a9_multcycle1*2 ,cortex_a9_mac_m2, cortex_a9_p0_wb")
19-
20+(define_reservation "cortex_a9_mult_long"
21+ "cortex_a9_mac_m1*3, cortex_a9_mac_m2, cortex_a9_p0_wb")
22
23 ;; Issue at the same time along the load store pipeline and
24 ;; the VFP / Neon pipeline is not possible.
25@@ -139,29 +140,35 @@
26 (eq_attr "insn" "smlaxy"))
27 "cortex_a9_mac16")
28
29-
30 (define_insn_reservation "cortex_a9_multiply" 4
31 (and (eq_attr "tune" "cortexa9")
32- (eq_attr "insn" "mul"))
33+ (eq_attr "insn" "mul,smmul,smmulr"))
34 "cortex_a9_mult")
35
36 (define_insn_reservation "cortex_a9_mac" 4
37 (and (eq_attr "tune" "cortexa9")
38- (eq_attr "insn" "mla"))
39+ (eq_attr "insn" "mla,smmla"))
40 "cortex_a9_mac")
41
42+(define_insn_reservation "cortex_a9_multiply_long" 5
43+ (and (eq_attr "tune" "cortexa9")
44+ (eq_attr "insn" "smull,umull,smulls,umulls,smlal,smlals,umlal,umlals"))
45+ "cortex_a9_mult_long")
46+
47 ;; An instruction with a result in E2 can be forwarded
48 ;; to E2 or E1 or M1 or the load store unit in the next cycle.
49
50 (define_bypass 1 "cortex_a9_dp"
51 "cortex_a9_dp_shift, cortex_a9_multiply,
52 cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
53- cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4")
54+ cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4,
55+ cortex_a9_multiply_long")
56
57 (define_bypass 2 "cortex_a9_dp_shift"
58 "cortex_a9_dp_shift, cortex_a9_multiply,
59 cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
60- cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4")
61+ cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4,
62+ cortex_a9_multiply_long")
63
64 ;; An instruction in the load store pipeline can provide
65 ;; read access to a DP instruction in the P0 default pipeline
66@@ -212,7 +219,7 @@
67
68 (define_bypass 1
69 "cortex_a9_fps"
70- "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply")
71+ "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply, cortex_a9_multiply_long")
72
73 ;; Scheduling on the FP_ADD pipeline.
74 (define_reservation "ca9fp_add" "ca9_issue_vfp_neon + ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4")
75
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106800.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106800.patch
deleted file mode 100644
index dfdeec724..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106800.patch
+++ /dev/null
@@ -1,1270 +0,0 @@
12011-09-07 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from mainline:
4
5 2011-08-04 Ira Rosen <ira.rosen@linaro.org>
6
7 gcc/
8 * tree-vectorizer.h (struct _stmt_vec_info): Add new field for
9 pattern def statement, and its access macro.
10 (NUM_PATTERNS): Set to 5.
11 * tree-vect-loop.c (vect_determine_vectorization_factor): Handle
12 pattern def statement.
13 (vect_transform_loop): Likewise.
14 * tree-vect-patterns.c (vect_vect_recog_func_ptrs): Add new
15 function vect_recog_over_widening_pattern ().
16 (vect_operation_fits_smaller_type): New function.
17 (vect_recog_over_widening_pattern, vect_mark_pattern_stmts):
18 Likewise.
19 (vect_pattern_recog_1): Move the code that marks pattern
20 statements to vect_mark_pattern_stmts (), and call it. Update
21 documentation.
22 * tree-vect-stmts.c (vect_supportable_shift): New function.
23 (vect_analyze_stmt): Handle pattern def statement.
24 (new_stmt_vec_info): Initialize pattern def statement.
25
26 gcc/testsuite/
27 * gcc.dg/vect/vect-over-widen-1.c: New test.
28 * gcc.dg/vect/vect-over-widen-2.c: New test.
29 * gcc.dg/vect/vect-over-widen-3.c: New test.
30 * gcc.dg/vect/vect-over-widen-4.c: New test.
31
32
33 2011-08-09 Ira Rosen <ira.rosen@linaro.org>
34
35 gcc/
36 PR tree-optimization/50014
37 * tree-vect-loop.c (vectorizable_reduction): Get def type before
38 calling vect_get_vec_def_for_stmt_copy ().
39
40 gcc/testsuite/
41 PR tree-optimization/50014
42 * gcc.dg/vect/pr50014.c: New test.
43
44
45 2011-08-11 Ira Rosen <ira.rosen@linaro.org>
46
47 gcc/
48 PR tree-optimization/50039
49 * tree-vect-patterns.c (vect_operation_fits_smaller_type): Check
50 that DEF_STMT has a stmt_vec_info.
51
52 gcc/testsuite/
53 PR tree-optimization/50039
54 * gcc.dg/vect/vect.exp: Run no-tree-fre-* tests with -fno-tree-fre.
55 * gcc.dg/vect/no-tree-fre-pr50039.c: New test.
56
57
58 2011-09-04 Jakub Jelinek <jakub@redhat.com>
59 Ira Rosen <ira.rosen@linaro.org>
60
61 gcc/
62 PR tree-optimization/50208
63 * tree-vect-patterns.c (vect_handle_widen_mult_by_const): Add an
64 argument. Check that def_stmt is inside the loop.
65 (vect_recog_widen_mult_pattern): Update calls to
66 vect_handle_widen_mult_by_cons.
67 (vect_operation_fits_smaller_type): Check that def_stmt is
68 inside the loop.
69
70 gcc/testsuite/
71 PR tree-optimization/50208
72 * gcc.dg/vect/no-fre-pre-pr50208.c: New test.
73 * gcc.dg/vect/vect.exp: Run no-fre-pre-*.c tests with
74 -fno-tree-fre -fno-tree-pre.
75
76=== added file 'gcc/testsuite/gcc.dg/vect/no-fre-pre-pr50208.c'
77--- old/gcc/testsuite/gcc.dg/vect/no-fre-pre-pr50208.c 1970-01-01 00:00:00 +0000
78+++ new/gcc/testsuite/gcc.dg/vect/no-fre-pre-pr50208.c 2011-09-05 06:23:37 +0000
79@@ -0,0 +1,17 @@
80+/* { dg-do compile } */
81+
82+char c;
83+int a, b;
84+
85+void foo (int j)
86+{
87+ int i;
88+ while (--j)
89+ {
90+ b = 3;
91+ for (i = 0; i < 2; ++i)
92+ a = b ^ c;
93+ }
94+}
95+
96+/* { dg-final { cleanup-tree-dump "vect" } } */
97
98=== added file 'gcc/testsuite/gcc.dg/vect/no-tree-fre-pr50039.c'
99--- old/gcc/testsuite/gcc.dg/vect/no-tree-fre-pr50039.c 1970-01-01 00:00:00 +0000
100+++ new/gcc/testsuite/gcc.dg/vect/no-tree-fre-pr50039.c 2011-09-05 06:23:37 +0000
101@@ -0,0 +1,15 @@
102+/* { dg-do compile } */
103+
104+extern unsigned char g_5;
105+extern int g_31, g_76;
106+int main(void) {
107+ int i, j;
108+ for (j=0; j < 2; ++j) {
109+ g_31 = -3;
110+ for (i=0; i < 2; ++i)
111+ g_76 = (g_31 ? g_31+1 : 0) ^ g_5;
112+ }
113+}
114+
115+/* { dg-final { cleanup-tree-dump "vect" } } */
116+
117
118=== added file 'gcc/testsuite/gcc.dg/vect/pr50014.c'
119--- old/gcc/testsuite/gcc.dg/vect/pr50014.c 1970-01-01 00:00:00 +0000
120+++ new/gcc/testsuite/gcc.dg/vect/pr50014.c 2011-09-05 06:23:37 +0000
121@@ -0,0 +1,16 @@
122+/* { dg-do compile } */
123+/* { dg-require-effective-target vect_int } */
124+
125+int f(unsigned char *s, int n)
126+{
127+ int sum = 0;
128+ int i;
129+
130+ for (i = 0; i < n; i++)
131+ sum += 256 * s[i];
132+
133+ return sum;
134+}
135+
136+/* { dg-final { cleanup-tree-dump "vect" } } */
137+
138
139=== added file 'gcc/testsuite/gcc.dg/vect/vect-over-widen-1.c'
140--- old/gcc/testsuite/gcc.dg/vect/vect-over-widen-1.c 1970-01-01 00:00:00 +0000
141+++ new/gcc/testsuite/gcc.dg/vect/vect-over-widen-1.c 2011-09-05 06:23:37 +0000
142@@ -0,0 +1,64 @@
143+/* { dg-require-effective-target vect_int } */
144+/* { dg-require-effective-target vect_shift } */
145+
146+#include <stdlib.h>
147+#include <stdarg.h>
148+#include "tree-vect.h"
149+
150+#define N 64
151+
152+/* Modified rgb to rgb conversion from FFmpeg. */
153+__attribute__ ((noinline)) void
154+foo (unsigned char *src, unsigned char *dst)
155+{
156+ unsigned char *s = src;
157+ unsigned short *d = (unsigned short *)dst;
158+ int i;
159+
160+ for (i = 0; i < N/4; i++)
161+ {
162+ const int b = *s++;
163+ const int g = *s++;
164+ const int r = *s++;
165+ const int a = *s++;
166+ *d = ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5));
167+ d++;
168+ }
169+
170+ s = src;
171+ d = (unsigned short *)dst;
172+ for (i = 0; i < N/4; i++)
173+ {
174+ const int b = *s++;
175+ const int g = *s++;
176+ const int r = *s++;
177+ const int a = *s++;
178+ if (*d != ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5)))
179+ abort ();
180+ d++;
181+ }
182+}
183+
184+int main (void)
185+{
186+ int i;
187+ unsigned char in[N], out[N];
188+
189+ check_vect ();
190+
191+ for (i = 0; i < N; i++)
192+ {
193+ in[i] = i;
194+ out[i] = 255;
195+ __asm__ volatile ("");
196+ }
197+
198+ foo (in, out);
199+
200+ return 0;
201+}
202+
203+/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" } } */
204+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
205+/* { dg-final { cleanup-tree-dump "vect" } } */
206+
207
208=== added file 'gcc/testsuite/gcc.dg/vect/vect-over-widen-2.c'
209--- old/gcc/testsuite/gcc.dg/vect/vect-over-widen-2.c 1970-01-01 00:00:00 +0000
210+++ new/gcc/testsuite/gcc.dg/vect/vect-over-widen-2.c 2011-09-05 06:23:37 +0000
211@@ -0,0 +1,65 @@
212+/* { dg-require-effective-target vect_int } */
213+/* { dg-require-effective-target vect_shift } */
214+
215+#include <stdlib.h>
216+#include <stdarg.h>
217+#include "tree-vect.h"
218+
219+#define N 64
220+
221+/* Modified rgb to rgb conversion from FFmpeg. */
222+__attribute__ ((noinline)) void
223+foo (unsigned char *src, unsigned char *dst)
224+{
225+ unsigned char *s = src;
226+ int *d = (int *)dst;
227+ int i;
228+
229+ for (i = 0; i < N/4; i++)
230+ {
231+ const int b = *s++;
232+ const int g = *s++;
233+ const int r = *s++;
234+ const int a = *s++;
235+ *d = ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5));
236+ d++;
237+ }
238+
239+ s = src;
240+ d = (int *)dst;
241+ for (i = 0; i < N/4; i++)
242+ {
243+ const int b = *s++;
244+ const int g = *s++;
245+ const int r = *s++;
246+ const int a = *s++;
247+ if (*d != ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5)))
248+ abort ();
249+ d++;
250+ }
251+}
252+
253+int main (void)
254+{
255+ int i;
256+ unsigned char in[N], out[N];
257+
258+ check_vect ();
259+
260+ for (i = 0; i < N; i++)
261+ {
262+ in[i] = i;
263+ out[i] = 255;
264+ __asm__ volatile ("");
265+ }
266+
267+ foo (in, out);
268+
269+ return 0;
270+}
271+
272+/* Final value stays in int, so no over-widening is detected at the moment. */
273+/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 0 "vect" } } */
274+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
275+/* { dg-final { cleanup-tree-dump "vect" } } */
276+
277
278=== added file 'gcc/testsuite/gcc.dg/vect/vect-over-widen-3.c'
279--- old/gcc/testsuite/gcc.dg/vect/vect-over-widen-3.c 1970-01-01 00:00:00 +0000
280+++ new/gcc/testsuite/gcc.dg/vect/vect-over-widen-3.c 2011-09-05 06:23:37 +0000
281@@ -0,0 +1,64 @@
282+/* { dg-require-effective-target vect_int } */
283+/* { dg-require-effective-target vect_shift } */
284+
285+#include <stdlib.h>
286+#include <stdarg.h>
287+#include "tree-vect.h"
288+
289+#define N 64
290+
291+/* Modified rgb to rgb conversion from FFmpeg. */
292+__attribute__ ((noinline)) void
293+foo (unsigned char *src, unsigned char *dst)
294+{
295+ unsigned char *s = src;
296+ unsigned short *d = (unsigned short *)dst;
297+ int i;
298+
299+ for (i = 0; i < N/4; i++)
300+ {
301+ const int b = *s++;
302+ const int g = *s++;
303+ const int r = *s++;
304+ const int a = *s++;
305+ *d = ((b>>3) | ((g&0xFFC)<<3) | ((r+0xF8)>>8) | (a<<9));
306+ d++;
307+ }
308+
309+ s = src;
310+ d = (unsigned short *)dst;
311+ for (i = 0; i < N/4; i++)
312+ {
313+ const int b = *s++;
314+ const int g = *s++;
315+ const int r = *s++;
316+ const int a = *s++;
317+ if (*d != ((b>>3) | ((g&0xFFC)<<3) | ((r+0xF8)>>8) | (a<<9)))
318+ abort ();
319+ d++;
320+ }
321+}
322+
323+int main (void)
324+{
325+ int i;
326+ unsigned char in[N], out[N];
327+
328+ check_vect ();
329+
330+ for (i = 0; i < N; i++)
331+ {
332+ in[i] = i;
333+ out[i] = 255;
334+ __asm__ volatile ("");
335+ }
336+
337+ foo (in, out);
338+
339+ return 0;
340+}
341+
342+/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 1 "vect" } } */
343+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
344+/* { dg-final { cleanup-tree-dump "vect" } } */
345+
346
347=== added file 'gcc/testsuite/gcc.dg/vect/vect-over-widen-4.c'
348--- old/gcc/testsuite/gcc.dg/vect/vect-over-widen-4.c 1970-01-01 00:00:00 +0000
349+++ new/gcc/testsuite/gcc.dg/vect/vect-over-widen-4.c 2011-09-05 06:23:37 +0000
350@@ -0,0 +1,68 @@
351+/* { dg-require-effective-target vect_int } */
352+/* { dg-require-effective-target vect_shift } */
353+
354+#include <stdlib.h>
355+#include <stdarg.h>
356+#include "tree-vect.h"
357+
358+#define N 64
359+
360+/* Modified rgb to rgb conversion from FFmpeg. */
361+__attribute__ ((noinline)) int
362+foo (unsigned char *src, unsigned char *dst)
363+{
364+ unsigned char *s = src;
365+ unsigned short *d = (unsigned short *)dst, res;
366+ int i, result = 0;
367+
368+ for (i = 0; i < N/4; i++)
369+ {
370+ const int b = *s++;
371+ const int g = *s++;
372+ const int r = *s++;
373+ const int a = *s++;
374+ res = ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5));
375+ *d = res;
376+ result += res;
377+ d++;
378+ }
379+
380+ s = src;
381+ d = (unsigned short *)dst;
382+ for (i = 0; i < N/4; i++)
383+ {
384+ const int b = *s++;
385+ const int g = *s++;
386+ const int r = *s++;
387+ const int a = *s++;
388+ if (*d != ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5)))
389+ abort ();
390+ d++;
391+ }
392+
393+ return result;
394+}
395+
396+int main (void)
397+{
398+ int i;
399+ unsigned char in[N], out[N];
400+
401+ check_vect ();
402+
403+ for (i = 0; i < N; i++)
404+ {
405+ in[i] = i;
406+ out[i] = 255;
407+ __asm__ volatile ("");
408+ }
409+
410+ foo (in, out);
411+
412+ return 0;
413+}
414+
415+/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" } } */
416+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
417+/* { dg-final { cleanup-tree-dump "vect" } } */
418+
419
420=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp'
421--- old/gcc/testsuite/gcc.dg/vect/vect.exp 2011-05-05 15:43:31 +0000
422+++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2011-09-05 06:23:37 +0000
423@@ -245,6 +245,18 @@
424 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/no-tree-reassoc-bb-slp-*.\[cS\]]] \
425 "" $VECT_SLP_CFLAGS
426
427+# -fno-tree-fre
428+set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
429+lappend DEFAULT_VECTCFLAGS "-fno-tree-fre"
430+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/no-tree-fre-*.\[cS\]]] \
431+ "" $DEFAULT_VECTCFLAGS
432+
433+# -fno-tree-fre -fno-tree-pre
434+set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
435+lappend DEFAULT_VECTCFLAGS "-fno-tree-fre" "-fno-tree-pre"
436+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/no-fre-pre*.\[cS\]]] \
437+ "" $DEFAULT_VECTCFLAGS
438+
439 # Clean up.
440 set dg-do-what-default ${save-dg-do-what-default}
441
442
443=== modified file 'gcc/tree-vect-loop.c'
444--- old/gcc/tree-vect-loop.c 2011-07-11 11:02:55 +0000
445+++ new/gcc/tree-vect-loop.c 2011-09-05 06:23:37 +0000
446@@ -181,8 +181,8 @@
447 stmt_vec_info stmt_info;
448 int i;
449 HOST_WIDE_INT dummy;
450- gimple stmt, pattern_stmt = NULL;
451- bool analyze_pattern_stmt = false;
452+ gimple stmt, pattern_stmt = NULL, pattern_def_stmt = NULL;
453+ bool analyze_pattern_stmt = false, pattern_def = false;
454
455 if (vect_print_dump_info (REPORT_DETAILS))
456 fprintf (vect_dump, "=== vect_determine_vectorization_factor ===");
457@@ -297,6 +297,29 @@
458 || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
459 analyze_pattern_stmt = true;
460
461+ /* If a pattern statement has a def stmt, analyze it too. */
462+ if (is_pattern_stmt_p (stmt_info)
463+ && (pattern_def_stmt = STMT_VINFO_PATTERN_DEF_STMT (stmt_info))
464+ && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_def_stmt))
465+ || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_def_stmt))))
466+ {
467+ if (pattern_def)
468+ pattern_def = false;
469+ else
470+ {
471+ if (vect_print_dump_info (REPORT_DETAILS))
472+ {
473+ fprintf (vect_dump, "==> examining pattern def stmt: ");
474+ print_gimple_stmt (vect_dump, pattern_def_stmt, 0,
475+ TDF_SLIM);
476+ }
477+
478+ pattern_def = true;
479+ stmt = pattern_def_stmt;
480+ stmt_info = vinfo_for_stmt (stmt);
481+ }
482+ }
483+
484 if (gimple_get_lhs (stmt) == NULL_TREE)
485 {
486 if (vect_print_dump_info (REPORT_UNVECTORIZED_LOCATIONS))
487@@ -401,7 +424,7 @@
488 || (nunits > vectorization_factor))
489 vectorization_factor = nunits;
490
491- if (!analyze_pattern_stmt)
492+ if (!analyze_pattern_stmt && !pattern_def)
493 gsi_next (&si);
494 }
495 }
496@@ -3985,7 +4008,7 @@
497 VEC (tree, heap) *vec_oprnds0 = NULL, *vec_oprnds1 = NULL, *vect_defs = NULL;
498 VEC (gimple, heap) *phis = NULL;
499 int vec_num;
500- tree def0, def1, tem;
501+ tree def0, def1, tem, op0, op1 = NULL_TREE;
502
503 if (nested_in_vect_loop_p (loop, stmt))
504 {
505@@ -4418,8 +4441,6 @@
506 /* Handle uses. */
507 if (j == 0)
508 {
509- tree op0, op1 = NULL_TREE;
510-
511 op0 = ops[!reduc_index];
512 if (op_type == ternary_op)
513 {
514@@ -4449,11 +4470,19 @@
515 {
516 if (!slp_node)
517 {
518- enum vect_def_type dt = vect_unknown_def_type; /* Dummy */
519- loop_vec_def0 = vect_get_vec_def_for_stmt_copy (dt, loop_vec_def0);
520+ enum vect_def_type dt;
521+ gimple dummy_stmt;
522+ tree dummy;
523+
524+ vect_is_simple_use (ops[!reduc_index], loop_vinfo, NULL,
525+ &dummy_stmt, &dummy, &dt);
526+ loop_vec_def0 = vect_get_vec_def_for_stmt_copy (dt,
527+ loop_vec_def0);
528 VEC_replace (tree, vec_oprnds0, 0, loop_vec_def0);
529 if (op_type == ternary_op)
530 {
531+ vect_is_simple_use (op1, loop_vinfo, NULL, &dummy_stmt,
532+ &dummy, &dt);
533 loop_vec_def1 = vect_get_vec_def_for_stmt_copy (dt,
534 loop_vec_def1);
535 VEC_replace (tree, vec_oprnds1, 0, loop_vec_def1);
536@@ -4758,8 +4787,8 @@
537 tree cond_expr = NULL_TREE;
538 gimple_seq cond_expr_stmt_list = NULL;
539 bool do_peeling_for_loop_bound;
540- gimple stmt, pattern_stmt;
541- bool transform_pattern_stmt = false;
542+ gimple stmt, pattern_stmt, pattern_def_stmt;
543+ bool transform_pattern_stmt = false, pattern_def = false;
544
545 if (vect_print_dump_info (REPORT_DETAILS))
546 fprintf (vect_dump, "=== vec_transform_loop ===");
547@@ -4903,6 +4932,30 @@
548 || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
549 transform_pattern_stmt = true;
550
551+ /* If pattern statement has a def stmt, vectorize it too. */
552+ if (is_pattern_stmt_p (stmt_info)
553+ && (pattern_def_stmt = STMT_VINFO_PATTERN_DEF_STMT (stmt_info))
554+ && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_def_stmt))
555+ || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_def_stmt))))
556+ {
557+ if (pattern_def)
558+ pattern_def = false;
559+ else
560+ {
561+ if (vect_print_dump_info (REPORT_DETAILS))
562+ {
563+ fprintf (vect_dump, "==> vectorizing pattern def"
564+ " stmt: ");
565+ print_gimple_stmt (vect_dump, pattern_def_stmt, 0,
566+ TDF_SLIM);
567+ }
568+
569+ pattern_def = true;
570+ stmt = pattern_def_stmt;
571+ stmt_info = vinfo_for_stmt (stmt);
572+ }
573+ }
574+
575 gcc_assert (STMT_VINFO_VECTYPE (stmt_info));
576 nunits = (unsigned int) TYPE_VECTOR_SUBPARTS (
577 STMT_VINFO_VECTYPE (stmt_info));
578@@ -4930,7 +4983,7 @@
579 /* Hybrid SLP stmts must be vectorized in addition to SLP. */
580 if (!vinfo_for_stmt (stmt) || PURE_SLP_STMT (stmt_info))
581 {
582- if (!transform_pattern_stmt)
583+ if (!transform_pattern_stmt && !pattern_def)
584 gsi_next (&si);
585 continue;
586 }
587@@ -4962,7 +5015,7 @@
588 }
589 }
590
591- if (!transform_pattern_stmt)
592+ if (!transform_pattern_stmt && !pattern_def)
593 gsi_next (&si);
594 } /* stmts in BB */
595 } /* BBs in loop */
596
597=== modified file 'gcc/tree-vect-patterns.c'
598--- old/gcc/tree-vect-patterns.c 2011-07-06 12:04:10 +0000
599+++ new/gcc/tree-vect-patterns.c 2011-09-05 06:23:37 +0000
600@@ -46,11 +46,14 @@
601 static gimple vect_recog_dot_prod_pattern (VEC (gimple, heap) **, tree *,
602 tree *);
603 static gimple vect_recog_pow_pattern (VEC (gimple, heap) **, tree *, tree *);
604+static gimple vect_recog_over_widening_pattern (VEC (gimple, heap) **, tree *,
605+ tree *);
606 static vect_recog_func_ptr vect_vect_recog_func_ptrs[NUM_PATTERNS] = {
607 vect_recog_widen_mult_pattern,
608 vect_recog_widen_sum_pattern,
609 vect_recog_dot_prod_pattern,
610- vect_recog_pow_pattern};
611+ vect_recog_pow_pattern,
612+ vect_recog_over_widening_pattern};
613
614
615 /* Function widened_name_p
616@@ -339,12 +342,14 @@
617 replace a_T = (TYPE) a_t; with a_it - (interm_type) a_t; */
618
619 static bool
620-vect_handle_widen_mult_by_const (tree const_oprnd, tree *oprnd,
621+vect_handle_widen_mult_by_const (gimple stmt, tree const_oprnd, tree *oprnd,
622 VEC (gimple, heap) **stmts, tree type,
623 tree *half_type, gimple def_stmt)
624 {
625 tree new_type, new_oprnd, tmp;
626 gimple new_stmt;
627+ loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
628+ struct loop *loop = LOOP_VINFO_LOOP (loop_info);
629
630 if (int_fits_type_p (const_oprnd, *half_type))
631 {
632@@ -354,6 +359,8 @@
633 }
634
635 if (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 4)
636+ || !gimple_bb (def_stmt)
637+ || !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
638 || !vinfo_for_stmt (def_stmt))
639 return false;
640
641@@ -522,7 +529,8 @@
642 {
643 if (TREE_CODE (oprnd0) == INTEGER_CST
644 && TREE_CODE (half_type1) == INTEGER_TYPE
645- && vect_handle_widen_mult_by_const (oprnd0, &oprnd1, stmts, type,
646+ && vect_handle_widen_mult_by_const (last_stmt, oprnd0, &oprnd1,
647+ stmts, type,
648 &half_type1, def_stmt1))
649 half_type0 = half_type1;
650 else
651@@ -532,7 +540,8 @@
652 {
653 if (TREE_CODE (oprnd1) == INTEGER_CST
654 && TREE_CODE (half_type0) == INTEGER_TYPE
655- && vect_handle_widen_mult_by_const (oprnd1, &oprnd0, stmts, type,
656+ && vect_handle_widen_mult_by_const (last_stmt, oprnd1, &oprnd0,
657+ stmts, type,
658 &half_type0, def_stmt0))
659 half_type1 = half_type0;
660 else
661@@ -826,6 +835,424 @@
662 }
663
664
665+/* Return TRUE if the operation in STMT can be performed on a smaller type.
666+
667+ Input:
668+ STMT - a statement to check.
669+ DEF - we support operations with two operands, one of which is constant.
670+ The other operand can be defined by a demotion operation, or by a
671+ previous statement in a sequence of over-promoted operations. In the
672+ later case DEF is used to replace that operand. (It is defined by a
673+ pattern statement we created for the previous statement in the
674+ sequence).
675+
676+ Input/output:
677+ NEW_TYPE - Output: a smaller type that we are trying to use. Input: if not
678+ NULL, it's the type of DEF.
679+ STMTS - additional pattern statements. If a pattern statement (type
680+ conversion) is created in this function, its original statement is
681+ added to STMTS.
682+
683+ Output:
684+ OP0, OP1 - if the operation fits a smaller type, OP0 and OP1 are the new
685+ operands to use in the new pattern statement for STMT (will be created
686+ in vect_recog_over_widening_pattern ()).
687+ NEW_DEF_STMT - in case DEF has to be promoted, we create two pattern
688+ statements for STMT: the first one is a type promotion and the second
689+ one is the operation itself. We return the type promotion statement
690+ in NEW_DEF_STMT and further store it in STMT_VINFO_PATTERN_DEF_STMT of
691+ the second pattern statement. */
692+
693+static bool
694+vect_operation_fits_smaller_type (gimple stmt, tree def, tree *new_type,
695+ tree *op0, tree *op1, gimple *new_def_stmt,
696+ VEC (gimple, heap) **stmts)
697+{
698+ enum tree_code code;
699+ tree const_oprnd, oprnd;
700+ tree interm_type = NULL_TREE, half_type, tmp, new_oprnd, type;
701+ gimple def_stmt, new_stmt;
702+ bool first = false;
703+ loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
704+ struct loop *loop = LOOP_VINFO_LOOP (loop_info);
705+
706+ *new_def_stmt = NULL;
707+
708+ if (!is_gimple_assign (stmt))
709+ return false;
710+
711+ code = gimple_assign_rhs_code (stmt);
712+ if (code != LSHIFT_EXPR && code != RSHIFT_EXPR
713+ && code != BIT_IOR_EXPR && code != BIT_XOR_EXPR && code != BIT_AND_EXPR)
714+ return false;
715+
716+ oprnd = gimple_assign_rhs1 (stmt);
717+ const_oprnd = gimple_assign_rhs2 (stmt);
718+ type = gimple_expr_type (stmt);
719+
720+ if (TREE_CODE (oprnd) != SSA_NAME
721+ || TREE_CODE (const_oprnd) != INTEGER_CST)
722+ return false;
723+
724+ /* If we are in the middle of a sequence, we use DEF from a previous
725+ statement. Otherwise, OPRND has to be a result of type promotion. */
726+ if (*new_type)
727+ {
728+ half_type = *new_type;
729+ oprnd = def;
730+ }
731+ else
732+ {
733+ first = true;
734+ if (!widened_name_p (oprnd, stmt, &half_type, &def_stmt, false)
735+ || !gimple_bb (def_stmt)
736+ || !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
737+ || !vinfo_for_stmt (def_stmt))
738+ return false;
739+ }
740+
741+ /* Can we perform the operation on a smaller type? */
742+ switch (code)
743+ {
744+ case BIT_IOR_EXPR:
745+ case BIT_XOR_EXPR:
746+ case BIT_AND_EXPR:
747+ if (!int_fits_type_p (const_oprnd, half_type))
748+ {
749+ /* HALF_TYPE is not enough. Try a bigger type if possible. */
750+ if (TYPE_PRECISION (type) < (TYPE_PRECISION (half_type) * 4))
751+ return false;
752+
753+ interm_type = build_nonstandard_integer_type (
754+ TYPE_PRECISION (half_type) * 2, TYPE_UNSIGNED (type));
755+ if (!int_fits_type_p (const_oprnd, interm_type))
756+ return false;
757+ }
758+
759+ break;
760+
761+ case LSHIFT_EXPR:
762+ /* Try intermediate type - HALF_TYPE is not enough for sure. */
763+ if (TYPE_PRECISION (type) < (TYPE_PRECISION (half_type) * 4))
764+ return false;
765+
766+ /* Check that HALF_TYPE size + shift amount <= INTERM_TYPE size.
767+ (e.g., if the original value was char, the shift amount is at most 8
768+ if we want to use short). */
769+ if (compare_tree_int (const_oprnd, TYPE_PRECISION (half_type)) == 1)
770+ return false;
771+
772+ interm_type = build_nonstandard_integer_type (
773+ TYPE_PRECISION (half_type) * 2, TYPE_UNSIGNED (type));
774+
775+ if (!vect_supportable_shift (code, interm_type))
776+ return false;
777+
778+ break;
779+
780+ case RSHIFT_EXPR:
781+ if (vect_supportable_shift (code, half_type))
782+ break;
783+
784+ /* Try intermediate type - HALF_TYPE is not supported. */
785+ if (TYPE_PRECISION (type) < (TYPE_PRECISION (half_type) * 4))
786+ return false;
787+
788+ interm_type = build_nonstandard_integer_type (
789+ TYPE_PRECISION (half_type) * 2, TYPE_UNSIGNED (type));
790+
791+ if (!vect_supportable_shift (code, interm_type))
792+ return false;
793+
794+ break;
795+
796+ default:
797+ gcc_unreachable ();
798+ }
799+
800+ /* There are four possible cases:
801+ 1. OPRND is defined by a type promotion (in that case FIRST is TRUE, it's
802+ the first statement in the sequence)
803+ a. The original, HALF_TYPE, is not enough - we replace the promotion
804+ from HALF_TYPE to TYPE with a promotion to INTERM_TYPE.
805+ b. HALF_TYPE is sufficient, OPRND is set as the RHS of the original
806+ promotion.
807+ 2. OPRND is defined by a pattern statement we created.
808+ a. Its type is not sufficient for the operation, we create a new stmt:
809+ a type conversion for OPRND from HALF_TYPE to INTERM_TYPE. We store
810+ this statement in NEW_DEF_STMT, and it is later put in
811+ STMT_VINFO_PATTERN_DEF_STMT of the pattern statement for STMT.
812+ b. OPRND is good to use in the new statement. */
813+ if (first)
814+ {
815+ if (interm_type)
816+ {
817+ /* Replace the original type conversion HALF_TYPE->TYPE with
818+ HALF_TYPE->INTERM_TYPE. */
819+ if (STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)))
820+ {
821+ new_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt));
822+ /* Check if the already created pattern stmt is what we need. */
823+ if (!is_gimple_assign (new_stmt)
824+ || gimple_assign_rhs_code (new_stmt) != NOP_EXPR
825+ || TREE_TYPE (gimple_assign_lhs (new_stmt)) != interm_type)
826+ return false;
827+
828+ oprnd = gimple_assign_lhs (new_stmt);
829+ }
830+ else
831+ {
832+ /* Create NEW_OPRND = (INTERM_TYPE) OPRND. */
833+ oprnd = gimple_assign_rhs1 (def_stmt);
834+ tmp = create_tmp_reg (interm_type, NULL);
835+ add_referenced_var (tmp);
836+ new_oprnd = make_ssa_name (tmp, NULL);
837+ new_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd,
838+ oprnd, NULL_TREE);
839+ SSA_NAME_DEF_STMT (new_oprnd) = new_stmt;
840+ STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)) = new_stmt;
841+ VEC_safe_push (gimple, heap, *stmts, def_stmt);
842+ oprnd = new_oprnd;
843+ }
844+ }
845+ else
846+ {
847+ /* Retrieve the operand before the type promotion. */
848+ oprnd = gimple_assign_rhs1 (def_stmt);
849+ }
850+ }
851+ else
852+ {
853+ if (interm_type)
854+ {
855+ /* Create a type conversion HALF_TYPE->INTERM_TYPE. */
856+ tmp = create_tmp_reg (interm_type, NULL);
857+ add_referenced_var (tmp);
858+ new_oprnd = make_ssa_name (tmp, NULL);
859+ new_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd,
860+ oprnd, NULL_TREE);
861+ SSA_NAME_DEF_STMT (new_oprnd) = new_stmt;
862+ oprnd = new_oprnd;
863+ *new_def_stmt = new_stmt;
864+ }
865+
866+ /* Otherwise, OPRND is already set. */
867+ }
868+
869+ if (interm_type)
870+ *new_type = interm_type;
871+ else
872+ *new_type = half_type;
873+
874+ *op0 = oprnd;
875+ *op1 = fold_convert (*new_type, const_oprnd);
876+
877+ return true;
878+}
879+
880+
881+/* Try to find a statement or a sequence of statements that can be performed
882+ on a smaller type:
883+
884+ type x_t;
885+ TYPE x_T, res0_T, res1_T;
886+ loop:
887+ S1 x_t = *p;
888+ S2 x_T = (TYPE) x_t;
889+ S3 res0_T = op (x_T, C0);
890+ S4 res1_T = op (res0_T, C1);
891+ S5 ... = () res1_T; - type demotion
892+
893+ where type 'TYPE' is at least double the size of type 'type', C0 and C1 are
894+ constants.
895+ Check if S3 and S4 can be done on a smaller type than 'TYPE', it can either
896+ be 'type' or some intermediate type. For now, we expect S5 to be a type
897+ demotion operation. We also check that S3 and S4 have only one use.
898+.
899+
900+*/
901+static gimple
902+vect_recog_over_widening_pattern (VEC (gimple, heap) **stmts,
903+ tree *type_in, tree *type_out)
904+{
905+ gimple stmt = VEC_pop (gimple, *stmts);
906+ gimple pattern_stmt = NULL, new_def_stmt, prev_stmt = NULL, use_stmt = NULL;
907+ tree op0, op1, vectype = NULL_TREE, lhs, use_lhs, use_type;
908+ imm_use_iterator imm_iter;
909+ use_operand_p use_p;
910+ int nuses = 0;
911+ tree var = NULL_TREE, new_type = NULL_TREE, tmp, new_oprnd;
912+ bool first;
913+ struct loop *loop = (gimple_bb (stmt))->loop_father;
914+
915+ first = true;
916+ while (1)
917+ {
918+ if (!vinfo_for_stmt (stmt)
919+ || STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (stmt)))
920+ return NULL;
921+
922+ new_def_stmt = NULL;
923+ if (!vect_operation_fits_smaller_type (stmt, var, &new_type,
924+ &op0, &op1, &new_def_stmt,
925+ stmts))
926+ {
927+ if (first)
928+ return NULL;
929+ else
930+ break;
931+ }
932+
933+ /* STMT can be performed on a smaller type. Check its uses. */
934+ lhs = gimple_assign_lhs (stmt);
935+ nuses = 0;
936+ FOR_EACH_IMM_USE_FAST (use_p, imm_iter, lhs)
937+ {
938+ if (is_gimple_debug (USE_STMT (use_p)))
939+ continue;
940+ use_stmt = USE_STMT (use_p);
941+ nuses++;
942+ }
943+
944+ if (nuses != 1 || !is_gimple_assign (use_stmt)
945+ || !gimple_bb (use_stmt)
946+ || !flow_bb_inside_loop_p (loop, gimple_bb (use_stmt)))
947+ return NULL;
948+
949+ /* Create pattern statement for STMT. */
950+ vectype = get_vectype_for_scalar_type (new_type);
951+ if (!vectype)
952+ return NULL;
953+
954+ /* We want to collect all the statements for which we create pattern
955+ statetments, except for the case when the last statement in the
956+ sequence doesn't have a corresponding pattern statement. In such
957+ case we associate the last pattern statement with the last statement
958+ in the sequence. Therefore, we only add an original statetement to
959+ the list if we know that it is not the last. */
960+ if (prev_stmt)
961+ VEC_safe_push (gimple, heap, *stmts, prev_stmt);
962+
963+ var = vect_recog_temp_ssa_var (new_type, NULL);
964+ pattern_stmt = gimple_build_assign_with_ops (
965+ gimple_assign_rhs_code (stmt), var, op0, op1);
966+ SSA_NAME_DEF_STMT (var) = pattern_stmt;
967+ STMT_VINFO_RELATED_STMT (vinfo_for_stmt (stmt)) = pattern_stmt;
968+ STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (stmt)) = new_def_stmt;
969+
970+ if (vect_print_dump_info (REPORT_DETAILS))
971+ {
972+ fprintf (vect_dump, "created pattern stmt: ");
973+ print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
974+ }
975+
976+ prev_stmt = stmt;
977+ stmt = use_stmt;
978+
979+ first = false;
980+ }
981+
982+ /* We got a sequence. We expect it to end with a type demotion operation.
983+ Otherwise, we quit (for now). There are three possible cases: the
984+ conversion is to NEW_TYPE (we don't do anything), the conversion is to
985+ a type bigger than NEW_TYPE and/or the signedness of USE_TYPE and
986+ NEW_TYPE differs (we create a new conversion statement). */
987+ if (CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (use_stmt)))
988+ {
989+ use_lhs = gimple_assign_lhs (use_stmt);
990+ use_type = TREE_TYPE (use_lhs);
991+ /* Support only type promotion or signedess change. */
992+ if (!INTEGRAL_TYPE_P (use_type)
993+ || TYPE_PRECISION (new_type) > TYPE_PRECISION (use_type))
994+ return NULL;
995+
996+ if (TYPE_UNSIGNED (new_type) != TYPE_UNSIGNED (use_type)
997+ || TYPE_PRECISION (new_type) != TYPE_PRECISION (use_type))
998+ {
999+ /* Create NEW_TYPE->USE_TYPE conversion. */
1000+ tmp = create_tmp_reg (use_type, NULL);
1001+ add_referenced_var (tmp);
1002+ new_oprnd = make_ssa_name (tmp, NULL);
1003+ pattern_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd,
1004+ var, NULL_TREE);
1005+ SSA_NAME_DEF_STMT (new_oprnd) = pattern_stmt;
1006+ STMT_VINFO_RELATED_STMT (vinfo_for_stmt (use_stmt)) = pattern_stmt;
1007+
1008+ *type_in = get_vectype_for_scalar_type (new_type);
1009+ *type_out = get_vectype_for_scalar_type (use_type);
1010+
1011+ /* We created a pattern statement for the last statement in the
1012+ sequence, so we don't need to associate it with the pattern
1013+ statement created for PREV_STMT. Therefore, we add PREV_STMT
1014+ to the list in order to mark it later in vect_pattern_recog_1. */
1015+ if (prev_stmt)
1016+ VEC_safe_push (gimple, heap, *stmts, prev_stmt);
1017+ }
1018+ else
1019+ {
1020+ if (prev_stmt)
1021+ STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (use_stmt))
1022+ = STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (prev_stmt));
1023+
1024+ *type_in = vectype;
1025+ *type_out = NULL_TREE;
1026+ }
1027+
1028+ VEC_safe_push (gimple, heap, *stmts, use_stmt);
1029+ }
1030+ else
1031+ /* TODO: support general case, create a conversion to the correct type. */
1032+ return NULL;
1033+
1034+ /* Pattern detected. */
1035+ if (vect_print_dump_info (REPORT_DETAILS))
1036+ {
1037+ fprintf (vect_dump, "vect_recog_over_widening_pattern: detected: ");
1038+ print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
1039+ }
1040+
1041+ return pattern_stmt;
1042+}
1043+
1044+
1045+/* Mark statements that are involved in a pattern. */
1046+
1047+static inline void
1048+vect_mark_pattern_stmts (gimple orig_stmt, gimple pattern_stmt,
1049+ tree pattern_vectype)
1050+{
1051+ stmt_vec_info pattern_stmt_info, def_stmt_info;
1052+ stmt_vec_info orig_stmt_info = vinfo_for_stmt (orig_stmt);
1053+ loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (orig_stmt_info);
1054+ gimple def_stmt;
1055+
1056+ set_vinfo_for_stmt (pattern_stmt,
1057+ new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
1058+ gimple_set_bb (pattern_stmt, gimple_bb (orig_stmt));
1059+ pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
1060+
1061+ STMT_VINFO_RELATED_STMT (pattern_stmt_info) = orig_stmt;
1062+ STMT_VINFO_DEF_TYPE (pattern_stmt_info)
1063+ = STMT_VINFO_DEF_TYPE (orig_stmt_info);
1064+ STMT_VINFO_VECTYPE (pattern_stmt_info) = pattern_vectype;
1065+ STMT_VINFO_IN_PATTERN_P (orig_stmt_info) = true;
1066+ STMT_VINFO_RELATED_STMT (orig_stmt_info) = pattern_stmt;
1067+ STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info)
1068+ = STMT_VINFO_PATTERN_DEF_STMT (orig_stmt_info);
1069+ if (STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info))
1070+ {
1071+ def_stmt = STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info);
1072+ set_vinfo_for_stmt (def_stmt,
1073+ new_stmt_vec_info (def_stmt, loop_vinfo, NULL));
1074+ gimple_set_bb (def_stmt, gimple_bb (orig_stmt));
1075+ def_stmt_info = vinfo_for_stmt (def_stmt);
1076+ STMT_VINFO_RELATED_STMT (def_stmt_info) = orig_stmt;
1077+ STMT_VINFO_DEF_TYPE (def_stmt_info)
1078+ = STMT_VINFO_DEF_TYPE (orig_stmt_info);
1079+ STMT_VINFO_VECTYPE (def_stmt_info) = pattern_vectype;
1080+ }
1081+}
1082+
1083 /* Function vect_pattern_recog_1
1084
1085 Input:
1086@@ -855,7 +1282,6 @@
1087 {
1088 gimple stmt = gsi_stmt (si), pattern_stmt;
1089 stmt_vec_info stmt_info;
1090- stmt_vec_info pattern_stmt_info;
1091 loop_vec_info loop_vinfo;
1092 tree pattern_vectype;
1093 tree type_in, type_out;
1094@@ -923,16 +1349,7 @@
1095 }
1096
1097 /* Mark the stmts that are involved in the pattern. */
1098- set_vinfo_for_stmt (pattern_stmt,
1099- new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
1100- gimple_set_bb (pattern_stmt, gimple_bb (stmt));
1101- pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
1102-
1103- STMT_VINFO_RELATED_STMT (pattern_stmt_info) = stmt;
1104- STMT_VINFO_DEF_TYPE (pattern_stmt_info) = STMT_VINFO_DEF_TYPE (stmt_info);
1105- STMT_VINFO_VECTYPE (pattern_stmt_info) = pattern_vectype;
1106- STMT_VINFO_IN_PATTERN_P (stmt_info) = true;
1107- STMT_VINFO_RELATED_STMT (stmt_info) = pattern_stmt;
1108+ vect_mark_pattern_stmts (stmt, pattern_stmt, pattern_vectype);
1109
1110 /* Patterns cannot be vectorized using SLP, because they change the order of
1111 computation. */
1112@@ -940,9 +1357,9 @@
1113 if (next == stmt)
1114 VEC_ordered_remove (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i);
1115
1116- /* In case of widen-mult by a constant, it is possible that an additional
1117- pattern stmt is created and inserted in STMTS_TO_REPLACE. We create a
1118- stmt_info for it, and mark the relevant statements. */
1119+ /* It is possible that additional pattern stmts are created and inserted in
1120+ STMTS_TO_REPLACE. We create a stmt_info for each of them, and mark the
1121+ relevant statements. */
1122 for (i = 0; VEC_iterate (gimple, stmts_to_replace, i, stmt)
1123 && (unsigned) i < (VEC_length (gimple, stmts_to_replace) - 1);
1124 i++)
1125@@ -955,16 +1372,7 @@
1126 print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
1127 }
1128
1129- set_vinfo_for_stmt (pattern_stmt,
1130- new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
1131- gimple_set_bb (pattern_stmt, gimple_bb (stmt));
1132- pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
1133-
1134- STMT_VINFO_RELATED_STMT (pattern_stmt_info) = stmt;
1135- STMT_VINFO_DEF_TYPE (pattern_stmt_info)
1136- = STMT_VINFO_DEF_TYPE (stmt_info);
1137- STMT_VINFO_VECTYPE (pattern_stmt_info) = STMT_VINFO_VECTYPE (stmt_info);
1138- STMT_VINFO_IN_PATTERN_P (stmt_info) = true;
1139+ vect_mark_pattern_stmts (stmt, pattern_stmt, NULL_TREE);
1140 }
1141
1142 VEC_free (gimple, heap, stmts_to_replace);
1143
1144=== modified file 'gcc/tree-vect-stmts.c'
1145--- old/gcc/tree-vect-stmts.c 2011-07-06 12:04:10 +0000
1146+++ new/gcc/tree-vect-stmts.c 2011-09-05 06:23:37 +0000
1147@@ -2246,6 +2246,42 @@
1148 }
1149
1150
1151+/* Return TRUE if CODE (a shift operation) is supported for SCALAR_TYPE
1152+ either as shift by a scalar or by a vector. */
1153+
1154+bool
1155+vect_supportable_shift (enum tree_code code, tree scalar_type)
1156+{
1157+
1158+ enum machine_mode vec_mode;
1159+ optab optab;
1160+ int icode;
1161+ tree vectype;
1162+
1163+ vectype = get_vectype_for_scalar_type (scalar_type);
1164+ if (!vectype)
1165+ return false;
1166+
1167+ optab = optab_for_tree_code (code, vectype, optab_scalar);
1168+ if (!optab
1169+ || optab_handler (optab, TYPE_MODE (vectype)) == CODE_FOR_nothing)
1170+ {
1171+ optab = optab_for_tree_code (code, vectype, optab_vector);
1172+ if (!optab
1173+ || (optab_handler (optab, TYPE_MODE (vectype))
1174+ == CODE_FOR_nothing))
1175+ return false;
1176+ }
1177+
1178+ vec_mode = TYPE_MODE (vectype);
1179+ icode = (int) optab_handler (optab, vec_mode);
1180+ if (icode == CODE_FOR_nothing)
1181+ return false;
1182+
1183+ return true;
1184+}
1185+
1186+
1187 /* Function vectorizable_shift.
1188
1189 Check if STMT performs a shift operation that can be vectorized.
1190@@ -4946,7 +4982,7 @@
1191 enum vect_relevant relevance = STMT_VINFO_RELEVANT (stmt_info);
1192 bool ok;
1193 tree scalar_type, vectype;
1194- gimple pattern_stmt;
1195+ gimple pattern_stmt, pattern_def_stmt;
1196
1197 if (vect_print_dump_info (REPORT_DETAILS))
1198 {
1199@@ -5016,6 +5052,23 @@
1200 return false;
1201 }
1202
1203+ if (is_pattern_stmt_p (stmt_info)
1204+ && (pattern_def_stmt = STMT_VINFO_PATTERN_DEF_STMT (stmt_info))
1205+ && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_def_stmt))
1206+ || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_def_stmt))))
1207+ {
1208+ /* Analyze def stmt of STMT if it's a pattern stmt. */
1209+ if (vect_print_dump_info (REPORT_DETAILS))
1210+ {
1211+ fprintf (vect_dump, "==> examining pattern def statement: ");
1212+ print_gimple_stmt (vect_dump, pattern_def_stmt, 0, TDF_SLIM);
1213+ }
1214+
1215+ if (!vect_analyze_stmt (pattern_def_stmt, need_to_vectorize, node))
1216+ return false;
1217+ }
1218+
1219+
1220 switch (STMT_VINFO_DEF_TYPE (stmt_info))
1221 {
1222 case vect_internal_def:
1223@@ -5336,6 +5389,7 @@
1224 STMT_VINFO_VECTORIZABLE (res) = true;
1225 STMT_VINFO_IN_PATTERN_P (res) = false;
1226 STMT_VINFO_RELATED_STMT (res) = NULL;
1227+ STMT_VINFO_PATTERN_DEF_STMT (res) = NULL;
1228 STMT_VINFO_DATA_REF (res) = NULL;
1229
1230 STMT_VINFO_DR_BASE_ADDRESS (res) = NULL;
1231
1232=== modified file 'gcc/tree-vectorizer.h'
1233--- old/gcc/tree-vectorizer.h 2011-07-11 11:02:55 +0000
1234+++ new/gcc/tree-vectorizer.h 2011-09-05 06:23:37 +0000
1235@@ -464,6 +464,9 @@
1236 pattern). */
1237 gimple related_stmt;
1238
1239+ /* Used to keep a def stmt of a pattern stmt if such exists. */
1240+ gimple pattern_def_stmt;
1241+
1242 /* List of datarefs that are known to have the same alignment as the dataref
1243 of this stmt. */
1244 VEC(dr_p,heap) *same_align_refs;
1245@@ -531,6 +534,7 @@
1246
1247 #define STMT_VINFO_IN_PATTERN_P(S) (S)->in_pattern_p
1248 #define STMT_VINFO_RELATED_STMT(S) (S)->related_stmt
1249+#define STMT_VINFO_PATTERN_DEF_STMT(S) (S)->pattern_def_stmt
1250 #define STMT_VINFO_SAME_ALIGN_REFS(S) (S)->same_align_refs
1251 #define STMT_VINFO_DEF_TYPE(S) (S)->def_type
1252 #define STMT_VINFO_DR_GROUP_FIRST_DR(S) (S)->first_dr
1253@@ -814,6 +818,7 @@
1254 extern void vect_get_load_cost (struct data_reference *, int, bool,
1255 unsigned int *, unsigned int *);
1256 extern void vect_get_store_cost (struct data_reference *, int, unsigned int *);
1257+extern bool vect_supportable_shift (enum tree_code, tree);
1258
1259 /* In tree-vect-data-refs.c. */
1260 extern bool vect_can_force_dr_alignment_p (const_tree, unsigned int);
1261@@ -891,7 +896,7 @@
1262 Additional pattern recognition functions can (and will) be added
1263 in the future. */
1264 typedef gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
1265-#define NUM_PATTERNS 4
1266+#define NUM_PATTERNS 5
1267 void vect_pattern_recog (loop_vec_info);
1268
1269 /* In tree-vectorizer.c. */
1270
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106802.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106802.patch
deleted file mode 100644
index ade96fdd1..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106802.patch
+++ /dev/null
@@ -1,948 +0,0 @@
12011-09-12 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF mainline:
4
5 2011-08-30 Andrew Stubbs <ams@codesourcery.com>
6
7 gcc/
8 * config/arm/arm.c (optimal_immediate_sequence_1): Make b1, b2,
9 b3 and b4 unsigned.
10
11 2011-08-30 Andrew Stubbs <ams@codesourcery.com>
12
13 gcc/
14 * config/arm/arm.c (arm_gen_constant): Set can_negate correctly
15 when code is SET.
16
17 2011-08-26 Andrew Stubbs <ams@codesourcery.com>
18
19 gcc/
20 * config/arm/arm.c (struct four_ints): New type.
21 (count_insns_for_constant): Delete function.
22 (find_best_start): Delete function.
23 (optimal_immediate_sequence): New function.
24 (optimal_immediate_sequence_1): New function.
25 (arm_gen_constant): Move constant splitting code to
26 optimal_immediate_sequence.
27 Rewrite constant negation/invertion code.
28
29 gcc/testsuite/
30 * gcc.target/arm/thumb2-replicated-constant1.c: New file.
31 * gcc.target/arm/thumb2-replicated-constant2.c: New file.
32 * gcc.target/arm/thumb2-replicated-constant3.c: New file.
33 * gcc.target/arm/thumb2-replicated-constant4.c: New file.
34
35 2011-08-26 Andrew Stubbs <ams@codesourcery.com>
36
37 gcc/
38 * config/arm/arm-protos.h (const_ok_for_op): Add prototype.
39 * config/arm/arm.c (const_ok_for_op): Add support for addw/subw.
40 Remove prototype. Remove static function type.
41 * config/arm/arm.md (*arm_addsi3): Add addw/subw support.
42 Add arch attribute.
43 * config/arm/constraints.md (Pj, PJ): New constraints.
44
45 2011-04-20 Andrew Stubbs <ams@codesourcery.com>
46
47 gcc/
48 * config/arm/arm.c (arm_gen_constant): Move mowv support ....
49 (const_ok_for_op): ... to here.
50
51 2011-04-20 Andrew Stubbs <ams@codesourcery.com>
52
53 gcc/
54 * config/arm/arm.c (arm_gen_constant): Remove redundant can_invert.
55
56
57=== modified file 'gcc/config/arm/arm-protos.h'
58--- old/gcc/config/arm/arm-protos.h 2011-07-04 14:03:49 +0000
59+++ new/gcc/config/arm/arm-protos.h 2011-08-25 13:26:58 +0000
60@@ -46,6 +46,7 @@
61 extern bool arm_small_register_classes_for_mode_p (enum machine_mode);
62 extern int arm_hard_regno_mode_ok (unsigned int, enum machine_mode);
63 extern int const_ok_for_arm (HOST_WIDE_INT);
64+extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
65 extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int);
67 extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *);
68
69=== modified file 'gcc/config/arm/arm.c'
70--- old/gcc/config/arm/arm.c 2011-08-24 17:35:16 +0000
71+++ new/gcc/config/arm/arm.c 2011-09-06 12:57:56 +0000
72@@ -63,6 +63,11 @@
73
74 void (*arm_lang_output_object_attributes_hook)(void);
75
76+struct four_ints
77+{
78+ int i[4];
79+};
80+
81 /* Forward function declarations. */
82 static bool arm_needs_doubleword_align (enum machine_mode, const_tree);
83 static int arm_compute_static_chain_stack_bytes (void);
84@@ -81,7 +86,6 @@
85 static bool arm_legitimate_address_p (enum machine_mode, rtx, bool);
86 static int thumb_far_jump_used_p (void);
87 static bool thumb_force_lr_save (void);
88-static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
89 static rtx emit_sfm (int, int);
90 static unsigned arm_size_return_regs (void);
91 static bool arm_assemble_integer (rtx, unsigned int, int);
92@@ -129,7 +133,13 @@
93 static int arm_comp_type_attributes (const_tree, const_tree);
94 static void arm_set_default_type_attributes (tree);
95 static int arm_adjust_cost (rtx, rtx, rtx, int);
96-static int count_insns_for_constant (HOST_WIDE_INT, int);
97+static int optimal_immediate_sequence (enum rtx_code code,
98+ unsigned HOST_WIDE_INT val,
99+ struct four_ints *return_sequence);
100+static int optimal_immediate_sequence_1 (enum rtx_code code,
101+ unsigned HOST_WIDE_INT val,
102+ struct four_ints *return_sequence,
103+ int i);
104 static int arm_get_strip_length (int);
105 static bool arm_function_ok_for_sibcall (tree, tree);
106 static enum machine_mode arm_promote_function_mode (const_tree,
107@@ -2525,7 +2535,7 @@
108 }
109
110 /* Return true if I is a valid constant for the operation CODE. */
111-static int
112+int
113 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
114 {
115 if (const_ok_for_arm (i))
116@@ -2533,7 +2543,21 @@
117
118 switch (code)
119 {
120+ case SET:
121+ /* See if we can use movw. */
122+ if (arm_arch_thumb2 && (i & 0xffff0000) == 0)
123+ return 1;
124+ else
125+ return 0;
126+
127 case PLUS:
128+ /* See if we can use addw or subw. */
129+ if (TARGET_THUMB2
130+ && ((i & 0xfffff000) == 0
131+ || ((-i) & 0xfffff000) == 0))
132+ return 1;
133+ /* else fall through. */
134+
135 case COMPARE:
136 case EQ:
137 case NE:
138@@ -2649,68 +2673,41 @@
139 1);
140 }
141
142-/* Return the number of instructions required to synthesize the given
143- constant, if we start emitting them from bit-position I. */
144-static int
145-count_insns_for_constant (HOST_WIDE_INT remainder, int i)
146-{
147- HOST_WIDE_INT temp1;
148- int step_size = TARGET_ARM ? 2 : 1;
149- int num_insns = 0;
150-
151- gcc_assert (TARGET_ARM || i == 0);
152-
153- do
154- {
155- int end;
156-
157- if (i <= 0)
158- i += 32;
159- if (remainder & (((1 << step_size) - 1) << (i - step_size)))
160- {
161- end = i - 8;
162- if (end < 0)
163- end += 32;
164- temp1 = remainder & ((0x0ff << end)
165- | ((i < end) ? (0xff >> (32 - end)) : 0));
166- remainder &= ~temp1;
167- num_insns++;
168- i -= 8 - step_size;
169- }
170- i -= step_size;
171- } while (remainder);
172- return num_insns;
173-}
174-
175-static int
176-find_best_start (unsigned HOST_WIDE_INT remainder)
177+/* Return a sequence of integers, in RETURN_SEQUENCE that fit into
178+ ARM/THUMB2 immediates, and add up to VAL.
179+ Thr function return value gives the number of insns required. */
180+static int
181+optimal_immediate_sequence (enum rtx_code code, unsigned HOST_WIDE_INT val,
182+ struct four_ints *return_sequence)
183 {
184 int best_consecutive_zeros = 0;
185 int i;
186 int best_start = 0;
187+ int insns1, insns2;
188+ struct four_ints tmp_sequence;
189
190 /* If we aren't targetting ARM, the best place to start is always at
191- the bottom. */
192- if (! TARGET_ARM)
193- return 0;
194-
195- for (i = 0; i < 32; i += 2)
196+ the bottom, otherwise look more closely. */
197+ if (TARGET_ARM)
198 {
199- int consecutive_zeros = 0;
200-
201- if (!(remainder & (3 << i)))
202+ for (i = 0; i < 32; i += 2)
203 {
204- while ((i < 32) && !(remainder & (3 << i)))
205- {
206- consecutive_zeros += 2;
207- i += 2;
208- }
209- if (consecutive_zeros > best_consecutive_zeros)
210- {
211- best_consecutive_zeros = consecutive_zeros;
212- best_start = i - consecutive_zeros;
213- }
214- i -= 2;
215+ int consecutive_zeros = 0;
216+
217+ if (!(val & (3 << i)))
218+ {
219+ while ((i < 32) && !(val & (3 << i)))
220+ {
221+ consecutive_zeros += 2;
222+ i += 2;
223+ }
224+ if (consecutive_zeros > best_consecutive_zeros)
225+ {
226+ best_consecutive_zeros = consecutive_zeros;
227+ best_start = i - consecutive_zeros;
228+ }
229+ i -= 2;
230+ }
231 }
232 }
233
234@@ -2737,13 +2734,161 @@
235 the constant starting from `best_start', and also starting from
236 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
237 yield a shorter sequence, we may as well use zero. */
238+ insns1 = optimal_immediate_sequence_1 (code, val, return_sequence, best_start);
239 if (best_start != 0
240- && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
241- && (count_insns_for_constant (remainder, 0) <=
242- count_insns_for_constant (remainder, best_start)))
243- best_start = 0;
244-
245- return best_start;
246+ && ((((unsigned HOST_WIDE_INT) 1) << best_start) < val))
247+ {
248+ insns2 = optimal_immediate_sequence_1 (code, val, &tmp_sequence, 0);
249+ if (insns2 <= insns1)
250+ {
251+ *return_sequence = tmp_sequence;
252+ insns1 = insns2;
253+ }
254+ }
255+
256+ return insns1;
257+}
258+
259+/* As for optimal_immediate_sequence, but starting at bit-position I. */
260+static int
261+optimal_immediate_sequence_1 (enum rtx_code code, unsigned HOST_WIDE_INT val,
262+ struct four_ints *return_sequence, int i)
263+{
264+ int remainder = val & 0xffffffff;
265+ int insns = 0;
266+
267+ /* Try and find a way of doing the job in either two or three
268+ instructions.
269+
270+ In ARM mode we can use 8-bit constants, rotated to any 2-bit aligned
271+ location. We start at position I. This may be the MSB, or
272+ optimial_immediate_sequence may have positioned it at the largest block
273+ of zeros that are aligned on a 2-bit boundary. We then fill up the temps,
274+ wrapping around to the top of the word when we drop off the bottom.
275+ In the worst case this code should produce no more than four insns.
276+
277+ In Thumb2 mode, we can use 32/16-bit replicated constants, and 8-bit
278+ constants, shifted to any arbitrary location. We should always start
279+ at the MSB. */
280+ do
281+ {
282+ int end;
283+ unsigned int b1, b2, b3, b4;
284+ unsigned HOST_WIDE_INT result;
285+ int loc;
286+
287+ gcc_assert (insns < 4);
288+
289+ if (i <= 0)
290+ i += 32;
291+
292+ /* First, find the next normal 12/8-bit shifted/rotated immediate. */
293+ if (remainder & ((TARGET_ARM ? (3 << (i - 2)) : (1 << (i - 1)))))
294+ {
295+ loc = i;
296+ if (i <= 12 && TARGET_THUMB2 && code == PLUS)
297+ /* We can use addw/subw for the last 12 bits. */
298+ result = remainder;
299+ else
300+ {
301+ /* Use an 8-bit shifted/rotated immediate. */
302+ end = i - 8;
303+ if (end < 0)
304+ end += 32;
305+ result = remainder & ((0x0ff << end)
306+ | ((i < end) ? (0xff >> (32 - end))
307+ : 0));
308+ i -= 8;
309+ }
310+ }
311+ else
312+ {
313+ /* Arm allows rotates by a multiple of two. Thumb-2 allows
314+ arbitrary shifts. */
315+ i -= TARGET_ARM ? 2 : 1;
316+ continue;
317+ }
318+
319+ /* Next, see if we can do a better job with a thumb2 replicated
320+ constant.
321+
322+ We do it this way around to catch the cases like 0x01F001E0 where
323+ two 8-bit immediates would work, but a replicated constant would
324+ make it worse.
325+
326+ TODO: 16-bit constants that don't clear all the bits, but still win.
327+ TODO: Arithmetic splitting for set/add/sub, rather than bitwise. */
328+ if (TARGET_THUMB2)
329+ {
330+ b1 = (remainder & 0xff000000) >> 24;
331+ b2 = (remainder & 0x00ff0000) >> 16;
332+ b3 = (remainder & 0x0000ff00) >> 8;
333+ b4 = remainder & 0xff;
334+
335+ if (loc > 24)
336+ {
337+ /* The 8-bit immediate already found clears b1 (and maybe b2),
338+ but must leave b3 and b4 alone. */
339+
340+ /* First try to find a 32-bit replicated constant that clears
341+ almost everything. We can assume that we can't do it in one,
342+ or else we wouldn't be here. */
343+ unsigned int tmp = b1 & b2 & b3 & b4;
344+ unsigned int tmp2 = tmp + (tmp << 8) + (tmp << 16)
345+ + (tmp << 24);
346+ unsigned int matching_bytes = (tmp == b1) + (tmp == b2)
347+ + (tmp == b3) + (tmp == b4);
348+ if (tmp
349+ && (matching_bytes >= 3
350+ || (matching_bytes == 2
351+ && const_ok_for_op (remainder & ~tmp2, code))))
352+ {
353+ /* At least 3 of the bytes match, and the fourth has at
354+ least as many bits set, or two of the bytes match
355+ and it will only require one more insn to finish. */
356+ result = tmp2;
357+ i = tmp != b1 ? 32
358+ : tmp != b2 ? 24
359+ : tmp != b3 ? 16
360+ : 8;
361+ }
362+
363+ /* Second, try to find a 16-bit replicated constant that can
364+ leave three of the bytes clear. If b2 or b4 is already
365+ zero, then we can. If the 8-bit from above would not
366+ clear b2 anyway, then we still win. */
367+ else if (b1 == b3 && (!b2 || !b4
368+ || (remainder & 0x00ff0000 & ~result)))
369+ {
370+ result = remainder & 0xff00ff00;
371+ i = 24;
372+ }
373+ }
374+ else if (loc > 16)
375+ {
376+ /* The 8-bit immediate already found clears b2 (and maybe b3)
377+ and we don't get here unless b1 is alredy clear, but it will
378+ leave b4 unchanged. */
379+
380+ /* If we can clear b2 and b4 at once, then we win, since the
381+ 8-bits couldn't possibly reach that far. */
382+ if (b2 == b4)
383+ {
384+ result = remainder & 0x00ff00ff;
385+ i = 16;
386+ }
387+ }
388+ }
389+
390+ return_sequence->i[insns++] = result;
391+ remainder &= ~result;
392+
393+ if (code == SET || code == MINUS)
394+ code = PLUS;
395+ }
396+ while (remainder);
397+
398+ return insns;
399 }
400
401 /* Emit an instruction with the indicated PATTERN. If COND is
402@@ -2760,7 +2905,6 @@
403
404 /* As above, but extra parameter GENERATE which, if clear, suppresses
405 RTL generation. */
406-/* ??? This needs more work for thumb2. */
407
408 static int
409 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
410@@ -2772,15 +2916,15 @@
411 int final_invert = 0;
412 int can_negate_initial = 0;
413 int i;
414- int num_bits_set = 0;
415 int set_sign_bit_copies = 0;
416 int clear_sign_bit_copies = 0;
417 int clear_zero_bit_copies = 0;
418 int set_zero_bit_copies = 0;
419- int insns = 0;
420+ int insns = 0, neg_insns, inv_insns;
421 unsigned HOST_WIDE_INT temp1, temp2;
422 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
423- int step_size = TARGET_ARM ? 2 : 1;
424+ struct four_ints *immediates;
425+ struct four_ints pos_immediates, neg_immediates, inv_immediates;
426
427 /* Find out which operations are safe for a given CODE. Also do a quick
428 check for degenerate cases; these can occur when DImode operations
429@@ -2789,7 +2933,6 @@
430 {
431 case SET:
432 can_invert = 1;
433- can_negate = 1;
434 break;
435
436 case PLUS:
437@@ -2817,9 +2960,6 @@
438 gen_rtx_SET (VOIDmode, target, source));
439 return 1;
440 }
441-
442- if (TARGET_THUMB2)
443- can_invert = 1;
444 break;
445
446 case AND:
447@@ -2861,6 +3001,7 @@
448 gen_rtx_NOT (mode, source)));
449 return 1;
450 }
451+ final_invert = 1;
452 break;
453
454 case MINUS:
455@@ -2883,7 +3024,6 @@
456 source)));
457 return 1;
458 }
459- can_negate = 1;
460
461 break;
462
463@@ -2892,9 +3032,7 @@
464 }
465
466 /* If we can do it in one insn get out quickly. */
467- if (const_ok_for_arm (val)
468- || (can_negate_initial && const_ok_for_arm (-val))
469- || (can_invert && const_ok_for_arm (~val)))
470+ if (const_ok_for_op (val, code))
471 {
472 if (generate)
473 emit_constant_insn (cond,
474@@ -2947,15 +3085,6 @@
475 switch (code)
476 {
477 case SET:
478- /* See if we can use movw. */
479- if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0)
480- {
481- if (generate)
482- emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
483- GEN_INT (val)));
484- return 1;
485- }
486-
487 /* See if we can do this by sign_extending a constant that is known
488 to be negative. This is a good, way of doing it, since the shift
489 may well merge into a subsequent insn. */
490@@ -3306,121 +3435,97 @@
491 break;
492 }
493
494- for (i = 0; i < 32; i++)
495- if (remainder & (1 << i))
496- num_bits_set++;
497-
498- if ((code == AND)
499- || (code != IOR && can_invert && num_bits_set > 16))
500- remainder ^= 0xffffffff;
501- else if (code == PLUS && num_bits_set > 16)
502- remainder = (-remainder) & 0xffffffff;
503-
504- /* For XOR, if more than half the bits are set and there's a sequence
505- of more than 8 consecutive ones in the pattern then we can XOR by the
506- inverted constant and then invert the final result; this may save an
507- instruction and might also lead to the final mvn being merged with
508- some other operation. */
509- else if (code == XOR && num_bits_set > 16
510- && (count_insns_for_constant (remainder ^ 0xffffffff,
511- find_best_start
512- (remainder ^ 0xffffffff))
513- < count_insns_for_constant (remainder,
514- find_best_start (remainder))))
515- {
516- remainder ^= 0xffffffff;
517- final_invert = 1;
518+ /* Calculate what the instruction sequences would be if we generated it
519+ normally, negated, or inverted. */
520+ if (code == AND)
521+ /* AND cannot be split into multiple insns, so invert and use BIC. */
522+ insns = 99;
523+ else
524+ insns = optimal_immediate_sequence (code, remainder, &pos_immediates);
525+
526+ if (can_negate)
527+ neg_insns = optimal_immediate_sequence (code, (-remainder) & 0xffffffff,
528+ &neg_immediates);
529+ else
530+ neg_insns = 99;
531+
532+ if (can_invert || final_invert)
533+ inv_insns = optimal_immediate_sequence (code, remainder ^ 0xffffffff,
534+ &inv_immediates);
535+ else
536+ inv_insns = 99;
537+
538+ immediates = &pos_immediates;
539+
540+ /* Is the negated immediate sequence more efficient? */
541+ if (neg_insns < insns && neg_insns <= inv_insns)
542+ {
543+ insns = neg_insns;
544+ immediates = &neg_immediates;
545+ }
546+ else
547+ can_negate = 0;
548+
549+ /* Is the inverted immediate sequence more efficient?
550+ We must allow for an extra NOT instruction for XOR operations, although
551+ there is some chance that the final 'mvn' will get optimized later. */
552+ if ((inv_insns + 1) < insns || (!final_invert && inv_insns < insns))
553+ {
554+ insns = inv_insns;
555+ immediates = &inv_immediates;
556 }
557 else
558 {
559 can_invert = 0;
560- can_negate = 0;
561+ final_invert = 0;
562 }
563
564- /* Now try and find a way of doing the job in either two or three
565- instructions.
566- We start by looking for the largest block of zeros that are aligned on
567- a 2-bit boundary, we then fill up the temps, wrapping around to the
568- top of the word when we drop off the bottom.
569- In the worst case this code should produce no more than four insns.
570- Thumb-2 constants are shifted, not rotated, so the MSB is always the
571- best place to start. */
572-
573- /* ??? Use thumb2 replicated constants when the high and low halfwords are
574- the same. */
575- {
576- /* Now start emitting the insns. */
577- i = find_best_start (remainder);
578- do
579- {
580- int end;
581-
582- if (i <= 0)
583- i += 32;
584- if (remainder & (3 << (i - 2)))
585- {
586- end = i - 8;
587- if (end < 0)
588- end += 32;
589- temp1 = remainder & ((0x0ff << end)
590- | ((i < end) ? (0xff >> (32 - end)) : 0));
591- remainder &= ~temp1;
592-
593- if (generate)
594- {
595- rtx new_src, temp1_rtx;
596-
597- if (code == SET || code == MINUS)
598- {
599- new_src = (subtargets ? gen_reg_rtx (mode) : target);
600- if (can_invert && code != MINUS)
601- temp1 = ~temp1;
602- }
603- else
604- {
605- if ((final_invert || remainder) && subtargets)
606- new_src = gen_reg_rtx (mode);
607- else
608- new_src = target;
609- if (can_invert)
610- temp1 = ~temp1;
611- else if (can_negate)
612- temp1 = -temp1;
613- }
614-
615- temp1 = trunc_int_for_mode (temp1, mode);
616- temp1_rtx = GEN_INT (temp1);
617-
618- if (code == SET)
619- ;
620- else if (code == MINUS)
621- temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
622- else
623- temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
624-
625- emit_constant_insn (cond,
626- gen_rtx_SET (VOIDmode, new_src,
627- temp1_rtx));
628- source = new_src;
629- }
630-
631- if (code == SET)
632- {
633- can_invert = 0;
634- code = PLUS;
635- }
636- else if (code == MINUS)
637+ /* Now output the chosen sequence as instructions. */
638+ if (generate)
639+ {
640+ for (i = 0; i < insns; i++)
641+ {
642+ rtx new_src, temp1_rtx;
643+
644+ temp1 = immediates->i[i];
645+
646+ if (code == SET || code == MINUS)
647+ new_src = (subtargets ? gen_reg_rtx (mode) : target);
648+ else if ((final_invert || i < (insns - 1)) && subtargets)
649+ new_src = gen_reg_rtx (mode);
650+ else
651+ new_src = target;
652+
653+ if (can_invert)
654+ temp1 = ~temp1;
655+ else if (can_negate)
656+ temp1 = -temp1;
657+
658+ temp1 = trunc_int_for_mode (temp1, mode);
659+ temp1_rtx = GEN_INT (temp1);
660+
661+ if (code == SET)
662+ ;
663+ else if (code == MINUS)
664+ temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
665+ else
666+ temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
667+
668+ emit_constant_insn (cond,
669+ gen_rtx_SET (VOIDmode, new_src,
670+ temp1_rtx));
671+ source = new_src;
672+
673+ if (code == SET)
674+ {
675+ can_negate = can_invert;
676+ can_invert = 0;
677 code = PLUS;
678-
679- insns++;
680- i -= 8 - step_size;
681- }
682- /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
683- shifts. */
684- i -= step_size;
685- }
686- while (remainder);
687- }
688+ }
689+ else if (code == MINUS)
690+ code = PLUS;
691+ }
692+ }
693
694 if (final_invert)
695 {
696
697=== modified file 'gcc/config/arm/arm.md'
698--- old/gcc/config/arm/arm.md 2011-08-25 11:42:09 +0000
699+++ new/gcc/config/arm/arm.md 2011-08-25 13:26:58 +0000
700@@ -701,21 +701,24 @@
701 ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will
702 ;; put the duplicated register first, and not try the commutative version.
703 (define_insn_and_split "*arm_addsi3"
704- [(set (match_operand:SI 0 "s_register_operand" "=r, k,r,r, k,r")
705- (plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k,rk")
706- (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,L, L,?n")))]
707+ [(set (match_operand:SI 0 "s_register_operand" "=r, k,r,r, k, r, k,r, k, r")
708+ (plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k, rk,k,rk,k, rk")
709+ (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,Pj,Pj,L, L,PJ,PJ,?n")))]
710 "TARGET_32BIT"
711 "@
712 add%?\\t%0, %1, %2
713 add%?\\t%0, %1, %2
714 add%?\\t%0, %2, %1
715- sub%?\\t%0, %1, #%n2
716- sub%?\\t%0, %1, #%n2
717+ addw%?\\t%0, %1, %2
718+ addw%?\\t%0, %1, %2
719+ sub%?\\t%0, %1, #%n2
720+ sub%?\\t%0, %1, #%n2
721+ subw%?\\t%0, %1, #%n2
722+ subw%?\\t%0, %1, #%n2
723 #"
724 "TARGET_32BIT
725 && GET_CODE (operands[2]) == CONST_INT
726- && !(const_ok_for_arm (INTVAL (operands[2]))
727- || const_ok_for_arm (-INTVAL (operands[2])))
728+ && !const_ok_for_op (INTVAL (operands[2]), PLUS)
729 && (reload_completed || !arm_eliminable_register (operands[1]))"
730 [(clobber (const_int 0))]
731 "
732@@ -724,8 +727,9 @@
733 operands[1], 0);
734 DONE;
735 "
736- [(set_attr "length" "4,4,4,4,4,16")
737- (set_attr "predicable" "yes")]
738+ [(set_attr "length" "4,4,4,4,4,4,4,4,4,16")
739+ (set_attr "predicable" "yes")
740+ (set_attr "arch" "*,*,*,t2,t2,*,*,t2,t2,*")]
741 )
742
743 (define_insn_and_split "*thumb1_addsi3"
744
745=== modified file 'gcc/config/arm/constraints.md'
746--- old/gcc/config/arm/constraints.md 2011-01-03 20:52:22 +0000
747+++ new/gcc/config/arm/constraints.md 2011-08-25 13:26:58 +0000
748@@ -31,7 +31,7 @@
749 ;; The following multi-letter normal constraints have been used:
750 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz
751 ;; in Thumb-1 state: Pa, Pb, Pc, Pd
752-;; in Thumb-2 state: Ps, Pt, Pu, Pv, Pw, Px
753+;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px
754
755 ;; The following memory constraints have been used:
756 ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
757@@ -74,6 +74,18 @@
758 (and (match_code "const_int")
759 (match_test "(ival & 0xffff0000) == 0")))))
760
761+(define_constraint "Pj"
762+ "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
763+ (and (match_code "const_int")
764+ (and (match_test "TARGET_THUMB2")
765+ (match_test "(ival & 0xfffff000) == 0"))))
766+
767+(define_constraint "PJ"
768+ "@internal A constant that satisfies the Pj constrant if negated."
769+ (and (match_code "const_int")
770+ (and (match_test "TARGET_THUMB2")
771+ (match_test "((-ival) & 0xfffff000) == 0"))))
772+
773 (define_register_constraint "k" "STACK_REG"
774 "@internal The stack register.")
775
776
777=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c'
778--- old/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c 1970-01-01 00:00:00 +0000
779+++ new/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c 2011-08-25 13:31:00 +0000
780@@ -0,0 +1,27 @@
781+/* Ensure simple replicated constant immediates work. */
782+/* { dg-options "-mthumb -O2" } */
783+/* { dg-require-effective-target arm_thumb2_ok } */
784+
785+int
786+foo1 (int a)
787+{
788+ return a + 0xfefefefe;
789+}
790+
791+/* { dg-final { scan-assembler "add.*#-16843010" } } */
792+
793+int
794+foo2 (int a)
795+{
796+ return a - 0xab00ab00;
797+}
798+
799+/* { dg-final { scan-assembler "sub.*#-1426019584" } } */
800+
801+int
802+foo3 (int a)
803+{
804+ return a & 0x00cd00cd;
805+}
806+
807+/* { dg-final { scan-assembler "and.*#13435085" } } */
808
809=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c'
810--- old/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c 1970-01-01 00:00:00 +0000
811+++ new/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c 2011-08-25 13:31:00 +0000
812@@ -0,0 +1,75 @@
813+/* Ensure split constants can use replicated patterns. */
814+/* { dg-options "-mthumb -O2" } */
815+/* { dg-require-effective-target arm_thumb2_ok } */
816+
817+int
818+foo1 (int a)
819+{
820+ return a + 0xfe00fe01;
821+}
822+
823+/* { dg-final { scan-assembler "add.*#-33489408" } } */
824+/* { dg-final { scan-assembler "add.*#1" } } */
825+
826+int
827+foo2 (int a)
828+{
829+ return a + 0xdd01dd00;
830+}
831+
832+/* { dg-final { scan-assembler "add.*#-587145984" } } */
833+/* { dg-final { scan-assembler "add.*#65536" } } */
834+
835+int
836+foo3 (int a)
837+{
838+ return a + 0x00443344;
839+}
840+
841+/* { dg-final { scan-assembler "add.*#4456516" } } */
842+/* { dg-final { scan-assembler "add.*#13056" } } */
843+
844+int
845+foo4 (int a)
846+{
847+ return a + 0x77330033;
848+}
849+
850+/* { dg-final { scan-assembler "add.*#1996488704" } } */
851+/* { dg-final { scan-assembler "add.*#3342387" } } */
852+
853+int
854+foo5 (int a)
855+{
856+ return a + 0x11221122;
857+}
858+
859+/* { dg-final { scan-assembler "add.*#285217024" } } */
860+/* { dg-final { scan-assembler "add.*#2228258" } } */
861+
862+int
863+foo6 (int a)
864+{
865+ return a + 0x66666677;
866+}
867+
868+/* { dg-final { scan-assembler "add.*#1717986918" } } */
869+/* { dg-final { scan-assembler "add.*#17" } } */
870+
871+int
872+foo7 (int a)
873+{
874+ return a + 0x99888888;
875+}
876+
877+/* { dg-final { scan-assembler "add.*#-2004318072" } } */
878+/* { dg-final { scan-assembler "add.*#285212672" } } */
879+
880+int
881+foo8 (int a)
882+{
883+ return a + 0xdddddfff;
884+}
885+
886+/* { dg-final { scan-assembler "add.*#-572662307" } } */
887+/* { dg-final { scan-assembler "addw.*#546" } } */
888
889=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c'
890--- old/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c 1970-01-01 00:00:00 +0000
891+++ new/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c 2011-08-25 13:31:00 +0000
892@@ -0,0 +1,28 @@
893+/* Ensure negated/inverted replicated constant immediates work. */
894+/* { dg-options "-mthumb -O2" } */
895+/* { dg-require-effective-target arm_thumb2_ok } */
896+
897+int
898+foo1 (int a)
899+{
900+ return a | 0xffffff00;
901+}
902+
903+/* { dg-final { scan-assembler "orn.*#255" } } */
904+
905+int
906+foo2 (int a)
907+{
908+ return a & 0xffeeffee;
909+}
910+
911+/* { dg-final { scan-assembler "bic.*#1114129" } } */
912+
913+int
914+foo3 (int a)
915+{
916+ return a & 0xaaaaaa00;
917+}
918+
919+/* { dg-final { scan-assembler "and.*#-1431655766" } } */
920+/* { dg-final { scan-assembler "bic.*#170" } } */
921
922=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c'
923--- old/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c 1970-01-01 00:00:00 +0000
924+++ new/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c 2011-08-25 13:31:00 +0000
925@@ -0,0 +1,22 @@
926+/* Ensure replicated constants don't make things worse. */
927+/* { dg-options "-mthumb -O2" } */
928+/* { dg-require-effective-target arm_thumb2_ok } */
929+
930+int
931+foo1 (int a)
932+{
933+ /* It might be tempting to use 0x01000100, but it wouldn't help. */
934+ return a + 0x01f001e0;
935+}
936+
937+/* { dg-final { scan-assembler "add.*#32505856" } } */
938+/* { dg-final { scan-assembler "add.*#480" } } */
939+
940+int
941+foo2 (int a)
942+{
943+ return a + 0x0f100e10;
944+}
945+
946+/* { dg-final { scan-assembler "add.*#252706816" } } */
947+/* { dg-final { scan-assembler "add.*#3600" } } */
948
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106803.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106803.patch
deleted file mode 100644
index 5b36959b6..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106803.patch
+++ /dev/null
@@ -1,201 +0,0 @@
12011-09-12 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 PR target/49030
5 * config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
6 * config/arm/arm.c (maybe_get_arm_condition_code): New function,
7 reusing the old code from get_arm_condition_code. Return ARM_NV
8 for invalid comparison codes.
9 (get_arm_condition_code): Redefine in terms of
10 maybe_get_arm_condition_code.
11 * config/arm/predicates.md (arm_comparison_operator): Use
12 maybe_get_arm_condition_code.
13
14 gcc/testsuite/
15 PR target/49030
16 * gcc.dg/torture/pr49030.c: New test.
17
18=== modified file 'gcc/config/arm/arm-protos.h'
19--- old/gcc/config/arm/arm-protos.h 2011-08-25 13:26:58 +0000
20+++ new/gcc/config/arm/arm-protos.h 2011-09-12 11:03:11 +0000
21@@ -179,6 +179,7 @@
22 #endif
23 extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
24 #ifdef RTX_CODE
25+extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
26 extern void thumb1_final_prescan_insn (rtx);
27 extern void thumb2_final_prescan_insn (rtx);
28 extern const char *thumb_load_double_from_address (rtx *);
29
30=== modified file 'gcc/config/arm/arm.c'
31--- old/gcc/config/arm/arm.c 2011-09-06 12:57:56 +0000
32+++ new/gcc/config/arm/arm.c 2011-09-12 11:03:11 +0000
33@@ -17494,10 +17494,10 @@
34 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
35
36 /* Returns the index of the ARM condition code string in
37- `arm_condition_codes'. COMPARISON should be an rtx like
38- `(eq (...) (...))'. */
39-static enum arm_cond_code
40-get_arm_condition_code (rtx comparison)
41+ `arm_condition_codes', or ARM_NV if the comparison is invalid.
42+ COMPARISON should be an rtx like `(eq (...) (...))'. */
43+enum arm_cond_code
44+maybe_get_arm_condition_code (rtx comparison)
45 {
46 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
47 enum arm_cond_code code;
48@@ -17521,11 +17521,11 @@
49 case CC_DLTUmode: code = ARM_CC;
50
51 dominance:
52- gcc_assert (comp_code == EQ || comp_code == NE);
53-
54 if (comp_code == EQ)
55 return ARM_INVERSE_CONDITION_CODE (code);
56- return code;
57+ if (comp_code == NE)
58+ return code;
59+ return ARM_NV;
60
61 case CC_NOOVmode:
62 switch (comp_code)
63@@ -17534,7 +17534,7 @@
64 case EQ: return ARM_EQ;
65 case GE: return ARM_PL;
66 case LT: return ARM_MI;
67- default: gcc_unreachable ();
68+ default: return ARM_NV;
69 }
70
71 case CC_Zmode:
72@@ -17542,7 +17542,7 @@
73 {
74 case NE: return ARM_NE;
75 case EQ: return ARM_EQ;
76- default: gcc_unreachable ();
77+ default: return ARM_NV;
78 }
79
80 case CC_Nmode:
81@@ -17550,7 +17550,7 @@
82 {
83 case NE: return ARM_MI;
84 case EQ: return ARM_PL;
85- default: gcc_unreachable ();
86+ default: return ARM_NV;
87 }
88
89 case CCFPEmode:
90@@ -17575,7 +17575,7 @@
91 /* UNEQ and LTGT do not have a representation. */
92 case UNEQ: /* Fall through. */
93 case LTGT: /* Fall through. */
94- default: gcc_unreachable ();
95+ default: return ARM_NV;
96 }
97
98 case CC_SWPmode:
99@@ -17591,7 +17591,7 @@
100 case GTU: return ARM_CC;
101 case LEU: return ARM_CS;
102 case LTU: return ARM_HI;
103- default: gcc_unreachable ();
104+ default: return ARM_NV;
105 }
106
107 case CC_Cmode:
108@@ -17599,7 +17599,7 @@
109 {
110 case LTU: return ARM_CS;
111 case GEU: return ARM_CC;
112- default: gcc_unreachable ();
113+ default: return ARM_NV;
114 }
115
116 case CC_CZmode:
117@@ -17611,7 +17611,7 @@
118 case GTU: return ARM_HI;
119 case LEU: return ARM_LS;
120 case LTU: return ARM_CC;
121- default: gcc_unreachable ();
122+ default: return ARM_NV;
123 }
124
125 case CC_NCVmode:
126@@ -17621,7 +17621,7 @@
127 case LT: return ARM_LT;
128 case GEU: return ARM_CS;
129 case LTU: return ARM_CC;
130- default: gcc_unreachable ();
131+ default: return ARM_NV;
132 }
133
134 case CCmode:
135@@ -17637,13 +17637,22 @@
136 case GTU: return ARM_HI;
137 case LEU: return ARM_LS;
138 case LTU: return ARM_CC;
139- default: gcc_unreachable ();
140+ default: return ARM_NV;
141 }
142
143 default: gcc_unreachable ();
144 }
145 }
146
147+/* Like maybe_get_arm_condition_code, but never return ARM_NV. */
148+static enum arm_cond_code
149+get_arm_condition_code (rtx comparison)
150+{
151+ enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
152+ gcc_assert (code != ARM_NV);
153+ return code;
154+}
155+
156 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
157 instructions. */
158 void
159
160=== modified file 'gcc/config/arm/predicates.md'
161--- old/gcc/config/arm/predicates.md 2011-08-13 08:40:36 +0000
162+++ new/gcc/config/arm/predicates.md 2011-09-05 09:40:19 +0000
163@@ -242,10 +242,9 @@
164 ;; True for integer comparisons and, if FP is active, for comparisons
165 ;; other than LTGT or UNEQ.
166 (define_special_predicate "arm_comparison_operator"
167- (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
168- (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
169- && (TARGET_FPA || TARGET_VFP)")
170- (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
171+ (and (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
172+ unordered,ordered,unlt,unle,unge,ungt")
173+ (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
174
175 (define_special_predicate "lt_ge_comparison_operator"
176 (match_code "lt,ge"))
177
178=== added file 'gcc/testsuite/gcc.dg/torture/pr49030.c'
179--- old/gcc/testsuite/gcc.dg/torture/pr49030.c 1970-01-01 00:00:00 +0000
180+++ new/gcc/testsuite/gcc.dg/torture/pr49030.c 2011-09-05 09:40:19 +0000
181@@ -0,0 +1,19 @@
182+void
183+sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
184+ unsigned long dst_skip)
185+{
186+ long long y;
187+ while (nsamples--)
188+ {
189+ y = (long long) (*src * 8388608.0f) << 8;
190+ if (y > 2147483647) {
191+ *(int *) dst = 2147483647;
192+ } else if (y < -2147483647 - 1) {
193+ *(int *) dst = -2147483647 - 1;
194+ } else {
195+ *(int *) dst = (int) y;
196+ }
197+ dst += dst_skip;
198+ src++;
199+ }
200+}
201
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106804.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106804.patch
deleted file mode 100644
index 09d076791..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106804.patch
+++ /dev/null
@@ -1,38 +0,0 @@
12011-09-01 Andrew Stubbs <ams@codesourcery.com>
2
3 gcc/
4 * config/arm/predicates.md (shift_amount_operand): Ensure shift
5 amount is positive.
6
7 gcc/testsuite/
8 * gcc.dg/pr50193-1.c: New file.
9
10=== modified file 'gcc/config/arm/predicates.md'
11--- old/gcc/config/arm/predicates.md 2011-09-05 09:40:19 +0000
12+++ new/gcc/config/arm/predicates.md 2011-09-12 11:24:34 +0000
13@@ -132,7 +132,8 @@
14 (define_predicate "shift_amount_operand"
15 (ior (and (match_test "TARGET_ARM")
16 (match_operand 0 "s_register_operand"))
17- (match_operand 0 "const_int_operand")))
18+ (and (match_operand 0 "const_int_operand")
19+ (match_test "INTVAL (op) > 0"))))
20
21 (define_predicate "arm_add_operand"
22 (ior (match_operand 0 "arm_rhs_operand")
23
24=== added file 'gcc/testsuite/gcc.dg/pr50193-1.c'
25--- old/gcc/testsuite/gcc.dg/pr50193-1.c 1970-01-01 00:00:00 +0000
26+++ new/gcc/testsuite/gcc.dg/pr50193-1.c 2011-09-01 12:22:14 +0000
27@@ -0,0 +1,10 @@
28+/* PR 50193: ARM: ICE on a | (b << negative-constant) */
29+/* Ensure that the compiler doesn't ICE. */
30+
31+/* { dg-options "-O2" } */
32+
33+int
34+foo(int a, int b)
35+{
36+ return a | (b << -3); /* { dg-warning "left shift count is negative" } */
37+}
38
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106805.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106805.patch
deleted file mode 100644
index 5dec32fa7..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106805.patch
+++ /dev/null
@@ -1,47 +0,0 @@
12011-09-12 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF mainline:
4
5 2011-09-08 Andrew Stubbs <ams@codesourcery.com>
6
7 PR tree-optimization/50318
8
9 gcc/
10 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Correct
11 typo in use of mult_rhs1 and mult_rhs2.
12
13 gcc/testsuite/
14 * gcc.target/arm/pr50318-1.c: New file.
15
16=== added file 'gcc/testsuite/gcc.target/arm/pr50318-1.c'
17--- old/gcc/testsuite/gcc.target/arm/pr50318-1.c 1970-01-01 00:00:00 +0000
18+++ new/gcc/testsuite/gcc.target/arm/pr50318-1.c 2011-09-08 20:11:43 +0000
19@@ -0,0 +1,11 @@
20+/* { dg-do compile } */
21+/* { dg-options "-O2" } */
22+/* { dg-require-effective-target arm_dsp } */
23+
24+long long test (unsigned int sec, unsigned long long nsecs)
25+{
26+ return (long long)(long)sec * 1000000000L + (long long)(unsigned
27+ long)nsecs;
28+}
29+
30+/* { dg-final { scan-assembler "umlal" } } */
31
32=== modified file 'gcc/tree-ssa-math-opts.c'
33--- old/gcc/tree-ssa-math-opts.c 2011-08-09 10:26:48 +0000
34+++ new/gcc/tree-ssa-math-opts.c 2011-09-08 20:11:43 +0000
35@@ -1699,9 +1699,9 @@
36
37 /* Handle constants. */
38 if (TREE_CODE (mult_rhs1) == INTEGER_CST)
39- rhs1 = fold_convert (type1, mult_rhs1);
40+ mult_rhs1 = fold_convert (type1, mult_rhs1);
41 if (TREE_CODE (mult_rhs2) == INTEGER_CST)
42- rhs2 = fold_convert (type2, mult_rhs2);
43+ mult_rhs2 = fold_convert (type2, mult_rhs2);
44
45 gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code, mult_rhs1, mult_rhs2,
46 add_rhs);
47
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106806.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106806.patch
deleted file mode 100644
index 2b96854c9..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106806.patch
+++ /dev/null
@@ -1,92 +0,0 @@
12011-09-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 gcc/testsuite/
4 * gcc.target/arm/pr50099.c: Fix testcase from previous commit.
5
62011-09-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
7
8 LP:838994
9 gcc/
10 Backport from mainline.
11
12 2011-09-06 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
13
14 PR target/50099
15 * config/arm/iterators.md (qhs_zextenddi_cstr): New.
16 (qhs_zextenddi_op): New.
17 * config/arm/arm.md ("zero_extend<mode>di2"): Use them.
18 * config/arm/predicates.md ("arm_extendqisi_mem_op"):
19 Distinguish between ARM and Thumb2 states.
20
21 gcc/testsuite/
22 * gcc.target/arm/pr50099.c: New test.
23
24=== modified file 'gcc/config/arm/arm.md'
25--- old/gcc/config/arm/arm.md 2011-08-25 13:26:58 +0000
26+++ new/gcc/config/arm/arm.md 2011-09-12 12:32:29 +0000
27@@ -4136,8 +4136,8 @@
28
29 (define_insn "zero_extend<mode>di2"
30 [(set (match_operand:DI 0 "s_register_operand" "=r")
31- (zero_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
32- "<qhs_extenddi_cstr>")))]
33+ (zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>"
34+ "<qhs_zextenddi_cstr>")))]
35 "TARGET_32BIT <qhs_zextenddi_cond>"
36 "#"
37 [(set_attr "length" "8")
38
39=== modified file 'gcc/config/arm/iterators.md'
40--- old/gcc/config/arm/iterators.md 2011-05-03 15:14:56 +0000
41+++ new/gcc/config/arm/iterators.md 2011-09-06 14:29:24 +0000
42@@ -379,10 +379,14 @@
43 (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
44 (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
45 (QI "&& arm_arch6")])
46+(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
47+ (HI "nonimmediate_operand")
48+ (QI "nonimmediate_operand")])
49 (define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
50 (HI "nonimmediate_operand")
51- (QI "nonimmediate_operand")])
52-(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
53+ (QI "arm_reg_or_extendqisi_mem_op")])
54+(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rUq")])
55+(define_mode_attr qhs_zextenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
56
57 ;;----------------------------------------------------------------------------
58 ;; Code attributes
59
60=== modified file 'gcc/config/arm/predicates.md'
61--- old/gcc/config/arm/predicates.md 2011-09-12 11:24:34 +0000
62+++ new/gcc/config/arm/predicates.md 2011-09-12 12:32:29 +0000
63@@ -289,8 +289,11 @@
64
65 (define_special_predicate "arm_extendqisi_mem_op"
66 (and (match_operand 0 "memory_operand")
67- (match_test "arm_legitimate_address_outer_p (mode, XEXP (op, 0),
68- SIGN_EXTEND, 0)")))
69+ (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
70+ XEXP (op, 0),
71+ SIGN_EXTEND,
72+ 0)
73+ : memory_address_p (QImode, XEXP (op, 0))")))
74
75 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
76 (ior (match_operand 0 "arm_extendqisi_mem_op")
77
78=== added file 'gcc/testsuite/gcc.target/arm/pr50099.c'
79--- old/gcc/testsuite/gcc.target/arm/pr50099.c 1970-01-01 00:00:00 +0000
80+++ new/gcc/testsuite/gcc.target/arm/pr50099.c 2011-09-09 16:42:45 +0000
81@@ -0,0 +1,10 @@
82+/* { dg-do compile } */
83+/* { dg-options "-O2" } */
84+
85+long long foo (signed char * arg)
86+{
87+ long long temp_1;
88+
89+ temp_1 = arg[256];
90+ return temp_1;
91+}
92
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106807.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106807.patch
deleted file mode 100644
index 9474030f5..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106807.patch
+++ /dev/null
@@ -1,767 +0,0 @@
12011-08-26 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from FSF mainline:
4 2011-04-06 Wei Guozhi <carrot@google.com>
5
6 PR target/47855
7 gcc/
8 * config/arm/arm.md (arm_cmpsi_insn): Compute attr "length".
9 (arm_cond_branch): Likewise.
10 (arm_cond_branch_reversed): Likewise.
11 (arm_jump): Likewise.
12 (push_multi): Likewise.
13 * config/arm/constraints.md (Py): New constraint.
14
15 2011-04-08 Wei Guozhi <carrot@google.com>
16
17 PR target/47855
18 * config/arm/arm-protos.h (arm_attr_length_push_multi): New prototype.
19 * config/arm/arm.c (arm_attr_length_push_multi): New function.
20 * config/arm/arm.md (*push_multi): Change the length computation to
21 call a C function.
22
232011-08-26 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
24
25 Backport from FSF mainline:
26
27 2011-08-18 Jiangning Liu <jiangning.liu@arm.com>
28
29 gcc/
30 * config/arm/arm.md (*ior_scc_scc): Enable for Thumb2 as well.
31 (*ior_scc_scc_cmp): Likewise
32 (*and_scc_scc): Likewise.
33 (*and_scc_scc_cmp): Likewise.
34 (*and_scc_scc_nodom): Likewise.
35 (*cmp_ite0, *cmp_ite1, *cmp_and, *cmp_ior): Handle Thumb2.
36
37 gcc/testsuite
38 * gcc.target/arm/thumb2-cond-cmp-1.c: New. Make sure conditional
39 compare can be generated.
40 * gcc.target/arm/thumb2-cond-cmp-2.c: Likewise.
41 * gcc.target/arm/thumb2-cond-cmp-3.c: Likewise.
42 * gcc.target/arm/thumb2-cond-cmp-4.c: Likewise.
43
44=== modified file 'gcc/config/arm/arm-protos.h'
45--- old/gcc/config/arm/arm-protos.h 2011-09-12 11:03:11 +0000
46+++ new/gcc/config/arm/arm-protos.h 2011-09-12 14:14:00 +0000
47@@ -156,6 +156,7 @@
48 extern const char *arm_output_memory_barrier (rtx *);
49 extern const char *arm_output_sync_insn (rtx, rtx *);
50 extern unsigned int arm_sync_loop_insns (rtx , rtx *);
51+extern int arm_attr_length_push_multi(rtx, rtx);
52
53 #if defined TREE_CODE
54 extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
55
56=== modified file 'gcc/config/arm/arm.c'
57--- old/gcc/config/arm/arm.c 2011-09-12 11:03:11 +0000
58+++ new/gcc/config/arm/arm.c 2011-09-12 14:14:00 +0000
59@@ -24391,4 +24391,30 @@
60 return NO_REGS;
61 }
62
63+/* Compute the atrribute "length" of insn "*push_multi".
64+ So this function MUST be kept in sync with that insn pattern. */
65+int
66+arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
67+{
68+ int i, regno, hi_reg;
69+ int num_saves = XVECLEN (parallel_op, 0);
70+
71+ /* ARM mode. */
72+ if (TARGET_ARM)
73+ return 4;
74+
75+ /* Thumb2 mode. */
76+ regno = REGNO (first_op);
77+ hi_reg = (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
78+ for (i = 1; i < num_saves && !hi_reg; i++)
79+ {
80+ regno = REGNO (XEXP (XVECEXP (parallel_op, 0, i), 0));
81+ hi_reg |= (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
82+ }
83+
84+ if (!hi_reg)
85+ return 2;
86+ return 4;
87+}
88+
89 #include "gt-arm.h"
90
91=== modified file 'gcc/config/arm/arm.md'
92--- old/gcc/config/arm/arm.md 2011-09-12 12:32:29 +0000
93+++ new/gcc/config/arm/arm.md 2011-09-12 14:14:00 +0000
94@@ -48,6 +48,15 @@
95 (DOM_CC_X_OR_Y 2)
96 ]
97 )
98+;; conditional compare combination
99+(define_constants
100+ [(CMP_CMP 0)
101+ (CMN_CMP 1)
102+ (CMP_CMN 2)
103+ (CMN_CMN 3)
104+ (NUM_OF_COND_CMP 4)
105+ ]
106+)
107
108 ;; UNSPEC Usage:
109 ;; Note: sin and cos are no-longer used.
110@@ -7198,13 +7207,17 @@
111
112 (define_insn "*arm_cmpsi_insn"
113 [(set (reg:CC CC_REGNUM)
114- (compare:CC (match_operand:SI 0 "s_register_operand" "r,r")
115- (match_operand:SI 1 "arm_add_operand" "rI,L")))]
116+ (compare:CC (match_operand:SI 0 "s_register_operand" "l,r,r,r")
117+ (match_operand:SI 1 "arm_add_operand" "Py,r,rI,L")))]
118 "TARGET_32BIT"
119 "@
120 cmp%?\\t%0, %1
121+ cmp%?\\t%0, %1
122+ cmp%?\\t%0, %1
123 cmn%?\\t%0, #%n1"
124- [(set_attr "conds" "set")]
125+ [(set_attr "conds" "set")
126+ (set_attr "arch" "t2,t2,any,any")
127+ (set_attr "length" "2,2,4,4")]
128 )
129
130 (define_insn "*cmpsi_shiftsi"
131@@ -7375,7 +7388,14 @@
132 return \"b%d1\\t%l0\";
133 "
134 [(set_attr "conds" "use")
135- (set_attr "type" "branch")]
136+ (set_attr "type" "branch")
137+ (set (attr "length")
138+ (if_then_else
139+ (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0))
140+ (and (ge (minus (match_dup 0) (pc)) (const_int -250))
141+ (le (minus (match_dup 0) (pc)) (const_int 256))))
142+ (const_int 2)
143+ (const_int 4)))]
144 )
145
146 (define_insn "*arm_cond_branch_reversed"
147@@ -7394,7 +7414,14 @@
148 return \"b%D1\\t%l0\";
149 "
150 [(set_attr "conds" "use")
151- (set_attr "type" "branch")]
152+ (set_attr "type" "branch")
153+ (set (attr "length")
154+ (if_then_else
155+ (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0))
156+ (and (ge (minus (match_dup 0) (pc)) (const_int -250))
157+ (le (minus (match_dup 0) (pc)) (const_int 256))))
158+ (const_int 2)
159+ (const_int 4)))]
160 )
161
162
163@@ -7846,7 +7873,14 @@
164 return \"b%?\\t%l0\";
165 }
166 "
167- [(set_attr "predicable" "yes")]
168+ [(set_attr "predicable" "yes")
169+ (set (attr "length")
170+ (if_then_else
171+ (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0))
172+ (and (ge (minus (match_dup 0) (pc)) (const_int -2044))
173+ (le (minus (match_dup 0) (pc)) (const_int 2048))))
174+ (const_int 2)
175+ (const_int 4)))]
176 )
177
178 (define_insn "*thumb_jump"
179@@ -8931,40 +8965,85 @@
180 (set_attr "length" "8,12")]
181 )
182
183-;; ??? Is it worth using these conditional patterns in Thumb-2 mode?
184 (define_insn "*cmp_ite0"
185 [(set (match_operand 6 "dominant_cc_register" "")
186 (compare
187 (if_then_else:SI
188 (match_operator 4 "arm_comparison_operator"
189- [(match_operand:SI 0 "s_register_operand" "r,r,r,r")
190- (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")])
191+ [(match_operand:SI 0 "s_register_operand"
192+ "l,l,l,r,r,r,r,r,r")
193+ (match_operand:SI 1 "arm_add_operand"
194+ "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
195 (match_operator:SI 5 "arm_comparison_operator"
196- [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
197- (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])
198+ [(match_operand:SI 2 "s_register_operand"
199+ "l,r,r,l,l,r,r,r,r")
200+ (match_operand:SI 3 "arm_add_operand"
201+ "lPy,rI,L,lPy,lPy,rI,rI,L,L")])
202 (const_int 0))
203 (const_int 0)))]
204- "TARGET_ARM"
205+ "TARGET_32BIT"
206 "*
207 {
208- static const char * const opcodes[4][2] =
209- {
210- {\"cmp\\t%2, %3\;cmp%d5\\t%0, %1\",
211- \"cmp\\t%0, %1\;cmp%d4\\t%2, %3\"},
212- {\"cmp\\t%2, %3\;cmn%d5\\t%0, #%n1\",
213- \"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\"},
214- {\"cmn\\t%2, #%n3\;cmp%d5\\t%0, %1\",
215- \"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\"},
216- {\"cmn\\t%2, #%n3\;cmn%d5\\t%0, #%n1\",
217- \"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\"}
218- };
219+ static const char * const cmp1[NUM_OF_COND_CMP][2] =
220+ {
221+ {\"cmp%d5\\t%0, %1\",
222+ \"cmp%d4\\t%2, %3\"},
223+ {\"cmn%d5\\t%0, #%n1\",
224+ \"cmp%d4\\t%2, %3\"},
225+ {\"cmp%d5\\t%0, %1\",
226+ \"cmn%d4\\t%2, #%n3\"},
227+ {\"cmn%d5\\t%0, #%n1\",
228+ \"cmn%d4\\t%2, #%n3\"}
229+ };
230+ static const char * const cmp2[NUM_OF_COND_CMP][2] =
231+ {
232+ {\"cmp\\t%2, %3\",
233+ \"cmp\\t%0, %1\"},
234+ {\"cmp\\t%2, %3\",
235+ \"cmn\\t%0, #%n1\"},
236+ {\"cmn\\t%2, #%n3\",
237+ \"cmp\\t%0, %1\"},
238+ {\"cmn\\t%2, #%n3\",
239+ \"cmn\\t%0, #%n1\"}
240+ };
241+ static const char * const ite[2] =
242+ {
243+ \"it\\t%d5\",
244+ \"it\\t%d4\"
245+ };
246+ static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
247+ CMP_CMP, CMN_CMP, CMP_CMP,
248+ CMN_CMP, CMP_CMN, CMN_CMN};
249 int swap =
250 comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
251
252- return opcodes[which_alternative][swap];
253+ output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
254+ if (TARGET_THUMB2) {
255+ output_asm_insn (ite[swap], operands);
256+ }
257+ output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
258+ return \"\";
259 }"
260 [(set_attr "conds" "set")
261- (set_attr "length" "8")]
262+ (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
263+ (set_attr_alternative "length"
264+ [(const_int 6)
265+ (const_int 8)
266+ (const_int 8)
267+ (const_int 8)
268+ (const_int 8)
269+ (if_then_else (eq_attr "is_thumb" "no")
270+ (const_int 8)
271+ (const_int 10))
272+ (if_then_else (eq_attr "is_thumb" "no")
273+ (const_int 8)
274+ (const_int 10))
275+ (if_then_else (eq_attr "is_thumb" "no")
276+ (const_int 8)
277+ (const_int 10))
278+ (if_then_else (eq_attr "is_thumb" "no")
279+ (const_int 8)
280+ (const_int 10))])]
281 )
282
283 (define_insn "*cmp_ite1"
284@@ -8972,35 +9051,81 @@
285 (compare
286 (if_then_else:SI
287 (match_operator 4 "arm_comparison_operator"
288- [(match_operand:SI 0 "s_register_operand" "r,r,r,r")
289- (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")])
290+ [(match_operand:SI 0 "s_register_operand"
291+ "l,l,l,r,r,r,r,r,r")
292+ (match_operand:SI 1 "arm_add_operand"
293+ "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
294 (match_operator:SI 5 "arm_comparison_operator"
295- [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
296- (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])
297+ [(match_operand:SI 2 "s_register_operand"
298+ "l,r,r,l,l,r,r,r,r")
299+ (match_operand:SI 3 "arm_add_operand"
300+ "lPy,rI,L,lPy,lPy,rI,rI,L,L")])
301 (const_int 1))
302 (const_int 0)))]
303- "TARGET_ARM"
304+ "TARGET_32BIT"
305 "*
306 {
307- static const char * const opcodes[4][2] =
308- {
309- {\"cmp\\t%0, %1\;cmp%d4\\t%2, %3\",
310- \"cmp\\t%2, %3\;cmp%D5\\t%0, %1\"},
311- {\"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\",
312- \"cmp\\t%2, %3\;cmn%D5\\t%0, #%n1\"},
313- {\"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\",
314- \"cmn\\t%2, #%n3\;cmp%D5\\t%0, %1\"},
315- {\"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\",
316- \"cmn\\t%2, #%n3\;cmn%D5\\t%0, #%n1\"}
317- };
318+ static const char * const cmp1[NUM_OF_COND_CMP][2] =
319+ {
320+ {\"cmp\\t%0, %1\",
321+ \"cmp\\t%2, %3\"},
322+ {\"cmn\\t%0, #%n1\",
323+ \"cmp\\t%2, %3\"},
324+ {\"cmp\\t%0, %1\",
325+ \"cmn\\t%2, #%n3\"},
326+ {\"cmn\\t%0, #%n1\",
327+ \"cmn\\t%2, #%n3\"}
328+ };
329+ static const char * const cmp2[NUM_OF_COND_CMP][2] =
330+ {
331+ {\"cmp%d4\\t%2, %3\",
332+ \"cmp%D5\\t%0, %1\"},
333+ {\"cmp%d4\\t%2, %3\",
334+ \"cmn%D5\\t%0, #%n1\"},
335+ {\"cmn%d4\\t%2, #%n3\",
336+ \"cmp%D5\\t%0, %1\"},
337+ {\"cmn%d4\\t%2, #%n3\",
338+ \"cmn%D5\\t%0, #%n1\"}
339+ };
340+ static const char * const ite[2] =
341+ {
342+ \"it\\t%d4\",
343+ \"it\\t%D5\"
344+ };
345+ static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
346+ CMP_CMP, CMN_CMP, CMP_CMP,
347+ CMN_CMP, CMP_CMN, CMN_CMN};
348 int swap =
349 comparison_dominates_p (GET_CODE (operands[5]),
350 reverse_condition (GET_CODE (operands[4])));
351
352- return opcodes[which_alternative][swap];
353+ output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
354+ if (TARGET_THUMB2) {
355+ output_asm_insn (ite[swap], operands);
356+ }
357+ output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
358+ return \"\";
359 }"
360 [(set_attr "conds" "set")
361- (set_attr "length" "8")]
362+ (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
363+ (set_attr_alternative "length"
364+ [(const_int 6)
365+ (const_int 8)
366+ (const_int 8)
367+ (const_int 8)
368+ (const_int 8)
369+ (if_then_else (eq_attr "is_thumb" "no")
370+ (const_int 8)
371+ (const_int 10))
372+ (if_then_else (eq_attr "is_thumb" "no")
373+ (const_int 8)
374+ (const_int 10))
375+ (if_then_else (eq_attr "is_thumb" "no")
376+ (const_int 8)
377+ (const_int 10))
378+ (if_then_else (eq_attr "is_thumb" "no")
379+ (const_int 8)
380+ (const_int 10))])]
381 )
382
383 (define_insn "*cmp_and"
384@@ -9008,34 +9133,80 @@
385 (compare
386 (and:SI
387 (match_operator 4 "arm_comparison_operator"
388- [(match_operand:SI 0 "s_register_operand" "r,r,r,r")
389- (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")])
390+ [(match_operand:SI 0 "s_register_operand"
391+ "l,l,l,r,r,r,r,r,r")
392+ (match_operand:SI 1 "arm_add_operand"
393+ "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
394 (match_operator:SI 5 "arm_comparison_operator"
395- [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
396- (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")]))
397+ [(match_operand:SI 2 "s_register_operand"
398+ "l,r,r,l,l,r,r,r,r")
399+ (match_operand:SI 3 "arm_add_operand"
400+ "lPy,rI,L,lPy,lPy,rI,rI,L,L")]))
401 (const_int 0)))]
402- "TARGET_ARM"
403+ "TARGET_32BIT"
404 "*
405 {
406- static const char *const opcodes[4][2] =
407- {
408- {\"cmp\\t%2, %3\;cmp%d5\\t%0, %1\",
409- \"cmp\\t%0, %1\;cmp%d4\\t%2, %3\"},
410- {\"cmp\\t%2, %3\;cmn%d5\\t%0, #%n1\",
411- \"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\"},
412- {\"cmn\\t%2, #%n3\;cmp%d5\\t%0, %1\",
413- \"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\"},
414- {\"cmn\\t%2, #%n3\;cmn%d5\\t%0, #%n1\",
415- \"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\"}
416- };
417+ static const char *const cmp1[NUM_OF_COND_CMP][2] =
418+ {
419+ {\"cmp%d5\\t%0, %1\",
420+ \"cmp%d4\\t%2, %3\"},
421+ {\"cmn%d5\\t%0, #%n1\",
422+ \"cmp%d4\\t%2, %3\"},
423+ {\"cmp%d5\\t%0, %1\",
424+ \"cmn%d4\\t%2, #%n3\"},
425+ {\"cmn%d5\\t%0, #%n1\",
426+ \"cmn%d4\\t%2, #%n3\"}
427+ };
428+ static const char *const cmp2[NUM_OF_COND_CMP][2] =
429+ {
430+ {\"cmp\\t%2, %3\",
431+ \"cmp\\t%0, %1\"},
432+ {\"cmp\\t%2, %3\",
433+ \"cmn\\t%0, #%n1\"},
434+ {\"cmn\\t%2, #%n3\",
435+ \"cmp\\t%0, %1\"},
436+ {\"cmn\\t%2, #%n3\",
437+ \"cmn\\t%0, #%n1\"}
438+ };
439+ static const char *const ite[2] =
440+ {
441+ \"it\\t%d5\",
442+ \"it\\t%d4\"
443+ };
444+ static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
445+ CMP_CMP, CMN_CMP, CMP_CMP,
446+ CMN_CMP, CMP_CMN, CMN_CMN};
447 int swap =
448 comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
449
450- return opcodes[which_alternative][swap];
451+ output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
452+ if (TARGET_THUMB2) {
453+ output_asm_insn (ite[swap], operands);
454+ }
455+ output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
456+ return \"\";
457 }"
458 [(set_attr "conds" "set")
459 (set_attr "predicable" "no")
460- (set_attr "length" "8")]
461+ (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
462+ (set_attr_alternative "length"
463+ [(const_int 6)
464+ (const_int 8)
465+ (const_int 8)
466+ (const_int 8)
467+ (const_int 8)
468+ (if_then_else (eq_attr "is_thumb" "no")
469+ (const_int 8)
470+ (const_int 10))
471+ (if_then_else (eq_attr "is_thumb" "no")
472+ (const_int 8)
473+ (const_int 10))
474+ (if_then_else (eq_attr "is_thumb" "no")
475+ (const_int 8)
476+ (const_int 10))
477+ (if_then_else (eq_attr "is_thumb" "no")
478+ (const_int 8)
479+ (const_int 10))])]
480 )
481
482 (define_insn "*cmp_ior"
483@@ -9043,34 +9214,80 @@
484 (compare
485 (ior:SI
486 (match_operator 4 "arm_comparison_operator"
487- [(match_operand:SI 0 "s_register_operand" "r,r,r,r")
488- (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")])
489+ [(match_operand:SI 0 "s_register_operand"
490+ "l,l,l,r,r,r,r,r,r")
491+ (match_operand:SI 1 "arm_add_operand"
492+ "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
493 (match_operator:SI 5 "arm_comparison_operator"
494- [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
495- (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")]))
496+ [(match_operand:SI 2 "s_register_operand"
497+ "l,r,r,l,l,r,r,r,r")
498+ (match_operand:SI 3 "arm_add_operand"
499+ "lPy,rI,L,lPy,lPy,rI,rI,L,L")]))
500 (const_int 0)))]
501- "TARGET_ARM"
502+ "TARGET_32BIT"
503 "*
504-{
505- static const char *const opcodes[4][2] =
506 {
507- {\"cmp\\t%0, %1\;cmp%D4\\t%2, %3\",
508- \"cmp\\t%2, %3\;cmp%D5\\t%0, %1\"},
509- {\"cmn\\t%0, #%n1\;cmp%D4\\t%2, %3\",
510- \"cmp\\t%2, %3\;cmn%D5\\t%0, #%n1\"},
511- {\"cmp\\t%0, %1\;cmn%D4\\t%2, #%n3\",
512- \"cmn\\t%2, #%n3\;cmp%D5\\t%0, %1\"},
513- {\"cmn\\t%0, #%n1\;cmn%D4\\t%2, #%n3\",
514- \"cmn\\t%2, #%n3\;cmn%D5\\t%0, #%n1\"}
515- };
516- int swap =
517- comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
518+ static const char *const cmp1[NUM_OF_COND_CMP][2] =
519+ {
520+ {\"cmp\\t%0, %1\",
521+ \"cmp\\t%2, %3\"},
522+ {\"cmn\\t%0, #%n1\",
523+ \"cmp\\t%2, %3\"},
524+ {\"cmp\\t%0, %1\",
525+ \"cmn\\t%2, #%n3\"},
526+ {\"cmn\\t%0, #%n1\",
527+ \"cmn\\t%2, #%n3\"}
528+ };
529+ static const char *const cmp2[NUM_OF_COND_CMP][2] =
530+ {
531+ {\"cmp%D4\\t%2, %3\",
532+ \"cmp%D5\\t%0, %1\"},
533+ {\"cmp%D4\\t%2, %3\",
534+ \"cmn%D5\\t%0, #%n1\"},
535+ {\"cmn%D4\\t%2, #%n3\",
536+ \"cmp%D5\\t%0, %1\"},
537+ {\"cmn%D4\\t%2, #%n3\",
538+ \"cmn%D5\\t%0, #%n1\"}
539+ };
540+ static const char *const ite[2] =
541+ {
542+ \"it\\t%D4\",
543+ \"it\\t%D5\"
544+ };
545+ static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
546+ CMP_CMP, CMN_CMP, CMP_CMP,
547+ CMN_CMP, CMP_CMN, CMN_CMN};
548+ int swap =
549+ comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
550
551- return opcodes[which_alternative][swap];
552-}
553-"
554+ output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
555+ if (TARGET_THUMB2) {
556+ output_asm_insn (ite[swap], operands);
557+ }
558+ output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
559+ return \"\";
560+ }
561+ "
562 [(set_attr "conds" "set")
563- (set_attr "length" "8")]
564+ (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
565+ (set_attr_alternative "length"
566+ [(const_int 6)
567+ (const_int 8)
568+ (const_int 8)
569+ (const_int 8)
570+ (const_int 8)
571+ (if_then_else (eq_attr "is_thumb" "no")
572+ (const_int 8)
573+ (const_int 10))
574+ (if_then_else (eq_attr "is_thumb" "no")
575+ (const_int 8)
576+ (const_int 10))
577+ (if_then_else (eq_attr "is_thumb" "no")
578+ (const_int 8)
579+ (const_int 10))
580+ (if_then_else (eq_attr "is_thumb" "no")
581+ (const_int 8)
582+ (const_int 10))])]
583 )
584
585 (define_insn_and_split "*ior_scc_scc"
586@@ -9082,11 +9299,11 @@
587 [(match_operand:SI 4 "s_register_operand" "r")
588 (match_operand:SI 5 "arm_add_operand" "rIL")])))
589 (clobber (reg:CC CC_REGNUM))]
590- "TARGET_ARM
591+ "TARGET_32BIT
592 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y)
593 != CCmode)"
594 "#"
595- "TARGET_ARM && reload_completed"
596+ "TARGET_32BIT && reload_completed"
597 [(set (match_dup 7)
598 (compare
599 (ior:SI
600@@ -9115,9 +9332,9 @@
601 (set (match_operand:SI 7 "s_register_operand" "=r")
602 (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
603 (match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
604- "TARGET_ARM"
605+ "TARGET_32BIT"
606 "#"
607- "TARGET_ARM && reload_completed"
608+ "TARGET_32BIT && reload_completed"
609 [(set (match_dup 0)
610 (compare
611 (ior:SI
612@@ -9138,11 +9355,11 @@
613 [(match_operand:SI 4 "s_register_operand" "r")
614 (match_operand:SI 5 "arm_add_operand" "rIL")])))
615 (clobber (reg:CC CC_REGNUM))]
616- "TARGET_ARM
617+ "TARGET_32BIT
618 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
619 != CCmode)"
620 "#"
621- "TARGET_ARM && reload_completed
622+ "TARGET_32BIT && reload_completed
623 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
624 != CCmode)"
625 [(set (match_dup 7)
626@@ -9173,9 +9390,9 @@
627 (set (match_operand:SI 7 "s_register_operand" "=r")
628 (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
629 (match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
630- "TARGET_ARM"
631+ "TARGET_32BIT"
632 "#"
633- "TARGET_ARM && reload_completed"
634+ "TARGET_32BIT && reload_completed"
635 [(set (match_dup 0)
636 (compare
637 (and:SI
638@@ -9200,11 +9417,11 @@
639 [(match_operand:SI 4 "s_register_operand" "r,r,r")
640 (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")])))
641 (clobber (reg:CC CC_REGNUM))]
642- "TARGET_ARM
643+ "TARGET_32BIT
644 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
645 == CCmode)"
646 "#"
647- "TARGET_ARM && reload_completed"
648+ "TARGET_32BIT && reload_completed"
649 [(parallel [(set (match_dup 0)
650 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
651 (clobber (reg:CC CC_REGNUM))])
652@@ -10314,6 +10531,8 @@
653 ;; Push multiple registers to the stack. Registers are in parallel (use ...)
654 ;; expressions. For simplicity, the first register is also in the unspec
655 ;; part.
656+;; To avoid the usage of GNU extension, the length attribute is computed
657+;; in a C function arm_attr_length_push_multi.
658 (define_insn "*push_multi"
659 [(match_parallel 2 "multi_register_push"
660 [(set (match_operand:BLK 0 "memory_operand" "=m")
661@@ -10353,7 +10572,9 @@
662
663 return \"\";
664 }"
665- [(set_attr "type" "store4")]
666+ [(set_attr "type" "store4")
667+ (set (attr "length")
668+ (symbol_ref "arm_attr_length_push_multi (operands[2], operands[1])"))]
669 )
670
671 (define_insn "stack_tie"
672
673=== modified file 'gcc/config/arm/constraints.md'
674--- old/gcc/config/arm/constraints.md 2011-08-25 13:26:58 +0000
675+++ new/gcc/config/arm/constraints.md 2011-09-12 14:14:00 +0000
676@@ -31,7 +31,7 @@
677 ;; The following multi-letter normal constraints have been used:
678 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz
679 ;; in Thumb-1 state: Pa, Pb, Pc, Pd
680-;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px
681+;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
682
683 ;; The following memory constraints have been used:
684 ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
685@@ -201,6 +201,11 @@
686 (and (match_code "const_int")
687 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
688
689+(define_constraint "Py"
690+ "@internal In Thumb-2 state a constant in the range 0 to 255"
691+ (and (match_code "const_int")
692+ (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
693+
694 (define_constraint "G"
695 "In ARM/Thumb-2 state a valid FPA immediate constant."
696 (and (match_code "const_double")
697
698=== added file 'gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c'
699--- old/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c 1970-01-01 00:00:00 +0000
700+++ new/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c 2011-09-12 14:14:00 +0000
701@@ -0,0 +1,13 @@
702+/* Use conditional compare */
703+/* { dg-options "-O2" } */
704+/* { dg-skip-if "" { arm_thumb1_ok } } */
705+/* { dg-final { scan-assembler "cmpne" } } */
706+
707+int f(int i, int j)
708+{
709+ if ( (i == '+') || (j == '-') ) {
710+ return 1;
711+ } else {
712+ return 0;
713+ }
714+}
715
716=== added file 'gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c'
717--- old/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c 1970-01-01 00:00:00 +0000
718+++ new/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c 2011-09-12 14:14:00 +0000
719@@ -0,0 +1,13 @@
720+/* Use conditional compare */
721+/* { dg-options "-O2" } */
722+/* { dg-skip-if "" { arm_thumb1_ok } } */
723+/* { dg-final { scan-assembler "cmpeq" } } */
724+
725+int f(int i, int j)
726+{
727+ if ( (i == '+') && (j == '-') ) {
728+ return 1;
729+ } else {
730+ return 0;
731+ }
732+}
733
734=== added file 'gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c'
735--- old/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c 1970-01-01 00:00:00 +0000
736+++ new/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c 2011-09-12 14:14:00 +0000
737@@ -0,0 +1,12 @@
738+/* Use conditional compare */
739+/* { dg-options "-O2" } */
740+/* { dg-skip-if "" { arm_thumb1_ok } } */
741+/* { dg-final { scan-assembler "cmpgt" } } */
742+
743+int f(int i, int j)
744+{
745+ if ( (i >= '+') ? (j > '-') : 0)
746+ return 1;
747+ else
748+ return 0;
749+}
750
751=== added file 'gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c'
752--- old/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c 1970-01-01 00:00:00 +0000
753+++ new/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c 2011-09-12 14:14:00 +0000
754@@ -0,0 +1,12 @@
755+/* Use conditional compare */
756+/* { dg-options "-O2" } */
757+/* { dg-skip-if "" { arm_thumb1_ok } } */
758+/* { dg-final { scan-assembler "cmpgt" } } */
759+
760+int f(int i, int j)
761+{
762+ if ( (i >= '+') ? (j <= '-') : 1)
763+ return 1;
764+ else
765+ return 0;
766+}
767
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106811.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106811.patch
deleted file mode 100644
index 41b5c6dbf..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106811.patch
+++ /dev/null
@@ -1,203 +0,0 @@
12011-09-15 Richard Sandiford <richard.sandiford@linaro.org>
2
3 Revert:
4
5 gcc/
6 PR target/49030
7 * config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
8 * config/arm/arm.c (maybe_get_arm_condition_code): New function,
9 reusing the old code from get_arm_condition_code. Return ARM_NV
10 for invalid comparison codes.
11 (get_arm_condition_code): Redefine in terms of
12 maybe_get_arm_condition_code.
13 * config/arm/predicates.md (arm_comparison_operator): Use
14 maybe_get_arm_condition_code.
15
16 gcc/testsuite/
17 PR target/49030
18 * gcc.dg/torture/pr49030.c: New test.
19
20=== modified file 'gcc/config/arm/arm-protos.h'
21--- old/gcc/config/arm/arm-protos.h 2011-09-12 14:14:00 +0000
22+++ new/gcc/config/arm/arm-protos.h 2011-09-15 09:45:31 +0000
23@@ -180,7 +180,6 @@
24 #endif
25 extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
26 #ifdef RTX_CODE
27-extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
28 extern void thumb1_final_prescan_insn (rtx);
29 extern void thumb2_final_prescan_insn (rtx);
30 extern const char *thumb_load_double_from_address (rtx *);
31
32=== modified file 'gcc/config/arm/arm.c'
33--- old/gcc/config/arm/arm.c 2011-09-12 14:14:00 +0000
34+++ new/gcc/config/arm/arm.c 2011-09-15 09:45:31 +0000
35@@ -17494,10 +17494,10 @@
36 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
37
38 /* Returns the index of the ARM condition code string in
39- `arm_condition_codes', or ARM_NV if the comparison is invalid.
40- COMPARISON should be an rtx like `(eq (...) (...))'. */
41-enum arm_cond_code
42-maybe_get_arm_condition_code (rtx comparison)
43+ `arm_condition_codes'. COMPARISON should be an rtx like
44+ `(eq (...) (...))'. */
45+static enum arm_cond_code
46+get_arm_condition_code (rtx comparison)
47 {
48 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
49 enum arm_cond_code code;
50@@ -17521,11 +17521,11 @@
51 case CC_DLTUmode: code = ARM_CC;
52
53 dominance:
54+ gcc_assert (comp_code == EQ || comp_code == NE);
55+
56 if (comp_code == EQ)
57 return ARM_INVERSE_CONDITION_CODE (code);
58- if (comp_code == NE)
59- return code;
60- return ARM_NV;
61+ return code;
62
63 case CC_NOOVmode:
64 switch (comp_code)
65@@ -17534,7 +17534,7 @@
66 case EQ: return ARM_EQ;
67 case GE: return ARM_PL;
68 case LT: return ARM_MI;
69- default: return ARM_NV;
70+ default: gcc_unreachable ();
71 }
72
73 case CC_Zmode:
74@@ -17542,7 +17542,7 @@
75 {
76 case NE: return ARM_NE;
77 case EQ: return ARM_EQ;
78- default: return ARM_NV;
79+ default: gcc_unreachable ();
80 }
81
82 case CC_Nmode:
83@@ -17550,7 +17550,7 @@
84 {
85 case NE: return ARM_MI;
86 case EQ: return ARM_PL;
87- default: return ARM_NV;
88+ default: gcc_unreachable ();
89 }
90
91 case CCFPEmode:
92@@ -17575,7 +17575,7 @@
93 /* UNEQ and LTGT do not have a representation. */
94 case UNEQ: /* Fall through. */
95 case LTGT: /* Fall through. */
96- default: return ARM_NV;
97+ default: gcc_unreachable ();
98 }
99
100 case CC_SWPmode:
101@@ -17591,7 +17591,7 @@
102 case GTU: return ARM_CC;
103 case LEU: return ARM_CS;
104 case LTU: return ARM_HI;
105- default: return ARM_NV;
106+ default: gcc_unreachable ();
107 }
108
109 case CC_Cmode:
110@@ -17599,7 +17599,7 @@
111 {
112 case LTU: return ARM_CS;
113 case GEU: return ARM_CC;
114- default: return ARM_NV;
115+ default: gcc_unreachable ();
116 }
117
118 case CC_CZmode:
119@@ -17611,7 +17611,7 @@
120 case GTU: return ARM_HI;
121 case LEU: return ARM_LS;
122 case LTU: return ARM_CC;
123- default: return ARM_NV;
124+ default: gcc_unreachable ();
125 }
126
127 case CC_NCVmode:
128@@ -17621,7 +17621,7 @@
129 case LT: return ARM_LT;
130 case GEU: return ARM_CS;
131 case LTU: return ARM_CC;
132- default: return ARM_NV;
133+ default: gcc_unreachable ();
134 }
135
136 case CCmode:
137@@ -17637,22 +17637,13 @@
138 case GTU: return ARM_HI;
139 case LEU: return ARM_LS;
140 case LTU: return ARM_CC;
141- default: return ARM_NV;
142+ default: gcc_unreachable ();
143 }
144
145 default: gcc_unreachable ();
146 }
147 }
148
149-/* Like maybe_get_arm_condition_code, but never return ARM_NV. */
150-static enum arm_cond_code
151-get_arm_condition_code (rtx comparison)
152-{
153- enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
154- gcc_assert (code != ARM_NV);
155- return code;
156-}
157-
158 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
159 instructions. */
160 void
161
162=== modified file 'gcc/config/arm/predicates.md'
163--- old/gcc/config/arm/predicates.md 2011-09-12 12:32:29 +0000
164+++ new/gcc/config/arm/predicates.md 2011-09-15 09:45:31 +0000
165@@ -243,9 +243,10 @@
166 ;; True for integer comparisons and, if FP is active, for comparisons
167 ;; other than LTGT or UNEQ.
168 (define_special_predicate "arm_comparison_operator"
169- (and (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
170- unordered,ordered,unlt,unle,unge,ungt")
171- (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
172+ (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
173+ (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
174+ && (TARGET_FPA || TARGET_VFP)")
175+ (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
176
177 (define_special_predicate "lt_ge_comparison_operator"
178 (match_code "lt,ge"))
179
180=== removed file 'gcc/testsuite/gcc.dg/torture/pr49030.c'
181--- old/gcc/testsuite/gcc.dg/torture/pr49030.c 2011-09-05 09:40:19 +0000
182+++ new/gcc/testsuite/gcc.dg/torture/pr49030.c 1970-01-01 00:00:00 +0000
183@@ -1,19 +0,0 @@
184-void
185-sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
186- unsigned long dst_skip)
187-{
188- long long y;
189- while (nsamples--)
190- {
191- y = (long long) (*src * 8388608.0f) << 8;
192- if (y > 2147483647) {
193- *(int *) dst = 2147483647;
194- } else if (y < -2147483647 - 1) {
195- *(int *) dst = -2147483647 - 1;
196- } else {
197- *(int *) dst = (int) y;
198- }
199- dst += dst_skip;
200- src++;
201- }
202-}
203
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106814.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106814.patch
deleted file mode 100644
index 91b2191cb..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106814.patch
+++ /dev/null
@@ -1,80 +0,0 @@
12011-09-22 Revital Eres <revital.eres@linaro.org>
2
3 gcc/
4 Backport from trunk -r178804:
5 modulo-sched.c (remove_node_from_ps): Return void
6 instead of bool.
7 (optimize_sc): Adjust call to remove_node_from_ps.
8 (sms_schedule): Add print info.
9
10=== modified file 'gcc/modulo-sched.c'
11--- old/gcc/modulo-sched.c 2011-08-09 04:51:48 +0000
12+++ new/gcc/modulo-sched.c 2011-09-14 11:06:06 +0000
13@@ -211,7 +211,7 @@
14 static bool try_scheduling_node_in_cycle (partial_schedule_ptr, ddg_node_ptr,
15 int, int, sbitmap, int *, sbitmap,
16 sbitmap);
17-static bool remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
18+static void remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
19
20 #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
21 #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
22@@ -834,8 +834,7 @@
23 if (next_ps_i->node->cuid == g->closing_branch->cuid)
24 break;
25
26- gcc_assert (next_ps_i);
27- gcc_assert (remove_node_from_ps (ps, next_ps_i));
28+ remove_node_from_ps (ps, next_ps_i);
29 success =
30 try_scheduling_node_in_cycle (ps, g->closing_branch,
31 g->closing_branch->cuid, c,
32@@ -1485,8 +1484,8 @@
33 if (dump_file)
34 {
35 fprintf (dump_file,
36- "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
37- stage_count);
38+ "%s:%d SMS succeeded %d %d (with ii, sc)\n",
39+ insn_file (tail), insn_line (tail), ps->ii, stage_count);
40 print_partial_schedule (ps, dump_file);
41 }
42
43@@ -2810,22 +2809,18 @@
44 }
45
46
47-/* Removes the given PS_INSN from the partial schedule. Returns false if the
48- node is not found in the partial schedule, else returns true. */
49-static bool
50+/* Removes the given PS_INSN from the partial schedule. */
51+static void
52 remove_node_from_ps (partial_schedule_ptr ps, ps_insn_ptr ps_i)
53 {
54 int row;
55
56- if (!ps || !ps_i)
57- return false;
58-
59+ gcc_assert (ps && ps_i);
60+
61 row = SMODULO (ps_i->cycle, ps->ii);
62 if (! ps_i->prev_in_row)
63 {
64- if (ps_i != ps->rows[row])
65- return false;
66-
67+ gcc_assert (ps_i == ps->rows[row]);
68 ps->rows[row] = ps_i->next_in_row;
69 if (ps->rows[row])
70 ps->rows[row]->prev_in_row = NULL;
71@@ -2839,7 +2834,7 @@
72
73 ps->rows_length[row] -= 1;
74 free (ps_i);
75- return true;
76+ return;
77 }
78
79 /* Unlike what literature describes for modulo scheduling (which focuses
80
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106815.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106815.patch
deleted file mode 100644
index 16779bbf1..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106815.patch
+++ /dev/null
@@ -1,528 +0,0 @@
12011-09-25 Ira Rosen <ira.rosen@linaro.org>
2
3 gcc/testsuite/
4 * lib/target-supports.exp (check_effective_target_vect_multiple_sizes):
5 Replace check_effective_target_arm_neon with
6 check_effective_target_arm_neon_ok.
7
8 Backport from mainline:
9
10 2011-09-06 Ira Rosen <ira.rosen@linaro.org>
11
12 gcc/
13 * config/arm/arm.c (arm_preferred_simd_mode): Check
14 TARGET_NEON_VECTORIZE_DOUBLE instead of
15 TARGET_NEON_VECTORIZE_QUAD.
16 (arm_autovectorize_vector_sizes): Likewise.
17 * config/arm/arm.opt (mvectorize-with-neon-quad): Make inverse
18 mask of mvectorize-with-neon-double. Add RejectNegative.
19 (mvectorize-with-neon-double): New.
20
21 gcc/testsuite/
22 * lib/target-supports.exp (check_effective_target_vect_multiple_sizes):
23 New procedure.
24 (add_options_for_quad_vectors): Replace with ...
25 (add_options_for_double_vectors): ... this.
26 * gfortran.dg/vect/pr19049.f90: Expect more printings on targets that
27 support multiple vector sizes since the vectorizer attempts to
28 vectorize with both vector sizes.
29 * gcc.dg/vect/no-vfa-vect-79.c,
30 gcc.dg/vect/no-vfa-vect-102a.c, gcc.dg/vect/vect-outer-1a.c,
31 gcc.dg/vect/vect-outer-1b.c, gcc.dg/vect/vect-outer-2b.c,
32 gcc.dg/vect/vect-outer-3a.c, gcc.dg/vect/no-vfa-vect-37.c,
33 gcc.dg/vect/vect-outer-3b.c, gcc.dg/vect/no-vfa-vect-101.c,
34 gcc.dg/vect/no-vfa-vect-102.c, gcc.dg/vect/vect-reduc-dot-s8b.c,
35 gcc.dg/vect/vect-outer-1.c, gcc.dg/vect/vect-104.c: Likewise.
36 * gcc.dg/vect/vect-42.c: Run with 64 bit vectors if applicable.
37 * gcc.dg/vect/vect-multitypes-6.c, gcc.dg/vect/vect-52.c,
38 gcc.dg/vect/vect-54.c, gcc.dg/vect/vect-46.c, gcc.dg/vect/vect-48.c,
39 gcc.dg/vect/vect-96.c, gcc.dg/vect/vect-multitypes-3.c,
40 gcc.dg/vect/vect-40.c: Likewise.
41 * gcc.dg/vect/vect-outer-5.c: Remove quad-vectors option as
42 redundant.
43 * gcc.dg/vect/vect-109.c, gcc.dg/vect/vect-peel-1.c,
44 gcc.dg/vect/vect-peel-2.c, gcc.dg/vect/slp-25.c,
45 gcc.dg/vect/vect-multitypes-1.c, gcc.dg/vect/slp-3.c,
46 gcc.dg/vect/no-vfa-pr29145.c, gcc.dg/vect/vect-multitypes-4.c:
47 Likewise.
48 * gcc.dg/vect/vect-peel-4.c: Make ia global.
49
50=== modified file 'gcc/config/arm/arm.c'
51--- old/gcc/config/arm/arm.c 2011-09-15 09:45:31 +0000
52+++ new/gcc/config/arm/arm.c 2011-09-19 07:44:24 +0000
53@@ -22974,7 +22974,7 @@
54 return false;
55 }
56
57-/* Use the option -mvectorize-with-neon-quad to override the use of doubleword
58+/* Use the option -mvectorize-with-neon-double to override the use of quardword
59 registers when autovectorizing for Neon, at least until multiple vector
60 widths are supported properly by the middle-end. */
61
62@@ -22985,15 +22985,15 @@
63 switch (mode)
64 {
65 case SFmode:
66- return TARGET_NEON_VECTORIZE_QUAD ? V4SFmode : V2SFmode;
67+ return TARGET_NEON_VECTORIZE_DOUBLE ? V2SFmode : V4SFmode;
68 case SImode:
69- return TARGET_NEON_VECTORIZE_QUAD ? V4SImode : V2SImode;
70+ return TARGET_NEON_VECTORIZE_DOUBLE ? V2SImode : V4SImode;
71 case HImode:
72- return TARGET_NEON_VECTORIZE_QUAD ? V8HImode : V4HImode;
73+ return TARGET_NEON_VECTORIZE_DOUBLE ? V4HImode : V8HImode;
74 case QImode:
75- return TARGET_NEON_VECTORIZE_QUAD ? V16QImode : V8QImode;
76+ return TARGET_NEON_VECTORIZE_DOUBLE ? V8QImode : V16QImode;
77 case DImode:
78- if (TARGET_NEON_VECTORIZE_QUAD)
79+ if (!TARGET_NEON_VECTORIZE_DOUBLE)
80 return V2DImode;
81 break;
82
83@@ -24226,7 +24226,7 @@
84 static unsigned int
85 arm_autovectorize_vector_sizes (void)
86 {
87- return TARGET_NEON_VECTORIZE_QUAD ? 16 | 8 : 0;
88+ return TARGET_NEON_VECTORIZE_DOUBLE ? 0 : (16 | 8);
89 }
90
91 static bool
92
93=== modified file 'gcc/config/arm/arm.opt'
94--- old/gcc/config/arm/arm.opt 2009-06-18 11:24:10 +0000
95+++ new/gcc/config/arm/arm.opt 2011-09-19 07:44:24 +0000
96@@ -158,9 +158,13 @@
97 Assume big endian bytes, little endian words
98
99 mvectorize-with-neon-quad
100-Target Report Mask(NEON_VECTORIZE_QUAD)
101+Target Report RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE)
102 Use Neon quad-word (rather than double-word) registers for vectorization
103
104+mvectorize-with-neon-double
105+Target Report RejectNegative Mask(NEON_VECTORIZE_DOUBLE)
106+Use Neon double-word (rather than quad-word) registers for vectorization
107+
108 mword-relocations
109 Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
110 Only generate absolute relocations on word sized values.
111
112=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c'
113--- old/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c 2011-04-28 11:46:58 +0000
114+++ new/gcc/testsuite/gcc.dg/vect/no-vfa-pr29145.c 2011-09-19 07:44:24 +0000
115@@ -1,5 +1,4 @@
116 /* { dg-require-effective-target vect_int } */
117-/* { dg-add-options quad_vectors } */
118
119 #include <stdarg.h>
120 #include "tree-vect.h"
121
122=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-vect-101.c'
123--- old/gcc/testsuite/gcc.dg/vect/no-vfa-vect-101.c 2007-09-04 12:05:19 +0000
124+++ new/gcc/testsuite/gcc.dg/vect/no-vfa-vect-101.c 2011-09-19 07:44:24 +0000
125@@ -45,6 +45,7 @@
126 }
127
128 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } } */
129-/* { dg-final { scan-tree-dump-times "can't determine dependence" 1 "vect" } } */
130+/* { dg-final { scan-tree-dump-times "can't determine dependence" 1 "vect" { xfail vect_multiple_sizes } } } */
131+/* { dg-final { scan-tree-dump-times "can't determine dependence" 2 "vect" { target vect_multiple_sizes } } } */
132 /* { dg-final { cleanup-tree-dump "vect" } } */
133
134
135=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-vect-102.c'
136--- old/gcc/testsuite/gcc.dg/vect/no-vfa-vect-102.c 2007-09-12 07:48:44 +0000
137+++ new/gcc/testsuite/gcc.dg/vect/no-vfa-vect-102.c 2011-09-19 07:44:24 +0000
138@@ -53,6 +53,7 @@
139 }
140
141 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } } */
142-/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 1 "vect" } } */
143+/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 1 "vect" { xfail vect_multiple_sizes } } } */
144+/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 2 "vect" { target vect_multiple_sizes } } } */
145 /* { dg-final { cleanup-tree-dump "vect" } } */
146
147
148=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-vect-102a.c'
149--- old/gcc/testsuite/gcc.dg/vect/no-vfa-vect-102a.c 2007-09-12 07:48:44 +0000
150+++ new/gcc/testsuite/gcc.dg/vect/no-vfa-vect-102a.c 2011-09-19 07:44:24 +0000
151@@ -53,6 +53,7 @@
152 }
153
154 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } } */
155-/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 1 "vect" } } */
156+/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 1 "vect" { xfail vect_multiple_sizes } } } */
157+/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 2 "vect" { target vect_multiple_sizes } } } */
158 /* { dg-final { cleanup-tree-dump "vect" } } */
159
160
161=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-vect-37.c'
162--- old/gcc/testsuite/gcc.dg/vect/no-vfa-vect-37.c 2009-05-08 12:39:01 +0000
163+++ new/gcc/testsuite/gcc.dg/vect/no-vfa-vect-37.c 2011-09-19 07:44:24 +0000
164@@ -58,5 +58,6 @@
165 If/when the aliasing problems are resolved, unalignment may
166 prevent vectorization on some targets. */
167 /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { xfail *-*-* } } } */
168-/* { dg-final { scan-tree-dump-times "can't determine dependence between" 2 "vect" } } */
169+/* { dg-final { scan-tree-dump-times "can't determine dependence" 2 "vect" { xfail vect_multiple_sizes } } } */
170+/* { dg-final { scan-tree-dump-times "can't determine dependence" 4 "vect" { target vect_multiple_sizes } } } */
171 /* { dg-final { cleanup-tree-dump "vect" } } */
172
173=== modified file 'gcc/testsuite/gcc.dg/vect/no-vfa-vect-79.c'
174--- old/gcc/testsuite/gcc.dg/vect/no-vfa-vect-79.c 2009-05-08 12:39:01 +0000
175+++ new/gcc/testsuite/gcc.dg/vect/no-vfa-vect-79.c 2011-09-19 07:44:24 +0000
176@@ -46,5 +46,6 @@
177 If/when the aliasing problems are resolved, unalignment may
178 prevent vectorization on some targets. */
179 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail *-*-* } } } */
180-/* { dg-final { scan-tree-dump-times "can't determine dependence between" 1 "vect" } } */
181+/* { dg-final { scan-tree-dump-times "can't determine dependence" 1 "vect" { xfail vect_multiple_sizes } } } */
182+/* { dg-final { scan-tree-dump-times "can't determine dependence" 2 "vect" { target vect_multiple_sizes } } } */
183 /* { dg-final { cleanup-tree-dump "vect" } } */
184
185=== modified file 'gcc/testsuite/gcc.dg/vect/slp-25.c'
186--- old/gcc/testsuite/gcc.dg/vect/slp-25.c 2010-10-04 14:59:30 +0000
187+++ new/gcc/testsuite/gcc.dg/vect/slp-25.c 2011-09-19 07:44:24 +0000
188@@ -1,5 +1,4 @@
189 /* { dg-require-effective-target vect_int } */
190-/* { dg-add-options quad_vectors } */
191
192 #include <stdarg.h>
193 #include "tree-vect.h"
194
195=== modified file 'gcc/testsuite/gcc.dg/vect/slp-3.c'
196--- old/gcc/testsuite/gcc.dg/vect/slp-3.c 2011-04-28 11:46:58 +0000
197+++ new/gcc/testsuite/gcc.dg/vect/slp-3.c 2011-09-19 07:44:24 +0000
198@@ -1,5 +1,4 @@
199 /* { dg-require-effective-target vect_int } */
200-/* { dg-add-options quad_vectors } */
201
202 #include <stdarg.h>
203 #include "tree-vect.h"
204
205=== modified file 'gcc/testsuite/gcc.dg/vect/vect-104.c'
206--- old/gcc/testsuite/gcc.dg/vect/vect-104.c 2007-09-12 07:48:44 +0000
207+++ new/gcc/testsuite/gcc.dg/vect/vect-104.c 2011-09-19 07:44:24 +0000
208@@ -64,6 +64,7 @@
209 }
210
211 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } } */
212-/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 1 "vect" } } */
213+/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 1 "vect" { xfail vect_multiple_sizes } } } */
214+/* { dg-final { scan-tree-dump-times "possible dependence between data-refs" 2 "vect" { target vect_multiple_sizes } } } */
215 /* { dg-final { cleanup-tree-dump "vect" } } */
216
217
218=== modified file 'gcc/testsuite/gcc.dg/vect/vect-109.c'
219--- old/gcc/testsuite/gcc.dg/vect/vect-109.c 2010-10-04 14:59:30 +0000
220+++ new/gcc/testsuite/gcc.dg/vect/vect-109.c 2011-09-19 07:44:24 +0000
221@@ -1,5 +1,4 @@
222 /* { dg-require-effective-target vect_int } */
223-/* { dg-add-options quad_vectors } */
224
225 #include <stdarg.h>
226 #include "tree-vect.h"
227
228=== modified file 'gcc/testsuite/gcc.dg/vect/vect-40.c'
229--- old/gcc/testsuite/gcc.dg/vect/vect-40.c 2009-05-25 14:18:21 +0000
230+++ new/gcc/testsuite/gcc.dg/vect/vect-40.c 2011-09-19 07:44:24 +0000
231@@ -1,4 +1,5 @@
232 /* { dg-require-effective-target vect_float } */
233+/* { dg-add-options double_vectors } */
234
235 #include <stdarg.h>
236 #include "tree-vect.h"
237
238=== modified file 'gcc/testsuite/gcc.dg/vect/vect-42.c'
239--- old/gcc/testsuite/gcc.dg/vect/vect-42.c 2010-10-04 14:59:30 +0000
240+++ new/gcc/testsuite/gcc.dg/vect/vect-42.c 2011-09-19 07:44:24 +0000
241@@ -1,4 +1,5 @@
242 /* { dg-require-effective-target vect_float } */
243+/* { dg-add-options double_vectors } */
244
245 #include <stdarg.h>
246 #include "tree-vect.h"
247
248=== modified file 'gcc/testsuite/gcc.dg/vect/vect-46.c'
249--- old/gcc/testsuite/gcc.dg/vect/vect-46.c 2009-05-25 14:18:21 +0000
250+++ new/gcc/testsuite/gcc.dg/vect/vect-46.c 2011-09-19 07:44:24 +0000
251@@ -1,4 +1,5 @@
252 /* { dg-require-effective-target vect_float } */
253+/* { dg-add-options double_vectors } */
254
255 #include <stdarg.h>
256 #include "tree-vect.h"
257
258=== modified file 'gcc/testsuite/gcc.dg/vect/vect-48.c'
259--- old/gcc/testsuite/gcc.dg/vect/vect-48.c 2009-11-04 10:22:22 +0000
260+++ new/gcc/testsuite/gcc.dg/vect/vect-48.c 2011-09-19 07:44:24 +0000
261@@ -1,4 +1,5 @@
262 /* { dg-require-effective-target vect_float } */
263+/* { dg-add-options double_vectors } */
264
265 #include <stdarg.h>
266 #include "tree-vect.h"
267
268=== modified file 'gcc/testsuite/gcc.dg/vect/vect-52.c'
269--- old/gcc/testsuite/gcc.dg/vect/vect-52.c 2009-11-04 10:22:22 +0000
270+++ new/gcc/testsuite/gcc.dg/vect/vect-52.c 2011-09-19 07:44:24 +0000
271@@ -1,4 +1,5 @@
272 /* { dg-require-effective-target vect_float } */
273+/* { dg-add-options double_vectors } */
274
275 #include <stdarg.h>
276 #include "tree-vect.h"
277
278=== modified file 'gcc/testsuite/gcc.dg/vect/vect-54.c'
279--- old/gcc/testsuite/gcc.dg/vect/vect-54.c 2009-10-27 11:46:07 +0000
280+++ new/gcc/testsuite/gcc.dg/vect/vect-54.c 2011-09-19 07:44:24 +0000
281@@ -1,4 +1,5 @@
282 /* { dg-require-effective-target vect_float } */
283+/* { dg-add-options double_vectors } */
284
285 #include <stdarg.h>
286 #include "tree-vect.h"
287
288=== modified file 'gcc/testsuite/gcc.dg/vect/vect-96.c'
289--- old/gcc/testsuite/gcc.dg/vect/vect-96.c 2010-10-04 14:59:30 +0000
290+++ new/gcc/testsuite/gcc.dg/vect/vect-96.c 2011-09-19 07:44:24 +0000
291@@ -1,4 +1,5 @@
292 /* { dg-require-effective-target vect_int } */
293+/* { dg-add-options double_vectors } */
294
295 #include <stdarg.h>
296 #include "tree-vect.h"
297
298=== modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c'
299--- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c 2010-10-04 14:59:30 +0000
300+++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c 2011-09-19 07:44:24 +0000
301@@ -1,5 +1,4 @@
302 /* { dg-require-effective-target vect_int } */
303-/* { dg-add-options quad_vectors } */
304
305 #include <stdarg.h>
306 #include "tree-vect.h"
307
308=== modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-3.c'
309--- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-3.c 2009-11-04 10:22:22 +0000
310+++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-3.c 2011-09-19 07:44:24 +0000
311@@ -1,4 +1,5 @@
312 /* { dg-require-effective-target vect_int } */
313+/* { dg-add-options double_vectors } */
314
315 #include <stdarg.h>
316 #include "tree-vect.h"
317
318=== modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c'
319--- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c 2010-10-04 14:59:30 +0000
320+++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c 2011-09-19 07:44:24 +0000
321@@ -1,5 +1,4 @@
322 /* { dg-require-effective-target vect_int } */
323-/* { dg-add-options quad_vectors } */
324
325 #include <stdarg.h>
326 #include "tree-vect.h"
327
328=== modified file 'gcc/testsuite/gcc.dg/vect/vect-multitypes-6.c'
329--- old/gcc/testsuite/gcc.dg/vect/vect-multitypes-6.c 2009-11-10 18:01:22 +0000
330+++ new/gcc/testsuite/gcc.dg/vect/vect-multitypes-6.c 2011-09-19 07:44:24 +0000
331@@ -1,4 +1,5 @@
332 /* { dg-require-effective-target vect_int } */
333+/* { dg-add-options double_vectors } */
334
335 #include <stdarg.h>
336 #include "tree-vect.h"
337
338=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-1.c'
339--- old/gcc/testsuite/gcc.dg/vect/vect-outer-1.c 2009-05-08 12:39:01 +0000
340+++ new/gcc/testsuite/gcc.dg/vect/vect-outer-1.c 2011-09-19 07:44:24 +0000
341@@ -22,5 +22,6 @@
342 }
343
344 /* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED" 1 "vect" { xfail *-*-* } } } */
345-/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" } } */
346+/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" { xfail vect_multiple_sizes } } } */
347+/* { dg-final { scan-tree-dump-times "strided access in outer loop" 2 "vect" { target vect_multiple_sizes } } } */
348 /* { dg-final { cleanup-tree-dump "vect" } } */
349
350=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-1a.c'
351--- old/gcc/testsuite/gcc.dg/vect/vect-outer-1a.c 2009-06-16 06:21:12 +0000
352+++ new/gcc/testsuite/gcc.dg/vect/vect-outer-1a.c 2011-09-19 07:44:24 +0000
353@@ -20,5 +20,6 @@
354 }
355
356 /* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED" 1 "vect" { xfail *-*-* } } } */
357-/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" } } */
358+/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" { xfail vect_multiple_sizes } } } */
359+/* { dg-final { scan-tree-dump-times "strided access in outer loop" 2 "vect" { target vect_multiple_sizes } } } */
360 /* { dg-final { cleanup-tree-dump "vect" } } */
361
362=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-1b.c'
363--- old/gcc/testsuite/gcc.dg/vect/vect-outer-1b.c 2007-08-19 11:02:48 +0000
364+++ new/gcc/testsuite/gcc.dg/vect/vect-outer-1b.c 2011-09-19 07:44:24 +0000
365@@ -22,5 +22,6 @@
366 }
367
368 /* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED" 1 "vect" { xfail *-*-* } } } */
369-/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" } } */
370+/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" { xfail vect_multiple_sizes } } } */
371+/* { dg-final { scan-tree-dump-times "strided access in outer loop" 2 "vect" { target vect_multiple_sizes } } } */
372 /* { dg-final { cleanup-tree-dump "vect" } } */
373
374=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-2b.c'
375--- old/gcc/testsuite/gcc.dg/vect/vect-outer-2b.c 2009-05-08 12:39:01 +0000
376+++ new/gcc/testsuite/gcc.dg/vect/vect-outer-2b.c 2011-09-19 07:44:24 +0000
377@@ -37,5 +37,6 @@
378 return 0;
379 }
380
381-/* { dg-final { scan-tree-dump-times "strided access in outer loop." 1 "vect" } } */
382+/* { dg-final { scan-tree-dump-times "strided access in outer loop" 1 "vect" { xfail vect_multiple_sizes } } } */
383+/* { dg-final { scan-tree-dump-times "strided access in outer loop" 2 "vect" { target vect_multiple_sizes } } } */
384 /* { dg-final { cleanup-tree-dump "vect" } } */
385
386=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-3a.c'
387--- old/gcc/testsuite/gcc.dg/vect/vect-outer-3a.c 2009-05-08 12:39:01 +0000
388+++ new/gcc/testsuite/gcc.dg/vect/vect-outer-3a.c 2011-09-19 07:44:24 +0000
389@@ -49,5 +49,6 @@
390 }
391
392 /* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED" 1 "vect" { xfail vect_no_align } } } */
393-/* { dg-final { scan-tree-dump-times "step doesn't divide the vector-size" 2 "vect" } } */
394+/* { dg-final { scan-tree-dump-times "step doesn't divide the vector-size" 2 "vect" { xfail vect_multiple_sizes } } } */
395+/* { dg-final { scan-tree-dump-times "step doesn't divide the vector-size" 3 "vect" { target vect_multiple_sizes } } } */
396 /* { dg-final { cleanup-tree-dump "vect" } } */
397
398=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-3b.c'
399--- old/gcc/testsuite/gcc.dg/vect/vect-outer-3b.c 2009-05-08 12:39:01 +0000
400+++ new/gcc/testsuite/gcc.dg/vect/vect-outer-3b.c 2011-09-19 07:44:24 +0000
401@@ -49,5 +49,6 @@
402 }
403
404 /* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED" 1 "vect" { xfail *-*-* } } } */
405-/* { dg-final { scan-tree-dump-times "strided access in outer loop" 2 "vect" } } */
406+/* { dg-final { scan-tree-dump-times "strided access in outer loop" 2 "vect" { xfail vect_multiple_sizes } } } */
407+/* { dg-final { scan-tree-dump-times "strided access in outer loop" 4 "vect" { target vect_multiple_sizes } } } */
408 /* { dg-final { cleanup-tree-dump "vect" } } */
409
410=== modified file 'gcc/testsuite/gcc.dg/vect/vect-outer-5.c'
411--- old/gcc/testsuite/gcc.dg/vect/vect-outer-5.c 2011-04-28 11:46:58 +0000
412+++ new/gcc/testsuite/gcc.dg/vect/vect-outer-5.c 2011-09-19 07:44:24 +0000
413@@ -1,5 +1,4 @@
414 /* { dg-require-effective-target vect_float } */
415-/* { dg-add-options quad_vectors } */
416
417 #include <stdarg.h>
418 #include <signal.h>
419
420=== modified file 'gcc/testsuite/gcc.dg/vect/vect-peel-1.c'
421--- old/gcc/testsuite/gcc.dg/vect/vect-peel-1.c 2011-01-10 12:41:40 +0000
422+++ new/gcc/testsuite/gcc.dg/vect/vect-peel-1.c 2011-09-19 07:44:24 +0000
423@@ -1,5 +1,4 @@
424 /* { dg-require-effective-target vect_int } */
425-/* { dg-add-options quad_vectors } */
426
427 #include <stdarg.h>
428 #include "tree-vect.h"
429
430=== modified file 'gcc/testsuite/gcc.dg/vect/vect-peel-2.c'
431--- old/gcc/testsuite/gcc.dg/vect/vect-peel-2.c 2011-01-10 12:41:40 +0000
432+++ new/gcc/testsuite/gcc.dg/vect/vect-peel-2.c 2011-09-19 07:44:24 +0000
433@@ -1,5 +1,4 @@
434 /* { dg-require-effective-target vect_int } */
435-/* { dg-add-options quad_vectors } */
436
437 #include <stdarg.h>
438 #include "tree-vect.h"
439
440=== modified file 'gcc/testsuite/gcc.dg/vect/vect-peel-4.c'
441--- old/gcc/testsuite/gcc.dg/vect/vect-peel-4.c 2011-01-10 12:41:40 +0000
442+++ new/gcc/testsuite/gcc.dg/vect/vect-peel-4.c 2011-09-19 07:44:24 +0000
443@@ -6,12 +6,12 @@
444 #define N 128
445
446 int ib[N+7];
447+int ia[N+1];
448
449 __attribute__ ((noinline))
450 int main1 ()
451 {
452 int i;
453- int ia[N+1];
454
455 /* Don't peel keeping one load and the store aligned. */
456 for (i = 0; i <= N; i++)
457
458=== modified file 'gcc/testsuite/gcc.dg/vect/vect-reduc-dot-s8b.c'
459--- old/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-s8b.c 2010-05-27 12:23:45 +0000
460+++ new/gcc/testsuite/gcc.dg/vect/vect-reduc-dot-s8b.c 2011-09-19 07:44:24 +0000
461@@ -58,7 +58,8 @@
462 }
463
464 /* { dg-final { scan-tree-dump-times "vect_recog_dot_prod_pattern: detected" 1 "vect" { xfail *-*-* } } } */
465-/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 1 "vect" } } */
466+/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 1 "vect" { xfail vect_multiple_sizes } } } */
467+/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 2 "vect" { target vect_multiple_sizes } } } */
468
469 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail *-*-* } } } */
470
471
472=== modified file 'gcc/testsuite/gfortran.dg/vect/pr19049.f90'
473--- old/gcc/testsuite/gfortran.dg/vect/pr19049.f90 2005-07-25 11:05:07 +0000
474+++ new/gcc/testsuite/gfortran.dg/vect/pr19049.f90 2011-09-19 07:44:24 +0000
475@@ -19,6 +19,7 @@
476 end
477
478 ! { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" } }
479-! { dg-final { scan-tree-dump-times "complicated access pattern" 1 "vect" } }
480+! { dg-final { scan-tree-dump-times "complicated access pattern" 1 "vect" { xfail vect_multiple_sizes } } }
481+! { dg-final { scan-tree-dump-times "complicated access pattern" 2 "vect" { target vect_multiple_sizes } } }
482 ! { dg-final { cleanup-tree-dump "vect" } }
483
484
485=== modified file 'gcc/testsuite/lib/target-supports.exp'
486--- old/gcc/testsuite/lib/target-supports.exp 2011-08-13 08:32:32 +0000
487+++ new/gcc/testsuite/lib/target-supports.exp 2011-09-20 07:54:28 +0000
488@@ -3265,6 +3265,24 @@
489 }]
490 }
491
492+# Return 1 if the target supports multiple vector sizes
493+
494+proc check_effective_target_vect_multiple_sizes { } {
495+ global et_vect_multiple_sizes
496+
497+ if [info exists et_vect_multiple_sizes_saved] {
498+ verbose "check_effective_target_vect_multiple_sizes: using cached result" 2
499+ } else {
500+ set et_vect_multiple_sizes_saved 0
501+ if { ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]) } {
502+ set et_vect_multiple_sizes_saved 1
503+ }
504+ }
505+
506+ verbose "check_effective_target_vect_multiple_sizes: returning $et_vect_multiple_sizes_saved" 2
507+ return $et_vect_multiple_sizes_saved
508+}
509+
510 # Return 1 if the target supports section-anchors
511
512 proc check_effective_target_section_anchors { } {
513@@ -3648,11 +3666,11 @@
514 return $flags
515 }
516
517-# Add to FLAGS the flags needed to enable 128-bit vectors.
518+# Add to FLAGS the flags needed to enable 64-bit vectors.
519
520-proc add_options_for_quad_vectors { flags } {
521+proc add_options_for_double_vectors { flags } {
522 if [is-effective-target arm_neon_ok] {
523- return "$flags -mvectorize-with-neon-quad"
524+ return "$flags -mvectorize-with-neon-double"
525 }
526
527 return $flags
528
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106816.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106816.patch
deleted file mode 100644
index 2f70b1b9c..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106816.patch
+++ /dev/null
@@ -1,387 +0,0 @@
12011-09-28 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-09-28 Richard Sandiford <richard.sandiford@linaro.org>
7
8 * config/arm/neon.md (neon_move_lo_quad_<mode>): Delete.
9 (neon_move_hi_quad_<mode>): Likewise.
10 (move_hi_quad_<mode>, move_lo_quad_<mode>): Use subreg moves.
11
122011-09-28 Richard Sandiford <richard.sandiford@linaro.org>
13
14 gcc/
15 Backport from mainline:
16
17 2011-09-27 Richard Sandiford <richard.sandiford@linaro.org>
18
19 * config/arm/neon.md (neon_vget_highv16qi, neon_vget_highv8hi)
20 (neon_vget_highv4si, neon_vget_highv4sf, neon_vget_highv2di)
21 (neon_vget_lowv16qi, neon_vget_lowv8hi, neon_vget_lowv4si)
22 (neon_vget_lowv4sf, neon_vget_lowv2di): Turn into define_expands
23 that produce subreg moves. Define using VQX iterators.
24
252011-09-28 Richard Sandiford <richard.sandiford@linaro.org>
26
27 gcc/
28 Backport from mainline:
29
30 2011-09-14 Richard Sandiford <richard.sandiford@linaro.org>
31
32 * simplify-rtx.c (simplify_subreg): Check that the inner mode is
33 a scalar integer before applying integer-only optimisations to
34 inner arithmetic.
35
36=== modified file 'gcc/config/arm/neon.md'
37--- old/gcc/config/arm/neon.md 2011-07-04 14:03:49 +0000
38+++ new/gcc/config/arm/neon.md 2011-09-28 15:14:59 +0000
39@@ -1235,66 +1235,14 @@
40 (const_string "neon_int_1") (const_string "neon_int_5")))]
41 )
42
43-; FIXME: We wouldn't need the following insns if we could write subregs of
44-; vector registers. Make an attempt at removing unnecessary moves, though
45-; we're really at the mercy of the register allocator.
46-
47-(define_insn "neon_move_lo_quad_<mode>"
48- [(set (match_operand:ANY128 0 "s_register_operand" "+w")
49- (vec_concat:ANY128
50- (match_operand:<V_HALF> 1 "s_register_operand" "w")
51- (vec_select:<V_HALF>
52- (match_dup 0)
53- (match_operand:ANY128 2 "vect_par_constant_high" ""))))]
54- "TARGET_NEON"
55-{
56- int dest = REGNO (operands[0]);
57- int src = REGNO (operands[1]);
58-
59- if (dest != src)
60- return "vmov\t%e0, %P1";
61- else
62- return "";
63-}
64- [(set_attr "neon_type" "neon_bp_simple")]
65-)
66-
67-(define_insn "neon_move_hi_quad_<mode>"
68- [(set (match_operand:ANY128 0 "s_register_operand" "+w")
69- (vec_concat:ANY128
70- (vec_select:<V_HALF>
71- (match_dup 0)
72- (match_operand:ANY128 2 "vect_par_constant_low" ""))
73- (match_operand:<V_HALF> 1 "s_register_operand" "w")))]
74-
75- "TARGET_NEON"
76-{
77- int dest = REGNO (operands[0]);
78- int src = REGNO (operands[1]);
79-
80- if (dest != src)
81- return "vmov\t%f0, %P1";
82- else
83- return "";
84-}
85- [(set_attr "neon_type" "neon_bp_simple")]
86-)
87-
88 (define_expand "move_hi_quad_<mode>"
89 [(match_operand:ANY128 0 "s_register_operand" "")
90 (match_operand:<V_HALF> 1 "s_register_operand" "")]
91 "TARGET_NEON"
92 {
93- rtvec v = rtvec_alloc (<V_mode_nunits>/2);
94- rtx t1;
95- int i;
96-
97- for (i=0; i < (<V_mode_nunits>/2); i++)
98- RTVEC_ELT (v, i) = GEN_INT (i);
99-
100- t1 = gen_rtx_PARALLEL (<MODE>mode, v);
101- emit_insn (gen_neon_move_hi_quad_<mode> (operands[0], operands[1], t1));
102-
103+ emit_move_insn (simplify_gen_subreg (<V_HALF>mode, operands[0], <MODE>mode,
104+ GET_MODE_SIZE (<V_HALF>mode)),
105+ operands[1]);
106 DONE;
107 })
108
109@@ -1303,16 +1251,9 @@
110 (match_operand:<V_HALF> 1 "s_register_operand" "")]
111 "TARGET_NEON"
112 {
113- rtvec v = rtvec_alloc (<V_mode_nunits>/2);
114- rtx t1;
115- int i;
116-
117- for (i=0; i < (<V_mode_nunits>/2); i++)
118- RTVEC_ELT (v, i) = GEN_INT ((<V_mode_nunits>/2) + i);
119-
120- t1 = gen_rtx_PARALLEL (<MODE>mode, v);
121- emit_insn (gen_neon_move_lo_quad_<mode> (operands[0], operands[1], t1));
122-
123+ emit_move_insn (simplify_gen_subreg (<V_HALF>mode, operands[0],
124+ <MODE>mode, 0),
125+ operands[1]);
126 DONE;
127 })
128
129@@ -2950,183 +2891,27 @@
130 (set_attr "neon_type" "neon_bp_simple")]
131 )
132
133-(define_insn "neon_vget_highv16qi"
134- [(set (match_operand:V8QI 0 "s_register_operand" "=w")
135- (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
136- (parallel [(const_int 8) (const_int 9)
137- (const_int 10) (const_int 11)
138- (const_int 12) (const_int 13)
139- (const_int 14) (const_int 15)])))]
140- "TARGET_NEON"
141-{
142- int dest = REGNO (operands[0]);
143- int src = REGNO (operands[1]);
144-
145- if (dest != src + 2)
146- return "vmov\t%P0, %f1";
147- else
148- return "";
149-}
150- [(set_attr "neon_type" "neon_bp_simple")]
151-)
152-
153-(define_insn "neon_vget_highv8hi"
154- [(set (match_operand:V4HI 0 "s_register_operand" "=w")
155- (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
156- (parallel [(const_int 4) (const_int 5)
157- (const_int 6) (const_int 7)])))]
158- "TARGET_NEON"
159-{
160- int dest = REGNO (operands[0]);
161- int src = REGNO (operands[1]);
162-
163- if (dest != src + 2)
164- return "vmov\t%P0, %f1";
165- else
166- return "";
167-}
168- [(set_attr "neon_type" "neon_bp_simple")]
169-)
170-
171-(define_insn "neon_vget_highv4si"
172- [(set (match_operand:V2SI 0 "s_register_operand" "=w")
173- (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
174- (parallel [(const_int 2) (const_int 3)])))]
175- "TARGET_NEON"
176-{
177- int dest = REGNO (operands[0]);
178- int src = REGNO (operands[1]);
179-
180- if (dest != src + 2)
181- return "vmov\t%P0, %f1";
182- else
183- return "";
184-}
185- [(set_attr "neon_type" "neon_bp_simple")]
186-)
187-
188-(define_insn "neon_vget_highv4sf"
189- [(set (match_operand:V2SF 0 "s_register_operand" "=w")
190- (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
191- (parallel [(const_int 2) (const_int 3)])))]
192- "TARGET_NEON"
193-{
194- int dest = REGNO (operands[0]);
195- int src = REGNO (operands[1]);
196-
197- if (dest != src + 2)
198- return "vmov\t%P0, %f1";
199- else
200- return "";
201-}
202- [(set_attr "neon_type" "neon_bp_simple")]
203-)
204-
205-(define_insn "neon_vget_highv2di"
206- [(set (match_operand:DI 0 "s_register_operand" "=w")
207- (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
208- (parallel [(const_int 1)])))]
209- "TARGET_NEON"
210-{
211- int dest = REGNO (operands[0]);
212- int src = REGNO (operands[1]);
213-
214- if (dest != src + 2)
215- return "vmov\t%P0, %f1";
216- else
217- return "";
218-}
219- [(set_attr "neon_type" "neon_bp_simple")]
220-)
221-
222-(define_insn "neon_vget_lowv16qi"
223- [(set (match_operand:V8QI 0 "s_register_operand" "=w")
224- (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
225- (parallel [(const_int 0) (const_int 1)
226- (const_int 2) (const_int 3)
227- (const_int 4) (const_int 5)
228- (const_int 6) (const_int 7)])))]
229- "TARGET_NEON"
230-{
231- int dest = REGNO (operands[0]);
232- int src = REGNO (operands[1]);
233-
234- if (dest != src)
235- return "vmov\t%P0, %e1";
236- else
237- return "";
238-}
239- [(set_attr "neon_type" "neon_bp_simple")]
240-)
241-
242-(define_insn "neon_vget_lowv8hi"
243- [(set (match_operand:V4HI 0 "s_register_operand" "=w")
244- (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
245- (parallel [(const_int 0) (const_int 1)
246- (const_int 2) (const_int 3)])))]
247- "TARGET_NEON"
248-{
249- int dest = REGNO (operands[0]);
250- int src = REGNO (operands[1]);
251-
252- if (dest != src)
253- return "vmov\t%P0, %e1";
254- else
255- return "";
256-}
257- [(set_attr "neon_type" "neon_bp_simple")]
258-)
259-
260-(define_insn "neon_vget_lowv4si"
261- [(set (match_operand:V2SI 0 "s_register_operand" "=w")
262- (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
263- (parallel [(const_int 0) (const_int 1)])))]
264- "TARGET_NEON"
265-{
266- int dest = REGNO (operands[0]);
267- int src = REGNO (operands[1]);
268-
269- if (dest != src)
270- return "vmov\t%P0, %e1";
271- else
272- return "";
273-}
274- [(set_attr "neon_type" "neon_bp_simple")]
275-)
276-
277-(define_insn "neon_vget_lowv4sf"
278- [(set (match_operand:V2SF 0 "s_register_operand" "=w")
279- (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
280- (parallel [(const_int 0) (const_int 1)])))]
281- "TARGET_NEON"
282-{
283- int dest = REGNO (operands[0]);
284- int src = REGNO (operands[1]);
285-
286- if (dest != src)
287- return "vmov\t%P0, %e1";
288- else
289- return "";
290-}
291- [(set_attr "neon_type" "neon_bp_simple")]
292-)
293-
294-(define_insn "neon_vget_lowv2di"
295- [(set (match_operand:DI 0 "s_register_operand" "=w")
296- (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
297- (parallel [(const_int 0)])))]
298- "TARGET_NEON"
299-{
300- int dest = REGNO (operands[0]);
301- int src = REGNO (operands[1]);
302-
303- if (dest != src)
304- return "vmov\t%P0, %e1";
305- else
306- return "";
307-}
308- [(set_attr "neon_type" "neon_bp_simple")]
309-)
310+(define_expand "neon_vget_high<mode>"
311+ [(match_operand:<V_HALF> 0 "s_register_operand")
312+ (match_operand:VQX 1 "s_register_operand")]
313+ "TARGET_NEON"
314+{
315+ emit_move_insn (operands[0],
316+ simplify_gen_subreg (<V_HALF>mode, operands[1], <MODE>mode,
317+ GET_MODE_SIZE (<V_HALF>mode)));
318+ DONE;
319+})
320+
321+(define_expand "neon_vget_low<mode>"
322+ [(match_operand:<V_HALF> 0 "s_register_operand")
323+ (match_operand:VQX 1 "s_register_operand")]
324+ "TARGET_NEON"
325+{
326+ emit_move_insn (operands[0],
327+ simplify_gen_subreg (<V_HALF>mode, operands[1],
328+ <MODE>mode, 0));
329+ DONE;
330+})
331
332 (define_insn "neon_vcvt<mode>"
333 [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
334
335=== modified file 'gcc/simplify-rtx.c'
336--- old/gcc/simplify-rtx.c 2011-08-13 08:32:32 +0000
337+++ new/gcc/simplify-rtx.c 2011-09-28 15:11:59 +0000
338@@ -5567,6 +5567,7 @@
339 /* Optimize SUBREG truncations of zero and sign extended values. */
340 if ((GET_CODE (op) == ZERO_EXTEND
341 || GET_CODE (op) == SIGN_EXTEND)
342+ && SCALAR_INT_MODE_P (innermode)
343 && GET_MODE_BITSIZE (outermode) < GET_MODE_BITSIZE (innermode))
344 {
345 unsigned int bitpos = subreg_lsb_1 (outermode, innermode, byte);
346@@ -5605,6 +5606,7 @@
347 if ((GET_CODE (op) == LSHIFTRT
348 || GET_CODE (op) == ASHIFTRT)
349 && SCALAR_INT_MODE_P (outermode)
350+ && SCALAR_INT_MODE_P (innermode)
351 /* Ensure that OUTERMODE is at least twice as wide as the INNERMODE
352 to avoid the possibility that an outer LSHIFTRT shifts by more
353 than the sign extension's sign_bit_copies and introduces zeros
354@@ -5624,6 +5626,7 @@
355 if ((GET_CODE (op) == LSHIFTRT
356 || GET_CODE (op) == ASHIFTRT)
357 && SCALAR_INT_MODE_P (outermode)
358+ && SCALAR_INT_MODE_P (innermode)
359 && GET_MODE_BITSIZE (outermode) < GET_MODE_BITSIZE (innermode)
360 && CONST_INT_P (XEXP (op, 1))
361 && GET_CODE (XEXP (op, 0)) == ZERO_EXTEND
362@@ -5638,6 +5641,7 @@
363 the outer subreg is effectively a truncation to the original mode. */
364 if (GET_CODE (op) == ASHIFT
365 && SCALAR_INT_MODE_P (outermode)
366+ && SCALAR_INT_MODE_P (innermode)
367 && GET_MODE_BITSIZE (outermode) < GET_MODE_BITSIZE (innermode)
368 && CONST_INT_P (XEXP (op, 1))
369 && (GET_CODE (XEXP (op, 0)) == ZERO_EXTEND
370@@ -5651,7 +5655,7 @@
371 /* Recognize a word extraction from a multi-word subreg. */
372 if ((GET_CODE (op) == LSHIFTRT
373 || GET_CODE (op) == ASHIFTRT)
374- && SCALAR_INT_MODE_P (outermode)
375+ && SCALAR_INT_MODE_P (innermode)
376 && GET_MODE_BITSIZE (outermode) >= BITS_PER_WORD
377 && GET_MODE_BITSIZE (innermode) >= (2 * GET_MODE_BITSIZE (outermode))
378 && CONST_INT_P (XEXP (op, 1))
379@@ -5673,6 +5677,7 @@
380
381 if ((GET_CODE (op) == LSHIFTRT
382 || GET_CODE (op) == ASHIFTRT)
383+ && SCALAR_INT_MODE_P (innermode)
384 && MEM_P (XEXP (op, 0))
385 && CONST_INT_P (XEXP (op, 1))
386 && GET_MODE_SIZE (outermode) < GET_MODE_SIZE (GET_MODE (op))
387
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106817.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106817.patch
deleted file mode 100644
index d44f8cf1a..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106817.patch
+++ /dev/null
@@ -1,290 +0,0 @@
12011-10-01 Revital Eres <revital.eres@linaro.org>
2
3 gcc/
4 Backport from mainline -r179380 and -r179381
5
6 * ddg.c (autoinc_var_is_used_p): New function.
7 (create_ddg_dep_from_intra_loop_link,
8 add_cross_iteration_register_deps): Call it.
9 * ddg.h (autoinc_var_is_used_p): Declare.
10 * modulo-sched.c (sms_schedule): Handle instructions with REG_INC.
11 (generate_reg_moves): Call autoinc_var_is_used_p. Skip
12 instructions that do not set a register and verify no regmoves
13 are created for !single_set instructions.
14
15 gcc/testsuite/
16
17 * gcc.dg/sms-10.c: New file
18
19=== modified file 'gcc/ddg.c'
20--- old/gcc/ddg.c 2011-07-31 11:29:10 +0000
21+++ new/gcc/ddg.c 2011-10-02 06:56:53 +0000
22@@ -145,6 +145,27 @@
23 return rtx_mem_access_p (PATTERN (insn));
24 }
25
26+/* Return true if DEF_INSN contains address being auto-inc or auto-dec
27+ which is used in USE_INSN. Otherwise return false. The result is
28+ being used to decide whether to remove the edge between def_insn and
29+ use_insn when -fmodulo-sched-allow-regmoves is set. This function
30+ doesn't need to consider the specific address register; no reg_moves
31+ will be allowed for any life range defined by def_insn and used
32+ by use_insn, if use_insn uses an address register auto-inc'ed by
33+ def_insn. */
34+bool
35+autoinc_var_is_used_p (rtx def_insn, rtx use_insn)
36+{
37+ rtx note;
38+
39+ for (note = REG_NOTES (def_insn); note; note = XEXP (note, 1))
40+ if (REG_NOTE_KIND (note) == REG_INC
41+ && reg_referenced_p (XEXP (note, 0), PATTERN (use_insn)))
42+ return true;
43+
44+ return false;
45+}
46+
47 /* Computes the dependence parameters (latency, distance etc.), creates
48 a ddg_edge and adds it to the given DDG. */
49 static void
50@@ -173,10 +194,15 @@
51 compensate for that by generating reg-moves based on the life-range
52 analysis. The anti-deps that will be deleted are the ones which
53 have true-deps edges in the opposite direction (in other words
54- the kernel has only one def of the relevant register). TODO:
55- support the removal of all anti-deps edges, i.e. including those
56+ the kernel has only one def of the relevant register).
57+ If the address that is being auto-inc or auto-dec in DEST_NODE
58+ is used in SRC_NODE then do not remove the edge to make sure
59+ reg-moves will not be created for this address.
60+ TODO: support the removal of all anti-deps edges, i.e. including those
61 whose register has multiple defs in the loop. */
62- if (flag_modulo_sched_allow_regmoves && (t == ANTI_DEP && dt == REG_DEP))
63+ if (flag_modulo_sched_allow_regmoves
64+ && (t == ANTI_DEP && dt == REG_DEP)
65+ && !autoinc_var_is_used_p (dest_node->insn, src_node->insn))
66 {
67 rtx set;
68
69@@ -302,10 +328,14 @@
70 gcc_assert (first_def_node);
71
72 /* Always create the edge if the use node is a branch in
73- order to prevent the creation of reg-moves. */
74+ order to prevent the creation of reg-moves.
75+ If the address that is being auto-inc or auto-dec in LAST_DEF
76+ is used in USE_INSN then do not remove the edge to make sure
77+ reg-moves will not be created for that address. */
78 if (DF_REF_ID (last_def) != DF_REF_ID (first_def)
79 || !flag_modulo_sched_allow_regmoves
80- || JUMP_P (use_node->insn))
81+ || JUMP_P (use_node->insn)
82+ || autoinc_var_is_used_p (DF_REF_INSN (last_def), use_insn))
83 create_ddg_dep_no_link (g, use_node, first_def_node, ANTI_DEP,
84 REG_DEP, 1);
85
86
87=== modified file 'gcc/ddg.h'
88--- old/gcc/ddg.h 2009-11-25 10:55:54 +0000
89+++ new/gcc/ddg.h 2011-10-02 06:56:53 +0000
90@@ -186,4 +186,6 @@
91 int find_nodes_on_paths (sbitmap result, ddg_ptr, sbitmap from, sbitmap to);
92 int longest_simple_path (ddg_ptr, int from, int to, sbitmap via);
93
94+bool autoinc_var_is_used_p (rtx, rtx);
95+
96 #endif /* GCC_DDG_H */
97
98=== modified file 'gcc/modulo-sched.c'
99--- old/gcc/modulo-sched.c 2011-09-14 11:06:06 +0000
100+++ new/gcc/modulo-sched.c 2011-10-02 06:56:53 +0000
101@@ -477,7 +477,12 @@
102 sbitmap *uses_of_defs;
103 rtx last_reg_move;
104 rtx prev_reg, old_reg;
105-
106+ rtx set = single_set (u->insn);
107+
108+ /* Skip instructions that do not set a register. */
109+ if ((set && !REG_P (SET_DEST (set))))
110+ continue;
111+
112 /* Compute the number of reg_moves needed for u, by looking at life
113 ranges started at u (excluding self-loops). */
114 for (e = u->out; e; e = e->next_out)
115@@ -494,6 +499,20 @@
116 && SCHED_COLUMN (e->dest) < SCHED_COLUMN (e->src))
117 nreg_moves4e--;
118
119+ if (nreg_moves4e >= 1)
120+ {
121+ /* !single_set instructions are not supported yet and
122+ thus we do not except to encounter them in the loop
123+ except from the doloop part. For the latter case
124+ we assume no regmoves are generated as the doloop
125+ instructions are tied to the branch with an edge. */
126+ gcc_assert (set);
127+ /* If the instruction contains auto-inc register then
128+ validate that the regmov is being generated for the
129+ target regsiter rather then the inc'ed register. */
130+ gcc_assert (!autoinc_var_is_used_p (u->insn, e->dest->insn));
131+ }
132+
133 nreg_moves = MAX (nreg_moves, nreg_moves4e);
134 }
135
136@@ -1266,12 +1285,10 @@
137 continue;
138 }
139
140- /* Don't handle BBs with calls or barriers or auto-increment insns
141- (to avoid creating invalid reg-moves for the auto-increment insns),
142+ /* Don't handle BBs with calls or barriers
143 or !single_set with the exception of instructions that include
144 count_reg---these instructions are part of the control part
145 that do-loop recognizes.
146- ??? Should handle auto-increment insns.
147 ??? Should handle insns defining subregs. */
148 for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn))
149 {
150@@ -1282,7 +1299,6 @@
151 || (NONDEBUG_INSN_P (insn) && !JUMP_P (insn)
152 && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE
153 && !reg_mentioned_p (count_reg, insn))
154- || (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0)
155 || (INSN_P (insn) && (set = single_set (insn))
156 && GET_CODE (SET_DEST (set)) == SUBREG))
157 break;
158@@ -1296,8 +1312,6 @@
159 fprintf (dump_file, "SMS loop-with-call\n");
160 else if (BARRIER_P (insn))
161 fprintf (dump_file, "SMS loop-with-barrier\n");
162- else if (FIND_REG_INC_NOTE (insn, NULL_RTX) != 0)
163- fprintf (dump_file, "SMS reg inc\n");
164 else if ((NONDEBUG_INSN_P (insn) && !JUMP_P (insn)
165 && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE))
166 fprintf (dump_file, "SMS loop-with-not-single-set\n");
167
168=== added file 'gcc/testsuite/gcc.dg/sms-10.c'
169--- old/gcc/testsuite/gcc.dg/sms-10.c 1970-01-01 00:00:00 +0000
170+++ new/gcc/testsuite/gcc.dg/sms-10.c 2011-10-02 06:56:53 +0000
171@@ -0,0 +1,118 @@
172+ /* { dg-do run } */
173+ /* { dg-options "-O2 -fmodulo-sched -fmodulo-sched-allow-regmoves -fdump-rtl-sms" } */
174+
175+
176+typedef __SIZE_TYPE__ size_t;
177+extern void *malloc (size_t);
178+extern void free (void *);
179+extern void abort (void);
180+
181+struct regstat_n_sets_and_refs_t
182+{
183+ int sets;
184+ int refs;
185+};
186+
187+struct regstat_n_sets_and_refs_t *regstat_n_sets_and_refs;
188+
189+struct df_reg_info
190+{
191+ unsigned int n_refs;
192+};
193+
194+struct df_d
195+{
196+ struct df_reg_info **def_regs;
197+ struct df_reg_info **use_regs;
198+};
199+struct df_d *df;
200+
201+static inline int
202+REG_N_SETS (int regno)
203+{
204+ return regstat_n_sets_and_refs[regno].sets;
205+}
206+
207+__attribute__ ((noinline))
208+ int max_reg_num (void)
209+{
210+ return 100;
211+}
212+
213+__attribute__ ((noinline))
214+ void regstat_init_n_sets_and_refs (void)
215+{
216+ unsigned int i;
217+ unsigned int max_regno = max_reg_num ();
218+
219+ for (i = 0; i < max_regno; i++)
220+ {
221+ (regstat_n_sets_and_refs[i].sets = (df->def_regs[(i)]->n_refs));
222+ (regstat_n_sets_and_refs[i].refs =
223+ (df->use_regs[(i)]->n_refs) + REG_N_SETS (i));
224+ }
225+}
226+
227+int a_sets[100] =
228+ { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
229+ 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
230+ 40, 41, 42,
231+ 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
232+ 62, 63, 64,
233+ 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
234+ 84, 85, 86,
235+ 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99
236+};
237+
238+int a_refs[100] =
239+ { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38,
240+ 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76,
241+ 78, 80, 82,
242+ 84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116,
243+ 118, 120,
244+ 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150,
245+ 152, 154, 156,
246+ 158, 160, 162, 164, 166, 168, 170, 172, 174, 176, 178, 180, 182, 184, 186,
247+ 188, 190, 192,
248+ 194, 196, 198
249+};
250+
251+int
252+main ()
253+{
254+ struct df_reg_info *b[100], *c[100];
255+ struct df_d df1;
256+ size_t s = sizeof (struct df_reg_info);
257+ struct regstat_n_sets_and_refs_t a[100];
258+
259+ df = &df1;
260+ regstat_n_sets_and_refs = a;
261+ int i;
262+
263+ for (i = 0; i < 100; i++)
264+ {
265+ b[i] = (struct df_reg_info *) malloc (s);
266+ b[i]->n_refs = i;
267+ c[i] = (struct df_reg_info *) malloc (s);
268+ c[i]->n_refs = i;
269+ }
270+
271+ df1.def_regs = b;
272+ df1.use_regs = c;
273+ regstat_init_n_sets_and_refs ();
274+
275+ for (i = 0; i < 100; i++)
276+ if ((a[i].sets != a_sets[i]) || (a[i].refs != a_refs[i]))
277+ abort ();
278+
279+ for (i = 0; i < 100; i++)
280+ {
281+ free (b[i]);
282+ free (c[i]);
283+ }
284+
285+ return 0;
286+}
287+
288+/* { dg-final { scan-rtl-dump-times "SMS succeeded" 1 "sms" { target powerpc*-*-* } } } */
289+/* { dg-final { cleanup-rtl-dump "sms" } } */
290
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106818.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106818.patch
deleted file mode 100644
index ef98142bc..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106818.patch
+++ /dev/null
@@ -1,105 +0,0 @@
12011-10-03 Michael Hope <michael.hope@linaro.org>
2
3 Backport from mainline:
4
5 2011-09-13 Sevak Sargsyan <sevak.sargsyan@ispras.ru>
6
7 gcc/
8 * config/arm/neon.md (neon_vabd<mode>_2, neon_vabd<mode>_3): New
9 define_insn patterns for combine.
10
11 gcc/testsuite/
12 * gcc.target/arm/neon-combine-sub-abs-into-vabd.c: New test.
13
14=== modified file 'gcc/config/arm/neon.md'
15--- old/gcc/config/arm/neon.md 2011-09-28 15:14:59 +0000
16+++ new/gcc/config/arm/neon.md 2011-10-03 01:32:17 +0000
17@@ -5428,3 +5428,32 @@
18 emit_insn (gen_neon_vec_pack_trunc_<V_double> (operands[0], tempreg));
19 DONE;
20 })
21+
22+(define_insn "neon_vabd<mode>_2"
23+ [(set (match_operand:VDQ 0 "s_register_operand" "=w")
24+ (abs:VDQ (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
25+ (match_operand:VDQ 2 "s_register_operand" "w"))))]
26+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
27+ "vabd.<V_s_elem> %<V_reg>0, %<V_reg>1, %<V_reg>2"
28+ [(set (attr "neon_type")
29+ (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
30+ (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
31+ (const_string "neon_fp_vadd_ddd_vabs_dd")
32+ (const_string "neon_fp_vadd_qqq_vabs_qq"))
33+ (const_string "neon_int_5")))]
34+)
35+
36+(define_insn "neon_vabd<mode>_3"
37+ [(set (match_operand:VDQ 0 "s_register_operand" "=w")
38+ (abs:VDQ (unspec:VDQ [(match_operand:VDQ 1 "s_register_operand" "w")
39+ (match_operand:VDQ 2 "s_register_operand" "w")]
40+ UNSPEC_VSUB)))]
41+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
42+ "vabd.<V_if_elem> %<V_reg>0, %<V_reg>1, %<V_reg>2"
43+ [(set (attr "neon_type")
44+ (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
45+ (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
46+ (const_string "neon_fp_vadd_ddd_vabs_dd")
47+ (const_string "neon_fp_vadd_qqq_vabs_qq"))
48+ (const_string "neon_int_5")))]
49+)
50
51=== added file 'gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c'
52--- old/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c 1970-01-01 00:00:00 +0000
53+++ new/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c 2011-10-03 01:32:17 +0000
54@@ -0,0 +1,50 @@
55+/* { dg-do compile } */
56+/* { dg-require-effective-target arm_neon_ok } */
57+/* { dg-options "-O2 -funsafe-math-optimizations" } */
58+/* { dg-add-options arm_neon } */
59+
60+#include <arm_neon.h>
61+float32x2_t f_sub_abs_to_vabd_32()
62+{
63+ float32x2_t val1 = vdup_n_f32 (10);
64+ float32x2_t val2 = vdup_n_f32 (30);
65+ float32x2_t sres = vsub_f32(val1, val2);
66+ float32x2_t res = vabs_f32 (sres);
67+
68+ return res;
69+}
70+/* { dg-final { scan-assembler "vabd\.f32" } }*/
71+
72+#include <arm_neon.h>
73+int8x8_t sub_abs_to_vabd_8()
74+{
75+ int8x8_t val1 = vdup_n_s8 (10);
76+ int8x8_t val2 = vdup_n_s8 (30);
77+ int8x8_t sres = vsub_s8(val1, val2);
78+ int8x8_t res = vabs_s8 (sres);
79+
80+ return res;
81+}
82+/* { dg-final { scan-assembler "vabd\.s8" } }*/
83+
84+int16x4_t sub_abs_to_vabd_16()
85+{
86+ int16x4_t val1 = vdup_n_s16 (10);
87+ int16x4_t val2 = vdup_n_s16 (30);
88+ int16x4_t sres = vsub_s16(val1, val2);
89+ int16x4_t res = vabs_s16 (sres);
90+
91+ return res;
92+}
93+/* { dg-final { scan-assembler "vabd\.s16" } }*/
94+
95+int32x2_t sub_abs_to_vabd_32()
96+{
97+ int32x2_t val1 = vdup_n_s32 (10);
98+ int32x2_t val2 = vdup_n_s32 (30);
99+ int32x2_t sres = vsub_s32(val1, val2);
100+ int32x2_t res = vabs_s32 (sres);
101+
102+ return res;
103+}
104+/* { dg-final { scan-assembler "vabd\.s32" } }*/
105
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106819.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106819.patch
deleted file mode 100644
index e097ec27f..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106819.patch
+++ /dev/null
@@ -1,436 +0,0 @@
12011-10-03 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-09-22 Richard Sandiford <richard.sandiford@linaro.org>
7
8 * config/arm/predicates.md (expandable_comparison_operator): New
9 predicate, extracted from...
10 (arm_comparison_operator): ...here.
11 * config/arm/arm.md (cbranchsi4, cbranchsf4, cbranchdf4, cbranchdi4)
12 (cstoresi4, cstoresf4, cstoredf4, cstoredi4, movsicc, movsfcc)
13 (movdfcc): Use expandable_comparison_operator.
14
15 gcc/testsuite/
16 Backport from mainline:
17
18 2011-09-22 Richard Sandiford <richard.sandiford@linaro.org>
19
20 * gcc.target/arm/cmp-1.c: New test.
21 * gcc.target/arm/cmp-2.c: Likewise.
22
232011-10-03 Richard Sandiford <richard.sandiford@linaro.org>
24
25 gcc/
26 Backport from mainline:
27
28 2011-09-07 Richard Sandiford <richard.sandiford@linaro.org>
29
30 PR target/49030
31 * config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
32 * config/arm/arm.c (maybe_get_arm_condition_code): New function,
33 reusing the old code from get_arm_condition_code. Return ARM_NV
34 for invalid comparison codes.
35 (get_arm_condition_code): Redefine in terms of
36 maybe_get_arm_condition_code.
37 * config/arm/predicates.md (arm_comparison_operator): Use
38 maybe_get_arm_condition_code.
39
40 gcc/testsuite/
41 Backport from mainline:
42
43 2011-09-07 Richard Sandiford <richard.sandiford@linaro.org>
44
45 PR target/49030
46 * gcc.dg/torture/pr49030.c: New test.
47
48=== modified file 'gcc/config/arm/arm-protos.h'
49--- old/gcc/config/arm/arm-protos.h 2011-09-15 09:45:31 +0000
50+++ new/gcc/config/arm/arm-protos.h 2011-10-03 09:46:40 +0000
51@@ -180,6 +180,7 @@
52 #endif
53 extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
54 #ifdef RTX_CODE
55+extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
56 extern void thumb1_final_prescan_insn (rtx);
57 extern void thumb2_final_prescan_insn (rtx);
58 extern const char *thumb_load_double_from_address (rtx *);
59
60=== modified file 'gcc/config/arm/arm.c'
61--- old/gcc/config/arm/arm.c 2011-09-19 07:44:24 +0000
62+++ new/gcc/config/arm/arm.c 2011-10-03 09:46:40 +0000
63@@ -17494,10 +17494,10 @@
64 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
65
66 /* Returns the index of the ARM condition code string in
67- `arm_condition_codes'. COMPARISON should be an rtx like
68- `(eq (...) (...))'. */
69-static enum arm_cond_code
70-get_arm_condition_code (rtx comparison)
71+ `arm_condition_codes', or ARM_NV if the comparison is invalid.
72+ COMPARISON should be an rtx like `(eq (...) (...))'. */
73+enum arm_cond_code
74+maybe_get_arm_condition_code (rtx comparison)
75 {
76 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
77 enum arm_cond_code code;
78@@ -17521,11 +17521,11 @@
79 case CC_DLTUmode: code = ARM_CC;
80
81 dominance:
82- gcc_assert (comp_code == EQ || comp_code == NE);
83-
84 if (comp_code == EQ)
85 return ARM_INVERSE_CONDITION_CODE (code);
86- return code;
87+ if (comp_code == NE)
88+ return code;
89+ return ARM_NV;
90
91 case CC_NOOVmode:
92 switch (comp_code)
93@@ -17534,7 +17534,7 @@
94 case EQ: return ARM_EQ;
95 case GE: return ARM_PL;
96 case LT: return ARM_MI;
97- default: gcc_unreachable ();
98+ default: return ARM_NV;
99 }
100
101 case CC_Zmode:
102@@ -17542,7 +17542,7 @@
103 {
104 case NE: return ARM_NE;
105 case EQ: return ARM_EQ;
106- default: gcc_unreachable ();
107+ default: return ARM_NV;
108 }
109
110 case CC_Nmode:
111@@ -17550,7 +17550,7 @@
112 {
113 case NE: return ARM_MI;
114 case EQ: return ARM_PL;
115- default: gcc_unreachable ();
116+ default: return ARM_NV;
117 }
118
119 case CCFPEmode:
120@@ -17575,7 +17575,7 @@
121 /* UNEQ and LTGT do not have a representation. */
122 case UNEQ: /* Fall through. */
123 case LTGT: /* Fall through. */
124- default: gcc_unreachable ();
125+ default: return ARM_NV;
126 }
127
128 case CC_SWPmode:
129@@ -17591,7 +17591,7 @@
130 case GTU: return ARM_CC;
131 case LEU: return ARM_CS;
132 case LTU: return ARM_HI;
133- default: gcc_unreachable ();
134+ default: return ARM_NV;
135 }
136
137 case CC_Cmode:
138@@ -17599,7 +17599,7 @@
139 {
140 case LTU: return ARM_CS;
141 case GEU: return ARM_CC;
142- default: gcc_unreachable ();
143+ default: return ARM_NV;
144 }
145
146 case CC_CZmode:
147@@ -17611,7 +17611,7 @@
148 case GTU: return ARM_HI;
149 case LEU: return ARM_LS;
150 case LTU: return ARM_CC;
151- default: gcc_unreachable ();
152+ default: return ARM_NV;
153 }
154
155 case CC_NCVmode:
156@@ -17621,7 +17621,7 @@
157 case LT: return ARM_LT;
158 case GEU: return ARM_CS;
159 case LTU: return ARM_CC;
160- default: gcc_unreachable ();
161+ default: return ARM_NV;
162 }
163
164 case CCmode:
165@@ -17637,13 +17637,22 @@
166 case GTU: return ARM_HI;
167 case LEU: return ARM_LS;
168 case LTU: return ARM_CC;
169- default: gcc_unreachable ();
170+ default: return ARM_NV;
171 }
172
173 default: gcc_unreachable ();
174 }
175 }
176
177+/* Like maybe_get_arm_condition_code, but never return ARM_NV. */
178+static enum arm_cond_code
179+get_arm_condition_code (rtx comparison)
180+{
181+ enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
182+ gcc_assert (code != ARM_NV);
183+ return code;
184+}
185+
186 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
187 instructions. */
188 void
189
190=== modified file 'gcc/config/arm/arm.md'
191--- old/gcc/config/arm/arm.md 2011-09-12 14:14:00 +0000
192+++ new/gcc/config/arm/arm.md 2011-10-03 09:47:33 +0000
193@@ -6543,7 +6543,7 @@
194
195 (define_expand "cbranchsi4"
196 [(set (pc) (if_then_else
197- (match_operator 0 "arm_comparison_operator"
198+ (match_operator 0 "expandable_comparison_operator"
199 [(match_operand:SI 1 "s_register_operand" "")
200 (match_operand:SI 2 "nonmemory_operand" "")])
201 (label_ref (match_operand 3 "" ""))
202@@ -6594,7 +6594,7 @@
203
204 (define_expand "cbranchsf4"
205 [(set (pc) (if_then_else
206- (match_operator 0 "arm_comparison_operator"
207+ (match_operator 0 "expandable_comparison_operator"
208 [(match_operand:SF 1 "s_register_operand" "")
209 (match_operand:SF 2 "arm_float_compare_operand" "")])
210 (label_ref (match_operand 3 "" ""))
211@@ -6606,7 +6606,7 @@
212
213 (define_expand "cbranchdf4"
214 [(set (pc) (if_then_else
215- (match_operator 0 "arm_comparison_operator"
216+ (match_operator 0 "expandable_comparison_operator"
217 [(match_operand:DF 1 "s_register_operand" "")
218 (match_operand:DF 2 "arm_float_compare_operand" "")])
219 (label_ref (match_operand 3 "" ""))
220@@ -6618,7 +6618,7 @@
221
222 (define_expand "cbranchdi4"
223 [(set (pc) (if_then_else
224- (match_operator 0 "arm_comparison_operator"
225+ (match_operator 0 "expandable_comparison_operator"
226 [(match_operand:DI 1 "cmpdi_operand" "")
227 (match_operand:DI 2 "cmpdi_operand" "")])
228 (label_ref (match_operand 3 "" ""))
229@@ -7473,7 +7473,7 @@
230
231 (define_expand "cstoresi4"
232 [(set (match_operand:SI 0 "s_register_operand" "")
233- (match_operator:SI 1 "arm_comparison_operator"
234+ (match_operator:SI 1 "expandable_comparison_operator"
235 [(match_operand:SI 2 "s_register_operand" "")
236 (match_operand:SI 3 "reg_or_int_operand" "")]))]
237 "TARGET_32BIT || TARGET_THUMB1"
238@@ -7609,7 +7609,7 @@
239
240 (define_expand "cstoresf4"
241 [(set (match_operand:SI 0 "s_register_operand" "")
242- (match_operator:SI 1 "arm_comparison_operator"
243+ (match_operator:SI 1 "expandable_comparison_operator"
244 [(match_operand:SF 2 "s_register_operand" "")
245 (match_operand:SF 3 "arm_float_compare_operand" "")]))]
246 "TARGET_32BIT && TARGET_HARD_FLOAT"
247@@ -7619,7 +7619,7 @@
248
249 (define_expand "cstoredf4"
250 [(set (match_operand:SI 0 "s_register_operand" "")
251- (match_operator:SI 1 "arm_comparison_operator"
252+ (match_operator:SI 1 "expandable_comparison_operator"
253 [(match_operand:DF 2 "s_register_operand" "")
254 (match_operand:DF 3 "arm_float_compare_operand" "")]))]
255 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
256@@ -7629,7 +7629,7 @@
257
258 (define_expand "cstoredi4"
259 [(set (match_operand:SI 0 "s_register_operand" "")
260- (match_operator:SI 1 "arm_comparison_operator"
261+ (match_operator:SI 1 "expandable_comparison_operator"
262 [(match_operand:DI 2 "cmpdi_operand" "")
263 (match_operand:DI 3 "cmpdi_operand" "")]))]
264 "TARGET_32BIT"
265@@ -7749,7 +7749,7 @@
266
267 (define_expand "movsicc"
268 [(set (match_operand:SI 0 "s_register_operand" "")
269- (if_then_else:SI (match_operand 1 "arm_comparison_operator" "")
270+ (if_then_else:SI (match_operand 1 "expandable_comparison_operator" "")
271 (match_operand:SI 2 "arm_not_operand" "")
272 (match_operand:SI 3 "arm_not_operand" "")))]
273 "TARGET_32BIT"
274@@ -7769,7 +7769,7 @@
275
276 (define_expand "movsfcc"
277 [(set (match_operand:SF 0 "s_register_operand" "")
278- (if_then_else:SF (match_operand 1 "arm_comparison_operator" "")
279+ (if_then_else:SF (match_operand 1 "expandable_comparison_operator" "")
280 (match_operand:SF 2 "s_register_operand" "")
281 (match_operand:SF 3 "nonmemory_operand" "")))]
282 "TARGET_32BIT && TARGET_HARD_FLOAT"
283@@ -7795,7 +7795,7 @@
284
285 (define_expand "movdfcc"
286 [(set (match_operand:DF 0 "s_register_operand" "")
287- (if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
288+ (if_then_else:DF (match_operand 1 "expandable_comparison_operator" "")
289 (match_operand:DF 2 "s_register_operand" "")
290 (match_operand:DF 3 "arm_float_add_operand" "")))]
291 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
292
293=== modified file 'gcc/config/arm/predicates.md'
294--- old/gcc/config/arm/predicates.md 2011-09-15 09:45:31 +0000
295+++ new/gcc/config/arm/predicates.md 2011-10-03 09:47:33 +0000
296@@ -242,11 +242,15 @@
297
298 ;; True for integer comparisons and, if FP is active, for comparisons
299 ;; other than LTGT or UNEQ.
300+(define_special_predicate "expandable_comparison_operator"
301+ (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
302+ unordered,ordered,unlt,unle,unge,ungt"))
303+
304+;; Likewise, but only accept comparisons that are directly supported
305+;; by ARM condition codes.
306 (define_special_predicate "arm_comparison_operator"
307- (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
308- (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
309- && (TARGET_FPA || TARGET_VFP)")
310- (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
311+ (and (match_operand 0 "expandable_comparison_operator")
312+ (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
313
314 (define_special_predicate "lt_ge_comparison_operator"
315 (match_code "lt,ge"))
316
317=== added file 'gcc/testsuite/gcc.dg/torture/pr49030.c'
318--- old/gcc/testsuite/gcc.dg/torture/pr49030.c 1970-01-01 00:00:00 +0000
319+++ new/gcc/testsuite/gcc.dg/torture/pr49030.c 2011-10-03 09:46:40 +0000
320@@ -0,0 +1,19 @@
321+void
322+sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
323+ unsigned long dst_skip)
324+{
325+ long long y;
326+ while (nsamples--)
327+ {
328+ y = (long long) (*src * 8388608.0f) << 8;
329+ if (y > 2147483647) {
330+ *(int *) dst = 2147483647;
331+ } else if (y < -2147483647 - 1) {
332+ *(int *) dst = -2147483647 - 1;
333+ } else {
334+ *(int *) dst = (int) y;
335+ }
336+ dst += dst_skip;
337+ src++;
338+ }
339+}
340
341=== added file 'gcc/testsuite/gcc.target/arm/cmp-1.c'
342--- old/gcc/testsuite/gcc.target/arm/cmp-1.c 1970-01-01 00:00:00 +0000
343+++ new/gcc/testsuite/gcc.target/arm/cmp-1.c 2011-10-03 09:47:33 +0000
344@@ -0,0 +1,37 @@
345+/* { dg-do compile } */
346+/* { dg-options "-O" } */
347+/* { dg-final { scan-assembler-not "\tbl\t" } } */
348+/* { dg-final { scan-assembler-not "__aeabi" } } */
349+int x, y;
350+
351+#define TEST_EXPR(NAME, ARGS, EXPR) \
352+ int NAME##1 ARGS { return (EXPR); } \
353+ int NAME##2 ARGS { return !(EXPR); } \
354+ int NAME##3 ARGS { return (EXPR) ? x : y; } \
355+ void NAME##4 ARGS { if (EXPR) x++; } \
356+ void NAME##5 ARGS { if (!(EXPR)) x++; }
357+
358+#define TEST(NAME, TYPE, OPERATOR) \
359+ TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), a1 OPERATOR a2) \
360+ TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), a1 OPERATOR *a2) \
361+ TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), *a1 OPERATOR a2) \
362+ TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), *a1 OPERATOR *a2) \
363+ TEST_EXPR (NAME##_rc, (TYPE a1), a1 OPERATOR 100) \
364+ TEST_EXPR (NAME##_cr, (TYPE a1), 100 OPERATOR a1)
365+
366+#define TEST_OP(NAME, OPERATOR) \
367+ TEST (sc_##NAME, signed char, OPERATOR) \
368+ TEST (uc_##NAME, unsigned char, OPERATOR) \
369+ TEST (ss_##NAME, short, OPERATOR) \
370+ TEST (us_##NAME, unsigned short, OPERATOR) \
371+ TEST (si_##NAME, int, OPERATOR) \
372+ TEST (ui_##NAME, unsigned int, OPERATOR) \
373+ TEST (sll_##NAME, long long, OPERATOR) \
374+ TEST (ull_##NAME, unsigned long long, OPERATOR)
375+
376+TEST_OP (eq, ==)
377+TEST_OP (ne, !=)
378+TEST_OP (lt, <)
379+TEST_OP (gt, >)
380+TEST_OP (le, <=)
381+TEST_OP (ge, >=)
382
383=== added file 'gcc/testsuite/gcc.target/arm/cmp-2.c'
384--- old/gcc/testsuite/gcc.target/arm/cmp-2.c 1970-01-01 00:00:00 +0000
385+++ new/gcc/testsuite/gcc.target/arm/cmp-2.c 2011-10-03 09:47:33 +0000
386@@ -0,0 +1,49 @@
387+/* { dg-do compile } */
388+/* { dg-require-effective-target arm_vfp_ok } */
389+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
390+/* { dg-options "-O -mfpu=vfp -mfloat-abi=softfp" } */
391+/* { dg-final { scan-assembler-not "\tbl\t" } } */
392+/* { dg-final { scan-assembler-not "__aeabi" } } */
393+int x, y;
394+
395+#define EQ(X, Y) ((X) == (Y))
396+#define NE(X, Y) ((X) != (Y))
397+#define LT(X, Y) ((X) < (Y))
398+#define GT(X, Y) ((X) > (Y))
399+#define LE(X, Y) ((X) <= (Y))
400+#define GE(X, Y) ((X) >= (Y))
401+
402+#define TEST_EXPR(NAME, ARGS, EXPR) \
403+ int NAME##1 ARGS { return (EXPR); } \
404+ int NAME##2 ARGS { return !(EXPR); } \
405+ int NAME##3 ARGS { return (EXPR) ? x : y; } \
406+ void NAME##4 ARGS { if (EXPR) x++; } \
407+ void NAME##5 ARGS { if (!(EXPR)) x++; }
408+
409+#define TEST(NAME, TYPE, OPERATOR) \
410+ TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), OPERATOR (a1, a2)) \
411+ TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), OPERATOR (a1, *a2)) \
412+ TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), OPERATOR (*a1, a2)) \
413+ TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), OPERATOR (*a1, *a2)) \
414+ TEST_EXPR (NAME##_rc, (TYPE a1), OPERATOR (a1, 100)) \
415+ TEST_EXPR (NAME##_cr, (TYPE a1), OPERATOR (100, a1))
416+
417+#define TEST_OP(NAME, OPERATOR) \
418+ TEST (f_##NAME, float, OPERATOR) \
419+ TEST (d_##NAME, double, OPERATOR) \
420+ TEST (ld_##NAME, long double, OPERATOR)
421+
422+TEST_OP (eq, EQ)
423+TEST_OP (ne, NE)
424+TEST_OP (lt, LT)
425+TEST_OP (gt, GT)
426+TEST_OP (le, LE)
427+TEST_OP (ge, GE)
428+TEST_OP (blt, __builtin_isless)
429+TEST_OP (bgt, __builtin_isgreater)
430+TEST_OP (ble, __builtin_islessequal)
431+TEST_OP (bge, __builtin_isgreaterequal)
432+/* This one should be expanded into separate ordered and equality
433+ comparisons. */
434+TEST_OP (blg, __builtin_islessgreater)
435+TEST_OP (bun, __builtin_isunordered)
436
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106820.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106820.patch
deleted file mode 100644
index 4a886ce56..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106820.patch
+++ /dev/null
@@ -1,378 +0,0 @@
12011-10-06 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from mainline:
4
5 2011-09-25 Ira Rosen <ira.rosen@linaro.org>
6
7 gcc/
8 * tree-data-ref.c (dr_analyze_innermost): Add new argument.
9 Allow not simple iv if analyzing basic block.
10 (create_data_ref): Update call to dr_analyze_innermost.
11 (stmt_with_adjacent_zero_store_dr_p, ref_base_address): Likewise.
12 * tree-loop-distribution.c (generate_memset_zero): Likewise.
13 * tree-predcom.c (find_looparound_phi): Likewise.
14 * tree-data-ref.h (dr_analyze_innermost): Add new argument.
15
16 gcc/testsuite/
17 * gcc.dg/vect/bb-slp-24.c: New.
18
19
20 2011-09-15 Ira Rosen <ira.rosen@linaro.org>
21
22 gcc/
23 * tree-vect-data-refs.c (vect_analyze_data_ref_dependence): Allow
24 read-after-read dependencies in basic block SLP.
25
26 gcc/testsuite/
27 * gcc.dg/vect/bb-slp-25.c: New.
28
29
30 2011-04-21 Richard Sandiford <richard.sandiford@linaro.org>
31
32 gcc/
33 * tree-vect-data-refs.c (vect_drs_dependent_in_basic_block): Use
34 operand_equal_p to compare DR_BASE_ADDRESSes.
35 (vect_check_interleaving): Likewise.
36
37 gcc/testsuite/
38 * gcc.dg/vect/vect-119.c: New test.
39
40=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-24.c'
41--- old/gcc/testsuite/gcc.dg/vect/bb-slp-24.c 1970-01-01 00:00:00 +0000
42+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-24.c 2011-10-02 08:43:10 +0000
43@@ -0,0 +1,59 @@
44+/* { dg-require-effective-target vect_int } */
45+
46+#include <stdarg.h>
47+#include "tree-vect.h"
48+
49+#define A 3
50+#define N 256
51+
52+short src[N], dst[N];
53+
54+void foo (short * __restrict__ dst, short * __restrict__ src, int h,
55+ int stride, int dummy)
56+{
57+ int i;
58+ h /= 8;
59+ for (i = 0; i < h; i++)
60+ {
61+ dst[0] += A*src[0];
62+ dst[1] += A*src[1];
63+ dst[2] += A*src[2];
64+ dst[3] += A*src[3];
65+ dst[4] += A*src[4];
66+ dst[5] += A*src[5];
67+ dst[6] += A*src[6];
68+ dst[7] += A*src[7];
69+ dst += stride;
70+ src += stride;
71+ if (dummy == 32)
72+ abort ();
73+ }
74+}
75+
76+
77+int main (void)
78+{
79+ int i;
80+
81+ check_vect ();
82+
83+ for (i = 0; i < N; i++)
84+ {
85+ dst[i] = 0;
86+ src[i] = i;
87+ }
88+
89+ foo (dst, src, N, 8, 0);
90+
91+ for (i = 0; i < N; i++)
92+ {
93+ if (dst[i] != A * i)
94+ abort ();
95+ }
96+
97+ return 0;
98+}
99+
100+/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target vect_element_align } } } */
101+/* { dg-final { cleanup-tree-dump "slp" } } */
102+
103
104=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-25.c'
105--- old/gcc/testsuite/gcc.dg/vect/bb-slp-25.c 1970-01-01 00:00:00 +0000
106+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-25.c 2011-10-02 08:43:10 +0000
107@@ -0,0 +1,59 @@
108+/* { dg-require-effective-target vect_int } */
109+
110+#include <stdarg.h>
111+#include "tree-vect.h"
112+
113+#define A 3
114+#define B 4
115+#define N 256
116+
117+short src[N], dst[N];
118+
119+void foo (short * __restrict__ dst, short * __restrict__ src, int h, int stride, int dummy)
120+{
121+ int i;
122+ h /= 16;
123+ for (i = 0; i < h; i++)
124+ {
125+ dst[0] += A*src[0] + src[stride];
126+ dst[1] += A*src[1] + src[1+stride];
127+ dst[2] += A*src[2] + src[2+stride];
128+ dst[3] += A*src[3] + src[3+stride];
129+ dst[4] += A*src[4] + src[4+stride];
130+ dst[5] += A*src[5] + src[5+stride];
131+ dst[6] += A*src[6] + src[6+stride];
132+ dst[7] += A*src[7] + src[7+stride];
133+ dst += 8;
134+ src += 8;
135+ if (dummy == 32)
136+ abort ();
137+ }
138+}
139+
140+
141+int main (void)
142+{
143+ int i;
144+
145+ check_vect ();
146+
147+ for (i = 0; i < N; i++)
148+ {
149+ dst[i] = 0;
150+ src[i] = i;
151+ }
152+
153+ foo (dst, src, N, 8, 0);
154+
155+ for (i = 0; i < N/2; i++)
156+ {
157+ if (dst[i] != A * i + i + 8)
158+ abort ();
159+ }
160+
161+ return 0;
162+}
163+
164+/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target vect_element_align } } } */
165+/* { dg-final { cleanup-tree-dump "slp" } } */
166+
167
168=== added file 'gcc/testsuite/gcc.dg/vect/vect-119.c'
169--- old/gcc/testsuite/gcc.dg/vect/vect-119.c 1970-01-01 00:00:00 +0000
170+++ new/gcc/testsuite/gcc.dg/vect/vect-119.c 2011-10-02 08:43:10 +0000
171@@ -0,0 +1,28 @@
172+/* { dg-do compile } */
173+
174+#define OUTER 32
175+#define INNER 40
176+
177+static unsigned int
178+bar (const unsigned int x[INNER][2], unsigned int sum)
179+{
180+ int i;
181+
182+ for (i = 0; i < INNER; i++)
183+ sum += x[i][0] * x[i][0] + x[i][1] * x[i][1];
184+ return sum;
185+}
186+
187+unsigned int foo (const unsigned int x[OUTER][INNER][2])
188+{
189+ int i;
190+ unsigned int sum;
191+
192+ sum = 0.0f;
193+ for (i = 0; i < OUTER; i++)
194+ sum = bar (x[i], sum);
195+ return sum;
196+}
197+
198+/* { dg-final { scan-tree-dump-times "Detected interleaving of size 2" 1 "vect" } } */
199+/* { dg-final { cleanup-tree-dump "vect" } } */
200
201=== modified file 'gcc/tree-data-ref.c'
202--- old/gcc/tree-data-ref.c 2011-05-26 14:27:33 +0000
203+++ new/gcc/tree-data-ref.c 2011-10-02 08:43:10 +0000
204@@ -721,11 +721,11 @@
205 }
206
207 /* Analyzes the behavior of the memory reference DR in the innermost loop or
208- basic block that contains it. Returns true if analysis succeed or false
209+ basic block that contains it. Returns true if analysis succeed or false
210 otherwise. */
211
212 bool
213-dr_analyze_innermost (struct data_reference *dr)
214+dr_analyze_innermost (struct data_reference *dr, struct loop *nest)
215 {
216 gimple stmt = DR_STMT (dr);
217 struct loop *loop = loop_containing_stmt (stmt);
218@@ -768,14 +768,25 @@
219 }
220 else
221 base = build_fold_addr_expr (base);
222+
223 if (in_loop)
224 {
225 if (!simple_iv (loop, loop_containing_stmt (stmt), base, &base_iv,
226 false))
227 {
228- if (dump_file && (dump_flags & TDF_DETAILS))
229- fprintf (dump_file, "failed: evolution of base is not affine.\n");
230- return false;
231+ if (nest)
232+ {
233+ if (dump_file && (dump_flags & TDF_DETAILS))
234+ fprintf (dump_file, "failed: evolution of base is not"
235+ " affine.\n");
236+ return false;
237+ }
238+ else
239+ {
240+ base_iv.base = base;
241+ base_iv.step = ssize_int (0);
242+ base_iv.no_overflow = true;
243+ }
244 }
245 }
246 else
247@@ -800,10 +811,18 @@
248 else if (!simple_iv (loop, loop_containing_stmt (stmt),
249 poffset, &offset_iv, false))
250 {
251- if (dump_file && (dump_flags & TDF_DETAILS))
252- fprintf (dump_file, "failed: evolution of offset is not"
253- " affine.\n");
254- return false;
255+ if (nest)
256+ {
257+ if (dump_file && (dump_flags & TDF_DETAILS))
258+ fprintf (dump_file, "failed: evolution of offset is not"
259+ " affine.\n");
260+ return false;
261+ }
262+ else
263+ {
264+ offset_iv.base = poffset;
265+ offset_iv.step = ssize_int (0);
266+ }
267 }
268 }
269
270@@ -967,7 +986,7 @@
271 DR_REF (dr) = memref;
272 DR_IS_READ (dr) = is_read;
273
274- dr_analyze_innermost (dr);
275+ dr_analyze_innermost (dr, nest);
276 dr_analyze_indices (dr, nest, loop);
277 dr_analyze_alias (dr);
278
279@@ -5185,7 +5204,7 @@
280 DR_STMT (dr) = stmt;
281 DR_REF (dr) = op0;
282
283- res = dr_analyze_innermost (dr)
284+ res = dr_analyze_innermost (dr, loop_containing_stmt (stmt))
285 && stride_of_unit_type_p (DR_STEP (dr), TREE_TYPE (op0));
286
287 free_data_ref (dr);
288@@ -5225,7 +5244,7 @@
289
290 DR_STMT (dr) = stmt;
291 DR_REF (dr) = *ref->pos;
292- dr_analyze_innermost (dr);
293+ dr_analyze_innermost (dr, loop_containing_stmt (stmt));
294 base_address = DR_BASE_ADDRESS (dr);
295
296 if (!base_address)
297
298=== modified file 'gcc/tree-data-ref.h'
299--- old/gcc/tree-data-ref.h 2011-03-27 09:38:18 +0000
300+++ new/gcc/tree-data-ref.h 2011-10-02 08:43:10 +0000
301@@ -386,7 +386,7 @@
302 DEF_VEC_ALLOC_O (data_ref_loc, heap);
303
304 bool get_references_in_stmt (gimple, VEC (data_ref_loc, heap) **);
305-bool dr_analyze_innermost (struct data_reference *);
306+bool dr_analyze_innermost (struct data_reference *, struct loop *);
307 extern bool compute_data_dependences_for_loop (struct loop *, bool,
308 VEC (loop_p, heap) **,
309 VEC (data_reference_p, heap) **,
310
311=== modified file 'gcc/tree-loop-distribution.c'
312--- old/gcc/tree-loop-distribution.c 2011-05-11 13:07:54 +0000
313+++ new/gcc/tree-loop-distribution.c 2011-10-02 08:43:10 +0000
314@@ -267,7 +267,7 @@
315
316 DR_STMT (dr) = stmt;
317 DR_REF (dr) = op0;
318- res = dr_analyze_innermost (dr);
319+ res = dr_analyze_innermost (dr, loop_containing_stmt (stmt));
320 gcc_assert (res && stride_of_unit_type_p (DR_STEP (dr), TREE_TYPE (op0)));
321
322 nb_bytes = build_size_arg_loc (loc, nb_iter, op0, &stmt_list);
323
324=== modified file 'gcc/tree-predcom.c'
325--- old/gcc/tree-predcom.c 2011-02-11 14:19:44 +0000
326+++ new/gcc/tree-predcom.c 2011-10-02 08:43:10 +0000
327@@ -1114,7 +1114,7 @@
328 memset (&init_dr, 0, sizeof (struct data_reference));
329 DR_REF (&init_dr) = init_ref;
330 DR_STMT (&init_dr) = phi;
331- if (!dr_analyze_innermost (&init_dr))
332+ if (!dr_analyze_innermost (&init_dr, loop))
333 return NULL;
334
335 if (!valid_initializer_p (&init_dr, ref->distance + 1, root->ref))
336
337=== modified file 'gcc/tree-vect-data-refs.c'
338--- old/gcc/tree-vect-data-refs.c 2011-07-04 11:13:51 +0000
339+++ new/gcc/tree-vect-data-refs.c 2011-10-02 08:43:10 +0000
340@@ -353,11 +353,7 @@
341
342 /* Check that the data-refs have same bases and offsets. If not, we can't
343 determine if they are dependent. */
344- if ((DR_BASE_ADDRESS (dra) != DR_BASE_ADDRESS (drb)
345- && (TREE_CODE (DR_BASE_ADDRESS (dra)) != ADDR_EXPR
346- || TREE_CODE (DR_BASE_ADDRESS (drb)) != ADDR_EXPR
347- || TREE_OPERAND (DR_BASE_ADDRESS (dra), 0)
348- != TREE_OPERAND (DR_BASE_ADDRESS (drb),0)))
349+ if (!operand_equal_p (DR_BASE_ADDRESS (dra), DR_BASE_ADDRESS (drb), 0)
350 || !dr_equal_offsets_p (dra, drb))
351 return true;
352
353@@ -403,11 +399,7 @@
354
355 /* Check that the data-refs have same first location (except init) and they
356 are both either store or load (not load and store). */
357- if ((DR_BASE_ADDRESS (dra) != DR_BASE_ADDRESS (drb)
358- && (TREE_CODE (DR_BASE_ADDRESS (dra)) != ADDR_EXPR
359- || TREE_CODE (DR_BASE_ADDRESS (drb)) != ADDR_EXPR
360- || TREE_OPERAND (DR_BASE_ADDRESS (dra), 0)
361- != TREE_OPERAND (DR_BASE_ADDRESS (drb),0)))
362+ if (!operand_equal_p (DR_BASE_ADDRESS (dra), DR_BASE_ADDRESS (drb), 0)
363 || !dr_equal_offsets_p (dra, drb)
364 || !tree_int_cst_compare (DR_INIT (dra), DR_INIT (drb))
365 || DR_IS_READ (dra) != DR_IS_READ (drb))
366@@ -615,6 +607,11 @@
367 if (vect_check_interleaving (dra, drb))
368 return false;
369
370+ /* Read-read is OK (we need this check here, after checking for
371+ interleaving). */
372+ if (DR_IS_READ (dra) && DR_IS_READ (drb))
373+ return false;
374+
375 if (vect_print_dump_info (REPORT_DR_DETAILS))
376 {
377 fprintf (vect_dump, "can't determine dependence between ");
378
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106821.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106821.patch
deleted file mode 100644
index f25a37858..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106821.patch
+++ /dev/null
@@ -1,240 +0,0 @@
12011-10-06 Ira Rosen <ira.rosen@linaro.org>
2
3 gcc/testsuite/
4 * gcc.dg/vect/bb-slp-26.c: Simplify to make the basic block
5 vectorizable.
6
7 Backport from mainline:
8
9 2011-09-25 Ira Rosen <ira.rosen@linaro.org>
10
11 gcc/
12 * tree-vect-slp.c (vect_slp_analyze_bb_1): Split out core part
13 of vect_analyze_bb here.
14 (vect_analyze_bb): Loop over vector sizes calling vect_analyze_bb_1.
15
16 gcc/testsuite/
17 * lib/target-supports.exp (check_effective_target_vect64): New.
18 * gcc.dg/vect/bb-slp-11.c: Expect the error message twice in case
19 of multiple vector sizes.
20 * gcc.dg/vect/bb-slp-26.c: New.
21
22=== modified file 'gcc/testsuite/gcc.dg/vect/bb-slp-11.c'
23--- old/gcc/testsuite/gcc.dg/vect/bb-slp-11.c 2010-11-22 12:16:52 +0000
24+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-11.c 2011-10-02 10:40:34 +0000
25@@ -49,6 +49,7 @@
26 }
27
28 /* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 0 "slp" } } */
29-/* { dg-final { scan-tree-dump-times "SLP with multiple types" 1 "slp" } } */
30+/* { dg-final { scan-tree-dump-times "SLP with multiple types" 1 "slp" { xfail vect_multiple_sizes } } } */
31+/* { dg-final { scan-tree-dump-times "SLP with multiple types" 2 "slp" { target vect_multiple_sizes } } } */
32 /* { dg-final { cleanup-tree-dump "slp" } } */
33
34
35=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-26.c'
36--- old/gcc/testsuite/gcc.dg/vect/bb-slp-26.c 1970-01-01 00:00:00 +0000
37+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-26.c 2011-10-02 10:40:34 +0000
38@@ -0,0 +1,60 @@
39+/* { dg-require-effective-target vect_int } */
40+
41+#include <stdarg.h>
42+#include "tree-vect.h"
43+
44+#define A 3
45+#define B 4
46+#define N 256
47+
48+char src[N], dst[N];
49+
50+void foo (char * __restrict__ dst, char * __restrict__ src, int h,
51+ int stride, int dummy)
52+{
53+ int i;
54+ h /= 16;
55+ for (i = 0; i < h; i++)
56+ {
57+ dst[0] += A*src[0];
58+ dst[1] += A*src[1];
59+ dst[2] += A*src[2];
60+ dst[3] += A*src[3];
61+ dst[4] += A*src[4];
62+ dst[5] += A*src[5];
63+ dst[6] += A*src[6];
64+ dst[7] += A*src[7];
65+ dst += 8;
66+ src += 8;
67+ if (dummy == 32)
68+ abort ();
69+ }
70+}
71+
72+
73+int main (void)
74+{
75+ int i;
76+
77+ check_vect ();
78+
79+ for (i = 0; i < N; i++)
80+ {
81+ dst[i] = 0;
82+ src[i] = i/8;
83+ }
84+
85+ foo (dst, src, N, 8, 0);
86+
87+ for (i = 0; i < N/2; i++)
88+ {
89+ if (dst[i] != A * src[i])
90+ abort ();
91+ }
92+
93+ return 0;
94+}
95+
96+/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target vect64 } } } */
97+/* { dg-final { cleanup-tree-dump "slp" } } */
98+
99
100=== modified file 'gcc/testsuite/lib/target-supports.exp'
101--- old/gcc/testsuite/lib/target-supports.exp 2011-09-20 07:54:28 +0000
102+++ new/gcc/testsuite/lib/target-supports.exp 2011-10-02 10:40:34 +0000
103@@ -3283,6 +3283,24 @@
104 return $et_vect_multiple_sizes_saved
105 }
106
107+# Return 1 if the target supports vectors of 64 bits.
108+
109+proc check_effective_target_vect64 { } {
110+ global et_vect64
111+
112+ if [info exists et_vect64_saved] {
113+ verbose "check_effective_target_vect64: using cached result" 2
114+ } else {
115+ set et_vect64_saved 0
116+ if { ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]) } {
117+ set et_vect64_saved 1
118+ }
119+ }
120+
121+ verbose "check_effective_target_vect64: returning $et_vect64_saved" 2
122+ return $et_vect64_saved
123+}
124+
125 # Return 1 if the target supports section-anchors
126
127 proc check_effective_target_section_anchors { } {
128
129=== modified file 'gcc/tree-vect-slp.c'
130--- old/gcc/tree-vect-slp.c 2011-07-06 12:04:10 +0000
131+++ new/gcc/tree-vect-slp.c 2011-10-02 10:40:34 +0000
132@@ -1664,42 +1664,18 @@
133
134 /* Check if the basic block can be vectorized. */
135
136-bb_vec_info
137-vect_slp_analyze_bb (basic_block bb)
138+static bb_vec_info
139+vect_slp_analyze_bb_1 (basic_block bb)
140 {
141 bb_vec_info bb_vinfo;
142 VEC (ddr_p, heap) *ddrs;
143 VEC (slp_instance, heap) *slp_instances;
144 slp_instance instance;
145- int i, insns = 0;
146- gimple_stmt_iterator gsi;
147+ int i;
148 int min_vf = 2;
149 int max_vf = MAX_VECTORIZATION_FACTOR;
150 bool data_dependence_in_bb = false;
151
152- current_vector_size = 0;
153-
154- if (vect_print_dump_info (REPORT_DETAILS))
155- fprintf (vect_dump, "===vect_slp_analyze_bb===\n");
156-
157- for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
158- {
159- gimple stmt = gsi_stmt (gsi);
160- if (!is_gimple_debug (stmt)
161- && !gimple_nop_p (stmt)
162- && gimple_code (stmt) != GIMPLE_LABEL)
163- insns++;
164- }
165-
166- if (insns > PARAM_VALUE (PARAM_SLP_MAX_INSNS_IN_BB))
167- {
168- if (vect_print_dump_info (REPORT_UNVECTORIZED_LOCATIONS))
169- fprintf (vect_dump, "not vectorized: too many instructions in basic "
170- "block.\n");
171-
172- return NULL;
173- }
174-
175 bb_vinfo = new_bb_vec_info (bb);
176 if (!bb_vinfo)
177 return NULL;
178@@ -1819,6 +1795,61 @@
179 }
180
181
182+bb_vec_info
183+vect_slp_analyze_bb (basic_block bb)
184+{
185+ bb_vec_info bb_vinfo;
186+ int insns = 0;
187+ gimple_stmt_iterator gsi;
188+ unsigned int vector_sizes;
189+
190+ if (vect_print_dump_info (REPORT_DETAILS))
191+ fprintf (vect_dump, "===vect_slp_analyze_bb===\n");
192+
193+ for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
194+ {
195+ gimple stmt = gsi_stmt (gsi);
196+ if (!is_gimple_debug (stmt)
197+ && !gimple_nop_p (stmt)
198+ && gimple_code (stmt) != GIMPLE_LABEL)
199+ insns++;
200+ }
201+
202+ if (insns > PARAM_VALUE (PARAM_SLP_MAX_INSNS_IN_BB))
203+ {
204+ if (vect_print_dump_info (REPORT_UNVECTORIZED_LOCATIONS))
205+ fprintf (vect_dump, "not vectorized: too many instructions in basic "
206+ "block.\n");
207+
208+ return NULL;
209+ }
210+
211+ /* Autodetect first vector size we try. */
212+ current_vector_size = 0;
213+ vector_sizes = targetm.vectorize.autovectorize_vector_sizes ();
214+
215+ while (1)
216+ {
217+ bb_vinfo = vect_slp_analyze_bb_1 (bb);
218+ if (bb_vinfo)
219+ return bb_vinfo;
220+
221+ destroy_bb_vec_info (bb_vinfo);
222+
223+ vector_sizes &= ~current_vector_size;
224+ if (vector_sizes == 0
225+ || current_vector_size == 0)
226+ return NULL;
227+
228+ /* Try the next biggest vector size. */
229+ current_vector_size = 1 << floor_log2 (vector_sizes);
230+ if (vect_print_dump_info (REPORT_DETAILS))
231+ fprintf (vect_dump, "***** Re-trying analysis with "
232+ "vector size %d\n", current_vector_size);
233+ }
234+}
235+
236+
237 /* SLP costs are calculated according to SLP instance unrolling factor (i.e.,
238 the number of created vector stmts depends on the unrolling factor).
239 However, the actual number of vector stmts for every SLP node depends on
240
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106825.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106825.patch
deleted file mode 100644
index 13e6fd26e..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106825.patch
+++ /dev/null
@@ -1,124 +0,0 @@
12011-10-13 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from mainline:
4
5 2011-10-07 Andrew Stubbs <ams@codesourcery.com>
6
7 gcc/
8 * config/arm/predicates.md (shift_amount_operand): Remove constant
9 range check.
10 (shift_operator): Check range of constants for all shift operators.
11
12 gcc/testsuite/
13 * gcc.dg/pr50193-1.c: New file.
14 * gcc.target/arm/shiftable.c: New file.
15
16=== modified file 'gcc/config/arm/predicates.md'
17--- old/gcc/config/arm/predicates.md 2011-10-03 09:47:33 +0000
18+++ new/gcc/config/arm/predicates.md 2011-10-10 11:43:28 +0000
19@@ -129,11 +129,12 @@
20 (ior (match_operand 0 "arm_rhs_operand")
21 (match_operand 0 "memory_operand")))
22
23+;; This doesn't have to do much because the constant is already checked
24+;; in the shift_operator predicate.
25 (define_predicate "shift_amount_operand"
26 (ior (and (match_test "TARGET_ARM")
27 (match_operand 0 "s_register_operand"))
28- (and (match_operand 0 "const_int_operand")
29- (match_test "INTVAL (op) > 0"))))
30+ (match_operand 0 "const_int_operand")))
31
32 (define_predicate "arm_add_operand"
33 (ior (match_operand 0 "arm_rhs_operand")
34@@ -219,13 +220,20 @@
35 (match_test "mode == GET_MODE (op)")))
36
37 ;; True for shift operators.
38+;; Notes:
39+;; * mult is only permitted with a constant shift amount
40+;; * patterns that permit register shift amounts only in ARM mode use
41+;; shift_amount_operand, patterns that always allow registers do not,
42+;; so we don't have to worry about that sort of thing here.
43 (define_special_predicate "shift_operator"
44 (and (ior (ior (and (match_code "mult")
45 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
46 (and (match_code "rotate")
47 (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
48 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
49- (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
50+ (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
51+ (match_test "GET_CODE (XEXP (op, 1)) != CONST_INT
52+ || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
53 (match_test "mode == GET_MODE (op)")))
54
55 ;; True for MULT, to identify which variant of shift_operator is in use.
56
57=== added file 'gcc/testsuite/gcc.target/arm/shiftable.c'
58--- old/gcc/testsuite/gcc.target/arm/shiftable.c 1970-01-01 00:00:00 +0000
59+++ new/gcc/testsuite/gcc.target/arm/shiftable.c 2011-10-10 11:43:28 +0000
60@@ -0,0 +1,63 @@
61+/* { dg-do compile } */
62+/* { dg-options "-O2" } */
63+/* { dg-require-effective-target arm32 } */
64+
65+/* ARM has shift-and-alu insns. Depending on the ALU op GCC represents some
66+ of these as a left shift, others as a multiply. Check that we match the
67+ right one. */
68+
69+int
70+plus (int a, int b)
71+{
72+ return (a * 64) + b;
73+}
74+
75+/* { dg-final { scan-assembler "add.*\[al]sl #6" } } */
76+
77+int
78+minus (int a, int b)
79+{
80+ return a - (b * 64);
81+}
82+
83+/* { dg-final { scan-assembler "sub.*\[al]sl #6" } } */
84+
85+int
86+ior (int a, int b)
87+{
88+ return (a * 64) | b;
89+}
90+
91+/* { dg-final { scan-assembler "orr.*\[al]sl #6" } } */
92+
93+int
94+xor (int a, int b)
95+{
96+ return (a * 64) ^ b;
97+}
98+
99+/* { dg-final { scan-assembler "eor.*\[al]sl #6" } } */
100+
101+int
102+and (int a, int b)
103+{
104+ return (a * 64) & b;
105+}
106+
107+/* { dg-final { scan-assembler "and.*\[al]sl #6" } } */
108+
109+int
110+rsb (int a, int b)
111+{
112+ return (a * 64) - b;
113+}
114+
115+/* { dg-final { scan-assembler "rsb.*\[al]sl #6" } } */
116+
117+int
118+mvn (int a, int b)
119+{
120+ return ~(a * 64);
121+}
122+
123+/* { dg-final { scan-assembler "mvn.*\[al]sl #6" } } */
124
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106826.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106826.patch
deleted file mode 100644
index 6642f8a66..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106826.patch
+++ /dev/null
@@ -1,362 +0,0 @@
12011-10-16 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from mainline:
4
5 2011-09-27 Ira Rosen <ira.rosen@linaro.org>
6
7 gcc/
8 * tree-vect-stmts.c (vectorizable_type_demotion): Handle basic block
9 vectorization.
10 (vectorizable_type_promotion): Likewise.
11 (vect_analyze_stmt): Call vectorizable_type_demotion and
12 vectorizable_type_promotion for basic blocks.
13 (supportable_widening_operation): Don't assume loop vectorization.
14 * tree-vect-slp.c (vect_build_slp_tree): Allow multiple types for
15 basic blocks. Update vectorization factor for basic block
16 vectorization.
17 (vect_analyze_slp_instance): Allow multiple types for basic block
18 vectorization. Recheck unrolling factor after construction of SLP
19 instance.
20
21 gcc/testsuite/
22 * gcc.dg/vect/bb-slp-11.c: Expect to get vectorized with 64-bit
23 vectors.
24 * gcc.dg/vect/bb-slp-27.c: New.
25 * gcc.dg/vect/bb-slp-28.c: New.
26
27
28 2011-10-04 Ira Rosen <ira.rosen@linaro.org>
29
30 gcc/testsuite/
31 * lib/target-supports.exp (check_effective_target_vect_multiple_sizes):
32 Make et_vect_multiple_sizes_saved global.
33 (check_effective_target_vect64): Make et_vect64_saved global.
34
35=== modified file 'gcc/testsuite/gcc.dg/vect/bb-slp-11.c'
36--- old/gcc/testsuite/gcc.dg/vect/bb-slp-11.c 2011-10-02 10:40:34 +0000
37+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-11.c 2011-10-06 11:08:08 +0000
38@@ -48,8 +48,6 @@
39 return 0;
40 }
41
42-/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 0 "slp" } } */
43-/* { dg-final { scan-tree-dump-times "SLP with multiple types" 1 "slp" { xfail vect_multiple_sizes } } } */
44-/* { dg-final { scan-tree-dump-times "SLP with multiple types" 2 "slp" { target vect_multiple_sizes } } } */
45+/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target vect64 } } } */
46 /* { dg-final { cleanup-tree-dump "slp" } } */
47
48
49=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-27.c'
50--- old/gcc/testsuite/gcc.dg/vect/bb-slp-27.c 1970-01-01 00:00:00 +0000
51+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-27.c 2011-10-06 11:08:08 +0000
52@@ -0,0 +1,49 @@
53+/* { dg-require-effective-target vect_int } */
54+
55+#include <stdarg.h>
56+#include "tree-vect.h"
57+
58+#define A 3
59+#define N 16
60+
61+short src[N], dst[N];
62+
63+void foo (int a)
64+{
65+ dst[0] += a*src[0];
66+ dst[1] += a*src[1];
67+ dst[2] += a*src[2];
68+ dst[3] += a*src[3];
69+ dst[4] += a*src[4];
70+ dst[5] += a*src[5];
71+ dst[6] += a*src[6];
72+ dst[7] += a*src[7];
73+}
74+
75+
76+int main (void)
77+{
78+ int i;
79+
80+ check_vect ();
81+
82+ for (i = 0; i < N; i++)
83+ {
84+ dst[i] = 0;
85+ src[i] = i;
86+ }
87+
88+ foo (A);
89+
90+ for (i = 0; i < 8; i++)
91+ {
92+ if (dst[i] != A * i)
93+ abort ();
94+ }
95+
96+ return 0;
97+}
98+
99+/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target { vect_int_mult && { vect_unpack && vect_pack_trunc } } } } } */
100+/* { dg-final { cleanup-tree-dump "slp" } } */
101+
102
103=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-28.c'
104--- old/gcc/testsuite/gcc.dg/vect/bb-slp-28.c 1970-01-01 00:00:00 +0000
105+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-28.c 2011-10-06 11:08:08 +0000
106@@ -0,0 +1,71 @@
107+/* { dg-require-effective-target vect_int } */
108+
109+#include <stdarg.h>
110+#include "tree-vect.h"
111+
112+#define A 300
113+#define N 16
114+
115+char src[N];
116+short dst[N];
117+short src1[N], dst1[N];
118+
119+void foo (int a)
120+{
121+ dst[0] = (short) (a * (int) src[0]);
122+ dst[1] = (short) (a * (int) src[1]);
123+ dst[2] = (short) (a * (int) src[2]);
124+ dst[3] = (short) (a * (int) src[3]);
125+ dst[4] = (short) (a * (int) src[4]);
126+ dst[5] = (short) (a * (int) src[5]);
127+ dst[6] = (short) (a * (int) src[6]);
128+ dst[7] = (short) (a * (int) src[7]);
129+ dst[8] = (short) (a * (int) src[8]);
130+ dst[9] = (short) (a * (int) src[9]);
131+ dst[10] = (short) (a * (int) src[10]);
132+ dst[11] = (short) (a * (int) src[11]);
133+ dst[12] = (short) (a * (int) src[12]);
134+ dst[13] = (short) (a * (int) src[13]);
135+ dst[14] = (short) (a * (int) src[14]);
136+ dst[15] = (short) (a * (int) src[15]);
137+
138+ dst1[0] += src1[0];
139+ dst1[1] += src1[1];
140+ dst1[2] += src1[2];
141+ dst1[3] += src1[3];
142+ dst1[4] += src1[4];
143+ dst1[5] += src1[5];
144+ dst1[6] += src1[6];
145+ dst1[7] += src1[7];
146+}
147+
148+
149+int main (void)
150+{
151+ int i;
152+
153+ check_vect ();
154+
155+ for (i = 0; i < N; i++)
156+ {
157+ dst[i] = 2;
158+ dst1[i] = 0;
159+ src[i] = i;
160+ src1[i] = i+2;
161+ }
162+
163+ foo (A);
164+
165+ for (i = 0; i < N; i++)
166+ {
167+ if (dst[i] != A * i
168+ || (i < N/2 && dst1[i] != i + 2))
169+ abort ();
170+ }
171+
172+ return 0;
173+}
174+
175+/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target { vect_int_mult && { vect_pack_trunc && vect_unpack } } } } } */
176+/* { dg-final { cleanup-tree-dump "slp" } } */
177+
178
179=== modified file 'gcc/testsuite/lib/target-supports.exp'
180--- old/gcc/testsuite/lib/target-supports.exp 2011-10-02 10:40:34 +0000
181+++ new/gcc/testsuite/lib/target-supports.exp 2011-10-06 11:08:08 +0000
182@@ -3268,7 +3268,7 @@
183 # Return 1 if the target supports multiple vector sizes
184
185 proc check_effective_target_vect_multiple_sizes { } {
186- global et_vect_multiple_sizes
187+ global et_vect_multiple_sizes_saved
188
189 if [info exists et_vect_multiple_sizes_saved] {
190 verbose "check_effective_target_vect_multiple_sizes: using cached result" 2
191@@ -3286,7 +3286,7 @@
192 # Return 1 if the target supports vectors of 64 bits.
193
194 proc check_effective_target_vect64 { } {
195- global et_vect64
196+ global et_vect64_saved
197
198 if [info exists et_vect64_saved] {
199 verbose "check_effective_target_vect64: using cached result" 2
200
201=== modified file 'gcc/tree-vect-slp.c'
202--- old/gcc/tree-vect-slp.c 2011-10-02 10:40:34 +0000
203+++ new/gcc/tree-vect-slp.c 2011-10-06 11:08:08 +0000
204@@ -386,20 +386,15 @@
205 return false;
206 }
207
208- ncopies = vectorization_factor / TYPE_VECTOR_SUBPARTS (vectype);
209- if (ncopies != 1)
210- {
211- if (vect_print_dump_info (REPORT_SLP))
212- fprintf (vect_dump, "SLP with multiple types ");
213-
214- /* FORNOW: multiple types are unsupported in BB SLP. */
215- if (bb_vinfo)
216- return false;
217- }
218-
219 /* In case of multiple types we need to detect the smallest type. */
220 if (*max_nunits < TYPE_VECTOR_SUBPARTS (vectype))
221- *max_nunits = TYPE_VECTOR_SUBPARTS (vectype);
222+ {
223+ *max_nunits = TYPE_VECTOR_SUBPARTS (vectype);
224+ if (bb_vinfo)
225+ vectorization_factor = *max_nunits;
226+ }
227+
228+ ncopies = vectorization_factor / TYPE_VECTOR_SUBPARTS (vectype);
229
230 if (is_gimple_call (stmt))
231 rhs_code = CALL_EXPR;
232@@ -1183,7 +1178,6 @@
233 if (loop_vinfo)
234 vectorization_factor = LOOP_VINFO_VECT_FACTOR (loop_vinfo);
235 else
236- /* No multitypes in BB SLP. */
237 vectorization_factor = nunits;
238
239 /* Calculate the unrolling factor. */
240@@ -1246,16 +1240,23 @@
241 &max_nunits, &load_permutation, &loads,
242 vectorization_factor))
243 {
244+ /* Calculate the unrolling factor based on the smallest type. */
245+ if (max_nunits > nunits)
246+ unrolling_factor = least_common_multiple (max_nunits, group_size)
247+ / group_size;
248+
249+ if (unrolling_factor != 1 && !loop_vinfo)
250+ {
251+ if (vect_print_dump_info (REPORT_SLP))
252+ fprintf (vect_dump, "Build SLP failed: unrolling required in basic"
253+ " block SLP");
254+ return false;
255+ }
256+
257 /* Create a new SLP instance. */
258 new_instance = XNEW (struct _slp_instance);
259 SLP_INSTANCE_TREE (new_instance) = node;
260 SLP_INSTANCE_GROUP_SIZE (new_instance) = group_size;
261- /* Calculate the unrolling factor based on the smallest type in the
262- loop. */
263- if (max_nunits > nunits)
264- unrolling_factor = least_common_multiple (max_nunits, group_size)
265- / group_size;
266-
267 SLP_INSTANCE_UNROLLING_FACTOR (new_instance) = unrolling_factor;
268 SLP_INSTANCE_OUTSIDE_OF_LOOP_COST (new_instance) = outside_cost;
269 SLP_INSTANCE_INSIDE_OF_LOOP_COST (new_instance) = inside_cost;
270
271=== modified file 'gcc/tree-vect-stmts.c'
272--- old/gcc/tree-vect-stmts.c 2011-10-04 08:57:25 +0000
273+++ new/gcc/tree-vect-stmts.c 2011-10-16 12:16:07 +0000
274@@ -3081,11 +3081,9 @@
275 VEC (tree, heap) *vec_oprnds0 = NULL;
276 VEC (tree, heap) *vec_dsts = NULL, *interm_types = NULL, *tmp_vec_dsts = NULL;
277 tree last_oprnd, intermediate_type;
278-
279- /* FORNOW: not supported by basic block SLP vectorization. */
280- gcc_assert (loop_vinfo);
281-
282- if (!STMT_VINFO_RELEVANT_P (stmt_info))
283+ bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
284+
285+ if (!STMT_VINFO_RELEVANT_P (stmt_info) && !bb_vinfo)
286 return false;
287
288 if (STMT_VINFO_DEF_TYPE (stmt_info) != vect_internal_def)
289@@ -3113,7 +3111,7 @@
290 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (op0))
291 && CONVERT_EXPR_CODE_P (code))))
292 return false;
293- if (!vect_is_simple_use_1 (op0, loop_vinfo, NULL,
294+ if (!vect_is_simple_use_1 (op0, loop_vinfo, bb_vinfo,
295 &def_stmt, &def, &dt[0], &vectype_in))
296 {
297 if (vect_print_dump_info (REPORT_DETAILS))
298@@ -3360,11 +3358,9 @@
299 int multi_step_cvt = 0;
300 VEC (tree, heap) *vec_oprnds0 = NULL, *vec_oprnds1 = NULL;
301 VEC (tree, heap) *vec_dsts = NULL, *interm_types = NULL, *tmp_vec_dsts = NULL;
302-
303- /* FORNOW: not supported by basic block SLP vectorization. */
304- gcc_assert (loop_vinfo);
305-
306- if (!STMT_VINFO_RELEVANT_P (stmt_info))
307+ bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
308+
309+ if (!STMT_VINFO_RELEVANT_P (stmt_info) && !bb_vinfo)
310 return false;
311
312 if (STMT_VINFO_DEF_TYPE (stmt_info) != vect_internal_def)
313@@ -3393,7 +3389,7 @@
314 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (op0))
315 && CONVERT_EXPR_CODE_P (code))))
316 return false;
317- if (!vect_is_simple_use_1 (op0, loop_vinfo, NULL,
318+ if (!vect_is_simple_use_1 (op0, loop_vinfo, bb_vinfo,
319 &def_stmt, &def, &dt[0], &vectype_in))
320 {
321 if (vect_print_dump_info (REPORT_DETAILS))
322@@ -5153,7 +5149,9 @@
323 else
324 {
325 if (bb_vinfo)
326- ok = (vectorizable_shift (stmt, NULL, NULL, node)
327+ ok = (vectorizable_type_promotion (stmt, NULL, NULL, node)
328+ || vectorizable_type_demotion (stmt, NULL, NULL, node)
329+ || vectorizable_shift (stmt, NULL, NULL, node)
330 || vectorizable_operation (stmt, NULL, NULL, node)
331 || vectorizable_assignment (stmt, NULL, NULL, node)
332 || vectorizable_load (stmt, NULL, NULL, node, NULL)
333@@ -5780,7 +5778,7 @@
334 {
335 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
336 loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_info);
337- struct loop *vect_loop = LOOP_VINFO_LOOP (loop_info);
338+ struct loop *vect_loop = NULL;
339 bool ordered_p;
340 enum machine_mode vec_mode;
341 enum insn_code icode1, icode2;
342@@ -5789,6 +5787,9 @@
343 tree wide_vectype = vectype_out;
344 enum tree_code c1, c2;
345
346+ if (loop_info)
347+ vect_loop = LOOP_VINFO_LOOP (loop_info);
348+
349 /* The result of a vectorized widening operation usually requires two vectors
350 (because the widened results do not fit int one vector). The generated
351 vector results would normally be expected to be generated in the same
352@@ -5809,7 +5810,8 @@
353 iterations in parallel). We therefore don't allow to change the order
354 of the computation in the inner-loop during outer-loop vectorization. */
355
356- if (STMT_VINFO_RELEVANT (stmt_info) == vect_used_by_reduction
357+ if (vect_loop
358+ && STMT_VINFO_RELEVANT (stmt_info) == vect_used_by_reduction
359 && !nested_in_vect_loop_p (vect_loop, stmt))
360 ordered_p = false;
361 else
362
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106827.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106827.patch
deleted file mode 100644
index 28caa4007..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106827.patch
+++ /dev/null
@@ -1,622 +0,0 @@
12011-10-17 Michael Hope <michael.hope@linaro.org>
2
3 Backport from mainline r178852:
4
5 2011-09-14 Julian Brown <julian@codesourcery.com>
6
7 gcc/
8 * config/arm/arm.c (arm_override_options): Add unaligned_access
9 support.
10 (arm_file_start): Emit attribute for unaligned access as appropriate.
11 * config/arm/arm.md (UNSPEC_UNALIGNED_LOAD)
12 (UNSPEC_UNALIGNED_STORE): Add constants for unspecs.
13 (insv, extzv): Add unaligned-access support.
14 (extv): Change to expander. Likewise.
15 (extzv_t1, extv_regsi): Add helpers.
16 (unaligned_loadsi, unaligned_loadhis, unaligned_loadhiu)
17 (unaligned_storesi, unaligned_storehi): New.
18 (*extv_reg): New (previous extv implementation).
19 * config/arm/arm.opt (munaligned_access): Add option.
20 * config/arm/constraints.md (Uw): New constraint.
21 * expmed.c (store_bit_field_1): Adjust bitfield numbering according
22 to size of access, not size of unit, when BITS_BIG_ENDIAN !=
23 BYTES_BIG_ENDIAN. Don't use bitfield accesses for
24 volatile accesses when -fstrict-volatile-bitfields is in effect.
25 (extract_bit_field_1): Likewise.
26
27 Backport from mainline r172697:
28
29 2011-04-19 Wei Guozhi <carrot@google.com>
30
31 PR target/47855
32 gcc/
33 * config/arm/arm-protos.h (thumb1_legitimate_address_p): New prototype.
34 * config/arm/arm.c (thumb1_legitimate_address_p): Remove the static
35 linkage.
36 * config/arm/constraints.md (Uu): New constraint.
37 * config/arm/arm.md (*arm_movqi_insn): Compute attr "length".
38
39=== modified file 'gcc/config/arm/arm-protos.h'
40Index: gcc-4_6-branch/gcc/config/arm/arm-protos.h
41===================================================================
42--- gcc-4_6-branch.orig/gcc/config/arm/arm-protos.h 2012-03-05 16:07:15.000000000 -0800
43+++ gcc-4_6-branch/gcc/config/arm/arm-protos.h 2012-03-05 16:07:50.392936694 -0800
44@@ -59,6 +59,7 @@
45 int);
46 extern rtx thumb_legitimize_reload_address (rtx *, enum machine_mode, int, int,
47 int);
48+extern int thumb1_legitimate_address_p (enum machine_mode, rtx, int);
49 extern int arm_const_double_rtx (rtx);
50 extern int neg_const_double_rtx_ok_for_fpa (rtx);
51 extern int vfp3_const_double_rtx (rtx);
52Index: gcc-4_6-branch/gcc/config/arm/arm.c
53===================================================================
54--- gcc-4_6-branch.orig/gcc/config/arm/arm.c 2012-03-05 16:07:15.000000000 -0800
55+++ gcc-4_6-branch/gcc/config/arm/arm.c 2012-03-05 16:07:50.400936694 -0800
56@@ -2065,6 +2065,28 @@
57 fix_cm3_ldrd = 0;
58 }
59
60+ /* Enable -munaligned-access by default for
61+ - all ARMv6 architecture-based processors
62+ - ARMv7-A, ARMv7-R, and ARMv7-M architecture-based processors.
63+
64+ Disable -munaligned-access by default for
65+ - all pre-ARMv6 architecture-based processors
66+ - ARMv6-M architecture-based processors. */
67+
68+ if (unaligned_access == 2)
69+ {
70+ if (arm_arch6 && (arm_arch_notm || arm_arch7))
71+ unaligned_access = 1;
72+ else
73+ unaligned_access = 0;
74+ }
75+ else if (unaligned_access == 1
76+ && !(arm_arch6 && (arm_arch_notm || arm_arch7)))
77+ {
78+ warning (0, "target CPU does not support unaligned accesses");
79+ unaligned_access = 0;
80+ }
81+
82 if (TARGET_THUMB1 && flag_schedule_insns)
83 {
84 /* Don't warn since it's on by default in -O2. */
85@@ -6123,7 +6145,7 @@
86 addresses based on the frame pointer or arg pointer until the
87 reload pass starts. This is so that eliminating such addresses
88 into stack based ones won't produce impossible code. */
89-static int
90+int
91 thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
92 {
93 /* ??? Not clear if this is right. Experiment. */
94@@ -22251,6 +22273,10 @@
95 val = 6;
96 asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val);
97
98+ /* Tag_CPU_unaligned_access. */
99+ asm_fprintf (asm_out_file, "\t.eabi_attribute 34, %d\n",
100+ unaligned_access);
101+
102 /* Tag_ABI_FP_16bit_format. */
103 if (arm_fp16_format)
104 asm_fprintf (asm_out_file, "\t.eabi_attribute 38, %d\n",
105Index: gcc-4_6-branch/gcc/config/arm/arm.md
106===================================================================
107--- gcc-4_6-branch.orig/gcc/config/arm/arm.md 2012-03-05 16:07:15.000000000 -0800
108+++ gcc-4_6-branch/gcc/config/arm/arm.md 2012-03-05 16:09:26.284941314 -0800
109@@ -114,6 +114,10 @@
110 ; another symbolic address.
111 (UNSPEC_MEMORY_BARRIER 28) ; Represent a memory barrier.
112 (UNSPEC_PIC_UNIFIED 29) ; Create a common pic addressing form.
113+ (UNSPEC_UNALIGNED_LOAD 30) ; Used to represent ldr/ldrh instructions that access
114+ ; unaligned locations, on architectures which support
115+ ; that.
116+ (UNSPEC_UNALIGNED_STORE 31) ; Same for str/strh.
117 ]
118 )
119
120@@ -2461,10 +2465,10 @@
121 ;;; this insv pattern, so this pattern needs to be reevalutated.
122
123 (define_expand "insv"
124- [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "")
125- (match_operand:SI 1 "general_operand" "")
126- (match_operand:SI 2 "general_operand" ""))
127- (match_operand:SI 3 "reg_or_int_operand" ""))]
128+ [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
129+ (match_operand 1 "general_operand" "")
130+ (match_operand 2 "general_operand" ""))
131+ (match_operand 3 "reg_or_int_operand" ""))]
132 "TARGET_ARM || arm_arch_thumb2"
133 "
134 {
135@@ -2475,35 +2479,70 @@
136
137 if (arm_arch_thumb2)
138 {
139- bool use_bfi = TRUE;
140-
141- if (GET_CODE (operands[3]) == CONST_INT)
142+ if (unaligned_access && MEM_P (operands[0])
143+ && s_register_operand (operands[3], GET_MODE (operands[3]))
144+ && (width == 16 || width == 32) && (start_bit % BITS_PER_UNIT) == 0)
145 {
146- HOST_WIDE_INT val = INTVAL (operands[3]) & mask;
147+ rtx base_addr;
148+
149+ if (BYTES_BIG_ENDIAN)
150+ start_bit = GET_MODE_BITSIZE (GET_MODE (operands[3])) - width
151+ - start_bit;
152
153- if (val == 0)
154+ if (width == 32)
155 {
156- emit_insn (gen_insv_zero (operands[0], operands[1],
157- operands[2]));
158- DONE;
159+ base_addr = adjust_address (operands[0], SImode,
160+ start_bit / BITS_PER_UNIT);
161+ emit_insn (gen_unaligned_storesi (base_addr, operands[3]));
162 }
163+ else
164+ {
165+ rtx tmp = gen_reg_rtx (HImode);
166
167- /* See if the set can be done with a single orr instruction. */
168- if (val == mask && const_ok_for_arm (val << start_bit))
169- use_bfi = FALSE;
170+ base_addr = adjust_address (operands[0], HImode,
171+ start_bit / BITS_PER_UNIT);
172+ emit_move_insn (tmp, gen_lowpart (HImode, operands[3]));
173+ emit_insn (gen_unaligned_storehi (base_addr, tmp));
174+ }
175+ DONE;
176 }
177-
178- if (use_bfi)
179+ else if (s_register_operand (operands[0], GET_MODE (operands[0])))
180 {
181- if (GET_CODE (operands[3]) != REG)
182- operands[3] = force_reg (SImode, operands[3]);
183+ bool use_bfi = TRUE;
184
185- emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2],
186- operands[3]));
187- DONE;
188+ if (GET_CODE (operands[3]) == CONST_INT)
189+ {
190+ HOST_WIDE_INT val = INTVAL (operands[3]) & mask;
191+
192+ if (val == 0)
193+ {
194+ emit_insn (gen_insv_zero (operands[0], operands[1],
195+ operands[2]));
196+ DONE;
197+ }
198+
199+ /* See if the set can be done with a single orr instruction. */
200+ if (val == mask && const_ok_for_arm (val << start_bit))
201+ use_bfi = FALSE;
202+ }
203+
204+ if (use_bfi)
205+ {
206+ if (GET_CODE (operands[3]) != REG)
207+ operands[3] = force_reg (SImode, operands[3]);
208+
209+ emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2],
210+ operands[3]));
211+ DONE;
212+ }
213 }
214+ else
215+ FAIL;
216 }
217
218+ if (!s_register_operand (operands[0], GET_MODE (operands[0])))
219+ FAIL;
220+
221 target = copy_rtx (operands[0]);
222 /* Avoid using a subreg as a subtarget, and avoid writing a paradoxical
223 subreg as the final target. */
224@@ -3695,12 +3734,10 @@
225 ;; to reduce register pressure later on.
226
227 (define_expand "extzv"
228- [(set (match_dup 4)
229- (ashift:SI (match_operand:SI 1 "register_operand" "")
230- (match_operand:SI 2 "const_int_operand" "")))
231- (set (match_operand:SI 0 "register_operand" "")
232- (lshiftrt:SI (match_dup 4)
233- (match_operand:SI 3 "const_int_operand" "")))]
234+ [(set (match_operand 0 "s_register_operand" "")
235+ (zero_extract (match_operand 1 "nonimmediate_operand" "")
236+ (match_operand 2 "const_int_operand" "")
237+ (match_operand 3 "const_int_operand" "")))]
238 "TARGET_THUMB1 || arm_arch_thumb2"
239 "
240 {
241@@ -3709,10 +3746,57 @@
242
243 if (arm_arch_thumb2)
244 {
245- emit_insn (gen_extzv_t2 (operands[0], operands[1], operands[2],
246- operands[3]));
247- DONE;
248+ HOST_WIDE_INT width = INTVAL (operands[2]);
249+ HOST_WIDE_INT bitpos = INTVAL (operands[3]);
250+
251+ if (unaligned_access && MEM_P (operands[1])
252+ && (width == 16 || width == 32) && (bitpos % BITS_PER_UNIT) == 0)
253+ {
254+ rtx base_addr;
255+
256+ if (BYTES_BIG_ENDIAN)
257+ bitpos = GET_MODE_BITSIZE (GET_MODE (operands[0])) - width
258+ - bitpos;
259+
260+ if (width == 32)
261+ {
262+ base_addr = adjust_address (operands[1], SImode,
263+ bitpos / BITS_PER_UNIT);
264+ emit_insn (gen_unaligned_loadsi (operands[0], base_addr));
265+ }
266+ else
267+ {
268+ rtx dest = operands[0];
269+ rtx tmp = gen_reg_rtx (SImode);
270+
271+ /* We may get a paradoxical subreg here. Strip it off. */
272+ if (GET_CODE (dest) == SUBREG
273+ && GET_MODE (dest) == SImode
274+ && GET_MODE (SUBREG_REG (dest)) == HImode)
275+ dest = SUBREG_REG (dest);
276+
277+ if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
278+ FAIL;
279+
280+ base_addr = adjust_address (operands[1], HImode,
281+ bitpos / BITS_PER_UNIT);
282+ emit_insn (gen_unaligned_loadhiu (tmp, base_addr));
283+ emit_move_insn (gen_lowpart (SImode, dest), tmp);
284+ }
285+ DONE;
286+ }
287+ else if (s_register_operand (operands[1], GET_MODE (operands[1])))
288+ {
289+ emit_insn (gen_extzv_t2 (operands[0], operands[1], operands[2],
290+ operands[3]));
291+ DONE;
292+ }
293+ else
294+ FAIL;
295 }
296+
297+ if (!s_register_operand (operands[1], GET_MODE (operands[1])))
298+ FAIL;
299
300 operands[3] = GEN_INT (rshift);
301
302@@ -3722,12 +3806,154 @@
303 DONE;
304 }
305
306- operands[2] = GEN_INT (lshift);
307- operands[4] = gen_reg_rtx (SImode);
308+ emit_insn (gen_extzv_t1 (operands[0], operands[1], GEN_INT (lshift),
309+ operands[3], gen_reg_rtx (SImode)));
310+ DONE;
311 }"
312 )
313
314-(define_insn "extv"
315+;; Helper for extzv, for the Thumb-1 register-shifts case.
316+
317+(define_expand "extzv_t1"
318+ [(set (match_operand:SI 4 "s_register_operand" "")
319+ (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
320+ (match_operand:SI 2 "const_int_operand" "")))
321+ (set (match_operand:SI 0 "s_register_operand" "")
322+ (lshiftrt:SI (match_dup 4)
323+ (match_operand:SI 3 "const_int_operand" "")))]
324+ "TARGET_THUMB1"
325+ "")
326+
327+(define_expand "extv"
328+ [(set (match_operand 0 "s_register_operand" "")
329+ (sign_extract (match_operand 1 "nonimmediate_operand" "")
330+ (match_operand 2 "const_int_operand" "")
331+ (match_operand 3 "const_int_operand" "")))]
332+ "arm_arch_thumb2"
333+{
334+ HOST_WIDE_INT width = INTVAL (operands[2]);
335+ HOST_WIDE_INT bitpos = INTVAL (operands[3]);
336+
337+ if (unaligned_access && MEM_P (operands[1]) && (width == 16 || width == 32)
338+ && (bitpos % BITS_PER_UNIT) == 0)
339+ {
340+ rtx base_addr;
341+
342+ if (BYTES_BIG_ENDIAN)
343+ bitpos = GET_MODE_BITSIZE (GET_MODE (operands[0])) - width - bitpos;
344+
345+ if (width == 32)
346+ {
347+ base_addr = adjust_address (operands[1], SImode,
348+ bitpos / BITS_PER_UNIT);
349+ emit_insn (gen_unaligned_loadsi (operands[0], base_addr));
350+ }
351+ else
352+ {
353+ rtx dest = operands[0];
354+ rtx tmp = gen_reg_rtx (SImode);
355+
356+ /* We may get a paradoxical subreg here. Strip it off. */
357+ if (GET_CODE (dest) == SUBREG
358+ && GET_MODE (dest) == SImode
359+ && GET_MODE (SUBREG_REG (dest)) == HImode)
360+ dest = SUBREG_REG (dest);
361+
362+ if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
363+ FAIL;
364+
365+ base_addr = adjust_address (operands[1], HImode,
366+ bitpos / BITS_PER_UNIT);
367+ emit_insn (gen_unaligned_loadhis (tmp, base_addr));
368+ emit_move_insn (gen_lowpart (SImode, dest), tmp);
369+ }
370+
371+ DONE;
372+ }
373+ else if (!s_register_operand (operands[1], GET_MODE (operands[1])))
374+ FAIL;
375+ else if (GET_MODE (operands[0]) == SImode
376+ && GET_MODE (operands[1]) == SImode)
377+ {
378+ emit_insn (gen_extv_regsi (operands[0], operands[1], operands[2],
379+ operands[3]));
380+ DONE;
381+ }
382+
383+ FAIL;
384+})
385+
386+; Helper to expand register forms of extv with the proper modes.
387+
388+(define_expand "extv_regsi"
389+ [(set (match_operand:SI 0 "s_register_operand" "")
390+ (sign_extract:SI (match_operand:SI 1 "s_register_operand" "")
391+ (match_operand 2 "const_int_operand" "")
392+ (match_operand 3 "const_int_operand" "")))]
393+ ""
394+{
395+})
396+
397+; ARMv6+ unaligned load/store instructions (used for packed structure accesses).
398+
399+(define_insn "unaligned_loadsi"
400+ [(set (match_operand:SI 0 "s_register_operand" "=l,r")
401+ (unspec:SI [(match_operand:SI 1 "memory_operand" "Uw,m")]
402+ UNSPEC_UNALIGNED_LOAD))]
403+ "unaligned_access && TARGET_32BIT"
404+ "ldr%?\t%0, %1\t@ unaligned"
405+ [(set_attr "arch" "t2,any")
406+ (set_attr "length" "2,4")
407+ (set_attr "predicable" "yes")
408+ (set_attr "type" "load1")])
409+
410+(define_insn "unaligned_loadhis"
411+ [(set (match_operand:SI 0 "s_register_operand" "=l,r")
412+ (sign_extend:SI
413+ (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,m")]
414+ UNSPEC_UNALIGNED_LOAD)))]
415+ "unaligned_access && TARGET_32BIT"
416+ "ldr%(sh%)\t%0, %1\t@ unaligned"
417+ [(set_attr "arch" "t2,any")
418+ (set_attr "length" "2,4")
419+ (set_attr "predicable" "yes")
420+ (set_attr "type" "load_byte")])
421+
422+(define_insn "unaligned_loadhiu"
423+ [(set (match_operand:SI 0 "s_register_operand" "=l,r")
424+ (zero_extend:SI
425+ (unspec:HI [(match_operand:HI 1 "memory_operand" "Uw,m")]
426+ UNSPEC_UNALIGNED_LOAD)))]
427+ "unaligned_access && TARGET_32BIT"
428+ "ldr%(h%)\t%0, %1\t@ unaligned"
429+ [(set_attr "arch" "t2,any")
430+ (set_attr "length" "2,4")
431+ (set_attr "predicable" "yes")
432+ (set_attr "type" "load_byte")])
433+
434+(define_insn "unaligned_storesi"
435+ [(set (match_operand:SI 0 "memory_operand" "=Uw,m")
436+ (unspec:SI [(match_operand:SI 1 "s_register_operand" "l,r")]
437+ UNSPEC_UNALIGNED_STORE))]
438+ "unaligned_access && TARGET_32BIT"
439+ "str%?\t%1, %0\t@ unaligned"
440+ [(set_attr "arch" "t2,any")
441+ (set_attr "length" "2,4")
442+ (set_attr "predicable" "yes")
443+ (set_attr "type" "store1")])
444+
445+(define_insn "unaligned_storehi"
446+ [(set (match_operand:HI 0 "memory_operand" "=Uw,m")
447+ (unspec:HI [(match_operand:HI 1 "s_register_operand" "l,r")]
448+ UNSPEC_UNALIGNED_STORE))]
449+ "unaligned_access && TARGET_32BIT"
450+ "str%(h%)\t%1, %0\t@ unaligned"
451+ [(set_attr "arch" "t2,any")
452+ (set_attr "length" "2,4")
453+ (set_attr "predicable" "yes")
454+ (set_attr "type" "store1")])
455+
456+(define_insn "*extv_reg"
457 [(set (match_operand:SI 0 "s_register_operand" "=r")
458 (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
459 (match_operand:SI 2 "const_int_operand" "M")
460@@ -6069,8 +6295,8 @@
461
462
463 (define_insn "*arm_movqi_insn"
464- [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
465- (match_operand:QI 1 "general_operand" "rI,K,m,r"))]
466+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,l,Uu,r,m")
467+ (match_operand:QI 1 "general_operand" "rI,K,Uu,l,m,r"))]
468 "TARGET_32BIT
469 && ( register_operand (operands[0], QImode)
470 || register_operand (operands[1], QImode))"
471@@ -6078,10 +6304,14 @@
472 mov%?\\t%0, %1
473 mvn%?\\t%0, #%B1
474 ldr%(b%)\\t%0, %1
475+ str%(b%)\\t%1, %0
476+ ldr%(b%)\\t%0, %1
477 str%(b%)\\t%1, %0"
478- [(set_attr "type" "*,*,load1,store1")
479- (set_attr "insn" "mov,mvn,*,*")
480- (set_attr "predicable" "yes")]
481+ [(set_attr "type" "*,*,load1,store1,load1,store1")
482+ (set_attr "insn" "mov,mvn,*,*,*,*")
483+ (set_attr "predicable" "yes")
484+ (set_attr "arch" "any,any,t2,t2,any,any")
485+ (set_attr "length" "4,4,2,2,4,4")]
486 )
487
488 (define_insn "*thumb1_movqi_insn"
489Index: gcc-4_6-branch/gcc/config/arm/arm.opt
490===================================================================
491--- gcc-4_6-branch.orig/gcc/config/arm/arm.opt 2012-03-05 16:07:14.000000000 -0800
492+++ gcc-4_6-branch/gcc/config/arm/arm.opt 2012-03-05 16:07:50.404936697 -0800
493@@ -173,3 +173,7 @@
494 Target Report Var(fix_cm3_ldrd) Init(2)
495 Avoid overlapping destination and address registers on LDRD instructions
496 that may trigger Cortex-M3 errata.
497+
498+munaligned-access
499+Target Report Var(unaligned_access) Init(2)
500+Enable unaligned word and halfword accesses to packed data.
501Index: gcc-4_6-branch/gcc/config/arm/constraints.md
502===================================================================
503--- gcc-4_6-branch.orig/gcc/config/arm/constraints.md 2012-03-05 16:07:14.000000000 -0800
504+++ gcc-4_6-branch/gcc/config/arm/constraints.md 2012-03-05 16:07:50.404936697 -0800
505@@ -36,6 +36,7 @@
506 ;; The following memory constraints have been used:
507 ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
508 ;; in ARM state: Uq
509+;; in Thumb state: Uu, Uw
510
511
512 (define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
513@@ -344,6 +345,27 @@
514 (and (match_code "mem")
515 (match_test "REG_P (XEXP (op, 0))")))
516
517+(define_memory_constraint "Uu"
518+ "@internal
519+ In Thumb state an address that is valid in 16bit encoding."
520+ (and (match_code "mem")
521+ (match_test "TARGET_THUMB
522+ && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
523+ 0)")))
524+
525+; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
526+; are actually LDM/STM instructions, so cannot be used to access unaligned
527+; data.
528+(define_memory_constraint "Uw"
529+ "@internal
530+ In Thumb state an address that is valid in 16bit encoding, and that can be
531+ used for unaligned accesses."
532+ (and (match_code "mem")
533+ (match_test "TARGET_THUMB
534+ && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
535+ 0)
536+ && GET_CODE (XEXP (op, 0)) != POST_INC")))
537+
538 ;; We used to have constraint letters for S and R in ARM state, but
539 ;; all uses of these now appear to have been removed.
540
541Index: gcc-4_6-branch/gcc/expmed.c
542===================================================================
543--- gcc-4_6-branch.orig/gcc/expmed.c 2012-01-04 15:37:51.000000000 -0800
544+++ gcc-4_6-branch/gcc/expmed.c 2012-03-05 16:07:50.404936697 -0800
545@@ -657,6 +657,10 @@
546 && GET_MODE (value) != BLKmode
547 && bitsize > 0
548 && GET_MODE_BITSIZE (op_mode) >= bitsize
549+ /* Do not use insv for volatile bitfields when
550+ -fstrict-volatile-bitfields is in effect. */
551+ && !(MEM_P (op0) && MEM_VOLATILE_P (op0)
552+ && flag_strict_volatile_bitfields > 0)
553 && ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
554 && (bitsize + bitpos > GET_MODE_BITSIZE (op_mode)))
555 && insn_data[CODE_FOR_insv].operand[1].predicate (GEN_INT (bitsize),
556@@ -700,19 +704,21 @@
557 copy_back = true;
558 }
559
560- /* On big-endian machines, we count bits from the most significant.
561- If the bit field insn does not, we must invert. */
562-
563- if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
564- xbitpos = unit - bitsize - xbitpos;
565-
566 /* We have been counting XBITPOS within UNIT.
567 Count instead within the size of the register. */
568- if (BITS_BIG_ENDIAN && !MEM_P (xop0))
569+ if (BYTES_BIG_ENDIAN && !MEM_P (xop0))
570 xbitpos += GET_MODE_BITSIZE (op_mode) - unit;
571
572 unit = GET_MODE_BITSIZE (op_mode);
573
574+ /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
575+ "backwards" from the size of the unit we are inserting into.
576+ Otherwise, we count bits from the most significant on a
577+ BYTES/BITS_BIG_ENDIAN machine. */
578+
579+ if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
580+ xbitpos = unit - bitsize - xbitpos;
581+
582 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
583 value1 = value;
584 if (GET_MODE (value) != op_mode)
585@@ -1528,6 +1534,10 @@
586 if (ext_mode != MAX_MACHINE_MODE
587 && bitsize > 0
588 && GET_MODE_BITSIZE (ext_mode) >= bitsize
589+ /* Do not use extv/extzv for volatile bitfields when
590+ -fstrict-volatile-bitfields is in effect. */
591+ && !(MEM_P (op0) && MEM_VOLATILE_P (op0)
592+ && flag_strict_volatile_bitfields > 0)
593 /* If op0 is a register, we need it in EXT_MODE to make it
594 acceptable to the format of ext(z)v. */
595 && !(GET_CODE (op0) == SUBREG && GET_MODE (op0) != ext_mode)
596@@ -1552,17 +1562,20 @@
597 /* Get ref to first byte containing part of the field. */
598 xop0 = adjust_address (xop0, byte_mode, xoffset);
599
600- /* On big-endian machines, we count bits from the most significant.
601- If the bit field insn does not, we must invert. */
602- if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
603- xbitpos = unit - bitsize - xbitpos;
604-
605 /* Now convert from counting within UNIT to counting in EXT_MODE. */
606- if (BITS_BIG_ENDIAN && !MEM_P (xop0))
607+ if (BYTES_BIG_ENDIAN && !MEM_P (xop0))
608 xbitpos += GET_MODE_BITSIZE (ext_mode) - unit;
609
610 unit = GET_MODE_BITSIZE (ext_mode);
611
612+ /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
613+ "backwards" from the size of the unit we are extracting from.
614+ Otherwise, we count bits from the most significant on a
615+ BYTES/BITS_BIG_ENDIAN machine. */
616+
617+ if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
618+ xbitpos = unit - bitsize - xbitpos;
619+
620 if (xtarget == 0)
621 xtarget = xspec_target = gen_reg_rtx (tmode);
622
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106828.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106828.patch
deleted file mode 100644
index 3c0ff0085..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106828.patch
+++ /dev/null
@@ -1,1951 +0,0 @@
12011-10-17 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-10-10 Richard Sandiford <richard.sandiford@linaro.org>
7
8 * modulo-sched.c (ps_reg_move_info): Add num_consecutive_stages.
9 (SCHED_FIRST_REG_MOVE, SCHED_NREG_MOVES): Delete.
10 (node_sched_params): Remove first_reg_move and nreg_moves.
11 (ps_num_consecutive_stages, extend_node_sched_params): New functions.
12 (update_node_sched_params): Move up file.
13 (print_node_sched_params): Print the stage. Don't dump info related
14 to first_reg_move and nreg_moves.
15 (set_columns_for_row): New function.
16 (set_columns_for_ps): Move up file and use set_columns_for_row.
17 (schedule_reg_move): New function.
18 (schedule_reg_moves): Call extend_node_sched_params and
19 schedule_reg_move. Extend size of uses bitmap. Initialize
20 num_consecutive_stages. Return false if a move could not be
21 scheduled.
22 (apply_reg_moves): Don't emit moves here.
23 (permute_partial_schedule): Handle register moves.
24 (duplicate_insns_of_cycles): Remove for_prolog. Emit moves according
25 to the same stage-count test as ddg nodes.
26 (generate_prolog_epilog): Update calls accordingly.
27 (sms_schedule): Allow move-scheduling to add a new first stage.
28
292011-10-17 Richard Sandiford <richard.sandiford@linaro.org>
30
31 gcc/
32 Backport from mainline:
33
34 2011-10-10 Richard Sandiford <richard.sandiford@linaro.org>
35
36 * modulo-sched.c (ps_insn): Adjust comment.
37 (ps_reg_move_info): New structure.
38 (partial_schedule): Add reg_moves field.
39 (SCHED_PARAMS): Use node_sched_param_vec instead of node_sched_params.
40 (node_sched_params): Turn first_reg_move into an identifier.
41 (ps_reg_move): New function.
42 (ps_rtl_insn): Cope with register moves.
43 (ps_first_note): Adjust comment and assert that the instruction
44 isn't a register move.
45 (node_sched_params): Replace with...
46 (node_sched_param_vec): ...this vector.
47 (set_node_sched_params): Adjust accordingly.
48 (print_node_sched_params): Take a partial schedule instead of a ddg.
49 Use ps_rtl_insn and ps_reg_move.
50 (generate_reg_moves): Rename to...
51 (schedule_reg_moves): ...this. Remove rescan parameter. Record each
52 move in the partial schedule, but don't emit it here. Don't perform
53 register substitutions here either.
54 (apply_reg_moves): New function.
55 (duplicate_insns_of_cycles): Use register indices directly,
56 rather than finding instructions using PREV_INSN. Use ps_reg_move.
57 (sms_schedule): Call schedule_reg_moves before committing to
58 a partial schedule. Try the next ii if the schedule fails.
59 Use apply_reg_moves instead of generate_reg_moves. Adjust
60 call to print_node_sched_params. Free node_sched_param_vec
61 instead of node_sched_params.
62 (create_partial_schedule): Initialize reg_moves.
63 (free_partial_schedule): Free reg_moves.
64
652011-10-17 Richard Sandiford <richard.sandiford@linaro.org>
66
67 gcc/
68 Backport from mainline:
69
70 2011-10-10 Richard Sandiford <richard.sandiford@linaro.org>
71
72 * modulo-sched.c (ps_insn): Replace node field with an identifier.
73 (SCHED_ASAP): Replace with..
74 (NODE_ASAP): ...this macro.
75 (SCHED_PARAMS): New macro.
76 (SCHED_TIME, SCHED_FIRST_REG_MOVE, SCHED_NREG_MOVES, SCHED_ROW)
77 (SCHED_STAGE, SCHED_COLUMN): Redefine using SCHED_PARAMS.
78 (node_sched_params): Remove asap.
79 (ps_rtl_insn, ps_first_note): New functions.
80 (set_node_sched_params): Use XCNEWVEC. Don't copy across the
81 asap values.
82 (print_node_sched_params): Use SCHED_PARAMS and NODE_ASAP.
83 (generate_reg_moves): Pass ids to the SCHED_* macros.
84 (update_node_sched_params): Take a ps insn identifier rather than
85 a node as parameter. Use ps_rtl_insn.
86 (set_columns_for_ps): Update for above field and SCHED_* macro changes.
87 (permute_partial_schedule): Use ps_rtl_insn and ps_first_note.
88 (optimize_sc): Update for above field and SCHED_* macro changes.
89 Update calls to try_scheduling_node_in_cycle and
90 update_node_sched_params.
91 (duplicate_insns_of_cycles): Adjust for above field and SCHED_*
92 macro changes. Use ps_rtl_insn and ps_first_note.
93 (sms_schedule): Pass ids to the SCHED_* macros.
94 (get_sched_window): Adjust for above field and SCHED_* macro changes.
95 Use NODE_ASAP instead of SCHED_ASAP.
96 (try_scheduling_node_in_cycle): Remove node parameter. Update
97 call to ps_add_node_check_conflicts. Pass ids to the SCHED_*
98 macros.
99 (sms_schedule_by_order): Update call to try_scheduling_node_in_cycle.
100 (ps_insert_empty_row): Adjust for above field changes.
101 (compute_split_row): Use ids rather than nodes.
102 (verify_partial_schedule): Adjust for above field changes.
103 (print_partial_schedule): Use ps_rtl_insn.
104 (create_ps_insn): Take an id rather than a node.
105 (ps_insn_find_column): Adjust for above field changes.
106 Use ps_rtl_insn.
107 (ps_insn_advance_column): Adjust for above field changes.
108 (add_node_to_ps): Remove node parameter. Update call to
109 create_ps_insn.
110 (ps_has_conflicts): Use ps_rtl_insn.
111 (ps_add_node_check_conflicts): Replace node parameter than an id.
112
1132011-10-17 Richard Sandiford <richard.sandiford@linaro.org>
114
115 gcc/
116 Backport from mainline:
117
118 2011-10-10 Richard Sandiford <richard.sandiford@linaro.org>
119
120 * modulo-sched.c (undo_replace_buff_elem): Delete.
121 (generate_reg_moves): Don't build and return an undo list.
122 (free_undo_replace_buff): Delete.
123 (sms_schedule): Adjust call to generate_reg_moves.
124 Don't call free_undo_replace_buff.
125
1262011-10-17 Richard Sandiford <richard.sandiford@linaro.org>
127
128 gcc/
129 Backport from mainline:
130
131 2011-08-08 Richard Sandiford <richard.sandiford@linaro.org>
132
133 * modulo-sched.c (get_sched_window): Use a table for the debug output.
134 Print the current ii.
135 (sms_schedule_by_order): Reduce whitespace in dump line.
136
1372011-10-17 Richard Sandiford <richard.sandiford@linaro.org>
138
139 gcc/
140 Backport from mainline:
141
142 2011-08-08 Richard Sandiford <richard.sandiford@linaro.org>
143
144 * modulo-sched.c (get_sched_window): Use just one loop for predecessors
145 and one loop for successors. Fix upper bound of memory range.
146
147=== modified file 'gcc/modulo-sched.c'
148--- old/gcc/modulo-sched.c 2011-10-02 06:56:53 +0000
149+++ new/gcc/modulo-sched.c 2011-10-10 14:35:32 +0000
150@@ -124,8 +124,10 @@
151 /* A single instruction in the partial schedule. */
152 struct ps_insn
153 {
154- /* The corresponding DDG_NODE. */
155- ddg_node_ptr node;
156+ /* Identifies the instruction to be scheduled. Values smaller than
157+ the ddg's num_nodes refer directly to ddg nodes. A value of
158+ X - num_nodes refers to register move X. */
159+ int id;
160
161 /* The (absolute) cycle in which the PS instruction is scheduled.
162 Same as SCHED_TIME (node). */
163@@ -137,6 +139,33 @@
164
165 };
166
167+/* Information about a register move that has been added to a partial
168+ schedule. */
169+struct ps_reg_move_info
170+{
171+ /* The source of the move is defined by the ps_insn with id DEF.
172+ The destination is used by the ps_insns with the ids in USES. */
173+ int def;
174+ sbitmap uses;
175+
176+ /* The original form of USES' instructions used OLD_REG, but they
177+ should now use NEW_REG. */
178+ rtx old_reg;
179+ rtx new_reg;
180+
181+ /* The number of consecutive stages that the move occupies. */
182+ int num_consecutive_stages;
183+
184+ /* An instruction that sets NEW_REG to the correct value. The first
185+ move associated with DEF will have an rhs of OLD_REG; later moves
186+ use the result of the previous move. */
187+ rtx insn;
188+};
189+
190+typedef struct ps_reg_move_info ps_reg_move_info;
191+DEF_VEC_O (ps_reg_move_info);
192+DEF_VEC_ALLOC_O (ps_reg_move_info, heap);
193+
194 /* Holds the partial schedule as an array of II rows. Each entry of the
195 array points to a linked list of PS_INSNs, which represents the
196 instructions that are scheduled for that row. */
197@@ -148,6 +177,10 @@
198 /* rows[i] points to linked list of insns scheduled in row i (0<=i<ii). */
199 ps_insn_ptr *rows;
200
201+ /* All the moves added for this partial schedule. Index X has
202+ a ps_insn id of X + g->num_nodes. */
203+ VEC (ps_reg_move_info, heap) *reg_moves;
204+
205 /* rows_length[i] holds the number of instructions in the row.
206 It is used only (as an optimization) to back off quickly from
207 trying to schedule a node in a full row; that is, to avoid running
208@@ -165,17 +198,6 @@
209 int stage_count; /* The stage count of the partial schedule. */
210 };
211
212-/* We use this to record all the register replacements we do in
213- the kernel so we can undo SMS if it is not profitable. */
214-struct undo_replace_buff_elem
215-{
216- rtx insn;
217- rtx orig_reg;
218- rtx new_reg;
219- struct undo_replace_buff_elem *next;
220-};
221-
222-
223
224 static partial_schedule_ptr create_partial_schedule (int ii, ddg_ptr, int history);
225 static void free_partial_schedule (partial_schedule_ptr);
226@@ -183,9 +205,7 @@
227 void print_partial_schedule (partial_schedule_ptr, FILE *);
228 static void verify_partial_schedule (partial_schedule_ptr, sbitmap);
229 static ps_insn_ptr ps_add_node_check_conflicts (partial_schedule_ptr,
230- ddg_node_ptr node, int cycle,
231- sbitmap must_precede,
232- sbitmap must_follow);
233+ int, int, sbitmap, sbitmap);
234 static void rotate_partial_schedule (partial_schedule_ptr, int);
235 void set_row_column_for_ps (partial_schedule_ptr);
236 static void ps_insert_empty_row (partial_schedule_ptr, int, sbitmap);
237@@ -201,43 +221,27 @@
238 static void permute_partial_schedule (partial_schedule_ptr, rtx);
239 static void generate_prolog_epilog (partial_schedule_ptr, struct loop *,
240 rtx, rtx);
241-static void duplicate_insns_of_cycles (partial_schedule_ptr,
242- int, int, int, rtx);
243 static int calculate_stage_count (partial_schedule_ptr, int);
244 static void calculate_must_precede_follow (ddg_node_ptr, int, int,
245 int, int, sbitmap, sbitmap, sbitmap);
246 static int get_sched_window (partial_schedule_ptr, ddg_node_ptr,
247 sbitmap, int, int *, int *, int *);
248-static bool try_scheduling_node_in_cycle (partial_schedule_ptr, ddg_node_ptr,
249- int, int, sbitmap, int *, sbitmap,
250- sbitmap);
251+static bool try_scheduling_node_in_cycle (partial_schedule_ptr, int, int,
252+ sbitmap, int *, sbitmap, sbitmap);
253 static void remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
254
255-#define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
256-#define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
257-#define SCHED_FIRST_REG_MOVE(x) \
258- (((node_sched_params_ptr)(x)->aux.info)->first_reg_move)
259-#define SCHED_NREG_MOVES(x) \
260- (((node_sched_params_ptr)(x)->aux.info)->nreg_moves)
261-#define SCHED_ROW(x) (((node_sched_params_ptr)(x)->aux.info)->row)
262-#define SCHED_STAGE(x) (((node_sched_params_ptr)(x)->aux.info)->stage)
263-#define SCHED_COLUMN(x) (((node_sched_params_ptr)(x)->aux.info)->column)
264+#define NODE_ASAP(node) ((node)->aux.count)
265+
266+#define SCHED_PARAMS(x) VEC_index (node_sched_params, node_sched_param_vec, x)
267+#define SCHED_TIME(x) (SCHED_PARAMS (x)->time)
268+#define SCHED_ROW(x) (SCHED_PARAMS (x)->row)
269+#define SCHED_STAGE(x) (SCHED_PARAMS (x)->stage)
270+#define SCHED_COLUMN(x) (SCHED_PARAMS (x)->column)
271
272 /* The scheduling parameters held for each node. */
273 typedef struct node_sched_params
274 {
275- int asap; /* A lower-bound on the absolute scheduling cycle. */
276- int time; /* The absolute scheduling cycle (time >= asap). */
277-
278- /* The following field (first_reg_move) is a pointer to the first
279- register-move instruction added to handle the modulo-variable-expansion
280- of the register defined by this node. This register-move copies the
281- original register defined by the node. */
282- rtx first_reg_move;
283-
284- /* The number of register-move instructions added, immediately preceding
285- first_reg_move. */
286- int nreg_moves;
287+ int time; /* The absolute scheduling cycle. */
288
289 int row; /* Holds time % ii. */
290 int stage; /* Holds time / ii. */
291@@ -247,6 +251,9 @@
292 int column;
293 } *node_sched_params_ptr;
294
295+typedef struct node_sched_params node_sched_params;
296+DEF_VEC_O (node_sched_params);
297+DEF_VEC_ALLOC_O (node_sched_params, heap);
298
299 /* The following three functions are copied from the current scheduler
300 code in order to use sched_analyze() for computing the dependencies.
301@@ -296,6 +303,49 @@
302 0
303 };
304
305+/* Partial schedule instruction ID in PS is a register move. Return
306+ information about it. */
307+static struct ps_reg_move_info *
308+ps_reg_move (partial_schedule_ptr ps, int id)
309+{
310+ gcc_checking_assert (id >= ps->g->num_nodes);
311+ return VEC_index (ps_reg_move_info, ps->reg_moves, id - ps->g->num_nodes);
312+}
313+
314+/* Return the rtl instruction that is being scheduled by partial schedule
315+ instruction ID, which belongs to schedule PS. */
316+static rtx
317+ps_rtl_insn (partial_schedule_ptr ps, int id)
318+{
319+ if (id < ps->g->num_nodes)
320+ return ps->g->nodes[id].insn;
321+ else
322+ return ps_reg_move (ps, id)->insn;
323+}
324+
325+/* Partial schedule instruction ID, which belongs to PS, occured in
326+ the original (unscheduled) loop. Return the first instruction
327+ in the loop that was associated with ps_rtl_insn (PS, ID).
328+ If the instruction had some notes before it, this is the first
329+ of those notes. */
330+static rtx
331+ps_first_note (partial_schedule_ptr ps, int id)
332+{
333+ gcc_assert (id < ps->g->num_nodes);
334+ return ps->g->nodes[id].first_note;
335+}
336+
337+/* Return the number of consecutive stages that are occupied by
338+ partial schedule instruction ID in PS. */
339+static int
340+ps_num_consecutive_stages (partial_schedule_ptr ps, int id)
341+{
342+ if (id < ps->g->num_nodes)
343+ return 1;
344+ else
345+ return ps_reg_move (ps, id)->num_consecutive_stages;
346+}
347+
348 /* Given HEAD and TAIL which are the first and last insns in a loop;
349 return the register which controls the loop. Return zero if it has
350 more than one occurrence in the loop besides the control part or the
351@@ -396,35 +446,59 @@
352 }
353
354
355-/* Points to the array that contains the sched data for each node. */
356-static node_sched_params_ptr node_sched_params;
357+/* A vector that contains the sched data for each ps_insn. */
358+static VEC (node_sched_params, heap) *node_sched_param_vec;
359
360-/* Allocate sched_params for each node and initialize it. Assumes that
361- the aux field of each node contain the asap bound (computed earlier),
362- and copies it into the sched_params field. */
363+/* Allocate sched_params for each node and initialize it. */
364 static void
365 set_node_sched_params (ddg_ptr g)
366 {
367- int i;
368-
369- /* Allocate for each node in the DDG a place to hold the "sched_data". */
370- /* Initialize ASAP/ALAP/HIGHT to zero. */
371- node_sched_params = (node_sched_params_ptr)
372- xcalloc (g->num_nodes,
373- sizeof (struct node_sched_params));
374-
375- /* Set the pointer of the general data of the node to point to the
376- appropriate sched_params structure. */
377- for (i = 0; i < g->num_nodes; i++)
378- {
379- /* Watch out for aliasing problems? */
380- node_sched_params[i].asap = g->nodes[i].aux.count;
381- g->nodes[i].aux.info = &node_sched_params[i];
382- }
383-}
384-
385-static void
386-print_node_sched_params (FILE *file, int num_nodes, ddg_ptr g)
387+ VEC_truncate (node_sched_params, node_sched_param_vec, 0);
388+ VEC_safe_grow_cleared (node_sched_params, heap,
389+ node_sched_param_vec, g->num_nodes);
390+}
391+
392+/* Make sure that node_sched_param_vec has an entry for every move in PS. */
393+static void
394+extend_node_sched_params (partial_schedule_ptr ps)
395+{
396+ VEC_safe_grow_cleared (node_sched_params, heap, node_sched_param_vec,
397+ ps->g->num_nodes + VEC_length (ps_reg_move_info,
398+ ps->reg_moves));
399+}
400+
401+/* Update the sched_params (time, row and stage) for node U using the II,
402+ the CYCLE of U and MIN_CYCLE.
403+ We're not simply taking the following
404+ SCHED_STAGE (u) = CALC_STAGE_COUNT (SCHED_TIME (u), min_cycle, ii);
405+ because the stages may not be aligned on cycle 0. */
406+static void
407+update_node_sched_params (int u, int ii, int cycle, int min_cycle)
408+{
409+ int sc_until_cycle_zero;
410+ int stage;
411+
412+ SCHED_TIME (u) = cycle;
413+ SCHED_ROW (u) = SMODULO (cycle, ii);
414+
415+ /* The calculation of stage count is done adding the number
416+ of stages before cycle zero and after cycle zero. */
417+ sc_until_cycle_zero = CALC_STAGE_COUNT (-1, min_cycle, ii);
418+
419+ if (SCHED_TIME (u) < 0)
420+ {
421+ stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
422+ SCHED_STAGE (u) = sc_until_cycle_zero - stage;
423+ }
424+ else
425+ {
426+ stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
427+ SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
428+ }
429+}
430+
431+static void
432+print_node_sched_params (FILE *file, int num_nodes, partial_schedule_ptr ps)
433 {
434 int i;
435
436@@ -432,22 +506,170 @@
437 return;
438 for (i = 0; i < num_nodes; i++)
439 {
440- node_sched_params_ptr nsp = &node_sched_params[i];
441- rtx reg_move = nsp->first_reg_move;
442- int j;
443+ node_sched_params_ptr nsp = SCHED_PARAMS (i);
444
445 fprintf (file, "Node = %d; INSN = %d\n", i,
446- (INSN_UID (g->nodes[i].insn)));
447- fprintf (file, " asap = %d:\n", nsp->asap);
448+ INSN_UID (ps_rtl_insn (ps, i)));
449+ fprintf (file, " asap = %d:\n", NODE_ASAP (&ps->g->nodes[i]));
450 fprintf (file, " time = %d:\n", nsp->time);
451- fprintf (file, " nreg_moves = %d:\n", nsp->nreg_moves);
452- for (j = 0; j < nsp->nreg_moves; j++)
453+ fprintf (file, " stage = %d:\n", nsp->stage);
454+ }
455+}
456+
457+/* Set SCHED_COLUMN for each instruction in row ROW of PS. */
458+static void
459+set_columns_for_row (partial_schedule_ptr ps, int row)
460+{
461+ ps_insn_ptr cur_insn;
462+ int column;
463+
464+ column = 0;
465+ for (cur_insn = ps->rows[row]; cur_insn; cur_insn = cur_insn->next_in_row)
466+ SCHED_COLUMN (cur_insn->id) = column++;
467+}
468+
469+/* Set SCHED_COLUMN for each instruction in PS. */
470+static void
471+set_columns_for_ps (partial_schedule_ptr ps)
472+{
473+ int row;
474+
475+ for (row = 0; row < ps->ii; row++)
476+ set_columns_for_row (ps, row);
477+}
478+
479+/* Try to schedule the move with ps_insn identifier I_REG_MOVE in PS.
480+ Its single predecessor has already been scheduled, as has its
481+ ddg node successors. (The move may have also another move as its
482+ successor, in which case that successor will be scheduled later.)
483+
484+ The move is part of a chain that satisfies register dependencies
485+ between a producing ddg node and various consuming ddg nodes.
486+ If some of these dependencies have a distance of 1 (meaning that
487+ the use is upward-exposoed) then DISTANCE1_USES is nonnull and
488+ contains the set of uses with distance-1 dependencies.
489+ DISTANCE1_USES is null otherwise.
490+
491+ MUST_FOLLOW is a scratch bitmap that is big enough to hold
492+ all current ps_insn ids.
493+
494+ Return true on success. */
495+static bool
496+schedule_reg_move (partial_schedule_ptr ps, int i_reg_move,
497+ sbitmap distance1_uses, sbitmap must_follow)
498+{
499+ unsigned int u;
500+ int this_time, this_distance, this_start, this_end, this_latency;
501+ int start, end, c, ii;
502+ sbitmap_iterator sbi;
503+ ps_reg_move_info *move;
504+ rtx this_insn;
505+ ps_insn_ptr psi;
506+
507+ move = ps_reg_move (ps, i_reg_move);
508+ ii = ps->ii;
509+ if (dump_file)
510+ {
511+ fprintf (dump_file, "Scheduling register move INSN %d; ii = %d"
512+ ", min cycle = %d\n\n", INSN_UID (move->insn), ii,
513+ PS_MIN_CYCLE (ps));
514+ print_rtl_single (dump_file, move->insn);
515+ fprintf (dump_file, "\n%11s %11s %5s\n", "start", "end", "time");
516+ fprintf (dump_file, "=========== =========== =====\n");
517+ }
518+
519+ start = INT_MIN;
520+ end = INT_MAX;
521+
522+ /* For dependencies of distance 1 between a producer ddg node A
523+ and consumer ddg node B, we have a chain of dependencies:
524+
525+ A --(T,L1,1)--> M1 --(T,L2,0)--> M2 ... --(T,Ln,0)--> B
526+
527+ where Mi is the ith move. For dependencies of distance 0 between
528+ a producer ddg node A and consumer ddg node C, we have a chain of
529+ dependencies:
530+
531+ A --(T,L1',0)--> M1' --(T,L2',0)--> M2' ... --(T,Ln',0)--> C
532+
533+ where Mi' occupies the same position as Mi but occurs a stage later.
534+ We can only schedule each move once, so if we have both types of
535+ chain, we model the second as:
536+
537+ A --(T,L1',1)--> M1 --(T,L2',0)--> M2 ... --(T,Ln',-1)--> C
538+
539+ First handle the dependencies between the previously-scheduled
540+ predecessor and the move. */
541+ this_insn = ps_rtl_insn (ps, move->def);
542+ this_latency = insn_latency (this_insn, move->insn);
543+ this_distance = distance1_uses && move->def < ps->g->num_nodes ? 1 : 0;
544+ this_time = SCHED_TIME (move->def) - this_distance * ii;
545+ this_start = this_time + this_latency;
546+ this_end = this_time + ii;
547+ if (dump_file)
548+ fprintf (dump_file, "%11d %11d %5d %d --(T,%d,%d)--> %d\n",
549+ this_start, this_end, SCHED_TIME (move->def),
550+ INSN_UID (this_insn), this_latency, this_distance,
551+ INSN_UID (move->insn));
552+
553+ if (start < this_start)
554+ start = this_start;
555+ if (end > this_end)
556+ end = this_end;
557+
558+ /* Handle the dependencies between the move and previously-scheduled
559+ successors. */
560+ EXECUTE_IF_SET_IN_SBITMAP (move->uses, 0, u, sbi)
561+ {
562+ this_insn = ps_rtl_insn (ps, u);
563+ this_latency = insn_latency (move->insn, this_insn);
564+ if (distance1_uses && !TEST_BIT (distance1_uses, u))
565+ this_distance = -1;
566+ else
567+ this_distance = 0;
568+ this_time = SCHED_TIME (u) + this_distance * ii;
569+ this_start = this_time - ii;
570+ this_end = this_time - this_latency;
571+ if (dump_file)
572+ fprintf (dump_file, "%11d %11d %5d %d --(T,%d,%d)--> %d\n",
573+ this_start, this_end, SCHED_TIME (u), INSN_UID (move->insn),
574+ this_latency, this_distance, INSN_UID (this_insn));
575+
576+ if (start < this_start)
577+ start = this_start;
578+ if (end > this_end)
579+ end = this_end;
580+ }
581+
582+ if (dump_file)
583+ {
584+ fprintf (dump_file, "----------- ----------- -----\n");
585+ fprintf (dump_file, "%11d %11d %5s %s\n", start, end, "", "(max, min)");
586+ }
587+
588+ sbitmap_zero (must_follow);
589+ SET_BIT (must_follow, move->def);
590+
591+ start = MAX (start, end - (ii - 1));
592+ for (c = end; c >= start; c--)
593+ {
594+ psi = ps_add_node_check_conflicts (ps, i_reg_move, c,
595+ move->uses, must_follow);
596+ if (psi)
597 {
598- fprintf (file, " reg_move = ");
599- print_rtl_single (file, reg_move);
600- reg_move = PREV_INSN (reg_move);
601+ update_node_sched_params (i_reg_move, ii, c, PS_MIN_CYCLE (ps));
602+ if (dump_file)
603+ fprintf (dump_file, "\nScheduled register move INSN %d at"
604+ " time %d, row %d\n\n", INSN_UID (move->insn), c,
605+ SCHED_ROW (i_reg_move));
606+ return true;
607 }
608 }
609+
610+ if (dump_file)
611+ fprintf (dump_file, "\nNo available slot\n\n");
612+
613+ return false;
614 }
615
616 /*
617@@ -461,22 +683,23 @@
618 nreg_moves = ----------------------------------- + 1 - { dependence.
619 ii { 1 if not.
620 */
621-static struct undo_replace_buff_elem *
622-generate_reg_moves (partial_schedule_ptr ps, bool rescan)
623+static bool
624+schedule_reg_moves (partial_schedule_ptr ps)
625 {
626 ddg_ptr g = ps->g;
627 int ii = ps->ii;
628 int i;
629- struct undo_replace_buff_elem *reg_move_replaces = NULL;
630
631 for (i = 0; i < g->num_nodes; i++)
632 {
633 ddg_node_ptr u = &g->nodes[i];
634 ddg_edge_ptr e;
635 int nreg_moves = 0, i_reg_move;
636- sbitmap *uses_of_defs;
637- rtx last_reg_move;
638 rtx prev_reg, old_reg;
639+ int first_move;
640+ int distances[2];
641+ sbitmap must_follow;
642+ sbitmap distance1_uses;
643 rtx set = single_set (u->insn);
644
645 /* Skip instructions that do not set a register. */
646@@ -485,18 +708,21 @@
647
648 /* Compute the number of reg_moves needed for u, by looking at life
649 ranges started at u (excluding self-loops). */
650+ distances[0] = distances[1] = false;
651 for (e = u->out; e; e = e->next_out)
652 if (e->type == TRUE_DEP && e->dest != e->src)
653 {
654- int nreg_moves4e = (SCHED_TIME (e->dest) - SCHED_TIME (e->src)) / ii;
655+ int nreg_moves4e = (SCHED_TIME (e->dest->cuid)
656+ - SCHED_TIME (e->src->cuid)) / ii;
657
658 if (e->distance == 1)
659- nreg_moves4e = (SCHED_TIME (e->dest) - SCHED_TIME (e->src) + ii) / ii;
660+ nreg_moves4e = (SCHED_TIME (e->dest->cuid)
661+ - SCHED_TIME (e->src->cuid) + ii) / ii;
662
663 /* If dest precedes src in the schedule of the kernel, then dest
664 will read before src writes and we can save one reg_copy. */
665- if (SCHED_ROW (e->dest) == SCHED_ROW (e->src)
666- && SCHED_COLUMN (e->dest) < SCHED_COLUMN (e->src))
667+ if (SCHED_ROW (e->dest->cuid) == SCHED_ROW (e->src->cuid)
668+ && SCHED_COLUMN (e->dest->cuid) < SCHED_COLUMN (e->src->cuid))
669 nreg_moves4e--;
670
671 if (nreg_moves4e >= 1)
672@@ -513,125 +739,105 @@
673 gcc_assert (!autoinc_var_is_used_p (u->insn, e->dest->insn));
674 }
675
676+ if (nreg_moves4e)
677+ {
678+ gcc_assert (e->distance < 2);
679+ distances[e->distance] = true;
680+ }
681 nreg_moves = MAX (nreg_moves, nreg_moves4e);
682 }
683
684 if (nreg_moves == 0)
685 continue;
686
687+ /* Create NREG_MOVES register moves. */
688+ first_move = VEC_length (ps_reg_move_info, ps->reg_moves);
689+ VEC_safe_grow_cleared (ps_reg_move_info, heap, ps->reg_moves,
690+ first_move + nreg_moves);
691+ extend_node_sched_params (ps);
692+
693+ /* Record the moves associated with this node. */
694+ first_move += ps->g->num_nodes;
695+
696+ /* Generate each move. */
697+ old_reg = prev_reg = SET_DEST (single_set (u->insn));
698+ for (i_reg_move = 0; i_reg_move < nreg_moves; i_reg_move++)
699+ {
700+ ps_reg_move_info *move = ps_reg_move (ps, first_move + i_reg_move);
701+
702+ move->def = i_reg_move > 0 ? first_move + i_reg_move - 1 : i;
703+ move->uses = sbitmap_alloc (first_move + nreg_moves);
704+ move->old_reg = old_reg;
705+ move->new_reg = gen_reg_rtx (GET_MODE (prev_reg));
706+ move->num_consecutive_stages = distances[0] && distances[1] ? 2 : 1;
707+ move->insn = gen_move_insn (move->new_reg, copy_rtx (prev_reg));
708+ sbitmap_zero (move->uses);
709+
710+ prev_reg = move->new_reg;
711+ }
712+
713+ distance1_uses = distances[1] ? sbitmap_alloc (g->num_nodes) : NULL;
714+
715 /* Every use of the register defined by node may require a different
716 copy of this register, depending on the time the use is scheduled.
717- Set a bitmap vector, telling which nodes use each copy of this
718- register. */
719- uses_of_defs = sbitmap_vector_alloc (nreg_moves, g->num_nodes);
720- sbitmap_vector_zero (uses_of_defs, nreg_moves);
721+ Record which uses require which move results. */
722 for (e = u->out; e; e = e->next_out)
723 if (e->type == TRUE_DEP && e->dest != e->src)
724 {
725- int dest_copy = (SCHED_TIME (e->dest) - SCHED_TIME (e->src)) / ii;
726+ int dest_copy = (SCHED_TIME (e->dest->cuid)
727+ - SCHED_TIME (e->src->cuid)) / ii;
728
729 if (e->distance == 1)
730- dest_copy = (SCHED_TIME (e->dest) - SCHED_TIME (e->src) + ii) / ii;
731+ dest_copy = (SCHED_TIME (e->dest->cuid)
732+ - SCHED_TIME (e->src->cuid) + ii) / ii;
733
734- if (SCHED_ROW (e->dest) == SCHED_ROW (e->src)
735- && SCHED_COLUMN (e->dest) < SCHED_COLUMN (e->src))
736+ if (SCHED_ROW (e->dest->cuid) == SCHED_ROW (e->src->cuid)
737+ && SCHED_COLUMN (e->dest->cuid) < SCHED_COLUMN (e->src->cuid))
738 dest_copy--;
739
740 if (dest_copy)
741- SET_BIT (uses_of_defs[dest_copy - 1], e->dest->cuid);
742+ {
743+ ps_reg_move_info *move;
744+
745+ move = ps_reg_move (ps, first_move + dest_copy - 1);
746+ SET_BIT (move->uses, e->dest->cuid);
747+ if (e->distance == 1)
748+ SET_BIT (distance1_uses, e->dest->cuid);
749+ }
750 }
751
752- /* Now generate the reg_moves, attaching relevant uses to them. */
753- SCHED_NREG_MOVES (u) = nreg_moves;
754- old_reg = prev_reg = copy_rtx (SET_DEST (single_set (u->insn)));
755- /* Insert the reg-moves right before the notes which precede
756- the insn they relates to. */
757- last_reg_move = u->first_note;
758-
759+ must_follow = sbitmap_alloc (first_move + nreg_moves);
760 for (i_reg_move = 0; i_reg_move < nreg_moves; i_reg_move++)
761+ if (!schedule_reg_move (ps, first_move + i_reg_move,
762+ distance1_uses, must_follow))
763+ break;
764+ sbitmap_free (must_follow);
765+ if (distance1_uses)
766+ sbitmap_free (distance1_uses);
767+ if (i_reg_move < nreg_moves)
768+ return false;
769+ }
770+ return true;
771+}
772+
773+/* Emit the moves associatied with PS. Apply the substitutions
774+ associated with them. */
775+static void
776+apply_reg_moves (partial_schedule_ptr ps)
777+{
778+ ps_reg_move_info *move;
779+ int i;
780+
781+ FOR_EACH_VEC_ELT (ps_reg_move_info, ps->reg_moves, i, move)
782+ {
783+ unsigned int i_use;
784+ sbitmap_iterator sbi;
785+
786+ EXECUTE_IF_SET_IN_SBITMAP (move->uses, 0, i_use, sbi)
787 {
788- unsigned int i_use = 0;
789- rtx new_reg = gen_reg_rtx (GET_MODE (prev_reg));
790- rtx reg_move = gen_move_insn (new_reg, prev_reg);
791- sbitmap_iterator sbi;
792-
793- add_insn_before (reg_move, last_reg_move, NULL);
794- last_reg_move = reg_move;
795-
796- if (!SCHED_FIRST_REG_MOVE (u))
797- SCHED_FIRST_REG_MOVE (u) = reg_move;
798-
799- EXECUTE_IF_SET_IN_SBITMAP (uses_of_defs[i_reg_move], 0, i_use, sbi)
800- {
801- struct undo_replace_buff_elem *rep;
802-
803- rep = (struct undo_replace_buff_elem *)
804- xcalloc (1, sizeof (struct undo_replace_buff_elem));
805- rep->insn = g->nodes[i_use].insn;
806- rep->orig_reg = old_reg;
807- rep->new_reg = new_reg;
808-
809- if (! reg_move_replaces)
810- reg_move_replaces = rep;
811- else
812- {
813- rep->next = reg_move_replaces;
814- reg_move_replaces = rep;
815- }
816-
817- replace_rtx (g->nodes[i_use].insn, old_reg, new_reg);
818- if (rescan)
819- df_insn_rescan (g->nodes[i_use].insn);
820- }
821-
822- prev_reg = new_reg;
823+ replace_rtx (ps->g->nodes[i_use].insn, move->old_reg, move->new_reg);
824+ df_insn_rescan (ps->g->nodes[i_use].insn);
825 }
826- sbitmap_vector_free (uses_of_defs);
827- }
828- return reg_move_replaces;
829-}
830-
831-/* Free memory allocated for the undo buffer. */
832-static void
833-free_undo_replace_buff (struct undo_replace_buff_elem *reg_move_replaces)
834-{
835-
836- while (reg_move_replaces)
837- {
838- struct undo_replace_buff_elem *rep = reg_move_replaces;
839-
840- reg_move_replaces = reg_move_replaces->next;
841- free (rep);
842- }
843-}
844-
845-/* Update the sched_params (time, row and stage) for node U using the II,
846- the CYCLE of U and MIN_CYCLE.
847- We're not simply taking the following
848- SCHED_STAGE (u) = CALC_STAGE_COUNT (SCHED_TIME (u), min_cycle, ii);
849- because the stages may not be aligned on cycle 0. */
850-static void
851-update_node_sched_params (ddg_node_ptr u, int ii, int cycle, int min_cycle)
852-{
853- int sc_until_cycle_zero;
854- int stage;
855-
856- SCHED_TIME (u) = cycle;
857- SCHED_ROW (u) = SMODULO (cycle, ii);
858-
859- /* The calculation of stage count is done adding the number
860- of stages before cycle zero and after cycle zero. */
861- sc_until_cycle_zero = CALC_STAGE_COUNT (-1, min_cycle, ii);
862-
863- if (SCHED_TIME (u) < 0)
864- {
865- stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
866- SCHED_STAGE (u) = sc_until_cycle_zero - stage;
867- }
868- else
869- {
870- stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
871- SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
872 }
873 }
874
875@@ -647,18 +853,19 @@
876 for (row = 0; row < ii; row++)
877 for (crr_insn = ps->rows[row]; crr_insn; crr_insn = crr_insn->next_in_row)
878 {
879- ddg_node_ptr u = crr_insn->node;
880+ int u = crr_insn->id;
881 int normalized_time = SCHED_TIME (u) - amount;
882 int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
883
884 if (dump_file)
885 {
886 /* Print the scheduling times after the rotation. */
887+ rtx insn = ps_rtl_insn (ps, u);
888+
889 fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
890- "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
891- INSN_UID (crr_insn->node->insn), normalized_time,
892- new_min_cycle);
893- if (JUMP_P (crr_insn->node->insn))
894+ "crr_insn->cycle=%d, min_cycle=%d", u,
895+ INSN_UID (insn), normalized_time, new_min_cycle);
896+ if (JUMP_P (insn))
897 fprintf (dump_file, " (branch)");
898 fprintf (dump_file, "\n");
899 }
900@@ -671,22 +878,6 @@
901 }
902 }
903
904-/* Set SCHED_COLUMN of each node according to its position in PS. */
905-static void
906-set_columns_for_ps (partial_schedule_ptr ps)
907-{
908- int row;
909-
910- for (row = 0; row < ps->ii; row++)
911- {
912- ps_insn_ptr cur_insn = ps->rows[row];
913- int column = 0;
914-
915- for (; cur_insn; cur_insn = cur_insn->next_in_row)
916- SCHED_COLUMN (cur_insn->node) = column++;
917- }
918-}
919-
920 /* Permute the insns according to their order in PS, from row 0 to
921 row ii-1, and position them right before LAST. This schedules
922 the insns of the loop kernel. */
923@@ -699,9 +890,18 @@
924
925 for (row = 0; row < ii ; row++)
926 for (ps_ij = ps->rows[row]; ps_ij; ps_ij = ps_ij->next_in_row)
927- if (PREV_INSN (last) != ps_ij->node->insn)
928- reorder_insns_nobb (ps_ij->node->first_note, ps_ij->node->insn,
929- PREV_INSN (last));
930+ {
931+ rtx insn = ps_rtl_insn (ps, ps_ij->id);
932+
933+ if (PREV_INSN (last) != insn)
934+ {
935+ if (ps_ij->id < ps->g->num_nodes)
936+ reorder_insns_nobb (ps_first_note (ps, ps_ij->id), insn,
937+ PREV_INSN (last));
938+ else
939+ add_insn_before (insn, last, NULL);
940+ }
941+ }
942 }
943
944 /* Set bitmaps TMP_FOLLOW and TMP_PRECEDE to MUST_FOLLOW and MUST_PRECEDE
945@@ -750,7 +950,7 @@
946 to row ii-1. If they are equal just bail out. */
947 stage_count = calculate_stage_count (ps, amount);
948 stage_count_curr =
949- calculate_stage_count (ps, SCHED_TIME (g->closing_branch) - (ii - 1));
950+ calculate_stage_count (ps, SCHED_TIME (g->closing_branch->cuid) - (ii - 1));
951
952 if (stage_count == stage_count_curr)
953 {
954@@ -779,7 +979,7 @@
955 print_partial_schedule (ps, dump_file);
956 }
957
958- if (SMODULO (SCHED_TIME (g->closing_branch), ii) == ii - 1)
959+ if (SMODULO (SCHED_TIME (g->closing_branch->cuid), ii) == ii - 1)
960 {
961 ok = true;
962 goto clear;
963@@ -794,7 +994,7 @@
964 {
965 bool success;
966 ps_insn_ptr next_ps_i;
967- int branch_cycle = SCHED_TIME (g->closing_branch);
968+ int branch_cycle = SCHED_TIME (g->closing_branch->cuid);
969 int row = SMODULO (branch_cycle, ps->ii);
970 int num_splits = 0;
971 sbitmap must_precede, must_follow, tmp_precede, tmp_follow;
972@@ -850,13 +1050,12 @@
973 branch so we can remove it from it's current cycle. */
974 for (next_ps_i = ps->rows[row];
975 next_ps_i; next_ps_i = next_ps_i->next_in_row)
976- if (next_ps_i->node->cuid == g->closing_branch->cuid)
977+ if (next_ps_i->id == g->closing_branch->cuid)
978 break;
979
980 remove_node_from_ps (ps, next_ps_i);
981 success =
982- try_scheduling_node_in_cycle (ps, g->closing_branch,
983- g->closing_branch->cuid, c,
984+ try_scheduling_node_in_cycle (ps, g->closing_branch->cuid, c,
985 sched_nodes, &num_splits,
986 tmp_precede, tmp_follow);
987 gcc_assert (num_splits == 0);
988@@ -874,8 +1073,7 @@
989 must_precede, branch_cycle, start, end,
990 step);
991 success =
992- try_scheduling_node_in_cycle (ps, g->closing_branch,
993- g->closing_branch->cuid,
994+ try_scheduling_node_in_cycle (ps, g->closing_branch->cuid,
995 branch_cycle, sched_nodes,
996 &num_splits, tmp_precede,
997 tmp_follow);
998@@ -889,7 +1087,7 @@
999 fprintf (dump_file,
1000 "SMS success in moving branch to cycle %d\n", c);
1001
1002- update_node_sched_params (g->closing_branch, ii, c,
1003+ update_node_sched_params (g->closing_branch->cuid, ii, c,
1004 PS_MIN_CYCLE (ps));
1005 ok = true;
1006 }
1007@@ -905,7 +1103,7 @@
1008
1009 static void
1010 duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage,
1011- int to_stage, int for_prolog, rtx count_reg)
1012+ int to_stage, rtx count_reg)
1013 {
1014 int row;
1015 ps_insn_ptr ps_ij;
1016@@ -913,9 +1111,9 @@
1017 for (row = 0; row < ps->ii; row++)
1018 for (ps_ij = ps->rows[row]; ps_ij; ps_ij = ps_ij->next_in_row)
1019 {
1020- ddg_node_ptr u_node = ps_ij->node;
1021- int j, i_reg_moves;
1022- rtx reg_move = NULL_RTX;
1023+ int u = ps_ij->id;
1024+ int first_u, last_u;
1025+ rtx u_insn;
1026
1027 /* Do not duplicate any insn which refers to count_reg as it
1028 belongs to the control part.
1029@@ -923,52 +1121,20 @@
1030 be ignored.
1031 TODO: This should be done by analyzing the control part of
1032 the loop. */
1033- if (reg_mentioned_p (count_reg, u_node->insn)
1034- || JUMP_P (ps_ij->node->insn))
1035+ u_insn = ps_rtl_insn (ps, u);
1036+ if (reg_mentioned_p (count_reg, u_insn)
1037+ || JUMP_P (u_insn))
1038 continue;
1039
1040- if (for_prolog)
1041- {
1042- /* SCHED_STAGE (u_node) >= from_stage == 0. Generate increasing
1043- number of reg_moves starting with the second occurrence of
1044- u_node, which is generated if its SCHED_STAGE <= to_stage. */
1045- i_reg_moves = to_stage - SCHED_STAGE (u_node) + 1;
1046- i_reg_moves = MAX (i_reg_moves, 0);
1047- i_reg_moves = MIN (i_reg_moves, SCHED_NREG_MOVES (u_node));
1048-
1049- /* The reg_moves start from the *first* reg_move backwards. */
1050- if (i_reg_moves)
1051- {
1052- reg_move = SCHED_FIRST_REG_MOVE (u_node);
1053- for (j = 1; j < i_reg_moves; j++)
1054- reg_move = PREV_INSN (reg_move);
1055- }
1056- }
1057- else /* It's for the epilog. */
1058- {
1059- /* SCHED_STAGE (u_node) <= to_stage. Generate all reg_moves,
1060- starting to decrease one stage after u_node no longer occurs;
1061- that is, generate all reg_moves until
1062- SCHED_STAGE (u_node) == from_stage - 1. */
1063- i_reg_moves = SCHED_NREG_MOVES (u_node)
1064- - (from_stage - SCHED_STAGE (u_node) - 1);
1065- i_reg_moves = MAX (i_reg_moves, 0);
1066- i_reg_moves = MIN (i_reg_moves, SCHED_NREG_MOVES (u_node));
1067-
1068- /* The reg_moves start from the *last* reg_move forwards. */
1069- if (i_reg_moves)
1070- {
1071- reg_move = SCHED_FIRST_REG_MOVE (u_node);
1072- for (j = 1; j < SCHED_NREG_MOVES (u_node); j++)
1073- reg_move = PREV_INSN (reg_move);
1074- }
1075- }
1076-
1077- for (j = 0; j < i_reg_moves; j++, reg_move = NEXT_INSN (reg_move))
1078- emit_insn (copy_rtx (PATTERN (reg_move)));
1079- if (SCHED_STAGE (u_node) >= from_stage
1080- && SCHED_STAGE (u_node) <= to_stage)
1081- duplicate_insn_chain (u_node->first_note, u_node->insn);
1082+ first_u = SCHED_STAGE (u);
1083+ last_u = first_u + ps_num_consecutive_stages (ps, u) - 1;
1084+ if (from_stage <= last_u && to_stage >= first_u)
1085+ {
1086+ if (u < ps->g->num_nodes)
1087+ duplicate_insn_chain (ps_first_note (ps, u), u_insn);
1088+ else
1089+ emit_insn (copy_rtx (PATTERN (u_insn)));
1090+ }
1091 }
1092 }
1093
1094@@ -1002,7 +1168,7 @@
1095 }
1096
1097 for (i = 0; i < last_stage; i++)
1098- duplicate_insns_of_cycles (ps, 0, i, 1, count_reg);
1099+ duplicate_insns_of_cycles (ps, 0, i, count_reg);
1100
1101 /* Put the prolog on the entry edge. */
1102 e = loop_preheader_edge (loop);
1103@@ -1014,7 +1180,7 @@
1104 start_sequence ();
1105
1106 for (i = 0; i < last_stage; i++)
1107- duplicate_insns_of_cycles (ps, i + 1, last_stage, 0, count_reg);
1108+ duplicate_insns_of_cycles (ps, i + 1, last_stage, count_reg);
1109
1110 /* Put the epilogue on the exit edge. */
1111 gcc_assert (single_exit (loop));
1112@@ -1350,10 +1516,9 @@
1113 {
1114 rtx head, tail;
1115 rtx count_reg, count_init;
1116- int mii, rec_mii;
1117- unsigned stage_count = 0;
1118+ int mii, rec_mii, stage_count, min_cycle;
1119 HOST_WIDEST_INT loop_count = 0;
1120- bool opt_sc_p = false;
1121+ bool opt_sc_p;
1122
1123 if (! (g = g_arr[loop->num]))
1124 continue;
1125@@ -1430,62 +1595,63 @@
1126 fprintf (dump_file, "SMS iis %d %d %d (rec_mii, mii, maxii)\n",
1127 rec_mii, mii, maxii);
1128
1129- /* After sms_order_nodes and before sms_schedule_by_order, to copy over
1130- ASAP. */
1131- set_node_sched_params (g);
1132-
1133- ps = sms_schedule_by_order (g, mii, maxii, node_order);
1134-
1135- if (ps)
1136+ for (;;)
1137 {
1138- /* Try to achieve optimized SC by normalizing the partial
1139- schedule (having the cycles start from cycle zero).
1140- The branch location must be placed in row ii-1 in the
1141- final scheduling. If failed, shift all instructions to
1142- position the branch in row ii-1. */
1143- opt_sc_p = optimize_sc (ps, g);
1144- if (opt_sc_p)
1145- stage_count = calculate_stage_count (ps, 0);
1146- else
1147+ set_node_sched_params (g);
1148+
1149+ stage_count = 0;
1150+ opt_sc_p = false;
1151+ ps = sms_schedule_by_order (g, mii, maxii, node_order);
1152+
1153+ if (ps)
1154 {
1155- /* Bring the branch to cycle ii-1. */
1156- int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1);
1157+ /* Try to achieve optimized SC by normalizing the partial
1158+ schedule (having the cycles start from cycle zero).
1159+ The branch location must be placed in row ii-1 in the
1160+ final scheduling. If failed, shift all instructions to
1161+ position the branch in row ii-1. */
1162+ opt_sc_p = optimize_sc (ps, g);
1163+ if (opt_sc_p)
1164+ stage_count = calculate_stage_count (ps, 0);
1165+ else
1166+ {
1167+ /* Bring the branch to cycle ii-1. */
1168+ int amount = (SCHED_TIME (g->closing_branch->cuid)
1169+ - (ps->ii - 1));
1170
1171+ if (dump_file)
1172+ fprintf (dump_file, "SMS schedule branch at cycle ii-1\n");
1173+
1174+ stage_count = calculate_stage_count (ps, amount);
1175+ }
1176+
1177+ gcc_assert (stage_count >= 1);
1178+ }
1179+
1180+ /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
1181+ 1 means that there is no interleaving between iterations thus
1182+ we let the scheduling passes do the job in this case. */
1183+ if (stage_count < PARAM_VALUE (PARAM_SMS_MIN_SC)
1184+ || (count_init && (loop_count <= stage_count))
1185+ || (flag_branch_probabilities && (trip_count <= stage_count)))
1186+ {
1187 if (dump_file)
1188- fprintf (dump_file, "SMS schedule branch at cycle ii-1\n");
1189-
1190- stage_count = calculate_stage_count (ps, amount);
1191- }
1192-
1193- gcc_assert (stage_count >= 1);
1194- PS_STAGE_COUNT (ps) = stage_count;
1195- }
1196-
1197- /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
1198- 1 means that there is no interleaving between iterations thus
1199- we let the scheduling passes do the job in this case. */
1200- if (stage_count < (unsigned) PARAM_VALUE (PARAM_SMS_MIN_SC)
1201- || (count_init && (loop_count <= stage_count))
1202- || (flag_branch_probabilities && (trip_count <= stage_count)))
1203- {
1204- if (dump_file)
1205- {
1206- fprintf (dump_file, "SMS failed... \n");
1207- fprintf (dump_file, "SMS sched-failed (stage-count=%d, loop-count=", stage_count);
1208- fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, loop_count);
1209- fprintf (dump_file, ", trip-count=");
1210- fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count);
1211- fprintf (dump_file, ")\n");
1212- }
1213- }
1214- else
1215- {
1216- struct undo_replace_buff_elem *reg_move_replaces;
1217+ {
1218+ fprintf (dump_file, "SMS failed... \n");
1219+ fprintf (dump_file, "SMS sched-failed (stage-count=%d,"
1220+ " loop-count=", stage_count);
1221+ fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, loop_count);
1222+ fprintf (dump_file, ", trip-count=");
1223+ fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count);
1224+ fprintf (dump_file, ")\n");
1225+ }
1226+ break;
1227+ }
1228
1229 if (!opt_sc_p)
1230 {
1231 /* Rotate the partial schedule to have the branch in row ii-1. */
1232- int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1);
1233+ int amount = SCHED_TIME (g->closing_branch->cuid) - (ps->ii - 1);
1234
1235 reset_sched_times (ps, amount);
1236 rotate_partial_schedule (ps, amount);
1237@@ -1493,6 +1659,29 @@
1238
1239 set_columns_for_ps (ps);
1240
1241+ min_cycle = PS_MIN_CYCLE (ps) - SMODULO (PS_MIN_CYCLE (ps), ps->ii);
1242+ if (!schedule_reg_moves (ps))
1243+ {
1244+ mii = ps->ii + 1;
1245+ free_partial_schedule (ps);
1246+ continue;
1247+ }
1248+
1249+ /* Moves that handle incoming values might have been added
1250+ to a new first stage. Bump the stage count if so.
1251+
1252+ ??? Perhaps we could consider rotating the schedule here
1253+ instead? */
1254+ if (PS_MIN_CYCLE (ps) < min_cycle)
1255+ {
1256+ reset_sched_times (ps, 0);
1257+ stage_count++;
1258+ }
1259+
1260+ /* The stage count should now be correct without rotation. */
1261+ gcc_checking_assert (stage_count == calculate_stage_count (ps, 0));
1262+ PS_STAGE_COUNT (ps) = stage_count;
1263+
1264 canon_loop (loop);
1265
1266 if (dump_file)
1267@@ -1531,17 +1720,16 @@
1268 /* The life-info is not valid any more. */
1269 df_set_bb_dirty (g->bb);
1270
1271- reg_move_replaces = generate_reg_moves (ps, true);
1272+ apply_reg_moves (ps);
1273 if (dump_file)
1274- print_node_sched_params (dump_file, g->num_nodes, g);
1275+ print_node_sched_params (dump_file, g->num_nodes, ps);
1276 /* Generate prolog and epilog. */
1277 generate_prolog_epilog (ps, loop, count_reg, count_init);
1278-
1279- free_undo_replace_buff (reg_move_replaces);
1280+ break;
1281 }
1282
1283 free_partial_schedule (ps);
1284- free (node_sched_params);
1285+ VEC_free (node_sched_params, heap, node_sched_param_vec);
1286 free (node_order);
1287 free_ddg (g);
1288 }
1289@@ -1643,9 +1831,11 @@
1290
1291 static int
1292 get_sched_window (partial_schedule_ptr ps, ddg_node_ptr u_node,
1293- sbitmap sched_nodes, int ii, int *start_p, int *step_p, int *end_p)
1294+ sbitmap sched_nodes, int ii, int *start_p, int *step_p,
1295+ int *end_p)
1296 {
1297 int start, step, end;
1298+ int early_start, late_start;
1299 ddg_edge_ptr e;
1300 sbitmap psp = sbitmap_alloc (ps->g->num_nodes);
1301 sbitmap pss = sbitmap_alloc (ps->g->num_nodes);
1302@@ -1653,6 +1843,8 @@
1303 sbitmap u_node_succs = NODE_SUCCESSORS (u_node);
1304 int psp_not_empty;
1305 int pss_not_empty;
1306+ int count_preds;
1307+ int count_succs;
1308
1309 /* 1. compute sched window for u (start, end, step). */
1310 sbitmap_zero (psp);
1311@@ -1660,214 +1852,119 @@
1312 psp_not_empty = sbitmap_a_and_b_cg (psp, u_node_preds, sched_nodes);
1313 pss_not_empty = sbitmap_a_and_b_cg (pss, u_node_succs, sched_nodes);
1314
1315- if (psp_not_empty && !pss_not_empty)
1316- {
1317- int early_start = INT_MIN;
1318-
1319- end = INT_MAX;
1320- for (e = u_node->in; e != 0; e = e->next_in)
1321- {
1322- ddg_node_ptr v_node = e->src;
1323-
1324- if (dump_file)
1325- {
1326- fprintf (dump_file, "\nProcessing edge: ");
1327- print_ddg_edge (dump_file, e);
1328- fprintf (dump_file,
1329- "\nScheduling %d (%d) in psp_not_empty,"
1330- " checking p %d (%d): ", u_node->cuid,
1331- INSN_UID (u_node->insn), v_node->cuid, INSN_UID
1332- (v_node->insn));
1333- }
1334-
1335- if (TEST_BIT (sched_nodes, v_node->cuid))
1336- {
1337- int p_st = SCHED_TIME (v_node);
1338-
1339- early_start =
1340- MAX (early_start, p_st + e->latency - (e->distance * ii));
1341-
1342- if (dump_file)
1343- fprintf (dump_file,
1344- "pred st = %d; early_start = %d; latency: %d",
1345- p_st, early_start, e->latency);
1346-
1347- if (e->data_type == MEM_DEP)
1348- end = MIN (end, SCHED_TIME (v_node) + ii - 1);
1349- }
1350- else if (dump_file)
1351- fprintf (dump_file, "the node is not scheduled\n");
1352- }
1353- start = early_start;
1354- end = MIN (end, early_start + ii);
1355- /* Schedule the node close to it's predecessors. */
1356- step = 1;
1357-
1358- if (dump_file)
1359- fprintf (dump_file,
1360- "\nScheduling %d (%d) in a window (%d..%d) with step %d\n",
1361- u_node->cuid, INSN_UID (u_node->insn), start, end, step);
1362- }
1363-
1364- else if (!psp_not_empty && pss_not_empty)
1365- {
1366- int late_start = INT_MAX;
1367-
1368- end = INT_MIN;
1369- for (e = u_node->out; e != 0; e = e->next_out)
1370- {
1371- ddg_node_ptr v_node = e->dest;
1372-
1373- if (dump_file)
1374- {
1375- fprintf (dump_file, "\nProcessing edge:");
1376- print_ddg_edge (dump_file, e);
1377- fprintf (dump_file,
1378- "\nScheduling %d (%d) in pss_not_empty,"
1379- " checking s %d (%d): ", u_node->cuid,
1380- INSN_UID (u_node->insn), v_node->cuid, INSN_UID
1381- (v_node->insn));
1382- }
1383-
1384- if (TEST_BIT (sched_nodes, v_node->cuid))
1385- {
1386- int s_st = SCHED_TIME (v_node);
1387-
1388- late_start = MIN (late_start,
1389- s_st - e->latency + (e->distance * ii));
1390-
1391- if (dump_file)
1392- fprintf (dump_file,
1393- "succ st = %d; late_start = %d; latency = %d",
1394- s_st, late_start, e->latency);
1395-
1396- if (e->data_type == MEM_DEP)
1397- end = MAX (end, SCHED_TIME (v_node) - ii + 1);
1398- if (dump_file)
1399- fprintf (dump_file, "end = %d\n", end);
1400-
1401- }
1402- else if (dump_file)
1403- fprintf (dump_file, "the node is not scheduled\n");
1404-
1405- }
1406- start = late_start;
1407- end = MAX (end, late_start - ii);
1408- /* Schedule the node close to it's successors. */
1409+ /* We first compute a forward range (start <= end), then decide whether
1410+ to reverse it. */
1411+ early_start = INT_MIN;
1412+ late_start = INT_MAX;
1413+ start = INT_MIN;
1414+ end = INT_MAX;
1415+ step = 1;
1416+
1417+ count_preds = 0;
1418+ count_succs = 0;
1419+
1420+ if (dump_file && (psp_not_empty || pss_not_empty))
1421+ {
1422+ fprintf (dump_file, "\nAnalyzing dependencies for node %d (INSN %d)"
1423+ "; ii = %d\n\n", u_node->cuid, INSN_UID (u_node->insn), ii);
1424+ fprintf (dump_file, "%11s %11s %11s %11s %5s\n",
1425+ "start", "early start", "late start", "end", "time");
1426+ fprintf (dump_file, "=========== =========== =========== ==========="
1427+ " =====\n");
1428+ }
1429+ /* Calculate early_start and limit end. Both bounds are inclusive. */
1430+ if (psp_not_empty)
1431+ for (e = u_node->in; e != 0; e = e->next_in)
1432+ {
1433+ int v = e->src->cuid;
1434+
1435+ if (TEST_BIT (sched_nodes, v))
1436+ {
1437+ int p_st = SCHED_TIME (v);
1438+ int earliest = p_st + e->latency - (e->distance * ii);
1439+ int latest = (e->data_type == MEM_DEP ? p_st + ii - 1 : INT_MAX);
1440+
1441+ if (dump_file)
1442+ {
1443+ fprintf (dump_file, "%11s %11d %11s %11d %5d",
1444+ "", earliest, "", latest, p_st);
1445+ print_ddg_edge (dump_file, e);
1446+ fprintf (dump_file, "\n");
1447+ }
1448+
1449+ early_start = MAX (early_start, earliest);
1450+ end = MIN (end, latest);
1451+
1452+ if (e->type == TRUE_DEP && e->data_type == REG_DEP)
1453+ count_preds++;
1454+ }
1455+ }
1456+
1457+ /* Calculate late_start and limit start. Both bounds are inclusive. */
1458+ if (pss_not_empty)
1459+ for (e = u_node->out; e != 0; e = e->next_out)
1460+ {
1461+ int v = e->dest->cuid;
1462+
1463+ if (TEST_BIT (sched_nodes, v))
1464+ {
1465+ int s_st = SCHED_TIME (v);
1466+ int earliest = (e->data_type == MEM_DEP ? s_st - ii + 1 : INT_MIN);
1467+ int latest = s_st - e->latency + (e->distance * ii);
1468+
1469+ if (dump_file)
1470+ {
1471+ fprintf (dump_file, "%11d %11s %11d %11s %5d",
1472+ earliest, "", latest, "", s_st);
1473+ print_ddg_edge (dump_file, e);
1474+ fprintf (dump_file, "\n");
1475+ }
1476+
1477+ start = MAX (start, earliest);
1478+ late_start = MIN (late_start, latest);
1479+
1480+ if (e->type == TRUE_DEP && e->data_type == REG_DEP)
1481+ count_succs++;
1482+ }
1483+ }
1484+
1485+ if (dump_file && (psp_not_empty || pss_not_empty))
1486+ {
1487+ fprintf (dump_file, "----------- ----------- ----------- -----------"
1488+ " -----\n");
1489+ fprintf (dump_file, "%11d %11d %11d %11d %5s %s\n",
1490+ start, early_start, late_start, end, "",
1491+ "(max, max, min, min)");
1492+ }
1493+
1494+ /* Get a target scheduling window no bigger than ii. */
1495+ if (early_start == INT_MIN && late_start == INT_MAX)
1496+ early_start = NODE_ASAP (u_node);
1497+ else if (early_start == INT_MIN)
1498+ early_start = late_start - (ii - 1);
1499+ late_start = MIN (late_start, early_start + (ii - 1));
1500+
1501+ /* Apply memory dependence limits. */
1502+ start = MAX (start, early_start);
1503+ end = MIN (end, late_start);
1504+
1505+ if (dump_file && (psp_not_empty || pss_not_empty))
1506+ fprintf (dump_file, "%11s %11d %11d %11s %5s final window\n",
1507+ "", start, end, "", "");
1508+
1509+ /* If there are at least as many successors as predecessors, schedule the
1510+ node close to its successors. */
1511+ if (pss_not_empty && count_succs >= count_preds)
1512+ {
1513+ int tmp = end;
1514+ end = start;
1515+ start = tmp;
1516 step = -1;
1517-
1518- if (dump_file)
1519- fprintf (dump_file,
1520- "\nScheduling %d (%d) in a window (%d..%d) with step %d\n",
1521- u_node->cuid, INSN_UID (u_node->insn), start, end, step);
1522-
1523- }
1524-
1525- else if (psp_not_empty && pss_not_empty)
1526- {
1527- int early_start = INT_MIN;
1528- int late_start = INT_MAX;
1529- int count_preds = 0;
1530- int count_succs = 0;
1531-
1532- start = INT_MIN;
1533- end = INT_MAX;
1534- for (e = u_node->in; e != 0; e = e->next_in)
1535- {
1536- ddg_node_ptr v_node = e->src;
1537-
1538- if (dump_file)
1539- {
1540- fprintf (dump_file, "\nProcessing edge:");
1541- print_ddg_edge (dump_file, e);
1542- fprintf (dump_file,
1543- "\nScheduling %d (%d) in psp_pss_not_empty,"
1544- " checking p %d (%d): ", u_node->cuid, INSN_UID
1545- (u_node->insn), v_node->cuid, INSN_UID
1546- (v_node->insn));
1547- }
1548-
1549- if (TEST_BIT (sched_nodes, v_node->cuid))
1550- {
1551- int p_st = SCHED_TIME (v_node);
1552-
1553- early_start = MAX (early_start,
1554- p_st + e->latency
1555- - (e->distance * ii));
1556-
1557- if (dump_file)
1558- fprintf (dump_file,
1559- "pred st = %d; early_start = %d; latency = %d",
1560- p_st, early_start, e->latency);
1561-
1562- if (e->type == TRUE_DEP && e->data_type == REG_DEP)
1563- count_preds++;
1564-
1565- if (e->data_type == MEM_DEP)
1566- end = MIN (end, SCHED_TIME (v_node) + ii - 1);
1567- }
1568- else if (dump_file)
1569- fprintf (dump_file, "the node is not scheduled\n");
1570-
1571- }
1572- for (e = u_node->out; e != 0; e = e->next_out)
1573- {
1574- ddg_node_ptr v_node = e->dest;
1575-
1576- if (dump_file)
1577- {
1578- fprintf (dump_file, "\nProcessing edge:");
1579- print_ddg_edge (dump_file, e);
1580- fprintf (dump_file,
1581- "\nScheduling %d (%d) in psp_pss_not_empty,"
1582- " checking s %d (%d): ", u_node->cuid, INSN_UID
1583- (u_node->insn), v_node->cuid, INSN_UID
1584- (v_node->insn));
1585- }
1586-
1587- if (TEST_BIT (sched_nodes, v_node->cuid))
1588- {
1589- int s_st = SCHED_TIME (v_node);
1590-
1591- late_start = MIN (late_start,
1592- s_st - e->latency
1593- + (e->distance * ii));
1594-
1595- if (dump_file)
1596- fprintf (dump_file,
1597- "succ st = %d; late_start = %d; latency = %d",
1598- s_st, late_start, e->latency);
1599-
1600- if (e->type == TRUE_DEP && e->data_type == REG_DEP)
1601- count_succs++;
1602-
1603- if (e->data_type == MEM_DEP)
1604- start = MAX (start, SCHED_TIME (v_node) - ii + 1);
1605- }
1606- else if (dump_file)
1607- fprintf (dump_file, "the node is not scheduled\n");
1608-
1609- }
1610- start = MAX (start, early_start);
1611- end = MIN (end, MIN (early_start + ii, late_start + 1));
1612- step = 1;
1613- /* If there are more successors than predecessors schedule the
1614- node close to it's successors. */
1615- if (count_succs >= count_preds)
1616- {
1617- int old_start = start;
1618-
1619- start = end - 1;
1620- end = old_start - 1;
1621- step = -1;
1622- }
1623- }
1624- else /* psp is empty && pss is empty. */
1625- {
1626- start = SCHED_ASAP (u_node);
1627- end = start + ii;
1628- step = 1;
1629- }
1630+ }
1631+
1632+ /* Now that we've finalized the window, make END an exclusive rather
1633+ than an inclusive bound. */
1634+ end += step;
1635
1636 *start_p = start;
1637 *step_p = step;
1638@@ -1880,10 +1977,10 @@
1639 if (dump_file)
1640 fprintf (dump_file, "\nEmpty window: start=%d, end=%d, step=%d\n",
1641 start, end, step);
1642- return -1;
1643+ return -1;
1644 }
1645
1646- return 0;
1647+ return 0;
1648 }
1649
1650 /* Calculate MUST_PRECEDE/MUST_FOLLOW bitmaps of U_NODE; which is the
1651@@ -1939,7 +2036,7 @@
1652 SCHED_TIME (e->src) - (e->distance * ii) == first_cycle_in_window */
1653 for (e = u_node->in; e != 0; e = e->next_in)
1654 if (TEST_BIT (sched_nodes, e->src->cuid)
1655- && ((SCHED_TIME (e->src) - (e->distance * ii)) ==
1656+ && ((SCHED_TIME (e->src->cuid) - (e->distance * ii)) ==
1657 first_cycle_in_window))
1658 {
1659 if (dump_file)
1660@@ -1964,7 +2061,7 @@
1661 SCHED_TIME (e->dest) + (e->distance * ii) == last_cycle_in_window */
1662 for (e = u_node->out; e != 0; e = e->next_out)
1663 if (TEST_BIT (sched_nodes, e->dest->cuid)
1664- && ((SCHED_TIME (e->dest) + (e->distance * ii)) ==
1665+ && ((SCHED_TIME (e->dest->cuid) + (e->distance * ii)) ==
1666 last_cycle_in_window))
1667 {
1668 if (dump_file)
1669@@ -1988,7 +2085,7 @@
1670 last row of the scheduling window) */
1671
1672 static bool
1673-try_scheduling_node_in_cycle (partial_schedule_ptr ps, ddg_node_ptr u_node,
1674+try_scheduling_node_in_cycle (partial_schedule_ptr ps,
1675 int u, int cycle, sbitmap sched_nodes,
1676 int *num_splits, sbitmap must_precede,
1677 sbitmap must_follow)
1678@@ -1997,11 +2094,10 @@
1679 bool success = 0;
1680
1681 verify_partial_schedule (ps, sched_nodes);
1682- psi = ps_add_node_check_conflicts (ps, u_node, cycle,
1683- must_precede, must_follow);
1684+ psi = ps_add_node_check_conflicts (ps, u, cycle, must_precede, must_follow);
1685 if (psi)
1686 {
1687- SCHED_TIME (u_node) = cycle;
1688+ SCHED_TIME (u) = cycle;
1689 SET_BIT (sched_nodes, u);
1690 success = 1;
1691 *num_splits = 0;
1692@@ -2062,8 +2158,8 @@
1693 &step, &end) == 0)
1694 {
1695 if (dump_file)
1696- fprintf (dump_file, "\nTrying to schedule node %d \
1697- INSN = %d in (%d .. %d) step %d\n", u, (INSN_UID
1698+ fprintf (dump_file, "\nTrying to schedule node %d "
1699+ "INSN = %d in (%d .. %d) step %d\n", u, (INSN_UID
1700 (g->nodes[u].insn)), start, end, step);
1701
1702 gcc_assert ((step > 0 && start < end)
1703@@ -2081,7 +2177,7 @@
1704 &tmp_precede, must_precede,
1705 c, start, end, step);
1706 success =
1707- try_scheduling_node_in_cycle (ps, u_node, u, c,
1708+ try_scheduling_node_in_cycle (ps, u, c,
1709 sched_nodes,
1710 &num_splits, tmp_precede,
1711 tmp_follow);
1712@@ -2181,7 +2277,7 @@
1713 for (crr_insn = rows_new[row];
1714 crr_insn; crr_insn = crr_insn->next_in_row)
1715 {
1716- ddg_node_ptr u = crr_insn->node;
1717+ int u = crr_insn->id;
1718 int new_time = SCHED_TIME (u) + (SCHED_TIME (u) / ii);
1719
1720 SCHED_TIME (u) = new_time;
1721@@ -2202,7 +2298,7 @@
1722 for (crr_insn = rows_new[row + 1];
1723 crr_insn; crr_insn = crr_insn->next_in_row)
1724 {
1725- ddg_node_ptr u = crr_insn->node;
1726+ int u = crr_insn->id;
1727 int new_time = SCHED_TIME (u) + (SCHED_TIME (u) / ii) + 1;
1728
1729 SCHED_TIME (u) = new_time;
1730@@ -2242,24 +2338,24 @@
1731 {
1732 ddg_edge_ptr e;
1733 int lower = INT_MIN, upper = INT_MAX;
1734- ddg_node_ptr crit_pred = NULL;
1735- ddg_node_ptr crit_succ = NULL;
1736+ int crit_pred = -1;
1737+ int crit_succ = -1;
1738 int crit_cycle;
1739
1740 for (e = u_node->in; e != 0; e = e->next_in)
1741 {
1742- ddg_node_ptr v_node = e->src;
1743+ int v = e->src->cuid;
1744
1745- if (TEST_BIT (sched_nodes, v_node->cuid)
1746- && (low == SCHED_TIME (v_node) + e->latency - (e->distance * ii)))
1747- if (SCHED_TIME (v_node) > lower)
1748+ if (TEST_BIT (sched_nodes, v)
1749+ && (low == SCHED_TIME (v) + e->latency - (e->distance * ii)))
1750+ if (SCHED_TIME (v) > lower)
1751 {
1752- crit_pred = v_node;
1753- lower = SCHED_TIME (v_node);
1754+ crit_pred = v;
1755+ lower = SCHED_TIME (v);
1756 }
1757 }
1758
1759- if (crit_pred != NULL)
1760+ if (crit_pred >= 0)
1761 {
1762 crit_cycle = SCHED_TIME (crit_pred) + 1;
1763 return SMODULO (crit_cycle, ii);
1764@@ -2267,17 +2363,18 @@
1765
1766 for (e = u_node->out; e != 0; e = e->next_out)
1767 {
1768- ddg_node_ptr v_node = e->dest;
1769- if (TEST_BIT (sched_nodes, v_node->cuid)
1770- && (up == SCHED_TIME (v_node) - e->latency + (e->distance * ii)))
1771- if (SCHED_TIME (v_node) < upper)
1772+ int v = e->dest->cuid;
1773+
1774+ if (TEST_BIT (sched_nodes, v)
1775+ && (up == SCHED_TIME (v) - e->latency + (e->distance * ii)))
1776+ if (SCHED_TIME (v) < upper)
1777 {
1778- crit_succ = v_node;
1779- upper = SCHED_TIME (v_node);
1780+ crit_succ = v;
1781+ upper = SCHED_TIME (v);
1782 }
1783 }
1784
1785- if (crit_succ != NULL)
1786+ if (crit_succ >= 0)
1787 {
1788 crit_cycle = SCHED_TIME (crit_succ);
1789 return SMODULO (crit_cycle, ii);
1790@@ -2301,10 +2398,10 @@
1791
1792 for (crr_insn = ps->rows[row]; crr_insn; crr_insn = crr_insn->next_in_row)
1793 {
1794- ddg_node_ptr u = crr_insn->node;
1795+ int u = crr_insn->id;
1796
1797 length++;
1798- gcc_assert (TEST_BIT (sched_nodes, u->cuid));
1799+ gcc_assert (TEST_BIT (sched_nodes, u));
1800 /* ??? Test also that all nodes of sched_nodes are in ps, perhaps by
1801 popcount (sched_nodes) == number of insns in ps. */
1802 gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
1803@@ -2719,6 +2816,7 @@
1804 partial_schedule_ptr ps = XNEW (struct partial_schedule);
1805 ps->rows = (ps_insn_ptr *) xcalloc (ii, sizeof (ps_insn_ptr));
1806 ps->rows_length = (int *) xcalloc (ii, sizeof (int));
1807+ ps->reg_moves = NULL;
1808 ps->ii = ii;
1809 ps->history = history;
1810 ps->min_cycle = INT_MAX;
1811@@ -2753,8 +2851,16 @@
1812 static void
1813 free_partial_schedule (partial_schedule_ptr ps)
1814 {
1815+ ps_reg_move_info *move;
1816+ unsigned int i;
1817+
1818 if (!ps)
1819 return;
1820+
1821+ FOR_EACH_VEC_ELT (ps_reg_move_info, ps->reg_moves, i, move)
1822+ sbitmap_free (move->uses);
1823+ VEC_free (ps_reg_move_info, heap, ps->reg_moves);
1824+
1825 free_ps_insns (ps);
1826 free (ps->rows);
1827 free (ps->rows_length);
1828@@ -2796,12 +2902,12 @@
1829 fprintf (dump, "\n[ROW %d ]: ", i);
1830 while (ps_i)
1831 {
1832- if (JUMP_P (ps_i->node->insn))
1833- fprintf (dump, "%d (branch), ",
1834- INSN_UID (ps_i->node->insn));
1835+ rtx insn = ps_rtl_insn (ps, ps_i->id);
1836+
1837+ if (JUMP_P (insn))
1838+ fprintf (dump, "%d (branch), ", INSN_UID (insn));
1839 else
1840- fprintf (dump, "%d, ",
1841- INSN_UID (ps_i->node->insn));
1842+ fprintf (dump, "%d, ", INSN_UID (insn));
1843
1844 ps_i = ps_i->next_in_row;
1845 }
1846@@ -2810,11 +2916,11 @@
1847
1848 /* Creates an object of PS_INSN and initializes it to the given parameters. */
1849 static ps_insn_ptr
1850-create_ps_insn (ddg_node_ptr node, int cycle)
1851+create_ps_insn (int id, int cycle)
1852 {
1853 ps_insn_ptr ps_i = XNEW (struct ps_insn);
1854
1855- ps_i->node = node;
1856+ ps_i->id = id;
1857 ps_i->next_in_row = NULL;
1858 ps_i->prev_in_row = NULL;
1859 ps_i->cycle = cycle;
1860@@ -2879,10 +2985,11 @@
1861 next_ps_i;
1862 next_ps_i = next_ps_i->next_in_row)
1863 {
1864- if (must_follow && TEST_BIT (must_follow, next_ps_i->node->cuid)
1865+ if (must_follow
1866+ && TEST_BIT (must_follow, next_ps_i->id)
1867 && ! first_must_follow)
1868 first_must_follow = next_ps_i;
1869- if (must_precede && TEST_BIT (must_precede, next_ps_i->node->cuid))
1870+ if (must_precede && TEST_BIT (must_precede, next_ps_i->id))
1871 {
1872 /* If we have already met a node that must follow, then
1873 there is no possible column. */
1874@@ -2893,8 +3000,8 @@
1875 }
1876 /* The closing branch must be the last in the row. */
1877 if (must_precede
1878- && TEST_BIT (must_precede, next_ps_i->node->cuid)
1879- && JUMP_P (next_ps_i->node->insn))
1880+ && TEST_BIT (must_precede, next_ps_i->id)
1881+ && JUMP_P (ps_rtl_insn (ps, next_ps_i->id)))
1882 return false;
1883
1884 last_in_row = next_ps_i;
1885@@ -2903,7 +3010,7 @@
1886 /* The closing branch is scheduled as well. Make sure there is no
1887 dependent instruction after it as the branch should be the last
1888 instruction in the row. */
1889- if (JUMP_P (ps_i->node->insn))
1890+ if (JUMP_P (ps_rtl_insn (ps, ps_i->id)))
1891 {
1892 if (first_must_follow)
1893 return false;
1894@@ -2954,7 +3061,6 @@
1895 {
1896 ps_insn_ptr prev, next;
1897 int row;
1898- ddg_node_ptr next_node;
1899
1900 if (!ps || !ps_i)
1901 return false;
1902@@ -2964,11 +3070,9 @@
1903 if (! ps_i->next_in_row)
1904 return false;
1905
1906- next_node = ps_i->next_in_row->node;
1907-
1908 /* Check if next_in_row is dependent on ps_i, both having same sched
1909 times (typically ANTI_DEP). If so, ps_i cannot skip over it. */
1910- if (must_follow && TEST_BIT (must_follow, next_node->cuid))
1911+ if (must_follow && TEST_BIT (must_follow, ps_i->next_in_row->id))
1912 return false;
1913
1914 /* Advance PS_I over its next_in_row in the doubly linked list. */
1915@@ -2999,7 +3103,7 @@
1916 before/after (respectively) the node pointed to by PS_I when scheduled
1917 in the same cycle. */
1918 static ps_insn_ptr
1919-add_node_to_ps (partial_schedule_ptr ps, ddg_node_ptr node, int cycle,
1920+add_node_to_ps (partial_schedule_ptr ps, int id, int cycle,
1921 sbitmap must_precede, sbitmap must_follow)
1922 {
1923 ps_insn_ptr ps_i;
1924@@ -3008,7 +3112,7 @@
1925 if (ps->rows_length[row] >= issue_rate)
1926 return NULL;
1927
1928- ps_i = create_ps_insn (node, cycle);
1929+ ps_i = create_ps_insn (id, cycle);
1930
1931 /* Finds and inserts PS_I according to MUST_FOLLOW and
1932 MUST_PRECEDE. */
1933@@ -3060,7 +3164,7 @@
1934 crr_insn;
1935 crr_insn = crr_insn->next_in_row)
1936 {
1937- rtx insn = crr_insn->node->insn;
1938+ rtx insn = ps_rtl_insn (ps, crr_insn->id);
1939
1940 if (!NONDEBUG_INSN_P (insn))
1941 continue;
1942@@ -3097,7 +3201,7 @@
1943 cuid N must be come before/after (respectively) the node pointed to by
1944 PS_I when scheduled in the same cycle. */
1945 ps_insn_ptr
1946-ps_add_node_check_conflicts (partial_schedule_ptr ps, ddg_node_ptr n,
1947+ps_add_node_check_conflicts (partial_schedule_ptr ps, int n,
1948 int c, sbitmap must_precede,
1949 sbitmap must_follow)
1950 {
1951
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106829.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106829.patch
deleted file mode 100644
index 02f8e5177..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106829.patch
+++ /dev/null
@@ -1,147 +0,0 @@
12011-10-19 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF:
4
5 2011-09-09 Andrew Stubbs <ams@codesourcery.com>
6
7 gcc/
8 * config/arm/arm-cores.def (generic-armv7-a): New architecture.
9 * config/arm/arm-tables.opt: Regenerate.
10 * config/arm/arm-tune.md: Regenerate.
11 * config/arm/arm.c (arm_file_start): Output .arch directive when
12 user passes -mcpu=generic-*.
13 (arm_issue_rate): Add genericv7a support.
14 * config/arm/arm.h (EXTRA_SPECS): Add asm_cpu_spec.
15 (ASM_CPU_SPEC): New define.
16 * config/arm/elf.h (ASM_SPEC): Use %(asm_cpu_spec).
17 * config/arm/semi.h (ASM_SPEC): Likewise.
18 * doc/invoke.texi (ARM Options): Document -mcpu=generic-*
19 and -mtune=generic-*.
20
21=== modified file 'gcc/config/arm/arm-cores.def'
22--- old/gcc/config/arm/arm-cores.def 2011-06-14 16:00:30 +0000
23+++ new/gcc/config/arm/arm-cores.def 2011-10-19 16:46:51 +0000
24@@ -124,6 +124,7 @@
25 ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e)
26 ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, v6t2)
27 ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, v6t2)
28+ARM_CORE("generic-armv7-a", genericv7a, 7A, FL_LDSCHED, cortex)
29 ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5)
30 ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex)
31 ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9)
32@@ -135,3 +136,4 @@
33 ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, cortex)
34 ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, cortex)
35 ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, cortex)
36+
37
38=== modified file 'gcc/config/arm/arm-tune.md'
39--- old/gcc/config/arm/arm-tune.md 2011-06-14 14:37:30 +0000
40+++ new/gcc/config/arm/arm-tune.md 2011-10-19 16:46:51 +0000
41@@ -1,5 +1,5 @@
42 ;; -*- buffer-read-only: t -*-
43 ;; Generated automatically by gentune.sh from arm-cores.def
44 (define_attr "tune"
45- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
46+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
47 (const (symbol_ref "((enum attr_tune) arm_tune)")))
48
49=== modified file 'gcc/config/arm/arm.c'
50--- old/gcc/config/arm/arm.c 2011-10-11 02:31:01 +0000
51+++ new/gcc/config/arm/arm.c 2011-10-19 16:46:51 +0000
52@@ -22185,6 +22185,8 @@
53 const char *fpu_name;
54 if (arm_selected_arch)
55 asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name);
56+ else if (strncmp (arm_selected_cpu->name, "generic", 7) == 0)
57+ asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_cpu->name + 8);
58 else
59 asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name);
60
61@@ -23717,6 +23719,7 @@
62 case cortexr4:
63 case cortexr4f:
64 case cortexr5:
65+ case genericv7a:
66 case cortexa5:
67 case cortexa8:
68 case cortexa9:
69
70=== modified file 'gcc/config/arm/arm.h'
71--- old/gcc/config/arm/arm.h 2011-09-05 14:32:11 +0000
72+++ new/gcc/config/arm/arm.h 2011-10-19 16:46:51 +0000
73@@ -198,6 +198,7 @@
74 Do not define this macro if it does not need to do anything. */
75 #define EXTRA_SPECS \
76 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
77+ { "asm_cpu_spec", ASM_CPU_SPEC }, \
78 SUBTARGET_EXTRA_SPECS
79
80 #ifndef SUBTARGET_EXTRA_SPECS
81@@ -2278,4 +2279,8 @@
82 instruction. */
83 #define MAX_LDM_STM_OPS 4
84
85+#define ASM_CPU_SPEC \
86+ " %{mcpu=generic-*:-march=%*;" \
87+ " :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}"
88+
89 #endif /* ! GCC_ARM_H */
90
91=== modified file 'gcc/config/arm/elf.h'
92--- old/gcc/config/arm/elf.h 2009-06-21 19:48:15 +0000
93+++ new/gcc/config/arm/elf.h 2011-10-19 16:46:51 +0000
94@@ -56,8 +56,7 @@
95 #define ASM_SPEC "\
96 %{mbig-endian:-EB} \
97 %{mlittle-endian:-EL} \
98-%{mcpu=*:-mcpu=%*} \
99-%{march=*:-march=%*} \
100+%(asm_cpu_spec) \
101 %{mapcs-*:-mapcs-%*} \
102 %(subtarget_asm_float_spec) \
103 %{mthumb-interwork:-mthumb-interwork} \
104
105=== modified file 'gcc/config/arm/semi.h'
106--- old/gcc/config/arm/semi.h 2007-08-02 09:49:31 +0000
107+++ new/gcc/config/arm/semi.h 2011-10-19 16:46:51 +0000
108@@ -65,8 +65,7 @@
109 #define ASM_SPEC "\
110 %{fpic|fpie: -k} %{fPIC|fPIE: -k} \
111 %{mbig-endian:-EB} \
112-%{mcpu=*:-mcpu=%*} \
113-%{march=*:-march=%*} \
114+%(arm_cpu_spec) \
115 %{mapcs-float:-mfloat} \
116 %{msoft-float:-mfloat-abi=soft} %{mhard-float:-mfloat-abi=hard} \
117 %{mfloat-abi=*} %{mfpu=*} \
118
119=== modified file 'gcc/doc/invoke.texi'
120--- old/gcc/doc/invoke.texi 2011-08-13 08:32:32 +0000
121+++ new/gcc/doc/invoke.texi 2011-10-19 16:46:51 +0000
122@@ -10215,6 +10215,10 @@
123 @samp{cortex-m0},
124 @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
125
126+@option{-mcpu=generic-@var{arch}} is also permissible, and is
127+equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}.
128+See @option{-mtune} for more information.
129+
130 @item -mtune=@var{name}
131 @opindex mtune
132 This option is very similar to the @option{-mcpu=} option, except that
133@@ -10226,6 +10230,13 @@
134 For some ARM implementations better performance can be obtained by using
135 this option.
136
137+@option{-mtune=generic-@var{arch}} specifies that GCC should tune the
138+performance for a blend of processors within architecture @var{arch}.
139+The aim is to generate code that run well on the current most popular
140+processors, balancing between optimizations that benefit some CPUs in the
141+range, and avoiding performance pitfalls of other CPUs. The effects of
142+this option may change in future GCC versions as CPU models come and go.
143+
144 @item -march=@var{name}
145 @opindex march
146 This specifies the name of the target ARM architecture. GCC uses this
147
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106830.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106830.patch
deleted file mode 100644
index 695aa8559..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106830.patch
+++ /dev/null
@@ -1,304 +0,0 @@
12011-10-19 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF:
4
5 2011-10-18 Andrew Stubbs <ams@codesourcery.com>
6
7 * config/arm/driver-arm.c (host_detect_local_cpu): Close the file
8 before exiting.
9
10 2011-10-18 Andrew Stubbs <ams@codesourcery.com>
11
12 gcc/
13 * config.host (arm*-*-linux*): Add driver-arm.o and x-arm.
14 * config/arm/arm.opt: Add 'native' processor_type and
15 arm_arch enum values.
16 * config/arm/arm.h (host_detect_local_cpu): New prototype.
17 (EXTRA_SPEC_FUNCTIONS): New define.
18 (MCPU_MTUNE_NATIVE_SPECS): New define.
19 (DRIVER_SELF_SPECS): New define.
20 * config/arm/driver-arm.c: New file.
21 * config/arm/x-arm: New file.
22 * doc/invoke.texi (ARM Options): Document -mcpu=native,
23 -mtune=native and -march=native.
24
25=== modified file 'gcc/config.host'
26--- old/gcc/config.host 2011-02-15 09:49:14 +0000
27+++ new/gcc/config.host 2011-10-19 17:01:50 +0000
28@@ -100,6 +100,14 @@
29 esac
30
31 case ${host} in
32+ arm*-*-linux*)
33+ case ${target} in
34+ arm*-*-*)
35+ host_extra_gcc_objs="driver-arm.o"
36+ host_xmake_file="${host_xmake_file} arm/x-arm"
37+ ;;
38+ esac
39+ ;;
40 alpha*-*-linux*)
41 case ${target} in
42 alpha*-*-linux*)
43
44=== modified file 'gcc/config/arm/arm.h'
45--- old/gcc/config/arm/arm.h 2011-10-19 16:46:51 +0000
46+++ new/gcc/config/arm/arm.h 2011-10-19 17:01:50 +0000
47@@ -2283,4 +2283,21 @@
48 " %{mcpu=generic-*:-march=%*;" \
49 " :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}"
50
51+/* -mcpu=native handling only makes sense with compiler running on
52+ an ARM chip. */
53+#if defined(__arm__)
54+extern const char *host_detect_local_cpu (int argc, const char **argv);
55+# define EXTRA_SPEC_FUNCTIONS \
56+ { "local_cpu_detect", host_detect_local_cpu },
57+
58+# define MCPU_MTUNE_NATIVE_SPECS \
59+ " %{march=native:%<march=native %:local_cpu_detect(arch)}" \
60+ " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \
61+ " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
62+#else
63+# define MCPU_MTUNE_NATIVE_SPECS ""
64+#endif
65+
66+#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS
67+
68 #endif /* ! GCC_ARM_H */
69
70=== modified file 'gcc/config/arm/arm.opt'
71--- old/gcc/config/arm/arm.opt 2011-10-11 02:31:01 +0000
72+++ new/gcc/config/arm/arm.opt 2011-10-19 17:01:50 +0000
73@@ -48,6 +48,11 @@
74 Target RejectNegative Joined
75 Specify the name of the target architecture
76
77+; Other arm_arch values are loaded from arm-tables.opt
78+; but that is a generated file and this is an odd-one-out.
79+EnumValue
80+Enum(arm_arch) String(native) Value(-1) DriverOnly
81+
82 marm
83 Target RejectNegative InverseMask(THUMB) Undocumented
84
85@@ -153,6 +158,11 @@
86 Target RejectNegative Joined
87 Tune code for the given processor
88
89+; Other processor_type values are loaded from arm-tables.opt
90+; but that is a generated file and this is an odd-one-out.
91+EnumValue
92+Enum(processor_type) String(native) Value(-1) DriverOnly
93+
94 mwords-little-endian
95 Target Report RejectNegative Mask(LITTLE_WORDS)
96 Assume big endian bytes, little endian words
97
98=== added file 'gcc/config/arm/driver-arm.c'
99--- old/gcc/config/arm/driver-arm.c 1970-01-01 00:00:00 +0000
100+++ new/gcc/config/arm/driver-arm.c 2011-10-19 17:07:55 +0000
101@@ -0,0 +1,149 @@
102+/* Subroutines for the gcc driver.
103+ Copyright (C) 2011 Free Software Foundation, Inc.
104+
105+This file is part of GCC.
106+
107+GCC is free software; you can redistribute it and/or modify
108+it under the terms of the GNU General Public License as published by
109+the Free Software Foundation; either version 3, or (at your option)
110+any later version.
111+
112+GCC is distributed in the hope that it will be useful,
113+but WITHOUT ANY WARRANTY; without even the implied warranty of
114+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
115+GNU General Public License for more details.
116+
117+You should have received a copy of the GNU General Public License
118+along with GCC; see the file COPYING3. If not see
119+<http://www.gnu.org/licenses/>. */
120+
121+#include "config.h"
122+#include "system.h"
123+#include "coretypes.h"
124+#include "tm.h"
125+#include "configargs.h"
126+
127+struct vendor_cpu {
128+ const char *part_no;
129+ const char *arch_name;
130+ const char *cpu_name;
131+};
132+
133+static struct vendor_cpu arm_cpu_table[] = {
134+ {"0x926", "armv5te", "arm926ej-s"},
135+ {"0xa26", "armv5te", "arm1026ej-s"},
136+ {"0xb02", "armv6k", "mpcore"},
137+ {"0xb36", "armv6j", "arm1136j-s"},
138+ {"0xb56", "armv6t2", "arm1156t2-s"},
139+ {"0xb76", "armv6zk", "arm1176jz-s"},
140+ {"0xc05", "armv7-a", "cortex-a5"},
141+ {"0xc08", "armv7-a", "cortex-a8"},
142+ {"0xc09", "armv7-a", "cortex-a9"},
143+ {"0xc0f", "armv7-a", "cortex-a15"},
144+ {"0xc14", "armv7-r", "cortex-r4"},
145+ {"0xc15", "armv7-r", "cortex-r5"},
146+ {"0xc20", "armv6-m", "cortex-m0"},
147+ {"0xc21", "armv6-m", "cortex-m1"},
148+ {"0xc23", "armv7-m", "cortex-m3"},
149+ {"0xc24", "armv7e-m", "cortex-m4"},
150+ {NULL, NULL, NULL}
151+};
152+
153+struct {
154+ const char *vendor_no;
155+ const struct vendor_cpu *vendor_parts;
156+} vendors[] = {
157+ {"0x41", arm_cpu_table},
158+ {NULL, NULL}
159+};
160+
161+/* This will be called by the spec parser in gcc.c when it sees
162+ a %:local_cpu_detect(args) construct. Currently it will be called
163+ with either "arch", "cpu" or "tune" as argument depending on if
164+ -march=native, -mcpu=native or -mtune=native is to be substituted.
165+
166+ It returns a string containing new command line parameters to be
167+ put at the place of the above two options, depending on what CPU
168+ this is executed. E.g. "-march=armv7-a" on a Cortex-A8 for
169+ -march=native. If the routine can't detect a known processor,
170+ the -march or -mtune option is discarded.
171+
172+ ARGC and ARGV are set depending on the actual arguments given
173+ in the spec. */
174+const char *
175+host_detect_local_cpu (int argc, const char **argv)
176+{
177+ const char *val = NULL;
178+ char buf[128];
179+ FILE *f = NULL;
180+ bool arch;
181+ const struct vendor_cpu *cpu_table = NULL;
182+
183+ if (argc < 1)
184+ goto not_found;
185+
186+ arch = strcmp (argv[0], "arch") == 0;
187+ if (!arch && strcmp (argv[0], "cpu") != 0 && strcmp (argv[0], "tune"))
188+ goto not_found;
189+
190+ f = fopen ("/proc/cpuinfo", "r");
191+ if (f == NULL)
192+ goto not_found;
193+
194+ while (fgets (buf, sizeof (buf), f) != NULL)
195+ {
196+ /* Ensure that CPU implementer is ARM (0x41). */
197+ if (strncmp (buf, "CPU implementer", sizeof ("CPU implementer") - 1) == 0)
198+ {
199+ int i;
200+ for (i = 0; vendors[i].vendor_no != NULL; i++)
201+ if (strstr (buf, vendors[i].vendor_no) != NULL)
202+ {
203+ cpu_table = vendors[i].vendor_parts;
204+ break;
205+ }
206+ }
207+
208+ /* Detect arch/cpu. */
209+ if (strncmp (buf, "CPU part", sizeof ("CPU part") - 1) == 0)
210+ {
211+ int i;
212+
213+ if (cpu_table == NULL)
214+ goto not_found;
215+
216+ for (i = 0; cpu_table[i].part_no != NULL; i++)
217+ if (strstr (buf, cpu_table[i].part_no) != NULL)
218+ {
219+ val = arch ? cpu_table[i].arch_name : cpu_table[i].cpu_name;
220+ break;
221+ }
222+ break;
223+ }
224+ }
225+
226+ fclose (f);
227+
228+ if (val == NULL)
229+ goto not_found;
230+
231+ return concat ("-m", argv[0], "=", val, NULL);
232+
233+not_found:
234+ {
235+ unsigned int i;
236+ unsigned int opt;
237+ const char *search[] = {NULL, "arch"};
238+
239+ if (f)
240+ fclose (f);
241+
242+ search[0] = argv[0];
243+ for (opt = 0; opt < ARRAY_SIZE (search); opt++)
244+ for (i = 0; i < ARRAY_SIZE (configure_default_options); i++)
245+ if (strcmp (configure_default_options[i].name, search[opt]) == 0)
246+ return concat ("-m", search[opt], "=",
247+ configure_default_options[i].value, NULL);
248+ return NULL;
249+ }
250+}
251
252=== added file 'gcc/config/arm/x-arm'
253--- old/gcc/config/arm/x-arm 1970-01-01 00:00:00 +0000
254+++ new/gcc/config/arm/x-arm 2011-10-19 17:01:50 +0000
255@@ -0,0 +1,3 @@
256+driver-arm.o: $(srcdir)/config/arm/driver-arm.c \
257+ $(CONFIG_H) $(SYSTEM_H)
258+ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
259
260=== modified file 'gcc/doc/invoke.texi'
261--- old/gcc/doc/invoke.texi 2011-10-19 16:46:51 +0000
262+++ new/gcc/doc/invoke.texi 2011-10-19 17:01:50 +0000
263@@ -10215,10 +10215,16 @@
264 @samp{cortex-m0},
265 @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
266
267+
268 @option{-mcpu=generic-@var{arch}} is also permissible, and is
269 equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}.
270 See @option{-mtune} for more information.
271
272+@option{-mcpu=native} causes the compiler to auto-detect the CPU
273+of the build computer. At present, this feature is only supported on
274+Linux, and not all architectures are recognised. If the auto-detect is
275+unsuccessful the option has no effect.
276+
277 @item -mtune=@var{name}
278 @opindex mtune
279 This option is very similar to the @option{-mcpu=} option, except that
280@@ -10237,6 +10243,11 @@
281 range, and avoiding performance pitfalls of other CPUs. The effects of
282 this option may change in future GCC versions as CPU models come and go.
283
284+@option{-mtune=native} causes the compiler to auto-detect the CPU
285+of the build computer. At present, this feature is only supported on
286+Linux, and not all architectures are recognised. If the auto-detect is
287+unsuccessful the option has no effect.
288+
289 @item -march=@var{name}
290 @opindex march
291 This specifies the name of the target ARM architecture. GCC uses this
292@@ -10250,6 +10261,11 @@
293 @samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m},
294 @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
295
296+@option{-march=native} causes the compiler to auto-detect the architecture
297+of the build computer. At present, this feature is only supported on
298+Linux, and not all architectures are recognised. If the auto-detect is
299+unsuccessful the option has no effect.
300+
301 @item -mfpu=@var{name}
302 @itemx -mfpe=@var{number}
303 @itemx -mfp=@var{number}
304
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106831.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106831.patch
deleted file mode 100644
index ad91d7736..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106831.patch
+++ /dev/null
@@ -1,123 +0,0 @@
12011-10-19 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF:
4
5 2011-10-18 Andrew Stubbs <ams@codesourcery.com>
6
7 PR tree-optimization/50717
8
9 gcc/
10 * tree-ssa-math-opts.c (is_widening_mult_p): Remove the 'type'
11 parameter. Calculate 'type' from stmt.
12 (convert_mult_to_widen): Update call the is_widening_mult_p.
13 (convert_plusminus_to_widen): Likewise.
14
15 gcc/testsuite/
16 * gcc.dg/pr50717-1.c: New file.
17 * gcc.target/arm/wmul-12.c: Correct types.
18 * gcc.target/arm/wmul-8.c: Correct types.
19
20=== added file 'gcc/testsuite/gcc.dg/pr50717-1.c'
21--- old/gcc/testsuite/gcc.dg/pr50717-1.c 1970-01-01 00:00:00 +0000
22+++ new/gcc/testsuite/gcc.dg/pr50717-1.c 2011-10-19 14:42:50 +0000
23@@ -0,0 +1,26 @@
24+/* PR tree-optimization/50717 */
25+/* Ensure that widening multiply-and-accumulate is not used where integer
26+ type promotion or users' casts should prevent it. */
27+
28+/* { dg-options "-O2 -fdump-tree-widening_mul" } */
29+
30+long long
31+f (unsigned int a, char b, long long c)
32+{
33+ return (a * b) + c;
34+}
35+
36+int
37+g (short a, short b, int c)
38+{
39+ return (short)(a * b) + c;
40+}
41+
42+int
43+h (char a, char b, int c)
44+{
45+ return (char)(a * b) + c;
46+}
47+
48+/* { dg-final { scan-tree-dump-times "WIDEN_MULT_PLUS_EXPR" 0 "widening_mul" } } */
49+/* { dg-final { cleanup-tree-dump "widening_mul" } } */
50
51=== modified file 'gcc/testsuite/gcc.target/arm/wmul-12.c'
52--- old/gcc/testsuite/gcc.target/arm/wmul-12.c 2011-07-22 15:46:42 +0000
53+++ new/gcc/testsuite/gcc.target/arm/wmul-12.c 2011-10-19 14:42:50 +0000
54@@ -4,8 +4,8 @@
55 long long
56 foo (int *b, int *c)
57 {
58- int tmp = *b * *c;
59- return 10 + (long long)tmp;
60+ long long tmp = (long long)*b * *c;
61+ return 10 + tmp;
62 }
63
64 /* { dg-final { scan-assembler "smlal" } } */
65
66=== modified file 'gcc/testsuite/gcc.target/arm/wmul-8.c'
67--- old/gcc/testsuite/gcc.target/arm/wmul-8.c 2011-07-15 14:16:54 +0000
68+++ new/gcc/testsuite/gcc.target/arm/wmul-8.c 2011-10-19 14:42:50 +0000
69@@ -4,7 +4,7 @@
70 long long
71 foo (long long a, int *b, int *c)
72 {
73- return a + *b * *c;
74+ return a + (long long)*b * *c;
75 }
76
77 /* { dg-final { scan-assembler "smlal" } } */
78
79=== modified file 'gcc/tree-ssa-math-opts.c'
80--- old/gcc/tree-ssa-math-opts.c 2011-09-08 20:11:43 +0000
81+++ new/gcc/tree-ssa-math-opts.c 2011-10-19 14:42:50 +0000
82@@ -1351,10 +1351,12 @@
83 and *TYPE2_OUT would give the operands of the multiplication. */
84
85 static bool
86-is_widening_mult_p (tree type, gimple stmt,
87+is_widening_mult_p (gimple stmt,
88 tree *type1_out, tree *rhs1_out,
89 tree *type2_out, tree *rhs2_out)
90 {
91+ tree type = TREE_TYPE (gimple_assign_lhs (stmt));
92+
93 if (TREE_CODE (type) != INTEGER_TYPE
94 && TREE_CODE (type) != FIXED_POINT_TYPE)
95 return false;
96@@ -1416,7 +1418,7 @@
97 if (TREE_CODE (type) != INTEGER_TYPE)
98 return false;
99
100- if (!is_widening_mult_p (type, stmt, &type1, &rhs1, &type2, &rhs2))
101+ if (!is_widening_mult_p (stmt, &type1, &rhs1, &type2, &rhs2))
102 return false;
103
104 to_mode = TYPE_MODE (type);
105@@ -1592,7 +1594,7 @@
106 if (code == PLUS_EXPR
107 && (rhs1_code == MULT_EXPR || rhs1_code == WIDEN_MULT_EXPR))
108 {
109- if (!is_widening_mult_p (type, rhs1_stmt, &type1, &mult_rhs1,
110+ if (!is_widening_mult_p (rhs1_stmt, &type1, &mult_rhs1,
111 &type2, &mult_rhs2))
112 return false;
113 add_rhs = rhs2;
114@@ -1600,7 +1602,7 @@
115 }
116 else if (rhs2_code == MULT_EXPR || rhs2_code == WIDEN_MULT_EXPR)
117 {
118- if (!is_widening_mult_p (type, rhs2_stmt, &type1, &mult_rhs1,
119+ if (!is_widening_mult_p (rhs2_stmt, &type1, &mult_rhs1,
120 &type2, &mult_rhs2))
121 return false;
122 add_rhs = rhs1;
123
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106832.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106832.patch
deleted file mode 100644
index 843f1cff2..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106832.patch
+++ /dev/null
@@ -1,24 +0,0 @@
12011-10-21 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF mainline:
4
5 2011-10-21 Andrew Stubbs <ams@codesourcery.com>
6
7 PR target/50809
8
9 gcc/
10 * config/arm/driver-arm.c (vendors): Make static.
11
12=== modified file 'gcc/config/arm/driver-arm.c'
13--- old/gcc/config/arm/driver-arm.c 2011-10-19 17:07:55 +0000
14+++ new/gcc/config/arm/driver-arm.c 2011-10-21 19:27:47 +0000
15@@ -49,7 +49,7 @@
16 {NULL, NULL, NULL}
17 };
18
19-struct {
20+static struct {
21 const char *vendor_no;
22 const struct vendor_cpu *vendor_parts;
23 } vendors[] = {
24
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106833.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106833.patch
deleted file mode 100644
index 1ad48e512..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106833.patch
+++ /dev/null
@@ -1,453 +0,0 @@
12011-10-27 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from mainline:
4
5 2011-10-16 Ira Rosen <ira.rosen@linaro.org>
6
7 gcc/
8 * tree-vect-stmts.c (vectorizable_load): For SLP without permutation
9 treat the first load of the node as the first element in its
10 interleaving chain.
11 * tree-vect-slp.c (vect_get_and_check_slp_defs): Swap the operands if
12 necessary and possible.
13 (vect_build_slp_tree): Add new argument. Allow load groups of any size
14 in basic blocks. Keep all the loads for further permutation check.
15 Use the new argument to determine if there is a permutation. Update
16 the recursive calls.
17 (vect_supported_load_permutation_p): Allow subchains of interleaving
18 chains in basic block vectorization.
19 (vect_analyze_slp_instance): Update the call to vect_build_slp_tree.
20 Check load permutation based on the new parameter.
21 (vect_schedule_slp_instance): Don't start from the first element in
22 interleaving chain unless the loads are permuted.
23
24 gcc/testsuite/
25 * gcc.dg/vect/bb-slp-29.c: New test.
26
27=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-29.c'
28--- old/gcc/testsuite/gcc.dg/vect/bb-slp-29.c 1970-01-01 00:00:00 +0000
29+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-29.c 2011-10-23 11:29:25 +0000
30@@ -0,0 +1,59 @@
31+/* { dg-require-effective-target vect_int } */
32+
33+#include <stdarg.h>
34+#include "tree-vect.h"
35+
36+#define A 3
37+#define B 4
38+#define N 256
39+
40+short src[N], dst[N];
41+
42+void foo (short * __restrict__ dst, short * __restrict__ src, int h, int stride, int dummy)
43+{
44+ int i;
45+ h /= 16;
46+ for (i = 0; i < h; i++)
47+ {
48+ dst[0] = A*src[0] + B*src[1];
49+ dst[1] = A*src[1] + B*src[2];
50+ dst[2] = A*src[2] + B*src[3];
51+ dst[3] = A*src[3] + B*src[4];
52+ dst[4] = A*src[4] + B*src[5];
53+ dst[5] = A*src[5] + B*src[6];
54+ dst[6] = A*src[6] + B*src[7];
55+ dst[7] = A*src[7] + B*src[8];
56+ dst += stride;
57+ src += stride;
58+ if (dummy == 32)
59+ abort ();
60+ }
61+}
62+
63+
64+int main (void)
65+{
66+ int i;
67+
68+ check_vect ();
69+
70+ for (i = 0; i < N; i++)
71+ {
72+ dst[i] = 0;
73+ src[i] = i;
74+ }
75+
76+ foo (dst, src, N, 8, 0);
77+
78+ for (i = 0; i < N/2; i++)
79+ {
80+ if (dst[i] != A * src[i] + B * src[i+1])
81+ abort ();
82+ }
83+
84+ return 0;
85+}
86+
87+/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target { vect_int_mult && vect_element_align } } } } */
88+/* { dg-final { cleanup-tree-dump "slp" } } */
89+
90
91=== modified file 'gcc/tree-vect-slp.c'
92--- old/gcc/tree-vect-slp.c 2011-10-06 11:08:08 +0000
93+++ new/gcc/tree-vect-slp.c 2011-10-23 11:29:25 +0000
94@@ -115,13 +115,15 @@
95 {
96 tree oprnd;
97 unsigned int i, number_of_oprnds;
98- tree def;
99+ tree def[2];
100 gimple def_stmt;
101 enum vect_def_type dt[2] = {vect_unknown_def_type, vect_unknown_def_type};
102 stmt_vec_info stmt_info =
103 vinfo_for_stmt (VEC_index (gimple, SLP_TREE_SCALAR_STMTS (slp_node), 0));
104 enum gimple_rhs_class rhs_class;
105 struct loop *loop = NULL;
106+ enum tree_code rhs_code;
107+ bool different_types = false;
108
109 if (loop_vinfo)
110 loop = LOOP_VINFO_LOOP (loop_vinfo);
111@@ -133,7 +135,7 @@
112 {
113 oprnd = gimple_op (stmt, i + 1);
114
115- if (!vect_is_simple_use (oprnd, loop_vinfo, bb_vinfo, &def_stmt, &def,
116+ if (!vect_is_simple_use (oprnd, loop_vinfo, bb_vinfo, &def_stmt, &def[i],
117 &dt[i])
118 || (!def_stmt && dt[i] != vect_constant_def))
119 {
120@@ -188,11 +190,11 @@
121 switch (gimple_code (def_stmt))
122 {
123 case GIMPLE_PHI:
124- def = gimple_phi_result (def_stmt);
125+ def[i] = gimple_phi_result (def_stmt);
126 break;
127
128 case GIMPLE_ASSIGN:
129- def = gimple_assign_lhs (def_stmt);
130+ def[i] = gimple_assign_lhs (def_stmt);
131 break;
132
133 default:
134@@ -206,8 +208,8 @@
135 {
136 /* op0 of the first stmt of the group - store its info. */
137 *first_stmt_dt0 = dt[i];
138- if (def)
139- *first_stmt_def0_type = TREE_TYPE (def);
140+ if (def[i])
141+ *first_stmt_def0_type = TREE_TYPE (def[i]);
142 else
143 *first_stmt_const_oprnd = oprnd;
144
145@@ -227,8 +229,8 @@
146 {
147 /* op1 of the first stmt of the group - store its info. */
148 *first_stmt_dt1 = dt[i];
149- if (def)
150- *first_stmt_def1_type = TREE_TYPE (def);
151+ if (def[i])
152+ *first_stmt_def1_type = TREE_TYPE (def[i]);
153 else
154 {
155 /* We assume that the stmt contains only one constant
156@@ -249,22 +251,53 @@
157 the def-stmt/s of the first stmt. */
158 if ((i == 0
159 && (*first_stmt_dt0 != dt[i]
160- || (*first_stmt_def0_type && def
161+ || (*first_stmt_def0_type && def[0]
162 && !types_compatible_p (*first_stmt_def0_type,
163- TREE_TYPE (def)))))
164+ TREE_TYPE (def[0])))))
165 || (i == 1
166 && (*first_stmt_dt1 != dt[i]
167- || (*first_stmt_def1_type && def
168+ || (*first_stmt_def1_type && def[1]
169 && !types_compatible_p (*first_stmt_def1_type,
170- TREE_TYPE (def)))))
171- || (!def
172+ TREE_TYPE (def[1])))))
173+ || (!def[i]
174 && !types_compatible_p (TREE_TYPE (*first_stmt_const_oprnd),
175- TREE_TYPE (oprnd))))
176+ TREE_TYPE (oprnd)))
177+ || different_types)
178 {
179- if (vect_print_dump_info (REPORT_SLP))
180- fprintf (vect_dump, "Build SLP failed: different types ");
181+ if (i != number_of_oprnds - 1)
182+ different_types = true;
183+ else
184+ {
185+ if (is_gimple_assign (stmt)
186+ && (rhs_code = gimple_assign_rhs_code (stmt))
187+ && TREE_CODE_CLASS (rhs_code) == tcc_binary
188+ && commutative_tree_code (rhs_code)
189+ && *first_stmt_dt0 == dt[1]
190+ && *first_stmt_dt1 == dt[0]
191+ && def[0] && def[1]
192+ && !(*first_stmt_def0_type
193+ && !types_compatible_p (*first_stmt_def0_type,
194+ TREE_TYPE (def[1])))
195+ && !(*first_stmt_def1_type
196+ && !types_compatible_p (*first_stmt_def1_type,
197+ TREE_TYPE (def[0]))))
198+ {
199+ if (vect_print_dump_info (REPORT_SLP))
200+ {
201+ fprintf (vect_dump, "Swapping operands of ");
202+ print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
203+ }
204+ swap_tree_operands (stmt, gimple_assign_rhs1_ptr (stmt),
205+ gimple_assign_rhs2_ptr (stmt));
206+ }
207+ else
208+ {
209+ if (vect_print_dump_info (REPORT_SLP))
210+ fprintf (vect_dump, "Build SLP failed: different types ");
211
212- return false;
213+ return false;
214+ }
215+ }
216 }
217 }
218 }
219@@ -278,10 +311,10 @@
220
221 case vect_internal_def:
222 case vect_reduction_def:
223- if (i == 0)
224+ if ((i == 0 && !different_types) || (i == 1 && different_types))
225 VEC_safe_push (gimple, heap, *def_stmts0, def_stmt);
226 else
227- VEC_safe_push (gimple, heap, *def_stmts1, def_stmt);
228+ VEC_safe_push (gimple, heap, *def_stmts1, def_stmt);
229 break;
230
231 default:
232@@ -289,7 +322,7 @@
233 if (vect_print_dump_info (REPORT_SLP))
234 {
235 fprintf (vect_dump, "Build SLP failed: illegal type of def ");
236- print_generic_expr (vect_dump, def, TDF_SLIM);
237+ print_generic_expr (vect_dump, def[i], TDF_SLIM);
238 }
239
240 return false;
241@@ -312,7 +345,7 @@
242 int ncopies_for_cost, unsigned int *max_nunits,
243 VEC (int, heap) **load_permutation,
244 VEC (slp_tree, heap) **loads,
245- unsigned int vectorization_factor)
246+ unsigned int vectorization_factor, bool *loads_permuted)
247 {
248 VEC (gimple, heap) *def_stmts0 = VEC_alloc (gimple, heap, group_size);
249 VEC (gimple, heap) *def_stmts1 = VEC_alloc (gimple, heap, group_size);
250@@ -523,7 +556,9 @@
251
252 /* Check that the size of interleaved loads group is not
253 greater than the SLP group size. */
254- if (DR_GROUP_SIZE (vinfo_for_stmt (stmt)) > ncopies * group_size)
255+ if (loop_vinfo
256+ && DR_GROUP_SIZE (vinfo_for_stmt (stmt))
257+ > ncopies * group_size)
258 {
259 if (vect_print_dump_info (REPORT_SLP))
260 {
261@@ -644,19 +679,22 @@
262 /* Strided loads were reached - stop the recursion. */
263 if (stop_recursion)
264 {
265+ VEC_safe_push (slp_tree, heap, *loads, *node);
266 if (permutation)
267 {
268- VEC_safe_push (slp_tree, heap, *loads, *node);
269+
270+ *loads_permuted = true;
271 *inside_cost
272 += targetm.vectorize.builtin_vectorization_cost (vec_perm, NULL, 0)
273 * group_size;
274 }
275 else
276- {
277- /* We don't check here complex numbers chains, so we keep them in
278- LOADS for further check in vect_supported_load_permutation_p. */
279+ {
280+ /* We don't check here complex numbers chains, so we set
281+ LOADS_PERMUTED for further check in
282+ vect_supported_load_permutation_p. */
283 if (rhs_code == REALPART_EXPR || rhs_code == IMAGPART_EXPR)
284- VEC_safe_push (slp_tree, heap, *loads, *node);
285+ *loads_permuted = true;
286 }
287
288 return true;
289@@ -675,7 +713,7 @@
290 if (!vect_build_slp_tree (loop_vinfo, bb_vinfo, &left_node, group_size,
291 inside_cost, outside_cost, ncopies_for_cost,
292 max_nunits, load_permutation, loads,
293- vectorization_factor))
294+ vectorization_factor, loads_permuted))
295 return false;
296
297 SLP_TREE_LEFT (*node) = left_node;
298@@ -693,7 +731,7 @@
299 if (!vect_build_slp_tree (loop_vinfo, bb_vinfo, &right_node, group_size,
300 inside_cost, outside_cost, ncopies_for_cost,
301 max_nunits, load_permutation, loads,
302- vectorization_factor))
303+ vectorization_factor, loads_permuted))
304 return false;
305
306 SLP_TREE_RIGHT (*node) = right_node;
307@@ -879,8 +917,10 @@
308 bool supported, bad_permutation = false;
309 sbitmap load_index;
310 slp_tree node, other_complex_node;
311- gimple stmt, first = NULL, other_node_first;
312+ gimple stmt, first = NULL, other_node_first, load, next_load, first_load;
313 unsigned complex_numbers = 0;
314+ struct data_reference *dr;
315+ bb_vec_info bb_vinfo;
316
317 /* FORNOW: permutations are only supported in SLP. */
318 if (!slp_instn)
319@@ -1040,6 +1080,76 @@
320 }
321 }
322
323+ /* In basic block vectorization we allow any subchain of an interleaving
324+ chain.
325+ FORNOW: not supported in loop SLP because of realignment compications. */
326+ bb_vinfo = STMT_VINFO_BB_VINFO (vinfo_for_stmt (stmt));
327+ bad_permutation = false;
328+ /* Check that for every node in the instance teh loads form a subchain. */
329+ if (bb_vinfo)
330+ {
331+ FOR_EACH_VEC_ELT (slp_tree, SLP_INSTANCE_LOADS (slp_instn), i, node)
332+ {
333+ next_load = NULL;
334+ first_load = NULL;
335+ FOR_EACH_VEC_ELT (gimple, SLP_TREE_SCALAR_STMTS (node), j, load)
336+ {
337+ if (!first_load)
338+ first_load = DR_GROUP_FIRST_DR (vinfo_for_stmt (load));
339+ else if (first_load
340+ != DR_GROUP_FIRST_DR (vinfo_for_stmt (load)))
341+ {
342+ bad_permutation = true;
343+ break;
344+ }
345+
346+ if (j != 0 && next_load != load)
347+ {
348+ bad_permutation = true;
349+ break;
350+ }
351+
352+ next_load = DR_GROUP_NEXT_DR (vinfo_for_stmt (load));
353+ }
354+
355+ if (bad_permutation)
356+ break;
357+ }
358+
359+ /* Check that the alignment of the first load in every subchain, i.e.,
360+ the first statement in every load node, is supported. */
361+ if (!bad_permutation)
362+ {
363+ FOR_EACH_VEC_ELT (slp_tree, SLP_INSTANCE_LOADS (slp_instn), i, node)
364+ {
365+ first_load = VEC_index (gimple, SLP_TREE_SCALAR_STMTS (node), 0);
366+ if (first_load
367+ != DR_GROUP_FIRST_DR (vinfo_for_stmt (first_load)))
368+ {
369+ dr = STMT_VINFO_DATA_REF (vinfo_for_stmt (first_load));
370+ if (vect_supportable_dr_alignment (dr, false)
371+ == dr_unaligned_unsupported)
372+ {
373+ if (vect_print_dump_info (REPORT_SLP))
374+ {
375+ fprintf (vect_dump, "unsupported unaligned load ");
376+ print_gimple_stmt (vect_dump, first_load, 0,
377+ TDF_SLIM);
378+ }
379+ bad_permutation = true;
380+ break;
381+ }
382+ }
383+ }
384+
385+ if (!bad_permutation)
386+ {
387+ VEC_free (int, heap, SLP_INSTANCE_LOAD_PERMUTATION (slp_instn));
388+ return true;
389+ }
390+ }
391+ }
392+
393 /* FORNOW: the only supported permutation is 0..01..1.. of length equal to
394 GROUP_SIZE and where each sequence of same drs is of GROUP_SIZE length as
395 well (unless it's reduction). */
396@@ -1149,6 +1259,7 @@
397 VEC (int, heap) *load_permutation;
398 VEC (slp_tree, heap) *loads;
399 struct data_reference *dr = STMT_VINFO_DATA_REF (vinfo_for_stmt (stmt));
400+ bool loads_permuted = false;
401
402 if (dr)
403 {
404@@ -1238,7 +1349,7 @@
405 if (vect_build_slp_tree (loop_vinfo, bb_vinfo, &node, group_size,
406 &inside_cost, &outside_cost, ncopies_for_cost,
407 &max_nunits, &load_permutation, &loads,
408- vectorization_factor))
409+ vectorization_factor, &loads_permuted))
410 {
411 /* Calculate the unrolling factor based on the smallest type. */
412 if (max_nunits > nunits)
413@@ -1263,7 +1374,8 @@
414 SLP_INSTANCE_LOADS (new_instance) = loads;
415 SLP_INSTANCE_FIRST_LOAD_STMT (new_instance) = NULL;
416 SLP_INSTANCE_LOAD_PERMUTATION (new_instance) = load_permutation;
417- if (VEC_length (slp_tree, loads))
418+
419+ if (loads_permuted)
420 {
421 if (!vect_supported_load_permutation_p (new_instance, group_size,
422 load_permutation))
423@@ -2542,10 +2654,11 @@
424 /* Loads should be inserted before the first load. */
425 if (SLP_INSTANCE_FIRST_LOAD_STMT (instance)
426 && STMT_VINFO_STRIDED_ACCESS (stmt_info)
427- && !REFERENCE_CLASS_P (gimple_get_lhs (stmt)))
428+ && !REFERENCE_CLASS_P (gimple_get_lhs (stmt))
429+ && SLP_INSTANCE_LOAD_PERMUTATION (instance))
430 si = gsi_for_stmt (SLP_INSTANCE_FIRST_LOAD_STMT (instance));
431 else if (is_pattern_stmt_p (stmt_info))
432- si = gsi_for_stmt (STMT_VINFO_RELATED_STMT (stmt_info));
433+ si = gsi_for_stmt (STMT_VINFO_RELATED_STMT (stmt_info));
434 else
435 si = gsi_for_stmt (stmt);
436
437
438=== modified file 'gcc/tree-vect-stmts.c'
439--- old/gcc/tree-vect-stmts.c 2011-10-16 12:16:07 +0000
440+++ new/gcc/tree-vect-stmts.c 2011-10-23 11:29:25 +0000
441@@ -4285,6 +4285,11 @@
442 if (strided_load)
443 {
444 first_stmt = DR_GROUP_FIRST_DR (stmt_info);
445+ if (slp
446+ && !SLP_INSTANCE_LOAD_PERMUTATION (slp_node_instance)
447+ && first_stmt != VEC_index (gimple, SLP_TREE_SCALAR_STMTS (slp_node), 0))
448+ first_stmt = VEC_index (gimple, SLP_TREE_SCALAR_STMTS (slp_node), 0);
449+
450 /* Check if the chain of loads is already vectorized. */
451 if (STMT_VINFO_VEC_STMT (vinfo_for_stmt (first_stmt)))
452 {
453
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106834.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106834.patch
deleted file mode 100644
index 421a8fe3a..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106834.patch
+++ /dev/null
@@ -1,1505 +0,0 @@
1 2011-10-18 Ira Rosen <ira.rosen@linaro.org>
2
3 gcc/
4 * doc/md.texi (vec_widen_ushiftl_hi, vec_widen_ushiftl_lo,
5 vec_widen_sshiftl_hi, vec_widen_sshiftl_lo): Document.
6 * tree-pretty-print.c (dump_generic_node): Handle WIDEN_LSHIFT_EXPR,
7 VEC_WIDEN_LSHIFT_HI_EXPR and VEC_WIDEN_LSHIFT_LO_EXPR.
8 (op_code_prio): Likewise.
9 (op_symbol_code): Handle WIDEN_LSHIFT_EXPR.
10 * optabs.c (optab_for_tree_code): Handle
11 VEC_WIDEN_LSHIFT_HI_EXPR and VEC_WIDEN_LSHIFT_LO_EXPR.
12 (init-optabs): Initialize optab codes for vec_widen_u/sshiftl_hi/lo.
13 * optabs.h (enum optab_index): Add OTI_vec_widen_u/sshiftl_hi/lo.
14 * genopinit.c (optabs): Initialize the new optabs.
15 * expr.c (expand_expr_real_2): Handle
16 VEC_WIDEN_LSHIFT_HI_EXPR and VEC_WIDEN_LSHIFT_LO_EXPR.
17 * gimple-pretty-print.c (dump_binary_rhs): Likewise.
18 * tree-vectorizer.h (NUM_PATTERNS): Increase to 8.
19 * tree.def (WIDEN_LSHIFT_EXPR, VEC_WIDEN_LSHIFT_HI_EXPR,
20 VEC_WIDEN_LSHIFT_LO_EXPR): New.
21 * cfgexpand.c (expand_debug_expr): Handle new tree codes.
22 * tree-vect-patterns.c (vect_vect_recog_func_ptrs): Add
23 vect_recog_widen_shift_pattern.
24 (vect_handle_widen_mult_by_const): Rename...
25 (vect_handle_widen_op_by_const): ...to this. Handle shifts.
26 Add a new argument, update documentation.
27 (vect_recog_widen_mult_pattern): Assume that only second
28 operand can be constant. Update call to
29 vect_handle_widen_op_by_const.
30 (vect_recog_over_widening_pattern): Fix typo.
31 (vect_recog_widen_shift_pattern): New.
32 * tree-vect-stmts.c (vectorizable_type_promotion): Handle
33 widening shifts.
34 (supportable_widening_operation): Likewise.
35 * tree-inline.c (estimate_operator_cost): Handle new tree codes.
36 * tree-vect-generic.c (expand_vector_operations_1): Likewise.
37 * tree-cfg.c (verify_gimple_assign_binary): Likewise.
38 * config/arm/neon.md (neon_vec_<US>shiftl_<mode>): New.
39 (vec_widen_<US>shiftl_lo_<mode>, neon_vec_<US>shiftl_hi_<mode>,
40 vec_widen_<US>shiftl_hi_<mode>, neon_vec_<US>shift_left_<mode>):
41 Likewise.
42 * config/arm/predicates.md (const_neon_scalar_shift_amount_operand):
43 New.
44 * config/arm/iterators.md (V_innermode): New.
45 * tree-vect-slp.c (vect_build_slp_tree): Require same shift operand
46 for widening shift.
47
48 gcc/testsuite
49 * testsuite/lib/target-supports.exp
50 (check_effective_target_vect_widen_shift): New.
51 * gcc.dg/vect/vect-widen-shift-s16.c: New.
52 * gcc.dg/vect/vect-widen-shift-s8.c: New.
53 * gcc.dg/vect/vect-widen-shift-u16.c: New.
54 * gcc.dg/vect/vect-widen-shift-u8.c: New.
55
56 2011-10-06 Jakub Jelinek <jakub@redhat.com>
57
58 gcc/
59 * tree-vect-patterns.c (vect_pattern_recog_1): Use
60 vect_recog_func_ptr typedef for the first argument.
61 (vect_pattern_recog): Rename vect_recog_func_ptr variable
62 to vect_recog_func, use vect_recog_func_ptr typedef for it.
63
64 2011-10-16 Ira Rosen <ira.rosen@linaro.org>
65
66 gcc/
67 PR tree-optimization/50727
68 * tree-vect-patterns.c (vect_operation_fits_smaller_type): Add
69 DEF_STMT to the list of statements to be replaced by the
70 pattern statements.
71
72 2011-10-09 Ira Rosen <ira.rosen@linaro.org>
73
74 gcc/
75 PR tree-optimization/50635
76 * tree-vect-patterns.c (vect_handle_widen_mult_by_const): Add
77 DEF_STMT to the list of statements to be replaced by the
78 pattern statements.
79 (vect_handle_widen_mult_by_const): Don't check TYPE_OUT.
80
81=== modified file 'gcc/cfgexpand.c'
82--- old/gcc/cfgexpand.c 2011-07-01 09:19:21 +0000
83+++ new/gcc/cfgexpand.c 2011-10-23 13:33:07 +0000
84@@ -3215,6 +3215,8 @@
85 case VEC_UNPACK_LO_EXPR:
86 case VEC_WIDEN_MULT_HI_EXPR:
87 case VEC_WIDEN_MULT_LO_EXPR:
88+ case VEC_WIDEN_LSHIFT_HI_EXPR:
89+ case VEC_WIDEN_LSHIFT_LO_EXPR:
90 return NULL;
91
92 /* Misc codes. */
93
94=== modified file 'gcc/config/arm/iterators.md'
95--- old/gcc/config/arm/iterators.md 2011-09-06 14:29:24 +0000
96+++ new/gcc/config/arm/iterators.md 2011-10-23 13:33:07 +0000
97@@ -388,6 +388,9 @@
98 (define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rUq")])
99 (define_mode_attr qhs_zextenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
100
101+;; Mode attribute for vshll.
102+(define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")])
103+
104 ;;----------------------------------------------------------------------------
105 ;; Code attributes
106 ;;----------------------------------------------------------------------------
107
108=== modified file 'gcc/config/arm/neon.md'
109--- old/gcc/config/arm/neon.md 2011-10-03 01:32:17 +0000
110+++ new/gcc/config/arm/neon.md 2011-10-23 13:33:07 +0000
111@@ -5316,6 +5316,44 @@
112 }
113 )
114
115+(define_insn "neon_vec_<US>shiftl_<mode>"
116+ [(set (match_operand:<V_widen> 0 "register_operand" "=w")
117+ (SE:<V_widen> (ashift:VW (match_operand:VW 1 "register_operand" "w")
118+ (match_operand:<V_innermode> 2 "const_neon_scalar_shift_amount_operand" ""))))]
119+ "TARGET_NEON"
120+{
121+ return "vshll.<US><V_sz_elem> %q0, %P1, %2";
122+}
123+ [(set_attr "neon_type" "neon_shift_1")]
124+)
125+
126+(define_expand "vec_widen_<US>shiftl_lo_<mode>"
127+ [(match_operand:<V_unpack> 0 "register_operand" "")
128+ (SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))
129+ (match_operand:SI 2 "immediate_operand" "i")]
130+ "TARGET_NEON && !BYTES_BIG_ENDIAN"
131+ {
132+ emit_insn (gen_neon_vec_<US>shiftl_<V_half> (operands[0],
133+ simplify_gen_subreg (<V_HALF>mode, operands[1], <MODE>mode, 0),
134+ operands[2]));
135+ DONE;
136+ }
137+)
138+
139+(define_expand "vec_widen_<US>shiftl_hi_<mode>"
140+ [(match_operand:<V_unpack> 0 "register_operand" "")
141+ (SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))
142+ (match_operand:SI 2 "immediate_operand" "i")]
143+ "TARGET_NEON && !BYTES_BIG_ENDIAN"
144+ {
145+ emit_insn (gen_neon_vec_<US>shiftl_<V_half> (operands[0],
146+ simplify_gen_subreg (<V_HALF>mode, operands[1], <MODE>mode,
147+ GET_MODE_SIZE (<V_HALF>mode)),
148+ operands[2]));
149+ DONE;
150+ }
151+)
152+
153 ;; Vectorize for non-neon-quad case
154 (define_insn "neon_unpack<US>_<mode>"
155 [(set (match_operand:<V_widen> 0 "register_operand" "=w")
156@@ -5392,6 +5430,34 @@
157 }
158 )
159
160+(define_expand "vec_widen_<US>shiftl_hi_<mode>"
161+ [(match_operand:<V_double_width> 0 "register_operand" "")
162+ (SE:<V_double_width> (match_operand:VDI 1 "register_operand" ""))
163+ (match_operand:SI 2 "immediate_operand" "i")]
164+ "TARGET_NEON"
165+ {
166+ rtx tmpreg = gen_reg_rtx (<V_widen>mode);
167+ emit_insn (gen_neon_vec_<US>shiftl_<mode> (tmpreg, operands[1], operands[2]));
168+ emit_insn (gen_neon_vget_high<V_widen_l> (operands[0], tmpreg));
169+
170+ DONE;
171+ }
172+)
173+
174+(define_expand "vec_widen_<US>shiftl_lo_<mode>"
175+ [(match_operand:<V_double_width> 0 "register_operand" "")
176+ (SE:<V_double_width> (match_operand:VDI 1 "register_operand" ""))
177+ (match_operand:SI 2 "immediate_operand" "i")]
178+ "TARGET_NEON"
179+ {
180+ rtx tmpreg = gen_reg_rtx (<V_widen>mode);
181+ emit_insn (gen_neon_vec_<US>shiftl_<mode> (tmpreg, operands[1], operands[2]));
182+ emit_insn (gen_neon_vget_low<V_widen_l> (operands[0], tmpreg));
183+
184+ DONE;
185+ }
186+)
187+
188 ;; The case when using all quad registers.
189 (define_insn "vec_pack_trunc_<mode>"
190 [(set (match_operand:<V_narrow_pack> 0 "register_operand" "=&w")
191
192=== modified file 'gcc/config/arm/predicates.md'
193--- old/gcc/config/arm/predicates.md 2011-10-10 11:43:28 +0000
194+++ new/gcc/config/arm/predicates.md 2011-10-23 13:33:07 +0000
195@@ -136,6 +136,11 @@
196 (match_operand 0 "s_register_operand"))
197 (match_operand 0 "const_int_operand")))
198
199+(define_predicate "const_neon_scalar_shift_amount_operand"
200+ (and (match_code "const_int")
201+ (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode)
202+ && ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0")))
203+
204 (define_predicate "arm_add_operand"
205 (ior (match_operand 0 "arm_rhs_operand")
206 (match_operand 0 "arm_neg_immediate_operand")))
207
208=== modified file 'gcc/doc/md.texi'
209--- old/gcc/doc/md.texi 2011-08-13 08:32:32 +0000
210+++ new/gcc/doc/md.texi 2011-10-23 13:33:07 +0000
211@@ -4230,6 +4230,17 @@
212 elements of the two vectors, and put the N/2 products of size 2*S in the
213 output vector (operand 0).
214
215+@cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
216+@cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
217+@cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
218+@cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
219+@item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
220+@itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
221+Signed/Unsigned widening shift left. The first input (operand 1) is a vector
222+with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
223+the high/low elements of operand 1, and put the N/2 results of size 2*S in the
224+output vector (operand 0).
225+
226 @cindex @code{mulhisi3} instruction pattern
227 @item @samp{mulhisi3}
228 Multiply operands 1 and 2, which have mode @code{HImode}, and store
229
230=== modified file 'gcc/expr.c'
231--- old/gcc/expr.c 2011-08-25 11:42:09 +0000
232+++ new/gcc/expr.c 2011-10-23 13:33:07 +0000
233@@ -8290,6 +8290,19 @@
234 return target;
235 }
236
237+ case VEC_WIDEN_LSHIFT_HI_EXPR:
238+ case VEC_WIDEN_LSHIFT_LO_EXPR:
239+ {
240+ tree oprnd0 = treeop0;
241+ tree oprnd1 = treeop1;
242+
243+ expand_operands (oprnd0, oprnd1, NULL_RTX, &op0, &op1, EXPAND_NORMAL);
244+ target = expand_widen_pattern_expr (ops, op0, op1, NULL_RTX,
245+ target, unsignedp);
246+ gcc_assert (target);
247+ return target;
248+ }
249+
250 case VEC_PACK_TRUNC_EXPR:
251 case VEC_PACK_SAT_EXPR:
252 case VEC_PACK_FIX_TRUNC_EXPR:
253
254=== modified file 'gcc/genopinit.c'
255--- old/gcc/genopinit.c 2011-07-15 13:06:31 +0000
256+++ new/gcc/genopinit.c 2011-10-23 13:33:07 +0000
257@@ -268,6 +268,10 @@
258 "set_optab_handler (vec_widen_umult_lo_optab, $A, CODE_FOR_$(vec_widen_umult_lo_$a$))",
259 "set_optab_handler (vec_widen_smult_hi_optab, $A, CODE_FOR_$(vec_widen_smult_hi_$a$))",
260 "set_optab_handler (vec_widen_smult_lo_optab, $A, CODE_FOR_$(vec_widen_smult_lo_$a$))",
261+ "set_optab_handler (vec_widen_ushiftl_hi_optab, $A, CODE_FOR_$(vec_widen_ushiftl_hi_$a$))",
262+ "set_optab_handler (vec_widen_ushiftl_lo_optab, $A, CODE_FOR_$(vec_widen_ushiftl_lo_$a$))",
263+ "set_optab_handler (vec_widen_sshiftl_hi_optab, $A, CODE_FOR_$(vec_widen_sshiftl_hi_$a$))",
264+ "set_optab_handler (vec_widen_sshiftl_lo_optab, $A, CODE_FOR_$(vec_widen_sshiftl_lo_$a$))",
265 "set_optab_handler (vec_unpacks_hi_optab, $A, CODE_FOR_$(vec_unpacks_hi_$a$))",
266 "set_optab_handler (vec_unpacks_lo_optab, $A, CODE_FOR_$(vec_unpacks_lo_$a$))",
267 "set_optab_handler (vec_unpacku_hi_optab, $A, CODE_FOR_$(vec_unpacku_hi_$a$))",
268
269=== modified file 'gcc/gimple-pretty-print.c'
270--- old/gcc/gimple-pretty-print.c 2011-05-05 15:42:22 +0000
271+++ new/gcc/gimple-pretty-print.c 2011-10-23 13:33:07 +0000
272@@ -343,6 +343,8 @@
273 case VEC_EXTRACT_ODD_EXPR:
274 case VEC_INTERLEAVE_HIGH_EXPR:
275 case VEC_INTERLEAVE_LOW_EXPR:
276+ case VEC_WIDEN_LSHIFT_HI_EXPR:
277+ case VEC_WIDEN_LSHIFT_LO_EXPR:
278 for (p = tree_code_name [(int) code]; *p; p++)
279 pp_character (buffer, TOUPPER (*p));
280 pp_string (buffer, " <");
281
282=== modified file 'gcc/optabs.c'
283--- old/gcc/optabs.c 2011-08-11 15:46:01 +0000
284+++ new/gcc/optabs.c 2011-10-23 13:33:07 +0000
285@@ -454,6 +454,14 @@
286 return TYPE_UNSIGNED (type) ?
287 vec_widen_umult_lo_optab : vec_widen_smult_lo_optab;
288
289+ case VEC_WIDEN_LSHIFT_HI_EXPR:
290+ return TYPE_UNSIGNED (type) ?
291+ vec_widen_ushiftl_hi_optab : vec_widen_sshiftl_hi_optab;
292+
293+ case VEC_WIDEN_LSHIFT_LO_EXPR:
294+ return TYPE_UNSIGNED (type) ?
295+ vec_widen_ushiftl_lo_optab : vec_widen_sshiftl_lo_optab;
296+
297 case VEC_UNPACK_HI_EXPR:
298 return TYPE_UNSIGNED (type) ?
299 vec_unpacku_hi_optab : vec_unpacks_hi_optab;
300@@ -6351,6 +6359,10 @@
301 init_optab (vec_widen_umult_lo_optab, UNKNOWN);
302 init_optab (vec_widen_smult_hi_optab, UNKNOWN);
303 init_optab (vec_widen_smult_lo_optab, UNKNOWN);
304+ init_optab (vec_widen_ushiftl_hi_optab, UNKNOWN);
305+ init_optab (vec_widen_ushiftl_lo_optab, UNKNOWN);
306+ init_optab (vec_widen_sshiftl_hi_optab, UNKNOWN);
307+ init_optab (vec_widen_sshiftl_lo_optab, UNKNOWN);
308 init_optab (vec_unpacks_hi_optab, UNKNOWN);
309 init_optab (vec_unpacks_lo_optab, UNKNOWN);
310 init_optab (vec_unpacku_hi_optab, UNKNOWN);
311
312=== modified file 'gcc/optabs.h'
313--- old/gcc/optabs.h 2011-07-27 14:12:45 +0000
314+++ new/gcc/optabs.h 2011-10-23 13:33:07 +0000
315@@ -350,6 +350,12 @@
316 OTI_vec_widen_umult_lo,
317 OTI_vec_widen_smult_hi,
318 OTI_vec_widen_smult_lo,
319+ /* Widening shift left.
320+ The high/low part of the resulting vector is returned. */
321+ OTI_vec_widen_ushiftl_hi,
322+ OTI_vec_widen_ushiftl_lo,
323+ OTI_vec_widen_sshiftl_hi,
324+ OTI_vec_widen_sshiftl_lo,
325 /* Extract and widen the high/low part of a vector of signed or
326 floating point elements. */
327 OTI_vec_unpacks_hi,
328@@ -542,6 +548,10 @@
329 #define vec_widen_umult_lo_optab (&optab_table[OTI_vec_widen_umult_lo])
330 #define vec_widen_smult_hi_optab (&optab_table[OTI_vec_widen_smult_hi])
331 #define vec_widen_smult_lo_optab (&optab_table[OTI_vec_widen_smult_lo])
332+#define vec_widen_ushiftl_hi_optab (&optab_table[OTI_vec_widen_ushiftl_hi])
333+#define vec_widen_ushiftl_lo_optab (&optab_table[OTI_vec_widen_ushiftl_lo])
334+#define vec_widen_sshiftl_hi_optab (&optab_table[OTI_vec_widen_sshiftl_hi])
335+#define vec_widen_sshiftl_lo_optab (&optab_table[OTI_vec_widen_sshiftl_lo])
336 #define vec_unpacks_hi_optab (&optab_table[OTI_vec_unpacks_hi])
337 #define vec_unpacks_lo_optab (&optab_table[OTI_vec_unpacks_lo])
338 #define vec_unpacku_hi_optab (&optab_table[OTI_vec_unpacku_hi])
339
340=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-shift-s16.c'
341--- old/gcc/testsuite/gcc.dg/vect/vect-widen-shift-s16.c 1970-01-01 00:00:00 +0000
342+++ new/gcc/testsuite/gcc.dg/vect/vect-widen-shift-s16.c 2011-10-23 13:33:07 +0000
343@@ -0,0 +1,107 @@
344+/* { dg-require-effective-target vect_int } */
345+/* { dg-require-effective-target vect_shift } */
346+
347+#include <stdarg.h>
348+#include "tree-vect.h"
349+
350+#define N 64
351+#define C 16
352+
353+__attribute__ ((noinline)) void
354+foo (short *src, int *dst)
355+{
356+ int i;
357+ short b, b0, b1, b2, b3, *s = src;
358+ int *d = dst;
359+
360+ for (i = 0; i < N/4; i++)
361+ {
362+ b0 = *s++;
363+ b1 = *s++;
364+ b2 = *s++;
365+ b3 = *s++;
366+ *d = b0 << C;
367+ d++;
368+ *d = b1 << C;
369+ d++;
370+ *d = b2 << C;
371+ d++;
372+ *d = b3 << C;
373+ d++;
374+ }
375+
376+ s = src;
377+ d = dst;
378+ for (i = 0; i < N; i++)
379+ {
380+ b = *s++;
381+ if (*d != b << C)
382+ abort ();
383+ d++;
384+ }
385+
386+ s = src;
387+ d = dst;
388+ for (i = 0; i < N/4; i++)
389+ {
390+ b0 = *s++;
391+ b1 = *s++;
392+ b2 = *s++;
393+ b3 = *s++;
394+ *d = b0 << C;
395+ d++;
396+ *d = b1 << C;
397+ d++;
398+ *d = b2 << C;
399+ d++;
400+ *d = b3 << 6;
401+ d++;
402+ }
403+
404+ s = src;
405+ d = dst;
406+ for (i = 0; i < N/4; i++)
407+ {
408+ b = *s++;
409+ if (*d != b << C)
410+ abort ();
411+ d++;
412+ b = *s++;
413+ if (*d != b << C)
414+ abort ();
415+ d++;
416+ b = *s++;
417+ if (*d != b << C)
418+ abort ();
419+ d++;
420+ b = *s++;
421+ if (*d != b << 6)
422+ abort ();
423+ d++;
424+ }
425+}
426+
427+int main (void)
428+{
429+ int i;
430+ short in[N];
431+ int out[N];
432+
433+ check_vect ();
434+
435+ for (i = 0; i < N; i++)
436+ {
437+ in[i] = i;
438+ out[i] = 255;
439+ __asm__ volatile ("");
440+ }
441+
442+ foo (in, out);
443+
444+ return 0;
445+}
446+
447+/* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 8 "vect" { target vect_widen_shift } } } */
448+/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
449+/* { dg-final { cleanup-tree-dump "vect" } } */
450+
451
452=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-shift-s8.c'
453--- old/gcc/testsuite/gcc.dg/vect/vect-widen-shift-s8.c 1970-01-01 00:00:00 +0000
454+++ new/gcc/testsuite/gcc.dg/vect/vect-widen-shift-s8.c 2011-10-23 13:33:07 +0000
455@@ -0,0 +1,58 @@
456+/* { dg-require-effective-target vect_int } */
457+/* { dg-require-effective-target vect_shift } */
458+
459+#include <stdarg.h>
460+#include "tree-vect.h"
461+
462+#define N 64
463+#define C 12
464+
465+__attribute__ ((noinline)) void
466+foo (char *src, int *dst)
467+{
468+ int i;
469+ char b, *s = src;
470+ int *d = dst;
471+
472+ for (i = 0; i < N; i++)
473+ {
474+ b = *s++;
475+ *d = b << C;
476+ d++;
477+ }
478+
479+ s = src;
480+ d = dst;
481+ for (i = 0; i < N; i++)
482+ {
483+ b = *s++;
484+ if (*d != b << C)
485+ abort ();
486+ d++;
487+ }
488+}
489+
490+int main (void)
491+{
492+ int i;
493+ char in[N];
494+ int out[N];
495+
496+ check_vect ();
497+
498+ for (i = 0; i < N; i++)
499+ {
500+ in[i] = i;
501+ out[i] = 255;
502+ __asm__ volatile ("");
503+ }
504+
505+ foo (in, out);
506+
507+ return 0;
508+}
509+
510+/* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 1 "vect" { target vect_widen_shift } } } */
511+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
512+/* { dg-final { cleanup-tree-dump "vect" } } */
513+
514
515=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-shift-u16.c'
516--- old/gcc/testsuite/gcc.dg/vect/vect-widen-shift-u16.c 1970-01-01 00:00:00 +0000
517+++ new/gcc/testsuite/gcc.dg/vect/vect-widen-shift-u16.c 2011-10-23 13:33:07 +0000
518@@ -0,0 +1,58 @@
519+/* { dg-require-effective-target vect_int } */
520+/* { dg-require-effective-target vect_shift } */
521+
522+#include <stdarg.h>
523+#include "tree-vect.h"
524+
525+#define N 64
526+#define C 7
527+
528+__attribute__ ((noinline)) void
529+foo (unsigned short *src, unsigned int *dst)
530+{
531+ int i;
532+ unsigned short b, *s = src;
533+ unsigned int *d = dst;
534+
535+ for (i = 0; i < N; i++)
536+ {
537+ b = *s++;
538+ *d = b << C;
539+ d++;
540+ }
541+
542+ s = src;
543+ d = dst;
544+ for (i = 0; i < N; i++)
545+ {
546+ b = *s++;
547+ if (*d != b << C)
548+ abort ();
549+ d++;
550+ }
551+}
552+
553+int main (void)
554+{
555+ int i;
556+ unsigned short in[N];
557+ unsigned int out[N];
558+
559+ check_vect ();
560+
561+ for (i = 0; i < N; i++)
562+ {
563+ in[i] = i;
564+ out[i] = 255;
565+ __asm__ volatile ("");
566+ }
567+
568+ foo (in, out);
569+
570+ return 0;
571+}
572+
573+/* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 1 "vect" { target vect_widen_shift } } } */
574+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
575+/* { dg-final { cleanup-tree-dump "vect" } } */
576+
577
578=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-shift-u8.c'
579--- old/gcc/testsuite/gcc.dg/vect/vect-widen-shift-u8.c 1970-01-01 00:00:00 +0000
580+++ new/gcc/testsuite/gcc.dg/vect/vect-widen-shift-u8.c 2011-10-23 13:33:07 +0000
581@@ -0,0 +1,65 @@
582+/* { dg-require-effective-target vect_int } */
583+/* { dg-require-effective-target vect_shift } */
584+
585+#include <stdarg.h>
586+#include "tree-vect.h"
587+
588+#define N 64
589+#define C1 10
590+#define C2 5
591+
592+__attribute__ ((noinline)) void
593+foo (unsigned char *src, unsigned int *dst1, unsigned int *dst2)
594+{
595+ int i;
596+ unsigned char b, *s = src;
597+ unsigned int *d1 = dst1, *d2 = dst2;
598+
599+ for (i = 0; i < N; i++)
600+ {
601+ b = *s++;
602+ *d1 = b << C1;
603+ d1++;
604+ *d2 = b << C2;
605+ d2++;
606+ }
607+
608+ s = src;
609+ d1 = dst1;
610+ d2 = dst2;
611+ for (i = 0; i < N; i++)
612+ {
613+ b = *s++;
614+ if (*d1 != b << C1 || *d2 != b << C2)
615+ abort ();
616+ d1++;
617+ d2++;
618+ }
619+}
620+
621+int main (void)
622+{
623+ int i;
624+ unsigned char in[N];
625+ unsigned int out1[N];
626+ unsigned int out2[N];
627+
628+ check_vect ();
629+
630+ for (i = 0; i < N; i++)
631+ {
632+ in[i] = i;
633+ out1[i] = 255;
634+ out2[i] = 255;
635+ __asm__ volatile ("");
636+ }
637+
638+ foo (in, out1, out2);
639+
640+ return 0;
641+}
642+
643+/* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 1 "vect" { target vect_widen_shift } } } */
644+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
645+/* { dg-final { cleanup-tree-dump "vect" } } */
646+
647
648=== modified file 'gcc/testsuite/lib/target-supports.exp'
649--- old/gcc/testsuite/lib/target-supports.exp 2011-10-06 11:08:08 +0000
650+++ new/gcc/testsuite/lib/target-supports.exp 2011-10-23 13:33:07 +0000
651@@ -2783,6 +2783,26 @@
652 }
653
654 # Return 1 if the target plus current options supports a vector
655+# widening shift, 0 otherwise.
656+#
657+# This won't change for different subtargets so cache the result.
658+
659+proc check_effective_target_vect_widen_shift { } {
660+ global et_vect_widen_shift_saved
661+
662+ if [info exists et_vect_shift_saved] {
663+ verbose "check_effective_target_vect_widen_shift: using cached result" 2
664+ } else {
665+ set et_vect_widen_shift_saved 0
666+ if { ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok]) } {
667+ set et_vect_widen_shift_saved 1
668+ }
669+ }
670+ verbose "check_effective_target_vect_widen_shift: returning $et_vect_widen_shift_saved" 2
671+ return $et_vect_widen_shift_saved
672+}
673+
674+# Return 1 if the target plus current options supports a vector
675 # dot-product of signed chars, 0 otherwise.
676 #
677 # This won't change for different subtargets so cache the result.
678
679=== modified file 'gcc/tree-cfg.c'
680--- old/gcc/tree-cfg.c 2011-07-15 13:44:50 +0000
681+++ new/gcc/tree-cfg.c 2011-10-23 13:33:07 +0000
682@@ -3473,6 +3473,44 @@
683 return false;
684 }
685
686+ case WIDEN_LSHIFT_EXPR:
687+ {
688+ if (!INTEGRAL_TYPE_P (lhs_type)
689+ || !INTEGRAL_TYPE_P (rhs1_type)
690+ || TREE_CODE (rhs2) != INTEGER_CST
691+ || (2 * TYPE_PRECISION (rhs1_type) > TYPE_PRECISION (lhs_type)))
692+ {
693+ error ("type mismatch in widening vector shift expression");
694+ debug_generic_expr (lhs_type);
695+ debug_generic_expr (rhs1_type);
696+ debug_generic_expr (rhs2_type);
697+ return true;
698+ }
699+
700+ return false;
701+ }
702+
703+ case VEC_WIDEN_LSHIFT_HI_EXPR:
704+ case VEC_WIDEN_LSHIFT_LO_EXPR:
705+ {
706+ if (TREE_CODE (rhs1_type) != VECTOR_TYPE
707+ || TREE_CODE (lhs_type) != VECTOR_TYPE
708+ || !INTEGRAL_TYPE_P (TREE_TYPE (rhs1_type))
709+ || !INTEGRAL_TYPE_P (TREE_TYPE (lhs_type))
710+ || TREE_CODE (rhs2) != INTEGER_CST
711+ || (2 * TYPE_PRECISION (TREE_TYPE (rhs1_type))
712+ > TYPE_PRECISION (TREE_TYPE (lhs_type))))
713+ {
714+ error ("type mismatch in widening vector shift expression");
715+ debug_generic_expr (lhs_type);
716+ debug_generic_expr (rhs1_type);
717+ debug_generic_expr (rhs2_type);
718+ return true;
719+ }
720+
721+ return false;
722+ }
723+
724 case PLUS_EXPR:
725 case MINUS_EXPR:
726 {
727
728=== modified file 'gcc/tree-inline.c'
729--- old/gcc/tree-inline.c 2011-08-13 08:32:32 +0000
730+++ new/gcc/tree-inline.c 2011-10-23 13:33:07 +0000
731@@ -3343,6 +3343,7 @@
732 case DOT_PROD_EXPR:
733 case WIDEN_MULT_PLUS_EXPR:
734 case WIDEN_MULT_MINUS_EXPR:
735+ case WIDEN_LSHIFT_EXPR:
736
737 case VEC_WIDEN_MULT_HI_EXPR:
738 case VEC_WIDEN_MULT_LO_EXPR:
739@@ -3357,6 +3358,8 @@
740 case VEC_EXTRACT_ODD_EXPR:
741 case VEC_INTERLEAVE_HIGH_EXPR:
742 case VEC_INTERLEAVE_LOW_EXPR:
743+ case VEC_WIDEN_LSHIFT_HI_EXPR:
744+ case VEC_WIDEN_LSHIFT_LO_EXPR:
745
746 return 1;
747
748
749=== modified file 'gcc/tree-pretty-print.c'
750--- old/gcc/tree-pretty-print.c 2010-11-05 09:00:50 +0000
751+++ new/gcc/tree-pretty-print.c 2011-10-23 13:33:07 +0000
752@@ -1539,6 +1539,7 @@
753 case RROTATE_EXPR:
754 case VEC_LSHIFT_EXPR:
755 case VEC_RSHIFT_EXPR:
756+ case WIDEN_LSHIFT_EXPR:
757 case BIT_IOR_EXPR:
758 case BIT_XOR_EXPR:
759 case BIT_AND_EXPR:
760@@ -2209,6 +2210,22 @@
761 pp_string (buffer, " > ");
762 break;
763
764+ case VEC_WIDEN_LSHIFT_HI_EXPR:
765+ pp_string (buffer, " VEC_WIDEN_LSHIFT_HI_EXPR < ");
766+ dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false);
767+ pp_string (buffer, ", ");
768+ dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false);
769+ pp_string (buffer, " > ");
770+ break;
771+
772+ case VEC_WIDEN_LSHIFT_LO_EXPR:
773+ pp_string (buffer, " VEC_WIDEN_LSHIFT_HI_EXPR < ");
774+ dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false);
775+ pp_string (buffer, ", ");
776+ dump_generic_node (buffer, TREE_OPERAND (node, 1), spc, flags, false);
777+ pp_string (buffer, " > ");
778+ break;
779+
780 case VEC_UNPACK_HI_EXPR:
781 pp_string (buffer, " VEC_UNPACK_HI_EXPR < ");
782 dump_generic_node (buffer, TREE_OPERAND (node, 0), spc, flags, false);
783@@ -2531,6 +2548,9 @@
784 case RSHIFT_EXPR:
785 case LROTATE_EXPR:
786 case RROTATE_EXPR:
787+ case VEC_WIDEN_LSHIFT_HI_EXPR:
788+ case VEC_WIDEN_LSHIFT_LO_EXPR:
789+ case WIDEN_LSHIFT_EXPR:
790 return 11;
791
792 case WIDEN_SUM_EXPR:
793@@ -2706,6 +2726,9 @@
794 case VEC_RSHIFT_EXPR:
795 return "v>>";
796
797+ case WIDEN_LSHIFT_EXPR:
798+ return "w<<";
799+
800 case POINTER_PLUS_EXPR:
801 return "+";
802
803
804=== modified file 'gcc/tree-vect-generic.c'
805--- old/gcc/tree-vect-generic.c 2011-02-08 14:16:50 +0000
806+++ new/gcc/tree-vect-generic.c 2011-10-23 13:33:07 +0000
807@@ -552,7 +552,9 @@
808 || code == VEC_UNPACK_LO_EXPR
809 || code == VEC_PACK_TRUNC_EXPR
810 || code == VEC_PACK_SAT_EXPR
811- || code == VEC_PACK_FIX_TRUNC_EXPR)
812+ || code == VEC_PACK_FIX_TRUNC_EXPR
813+ || code == VEC_WIDEN_LSHIFT_HI_EXPR
814+ || code == VEC_WIDEN_LSHIFT_LO_EXPR)
815 type = TREE_TYPE (rhs1);
816
817 /* Optabs will try converting a negation into a subtraction, so
818
819=== modified file 'gcc/tree-vect-patterns.c'
820--- old/gcc/tree-vect-patterns.c 2011-09-05 06:23:37 +0000
821+++ new/gcc/tree-vect-patterns.c 2011-10-23 13:33:07 +0000
822@@ -48,12 +48,15 @@
823 static gimple vect_recog_pow_pattern (VEC (gimple, heap) **, tree *, tree *);
824 static gimple vect_recog_over_widening_pattern (VEC (gimple, heap) **, tree *,
825 tree *);
826+static gimple vect_recog_widen_shift_pattern (VEC (gimple, heap) **,
827+ tree *, tree *);
828 static vect_recog_func_ptr vect_vect_recog_func_ptrs[NUM_PATTERNS] = {
829 vect_recog_widen_mult_pattern,
830 vect_recog_widen_sum_pattern,
831 vect_recog_dot_prod_pattern,
832 vect_recog_pow_pattern,
833- vect_recog_over_widening_pattern};
834+ vect_recog_over_widening_pattern,
835+ vect_recog_widen_shift_pattern};
836
837
838 /* Function widened_name_p
839@@ -331,27 +334,38 @@
840 return pattern_stmt;
841 }
842
843-/* Handle two cases of multiplication by a constant. The first one is when
844- the constant, CONST_OPRND, fits the type (HALF_TYPE) of the second
845- operand (OPRND). In that case, we can peform widen-mult from HALF_TYPE to
846- TYPE.
847+
848+/* Handle widening operation by a constant. At the moment we support MULT_EXPR
849+ and LSHIFT_EXPR.
850+
851+ For MULT_EXPR we check that CONST_OPRND fits HALF_TYPE, and for LSHIFT_EXPR
852+ we check that CONST_OPRND is less or equal to the size of HALF_TYPE.
853
854 Otherwise, if the type of the result (TYPE) is at least 4 times bigger than
855- HALF_TYPE, and CONST_OPRND fits an intermediate type (2 times smaller than
856- TYPE), we can perform widen-mult from the intermediate type to TYPE and
857- replace a_T = (TYPE) a_t; with a_it - (interm_type) a_t; */
858+ HALF_TYPE, and there is an intermediate type (2 times smaller than TYPE)
859+ that satisfies the above restrictions, we can perform a widening opeartion
860+ from the intermediate type to TYPE and replace a_T = (TYPE) a_t;
861+ with a_it = (interm_type) a_t; */
862
863 static bool
864-vect_handle_widen_mult_by_const (gimple stmt, tree const_oprnd, tree *oprnd,
865- VEC (gimple, heap) **stmts, tree type,
866- tree *half_type, gimple def_stmt)
867+vect_handle_widen_op_by_const (gimple stmt, enum tree_code code,
868+ tree const_oprnd, tree *oprnd,
869+ VEC (gimple, heap) **stmts, tree type,
870+ tree *half_type, gimple def_stmt)
871 {
872 tree new_type, new_oprnd, tmp;
873 gimple new_stmt;
874 loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
875 struct loop *loop = LOOP_VINFO_LOOP (loop_info);
876
877- if (int_fits_type_p (const_oprnd, *half_type))
878+ if (code != MULT_EXPR && code != LSHIFT_EXPR)
879+ return false;
880+
881+ if (((code == MULT_EXPR && int_fits_type_p (const_oprnd, *half_type))
882+ || (code == LSHIFT_EXPR
883+ && compare_tree_int (const_oprnd, TYPE_PRECISION (*half_type))
884+ != 1))
885+ && TYPE_PRECISION (type) == (TYPE_PRECISION (*half_type) * 2))
886 {
887 /* CONST_OPRND is a constant of HALF_TYPE. */
888 *oprnd = gimple_assign_rhs1 (def_stmt);
889@@ -364,14 +378,16 @@
890 || !vinfo_for_stmt (def_stmt))
891 return false;
892
893- /* TYPE is 4 times bigger than HALF_TYPE, try widen-mult for
894+ /* TYPE is 4 times bigger than HALF_TYPE, try widening operation for
895 a type 2 times bigger than HALF_TYPE. */
896 new_type = build_nonstandard_integer_type (TYPE_PRECISION (type) / 2,
897 TYPE_UNSIGNED (type));
898- if (!int_fits_type_p (const_oprnd, new_type))
899+ if ((code == MULT_EXPR && !int_fits_type_p (const_oprnd, new_type))
900+ || (code == LSHIFT_EXPR
901+ && compare_tree_int (const_oprnd, TYPE_PRECISION (new_type)) == 1))
902 return false;
903
904- /* Use NEW_TYPE for widen_mult. */
905+ /* Use NEW_TYPE for widening operation. */
906 if (STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)))
907 {
908 new_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt));
909@@ -381,6 +397,7 @@
910 || TREE_TYPE (gimple_assign_lhs (new_stmt)) != new_type)
911 return false;
912
913+ VEC_safe_push (gimple, heap, *stmts, def_stmt);
914 *oprnd = gimple_assign_lhs (new_stmt);
915 }
916 else
917@@ -392,7 +409,6 @@
918 new_oprnd = make_ssa_name (tmp, NULL);
919 new_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd, *oprnd,
920 NULL_TREE);
921- SSA_NAME_DEF_STMT (new_oprnd) = new_stmt;
922 STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)) = new_stmt;
923 VEC_safe_push (gimple, heap, *stmts, def_stmt);
924 *oprnd = new_oprnd;
925@@ -402,7 +418,6 @@
926 return true;
927 }
928
929-
930 /* Function vect_recog_widen_mult_pattern
931
932 Try to find the following pattern:
933@@ -491,7 +506,7 @@
934 enum tree_code dummy_code;
935 int dummy_int;
936 VEC (tree, heap) *dummy_vec;
937- bool op0_ok, op1_ok;
938+ bool op1_ok;
939
940 if (!is_gimple_assign (last_stmt))
941 return NULL;
942@@ -511,38 +526,23 @@
943 return NULL;
944
945 /* Check argument 0. */
946- op0_ok = widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0, false);
947+ if (!widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0, false))
948+ return NULL;
949 /* Check argument 1. */
950 op1_ok = widened_name_p (oprnd1, last_stmt, &half_type1, &def_stmt1, false);
951
952- /* In case of multiplication by a constant one of the operands may not match
953- the pattern, but not both. */
954- if (!op0_ok && !op1_ok)
955- return NULL;
956-
957- if (op0_ok && op1_ok)
958+ if (op1_ok)
959 {
960 oprnd0 = gimple_assign_rhs1 (def_stmt0);
961 oprnd1 = gimple_assign_rhs1 (def_stmt1);
962 }
963- else if (!op0_ok)
964- {
965- if (TREE_CODE (oprnd0) == INTEGER_CST
966- && TREE_CODE (half_type1) == INTEGER_TYPE
967- && vect_handle_widen_mult_by_const (last_stmt, oprnd0, &oprnd1,
968- stmts, type,
969- &half_type1, def_stmt1))
970- half_type0 = half_type1;
971- else
972- return NULL;
973- }
974- else if (!op1_ok)
975+ else
976 {
977 if (TREE_CODE (oprnd1) == INTEGER_CST
978 && TREE_CODE (half_type0) == INTEGER_TYPE
979- && vect_handle_widen_mult_by_const (last_stmt, oprnd1, &oprnd0,
980- stmts, type,
981- &half_type0, def_stmt0))
982+ && vect_handle_widen_op_by_const (last_stmt, MULT_EXPR, oprnd1,
983+ &oprnd0, stmts, type,
984+ &half_type0, def_stmt0))
985 half_type1 = half_type0;
986 else
987 return NULL;
988@@ -998,6 +998,7 @@
989 || TREE_TYPE (gimple_assign_lhs (new_stmt)) != interm_type)
990 return false;
991
992+ VEC_safe_push (gimple, heap, *stmts, def_stmt);
993 oprnd = gimple_assign_lhs (new_stmt);
994 }
995 else
996@@ -1128,7 +1129,7 @@
997 statetments, except for the case when the last statement in the
998 sequence doesn't have a corresponding pattern statement. In such
999 case we associate the last pattern statement with the last statement
1000- in the sequence. Therefore, we only add an original statetement to
1001+ in the sequence. Therefore, we only add the original statement to
1002 the list if we know that it is not the last. */
1003 if (prev_stmt)
1004 VEC_safe_push (gimple, heap, *stmts, prev_stmt);
1005@@ -1215,6 +1216,231 @@
1006 }
1007
1008
1009+/* Detect widening shift pattern:
1010+
1011+ type a_t;
1012+ TYPE a_T, res_T;
1013+
1014+ S1 a_t = ;
1015+ S2 a_T = (TYPE) a_t;
1016+ S3 res_T = a_T << CONST;
1017+
1018+ where type 'TYPE' is at least double the size of type 'type'.
1019+
1020+ Also detect unsigned cases:
1021+
1022+ unsigned type a_t;
1023+ unsigned TYPE u_res_T;
1024+ TYPE a_T, res_T;
1025+
1026+ S1 a_t = ;
1027+ S2 a_T = (TYPE) a_t;
1028+ S3 res_T = a_T << CONST;
1029+ S4 u_res_T = (unsigned TYPE) res_T;
1030+
1031+ And a case when 'TYPE' is 4 times bigger than 'type'. In that case we
1032+ create an additional pattern stmt for S2 to create a variable of an
1033+ intermediate type, and perform widen-shift on the intermediate type:
1034+
1035+ type a_t;
1036+ interm_type a_it;
1037+ TYPE a_T, res_T, res_T';
1038+
1039+ S1 a_t = ;
1040+ S2 a_T = (TYPE) a_t;
1041+ '--> a_it = (interm_type) a_t;
1042+ S3 res_T = a_T << CONST;
1043+ '--> res_T' = a_it <<* CONST;
1044+
1045+ Input/Output:
1046+
1047+ * STMTS: Contains a stmt from which the pattern search begins.
1048+ In case of unsigned widen-shift, the original stmt (S3) is replaced with S4
1049+ in STMTS. When an intermediate type is used and a pattern statement is
1050+ created for S2, we also put S2 here (before S3).
1051+
1052+ Output:
1053+
1054+ * TYPE_IN: The type of the input arguments to the pattern.
1055+
1056+ * TYPE_OUT: The type of the output of this pattern.
1057+
1058+ * Return value: A new stmt that will be used to replace the sequence of
1059+ stmts that constitute the pattern. In this case it will be:
1060+ WIDEN_LSHIFT_EXPR <a_t, CONST>. */
1061+
1062+static gimple
1063+vect_recog_widen_shift_pattern (VEC (gimple, heap) **stmts,
1064+ tree *type_in, tree *type_out)
1065+{
1066+ gimple last_stmt = VEC_pop (gimple, *stmts);
1067+ gimple def_stmt0;
1068+ tree oprnd0, oprnd1;
1069+ tree type, half_type0;
1070+ gimple pattern_stmt, orig_stmt = NULL;
1071+ tree vectype, vectype_out = NULL_TREE;
1072+ tree dummy;
1073+ tree var;
1074+ enum tree_code dummy_code;
1075+ int dummy_int;
1076+ VEC (tree, heap) * dummy_vec;
1077+ gimple use_stmt = NULL;
1078+ bool over_widen = false;
1079+
1080+ if (!is_gimple_assign (last_stmt) || !vinfo_for_stmt (last_stmt))
1081+ return NULL;
1082+
1083+ orig_stmt = last_stmt;
1084+ if (STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (last_stmt)))
1085+ {
1086+ /* This statement was also detected as over-widening operation (it can't
1087+ be any other pattern, because only over-widening detects shifts).
1088+ LAST_STMT is the final type demotion statement, but its related
1089+ statement is shift. We analyze the related statement to catch cases:
1090+
1091+ orig code:
1092+ type a_t;
1093+ itype res;
1094+ TYPE a_T, res_T;
1095+
1096+ S1 a_T = (TYPE) a_t;
1097+ S2 res_T = a_T << CONST;
1098+ S3 res = (itype)res_T;
1099+
1100+ (size of type * 2 <= size of itype
1101+ and size of itype * 2 <= size of TYPE)
1102+
1103+ code after over-widening pattern detection:
1104+
1105+ S1 a_T = (TYPE) a_t;
1106+ --> a_it = (itype) a_t;
1107+ S2 res_T = a_T << CONST;
1108+ S3 res = (itype)res_T; <--- LAST_STMT
1109+ --> res = a_it << CONST;
1110+
1111+ after widen_shift:
1112+
1113+ S1 a_T = (TYPE) a_t;
1114+ --> a_it = (itype) a_t; - redundant
1115+ S2 res_T = a_T << CONST;
1116+ S3 res = (itype)res_T;
1117+ --> res = a_t w<< CONST;
1118+
1119+ i.e., we replace the three statements with res = a_t w<< CONST. */
1120+ last_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (last_stmt));
1121+ over_widen = true;
1122+ }
1123+
1124+ if (gimple_assign_rhs_code (last_stmt) != LSHIFT_EXPR)
1125+ return NULL;
1126+
1127+ oprnd0 = gimple_assign_rhs1 (last_stmt);
1128+ oprnd1 = gimple_assign_rhs2 (last_stmt);
1129+ if (TREE_CODE (oprnd0) != SSA_NAME || TREE_CODE (oprnd1) != INTEGER_CST)
1130+ return NULL;
1131+
1132+ /* Check operand 0: it has to be defined by a type promotion. */
1133+ if (!widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0, false))
1134+ return NULL;
1135+
1136+ /* Check operand 1: has to be positive. We check that it fits the type
1137+ in vect_handle_widen_op_by_const (). */
1138+ if (tree_int_cst_compare (oprnd1, size_zero_node) <= 0)
1139+ return NULL;
1140+
1141+ oprnd0 = gimple_assign_rhs1 (def_stmt0);
1142+ type = gimple_expr_type (last_stmt);
1143+
1144+ /* Check if this a widening operation. */
1145+ if (!vect_handle_widen_op_by_const (last_stmt, LSHIFT_EXPR, oprnd1,
1146+ &oprnd0, stmts,
1147+ type, &half_type0, def_stmt0))
1148+ return NULL;
1149+
1150+ /* Handle unsigned case. Look for
1151+ S4 u_res_T = (unsigned TYPE) res_T;
1152+ Use unsigned TYPE as the type for WIDEN_LSHIFT_EXPR. */
1153+ if (TYPE_UNSIGNED (type) != TYPE_UNSIGNED (half_type0))
1154+ {
1155+ tree lhs = gimple_assign_lhs (last_stmt), use_lhs;
1156+ imm_use_iterator imm_iter;
1157+ use_operand_p use_p;
1158+ int nuses = 0;
1159+ tree use_type;
1160+
1161+ if (over_widen)
1162+ {
1163+ /* In case of over-widening pattern, S4 should be ORIG_STMT itself.
1164+ We check here that TYPE is the correct type for the operation,
1165+ i.e., it's the type of the original result. */
1166+ tree orig_type = gimple_expr_type (orig_stmt);
1167+ if ((TYPE_UNSIGNED (type) != TYPE_UNSIGNED (orig_type))
1168+ || (TYPE_PRECISION (type) != TYPE_PRECISION (orig_type)))
1169+ return NULL;
1170+ }
1171+ else
1172+ {
1173+ FOR_EACH_IMM_USE_FAST (use_p, imm_iter, lhs)
1174+ {
1175+ if (is_gimple_debug (USE_STMT (use_p)))
1176+ continue;
1177+ use_stmt = USE_STMT (use_p);
1178+ nuses++;
1179+ }
1180+
1181+ if (nuses != 1 || !is_gimple_assign (use_stmt)
1182+ || !CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (use_stmt)))
1183+ return NULL;
1184+
1185+ use_lhs = gimple_assign_lhs (use_stmt);
1186+ use_type = TREE_TYPE (use_lhs);
1187+
1188+ if (!INTEGRAL_TYPE_P (use_type)
1189+ || (TYPE_UNSIGNED (type) == TYPE_UNSIGNED (use_type))
1190+ || (TYPE_PRECISION (type) != TYPE_PRECISION (use_type)))
1191+ return NULL;
1192+
1193+ type = use_type;
1194+ }
1195+ }
1196+
1197+ /* Pattern detected. */
1198+ if (vect_print_dump_info (REPORT_DETAILS))
1199+ fprintf (vect_dump, "vect_recog_widen_shift_pattern: detected: ");
1200+
1201+ /* Check target support. */
1202+ vectype = get_vectype_for_scalar_type (half_type0);
1203+ vectype_out = get_vectype_for_scalar_type (type);
1204+
1205+ if (!vectype
1206+ || !vectype_out
1207+ || !supportable_widening_operation (WIDEN_LSHIFT_EXPR, last_stmt,
1208+ vectype_out, vectype,
1209+ &dummy, &dummy, &dummy_code,
1210+ &dummy_code, &dummy_int,
1211+ &dummy_vec))
1212+ return NULL;
1213+
1214+ *type_in = vectype;
1215+ *type_out = vectype_out;
1216+
1217+ /* Pattern supported. Create a stmt to be used to replace the pattern. */
1218+ var = vect_recog_temp_ssa_var (type, NULL);
1219+ pattern_stmt =
1220+ gimple_build_assign_with_ops (WIDEN_LSHIFT_EXPR, var, oprnd0, oprnd1);
1221+
1222+ if (vect_print_dump_info (REPORT_DETAILS))
1223+ print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
1224+
1225+ if (use_stmt)
1226+ last_stmt = use_stmt;
1227+ else
1228+ last_stmt = orig_stmt;
1229+
1230+ VEC_safe_push (gimple, heap, *stmts, last_stmt);
1231+ return pattern_stmt;
1232+}
1233+
1234 /* Mark statements that are involved in a pattern. */
1235
1236 static inline void
1237@@ -1278,7 +1504,8 @@
1238 static void
1239 vect_pattern_recog_1 (
1240 gimple (* vect_recog_func) (VEC (gimple, heap) **, tree *, tree *),
1241- gimple_stmt_iterator si)
1242+ gimple_stmt_iterator si,
1243+ VEC (gimple, heap) **stmts_to_replace)
1244 {
1245 gimple stmt = gsi_stmt (si), pattern_stmt;
1246 stmt_vec_info stmt_info;
1247@@ -1288,14 +1515,14 @@
1248 enum tree_code code;
1249 int i;
1250 gimple next;
1251- VEC (gimple, heap) *stmts_to_replace = VEC_alloc (gimple, heap, 1);
1252
1253- VEC_quick_push (gimple, stmts_to_replace, stmt);
1254- pattern_stmt = (* vect_recog_func) (&stmts_to_replace, &type_in, &type_out);
1255+ VEC_truncate (gimple, *stmts_to_replace, 0);
1256+ VEC_quick_push (gimple, *stmts_to_replace, stmt);
1257+ pattern_stmt = (* vect_recog_func) (stmts_to_replace, &type_in, &type_out);
1258 if (!pattern_stmt)
1259 return;
1260
1261- stmt = VEC_last (gimple, stmts_to_replace);
1262+ stmt = VEC_last (gimple, *stmts_to_replace);
1263 stmt_info = vinfo_for_stmt (stmt);
1264 loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info);
1265
1266@@ -1303,8 +1530,6 @@
1267 {
1268 /* No need to check target support (already checked by the pattern
1269 recognition function). */
1270- if (type_out)
1271- gcc_assert (VECTOR_MODE_P (TYPE_MODE (type_out)));
1272 pattern_vectype = type_out ? type_out : type_in;
1273 }
1274 else
1275@@ -1360,8 +1585,8 @@
1276 /* It is possible that additional pattern stmts are created and inserted in
1277 STMTS_TO_REPLACE. We create a stmt_info for each of them, and mark the
1278 relevant statements. */
1279- for (i = 0; VEC_iterate (gimple, stmts_to_replace, i, stmt)
1280- && (unsigned) i < (VEC_length (gimple, stmts_to_replace) - 1);
1281+ for (i = 0; VEC_iterate (gimple, *stmts_to_replace, i, stmt)
1282+ && (unsigned) i < (VEC_length (gimple, *stmts_to_replace) - 1);
1283 i++)
1284 {
1285 stmt_info = vinfo_for_stmt (stmt);
1286@@ -1374,8 +1599,6 @@
1287
1288 vect_mark_pattern_stmts (stmt, pattern_stmt, NULL_TREE);
1289 }
1290-
1291- VEC_free (gimple, heap, stmts_to_replace);
1292 }
1293
1294
1295@@ -1465,6 +1688,7 @@
1296 gimple_stmt_iterator si;
1297 unsigned int i, j;
1298 gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
1299+ VEC (gimple, heap) *stmts_to_replace = VEC_alloc (gimple, heap, 1);
1300
1301 if (vect_print_dump_info (REPORT_DETAILS))
1302 fprintf (vect_dump, "=== vect_pattern_recog ===");
1303@@ -1480,8 +1704,11 @@
1304 for (j = 0; j < NUM_PATTERNS; j++)
1305 {
1306 vect_recog_func_ptr = vect_vect_recog_func_ptrs[j];
1307- vect_pattern_recog_1 (vect_recog_func_ptr, si);
1308+ vect_pattern_recog_1 (vect_recog_func_ptr, si,
1309+ &stmts_to_replace);
1310 }
1311 }
1312 }
1313+
1314+ VEC_free (gimple, heap, stmts_to_replace);
1315 }
1316
1317=== modified file 'gcc/tree-vect-slp.c'
1318--- old/gcc/tree-vect-slp.c 2011-10-23 11:29:25 +0000
1319+++ new/gcc/tree-vect-slp.c 2011-10-27 11:27:59 +0000
1320@@ -480,6 +480,11 @@
1321 }
1322 }
1323 }
1324+ else if (rhs_code == WIDEN_LSHIFT_EXPR)
1325+ {
1326+ need_same_oprnds = true;
1327+ first_op1 = gimple_assign_rhs2 (stmt);
1328+ }
1329 }
1330 else
1331 {
1332
1333=== modified file 'gcc/tree-vect-stmts.c'
1334--- old/gcc/tree-vect-stmts.c 2011-10-23 11:29:25 +0000
1335+++ new/gcc/tree-vect-stmts.c 2011-10-27 11:27:59 +0000
1336@@ -3359,6 +3359,7 @@
1337 VEC (tree, heap) *vec_oprnds0 = NULL, *vec_oprnds1 = NULL;
1338 VEC (tree, heap) *vec_dsts = NULL, *interm_types = NULL, *tmp_vec_dsts = NULL;
1339 bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
1340+ unsigned int k;
1341
1342 if (!STMT_VINFO_RELEVANT_P (stmt_info) && !bb_vinfo)
1343 return false;
1344@@ -3375,7 +3376,8 @@
1345
1346 code = gimple_assign_rhs_code (stmt);
1347 if (!CONVERT_EXPR_CODE_P (code)
1348- && code != WIDEN_MULT_EXPR)
1349+ && code != WIDEN_MULT_EXPR
1350+ && code != WIDEN_LSHIFT_EXPR)
1351 return false;
1352
1353 scalar_dest = gimple_assign_lhs (stmt);
1354@@ -3403,7 +3405,7 @@
1355 bool ok;
1356
1357 op1 = gimple_assign_rhs2 (stmt);
1358- if (code == WIDEN_MULT_EXPR)
1359+ if (code == WIDEN_MULT_EXPR || code == WIDEN_LSHIFT_EXPR)
1360 {
1361 /* For WIDEN_MULT_EXPR, if OP0 is a constant, use the type of
1362 OP1. */
1363@@ -3480,7 +3482,7 @@
1364 fprintf (vect_dump, "transform type promotion operation. ncopies = %d.",
1365 ncopies);
1366
1367- if (code == WIDEN_MULT_EXPR)
1368+ if (code == WIDEN_MULT_EXPR || code == WIDEN_LSHIFT_EXPR)
1369 {
1370 if (CONSTANT_CLASS_P (op0))
1371 op0 = fold_convert (TREE_TYPE (op1), op0);
1372@@ -3521,6 +3523,8 @@
1373 if (op_type == binary_op)
1374 vec_oprnds1 = VEC_alloc (tree, heap, 1);
1375 }
1376+ else if (code == WIDEN_LSHIFT_EXPR)
1377+ vec_oprnds1 = VEC_alloc (tree, heap, slp_node->vec_stmts_size);
1378
1379 /* In case the vectorization factor (VF) is bigger than the number
1380 of elements that we can fit in a vectype (nunits), we have to generate
1381@@ -3534,15 +3538,33 @@
1382 if (j == 0)
1383 {
1384 if (slp_node)
1385- vect_get_slp_defs (op0, op1, slp_node, &vec_oprnds0,
1386- &vec_oprnds1, -1);
1387- else
1388+ {
1389+ if (code == WIDEN_LSHIFT_EXPR)
1390+ {
1391+ vec_oprnd1 = op1;
1392+ /* Store vec_oprnd1 for every vector stmt to be created
1393+ for SLP_NODE. We check during the analysis that all
1394+ the shift arguments are the same. */
1395+ for (k = 0; k < slp_node->vec_stmts_size - 1; k++)
1396+ VEC_quick_push (tree, vec_oprnds1, vec_oprnd1);
1397+
1398+ vect_get_slp_defs (op0, NULL_TREE, slp_node, &vec_oprnds0, NULL,
1399+ -1);
1400+ }
1401+ else
1402+ vect_get_slp_defs (op0, op1, slp_node, &vec_oprnds0,
1403+ &vec_oprnds1, -1);
1404+ }
1405+ else
1406 {
1407 vec_oprnd0 = vect_get_vec_def_for_operand (op0, stmt, NULL);
1408 VEC_quick_push (tree, vec_oprnds0, vec_oprnd0);
1409 if (op_type == binary_op)
1410 {
1411- vec_oprnd1 = vect_get_vec_def_for_operand (op1, stmt, NULL);
1412+ if (code == WIDEN_LSHIFT_EXPR)
1413+ vec_oprnd1 = op1;
1414+ else
1415+ vec_oprnd1 = vect_get_vec_def_for_operand (op1, stmt, NULL);
1416 VEC_quick_push (tree, vec_oprnds1, vec_oprnd1);
1417 }
1418 }
1419@@ -3553,7 +3575,10 @@
1420 VEC_replace (tree, vec_oprnds0, 0, vec_oprnd0);
1421 if (op_type == binary_op)
1422 {
1423- vec_oprnd1 = vect_get_vec_def_for_stmt_copy (dt[1], vec_oprnd1);
1424+ if (code == WIDEN_LSHIFT_EXPR)
1425+ vec_oprnd1 = op1;
1426+ else
1427+ vec_oprnd1 = vect_get_vec_def_for_stmt_copy (dt[1], vec_oprnd1);
1428 VEC_replace (tree, vec_oprnds1, 0, vec_oprnd1);
1429 }
1430 }
1431@@ -5853,6 +5878,19 @@
1432 }
1433 break;
1434
1435+ case WIDEN_LSHIFT_EXPR:
1436+ if (BYTES_BIG_ENDIAN)
1437+ {
1438+ c1 = VEC_WIDEN_LSHIFT_HI_EXPR;
1439+ c2 = VEC_WIDEN_LSHIFT_LO_EXPR;
1440+ }
1441+ else
1442+ {
1443+ c2 = VEC_WIDEN_LSHIFT_HI_EXPR;
1444+ c1 = VEC_WIDEN_LSHIFT_LO_EXPR;
1445+ }
1446+ break;
1447+
1448 CASE_CONVERT:
1449 if (BYTES_BIG_ENDIAN)
1450 {
1451
1452=== modified file 'gcc/tree-vectorizer.h'
1453--- old/gcc/tree-vectorizer.h 2011-09-05 06:23:37 +0000
1454+++ new/gcc/tree-vectorizer.h 2011-10-23 13:33:07 +0000
1455@@ -896,7 +896,7 @@
1456 Additional pattern recognition functions can (and will) be added
1457 in the future. */
1458 typedef gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
1459-#define NUM_PATTERNS 5
1460+#define NUM_PATTERNS 6
1461 void vect_pattern_recog (loop_vec_info);
1462
1463 /* In tree-vectorizer.c. */
1464
1465=== modified file 'gcc/tree.def'
1466--- old/gcc/tree.def 2011-01-21 14:14:12 +0000
1467+++ new/gcc/tree.def 2011-10-23 13:33:07 +0000
1468@@ -1092,6 +1092,19 @@
1469 is subtracted from t3. */
1470 DEFTREECODE (WIDEN_MULT_MINUS_EXPR, "widen_mult_minus_expr", tcc_expression, 3)
1471
1472+/* Widening shift left.
1473+ The first operand is of type t1.
1474+ The second operand is the number of bits to shift by; it need not be the
1475+ same type as the first operand and result.
1476+ Note that the result is undefined if the second operand is larger
1477+ than or equal to the first operand's type size.
1478+ The type of the entire expression is t2, such that t2 is at least twice
1479+ the size of t1.
1480+ WIDEN_LSHIFT_EXPR is equivalent to first widening (promoting)
1481+ the first argument from type t1 to type t2, and then shifting it
1482+ by the second argument. */
1483+DEFTREECODE (WIDEN_LSHIFT_EXPR, "widen_lshift_expr", tcc_binary, 2)
1484+
1485 /* Fused multiply-add.
1486 All operands and the result are of the same type. No intermediate
1487 rounding is performed after multiplying operand one with operand two
1488@@ -1147,6 +1160,16 @@
1489 DEFTREECODE (VEC_INTERLEAVE_HIGH_EXPR, "vec_interleavehigh_expr", tcc_binary, 2)
1490 DEFTREECODE (VEC_INTERLEAVE_LOW_EXPR, "vec_interleavelow_expr", tcc_binary, 2)
1491
1492+/* Widening vector shift left in bits.
1493+ Operand 0 is a vector to be shifted with N elements of size S.
1494+ Operand 1 is an integer shift amount in bits.
1495+ The result of the operation is N elements of size 2*S.
1496+ VEC_WIDEN_LSHIFT_HI_EXPR computes the N/2 high results.
1497+ VEC_WIDEN_LSHIFT_LO_EXPR computes the N/2 low results.
1498+ */
1499+DEFTREECODE (VEC_WIDEN_LSHIFT_HI_EXPR, "widen_lshift_hi_expr", tcc_binary, 2)
1500+DEFTREECODE (VEC_WIDEN_LSHIFT_LO_EXPR, "widen_lshift_lo_expr", tcc_binary, 2)
1501+
1502 /* PREDICT_EXPR. Specify hint for branch prediction. The
1503 PREDICT_EXPR_PREDICTOR specify predictor and PREDICT_EXPR_OUTCOME the
1504 outcome (0 for not taken and 1 for taken). Once the profile is guessed
1505
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106836.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106836.patch
deleted file mode 100644
index 95b9ea9b8..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106836.patch
+++ /dev/null
@@ -1,61 +0,0 @@
12011-11-04 Revital Eres <revital.eres@linaro.org>
2
3 Backport from mainline -r180673:
4
5 gcc/
6 * modulo-sched.c (generate_prolog_epilog): Mark prolog
7 and epilog as BB_DISABLE_SCHEDULE.
8 (mark_loop_unsched): New function.
9 (sms_schedule): Call it.
10
11=== modified file 'gcc/modulo-sched.c'
12--- old/gcc/modulo-sched.c 2011-10-10 14:35:32 +0000
13+++ new/gcc/modulo-sched.c 2011-10-30 05:31:00 +0000
14@@ -1173,6 +1173,8 @@
15 /* Put the prolog on the entry edge. */
16 e = loop_preheader_edge (loop);
17 split_edge_and_insert (e, get_insns ());
18+ if (!flag_resched_modulo_sched)
19+ e->dest->flags |= BB_DISABLE_SCHEDULE;
20
21 end_sequence ();
22
23@@ -1186,9 +1188,24 @@
24 gcc_assert (single_exit (loop));
25 e = single_exit (loop);
26 split_edge_and_insert (e, get_insns ());
27+ if (!flag_resched_modulo_sched)
28+ e->dest->flags |= BB_DISABLE_SCHEDULE;
29+
30 end_sequence ();
31 }
32
33+/* Mark LOOP as software pipelined so the later
34+ scheduling passes don't touch it. */
35+static void
36+mark_loop_unsched (struct loop *loop)
37+{
38+ unsigned i;
39+ basic_block *bbs = get_loop_body (loop);
40+
41+ for (i = 0; i < loop->num_nodes; i++)
42+ bbs[i]->flags |= BB_DISABLE_SCHEDULE;
43+}
44+
45 /* Return true if all the BBs of the loop are empty except the
46 loop header. */
47 static bool
48@@ -1714,9 +1731,10 @@
49 permute_partial_schedule (ps, g->closing_branch->first_note);
50
51 /* Mark this loop as software pipelined so the later
52- scheduling passes doesn't touch it. */
53+ scheduling passes don't touch it. */
54 if (! flag_resched_modulo_sched)
55- g->bb->flags |= BB_DISABLE_SCHEDULE;
56+ mark_loop_unsched (loop);
57+
58 /* The life-info is not valid any more. */
59 df_set_bb_dirty (g->bb);
60
61
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106839.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106839.patch
deleted file mode 100644
index dcffe1945..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106839.patch
+++ /dev/null
@@ -1,23 +0,0 @@
12011-11-02 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF mainline:
4
5 2011-11-01 Andrew Stubbs <ams@codesourcery.com>
6
7 gcc/
8 * config/arm/bpabi.h (BE8_LINK_SPEC): Recognize generic-armv7 tuning.
9
10=== modified file 'gcc/config/arm/bpabi.h'
11--- old/gcc/config/arm/bpabi.h 2010-12-20 17:48:51 +0000
12+++ new/gcc/config/arm/bpabi.h 2011-11-02 21:02:53 +0000
13@@ -56,7 +56,8 @@
14 "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}"
15
16 #define BE8_LINK_SPEC " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5"\
17- "|mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15:%{!r:--be8}}}"
18+ "|mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15|mcpu=generic-armv7-a"\
19+ ":%{!r:--be8}}}"
20
21 /* Tell the assembler to build BPABI binaries. */
22 #undef SUBTARGET_EXTRA_ASM_SPEC
23
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106840.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106840.patch
deleted file mode 100644
index 70a7bdfa2..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106840.patch
+++ /dev/null
@@ -1,1400 +0,0 @@
12011-11-17 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from mainline:
4
5 2011-11-03 Ira Rosen <ira.rosen@linaro.org>
6
7 gcc/
8 * tree-vectorizer.h (slp_void_p): New.
9 (struct _slp_tree): Replace left and right with children. Update
10 documentation.
11 (struct _slp_oprnd_info): New.
12 (vect_get_vec_defs): Declare.
13 (vect_get_slp_defs): Update arguments.
14 * tree-vect-loop.c (vect_create_epilog_for_reduction): Call
15 vect_get_vec_defs instead of vect_get_slp_defs.
16 (vectorizable_reduction): Likewise.
17 * tree-vect-stmts.c (vect_get_vec_defs): Remove static, add argument.
18 Update call to vect_get_slp_defs.
19 (vectorizable_conversion): Update call to vect_get_vec_defs.
20 (vectorizable_assignment, vectorizable_shift,
21 vectorizable_operation): Likewise.
22 (vectorizable_type_demotion): Call vect_get_vec_defs instead of
23 vect_get_slp_defs.
24 (vectorizable_type_promotion, vectorizable_store): Likewise.
25 (vect_analyze_stmt): Fix typo.
26 * tree-vect-slp.c (vect_free_slp_tree): Update SLP tree traversal.
27 (vect_print_slp_tree, vect_mark_slp_stmts,
28 vect_mark_slp_stmts_relevant, vect_slp_rearrange_stmts,
29 vect_detect_hybrid_slp_stmts, vect_slp_analyze_node_operations,
30 vect_schedule_slp_instance): Likewise.
31 (vect_create_new_slp_node): New.
32 (vect_create_oprnd_info, vect_free_oprnd_info): Likewise.
33 (vect_get_and_check_slp_defs): Pass information about defs using
34 oprnds_info, allow any number of operands.
35 (vect_build_slp_tree): Likewise. Update calls to
36 vect_get_and_check_slp_defs. Fix comments.
37 (vect_analyze_slp_instance): Move node creation to
38 vect_create_new_slp_node.
39 (vect_get_slp_defs): Allow any number of operands.
40
41 2011-11-11 Jakub Jelinek <jakub@redhat.com>
42
43 gcc/
44 * tree-vect-slp.c (vect_free_slp_tree): Also free SLP_TREE_CHILDREN
45 vector.
46 (vect_create_new_slp_node): Don't allocate node before checking stmt
47 type.
48 (vect_free_oprnd_info): Remove FREE_DEF_STMTS argument, always
49 free def_stmts vectors and additionally free oprnd_info.
50 (vect_build_slp_tree): Adjust callers. Call it even if
51 stop_recursion. If vect_create_new_slp_node or
52 vect_build_slp_tree fails, properly handle freeing memory.
53 If it succeeded, clear def_stmts in oprnd_info.
54
55=== modified file 'gcc/tree-vect-loop.c'
56--- old/gcc/tree-vect-loop.c 2011-09-05 06:23:37 +0000
57+++ new/gcc/tree-vect-loop.c 2011-11-14 11:38:08 +0000
58@@ -3282,8 +3282,8 @@
59
60 /* Get the loop-entry arguments. */
61 if (slp_node)
62- vect_get_slp_defs (reduction_op, NULL_TREE, slp_node, &vec_initial_defs,
63- NULL, reduc_index);
64+ vect_get_vec_defs (reduction_op, NULL_TREE, stmt, &vec_initial_defs,
65+ NULL, slp_node, reduc_index);
66 else
67 {
68 vec_initial_defs = VEC_alloc (tree, heap, 1);
69@@ -4451,8 +4451,8 @@
70 }
71
72 if (slp_node)
73- vect_get_slp_defs (op0, op1, slp_node, &vec_oprnds0, &vec_oprnds1,
74- -1);
75+ vect_get_vec_defs (op0, op1, stmt, &vec_oprnds0, &vec_oprnds1,
76+ slp_node, -1);
77 else
78 {
79 loop_vec_def0 = vect_get_vec_def_for_operand (ops[!reduc_index],
80
81=== modified file 'gcc/tree-vect-slp.c'
82--- old/gcc/tree-vect-slp.c 2011-10-27 11:27:59 +0000
83+++ new/gcc/tree-vect-slp.c 2011-11-14 11:38:08 +0000
84@@ -67,15 +67,16 @@
85 static void
86 vect_free_slp_tree (slp_tree node)
87 {
88+ int i;
89+ slp_void_p child;
90+
91 if (!node)
92 return;
93
94- if (SLP_TREE_LEFT (node))
95- vect_free_slp_tree (SLP_TREE_LEFT (node));
96-
97- if (SLP_TREE_RIGHT (node))
98- vect_free_slp_tree (SLP_TREE_RIGHT (node));
99-
100+ FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
101+ vect_free_slp_tree ((slp_tree) child);
102+
103+ VEC_free (slp_void_p, heap, SLP_TREE_CHILDREN (node));
104 VEC_free (gimple, heap, SLP_TREE_SCALAR_STMTS (node));
105
106 if (SLP_TREE_VEC_STMTS (node))
107@@ -96,48 +97,116 @@
108 }
109
110
111-/* Get the defs for the rhs of STMT (collect them in DEF_STMTS0/1), check that
112- they are of a legal type and that they match the defs of the first stmt of
113- the SLP group (stored in FIRST_STMT_...). */
114+/* Create an SLP node for SCALAR_STMTS. */
115+
116+static slp_tree
117+vect_create_new_slp_node (VEC (gimple, heap) *scalar_stmts)
118+{
119+ slp_tree node;
120+ gimple stmt = VEC_index (gimple, scalar_stmts, 0);
121+ unsigned int nops;
122+
123+ if (is_gimple_call (stmt))
124+ nops = gimple_call_num_args (stmt);
125+ else if (is_gimple_assign (stmt))
126+ nops = gimple_num_ops (stmt) - 1;
127+ else
128+ return NULL;
129+
130+ node = XNEW (struct _slp_tree);
131+ SLP_TREE_SCALAR_STMTS (node) = scalar_stmts;
132+ SLP_TREE_VEC_STMTS (node) = NULL;
133+ SLP_TREE_CHILDREN (node) = VEC_alloc (slp_void_p, heap, nops);
134+ SLP_TREE_OUTSIDE_OF_LOOP_COST (node) = 0;
135+ SLP_TREE_INSIDE_OF_LOOP_COST (node) = 0;
136+
137+ return node;
138+}
139+
140+
141+/* Allocate operands info for NOPS operands, and GROUP_SIZE def-stmts for each
142+ operand. */
143+static VEC (slp_oprnd_info, heap) *
144+vect_create_oprnd_info (int nops, int group_size)
145+{
146+ int i;
147+ slp_oprnd_info oprnd_info;
148+ VEC (slp_oprnd_info, heap) *oprnds_info;
149+
150+ oprnds_info = VEC_alloc (slp_oprnd_info, heap, nops);
151+ for (i = 0; i < nops; i++)
152+ {
153+ oprnd_info = XNEW (struct _slp_oprnd_info);
154+ oprnd_info->def_stmts = VEC_alloc (gimple, heap, group_size);
155+ oprnd_info->first_dt = vect_uninitialized_def;
156+ oprnd_info->first_def_type = NULL_TREE;
157+ oprnd_info->first_const_oprnd = NULL_TREE;
158+ oprnd_info->first_pattern = false;
159+ VEC_quick_push (slp_oprnd_info, oprnds_info, oprnd_info);
160+ }
161+
162+ return oprnds_info;
163+}
164+
165+
166+/* Free operands info. */
167+
168+static void
169+vect_free_oprnd_info (VEC (slp_oprnd_info, heap) **oprnds_info)
170+{
171+ int i;
172+ slp_oprnd_info oprnd_info;
173+
174+ FOR_EACH_VEC_ELT (slp_oprnd_info, *oprnds_info, i, oprnd_info)
175+ {
176+ VEC_free (gimple, heap, oprnd_info->def_stmts);
177+ XDELETE (oprnd_info);
178+ }
179+
180+ VEC_free (slp_oprnd_info, heap, *oprnds_info);
181+}
182+
183+
184+/* Get the defs for the rhs of STMT (collect them in OPRNDS_INFO), check that
185+ they are of a valid type and that they match the defs of the first stmt of
186+ the SLP group (stored in OPRNDS_INFO). */
187
188 static bool
189 vect_get_and_check_slp_defs (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo,
190 slp_tree slp_node, gimple stmt,
191- VEC (gimple, heap) **def_stmts0,
192- VEC (gimple, heap) **def_stmts1,
193- enum vect_def_type *first_stmt_dt0,
194- enum vect_def_type *first_stmt_dt1,
195- tree *first_stmt_def0_type,
196- tree *first_stmt_def1_type,
197- tree *first_stmt_const_oprnd,
198- int ncopies_for_cost,
199- bool *pattern0, bool *pattern1)
200+ int ncopies_for_cost, bool first,
201+ VEC (slp_oprnd_info, heap) **oprnds_info)
202 {
203 tree oprnd;
204 unsigned int i, number_of_oprnds;
205- tree def[2];
206+ tree def, def_op0 = NULL_TREE;
207 gimple def_stmt;
208- enum vect_def_type dt[2] = {vect_unknown_def_type, vect_unknown_def_type};
209- stmt_vec_info stmt_info =
210- vinfo_for_stmt (VEC_index (gimple, SLP_TREE_SCALAR_STMTS (slp_node), 0));
211- enum gimple_rhs_class rhs_class;
212+ enum vect_def_type dt = vect_uninitialized_def;
213+ enum vect_def_type dt_op0 = vect_uninitialized_def;
214+ stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
215+ tree lhs = gimple_get_lhs (stmt);
216 struct loop *loop = NULL;
217 enum tree_code rhs_code;
218 bool different_types = false;
219+ bool pattern = false;
220+ slp_oprnd_info oprnd_info, oprnd0_info, oprnd1_info;
221
222 if (loop_vinfo)
223 loop = LOOP_VINFO_LOOP (loop_vinfo);
224
225- rhs_class = get_gimple_rhs_class (gimple_assign_rhs_code (stmt));
226- number_of_oprnds = gimple_num_ops (stmt) - 1; /* RHS only */
227+ if (is_gimple_call (stmt))
228+ number_of_oprnds = gimple_call_num_args (stmt);
229+ else
230+ number_of_oprnds = gimple_num_ops (stmt) - 1;
231
232 for (i = 0; i < number_of_oprnds; i++)
233 {
234 oprnd = gimple_op (stmt, i + 1);
235+ oprnd_info = VEC_index (slp_oprnd_info, *oprnds_info, i);
236
237- if (!vect_is_simple_use (oprnd, loop_vinfo, bb_vinfo, &def_stmt, &def[i],
238- &dt[i])
239- || (!def_stmt && dt[i] != vect_constant_def))
240+ if (!vect_is_simple_use (oprnd, loop_vinfo, bb_vinfo, &def_stmt, &def,
241+ &dt)
242+ || (!def_stmt && dt != vect_constant_def))
243 {
244 if (vect_print_dump_info (REPORT_SLP))
245 {
246@@ -158,29 +227,24 @@
247 && !STMT_VINFO_RELEVANT (vinfo_for_stmt (def_stmt))
248 && !STMT_VINFO_LIVE_P (vinfo_for_stmt (def_stmt)))
249 {
250- if (!*first_stmt_dt0)
251- *pattern0 = true;
252- else
253- {
254- if (i == 1 && !*first_stmt_dt1)
255- *pattern1 = true;
256- else if ((i == 0 && !*pattern0) || (i == 1 && !*pattern1))
257- {
258- if (vect_print_dump_info (REPORT_DETAILS))
259- {
260- fprintf (vect_dump, "Build SLP failed: some of the stmts"
261- " are in a pattern, and others are not ");
262- print_generic_expr (vect_dump, oprnd, TDF_SLIM);
263- }
264+ pattern = true;
265+ if (!first && !oprnd_info->first_pattern)
266+ {
267+ if (vect_print_dump_info (REPORT_DETAILS))
268+ {
269+ fprintf (vect_dump, "Build SLP failed: some of the stmts"
270+ " are in a pattern, and others are not ");
271+ print_generic_expr (vect_dump, oprnd, TDF_SLIM);
272+ }
273
274- return false;
275- }
276+ return false;
277 }
278
279 def_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt));
280- dt[i] = STMT_VINFO_DEF_TYPE (vinfo_for_stmt (def_stmt));
281+ dt = STMT_VINFO_DEF_TYPE (vinfo_for_stmt (def_stmt));
282
283- if (*dt == vect_unknown_def_type)
284+ if (dt == vect_unknown_def_type
285+ || STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (def_stmt)))
286 {
287 if (vect_print_dump_info (REPORT_DETAILS))
288 fprintf (vect_dump, "Unsupported pattern.");
289@@ -190,11 +254,11 @@
290 switch (gimple_code (def_stmt))
291 {
292 case GIMPLE_PHI:
293- def[i] = gimple_phi_result (def_stmt);
294+ def = gimple_phi_result (def_stmt);
295 break;
296
297 case GIMPLE_ASSIGN:
298- def[i] = gimple_assign_lhs (def_stmt);
299+ def = gimple_assign_lhs (def_stmt);
300 break;
301
302 default:
303@@ -204,117 +268,125 @@
304 }
305 }
306
307- if (!*first_stmt_dt0)
308+ if (first)
309 {
310- /* op0 of the first stmt of the group - store its info. */
311- *first_stmt_dt0 = dt[i];
312- if (def[i])
313- *first_stmt_def0_type = TREE_TYPE (def[i]);
314- else
315- *first_stmt_const_oprnd = oprnd;
316+ oprnd_info->first_dt = dt;
317+ oprnd_info->first_pattern = pattern;
318+ if (def)
319+ {
320+ oprnd_info->first_def_type = TREE_TYPE (def);
321+ oprnd_info->first_const_oprnd = NULL_TREE;
322+ }
323+ else
324+ {
325+ oprnd_info->first_def_type = NULL_TREE;
326+ oprnd_info->first_const_oprnd = oprnd;
327+ }
328
329- /* Analyze costs (for the first stmt of the group only). */
330- if (rhs_class != GIMPLE_SINGLE_RHS)
331- /* Not memory operation (we don't call this functions for loads). */
332- vect_model_simple_cost (stmt_info, ncopies_for_cost, dt, slp_node);
333- else
334- /* Store. */
335- vect_model_store_cost (stmt_info, ncopies_for_cost, false,
336- dt[0], slp_node);
337+ if (i == 0)
338+ {
339+ def_op0 = def;
340+ dt_op0 = dt;
341+ /* Analyze costs (for the first stmt of the group only). */
342+ if (REFERENCE_CLASS_P (lhs))
343+ /* Store. */
344+ vect_model_store_cost (stmt_info, ncopies_for_cost, false,
345+ dt, slp_node);
346+ else
347+ /* Not memory operation (we don't call this function for
348+ loads). */
349+ vect_model_simple_cost (stmt_info, ncopies_for_cost, &dt,
350+ slp_node);
351+ }
352 }
353
354 else
355 {
356- if (!*first_stmt_dt1 && i == 1)
357- {
358- /* op1 of the first stmt of the group - store its info. */
359- *first_stmt_dt1 = dt[i];
360- if (def[i])
361- *first_stmt_def1_type = TREE_TYPE (def[i]);
362- else
363- {
364- /* We assume that the stmt contains only one constant
365- operand. We fail otherwise, to be on the safe side. */
366- if (*first_stmt_const_oprnd)
367- {
368- if (vect_print_dump_info (REPORT_SLP))
369- fprintf (vect_dump, "Build SLP failed: two constant "
370- "oprnds in stmt");
371- return false;
372- }
373- *first_stmt_const_oprnd = oprnd;
374- }
375- }
376- else
377- {
378- /* Not first stmt of the group, check that the def-stmt/s match
379- the def-stmt/s of the first stmt. */
380- if ((i == 0
381- && (*first_stmt_dt0 != dt[i]
382- || (*first_stmt_def0_type && def[0]
383- && !types_compatible_p (*first_stmt_def0_type,
384- TREE_TYPE (def[0])))))
385- || (i == 1
386- && (*first_stmt_dt1 != dt[i]
387- || (*first_stmt_def1_type && def[1]
388- && !types_compatible_p (*first_stmt_def1_type,
389- TREE_TYPE (def[1])))))
390- || (!def[i]
391- && !types_compatible_p (TREE_TYPE (*first_stmt_const_oprnd),
392- TREE_TYPE (oprnd)))
393- || different_types)
394- {
395- if (i != number_of_oprnds - 1)
396- different_types = true;
397+ /* Not first stmt of the group, check that the def-stmt/s match
398+ the def-stmt/s of the first stmt. Allow different definition
399+ types for reduction chains: the first stmt must be a
400+ vect_reduction_def (a phi node), and the rest
401+ vect_internal_def. */
402+ if (((oprnd_info->first_dt != dt
403+ && !(oprnd_info->first_dt == vect_reduction_def
404+ && dt == vect_internal_def))
405+ || (oprnd_info->first_def_type != NULL_TREE
406+ && def
407+ && !types_compatible_p (oprnd_info->first_def_type,
408+ TREE_TYPE (def))))
409+ || (!def
410+ && !types_compatible_p (TREE_TYPE (oprnd_info->first_const_oprnd),
411+ TREE_TYPE (oprnd)))
412+ || different_types)
413+ {
414+ if (number_of_oprnds != 2)
415+ {
416+ if (vect_print_dump_info (REPORT_SLP))
417+ fprintf (vect_dump, "Build SLP failed: different types ");
418+
419+ return false;
420+ }
421+
422+ /* Try to swap operands in case of binary operation. */
423+ if (i == 0)
424+ different_types = true;
425+ else
426+ {
427+ oprnd0_info = VEC_index (slp_oprnd_info, *oprnds_info, 0);
428+ if (is_gimple_assign (stmt)
429+ && (rhs_code = gimple_assign_rhs_code (stmt))
430+ && TREE_CODE_CLASS (rhs_code) == tcc_binary
431+ && commutative_tree_code (rhs_code)
432+ && oprnd0_info->first_dt == dt
433+ && oprnd_info->first_dt == dt_op0
434+ && def_op0 && def
435+ && !(oprnd0_info->first_def_type
436+ && !types_compatible_p (oprnd0_info->first_def_type,
437+ TREE_TYPE (def)))
438+ && !(oprnd_info->first_def_type
439+ && !types_compatible_p (oprnd_info->first_def_type,
440+ TREE_TYPE (def_op0))))
441+ {
442+ if (vect_print_dump_info (REPORT_SLP))
443+ {
444+ fprintf (vect_dump, "Swapping operands of ");
445+ print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
446+ }
447+
448+ swap_tree_operands (stmt, gimple_assign_rhs1_ptr (stmt),
449+ gimple_assign_rhs2_ptr (stmt));
450+ }
451 else
452- {
453- if (is_gimple_assign (stmt)
454- && (rhs_code = gimple_assign_rhs_code (stmt))
455- && TREE_CODE_CLASS (rhs_code) == tcc_binary
456- && commutative_tree_code (rhs_code)
457- && *first_stmt_dt0 == dt[1]
458- && *first_stmt_dt1 == dt[0]
459- && def[0] && def[1]
460- && !(*first_stmt_def0_type
461- && !types_compatible_p (*first_stmt_def0_type,
462- TREE_TYPE (def[1])))
463- && !(*first_stmt_def1_type
464- && !types_compatible_p (*first_stmt_def1_type,
465- TREE_TYPE (def[0]))))
466- {
467- if (vect_print_dump_info (REPORT_SLP))
468- {
469- fprintf (vect_dump, "Swapping operands of ");
470- print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
471- }
472- swap_tree_operands (stmt, gimple_assign_rhs1_ptr (stmt),
473- gimple_assign_rhs2_ptr (stmt));
474- }
475- else
476- {
477- if (vect_print_dump_info (REPORT_SLP))
478- fprintf (vect_dump, "Build SLP failed: different types ");
479-
480- return false;
481- }
482- }
483+ {
484+ if (vect_print_dump_info (REPORT_SLP))
485+ fprintf (vect_dump, "Build SLP failed: different types ");
486+
487+ return false;
488+ }
489 }
490 }
491 }
492
493 /* Check the types of the definitions. */
494- switch (dt[i])
495+ switch (dt)
496 {
497 case vect_constant_def:
498 case vect_external_def:
499+ case vect_reduction_def:
500 break;
501
502 case vect_internal_def:
503- case vect_reduction_def:
504- if ((i == 0 && !different_types) || (i == 1 && different_types))
505- VEC_safe_push (gimple, heap, *def_stmts0, def_stmt);
506+ if (different_types)
507+ {
508+ oprnd0_info = VEC_index (slp_oprnd_info, *oprnds_info, 0);
509+ oprnd1_info = VEC_index (slp_oprnd_info, *oprnds_info, 0);
510+ if (i == 0)
511+ VEC_quick_push (gimple, oprnd1_info->def_stmts, def_stmt);
512+ else
513+ VEC_quick_push (gimple, oprnd0_info->def_stmts, def_stmt);
514+ }
515 else
516- VEC_safe_push (gimple, heap, *def_stmts1, def_stmt);
517+ VEC_quick_push (gimple, oprnd_info->def_stmts, def_stmt);
518 break;
519
520 default:
521@@ -322,7 +394,7 @@
522 if (vect_print_dump_info (REPORT_SLP))
523 {
524 fprintf (vect_dump, "Build SLP failed: illegal type of def ");
525- print_generic_expr (vect_dump, def[i], TDF_SLIM);
526+ print_generic_expr (vect_dump, def, TDF_SLIM);
527 }
528
529 return false;
530@@ -347,15 +419,10 @@
531 VEC (slp_tree, heap) **loads,
532 unsigned int vectorization_factor, bool *loads_permuted)
533 {
534- VEC (gimple, heap) *def_stmts0 = VEC_alloc (gimple, heap, group_size);
535- VEC (gimple, heap) *def_stmts1 = VEC_alloc (gimple, heap, group_size);
536 unsigned int i;
537 VEC (gimple, heap) *stmts = SLP_TREE_SCALAR_STMTS (*node);
538 gimple stmt = VEC_index (gimple, stmts, 0);
539- enum vect_def_type first_stmt_dt0 = vect_uninitialized_def;
540- enum vect_def_type first_stmt_dt1 = vect_uninitialized_def;
541 enum tree_code first_stmt_code = ERROR_MARK, rhs_code = ERROR_MARK;
542- tree first_stmt_def1_type = NULL_TREE, first_stmt_def0_type = NULL_TREE;
543 tree lhs;
544 bool stop_recursion = false, need_same_oprnds = false;
545 tree vectype, scalar_type, first_op1 = NULL_TREE;
546@@ -364,13 +431,21 @@
547 int icode;
548 enum machine_mode optab_op2_mode;
549 enum machine_mode vec_mode;
550- tree first_stmt_const_oprnd = NULL_TREE;
551 struct data_reference *first_dr;
552- bool pattern0 = false, pattern1 = false;
553 HOST_WIDE_INT dummy;
554 bool permutation = false;
555 unsigned int load_place;
556 gimple first_load, prev_first_load = NULL;
557+ VEC (slp_oprnd_info, heap) *oprnds_info;
558+ unsigned int nops;
559+ slp_oprnd_info oprnd_info;
560+
561+ if (is_gimple_call (stmt))
562+ nops = gimple_call_num_args (stmt);
563+ else
564+ nops = gimple_num_ops (stmt) - 1;
565+
566+ oprnds_info = vect_create_oprnd_info (nops, group_size);
567
568 /* For every stmt in NODE find its def stmt/s. */
569 FOR_EACH_VEC_ELT (gimple, stmts, i, stmt)
570@@ -391,6 +466,7 @@
571 print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
572 }
573
574+ vect_free_oprnd_info (&oprnds_info);
575 return false;
576 }
577
578@@ -400,10 +476,11 @@
579 if (vect_print_dump_info (REPORT_SLP))
580 {
581 fprintf (vect_dump,
582- "Build SLP failed: not GIMPLE_ASSIGN nor GIMPLE_CALL");
583+ "Build SLP failed: not GIMPLE_ASSIGN nor GIMPLE_CALL ");
584 print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
585 }
586
587+ vect_free_oprnd_info (&oprnds_info);
588 return false;
589 }
590
591@@ -416,6 +493,8 @@
592 fprintf (vect_dump, "Build SLP failed: unsupported data-type ");
593 print_generic_expr (vect_dump, scalar_type, TDF_SLIM);
594 }
595+
596+ vect_free_oprnd_info (&oprnds_info);
597 return false;
598 }
599
600@@ -462,6 +541,7 @@
601 {
602 if (vect_print_dump_info (REPORT_SLP))
603 fprintf (vect_dump, "Build SLP failed: no optab.");
604+ vect_free_oprnd_info (&oprnds_info);
605 return false;
606 }
607 icode = (int) optab_handler (optab, vec_mode);
608@@ -470,6 +550,7 @@
609 if (vect_print_dump_info (REPORT_SLP))
610 fprintf (vect_dump, "Build SLP failed: "
611 "op not supported by target.");
612+ vect_free_oprnd_info (&oprnds_info);
613 return false;
614 }
615 optab_op2_mode = insn_data[icode].operand[2].mode;
616@@ -506,6 +587,7 @@
617 print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
618 }
619
620+ vect_free_oprnd_info (&oprnds_info);
621 return false;
622 }
623
624@@ -519,6 +601,7 @@
625 print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
626 }
627
628+ vect_free_oprnd_info (&oprnds_info);
629 return false;
630 }
631 }
632@@ -530,15 +613,12 @@
633 {
634 /* Store. */
635 if (!vect_get_and_check_slp_defs (loop_vinfo, bb_vinfo, *node,
636- stmt, &def_stmts0, &def_stmts1,
637- &first_stmt_dt0,
638- &first_stmt_dt1,
639- &first_stmt_def0_type,
640- &first_stmt_def1_type,
641- &first_stmt_const_oprnd,
642- ncopies_for_cost,
643- &pattern0, &pattern1))
644- return false;
645+ stmt, ncopies_for_cost,
646+ (i == 0), &oprnds_info))
647+ {
648+ vect_free_oprnd_info (&oprnds_info);
649+ return false;
650+ }
651 }
652 else
653 {
654@@ -556,6 +636,7 @@
655 print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
656 }
657
658+ vect_free_oprnd_info (&oprnds_info);
659 return false;
660 }
661
662@@ -573,6 +654,7 @@
663 print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
664 }
665
666+ vect_free_oprnd_info (&oprnds_info);
667 return false;
668 }
669
670@@ -593,6 +675,7 @@
671 print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
672 }
673
674+ vect_free_oprnd_info (&oprnds_info);
675 return false;
676 }
677 }
678@@ -612,6 +695,7 @@
679 print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
680 }
681
682+ vect_free_oprnd_info (&oprnds_info);
683 return false;
684 }
685
686@@ -639,7 +723,7 @@
687 {
688 if (TREE_CODE_CLASS (rhs_code) == tcc_reference)
689 {
690- /* Not strided load. */
691+ /* Not strided load. */
692 if (vect_print_dump_info (REPORT_SLP))
693 {
694 fprintf (vect_dump, "Build SLP failed: not strided load ");
695@@ -647,6 +731,7 @@
696 }
697
698 /* FORNOW: Not strided loads are not supported. */
699+ vect_free_oprnd_info (&oprnds_info);
700 return false;
701 }
702
703@@ -661,19 +746,18 @@
704 print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
705 }
706
707+ vect_free_oprnd_info (&oprnds_info);
708 return false;
709 }
710
711 /* Find the def-stmts. */
712 if (!vect_get_and_check_slp_defs (loop_vinfo, bb_vinfo, *node, stmt,
713- &def_stmts0, &def_stmts1,
714- &first_stmt_dt0, &first_stmt_dt1,
715- &first_stmt_def0_type,
716- &first_stmt_def1_type,
717- &first_stmt_const_oprnd,
718- ncopies_for_cost,
719- &pattern0, &pattern1))
720- return false;
721+ ncopies_for_cost, (i == 0),
722+ &oprnds_info))
723+ {
724+ vect_free_oprnd_info (&oprnds_info);
725+ return false;
726+ }
727 }
728 }
729
730@@ -702,46 +786,37 @@
731 *loads_permuted = true;
732 }
733
734+ vect_free_oprnd_info (&oprnds_info);
735 return true;
736 }
737
738 /* Create SLP_TREE nodes for the definition node/s. */
739- if (first_stmt_dt0 == vect_internal_def)
740- {
741- slp_tree left_node = XNEW (struct _slp_tree);
742- SLP_TREE_SCALAR_STMTS (left_node) = def_stmts0;
743- SLP_TREE_VEC_STMTS (left_node) = NULL;
744- SLP_TREE_LEFT (left_node) = NULL;
745- SLP_TREE_RIGHT (left_node) = NULL;
746- SLP_TREE_OUTSIDE_OF_LOOP_COST (left_node) = 0;
747- SLP_TREE_INSIDE_OF_LOOP_COST (left_node) = 0;
748- if (!vect_build_slp_tree (loop_vinfo, bb_vinfo, &left_node, group_size,
749- inside_cost, outside_cost, ncopies_for_cost,
750- max_nunits, load_permutation, loads,
751- vectorization_factor, loads_permuted))
752- return false;
753-
754- SLP_TREE_LEFT (*node) = left_node;
755- }
756-
757- if (first_stmt_dt1 == vect_internal_def)
758- {
759- slp_tree right_node = XNEW (struct _slp_tree);
760- SLP_TREE_SCALAR_STMTS (right_node) = def_stmts1;
761- SLP_TREE_VEC_STMTS (right_node) = NULL;
762- SLP_TREE_LEFT (right_node) = NULL;
763- SLP_TREE_RIGHT (right_node) = NULL;
764- SLP_TREE_OUTSIDE_OF_LOOP_COST (right_node) = 0;
765- SLP_TREE_INSIDE_OF_LOOP_COST (right_node) = 0;
766- if (!vect_build_slp_tree (loop_vinfo, bb_vinfo, &right_node, group_size,
767- inside_cost, outside_cost, ncopies_for_cost,
768- max_nunits, load_permutation, loads,
769- vectorization_factor, loads_permuted))
770- return false;
771-
772- SLP_TREE_RIGHT (*node) = right_node;
773- }
774-
775+ FOR_EACH_VEC_ELT (slp_oprnd_info, oprnds_info, i, oprnd_info)
776+ {
777+ slp_tree child;
778+
779+ if (oprnd_info->first_dt != vect_internal_def)
780+ continue;
781+
782+ child = vect_create_new_slp_node (oprnd_info->def_stmts);
783+ if (!child
784+ || !vect_build_slp_tree (loop_vinfo, bb_vinfo, &child, group_size,
785+ inside_cost, outside_cost, ncopies_for_cost,
786+ max_nunits, load_permutation, loads,
787+ vectorization_factor, loads_permuted))
788+ {
789+ if (child)
790+ oprnd_info->def_stmts = NULL;
791+ vect_free_slp_tree (child);
792+ vect_free_oprnd_info (&oprnds_info);
793+ return false;
794+ }
795+
796+ oprnd_info->def_stmts = NULL;
797+ VEC_quick_push (slp_void_p, SLP_TREE_CHILDREN (*node), child);
798+ }
799+
800+ vect_free_oprnd_info (&oprnds_info);
801 return true;
802 }
803
804@@ -751,6 +826,7 @@
805 {
806 int i;
807 gimple stmt;
808+ slp_void_p child;
809
810 if (!node)
811 return;
812@@ -763,8 +839,8 @@
813 }
814 fprintf (vect_dump, "\n");
815
816- vect_print_slp_tree (SLP_TREE_LEFT (node));
817- vect_print_slp_tree (SLP_TREE_RIGHT (node));
818+ FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
819+ vect_print_slp_tree ((slp_tree) child);
820 }
821
822
823@@ -778,6 +854,7 @@
824 {
825 int i;
826 gimple stmt;
827+ slp_void_p child;
828
829 if (!node)
830 return;
831@@ -786,8 +863,8 @@
832 if (j < 0 || i == j)
833 STMT_SLP_TYPE (vinfo_for_stmt (stmt)) = mark;
834
835- vect_mark_slp_stmts (SLP_TREE_LEFT (node), mark, j);
836- vect_mark_slp_stmts (SLP_TREE_RIGHT (node), mark, j);
837+ FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
838+ vect_mark_slp_stmts ((slp_tree) child, mark, j);
839 }
840
841
842@@ -799,6 +876,7 @@
843 int i;
844 gimple stmt;
845 stmt_vec_info stmt_info;
846+ slp_void_p child;
847
848 if (!node)
849 return;
850@@ -811,8 +889,8 @@
851 STMT_VINFO_RELEVANT (stmt_info) = vect_used_in_scope;
852 }
853
854- vect_mark_slp_stmts_relevant (SLP_TREE_LEFT (node));
855- vect_mark_slp_stmts_relevant (SLP_TREE_RIGHT (node));
856+ FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
857+ vect_mark_slp_stmts_relevant ((slp_tree) child);
858 }
859
860
861@@ -885,12 +963,13 @@
862 gimple stmt;
863 VEC (gimple, heap) *tmp_stmts;
864 unsigned int index, i;
865+ slp_void_p child;
866
867 if (!node)
868 return;
869
870- vect_slp_rearrange_stmts (SLP_TREE_LEFT (node), group_size, permutation);
871- vect_slp_rearrange_stmts (SLP_TREE_RIGHT (node), group_size, permutation);
872+ FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
873+ vect_slp_rearrange_stmts ((slp_tree) child, group_size, permutation);
874
875 gcc_assert (group_size == VEC_length (gimple, SLP_TREE_SCALAR_STMTS (node)));
876 tmp_stmts = VEC_alloc (gimple, heap, group_size);
877@@ -1253,7 +1332,7 @@
878 gimple stmt)
879 {
880 slp_instance new_instance;
881- slp_tree node = XNEW (struct _slp_tree);
882+ slp_tree node;
883 unsigned int group_size = DR_GROUP_SIZE (vinfo_for_stmt (stmt));
884 unsigned int unrolling_factor = 1, nunits;
885 tree vectype, scalar_type = NULL_TREE;
886@@ -1265,6 +1344,7 @@
887 VEC (slp_tree, heap) *loads;
888 struct data_reference *dr = STMT_VINFO_DATA_REF (vinfo_for_stmt (stmt));
889 bool loads_permuted = false;
890+ VEC (gimple, heap) *scalar_stmts;
891
892 if (dr)
893 {
894@@ -1308,39 +1388,26 @@
895 }
896
897 /* Create a node (a root of the SLP tree) for the packed strided stores. */
898- SLP_TREE_SCALAR_STMTS (node) = VEC_alloc (gimple, heap, group_size);
899+ scalar_stmts = VEC_alloc (gimple, heap, group_size);
900 next = stmt;
901 if (dr)
902 {
903 /* Collect the stores and store them in SLP_TREE_SCALAR_STMTS. */
904 while (next)
905 {
906- VEC_safe_push (gimple, heap, SLP_TREE_SCALAR_STMTS (node), next);
907+ VEC_safe_push (gimple, heap, scalar_stmts, next);
908 next = DR_GROUP_NEXT_DR (vinfo_for_stmt (next));
909 }
910 }
911 else
912 {
913 /* Collect reduction statements. */
914- for (i = 0; VEC_iterate (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i,
915- next);
916- i++)
917- {
918- VEC_safe_push (gimple, heap, SLP_TREE_SCALAR_STMTS (node), next);
919- if (vect_print_dump_info (REPORT_DETAILS))
920- {
921- fprintf (vect_dump, "pushing reduction into node: ");
922- print_gimple_stmt (vect_dump, next, 0, TDF_SLIM);
923- }
924- }
925+ VEC (gimple, heap) *reductions = LOOP_VINFO_REDUCTIONS (loop_vinfo);
926+ for (i = 0; VEC_iterate (gimple, reductions, i, next); i++)
927+ VEC_safe_push (gimple, heap, scalar_stmts, next);
928 }
929
930- SLP_TREE_VEC_STMTS (node) = NULL;
931- SLP_TREE_NUMBER_OF_VEC_STMTS (node) = 0;
932- SLP_TREE_LEFT (node) = NULL;
933- SLP_TREE_RIGHT (node) = NULL;
934- SLP_TREE_OUTSIDE_OF_LOOP_COST (node) = 0;
935- SLP_TREE_INSIDE_OF_LOOP_COST (node) = 0;
936+ node = vect_create_new_slp_node (scalar_stmts);
937
938 /* Calculate the number of vector stmts to create based on the unrolling
939 factor (number of vectors is 1 if NUNITS >= GROUP_SIZE, and is
940@@ -1517,6 +1584,7 @@
941 imm_use_iterator imm_iter;
942 gimple use_stmt;
943 stmt_vec_info stmt_vinfo;
944+ slp_void_p child;
945
946 if (!node)
947 return;
948@@ -1534,8 +1602,8 @@
949 == vect_reduction_def))
950 vect_mark_slp_stmts (node, hybrid, i);
951
952- vect_detect_hybrid_slp_stmts (SLP_TREE_LEFT (node));
953- vect_detect_hybrid_slp_stmts (SLP_TREE_RIGHT (node));
954+ FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
955+ vect_detect_hybrid_slp_stmts ((slp_tree) child);
956 }
957
958
959@@ -1625,13 +1693,14 @@
960 bool dummy;
961 int i;
962 gimple stmt;
963+ slp_void_p child;
964
965 if (!node)
966 return true;
967
968- if (!vect_slp_analyze_node_operations (bb_vinfo, SLP_TREE_LEFT (node))
969- || !vect_slp_analyze_node_operations (bb_vinfo, SLP_TREE_RIGHT (node)))
970- return false;
971+ FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
972+ if (!vect_slp_analyze_node_operations (bb_vinfo, (slp_tree) child))
973+ return false;
974
975 FOR_EACH_VEC_ELT (gimple, SLP_TREE_SCALAR_STMTS (node), i, stmt)
976 {
977@@ -2207,88 +2276,102 @@
978 If the scalar definitions are loop invariants or constants, collect them and
979 call vect_get_constant_vectors() to create vector stmts.
980 Otherwise, the def-stmts must be already vectorized and the vectorized stmts
981- must be stored in the LEFT/RIGHT node of SLP_NODE, and we call
982- vect_get_slp_vect_defs() to retrieve them.
983- If VEC_OPRNDS1 is NULL, don't get vector defs for the second operand (from
984- the right node. This is used when the second operand must remain scalar. */
985+ must be stored in the corresponding child of SLP_NODE, and we call
986+ vect_get_slp_vect_defs () to retrieve them. */
987
988 void
989-vect_get_slp_defs (tree op0, tree op1, slp_tree slp_node,
990- VEC (tree,heap) **vec_oprnds0,
991- VEC (tree,heap) **vec_oprnds1, int reduc_index)
992+vect_get_slp_defs (VEC (tree, heap) *ops, slp_tree slp_node,
993+ VEC (slp_void_p, heap) **vec_oprnds, int reduc_index)
994 {
995- gimple first_stmt;
996- enum tree_code code;
997- int number_of_vects;
998+ gimple first_stmt, first_def;
999+ int number_of_vects = 0, i;
1000+ unsigned int child_index = 0;
1001 HOST_WIDE_INT lhs_size_unit, rhs_size_unit;
1002+ slp_tree child = NULL;
1003+ VEC (tree, heap) *vec_defs;
1004+ tree oprnd, def_lhs;
1005+ bool vectorized_defs;
1006
1007 first_stmt = VEC_index (gimple, SLP_TREE_SCALAR_STMTS (slp_node), 0);
1008- /* The number of vector defs is determined by the number of vector statements
1009- in the node from which we get those statements. */
1010- if (SLP_TREE_LEFT (slp_node))
1011- number_of_vects = SLP_TREE_NUMBER_OF_VEC_STMTS (SLP_TREE_LEFT (slp_node));
1012- else
1013- {
1014- number_of_vects = SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);
1015- /* Number of vector stmts was calculated according to LHS in
1016- vect_schedule_slp_instance(), fix it by replacing LHS with RHS, if
1017- necessary. See vect_get_smallest_scalar_type () for details. */
1018- vect_get_smallest_scalar_type (first_stmt, &lhs_size_unit,
1019- &rhs_size_unit);
1020- if (rhs_size_unit != lhs_size_unit)
1021- {
1022- number_of_vects *= rhs_size_unit;
1023- number_of_vects /= lhs_size_unit;
1024- }
1025+ FOR_EACH_VEC_ELT (tree, ops, i, oprnd)
1026+ {
1027+ /* For each operand we check if it has vectorized definitions in a child
1028+ node or we need to create them (for invariants and constants). We
1029+ check if the LHS of the first stmt of the next child matches OPRND.
1030+ If it does, we found the correct child. Otherwise, we call
1031+ vect_get_constant_vectors (), and not advance CHILD_INDEX in order
1032+ to check this child node for the next operand. */
1033+ vectorized_defs = false;
1034+ if (VEC_length (slp_void_p, SLP_TREE_CHILDREN (slp_node)) > child_index)
1035+ {
1036+ child = (slp_tree) VEC_index (slp_void_p,
1037+ SLP_TREE_CHILDREN (slp_node),
1038+ child_index);
1039+ first_def = VEC_index (gimple, SLP_TREE_SCALAR_STMTS (child), 0);
1040+
1041+ /* In the end of a pattern sequence we have a use of the original stmt,
1042+ so we need to compare OPRND with the original def. */
1043+ if (is_pattern_stmt_p (vinfo_for_stmt (first_def))
1044+ && !STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (first_stmt))
1045+ && !is_pattern_stmt_p (vinfo_for_stmt (first_stmt)))
1046+ first_def = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (first_def));
1047+
1048+ if (is_gimple_call (first_def))
1049+ def_lhs = gimple_call_lhs (first_def);
1050+ else
1051+ def_lhs = gimple_assign_lhs (first_def);
1052+
1053+ if (operand_equal_p (oprnd, def_lhs, 0))
1054+ {
1055+ /* The number of vector defs is determined by the number of
1056+ vector statements in the node from which we get those
1057+ statements. */
1058+ number_of_vects = SLP_TREE_NUMBER_OF_VEC_STMTS (child);
1059+ vectorized_defs = true;
1060+ child_index++;
1061+ }
1062+ }
1063+
1064+ if (!vectorized_defs)
1065+ {
1066+ if (i == 0)
1067+ {
1068+ number_of_vects = SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);
1069+ /* Number of vector stmts was calculated according to LHS in
1070+ vect_schedule_slp_instance (), fix it by replacing LHS with
1071+ RHS, if necessary. See vect_get_smallest_scalar_type () for
1072+ details. */
1073+ vect_get_smallest_scalar_type (first_stmt, &lhs_size_unit,
1074+ &rhs_size_unit);
1075+ if (rhs_size_unit != lhs_size_unit)
1076+ {
1077+ number_of_vects *= rhs_size_unit;
1078+ number_of_vects /= lhs_size_unit;
1079+ }
1080+ }
1081+ }
1082+
1083+ /* Allocate memory for vectorized defs. */
1084+ vec_defs = VEC_alloc (tree, heap, number_of_vects);
1085+
1086+ /* For reduction defs we call vect_get_constant_vectors (), since we are
1087+ looking for initial loop invariant values. */
1088+ if (vectorized_defs && reduc_index == -1)
1089+ /* The defs are already vectorized. */
1090+ vect_get_slp_vect_defs (child, &vec_defs);
1091+ else
1092+ /* Build vectors from scalar defs. */
1093+ vect_get_constant_vectors (oprnd, slp_node, &vec_defs, i,
1094+ number_of_vects, reduc_index);
1095+
1096+ VEC_quick_push (slp_void_p, *vec_oprnds, (slp_void_p) vec_defs);
1097+
1098+ /* For reductions, we only need initial values. */
1099+ if (reduc_index != -1)
1100+ return;
1101 }
1102-
1103- /* Allocate memory for vectorized defs. */
1104- *vec_oprnds0 = VEC_alloc (tree, heap, number_of_vects);
1105-
1106- /* SLP_NODE corresponds either to a group of stores or to a group of
1107- unary/binary operations. We don't call this function for loads.
1108- For reduction defs we call vect_get_constant_vectors(), since we are
1109- looking for initial loop invariant values. */
1110- if (SLP_TREE_LEFT (slp_node) && reduc_index == -1)
1111- /* The defs are already vectorized. */
1112- vect_get_slp_vect_defs (SLP_TREE_LEFT (slp_node), vec_oprnds0);
1113- else
1114- /* Build vectors from scalar defs. */
1115- vect_get_constant_vectors (op0, slp_node, vec_oprnds0, 0, number_of_vects,
1116- reduc_index);
1117-
1118- if (STMT_VINFO_DATA_REF (vinfo_for_stmt (first_stmt)))
1119- /* Since we don't call this function with loads, this is a group of
1120- stores. */
1121- return;
1122-
1123- /* For reductions, we only need initial values. */
1124- if (reduc_index != -1)
1125- return;
1126-
1127- code = gimple_assign_rhs_code (first_stmt);
1128- if (get_gimple_rhs_class (code) != GIMPLE_BINARY_RHS || !vec_oprnds1)
1129- return;
1130-
1131- /* The number of vector defs is determined by the number of vector statements
1132- in the node from which we get those statements. */
1133- if (SLP_TREE_RIGHT (slp_node))
1134- number_of_vects = SLP_TREE_NUMBER_OF_VEC_STMTS (SLP_TREE_RIGHT (slp_node));
1135- else
1136- number_of_vects = SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);
1137-
1138- *vec_oprnds1 = VEC_alloc (tree, heap, number_of_vects);
1139-
1140- if (SLP_TREE_RIGHT (slp_node))
1141- /* The defs are already vectorized. */
1142- vect_get_slp_vect_defs (SLP_TREE_RIGHT (slp_node), vec_oprnds1);
1143- else
1144- /* Build vectors from scalar defs. */
1145- vect_get_constant_vectors (op1, slp_node, vec_oprnds1, 1, number_of_vects,
1146- -1);
1147 }
1148
1149-
1150 /* Create NCOPIES permutation statements using the mask MASK_BYTES (by
1151 building a vector of type MASK_TYPE from it) and two input vectors placed in
1152 DR_CHAIN at FIRST_VEC_INDX and SECOND_VEC_INDX for the first copy and
1153@@ -2605,14 +2688,14 @@
1154 tree vectype;
1155 int i;
1156 slp_tree loads_node;
1157+ slp_void_p child;
1158
1159 if (!node)
1160 return false;
1161
1162- vect_schedule_slp_instance (SLP_TREE_LEFT (node), instance,
1163- vectorization_factor);
1164- vect_schedule_slp_instance (SLP_TREE_RIGHT (node), instance,
1165- vectorization_factor);
1166+ FOR_EACH_VEC_ELT (slp_void_p, SLP_TREE_CHILDREN (node), i, child)
1167+ vect_schedule_slp_instance ((slp_tree) child, instance,
1168+ vectorization_factor);
1169
1170 stmt = VEC_index (gimple, SLP_TREE_SCALAR_STMTS (node), 0);
1171 stmt_info = vinfo_for_stmt (stmt);
1172
1173=== modified file 'gcc/tree-vect-stmts.c'
1174--- old/gcc/tree-vect-stmts.c 2011-10-27 11:27:59 +0000
1175+++ new/gcc/tree-vect-stmts.c 2011-11-14 11:38:08 +0000
1176@@ -1419,16 +1419,35 @@
1177 }
1178
1179
1180-/* Get vectorized definitions for OP0 and OP1, or SLP_NODE if it is not
1181- NULL. */
1182+/* Get vectorized definitions for OP0 and OP1.
1183+ REDUC_INDEX is the index of reduction operand in case of reduction,
1184+ and -1 otherwise. */
1185
1186-static void
1187+void
1188 vect_get_vec_defs (tree op0, tree op1, gimple stmt,
1189- VEC(tree,heap) **vec_oprnds0, VEC(tree,heap) **vec_oprnds1,
1190- slp_tree slp_node)
1191+ VEC (tree, heap) **vec_oprnds0,
1192+ VEC (tree, heap) **vec_oprnds1,
1193+ slp_tree slp_node, int reduc_index)
1194 {
1195 if (slp_node)
1196- vect_get_slp_defs (op0, op1, slp_node, vec_oprnds0, vec_oprnds1, -1);
1197+ {
1198+ int nops = (op1 == NULL_TREE) ? 1 : 2;
1199+ VEC (tree, heap) *ops = VEC_alloc (tree, heap, nops);
1200+ VEC (slp_void_p, heap) *vec_defs = VEC_alloc (slp_void_p, heap, nops);
1201+
1202+ VEC_quick_push (tree, ops, op0);
1203+ if (op1)
1204+ VEC_quick_push (tree, ops, op1);
1205+
1206+ vect_get_slp_defs (ops, slp_node, &vec_defs, reduc_index);
1207+
1208+ *vec_oprnds0 = (VEC (tree, heap) *) VEC_index (slp_void_p, vec_defs, 0);
1209+ if (op1)
1210+ *vec_oprnds1 = (VEC (tree, heap) *) VEC_index (slp_void_p, vec_defs, 1);
1211+
1212+ VEC_free (tree, heap, ops);
1213+ VEC_free (slp_void_p, heap, vec_defs);
1214+ }
1215 else
1216 {
1217 tree vec_oprnd;
1218@@ -2016,7 +2035,8 @@
1219 for (j = 0; j < ncopies; j++)
1220 {
1221 if (j == 0)
1222- vect_get_vec_defs (op0, NULL, stmt, &vec_oprnds0, NULL, slp_node);
1223+ vect_get_vec_defs (op0, NULL, stmt, &vec_oprnds0, NULL, slp_node,
1224+ -1);
1225 else
1226 vect_get_vec_defs_for_stmt_copy (dt, &vec_oprnds0, NULL);
1227
1228@@ -2221,7 +2241,7 @@
1229 {
1230 /* Handle uses. */
1231 if (j == 0)
1232- vect_get_vec_defs (op, NULL, stmt, &vec_oprnds, NULL, slp_node);
1233+ vect_get_vec_defs (op, NULL, stmt, &vec_oprnds, NULL, slp_node, -1);
1234 else
1235 vect_get_vec_defs_for_stmt_copy (dt, &vec_oprnds, NULL);
1236
1237@@ -2576,10 +2596,10 @@
1238 operand 1 should be of a vector type (the usual case). */
1239 if (vec_oprnd1)
1240 vect_get_vec_defs (op0, NULL_TREE, stmt, &vec_oprnds0, NULL,
1241- slp_node);
1242+ slp_node, -1);
1243 else
1244 vect_get_vec_defs (op0, op1, stmt, &vec_oprnds0, &vec_oprnds1,
1245- slp_node);
1246+ slp_node, -1);
1247 }
1248 else
1249 vect_get_vec_defs_for_stmt_copy (dt, &vec_oprnds0, &vec_oprnds1);
1250@@ -2887,10 +2907,10 @@
1251 {
1252 if (op_type == binary_op || op_type == ternary_op)
1253 vect_get_vec_defs (op0, op1, stmt, &vec_oprnds0, &vec_oprnds1,
1254- slp_node);
1255+ slp_node, -1);
1256 else
1257 vect_get_vec_defs (op0, NULL_TREE, stmt, &vec_oprnds0, NULL,
1258- slp_node);
1259+ slp_node, -1);
1260 if (op_type == ternary_op)
1261 {
1262 vec_oprnds2 = VEC_alloc (tree, heap, 1);
1263@@ -3202,7 +3222,8 @@
1264 {
1265 /* Handle uses. */
1266 if (slp_node)
1267- vect_get_slp_defs (op0, NULL_TREE, slp_node, &vec_oprnds0, NULL, -1);
1268+ vect_get_vec_defs (op0, NULL_TREE, stmt, &vec_oprnds0, NULL,
1269+ slp_node, -1);
1270 else
1271 {
1272 VEC_free (tree, heap, vec_oprnds0);
1273@@ -3548,12 +3569,12 @@
1274 for (k = 0; k < slp_node->vec_stmts_size - 1; k++)
1275 VEC_quick_push (tree, vec_oprnds1, vec_oprnd1);
1276
1277- vect_get_slp_defs (op0, NULL_TREE, slp_node, &vec_oprnds0, NULL,
1278- -1);
1279+ vect_get_vec_defs (op0, NULL_TREE, stmt, &vec_oprnds0, NULL,
1280+ slp_node, -1);
1281 }
1282 else
1283- vect_get_slp_defs (op0, op1, slp_node, &vec_oprnds0,
1284- &vec_oprnds1, -1);
1285+ vect_get_vec_defs (op0, op1, stmt, &vec_oprnds0,
1286+ &vec_oprnds1, slp_node, -1);
1287 }
1288 else
1289 {
1290@@ -3796,6 +3817,7 @@
1291 vec_num = SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);
1292 first_stmt = VEC_index (gimple, SLP_TREE_SCALAR_STMTS (slp_node), 0);
1293 first_dr = STMT_VINFO_DATA_REF (vinfo_for_stmt (first_stmt));
1294+ op = gimple_assign_rhs1 (first_stmt);
1295 }
1296 else
1297 /* VEC_NUM is the number of vect stmts to be created for this
1298@@ -3878,8 +3900,8 @@
1299 if (slp)
1300 {
1301 /* Get vectorized arguments for SLP_NODE. */
1302- vect_get_slp_defs (NULL_TREE, NULL_TREE, slp_node, &vec_oprnds,
1303- NULL, -1);
1304+ vect_get_vec_defs (op, NULL_TREE, stmt, &vec_oprnds,
1305+ NULL, slp_node, -1);
1306
1307 vec_oprnd = VEC_index (tree, vec_oprnds, 0);
1308 }
1309@@ -5040,7 +5062,7 @@
1310 In basic blocks we only analyze statements that are a part of some SLP
1311 instance, therefore, all the statements are relevant.
1312
1313- Pattern statement need to be analyzed instead of the original statement
1314+ Pattern statement needs to be analyzed instead of the original statement
1315 if the original statement is not relevant. Otherwise, we analyze both
1316 statements. */
1317
1318
1319=== modified file 'gcc/tree-vectorizer.h'
1320--- old/gcc/tree-vectorizer.h 2011-10-23 13:33:07 +0000
1321+++ new/gcc/tree-vectorizer.h 2011-11-14 11:38:08 +0000
1322@@ -73,15 +73,15 @@
1323 /************************************************************************
1324 SLP
1325 ************************************************************************/
1326+typedef void *slp_void_p;
1327+DEF_VEC_P (slp_void_p);
1328+DEF_VEC_ALLOC_P (slp_void_p, heap);
1329
1330-/* A computation tree of an SLP instance. Each node corresponds to a group of
1331+/* A computation tree of an SLP instance. Each node corresponds to a group of
1332 stmts to be packed in a SIMD stmt. */
1333 typedef struct _slp_tree {
1334- /* Only binary and unary operations are supported. LEFT child corresponds to
1335- the first operand and RIGHT child to the second if the operation is
1336- binary. */
1337- struct _slp_tree *left;
1338- struct _slp_tree *right;
1339+ /* Nodes that contain def-stmts of this node statements operands. */
1340+ VEC (slp_void_p, heap) *children;
1341 /* A group of scalar stmts to be vectorized together. */
1342 VEC (gimple, heap) *stmts;
1343 /* Vectorized stmt/s. */
1344@@ -146,14 +146,32 @@
1345 #define SLP_INSTANCE_LOADS(S) (S)->loads
1346 #define SLP_INSTANCE_FIRST_LOAD_STMT(S) (S)->first_load
1347
1348-#define SLP_TREE_LEFT(S) (S)->left
1349-#define SLP_TREE_RIGHT(S) (S)->right
1350+#define SLP_TREE_CHILDREN(S) (S)->children
1351 #define SLP_TREE_SCALAR_STMTS(S) (S)->stmts
1352 #define SLP_TREE_VEC_STMTS(S) (S)->vec_stmts
1353 #define SLP_TREE_NUMBER_OF_VEC_STMTS(S) (S)->vec_stmts_size
1354 #define SLP_TREE_OUTSIDE_OF_LOOP_COST(S) (S)->cost.outside_of_loop
1355 #define SLP_TREE_INSIDE_OF_LOOP_COST(S) (S)->cost.inside_of_loop
1356
1357+/* This structure is used in creation of an SLP tree. Each instance
1358+ corresponds to the same operand in a group of scalar stmts in an SLP
1359+ node. */
1360+typedef struct _slp_oprnd_info
1361+{
1362+ /* Def-stmts for the operands. */
1363+ VEC (gimple, heap) *def_stmts;
1364+ /* Information about the first statement, its vector def-type, type, the
1365+ operand itself in case it's constant, and an indication if it's a pattern
1366+ stmt. */
1367+ enum vect_def_type first_dt;
1368+ tree first_def_type;
1369+ tree first_const_oprnd;
1370+ bool first_pattern;
1371+} *slp_oprnd_info;
1372+
1373+DEF_VEC_P(slp_oprnd_info);
1374+DEF_VEC_ALLOC_P(slp_oprnd_info, heap);
1375+
1376
1377 typedef struct _vect_peel_info
1378 {
1379@@ -819,6 +837,8 @@
1380 unsigned int *, unsigned int *);
1381 extern void vect_get_store_cost (struct data_reference *, int, unsigned int *);
1382 extern bool vect_supportable_shift (enum tree_code, tree);
1383+extern void vect_get_vec_defs (tree, tree, gimple, VEC (tree, heap) **,
1384+ VEC (tree, heap) **, slp_tree, int);
1385
1386 /* In tree-vect-data-refs.c. */
1387 extern bool vect_can_force_dr_alignment_p (const_tree, unsigned int);
1388@@ -885,8 +905,9 @@
1389 extern bool vect_analyze_slp (loop_vec_info, bb_vec_info);
1390 extern void vect_make_slp_decision (loop_vec_info);
1391 extern void vect_detect_hybrid_slp (loop_vec_info);
1392-extern void vect_get_slp_defs (tree, tree, slp_tree, VEC (tree,heap) **,
1393- VEC (tree,heap) **, int);
1394+extern void vect_get_slp_defs (VEC (tree, heap) *, slp_tree,
1395+ VEC (slp_void_p, heap) **, int);
1396+
1397 extern LOC find_bb_location (basic_block);
1398 extern bb_vec_info vect_slp_analyze_bb (basic_block);
1399 extern void vect_slp_transform_bb (basic_block);
1400
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106841.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106841.patch
deleted file mode 100644
index d72446919..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106841.patch
+++ /dev/null
@@ -1,515 +0,0 @@
12011-11-21 Michael Hope <michael.hope@linaro.org>
2
3 Backport from mainline r180131:
4
5 2011-10-18 Julian Brown <julian@codesourcery.com>
6
7 gcc/
8 * config/arm/arm.c (arm_block_move_unaligned_straight)
9 (arm_adjust_block_mem, arm_block_move_unaligned_loop)
10 (arm_movmemqi_unaligned): New.
11 (arm_gen_movmemqi): Support unaligned block copies.
12
13 gcc/testsuite/
14 * lib/target-supports.exp (check_effective_target_arm_unaligned): New.
15 * gcc.target/arm/unaligned-memcpy-1.c: New.
16 * gcc.target/arm/unaligned-memcpy-2.c: New.
17 * gcc.target/arm/unaligned-memcpy-3.c: New.
18 * gcc.target/arm/unaligned-memcpy-4.c: New.
19
20 2011-09-15 James Greenhalgh <james.greenhalgh@arm.com>
21
22 gcc/
23 * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): New builtin macro.
24
25=== modified file 'gcc/config/arm/arm.c'
26--- old/gcc/config/arm/arm.c 2011-10-26 11:38:30 +0000
27+++ new/gcc/config/arm/arm.c 2011-11-21 01:45:54 +0000
28@@ -10803,6 +10803,335 @@
29 return true;
30 }
31
32+/* Copy a block of memory using plain ldr/str/ldrh/strh instructions, to permit
33+ unaligned copies on processors which support unaligned semantics for those
34+ instructions. INTERLEAVE_FACTOR can be used to attempt to hide load latency
35+ (using more registers) by doing e.g. load/load/store/store for a factor of 2.
36+ An interleave factor of 1 (the minimum) will perform no interleaving.
37+ Load/store multiple are used for aligned addresses where possible. */
38+
39+static void
40+arm_block_move_unaligned_straight (rtx dstbase, rtx srcbase,
41+ HOST_WIDE_INT length,
42+ unsigned int interleave_factor)
43+{
44+ rtx *regs = XALLOCAVEC (rtx, interleave_factor);
45+ int *regnos = XALLOCAVEC (int, interleave_factor);
46+ HOST_WIDE_INT block_size_bytes = interleave_factor * UNITS_PER_WORD;
47+ HOST_WIDE_INT i, j;
48+ HOST_WIDE_INT remaining = length, words;
49+ rtx halfword_tmp = NULL, byte_tmp = NULL;
50+ rtx dst, src;
51+ bool src_aligned = MEM_ALIGN (srcbase) >= BITS_PER_WORD;
52+ bool dst_aligned = MEM_ALIGN (dstbase) >= BITS_PER_WORD;
53+ HOST_WIDE_INT srcoffset, dstoffset;
54+ HOST_WIDE_INT src_autoinc, dst_autoinc;
55+ rtx mem, addr;
56+
57+ gcc_assert (1 <= interleave_factor && interleave_factor <= 4);
58+
59+ /* Use hard registers if we have aligned source or destination so we can use
60+ load/store multiple with contiguous registers. */
61+ if (dst_aligned || src_aligned)
62+ for (i = 0; i < interleave_factor; i++)
63+ regs[i] = gen_rtx_REG (SImode, i);
64+ else
65+ for (i = 0; i < interleave_factor; i++)
66+ regs[i] = gen_reg_rtx (SImode);
67+
68+ dst = copy_addr_to_reg (XEXP (dstbase, 0));
69+ src = copy_addr_to_reg (XEXP (srcbase, 0));
70+
71+ srcoffset = dstoffset = 0;
72+
73+ /* Calls to arm_gen_load_multiple and arm_gen_store_multiple update SRC/DST.
74+ For copying the last bytes we want to subtract this offset again. */
75+ src_autoinc = dst_autoinc = 0;
76+
77+ for (i = 0; i < interleave_factor; i++)
78+ regnos[i] = i;
79+
80+ /* Copy BLOCK_SIZE_BYTES chunks. */
81+
82+ for (i = 0; i + block_size_bytes <= length; i += block_size_bytes)
83+ {
84+ /* Load words. */
85+ if (src_aligned && interleave_factor > 1)
86+ {
87+ emit_insn (arm_gen_load_multiple (regnos, interleave_factor, src,
88+ TRUE, srcbase, &srcoffset));
89+ src_autoinc += UNITS_PER_WORD * interleave_factor;
90+ }
91+ else
92+ {
93+ for (j = 0; j < interleave_factor; j++)
94+ {
95+ addr = plus_constant (src, srcoffset + j * UNITS_PER_WORD
96+ - src_autoinc);
97+ mem = adjust_automodify_address (srcbase, SImode, addr,
98+ srcoffset + j * UNITS_PER_WORD);
99+ emit_insn (gen_unaligned_loadsi (regs[j], mem));
100+ }
101+ srcoffset += block_size_bytes;
102+ }
103+
104+ /* Store words. */
105+ if (dst_aligned && interleave_factor > 1)
106+ {
107+ emit_insn (arm_gen_store_multiple (regnos, interleave_factor, dst,
108+ TRUE, dstbase, &dstoffset));
109+ dst_autoinc += UNITS_PER_WORD * interleave_factor;
110+ }
111+ else
112+ {
113+ for (j = 0; j < interleave_factor; j++)
114+ {
115+ addr = plus_constant (dst, dstoffset + j * UNITS_PER_WORD
116+ - dst_autoinc);
117+ mem = adjust_automodify_address (dstbase, SImode, addr,
118+ dstoffset + j * UNITS_PER_WORD);
119+ emit_insn (gen_unaligned_storesi (mem, regs[j]));
120+ }
121+ dstoffset += block_size_bytes;
122+ }
123+
124+ remaining -= block_size_bytes;
125+ }
126+
127+ /* Copy any whole words left (note these aren't interleaved with any
128+ subsequent halfword/byte load/stores in the interests of simplicity). */
129+
130+ words = remaining / UNITS_PER_WORD;
131+
132+ gcc_assert (words < interleave_factor);
133+
134+ if (src_aligned && words > 1)
135+ {
136+ emit_insn (arm_gen_load_multiple (regnos, words, src, TRUE, srcbase,
137+ &srcoffset));
138+ src_autoinc += UNITS_PER_WORD * words;
139+ }
140+ else
141+ {
142+ for (j = 0; j < words; j++)
143+ {
144+ addr = plus_constant (src,
145+ srcoffset + j * UNITS_PER_WORD - src_autoinc);
146+ mem = adjust_automodify_address (srcbase, SImode, addr,
147+ srcoffset + j * UNITS_PER_WORD);
148+ emit_insn (gen_unaligned_loadsi (regs[j], mem));
149+ }
150+ srcoffset += words * UNITS_PER_WORD;
151+ }
152+
153+ if (dst_aligned && words > 1)
154+ {
155+ emit_insn (arm_gen_store_multiple (regnos, words, dst, TRUE, dstbase,
156+ &dstoffset));
157+ dst_autoinc += words * UNITS_PER_WORD;
158+ }
159+ else
160+ {
161+ for (j = 0; j < words; j++)
162+ {
163+ addr = plus_constant (dst,
164+ dstoffset + j * UNITS_PER_WORD - dst_autoinc);
165+ mem = adjust_automodify_address (dstbase, SImode, addr,
166+ dstoffset + j * UNITS_PER_WORD);
167+ emit_insn (gen_unaligned_storesi (mem, regs[j]));
168+ }
169+ dstoffset += words * UNITS_PER_WORD;
170+ }
171+
172+ remaining -= words * UNITS_PER_WORD;
173+
174+ gcc_assert (remaining < 4);
175+
176+ /* Copy a halfword if necessary. */
177+
178+ if (remaining >= 2)
179+ {
180+ halfword_tmp = gen_reg_rtx (SImode);
181+
182+ addr = plus_constant (src, srcoffset - src_autoinc);
183+ mem = adjust_automodify_address (srcbase, HImode, addr, srcoffset);
184+ emit_insn (gen_unaligned_loadhiu (halfword_tmp, mem));
185+
186+ /* Either write out immediately, or delay until we've loaded the last
187+ byte, depending on interleave factor. */
188+ if (interleave_factor == 1)
189+ {
190+ addr = plus_constant (dst, dstoffset - dst_autoinc);
191+ mem = adjust_automodify_address (dstbase, HImode, addr, dstoffset);
192+ emit_insn (gen_unaligned_storehi (mem,
193+ gen_lowpart (HImode, halfword_tmp)));
194+ halfword_tmp = NULL;
195+ dstoffset += 2;
196+ }
197+
198+ remaining -= 2;
199+ srcoffset += 2;
200+ }
201+
202+ gcc_assert (remaining < 2);
203+
204+ /* Copy last byte. */
205+
206+ if ((remaining & 1) != 0)
207+ {
208+ byte_tmp = gen_reg_rtx (SImode);
209+
210+ addr = plus_constant (src, srcoffset - src_autoinc);
211+ mem = adjust_automodify_address (srcbase, QImode, addr, srcoffset);
212+ emit_move_insn (gen_lowpart (QImode, byte_tmp), mem);
213+
214+ if (interleave_factor == 1)
215+ {
216+ addr = plus_constant (dst, dstoffset - dst_autoinc);
217+ mem = adjust_automodify_address (dstbase, QImode, addr, dstoffset);
218+ emit_move_insn (mem, gen_lowpart (QImode, byte_tmp));
219+ byte_tmp = NULL;
220+ dstoffset++;
221+ }
222+
223+ remaining--;
224+ srcoffset++;
225+ }
226+
227+ /* Store last halfword if we haven't done so already. */
228+
229+ if (halfword_tmp)
230+ {
231+ addr = plus_constant (dst, dstoffset - dst_autoinc);
232+ mem = adjust_automodify_address (dstbase, HImode, addr, dstoffset);
233+ emit_insn (gen_unaligned_storehi (mem,
234+ gen_lowpart (HImode, halfword_tmp)));
235+ dstoffset += 2;
236+ }
237+
238+ /* Likewise for last byte. */
239+
240+ if (byte_tmp)
241+ {
242+ addr = plus_constant (dst, dstoffset - dst_autoinc);
243+ mem = adjust_automodify_address (dstbase, QImode, addr, dstoffset);
244+ emit_move_insn (mem, gen_lowpart (QImode, byte_tmp));
245+ dstoffset++;
246+ }
247+
248+ gcc_assert (remaining == 0 && srcoffset == dstoffset);
249+}
250+
251+/* From mips_adjust_block_mem:
252+
253+ Helper function for doing a loop-based block operation on memory
254+ reference MEM. Each iteration of the loop will operate on LENGTH
255+ bytes of MEM.
256+
257+ Create a new base register for use within the loop and point it to
258+ the start of MEM. Create a new memory reference that uses this
259+ register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
260+
261+static void
262+arm_adjust_block_mem (rtx mem, HOST_WIDE_INT length, rtx *loop_reg,
263+ rtx *loop_mem)
264+{
265+ *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
266+
267+ /* Although the new mem does not refer to a known location,
268+ it does keep up to LENGTH bytes of alignment. */
269+ *loop_mem = change_address (mem, BLKmode, *loop_reg);
270+ set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
271+}
272+
273+/* From mips_block_move_loop:
274+
275+ Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
276+ bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
277+ the memory regions do not overlap. */
278+
279+static void
280+arm_block_move_unaligned_loop (rtx dest, rtx src, HOST_WIDE_INT length,
281+ unsigned int interleave_factor,
282+ HOST_WIDE_INT bytes_per_iter)
283+{
284+ rtx label, src_reg, dest_reg, final_src, test;
285+ HOST_WIDE_INT leftover;
286+
287+ leftover = length % bytes_per_iter;
288+ length -= leftover;
289+
290+ /* Create registers and memory references for use within the loop. */
291+ arm_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
292+ arm_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
293+
294+ /* Calculate the value that SRC_REG should have after the last iteration of
295+ the loop. */
296+ final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
297+ 0, 0, OPTAB_WIDEN);
298+
299+ /* Emit the start of the loop. */
300+ label = gen_label_rtx ();
301+ emit_label (label);
302+
303+ /* Emit the loop body. */
304+ arm_block_move_unaligned_straight (dest, src, bytes_per_iter,
305+ interleave_factor);
306+
307+ /* Move on to the next block. */
308+ emit_move_insn (src_reg, plus_constant (src_reg, bytes_per_iter));
309+ emit_move_insn (dest_reg, plus_constant (dest_reg, bytes_per_iter));
310+
311+ /* Emit the loop condition. */
312+ test = gen_rtx_NE (VOIDmode, src_reg, final_src);
313+ emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
314+
315+ /* Mop up any left-over bytes. */
316+ if (leftover)
317+ arm_block_move_unaligned_straight (dest, src, leftover, interleave_factor);
318+}
319+
320+/* Emit a block move when either the source or destination is unaligned (not
321+ aligned to a four-byte boundary). This may need further tuning depending on
322+ core type, optimize_size setting, etc. */
323+
324+static int
325+arm_movmemqi_unaligned (rtx *operands)
326+{
327+ HOST_WIDE_INT length = INTVAL (operands[2]);
328+
329+ if (optimize_size)
330+ {
331+ bool src_aligned = MEM_ALIGN (operands[1]) >= BITS_PER_WORD;
332+ bool dst_aligned = MEM_ALIGN (operands[0]) >= BITS_PER_WORD;
333+ /* Inlined memcpy using ldr/str/ldrh/strh can be quite big: try to limit
334+ size of code if optimizing for size. We'll use ldm/stm if src_aligned
335+ or dst_aligned though: allow more interleaving in those cases since the
336+ resulting code can be smaller. */
337+ unsigned int interleave_factor = (src_aligned || dst_aligned) ? 2 : 1;
338+ HOST_WIDE_INT bytes_per_iter = (src_aligned || dst_aligned) ? 8 : 4;
339+
340+ if (length > 12)
341+ arm_block_move_unaligned_loop (operands[0], operands[1], length,
342+ interleave_factor, bytes_per_iter);
343+ else
344+ arm_block_move_unaligned_straight (operands[0], operands[1], length,
345+ interleave_factor);
346+ }
347+ else
348+ {
349+ /* Note that the loop created by arm_block_move_unaligned_loop may be
350+ subject to loop unrolling, which makes tuning this condition a little
351+ redundant. */
352+ if (length > 32)
353+ arm_block_move_unaligned_loop (operands[0], operands[1], length, 4, 16);
354+ else
355+ arm_block_move_unaligned_straight (operands[0], operands[1], length, 4);
356+ }
357+
358+ return 1;
359+}
360+
361 int
362 arm_gen_movmemqi (rtx *operands)
363 {
364@@ -10815,8 +11144,13 @@
365
366 if (GET_CODE (operands[2]) != CONST_INT
367 || GET_CODE (operands[3]) != CONST_INT
368- || INTVAL (operands[2]) > 64
369- || INTVAL (operands[3]) & 3)
370+ || INTVAL (operands[2]) > 64)
371+ return 0;
372+
373+ if (unaligned_access && (INTVAL (operands[3]) & 3) != 0)
374+ return arm_movmemqi_unaligned (operands);
375+
376+ if (INTVAL (operands[3]) & 3)
377 return 0;
378
379 dstbase = operands[0];
380
381=== modified file 'gcc/config/arm/arm.h'
382--- old/gcc/config/arm/arm.h 2011-10-19 17:01:50 +0000
383+++ new/gcc/config/arm/arm.h 2011-11-21 01:45:54 +0000
384@@ -47,6 +47,8 @@
385 { \
386 if (TARGET_DSP_MULTIPLY) \
387 builtin_define ("__ARM_FEATURE_DSP"); \
388+ if (unaligned_access) \
389+ builtin_define ("__ARM_FEATURE_UNALIGNED"); \
390 /* Define __arm__ even when in thumb mode, for \
391 consistency with armcc. */ \
392 builtin_define ("__arm__"); \
393
394=== added file 'gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c'
395--- old/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c 1970-01-01 00:00:00 +0000
396+++ new/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c 2011-10-19 22:56:19 +0000
397@@ -0,0 +1,19 @@
398+/* { dg-do compile } */
399+/* { dg-require-effective-target arm_unaligned } */
400+/* { dg-options "-O2" } */
401+
402+#include <string.h>
403+
404+void unknown_alignment (char *dest, char *src)
405+{
406+ memcpy (dest, src, 15);
407+}
408+
409+/* We should see three unaligned word loads and store pairs, one unaligned
410+ ldrh/strh pair, and an ldrb/strb pair. Sanity check that. */
411+
412+/* { dg-final { scan-assembler-times "@ unaligned" 8 } } */
413+/* { dg-final { scan-assembler-times "ldrh" 1 } } */
414+/* { dg-final { scan-assembler-times "strh" 1 } } */
415+/* { dg-final { scan-assembler-times "ldrb" 1 } } */
416+/* { dg-final { scan-assembler-times "strb" 1 } } */
417
418=== added file 'gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c'
419--- old/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c 1970-01-01 00:00:00 +0000
420+++ new/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c 2011-10-19 22:56:19 +0000
421@@ -0,0 +1,21 @@
422+/* { dg-do compile } */
423+/* { dg-require-effective-target arm_unaligned } */
424+/* { dg-options "-O2" } */
425+
426+#include <string.h>
427+
428+char dest[16];
429+
430+void aligned_dest (char *src)
431+{
432+ memcpy (dest, src, 15);
433+}
434+
435+/* Expect a multi-word store for the main part of the copy, but subword
436+ loads/stores for the remainder. */
437+
438+/* { dg-final { scan-assembler-times "stmia" 1 } } */
439+/* { dg-final { scan-assembler-times "ldrh" 1 } } */
440+/* { dg-final { scan-assembler-times "strh" 1 } } */
441+/* { dg-final { scan-assembler-times "ldrb" 1 } } */
442+/* { dg-final { scan-assembler-times "strb" 1 } } */
443
444=== added file 'gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c'
445--- old/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c 1970-01-01 00:00:00 +0000
446+++ new/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c 2011-10-19 22:56:19 +0000
447@@ -0,0 +1,21 @@
448+/* { dg-do compile } */
449+/* { dg-require-effective-target arm_unaligned } */
450+/* { dg-options "-O2" } */
451+
452+#include <string.h>
453+
454+char src[16];
455+
456+void aligned_src (char *dest)
457+{
458+ memcpy (dest, src, 15);
459+}
460+
461+/* Expect a multi-word load for the main part of the copy, but subword
462+ loads/stores for the remainder. */
463+
464+/* { dg-final { scan-assembler-times "ldmia" 1 } } */
465+/* { dg-final { scan-assembler-times "ldrh" 1 } } */
466+/* { dg-final { scan-assembler-times "strh" 1 } } */
467+/* { dg-final { scan-assembler-times "ldrb" 1 } } */
468+/* { dg-final { scan-assembler-times "strb" 1 } } */
469
470=== added file 'gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c'
471--- old/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c 1970-01-01 00:00:00 +0000
472+++ new/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c 2011-10-19 22:56:19 +0000
473@@ -0,0 +1,18 @@
474+/* { dg-do compile } */
475+/* { dg-require-effective-target arm_unaligned } */
476+/* { dg-options "-O2" } */
477+
478+#include <string.h>
479+
480+char src[16];
481+char dest[16];
482+
483+void aligned_both (void)
484+{
485+ memcpy (dest, src, 15);
486+}
487+
488+/* We know both src and dest to be aligned: expect multiword loads/stores. */
489+
490+/* { dg-final { scan-assembler-times "ldmia" 1 } } */
491+/* { dg-final { scan-assembler-times "stmia" 1 } } */
492
493=== modified file 'gcc/testsuite/lib/target-supports.exp'
494--- old/gcc/testsuite/lib/target-supports.exp 2011-10-23 13:33:07 +0000
495+++ new/gcc/testsuite/lib/target-supports.exp 2011-11-21 01:45:54 +0000
496@@ -1894,6 +1894,18 @@
497 }]
498 }
499
500+# Return 1 if this is an ARM target that supports unaligned word/halfword
501+# load/store instructions.
502+
503+proc check_effective_target_arm_unaligned { } {
504+ return [check_no_compiler_messages arm_unaligned assembly {
505+ #ifndef __ARM_FEATURE_UNALIGNED
506+ #error no unaligned support
507+ #endif
508+ int i;
509+ }]
510+}
511+
512 # Add the options needed for NEON. We need either -mfloat-abi=softfp
513 # or -mfloat-abi=hard, but if one is already specified by the
514 # multilib, use it. Similarly, if a -mfpu option already enables
515
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106842.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106842.patch
deleted file mode 100644
index 2cf2741ba..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106842.patch
+++ /dev/null
@@ -1,375 +0,0 @@
12011-11-22 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from mainline:
4
5 2011-10-06 Jakub Jelinek <jakub@redhat.com>
6
7 gcc/
8 PR tree-optimization/50596
9 * tree-vectorizer.h (vect_is_simple_cond): New prototype.
10 (NUM_PATTERNS): Change to 6.
11 * tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern): New
12 function.
13 (vect_vect_recog_func_ptrs): Add vect_recog_mixed_size_cond_pattern.
14 (vect_mark_pattern_stmts): Don't create stmt_vinfo for def_stmt
15 if it already has one, and don't set STMT_VINFO_VECTYPE in it
16 if it is already set.
17 * tree-vect-stmts.c (vect_mark_stmts_to_be_vectorized): Handle
18 COND_EXPR in pattern stmts.
19 (vect_is_simple_cond): No longer static.
20
21 gcc/testsuite:
22 PR tree-optimization/50596
23 * gcc.dg/vect/vect-cond-8.c: New test.
24
25 2011-10-07 Jakub Jelinek <jakub@redhat.com>
26
27 gcc/
28 PR tree-optimization/50650
29 * tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern): Don't
30 call vect_is_simple_cond here, instead fail if cond_expr isn't
31 COMPARISON_CLASS_P or if get_vectype_for_scalar_type returns NULL
32 for cond_expr's first operand.
33 * tree-vect-stmts.c (vect_is_simple_cond): Static again.
34 * tree-vectorizer.h (vect_is_simple_cond): Remove prototype.
35
36
37 gcc/
38 * tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern): Reduce
39 it to integral types only.
40
41 gcc/testsuite/
42 * gcc.dg/vect/pr30858.c: Expect the error message twice for targets
43 with multiple vector sizes.
44 * gcc.dg/vect/vect-cond-8.c: Rename to...
45 * gcc.dg/vect/vect-cond-8a.c: ... this and change the type from float
46 to int.
47 * lib/target-supports.exp (check_effective_target_vect_condition):
48 Return true for NEON.
49
50=== modified file 'gcc/testsuite/gcc.dg/vect/pr30858.c'
51Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/pr30858.c
52===================================================================
53--- gcc-4_6-branch.orig/gcc/testsuite/gcc.dg/vect/pr30858.c 2012-01-04 15:33:52.000000000 -0800
54+++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/pr30858.c 2012-03-05 16:23:47.748983031 -0800
55@@ -11,5 +11,6 @@
56 }
57
58 /* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" } } */
59-/* { dg-final { scan-tree-dump-times "Unknown def-use cycle pattern." 1 "vect" } } */
60+/* { dg-final { scan-tree-dump-times "Unknown def-use cycle pattern." 1 "vect" { xfail vect_multiple_sizes } } } */
61+/* { dg-final { scan-tree-dump-times "Unknown def-use cycle pattern." 2 "vect" { target vect_multiple_sizes } } } */
62 /* { dg-final { cleanup-tree-dump "vect" } } */
63Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-cond-8a.c
64===================================================================
65--- /dev/null 1970-01-01 00:00:00.000000000 +0000
66+++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-cond-8a.c 2012-03-05 16:23:47.748983031 -0800
67@@ -0,0 +1,75 @@
68+/* { dg-require-effective-target vect_condition } */
69+
70+#include "tree-vect.h"
71+
72+#define N 1024
73+int a[N], b[N], c[N];
74+char d[N], e[N], f[N];
75+unsigned char k[N];
76+
77+__attribute__((noinline, noclone)) void
78+f1 (void)
79+{
80+ int i;
81+ for (i = 0; i < N; ++i)
82+ k[i] = a[i] < b[i] ? 17 : 0;
83+}
84+
85+__attribute__((noinline, noclone)) void
86+f2 (void)
87+{
88+ int i;
89+ for (i = 0; i < N; ++i)
90+ k[i] = a[i] < b[i] ? 0 : 24;
91+}
92+
93+__attribute__((noinline, noclone)) void
94+f3 (void)
95+{
96+ int i;
97+ for (i = 0; i < N; ++i)
98+ k[i] = a[i] < b[i] ? 51 : 12;
99+}
100+
101+int
102+main ()
103+{
104+ int i;
105+
106+ check_vect ();
107+
108+ for (i = 0; i < N; i++)
109+ {
110+ switch (i % 9)
111+ {
112+ case 0: asm (""); a[i] = - i - 1; b[i] = i + 1; break;
113+ case 1: a[i] = 0; b[i] = 0; break;
114+ case 2: a[i] = i + 1; b[i] = - i - 1; break;
115+ case 3: a[i] = i; b[i] = i + 7; break;
116+ case 4: a[i] = i; b[i] = i; break;
117+ case 5: a[i] = i + 16; b[i] = i + 3; break;
118+ case 6: a[i] = - i - 5; b[i] = - i; break;
119+ case 7: a[i] = - i; b[i] = - i; break;
120+ case 8: a[i] = - i; b[i] = - i - 7; break;
121+ }
122+ d[i] = i;
123+ e[i] = 2 * i;
124+ }
125+ f1 ();
126+ for (i = 0; i < N; i++)
127+ if (k[i] != ((i % 3) == 0 ? 17 : 0))
128+ abort ();
129+ f2 ();
130+ for (i = 0; i < N; i++)
131+ if (k[i] != ((i % 3) == 0 ? 0 : 24))
132+ abort ();
133+ f3 ();
134+ for (i = 0; i < N; i++)
135+ if (k[i] != ((i % 3) == 0 ? 51 : 12))
136+ abort ();
137+
138+ return 0;
139+}
140+
141+/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops" 3 "vect" } } */
142+/* { dg-final { cleanup-tree-dump "vect" } } */
143Index: gcc-4_6-branch/gcc/tree-vect-patterns.c
144===================================================================
145--- gcc-4_6-branch.orig/gcc/tree-vect-patterns.c 2012-03-05 16:23:10.000000000 -0800
146+++ gcc-4_6-branch/gcc/tree-vect-patterns.c 2012-03-05 16:23:47.748983031 -0800
147@@ -50,13 +50,16 @@
148 tree *);
149 static gimple vect_recog_widen_shift_pattern (VEC (gimple, heap) **,
150 tree *, tree *);
151+static gimple vect_recog_mixed_size_cond_pattern (VEC (gimple, heap) **,
152+ tree *, tree *);
153 static vect_recog_func_ptr vect_vect_recog_func_ptrs[NUM_PATTERNS] = {
154 vect_recog_widen_mult_pattern,
155 vect_recog_widen_sum_pattern,
156 vect_recog_dot_prod_pattern,
157 vect_recog_pow_pattern,
158 vect_recog_over_widening_pattern,
159- vect_recog_widen_shift_pattern};
160+ vect_recog_widen_shift_pattern,
161+ vect_recog_mixed_size_cond_pattern};
162
163
164 /* Function widened_name_p
165@@ -1441,6 +1444,118 @@
166 return pattern_stmt;
167 }
168
169+/* Function vect_recog_mixed_size_cond_pattern
170+
171+ Try to find the following pattern:
172+
173+ type x_t, y_t;
174+ TYPE a_T, b_T, c_T;
175+ loop:
176+ S1 a_T = x_t CMP y_t ? b_T : c_T;
177+
178+ where type 'TYPE' is an integral type which has different size
179+ from 'type'. b_T and c_T are constants and if 'TYPE' is wider
180+ than 'type', the constants need to fit into an integer type
181+ with the same width as 'type'.
182+
183+ Input:
184+
185+ * LAST_STMT: A stmt from which the pattern search begins.
186+
187+ Output:
188+
189+ * TYPE_IN: The type of the input arguments to the pattern.
190+
191+ * TYPE_OUT: The type of the output of this pattern.
192+
193+ * Return value: A new stmt that will be used to replace the pattern.
194+ Additionally a def_stmt is added.
195+
196+ a_it = x_t CMP y_t ? b_it : c_it;
197+ a_T = (TYPE) a_it; */
198+
199+static gimple
200+vect_recog_mixed_size_cond_pattern (VEC (gimple, heap) **stmts, tree *type_in,
201+ tree *type_out)
202+{
203+ gimple last_stmt = VEC_index (gimple, *stmts, 0);
204+ tree cond_expr, then_clause, else_clause;
205+ stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt), def_stmt_info;
206+ tree type, vectype, comp_vectype, comp_type, op, tmp;
207+ enum machine_mode cmpmode;
208+ gimple pattern_stmt, def_stmt;
209+ loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
210+
211+ if (!is_gimple_assign (last_stmt)
212+ || gimple_assign_rhs_code (last_stmt) != COND_EXPR
213+ || STMT_VINFO_DEF_TYPE (stmt_vinfo) != vect_internal_def)
214+ return NULL;
215+
216+ op = gimple_assign_rhs1 (last_stmt);
217+ cond_expr = TREE_OPERAND (op, 0);
218+ then_clause = TREE_OPERAND (op, 1);
219+ else_clause = TREE_OPERAND (op, 2);
220+
221+ if (TREE_CODE (then_clause) != INTEGER_CST
222+ || TREE_CODE (else_clause) != INTEGER_CST)
223+ return NULL;
224+
225+ if (!COMPARISON_CLASS_P (cond_expr))
226+ return NULL;
227+
228+ type = gimple_expr_type (last_stmt);
229+ comp_type = TREE_TYPE (TREE_OPERAND (cond_expr, 0));
230+ if (!INTEGRAL_TYPE_P (comp_type)
231+ || !INTEGRAL_TYPE_P (type))
232+ return NULL;
233+
234+ comp_vectype = get_vectype_for_scalar_type (comp_type);
235+ if (comp_vectype == NULL_TREE)
236+ return NULL;
237+
238+ cmpmode = GET_MODE_INNER (TYPE_MODE (comp_vectype));
239+
240+ if (GET_MODE_BITSIZE (TYPE_MODE (type)) == GET_MODE_BITSIZE (cmpmode))
241+ return NULL;
242+
243+ vectype = get_vectype_for_scalar_type (type);
244+ if (vectype == NULL_TREE)
245+ return NULL;
246+
247+ if (types_compatible_p (vectype, comp_vectype))
248+ return NULL;
249+
250+ if (!expand_vec_cond_expr_p (comp_vectype, TYPE_MODE (comp_vectype)))
251+ return NULL;
252+
253+ if (GET_MODE_BITSIZE (TYPE_MODE (type)) > GET_MODE_BITSIZE (cmpmode))
254+ {
255+ if (!int_fits_type_p (then_clause, comp_type)
256+ || !int_fits_type_p (else_clause, comp_type))
257+ return NULL;
258+ }
259+
260+ tmp = build3 (COND_EXPR, comp_type, unshare_expr (cond_expr),
261+ fold_convert (comp_type, then_clause),
262+ fold_convert (comp_type, else_clause));
263+ def_stmt = gimple_build_assign (vect_recog_temp_ssa_var (comp_type, NULL), tmp);
264+
265+ pattern_stmt
266+ = gimple_build_assign_with_ops (NOP_EXPR,
267+ vect_recog_temp_ssa_var (type, NULL),
268+ gimple_assign_lhs (def_stmt), NULL_TREE);
269+
270+ STMT_VINFO_PATTERN_DEF_STMT (stmt_vinfo) = def_stmt;
271+ def_stmt_info = new_stmt_vec_info (def_stmt, loop_vinfo, NULL);
272+ set_vinfo_for_stmt (def_stmt, def_stmt_info);
273+ STMT_VINFO_VECTYPE (def_stmt_info) = comp_vectype;
274+ *type_in = vectype;
275+ *type_out = vectype;
276+
277+ return pattern_stmt;
278+}
279+
280+
281 /* Mark statements that are involved in a pattern. */
282
283 static inline void
284@@ -1468,14 +1583,18 @@
285 if (STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info))
286 {
287 def_stmt = STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info);
288- set_vinfo_for_stmt (def_stmt,
289- new_stmt_vec_info (def_stmt, loop_vinfo, NULL));
290- gimple_set_bb (def_stmt, gimple_bb (orig_stmt));
291 def_stmt_info = vinfo_for_stmt (def_stmt);
292+ if (def_stmt_info == NULL)
293+ {
294+ def_stmt_info = new_stmt_vec_info (def_stmt, loop_vinfo, NULL);
295+ set_vinfo_for_stmt (def_stmt, def_stmt_info);
296+ }
297+ gimple_set_bb (def_stmt, gimple_bb (orig_stmt));
298 STMT_VINFO_RELATED_STMT (def_stmt_info) = orig_stmt;
299 STMT_VINFO_DEF_TYPE (def_stmt_info)
300 = STMT_VINFO_DEF_TYPE (orig_stmt_info);
301- STMT_VINFO_VECTYPE (def_stmt_info) = pattern_vectype;
302+ if (STMT_VINFO_VECTYPE (def_stmt_info) == NULL_TREE)
303+ STMT_VINFO_VECTYPE (def_stmt_info) = pattern_vectype;
304 }
305 }
306
307Index: gcc-4_6-branch/gcc/tree-vect-stmts.c
308===================================================================
309--- gcc-4_6-branch.orig/gcc/tree-vect-stmts.c 2012-03-05 16:23:11.000000000 -0800
310+++ gcc-4_6-branch/gcc/tree-vect-stmts.c 2012-03-05 16:23:47.748983031 -0800
311@@ -655,20 +655,40 @@
312 tree rhs = gimple_assign_rhs1 (stmt);
313 unsigned int op_num;
314 tree op;
315+ enum tree_code rhs_code;
316 switch (get_gimple_rhs_class (gimple_assign_rhs_code (stmt)))
317 {
318 case GIMPLE_SINGLE_RHS:
319- op_num = TREE_OPERAND_LENGTH (gimple_assign_rhs1 (stmt));
320- for (i = 0; i < op_num; i++)
321- {
322- op = TREE_OPERAND (rhs, i);
323- if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
324- &worklist))
325- {
326- VEC_free (gimple, heap, worklist);
327- return false;
328- }
329- }
330+ op = gimple_assign_rhs1 (stmt);
331+ rhs_code = gimple_assign_rhs_code (stmt);
332+ i = 0;
333+ if (rhs_code == COND_EXPR
334+ && COMPARISON_CLASS_P (TREE_OPERAND (op, 0)))
335+ {
336+ op = TREE_OPERAND (op, 0);
337+ if (!process_use (stmt, TREE_OPERAND (op, 0),
338+ loop_vinfo,
339+ live_p, relevant, &worklist)
340+ || !process_use (stmt, TREE_OPERAND (op, 1),
341+ loop_vinfo,
342+ live_p, relevant, &worklist))
343+ {
344+ VEC_free (gimple, heap, worklist);
345+ return false;
346+ }
347+ i = 1;
348+ }
349+ op_num = TREE_OPERAND_LENGTH (gimple_assign_rhs1 (stmt));
350+ for (i; i < op_num; i++)
351+ {
352+ op = TREE_OPERAND (rhs, i);
353+ if (!process_use (stmt, op, loop_vinfo, live_p, relevant,
354+ &worklist))
355+ {
356+ VEC_free (gimple, heap, worklist);
357+ return false;
358+ }
359+ }
360 break;
361
362 case GIMPLE_BINARY_RHS:
363Index: gcc-4_6-branch/gcc/tree-vectorizer.h
364===================================================================
365--- gcc-4_6-branch.orig/gcc/tree-vectorizer.h 2012-03-05 16:23:11.000000000 -0800
366+++ gcc-4_6-branch/gcc/tree-vectorizer.h 2012-03-05 16:23:47.748983031 -0800
367@@ -917,7 +917,7 @@
368 Additional pattern recognition functions can (and will) be added
369 in the future. */
370 typedef gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
371-#define NUM_PATTERNS 6
372+#define NUM_PATTERNS 7
373 void vect_pattern_recog (loop_vec_info);
374
375 /* In tree-vectorizer.c. */
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106843.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106843.patch
deleted file mode 100644
index ea42ad6ee..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106843.patch
+++ /dev/null
@@ -1,805 +0,0 @@
12011-11-22 Ira Rosen <ira.rosen@linaro.org>
2 Backport from mainline:
3
4 2011-11-06 Ira Rosen <ira.rosen@linaro.org>
5
6 gcc/
7 * tree-vectorizer.h (vectorizable_condition): Add argument.
8 * tree-vect-loop.c (vectorizable_reduction): Fail for condition
9 in SLP. Update calls to vectorizable_condition.
10 * tree-vect-stmts.c (vect_is_simple_cond): Add basic block info to
11 the arguments. Pass it to vect_is_simple_use_1.
12 (vectorizable_condition): Add slp_node to the arguments. Support
13 vectorization of basic blocks. Fail for reduction in SLP. Update
14 calls to vect_is_simple_cond and vect_is_simple_use. Support SLP:
15 call vect_get_slp_defs to get vector operands.
16 (vect_analyze_stmt): Update calls to vectorizable_condition.
17 (vect_transform_stmt): Likewise.
18 * tree-vect-slp.c (vect_create_new_slp_node): Handle COND_EXPR.
19 (vect_get_and_check_slp_defs): Handle COND_EXPR. Allow pattern
20 def stmts.
21 (vect_build_slp_tree): Handle COND_EXPR.
22 (vect_analyze_slp_instance): Push pattern statements to root node.
23 (vect_get_constant_vectors): Fix comments. Handle COND_EXPR.
24
25 gcc/testsuite/
26 * gcc.dg/vect/bb-slp-cond-1.c: New test.
27 * gcc.dg/vect/slp-cond-1.c: New test.
28
29=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c'
30--- old/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c 1970-01-01 00:00:00 +0000
31+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c 2011-11-20 08:24:08 +0000
32@@ -0,0 +1,46 @@
33+/* { dg-require-effective-target vect_condition } */
34+
35+#include "tree-vect.h"
36+
37+#define N 128
38+
39+__attribute__((noinline, noclone)) void
40+foo (int *a, int stride)
41+{
42+ int i;
43+
44+ for (i = 0; i < N/stride; i++, a += stride)
45+ {
46+ a[0] = a[0] ? 1 : 5;
47+ a[1] = a[1] ? 2 : 6;
48+ a[2] = a[2] ? 3 : 7;
49+ a[3] = a[3] ? 4 : 8;
50+ }
51+}
52+
53+
54+int a[N];
55+int main ()
56+{
57+ int i;
58+
59+ check_vect ();
60+
61+ for (i = 0; i < N; i++)
62+ a[i] = i;
63+
64+ foo (a, 4);
65+
66+ for (i = 1; i < N; i++)
67+ if (a[i] != i%4 + 1)
68+ abort ();
69+
70+ if (a[0] != 5)
71+ abort ();
72+
73+ return 0;
74+}
75+
76+/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target vect_element_align } } } */
77+/* { dg-final { cleanup-tree-dump "slp" } } */
78+
79
80=== added file 'gcc/testsuite/gcc.dg/vect/slp-cond-1.c'
81--- old/gcc/testsuite/gcc.dg/vect/slp-cond-1.c 1970-01-01 00:00:00 +0000
82+++ new/gcc/testsuite/gcc.dg/vect/slp-cond-1.c 2011-11-20 08:24:08 +0000
83@@ -0,0 +1,126 @@
84+/* { dg-require-effective-target vect_condition } */
85+#include "tree-vect.h"
86+
87+#define N 32
88+int a[N], b[N];
89+int d[N], e[N];
90+int k[N];
91+
92+__attribute__((noinline, noclone)) void
93+f1 (void)
94+{
95+ int i;
96+ for (i = 0; i < N/4; i++)
97+ {
98+ k[4*i] = a[4*i] < b[4*i] ? 17 : 0;
99+ k[4*i+1] = a[4*i+1] < b[4*i+1] ? 17 : 0;
100+ k[4*i+2] = a[4*i+2] < b[4*i+2] ? 17 : 0;
101+ k[4*i+3] = a[4*i+3] < b[4*i+3] ? 17 : 0;
102+ }
103+}
104+
105+__attribute__((noinline, noclone)) void
106+f2 (void)
107+{
108+ int i;
109+ for (i = 0; i < N/2; ++i)
110+ {
111+ k[2*i] = a[2*i] < b[2*i] ? 0 : 24;
112+ k[2*i+1] = a[2*i+1] < b[2*i+1] ? 7 : 4;
113+ }
114+}
115+
116+__attribute__((noinline, noclone)) void
117+f3 (void)
118+{
119+ int i;
120+ for (i = 0; i < N/2; ++i)
121+ {
122+ k[2*i] = a[2*i] < b[2*i] ? 51 : 12;
123+ k[2*i+1] = a[2*i+1] > b[2*i+1] ? 51 : 12;
124+ }
125+}
126+
127+__attribute__((noinline, noclone)) void
128+f4 (void)
129+{
130+ int i;
131+ for (i = 0; i < N/2; ++i)
132+ {
133+ int d0 = d[2*i], e0 = e[2*i];
134+ int d1 = d[2*i+1], e1 = e[2*i+1];
135+ k[2*i] = a[2*i] >= b[2*i] ? d0 : e0;
136+ k[2*i+1] = a[2*i+1] >= b[2*i+1] ? d1 : e1;
137+ }
138+}
139+
140+int
141+main ()
142+{
143+ int i;
144+
145+ check_vect ();
146+
147+ for (i = 0; i < N; i++)
148+ {
149+ switch (i % 9)
150+ {
151+ case 0: asm (""); a[i] = - i - 1; b[i] = i + 1; break;
152+ case 1: a[i] = 0; b[i] = 0; break;
153+ case 2: a[i] = i + 1; b[i] = - i - 1; break;
154+ case 3: a[i] = i; b[i] = i + 7; break;
155+ case 4: a[i] = i; b[i] = i; break;
156+ case 5: a[i] = i + 16; b[i] = i + 3; break;
157+ case 6: a[i] = - i - 5; b[i] = - i; break;
158+ case 7: a[i] = - i; b[i] = - i; break;
159+ case 8: a[i] = - i; b[i] = - i - 7; break;
160+ }
161+ d[i] = i;
162+ e[i] = 2 * i;
163+ }
164+ f1 ();
165+ for (i = 0; i < N; i++)
166+ if (k[i] != ((i % 3) == 0 ? 17 : 0))
167+ abort ();
168+
169+ f2 ();
170+ for (i = 0; i < N; i++)
171+ {
172+ switch (i % 9)
173+ {
174+ case 0:
175+ case 6:
176+ if (k[i] != ((i/9 % 2) == 0 ? 0 : 7))
177+ abort ();
178+ break;
179+ case 1:
180+ case 5:
181+ case 7:
182+ if (k[i] != ((i/9 % 2) == 0 ? 4 : 24))
183+ abort ();
184+ break;
185+ case 2:
186+ case 4:
187+ case 8:
188+ if (k[i] != ((i/9 % 2) == 0 ? 24 : 4))
189+ abort ();
190+ break;
191+ case 3:
192+ if (k[i] != ((i/9 % 2) == 0 ? 7 : 0))
193+ abort ();
194+ break;
195+ }
196+ }
197+
198+ f3 ();
199+
200+ f4 ();
201+ for (i = 0; i < N; i++)
202+ if (k[i] != ((i % 3) == 0 ? e[i] : d[i]))
203+ abort ();
204+
205+ return 0;
206+}
207+
208+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "vect" } } */
209+/* { dg-final { cleanup-tree-dump "vect" } } */
210
211=== modified file 'gcc/tree-vect-loop.c'
212--- old/gcc/tree-vect-loop.c 2011-11-14 11:38:08 +0000
213+++ new/gcc/tree-vect-loop.c 2011-11-20 08:24:08 +0000
214@@ -4087,6 +4087,9 @@
215 gcc_unreachable ();
216 }
217
218+ if (code == COND_EXPR && slp_node)
219+ return false;
220+
221 scalar_dest = gimple_assign_lhs (stmt);
222 scalar_type = TREE_TYPE (scalar_dest);
223 if (!POINTER_TYPE_P (scalar_type) && !INTEGRAL_TYPE_P (scalar_type)
224@@ -4161,7 +4164,7 @@
225
226 if (code == COND_EXPR)
227 {
228- if (!vectorizable_condition (stmt, gsi, NULL, ops[reduc_index], 0))
229+ if (!vectorizable_condition (stmt, gsi, NULL, ops[reduc_index], 0, NULL))
230 {
231 if (vect_print_dump_info (REPORT_DETAILS))
232 fprintf (vect_dump, "unsupported condition in reduction");
233@@ -4433,7 +4436,7 @@
234 gcc_assert (!slp_node);
235 vectorizable_condition (stmt, gsi, vec_stmt,
236 PHI_RESULT (VEC_index (gimple, phis, 0)),
237- reduc_index);
238+ reduc_index, NULL);
239 /* Multiple types are not supported for condition. */
240 break;
241 }
242
243=== modified file 'gcc/tree-vect-slp.c'
244--- old/gcc/tree-vect-slp.c 2011-11-14 11:38:08 +0000
245+++ new/gcc/tree-vect-slp.c 2011-11-21 06:58:40 +0000
246@@ -109,7 +109,11 @@
247 if (is_gimple_call (stmt))
248 nops = gimple_call_num_args (stmt);
249 else if (is_gimple_assign (stmt))
250- nops = gimple_num_ops (stmt) - 1;
251+ {
252+ nops = gimple_num_ops (stmt) - 1;
253+ if (gimple_assign_rhs_code (stmt) == COND_EXPR)
254+ nops = 4;
255+ }
256 else
257 return NULL;
258
259@@ -190,20 +194,51 @@
260 bool different_types = false;
261 bool pattern = false;
262 slp_oprnd_info oprnd_info, oprnd0_info, oprnd1_info;
263+ int op_idx = 1;
264+ tree compare_rhs = NULL_TREE, rhs = NULL_TREE;
265+ int cond_idx = -1;
266
267 if (loop_vinfo)
268 loop = LOOP_VINFO_LOOP (loop_vinfo);
269
270 if (is_gimple_call (stmt))
271 number_of_oprnds = gimple_call_num_args (stmt);
272+ else if (is_gimple_assign (stmt))
273+ {
274+ number_of_oprnds = gimple_num_ops (stmt) - 1;
275+ if (gimple_assign_rhs_code (stmt) == COND_EXPR)
276+ {
277+ number_of_oprnds = 4;
278+ cond_idx = 0;
279+ rhs = gimple_assign_rhs1 (stmt);
280+ }
281+ }
282 else
283- number_of_oprnds = gimple_num_ops (stmt) - 1;
284+ return false;
285
286 for (i = 0; i < number_of_oprnds; i++)
287 {
288- oprnd = gimple_op (stmt, i + 1);
289+ if (compare_rhs)
290+ oprnd = compare_rhs;
291+ else
292+ oprnd = gimple_op (stmt, op_idx++);
293+
294 oprnd_info = VEC_index (slp_oprnd_info, *oprnds_info, i);
295
296+ if (-1 < cond_idx && cond_idx < 4)
297+ {
298+ if (compare_rhs)
299+ compare_rhs = NULL_TREE;
300+ else
301+ oprnd = TREE_OPERAND (rhs, cond_idx++);
302+ }
303+
304+ if (COMPARISON_CLASS_P (oprnd))
305+ {
306+ compare_rhs = TREE_OPERAND (oprnd, 1);
307+ oprnd = TREE_OPERAND (oprnd, 0);
308+ }
309+
310 if (!vect_is_simple_use (oprnd, loop_vinfo, bb_vinfo, &def_stmt, &def,
311 &dt)
312 || (!def_stmt && dt != vect_constant_def))
313@@ -243,8 +278,7 @@
314 def_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt));
315 dt = STMT_VINFO_DEF_TYPE (vinfo_for_stmt (def_stmt));
316
317- if (dt == vect_unknown_def_type
318- || STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (def_stmt)))
319+ if (dt == vect_unknown_def_type)
320 {
321 if (vect_print_dump_info (REPORT_DETAILS))
322 fprintf (vect_dump, "Unsupported pattern.");
323@@ -423,6 +457,7 @@
324 VEC (gimple, heap) *stmts = SLP_TREE_SCALAR_STMTS (*node);
325 gimple stmt = VEC_index (gimple, stmts, 0);
326 enum tree_code first_stmt_code = ERROR_MARK, rhs_code = ERROR_MARK;
327+ enum tree_code first_cond_code = ERROR_MARK;
328 tree lhs;
329 bool stop_recursion = false, need_same_oprnds = false;
330 tree vectype, scalar_type, first_op1 = NULL_TREE;
331@@ -439,11 +474,18 @@
332 VEC (slp_oprnd_info, heap) *oprnds_info;
333 unsigned int nops;
334 slp_oprnd_info oprnd_info;
335+ tree cond;
336
337 if (is_gimple_call (stmt))
338 nops = gimple_call_num_args (stmt);
339+ else if (is_gimple_assign (stmt))
340+ {
341+ nops = gimple_num_ops (stmt) - 1;
342+ if (gimple_assign_rhs_code (stmt) == COND_EXPR)
343+ nops = 4;
344+ }
345 else
346- nops = gimple_num_ops (stmt) - 1;
347+ return false;
348
349 oprnds_info = vect_create_oprnd_info (nops, group_size);
350
351@@ -484,6 +526,22 @@
352 return false;
353 }
354
355+ if (is_gimple_assign (stmt)
356+ && gimple_assign_rhs_code (stmt) == COND_EXPR
357+ && (cond = TREE_OPERAND (gimple_assign_rhs1 (stmt), 0))
358+ && !COMPARISON_CLASS_P (cond))
359+ {
360+ if (vect_print_dump_info (REPORT_SLP))
361+ {
362+ fprintf (vect_dump,
363+ "Build SLP failed: condition is not comparison ");
364+ print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
365+ }
366+
367+ vect_free_oprnd_info (&oprnds_info);
368+ return false;
369+ }
370+
371 scalar_type = vect_get_smallest_scalar_type (stmt, &dummy, &dummy);
372 vectype = get_vectype_for_scalar_type (scalar_type);
373 if (!vectype)
374@@ -737,7 +795,8 @@
375
376 /* Not memory operation. */
377 if (TREE_CODE_CLASS (rhs_code) != tcc_binary
378- && TREE_CODE_CLASS (rhs_code) != tcc_unary)
379+ && TREE_CODE_CLASS (rhs_code) != tcc_unary
380+ && rhs_code != COND_EXPR)
381 {
382 if (vect_print_dump_info (REPORT_SLP))
383 {
384@@ -750,6 +809,26 @@
385 return false;
386 }
387
388+ if (rhs_code == COND_EXPR)
389+ {
390+ tree cond_expr = TREE_OPERAND (gimple_assign_rhs1 (stmt), 0);
391+
392+ if (i == 0)
393+ first_cond_code = TREE_CODE (cond_expr);
394+ else if (first_cond_code != TREE_CODE (cond_expr))
395+ {
396+ if (vect_print_dump_info (REPORT_SLP))
397+ {
398+ fprintf (vect_dump, "Build SLP failed: different"
399+ " operation");
400+ print_gimple_stmt (vect_dump, stmt, 0, TDF_SLIM);
401+ }
402+
403+ vect_free_oprnd_info (&oprnds_info);
404+ return false;
405+ }
406+ }
407+
408 /* Find the def-stmts. */
409 if (!vect_get_and_check_slp_defs (loop_vinfo, bb_vinfo, *node, stmt,
410 ncopies_for_cost, (i == 0),
411@@ -1395,7 +1474,12 @@
412 /* Collect the stores and store them in SLP_TREE_SCALAR_STMTS. */
413 while (next)
414 {
415- VEC_safe_push (gimple, heap, scalar_stmts, next);
416+ if (STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (next))
417+ && STMT_VINFO_RELATED_STMT (vinfo_for_stmt (next)))
418+ VEC_safe_push (gimple, heap, scalar_stmts,
419+ STMT_VINFO_RELATED_STMT (vinfo_for_stmt (next)));
420+ else
421+ VEC_safe_push (gimple, heap, scalar_stmts, next);
422 next = DR_GROUP_NEXT_DR (vinfo_for_stmt (next));
423 }
424 }
425@@ -1404,7 +1488,7 @@
426 /* Collect reduction statements. */
427 VEC (gimple, heap) *reductions = LOOP_VINFO_REDUCTIONS (loop_vinfo);
428 for (i = 0; VEC_iterate (gimple, reductions, i, next); i++)
429- VEC_safe_push (gimple, heap, scalar_stmts, next);
430+ VEC_safe_push (gimple, heap, scalar_stmts, next);
431 }
432
433 node = vect_create_new_slp_node (scalar_stmts);
434@@ -2160,15 +2244,15 @@
435
436 For example, we have two scalar operands, s1 and s2 (e.g., group of
437 strided accesses of size two), while NUNITS is four (i.e., four scalars
438- of this type can be packed in a vector). The output vector will contain
439- two copies of each scalar operand: {s1, s2, s1, s2}. (NUMBER_OF_COPIES
440+ of this type can be packed in a vector). The output vector will contain
441+ two copies of each scalar operand: {s1, s2, s1, s2}. (NUMBER_OF_COPIES
442 will be 2).
443
444 If GROUP_SIZE > NUNITS, the scalars will be split into several vectors
445 containing the operands.
446
447 For example, NUNITS is four as before, and the group size is 8
448- (s1, s2, ..., s8). We will create two vectors {s1, s2, s3, s4} and
449+ (s1, s2, ..., s8). We will create two vectors {s1, s2, s3, s4} and
450 {s5, s6, s7, s8}. */
451
452 number_of_copies = least_common_multiple (nunits, group_size) / group_size;
453@@ -2180,8 +2264,18 @@
454 {
455 if (is_store)
456 op = gimple_assign_rhs1 (stmt);
457- else
458+ else if (gimple_assign_rhs_code (stmt) != COND_EXPR)
459 op = gimple_op (stmt, op_num + 1);
460+ else
461+ {
462+ if (op_num == 0 || op_num == 1)
463+ {
464+ tree cond = TREE_OPERAND (gimple_assign_rhs1 (stmt), 0);
465+ op = TREE_OPERAND (cond, op_num);
466+ }
467+ else
468+ op = TREE_OPERAND (gimple_assign_rhs1 (stmt), op_num - 1);
469+ }
470
471 if (reduc_index != -1)
472 {
473
474=== modified file 'gcc/tree-vect-stmts.c'
475--- old/gcc/tree-vect-stmts.c 2011-11-22 16:52:23 +0000
476+++ new/gcc/tree-vect-stmts.c 2011-11-22 17:10:17 +0000
477@@ -4816,7 +4816,7 @@
478 condition operands are supportable using vec_is_simple_use. */
479
480 static bool
481-vect_is_simple_cond (tree cond, loop_vec_info loop_vinfo)
482+vect_is_simple_cond (tree cond, loop_vec_info loop_vinfo, bb_vec_info bb_vinfo)
483 {
484 tree lhs, rhs;
485 tree def;
486@@ -4831,7 +4831,7 @@
487 if (TREE_CODE (lhs) == SSA_NAME)
488 {
489 gimple lhs_def_stmt = SSA_NAME_DEF_STMT (lhs);
490- if (!vect_is_simple_use (lhs, loop_vinfo, NULL, &lhs_def_stmt, &def,
491+ if (!vect_is_simple_use (lhs, loop_vinfo, bb_vinfo, &lhs_def_stmt, &def,
492 &dt))
493 return false;
494 }
495@@ -4842,7 +4842,7 @@
496 if (TREE_CODE (rhs) == SSA_NAME)
497 {
498 gimple rhs_def_stmt = SSA_NAME_DEF_STMT (rhs);
499- if (!vect_is_simple_use (rhs, loop_vinfo, NULL, &rhs_def_stmt, &def,
500+ if (!vect_is_simple_use (rhs, loop_vinfo, bb_vinfo, &rhs_def_stmt, &def,
501 &dt))
502 return false;
503 }
504@@ -4868,7 +4868,8 @@
505
506 bool
507 vectorizable_condition (gimple stmt, gimple_stmt_iterator *gsi,
508- gimple *vec_stmt, tree reduc_def, int reduc_index)
509+ gimple *vec_stmt, tree reduc_def, int reduc_index,
510+ slp_tree slp_node)
511 {
512 tree scalar_dest = NULL_TREE;
513 tree vec_dest = NULL_TREE;
514@@ -4885,19 +4886,24 @@
515 tree def;
516 enum vect_def_type dt, dts[4];
517 int nunits = TYPE_VECTOR_SUBPARTS (vectype);
518- int ncopies = LOOP_VINFO_VECT_FACTOR (loop_vinfo) / nunits;
519+ int ncopies;
520 enum tree_code code;
521 stmt_vec_info prev_stmt_info = NULL;
522- int j;
523+ int i, j;
524+ bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_info);
525+ VEC (tree, heap) *vec_oprnds0 = NULL, *vec_oprnds1 = NULL;
526+ VEC (tree, heap) *vec_oprnds2 = NULL, *vec_oprnds3 = NULL;
527
528- /* FORNOW: unsupported in basic block SLP. */
529- gcc_assert (loop_vinfo);
530+ if (slp_node || PURE_SLP_STMT (stmt_info))
531+ ncopies = 1;
532+ else
533+ ncopies = LOOP_VINFO_VECT_FACTOR (loop_vinfo) / nunits;
534
535 gcc_assert (ncopies >= 1);
536- if (reduc_index && ncopies > 1)
537+ if (reduc_index && (ncopies > 1 || STMT_SLP_TYPE (stmt_info)))
538 return false; /* FORNOW */
539
540- if (!STMT_VINFO_RELEVANT_P (stmt_info))
541+ if (!STMT_VINFO_RELEVANT_P (stmt_info) && !bb_vinfo)
542 return false;
543
544 if (STMT_VINFO_DEF_TYPE (stmt_info) != vect_internal_def
545@@ -4905,10 +4911,6 @@
546 && reduc_def))
547 return false;
548
549- /* FORNOW: SLP not supported. */
550- if (STMT_SLP_TYPE (stmt_info))
551- return false;
552-
553 /* FORNOW: not yet supported. */
554 if (STMT_VINFO_LIVE_P (stmt_info))
555 {
556@@ -4932,7 +4934,7 @@
557 then_clause = TREE_OPERAND (op, 1);
558 else_clause = TREE_OPERAND (op, 2);
559
560- if (!vect_is_simple_cond (cond_expr, loop_vinfo))
561+ if (!vect_is_simple_cond (cond_expr, loop_vinfo, bb_vinfo))
562 return false;
563
564 /* We do not handle two different vector types for the condition
565@@ -4944,7 +4946,7 @@
566 if (TREE_CODE (then_clause) == SSA_NAME)
567 {
568 gimple then_def_stmt = SSA_NAME_DEF_STMT (then_clause);
569- if (!vect_is_simple_use (then_clause, loop_vinfo, NULL,
570+ if (!vect_is_simple_use (then_clause, loop_vinfo, bb_vinfo,
571 &then_def_stmt, &def, &dt))
572 return false;
573 }
574@@ -4956,7 +4958,7 @@
575 if (TREE_CODE (else_clause) == SSA_NAME)
576 {
577 gimple else_def_stmt = SSA_NAME_DEF_STMT (else_clause);
578- if (!vect_is_simple_use (else_clause, loop_vinfo, NULL,
579+ if (!vect_is_simple_use (else_clause, loop_vinfo, bb_vinfo,
580 &else_def_stmt, &def, &dt))
581 return false;
582 }
583@@ -4974,7 +4976,15 @@
584 return expand_vec_cond_expr_p (TREE_TYPE (op), vec_mode);
585 }
586
587- /* Transform */
588+ /* Transform. */
589+
590+ if (!slp_node)
591+ {
592+ vec_oprnds0 = VEC_alloc (tree, heap, 1);
593+ vec_oprnds1 = VEC_alloc (tree, heap, 1);
594+ vec_oprnds2 = VEC_alloc (tree, heap, 1);
595+ vec_oprnds3 = VEC_alloc (tree, heap, 1);
596+ }
597
598 /* Handle def. */
599 scalar_dest = gimple_assign_lhs (stmt);
600@@ -4983,67 +4993,118 @@
601 /* Handle cond expr. */
602 for (j = 0; j < ncopies; j++)
603 {
604- gimple new_stmt;
605+ gimple new_stmt = NULL;
606 if (j == 0)
607 {
608- gimple gtemp;
609- vec_cond_lhs =
610+ if (slp_node)
611+ {
612+ VEC (tree, heap) *ops = VEC_alloc (tree, heap, 4);
613+ VEC (slp_void_p, heap) *vec_defs;
614+
615+ vec_defs = VEC_alloc (slp_void_p, heap, 4);
616+ VEC_safe_push (tree, heap, ops, TREE_OPERAND (cond_expr, 0));
617+ VEC_safe_push (tree, heap, ops, TREE_OPERAND (cond_expr, 1));
618+ VEC_safe_push (tree, heap, ops, then_clause);
619+ VEC_safe_push (tree, heap, ops, else_clause);
620+ vect_get_slp_defs (ops, slp_node, &vec_defs, -1);
621+ vec_oprnds3 = (VEC (tree, heap) *) VEC_pop (slp_void_p, vec_defs);
622+ vec_oprnds2 = (VEC (tree, heap) *) VEC_pop (slp_void_p, vec_defs);
623+ vec_oprnds1 = (VEC (tree, heap) *) VEC_pop (slp_void_p, vec_defs);
624+ vec_oprnds0 = (VEC (tree, heap) *) VEC_pop (slp_void_p, vec_defs);
625+
626+ VEC_free (tree, heap, ops);
627+ VEC_free (slp_void_p, heap, vec_defs);
628+ }
629+ else
630+ {
631+ gimple gtemp;
632+ vec_cond_lhs =
633 vect_get_vec_def_for_operand (TREE_OPERAND (cond_expr, 0),
634 stmt, NULL);
635- vect_is_simple_use (TREE_OPERAND (cond_expr, 0), loop_vinfo,
636+ vect_is_simple_use (TREE_OPERAND (cond_expr, 0), loop_vinfo,
637 NULL, &gtemp, &def, &dts[0]);
638- vec_cond_rhs =
639- vect_get_vec_def_for_operand (TREE_OPERAND (cond_expr, 1),
640- stmt, NULL);
641- vect_is_simple_use (TREE_OPERAND (cond_expr, 1), loop_vinfo,
642- NULL, &gtemp, &def, &dts[1]);
643- if (reduc_index == 1)
644- vec_then_clause = reduc_def;
645- else
646- {
647- vec_then_clause = vect_get_vec_def_for_operand (then_clause,
648- stmt, NULL);
649- vect_is_simple_use (then_clause, loop_vinfo,
650- NULL, &gtemp, &def, &dts[2]);
651- }
652- if (reduc_index == 2)
653- vec_else_clause = reduc_def;
654- else
655- {
656- vec_else_clause = vect_get_vec_def_for_operand (else_clause,
657- stmt, NULL);
658- vect_is_simple_use (else_clause, loop_vinfo,
659+
660+ vec_cond_rhs =
661+ vect_get_vec_def_for_operand (TREE_OPERAND (cond_expr, 1),
662+ stmt, NULL);
663+ vect_is_simple_use (TREE_OPERAND (cond_expr, 1), loop_vinfo,
664+ NULL, &gtemp, &def, &dts[1]);
665+ if (reduc_index == 1)
666+ vec_then_clause = reduc_def;
667+ else
668+ {
669+ vec_then_clause = vect_get_vec_def_for_operand (then_clause,
670+ stmt, NULL);
671+ vect_is_simple_use (then_clause, loop_vinfo,
672+ NULL, &gtemp, &def, &dts[2]);
673+ }
674+ if (reduc_index == 2)
675+ vec_else_clause = reduc_def;
676+ else
677+ {
678+ vec_else_clause = vect_get_vec_def_for_operand (else_clause,
679+ stmt, NULL);
680+ vect_is_simple_use (else_clause, loop_vinfo,
681 NULL, &gtemp, &def, &dts[3]);
682+ }
683 }
684 }
685 else
686 {
687- vec_cond_lhs = vect_get_vec_def_for_stmt_copy (dts[0], vec_cond_lhs);
688- vec_cond_rhs = vect_get_vec_def_for_stmt_copy (dts[1], vec_cond_rhs);
689+ vec_cond_lhs = vect_get_vec_def_for_stmt_copy (dts[0],
690+ VEC_pop (tree, vec_oprnds0));
691+ vec_cond_rhs = vect_get_vec_def_for_stmt_copy (dts[1],
692+ VEC_pop (tree, vec_oprnds1));
693 vec_then_clause = vect_get_vec_def_for_stmt_copy (dts[2],
694- vec_then_clause);
695+ VEC_pop (tree, vec_oprnds2));
696 vec_else_clause = vect_get_vec_def_for_stmt_copy (dts[3],
697- vec_else_clause);
698+ VEC_pop (tree, vec_oprnds3));
699+ }
700+
701+ if (!slp_node)
702+ {
703+ VEC_quick_push (tree, vec_oprnds0, vec_cond_lhs);
704+ VEC_quick_push (tree, vec_oprnds1, vec_cond_rhs);
705+ VEC_quick_push (tree, vec_oprnds2, vec_then_clause);
706+ VEC_quick_push (tree, vec_oprnds3, vec_else_clause);
707 }
708
709 /* Arguments are ready. Create the new vector stmt. */
710- vec_compare = build2 (TREE_CODE (cond_expr), vectype,
711- vec_cond_lhs, vec_cond_rhs);
712- vec_cond_expr = build3 (VEC_COND_EXPR, vectype,
713- vec_compare, vec_then_clause, vec_else_clause);
714-
715- new_stmt = gimple_build_assign (vec_dest, vec_cond_expr);
716- new_temp = make_ssa_name (vec_dest, new_stmt);
717- gimple_assign_set_lhs (new_stmt, new_temp);
718- vect_finish_stmt_generation (stmt, new_stmt, gsi);
719- if (j == 0)
720- STMT_VINFO_VEC_STMT (stmt_info) = *vec_stmt = new_stmt;
721- else
722- STMT_VINFO_RELATED_STMT (prev_stmt_info) = new_stmt;
723-
724- prev_stmt_info = vinfo_for_stmt (new_stmt);
725+ FOR_EACH_VEC_ELT (tree, vec_oprnds0, i, vec_cond_lhs)
726+ {
727+ vec_cond_rhs = VEC_index (tree, vec_oprnds1, i);
728+ vec_then_clause = VEC_index (tree, vec_oprnds2, i);
729+ vec_else_clause = VEC_index (tree, vec_oprnds3, i);
730+
731+ vec_compare = build2 (TREE_CODE (cond_expr), vectype,
732+ vec_cond_lhs, vec_cond_rhs);
733+ vec_cond_expr = build3 (VEC_COND_EXPR, vectype,
734+ vec_compare, vec_then_clause, vec_else_clause);
735+
736+ new_stmt = gimple_build_assign (vec_dest, vec_cond_expr);
737+ new_temp = make_ssa_name (vec_dest, new_stmt);
738+ gimple_assign_set_lhs (new_stmt, new_temp);
739+ vect_finish_stmt_generation (stmt, new_stmt, gsi);
740+ if (slp_node)
741+ VEC_quick_push (gimple, SLP_TREE_VEC_STMTS (slp_node), new_stmt);
742+ }
743+
744+ if (slp_node)
745+ continue;
746+
747+ if (j == 0)
748+ STMT_VINFO_VEC_STMT (stmt_info) = *vec_stmt = new_stmt;
749+ else
750+ STMT_VINFO_RELATED_STMT (prev_stmt_info) = new_stmt;
751+
752+ prev_stmt_info = vinfo_for_stmt (new_stmt);
753 }
754
755+ VEC_free (tree, heap, vec_oprnds0);
756+ VEC_free (tree, heap, vec_oprnds1);
757+ VEC_free (tree, heap, vec_oprnds2);
758+ VEC_free (tree, heap, vec_oprnds3);
759+
760 return true;
761 }
762
763@@ -5217,7 +5278,7 @@
764 || vectorizable_call (stmt, NULL, NULL)
765 || vectorizable_store (stmt, NULL, NULL, NULL)
766 || vectorizable_reduction (stmt, NULL, NULL, NULL)
767- || vectorizable_condition (stmt, NULL, NULL, NULL, 0));
768+ || vectorizable_condition (stmt, NULL, NULL, NULL, 0, NULL));
769 else
770 {
771 if (bb_vinfo)
772@@ -5227,7 +5288,8 @@
773 || vectorizable_operation (stmt, NULL, NULL, node)
774 || vectorizable_assignment (stmt, NULL, NULL, node)
775 || vectorizable_load (stmt, NULL, NULL, node, NULL)
776- || vectorizable_store (stmt, NULL, NULL, node));
777+ || vectorizable_store (stmt, NULL, NULL, node)
778+ || vectorizable_condition (stmt, NULL, NULL, NULL, 0, node));
779 }
780
781 if (!ok)
782@@ -5343,8 +5405,7 @@
783 break;
784
785 case condition_vec_info_type:
786- gcc_assert (!slp_node);
787- done = vectorizable_condition (stmt, gsi, &vec_stmt, NULL, 0);
788+ done = vectorizable_condition (stmt, gsi, &vec_stmt, NULL, 0, slp_node);
789 gcc_assert (done);
790 break;
791
792
793=== modified file 'gcc/tree-vectorizer.h'
794--- old/gcc/tree-vectorizer.h 2011-11-22 16:52:23 +0000
795+++ new/gcc/tree-vectorizer.h 2011-11-22 17:10:17 +0000
796@@ -832,7 +832,7 @@
797 extern void vect_remove_stores (gimple);
798 extern bool vect_analyze_stmt (gimple, bool *, slp_tree);
799 extern bool vectorizable_condition (gimple, gimple_stmt_iterator *, gimple *,
800- tree, int);
801+ tree, int, slp_tree);
802 extern void vect_get_load_cost (struct data_reference *, int, bool,
803 unsigned int *, unsigned int *);
804 extern void vect_get_store_cost (struct data_reference *, int, unsigned int *);
805
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106844.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106844.patch
deleted file mode 100644
index e501959c7..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106844.patch
+++ /dev/null
@@ -1,495 +0,0 @@
12011-11-27 Ira Rosen <ira.rosen@linaro.org>
2
3 gcc/
4 * tree-vectorizer.h (vect_pattern_recog): Add new argument.
5 * tree-vect-loop.c (vect_analyze_loop_2): Update call to
6 vect_pattern_recog.
7 * tree-vect-patterns.c (widened_name_p): Pass basic block
8 info to vect_is_simple_use.
9 (vect_recog_dot_prod_pattern): Fail for basic blocks.
10 (vect_recog_widen_sum_pattern): Likewise.
11 (vect_handle_widen_op_by_const): Support basic blocks.
12 (vect_operation_fits_smaller_type,
13 vect_recog_over_widening_pattern): Likewise.
14 (vect_recog_mixed_size_cond_pattern): Support basic blocks.
15 Add printing.
16 (vect_mark_pattern_stmts): Update calls to new_stmt_vec_info.
17 (vect_pattern_recog_1): Check for reduction only in loops.
18 (vect_pattern_recog): Add new argument. Support basic blocks.
19 * tree-vect-stmts.c (vectorizable_conversion): Pass basic block
20 info to vect_is_simple_use_1.
21 * tree-vect-slp.c (vect_get_and_check_slp_defs): Support basic
22 blocks.
23 (vect_slp_analyze_bb_1): Call vect_pattern_recog.
24
25 gcc/testsuite/
26 * gcc.dg/vect/bb-slp-pattern-1.c: New test.
27 * gcc.dg/vect/bb-slp-pattern-2.c: New test.
28
29=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c'
30--- old/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c 1970-01-01 00:00:00 +0000
31+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-1.c 2011-11-23 06:37:10 +0000
32@@ -0,0 +1,55 @@
33+/* { dg-require-effective-target vect_int } */
34+
35+#include <stdarg.h>
36+#include "tree-vect.h"
37+
38+#define N 8
39+
40+unsigned short X[N];
41+unsigned short Y[N];
42+unsigned int result[N];
43+
44+/* unsigned short->unsigned int widening-mult. */
45+__attribute__ ((noinline, noclone)) void
46+foo (void)
47+{
48+ result[0] = (unsigned int)(X[0] * Y[0]);
49+ result[1] = (unsigned int)(X[1] * Y[1]);
50+ result[2] = (unsigned int)(X[2] * Y[2]);
51+ result[3] = (unsigned int)(X[3] * Y[3]);
52+ result[4] = (unsigned int)(X[4] * Y[4]);
53+ result[5] = (unsigned int)(X[5] * Y[5]);
54+ result[6] = (unsigned int)(X[6] * Y[6]);
55+ result[7] = (unsigned int)(X[7] * Y[7]);
56+}
57+
58+int main (void)
59+{
60+ int i, tmp;
61+
62+ check_vect ();
63+
64+ for (i = 0; i < N; i++)
65+ {
66+ X[i] = i;
67+ Y[i] = 64-i;
68+ }
69+
70+ foo ();
71+
72+ for (i = 0; i < N; i++)
73+ {
74+ __asm__ volatile ("");
75+ tmp = X[i] * Y[i];
76+ if (result[i] != tmp)
77+ abort ();
78+ }
79+
80+ return 0;
81+}
82+
83+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "slp" { target { vect_widen_mult_hi_to_si || vect_unpack } } } } */
84+/* { dg-final { scan-tree-dump-times "vect_recog_widen_mult_pattern: detected" 8 "slp" { target vect_widen_mult_hi_to_si_pattern } } } */
85+/* { dg-final { scan-tree-dump-times "pattern recognized" 8 "slp" { target vect_widen_mult_hi_to_si_pattern } } } */
86+/* { dg-final { cleanup-tree-dump "slp" } } */
87+
88
89=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-pattern-2.c'
90--- old/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-2.c 1970-01-01 00:00:00 +0000
91+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-pattern-2.c 2011-11-23 06:37:10 +0000
92@@ -0,0 +1,53 @@
93+/* { dg-require-effective-target vect_condition } */
94+
95+#include "tree-vect.h"
96+
97+#define N 128
98+
99+__attribute__((noinline, noclone)) void
100+foo (short * __restrict__ a, int * __restrict__ b, int stride)
101+{
102+ int i;
103+
104+ for (i = 0; i < N/stride; i++, a += stride, b += stride)
105+ {
106+ a[0] = b[0] ? 1 : 7;
107+ a[1] = b[1] ? 2 : 0;
108+ a[2] = b[2] ? 3 : 0;
109+ a[3] = b[3] ? 4 : 0;
110+ a[4] = b[4] ? 5 : 0;
111+ a[5] = b[5] ? 6 : 0;
112+ a[6] = b[6] ? 7 : 0;
113+ a[7] = b[7] ? 8 : 0;
114+ }
115+}
116+
117+short a[N];
118+int b[N];
119+int main ()
120+{
121+ int i;
122+
123+ check_vect ();
124+
125+ for (i = 0; i < N; i++)
126+ {
127+ a[i] = i;
128+ b[i] = -i;
129+ }
130+
131+ foo (a, b, 8);
132+
133+ for (i = 1; i < N; i++)
134+ if (a[i] != i%8 + 1)
135+ abort ();
136+
137+ if (a[0] != 7)
138+ abort ();
139+
140+ return 0;
141+}
142+
143+/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target { vect_element_align && vect_pack_trunc } } } } */
144+/* { dg-final { cleanup-tree-dump "slp" } } */
145+
146
147=== modified file 'gcc/tree-vect-loop.c'
148--- old/gcc/tree-vect-loop.c 2011-11-20 08:24:08 +0000
149+++ new/gcc/tree-vect-loop.c 2011-11-23 06:47:35 +0000
150@@ -1458,7 +1458,7 @@
151
152 vect_analyze_scalar_cycles (loop_vinfo);
153
154- vect_pattern_recog (loop_vinfo);
155+ vect_pattern_recog (loop_vinfo, NULL);
156
157 /* Data-flow analysis to detect stmts that do not need to be vectorized. */
158
159
160=== modified file 'gcc/tree-vect-patterns.c'
161--- old/gcc/tree-vect-patterns.c 2011-11-20 09:11:09 +0000
162+++ new/gcc/tree-vect-patterns.c 2011-11-23 07:49:33 +0000
163@@ -83,11 +83,13 @@
164 tree oprnd0;
165 enum vect_def_type dt;
166 tree def;
167+ bb_vec_info bb_vinfo;
168
169 stmt_vinfo = vinfo_for_stmt (use_stmt);
170 loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
171+ bb_vinfo = STMT_VINFO_BB_VINFO (stmt_vinfo);
172
173- if (!vect_is_simple_use (name, loop_vinfo, NULL, def_stmt, &def, &dt))
174+ if (!vect_is_simple_use (name, loop_vinfo, bb_vinfo, def_stmt, &def, &dt))
175 return false;
176
177 if (dt != vect_internal_def
178@@ -111,7 +113,7 @@
179 || (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 2)))
180 return false;
181
182- if (!vect_is_simple_use (oprnd0, loop_vinfo, NULL, &dummy_gimple, &dummy,
183+ if (!vect_is_simple_use (oprnd0, loop_vinfo, bb_vinfo, &dummy_gimple, &dummy,
184 &dt))
185 return false;
186
187@@ -188,9 +190,14 @@
188 gimple pattern_stmt;
189 tree prod_type;
190 loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
191- struct loop *loop = LOOP_VINFO_LOOP (loop_info);
192+ struct loop *loop;
193 tree var, rhs;
194
195+ if (!loop_info)
196+ return NULL;
197+
198+ loop = LOOP_VINFO_LOOP (loop_info);
199+
200 if (!is_gimple_assign (last_stmt))
201 return NULL;
202
203@@ -358,8 +365,16 @@
204 {
205 tree new_type, new_oprnd, tmp;
206 gimple new_stmt;
207- loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
208- struct loop *loop = LOOP_VINFO_LOOP (loop_info);
209+ loop_vec_info loop_vinfo;
210+ struct loop *loop = NULL;
211+ bb_vec_info bb_vinfo;
212+ stmt_vec_info stmt_vinfo;
213+
214+ stmt_vinfo = vinfo_for_stmt (stmt);
215+ loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
216+ bb_vinfo = STMT_VINFO_BB_VINFO (stmt_vinfo);
217+ if (loop_vinfo)
218+ loop = LOOP_VINFO_LOOP (loop_vinfo);
219
220 if (code != MULT_EXPR && code != LSHIFT_EXPR)
221 return false;
222@@ -377,7 +392,9 @@
223
224 if (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 4)
225 || !gimple_bb (def_stmt)
226- || !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
227+ || (loop && !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt)))
228+ || (!loop && gimple_bb (def_stmt) != BB_VINFO_BB (bb_vinfo)
229+ && gimple_code (def_stmt) != GIMPLE_PHI)
230 || !vinfo_for_stmt (def_stmt))
231 return false;
232
233@@ -774,9 +791,14 @@
234 tree type, half_type;
235 gimple pattern_stmt;
236 loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
237- struct loop *loop = LOOP_VINFO_LOOP (loop_info);
238+ struct loop *loop;
239 tree var;
240
241+ if (!loop_info)
242+ return NULL;
243+
244+ loop = LOOP_VINFO_LOOP (loop_info);
245+
246 if (!is_gimple_assign (last_stmt))
247 return NULL;
248
249@@ -877,7 +899,11 @@
250 gimple def_stmt, new_stmt;
251 bool first = false;
252 loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
253- struct loop *loop = LOOP_VINFO_LOOP (loop_info);
254+ bb_vec_info bb_info = STMT_VINFO_BB_VINFO (vinfo_for_stmt (stmt));
255+ struct loop *loop = NULL;
256+
257+ if (loop_info)
258+ loop = LOOP_VINFO_LOOP (loop_info);
259
260 *new_def_stmt = NULL;
261
262@@ -909,7 +935,9 @@
263 first = true;
264 if (!widened_name_p (oprnd, stmt, &half_type, &def_stmt, false)
265 || !gimple_bb (def_stmt)
266- || !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
267+ || (loop && !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt)))
268+ || (!loop && gimple_bb (def_stmt) != BB_VINFO_BB (bb_info)
269+ && gimple_code (def_stmt) != GIMPLE_PHI)
270 || !vinfo_for_stmt (def_stmt))
271 return false;
272 }
273@@ -1087,7 +1115,16 @@
274 int nuses = 0;
275 tree var = NULL_TREE, new_type = NULL_TREE, tmp, new_oprnd;
276 bool first;
277- struct loop *loop = (gimple_bb (stmt))->loop_father;
278+ loop_vec_info loop_vinfo;
279+ struct loop *loop = NULL;
280+ bb_vec_info bb_vinfo;
281+ stmt_vec_info stmt_vinfo;
282+
283+ stmt_vinfo = vinfo_for_stmt (stmt);
284+ loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
285+ bb_vinfo = STMT_VINFO_BB_VINFO (stmt_vinfo);
286+ if (loop_vinfo)
287+ loop = LOOP_VINFO_LOOP (loop_vinfo);
288
289 first = true;
290 while (1)
291@@ -1120,7 +1157,8 @@
292
293 if (nuses != 1 || !is_gimple_assign (use_stmt)
294 || !gimple_bb (use_stmt)
295- || !flow_bb_inside_loop_p (loop, gimple_bb (use_stmt)))
296+ || (loop && !flow_bb_inside_loop_p (loop, gimple_bb (use_stmt)))
297+ || (!loop && gimple_bb (use_stmt) != BB_VINFO_BB (bb_vinfo)))
298 return NULL;
299
300 /* Create pattern statement for STMT. */
301@@ -1485,6 +1523,7 @@
302 enum machine_mode cmpmode;
303 gimple pattern_stmt, def_stmt;
304 loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
305+ bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_vinfo);
306
307 if (!is_gimple_assign (last_stmt)
308 || gimple_assign_rhs_code (last_stmt) != COND_EXPR
309@@ -1538,7 +1577,8 @@
310 tmp = build3 (COND_EXPR, comp_type, unshare_expr (cond_expr),
311 fold_convert (comp_type, then_clause),
312 fold_convert (comp_type, else_clause));
313- def_stmt = gimple_build_assign (vect_recog_temp_ssa_var (comp_type, NULL), tmp);
314+ def_stmt = gimple_build_assign (vect_recog_temp_ssa_var (comp_type, NULL),
315+ tmp);
316
317 pattern_stmt
318 = gimple_build_assign_with_ops (NOP_EXPR,
319@@ -1546,12 +1586,15 @@
320 gimple_assign_lhs (def_stmt), NULL_TREE);
321
322 STMT_VINFO_PATTERN_DEF_STMT (stmt_vinfo) = def_stmt;
323- def_stmt_info = new_stmt_vec_info (def_stmt, loop_vinfo, NULL);
324+ def_stmt_info = new_stmt_vec_info (def_stmt, loop_vinfo, bb_vinfo);
325 set_vinfo_for_stmt (def_stmt, def_stmt_info);
326 STMT_VINFO_VECTYPE (def_stmt_info) = comp_vectype;
327 *type_in = vectype;
328 *type_out = vectype;
329
330+ if (vect_print_dump_info (REPORT_DETAILS))
331+ fprintf (vect_dump, "vect_recog_mixed_size_cond_pattern: detected: ");
332+
333 return pattern_stmt;
334 }
335
336@@ -1565,10 +1608,11 @@
337 stmt_vec_info pattern_stmt_info, def_stmt_info;
338 stmt_vec_info orig_stmt_info = vinfo_for_stmt (orig_stmt);
339 loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (orig_stmt_info);
340+ bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (orig_stmt_info);
341 gimple def_stmt;
342
343 set_vinfo_for_stmt (pattern_stmt,
344- new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
345+ new_stmt_vec_info (pattern_stmt, loop_vinfo, bb_vinfo));
346 gimple_set_bb (pattern_stmt, gimple_bb (orig_stmt));
347 pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
348
349@@ -1586,7 +1630,7 @@
350 def_stmt_info = vinfo_for_stmt (def_stmt);
351 if (def_stmt_info == NULL)
352 {
353- def_stmt_info = new_stmt_vec_info (def_stmt, loop_vinfo, NULL);
354+ def_stmt_info = new_stmt_vec_info (def_stmt, loop_vinfo, bb_vinfo);
355 set_vinfo_for_stmt (def_stmt, def_stmt_info);
356 }
357 gimple_set_bb (def_stmt, gimple_bb (orig_stmt));
358@@ -1697,9 +1741,10 @@
359
360 /* Patterns cannot be vectorized using SLP, because they change the order of
361 computation. */
362- FOR_EACH_VEC_ELT (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i, next)
363- if (next == stmt)
364- VEC_ordered_remove (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i);
365+ if (loop_vinfo)
366+ FOR_EACH_VEC_ELT (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i, next)
367+ if (next == stmt)
368+ VEC_ordered_remove (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i);
369
370 /* It is possible that additional pattern stmts are created and inserted in
371 STMTS_TO_REPLACE. We create a stmt_info for each of them, and mark the
372@@ -1799,26 +1844,46 @@
373 be recorded in S3. */
374
375 void
376-vect_pattern_recog (loop_vec_info loop_vinfo)
377+vect_pattern_recog (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo)
378 {
379- struct loop *loop = LOOP_VINFO_LOOP (loop_vinfo);
380- basic_block *bbs = LOOP_VINFO_BBS (loop_vinfo);
381- unsigned int nbbs = loop->num_nodes;
382+ struct loop *loop;
383+ basic_block *bbs, bb;
384+ unsigned int nbbs;
385 gimple_stmt_iterator si;
386 unsigned int i, j;
387 gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
388 VEC (gimple, heap) *stmts_to_replace = VEC_alloc (gimple, heap, 1);
389+ gimple stmt;
390
391 if (vect_print_dump_info (REPORT_DETAILS))
392 fprintf (vect_dump, "=== vect_pattern_recog ===");
393
394- /* Scan through the loop stmts, applying the pattern recognition
395+ if (loop_vinfo)
396+ {
397+ loop = LOOP_VINFO_LOOP (loop_vinfo);
398+ bbs = LOOP_VINFO_BBS (loop_vinfo);
399+ nbbs = loop->num_nodes;
400+ }
401+ else
402+ {
403+ bb = BB_VINFO_BB (bb_vinfo);
404+ nbbs = 1;
405+ bbs = XNEW (basic_block);
406+ bbs[0] = bb;
407+ }
408+
409+ /* Scan through the stmts, applying the pattern recognition
410 functions starting at each stmt visited: */
411 for (i = 0; i < nbbs; i++)
412 {
413 basic_block bb = bbs[i];
414 for (si = gsi_start_bb (bb); !gsi_end_p (si); gsi_next (&si))
415 {
416+ if (bb_vinfo && (stmt = gsi_stmt (si))
417+ && vinfo_for_stmt (stmt)
418+ && !STMT_VINFO_VECTORIZABLE (vinfo_for_stmt (stmt)))
419+ continue;
420+
421 /* Scan over all generic vect_recog_xxx_pattern functions. */
422 for (j = 0; j < NUM_PATTERNS; j++)
423 {
424@@ -1830,4 +1895,6 @@
425 }
426
427 VEC_free (gimple, heap, stmts_to_replace);
428+ if (bb_vinfo)
429+ free (bbs);
430 }
431
432=== modified file 'gcc/tree-vect-slp.c'
433--- old/gcc/tree-vect-slp.c 2011-11-21 06:58:40 +0000
434+++ new/gcc/tree-vect-slp.c 2011-11-23 06:47:35 +0000
435@@ -255,12 +255,14 @@
436 /* Check if DEF_STMT is a part of a pattern in LOOP and get the def stmt
437 from the pattern. Check that all the stmts of the node are in the
438 pattern. */
439- if (loop && def_stmt && gimple_bb (def_stmt)
440- && flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
441+ if (def_stmt && gimple_bb (def_stmt)
442+ && ((loop && flow_bb_inside_loop_p (loop, gimple_bb (def_stmt)))
443+ || (!loop && gimple_bb (def_stmt) == BB_VINFO_BB (bb_vinfo)
444+ && gimple_code (def_stmt) != GIMPLE_PHI))
445 && vinfo_for_stmt (def_stmt)
446 && STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (def_stmt))
447- && !STMT_VINFO_RELEVANT (vinfo_for_stmt (def_stmt))
448- && !STMT_VINFO_LIVE_P (vinfo_for_stmt (def_stmt)))
449+ && !STMT_VINFO_RELEVANT (vinfo_for_stmt (def_stmt))
450+ && !STMT_VINFO_LIVE_P (vinfo_for_stmt (def_stmt)))
451 {
452 pattern = true;
453 if (!first && !oprnd_info->first_pattern)
454@@ -1972,6 +1974,8 @@
455 return NULL;
456 }
457
458+ vect_pattern_recog (NULL, bb_vinfo);
459+
460 if (!vect_analyze_data_ref_dependences (NULL, bb_vinfo, &max_vf,
461 &data_dependence_in_bb)
462 || min_vf > max_vf
463
464=== modified file 'gcc/tree-vect-stmts.c'
465--- old/gcc/tree-vect-stmts.c 2011-11-22 17:10:17 +0000
466+++ new/gcc/tree-vect-stmts.c 2011-11-23 06:47:35 +0000
467@@ -3451,11 +3451,11 @@
468 /* For WIDEN_MULT_EXPR, if OP0 is a constant, use the type of
469 OP1. */
470 if (CONSTANT_CLASS_P (op0))
471- ok = vect_is_simple_use_1 (op1, loop_vinfo, NULL,
472+ ok = vect_is_simple_use_1 (op1, loop_vinfo, bb_vinfo,
473 &def_stmt, &def, &dt[1], &vectype_in);
474 else
475- ok = vect_is_simple_use (op1, loop_vinfo, NULL, &def_stmt, &def,
476- &dt[1]);
477+ ok = vect_is_simple_use (op1, loop_vinfo, bb_vinfo, &def_stmt,
478+ &def, &dt[1]);
479
480 if (!ok)
481 {
482
483=== modified file 'gcc/tree-vectorizer.h'
484--- old/gcc/tree-vectorizer.h 2011-11-22 17:10:17 +0000
485+++ new/gcc/tree-vectorizer.h 2011-11-23 06:47:35 +0000
486@@ -918,7 +918,7 @@
487 in the future. */
488 typedef gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
489 #define NUM_PATTERNS 7
490-void vect_pattern_recog (loop_vec_info);
491+void vect_pattern_recog (loop_vec_info, bb_vec_info);
492
493 /* In tree-vectorizer.c. */
494 unsigned vectorize_loops (void);
495
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106845.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106845.patch
deleted file mode 100644
index 17cfd1068..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106845.patch
+++ /dev/null
@@ -1,1818 +0,0 @@
12011-11-28 David Alan Gilbert <david.gilbert@linaro.org>
2
3 Backport from mainline (svn r19983):
4
5 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org>
6
7 gcc/testsuite/
8 * gcc.dg/di-longlong64-sync-1.c: New test.
9 * gcc.dg/di-sync-multithread.c: New test.
10 * gcc.target/arm/di-longlong64-sync-withhelpers.c: New test.
11 * gcc.target/arm/di-longlong64-sync-withldrexd.c: New test.
12 * lib/target-supports.exp: (arm_arch_*_ok): Series of effective-target
13 tests for v5, v6, v6k, and v7-a, and add-options helpers.
14 (check_effective_target_arm_arm_ok): New helper.
15 (check_effective_target_sync_longlong): New helper.
16
172011-11-28 David Alan Gilbert <david.gilbert@linaro.org>
18
19 Backport from mainline (svn r19982):
20
21 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org>
22
23 gcc/
24 * config/arm/linux-atomic-64bit.c: New (based on linux-atomic.c).
25 * config/arm/linux-atomic.c: Change comment to point to 64bit version.
26 (SYNC_LOCK_RELEASE): Instantiate 64bit version.
27 * config/arm/t-linux-eabi: Pull in linux-atomic-64bit.c.
28
292011-11-28 David Alan Gilbert <david.gilbert@linaro.org>
30
31 Backport from mainline (svn r19981):
32
33 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org>
34
35 gcc/
36 * config/arm/arm.c (arm_output_ldrex): Support ldrexd.
37 (arm_output_strex): Support strexd.
38 (arm_output_it): New helper to output it in Thumb2 mode only.
39 (arm_output_sync_loop): Support DI mode. Change comment to
40 not support const_int.
41 (arm_expand_sync): Support DI mode.
42 * config/arm/arm.h (TARGET_HAVE_LDREXBHD): Split into LDREXBH
43 and LDREXD.
44 * config/arm/iterators.md (NARROW): move from sync.md.
45 (QHSD): New iterator for all current ARM integer modes.
46 (SIDI): New iterator for SI and DI modes only.
47 * config/arm/sync.md (sync_predtab): New mode_attr.
48 (sync_compare_and_swapsi): Fold into sync_compare_and_swap<mode>.
49 (sync_lock_test_and_setsi): Fold into sync_lock_test_and_setsi<mode>.
50 (sync_<sync_optab>si): Fold into sync_<sync_optab><mode>.
51 (sync_nandsi): Fold into sync_nand<mode>.
52 (sync_new_<sync_optab>si): Fold into sync_new_<sync_optab><mode>.
53 (sync_new_nandsi): Fold into sync_new_nand<mode>.
54 (sync_old_<sync_optab>si): Fold into sync_old_<sync_optab><mode>.
55 (sync_old_nandsi): Fold into sync_old_nand<mode>.
56 (sync_compare_and_swap<mode>): Support SI & DI.
57 (sync_lock_test_and_set<mode>): Likewise.
58 (sync_<sync_optab><mode>): Likewise.
59 (sync_nand<mode>): Likewise.
60 (sync_new_<sync_optab><mode>): Likewise.
61 (sync_new_nand<mode>): Likewise.
62 (sync_old_<sync_optab><mode>): Likewise.
63 (sync_old_nand<mode>): Likewise.
64 (arm_sync_compare_and_swapsi): Turn into iterator on SI & DI.
65 (arm_sync_lock_test_and_setsi): Likewise.
66 (arm_sync_new_<sync_optab>si): Likewise.
67 (arm_sync_new_nandsi): Likewise.
68 (arm_sync_old_<sync_optab>si): Likewise.
69 (arm_sync_old_nandsi): Likewise.
70 (arm_sync_compare_and_swap<mode> NARROW): use sync_predtab, fix indent.
71 (arm_sync_lock_test_and_setsi<mode> NARROW): Likewise.
72 (arm_sync_new_<sync_optab><mode> NARROW): Likewise.
73 (arm_sync_new_nand<mode> NARROW): Likewise.
74 (arm_sync_old_<sync_optab><mode> NARROW): Likewise.
75 (arm_sync_old_nand<mode> NARROW): Likewise.
76
772011-11-28 David Alan Gilbert <david.gilbert@linaro.org>
78
79 Backport from mainline (svn r19980):
80
81 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org>
82
83 PR target/48126
84
85 gcc/
86 * config/arm/arm.c (arm_output_sync_loop): Move label before barrier.
87
882011-11-28 David Alan Gilbert <david.gilbert@linaro.org>
89
90 Backport from mainline (svn r19979):
91
92 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org>
93
94 gcc/
95 * config/arm/arm.h (TARGET_HAVE_DMB_MCR): MCR Not available in Thumb1.
96
97=== modified file 'gcc/config/arm/arm.c'
98--- old/gcc/config/arm/arm.c 2011-11-21 01:45:54 +0000
99+++ new/gcc/config/arm/arm.c 2011-11-28 15:07:01 +0000
100@@ -24307,12 +24307,26 @@
101 rtx target,
102 rtx memory)
103 {
104- const char *suffix = arm_ldrex_suffix (mode);
105- rtx operands[2];
106+ rtx operands[3];
107
108 operands[0] = target;
109- operands[1] = memory;
110- arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix);
111+ if (mode != DImode)
112+ {
113+ const char *suffix = arm_ldrex_suffix (mode);
114+ operands[1] = memory;
115+ arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix);
116+ }
117+ else
118+ {
119+ /* The restrictions on target registers in ARM mode are that the two
120+ registers are consecutive and the first one is even; Thumb is
121+ actually more flexible, but DI should give us this anyway.
122+ Note that the 1st register always gets the lowest word in memory. */
123+ gcc_assert ((REGNO (target) & 1) == 0);
124+ operands[1] = gen_rtx_REG (SImode, REGNO (target) + 1);
125+ operands[2] = memory;
126+ arm_output_asm_insn (emit, 0, operands, "ldrexd\t%%0, %%1, %%C2");
127+ }
128 }
129
130 /* Emit a strex{b,h,d, } instruction appropriate for the specified
131@@ -24325,14 +24339,41 @@
132 rtx value,
133 rtx memory)
134 {
135- const char *suffix = arm_ldrex_suffix (mode);
136- rtx operands[3];
137+ rtx operands[4];
138
139 operands[0] = result;
140 operands[1] = value;
141- operands[2] = memory;
142- arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2", suffix,
143- cc);
144+ if (mode != DImode)
145+ {
146+ const char *suffix = arm_ldrex_suffix (mode);
147+ operands[2] = memory;
148+ arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2",
149+ suffix, cc);
150+ }
151+ else
152+ {
153+ /* The restrictions on target registers in ARM mode are that the two
154+ registers are consecutive and the first one is even; Thumb is
155+ actually more flexible, but DI should give us this anyway.
156+ Note that the 1st register always gets the lowest word in memory. */
157+ gcc_assert ((REGNO (value) & 1) == 0 || TARGET_THUMB2);
158+ operands[2] = gen_rtx_REG (SImode, REGNO (value) + 1);
159+ operands[3] = memory;
160+ arm_output_asm_insn (emit, 0, operands, "strexd%s\t%%0, %%1, %%2, %%C3",
161+ cc);
162+ }
163+}
164+
165+/* Helper to emit an it instruction in Thumb2 mode only; although the assembler
166+ will ignore it in ARM mode, emitting it will mess up instruction counts we
167+ sometimes keep 'flags' are the extra t's and e's if it's more than one
168+ instruction that is conditional. */
169+static void
170+arm_output_it (emit_f emit, const char *flags, const char *cond)
171+{
172+ rtx operands[1]; /* Don't actually use the operand. */
173+ if (TARGET_THUMB2)
174+ arm_output_asm_insn (emit, 0, operands, "it%s\t%s", flags, cond);
175 }
176
177 /* Helper to emit a two operand instruction. */
178@@ -24374,7 +24415,7 @@
179
180 required_value:
181
182- RTX register or const_int representing the required old_value for
183+ RTX register representing the required old_value for
184 the modify to continue, if NULL no comparsion is performed. */
185 static void
186 arm_output_sync_loop (emit_f emit,
187@@ -24388,7 +24429,13 @@
188 enum attr_sync_op sync_op,
189 int early_barrier_required)
190 {
191- rtx operands[1];
192+ rtx operands[2];
193+ /* We'll use the lo for the normal rtx in the none-DI case
194+ as well as the least-sig word in the DI case. */
195+ rtx old_value_lo, required_value_lo, new_value_lo, t1_lo;
196+ rtx old_value_hi, required_value_hi, new_value_hi, t1_hi;
197+
198+ bool is_di = mode == DImode;
199
200 gcc_assert (t1 != t2);
201
202@@ -24399,82 +24446,142 @@
203
204 arm_output_ldrex (emit, mode, old_value, memory);
205
206+ if (is_di)
207+ {
208+ old_value_lo = gen_lowpart (SImode, old_value);
209+ old_value_hi = gen_highpart (SImode, old_value);
210+ if (required_value)
211+ {
212+ required_value_lo = gen_lowpart (SImode, required_value);
213+ required_value_hi = gen_highpart (SImode, required_value);
214+ }
215+ else
216+ {
217+ /* Silence false potentially unused warning. */
218+ required_value_lo = NULL_RTX;
219+ required_value_hi = NULL_RTX;
220+ }
221+ new_value_lo = gen_lowpart (SImode, new_value);
222+ new_value_hi = gen_highpart (SImode, new_value);
223+ t1_lo = gen_lowpart (SImode, t1);
224+ t1_hi = gen_highpart (SImode, t1);
225+ }
226+ else
227+ {
228+ old_value_lo = old_value;
229+ new_value_lo = new_value;
230+ required_value_lo = required_value;
231+ t1_lo = t1;
232+
233+ /* Silence false potentially unused warning. */
234+ t1_hi = NULL_RTX;
235+ new_value_hi = NULL_RTX;
236+ required_value_hi = NULL_RTX;
237+ old_value_hi = NULL_RTX;
238+ }
239+
240 if (required_value)
241 {
242- rtx operands[2];
243+ operands[0] = old_value_lo;
244+ operands[1] = required_value_lo;
245
246- operands[0] = old_value;
247- operands[1] = required_value;
248 arm_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1");
249+ if (is_di)
250+ {
251+ arm_output_it (emit, "", "eq");
252+ arm_output_op2 (emit, "cmpeq", old_value_hi, required_value_hi);
253+ }
254 arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX);
255 }
256
257 switch (sync_op)
258 {
259 case SYNC_OP_ADD:
260- arm_output_op3 (emit, "add", t1, old_value, new_value);
261+ arm_output_op3 (emit, is_di ? "adds" : "add",
262+ t1_lo, old_value_lo, new_value_lo);
263+ if (is_di)
264+ arm_output_op3 (emit, "adc", t1_hi, old_value_hi, new_value_hi);
265 break;
266
267 case SYNC_OP_SUB:
268- arm_output_op3 (emit, "sub", t1, old_value, new_value);
269+ arm_output_op3 (emit, is_di ? "subs" : "sub",
270+ t1_lo, old_value_lo, new_value_lo);
271+ if (is_di)
272+ arm_output_op3 (emit, "sbc", t1_hi, old_value_hi, new_value_hi);
273 break;
274
275 case SYNC_OP_IOR:
276- arm_output_op3 (emit, "orr", t1, old_value, new_value);
277+ arm_output_op3 (emit, "orr", t1_lo, old_value_lo, new_value_lo);
278+ if (is_di)
279+ arm_output_op3 (emit, "orr", t1_hi, old_value_hi, new_value_hi);
280 break;
281
282 case SYNC_OP_XOR:
283- arm_output_op3 (emit, "eor", t1, old_value, new_value);
284+ arm_output_op3 (emit, "eor", t1_lo, old_value_lo, new_value_lo);
285+ if (is_di)
286+ arm_output_op3 (emit, "eor", t1_hi, old_value_hi, new_value_hi);
287 break;
288
289 case SYNC_OP_AND:
290- arm_output_op3 (emit,"and", t1, old_value, new_value);
291+ arm_output_op3 (emit,"and", t1_lo, old_value_lo, new_value_lo);
292+ if (is_di)
293+ arm_output_op3 (emit, "and", t1_hi, old_value_hi, new_value_hi);
294 break;
295
296 case SYNC_OP_NAND:
297- arm_output_op3 (emit, "and", t1, old_value, new_value);
298- arm_output_op2 (emit, "mvn", t1, t1);
299+ arm_output_op3 (emit, "and", t1_lo, old_value_lo, new_value_lo);
300+ if (is_di)
301+ arm_output_op3 (emit, "and", t1_hi, old_value_hi, new_value_hi);
302+ arm_output_op2 (emit, "mvn", t1_lo, t1_lo);
303+ if (is_di)
304+ arm_output_op2 (emit, "mvn", t1_hi, t1_hi);
305 break;
306
307 case SYNC_OP_NONE:
308 t1 = new_value;
309+ t1_lo = new_value_lo;
310+ if (is_di)
311+ t1_hi = new_value_hi;
312 break;
313 }
314
315+ /* Note that the result of strex is a 0/1 flag that's always 1 register. */
316 if (t2)
317 {
318- arm_output_strex (emit, mode, "", t2, t1, memory);
319- operands[0] = t2;
320- arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
321- arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=",
322- LOCAL_LABEL_PREFIX);
323+ arm_output_strex (emit, mode, "", t2, t1, memory);
324+ operands[0] = t2;
325+ arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
326+ arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=",
327+ LOCAL_LABEL_PREFIX);
328 }
329 else
330 {
331 /* Use old_value for the return value because for some operations
332 the old_value can easily be restored. This saves one register. */
333- arm_output_strex (emit, mode, "", old_value, t1, memory);
334- operands[0] = old_value;
335+ arm_output_strex (emit, mode, "", old_value_lo, t1, memory);
336+ operands[0] = old_value_lo;
337 arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0");
338 arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=",
339 LOCAL_LABEL_PREFIX);
340
341+ /* Note that we only used the _lo half of old_value as a temporary
342+ so in DI we don't have to restore the _hi part. */
343 switch (sync_op)
344 {
345 case SYNC_OP_ADD:
346- arm_output_op3 (emit, "sub", old_value, t1, new_value);
347+ arm_output_op3 (emit, "sub", old_value_lo, t1_lo, new_value_lo);
348 break;
349
350 case SYNC_OP_SUB:
351- arm_output_op3 (emit, "add", old_value, t1, new_value);
352+ arm_output_op3 (emit, "add", old_value_lo, t1_lo, new_value_lo);
353 break;
354
355 case SYNC_OP_XOR:
356- arm_output_op3 (emit, "eor", old_value, t1, new_value);
357+ arm_output_op3 (emit, "eor", old_value_lo, t1_lo, new_value_lo);
358 break;
359
360 case SYNC_OP_NONE:
361- arm_output_op2 (emit, "mov", old_value, required_value);
362+ arm_output_op2 (emit, "mov", old_value_lo, required_value_lo);
363 break;
364
365 default:
366@@ -24482,8 +24589,11 @@
367 }
368 }
369
370+ /* Note: label is before barrier so that in cmp failure case we still get
371+ a barrier to stop subsequent loads floating upwards past the ldrex
372+ PR target/48126. */
373+ arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX);
374 arm_process_output_memory_barrier (emit, NULL);
375- arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX);
376 }
377
378 static rtx
379@@ -24577,7 +24687,7 @@
380 target = gen_reg_rtx (mode);
381
382 memory = arm_legitimize_sync_memory (memory);
383- if (mode != SImode)
384+ if (mode != SImode && mode != DImode)
385 {
386 rtx load_temp = gen_reg_rtx (SImode);
387
388
389=== modified file 'gcc/config/arm/arm.h'
390--- old/gcc/config/arm/arm.h 2011-11-21 01:45:54 +0000
391+++ new/gcc/config/arm/arm.h 2011-11-28 15:07:01 +0000
392@@ -300,7 +300,8 @@
393 #define TARGET_HAVE_DMB (arm_arch7)
394
395 /* Nonzero if this chip implements a memory barrier via CP15. */
396-#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
397+#define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
398+ && ! TARGET_THUMB1)
399
400 /* Nonzero if this chip implements a memory barrier instruction. */
401 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
402@@ -308,8 +309,12 @@
403 /* Nonzero if this chip supports ldrex and strex */
404 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
405
406-/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
407-#define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
408+/* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
409+#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
410+
411+/* Nonzero if this chip supports ldrexd and strexd. */
412+#define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \
413+ && arm_arch_notm)
414
415 /* Nonzero if integer division instructions supported. */
416 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
417
418=== modified file 'gcc/config/arm/iterators.md'
419--- old/gcc/config/arm/iterators.md 2011-10-23 13:33:07 +0000
420+++ new/gcc/config/arm/iterators.md 2011-11-28 15:07:01 +0000
421@@ -33,6 +33,15 @@
422 ;; A list of integer modes that are up to one word long
423 (define_mode_iterator QHSI [QI HI SI])
424
425+;; A list of integer modes that are less than a word
426+(define_mode_iterator NARROW [QI HI])
427+
428+;; A list of all the integer modes upto 64bit
429+(define_mode_iterator QHSD [QI HI SI DI])
430+
431+;; A list of the 32bit and 64bit integer modes
432+(define_mode_iterator SIDI [SI DI])
433+
434 ;; Integer element sizes implemented by IWMMXT.
435 (define_mode_iterator VMMX [V2SI V4HI V8QI])
436
437
438=== added file 'gcc/config/arm/linux-atomic-64bit.c'
439--- old/gcc/config/arm/linux-atomic-64bit.c 1970-01-01 00:00:00 +0000
440+++ new/gcc/config/arm/linux-atomic-64bit.c 2011-10-14 15:50:44 +0000
441@@ -0,0 +1,166 @@
442+/* 64bit Linux-specific atomic operations for ARM EABI.
443+ Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
444+ Based on linux-atomic.c
445+
446+ 64 bit additions david.gilbert@linaro.org
447+
448+This file is part of GCC.
449+
450+GCC is free software; you can redistribute it and/or modify it under
451+the terms of the GNU General Public License as published by the Free
452+Software Foundation; either version 3, or (at your option) any later
453+version.
454+
455+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
456+WARRANTY; without even the implied warranty of MERCHANTABILITY or
457+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
458+for more details.
459+
460+Under Section 7 of GPL version 3, you are granted additional
461+permissions described in the GCC Runtime Library Exception, version
462+3.1, as published by the Free Software Foundation.
463+
464+You should have received a copy of the GNU General Public License and
465+a copy of the GCC Runtime Library Exception along with this program;
466+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
467+<http://www.gnu.org/licenses/>. */
468+
469+/* 64bit helper functions for atomic operations; the compiler will
470+ call these when the code is compiled for a CPU without ldrexd/strexd.
471+ (If the CPU had those then the compiler inlines the operation).
472+
473+ These helpers require a kernel helper that's only present on newer
474+ kernels; we check for that in an init section and bail out rather
475+ unceremoneously. */
476+
477+extern unsigned int __write (int fd, const void *buf, unsigned int count);
478+extern void abort (void);
479+
480+/* Kernel helper for compare-and-exchange. */
481+typedef int (__kernel_cmpxchg64_t) (const long long* oldval,
482+ const long long* newval,
483+ long long *ptr);
484+#define __kernel_cmpxchg64 (*(__kernel_cmpxchg64_t *) 0xffff0f60)
485+
486+/* Kernel helper page version number. */
487+#define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
488+
489+/* Check that the kernel has a new enough version at load. */
490+static void __check_for_sync8_kernelhelper (void)
491+{
492+ if (__kernel_helper_version < 5)
493+ {
494+ const char err[] = "A newer kernel is required to run this binary. "
495+ "(__kernel_cmpxchg64 helper)\n";
496+ /* At this point we need a way to crash with some information
497+ for the user - I'm not sure I can rely on much else being
498+ available at this point, so do the same as generic-morestack.c
499+ write () and abort (). */
500+ __write (2 /* stderr. */, err, sizeof (err));
501+ abort ();
502+ }
503+};
504+
505+static void (*__sync8_kernelhelper_inithook[]) (void)
506+ __attribute__ ((used, section (".init_array"))) = {
507+ &__check_for_sync8_kernelhelper
508+};
509+
510+#define HIDDEN __attribute__ ((visibility ("hidden")))
511+
512+#define FETCH_AND_OP_WORD64(OP, PFX_OP, INF_OP) \
513+ long long HIDDEN \
514+ __sync_fetch_and_##OP##_8 (long long *ptr, long long val) \
515+ { \
516+ int failure; \
517+ long long tmp,tmp2; \
518+ \
519+ do { \
520+ tmp = *ptr; \
521+ tmp2 = PFX_OP (tmp INF_OP val); \
522+ failure = __kernel_cmpxchg64 (&tmp, &tmp2, ptr); \
523+ } while (failure != 0); \
524+ \
525+ return tmp; \
526+ }
527+
528+FETCH_AND_OP_WORD64 (add, , +)
529+FETCH_AND_OP_WORD64 (sub, , -)
530+FETCH_AND_OP_WORD64 (or, , |)
531+FETCH_AND_OP_WORD64 (and, , &)
532+FETCH_AND_OP_WORD64 (xor, , ^)
533+FETCH_AND_OP_WORD64 (nand, ~, &)
534+
535+#define NAME_oldval(OP, WIDTH) __sync_fetch_and_##OP##_##WIDTH
536+#define NAME_newval(OP, WIDTH) __sync_##OP##_and_fetch_##WIDTH
537+
538+/* Implement both __sync_<op>_and_fetch and __sync_fetch_and_<op> for
539+ subword-sized quantities. */
540+
541+#define OP_AND_FETCH_WORD64(OP, PFX_OP, INF_OP) \
542+ long long HIDDEN \
543+ __sync_##OP##_and_fetch_8 (long long *ptr, long long val) \
544+ { \
545+ int failure; \
546+ long long tmp,tmp2; \
547+ \
548+ do { \
549+ tmp = *ptr; \
550+ tmp2 = PFX_OP (tmp INF_OP val); \
551+ failure = __kernel_cmpxchg64 (&tmp, &tmp2, ptr); \
552+ } while (failure != 0); \
553+ \
554+ return tmp2; \
555+ }
556+
557+OP_AND_FETCH_WORD64 (add, , +)
558+OP_AND_FETCH_WORD64 (sub, , -)
559+OP_AND_FETCH_WORD64 (or, , |)
560+OP_AND_FETCH_WORD64 (and, , &)
561+OP_AND_FETCH_WORD64 (xor, , ^)
562+OP_AND_FETCH_WORD64 (nand, ~, &)
563+
564+long long HIDDEN
565+__sync_val_compare_and_swap_8 (long long *ptr, long long oldval,
566+ long long newval)
567+{
568+ int failure;
569+ long long actual_oldval;
570+
571+ while (1)
572+ {
573+ actual_oldval = *ptr;
574+
575+ if (__builtin_expect (oldval != actual_oldval, 0))
576+ return actual_oldval;
577+
578+ failure = __kernel_cmpxchg64 (&actual_oldval, &newval, ptr);
579+
580+ if (__builtin_expect (!failure, 1))
581+ return oldval;
582+ }
583+}
584+
585+typedef unsigned char bool;
586+
587+bool HIDDEN
588+__sync_bool_compare_and_swap_8 (long long *ptr, long long oldval,
589+ long long newval)
590+{
591+ int failure = __kernel_cmpxchg64 (&oldval, &newval, ptr);
592+ return (failure == 0);
593+}
594+
595+long long HIDDEN
596+__sync_lock_test_and_set_8 (long long *ptr, long long val)
597+{
598+ int failure;
599+ long long oldval;
600+
601+ do {
602+ oldval = *ptr;
603+ failure = __kernel_cmpxchg64 (&oldval, &val, ptr);
604+ } while (failure != 0);
605+
606+ return oldval;
607+}
608
609=== modified file 'gcc/config/arm/linux-atomic.c'
610--- old/gcc/config/arm/linux-atomic.c 2011-01-03 20:52:22 +0000
611+++ new/gcc/config/arm/linux-atomic.c 2011-10-14 15:50:44 +0000
612@@ -32,8 +32,8 @@
613 #define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)
614
615 /* Note: we implement byte, short and int versions of atomic operations using
616- the above kernel helpers, but there is no support for "long long" (64-bit)
617- operations as yet. */
618+ the above kernel helpers; see linux-atomic-64bit.c for "long long" (64-bit)
619+ operations. */
620
621 #define HIDDEN __attribute__ ((visibility ("hidden")))
622
623@@ -273,6 +273,7 @@
624 *ptr = 0; \
625 }
626
627+SYNC_LOCK_RELEASE (long long, 8)
628 SYNC_LOCK_RELEASE (int, 4)
629 SYNC_LOCK_RELEASE (short, 2)
630 SYNC_LOCK_RELEASE (char, 1)
631
632=== modified file 'gcc/config/arm/sync.md'
633--- old/gcc/config/arm/sync.md 2010-12-31 13:25:33 +0000
634+++ new/gcc/config/arm/sync.md 2011-10-14 15:47:15 +0000
635@@ -1,6 +1,7 @@
636 ;; Machine description for ARM processor synchronization primitives.
637 ;; Copyright (C) 2010 Free Software Foundation, Inc.
638 ;; Written by Marcus Shawcroft (marcus.shawcroft@arm.com)
639+;; 64bit Atomics by Dave Gilbert (david.gilbert@linaro.org)
640 ;;
641 ;; This file is part of GCC.
642 ;;
643@@ -33,31 +34,24 @@
644 MEM_VOLATILE_P (operands[0]) = 1;
645 })
646
647-(define_expand "sync_compare_and_swapsi"
648- [(set (match_operand:SI 0 "s_register_operand")
649- (unspec_volatile:SI [(match_operand:SI 1 "memory_operand")
650- (match_operand:SI 2 "s_register_operand")
651- (match_operand:SI 3 "s_register_operand")]
652- VUNSPEC_SYNC_COMPARE_AND_SWAP))]
653- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
654- {
655- struct arm_sync_generator generator;
656- generator.op = arm_sync_generator_omrn;
657- generator.u.omrn = gen_arm_sync_compare_and_swapsi;
658- arm_expand_sync (SImode, &generator, operands[0], operands[1], operands[2],
659- operands[3]);
660- DONE;
661- })
662
663-(define_mode_iterator NARROW [QI HI])
664+(define_mode_attr sync_predtab [(SI "TARGET_HAVE_LDREX &&
665+ TARGET_HAVE_MEMORY_BARRIER")
666+ (QI "TARGET_HAVE_LDREXBH &&
667+ TARGET_HAVE_MEMORY_BARRIER")
668+ (HI "TARGET_HAVE_LDREXBH &&
669+ TARGET_HAVE_MEMORY_BARRIER")
670+ (DI "TARGET_HAVE_LDREXD &&
671+ ARM_DOUBLEWORD_ALIGN &&
672+ TARGET_HAVE_MEMORY_BARRIER")])
673
674 (define_expand "sync_compare_and_swap<mode>"
675- [(set (match_operand:NARROW 0 "s_register_operand")
676- (unspec_volatile:NARROW [(match_operand:NARROW 1 "memory_operand")
677- (match_operand:NARROW 2 "s_register_operand")
678- (match_operand:NARROW 3 "s_register_operand")]
679+ [(set (match_operand:QHSD 0 "s_register_operand")
680+ (unspec_volatile:QHSD [(match_operand:QHSD 1 "memory_operand")
681+ (match_operand:QHSD 2 "s_register_operand")
682+ (match_operand:QHSD 3 "s_register_operand")]
683 VUNSPEC_SYNC_COMPARE_AND_SWAP))]
684- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
685+ "<sync_predtab>"
686 {
687 struct arm_sync_generator generator;
688 generator.op = arm_sync_generator_omrn;
689@@ -67,25 +61,11 @@
690 DONE;
691 })
692
693-(define_expand "sync_lock_test_and_setsi"
694- [(match_operand:SI 0 "s_register_operand")
695- (match_operand:SI 1 "memory_operand")
696- (match_operand:SI 2 "s_register_operand")]
697- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
698- {
699- struct arm_sync_generator generator;
700- generator.op = arm_sync_generator_omn;
701- generator.u.omn = gen_arm_sync_lock_test_and_setsi;
702- arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
703- operands[2]);
704- DONE;
705- })
706-
707 (define_expand "sync_lock_test_and_set<mode>"
708- [(match_operand:NARROW 0 "s_register_operand")
709- (match_operand:NARROW 1 "memory_operand")
710- (match_operand:NARROW 2 "s_register_operand")]
711- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
712+ [(match_operand:QHSD 0 "s_register_operand")
713+ (match_operand:QHSD 1 "memory_operand")
714+ (match_operand:QHSD 2 "s_register_operand")]
715+ "<sync_predtab>"
716 {
717 struct arm_sync_generator generator;
718 generator.op = arm_sync_generator_omn;
719@@ -115,51 +95,25 @@
720 (plus "*")
721 (minus "*")])
722
723-(define_expand "sync_<sync_optab>si"
724- [(match_operand:SI 0 "memory_operand")
725- (match_operand:SI 1 "s_register_operand")
726- (syncop:SI (match_dup 0) (match_dup 1))]
727- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
728- {
729- struct arm_sync_generator generator;
730- generator.op = arm_sync_generator_omn;
731- generator.u.omn = gen_arm_sync_new_<sync_optab>si;
732- arm_expand_sync (SImode, &generator, NULL, operands[0], NULL, operands[1]);
733- DONE;
734- })
735-
736-(define_expand "sync_nandsi"
737- [(match_operand:SI 0 "memory_operand")
738- (match_operand:SI 1 "s_register_operand")
739- (not:SI (and:SI (match_dup 0) (match_dup 1)))]
740- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
741- {
742- struct arm_sync_generator generator;
743- generator.op = arm_sync_generator_omn;
744- generator.u.omn = gen_arm_sync_new_nandsi;
745- arm_expand_sync (SImode, &generator, NULL, operands[0], NULL, operands[1]);
746- DONE;
747- })
748-
749 (define_expand "sync_<sync_optab><mode>"
750- [(match_operand:NARROW 0 "memory_operand")
751- (match_operand:NARROW 1 "s_register_operand")
752- (syncop:NARROW (match_dup 0) (match_dup 1))]
753- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
754+ [(match_operand:QHSD 0 "memory_operand")
755+ (match_operand:QHSD 1 "s_register_operand")
756+ (syncop:QHSD (match_dup 0) (match_dup 1))]
757+ "<sync_predtab>"
758 {
759 struct arm_sync_generator generator;
760 generator.op = arm_sync_generator_omn;
761 generator.u.omn = gen_arm_sync_new_<sync_optab><mode>;
762 arm_expand_sync (<MODE>mode, &generator, NULL, operands[0], NULL,
763- operands[1]);
764+ operands[1]);
765 DONE;
766 })
767
768 (define_expand "sync_nand<mode>"
769- [(match_operand:NARROW 0 "memory_operand")
770- (match_operand:NARROW 1 "s_register_operand")
771- (not:NARROW (and:NARROW (match_dup 0) (match_dup 1)))]
772- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
773+ [(match_operand:QHSD 0 "memory_operand")
774+ (match_operand:QHSD 1 "s_register_operand")
775+ (not:QHSD (and:QHSD (match_dup 0) (match_dup 1)))]
776+ "<sync_predtab>"
777 {
778 struct arm_sync_generator generator;
779 generator.op = arm_sync_generator_omn;
780@@ -169,57 +123,27 @@
781 DONE;
782 })
783
784-(define_expand "sync_new_<sync_optab>si"
785- [(match_operand:SI 0 "s_register_operand")
786- (match_operand:SI 1 "memory_operand")
787- (match_operand:SI 2 "s_register_operand")
788- (syncop:SI (match_dup 1) (match_dup 2))]
789- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
790- {
791- struct arm_sync_generator generator;
792- generator.op = arm_sync_generator_omn;
793- generator.u.omn = gen_arm_sync_new_<sync_optab>si;
794- arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
795- operands[2]);
796- DONE;
797- })
798-
799-(define_expand "sync_new_nandsi"
800- [(match_operand:SI 0 "s_register_operand")
801- (match_operand:SI 1 "memory_operand")
802- (match_operand:SI 2 "s_register_operand")
803- (not:SI (and:SI (match_dup 1) (match_dup 2)))]
804- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
805- {
806- struct arm_sync_generator generator;
807- generator.op = arm_sync_generator_omn;
808- generator.u.omn = gen_arm_sync_new_nandsi;
809- arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
810- operands[2]);
811- DONE;
812- })
813-
814 (define_expand "sync_new_<sync_optab><mode>"
815- [(match_operand:NARROW 0 "s_register_operand")
816- (match_operand:NARROW 1 "memory_operand")
817- (match_operand:NARROW 2 "s_register_operand")
818- (syncop:NARROW (match_dup 1) (match_dup 2))]
819- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
820+ [(match_operand:QHSD 0 "s_register_operand")
821+ (match_operand:QHSD 1 "memory_operand")
822+ (match_operand:QHSD 2 "s_register_operand")
823+ (syncop:QHSD (match_dup 1) (match_dup 2))]
824+ "<sync_predtab>"
825 {
826 struct arm_sync_generator generator;
827 generator.op = arm_sync_generator_omn;
828 generator.u.omn = gen_arm_sync_new_<sync_optab><mode>;
829 arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1],
830- NULL, operands[2]);
831+ NULL, operands[2]);
832 DONE;
833 })
834
835 (define_expand "sync_new_nand<mode>"
836- [(match_operand:NARROW 0 "s_register_operand")
837- (match_operand:NARROW 1 "memory_operand")
838- (match_operand:NARROW 2 "s_register_operand")
839- (not:NARROW (and:NARROW (match_dup 1) (match_dup 2)))]
840- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
841+ [(match_operand:QHSD 0 "s_register_operand")
842+ (match_operand:QHSD 1 "memory_operand")
843+ (match_operand:QHSD 2 "s_register_operand")
844+ (not:QHSD (and:QHSD (match_dup 1) (match_dup 2)))]
845+ "<sync_predtab>"
846 {
847 struct arm_sync_generator generator;
848 generator.op = arm_sync_generator_omn;
849@@ -229,57 +153,27 @@
850 DONE;
851 });
852
853-(define_expand "sync_old_<sync_optab>si"
854- [(match_operand:SI 0 "s_register_operand")
855- (match_operand:SI 1 "memory_operand")
856- (match_operand:SI 2 "s_register_operand")
857- (syncop:SI (match_dup 1) (match_dup 2))]
858- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
859- {
860- struct arm_sync_generator generator;
861- generator.op = arm_sync_generator_omn;
862- generator.u.omn = gen_arm_sync_old_<sync_optab>si;
863- arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
864- operands[2]);
865- DONE;
866- })
867-
868-(define_expand "sync_old_nandsi"
869- [(match_operand:SI 0 "s_register_operand")
870- (match_operand:SI 1 "memory_operand")
871- (match_operand:SI 2 "s_register_operand")
872- (not:SI (and:SI (match_dup 1) (match_dup 2)))]
873- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
874- {
875- struct arm_sync_generator generator;
876- generator.op = arm_sync_generator_omn;
877- generator.u.omn = gen_arm_sync_old_nandsi;
878- arm_expand_sync (SImode, &generator, operands[0], operands[1], NULL,
879- operands[2]);
880- DONE;
881- })
882-
883 (define_expand "sync_old_<sync_optab><mode>"
884- [(match_operand:NARROW 0 "s_register_operand")
885- (match_operand:NARROW 1 "memory_operand")
886- (match_operand:NARROW 2 "s_register_operand")
887- (syncop:NARROW (match_dup 1) (match_dup 2))]
888- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
889+ [(match_operand:QHSD 0 "s_register_operand")
890+ (match_operand:QHSD 1 "memory_operand")
891+ (match_operand:QHSD 2 "s_register_operand")
892+ (syncop:QHSD (match_dup 1) (match_dup 2))]
893+ "<sync_predtab>"
894 {
895 struct arm_sync_generator generator;
896 generator.op = arm_sync_generator_omn;
897 generator.u.omn = gen_arm_sync_old_<sync_optab><mode>;
898 arm_expand_sync (<MODE>mode, &generator, operands[0], operands[1],
899- NULL, operands[2]);
900+ NULL, operands[2]);
901 DONE;
902 })
903
904 (define_expand "sync_old_nand<mode>"
905- [(match_operand:NARROW 0 "s_register_operand")
906- (match_operand:NARROW 1 "memory_operand")
907- (match_operand:NARROW 2 "s_register_operand")
908- (not:NARROW (and:NARROW (match_dup 1) (match_dup 2)))]
909- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
910+ [(match_operand:QHSD 0 "s_register_operand")
911+ (match_operand:QHSD 1 "memory_operand")
912+ (match_operand:QHSD 2 "s_register_operand")
913+ (not:QHSD (and:QHSD (match_dup 1) (match_dup 2)))]
914+ "<sync_predtab>"
915 {
916 struct arm_sync_generator generator;
917 generator.op = arm_sync_generator_omn;
918@@ -289,22 +183,22 @@
919 DONE;
920 })
921
922-(define_insn "arm_sync_compare_and_swapsi"
923- [(set (match_operand:SI 0 "s_register_operand" "=&r")
924- (unspec_volatile:SI
925- [(match_operand:SI 1 "arm_sync_memory_operand" "+Q")
926- (match_operand:SI 2 "s_register_operand" "r")
927- (match_operand:SI 3 "s_register_operand" "r")]
928- VUNSPEC_SYNC_COMPARE_AND_SWAP))
929- (set (match_dup 1) (unspec_volatile:SI [(match_dup 2)]
930+(define_insn "arm_sync_compare_and_swap<mode>"
931+ [(set (match_operand:SIDI 0 "s_register_operand" "=&r")
932+ (unspec_volatile:SIDI
933+ [(match_operand:SIDI 1 "arm_sync_memory_operand" "+Q")
934+ (match_operand:SIDI 2 "s_register_operand" "r")
935+ (match_operand:SIDI 3 "s_register_operand" "r")]
936+ VUNSPEC_SYNC_COMPARE_AND_SWAP))
937+ (set (match_dup 1) (unspec_volatile:SIDI [(match_dup 2)]
938 VUNSPEC_SYNC_COMPARE_AND_SWAP))
939 (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)]
940 VUNSPEC_SYNC_COMPARE_AND_SWAP))
941 ]
942- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
943+ "<sync_predtab>"
944 {
945 return arm_output_sync_insn (insn, operands);
946- }
947+ }
948 [(set_attr "sync_result" "0")
949 (set_attr "sync_memory" "1")
950 (set_attr "sync_required_value" "2")
951@@ -318,7 +212,7 @@
952 (zero_extend:SI
953 (unspec_volatile:NARROW
954 [(match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")
955- (match_operand:SI 2 "s_register_operand" "r")
956+ (match_operand:SI 2 "s_register_operand" "r")
957 (match_operand:SI 3 "s_register_operand" "r")]
958 VUNSPEC_SYNC_COMPARE_AND_SWAP)))
959 (set (match_dup 1) (unspec_volatile:NARROW [(match_dup 2)]
960@@ -326,10 +220,10 @@
961 (set (reg:CC CC_REGNUM) (unspec_volatile:CC [(match_dup 1)]
962 VUNSPEC_SYNC_COMPARE_AND_SWAP))
963 ]
964- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
965+ "<sync_predtab>"
966 {
967 return arm_output_sync_insn (insn, operands);
968- }
969+ }
970 [(set_attr "sync_result" "0")
971 (set_attr "sync_memory" "1")
972 (set_attr "sync_required_value" "2")
973@@ -338,18 +232,18 @@
974 (set_attr "conds" "clob")
975 (set_attr "predicable" "no")])
976
977-(define_insn "arm_sync_lock_test_and_setsi"
978- [(set (match_operand:SI 0 "s_register_operand" "=&r")
979- (match_operand:SI 1 "arm_sync_memory_operand" "+Q"))
980+(define_insn "arm_sync_lock_test_and_set<mode>"
981+ [(set (match_operand:SIDI 0 "s_register_operand" "=&r")
982+ (match_operand:SIDI 1 "arm_sync_memory_operand" "+Q"))
983 (set (match_dup 1)
984- (unspec_volatile:SI [(match_operand:SI 2 "s_register_operand" "r")]
985- VUNSPEC_SYNC_LOCK))
986+ (unspec_volatile:SIDI [(match_operand:SIDI 2 "s_register_operand" "r")]
987+ VUNSPEC_SYNC_LOCK))
988 (clobber (reg:CC CC_REGNUM))
989 (clobber (match_scratch:SI 3 "=&r"))]
990- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
991+ "<sync_predtab>"
992 {
993 return arm_output_sync_insn (insn, operands);
994- }
995+ }
996 [(set_attr "sync_release_barrier" "no")
997 (set_attr "sync_result" "0")
998 (set_attr "sync_memory" "1")
999@@ -364,10 +258,10 @@
1000 (zero_extend:SI (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q")))
1001 (set (match_dup 1)
1002 (unspec_volatile:NARROW [(match_operand:SI 2 "s_register_operand" "r")]
1003- VUNSPEC_SYNC_LOCK))
1004+ VUNSPEC_SYNC_LOCK))
1005 (clobber (reg:CC CC_REGNUM))
1006 (clobber (match_scratch:SI 3 "=&r"))]
1007- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
1008+ "<sync_predtab>"
1009 {
1010 return arm_output_sync_insn (insn, operands);
1011 }
1012@@ -380,22 +274,48 @@
1013 (set_attr "conds" "clob")
1014 (set_attr "predicable" "no")])
1015
1016-(define_insn "arm_sync_new_<sync_optab>si"
1017+(define_insn "arm_sync_new_<sync_optab><mode>"
1018+ [(set (match_operand:SIDI 0 "s_register_operand" "=&r")
1019+ (unspec_volatile:SIDI [(syncop:SIDI
1020+ (match_operand:SIDI 1 "arm_sync_memory_operand" "+Q")
1021+ (match_operand:SIDI 2 "s_register_operand" "r"))
1022+ ]
1023+ VUNSPEC_SYNC_NEW_OP))
1024+ (set (match_dup 1)
1025+ (unspec_volatile:SIDI [(match_dup 1) (match_dup 2)]
1026+ VUNSPEC_SYNC_NEW_OP))
1027+ (clobber (reg:CC CC_REGNUM))
1028+ (clobber (match_scratch:SI 3 "=&r"))]
1029+ "<sync_predtab>"
1030+ {
1031+ return arm_output_sync_insn (insn, operands);
1032+ }
1033+ [(set_attr "sync_result" "0")
1034+ (set_attr "sync_memory" "1")
1035+ (set_attr "sync_new_value" "2")
1036+ (set_attr "sync_t1" "0")
1037+ (set_attr "sync_t2" "3")
1038+ (set_attr "sync_op" "<sync_optab>")
1039+ (set_attr "conds" "clob")
1040+ (set_attr "predicable" "no")])
1041+
1042+(define_insn "arm_sync_new_<sync_optab><mode>"
1043 [(set (match_operand:SI 0 "s_register_operand" "=&r")
1044 (unspec_volatile:SI [(syncop:SI
1045- (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
1046- (match_operand:SI 2 "s_register_operand" "r"))
1047- ]
1048- VUNSPEC_SYNC_NEW_OP))
1049+ (zero_extend:SI
1050+ (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
1051+ (match_operand:SI 2 "s_register_operand" "r"))
1052+ ]
1053+ VUNSPEC_SYNC_NEW_OP))
1054 (set (match_dup 1)
1055- (unspec_volatile:SI [(match_dup 1) (match_dup 2)]
1056- VUNSPEC_SYNC_NEW_OP))
1057+ (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
1058+ VUNSPEC_SYNC_NEW_OP))
1059 (clobber (reg:CC CC_REGNUM))
1060 (clobber (match_scratch:SI 3 "=&r"))]
1061- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
1062+ "<sync_predtab>"
1063 {
1064 return arm_output_sync_insn (insn, operands);
1065- }
1066+ }
1067 [(set_attr "sync_result" "0")
1068 (set_attr "sync_memory" "1")
1069 (set_attr "sync_new_value" "2")
1070@@ -405,22 +325,22 @@
1071 (set_attr "conds" "clob")
1072 (set_attr "predicable" "no")])
1073
1074-(define_insn "arm_sync_new_nandsi"
1075- [(set (match_operand:SI 0 "s_register_operand" "=&r")
1076- (unspec_volatile:SI [(not:SI (and:SI
1077- (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
1078- (match_operand:SI 2 "s_register_operand" "r")))
1079- ]
1080- VUNSPEC_SYNC_NEW_OP))
1081+(define_insn "arm_sync_new_nand<mode>"
1082+ [(set (match_operand:SIDI 0 "s_register_operand" "=&r")
1083+ (unspec_volatile:SIDI [(not:SIDI (and:SIDI
1084+ (match_operand:SIDI 1 "arm_sync_memory_operand" "+Q")
1085+ (match_operand:SIDI 2 "s_register_operand" "r")))
1086+ ]
1087+ VUNSPEC_SYNC_NEW_OP))
1088 (set (match_dup 1)
1089- (unspec_volatile:SI [(match_dup 1) (match_dup 2)]
1090- VUNSPEC_SYNC_NEW_OP))
1091+ (unspec_volatile:SIDI [(match_dup 1) (match_dup 2)]
1092+ VUNSPEC_SYNC_NEW_OP))
1093 (clobber (reg:CC CC_REGNUM))
1094 (clobber (match_scratch:SI 3 "=&r"))]
1095- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
1096+ "<sync_predtab>"
1097 {
1098 return arm_output_sync_insn (insn, operands);
1099- }
1100+ }
1101 [(set_attr "sync_result" "0")
1102 (set_attr "sync_memory" "1")
1103 (set_attr "sync_new_value" "2")
1104@@ -430,50 +350,24 @@
1105 (set_attr "conds" "clob")
1106 (set_attr "predicable" "no")])
1107
1108-(define_insn "arm_sync_new_<sync_optab><mode>"
1109- [(set (match_operand:SI 0 "s_register_operand" "=&r")
1110- (unspec_volatile:SI [(syncop:SI
1111- (zero_extend:SI
1112- (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
1113- (match_operand:SI 2 "s_register_operand" "r"))
1114- ]
1115- VUNSPEC_SYNC_NEW_OP))
1116- (set (match_dup 1)
1117- (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
1118- VUNSPEC_SYNC_NEW_OP))
1119- (clobber (reg:CC CC_REGNUM))
1120- (clobber (match_scratch:SI 3 "=&r"))]
1121- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
1122- {
1123- return arm_output_sync_insn (insn, operands);
1124- }
1125- [(set_attr "sync_result" "0")
1126- (set_attr "sync_memory" "1")
1127- (set_attr "sync_new_value" "2")
1128- (set_attr "sync_t1" "0")
1129- (set_attr "sync_t2" "3")
1130- (set_attr "sync_op" "<sync_optab>")
1131- (set_attr "conds" "clob")
1132- (set_attr "predicable" "no")])
1133-
1134 (define_insn "arm_sync_new_nand<mode>"
1135 [(set (match_operand:SI 0 "s_register_operand" "=&r")
1136 (unspec_volatile:SI
1137 [(not:SI
1138 (and:SI
1139- (zero_extend:SI
1140- (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
1141- (match_operand:SI 2 "s_register_operand" "r")))
1142+ (zero_extend:SI
1143+ (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
1144+ (match_operand:SI 2 "s_register_operand" "r")))
1145 ] VUNSPEC_SYNC_NEW_OP))
1146 (set (match_dup 1)
1147 (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
1148- VUNSPEC_SYNC_NEW_OP))
1149+ VUNSPEC_SYNC_NEW_OP))
1150 (clobber (reg:CC CC_REGNUM))
1151 (clobber (match_scratch:SI 3 "=&r"))]
1152- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
1153+ "<sync_predtab>"
1154 {
1155 return arm_output_sync_insn (insn, operands);
1156- }
1157+ }
1158 [(set_attr "sync_result" "0")
1159 (set_attr "sync_memory" "1")
1160 (set_attr "sync_new_value" "2")
1161@@ -483,20 +377,20 @@
1162 (set_attr "conds" "clob")
1163 (set_attr "predicable" "no")])
1164
1165-(define_insn "arm_sync_old_<sync_optab>si"
1166- [(set (match_operand:SI 0 "s_register_operand" "=&r")
1167- (unspec_volatile:SI [(syncop:SI
1168- (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
1169- (match_operand:SI 2 "s_register_operand" "r"))
1170- ]
1171- VUNSPEC_SYNC_OLD_OP))
1172+(define_insn "arm_sync_old_<sync_optab><mode>"
1173+ [(set (match_operand:SIDI 0 "s_register_operand" "=&r")
1174+ (unspec_volatile:SIDI [(syncop:SIDI
1175+ (match_operand:SIDI 1 "arm_sync_memory_operand" "+Q")
1176+ (match_operand:SIDI 2 "s_register_operand" "r"))
1177+ ]
1178+ VUNSPEC_SYNC_OLD_OP))
1179 (set (match_dup 1)
1180- (unspec_volatile:SI [(match_dup 1) (match_dup 2)]
1181- VUNSPEC_SYNC_OLD_OP))
1182+ (unspec_volatile:SIDI [(match_dup 1) (match_dup 2)]
1183+ VUNSPEC_SYNC_OLD_OP))
1184 (clobber (reg:CC CC_REGNUM))
1185- (clobber (match_scratch:SI 3 "=&r"))
1186+ (clobber (match_scratch:SIDI 3 "=&r"))
1187 (clobber (match_scratch:SI 4 "<sync_clobber>"))]
1188- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
1189+ "<sync_predtab>"
1190 {
1191 return arm_output_sync_insn (insn, operands);
1192 }
1193@@ -509,47 +403,21 @@
1194 (set_attr "conds" "clob")
1195 (set_attr "predicable" "no")])
1196
1197-(define_insn "arm_sync_old_nandsi"
1198- [(set (match_operand:SI 0 "s_register_operand" "=&r")
1199- (unspec_volatile:SI [(not:SI (and:SI
1200- (match_operand:SI 1 "arm_sync_memory_operand" "+Q")
1201- (match_operand:SI 2 "s_register_operand" "r")))
1202- ]
1203- VUNSPEC_SYNC_OLD_OP))
1204- (set (match_dup 1)
1205- (unspec_volatile:SI [(match_dup 1) (match_dup 2)]
1206- VUNSPEC_SYNC_OLD_OP))
1207- (clobber (reg:CC CC_REGNUM))
1208- (clobber (match_scratch:SI 3 "=&r"))
1209- (clobber (match_scratch:SI 4 "=&r"))]
1210- "TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER"
1211- {
1212- return arm_output_sync_insn (insn, operands);
1213- }
1214- [(set_attr "sync_result" "0")
1215- (set_attr "sync_memory" "1")
1216- (set_attr "sync_new_value" "2")
1217- (set_attr "sync_t1" "3")
1218- (set_attr "sync_t2" "4")
1219- (set_attr "sync_op" "nand")
1220- (set_attr "conds" "clob")
1221- (set_attr "predicable" "no")])
1222-
1223 (define_insn "arm_sync_old_<sync_optab><mode>"
1224 [(set (match_operand:SI 0 "s_register_operand" "=&r")
1225 (unspec_volatile:SI [(syncop:SI
1226- (zero_extend:SI
1227- (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
1228- (match_operand:SI 2 "s_register_operand" "r"))
1229- ]
1230- VUNSPEC_SYNC_OLD_OP))
1231+ (zero_extend:SI
1232+ (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
1233+ (match_operand:SI 2 "s_register_operand" "r"))
1234+ ]
1235+ VUNSPEC_SYNC_OLD_OP))
1236 (set (match_dup 1)
1237- (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
1238- VUNSPEC_SYNC_OLD_OP))
1239+ (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
1240+ VUNSPEC_SYNC_OLD_OP))
1241 (clobber (reg:CC CC_REGNUM))
1242 (clobber (match_scratch:SI 3 "=&r"))
1243 (clobber (match_scratch:SI 4 "<sync_clobber>"))]
1244- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
1245+ "<sync_predtab>"
1246 {
1247 return arm_output_sync_insn (insn, operands);
1248 }
1249@@ -563,20 +431,46 @@
1250 (set_attr "predicable" "no")])
1251
1252 (define_insn "arm_sync_old_nand<mode>"
1253+ [(set (match_operand:SIDI 0 "s_register_operand" "=&r")
1254+ (unspec_volatile:SIDI [(not:SIDI (and:SIDI
1255+ (match_operand:SIDI 1 "arm_sync_memory_operand" "+Q")
1256+ (match_operand:SIDI 2 "s_register_operand" "r")))
1257+ ]
1258+ VUNSPEC_SYNC_OLD_OP))
1259+ (set (match_dup 1)
1260+ (unspec_volatile:SIDI [(match_dup 1) (match_dup 2)]
1261+ VUNSPEC_SYNC_OLD_OP))
1262+ (clobber (reg:CC CC_REGNUM))
1263+ (clobber (match_scratch:SIDI 3 "=&r"))
1264+ (clobber (match_scratch:SI 4 "=&r"))]
1265+ "<sync_predtab>"
1266+ {
1267+ return arm_output_sync_insn (insn, operands);
1268+ }
1269+ [(set_attr "sync_result" "0")
1270+ (set_attr "sync_memory" "1")
1271+ (set_attr "sync_new_value" "2")
1272+ (set_attr "sync_t1" "3")
1273+ (set_attr "sync_t2" "4")
1274+ (set_attr "sync_op" "nand")
1275+ (set_attr "conds" "clob")
1276+ (set_attr "predicable" "no")])
1277+
1278+(define_insn "arm_sync_old_nand<mode>"
1279 [(set (match_operand:SI 0 "s_register_operand" "=&r")
1280- (unspec_volatile:SI [(not:SI (and:SI
1281- (zero_extend:SI
1282- (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
1283- (match_operand:SI 2 "s_register_operand" "r")))
1284- ]
1285- VUNSPEC_SYNC_OLD_OP))
1286+ (unspec_volatile:SI [(not:SI (and:SI
1287+ (zero_extend:SI
1288+ (match_operand:NARROW 1 "arm_sync_memory_operand" "+Q"))
1289+ (match_operand:SI 2 "s_register_operand" "r")))
1290+ ]
1291+ VUNSPEC_SYNC_OLD_OP))
1292 (set (match_dup 1)
1293- (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
1294- VUNSPEC_SYNC_OLD_OP))
1295+ (unspec_volatile:NARROW [(match_dup 1) (match_dup 2)]
1296+ VUNSPEC_SYNC_OLD_OP))
1297 (clobber (reg:CC CC_REGNUM))
1298 (clobber (match_scratch:SI 3 "=&r"))
1299 (clobber (match_scratch:SI 4 "=&r"))]
1300- "TARGET_HAVE_LDREXBHD && TARGET_HAVE_MEMORY_BARRIER"
1301+ "<sync_predtab>"
1302 {
1303 return arm_output_sync_insn (insn, operands);
1304 }
1305
1306=== modified file 'gcc/config/arm/t-linux-eabi'
1307--- old/gcc/config/arm/t-linux-eabi 2011-01-03 20:52:22 +0000
1308+++ new/gcc/config/arm/t-linux-eabi 2011-10-14 15:50:44 +0000
1309@@ -36,3 +36,4 @@
1310 EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o
1311
1312 LIB2FUNCS_STATIC_EXTRA += $(srcdir)/config/arm/linux-atomic.c
1313+LIB2FUNCS_STATIC_EXTRA += $(srcdir)/config/arm/linux-atomic-64bit.c
1314
1315=== added file 'gcc/testsuite/gcc.dg/di-longlong64-sync-1.c'
1316--- old/gcc/testsuite/gcc.dg/di-longlong64-sync-1.c 1970-01-01 00:00:00 +0000
1317+++ new/gcc/testsuite/gcc.dg/di-longlong64-sync-1.c 2011-10-14 15:56:32 +0000
1318@@ -0,0 +1,164 @@
1319+/* { dg-do run } */
1320+/* { dg-require-effective-target sync_longlong } */
1321+/* { dg-options "-std=gnu99" } */
1322+/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
1323+/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
1324+
1325+
1326+/* Test basic functionality of the intrinsics. The operations should
1327+ not be optimized away if no one checks the return values. */
1328+
1329+/* Based on ia64-sync-[12].c, but 1) long on ARM is 32 bit so use long long
1330+ (an explicit 64bit type maybe a better bet) and 2) Use values that cross
1331+ the 32bit boundary and cause carries since the actual maths are done as
1332+ pairs of 32 bit instructions. */
1333+
1334+/* Note: This file is #included by some of the ARM tests. */
1335+
1336+__extension__ typedef __SIZE_TYPE__ size_t;
1337+
1338+extern void abort (void);
1339+extern void *memcpy (void *, const void *, size_t);
1340+extern int memcmp (const void *, const void *, size_t);
1341+
1342+/* Temporary space where the work actually gets done. */
1343+static long long AL[24];
1344+/* Values copied into AL before we start. */
1345+static long long init_di[24] = { 0x100000002ll, 0x200000003ll, 0, 1,
1346+
1347+ 0x100000002ll, 0x100000002ll,
1348+ 0x100000002ll, 0x100000002ll,
1349+
1350+ 0, 0x1000e0de0000ll,
1351+ 42 , 0xc001c0de0000ll,
1352+
1353+ -1ll, 0, 0xff00ff0000ll, -1ll,
1354+
1355+ 0, 0x1000e0de0000ll,
1356+ 42 , 0xc001c0de0000ll,
1357+
1358+ -1ll, 0, 0xff00ff0000ll, -1ll};
1359+/* This is what should be in AL at the end. */
1360+static long long test_di[24] = { 0x1234567890ll, 0x1234567890ll, 1, 0,
1361+
1362+ 0x100000002ll, 0x100000002ll,
1363+ 0x100000002ll, 0x100000002ll,
1364+
1365+ 1, 0xc001c0de0000ll,
1366+ 20, 0x1000e0de0000ll,
1367+
1368+ 0x300000007ll , 0x500000009ll,
1369+ 0xf100ff0001ll, ~0xa00000007ll,
1370+
1371+ 1, 0xc001c0de0000ll,
1372+ 20, 0x1000e0de0000ll,
1373+
1374+ 0x300000007ll , 0x500000009ll,
1375+ 0xf100ff0001ll, ~0xa00000007ll };
1376+
1377+/* First check they work in terms of what they do to memory. */
1378+static void
1379+do_noret_di (void)
1380+{
1381+ __sync_val_compare_and_swap (AL+0, 0x100000002ll, 0x1234567890ll);
1382+ __sync_bool_compare_and_swap (AL+1, 0x200000003ll, 0x1234567890ll);
1383+ __sync_lock_test_and_set (AL+2, 1);
1384+ __sync_lock_release (AL+3);
1385+
1386+ /* The following tests should not change the value since the
1387+ original does NOT match. */
1388+ __sync_val_compare_and_swap (AL+4, 0x000000002ll, 0x1234567890ll);
1389+ __sync_val_compare_and_swap (AL+5, 0x100000000ll, 0x1234567890ll);
1390+ __sync_bool_compare_and_swap (AL+6, 0x000000002ll, 0x1234567890ll);
1391+ __sync_bool_compare_and_swap (AL+7, 0x100000000ll, 0x1234567890ll);
1392+
1393+ __sync_fetch_and_add (AL+8, 1);
1394+ __sync_fetch_and_add (AL+9, 0xb000e0000000ll); /* + to both halves & carry. */
1395+ __sync_fetch_and_sub (AL+10, 22);
1396+ __sync_fetch_and_sub (AL+11, 0xb000e0000000ll);
1397+
1398+ __sync_fetch_and_and (AL+12, 0x300000007ll);
1399+ __sync_fetch_and_or (AL+13, 0x500000009ll);
1400+ __sync_fetch_and_xor (AL+14, 0xe00000001ll);
1401+ __sync_fetch_and_nand (AL+15, 0xa00000007ll);
1402+
1403+ /* These should be the same as the fetch_and_* cases except for
1404+ return value. */
1405+ __sync_add_and_fetch (AL+16, 1);
1406+ /* add to both halves & carry. */
1407+ __sync_add_and_fetch (AL+17, 0xb000e0000000ll);
1408+ __sync_sub_and_fetch (AL+18, 22);
1409+ __sync_sub_and_fetch (AL+19, 0xb000e0000000ll);
1410+
1411+ __sync_and_and_fetch (AL+20, 0x300000007ll);
1412+ __sync_or_and_fetch (AL+21, 0x500000009ll);
1413+ __sync_xor_and_fetch (AL+22, 0xe00000001ll);
1414+ __sync_nand_and_fetch (AL+23, 0xa00000007ll);
1415+}
1416+
1417+/* Now check return values. */
1418+static void
1419+do_ret_di (void)
1420+{
1421+ if (__sync_val_compare_and_swap (AL+0, 0x100000002ll, 0x1234567890ll) !=
1422+ 0x100000002ll) abort ();
1423+ if (__sync_bool_compare_and_swap (AL+1, 0x200000003ll, 0x1234567890ll) !=
1424+ 1) abort ();
1425+ if (__sync_lock_test_and_set (AL+2, 1) != 0) abort ();
1426+ __sync_lock_release (AL+3); /* no return value, but keep to match results. */
1427+
1428+ /* The following tests should not change the value since the
1429+ original does NOT match. */
1430+ if (__sync_val_compare_and_swap (AL+4, 0x000000002ll, 0x1234567890ll) !=
1431+ 0x100000002ll) abort ();
1432+ if (__sync_val_compare_and_swap (AL+5, 0x100000000ll, 0x1234567890ll) !=
1433+ 0x100000002ll) abort ();
1434+ if (__sync_bool_compare_and_swap (AL+6, 0x000000002ll, 0x1234567890ll) !=
1435+ 0) abort ();
1436+ if (__sync_bool_compare_and_swap (AL+7, 0x100000000ll, 0x1234567890ll) !=
1437+ 0) abort ();
1438+
1439+ if (__sync_fetch_and_add (AL+8, 1) != 0) abort ();
1440+ if (__sync_fetch_and_add (AL+9, 0xb000e0000000ll) != 0x1000e0de0000ll) abort ();
1441+ if (__sync_fetch_and_sub (AL+10, 22) != 42) abort ();
1442+ if (__sync_fetch_and_sub (AL+11, 0xb000e0000000ll) != 0xc001c0de0000ll)
1443+ abort ();
1444+
1445+ if (__sync_fetch_and_and (AL+12, 0x300000007ll) != -1ll) abort ();
1446+ if (__sync_fetch_and_or (AL+13, 0x500000009ll) != 0) abort ();
1447+ if (__sync_fetch_and_xor (AL+14, 0xe00000001ll) != 0xff00ff0000ll) abort ();
1448+ if (__sync_fetch_and_nand (AL+15, 0xa00000007ll) != -1ll) abort ();
1449+
1450+ /* These should be the same as the fetch_and_* cases except for
1451+ return value. */
1452+ if (__sync_add_and_fetch (AL+16, 1) != 1) abort ();
1453+ if (__sync_add_and_fetch (AL+17, 0xb000e0000000ll) != 0xc001c0de0000ll)
1454+ abort ();
1455+ if (__sync_sub_and_fetch (AL+18, 22) != 20) abort ();
1456+ if (__sync_sub_and_fetch (AL+19, 0xb000e0000000ll) != 0x1000e0de0000ll)
1457+ abort ();
1458+
1459+ if (__sync_and_and_fetch (AL+20, 0x300000007ll) != 0x300000007ll) abort ();
1460+ if (__sync_or_and_fetch (AL+21, 0x500000009ll) != 0x500000009ll) abort ();
1461+ if (__sync_xor_and_fetch (AL+22, 0xe00000001ll) != 0xf100ff0001ll) abort ();
1462+ if (__sync_nand_and_fetch (AL+23, 0xa00000007ll) != ~0xa00000007ll) abort ();
1463+}
1464+
1465+int main ()
1466+{
1467+ memcpy (AL, init_di, sizeof (init_di));
1468+
1469+ do_noret_di ();
1470+
1471+ if (memcmp (AL, test_di, sizeof (test_di)))
1472+ abort ();
1473+
1474+ memcpy (AL, init_di, sizeof (init_di));
1475+
1476+ do_ret_di ();
1477+
1478+ if (memcmp (AL, test_di, sizeof (test_di)))
1479+ abort ();
1480+
1481+ return 0;
1482+}
1483
1484=== added file 'gcc/testsuite/gcc.dg/di-sync-multithread.c'
1485--- old/gcc/testsuite/gcc.dg/di-sync-multithread.c 1970-01-01 00:00:00 +0000
1486+++ new/gcc/testsuite/gcc.dg/di-sync-multithread.c 2011-10-14 15:56:32 +0000
1487@@ -0,0 +1,205 @@
1488+/* { dg-do run } */
1489+/* { dg-require-effective-target sync_longlong } */
1490+/* { dg-require-effective-target pthread_h } */
1491+/* { dg-require-effective-target pthread } */
1492+/* { dg-options "-pthread -std=gnu99" } */
1493+
1494+/* test of long long atomic ops performed in parallel in 3 pthreads
1495+ david.gilbert@linaro.org */
1496+
1497+#include <pthread.h>
1498+#include <unistd.h>
1499+
1500+/*#define DEBUGIT 1 */
1501+
1502+#ifdef DEBUGIT
1503+#include <stdio.h>
1504+
1505+#define DOABORT(x,...) {\
1506+ fprintf (stderr, x, __VA_ARGS__); fflush (stderr); abort ();\
1507+ }
1508+
1509+#else
1510+
1511+#define DOABORT(x,...) abort ();
1512+
1513+#endif
1514+
1515+/* Passed to each thread to describe which bits it is going to work on. */
1516+struct threadwork {
1517+ unsigned long long count; /* incremented each time the worker loops. */
1518+ unsigned int thread; /* ID */
1519+ unsigned int addlsb; /* 8 bit */
1520+ unsigned int logic1lsb; /* 5 bit */
1521+ unsigned int logic2lsb; /* 8 bit */
1522+};
1523+
1524+/* The shared word where all the atomic work is done. */
1525+static volatile long long workspace;
1526+
1527+/* A shared word to tell the workers to quit when non-0. */
1528+static long long doquit;
1529+
1530+extern void abort (void);
1531+
1532+/* Note this test doesn't test the return values much. */
1533+void*
1534+worker (void* data)
1535+{
1536+ struct threadwork *tw = (struct threadwork*)data;
1537+ long long add1bit = 1ll << tw->addlsb;
1538+ long long logic1bit = 1ll << tw->logic1lsb;
1539+ long long logic2bit = 1ll << tw->logic2lsb;
1540+
1541+ /* Clear the bits we use. */
1542+ __sync_and_and_fetch (&workspace, ~(0xffll * add1bit));
1543+ __sync_fetch_and_and (&workspace, ~(0x1fll * logic1bit));
1544+ __sync_fetch_and_and (&workspace, ~(0xffll * logic2bit));
1545+
1546+ do
1547+ {
1548+ long long tmp1, tmp2, tmp3;
1549+ /* OK, lets try and do some stuff to the workspace - by the end
1550+ of the main loop our area should be the same as it is now - i.e. 0. */
1551+
1552+ /* Push the arithmetic section upto 128 - one of the threads will
1553+ case this to carry accross the 32bit boundary. */
1554+ for (tmp2 = 0; tmp2 < 64; tmp2++)
1555+ {
1556+ /* Add 2 using the two different adds. */
1557+ tmp1 = __sync_add_and_fetch (&workspace, add1bit);
1558+ tmp3 = __sync_fetch_and_add (&workspace, add1bit);
1559+
1560+ /* The value should be the intermediate add value in both cases. */
1561+ if ((tmp1 & (add1bit * 0xff)) != (tmp3 & (add1bit * 0xff)))
1562+ DOABORT ("Mismatch of add intermediates on thread %d "
1563+ "workspace=0x%llx tmp1=0x%llx "
1564+ "tmp2=0x%llx tmp3=0x%llx\n",
1565+ tw->thread, workspace, tmp1, tmp2, tmp3);
1566+ }
1567+
1568+ /* Set the logic bits. */
1569+ tmp2=__sync_or_and_fetch (&workspace,
1570+ 0x1fll * logic1bit | 0xffll * logic2bit);
1571+
1572+ /* Check the logic bits are set and the arithmetic value is correct. */
1573+ if ((tmp2 & (0x1fll * logic1bit | 0xffll * logic2bit
1574+ | 0xffll * add1bit))
1575+ != (0x1fll * logic1bit | 0xffll * logic2bit | 0x80ll * add1bit))
1576+ DOABORT ("Midloop check failed on thread %d "
1577+ "workspace=0x%llx tmp2=0x%llx "
1578+ "masktmp2=0x%llx expected=0x%llx\n",
1579+ tw->thread, workspace, tmp2,
1580+ tmp2 & (0x1fll * logic1bit | 0xffll * logic2bit |
1581+ 0xffll * add1bit),
1582+ (0x1fll * logic1bit | 0xffll * logic2bit | 0x80ll * add1bit));
1583+
1584+ /* Pull the arithmetic set back down to 0 - again this should cause a
1585+ carry across the 32bit boundary in one thread. */
1586+
1587+ for (tmp2 = 0; tmp2 < 64; tmp2++)
1588+ {
1589+ /* Subtract 2 using the two different subs. */
1590+ tmp1=__sync_sub_and_fetch (&workspace, add1bit);
1591+ tmp3=__sync_fetch_and_sub (&workspace, add1bit);
1592+
1593+ /* The value should be the intermediate sub value in both cases. */
1594+ if ((tmp1 & (add1bit * 0xff)) != (tmp3 & (add1bit * 0xff)))
1595+ DOABORT ("Mismatch of sub intermediates on thread %d "
1596+ "workspace=0x%llx tmp1=0x%llx "
1597+ "tmp2=0x%llx tmp3=0x%llx\n",
1598+ tw->thread, workspace, tmp1, tmp2, tmp3);
1599+ }
1600+
1601+
1602+ /* Clear the logic bits. */
1603+ __sync_fetch_and_xor (&workspace, 0x1fll * logic1bit);
1604+ tmp3=__sync_and_and_fetch (&workspace, ~(0xffll * logic2bit));
1605+
1606+ /* The logic bits and the arithmetic bits should be zero again. */
1607+ if (tmp3 & (0x1fll * logic1bit | 0xffll * logic2bit | 0xffll * add1bit))
1608+ DOABORT ("End of worker loop; bits none 0 on thread %d "
1609+ "workspace=0x%llx tmp3=0x%llx "
1610+ "mask=0x%llx maskedtmp3=0x%llx\n",
1611+ tw->thread, workspace, tmp3, (0x1fll * logic1bit |
1612+ 0xffll * logic2bit | 0xffll * add1bit),
1613+ tmp3 & (0x1fll * logic1bit | 0xffll * logic2bit | 0xffll * add1bit));
1614+
1615+ __sync_add_and_fetch (&tw->count, 1);
1616+ }
1617+ while (!__sync_bool_compare_and_swap (&doquit, 1, 1));
1618+
1619+ pthread_exit (0);
1620+}
1621+
1622+int
1623+main ()
1624+{
1625+ /* We have 3 threads doing three sets of operations, an 8 bit
1626+ arithmetic field, a 5 bit logic field and an 8 bit logic
1627+ field (just to pack them all in).
1628+
1629+ 6 5 4 4 3 2 1
1630+ 3 6 8 0 2 4 6 8 0
1631+ |...,...|...,...|...,...|...,...|...,...|...,...|...,...|...,...
1632+ - T0 -- T1 -- T2 --T2 -- T0 -*- T2-- T1-- T1 -***- T0-
1633+ logic2 logic2 arith log2 arith log1 log1 arith log1
1634+
1635+ */
1636+ unsigned int t;
1637+ long long tmp;
1638+ int err;
1639+
1640+ struct threadwork tw[3]={
1641+ { 0ll, 0, 27, 0, 56 },
1642+ { 0ll, 1, 8,16, 48 },
1643+ { 0ll, 2, 40,21, 35 }
1644+ };
1645+
1646+ pthread_t threads[3];
1647+
1648+ __sync_lock_release (&doquit);
1649+
1650+ /* Get the work space into a known value - All 1's. */
1651+ __sync_lock_release (&workspace); /* Now all 0. */
1652+ tmp = __sync_val_compare_and_swap (&workspace, 0, -1ll);
1653+ if (tmp!=0)
1654+ DOABORT ("Initial __sync_val_compare_and_swap wasn't 0 workspace=0x%llx "
1655+ "tmp=0x%llx\n", workspace,tmp);
1656+
1657+ for (t = 0; t < 3; t++)
1658+ {
1659+ err=pthread_create (&threads[t], NULL , worker, &tw[t]);
1660+ if (err) DOABORT ("pthread_create failed on thread %d with error %d\n",
1661+ t, err);
1662+ };
1663+
1664+ sleep (5);
1665+
1666+ /* Stop please. */
1667+ __sync_lock_test_and_set (&doquit, 1ll);
1668+
1669+ for (t = 0; t < 3; t++)
1670+ {
1671+ err=pthread_join (threads[t], NULL);
1672+ if (err)
1673+ DOABORT ("pthread_join failed on thread %d with error %d\n", t, err);
1674+ };
1675+
1676+ __sync_synchronize ();
1677+
1678+ /* OK, so all the workers have finished -
1679+ the workers should have zero'd their workspace, the unused areas
1680+ should still be 1. */
1681+ if (!__sync_bool_compare_and_swap (&workspace, 0x040000e0ll, 0))
1682+ DOABORT ("End of run workspace mismatch, got %llx\n", workspace);
1683+
1684+ /* All the workers should have done some work. */
1685+ for (t = 0; t < 3; t++)
1686+ {
1687+ if (tw[t].count == 0) DOABORT ("Worker %d gave 0 count\n", t);
1688+ };
1689+
1690+ return 0;
1691+}
1692+
1693
1694=== added file 'gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c'
1695--- old/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c 1970-01-01 00:00:00 +0000
1696+++ new/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c 2011-10-14 15:56:32 +0000
1697@@ -0,0 +1,14 @@
1698+/* { dg-do compile } */
1699+/* { dg-require-effective-target arm_arch_v5_ok } */
1700+/* { dg-options "-std=gnu99" } */
1701+/* { dg-add-options arm_arch_v5 } */
1702+/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
1703+/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
1704+/* { dg-message "file included" "In file included" { target *-*-* } 0 } */
1705+
1706+#include "../../gcc.dg/di-longlong64-sync-1.c"
1707+
1708+/* On an old ARM we have no ldrexd or strexd so we have to use helpers. */
1709+/* { dg-final { scan-assembler-not "ldrexd" } } */
1710+/* { dg-final { scan-assembler-not "strexd" } } */
1711+/* { dg-final { scan-assembler "__sync_" } } */
1712
1713=== added file 'gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c'
1714--- old/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c 1970-01-01 00:00:00 +0000
1715+++ new/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c 2011-10-14 15:56:32 +0000
1716@@ -0,0 +1,17 @@
1717+/* { dg-do compile } */
1718+/* { dg-require-effective-target arm_arm_ok } */
1719+/* { dg-options "-marm -std=gnu99" } */
1720+/* { dg-require-effective-target arm_arch_v6k_ok } */
1721+/* { dg-add-options arm_arch_v6k } */
1722+/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
1723+/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
1724+/* { dg-message "file included" "In file included" { target *-*-* } 0 } */
1725+
1726+#include "../../gcc.dg/di-longlong64-sync-1.c"
1727+
1728+/* We should be using ldrexd, strexd and no helpers or shorter ldrex. */
1729+/* { dg-final { scan-assembler-times "\tldrexd" 46 } } */
1730+/* { dg-final { scan-assembler-times "\tstrexd" 46 } } */
1731+/* { dg-final { scan-assembler-not "__sync_" } } */
1732+/* { dg-final { scan-assembler-not "ldrex\t" } } */
1733+/* { dg-final { scan-assembler-not "strex\t" } } */
1734
1735=== modified file 'gcc/testsuite/lib/target-supports.exp'
1736--- old/gcc/testsuite/lib/target-supports.exp 2011-11-22 17:10:17 +0000
1737+++ new/gcc/testsuite/lib/target-supports.exp 2011-11-28 15:07:01 +0000
1738@@ -2000,6 +2000,47 @@
1739 check_effective_target_arm_fp16_ok_nocache]
1740 }
1741
1742+# Creates a series of routines that return 1 if the given architecture
1743+# can be selected and a routine to give the flags to select that architecture
1744+# Note: Extra flags may be added to disable options from newer compilers
1745+# (Thumb in particular - but others may be added in the future)
1746+# Usage: /* { dg-require-effective-target arm_arch_v5_ok } */
1747+# /* { dg-add-options arm_arch_v5 } */
1748+foreach { armfunc armflag armdef } { v5 "-march=armv5 -marm" __ARM_ARCH_5__
1749+ v6 "-march=armv6" __ARM_ARCH_6__
1750+ v6k "-march=armv6k" __ARM_ARCH_6K__
1751+ v7a "-march=armv7-a" __ARM_ARCH_7A__ } {
1752+ eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef ] {
1753+ proc check_effective_target_arm_arch_FUNC_ok { } {
1754+ if { [ string match "*-marm*" "FLAG" ] &&
1755+ ![check_effective_target_arm_arm_ok] } {
1756+ return 0
1757+ }
1758+ return [check_no_compiler_messages arm_arch_FUNC_ok assembly {
1759+ #if !defined (DEF)
1760+ #error FOO
1761+ #endif
1762+ } "FLAG" ]
1763+ }
1764+
1765+ proc add_options_for_arm_arch_FUNC { flags } {
1766+ return "$flags FLAG"
1767+ }
1768+ }]
1769+}
1770+
1771+# Return 1 if this is an ARM target where -marm causes ARM to be
1772+# used (not Thumb)
1773+
1774+proc check_effective_target_arm_arm_ok { } {
1775+ return [check_no_compiler_messages arm_arm_ok assembly {
1776+ #if !defined (__arm__) || defined (__thumb__) || defined (__thumb2__)
1777+ #error FOO
1778+ #endif
1779+ } "-marm"]
1780+}
1781+
1782+
1783 # Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
1784 # used.
1785
1786@@ -3384,6 +3425,31 @@
1787 return $et_sync_int_long_saved
1788 }
1789
1790+# Return 1 if the target supports atomic operations on "long long" and can
1791+# execute them
1792+# So far only put checks in for ARM, others may want to add their own
1793+proc check_effective_target_sync_longlong { } {
1794+ return [check_runtime sync_longlong_runtime {
1795+ #include <stdlib.h>
1796+ int main ()
1797+ {
1798+ long long l1;
1799+
1800+ if (sizeof (long long) != 8)
1801+ exit (1);
1802+
1803+ #ifdef __arm__
1804+ /* Just check for native; checking for kernel fallback is tricky. */
1805+ asm volatile ("ldrexd r0,r1, [%0]" : : "r" (&l1) : "r0", "r1");
1806+ #else
1807+ # error "Add other suitable archs here"
1808+ #endif
1809+
1810+ exit (0);
1811+ }
1812+ } "" ]
1813+}
1814+
1815 # Return 1 if the target supports atomic operations on "char" and "short".
1816
1817 proc check_effective_target_sync_char_short { } {
1818
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106846.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106846.patch
deleted file mode 100644
index 88d74c72f..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106846.patch
+++ /dev/null
@@ -1,487 +0,0 @@
12011-11-27 Ira Rosen <ira.rosen@linaro.org>
2
3 Needs to be merged upstream:
4
5 gcc/
6 * tree-vect-patterns.c (widened_name_p): Rename to ...
7 (type_conversion_p): ... this. Add new argument to determine
8 if it's a promotion or demotion operation. Check for
9 CONVERT_EXPR_CODE_P instead of NOP_EXPR.
10 (vect_recog_dot_prod_pattern): Call type_conversion_p instead
11 widened_name_p.
12 (vect_recog_widen_mult_pattern, vect_recog_widen_sum_pattern,
13 vect_operation_fits_smaller_type, vect_recog_widen_shift_pattern):
14 Likewise.
15 (vect_recog_mixed_size_cond_pattern): Likewise and allow
16 non-constant then and else clauses.
17
18 gcc/testsuite/
19 * gcc.dg/vect/bb-slp-cond-3.c: New test.
20 * gcc.dg/vect/bb-slp-cond-4.c: New test.
21
22=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-cond-3.c'
23--- old/gcc/testsuite/gcc.dg/vect/bb-slp-cond-3.c 1970-01-01 00:00:00 +0000
24+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-cond-3.c 2011-11-27 11:29:32 +0000
25@@ -0,0 +1,85 @@
26+/* { dg-require-effective-target vect_condition } */
27+
28+#include "tree-vect.h"
29+
30+#define N 64
31+
32+/* Comparison in int, then/else and result in unsigned char. */
33+
34+static inline unsigned char
35+foo (int x, int y, int a, int b)
36+{
37+ if (x >= y)
38+ return a;
39+ else
40+ return b;
41+}
42+
43+__attribute__((noinline, noclone)) void
44+bar (unsigned char * __restrict__ a, unsigned char * __restrict__ b,
45+ unsigned char * __restrict__ c, unsigned char * __restrict__ d,
46+ unsigned char * __restrict__ e, int stride, int w)
47+{
48+ int i;
49+ for (i = 0; i < N/stride; i++, a += stride, b += stride, c += stride,
50+ d += stride, e += stride)
51+ {
52+ e[0] = foo (c[0], d[0], a[0] * w, b[0] * w);
53+ e[1] = foo (c[1], d[1], a[1] * w, b[1] * w);
54+ e[2] = foo (c[2], d[2], a[2] * w, b[2] * w);
55+ e[3] = foo (c[3], d[3], a[3] * w, b[3] * w);
56+ e[4] = foo (c[4], d[4], a[4] * w, b[4] * w);
57+ e[5] = foo (c[5], d[5], a[5] * w, b[5] * w);
58+ e[6] = foo (c[6], d[6], a[6] * w, b[6] * w);
59+ e[7] = foo (c[7], d[7], a[7] * w, b[7] * w);
60+ e[8] = foo (c[8], d[8], a[8] * w, b[8] * w);
61+ e[9] = foo (c[9], d[9], a[9] * w, b[9] * w);
62+ e[10] = foo (c[10], d[10], a[10] * w, b[10] * w);
63+ e[11] = foo (c[11], d[11], a[11] * w, b[11] * w);
64+ e[12] = foo (c[12], d[12], a[12] * w, b[12] * w);
65+ e[13] = foo (c[13], d[13], a[13] * w, b[13] * w);
66+ e[14] = foo (c[14], d[14], a[14] * w, b[14] * w);
67+ e[15] = foo (c[15], d[15], a[15] * w, b[15] * w);
68+ }
69+}
70+
71+
72+unsigned char a[N], b[N], c[N], d[N], e[N];
73+
74+int main ()
75+{
76+ int i;
77+
78+ check_vect ();
79+
80+ for (i = 0; i < N; i++)
81+ {
82+ a[i] = i;
83+ b[i] = 5;
84+ e[i] = 0;
85+
86+ switch (i % 9)
87+ {
88+ case 0: asm (""); c[i] = i; d[i] = i + 1; break;
89+ case 1: c[i] = 0; d[i] = 0; break;
90+ case 2: c[i] = i + 1; d[i] = i - 1; break;
91+ case 3: c[i] = i; d[i] = i + 7; break;
92+ case 4: c[i] = i; d[i] = i; break;
93+ case 5: c[i] = i + 16; d[i] = i + 3; break;
94+ case 6: c[i] = i - 5; d[i] = i; break;
95+ case 7: c[i] = i; d[i] = i; break;
96+ case 8: c[i] = i; d[i] = i - 7; break;
97+ }
98+ }
99+
100+ bar (a, b, c, d, e, 16, 2);
101+ for (i = 0; i < N; i++)
102+ if (e[i] != ((i % 3) == 0 ? 10 : 2 * i))
103+ abort ();
104+
105+ return 0;
106+}
107+
108+/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target { vect_element_align && vect_int_mult } } } } */
109+/* { dg-final { cleanup-tree-dump "slp" } } */
110+
111
112=== added file 'gcc/testsuite/gcc.dg/vect/bb-slp-cond-4.c'
113--- old/gcc/testsuite/gcc.dg/vect/bb-slp-cond-4.c 1970-01-01 00:00:00 +0000
114+++ new/gcc/testsuite/gcc.dg/vect/bb-slp-cond-4.c 2011-11-27 11:29:32 +0000
115@@ -0,0 +1,85 @@
116+/* { dg-require-effective-target vect_condition } */
117+
118+#include "tree-vect.h"
119+
120+#define N 64
121+
122+/* Comparison in short, then/else and result in int. */
123+static inline int
124+foo (short x, short y, int a, int b)
125+{
126+ if (x >= y)
127+ return a;
128+ else
129+ return b;
130+}
131+
132+__attribute__((noinline, noclone)) void
133+bar (short * __restrict__ a, short * __restrict__ b,
134+ short * __restrict__ c, short * __restrict__ d,
135+ int * __restrict__ e, int stride, int w)
136+{
137+ int i;
138+ for (i = 0; i < N/stride; i++, a += stride, b += stride, c += stride,
139+ d += stride, e += stride)
140+ {
141+ e[0] = foo (c[0], d[0], a[0], b[0]);
142+ e[1] = foo (c[1], d[1], a[1], b[1]);
143+ e[2] = foo (c[2], d[2], a[2], b[2]);
144+ e[3] = foo (c[3], d[3], a[3], b[3]);
145+ e[4] = foo (c[4], d[4], a[4], b[4]);
146+ e[5] = foo (c[5], d[5], a[5], b[5]);
147+ e[6] = foo (c[6], d[6], a[6], b[6]);
148+ e[7] = foo (c[7], d[7], a[7], b[7]);
149+ e[8] = foo (c[8], d[8], a[8], b[8]);
150+ e[9] = foo (c[9], d[9], a[9], b[9]);
151+ e[10] = foo (c[10], d[10], a[10], b[10]);
152+ e[11] = foo (c[11], d[11], a[11], b[11]);
153+ e[12] = foo (c[12], d[12], a[12], b[12]);
154+ e[13] = foo (c[13], d[13], a[13], b[13]);
155+ e[14] = foo (c[14], d[14], a[14], b[14]);
156+ e[15] = foo (c[15], d[15], a[15], b[15]);
157+ }
158+}
159+
160+
161+short a[N], b[N], c[N], d[N];
162+int e[N];
163+
164+int main ()
165+{
166+ int i;
167+
168+ check_vect ();
169+
170+ for (i = 0; i < N; i++)
171+ {
172+ a[i] = i;
173+ b[i] = 5;
174+ e[i] = 0;
175+
176+ switch (i % 9)
177+ {
178+ case 0: asm (""); c[i] = - i - 1; d[i] = i + 1; break;
179+ case 1: c[i] = 0; d[i] = 0; break;
180+ case 2: c[i] = i + 1; d[i] = - i - 1; break;
181+ case 3: c[i] = i; d[i] = i + 7; break;
182+ case 4: c[i] = i; d[i] = i; break;
183+ case 5: c[i] = i + 16; d[i] = i + 3; break;
184+ case 6: c[i] = - i - 5; d[i] = - i; break;
185+ case 7: c[i] = - i; d[i] = - i; break;
186+ case 8: c[i] = - i; d[i] = - i - 7; break;
187+ }
188+ }
189+
190+ bar (a, b, c, d, e, 16, 2);
191+ for (i = 0; i < N; i++)
192+ if (e[i] != ((i % 3) == 0 ? 5 : i))
193+ abort ();
194+
195+ return 0;
196+}
197+
198+/* { dg-final { scan-tree-dump-times "basic block vectorized using SLP" 1 "slp" { target vect_element_align } } } */
199+/* { dg-final { cleanup-tree-dump "slp" } } */
200+
201
202=== modified file 'gcc/tree-vect-patterns.c'
203--- old/gcc/tree-vect-patterns.c 2011-11-23 07:49:33 +0000
204+++ new/gcc/tree-vect-patterns.c 2011-11-27 12:17:31 +0000
205@@ -62,18 +62,16 @@
206 vect_recog_mixed_size_cond_pattern};
207
208
209-/* Function widened_name_p
210-
211- Check whether NAME, an ssa-name used in USE_STMT,
212- is a result of a type-promotion, such that:
213- DEF_STMT: NAME = NOP (name0)
214- where the type of name0 (HALF_TYPE) is smaller than the type of NAME.
215+/* Check whether NAME, an ssa-name used in USE_STMT,
216+ is a result of a type promotion or demotion, such that:
217+ DEF_STMT: NAME = NOP (name0)
218+ where the type of name0 (ORIG_TYPE) is smaller/bigger than the type of NAME.
219 If CHECK_SIGN is TRUE, check that either both types are signed or both are
220 unsigned. */
221
222 static bool
223-widened_name_p (tree name, gimple use_stmt, tree *half_type, gimple *def_stmt,
224- bool check_sign)
225+type_conversion_p (tree name, gimple use_stmt, bool check_sign,
226+ tree *orig_type, gimple *def_stmt, bool *promotion)
227 {
228 tree dummy;
229 gimple dummy_gimple;
230@@ -96,21 +94,27 @@
231 && dt != vect_external_def && dt != vect_constant_def)
232 return false;
233
234- if (! *def_stmt)
235+ if (!*def_stmt)
236 return false;
237
238 if (!is_gimple_assign (*def_stmt))
239 return false;
240
241- if (gimple_assign_rhs_code (*def_stmt) != NOP_EXPR)
242+ if (!CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (*def_stmt)))
243 return false;
244
245 oprnd0 = gimple_assign_rhs1 (*def_stmt);
246
247- *half_type = TREE_TYPE (oprnd0);
248- if (!INTEGRAL_TYPE_P (type) || !INTEGRAL_TYPE_P (*half_type)
249- || ((TYPE_UNSIGNED (type) != TYPE_UNSIGNED (*half_type)) && check_sign)
250- || (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 2)))
251+ *orig_type = TREE_TYPE (oprnd0);
252+ if (!INTEGRAL_TYPE_P (type) || !INTEGRAL_TYPE_P (*orig_type)
253+ || ((TYPE_UNSIGNED (type) != TYPE_UNSIGNED (*orig_type)) && check_sign))
254+ return false;
255+
256+ if (TYPE_PRECISION (type) >= (TYPE_PRECISION (*orig_type) * 2))
257+ *promotion = true;
258+ else if (TYPE_PRECISION (*orig_type) >= (TYPE_PRECISION (type) * 2))
259+ *promotion = false;
260+ else
261 return false;
262
263 if (!vect_is_simple_use (oprnd0, loop_vinfo, bb_vinfo, &dummy_gimple, &dummy,
264@@ -192,6 +196,7 @@
265 loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
266 struct loop *loop;
267 tree var, rhs;
268+ bool promotion;
269
270 if (!loop_info)
271 return NULL;
272@@ -255,7 +260,9 @@
273 return NULL;
274 stmt = last_stmt;
275
276- if (widened_name_p (oprnd0, stmt, &half_type, &def_stmt, true))
277+ if (type_conversion_p (oprnd0, stmt, true, &half_type, &def_stmt,
278+ &promotion)
279+ && promotion)
280 {
281 stmt = def_stmt;
282 oprnd0 = gimple_assign_rhs1 (stmt);
283@@ -310,10 +317,14 @@
284 if (!types_compatible_p (TREE_TYPE (oprnd0), prod_type)
285 || !types_compatible_p (TREE_TYPE (oprnd1), prod_type))
286 return NULL;
287- if (!widened_name_p (oprnd0, stmt, &half_type0, &def_stmt, true))
288+ if (!type_conversion_p (oprnd0, stmt, true, &half_type0, &def_stmt,
289+ &promotion)
290+ || !promotion)
291 return NULL;
292 oprnd00 = gimple_assign_rhs1 (def_stmt);
293- if (!widened_name_p (oprnd1, stmt, &half_type1, &def_stmt, true))
294+ if (!type_conversion_p (oprnd0, stmt, true, &half_type1, &def_stmt,
295+ &promotion)
296+ || !promotion)
297 return NULL;
298 oprnd01 = gimple_assign_rhs1 (def_stmt);
299 if (!types_compatible_p (half_type0, half_type1))
300@@ -526,7 +537,7 @@
301 enum tree_code dummy_code;
302 int dummy_int;
303 VEC (tree, heap) *dummy_vec;
304- bool op1_ok;
305+ bool op1_ok, promotion;
306
307 if (!is_gimple_assign (last_stmt))
308 return NULL;
309@@ -546,12 +557,14 @@
310 return NULL;
311
312 /* Check argument 0. */
313- if (!widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0, false))
314+ if (!type_conversion_p (oprnd0, last_stmt, false, &half_type0, &def_stmt0,
315+ &promotion)
316+ || !promotion)
317 return NULL;
318- /* Check argument 1. */
319- op1_ok = widened_name_p (oprnd1, last_stmt, &half_type1, &def_stmt1, false);
320-
321- if (op1_ok)
322+ /* Check argument 1. */
323+ op1_ok = type_conversion_p (oprnd1, last_stmt, false, &half_type1,
324+ &def_stmt1, &promotion);
325+ if (op1_ok && promotion)
326 {
327 oprnd0 = gimple_assign_rhs1 (def_stmt0);
328 oprnd1 = gimple_assign_rhs1 (def_stmt1);
329@@ -793,6 +806,7 @@
330 loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
331 struct loop *loop;
332 tree var;
333+ bool promotion;
334
335 if (!loop_info)
336 return NULL;
337@@ -832,8 +846,10 @@
338 Left to check that oprnd0 is defined by a cast from type 'type' to type
339 'TYPE'. */
340
341- if (!widened_name_p (oprnd0, last_stmt, &half_type, &stmt, true))
342- return NULL;
343+ if (!type_conversion_p (oprnd0, last_stmt, true, &half_type, &stmt,
344+ &promotion)
345+ || !promotion)
346+ return NULL;
347
348 oprnd0 = gimple_assign_rhs1 (stmt);
349 *type_in = half_type;
350@@ -899,6 +915,7 @@
351 gimple def_stmt, new_stmt;
352 bool first = false;
353 loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
354+ bool promotion;
355 bb_vec_info bb_info = STMT_VINFO_BB_VINFO (vinfo_for_stmt (stmt));
356 struct loop *loop = NULL;
357
358@@ -933,7 +950,9 @@
359 else
360 {
361 first = true;
362- if (!widened_name_p (oprnd, stmt, &half_type, &def_stmt, false)
363+ if (!type_conversion_p (oprnd, stmt, false, &half_type, &def_stmt,
364+ &promotion)
365+ || !promotion
366 || !gimple_bb (def_stmt)
367 || (loop && !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt)))
368 || (!loop && gimple_bb (def_stmt) != BB_VINFO_BB (bb_info)
369@@ -1327,6 +1346,7 @@
370 VEC (tree, heap) * dummy_vec;
371 gimple use_stmt = NULL;
372 bool over_widen = false;
373+ bool promotion;
374
375 if (!is_gimple_assign (last_stmt) || !vinfo_for_stmt (last_stmt))
376 return NULL;
377@@ -1381,8 +1401,10 @@
378 return NULL;
379
380 /* Check operand 0: it has to be defined by a type promotion. */
381- if (!widened_name_p (oprnd0, last_stmt, &half_type0, &def_stmt0, false))
382- return NULL;
383+ if (!type_conversion_p (oprnd0, last_stmt, false, &half_type0, &def_stmt0,
384+ &promotion)
385+ || !promotion)
386+ return NULL;
387
388 /* Check operand 1: has to be positive. We check that it fits the type
389 in vect_handle_widen_op_by_const (). */
390@@ -1492,9 +1514,9 @@
391 S1 a_T = x_t CMP y_t ? b_T : c_T;
392
393 where type 'TYPE' is an integral type which has different size
394- from 'type'. b_T and c_T are constants and if 'TYPE' is wider
395+ from 'type'. b_T and c_T are either constants (and if 'TYPE' is wider
396 than 'type', the constants need to fit into an integer type
397- with the same width as 'type'.
398+ with the same width as 'type') or results of conversion from 'type'.
399
400 Input:
401
402@@ -1523,6 +1545,9 @@
403 enum machine_mode cmpmode;
404 gimple pattern_stmt, def_stmt;
405 loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
406+ tree orig_type0 = NULL_TREE, orig_type1 = NULL_TREE;
407+ gimple def_stmt0 = NULL, def_stmt1 = NULL;
408+ bool promotion;
409 bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_vinfo);
410
411 if (!is_gimple_assign (last_stmt)
412@@ -1535,25 +1560,40 @@
413 then_clause = TREE_OPERAND (op, 1);
414 else_clause = TREE_OPERAND (op, 2);
415
416- if (TREE_CODE (then_clause) != INTEGER_CST
417- || TREE_CODE (else_clause) != INTEGER_CST)
418- return NULL;
419-
420 if (!COMPARISON_CLASS_P (cond_expr))
421 return NULL;
422
423 type = gimple_expr_type (last_stmt);
424 comp_type = TREE_TYPE (TREE_OPERAND (cond_expr, 0));
425- if (!INTEGRAL_TYPE_P (comp_type)
426- || !INTEGRAL_TYPE_P (type))
427- return NULL;
428-
429 comp_vectype = get_vectype_for_scalar_type (comp_type);
430 if (comp_vectype == NULL_TREE)
431 return NULL;
432
433+ if (types_compatible_p (type, comp_type)
434+ || !INTEGRAL_TYPE_P (comp_type)
435+ || !INTEGRAL_TYPE_P (type))
436+ return NULL;
437+
438+ if ((TREE_CODE (then_clause) != INTEGER_CST
439+ && !type_conversion_p (then_clause, last_stmt, false, &orig_type0,
440+ &def_stmt0, &promotion))
441+ || (TREE_CODE (else_clause) != INTEGER_CST
442+ && !type_conversion_p (else_clause, last_stmt, false, &orig_type1,
443+ &def_stmt1, &promotion)))
444+ return NULL;
445+
446+ if (orig_type0 && orig_type1
447+ && (!types_compatible_p (orig_type0, orig_type1)
448+ || !types_compatible_p (orig_type0, comp_type)))
449+ return NULL;
450+
451+ if (orig_type0)
452+ then_clause = gimple_assign_rhs1 (def_stmt0);
453+
454+ if (orig_type1)
455+ else_clause = gimple_assign_rhs1 (def_stmt1);
456+
457 cmpmode = GET_MODE_INNER (TYPE_MODE (comp_vectype));
458-
459 if (GET_MODE_BITSIZE (TYPE_MODE (type)) == GET_MODE_BITSIZE (cmpmode))
460 return NULL;
461
462@@ -1561,18 +1601,15 @@
463 if (vectype == NULL_TREE)
464 return NULL;
465
466- if (types_compatible_p (vectype, comp_vectype))
467- return NULL;
468-
469 if (!expand_vec_cond_expr_p (comp_vectype, TYPE_MODE (comp_vectype)))
470 return NULL;
471
472- if (GET_MODE_BITSIZE (TYPE_MODE (type)) > GET_MODE_BITSIZE (cmpmode))
473- {
474- if (!int_fits_type_p (then_clause, comp_type)
475- || !int_fits_type_p (else_clause, comp_type))
476- return NULL;
477- }
478+ if (GET_MODE_BITSIZE (TYPE_MODE (type)) > GET_MODE_BITSIZE (cmpmode)
479+ && ((TREE_CODE (then_clause) == INTEGER_CST
480+ && !int_fits_type_p (then_clause, comp_type))
481+ || (TREE_CODE (else_clause) == INTEGER_CST
482+ && !int_fits_type_p (else_clause, comp_type))))
483+ return NULL;
484
485 tmp = build3 (COND_EXPR, comp_type, unshare_expr (cond_expr),
486 fold_convert (comp_type, then_clause),
487
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106848.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106848.patch
deleted file mode 100644
index 43a2a4da9..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106848.patch
+++ /dev/null
@@ -1,276 +0,0 @@
12011-12-05 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline -A15 tuning.
4 2011-11-30 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
5
6 * config/arm/arm.c (arm_issue_rate): Cortex-A15 can triple issue.
7 * config/arm/arm.md (mul64): New attribute.
8 (generic_sched): Cortex-A15 is not scheduled generically.
9 (cortex-a15.md): Include.
10 * config/arm/cortex-a15.md: New machine description.
11 * config/arm/t-arm (MD_INCLUDES): Add cortex-a15.md.
12
13 2011-11-30 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
14 * config/arm/t-arm (MD_INCLUDES): Ensure all md files are listed.
15
16=== modified file 'gcc/config/arm/arm.c'
17--- old/gcc/config/arm/arm.c 2011-12-05 10:55:48 +0000
18+++ new/gcc/config/arm/arm.c 2011-12-05 12:33:25 +0000
19@@ -24056,6 +24056,9 @@
20 {
21 switch (arm_tune)
22 {
23+ case cortexa15:
24+ return 3;
25+
26 case cortexr4:
27 case cortexr4f:
28 case cortexr5:
29
30=== modified file 'gcc/config/arm/arm.md'
31--- old/gcc/config/arm/arm.md 2011-10-26 11:38:30 +0000
32+++ new/gcc/config/arm/arm.md 2011-12-02 00:38:59 +0000
33@@ -345,6 +345,13 @@
34 (const_string "mult")
35 (const_string "alu")))
36
37+; Is this an (integer side) multiply with a 64-bit result?
38+(define_attr "mul64" "no,yes"
39+ (if_then_else
40+ (eq_attr "insn" "smlalxy,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
41+ (const_string "yes")
42+ (const_string "no")))
43+
44 ; Load scheduling, set from the arm_ld_sched variable
45 ; initialized by arm_option_override()
46 (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
47@@ -511,7 +518,7 @@
48
49 (define_attr "generic_sched" "yes,no"
50 (const (if_then_else
51- (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4")
52+ (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexa15,cortexm4")
53 (eq_attr "tune_cortexr4" "yes"))
54 (const_string "no")
55 (const_string "yes"))))
56@@ -537,6 +544,7 @@
57 (include "cortex-a5.md")
58 (include "cortex-a8.md")
59 (include "cortex-a9.md")
60+(include "cortex-a15.md")
61 (include "cortex-r4.md")
62 (include "cortex-r4f.md")
63 (include "cortex-m4.md")
64
65=== added file 'gcc/config/arm/cortex-a15.md'
66--- old/gcc/config/arm/cortex-a15.md 1970-01-01 00:00:00 +0000
67+++ new/gcc/config/arm/cortex-a15.md 2011-12-02 00:38:59 +0000
68@@ -0,0 +1,186 @@
69+;; ARM Cortex-A15 pipeline description
70+;; Copyright (C) 2011 Free Software Foundation, Inc.
71+;;
72+;; Written by Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
73+
74+;; This file is part of GCC.
75+;;
76+;; GCC is free software; you can redistribute it and/or modify it
77+;; under the terms of the GNU General Public License as published by
78+;; the Free Software Foundation; either version 3, or (at your option)
79+;; any later version.
80+;;
81+;; GCC is distributed in the hope that it will be useful, but
82+;; WITHOUT ANY WARRANTY; without even the implied warranty of
83+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
84+;; General Public License for more details.
85+;;
86+;; You should have received a copy of the GNU General Public License
87+;; along with GCC; see the file COPYING3. If not see
88+;; <http://www.gnu.org/licenses/>.
89+
90+(define_automaton "cortex_a15")
91+
92+;; The Cortex-A15 core is modelled as a triple issue pipeline that has
93+;; the following dispatch units.
94+;; 1. Two pipelines for simple integer operations: SX1, SX2
95+;; 2. Two pipelines for Neon and FP data-processing operations: CX1, CX2
96+;; 3. One pipeline for branch operations: BX
97+;; 4. One pipeline for integer multiply and divide operations: MX
98+;; 5. Two pipelines for load and store operations: LS1, LS2
99+;;
100+;; We can issue into three pipelines per-cycle.
101+;;
102+;; We assume that where we have unit pairs xx1 is always filled before xx2.
103+
104+;; The three issue units
105+(define_cpu_unit "ca15_i0, ca15_i1, ca15_i2" "cortex_a15")
106+
107+(define_reservation "ca15_issue1" "(ca15_i0|ca15_i1|ca15_i2)")
108+(define_reservation "ca15_issue2" "((ca15_i0+ca15_i1)|(ca15_i1+ca15_i2))")
109+(define_reservation "ca15_issue3" "(ca15_i0+ca15_i1+ca15_i2)")
110+(final_presence_set "ca15_i1" "ca15_i0")
111+(final_presence_set "ca15_i2" "ca15_i1")
112+
113+;; The main dispatch units
114+(define_cpu_unit "ca15_sx1, ca15_sx2" "cortex_a15")
115+(define_cpu_unit "ca15_cx1, ca15_cx2" "cortex_a15")
116+(define_cpu_unit "ca15_ls1, ca15_ls2" "cortex_a15")
117+(define_cpu_unit "ca15_bx, ca15_mx" "cortex_a15")
118+
119+(define_reservation "ca15_ls" "(ca15_ls1|ca15_ls2)")
120+
121+;; The extended load-store pipeline
122+(define_cpu_unit "ca15_ldr, ca15_str" "cortex_a15")
123+
124+;; The extended ALU pipeline
125+(define_cpu_unit "ca15_sx1_alu, ca15_sx1_shf, ca15_sx1_sat" "cortex_a15")
126+(define_cpu_unit "ca15_sx2_alu, ca15_sx2_shf, ca15_sx2_sat" "cortex_a15")
127+
128+;; Simple Execution Unit:
129+;;
130+;; Simple ALU without shift
131+(define_insn_reservation "cortex_a15_alu" 2
132+ (and (eq_attr "tune" "cortexa15")
133+ (and (eq_attr "type" "alu")
134+ (eq_attr "neon_type" "none")))
135+ "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
136+
137+;; ALU ops with immediate shift
138+(define_insn_reservation "cortex_a15_alu_shift" 3
139+ (and (eq_attr "tune" "cortexa15")
140+ (and (eq_attr "type" "alu_shift")
141+ (eq_attr "neon_type" "none")))
142+ "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
143+ |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
144+
145+;; ALU ops with register controlled shift
146+(define_insn_reservation "cortex_a15_alu_shift_reg" 3
147+ (and (eq_attr "tune" "cortexa15")
148+ (and (eq_attr "type" "alu_shift_reg")
149+ (eq_attr "neon_type" "none")))
150+ "(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
151+ |(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\
152+ |(ca15_issue1+ca15_sx1,ca15_sx1+ca15_sx1_shf),ca15_sx1_alu)")
153+
154+;; Multiply Execution Unit:
155+;;
156+;; 32-bit multiplies
157+(define_insn_reservation "cortex_a15_mult32" 3
158+ (and (eq_attr "tune" "cortexa15")
159+ (and (eq_attr "type" "mult")
160+ (and (eq_attr "neon_type" "none")
161+ (eq_attr "mul64" "no"))))
162+ "ca15_issue1,ca15_mx")
163+
164+;; 64-bit multiplies
165+(define_insn_reservation "cortex_a15_mult64" 4
166+ (and (eq_attr "tune" "cortexa15")
167+ (and (eq_attr "type" "mult")
168+ (and (eq_attr "neon_type" "none")
169+ (eq_attr "mul64" "yes"))))
170+ "ca15_issue1,ca15_mx*2")
171+
172+;; Integer divide
173+(define_insn_reservation "cortex_a15_udiv" 9
174+ (and (eq_attr "tune" "cortexa15")
175+ (eq_attr "insn" "udiv"))
176+ "ca15_issue1,ca15_mx")
177+
178+(define_insn_reservation "cortex_a15_sdiv" 10
179+ (and (eq_attr "tune" "cortexa15")
180+ (eq_attr "insn" "sdiv"))
181+ "ca15_issue1,ca15_mx")
182+
183+;; Block all issue pipes for a cycle
184+(define_insn_reservation "cortex_a15_block" 1
185+ (and (eq_attr "tune" "cortexa15")
186+ (and (eq_attr "type" "block")
187+ (eq_attr "neon_type" "none")))
188+ "ca15_issue3")
189+
190+;; Branch execution Unit
191+;;
192+;; Branches take one issue slot.
193+;; No latency as there is no result
194+(define_insn_reservation "cortex_a15_branch" 0
195+ (and (eq_attr "tune" "cortexa15")
196+ (and (eq_attr "type" "branch")
197+ (eq_attr "neon_type" "none")))
198+ "ca15_issue1,ca15_bx")
199+
200+
201+;; We lie with calls. They take up all issue slots, and form a block in the
202+;; pipeline. The result however is available the next cycle.
203+;;
204+;; Addition of new units requires this to be updated.
205+(define_insn_reservation "cortex_a15_call" 1
206+ (and (eq_attr "tune" "cortexa15")
207+ (and (eq_attr "type" "call")
208+ (eq_attr "neon_type" "none")))
209+ "ca15_issue3,\
210+ ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx1+ca15_cx2+ca15_ls1+ca15_ls2,\
211+ ca15_sx1_alu+ca15_sx1_shf+ca15_sx1_sat+ca15_sx2_alu+ca15_sx2_shf\
212+ +ca15_sx2_sat+ca15_ldr+ca15_str")
213+
214+;; Load-store execution Unit
215+;;
216+;; Loads of up to two words.
217+(define_insn_reservation "cortex_a15_load1" 4
218+ (and (eq_attr "tune" "cortexa15")
219+ (and (eq_attr "type" "load_byte,load1,load2")
220+ (eq_attr "neon_type" "none")))
221+ "ca15_issue1,ca15_ls,ca15_ldr,nothing")
222+
223+;; Loads of three or four words.
224+(define_insn_reservation "cortex_a15_load3" 5
225+ (and (eq_attr "tune" "cortexa15")
226+ (and (eq_attr "type" "load3,load4")
227+ (eq_attr "neon_type" "none")))
228+ "ca15_issue2,ca15_ls1+ca15_ls2,ca15_ldr,ca15_ldr,nothing")
229+
230+;; Stores of up to two words.
231+(define_insn_reservation "cortex_a15_store1" 0
232+ (and (eq_attr "tune" "cortexa15")
233+ (and (eq_attr "type" "store1,store2")
234+ (eq_attr "neon_type" "none")))
235+ "ca15_issue1,ca15_ls,ca15_str")
236+
237+;; Stores of three or four words.
238+(define_insn_reservation "cortex_a15_store3" 0
239+ (and (eq_attr "tune" "cortexa15")
240+ (and (eq_attr "type" "store3,store4")
241+ (eq_attr "neon_type" "none")))
242+ "ca15_issue2,ca15_ls1+ca15_ls2,ca15_str,ca15_str")
243+
244+;; Simple execution unit bypasses
245+(define_bypass 1 "cortex_a15_alu"
246+ "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")
247+(define_bypass 2 "cortex_a15_alu_shift"
248+ "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")
249+(define_bypass 2 "cortex_a15_alu_shift_reg"
250+ "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")
251+(define_bypass 1 "cortex_a15_alu" "cortex_a15_load1,cortex_a15_load3")
252+(define_bypass 2 "cortex_a15_alu_shift" "cortex_a15_load1,cortex_a15_load3")
253+(define_bypass 2 "cortex_a15_alu_shift_reg"
254+ "cortex_a15_load1,cortex_a15_load3")
255
256=== modified file 'gcc/config/arm/t-arm'
257--- old/gcc/config/arm/t-arm 2011-01-03 20:52:22 +0000
258+++ new/gcc/config/arm/t-arm 2011-12-02 00:38:59 +0000
259@@ -31,6 +31,16 @@
260 $(srcdir)/config/arm/fmp626.md \
261 $(srcdir)/config/arm/fa726te.md \
262 $(srcdir)/config/arm/arm926ejs.md \
263+ $(srcdir)/config/arm/cortex-a15.md \
264+ $(srcdir)/config/arm/cortex-a5.md \
265+ $(srcdir)/config/arm/cortex-a8.md \
266+ $(srcdir)/config/arm/cortex-a8-neon.md \
267+ $(srcdir)/config/arm/cortex-a9.md \
268+ $(srcdir)/config/arm/cortex-a9-neon.md \
269+ $(srcdir)/config/arm/cortex-m4-fpu.md \
270+ $(srcdir)/config/arm/cortex-m4.md \
271+ $(srcdir)/config/arm/cortex-r4f.md \
272+ $(srcdir)/config/arm/cortex-r4.md \
273 $(srcdir)/config/arm/cirrus.md \
274 $(srcdir)/config/arm/fpa.md \
275 $(srcdir)/config/arm/vec-common.md \
276
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106853.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106853.patch
deleted file mode 100644
index 8c51c1d1f..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106853.patch
+++ /dev/null
@@ -1,69 +0,0 @@
12011-12-20 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from mainline:
4
5 2011-11-29 Ira Rosen <ira.rosen@linaro.org>
6
7 PR tree-optimization/51301
8 gcc/
9 * tree-vect-patterns.c (vect_recog_over_widening_pattern): Check that
10 the last statement doesn't convert to a bigger type than the original
11 type of the computation.
12
13 gcc/testsuite/
14 * gcc.dg/vect/pr51301.c: New test.
15
16=== added file 'gcc/testsuite/gcc.dg/vect/pr51301.c'
17--- old/gcc/testsuite/gcc.dg/vect/pr51301.c 1970-01-01 00:00:00 +0000
18+++ new/gcc/testsuite/gcc.dg/vect/pr51301.c 2011-11-30 17:54:51 +0000
19@@ -0,0 +1,15 @@
20+/* { dg-do compile } */
21+
22+typedef signed char int8_t;
23+typedef signed long long int64_t;
24+int64_t
25+f0a (int8_t * __restrict__ arg1)
26+{
27+ int idx;
28+ int64_t result = 0;
29+ for (idx = 0; idx < 416; idx += 1)
30+ result += arg1[idx] << (arg1[idx] == arg1[idx]);
31+ return result;
32+}
33+
34+/* { dg-final { cleanup-tree-dump "vect" } } */
35
36=== modified file 'gcc/tree-vect-patterns.c'
37--- old/gcc/tree-vect-patterns.c 2011-11-27 12:17:31 +0000
38+++ new/gcc/tree-vect-patterns.c 2011-12-20 07:47:44 +0000
39@@ -1138,6 +1138,7 @@
40 struct loop *loop = NULL;
41 bb_vec_info bb_vinfo;
42 stmt_vec_info stmt_vinfo;
43+ tree type = NULL;
44
45 stmt_vinfo = vinfo_for_stmt (stmt);
46 loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo);
47@@ -1207,6 +1208,7 @@
48 print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
49 }
50
51+ type = gimple_expr_type (stmt);
52 prev_stmt = stmt;
53 stmt = use_stmt;
54
55@@ -1222,9 +1224,11 @@
56 {
57 use_lhs = gimple_assign_lhs (use_stmt);
58 use_type = TREE_TYPE (use_lhs);
59- /* Support only type promotion or signedess change. */
60+ /* Support only type promotion or signedess change. Check that USE_TYPE
61+ is not bigger than the original type. */
62 if (!INTEGRAL_TYPE_P (use_type)
63- || TYPE_PRECISION (new_type) > TYPE_PRECISION (use_type))
64+ || TYPE_PRECISION (new_type) > TYPE_PRECISION (use_type)
65+ || TYPE_PRECISION (type) < TYPE_PRECISION (use_type))
66 return NULL;
67
68 if (TYPE_UNSIGNED (new_type) != TYPE_UNSIGNED (use_type)
69
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106855.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106855.patch
deleted file mode 100644
index c433fc73f..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106855.patch
+++ /dev/null
@@ -1,22 +0,0 @@
12012-01-05 Michael Hope <michael.hope@linaro.org>
2
3 Backport from mainline r182271:
4
5 2011-12-13 Revital Eres <revital.eres@linaro.org>
6
7 gcc/
8 * modulo-sched.c (mark_loop_unsched): Free bbs.
9
10=== modified file 'gcc/modulo-sched.c'
11--- old/gcc/modulo-sched.c 2011-10-30 05:31:00 +0000
12+++ new/gcc/modulo-sched.c 2012-01-05 02:45:23 +0000
13@@ -1204,6 +1204,8 @@
14
15 for (i = 0; i < loop->num_nodes; i++)
16 bbs[i]->flags |= BB_DISABLE_SCHEDULE;
17+
18+ free (bbs);
19 }
20
21 /* Return true if all the BBs of the loop are empty except the
22
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106860.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106860.patch
deleted file mode 100644
index 895d6a6cf..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106860.patch
+++ /dev/null
@@ -1,104 +0,0 @@
12012-01-12 Ulrich Weigand <ulrich.weigand@linaro.org>
2
3 LP 879725
4 Backport from mainline:
5
6 2012-01-02 Revital Eres <revital.eres@linaro.org>
7
8 gcc/
9 * ddg.c (def_has_ccmode_p): New function.
10 (add_cross_iteration_register_deps,
11 create_ddg_dep_from_intra_loop_link): Call it.
12
13 gcc/testsuite/
14 * gcc.dg/sms-11.c: New file.
15
16=== modified file 'gcc/ddg.c'
17--- old/gcc/ddg.c 2011-10-02 06:56:53 +0000
18+++ new/gcc/ddg.c 2012-01-10 16:05:14 +0000
19@@ -166,6 +166,24 @@
20 return false;
21 }
22
23+/* Return true if one of the definitions in INSN has MODE_CC. Otherwise
24+ return false. */
25+static bool
26+def_has_ccmode_p (rtx insn)
27+{
28+ df_ref *def;
29+
30+ for (def = DF_INSN_DEFS (insn); *def; def++)
31+ {
32+ enum machine_mode mode = GET_MODE (DF_REF_REG (*def));
33+
34+ if (GET_MODE_CLASS (mode) == MODE_CC)
35+ return true;
36+ }
37+
38+ return false;
39+}
40+
41 /* Computes the dependence parameters (latency, distance etc.), creates
42 a ddg_edge and adds it to the given DDG. */
43 static void
44@@ -202,6 +220,7 @@
45 whose register has multiple defs in the loop. */
46 if (flag_modulo_sched_allow_regmoves
47 && (t == ANTI_DEP && dt == REG_DEP)
48+ && !def_has_ccmode_p (dest_node->insn)
49 && !autoinc_var_is_used_p (dest_node->insn, src_node->insn))
50 {
51 rtx set;
52@@ -335,7 +354,8 @@
53 if (DF_REF_ID (last_def) != DF_REF_ID (first_def)
54 || !flag_modulo_sched_allow_regmoves
55 || JUMP_P (use_node->insn)
56- || autoinc_var_is_used_p (DF_REF_INSN (last_def), use_insn))
57+ || autoinc_var_is_used_p (DF_REF_INSN (last_def), use_insn)
58+ || def_has_ccmode_p (DF_REF_INSN (last_def)))
59 create_ddg_dep_no_link (g, use_node, first_def_node, ANTI_DEP,
60 REG_DEP, 1);
61
62
63=== added file 'gcc/testsuite/gcc.dg/sms-11.c'
64--- old/gcc/testsuite/gcc.dg/sms-11.c 1970-01-01 00:00:00 +0000
65+++ new/gcc/testsuite/gcc.dg/sms-11.c 2012-01-10 16:05:14 +0000
66@@ -0,0 +1,37 @@
67+/* { dg-do run } */
68+/* { dg-options "-O2 -fmodulo-sched -fmodulo-sched-allow-regmoves -fdump-rtl-sms" } */
69+
70+extern void abort (void);
71+
72+float out[4][4] = { 6, 6, 7, 5, 6, 7, 5, 5, 6, 4, 4, 4, 6, 2, 3, 4 };
73+
74+void
75+invert (void)
76+{
77+ int i, j, k = 0, swap;
78+ float tmp[4][4] = { 5, 6, 7, 5, 6, 7, 5, 5, 4, 4, 4, 4, 3, 2, 3, 4 };
79+
80+ for (i = 0; i < 4; i++)
81+ {
82+ for (j = i + 1; j < 4; j++)
83+ if (tmp[j][i] > tmp[i][i])
84+ swap = j;
85+
86+ if (swap != i)
87+ tmp[i][k] = tmp[swap][k];
88+ }
89+
90+ for (i = 0; i < 4; i++)
91+ for (j = 0; j < 4; j++)
92+ if (tmp[i][j] != out[i][j])
93+ abort ();
94+}
95+
96+int
97+main ()
98+{
99+ invert ();
100+ return 0;
101+}
102+
103+/* { dg-final { cleanup-rtl-dump "sms" } } */
104
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106861.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106861.patch
deleted file mode 100644
index 0199f7b89..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106861.patch
+++ /dev/null
@@ -1,76 +0,0 @@
12012-01-18 Michael Hope <michael.hope@linaro.org>
2
3 Backport from mainline r183126:
4
5 2012-01-12 Ira Rosen <irar@il.ibm.com>
6
7 gcc/
8 PR tree-optimization/51799
9 * tree-vect-patterns.c (vect_recog_over_widening_pattern): Check
10 that the last operation is a type demotion.
11
12 gcc/testsuite/
13 * gcc.dg/vect/pr51799.c: New test.
14 * gcc.dg/vect/vect-widen-shift-u8.c: Expect two widening shift
15 patterns.
16
17=== added file 'gcc/testsuite/gcc.dg/vect/pr51799.c'
18--- old/gcc/testsuite/gcc.dg/vect/pr51799.c 1970-01-01 00:00:00 +0000
19+++ new/gcc/testsuite/gcc.dg/vect/pr51799.c 2012-01-18 01:53:19 +0000
20@@ -0,0 +1,18 @@
21+/* { dg-do compile } */
22+
23+typedef signed char int8_t;
24+typedef unsigned char uint8_t;
25+typedef signed short int16_t;
26+typedef unsigned long uint32_t;
27+void
28+f0a (uint32_t * __restrict__ result, int8_t * __restrict__ arg1,
29+ uint32_t * __restrict__ arg4, int8_t temp_6)
30+{
31+ int idx;
32+ for (idx = 0; idx < 416; idx += 1)
33+ {
34+ result[idx] = (uint8_t)(((arg1[idx] << 7) + arg4[idx]) * temp_6);
35+ }
36+}
37+
38+/* { dg-final { cleanup-tree-dump "vect" } } */
39
40=== modified file 'gcc/testsuite/gcc.dg/vect/vect-widen-shift-u8.c'
41--- old/gcc/testsuite/gcc.dg/vect/vect-widen-shift-u8.c 2011-10-23 13:33:07 +0000
42+++ new/gcc/testsuite/gcc.dg/vect/vect-widen-shift-u8.c 2012-01-18 01:53:19 +0000
43@@ -59,7 +59,6 @@
44 return 0;
45 }
46
47-/* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 1 "vect" { target vect_widen_shift } } } */
48+/* { dg-final { scan-tree-dump-times "vect_recog_widen_shift_pattern: detected" 2 "vect" { target vect_widen_shift } } } */
49 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
50 /* { dg-final { cleanup-tree-dump "vect" } } */
51-
52
53=== modified file 'gcc/tree-vect-patterns.c'
54--- old/gcc/tree-vect-patterns.c 2011-12-20 07:47:44 +0000
55+++ new/gcc/tree-vect-patterns.c 2012-01-18 01:53:19 +0000
56@@ -1224,13 +1224,15 @@
57 {
58 use_lhs = gimple_assign_lhs (use_stmt);
59 use_type = TREE_TYPE (use_lhs);
60- /* Support only type promotion or signedess change. Check that USE_TYPE
61- is not bigger than the original type. */
62+ /* Support only type demotion or signedess change. */
63 if (!INTEGRAL_TYPE_P (use_type)
64- || TYPE_PRECISION (new_type) > TYPE_PRECISION (use_type)
65- || TYPE_PRECISION (type) < TYPE_PRECISION (use_type))
66+ || TYPE_PRECISION (type) <= TYPE_PRECISION (use_type))
67 return NULL;
68
69+ /* Check that NEW_TYPE is not bigger than the conversion result. */
70+ if (TYPE_PRECISION (new_type) > TYPE_PRECISION (use_type))
71+ return NULL;
72+
73 if (TYPE_UNSIGNED (new_type) != TYPE_UNSIGNED (use_type)
74 || TYPE_PRECISION (new_type) != TYPE_PRECISION (use_type))
75 {
76
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106862.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106862.patch
deleted file mode 100644
index a20d889a5..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106862.patch
+++ /dev/null
@@ -1,45 +0,0 @@
12012-01-16 Michael Hope <michael.hope@linaro.org>
2
3 Backport from mainline r183011:
4
5 2012-01-09 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
6
7 * config/arm/arm-cores.def (cortex-a15): Use cortex_a15_tune for
8 tuning parameters.
9 * config/arm/arm.c (arm_cortex_a15_tune): New static variable.
10
11=== modified file 'gcc/config/arm/arm-cores.def'
12--- old/gcc/config/arm/arm-cores.def 2011-10-19 16:46:51 +0000
13+++ new/gcc/config/arm/arm-cores.def 2012-01-15 22:02:31 +0000
14@@ -128,7 +128,7 @@
15 ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5)
16 ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex)
17 ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9)
18-ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
19+ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
20 ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex)
21 ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex)
22 ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex)
23
24=== modified file 'gcc/config/arm/arm.c'
25--- old/gcc/config/arm/arm.c 2012-01-05 15:35:39 +0000
26+++ new/gcc/config/arm/arm.c 2012-01-15 22:02:31 +0000
27@@ -983,6 +983,17 @@
28 arm_default_branch_cost
29 };
30
31+const struct tune_params arm_cortex_a15_tune =
32+{
33+ arm_9e_rtx_costs,
34+ NULL,
35+ 1, /* Constant limit. */
36+ 1, /* Max cond insns. */
37+ ARM_PREFETCH_NOT_BENEFICIAL, /* TODO: Calculate correct values. */
38+ false, /* Prefer constant pool. */
39+ arm_cortex_a5_branch_cost
40+};
41+
42 const struct tune_params arm_fa726te_tune =
43 {
44 arm_9e_rtx_costs,
45
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106863.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106863.patch
deleted file mode 100644
index e93493f17..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106863.patch
+++ /dev/null
@@ -1,47 +0,0 @@
1 2012-01-16 Michael Hope <michael.hope@linaro.org>
2
3 Backport from mainline r182561:
4
5 2011-12-20 Richard Henderson <rth@redhat.com>
6
7 gcc/
8 * config/arm/arm.md (*arm_cmpdi_unsigned): Enable for thumb2.
9 * config/arm/arm.c (arm_select_cc_mode): Use it.
10
11=== modified file 'gcc/config/arm/arm.c'
12--- old/gcc/config/arm/arm.c 2012-01-15 22:02:31 +0000
13+++ new/gcc/config/arm/arm.c 2012-01-23 00:06:27 +0000
14@@ -11602,7 +11602,7 @@
15 return CC_Zmode;
16
17 /* We can do an equality test in three Thumb instructions. */
18- if (!TARGET_ARM)
19+ if (!TARGET_32BIT)
20 return CC_Zmode;
21
22 /* FALLTHROUGH */
23@@ -11614,7 +11614,7 @@
24 /* DImode unsigned comparisons can be implemented by cmp +
25 cmpeq without a scratch register. Not worth doing in
26 Thumb-2. */
27- if (TARGET_ARM)
28+ if (TARGET_32BIT)
29 return CC_CZmode;
30
31 /* FALLTHROUGH */
32
33=== modified file 'gcc/config/arm/arm.md'
34--- old/gcc/config/arm/arm.md 2012-01-05 15:35:39 +0000
35+++ new/gcc/config/arm/arm.md 2012-01-15 21:02:00 +0000
36@@ -7515,8 +7515,8 @@
37 [(set (reg:CC_CZ CC_REGNUM)
38 (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r")
39 (match_operand:DI 1 "arm_di_operand" "rDi")))]
40- "TARGET_ARM"
41- "cmp%?\\t%R0, %R1\;cmpeq\\t%Q0, %Q1"
42+ "TARGET_32BIT"
43+ "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1"
44 [(set_attr "conds" "set")
45 (set_attr "length" "8")]
46 )
47
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106864.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106864.patch
deleted file mode 100644
index f15f37a58..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106864.patch
+++ /dev/null
@@ -1,63 +0,0 @@
1 2012-01-16 Michael Hope <michael.hope@linaro.org>
2
3 Backport from mainline r181210:
4
5 gcc/
6 2011-11-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
7
8 * config/arm/arm-cores.def: Add -mcpu=cortex-a7.
9 * config/arm/arm-tables.opt: Regenerate.
10 * config/arm/arm-tune.md: Likewise.
11 * config/arm/bpabi.h (BE8_LINK_SPEC): Add Cortex A-7.
12 * doc/invoke.texi: Document -mcpu=cortex-a7.
13
14=== modified file 'gcc/config/arm/arm-cores.def'
15--- old/gcc/config/arm/arm-cores.def 2012-01-15 22:02:31 +0000
16+++ new/gcc/config/arm/arm-cores.def 2012-01-23 00:36:02 +0000
17@@ -126,6 +126,7 @@
18 ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, v6t2)
19 ARM_CORE("generic-armv7-a", genericv7a, 7A, FL_LDSCHED, cortex)
20 ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5)
21+ARM_CORE("cortex-a7", cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
22 ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex)
23 ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9)
24 ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
25
26=== modified file 'gcc/config/arm/arm-tune.md'
27--- old/gcc/config/arm/arm-tune.md 2011-10-19 16:46:51 +0000
28+++ new/gcc/config/arm/arm-tune.md 2012-01-15 22:43:29 +0000
29@@ -1,5 +1,5 @@
30 ;; -*- buffer-read-only: t -*-
31 ;; Generated automatically by gentune.sh from arm-cores.def
32 (define_attr "tune"
33- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
34+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0"
35 (const (symbol_ref "((enum attr_tune) arm_tune)")))
36
37=== modified file 'gcc/config/arm/bpabi.h'
38--- old/gcc/config/arm/bpabi.h 2011-11-02 21:02:53 +0000
39+++ new/gcc/config/arm/bpabi.h 2012-01-15 22:43:29 +0000
40@@ -56,6 +56,7 @@
41 "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}"
42
43 #define BE8_LINK_SPEC " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5"\
44+ "|mcpu=cortex-a7"\
45 "|mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15|mcpu=generic-armv7-a"\
46 ":%{!r:--be8}}}"
47
48
49=== modified file 'gcc/doc/invoke.texi'
50--- old/gcc/doc/invoke.texi 2012-01-05 15:35:39 +0000
51+++ new/gcc/doc/invoke.texi 2012-01-15 22:43:29 +0000
52@@ -10202,8 +10202,8 @@
53 @samp{arm10e}, @samp{arm1020e}, @samp{arm1022e},
54 @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
55 @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
56-@samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a15},
57-@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
58+@samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9},
59+@samp{cortex-a15}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
60 @samp{cortex-m4}, @samp{cortex-m3},
61 @samp{cortex-m1},
62 @samp{cortex-m0},
63
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106865.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106865.patch
deleted file mode 100644
index 5b0735b00..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106865.patch
+++ /dev/null
@@ -1,25 +0,0 @@
12012-01-20 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline
4 2012-01-20 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
5
6 PR target/51819
7 * config/arm/arm.c (arm_print_operand): Correct output of alignment
8 hints for neon loads and stores.
9
10=== modified file 'gcc/config/arm/arm.c'
11--- old/gcc/config/arm/arm.c 2012-01-23 00:06:27 +0000
12+++ new/gcc/config/arm/arm.c 2012-01-23 18:54:21 +0000
13@@ -17463,9 +17463,9 @@
14 /* Only certain alignment specifiers are supported by the hardware. */
15 if (memsize == 16 && (align % 32) == 0)
16 align_bits = 256;
17- else if ((memsize == 8 || memsize == 16) && (align % 16) == 0)
18+ else if (memsize == 16 && (align % 16) == 0)
19 align_bits = 128;
20- else if ((align % 8) == 0)
21+ else if (memsize >= 8 && (align % 8) == 0)
22 align_bits = 64;
23 else
24 align_bits = 0;
25
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106869.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106869.patch
deleted file mode 100644
index de3d2ff4c..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106869.patch
+++ /dev/null
@@ -1,2389 +0,0 @@
12012-02-08 Ulrich Weigand <ulrich.weigand@linaro.org>
2
3 gcc/
4 * config/arm/arm.c (arm_option_optimization_table): Enable
5 -fsched-pressure using -fsched-pressure-algorithm=model by
6 default when optimizing.
7
82012-02-08 Richard Sandiford <richard.sandiford@linaro.org>
9
10 gcc/
11 * sched-deps.c (fixup_sched_groups): Rename to...
12 (chain_to_prev_insn): ...this.
13 (chain_to_prev_insn_p): New function.
14 (deps_analyze_insn): Use it instead of SCHED_GROUP_P.
15
162012-02-08 Richard Sandiford <richard.sandiford@linaro.org>
17
18 gcc/
19 * sched-int.h (_haifa_insn_data): Move priority_status.
20 Add model_index.
21 (INSN_MODEL_INDEX): New macro.
22 * haifa-sched.c (insn_delay): New function.
23 (sched_regno_pressure_class): Update commentary.
24 (mark_regno_birth_or_death): Pass the liveness bitmap and
25 pressure array as arguments, instead of using curr_reg_live and
26 curr_reg_pressure. Only update the pressure if the bit in the
27 liveness set has changed.
28 (initiate_reg_pressure_info): Always trust the live-in set for
29 SCHED_PRESSURE_MODEL.
30 (initiate_bb_reg_pressure_info): Update call to
31 mark_regno_birth_or_death.
32 (dep_list_size): Take the list as argument.
33 (calculate_reg_deaths): New function, extracted from...
34 (setup_insn_reg_pressure_info): ...here.
35 (MODEL_BAR): New macro.
36 (model_pressure_data, model_insn_info, model_pressure_limit)
37 (model_pressure_group): New structures.
38 (model_schedule, model_worklist, model_insns, model_num_insns)
39 (model_curr_point, model_before_pressure, model_next_priority):
40 New variables.
41 (MODEL_PRESSURE_DATA, MODEL_MAX_PRESSURE, MODEL_REF_PRESSURE)
42 (MODEL_INSN_INFO, MODEL_INSN): New macros.
43 (model_index, model_update_limit_points_in_group): New functions.
44 (model_update_limit_points, model_last_use_except): Likewise.
45 (model_start_update_pressure, model_update_pressure): Likewise.
46 (model_recompute, model_spill_cost, model_excess_group_cost): Likewise.
47 (model_excess_cost, model_dump_pressure_points): Likewise.
48 (model_set_excess_costs): Likewise.
49 (rank_for_schedule): Extend SCHED_PRIORITY_WEIGHTED ordering to
50 SCHED_PRIORITY_MODEL. Use insn_delay. Use the order in the model
51 schedule as an alternative tie-breaker. Update the call to
52 dep_list_size.
53 (ready_sort): Call model_set_excess_costs.
54 (update_register_pressure): Update call to mark_regno_birth_or_death.
55 Rely on that function to check liveness rather than doing it here.
56 (model_classify_pressure, model_order_p, model_add_to_worklist_at)
57 (model_remove_from_worklist, model_add_to_worklist, model_promote_insn)
58 (model_add_to_schedule, model_analyze_insns, model_init_pressure_group)
59 (model_record_pressure, model_record_pressures): New functions.
60 (model_record_final_pressures, model_add_successors_to_worklist)
61 (model_promote_predecessors, model_choose_insn): Likewise.
62 (model_reset_queue_indices, model_dump_pressure_summary): Likewise.
63 (model_start_schedule, model_finalize_pressure_group): Likewise.
64 (model_end_schedule): Likewise.
65 (schedule_insn): Say when we're scheduling the next instruction
66 in the model schedule.
67 (schedule_insn): Handle SCHED_PRESSURE_MODEL.
68 (queue_to_ready): Do not add instructions that are
69 MAX_SCHED_READY_INSNS beyond the current point of the model schedule.
70 Always allow the next instruction in the model schedule to be added.
71 (debug_ready_list): Print the INSN_REG_PRESSURE_EXCESS_COST_CHANGE
72 and delay for SCHED_PRESSURE_MODEL too.
73 (prune_ready_list): Extend SCHED_PRIORITY_WEIGHTED handling to
74 SCHED_PRIORITY_MODEL, but also take the DFA into account.
75 (schedule_block): Call model_start_schedule and model_end_schedule.
76 Extend SCHED_PRIORITY_WEIGHTED stall handling to SCHED_PRIORITY_MODEL.
77 (sched_init): Extend INSN_REG_PRESSURE_EXCESS_COST_CHANGE handling
78 to SCHED_PRESSURE_MODEL, but don't allocate saved_reg_live or
79 region_ref_regs.
80 (sched_finish): Update accordingly.
81 (fix_tick_ready): Extend INSN_REG_PRESSURE_EXCESS_COST_CHANGE handling
82 to SCHED_PRESSURE_MODEL.
83 (add_jump_dependencies): Update call to dep_list_size.
84 (haifa_finish_h_i_d): Fix leak of max_reg_pressure.
85 (haifa_init_insn): Extend INSN_REG_PRESSURE_EXCESS_COST_CHANGE handling
86 to SCHED_PRESSURE_MODEL.
87 * sched-deps.c (init_insn_reg_pressure_info): Likewise, but don't
88 allocate INSN_MAX_REG_PRESSURE for SCHED_PRESSURE_MODEL.
89 (sched_analyze_insn): Extend INSN_REG_PRESSURE_EXCESS_COST_CHANGE
90 handling to SCHED_PRESSURE_MODEL.
91
922012-02-08 Richard Sandiford <richard.sandiford@linaro.org>
93
94 gcc/
95 * common.opt (fsched-pressure-algorithm=): New option.
96 * flag-types.h (sched_pressure_algorithm): New enum.
97 * sched-int.h (sched_pressure_p): Replace with...
98 (sched_pressure): ...this new variable.
99 * haifa-sched.c (sched_pressure_p): Replace with...
100 (sched_pressure): ...this new variable.
101 (sched_regno_pressure_class, rank_for_schedule, ready_sort)
102 (update_reg_and_insn_max_reg_pressure, schedule_insn)
103 (debug_ready_list, schedule_block, sched_init, sched_finish)
104 (fix_tick_ready, haifa_init_insn): Update accordingly.
105 * sched-deps.c (init_insn_reg_pressure_info): Likewise.
106 * sched-rgn.c (schedule_region): Likewise.
107
1082012-02-08 Richard Sandiford <richard.sandiford@linaro.org>
109
110 gcc/
111 Backport from mainline:
112
113 2011-04-01 Bernd Schmidt <bernds@codesourcery.com>
114
115 * haifa-sched.c (prune_ready_list): New function, broken out of
116 schedule_block.
117 (schedule_block): Use it.
118
119=== modified file 'gcc/common.opt'
120--- old/gcc/common.opt 2011-04-11 15:26:47 +0000
121+++ new/gcc/common.opt 2012-02-08 23:38:13 +0000
122@@ -1614,6 +1614,19 @@
123 Common Report Var(flag_sched_pressure) Init(0) Optimization
124 Enable register pressure sensitive insn scheduling
125
126+fsched-pressure-algorithm=
127+Common Joined RejectNegative Enum(sched_pressure_algorithm) Var(flag_sched_pressure_algorithm) Init(SCHED_PRESSURE_WEIGHTED)
128+-fira-algorithm=[CB|priority] Set the used IRA algorithm
129+
130+Enum
131+Name(sched_pressure_algorithm) Type(enum sched_pressure_algorithm) UnknownError(unknown %<fsched-pressure%> algorithm %qs)
132+
133+EnumValue
134+Enum(sched_pressure_algorithm) String(weighted) Value(SCHED_PRESSURE_WEIGHTED)
135+
136+EnumValue
137+Enum(sched_pressure_algorithm) String(model) Value(SCHED_PRESSURE_MODEL)
138+
139 fsched-spec
140 Common Report Var(flag_schedule_speculative) Init(1) Optimization
141 Allow speculative motion of non-loads
142
143=== modified file 'gcc/config/arm/arm.c'
144--- old/gcc/config/arm/arm.c 2012-02-01 14:13:07 +0000
145+++ new/gcc/config/arm/arm.c 2012-02-09 00:47:59 +0000
146@@ -311,6 +311,11 @@
147 /* Set default optimization options. */
148 static const struct default_options arm_option_optimization_table[] =
149 {
150+ /* Enable -fsched-pressure using -fsched-pressure-algorithm=model
151+ by default when optimizing. */
152+ { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
153+ { OPT_LEVELS_1_PLUS, OPT_fsched_pressure_algorithm_,
154+ NULL, SCHED_PRESSURE_MODEL },
155 /* Enable section anchors by default at -O1 or higher. */
156 { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
157 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
158
159=== modified file 'gcc/flag-types.h'
160--- old/gcc/flag-types.h 2010-11-24 13:28:38 +0000
161+++ new/gcc/flag-types.h 2012-02-08 23:38:13 +0000
162@@ -106,6 +106,14 @@
163 };
164 #endif
165
166+/* The algorithm used to implement -fsched-pressure. */
167+enum sched_pressure_algorithm
168+{
169+ SCHED_PRESSURE_NONE,
170+ SCHED_PRESSURE_WEIGHTED,
171+ SCHED_PRESSURE_MODEL
172+};
173+
174 /* The algorithm used for the integrated register allocator (IRA). */
175 enum ira_algorithm
176 {
177
178=== modified file 'gcc/haifa-sched.c'
179--- old/gcc/haifa-sched.c 2011-02-19 20:59:23 +0000
180+++ new/gcc/haifa-sched.c 2012-02-08 23:39:02 +0000
181@@ -348,6 +348,14 @@
182 /* Create empty basic block after the specified block. */
183 basic_block (* sched_create_empty_bb) (basic_block);
184
185+/* Return the number of cycles until INSN is expected to be ready.
186+ Return zero if it already is. */
187+static int
188+insn_delay (rtx insn)
189+{
190+ return MAX (INSN_TICK (insn) - clock_var, 0);
191+}
192+
193 static int
194 may_trap_exp (const_rtx x, int is_store)
195 {
196@@ -571,10 +579,10 @@
197
198 /* Do register pressure sensitive insn scheduling if the flag is set
199 up. */
200-bool sched_pressure_p;
201+enum sched_pressure_algorithm sched_pressure;
202
203 /* Map regno -> its cover class. The map defined only when
204- SCHED_PRESSURE_P is true. */
205+ SCHED_PRESSURE != SCHED_PRESSURE_NONE. */
206 enum reg_class *sched_regno_cover_class;
207
208 /* The current register pressure. Only elements corresponding cover
209@@ -602,10 +610,12 @@
210 bitmap_clear (region_ref_regs);
211 }
212
213-/* Update current register pressure related info after birth (if
214- BIRTH_P) or death of register REGNO. */
215-static void
216-mark_regno_birth_or_death (int regno, bool birth_p)
217+/* PRESSURE[CL] describes the pressure on register class CL. Update it
218+ for the birth (if BIRTH_P) or death (if !BIRTH_P) of register REGNO.
219+ LIVE tracks the set of live registers; if it is null, assume that
220+ every birth or death is genuine. */
221+static inline void
222+mark_regno_birth_or_death (bitmap live, int *pressure, int regno, bool birth_p)
223 {
224 enum reg_class cover_class;
225
226@@ -616,15 +626,17 @@
227 {
228 if (birth_p)
229 {
230- bitmap_set_bit (curr_reg_live, regno);
231- curr_reg_pressure[cover_class]
232- += ira_reg_class_nregs[cover_class][PSEUDO_REGNO_MODE (regno)];
233+ if (!live || bitmap_set_bit (live, regno))
234+ pressure[cover_class]
235+ += (ira_reg_class_nregs
236+ [cover_class][PSEUDO_REGNO_MODE (regno)]);
237 }
238 else
239 {
240- bitmap_clear_bit (curr_reg_live, regno);
241- curr_reg_pressure[cover_class]
242- -= ira_reg_class_nregs[cover_class][PSEUDO_REGNO_MODE (regno)];
243+ if (!live || bitmap_clear_bit (live, regno))
244+ pressure[cover_class]
245+ -= (ira_reg_class_nregs
246+ [cover_class][PSEUDO_REGNO_MODE (regno)]);
247 }
248 }
249 }
250@@ -633,13 +645,13 @@
251 {
252 if (birth_p)
253 {
254- bitmap_set_bit (curr_reg_live, regno);
255- curr_reg_pressure[cover_class]++;
256+ if (!live || bitmap_set_bit (live, regno))
257+ pressure[cover_class]++;
258 }
259 else
260 {
261- bitmap_clear_bit (curr_reg_live, regno);
262- curr_reg_pressure[cover_class]--;
263+ if (!live || bitmap_clear_bit (live, regno))
264+ pressure[cover_class]--;
265 }
266 }
267 }
268@@ -657,8 +669,10 @@
269 curr_reg_pressure[ira_reg_class_cover[i]] = 0;
270 bitmap_clear (curr_reg_live);
271 EXECUTE_IF_SET_IN_BITMAP (live, 0, j, bi)
272- if (current_nr_blocks == 1 || bitmap_bit_p (region_ref_regs, j))
273- mark_regno_birth_or_death (j, true);
274+ if (sched_pressure == SCHED_PRESSURE_MODEL
275+ || current_nr_blocks == 1
276+ || bitmap_bit_p (region_ref_regs, j))
277+ mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure, j, true);
278 }
279
280 /* Mark registers in X as mentioned in the current region. */
281@@ -712,7 +726,8 @@
282 if (regno == INVALID_REGNUM)
283 break;
284 if (! bitmap_bit_p (df_get_live_in (bb), regno))
285- mark_regno_birth_or_death (regno, true);
286+ mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure,
287+ regno, true);
288 }
289 #endif
290 }
291@@ -956,19 +971,19 @@
292 return true;
293 }
294
295-/* Compute the number of nondebug forward deps of an insn. */
296+/* Compute the number of nondebug deps in list LIST for INSN. */
297
298 static int
299-dep_list_size (rtx insn)
300+dep_list_size (rtx insn, sd_list_types_def list)
301 {
302 sd_iterator_def sd_it;
303 dep_t dep;
304 int dbgcount = 0, nodbgcount = 0;
305
306 if (!MAY_HAVE_DEBUG_INSNS)
307- return sd_lists_size (insn, SD_LIST_FORW);
308+ return sd_lists_size (insn, list);
309
310- FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
311+ FOR_EACH_DEP (insn, list, sd_it, dep)
312 {
313 if (DEBUG_INSN_P (DEP_CON (dep)))
314 dbgcount++;
315@@ -976,7 +991,7 @@
316 nodbgcount++;
317 }
318
319- gcc_assert (dbgcount + nodbgcount == sd_lists_size (insn, SD_LIST_FORW));
320+ gcc_assert (dbgcount + nodbgcount == sd_lists_size (insn, list));
321
322 return nodbgcount;
323 }
324@@ -995,7 +1010,7 @@
325 {
326 int this_priority = -1;
327
328- if (dep_list_size (insn) == 0)
329+ if (dep_list_size (insn, SD_LIST_FORW) == 0)
330 /* ??? We should set INSN_PRIORITY to insn_cost when and insn has
331 some forward deps but all of them are ignored by
332 contributes_to_priority hook. At the moment we set priority of
333@@ -1091,6 +1106,22 @@
334 qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \
335 while (0)
336
337+/* For each cover class CL, set DEATH[CL] to the number of registers
338+ in that class that die in INSN. */
339+
340+static void
341+calculate_reg_deaths (rtx insn, int *death)
342+{
343+ int i;
344+ struct reg_use_data *use;
345+
346+ for (i = 0; i < ira_reg_class_cover_size; i++)
347+ death[ira_reg_class_cover[i]] = 0;
348+ for (use = INSN_REG_USE_LIST (insn); use != NULL; use = use->next_insn_use)
349+ if (dying_use_p (use))
350+ mark_regno_birth_or_death (0, death, use->regno, true);
351+}
352+
353 /* Setup info about the current register pressure impact of scheduling
354 INSN at the current scheduling point. */
355 static void
356@@ -1102,23 +1133,12 @@
357 enum reg_class cl;
358 struct reg_pressure_data *pressure_info;
359 int *max_reg_pressure;
360- struct reg_use_data *use;
361 static int death[N_REG_CLASSES];
362
363 gcc_checking_assert (!DEBUG_INSN_P (insn));
364
365 excess_cost_change = 0;
366- for (i = 0; i < ira_reg_class_cover_size; i++)
367- death[ira_reg_class_cover[i]] = 0;
368- for (use = INSN_REG_USE_LIST (insn); use != NULL; use = use->next_insn_use)
369- if (dying_use_p (use))
370- {
371- cl = sched_regno_cover_class[use->regno];
372- if (use->regno < FIRST_PSEUDO_REGISTER)
373- death[cl]++;
374- else
375- death[cl] += ira_reg_class_nregs[cl][PSEUDO_REGNO_MODE (use->regno)];
376- }
377+ calculate_reg_deaths (insn, death);
378 pressure_info = INSN_REG_PRESSURE (insn);
379 max_reg_pressure = INSN_MAX_REG_PRESSURE (insn);
380 gcc_assert (pressure_info != NULL && max_reg_pressure != NULL);
381@@ -1139,7 +1159,765 @@
382 }
383 INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insn) = excess_cost_change;
384 }
385-
386+
387+/* This is the first page of code related to SCHED_PRESSURE_MODEL.
388+ It tries to make the scheduler take register pressure into account
389+ without introducing too many unnecessary stalls. It hooks into the
390+ main scheduling algorithm at several points:
391+
392+ - Before scheduling starts, model_start_schedule constructs a
393+ "model schedule" for the current block. This model schedule is
394+ chosen solely to keep register pressure down. It does not take the
395+ target's pipeline or the original instruction order into account,
396+ except as a tie-breaker. It also doesn't work to a particular
397+ pressure limit.
398+
399+ This model schedule gives us an idea of what pressure can be
400+ achieved for the block gives us an example of a schedule that
401+ keeps to that pressure. It also makes the final schedule less
402+ dependent on the original instruction order. This is important
403+ because the original order can either be "wide" (many values live
404+ at once, such as in user-scheduled code) or "narrow" (few values
405+ live at once, such as after loop unrolling, where several
406+ iterations are executed sequentially).
407+
408+ We do not apply this model schedule to the rtx stream. We simply
409+ record it in model_schedule. We also compute the maximum pressure,
410+ MP, that was seen during this schedule.
411+
412+ - Instructions are added to the ready queue even if they require
413+ a stall. The length of the stall is instead computed as:
414+
415+ MAX (INSN_TICK (INSN) - clock_var, 0)
416+
417+ (= insn_delay). This allows rank_for_schedule to choose between
418+ introducing a deliberate stall or increasing pressure.
419+
420+ - Before sorting the ready queue, model_set_excess_costs assigns
421+ a pressure-based cost to each ready instruction in the queue.
422+ This is the instruction's INSN_REG_PRESSURE_EXCESS_COST_CHANGE
423+ (ECC for short) and is effectively measured in cycles.
424+
425+ - rank_for_schedule ranks instructions based on:
426+
427+ ECC (insn) + insn_delay (insn)
428+
429+ then as:
430+
431+ insn_delay (insn)
432+
433+ So, for example, an instruction X1 with an ECC of 1 that can issue
434+ now will win over an instruction X0 with an ECC of zero that would
435+ introduce a stall of one cycle. However, an instruction X2 with an
436+ ECC of 2 that can issue now will lose to X0.
437+
438+ - When an instruction is scheduled, model_recompute updates the model
439+ schedule with the new pressures (some of which might now exceed the
440+ original maximum pressure MP). model_update_limit_points then searches
441+ for the new point of maximum pressure, if not already known. */
442+
443+/* Used to separate high-verbosity debug information for SCHED_PRESSURE_MODEL
444+ from surrounding debug information. */
445+#define MODEL_BAR \
446+ ";;\t\t+------------------------------------------------------\n"
447+
448+/* Information about the pressure on a particular register class at a
449+ particular point of the model schedule. */
450+struct model_pressure_data {
451+ /* The pressure at this point of the model schedule, or -1 if the
452+ point is associated with an instruction that has already been
453+ scheduled. */
454+ int ref_pressure;
455+
456+ /* The maximum pressure during or after this point of the model schedule. */
457+ int max_pressure;
458+};
459+
460+/* Per-instruction information that is used while building the model
461+ schedule. Here, "schedule" refers to the model schedule rather
462+ than the main schedule. */
463+struct model_insn_info {
464+ /* The instruction itself. */
465+ rtx insn;
466+
467+ /* If this instruction is in model_worklist, these fields link to the
468+ previous (higher-priority) and next (lower-priority) instructions
469+ in the list. */
470+ struct model_insn_info *prev;
471+ struct model_insn_info *next;
472+
473+ /* While constructing the schedule, QUEUE_INDEX describes whether an
474+ instruction has already been added to the schedule (QUEUE_SCHEDULED),
475+ is in model_worklist (QUEUE_READY), or neither (QUEUE_NOWHERE).
476+ old_queue records the value that QUEUE_INDEX had before scheduling
477+ started, so that we can restore it once the schedule is complete. */
478+ int old_queue;
479+
480+ /* The relative importance of an unscheduled instruction. Higher
481+ values indicate greater importance. */
482+ unsigned int model_priority;
483+
484+ /* The length of the longest path of satisfied true dependencies
485+ that leads to this instruction. */
486+ unsigned int depth;
487+
488+ /* The length of the longest path of dependencies of any kind
489+ that leads from this instruction. */
490+ unsigned int alap;
491+
492+ /* The number of predecessor nodes that must still be scheduled. */
493+ int unscheduled_preds;
494+};
495+
496+/* Information about the pressure limit for a particular register class.
497+ This structure is used when applying a model schedule to the main
498+ schedule. */
499+struct model_pressure_limit {
500+ /* The maximum register pressure seen in the original model schedule. */
501+ int orig_pressure;
502+
503+ /* The maximum register pressure seen in the current model schedule
504+ (which excludes instructions that have already been scheduled). */
505+ int pressure;
506+
507+ /* The point of the current model schedule at which PRESSURE is first
508+ reached. It is set to -1 if the value needs to be recomputed. */
509+ int point;
510+};
511+
512+/* Describes a particular way of measuring register pressure. */
513+struct model_pressure_group {
514+ /* Index CCI describes the maximum pressure on ira_reg_class_cover[CCI]. */
515+ struct model_pressure_limit limits[N_REG_CLASSES];
516+
517+ /* Index (POINT * ira_num_pressure_classes + CCI) describes the pressure
518+ on register class ira_reg_class_cover[CCI] at point POINT of the
519+ current model schedule. A POINT of model_num_insns describes the
520+ pressure at the end of the schedule. */
521+ struct model_pressure_data *model;
522+};
523+
524+/* Index POINT gives the instruction at point POINT of the model schedule.
525+ This array doesn't change during main scheduling. */
526+static VEC (rtx, heap) *model_schedule;
527+
528+/* The list of instructions in the model worklist, sorted in order of
529+ decreasing priority. */
530+static struct model_insn_info *model_worklist;
531+
532+/* Index I describes the instruction with INSN_LUID I. */
533+static struct model_insn_info *model_insns;
534+
535+/* The number of instructions in the model schedule. */
536+static int model_num_insns;
537+
538+/* The index of the first instruction in model_schedule that hasn't yet been
539+ added to the main schedule, or model_num_insns if all of them have. */
540+static int model_curr_point;
541+
542+/* Describes the pressure before each instruction in the model schedule. */
543+static struct model_pressure_group model_before_pressure;
544+
545+/* The first unused model_priority value (as used in model_insn_info). */
546+static unsigned int model_next_priority;
547+
548+
549+/* The model_pressure_data for ira_reg_class_cover[CCI] in GROUP
550+ at point POINT of the model schedule. */
551+#define MODEL_PRESSURE_DATA(GROUP, POINT, CCI) \
552+ (&(GROUP)->model[(POINT) * ira_reg_class_cover_size + (CCI)])
553+
554+/* The maximum pressure on ira_reg_class_cover[CCI] in GROUP at or
555+ after point POINT of the model schedule. */
556+#define MODEL_MAX_PRESSURE(GROUP, POINT, CCI) \
557+ (MODEL_PRESSURE_DATA (GROUP, POINT, CCI)->max_pressure)
558+
559+/* The pressure on ira_reg_class_cover[CCI] in GROUP at point POINT
560+ of the model schedule. */
561+#define MODEL_REF_PRESSURE(GROUP, POINT, CCI) \
562+ (MODEL_PRESSURE_DATA (GROUP, POINT, CCI)->ref_pressure)
563+
564+/* Information about INSN that is used when creating the model schedule. */
565+#define MODEL_INSN_INFO(INSN) \
566+ (&model_insns[INSN_LUID (INSN)])
567+
568+/* The instruction at point POINT of the model schedule. */
569+#define MODEL_INSN(POINT) \
570+ (VEC_index (rtx, model_schedule, POINT))
571+
572+
573+/* Return INSN's index in the model schedule, or model_num_insns if it
574+ doesn't belong to that schedule. */
575+
576+static int
577+model_index (rtx insn)
578+{
579+ if (INSN_MODEL_INDEX (insn) == 0)
580+ return model_num_insns;
581+ return INSN_MODEL_INDEX (insn) - 1;
582+}
583+
584+/* Make sure that GROUP->limits is up-to-date for the current point
585+ of the model schedule. */
586+
587+static void
588+model_update_limit_points_in_group (struct model_pressure_group *group)
589+{
590+ int cci, max_pressure, point;
591+
592+ for (cci = 0; cci < ira_reg_class_cover_size; cci++)
593+ {
594+ /* We may have passed the final point at which the pressure in
595+ group->limits[cci].pressure was reached. Update the limit if so. */
596+ max_pressure = MODEL_MAX_PRESSURE (group, model_curr_point, cci);
597+ group->limits[cci].pressure = max_pressure;
598+
599+ /* Find the point at which MAX_PRESSURE is first reached. We need
600+ to search in three cases:
601+
602+ - We've already moved past the previous pressure point.
603+ In this case we search forward from model_curr_point.
604+
605+ - We scheduled the previous point of maximum pressure ahead of
606+ its position in the model schedule, but doing so didn't bring
607+ the pressure point earlier. In this case we search forward
608+ from that previous pressure point.
609+
610+ - Scheduling an instruction early caused the maximum pressure
611+ to decrease. In this case we will have set the pressure
612+ point to -1, and we search forward from model_curr_point. */
613+ point = MAX (group->limits[cci].point, model_curr_point);
614+ while (point < model_num_insns
615+ && MODEL_REF_PRESSURE (group, point, cci) < max_pressure)
616+ point++;
617+ group->limits[cci].point = point;
618+
619+ gcc_assert (MODEL_REF_PRESSURE (group, point, cci) == max_pressure);
620+ gcc_assert (MODEL_MAX_PRESSURE (group, point, cci) == max_pressure);
621+ }
622+}
623+
624+/* Make sure that all register-pressure limits are up-to-date for the
625+ current position in the model schedule. */
626+
627+static void
628+model_update_limit_points (void)
629+{
630+ model_update_limit_points_in_group (&model_before_pressure);
631+}
632+
633+/* Return the model_index of the last unscheduled use in chain USE
634+ outside of USE's instruction. Return -1 if there are no other uses,
635+ or model_num_insns if the register is live at the end of the block. */
636+
637+static int
638+model_last_use_except (struct reg_use_data *use)
639+{
640+ struct reg_use_data *next;
641+ int last, index;
642+
643+ last = -1;
644+ for (next = use->next_regno_use; next != use; next = next->next_regno_use)
645+ if (NONDEBUG_INSN_P (next->insn)
646+ && QUEUE_INDEX (next->insn) != QUEUE_SCHEDULED)
647+ {
648+ index = model_index (next->insn);
649+ if (index == model_num_insns)
650+ return model_num_insns;
651+ if (last < index)
652+ last = index;
653+ }
654+ return last;
655+}
656+
657+/* An instruction with model_index POINT has just been scheduled, and it
658+ adds DELTA to the pressure on ira_reg_class_cover[CCI] after POINT - 1.
659+ Update MODEL_REF_PRESSURE (GROUP, POINT, CCI) and
660+ MODEL_MAX_PRESSURE (GROUP, POINT, CCI) accordingly. */
661+
662+static void
663+model_start_update_pressure (struct model_pressure_group *group,
664+ int point, int cci, int delta)
665+{
666+ int next_max_pressure;
667+
668+ if (point == model_num_insns)
669+ {
670+ /* The instruction wasn't part of the model schedule; it was moved
671+ from a different block. Update the pressure for the end of
672+ the model schedule. */
673+ MODEL_REF_PRESSURE (group, point, cci) += delta;
674+ MODEL_MAX_PRESSURE (group, point, cci) += delta;
675+ }
676+ else
677+ {
678+ /* Record that this instruction has been scheduled. Nothing now
679+ changes between POINT and POINT + 1, so get the maximum pressure
680+ from the latter. If the maximum pressure decreases, the new
681+ pressure point may be before POINT. */
682+ MODEL_REF_PRESSURE (group, point, cci) = -1;
683+ next_max_pressure = MODEL_MAX_PRESSURE (group, point + 1, cci);
684+ if (MODEL_MAX_PRESSURE (group, point, cci) > next_max_pressure)
685+ {
686+ MODEL_MAX_PRESSURE (group, point, cci) = next_max_pressure;
687+ if (group->limits[cci].point == point)
688+ group->limits[cci].point = -1;
689+ }
690+ }
691+}
692+
693+/* Record that scheduling a later instruction has changed the pressure
694+ at point POINT of the model schedule by DELTA (which might be 0).
695+ Update GROUP accordingly. Return nonzero if these changes might
696+ trigger changes to previous points as well. */
697+
698+static int
699+model_update_pressure (struct model_pressure_group *group,
700+ int point, int cci, int delta)
701+{
702+ int ref_pressure, max_pressure, next_max_pressure;
703+
704+ /* If POINT hasn't yet been scheduled, update its pressure. */
705+ ref_pressure = MODEL_REF_PRESSURE (group, point, cci);
706+ if (ref_pressure >= 0 && delta != 0)
707+ {
708+ ref_pressure += delta;
709+ MODEL_REF_PRESSURE (group, point, cci) = ref_pressure;
710+
711+ /* Check whether the maximum pressure in the overall schedule
712+ has increased. (This means that the MODEL_MAX_PRESSURE of
713+ every point <= POINT will need to increae too; see below.) */
714+ if (group->limits[cci].pressure < ref_pressure)
715+ group->limits[cci].pressure = ref_pressure;
716+
717+ /* If we are at maximum pressure, and the maximum pressure
718+ point was previously unknown or later than POINT,
719+ bring it forward. */
720+ if (group->limits[cci].pressure == ref_pressure
721+ && !IN_RANGE (group->limits[cci].point, 0, point))
722+ group->limits[cci].point = point;
723+
724+ /* If POINT used to be the point of maximum pressure, but isn't
725+ any longer, we need to recalculate it using a forward walk. */
726+ if (group->limits[cci].pressure > ref_pressure
727+ && group->limits[cci].point == point)
728+ group->limits[cci].point = -1;
729+ }
730+
731+ /* Update the maximum pressure at POINT. Changes here might also
732+ affect the maximum pressure at POINT - 1. */
733+ next_max_pressure = MODEL_MAX_PRESSURE (group, point + 1, cci);
734+ max_pressure = MAX (ref_pressure, next_max_pressure);
735+ if (MODEL_MAX_PRESSURE (group, point, cci) != max_pressure)
736+ {
737+ MODEL_MAX_PRESSURE (group, point, cci) = max_pressure;
738+ return 1;
739+ }
740+ return 0;
741+}
742+
743+/* INSN has just been scheduled. Update the model schedule accordingly. */
744+
745+static void
746+model_recompute (rtx insn)
747+{
748+ struct {
749+ int last_use;
750+ int regno;
751+ } uses[FIRST_PSEUDO_REGISTER + MAX_RECOG_OPERANDS];
752+ struct reg_use_data *use;
753+ struct reg_pressure_data *reg_pressure;
754+ int delta[N_REG_CLASSES];
755+ int cci, point, mix, new_last, cl, ref_pressure, queue;
756+ unsigned int i, num_uses, num_pending_births;
757+ bool print_p;
758+
759+ /* The destinations of INSN were previously live from POINT onwards, but are
760+ now live from model_curr_point onwards. Set up DELTA accordingly. */
761+ point = model_index (insn);
762+ reg_pressure = INSN_REG_PRESSURE (insn);
763+ for (cci = 0; cci < ira_reg_class_cover_size; cci++)
764+ {
765+ cl = ira_reg_class_cover[cci];
766+ delta[cl] = reg_pressure[cci].set_increase;
767+ }
768+
769+ /* Record which registers previously died at POINT, but which now die
770+ before POINT. Adjust DELTA so that it represents the effect of
771+ this change after POINT - 1. Set NUM_PENDING_BIRTHS to the number of
772+ registers that will be born in the range [model_curr_point, POINT). */
773+ num_uses = 0;
774+ num_pending_births = 0;
775+ for (use = INSN_REG_USE_LIST (insn); use != NULL; use = use->next_insn_use)
776+ {
777+ new_last = model_last_use_except (use);
778+ if (new_last < point)
779+ {
780+ gcc_assert (num_uses < ARRAY_SIZE (uses));
781+ uses[num_uses].last_use = new_last;
782+ uses[num_uses].regno = use->regno;
783+ /* This register is no longer live after POINT - 1. */
784+ mark_regno_birth_or_death (NULL, delta, use->regno, false);
785+ num_uses++;
786+ if (new_last >= 0)
787+ num_pending_births++;
788+ }
789+ }
790+
791+ /* Update the MODEL_REF_PRESSURE and MODEL_MAX_PRESSURE for POINT.
792+ Also set each group pressure limit for POINT. */
793+ for (cci = 0; cci < ira_reg_class_cover_size; cci++)
794+ {
795+ cl = ira_reg_class_cover[cci];
796+ model_start_update_pressure (&model_before_pressure,
797+ point, cci, delta[cl]);
798+ }
799+
800+ /* Walk the model schedule backwards, starting immediately before POINT. */
801+ print_p = false;
802+ if (point != model_curr_point)
803+ do
804+ {
805+ point--;
806+ insn = MODEL_INSN (point);
807+ queue = QUEUE_INDEX (insn);
808+
809+ if (queue != QUEUE_SCHEDULED)
810+ {
811+ /* DELTA describes the effect of the move on the register pressure
812+ after POINT. Make it describe the effect on the pressure
813+ before POINT. */
814+ i = 0;
815+ while (i < num_uses)
816+ {
817+ if (uses[i].last_use == point)
818+ {
819+ /* This register is now live again. */
820+ mark_regno_birth_or_death (NULL, delta,
821+ uses[i].regno, true);
822+
823+ /* Remove this use from the array. */
824+ uses[i] = uses[num_uses - 1];
825+ num_uses--;
826+ num_pending_births--;
827+ }
828+ else
829+ i++;
830+ }
831+
832+ if (sched_verbose >= 5)
833+ {
834+ char buf[2048];
835+
836+ if (!print_p)
837+ {
838+ fprintf (sched_dump, MODEL_BAR);
839+ fprintf (sched_dump, ";;\t\t| New pressure for model"
840+ " schedule\n");
841+ fprintf (sched_dump, MODEL_BAR);
842+ print_p = true;
843+ }
844+
845+ print_pattern (buf, PATTERN (insn), 0);
846+ fprintf (sched_dump, ";;\t\t| %3d %4d %-30s ",
847+ point, INSN_UID (insn), buf);
848+ for (cci = 0; cci < ira_reg_class_cover_size; cci++)
849+ {
850+ cl = ira_reg_class_cover[cci];
851+ ref_pressure = MODEL_REF_PRESSURE (&model_before_pressure,
852+ point, cci);
853+ fprintf (sched_dump, " %s:[%d->%d]",
854+ reg_class_names[ira_reg_class_cover[cci]],
855+ ref_pressure, ref_pressure + delta[cl]);
856+ }
857+ fprintf (sched_dump, "\n");
858+ }
859+ }
860+
861+ /* Adjust the pressure at POINT. Set MIX to nonzero if POINT - 1
862+ might have changed as well. */
863+ mix = num_pending_births;
864+ for (cci = 0; cci < ira_reg_class_cover_size; cci++)
865+ {
866+ cl = ira_reg_class_cover[cci];
867+ mix |= delta[cl];
868+ mix |= model_update_pressure (&model_before_pressure,
869+ point, cci, delta[cl]);
870+ }
871+ }
872+ while (mix && point > model_curr_point);
873+
874+ if (print_p)
875+ fprintf (sched_dump, MODEL_BAR);
876+}
877+
878+/* model_spill_cost (CL, P, P') returns the cost of increasing the
879+ pressure on CL from P to P'. We use this to calculate a "base ECC",
880+ baseECC (CL, X), for each cover class CL and each instruction X.
881+ Supposing X changes the pressure on CL from P to P', and that the
882+ maximum pressure on CL in the current model schedule is MP', then:
883+
884+ * if X occurs before or at the next point of maximum pressure in
885+ the model schedule and P' > MP', then:
886+
887+ baseECC (CL, X) = model_spill_cost (CL, MP, P')
888+
889+ The idea is that the pressure after scheduling a fixed set of
890+ instructions -- in this case, the set up to and including the
891+ next maximum pressure point -- is going to be the same regardless
892+ of the order; we simply want to keep the intermediate pressure
893+ under control. Thus X has a cost of zero unless scheduling it
894+ now would exceed MP'.
895+
896+ If all increases in the set are by the same amount, no zero-cost
897+ instruction will ever cause the pressure to exceed MP'. However,
898+ if X is instead moved past an instruction X' with pressure in the
899+ range (MP' - (P' - P), MP'), the pressure at X' will increase
900+ beyond MP'. Since baseECC is very much a heuristic anyway,
901+ it doesn't seem worth the overhead of tracking cases like these.
902+
903+ The cost of exceeding MP' is always based on the original maximum
904+ pressure MP. This is so that going 2 registers over the original
905+ limit has the same cost regardless of whether it comes from two
906+ separate +1 deltas or from a single +2 delta.
907+
908+ * if X occurs after the next point of maximum pressure in the model
909+ schedule and P' > P, then:
910+
911+ baseECC (CL, X) = model_spill_cost (CL, MP, MP' + (P' - P))
912+
913+ That is, if we move X forward across a point of maximum pressure,
914+ and if X increases the pressure by P' - P, then we conservatively
915+ assume that scheduling X next would increase the maximum pressure
916+ by P' - P. Again, the cost of doing this is based on the original
917+ maximum pressure MP, for the same reason as above.
918+
919+ * if P' < P, P > MP, and X occurs at or after the next point of
920+ maximum pressure, then:
921+
922+ baseECC (CL, X) = -model_spill_cost (CL, MAX (MP, P'), P)
923+
924+ That is, if we have already exceeded the original maximum pressure MP,
925+ and if X might reduce the maximum pressure again -- or at least push
926+ it further back, and thus allow more scheduling freedom -- it is given
927+ a negative cost to reflect the improvement.
928+
929+ * otherwise,
930+
931+ baseECC (CL, X) = 0
932+
933+ In this case, X is not expected to affect the maximum pressure MP',
934+ so it has zero cost.
935+
936+ We then create a combined value baseECC (X) that is the sum of
937+ baseECC (CL, X) for each cover class CL.
938+
939+ baseECC (X) could itself be used as the ECC value described above.
940+ However, this is often too conservative, in the sense that it
941+ tends to make high-priority instructions that increase pressure
942+ wait too long in cases where introducing a spill would be better.
943+ For this reason the final ECC is a priority-adjusted form of
944+ baseECC (X). Specifically, we calculate:
945+
946+ P (X) = INSN_PRIORITY (X) - insn_delay (X) - baseECC (X)
947+ baseP = MAX { P (X) | baseECC (X) <= 0 }
948+
949+ Then:
950+
951+ ECC (X) = MAX (MIN (baseP - P (X), baseECC (X)), 0)
952+
953+ Thus an instruction's effect on pressure is ignored if it has a high
954+ enough priority relative to the ones that don't increase pressure.
955+ Negative values of baseECC (X) do not increase the priority of X
956+ itself, but they do make it harder for other instructions to
957+ increase the pressure further.
958+
959+ This pressure cost is deliberately timid. The intention has been
960+ to choose a heuristic that rarely interferes with the normal list
961+ scheduler in cases where that scheduler would produce good code.
962+ We simply want to curb some of its worst excesses. */
963+
964+/* Return the cost of increasing the pressure in class CL from FROM to TO.
965+
966+ Here we use the very simplistic cost model that every register above
967+ ira_available_class_regs[CL] has a spill cost of 1. We could use other
968+ measures instead, such as one based on MEMORY_MOVE_COST. However:
969+
970+ (1) In order for an instruction to be scheduled, the higher cost
971+ would need to be justified in a single saving of that many stalls.
972+ This is overly pessimistic, because the benefit of spilling is
973+ often to avoid a sequence of several short stalls rather than
974+ a single long one.
975+
976+ (2) The cost is still arbitrary. Because we are not allocating
977+ registers during scheduling, we have no way of knowing for
978+ sure how many memory accesses will be required by each spill,
979+ where the spills will be placed within the block, or even
980+ which block(s) will contain the spills.
981+
982+ So a higher cost than 1 is often too conservative in practice,
983+ forcing blocks to contain unnecessary stalls instead of spill code.
984+ The simple cost below seems to be the best compromise. It reduces
985+ the interference with the normal list scheduler, which helps make
986+ it more suitable for a default-on option. */
987+
988+static int
989+model_spill_cost (int cl, int from, int to)
990+{
991+ from = MAX (from, ira_available_class_regs[cl]);
992+ return MAX (to, from) - from;
993+}
994+
995+/* Return baseECC (ira_reg_class_cover[CCI], POINT), given that
996+ P = curr_reg_pressure[ira_reg_class_cover[CCI]] and that
997+ P' = P + DELTA. */
998+
999+static int
1000+model_excess_group_cost (struct model_pressure_group *group,
1001+ int point, int cci, int delta)
1002+{
1003+ int pressure, cl;
1004+
1005+ cl = ira_reg_class_cover[cci];
1006+ if (delta < 0 && point >= group->limits[cci].point)
1007+ {
1008+ pressure = MAX (group->limits[cci].orig_pressure,
1009+ curr_reg_pressure[cl] + delta);
1010+ return -model_spill_cost (cl, pressure, curr_reg_pressure[cl]);
1011+ }
1012+
1013+ if (delta > 0)
1014+ {
1015+ if (point > group->limits[cci].point)
1016+ pressure = group->limits[cci].pressure + delta;
1017+ else
1018+ pressure = curr_reg_pressure[cl] + delta;
1019+
1020+ if (pressure > group->limits[cci].pressure)
1021+ return model_spill_cost (cl, group->limits[cci].orig_pressure,
1022+ pressure);
1023+ }
1024+
1025+ return 0;
1026+}
1027+
1028+/* Return baseECC (MODEL_INSN (INSN)). Dump the costs to sched_dump
1029+ if PRINT_P. */
1030+
1031+static int
1032+model_excess_cost (rtx insn, bool print_p)
1033+{
1034+ int point, cci, cl, cost, this_cost, delta;
1035+ struct reg_pressure_data *insn_reg_pressure;
1036+ int insn_death[N_REG_CLASSES];
1037+
1038+ calculate_reg_deaths (insn, insn_death);
1039+ point = model_index (insn);
1040+ insn_reg_pressure = INSN_REG_PRESSURE (insn);
1041+ cost = 0;
1042+
1043+ if (print_p)
1044+ fprintf (sched_dump, ";;\t\t| %3d %4d | %4d %+3d |", point,
1045+ INSN_UID (insn), INSN_PRIORITY (insn), insn_delay (insn));
1046+
1047+ /* Sum up the individual costs for each register class. */
1048+ for (cci = 0; cci < ira_reg_class_cover_size; cci++)
1049+ {
1050+ cl = ira_reg_class_cover[cci];
1051+ delta = insn_reg_pressure[cci].set_increase - insn_death[cl];
1052+ this_cost = model_excess_group_cost (&model_before_pressure,
1053+ point, cci, delta);
1054+ cost += this_cost;
1055+ if (print_p)
1056+ fprintf (sched_dump, " %s:[%d base cost %d]",
1057+ reg_class_names[cl], delta, this_cost);
1058+ }
1059+
1060+ if (print_p)
1061+ fprintf (sched_dump, "\n");
1062+
1063+ return cost;
1064+}
1065+
1066+/* Dump the next points of maximum pressure for GROUP. */
1067+
1068+static void
1069+model_dump_pressure_points (struct model_pressure_group *group)
1070+{
1071+ int cci, cl;
1072+
1073+ fprintf (sched_dump, ";;\t\t| pressure points");
1074+ for (cci = 0; cci < ira_reg_class_cover_size; cci++)
1075+ {
1076+ cl = ira_reg_class_cover[cci];
1077+ fprintf (sched_dump, " %s:[%d->%d at ", reg_class_names[cl],
1078+ curr_reg_pressure[cl], group->limits[cci].pressure);
1079+ if (group->limits[cci].point < model_num_insns)
1080+ fprintf (sched_dump, "%d:%d]", group->limits[cci].point,
1081+ INSN_UID (MODEL_INSN (group->limits[cci].point)));
1082+ else
1083+ fprintf (sched_dump, "end]");
1084+ }
1085+ fprintf (sched_dump, "\n");
1086+}
1087+
1088+/* Set INSN_REG_PRESSURE_EXCESS_COST_CHANGE for INSNS[0...COUNT-1]. */
1089+
1090+static void
1091+model_set_excess_costs (rtx *insns, int count)
1092+{
1093+ int i, cost, priority_base, priority;
1094+ bool print_p;
1095+
1096+ /* Record the baseECC value for each instruction in the model schedule,
1097+ except that negative costs are converted to zero ones now rather thatn
1098+ later. Do not assign a cost to debug instructions, since they must
1099+ not change code-generation decisions. Experiments suggest we also
1100+ get better results by not assigning a cost to instructions from
1101+ a different block.
1102+
1103+ Set PRIORITY_BASE to baseP in the block comment above. This is the
1104+ maximum priority of the "cheap" instructions, which should always
1105+ include the next model instruction. */
1106+ priority_base = 0;
1107+ print_p = false;
1108+ for (i = 0; i < count; i++)
1109+ if (INSN_MODEL_INDEX (insns[i]))
1110+ {
1111+ if (sched_verbose >= 6 && !print_p)
1112+ {
1113+ fprintf (sched_dump, MODEL_BAR);
1114+ fprintf (sched_dump, ";;\t\t| Pressure costs for ready queue\n");
1115+ model_dump_pressure_points (&model_before_pressure);
1116+ fprintf (sched_dump, MODEL_BAR);
1117+ print_p = true;
1118+ }
1119+ cost = model_excess_cost (insns[i], print_p);
1120+ if (cost <= 0)
1121+ {
1122+ priority = INSN_PRIORITY (insns[i]) - insn_delay (insns[i]) - cost;
1123+ priority_base = MAX (priority_base, priority);
1124+ cost = 0;
1125+ }
1126+ INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insns[i]) = cost;
1127+ }
1128+ if (print_p)
1129+ fprintf (sched_dump, MODEL_BAR);
1130+
1131+ /* Use MAX (baseECC, 0) and baseP to calculcate ECC for each
1132+ instruction. */
1133+ for (i = 0; i < count; i++)
1134+ {
1135+ cost = INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insns[i]);
1136+ priority = INSN_PRIORITY (insns[i]) - insn_delay (insns[i]);
1137+ if (cost > 0 && priority > priority_base)
1138+ {
1139+ cost += priority_base - priority;
1140+ INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insns[i]) = MAX (cost, 0);
1141+ }
1142+ }
1143+}
1144+
1145 /* Returns a positive value if x is preferred; returns a negative value if
1146 y is preferred. Should never return 0, since that will make the sort
1147 unstable. */
1148@@ -1170,23 +1948,20 @@
1149 /* Make sure that priority of TMP and TMP2 are initialized. */
1150 gcc_assert (INSN_PRIORITY_KNOWN (tmp) && INSN_PRIORITY_KNOWN (tmp2));
1151
1152- if (sched_pressure_p)
1153+ if (sched_pressure != SCHED_PRESSURE_NONE)
1154 {
1155 int diff;
1156
1157 /* Prefer insn whose scheduling results in the smallest register
1158 pressure excess. */
1159 if ((diff = (INSN_REG_PRESSURE_EXCESS_COST_CHANGE (tmp)
1160- + (INSN_TICK (tmp) > clock_var
1161- ? INSN_TICK (tmp) - clock_var : 0)
1162+ + insn_delay (tmp)
1163 - INSN_REG_PRESSURE_EXCESS_COST_CHANGE (tmp2)
1164- - (INSN_TICK (tmp2) > clock_var
1165- ? INSN_TICK (tmp2) - clock_var : 0))) != 0)
1166+ - insn_delay (tmp2))))
1167 return diff;
1168 }
1169
1170-
1171- if (sched_pressure_p
1172+ if (sched_pressure != SCHED_PRESSURE_NONE
1173 && (INSN_TICK (tmp2) > clock_var || INSN_TICK (tmp) > clock_var))
1174 {
1175 if (INSN_TICK (tmp) <= clock_var)
1176@@ -1277,11 +2052,22 @@
1177 return val;
1178 }
1179
1180+ /* Prefer instructions that occur earlier in the model schedule. */
1181+ if (sched_pressure == SCHED_PRESSURE_MODEL)
1182+ {
1183+ int diff;
1184+
1185+ diff = model_index (tmp) - model_index (tmp2);
1186+ if (diff != 0)
1187+ return diff;
1188+ }
1189+
1190 /* Prefer the insn which has more later insns that depend on it.
1191 This gives the scheduler more freedom when scheduling later
1192 instructions at the expense of added register pressure. */
1193
1194- val = (dep_list_size (tmp2) - dep_list_size (tmp));
1195+ val = (dep_list_size (tmp2, SD_LIST_FORW)
1196+ - dep_list_size (tmp, SD_LIST_FORW));
1197
1198 if (flag_sched_dep_count_heuristic && val != 0)
1199 return val;
1200@@ -1480,12 +2266,15 @@
1201 int i;
1202 rtx *first = ready_lastpos (ready);
1203
1204- if (sched_pressure_p)
1205+ if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
1206 {
1207 for (i = 0; i < ready->n_ready; i++)
1208 if (!DEBUG_INSN_P (first[i]))
1209 setup_insn_reg_pressure_info (first[i]);
1210 }
1211+ if (sched_pressure == SCHED_PRESSURE_MODEL
1212+ && model_curr_point < model_num_insns)
1213+ model_set_excess_costs (first, ready->n_ready);
1214 SCHED_SORT (first, ready->n_ready);
1215 }
1216
1217@@ -1551,10 +2340,12 @@
1218 gcc_checking_assert (!DEBUG_INSN_P (insn));
1219
1220 for (use = INSN_REG_USE_LIST (insn); use != NULL; use = use->next_insn_use)
1221- if (dying_use_p (use) && bitmap_bit_p (curr_reg_live, use->regno))
1222- mark_regno_birth_or_death (use->regno, false);
1223+ if (dying_use_p (use))
1224+ mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure,
1225+ use->regno, false);
1226 for (set = INSN_REG_SET_LIST (insn); set != NULL; set = set->next_insn_set)
1227- mark_regno_birth_or_death (set->regno, true);
1228+ mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure,
1229+ set->regno, true);
1230 }
1231
1232 /* Set up or update (if UPDATE_P) max register pressure (see its
1233@@ -1626,11 +2417,618 @@
1234 void
1235 sched_setup_bb_reg_pressure_info (basic_block bb, rtx after)
1236 {
1237- gcc_assert (sched_pressure_p);
1238+ gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED);
1239 initiate_bb_reg_pressure_info (bb);
1240 setup_insn_max_reg_pressure (after, false);
1241 }
1242-
1243+
1244+/* Return (in order):
1245+
1246+ - positive if INSN adversely affects the pressure on one
1247+ register class
1248+
1249+ - negative if INSN reduces the pressure on one register class
1250+
1251+ - 0 if INSN doesn't affect the pressure on any register class. */
1252+
1253+static int
1254+model_classify_pressure (struct model_insn_info *insn)
1255+{
1256+ struct reg_pressure_data *reg_pressure;
1257+ int death[N_REG_CLASSES];
1258+ int cci, cl, sum;
1259+
1260+ calculate_reg_deaths (insn->insn, death);
1261+ reg_pressure = INSN_REG_PRESSURE (insn->insn);
1262+ sum = 0;
1263+ for (cci = 0; cci < ira_reg_class_cover_size; cci++)
1264+ {
1265+ cl = ira_reg_class_cover[cci];
1266+ if (death[cl] < reg_pressure[cci].set_increase)
1267+ return 1;
1268+ sum += reg_pressure[cci].set_increase - death[cl];
1269+ }
1270+ return sum;
1271+}
1272+
1273+/* Return true if INSN1 should come before INSN2 in the model schedule. */
1274+
1275+static int
1276+model_order_p (struct model_insn_info *insn1, struct model_insn_info *insn2)
1277+{
1278+ unsigned int height1, height2;
1279+ unsigned int priority1, priority2;
1280+
1281+ /* Prefer instructions with a higher model priority. */
1282+ if (insn1->model_priority != insn2->model_priority)
1283+ return insn1->model_priority > insn2->model_priority;
1284+
1285+ /* Combine the length of the longest path of satisfied true dependencies
1286+ that leads to each instruction (depth) with the length of the longest
1287+ path of any dependencies that leads from the instruction (alap).
1288+ Prefer instructions with the greatest combined length. If the combined
1289+ lengths are equal, prefer instructions with the greatest depth.
1290+
1291+ The idea is that, if we have a set S of "equal" instructions that each
1292+ have ALAP value X, and we pick one such instruction I, any true-dependent
1293+ successors of I that have ALAP value X - 1 should be preferred over S.
1294+ This encourages the schedule to be "narrow" rather than "wide".
1295+ However, if I is a low-priority instruction that we decided to
1296+ schedule because of its model_classify_pressure, and if there
1297+ is a set of higher-priority instructions T, the aforementioned
1298+ successors of I should not have the edge over T. */
1299+ height1 = insn1->depth + insn1->alap;
1300+ height2 = insn2->depth + insn2->alap;
1301+ if (height1 != height2)
1302+ return height1 > height2;
1303+ if (insn1->depth != insn2->depth)
1304+ return insn1->depth > insn2->depth;
1305+
1306+ /* We have no real preference between INSN1 an INSN2 as far as attempts
1307+ to reduce pressure go. Prefer instructions with higher priorities. */
1308+ priority1 = INSN_PRIORITY (insn1->insn);
1309+ priority2 = INSN_PRIORITY (insn2->insn);
1310+ if (priority1 != priority2)
1311+ return priority1 > priority2;
1312+
1313+ /* Use the original rtl sequence as a tie-breaker. */
1314+ return insn1 < insn2;
1315+}
1316+
1317+/* Add INSN to the model worklist immediately after PREV. Add it to the
1318+ beginning of the list if PREV is null. */
1319+
1320+static void
1321+model_add_to_worklist_at (struct model_insn_info *insn,
1322+ struct model_insn_info *prev)
1323+{
1324+ gcc_assert (QUEUE_INDEX (insn->insn) == QUEUE_NOWHERE);
1325+ QUEUE_INDEX (insn->insn) = QUEUE_READY;
1326+
1327+ insn->prev = prev;
1328+ if (prev)
1329+ {
1330+ insn->next = prev->next;
1331+ prev->next = insn;
1332+ }
1333+ else
1334+ {
1335+ insn->next = model_worklist;
1336+ model_worklist = insn;
1337+ }
1338+ if (insn->next)
1339+ insn->next->prev = insn;
1340+}
1341+
1342+/* Remove INSN from the model worklist. */
1343+
1344+static void
1345+model_remove_from_worklist (struct model_insn_info *insn)
1346+{
1347+ gcc_assert (QUEUE_INDEX (insn->insn) == QUEUE_READY);
1348+ QUEUE_INDEX (insn->insn) = QUEUE_NOWHERE;
1349+
1350+ if (insn->prev)
1351+ insn->prev->next = insn->next;
1352+ else
1353+ model_worklist = insn->next;
1354+ if (insn->next)
1355+ insn->next->prev = insn->prev;
1356+}
1357+
1358+/* Add INSN to the model worklist. Start looking for a suitable position
1359+ between neighbors PREV and NEXT, testing at most MAX_SCHED_READY_INSNS
1360+ insns either side. A null PREV indicates the beginning of the list and
1361+ a null NEXT indicates the end. */
1362+
1363+static void
1364+model_add_to_worklist (struct model_insn_info *insn,
1365+ struct model_insn_info *prev,
1366+ struct model_insn_info *next)
1367+{
1368+ int count;
1369+
1370+ count = MAX_SCHED_READY_INSNS;
1371+ if (count > 0 && prev && model_order_p (insn, prev))
1372+ do
1373+ {
1374+ count--;
1375+ prev = prev->prev;
1376+ }
1377+ while (count > 0 && prev && model_order_p (insn, prev));
1378+ else
1379+ while (count > 0 && next && model_order_p (next, insn))
1380+ {
1381+ count--;
1382+ prev = next;
1383+ next = next->next;
1384+ }
1385+ model_add_to_worklist_at (insn, prev);
1386+}
1387+
1388+/* INSN may now have a higher priority (in the model_order_p sense)
1389+ than before. Move it up the worklist if necessary. */
1390+
1391+static void
1392+model_promote_insn (struct model_insn_info *insn)
1393+{
1394+ struct model_insn_info *prev;
1395+ int count;
1396+
1397+ prev = insn->prev;
1398+ count = MAX_SCHED_READY_INSNS;
1399+ while (count > 0 && prev && model_order_p (insn, prev))
1400+ {
1401+ count--;
1402+ prev = prev->prev;
1403+ }
1404+ if (prev != insn->prev)
1405+ {
1406+ model_remove_from_worklist (insn);
1407+ model_add_to_worklist_at (insn, prev);
1408+ }
1409+}
1410+
1411+/* Add INSN to the end of the model schedule. */
1412+
1413+static void
1414+model_add_to_schedule (rtx insn)
1415+{
1416+ unsigned int point;
1417+
1418+ gcc_assert (QUEUE_INDEX (insn) == QUEUE_NOWHERE);
1419+ QUEUE_INDEX (insn) = QUEUE_SCHEDULED;
1420+
1421+ point = VEC_length (rtx, model_schedule);
1422+ VEC_quick_push (rtx, model_schedule, insn);
1423+ INSN_MODEL_INDEX (insn) = point + 1;
1424+}
1425+
1426+/* Analyze the instructions that are to be scheduled, setting up
1427+ MODEL_INSN_INFO (...) and model_num_insns accordingly. Add ready
1428+ instructions to model_worklist. */
1429+
1430+static void
1431+model_analyze_insns (void)
1432+{
1433+ rtx start, end, iter;
1434+ sd_iterator_def sd_it;
1435+ dep_t dep;
1436+ struct model_insn_info *insn, *con;
1437+
1438+ model_num_insns = 0;
1439+ start = PREV_INSN (current_sched_info->next_tail);
1440+ end = current_sched_info->prev_head;
1441+ for (iter = start; iter != end; iter = PREV_INSN (iter))
1442+ if (NONDEBUG_INSN_P (iter))
1443+ {
1444+ insn = MODEL_INSN_INFO (iter);
1445+ insn->insn = iter;
1446+ FOR_EACH_DEP (iter, SD_LIST_FORW, sd_it, dep)
1447+ {
1448+ con = MODEL_INSN_INFO (DEP_CON (dep));
1449+ if (con->insn && insn->alap < con->alap + 1)
1450+ insn->alap = con->alap + 1;
1451+ }
1452+
1453+ insn->old_queue = QUEUE_INDEX (iter);
1454+ QUEUE_INDEX (iter) = QUEUE_NOWHERE;
1455+
1456+ insn->unscheduled_preds = dep_list_size (iter, SD_LIST_HARD_BACK);
1457+ if (insn->unscheduled_preds == 0)
1458+ model_add_to_worklist (insn, NULL, model_worklist);
1459+
1460+ model_num_insns++;
1461+ }
1462+}
1463+
1464+/* The global state describes the register pressure at the start of the
1465+ model schedule. Initialize GROUP accordingly. */
1466+
1467+static void
1468+model_init_pressure_group (struct model_pressure_group *group)
1469+{
1470+ int cci, cl;
1471+
1472+ for (cci = 0; cci < ira_reg_class_cover_size; cci++)
1473+ {
1474+ cl = ira_reg_class_cover[cci];
1475+ group->limits[cci].pressure = curr_reg_pressure[cl];
1476+ group->limits[cci].point = 0;
1477+ }
1478+ /* Use index model_num_insns to record the state after the last
1479+ instruction in the model schedule. */
1480+ group->model = XNEWVEC (struct model_pressure_data,
1481+ (model_num_insns + 1) * ira_reg_class_cover_size);
1482+}
1483+
1484+/* Record that MODEL_REF_PRESSURE (GROUP, POINT, CCI) is PRESSURE.
1485+ Update the maximum pressure for the whole schedule. */
1486+
1487+static void
1488+model_record_pressure (struct model_pressure_group *group,
1489+ int point, int cci, int pressure)
1490+{
1491+ MODEL_REF_PRESSURE (group, point, cci) = pressure;
1492+ if (group->limits[cci].pressure < pressure)
1493+ {
1494+ group->limits[cci].pressure = pressure;
1495+ group->limits[cci].point = point;
1496+ }
1497+}
1498+
1499+/* INSN has just been added to the end of the model schedule. Record its
1500+ register-pressure information. */
1501+
1502+static void
1503+model_record_pressures (struct model_insn_info *insn)
1504+{
1505+ struct reg_pressure_data *reg_pressure;
1506+ int point, cci, cl, delta;
1507+ int death[N_REG_CLASSES];
1508+
1509+ point = model_index (insn->insn);
1510+ if (sched_verbose >= 2)
1511+ {
1512+ char buf[2048];
1513+
1514+ if (point == 0)
1515+ {
1516+ fprintf (sched_dump, "\n;;\tModel schedule:\n;;\n");
1517+ fprintf (sched_dump, ";;\t| idx insn | mpri hght dpth prio |\n");
1518+ }
1519+ print_pattern (buf, PATTERN (insn->insn), 0);
1520+ fprintf (sched_dump, ";;\t| %3d %4d | %4d %4d %4d %4d | %-30s ",
1521+ point, INSN_UID (insn->insn), insn->model_priority,
1522+ insn->depth + insn->alap, insn->depth,
1523+ INSN_PRIORITY (insn->insn), buf);
1524+ }
1525+ calculate_reg_deaths (insn->insn, death);
1526+ reg_pressure = INSN_REG_PRESSURE (insn->insn);
1527+ for (cci = 0; cci < ira_reg_class_cover_size; cci++)
1528+ {
1529+ cl = ira_reg_class_cover[cci];
1530+ delta = reg_pressure[cci].set_increase - death[cl];
1531+ if (sched_verbose >= 2)
1532+ fprintf (sched_dump, " %s:[%d,%+d]", reg_class_names[cl],
1533+ curr_reg_pressure[cl], delta);
1534+ model_record_pressure (&model_before_pressure, point, cci,
1535+ curr_reg_pressure[cl]);
1536+ }
1537+ if (sched_verbose >= 2)
1538+ fprintf (sched_dump, "\n");
1539+}
1540+
1541+/* All instructions have been added to the model schedule. Record the
1542+ final register pressure in GROUP and set up all MODEL_MAX_PRESSUREs. */
1543+
1544+static void
1545+model_record_final_pressures (struct model_pressure_group *group)
1546+{
1547+ int point, cci, max_pressure, ref_pressure, cl;
1548+
1549+ for (cci = 0; cci < ira_reg_class_cover_size; cci++)
1550+ {
1551+ /* Record the final pressure for this class. */
1552+ cl = ira_reg_class_cover[cci];
1553+ point = model_num_insns;
1554+ ref_pressure = curr_reg_pressure[cl];
1555+ model_record_pressure (group, point, cci, ref_pressure);
1556+
1557+ /* Record the original maximum pressure. */
1558+ group->limits[cci].orig_pressure = group->limits[cci].pressure;
1559+
1560+ /* Update the MODEL_MAX_PRESSURE for every point of the schedule. */
1561+ max_pressure = ref_pressure;
1562+ MODEL_MAX_PRESSURE (group, point, cci) = max_pressure;
1563+ while (point > 0)
1564+ {
1565+ point--;
1566+ ref_pressure = MODEL_REF_PRESSURE (group, point, cci);
1567+ max_pressure = MAX (max_pressure, ref_pressure);
1568+ MODEL_MAX_PRESSURE (group, point, cci) = max_pressure;
1569+ }
1570+ }
1571+}
1572+
1573+/* Update all successors of INSN, given that INSN has just been scheduled. */
1574+
1575+static void
1576+model_add_successors_to_worklist (struct model_insn_info *insn)
1577+{
1578+ sd_iterator_def sd_it;
1579+ struct model_insn_info *con;
1580+ dep_t dep;
1581+
1582+ FOR_EACH_DEP (insn->insn, SD_LIST_FORW, sd_it, dep)
1583+ {
1584+ con = MODEL_INSN_INFO (DEP_CON (dep));
1585+ /* Ignore debug instructions, and instructions from other blocks. */
1586+ if (con->insn)
1587+ {
1588+ con->unscheduled_preds--;
1589+
1590+ /* Update the depth field of each true-dependent successor.
1591+ Increasing the depth gives them a higher priority than
1592+ before. */
1593+ if (DEP_TYPE (dep) == REG_DEP_TRUE && con->depth < insn->depth + 1)
1594+ {
1595+ con->depth = insn->depth + 1;
1596+ if (QUEUE_INDEX (con->insn) == QUEUE_READY)
1597+ model_promote_insn (con);
1598+ }
1599+
1600+ /* If this is a true dependency, or if there are no remaining
1601+ dependencies for CON (meaning that CON only had non-true
1602+ dependencies), make sure that CON is on the worklist.
1603+ We don't bother otherwise because it would tend to fill the
1604+ worklist with a lot of low-priority instructions that are not
1605+ yet ready to issue. */
1606+ if ((con->depth > 0 || con->unscheduled_preds == 0)
1607+ && QUEUE_INDEX (con->insn) == QUEUE_NOWHERE)
1608+ model_add_to_worklist (con, insn, insn->next);
1609+ }
1610+ }
1611+}
1612+
1613+/* Give INSN a higher priority than any current instruction, then give
1614+ unscheduled predecessors of INSN a higher priority still. If any of
1615+ those predecessors are not on the model worklist, do the same for its
1616+ predecessors, and so on. */
1617+
1618+static void
1619+model_promote_predecessors (struct model_insn_info *insn)
1620+{
1621+ struct model_insn_info *pro, *first;
1622+ sd_iterator_def sd_it;
1623+ dep_t dep;
1624+
1625+ if (sched_verbose >= 7)
1626+ fprintf (sched_dump, ";;\t+--- priority of %d = %d, priority of",
1627+ INSN_UID (insn->insn), model_next_priority);
1628+ insn->model_priority = model_next_priority++;
1629+ model_remove_from_worklist (insn);
1630+ model_add_to_worklist_at (insn, NULL);
1631+
1632+ first = NULL;
1633+ for (;;)
1634+ {
1635+ FOR_EACH_DEP (insn->insn, SD_LIST_HARD_BACK, sd_it, dep)
1636+ {
1637+ pro = MODEL_INSN_INFO (DEP_PRO (dep));
1638+ /* The first test is to ignore debug instructions, and instructions
1639+ from other blocks. */
1640+ if (pro->insn
1641+ && pro->model_priority != model_next_priority
1642+ && QUEUE_INDEX (pro->insn) != QUEUE_SCHEDULED)
1643+ {
1644+ pro->model_priority = model_next_priority;
1645+ if (sched_verbose >= 7)
1646+ fprintf (sched_dump, " %d", INSN_UID (pro->insn));
1647+ if (QUEUE_INDEX (pro->insn) == QUEUE_READY)
1648+ {
1649+ /* PRO is already in the worklist, but it now has
1650+ a higher priority than before. Move it at the
1651+ appropriate place. */
1652+ model_remove_from_worklist (pro);
1653+ model_add_to_worklist (pro, NULL, model_worklist);
1654+ }
1655+ else
1656+ {
1657+ /* PRO isn't in the worklist. Recursively process
1658+ its predecessors until we find one that is. */
1659+ pro->next = first;
1660+ first = pro;
1661+ }
1662+ }
1663+ }
1664+ if (!first)
1665+ break;
1666+ insn = first;
1667+ first = insn->next;
1668+ }
1669+ if (sched_verbose >= 7)
1670+ fprintf (sched_dump, " = %d\n", model_next_priority);
1671+ model_next_priority++;
1672+}
1673+
1674+/* Pick one instruction from model_worklist and process it. */
1675+
1676+static void
1677+model_choose_insn (void)
1678+{
1679+ struct model_insn_info *insn, *fallback;
1680+ int count;
1681+
1682+ if (sched_verbose >= 7)
1683+ {
1684+ fprintf (sched_dump, ";;\t+--- worklist:\n");
1685+ insn = model_worklist;
1686+ count = MAX_SCHED_READY_INSNS;
1687+ while (count > 0 && insn)
1688+ {
1689+ fprintf (sched_dump, ";;\t+--- %d [%d, %d, %d, %d]\n",
1690+ INSN_UID (insn->insn), insn->model_priority,
1691+ insn->depth + insn->alap, insn->depth,
1692+ INSN_PRIORITY (insn->insn));
1693+ count--;
1694+ insn = insn->next;
1695+ }
1696+ }
1697+
1698+ /* Look for a ready instruction whose model_classify_priority is zero
1699+ or negative, picking the highest-priority one. Adding such an
1700+ instruction to the schedule now should do no harm, and may actually
1701+ do some good.
1702+
1703+ Failing that, see whether there is an instruction with the highest
1704+ extant model_priority that is not yet ready, but which would reduce
1705+ pressure if it became ready. This is designed to catch cases like:
1706+
1707+ (set (mem (reg R1)) (reg R2))
1708+
1709+ where the instruction is the last remaining use of R1 and where the
1710+ value of R2 is not yet available (or vice versa). The death of R1
1711+ means that this instruction already reduces pressure. It is of
1712+ course possible that the computation of R2 involves other registers
1713+ that are hard to kill, but such cases are rare enough for this
1714+ heuristic to be a win in general.
1715+
1716+ Failing that, just pick the highest-priority instruction in the
1717+ worklist. */
1718+ count = MAX_SCHED_READY_INSNS;
1719+ insn = model_worklist;
1720+ fallback = 0;
1721+ for (;;)
1722+ {
1723+ if (count == 0 || !insn)
1724+ {
1725+ insn = fallback ? fallback : model_worklist;
1726+ break;
1727+ }
1728+ if (insn->unscheduled_preds)
1729+ {
1730+ if (model_worklist->model_priority == insn->model_priority
1731+ && !fallback
1732+ && model_classify_pressure (insn) < 0)
1733+ fallback = insn;
1734+ }
1735+ else
1736+ {
1737+ if (model_classify_pressure (insn) <= 0)
1738+ break;
1739+ }
1740+ count--;
1741+ insn = insn->next;
1742+ }
1743+
1744+ if (sched_verbose >= 7 && insn != model_worklist)
1745+ {
1746+ if (insn->unscheduled_preds)
1747+ fprintf (sched_dump, ";;\t+--- promoting insn %d, with dependencies\n",
1748+ INSN_UID (insn->insn));
1749+ else
1750+ fprintf (sched_dump, ";;\t+--- promoting insn %d, which is ready\n",
1751+ INSN_UID (insn->insn));
1752+ }
1753+ if (insn->unscheduled_preds)
1754+ /* INSN isn't yet ready to issue. Give all its predecessors the
1755+ highest priority. */
1756+ model_promote_predecessors (insn);
1757+ else
1758+ {
1759+ /* INSN is ready. Add it to the end of model_schedule and
1760+ process its successors. */
1761+ model_add_successors_to_worklist (insn);
1762+ model_remove_from_worklist (insn);
1763+ model_add_to_schedule (insn->insn);
1764+ model_record_pressures (insn);
1765+ update_register_pressure (insn->insn);
1766+ }
1767+}
1768+
1769+/* Restore all QUEUE_INDEXs to the values that they had before
1770+ model_start_schedule was called. */
1771+
1772+static void
1773+model_reset_queue_indices (void)
1774+{
1775+ unsigned int i;
1776+ rtx insn;
1777+
1778+ FOR_EACH_VEC_ELT (rtx, model_schedule, i, insn)
1779+ QUEUE_INDEX (insn) = MODEL_INSN_INFO (insn)->old_queue;
1780+}
1781+
1782+/* We have calculated the model schedule and spill costs. Print a summary
1783+ to sched_dump. */
1784+
1785+static void
1786+model_dump_pressure_summary (void)
1787+{
1788+ int cci, cl;
1789+
1790+ fprintf (sched_dump, ";; Pressure summary:");
1791+ for (cci = 0; cci < ira_reg_class_cover_size; cci++)
1792+ {
1793+ cl = ira_reg_class_cover[cci];
1794+ fprintf (sched_dump, " %s:%d", reg_class_names[cl],
1795+ model_before_pressure.limits[cci].pressure);
1796+ }
1797+ fprintf (sched_dump, "\n\n");
1798+}
1799+
1800+/* Initialize the SCHED_PRESSURE_MODEL information for the current
1801+ scheduling region. */
1802+
1803+static void
1804+model_start_schedule (void)
1805+{
1806+ basic_block bb;
1807+
1808+ model_next_priority = 1;
1809+ model_schedule = VEC_alloc (rtx, heap, sched_max_luid);
1810+ model_insns = XCNEWVEC (struct model_insn_info, sched_max_luid);
1811+
1812+ bb = BLOCK_FOR_INSN (NEXT_INSN (current_sched_info->prev_head));
1813+ initiate_reg_pressure_info (df_get_live_in (bb));
1814+
1815+ model_analyze_insns ();
1816+ model_init_pressure_group (&model_before_pressure);
1817+ while (model_worklist)
1818+ model_choose_insn ();
1819+ gcc_assert (model_num_insns == (int) VEC_length (rtx, model_schedule));
1820+ if (sched_verbose >= 2)
1821+ fprintf (sched_dump, "\n");
1822+
1823+ model_record_final_pressures (&model_before_pressure);
1824+ model_reset_queue_indices ();
1825+
1826+ XDELETEVEC (model_insns);
1827+
1828+ model_curr_point = 0;
1829+ initiate_reg_pressure_info (df_get_live_in (bb));
1830+ if (sched_verbose >= 1)
1831+ model_dump_pressure_summary ();
1832+}
1833+
1834+/* Free the information associated with GROUP. */
1835+
1836+static void
1837+model_finalize_pressure_group (struct model_pressure_group *group)
1838+{
1839+ XDELETEVEC (group->model);
1840+}
1841+
1842+/* Free the information created by model_start_schedule. */
1843+
1844+static void
1845+model_end_schedule (void)
1846+{
1847+ model_finalize_pressure_group (&model_before_pressure);
1848+ VEC_free (rtx, heap, model_schedule);
1849+}
1850+
1851 /* INSN is the "currently executing insn". Launch each insn which was
1852 waiting on INSN. READY is the ready list which contains the insns
1853 that are ready to fire. CLOCK is the current cycle. The function
1854@@ -1667,10 +3065,14 @@
1855 reg_class_names[ira_reg_class_cover[i]],
1856 pressure_info[i].set_increase, pressure_info[i].change);
1857 }
1858+ if (sched_pressure == SCHED_PRESSURE_MODEL
1859+ && model_curr_point < model_num_insns
1860+ && model_index (insn) == model_curr_point)
1861+ fprintf (sched_dump, ":model %d", model_curr_point);
1862 fputc ('\n', sched_dump);
1863 }
1864
1865- if (sched_pressure_p && !DEBUG_INSN_P (insn))
1866+ if (sched_pressure == SCHED_PRESSURE_WEIGHTED && !DEBUG_INSN_P (insn))
1867 update_reg_and_insn_max_reg_pressure (insn);
1868
1869 /* Scheduling instruction should have all its dependencies resolved and
1870@@ -1728,6 +3130,24 @@
1871 gcc_assert (QUEUE_INDEX (insn) == QUEUE_NOWHERE);
1872 QUEUE_INDEX (insn) = QUEUE_SCHEDULED;
1873
1874+ if (sched_pressure == SCHED_PRESSURE_MODEL
1875+ && model_curr_point < model_num_insns
1876+ && NONDEBUG_INSN_P (insn))
1877+ {
1878+ if (model_index (insn) == model_curr_point)
1879+ do
1880+ model_curr_point++;
1881+ while (model_curr_point < model_num_insns
1882+ && (QUEUE_INDEX (MODEL_INSN (model_curr_point))
1883+ == QUEUE_SCHEDULED));
1884+ else
1885+ model_recompute (insn);
1886+ model_update_limit_points ();
1887+ update_register_pressure (insn);
1888+ if (sched_verbose >= 2)
1889+ print_curr_reg_pressure ();
1890+ }
1891+
1892 gcc_assert (INSN_TICK (insn) >= MIN_TICK);
1893 if (INSN_TICK (insn) > clock_var)
1894 /* INSN has been prematurely moved from the queue to the ready list.
1895@@ -2056,7 +3476,16 @@
1896 /* If the ready list is full, delay the insn for 1 cycle.
1897 See the comment in schedule_block for the rationale. */
1898 if (!reload_completed
1899- && ready->n_ready - ready->n_debug > MAX_SCHED_READY_INSNS
1900+ && (ready->n_ready - ready->n_debug > MAX_SCHED_READY_INSNS
1901+ || (sched_pressure == SCHED_PRESSURE_MODEL
1902+ /* Limit pressure recalculations to MAX_SCHED_READY_INSNS
1903+ instructions too. */
1904+ && model_index (insn) > (model_curr_point
1905+ + MAX_SCHED_READY_INSNS)))
1906+ && !(sched_pressure == SCHED_PRESSURE_MODEL
1907+ && model_curr_point < model_num_insns
1908+ /* Always allow the next model instruction to issue. */
1909+ && model_index (insn) == model_curr_point)
1910 && !SCHED_GROUP_P (insn)
1911 && insn != skip_insn)
1912 {
1913@@ -2293,12 +3722,12 @@
1914 fprintf (sched_dump, " %s:%d",
1915 (*current_sched_info->print_insn) (p[i], 0),
1916 INSN_LUID (p[i]));
1917- if (sched_pressure_p)
1918+ if (sched_pressure != SCHED_PRESSURE_NONE)
1919 fprintf (sched_dump, "(cost=%d",
1920 INSN_REG_PRESSURE_EXCESS_COST_CHANGE (p[i]));
1921 if (INSN_TICK (p[i]) > clock_var)
1922 fprintf (sched_dump, ":delay=%d", INSN_TICK (p[i]) - clock_var);
1923- if (sched_pressure_p)
1924+ if (sched_pressure != SCHED_PRESSURE_NONE)
1925 fprintf (sched_dump, ")");
1926 }
1927 fprintf (sched_dump, "\n");
1928@@ -2609,8 +4038,8 @@
1929 {
1930 if (state_dead_lock_p (state)
1931 || insn_finishes_cycle_p (insn))
1932- /* We won't issue any more instructions in the next
1933- choice_state. */
1934+ /* We won't issue any more instructions in the next
1935+ choice_state. */
1936 top->rest = 0;
1937 else
1938 top->rest--;
1939@@ -2813,6 +4242,59 @@
1940 }
1941 }
1942
1943+/* Examine all insns on the ready list and queue those which can't be
1944+ issued in this cycle. TEMP_STATE is temporary scheduler state we
1945+ can use as scratch space. If FIRST_CYCLE_INSN_P is true, no insns
1946+ have been issued for the current cycle, which means it is valid to
1947+ issue an asm statement. */
1948+
1949+static void
1950+prune_ready_list (state_t temp_state, bool first_cycle_insn_p)
1951+{
1952+ int i;
1953+
1954+ restart:
1955+ for (i = 0; i < ready.n_ready; i++)
1956+ {
1957+ rtx insn = ready_element (&ready, i);
1958+ int cost = 0;
1959+
1960+ if (recog_memoized (insn) < 0)
1961+ {
1962+ if (!first_cycle_insn_p
1963+ && (GET_CODE (PATTERN (insn)) == ASM_INPUT
1964+ || asm_noperands (PATTERN (insn)) >= 0))
1965+ cost = 1;
1966+ }
1967+ else if (sched_pressure != SCHED_PRESSURE_NONE)
1968+ {
1969+ if (sched_pressure == SCHED_PRESSURE_MODEL
1970+ && INSN_TICK (insn) <= clock_var)
1971+ {
1972+ memcpy (temp_state, curr_state, dfa_state_size);
1973+ if (state_transition (temp_state, insn) >= 0)
1974+ INSN_TICK (insn) = clock_var + 1;
1975+ }
1976+ cost = 0;
1977+ }
1978+ else
1979+ {
1980+ memcpy (temp_state, curr_state, dfa_state_size);
1981+ cost = state_transition (temp_state, insn);
1982+ if (cost < 0)
1983+ cost = 0;
1984+ else if (cost == 0)
1985+ cost = 1;
1986+ }
1987+ if (cost >= 1)
1988+ {
1989+ ready_remove (&ready, i);
1990+ queue_insn (insn, cost);
1991+ goto restart;
1992+ }
1993+ }
1994+}
1995+
1996 /* Use forward list scheduling to rearrange insns of block pointed to by
1997 TARGET_BB, possibly bringing insns from subsequent blocks in the same
1998 region. */
1999@@ -2882,6 +4364,9 @@
2000 in try_ready () (which is called through init_ready_list ()). */
2001 (*current_sched_info->init_ready_list) ();
2002
2003+ if (sched_pressure == SCHED_PRESSURE_MODEL)
2004+ model_start_schedule ();
2005+
2006 /* The algorithm is O(n^2) in the number of ready insns at any given
2007 time in the worst case. Before reload we are more likely to have
2008 big lists so truncate them to a reasonable size. */
2009@@ -2963,6 +4448,10 @@
2010 }
2011 while (advance > 0);
2012
2013+ prune_ready_list (temp_state, true);
2014+ if (ready.n_ready == 0)
2015+ continue;
2016+
2017 if (sort_p)
2018 {
2019 /* Sort the ready list based on priority. */
2020@@ -3040,7 +4529,7 @@
2021 fprintf (sched_dump, ";;\tReady list (t = %3d): ",
2022 clock_var);
2023 debug_ready_list (&ready);
2024- if (sched_pressure_p)
2025+ if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
2026 print_curr_reg_pressure ();
2027 }
2028
2029@@ -3084,7 +4573,8 @@
2030 else
2031 insn = ready_remove_first (&ready);
2032
2033- if (sched_pressure_p && INSN_TICK (insn) > clock_var)
2034+ if (sched_pressure != SCHED_PRESSURE_NONE
2035+ && INSN_TICK (insn) > clock_var)
2036 {
2037 ready_add (&ready, insn, true);
2038 advance = 1;
2039@@ -3112,44 +4602,6 @@
2040 }
2041
2042 sort_p = TRUE;
2043- memcpy (temp_state, curr_state, dfa_state_size);
2044- if (recog_memoized (insn) < 0)
2045- {
2046- asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
2047- || asm_noperands (PATTERN (insn)) >= 0);
2048- if (!first_cycle_insn_p && asm_p)
2049- /* This is asm insn which is tried to be issued on the
2050- cycle not first. Issue it on the next cycle. */
2051- cost = 1;
2052- else
2053- /* A USE insn, or something else we don't need to
2054- understand. We can't pass these directly to
2055- state_transition because it will trigger a
2056- fatal error for unrecognizable insns. */
2057- cost = 0;
2058- }
2059- else if (sched_pressure_p)
2060- cost = 0;
2061- else
2062- {
2063- cost = state_transition (temp_state, insn);
2064- if (cost < 0)
2065- cost = 0;
2066- else if (cost == 0)
2067- cost = 1;
2068- }
2069-
2070- if (cost >= 1)
2071- {
2072- queue_insn (insn, cost);
2073- if (SCHED_GROUP_P (insn))
2074- {
2075- advance = cost;
2076- break;
2077- }
2078-
2079- continue;
2080- }
2081
2082 if (current_sched_info->can_schedule_ready_p
2083 && ! (*current_sched_info->can_schedule_ready_p) (insn))
2084@@ -3200,11 +4652,17 @@
2085 reemit_notes (insn);
2086 last_scheduled_insn = insn;
2087
2088- if (memcmp (curr_state, temp_state, dfa_state_size) != 0)
2089- {
2090- cycle_issued_insns++;
2091- memcpy (curr_state, temp_state, dfa_state_size);
2092- }
2093+ if (recog_memoized (insn) >= 0)
2094+ {
2095+ cost = state_transition (curr_state, insn);
2096+ if (sched_pressure != SCHED_PRESSURE_WEIGHTED)
2097+ gcc_assert (cost < 0);
2098+ cycle_issued_insns++;
2099+ asm_p = false;
2100+ }
2101+ else
2102+ asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
2103+ || asm_noperands (PATTERN (insn)) >= 0);
2104
2105 if (targetm.sched.variable_issue)
2106 can_issue_more =
2107@@ -3225,6 +4683,9 @@
2108
2109 first_cycle_insn_p = false;
2110
2111+ if (ready.n_ready > 0)
2112+ prune_ready_list (temp_state, false);
2113+
2114 /* Sort the ready list based on priority. This must be
2115 redone here, as schedule_insn may have readied additional
2116 insns that will not be sorted correctly. */
2117@@ -3321,6 +4782,9 @@
2118 }
2119 }
2120
2121+ if (sched_pressure == SCHED_PRESSURE_MODEL)
2122+ model_end_schedule ();
2123+
2124 if (sched_verbose)
2125 fprintf (sched_dump, ";; total time = %d\n", clock_var);
2126
2127@@ -3424,10 +4888,14 @@
2128 if (targetm.sched.dispatch (NULL_RTX, IS_DISPATCH_ON))
2129 targetm.sched.dispatch_do (NULL_RTX, DISPATCH_INIT);
2130
2131- sched_pressure_p = (flag_sched_pressure && ! reload_completed
2132- && common_sched_info->sched_pass_id == SCHED_RGN_PASS);
2133+ if (flag_sched_pressure
2134+ && !reload_completed
2135+ && common_sched_info->sched_pass_id == SCHED_RGN_PASS)
2136+ sched_pressure = flag_sched_pressure_algorithm;
2137+ else
2138+ sched_pressure = SCHED_PRESSURE_NONE;
2139
2140- if (sched_pressure_p)
2141+ if (sched_pressure != SCHED_PRESSURE_NONE)
2142 ira_setup_eliminable_regset ();
2143
2144 /* Initialize SPEC_INFO. */
2145@@ -3504,7 +4972,7 @@
2146 if (targetm.sched.init_global)
2147 targetm.sched.init_global (sched_dump, sched_verbose, get_max_uid () + 1);
2148
2149- if (sched_pressure_p)
2150+ if (sched_pressure != SCHED_PRESSURE_NONE)
2151 {
2152 int i, max_regno = max_reg_num ();
2153
2154@@ -3517,8 +4985,11 @@
2155 ? ira_class_translate[REGNO_REG_CLASS (i)]
2156 : reg_cover_class (i));
2157 curr_reg_live = BITMAP_ALLOC (NULL);
2158- saved_reg_live = BITMAP_ALLOC (NULL);
2159- region_ref_regs = BITMAP_ALLOC (NULL);
2160+ if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
2161+ {
2162+ saved_reg_live = BITMAP_ALLOC (NULL);
2163+ region_ref_regs = BITMAP_ALLOC (NULL);
2164+ }
2165 }
2166
2167 curr_state = xmalloc (dfa_state_size);
2168@@ -3618,12 +5089,15 @@
2169 sched_finish (void)
2170 {
2171 haifa_finish_h_i_d ();
2172- if (sched_pressure_p)
2173+ if (sched_pressure != SCHED_PRESSURE_NONE)
2174 {
2175+ if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
2176+ {
2177+ BITMAP_FREE (region_ref_regs);
2178+ BITMAP_FREE (saved_reg_live);
2179+ }
2180+ BITMAP_FREE (curr_reg_live);
2181 free (sched_regno_cover_class);
2182- BITMAP_FREE (region_ref_regs);
2183- BITMAP_FREE (saved_reg_live);
2184- BITMAP_FREE (curr_reg_live);
2185 }
2186 free (curr_state);
2187
2188@@ -3936,7 +5410,7 @@
2189 INSN_TICK (next) = tick;
2190
2191 delay = tick - clock_var;
2192- if (delay <= 0 || sched_pressure_p)
2193+ if (delay <= 0 || sched_pressure != SCHED_PRESSURE_NONE)
2194 delay = QUEUE_READY;
2195
2196 change_queue_index (next, delay);
2197@@ -5185,7 +6659,7 @@
2198 if (insn == jump)
2199 break;
2200
2201- if (dep_list_size (insn) == 0)
2202+ if (dep_list_size (insn, SD_LIST_FORW) == 0)
2203 {
2204 dep_def _new_dep, *new_dep = &_new_dep;
2205
2206@@ -5556,6 +7030,7 @@
2207
2208 FOR_EACH_VEC_ELT (haifa_insn_data_def, h_i_d, i, data)
2209 {
2210+ free (data->max_reg_pressure);
2211 if (data->reg_pressure != NULL)
2212 free (data->reg_pressure);
2213 for (use = data->reg_use_list; use != NULL; use = next)
2214
2215=== modified file 'gcc/sched-deps.c'
2216--- old/gcc/sched-deps.c 2011-12-08 13:33:58 +0000
2217+++ new/gcc/sched-deps.c 2012-02-08 23:39:45 +0000
2218@@ -450,7 +450,7 @@
2219 static void add_dependence_list_and_free (struct deps_desc *, rtx,
2220 rtx *, int, enum reg_note);
2221 static void delete_all_dependences (rtx);
2222-static void fixup_sched_groups (rtx);
2223+static void chain_to_prev_insn (rtx);
2224
2225 static void flush_pending_lists (struct deps_desc *, rtx, int, int);
2226 static void sched_analyze_1 (struct deps_desc *, rtx, rtx);
2227@@ -1490,7 +1490,7 @@
2228 the previous nonnote insn. */
2229
2230 static void
2231-fixup_sched_groups (rtx insn)
2232+chain_to_prev_insn (rtx insn)
2233 {
2234 sd_iterator_def sd_it;
2235 dep_t dep;
2236@@ -1999,7 +1999,7 @@
2237 static struct reg_pressure_data *pressure_info;
2238 rtx link;
2239
2240- gcc_assert (sched_pressure_p);
2241+ gcc_assert (sched_pressure != SCHED_PRESSURE_NONE);
2242
2243 if (! INSN_P (insn))
2244 return;
2245@@ -2030,8 +2030,9 @@
2246 len = sizeof (struct reg_pressure_data) * ira_reg_class_cover_size;
2247 pressure_info
2248 = INSN_REG_PRESSURE (insn) = (struct reg_pressure_data *) xmalloc (len);
2249- INSN_MAX_REG_PRESSURE (insn) = (int *) xcalloc (ira_reg_class_cover_size
2250- * sizeof (int), 1);
2251+ if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
2252+ INSN_MAX_REG_PRESSURE (insn) = (int *) xcalloc (ira_reg_class_cover_size
2253+ * sizeof (int), 1);
2254 for (i = 0; i < ira_reg_class_cover_size; i++)
2255 {
2256 cl = ira_reg_class_cover[i];
2257@@ -2775,7 +2776,7 @@
2258 || (NONJUMP_INSN_P (insn) && control_flow_insn_p (insn)))
2259 reg_pending_barrier = MOVE_BARRIER;
2260
2261- if (sched_pressure_p)
2262+ if (sched_pressure != SCHED_PRESSURE_NONE)
2263 {
2264 setup_insn_reg_uses (deps, insn);
2265 setup_insn_reg_pressure_info (insn);
2266@@ -3076,7 +3077,7 @@
2267 instructions that follow seem like they should be part
2268 of the call group.
2269
2270- Also, if we did, fixup_sched_groups() would move the
2271+ Also, if we did, chain_to_prev_insn would move the
2272 deps of the debug insn to the call insn, modifying
2273 non-debug post-dependency counts of the debug insn
2274 dependencies and otherwise messing with the scheduling
2275@@ -3222,6 +3223,37 @@
2276 return true;
2277 }
2278
2279+/* Return true if INSN should be made dependent on the previous instruction
2280+ group, and if all INSN's dependencies should be moved to the first
2281+ instruction of that group. */
2282+
2283+static bool
2284+chain_to_prev_insn_p (rtx insn)
2285+{
2286+ rtx prev, x;
2287+
2288+ /* INSN forms a group with the previous instruction. */
2289+ if (SCHED_GROUP_P (insn))
2290+ return true;
2291+
2292+ /* If the previous instruction clobbers a register R and this one sets
2293+ part of R, the clobber was added specifically to help us track the
2294+ liveness of R. There's no point scheduling the clobber and leaving
2295+ INSN behind, especially if we move the clobber to another block. */
2296+ prev = prev_nonnote_nondebug_insn (insn);
2297+ if (prev
2298+ && INSN_P (prev)
2299+ && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
2300+ && GET_CODE (PATTERN (prev)) == CLOBBER)
2301+ {
2302+ x = XEXP (PATTERN (prev), 0);
2303+ if (set_of (x, insn))
2304+ return true;
2305+ }
2306+
2307+ return false;
2308+}
2309+
2310 /* Analyze INSN with DEPS as a context. */
2311 void
2312 deps_analyze_insn (struct deps_desc *deps, rtx insn)
2313@@ -3358,8 +3390,9 @@
2314
2315 /* Fixup the dependencies in the sched group. */
2316 if ((NONJUMP_INSN_P (insn) || JUMP_P (insn))
2317- && SCHED_GROUP_P (insn) && !sel_sched_p ())
2318- fixup_sched_groups (insn);
2319+ && chain_to_prev_insn_p (insn)
2320+ && !sel_sched_p ())
2321+ chain_to_prev_insn (insn);
2322 }
2323
2324 /* Initialize DEPS for the new block beginning with HEAD. */
2325
2326=== modified file 'gcc/sched-int.h'
2327--- old/gcc/sched-int.h 2011-02-02 04:31:35 +0000
2328+++ new/gcc/sched-int.h 2012-02-08 23:39:02 +0000
2329@@ -651,7 +651,7 @@
2330
2331 /* Do register pressure sensitive insn scheduling if the flag is set
2332 up. */
2333-extern bool sched_pressure_p;
2334+extern enum sched_pressure_algorithm sched_pressure;
2335
2336 /* Map regno -> its cover class. The map defined only when
2337 SCHED_PRESSURE_P is true. */
2338@@ -773,16 +773,16 @@
2339
2340 short cost;
2341
2342+ /* '> 0' if priority is valid,
2343+ '== 0' if priority was not yet computed,
2344+ '< 0' if priority in invalid and should be recomputed. */
2345+ signed char priority_status;
2346+
2347 /* Set if there's DEF-USE dependence between some speculatively
2348 moved load insn and this one. */
2349 unsigned int fed_by_spec_load : 1;
2350 unsigned int is_load_insn : 1;
2351
2352- /* '> 0' if priority is valid,
2353- '== 0' if priority was not yet computed,
2354- '< 0' if priority in invalid and should be recomputed. */
2355- signed char priority_status;
2356-
2357 /* What speculations are necessary to apply to schedule the instruction. */
2358 ds_t todo_spec;
2359
2360@@ -817,6 +817,7 @@
2361 /* Info about how scheduling the insn changes cost of register
2362 pressure excess (between source and target). */
2363 int reg_pressure_excess_cost_change;
2364+ int model_index;
2365 };
2366
2367 typedef struct _haifa_insn_data haifa_insn_data_def;
2368@@ -839,6 +840,7 @@
2369 #define INSN_REG_PRESSURE_EXCESS_COST_CHANGE(INSN) \
2370 (HID (INSN)->reg_pressure_excess_cost_change)
2371 #define INSN_PRIORITY_STATUS(INSN) (HID (INSN)->priority_status)
2372+#define INSN_MODEL_INDEX(INSN) (HID (INSN)->model_index)
2373
2374 typedef struct _haifa_deps_insn_data haifa_deps_insn_data_def;
2375 typedef haifa_deps_insn_data_def *haifa_deps_insn_data_t;
2376
2377=== modified file 'gcc/sched-rgn.c'
2378--- old/gcc/sched-rgn.c 2011-06-04 10:15:48 +0000
2379+++ new/gcc/sched-rgn.c 2012-02-08 23:38:13 +0000
2380@@ -2943,7 +2943,7 @@
2381
2382 sched_extend_ready_list (rgn_n_insns);
2383
2384- if (sched_pressure_p)
2385+ if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
2386 {
2387 sched_init_region_reg_pressure_info ();
2388 for (bb = 0; bb < current_nr_blocks; bb++)
2389
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106870.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106870.patch
deleted file mode 100644
index 1a5448403..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106870.patch
+++ /dev/null
@@ -1,28 +0,0 @@
12012-02-20 Andrew Stubbs <ams@codesourcery.com>
2
3 gcc/
4 * config/arm/arm.c (arm_print_operand): Avoid null-pointer
5 dereference from MEM_SIZE.
6
7=== modified file 'gcc/config/arm/arm.c'
8--- old/gcc/config/arm/arm.c 2012-02-09 00:47:59 +0000
9+++ new/gcc/config/arm/arm.c 2012-02-20 15:32:26 +0000
10@@ -17446,6 +17446,7 @@
11 rtx addr;
12 bool postinc = FALSE;
13 unsigned align, memsize, align_bits;
14+ rtx memsize_rtx;
15
16 gcc_assert (GET_CODE (x) == MEM);
17 addr = XEXP (x, 0);
18@@ -17460,7 +17461,8 @@
19 instruction (for some alignments) as an aid to the memory subsystem
20 of the target. */
21 align = MEM_ALIGN (x) >> 3;
22- memsize = INTVAL (MEM_SIZE (x));
23+ memsize_rtx = MEM_SIZE (x);
24+ memsize = memsize_rtx ? INTVAL (memsize_rtx) : 0;
25
26 /* Only certain alignment specifiers are supported by the hardware. */
27 if (memsize == 16 && (align % 32) == 0)
28
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106872.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106872.patch
deleted file mode 100644
index 9bfd969df..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106872.patch
+++ /dev/null
@@ -1,126 +0,0 @@
12012-02-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline.
4 2011-12-05 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
5
6 gcc/
7 * config/arm/arm.c (vfp3_const_double_for_fract_bits): Define.
8 * config/arm/arm-protos.h (vfp3_const_double_for_fract_bits): Declare.
9 * config/arm/constraints.md ("Dt"): New constraint.
10 * config/arm/predicates.md (const_double_vcvt_power_of_two_reciprocal):
11 New.
12 * config/arm/vfp.md (*arm_combine_vcvt_f32_s32): New.
13 (*arm_combine_vcvt_f32_u32): New.
14
15 LP:#900426
16
17 2011-12-06 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
18 * config/arm/vfp.md (*combine_vcvt_f64_<FCVTI32typename>): Fix
19 formatting character for vmov.f64 case.
20
212012-02-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
22
23 gcc/
24 * config/arm/arm.c (arm_print_operand): Remove wrongly merged code.
25 (vfp3_const_double_for_fract_bits): Likewise.
26
27=== modified file 'gcc/config/arm/arm-protos.h'
28--- old/gcc/config/arm/arm-protos.h 2011-12-06 10:42:29 +0000
29+++ new/gcc/config/arm/arm-protos.h 2012-02-22 13:31:54 +0000
30@@ -238,6 +238,7 @@
31 };
32
33 extern const struct tune_params *current_tune;
34+extern int vfp3_const_double_for_fract_bits (rtx);
35 #endif /* RTX_CODE */
36
37 #endif /* ! GCC_ARM_PROTOS_H */
38
39=== modified file 'gcc/config/arm/constraints.md'
40--- old/gcc/config/arm/constraints.md 2011-12-06 10:42:29 +0000
41+++ new/gcc/config/arm/constraints.md 2012-02-22 13:31:54 +0000
42@@ -29,7 +29,7 @@
43 ;; in Thumb-1 state: I, J, K, L, M, N, O
44
45 ;; The following multi-letter normal constraints have been used:
46-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz
47+;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
48 ;; in Thumb-1 state: Pa, Pb, Pc, Pd
49 ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
50
51@@ -291,6 +291,12 @@
52 (and (match_code "const_double")
53 (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
54
55+(define_constraint "Dt"
56+ "@internal
57+ In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
58+ (and (match_code "const_double")
59+ (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
60+
61 (define_memory_constraint "Ut"
62 "@internal
63 In ARM/Thumb-2 state an address valid for loading/storing opaque structure
64
65=== modified file 'gcc/config/arm/predicates.md'
66--- old/gcc/config/arm/predicates.md 2011-12-06 10:42:29 +0000
67+++ new/gcc/config/arm/predicates.md 2012-02-22 13:31:54 +0000
68@@ -725,6 +725,11 @@
69 return true;
70 })
71
72+(define_predicate "const_double_vcvt_power_of_two_reciprocal"
73+ (and (match_code "const_double")
74+ (match_test "TARGET_32BIT && TARGET_VFP
75+ && vfp3_const_double_for_fract_bits (op)")))
76+
77 (define_special_predicate "neon_struct_operand"
78 (and (match_code "mem")
79 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
80
81=== modified file 'gcc/config/arm/vfp.md'
82--- old/gcc/config/arm/vfp.md 2011-12-06 10:42:29 +0000
83+++ new/gcc/config/arm/vfp.md 2012-02-22 13:31:54 +0000
84@@ -1131,9 +1131,40 @@
85 (set_attr "type" "fcmpd")]
86 )
87
88+;; Fixed point to floating point conversions.
89+(define_code_iterator FCVT [unsigned_float float])
90+(define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
91+
92+(define_insn "*combine_vcvt_f32_<FCVTI32typename>"
93+ [(set (match_operand:SF 0 "s_register_operand" "=t")
94+ (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0"))
95+ (match_operand 2
96+ "const_double_vcvt_power_of_two_reciprocal" "Dt")))]
97+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
98+ "vcvt.f32.<FCVTI32typename>\\t%0, %1, %v2"
99+ [(set_attr "predicable" "no")
100+ (set_attr "type" "f_cvt")]
101+)
102+
103+;; Not the ideal way of implementing this. Ideally we would be able to split
104+;; this into a move to a DP register and then a vcvt.f64.i32
105+(define_insn "*combine_vcvt_f64_<FCVTI32typename>"
106+ [(set (match_operand:DF 0 "s_register_operand" "=x,x,w")
107+ (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r"))
108+ (match_operand 2
109+ "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))]
110+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math
111+ && !TARGET_VFP_SINGLE"
112+ "@
113+ vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
114+ vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
115+ vmov.f64\\t%P0, %1, %1\; vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
116+ [(set_attr "predicable" "no")
117+ (set_attr "type" "f_cvt")
118+ (set_attr "length" "8")]
119+)
120
121 ;; Store multiple insn used in function prologue.
122-
123 (define_insn "*push_multi_vfp"
124 [(match_parallel 2 "multi_register_push"
125 [(set (match_operand:BLK 0 "memory_operand" "=m")
126
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106873.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106873.patch
deleted file mode 100644
index 5ce71a513..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106873.patch
+++ /dev/null
@@ -1,80 +0,0 @@
1 2012-02-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 LP:#922474
4 gcc/
5 * config/arm/sync.md (sync_lock_releasedi): Define.
6 (arm_sync_lock_releasedi): Likewise.
7 gcc/testsuite
8 Backport from mainline.
9 2012-01-30 Greta Yorsh <Greta.Yorsh@arm.com>
10 * gcc.target/arm/di-longlong64-sync-withldrexd.c: Accept
11 new code generated for __sync_lock_release.
12
13=== modified file 'gcc/config/arm/arm.md'
14--- old/gcc/config/arm/arm.md 2012-02-01 14:13:07 +0000
15+++ new/gcc/config/arm/arm.md 2012-02-22 18:37:56 +0000
16@@ -157,6 +157,7 @@
17 (VUNSPEC_SYNC_OP 23) ; Represent a sync_<op>
18 (VUNSPEC_SYNC_NEW_OP 24) ; Represent a sync_new_<op>
19 (VUNSPEC_SYNC_OLD_OP 25) ; Represent a sync_old_<op>
20+ (VUNSPEC_SYNC_RELEASE 26) ; Represent a sync_lock_release.
21 ]
22 )
23
24
25=== modified file 'gcc/config/arm/sync.md'
26--- old/gcc/config/arm/sync.md 2011-10-14 15:47:15 +0000
27+++ new/gcc/config/arm/sync.md 2012-02-22 18:37:56 +0000
28@@ -494,3 +494,36 @@
29 (set_attr "conds" "unconditional")
30 (set_attr "predicable" "no")])
31
32+(define_expand "sync_lock_releasedi"
33+ [(match_operand:DI 0 "memory_operand")
34+ (match_operand:DI 1 "s_register_operand")]
35+ "TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_MEMORY_BARRIER"
36+ {
37+ struct arm_sync_generator generator;
38+ rtx tmp1 = gen_reg_rtx (DImode);
39+ generator.op = arm_sync_generator_omn;
40+ generator.u.omn = gen_arm_sync_lock_releasedi;
41+ arm_expand_sync (DImode, &generator, operands[1], operands[0], NULL, tmp1);
42+ DONE;
43+ }
44+)
45+
46+(define_insn "arm_sync_lock_releasedi"
47+ [(set (match_operand:DI 2 "s_register_operand" "=&r")
48+ (unspec_volatile:DI [(match_operand:DI 1 "arm_sync_memory_operand" "+Q")
49+ (match_operand:DI 0 "s_register_operand" "r")]
50+ VUNSPEC_SYNC_RELEASE))
51+ (clobber (reg:CC CC_REGNUM))
52+ (clobber (match_scratch:SI 3 "=&r"))]
53+ "TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_MEMORY_BARRIER"
54+ {
55+ return arm_output_sync_insn (insn, operands);
56+ }
57+ [(set_attr "sync_memory" "1")
58+ (set_attr "sync_result" "2")
59+ (set_attr "sync_t1" "2")
60+ (set_attr "sync_t2" "3")
61+ (set_attr "sync_new_value" "0")
62+ (set_attr "conds" "clob")
63+ (set_attr "predicable" "no")]
64+)
65
66=== modified file 'gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c'
67--- old/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c 2011-10-14 15:56:32 +0000
68+++ new/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c 2012-02-22 18:37:56 +0000
69@@ -10,8 +10,8 @@
70 #include "../../gcc.dg/di-longlong64-sync-1.c"
71
72 /* We should be using ldrexd, strexd and no helpers or shorter ldrex. */
73-/* { dg-final { scan-assembler-times "\tldrexd" 46 } } */
74-/* { dg-final { scan-assembler-times "\tstrexd" 46 } } */
75+/* { dg-final { scan-assembler-times "\tldrexd" 48 } } */
76+/* { dg-final { scan-assembler-times "\tstrexd" 48 } } */
77 /* { dg-final { scan-assembler-not "__sync_" } } */
78 /* { dg-final { scan-assembler-not "ldrex\t" } } */
79 /* { dg-final { scan-assembler-not "strex\t" } } */
80
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106874.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106874.patch
deleted file mode 100644
index 092650dc9..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106874.patch
+++ /dev/null
@@ -1,46 +0,0 @@
1 2012-02-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline.
4 gcc/
5 2012-02-21 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
6
7 Revert r183011
8 * config/arm/arm-cores.def (cortex-a15): Use generic Cortex tuning
9 parameters.
10 * config/arm/arm.c (arm_cortex_a15_tune): Remove.
11
12=== modified file 'gcc/config/arm/arm-cores.def'
13--- old/gcc/config/arm/arm-cores.def 2012-01-23 00:36:02 +0000
14+++ new/gcc/config/arm/arm-cores.def 2012-02-22 15:53:56 +0000
15@@ -129,7 +129,7 @@
16 ARM_CORE("cortex-a7", cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
17 ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex)
18 ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9)
19-ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
20+ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
21 ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex)
22 ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex)
23 ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex)
24
25=== modified file 'gcc/config/arm/arm.c'
26--- old/gcc/config/arm/arm.c 2012-02-24 16:20:29 +0000
27+++ new/gcc/config/arm/arm.c 2012-02-24 17:33:58 +0000
28@@ -988,17 +988,6 @@
29 arm_default_branch_cost
30 };
31
32-const struct tune_params arm_cortex_a15_tune =
33-{
34- arm_9e_rtx_costs,
35- NULL,
36- 1, /* Constant limit. */
37- 1, /* Max cond insns. */
38- ARM_PREFETCH_NOT_BENEFICIAL, /* TODO: Calculate correct values. */
39- false, /* Prefer constant pool. */
40- arm_cortex_a5_branch_cost
41-};
42-
43 const struct tune_params arm_fa726te_tune =
44 {
45 arm_9e_rtx_costs,
46
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106876.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106876.patch
deleted file mode 100644
index 048e85b4d..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106876.patch
+++ /dev/null
@@ -1,109 +0,0 @@
12012-03-06 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 LP:942307
4 gcc/
5 PR target/50305
6 * config/arm/arm.c (arm_legitimize_reload_address): Recognize
7 output of a previous pass through legitimize_reload_address.
8 Do not attempt to optimize addresses if the base register is
9 equivalent to a constant.
10 gcc/testsuite/
11 PR target/50305
12 * gcc.target/arm/pr50305.c: New test.
13
14=== modified file 'gcc/config/arm/arm.c'
15--- old/gcc/config/arm/arm.c 2012-03-02 13:53:14 +0000
16+++ new/gcc/config/arm/arm.c 2012-03-06 11:01:55 +0000
17@@ -6632,9 +6632,26 @@
18 int opnum, int type,
19 int ind_levels ATTRIBUTE_UNUSED)
20 {
21+ /* We must recognize output that we have already generated ourselves. */
22+ if (GET_CODE (*p) == PLUS
23+ && GET_CODE (XEXP (*p, 0)) == PLUS
24+ && GET_CODE (XEXP (XEXP (*p, 0), 0)) == REG
25+ && GET_CODE (XEXP (XEXP (*p, 0), 1)) == CONST_INT
26+ && GET_CODE (XEXP (*p, 1)) == CONST_INT)
27+ {
28+ push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
29+ MODE_BASE_REG_CLASS (mode), GET_MODE (*p),
30+ VOIDmode, 0, 0, opnum, (enum reload_type) type);
31+ return true;
32+ }
33+
34 if (GET_CODE (*p) == PLUS
35 && GET_CODE (XEXP (*p, 0)) == REG
36 && ARM_REGNO_OK_FOR_BASE_P (REGNO (XEXP (*p, 0)))
37+ /* If the base register is equivalent to a constant, let the generic
38+ code handle it. Otherwise we will run into problems if a future
39+ reload pass decides to rematerialize the constant. */
40+ && !reg_equiv_constant [ORIGINAL_REGNO (XEXP (*p, 0))]
41 && GET_CODE (XEXP (*p, 1)) == CONST_INT)
42 {
43 HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));
44
45=== added file 'gcc/testsuite/gcc.target/arm/pr50305.c'
46--- old/gcc/testsuite/gcc.target/arm/pr50305.c 1970-01-01 00:00:00 +0000
47+++ new/gcc/testsuite/gcc.target/arm/pr50305.c 2012-03-01 13:07:48 +0000
48@@ -0,0 +1,60 @@
49+/* { dg-do compile } */
50+/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */
51+/* { dg-options "-O2 -fno-omit-frame-pointer -marm -march=armv7-a -mfpu=vfp3" } */
52+
53+struct event {
54+ unsigned long long id;
55+ unsigned int flag;
56+};
57+
58+void dummy(void)
59+{
60+ /* This is here to ensure that the offset of perf_event_id below
61+ relative to the LANCHOR symbol exceeds the allowed displacement. */
62+ static int __warned[300];
63+ __warned[0] = 1;
64+}
65+
66+extern void *kmem_cache_alloc_trace (void *cachep);
67+extern void *cs_cachep;
68+extern int nr_cpu_ids;
69+
70+struct event *
71+event_alloc (int cpu)
72+{
73+ static unsigned long long __attribute__((aligned(8))) perf_event_id;
74+ struct event *event;
75+ unsigned long long result;
76+ unsigned long tmp;
77+
78+ if (cpu >= nr_cpu_ids)
79+ return 0;
80+
81+ event = kmem_cache_alloc_trace (cs_cachep);
82+
83+ __asm__ __volatile__ ("dmb" : : : "memory");
84+
85+ __asm__ __volatile__("@ atomic64_add_return\n"
86+"1: ldrexd %0, %H0, [%3]\n"
87+" adds %0, %0, %4\n"
88+" adc %H0, %H0, %H4\n"
89+" strexd %1, %0, %H0, [%3]\n"
90+" teq %1, #0\n"
91+" bne 1b"
92+ : "=&r" (result), "=&r" (tmp), "+Qo" (perf_event_id)
93+ : "r" (&perf_event_id), "r" (1LL)
94+ : "cc");
95+
96+ __asm__ __volatile__ ("dmb" : : : "memory");
97+
98+ event->id = result;
99+
100+ if (cpu)
101+ event->flag = 1;
102+
103+ for (cpu = 0; cpu < nr_cpu_ids; cpu++)
104+ kmem_cache_alloc_trace (cs_cachep);
105+
106+ return event;
107+}
108+
109
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106877.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106877.patch
deleted file mode 100644
index b83b957c6..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106877.patch
+++ /dev/null
@@ -1,239 +0,0 @@
12012-03-06 Ulrich Weigand <ulrich.weigand@linaro.org>
2
3 Backport from mainline:
4
5 gcc/
6 * config/arm/arm.c (arm_sat_operator_match): New function.
7 * config/arm/arm-protos.h (arm_sat_operator_match): Add prototype.
8 * config/arm/arm.md ("insn" attribute): Add "sat" value.
9 ("SAT", "SATrev"): New code iterators.
10 ("SATlo", "SAThi"): New code iterator attributes.
11 ("*satsi_<SAT:code>"): New pattern.
12 ("*satsi_<SAT:code>_shift"): Likewise.
13 * config/arm/predicates.md (sat_shift_operator): New.
14
15 gcc/testsuite/
16 * gcc.target/arm/sat-1.c: New test.
17
18=== modified file 'gcc/config/arm/arm-protos.h'
19--- old/gcc/config/arm/arm-protos.h 2012-02-22 13:31:54 +0000
20+++ new/gcc/config/arm/arm-protos.h 2012-02-29 14:29:56 +0000
21@@ -104,6 +104,7 @@
22 extern int symbol_mentioned_p (rtx);
23 extern int label_mentioned_p (rtx);
24 extern RTX_CODE minmax_code (rtx);
25+extern bool arm_sat_operator_match (rtx, rtx, int *, bool *);
26 extern int adjacent_mem_locations (rtx, rtx);
27 extern bool gen_ldm_seq (rtx *, int, bool);
28 extern bool gen_stm_seq (rtx *, int);
29
30=== modified file 'gcc/config/arm/arm.c'
31--- old/gcc/config/arm/arm.c 2012-03-06 11:01:55 +0000
32+++ new/gcc/config/arm/arm.c 2012-03-06 13:24:25 +0000
33@@ -9978,6 +9978,42 @@
34 }
35 }
36
37+/* Match pair of min/max operators that can be implemented via usat/ssat. */
38+
39+bool
40+arm_sat_operator_match (rtx lo_bound, rtx hi_bound,
41+ int *mask, bool *signed_sat)
42+{
43+ /* The high bound must be a power of two minus one. */
44+ int log = exact_log2 (INTVAL (hi_bound) + 1);
45+ if (log == -1)
46+ return false;
47+
48+ /* The low bound is either zero (for usat) or one less than the
49+ negation of the high bound (for ssat). */
50+ if (INTVAL (lo_bound) == 0)
51+ {
52+ if (mask)
53+ *mask = log;
54+ if (signed_sat)
55+ *signed_sat = false;
56+
57+ return true;
58+ }
59+
60+ if (INTVAL (lo_bound) == -INTVAL (hi_bound) - 1)
61+ {
62+ if (mask)
63+ *mask = log + 1;
64+ if (signed_sat)
65+ *signed_sat = true;
66+
67+ return true;
68+ }
69+
70+ return false;
71+}
72+
73 /* Return 1 if memory locations are adjacent. */
74 int
75 adjacent_mem_locations (rtx a, rtx b)
76
77=== modified file 'gcc/config/arm/arm.md'
78--- old/gcc/config/arm/arm.md 2012-03-02 13:53:14 +0000
79+++ new/gcc/config/arm/arm.md 2012-03-06 13:24:25 +0000
80@@ -286,7 +286,7 @@
81 ;; scheduling information.
82
83 (define_attr "insn"
84- "mov,mvn,smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,umaal,smlald,smlsld,clz,mrs,msr,xtab,sdiv,udiv,other"
85+ "mov,mvn,smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,umaal,smlald,smlsld,clz,mrs,msr,xtab,sdiv,udiv,sat,other"
86 (const_string "other"))
87
88 ; TYPE attribute is used to detect floating point instructions which, if
89@@ -3424,6 +3424,60 @@
90 (const_int 12)))]
91 )
92
93+(define_code_iterator SAT [smin smax])
94+(define_code_iterator SATrev [smin smax])
95+(define_code_attr SATlo [(smin "1") (smax "2")])
96+(define_code_attr SAThi [(smin "2") (smax "1")])
97+
98+(define_insn "*satsi_<SAT:code>"
99+ [(set (match_operand:SI 0 "s_register_operand" "=r")
100+ (SAT:SI (SATrev:SI (match_operand:SI 3 "s_register_operand" "r")
101+ (match_operand:SI 1 "const_int_operand" "i"))
102+ (match_operand:SI 2 "const_int_operand" "i")))]
103+ "TARGET_32BIT && arm_arch6 && <SAT:CODE> != <SATrev:CODE>
104+ && arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>], NULL, NULL)"
105+{
106+ int mask;
107+ bool signed_sat;
108+ if (!arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>],
109+ &mask, &signed_sat))
110+ gcc_unreachable ();
111+
112+ operands[1] = GEN_INT (mask);
113+ if (signed_sat)
114+ return "ssat%?\t%0, %1, %3";
115+ else
116+ return "usat%?\t%0, %1, %3";
117+}
118+ [(set_attr "predicable" "yes")
119+ (set_attr "insn" "sat")])
120+
121+(define_insn "*satsi_<SAT:code>_shift"
122+ [(set (match_operand:SI 0 "s_register_operand" "=r")
123+ (SAT:SI (SATrev:SI (match_operator:SI 3 "sat_shift_operator"
124+ [(match_operand:SI 4 "s_register_operand" "r")
125+ (match_operand:SI 5 "const_int_operand" "i")])
126+ (match_operand:SI 1 "const_int_operand" "i"))
127+ (match_operand:SI 2 "const_int_operand" "i")))]
128+ "TARGET_32BIT && arm_arch6 && <SAT:CODE> != <SATrev:CODE>
129+ && arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>], NULL, NULL)"
130+{
131+ int mask;
132+ bool signed_sat;
133+ if (!arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>],
134+ &mask, &signed_sat))
135+ gcc_unreachable ();
136+
137+ operands[1] = GEN_INT (mask);
138+ if (signed_sat)
139+ return "ssat%?\t%0, %1, %4%S3";
140+ else
141+ return "usat%?\t%0, %1, %4%S3";
142+}
143+ [(set_attr "predicable" "yes")
144+ (set_attr "insn" "sat")
145+ (set_attr "shift" "3")
146+ (set_attr "type" "alu_shift")])
147
148 ;; Shift and rotation insns
149
150
151=== modified file 'gcc/config/arm/predicates.md'
152--- old/gcc/config/arm/predicates.md 2012-02-22 13:31:54 +0000
153+++ new/gcc/config/arm/predicates.md 2012-02-29 14:29:56 +0000
154@@ -241,6 +241,15 @@
155 || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
156 (match_test "mode == GET_MODE (op)")))
157
158+;; True for shift operators which can be used with saturation instructions.
159+(define_special_predicate "sat_shift_operator"
160+ (and (ior (and (match_code "mult")
161+ (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
162+ (and (match_code "ashift,ashiftrt")
163+ (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
164+ && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
165+ (match_test "mode == GET_MODE (op)")))
166+
167 ;; True for MULT, to identify which variant of shift_operator is in use.
168 (define_special_predicate "mult_operator"
169 (match_code "mult"))
170
171=== added file 'gcc/testsuite/gcc.target/arm/sat-1.c'
172--- old/gcc/testsuite/gcc.target/arm/sat-1.c 1970-01-01 00:00:00 +0000
173+++ new/gcc/testsuite/gcc.target/arm/sat-1.c 2012-02-29 14:29:56 +0000
174@@ -0,0 +1,64 @@
175+/* { dg-do compile } */
176+/* { dg-require-effective-target arm_arm_ok } */
177+/* { dg-require-effective-target arm_arch_v6_ok } */
178+/* { dg-options "-O2 -marm" } */
179+/* { dg-add-options arm_arch_v6 } */
180+
181+
182+static inline int sat1 (int a, int amin, int amax)
183+{
184+ if (a < amin) return amin;
185+ else if (a > amax) return amax;
186+ else return a;
187+}
188+
189+static inline int sat2 (int a, int amin, int amax)
190+{
191+ if (a > amax) return amax;
192+ else if (a < amin) return amin;
193+ else return a;
194+}
195+
196+int u1 (int x)
197+{
198+ return sat1 (x, 0, 63);
199+}
200+
201+int us1 (int x)
202+{
203+ return sat1 (x >> 5, 0, 63);
204+}
205+
206+int s1 (int x)
207+{
208+ return sat1 (x, -64, 63);
209+}
210+
211+int ss1 (int x)
212+{
213+ return sat1 (x >> 5, -64, 63);
214+}
215+
216+int u2 (int x)
217+{
218+ return sat2 (x, 0, 63);
219+}
220+
221+int us2 (int x)
222+{
223+ return sat2 (x >> 5, 0, 63);
224+}
225+
226+int s2 (int x)
227+{
228+ return sat2 (x, -64, 63);
229+}
230+
231+int ss2 (int x)
232+{
233+ return sat2 (x >> 5, -64, 63);
234+}
235+
236+/* { dg-final { scan-assembler-times "usat" 4 } } */
237+/* { dg-final { scan-assembler-times "ssat" 4 } } */
238+
239
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106878.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106878.patch
deleted file mode 100644
index fc1633d36..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106878.patch
+++ /dev/null
@@ -1,69 +0,0 @@
12012-03-08 Michael Hope <michael.hope@linaro.org>
2
3 Backport proposed patch:
4
5 gcc/
6 2012-01-31 Richard Henderson <rth@redhat.com>
7
8 * longlong.h [arm] (umul_ppmm): Use umull. Enable for thumb2.
9 [arm] (count_trailing_zeros): Use __builtin_ctz.
10
11=== modified file 'gcc/longlong.h'
12--- old/gcc/longlong.h 2011-10-04 07:28:50 +0000
13+++ new/gcc/longlong.h 2012-02-22 01:51:14 +0000
14@@ -203,7 +203,7 @@
15 UDItype __umulsidi3 (USItype, USItype);
16 #endif
17
18-#if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
19+#if defined (__arm__) && (defined (__thumb2__) || !defined (__thumb__)) && W_TYPE_SIZE == 32
20 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
21 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
22 : "=r" ((USItype) (sh)), \
23@@ -220,9 +220,12 @@
24 "rI" ((USItype) (bh)), \
25 "r" ((USItype) (al)), \
26 "rI" ((USItype) (bl)) __CLOBBER_CC)
27-#define umul_ppmm(xh, xl, a, b) \
28-{register USItype __t0, __t1, __t2; \
29- __asm__ ("%@ Inlined umul_ppmm\n" \
30+# if defined(__ARM_ARCH_2__) || defined(__ARM_ARCH_2A__) \
31+ || defined(__ARM_ARCH_3__)
32+# define umul_ppmm(xh, xl, a, b) \
33+ do { \
34+ register USItype __t0, __t1, __t2; \
35+ __asm__ ("%@ Inlined umul_ppmm\n" \
36 " mov %2, %5, lsr #16\n" \
37 " mov %0, %6, lsr #16\n" \
38 " bic %3, %5, %2, lsl #16\n" \
39@@ -239,14 +242,26 @@
40 "=r" ((USItype) (xl)), \
41 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
42 : "r" ((USItype) (a)), \
43- "r" ((USItype) (b)) __CLOBBER_CC );}
44-#define UMUL_TIME 20
45-#define UDIV_TIME 100
46+ "r" ((USItype) (b)) __CLOBBER_CC ); \
47+ } while (0)
48+# define UMUL_TIME 20
49+# else
50+# define umul_ppmm(xh, xl, a, b) \
51+ do { \
52+ /* Generate umull, under compiler control. */ \
53+ register UDItype __t0 = (UDItype)(USItype)(a) * (USItype)(b); \
54+ (xl) = (USItype)__t0; \
55+ (xh) = (USItype)(__t0 >> 32); \
56+ } while (0)
57+# define UMUL_TIME 3
58+# endif
59+# define UDIV_TIME 100
60 #endif /* __arm__ */
61
62 #if defined(__arm__)
63 /* Let gcc decide how best to implement count_leading_zeros. */
64 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
65+#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X))
66 #define COUNT_LEADING_ZEROS_0 32
67 #endif
68
69
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106879.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106879.patch
deleted file mode 100644
index a97a27b60..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106879.patch
+++ /dev/null
@@ -1,643 +0,0 @@
12012-03-08 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline.
4 2012-02-28 Richard Earnshaw <rearnsha@arm.com>
5
6 * arm.c (aapcs_vfp_is_call_or_return_candidate): Only use the machine
7 mode if there is no type information available.
8
9 2012-02-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
10
11 * gcc.target/arm/aapcs/vfp1.c (dg_do run): Run on all eabi variants.
12 * gcc.target/arm/aapcs/vfp2.c: Likewise.
13 * gcc.target/arm/aapcs/vfp3.c: Likewise.
14 * gcc.target/arm/aapcs/vfp4.c: Likewise.
15 * gcc.target/arm/aapcs/vfp5.c: Likewise.
16 * gcc.target/arm/aapcs/vfp6.c: Likewise.
17 * gcc.target/arm/aapcs/vfp7.c: Likewise.
18 * gcc.target/arm/aapcs/vfp8.c: Likewise.
19 * gcc.target/arm/aapcs/vfp9.c: Likewise.
20 * gcc.target/arm/aapcs/vfp10.c: Likewise.
21 * gcc.target/arm/aapcs/vfp11.c: Likewise.
22 * gcc.target/arm/aapcs/vfp12.c: Likewise.
23 * gcc.target/arm/aapcs/vfp13.c: Likewise.
24 * gcc.target/arm/aapcs/vfp14.c: Likewise.
25 * gcc.target/arm/aapcs/vfp15.c: Likewise.
26 * gcc.target/arm/aapcs/vfp16.c: Likewise.
27 * gcc.target/arm/aapcs/vfp17.c: Likewise.
28 * gcc.target/arm/neon-constants.h: New file.
29 * gcc.target/arm/aapcs/neon-constants.h: New file.
30 * gcc.target/arm/aapcs/neon-vect1.c: New test.
31 * gcc.target/arm/aapcs/neon-vect2.c: New test.
32 * gcc.target/arm/aapcs/neon-vect3.c: New test.
33 * gcc.target/arm/aapcs/neon-vect4.c: New test.
34 * gcc.target/arm/aapcs/neon-vect5.c: New test.
35 * gcc.target/arm/aapcs/neon-vect6.c: New test.
36 * gcc.target/arm/aapcs/neon-vect7.c: New test.
37 * gcc.target/arm/aapcs/neon-vect8.c: New test.
38
39=== modified file 'gcc/config/arm/arm.c'
40--- old/gcc/config/arm/arm.c 2012-03-06 13:24:25 +0000
41+++ new/gcc/config/arm/arm.c 2012-03-08 15:46:42 +0000
42@@ -4331,6 +4331,11 @@
43 (TARGET_VFP_DOUBLE || !is_double));
44 }
45
46+/* Return true if an argument whose type is TYPE, or mode is MODE, is
47+ suitable for passing or returning in VFP registers for the PCS
48+ variant selected. If it is, then *BASE_MODE is updated to contain
49+ a machine mode describing each element of the argument's type and
50+ *COUNT to hold the number of such elements. */
51 static bool
52 aapcs_vfp_is_call_or_return_candidate (enum arm_pcs pcs_variant,
53 enum machine_mode mode, const_tree type,
54@@ -4338,9 +4343,20 @@
55 {
56 enum machine_mode new_mode = VOIDmode;
57
58- if (GET_MODE_CLASS (mode) == MODE_FLOAT
59- || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
60- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
61+ /* If we have the type information, prefer that to working things
62+ out from the mode. */
63+ if (type)
64+ {
65+ int ag_count = aapcs_vfp_sub_candidate (type, &new_mode);
66+
67+ if (ag_count > 0 && ag_count <= 4)
68+ *count = ag_count;
69+ else
70+ return false;
71+ }
72+ else if (GET_MODE_CLASS (mode) == MODE_FLOAT
73+ || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
74+ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
75 {
76 *count = 1;
77 new_mode = mode;
78@@ -4350,15 +4366,6 @@
79 *count = 2;
80 new_mode = (mode == DCmode ? DFmode : SFmode);
81 }
82- else if (type && (mode == BLKmode || TREE_CODE (type) == VECTOR_TYPE))
83- {
84- int ag_count = aapcs_vfp_sub_candidate (type, &new_mode);
85-
86- if (ag_count > 0 && ag_count <= 4)
87- *count = ag_count;
88- else
89- return false;
90- }
91 else
92 return false;
93
94
95=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/abitest.h'
96--- old/gcc/testsuite/gcc.target/arm/aapcs/abitest.h 2009-08-06 17:15:19 +0000
97+++ new/gcc/testsuite/gcc.target/arm/aapcs/abitest.h 2012-03-01 09:33:24 +0000
98@@ -1,3 +1,4 @@
99+
100 #define IN_FRAMEWORK
101
102 #ifdef VFP
103@@ -10,6 +11,13 @@
104 #define D6 48
105 #define D7 56
106
107+#ifdef NEON
108+#define Q0 D0
109+#define Q1 D2
110+#define Q2 D4
111+#define Q3 D6
112+#endif
113+
114 #define S0 64
115 #define S1 68
116 #define S2 72
117@@ -27,24 +35,19 @@
118 #define S14 120
119 #define S15 124
120
121-#define R0 128
122-#define R1 132
123-#define R2 136
124-#define R3 140
125-
126-#define STACK 144
127-
128+#define CORE_REG_START 128
129 #else
130-
131-#define R0 0
132-#define R1 4
133-#define R2 8
134-#define R3 12
135-
136-#define STACK 16
137-
138+#define CORE_REG_START 0
139 #endif
140
141+#define R0 CORE_REG_START
142+#define R1 (R0 + 4)
143+#define R2 (R1 + 4)
144+#define R3 (R2 + 4)
145+#define STACK (R3 + 4)
146+
147+
148+
149 extern void abort (void);
150
151 __attribute__((naked)) void dumpregs () __asm("myfunc");
152
153=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h'
154--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h 1970-01-01 00:00:00 +0000
155+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h 2012-03-01 09:33:24 +0000
156@@ -0,0 +1,33 @@
157+
158+
159+#include "arm_neon.h"
160+
161+const int32x4_t i32x4_constvec1 = { 1101, 1102, 1103, 1104};
162+const int32x4_t i32x4_constvec2 = { 2101, 2102, 2103, 2104};
163+
164+#define ELEM(INDEX) .val[INDEX]
165+
166+const int32x4x2_t i32x4x2_constvec1 = {ELEM(0) = {0xaddebccb,11,12,13},
167+ ELEM(1) = {14, 15, 16, 17} };
168+
169+const int32x4x2_t i32x4x2_constvec2 = { ELEM(0) = {0xaadebcca,11,12,13},
170+ ELEM(1) = {140, 15, 16, 17}};
171+
172+const int32x4x3_t i32x4x3_constvec1 = { ELEM(0) = {0xabbccdde,8, 9, 10},
173+ ELEM(1) = {0xabcccdde, 26, 27, 28},
174+ ELEM(2) = {0xaccccddf, 29, 30, 31}};
175+
176+const int32x4x3_t i32x4x3_constvec2 = { ELEM(0) = {0xbccccdd0,8, 9, 10},
177+ ELEM(1) = {0xbdfe1000, 26, 27, 28},
178+ ELEM(2) = {0xaccccddf, 29, 30, 31}};
179+const float32x4x2_t f32x4x2_constvec1 =
180+ { ELEM(0) = { 7.101f, 0.201f, 0.301f, 0.401f} ,
181+ ELEM(1) = { 8.101f, 0.501f, 0.601f, 0.701f} };
182+
183+const float32x4x2_t f32x4x2_constvec2 =
184+ { ELEM(0) = { 11.99f , 11.21f, 1.27f, 8.74f},
185+ ELEM(1) = { 13.45f , 1.23f ,1.24f, 1.26f}};
186+
187+const int32x2_t i32x2_constvec1 = { 1283, 1345 };
188+const int32x2x2_t i32x2x2_constvec1 = { ELEM(0) = { 0xabcdefab, 32 },
189+ ELEM(1) = { 0xabcdefbc, 33 }};
190
191=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c'
192--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c 1970-01-01 00:00:00 +0000
193+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c 2012-03-01 09:33:24 +0000
194@@ -0,0 +1,27 @@
195+/* Test AAPCS layout (VFP variant for Neon types) */
196+
197+/* { dg-do run { target arm*-*-*eabi* } } */
198+/* { dg-require-effective-target arm_hard_vfp_ok } */
199+/* { dg-require-effective-target arm_neon_ok } */
200+/* { dg-require-effective-target arm32 } */
201+/* { dg-add-options arm_neon } */
202+
203+
204+#ifndef IN_FRAMEWORK
205+#define VFP
206+#define NEON
207+#define TESTFILE "neon-vect1.c"
208+#include "neon-constants.h"
209+
210+
211+#include "abitest.h"
212+#else
213+
214+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
215+ARG(float, 3.0f, S4) /* D2, Q1 */
216+ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */
217+ARG(double, 12.0, D3) /* Backfill this particular argument. */
218+ARG(int32x4x2_t, i32x4x2_constvec2, STACK)
219+ARG(float, 5.0f, STACK+sizeof(int32x4x2_t)) /* No backfill allowed. */
220+LAST_ARG(int, 3, R0)
221+#endif
222
223=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c'
224--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c 1970-01-01 00:00:00 +0000
225+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c 2012-03-01 09:33:24 +0000
226@@ -0,0 +1,23 @@
227+/* Test AAPCS layout (VFP variant for Neon types) */
228+
229+/* { dg-do run { target arm*-*-*eabi* } } */
230+/* { dg-require-effective-target arm_hard_vfp_ok } */
231+/* { dg-require-effective-target arm_neon_ok } */
232+/* { dg-require-effective-target arm32 } */
233+/* { dg-add-options arm_neon } */
234+
235+
236+#ifndef IN_FRAMEWORK
237+#define VFP
238+#define NEON
239+#define TESTFILE "neon-vect2.c"
240+#include "neon-constants.h"
241+
242+
243+#include "abitest.h"
244+#else
245+
246+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1. */
247+ARG(float, 3.0f, S4) /* D2, Q1 occupied. */
248+LAST_ARG(int, 3, R0)
249+#endif
250
251=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c'
252--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c 1970-01-01 00:00:00 +0000
253+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c 2012-03-01 09:33:24 +0000
254@@ -0,0 +1,26 @@
255+/* Test AAPCS layout (VFP variant for Neon types) */
256+
257+/* { dg-do run { target arm*-*-*eabi* } } */
258+/* { dg-require-effective-target arm_hard_vfp_ok } */
259+/* { dg-require-effective-target arm_neon_ok } */
260+/* { dg-require-effective-target arm32 } */
261+/* { dg-add-options arm_neon } */
262+
263+
264+#ifndef IN_FRAMEWORK
265+#define VFP
266+#define NEON
267+#define TESTFILE "neon-vect3.c"
268+#include "neon-constants.h"
269+
270+
271+#include "abitest.h"
272+#else
273+
274+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
275+ARG(float, 3.0f, S4) /* D2, Q1 */
276+ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */
277+ARG(int32x4x2_t, i32x4x2_constvec2, STACK)
278+ARG(double, 11.0, STACK+sizeof(int32x4x2_t)) /* No backfill in D3. */
279+LAST_ARG(int, 3, R0)
280+#endif
281
282=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c'
283--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c 1970-01-01 00:00:00 +0000
284+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c 2012-03-01 09:33:24 +0000
285@@ -0,0 +1,27 @@
286+/* Test AAPCS layout (VFP variant for Neon types) */
287+
288+/* { dg-do run { target arm*-*-*eabi* } } */
289+/* { dg-require-effective-target arm_hard_vfp_ok } */
290+/* { dg-require-effective-target arm_neon_ok } */
291+/* { dg-require-effective-target arm32 } */
292+/* { dg-add-options arm_neon } */
293+
294+
295+#ifndef IN_FRAMEWORK
296+#define VFP
297+#define NEON
298+#define TESTFILE "neon-vect4.c"
299+#include "neon-constants.h"
300+
301+
302+#include "abitest.h"
303+#else
304+
305+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
306+ARG(float, 3.0f, S4) /* D2, Q1 */
307+ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */
308+ARG(double, 12.0, D3) /* Backfill this particular argument. */
309+ARG(float, 5.0f, S5) /* Backfill in S5. */
310+ARG(int32x4x2_t, i32x4x2_constvec2, STACK)
311+LAST_ARG(int, 3, R0)
312+#endif
313
314=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c'
315--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c 1970-01-01 00:00:00 +0000
316+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c 2012-03-01 09:33:24 +0000
317@@ -0,0 +1,28 @@
318+/* Test AAPCS layout (VFP variant for Neon types) */
319+
320+/* { dg-do run { target arm*-*-*eabi* } } */
321+/* { dg-require-effective-target arm_hard_vfp_ok } */
322+/* { dg-require-effective-target arm_neon_ok } */
323+/* { dg-require-effective-target arm32 } */
324+/* { dg-add-options arm_neon } */
325+
326+
327+#ifndef IN_FRAMEWORK
328+#define VFP
329+#define NEON
330+#define TESTFILE "neon-vect5.c"
331+#include "neon-constants.h"
332+
333+
334+#include "abitest.h"
335+#else
336+
337+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
338+ARG(float, 3.0f, S4) /* D2, Q1 */
339+ARG(float32x4x2_t, f32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */
340+ARG(double, 12.0, D3) /* Backfill this particular argument. */
341+ARG(int32x4x2_t, i32x4x2_constvec2, STACK)
342+ARG(float, 5.0f, STACK+sizeof(int32x4x2_t)) /* No backfill allowed. */
343+LAST_ARG(int, 3, R0)
344+
345+#endif
346
347=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c'
348--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c 1970-01-01 00:00:00 +0000
349+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c 2012-03-01 09:33:24 +0000
350@@ -0,0 +1,24 @@
351+/* Test AAPCS layout (VFP variant for Neon types) */
352+
353+/* { dg-do run { target arm*-*-*eabi* } } */
354+/* { dg-require-effective-target arm_hard_vfp_ok } */
355+/* { dg-require-effective-target arm_neon_ok } */
356+/* { dg-require-effective-target arm32 } */
357+/* { dg-add-options arm_neon } */
358+
359+
360+#ifndef IN_FRAMEWORK
361+#define VFP
362+#define NEON
363+#define TESTFILE "neon-vect6.c"
364+#include "neon-constants.h"
365+
366+
367+#include "abitest.h"
368+#else
369+
370+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
371+ARG(int32x4x3_t, i32x4x3_constvec1, Q1) /* Q1, Q2, Q3 */
372+ARG(int32x4x3_t, i32x4x3_constvec2, STACK)
373+LAST_ARG(int, 3, R0)
374+#endif
375
376=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c'
377--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c 1970-01-01 00:00:00 +0000
378+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c 2012-03-01 09:33:24 +0000
379@@ -0,0 +1,27 @@
380+/* Test AAPCS layout (VFP variant for Neon types) */
381+
382+/* { dg-do run { target arm*-*-*eabi* } } */
383+/* { dg-require-effective-target arm_hard_vfp_ok } */
384+/* { dg-require-effective-target arm_neon_ok } */
385+/* { dg-require-effective-target arm32 } */
386+/* { dg-add-options arm_neon } */
387+
388+
389+#ifndef IN_FRAMEWORK
390+#define VFP
391+#define NEON
392+#define TESTFILE "neon-vect7.c"
393+#include "neon-constants.h"
394+
395+
396+#include "abitest.h"
397+#else
398+
399+ARG(float, 24.3f, S0) /* S0 , D0, Q0 */
400+ARG(int32x4x3_t, i32x4x3_constvec1, Q1) /* Q1, Q2, Q3 */
401+ARG(double, 25.6, D1)
402+ARG(float, 12.67f, S1)
403+ARG(int32x4x3_t, i32x4x3_constvec2, STACK)
404+ARG(double, 2.47, STACK+sizeof(int32x4x3_t))
405+LAST_ARG(int, 3, R0)
406+#endif
407
408=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c'
409--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c 1970-01-01 00:00:00 +0000
410+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c 2012-03-01 09:33:24 +0000
411@@ -0,0 +1,27 @@
412+/* Test AAPCS layout (VFP variant for Neon types) */
413+
414+/* { dg-do run { target arm*-*-*eabi* } } */
415+/* { dg-require-effective-target arm_hard_vfp_ok } */
416+/* { dg-require-effective-target arm_neon_ok } */
417+/* { dg-require-effective-target arm32 } */
418+/* { dg-add-options arm_neon } */
419+
420+
421+#ifndef IN_FRAMEWORK
422+#define VFP
423+#define NEON
424+#define TESTFILE "neon-vect8.c"
425+#include "neon-constants.h"
426+
427+
428+#include "abitest.h"
429+#else
430+
431+ARG(float, 24.3f, S0) /* S0 , D0, Q0 */
432+ARG(int32x2_t, i32x2_constvec1, D1) /* D1 */
433+ARG(double, 25.6, D2)
434+ARG(float, 12.67f, S1)
435+ARG(int32x4x3_t, i32x4x3_constvec2, STACK)
436+ARG(double, 2.47, STACK+sizeof(int32x4x3_t))
437+LAST_ARG(int, 3, R0)
438+#endif
439
440=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp1.c'
441--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c 2009-08-06 13:27:45 +0000
442+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c 2012-03-01 09:33:24 +0000
443@@ -1,6 +1,6 @@
444 /* Test AAPCS layout (VFP variant) */
445
446-/* { dg-do run { target arm*-*-eabi* } } */
447+/* { dg-do run { target arm*-*-*eabi* } } */
448 /* { dg-require-effective-target arm_hard_vfp_ok } */
449 /* { dg-require-effective-target arm32 } */
450 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
451
452=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp10.c'
453--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c 2009-08-06 13:27:45 +0000
454+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c 2012-03-01 09:33:24 +0000
455@@ -1,6 +1,6 @@
456 /* Test AAPCS layout (VFP variant) */
457
458-/* { dg-do run { target arm*-*-eabi* } } */
459+/* { dg-do run { target arm*-*-*eabi* } } */
460 /* { dg-require-effective-target arm_hard_vfp_ok } */
461 /* { dg-require-effective-target arm32 } */
462 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
463
464=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp11.c'
465--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c 2009-08-06 13:27:45 +0000
466+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c 2012-03-01 09:33:24 +0000
467@@ -1,6 +1,6 @@
468 /* Test AAPCS layout (VFP variant) */
469
470-/* { dg-do run { target arm*-*-eabi* } } */
471+/* { dg-do run { target arm*-*-*eabi* } } */
472 /* { dg-require-effective-target arm_hard_vfp_ok } */
473 /* { dg-require-effective-target arm32 } */
474 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
475
476=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp12.c'
477--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c 2009-08-06 13:27:45 +0000
478+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c 2012-03-01 09:33:24 +0000
479@@ -1,6 +1,6 @@
480 /* Test AAPCS layout (VFP variant) */
481
482-/* { dg-do run { target arm*-*-eabi* } } */
483+/* { dg-do run { target arm*-*-*eabi* } } */
484 /* { dg-require-effective-target arm_hard_vfp_ok } */
485 /* { dg-require-effective-target arm32 } */
486 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
487
488=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp13.c'
489--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c 2009-08-06 13:27:45 +0000
490+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c 2012-03-01 09:33:24 +0000
491@@ -1,6 +1,6 @@
492 /* Test AAPCS layout (VFP variant) */
493
494-/* { dg-do run { target arm*-*-eabi* } } */
495+/* { dg-do run { target arm*-*-*eabi* } } */
496 /* { dg-require-effective-target arm_hard_vfp_ok } */
497 /* { dg-require-effective-target arm32 } */
498 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
499
500=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp14.c'
501--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c 2009-08-06 13:27:45 +0000
502+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c 2012-03-01 09:33:24 +0000
503@@ -1,6 +1,6 @@
504 /* Test AAPCS layout (VFP variant) */
505
506-/* { dg-do run { target arm*-*-eabi* } } */
507+/* { dg-do run { target arm*-*-*eabi* } } */
508 /* { dg-require-effective-target arm_hard_vfp_ok } */
509 /* { dg-require-effective-target arm32 } */
510 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
511
512=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp15.c'
513--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c 2009-08-06 17:15:19 +0000
514+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c 2012-03-01 09:33:24 +0000
515@@ -1,6 +1,6 @@
516 /* Test AAPCS layout (VFP variant) */
517
518-/* { dg-do run { target arm*-*-eabi* } } */
519+/* { dg-do run { target arm*-*-*eabi* } } */
520 /* { dg-require-effective-target arm_hard_vfp_ok } */
521 /* { dg-require-effective-target arm32 } */
522 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
523
524=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp16.c'
525--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c 2009-08-06 17:15:19 +0000
526+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c 2012-03-01 09:33:24 +0000
527@@ -1,6 +1,6 @@
528 /* Test AAPCS layout (VFP variant) */
529
530-/* { dg-do run { target arm*-*-eabi* } } */
531+/* { dg-do run { target arm*-*-*eabi* } } */
532 /* { dg-require-effective-target arm_hard_vfp_ok } */
533 /* { dg-require-effective-target arm32 } */
534 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
535
536=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp17.c'
537--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c 2009-08-06 17:15:19 +0000
538+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c 2012-03-01 09:33:24 +0000
539@@ -1,6 +1,6 @@
540 /* Test AAPCS layout (VFP variant) */
541
542-/* { dg-do run { target arm*-*-eabi* } } */
543+/* { dg-do run { target arm*-*-*eabi* } } */
544 /* { dg-require-effective-target arm_hard_vfp_ok } */
545 /* { dg-require-effective-target arm32 } */
546 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
547
548=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp2.c'
549--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c 2009-08-06 13:27:45 +0000
550+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c 2012-03-01 09:33:24 +0000
551@@ -1,6 +1,6 @@
552 /* Test AAPCS layout (VFP variant) */
553
554-/* { dg-do run { target arm*-*-eabi* } } */
555+/* { dg-do run { target arm*-*-*eabi* } } */
556 /* { dg-require-effective-target arm_hard_vfp_ok } */
557 /* { dg-require-effective-target arm32 } */
558 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
559
560=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp3.c'
561--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c 2009-08-06 13:27:45 +0000
562+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c 2012-03-01 09:33:24 +0000
563@@ -1,6 +1,6 @@
564 /* Test AAPCS layout (VFP variant) */
565
566-/* { dg-do run { target arm*-*-eabi* } } */
567+/* { dg-do run { target arm*-*-*eabi* } } */
568 /* { dg-require-effective-target arm_hard_vfp_ok } */
569 /* { dg-require-effective-target arm32 } */
570 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
571
572=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp4.c'
573--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c 2009-08-06 13:27:45 +0000
574+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c 2012-03-01 09:33:24 +0000
575@@ -1,6 +1,6 @@
576 /* Test AAPCS layout (VFP variant) */
577
578-/* { dg-do run { target arm*-*-eabi* } } */
579+/* { dg-do run { target arm*-*-*eabi* } } */
580 /* { dg-require-effective-target arm_hard_vfp_ok } */
581 /* { dg-require-effective-target arm32 } */
582 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
583
584=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp5.c'
585--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c 2009-08-06 13:27:45 +0000
586+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c 2012-03-01 09:33:24 +0000
587@@ -1,6 +1,6 @@
588 /* Test AAPCS layout (VFP variant) */
589
590-/* { dg-do run { target arm*-*-eabi* } } */
591+/* { dg-do run { target arm*-*-*eabi* } } */
592 /* { dg-require-effective-target arm_hard_vfp_ok } */
593 /* { dg-require-effective-target arm32 } */
594 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
595
596=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp6.c'
597--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c 2009-08-06 13:27:45 +0000
598+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c 2012-03-01 09:33:24 +0000
599@@ -1,6 +1,6 @@
600 /* Test AAPCS layout (VFP variant) */
601
602-/* { dg-do run { target arm*-*-eabi* } } */
603+/* { dg-do run { target arm*-*-*eabi* } } */
604 /* { dg-require-effective-target arm_hard_vfp_ok } */
605 /* { dg-require-effective-target arm32 } */
606 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
607
608=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp7.c'
609--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c 2009-08-06 13:27:45 +0000
610+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c 2012-03-01 09:33:24 +0000
611@@ -1,6 +1,6 @@
612 /* Test AAPCS layout (VFP variant) */
613
614-/* { dg-do run { target arm*-*-eabi* } } */
615+/* { dg-do run { target arm*-*-*eabi* } } */
616 /* { dg-require-effective-target arm_hard_vfp_ok } */
617 /* { dg-require-effective-target arm32 } */
618 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
619
620=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp8.c'
621--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c 2009-08-06 13:27:45 +0000
622+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c 2012-03-01 09:33:24 +0000
623@@ -1,6 +1,6 @@
624 /* Test AAPCS layout (VFP variant) */
625
626-/* { dg-do run { target arm*-*-eabi* } } */
627+/* { dg-do run { target arm*-*-*eabi* } } */
628 /* { dg-require-effective-target arm_hard_vfp_ok } */
629 /* { dg-require-effective-target arm32 } */
630 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
631
632=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp9.c'
633--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c 2009-08-06 13:27:45 +0000
634+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c 2012-03-01 09:33:24 +0000
635@@ -1,6 +1,6 @@
636 /* Test AAPCS layout (VFP variant) */
637
638-/* { dg-do run { target arm*-*-eabi* } } */
639+/* { dg-do run { target arm*-*-*eabi* } } */
640 /* { dg-require-effective-target arm_hard_vfp_ok } */
641 /* { dg-require-effective-target arm32 } */
642 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
643
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106882.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106882.patch
deleted file mode 100644
index 7ac7645b9..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106882.patch
+++ /dev/null
@@ -1,53 +0,0 @@
12012-03-26 Ulrich Weigand <ulrich.weigand@linaro.org>
2
3 LP 960283
4 LP 960274
5 LP 960817
6
7 Backport from mainline:
8
9 gcc/
10 PR tree-optimization/52686
11 * tree-vect-data-refs.c (vect_get_smallest_scalar_type): Handle
12 WIDEN_LSHIFT_EXPR.
13
14 gcc/testsuite/
15 PR tree-optimization/52686
16 * gcc.target/arm/pr52686.c: New test.
17
18=== added file 'gcc/testsuite/gcc.target/arm/pr52686.c'
19--- old/gcc/testsuite/gcc.target/arm/pr52686.c 1970-01-01 00:00:00 +0000
20+++ new/gcc/testsuite/gcc.target/arm/pr52686.c 2012-03-23 16:26:22 +0000
21@@ -0,0 +1,19 @@
22+/* PR target/52375 */
23+/* { dg-do compile } */
24+/* { dg-require-effective-target arm_neon_ok } */
25+/* { dg-options "-march=armv7-a -mfloat-abi=softfp -mfpu=neon -O -ftree-vectorize" } */
26+
27+unsigned int output[4];
28+
29+void test (unsigned short *p)
30+{
31+ unsigned int x = *p;
32+ if (x)
33+ {
34+ output[0] = x << 1;
35+ output[1] = x << 1;
36+ output[2] = x << 1;
37+ output[3] = x << 1;
38+ }
39+}
40+
41
42=== modified file 'gcc/tree-vect-data-refs.c'
43--- old/gcc/tree-vect-data-refs.c 2012-01-05 15:35:39 +0000
44+++ new/gcc/tree-vect-data-refs.c 2012-03-23 16:26:22 +0000
45@@ -111,6 +111,7 @@
46 if (is_gimple_assign (stmt)
47 && (gimple_assign_cast_p (stmt)
48 || gimple_assign_rhs_code (stmt) == WIDEN_MULT_EXPR
49+ || gimple_assign_rhs_code (stmt) == WIDEN_LSHIFT_EXPR
50 || gimple_assign_rhs_code (stmt) == FLOAT_EXPR))
51 {
52 tree rhs_type = TREE_TYPE (gimple_assign_rhs1 (stmt));
53
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/mips64-default-n64.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/mips64-default-n64.patch
new file mode 100644
index 000000000..bf930ec36
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/mips64-default-n64.patch
@@ -0,0 +1,32 @@
1MIPS64 defaults to n32 ABI, this patch makes it
2so that it defaults to N64 ABI
3
4Upstream-Status: Inappropriate [OE config specific]
5
6Signed-off-by: Khem Raj <raj.khem@gmail.com>
7Index: gcc-4_6-branch/gcc/config.gcc
8===================================================================
9--- gcc-4_6-branch.orig/gcc/config.gcc 2012-04-22 19:12:12.431061229 -0700
10+++ gcc-4_6-branch/gcc/config.gcc 2012-04-22 19:13:36.307065289 -0700
11@@ -1882,7 +1882,7 @@
12 mips64*-*-linux* | mipsisa64*-*-linux*)
13 tm_file="dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h ${tm_file} mips/linux.h mips/linux64.h"
14 tmake_file="${tmake_file} mips/t-linux64 mips/t-libgcc-mips16"
15- tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_N32"
16+ tm_defines="${tm_defines} MIPS_ABI_DEFAULT=ABI_64"
17 case ${target} in
18 mips64el-st-linux-gnu)
19 tm_file="${tm_file} mips/st.h"
20Index: gcc-4_6-branch/gcc/config/mips/linux64.h
21===================================================================
22--- gcc-4_6-branch.orig/gcc/config/mips/linux64.h 2012-04-22 19:10:59.743057711 -0700
23+++ gcc-4_6-branch/gcc/config/mips/linux64.h 2012-04-22 19:11:56.919060479 -0700
24@@ -26,7 +26,7 @@
25 BASE_DRIVER_SELF_SPECS, \
26 LINUX_DRIVER_SELF_SPECS \
27 " %{!EB:%{!EL:%(endian_spec)}}" \
28- " %{!mabi=*: -mabi=n32}"
29+ " %{!mabi=*: -mabi=64}"
30
31 #undef LIB_SPEC
32 #define LIB_SPEC "\
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/optional_libstdc.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/optional_libstdc.patch
new file mode 100644
index 000000000..fe157a892
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/optional_libstdc.patch
@@ -0,0 +1,86 @@
1Upstream-Status: Inappropriate [embedded specific]
2
3gcc-runtime builds libstdc++ separately from gcc-cross-*. Its configure tests using g++
4will not run correctly since by default the linker will try to link against libstdc++
5which shouldn't exist yet. We need an option to disable -lstdc++
6option whilst leaving -lc, -lgcc and other automatic library dependencies added by gcc
7driver. This patch adds such an option which only disables the -lstdc++.
8
9A "standard" gcc build uses xgcc and hence avoids this. We should ask upstream how to
10do this officially, the likely answer is don't build libstdc++ separately.
11
12RP 29/6/10
13
14Index: gcc-4.6.0/gcc/cp/g++spec.c
15===================================================================
16--- gcc-4.6.0.orig/gcc/cp/g++spec.c
17+++ gcc-4.6.0/gcc/cp/g++spec.c
18@@ -127,6 +127,7 @@ lang_specific_driver (struct cl_decoded_
19 switch (decoded_options[i].opt_index)
20 {
21 case OPT_nostdlib:
22+ case OPT_nostdlib__:
23 case OPT_nodefaultlibs:
24 library = -1;
25 break;
26Index: gcc-4.6.0/gcc/doc/invoke.texi
27===================================================================
28--- gcc-4.6.0.orig/gcc/doc/invoke.texi
29+++ gcc-4.6.0/gcc/doc/invoke.texi
30@@ -193,7 +193,7 @@ in the following sections.
31 -fno-pretty-templates @gol
32 -frepo -fno-rtti -fstats -ftemplate-depth=@var{n} @gol
33 -fno-threadsafe-statics -fuse-cxa-atexit -fno-weak -nostdinc++ @gol
34--fno-default-inline -fvisibility-inlines-hidden @gol
35+-nostdlib++ -fno-default-inline -fvisibility-inlines-hidden @gol
36 -fvisibility-ms-compat @gol
37 -Wabi -Wconversion-null -Wctor-dtor-privacy @gol
38 -Wnoexcept -Wnon-virtual-dtor -Wreorder @gol
39@@ -431,7 +431,7 @@ Objective-C and Objective-C++ Dialects}.
40 @gccoptlist{@var{object-file-name} -l@var{library} @gol
41 -nostartfiles -nodefaultlibs -nostdlib -pie -rdynamic @gol
42 -s -static -static-libgcc -static-libstdc++ -shared @gol
43--shared-libgcc -symbolic @gol
44+-shared-libgcc -symbolic -nostdlib++ @gol
45 -T @var{script} -Wl,@var{option} -Xlinker @var{option} @gol
46 -u @var{symbol}}
47
48@@ -9069,6 +9069,11 @@ These entries are usually resolved by en
49 libc. These entry points should be supplied through some other
50 mechanism when this option is specified.
51
52+@item -nostdlib++
53+@opindex nostdlib++
54+Do not use the standard system C++ runtime libraries when linking.
55+Only the libraries you specify will be passed to the linker.
56+
57 @cindex @option{-lgcc}, use with @option{-nostdlib}
58 @cindex @option{-nostdlib} and unresolved references
59 @cindex unresolved references and @option{-nostdlib}
60Index: gcc-4.6.0/gcc/c-family/c.opt
61===================================================================
62--- gcc-4.6.0.orig/gcc/c-family/c.opt
63+++ gcc-4.6.0/gcc/c-family/c.opt
64@@ -1111,6 +1111,10 @@ nostdinc++
65 C++ ObjC++
66 Do not search standard system include directories for C++
67
68+nostdlib++
69+Driver
70+Do not link standard C++ runtime library
71+
72 o
73 C ObjC C++ ObjC++ Joined Separate
74 ; Documented in common.opt
75Index: gcc-4.6.0/gcc/gcc.c
76===================================================================
77--- gcc-4.6.0.orig/gcc/gcc.c
78+++ gcc-4.6.0/gcc/gcc.c
79@@ -666,6 +666,7 @@ proper position among the other output f
80 %(mflib) " STACK_SPLIT_SPEC "\
81 %{fprofile-arcs|fprofile-generate*|coverage:-lgcov}\
82 %{!nostdlib:%{!nodefaultlibs:%(link_ssp) %(link_gcc_c_sequence)}}\
83+ %{!nostdlib++:}\
84 %{!nostdlib:%{!nostartfiles:%E}} %{T*} }}}}}}"
85 #endif
86
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/powerpc-e5500.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/powerpc-e5500.patch
new file mode 100644
index 000000000..1f478f3ea
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/powerpc-e5500.patch
@@ -0,0 +1,465 @@
1Upstream-Status: Pending
2
3Implements basic e5500 enablement in gcc, with a scheduler, -mcpu
4flag, etc...
5
6Also splits the masks for popcntb, popcntd, and cmpb. Originally those
7masks would also control other instructions that e5500 does not
8support (so, we either get none or all).
9
10For the lack of means to do tests, those instructions were never
11enabled until now. The new instructions enabled with this patch are:
12popcntb, popcntw, popcntd, bpermd, prtyw, prtyd, cmpb, ldbrx, and
13stdbrx.
14
15Signed-off-by: Edmar Wienskoski <edmar@freescale.com>
16Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
17
18Index: gcc-4_6-branch/gcc/config.gcc
19===================================================================
20--- gcc-4_6-branch.orig/gcc/config.gcc
21+++ gcc-4_6-branch/gcc/config.gcc
22@@ -395,7 +395,7 @@ powerpc*-*-*)
23 extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h"
24 need_64bit_hwint=yes
25 case x$with_cpu in
26- xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64)
27+ xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500)
28 cpu_is_64bit=yes
29 ;;
30 esac
31@@ -3493,7 +3493,7 @@ case "${target}" in
32 | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
33 | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \
34 | 604 | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
35- | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | titan\
36+ | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | e5500 | titan\
37 | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
38 # OK
39 ;;
40Index: gcc-4_6-branch/gcc/config/rs6000/e5500.md
41===================================================================
42--- /dev/null
43+++ gcc-4_6-branch/gcc/config/rs6000/e5500.md
44@@ -0,0 +1,176 @@
45+;; Pipeline description for Freescale PowerPC e5500 core.
46+;; Copyright (C) 2011 Free Software Foundation, Inc.
47+;; Contributed by Edmar Wienskoski (edmar@freescale.com)
48+;;
49+;; This file is part of GCC.
50+;;
51+;; GCC is free software; you can redistribute it and/or modify it
52+;; under the terms of the GNU General Public License as published
53+;; by the Free Software Foundation; either version 3, or (at your
54+;; option) any later version.
55+;;
56+;; GCC is distributed in the hope that it will be useful, but WITHOUT
57+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
58+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
59+;; License for more details.
60+;;
61+;; You should have received a copy of the GNU General Public License
62+;; along with GCC; see the file COPYING3. If not see
63+;; <http://www.gnu.org/licenses/>.
64+;;
65+;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
66+;; Max issue 3 insns/clock cycle (includes 1 branch)
67+
68+(define_automaton "e5500_most,e5500_long")
69+(define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most")
70+
71+;; SFX.
72+(define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most")
73+
74+;; CFX.
75+(define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most")
76+
77+;; Non-pipelined division.
78+(define_cpu_unit "e5500_cfx_div" "e5500_long")
79+
80+;; LSU.
81+(define_cpu_unit "e5500_lsu" "e5500_most")
82+
83+;; FPU.
84+(define_cpu_unit "e5500_fpu" "e5500_long")
85+
86+;; BU.
87+(define_cpu_unit "e5500_bu" "e5500_most")
88+
89+;; The following units are used to make the automata deterministic.
90+(define_cpu_unit "present_e5500_decode_0" "e5500_most")
91+(define_cpu_unit "present_e5500_sfx_0" "e5500_most")
92+(presence_set "present_e5500_decode_0" "e5500_decode_0")
93+(presence_set "present_e5500_sfx_0" "e5500_sfx_0")
94+
95+;; Some useful abbreviations.
96+(define_reservation "e5500_decode"
97+ "e5500_decode_0|e5500_decode_1+present_e5500_decode_0")
98+(define_reservation "e5500_sfx"
99+ "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0")
100+
101+;; SFX.
102+(define_insn_reservation "e5500_sfx" 1
103+ (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
104+ shift,cntlz,exts")
105+ (eq_attr "cpu" "ppce5500"))
106+ "e5500_decode,e5500_sfx")
107+
108+(define_insn_reservation "e5500_sfx2" 2
109+ (and (eq_attr "type" "cmp,compare,fast_compare,trap")
110+ (eq_attr "cpu" "ppce5500"))
111+ "e5500_decode,e5500_sfx")
112+
113+(define_insn_reservation "e5500_delayed" 2
114+ (and (eq_attr "type" "var_shift_rotate,var_delayed_compare,popcnt")
115+ (eq_attr "cpu" "ppce5500"))
116+ "e5500_decode,e5500_sfx*2")
117+
118+(define_insn_reservation "e5500_two" 2
119+ (and (eq_attr "type" "two")
120+ (eq_attr "cpu" "ppce5500"))
121+ "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx")
122+
123+(define_insn_reservation "e5500_three" 3
124+ (and (eq_attr "type" "three")
125+ (eq_attr "cpu" "ppce5500"))
126+ "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx")
127+
128+;; SFX - Mfcr.
129+(define_insn_reservation "e5500_mfcr" 4
130+ (and (eq_attr "type" "mfcr")
131+ (eq_attr "cpu" "ppce5500"))
132+ "e5500_decode,e5500_sfx_0*4")
133+
134+;; SFX - Mtcrf.
135+(define_insn_reservation "e5500_mtcrf" 1
136+ (and (eq_attr "type" "mtcr")
137+ (eq_attr "cpu" "ppce5500"))
138+ "e5500_decode,e5500_sfx_0")
139+
140+;; SFX - Mtjmpr.
141+(define_insn_reservation "e5500_mtjmpr" 1
142+ (and (eq_attr "type" "mtjmpr,mfjmpr")
143+ (eq_attr "cpu" "ppce5500"))
144+ "e5500_decode,e5500_sfx")
145+
146+;; CFX - Multiply.
147+(define_insn_reservation "e5500_multiply" 4
148+ (and (eq_attr "type" "imul")
149+ (eq_attr "cpu" "ppce5500"))
150+ "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
151+
152+(define_insn_reservation "e5500_multiply_i" 5
153+ (and (eq_attr "type" "imul2,imul3,imul_compare")
154+ (eq_attr "cpu" "ppce5500"))
155+ "e5500_decode,e5500_cfx_stage0,\
156+ e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
157+
158+;; CFX - Divide.
159+(define_insn_reservation "e5500_divide" 16
160+ (and (eq_attr "type" "idiv")
161+ (eq_attr "cpu" "ppce5500"))
162+ "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
163+ e5500_cfx_div*15")
164+
165+(define_insn_reservation "e5500_divide_d" 26
166+ (and (eq_attr "type" "ldiv")
167+ (eq_attr "cpu" "ppce5500"))
168+ "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
169+ e5500_cfx_div*25")
170+
171+;; LSU - Loads.
172+(define_insn_reservation "e5500_load" 3
173+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
174+ load_l,sync")
175+ (eq_attr "cpu" "ppce5500"))
176+ "e5500_decode,e5500_lsu")
177+
178+(define_insn_reservation "e5500_fpload" 4
179+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
180+ (eq_attr "cpu" "ppce5500"))
181+ "e5500_decode,e5500_lsu")
182+
183+;; LSU - Stores.
184+(define_insn_reservation "e5500_store" 3
185+ (and (eq_attr "type" "store,store_ux,store_u,store_c")
186+ (eq_attr "cpu" "ppce5500"))
187+ "e5500_decode,e5500_lsu")
188+
189+(define_insn_reservation "e5500_fpstore" 3
190+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
191+ (eq_attr "cpu" "ppce5500"))
192+ "e5500_decode,e5500_lsu")
193+
194+;; FP.
195+(define_insn_reservation "e5500_float" 7
196+ (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
197+ (eq_attr "cpu" "ppce5500"))
198+ "e5500_decode,e5500_fpu")
199+
200+(define_insn_reservation "e5500_sdiv" 20
201+ (and (eq_attr "type" "sdiv")
202+ (eq_attr "cpu" "ppce5500"))
203+ "e5500_decode,e5500_fpu*20")
204+
205+(define_insn_reservation "e5500_ddiv" 35
206+ (and (eq_attr "type" "ddiv")
207+ (eq_attr "cpu" "ppce5500"))
208+ "e5500_decode,e5500_fpu*35")
209+
210+;; BU.
211+(define_insn_reservation "e5500_branch" 1
212+ (and (eq_attr "type" "jmpreg,branch,isync")
213+ (eq_attr "cpu" "ppce5500"))
214+ "e5500_decode,e5500_bu")
215+
216+;; BU - CR logical.
217+(define_insn_reservation "e5500_cr_logical" 1
218+ (and (eq_attr "type" "cr_logical,delayed_cr")
219+ (eq_attr "cpu" "ppce5500"))
220+ "e5500_decode,e5500_bu")
221Index: gcc-4_6-branch/gcc/config/rs6000/rs6000-opts.h
222===================================================================
223--- gcc-4_6-branch.orig/gcc/config/rs6000/rs6000-opts.h
224+++ gcc-4_6-branch/gcc/config/rs6000/rs6000-opts.h
225@@ -53,6 +53,7 @@ enum processor_type
226 PROCESSOR_PPCE300C3,
227 PROCESSOR_PPCE500MC,
228 PROCESSOR_PPCE500MC64,
229+ PROCESSOR_PPCE5500,
230 PROCESSOR_POWER4,
231 PROCESSOR_POWER5,
232 PROCESSOR_POWER6,
233Index: gcc-4_6-branch/gcc/config/rs6000/rs6000.c
234===================================================================
235--- gcc-4_6-branch.orig/gcc/config/rs6000/rs6000.c
236+++ gcc-4_6-branch/gcc/config/rs6000/rs6000.c
237@@ -779,6 +779,25 @@ struct processor_costs ppce500mc64_cost
238 1, /* prefetch streams /*/
239 };
240
241+/* Instruction costs on PPCE5500 processors. */
242+static const
243+struct processor_costs ppce5500_cost = {
244+ COSTS_N_INSNS (5), /* mulsi */
245+ COSTS_N_INSNS (5), /* mulsi_const */
246+ COSTS_N_INSNS (5), /* mulsi_const9 */
247+ COSTS_N_INSNS (5), /* muldi */
248+ COSTS_N_INSNS (14), /* divsi */
249+ COSTS_N_INSNS (14), /* divdi */
250+ COSTS_N_INSNS (7), /* fp */
251+ COSTS_N_INSNS (10), /* dmul */
252+ COSTS_N_INSNS (36), /* sdiv */
253+ COSTS_N_INSNS (66), /* ddiv */
254+ 64, /* cache line size */
255+ 32, /* l1 cache */
256+ 128, /* l2 cache */
257+ 1, /* prefetch streams /*/
258+};
259+
260 /* Instruction costs on AppliedMicro Titan processors. */
261 static const
262 struct processor_costs titan_cost = {
263@@ -1784,6 +1803,9 @@ static struct rs6000_ptt const processor
264 | MASK_ISEL},
265 {"e500mc64", PROCESSOR_PPCE500MC64, POWERPC_BASE_MASK | MASK_POWERPC64
266 | MASK_PPC_GFXOPT | MASK_ISEL},
267+ {"e5500", PROCESSOR_PPCE5500, POWERPC_BASE_MASK | MASK_POWERPC64
268+ | MASK_PPC_GFXOPT | MASK_ISEL | MASK_CMPB | MASK_POPCNTB
269+ | MASK_POPCNTD},
270 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
271 {"970", PROCESSOR_POWER4,
272 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
273@@ -2741,7 +2763,8 @@ rs6000_option_override_internal (bool gl
274 : PROCESSOR_DEFAULT));
275
276 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
277- || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
278+ || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
279+ || rs6000_cpu == PROCESSOR_PPCE5500)
280 {
281 if (TARGET_ALTIVEC)
282 error ("AltiVec not supported in this target");
283@@ -2842,9 +2865,14 @@ rs6000_option_override_internal (bool gl
284 user's opinion, though. */
285 if (rs6000_block_move_inline_limit == 0
286 && (rs6000_cpu == PROCESSOR_PPCE500MC
287- || rs6000_cpu == PROCESSOR_PPCE500MC64))
288+ || rs6000_cpu == PROCESSOR_PPCE500MC64
289+ || rs6000_cpu == PROCESSOR_PPCE5500))
290 rs6000_block_move_inline_limit = 128;
291
292+ /* Those machines does not have fsqrt instruction */
293+ if (rs6000_cpu == PROCESSOR_PPCE5500)
294+ target_flags &= ~MASK_PPC_GPOPT;
295+
296 /* store_one_arg depends on expand_block_move to handle at least the
297 size of reg_parm_stack_space. */
298 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
299@@ -2976,7 +3004,8 @@ rs6000_option_override_internal (bool gl
300 #endif
301
302 if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC
303- || rs6000_cpu == PROCESSOR_PPCE500MC64)
304+ || rs6000_cpu == PROCESSOR_PPCE500MC64
305+ || rs6000_cpu == PROCESSOR_PPCE5500)
306 {
307 /* The e500 and e500mc do not have string instructions, and we set
308 MASK_STRING above when optimizing for size. */
309@@ -3023,7 +3052,8 @@ rs6000_option_override_internal (bool gl
310 || rs6000_cpu == PROCESSOR_POWER6
311 || rs6000_cpu == PROCESSOR_POWER7
312 || rs6000_cpu == PROCESSOR_PPCE500MC
313- || rs6000_cpu == PROCESSOR_PPCE500MC64);
314+ || rs6000_cpu == PROCESSOR_PPCE500MC64
315+ || rs6000_cpu == PROCESSOR_PPCE5500);
316
317 /* Allow debug switches to override the above settings. These are set to -1
318 in rs6000.opt to indicate the user hasn't directly set the switch. */
319@@ -3245,6 +3275,10 @@ rs6000_option_override_internal (bool gl
320 rs6000_cost = &ppce500mc64_cost;
321 break;
322
323+ case PROCESSOR_PPCE5500:
324+ rs6000_cost = &ppce5500_cost;
325+ break;
326+
327 case PROCESSOR_TITAN:
328 rs6000_cost = &titan_cost;
329 break;
330@@ -23227,6 +23261,7 @@ rs6000_adjust_cost (rtx insn, rtx link,
331 || rs6000_cpu_attr == CPU_PPC750
332 || rs6000_cpu_attr == CPU_PPC7400
333 || rs6000_cpu_attr == CPU_PPC7450
334+ || rs6000_cpu_attr == CPU_PPCE5500
335 || rs6000_cpu_attr == CPU_POWER4
336 || rs6000_cpu_attr == CPU_POWER5
337 || rs6000_cpu_attr == CPU_POWER7
338@@ -23771,6 +23806,7 @@ rs6000_issue_rate (void)
339 case CPU_PPCE300C3:
340 case CPU_PPCE500MC:
341 case CPU_PPCE500MC64:
342+ case CPU_PPCE5500:
343 case CPU_TITAN:
344 return 2;
345 case CPU_RIOS2:
346Index: gcc-4_6-branch/gcc/config/rs6000/rs6000.h
347===================================================================
348--- gcc-4_6-branch.orig/gcc/config/rs6000/rs6000.h
349+++ gcc-4_6-branch/gcc/config/rs6000/rs6000.h
350@@ -168,6 +168,7 @@
351 %{mcpu=e300c3: -me300} \
352 %{mcpu=e500mc: -me500mc} \
353 %{mcpu=e500mc64: -me500mc64} \
354+%{mcpu=e5500: -me5500} \
355 %{maltivec: -maltivec} \
356 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
357 -many"
358@@ -477,13 +478,13 @@ extern int rs6000_vector_align[];
359
360 #define TARGET_FCTIDZ TARGET_FCFID
361 #define TARGET_STFIWX TARGET_PPC_GFXOPT
362-#define TARGET_LFIWAX TARGET_CMPB
363-#define TARGET_LFIWZX TARGET_POPCNTD
364-#define TARGET_FCFIDS TARGET_POPCNTD
365-#define TARGET_FCFIDU TARGET_POPCNTD
366-#define TARGET_FCFIDUS TARGET_POPCNTD
367-#define TARGET_FCTIDUZ TARGET_POPCNTD
368-#define TARGET_FCTIWUZ TARGET_POPCNTD
369+#define TARGET_LFIWAX (TARGET_CMPB && rs6000_cpu != PROCESSOR_PPCE5500)
370+#define TARGET_LFIWZX (TARGET_POPCNTD && rs6000_cpu != PROCESSOR_PPCE5500)
371+#define TARGET_FCFIDS TARGET_LFIWZX
372+#define TARGET_FCFIDU TARGET_LFIWZX
373+#define TARGET_FCFIDUS TARGET_LFIWZX
374+#define TARGET_FCTIDUZ TARGET_LFIWZX
375+#define TARGET_FCTIWUZ TARGET_LFIWZX
376
377 /* E500 processors only support plain "sync", not lwsync. */
378 #define TARGET_NO_LWSYNC TARGET_E500
379@@ -494,10 +495,12 @@ extern int rs6000_vector_align[];
380
381 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
382 && TARGET_DOUBLE_FLOAT \
383- && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
384+ && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)) \
385+ && rs6000_cpu != PROCESSOR_PPCE5500)
386
387 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
388- && TARGET_FPRS && TARGET_SINGLE_FLOAT)
389+ && TARGET_FPRS && TARGET_SINGLE_FLOAT \
390+ && rs6000_cpu != PROCESSOR_PPCE5500)
391
392 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
393 && TARGET_DOUBLE_FLOAT \
394Index: gcc-4_6-branch/gcc/config/rs6000/rs6000.md
395===================================================================
396--- gcc-4_6-branch.orig/gcc/config/rs6000/rs6000.md
397+++ gcc-4_6-branch/gcc/config/rs6000/rs6000.md
398@@ -126,7 +126,7 @@
399
400 ;; Define an insn type attribute. This is used in function unit delay
401 ;; computations.
402-(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
403+(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
404 (const_string "integer"))
405
406 ;; Define floating point instruction sub-types for use with Xfpu.md
407@@ -148,7 +148,7 @@
408 ;; Processor type -- this attribute must exactly match the processor_type
409 ;; enumeration in rs6000.h.
410
411-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
412+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,power4,power5,power6,power7,cell,ppca2,titan"
413 (const (symbol_ref "rs6000_cpu_attr")))
414
415
416@@ -176,6 +176,7 @@
417 (include "e300c2c3.md")
418 (include "e500mc.md")
419 (include "e500mc64.md")
420+(include "e5500.md")
421 (include "power4.md")
422 (include "power5.md")
423 (include "power6.md")
424@@ -2302,13 +2303,17 @@
425 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
426 UNSPEC_POPCNTB))]
427 "TARGET_POPCNTB"
428- "popcntb %0,%1")
429+ "popcntb %0,%1"
430+ [(set_attr "length" "4")
431+ (set_attr "type" "popcnt")])
432
433 (define_insn "popcntd<mode>2"
434 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
435 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
436 "TARGET_POPCNTD"
437- "popcnt<wd> %0,%1")
438+ "popcnt<wd> %0,%1"
439+ [(set_attr "length" "4")
440+ (set_attr "type" "popcnt")])
441
442 (define_expand "popcount<mode>2"
443 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
444@@ -5957,10 +5962,10 @@
445 && ((TARGET_PPC_GFXOPT
446 && !HONOR_NANS (<MODE>mode)
447 && !HONOR_SIGNED_ZEROS (<MODE>mode))
448- || TARGET_CMPB
449+ || TARGET_LFIWAX
450 || VECTOR_UNIT_VSX_P (<MODE>mode))"
451 {
452- if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
453+ if (TARGET_LFIWAX || VECTOR_UNIT_VSX_P (<MODE>mode))
454 {
455 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
456 operands[2]));
457@@ -5979,7 +5984,7 @@
458 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
459 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
460 UNSPEC_COPYSIGN))]
461- "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
462+ "TARGET_LFIWAX && !VECTOR_UNIT_VSX_P (<MODE>mode)"
463 "fcpsgn %0,%2,%1"
464 [(set_attr "type" "fp")])
465
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr32219.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr32219.patch
new file mode 100644
index 000000000..c0e35940a
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr32219.patch
@@ -0,0 +1,72 @@
1Upstream-Status:Backport
2Hi,
3
4As suggested by richi.
5regtested on i686-linux-gnu with all default languages and no regressions.
6Ok for trunk?
7
8gcc/ChangeLog
92010-03-15 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
10
11 PR target/32219
12 * varasm.c (default_binds_local_p_1): Weak data is not local.
13
14gcc/testsuite/ChangeLog
152010-03-15 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
16
17 PR target/32219
18 * gcc.dg/visibility-21.c: New test.
19
20Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
21---
22 gcc/testsuite/gcc.dg/visibility-21.c | 14 ++++++++++++++
23 gcc/varasm.c | 8 ++++----
24 2 files changed, 18 insertions(+), 4 deletions(-)
25 create mode 100644 gcc/testsuite/gcc.dg/visibility-21.c
26
27Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/visibility-21.c
28===================================================================
29--- /dev/null 1970-01-01 00:00:00.000000000 +0000
30+++ gcc-4_6-branch/gcc/testsuite/gcc.dg/visibility-21.c 2011-10-18 17:11:33.224827436 -0700
31@@ -0,0 +1,14 @@
32+/* PR target/32219 */
33+/* { dg-do run } */
34+/* { dg-require-visibility "" } */
35+/* { dg-options "-fPIC" { target fpic } } */
36+
37+extern void f() __attribute__((weak,visibility("hidden")));
38+extern int puts( char const* );
39+int main()
40+{
41+ if (f)
42+ f();
43+ return 0;
44+}
45+
46Index: gcc-4_6-branch/gcc/varasm.c
47===================================================================
48--- gcc-4_6-branch.orig/gcc/varasm.c 2011-09-16 19:58:21.000000000 -0700
49+++ gcc-4_6-branch/gcc/varasm.c 2011-10-18 17:19:06.431074788 -0700
50@@ -6760,6 +6760,10 @@
51 /* Static variables are always local. */
52 else if (! TREE_PUBLIC (exp))
53 local_p = true;
54+ /* hidden weak can't be overridden by something non-local, all
55+ that is possible is that it is not defined at all. */
56+ else if (DECL_WEAK (exp))
57+ local_p = false;
58 /* A variable is local if the user has said explicitly that it will
59 be. */
60 else if ((DECL_VISIBILITY_SPECIFIED (exp)
61@@ -6773,11 +6777,6 @@
62 local. */
63 else if (DECL_VISIBILITY (exp) != VISIBILITY_DEFAULT)
64 local_p = true;
65- /* Default visibility weak data can be overridden by a strong symbol
66- in another module and so are not local. */
67- else if (DECL_WEAK (exp)
68- && !resolved_locally)
69- local_p = false;
70 /* If PIC, then assume that any global name can be overridden by
71 symbols resolved from other modules. */
72 else if (shlib)
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr46934.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr46934.patch
new file mode 100644
index 000000000..60b7012bd
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr46934.patch
@@ -0,0 +1,393 @@
1Upstream-Status:Backport
22011-09-19 chengbin <bin.cheng@arm.com>
3
4 Backport r174035 from mainline
5 2011-05-22 Tom de Vries <tom@codesourcery.com>
6
7 PR middle-end/48689
8 * fold-const.c (fold_checksum_tree): Guard TREE_CHAIN use with
9 CODE_CONTAINS_STRUCT (TS_COMMON).
10
11 Backport r172297 from mainline
12 2011-04-11 Chung-Lin Tang <cltang@codesourcery.com>
13 Richard Earnshaw <rearnsha@arm.com>
14
15 PR target/48250
16 * config/arm/arm.c (arm_legitimize_reload_address): Update cases
17 to use sign-magnitude offsets. Reject unsupported unaligned
18 cases. Add detailed description in comments.
19 * config/arm/arm.md (reload_outdf): Disable for ARM mode; change
20 condition from TARGET_32BIT to TARGET_ARM.
21
22 Backport r171978 from mainline
23 2011-04-05 Tom de Vries <tom@codesourcery.com>
24
25 PR target/43920
26 * config/arm/arm.h (BRANCH_COST): Set to 1 for Thumb-2 when optimizing
27 for size.
28
29 Backport r171632 from mainline
30 2011-03-28 Richard Sandiford <richard.sandiford@linaro.org>
31
32 * builtins.c (expand_builtin_memset_args): Use gen_int_mode
33 instead of GEN_INT.
34
35 Backport r171379 from mainline
36 2011-03-23 Chung-Lin Tang <cltang@codesourcery.com>
37
38 PR target/46934
39 * config/arm/arm.md (casesi): Use the gen_int_mode() function
40 to subtract lower bound instead of GEN_INT().
41
42 Backport r171251 from mainline
43 2011-03-21 Daniel Jacobowitz <dan@codesourcery.com>
44
45 * config/arm/unwind-arm.c (__gnu_unwind_pr_common): Correct test
46 for barrier handlers.
47
48 Backport r171096 from mainline
49 2011-03-17 Chung-Lin Tang <cltang@codesourcery.com>
50
51 PR target/43872
52 * config/arm/arm.c (arm_get_frame_offsets): Adjust early
53 return condition with !cfun->calls_alloca.
54
55Index: gcc-4_6-branch/gcc/builtins.c
56===================================================================
57--- gcc-4_6-branch.orig/gcc/builtins.c 2011-10-17 17:45:32.050502963 -0700
58+++ gcc-4_6-branch/gcc/builtins.c 2011-10-17 17:46:11.154696878 -0700
59@@ -3972,6 +3972,7 @@
60 {
61 tree fndecl, fn;
62 enum built_in_function fcode;
63+ enum machine_mode val_mode;
64 char c;
65 unsigned int dest_align;
66 rtx dest_mem, dest_addr, len_rtx;
67@@ -4006,14 +4007,14 @@
68
69 len_rtx = expand_normal (len);
70 dest_mem = get_memory_rtx (dest, len);
71+ val_mode = TYPE_MODE (unsigned_char_type_node);
72
73 if (TREE_CODE (val) != INTEGER_CST)
74 {
75 rtx val_rtx;
76
77 val_rtx = expand_normal (val);
78- val_rtx = convert_to_mode (TYPE_MODE (unsigned_char_type_node),
79- val_rtx, 0);
80+ val_rtx = convert_to_mode (val_mode, val_rtx, 0);
81
82 /* Assume that we can memset by pieces if we can store
83 * the coefficients by pieces (in the required modes).
84@@ -4024,8 +4025,7 @@
85 builtin_memset_read_str, &c, dest_align,
86 true))
87 {
88- val_rtx = force_reg (TYPE_MODE (unsigned_char_type_node),
89- val_rtx);
90+ val_rtx = force_reg (val_mode, val_rtx);
91 store_by_pieces (dest_mem, tree_low_cst (len, 1),
92 builtin_memset_gen_str, val_rtx, dest_align,
93 true, 0);
94@@ -4051,7 +4051,8 @@
95 true))
96 store_by_pieces (dest_mem, tree_low_cst (len, 1),
97 builtin_memset_read_str, &c, dest_align, true, 0);
98- else if (!set_storage_via_setmem (dest_mem, len_rtx, GEN_INT (c),
99+ else if (!set_storage_via_setmem (dest_mem, len_rtx,
100+ gen_int_mode (c, val_mode),
101 dest_align, expected_align,
102 expected_size))
103 goto do_libcall;
104Index: gcc-4_6-branch/gcc/config/arm/arm.c
105===================================================================
106--- gcc-4_6-branch.orig/gcc/config/arm/arm.c 2011-10-17 17:45:41.914551883 -0700
107+++ gcc-4_6-branch/gcc/config/arm/arm.c 2011-10-17 17:48:35.447412371 -0700
108@@ -6406,23 +6406,126 @@
109 HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));
110 HOST_WIDE_INT low, high;
111
112- if (mode == DImode || (mode == DFmode && TARGET_SOFT_FLOAT))
113- low = ((val & 0xf) ^ 0x8) - 0x8;
114- else if (TARGET_MAVERICK && TARGET_HARD_FLOAT)
115- /* Need to be careful, -256 is not a valid offset. */
116- low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);
117- else if (mode == SImode
118- || (mode == SFmode && TARGET_SOFT_FLOAT)
119- || ((mode == HImode || mode == QImode) && ! arm_arch4))
120- /* Need to be careful, -4096 is not a valid offset. */
121- low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff);
122- else if ((mode == HImode || mode == QImode) && arm_arch4)
123- /* Need to be careful, -256 is not a valid offset. */
124- low = val >= 0 ? (val & 0xff) : -((-val) & 0xff);
125- else if (GET_MODE_CLASS (mode) == MODE_FLOAT
126- && TARGET_HARD_FLOAT && TARGET_FPA)
127- /* Need to be careful, -1024 is not a valid offset. */
128- low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff);
129+ /* Detect coprocessor load/stores. */
130+ bool coproc_p = ((TARGET_HARD_FLOAT
131+ && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK)
132+ && (mode == SFmode || mode == DFmode
133+ || (mode == DImode && TARGET_MAVERICK)))
134+ || (TARGET_REALLY_IWMMXT
135+ && VALID_IWMMXT_REG_MODE (mode))
136+ || (TARGET_NEON
137+ && (VALID_NEON_DREG_MODE (mode)
138+ || VALID_NEON_QREG_MODE (mode))));
139+
140+ /* For some conditions, bail out when lower two bits are unaligned. */
141+ if ((val & 0x3) != 0
142+ /* Coprocessor load/store indexes are 8-bits + '00' appended. */
143+ && (coproc_p
144+ /* For DI, and DF under soft-float: */
145+ || ((mode == DImode || mode == DFmode)
146+ /* Without ldrd, we use stm/ldm, which does not
147+ fair well with unaligned bits. */
148+ && (! TARGET_LDRD
149+ /* Thumb-2 ldrd/strd is [-1020,+1020] in steps of 4. */
150+ || TARGET_THUMB2))))
151+ return false;
152+
153+ /* When breaking down a [reg+index] reload address into [(reg+high)+low],
154+ of which the (reg+high) gets turned into a reload add insn,
155+ we try to decompose the index into high/low values that can often
156+ also lead to better reload CSE.
157+ For example:
158+ ldr r0, [r2, #4100] // Offset too large
159+ ldr r1, [r2, #4104] // Offset too large
160+
161+ is best reloaded as:
162+ add t1, r2, #4096
163+ ldr r0, [t1, #4]
164+ add t2, r2, #4096
165+ ldr r1, [t2, #8]
166+
167+ which post-reload CSE can simplify in most cases to eliminate the
168+ second add instruction:
169+ add t1, r2, #4096
170+ ldr r0, [t1, #4]
171+ ldr r1, [t1, #8]
172+
173+ The idea here is that we want to split out the bits of the constant
174+ as a mask, rather than as subtracting the maximum offset that the
175+ respective type of load/store used can handle.
176+
177+ When encountering negative offsets, we can still utilize it even if
178+ the overall offset is positive; sometimes this may lead to an immediate
179+ that can be constructed with fewer instructions.
180+ For example:
181+ ldr r0, [r2, #0x3FFFFC]
182+
183+ This is best reloaded as:
184+ add t1, r2, #0x400000
185+ ldr r0, [t1, #-4]
186+
187+ The trick for spotting this for a load insn with N bits of offset
188+ (i.e. bits N-1:0) is to look at bit N; if it is set, then chose a
189+ negative offset that is going to make bit N and all the bits below
190+ it become zero in the remainder part.
191+
192+ The SIGN_MAG_LOW_ADDR_BITS macro below implements this, with respect
193+ to sign-magnitude addressing (i.e. separate +- bit, or 1's complement),
194+ used in most cases of ARM load/store instructions. */
195+
196+#define SIGN_MAG_LOW_ADDR_BITS(VAL, N) \
197+ (((VAL) & ((1 << (N)) - 1)) \
198+ ? (((VAL) & ((1 << ((N) + 1)) - 1)) ^ (1 << (N))) - (1 << (N)) \
199+ : 0)
200+
201+ if (coproc_p)
202+ low = SIGN_MAG_LOW_ADDR_BITS (val, 10);
203+ else if (GET_MODE_SIZE (mode) == 8)
204+ {
205+ if (TARGET_LDRD)
206+ low = (TARGET_THUMB2
207+ ? SIGN_MAG_LOW_ADDR_BITS (val, 10)
208+ : SIGN_MAG_LOW_ADDR_BITS (val, 8));
209+ else
210+ /* For pre-ARMv5TE (without ldrd), we use ldm/stm(db/da/ib)
211+ to access doublewords. The supported load/store offsets are
212+ -8, -4, and 4, which we try to produce here. */
213+ low = ((val & 0xf) ^ 0x8) - 0x8;
214+ }
215+ else if (GET_MODE_SIZE (mode) < 8)
216+ {
217+ /* NEON element load/stores do not have an offset. */
218+ if (TARGET_NEON_FP16 && mode == HFmode)
219+ return false;
220+
221+ if (TARGET_THUMB2)
222+ {
223+ /* Thumb-2 has an asymmetrical index range of (-256,4096).
224+ Try the wider 12-bit range first, and re-try if the result
225+ is out of range. */
226+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
227+ if (low < -255)
228+ low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
229+ }
230+ else
231+ {
232+ if (mode == HImode || mode == HFmode)
233+ {
234+ if (arm_arch4)
235+ low = SIGN_MAG_LOW_ADDR_BITS (val, 8);
236+ else
237+ {
238+ /* The storehi/movhi_bytes fallbacks can use only
239+ [-4094,+4094] of the full ldrb/strb index range. */
240+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
241+ if (low == 4095 || low == -4095)
242+ return false;
243+ }
244+ }
245+ else
246+ low = SIGN_MAG_LOW_ADDR_BITS (val, 12);
247+ }
248+ }
249 else
250 return false;
251
252@@ -15415,7 +15518,10 @@
253 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
254 /* A leaf function does not need any stack alignment if it has nothing
255 on the stack. */
256- if (leaf && frame_size == 0)
257+ if (leaf && frame_size == 0
258+ /* However if it calls alloca(), we have a dynamically allocated
259+ block of BIGGEST_ALIGNMENT on stack, so still do stack alignment. */
260+ && ! cfun->calls_alloca)
261 {
262 offsets->outgoing_args = offsets->soft_frame;
263 offsets->locals_base = offsets->soft_frame;
264Index: gcc-4_6-branch/gcc/config/arm/arm.h
265===================================================================
266--- gcc-4_6-branch.orig/gcc/config/arm/arm.h 2011-10-17 17:45:41.910551858 -0700
267+++ gcc-4_6-branch/gcc/config/arm/arm.h 2011-10-17 17:48:35.447412371 -0700
268@@ -2041,7 +2041,8 @@
269 /* Try to generate sequences that don't involve branches, we can then use
270 conditional instructions */
271 #define BRANCH_COST(speed_p, predictable_p) \
272- (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
273+ (TARGET_32BIT ? (TARGET_THUMB2 && !speed_p ? 1 : 4) \
274+ : (optimize > 0 ? 2 : 0))
275
276 /* Position Independent Code. */
277 /* We decide which register to use based on the compilation options and
278Index: gcc-4_6-branch/gcc/config/arm/arm.md
279===================================================================
280--- gcc-4_6-branch.orig/gcc/config/arm/arm.md 2011-10-17 17:46:11.002696119 -0700
281+++ gcc-4_6-branch/gcc/config/arm/arm.md 2011-10-17 17:46:11.202697111 -0700
282@@ -6187,7 +6187,7 @@
283 [(match_operand:DF 0 "arm_reload_memory_operand" "=o")
284 (match_operand:DF 1 "s_register_operand" "r")
285 (match_operand:SI 2 "s_register_operand" "=&r")]
286- "TARGET_32BIT"
287+ "TARGET_THUMB2"
288 "
289 {
290 enum rtx_code code = GET_CODE (XEXP (operands[0], 0));
291@@ -8359,7 +8359,8 @@
292 rtx reg = gen_reg_rtx (SImode);
293
294 emit_insn (gen_addsi3 (reg, operands[0],
295- GEN_INT (-INTVAL (operands[1]))));
296+ gen_int_mode (-INTVAL (operands[1]),
297+ SImode)));
298 operands[0] = reg;
299 }
300
301Index: gcc-4_6-branch/gcc/config/arm/unwind-arm.c
302===================================================================
303--- gcc-4_6-branch.orig/gcc/config/arm/unwind-arm.c 2011-10-17 17:45:41.390549278 -0700
304+++ gcc-4_6-branch/gcc/config/arm/unwind-arm.c 2011-10-17 17:46:11.000000000 -0700
305@@ -1196,8 +1196,6 @@
306 ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1];
307
308 if (data[0] & uint32_highbit)
309- phase2_call_unexpected_after_unwind = 1;
310- else
311 {
312 data += rtti_count + 1;
313 /* Setup for entry to the handler. */
314@@ -1207,6 +1205,8 @@
315 _Unwind_SetGR (context, 0, (_uw) ucbp);
316 return _URC_INSTALL_CONTEXT;
317 }
318+ else
319+ phase2_call_unexpected_after_unwind = 1;
320 }
321 if (data[0] & uint32_highbit)
322 data++;
323Index: gcc-4_6-branch/gcc/fold-const.c
324===================================================================
325--- gcc-4_6-branch.orig/gcc/fold-const.c 2011-10-17 17:45:32.050502963 -0700
326+++ gcc-4_6-branch/gcc/fold-const.c 2011-10-17 17:46:11.178696990 -0700
327@@ -13788,7 +13788,8 @@
328 if (TREE_CODE_CLASS (code) != tcc_type
329 && TREE_CODE_CLASS (code) != tcc_declaration
330 && code != TREE_LIST
331- && code != SSA_NAME)
332+ && code != SSA_NAME
333+ && CODE_CONTAINS_STRUCT (code, TS_COMMON))
334 fold_checksum_tree (TREE_CHAIN (expr), ctx, ht);
335 switch (TREE_CODE_CLASS (code))
336 {
337Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr40887.c
338===================================================================
339--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr40887.c 2011-06-24 08:13:47.000000000 -0700
340+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr40887.c 2011-10-17 17:46:11.182697014 -0700
341@@ -1,5 +1,6 @@
342 /* { dg-options "-O2 -march=armv5te" } */
343 /* { dg-final { scan-assembler "blx" } } */
344+/* { dg-prune-output "switch .* conflicts with" } */
345
346 int (*indirect_func)();
347
348Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr42575.c
349===================================================================
350--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr42575.c 2011-06-24 08:13:47.000000000 -0700
351+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr42575.c 2011-10-17 17:46:11.182697014 -0700
352@@ -1,4 +1,4 @@
353-/* { dg-options "-O2 -march=armv7-a" } */
354+/* { dg-options "-O2" } */
355 /* Make sure RA does good job allocating registers and avoids
356 unnecessary moves. */
357 /* { dg-final { scan-assembler-not "mov" } } */
358Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr43698.c
359===================================================================
360--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr43698.c 2011-06-24 08:13:47.000000000 -0700
361+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr43698.c 2011-10-17 17:46:11.182697014 -0700
362@@ -1,5 +1,5 @@
363 /* { dg-do run } */
364-/* { dg-options "-Os -march=armv7-a" } */
365+/* { dg-options "-Os" } */
366 #include <stdint.h>
367 #include <stdlib.h>
368
369Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr44788.c
370===================================================================
371--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/pr44788.c 2011-06-24 08:13:47.000000000 -0700
372+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr44788.c 2011-10-17 17:46:11.182697014 -0700
373@@ -1,6 +1,6 @@
374 /* { dg-do compile } */
375 /* { dg-require-effective-target arm_thumb2_ok } */
376-/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */
377+/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -mfpu=vfp3 -mfloat-abi=softfp" } */
378
379 void joint_decode(float* mlt_buffer1, int t) {
380 int i;
381Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/sync-1.c
382===================================================================
383--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/sync-1.c 2011-06-24 08:13:47.000000000 -0700
384+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/sync-1.c 2011-10-17 17:46:11.182697014 -0700
385@@ -1,5 +1,6 @@
386-/* { dg-do run } */
387-/* { dg-options "-O2 -march=armv7-a" } */
388+
389+/* { dg-do run { target sync_int_long } } */
390+/* { dg-options "-O2" } */
391
392 volatile int mem;
393
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr47551.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr47551.patch
new file mode 100644
index 000000000..2c6bcda9b
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/pr47551.patch
@@ -0,0 +1,64 @@
1Upstream-Status:Backport
22011-02-02 Richard Sandiford <richard.sandiford@linaro.org>
3
4 gcc/
5 PR target/47551
6 * config/arm/arm.c (coproc_secondary_reload_class): Handle
7 structure modes. Don't check neon_vector_mem_operand for
8 vector or structure modes.
9
10 gcc/testsuite/
11 PR target/47551
12 * gcc.target/arm/neon-modes-2.c: New test.
13
14=== modified file 'gcc/config/arm/arm.c'
15--- old/gcc/config/arm/arm.c 2011-02-21 14:04:51 +0000
16+++ new/gcc/config/arm/arm.c 2011-03-02 11:38:43 +0000
17@@ -9139,11 +9139,14 @@
18 return GENERAL_REGS;
19 }
20
21+ /* The neon move patterns handle all legitimate vector and struct
22+ addresses. */
23 if (TARGET_NEON
24+ && MEM_P (x)
25 && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
26- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
27- && neon_vector_mem_operand (x, 0))
28- return NO_REGS;
29+ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
30+ || VALID_NEON_STRUCT_MODE (mode)))
31+ return NO_REGS;
32
33 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
34 return NO_REGS;
35
36=== added file 'gcc/testsuite/gcc.target/arm/neon-modes-2.c'
37--- old/gcc/testsuite/gcc.target/arm/neon-modes-2.c 1970-01-01 00:00:00 +0000
38+++ new/gcc/testsuite/gcc.target/arm/neon-modes-2.c 2011-02-02 10:02:45 +0000
39@@ -0,0 +1,24 @@
40+/* { dg-do compile } */
41+/* { dg-require-effective-target arm_neon_ok } */
42+/* { dg-options "-O1" } */
43+/* { dg-add-options arm_neon } */
44+
45+#include "arm_neon.h"
46+
47+#define SETUP(A) x##A = vld3_u32 (ptr + A * 0x20)
48+#define MODIFY(A) x##A = vld3_lane_u32 (ptr + A * 0x20 + 0x10, x##A, 1)
49+#define STORE(A) vst3_u32 (ptr + A * 0x20, x##A)
50+
51+#define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5)
52+
53+void
54+bar (uint32_t *ptr, int y)
55+{
56+ uint32x2x3_t MANY (SETUP);
57+ int *x = __builtin_alloca (y);
58+ int z[0x1000];
59+ foo (x, z);
60+ MANY (MODIFY);
61+ foo (x, z);
62+ MANY (STORE);
63+}
64
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/use-defaults.h-and-t-oe-in-B.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/use-defaults.h-and-t-oe-in-B.patch
new file mode 100644
index 000000000..b4351ee7e
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/use-defaults.h-and-t-oe-in-B.patch
@@ -0,0 +1,80 @@
1Upstream-Status: Pending
2
3Use the defaults.h in ${B} instead of ${S}, and t-oe in ${B}, so that
4the source can be shared between gcc-cross-initial,
5gcc-cross-intermediate, gcc-cross, gcc-runtime, and also the sdk build.
6---
7 gcc/Makefile.in | 2 +-
8 gcc/configure | 4 ++--
9 gcc/configure.ac | 4 ++--
10 gcc/mkconfig.sh | 4 ++--
11 4 files changed, 7 insertions(+), 7 deletions(-)
12
13diff --git a/gcc/Makefile.in b/gcc/Makefile.in
14index 7790915..3a0c34a 100644
15--- a/gcc/Makefile.in
16+++ b/gcc/Makefile.in
17@@ -463,7 +463,7 @@ LIMITS_H_TEST = [ -f $(SYSTEM_HEADER_DIR)/limits.h ]
18 TARGET_SYSTEM_ROOT = @TARGET_SYSTEM_ROOT@
19
20 xmake_file=@xmake_file@
21-tmake_file=@tmake_file@
22+tmake_file=@tmake_file@ ./t-oe
23 TM_ENDIAN_CONFIG=@TM_ENDIAN_CONFIG@
24 TM_MULTILIB_CONFIG=@TM_MULTILIB_CONFIG@
25 TM_MULTILIB_EXCEPTIONS_CONFIG=@TM_MULTILIB_EXCEPTIONS_CONFIG@
26diff --git a/gcc/configure b/gcc/configure
27index 82fa3e4..d4711b5 100755
28--- a/gcc/configure
29+++ b/gcc/configure
30@@ -11227,8 +11227,8 @@ for f in $tm_file; do
31 tm_include_list="${tm_include_list} $f"
32 ;;
33 defaults.h )
34- tm_file_list="${tm_file_list} \$(srcdir)/$f"
35- tm_include_list="${tm_include_list} $f"
36+ tm_file_list="${tm_file_list} ./$f"
37+ tm_include_list="${tm_include_list} ./$f"
38 ;;
39 * )
40 tm_file_list="${tm_file_list} \$(srcdir)/config/$f"
41diff --git a/gcc/configure.ac b/gcc/configure.ac
42index 844d8da..a960343 100644
43--- a/gcc/configure.ac
44+++ b/gcc/configure.ac
45@@ -1628,8 +1628,8 @@ for f in $tm_file; do
46 tm_include_list="${tm_include_list} $f"
47 ;;
48 defaults.h )
49- tm_file_list="${tm_file_list} \$(srcdir)/$f"
50- tm_include_list="${tm_include_list} $f"
51+ tm_file_list="${tm_file_list} ./$f"
52+ tm_include_list="${tm_include_list} ./$f"
53 ;;
54 * )
55 tm_file_list="${tm_file_list} \$(srcdir)/config/$f"
56diff --git a/gcc/mkconfig.sh b/gcc/mkconfig.sh
57index d56df8c..875d0f1 100644
58--- a/gcc/mkconfig.sh
59+++ b/gcc/mkconfig.sh
60@@ -77,7 +77,7 @@ if [ -n "$HEADERS" ]; then
61 if [ $# -ge 1 ]; then
62 echo '#ifdef IN_GCC' >> ${output}T
63 for file in "$@"; do
64- if test x"$file" = x"defaults.h"; then
65+ if test x"$file" = x"./defaults.h"; then
66 postpone_defaults_h="yes"
67 else
68 echo "# include \"$file\"" >> ${output}T
69@@ -103,7 +103,7 @@ esac
70
71 # If we postponed including defaults.h, add the #include now.
72 if test x"$postpone_defaults_h" = x"yes"; then
73- echo "# include \"defaults.h\"" >> ${output}T
74+ echo "# include \"./defaults.h\"" >> ${output}T
75 fi
76
77 # Add multiple inclusion protection guard, part two.
78--
791.7.1
80
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/zecke-xgcc-cpp.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/zecke-xgcc-cpp.patch
new file mode 100644
index 000000000..6192c4820
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/zecke-xgcc-cpp.patch
@@ -0,0 +1,30 @@
1Upstream-Status: Inappropriate [embedded specific]
2
3upstream: n/a
4comment: Use the preprocessor we have just compiled instead the one of
5the system. There might be incompabilities between us and them.
6
7Index: gcc-4.6.0/Makefile.in
8===================================================================
9--- gcc-4.6.0.orig/Makefile.in
10+++ gcc-4.6.0/Makefile.in
11@@ -270,6 +270,7 @@ BASE_TARGET_EXPORTS = \
12 AR="$(AR_FOR_TARGET)"; export AR; \
13 AS="$(COMPILER_AS_FOR_TARGET)"; export AS; \
14 CC="$(CC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export CC; \
15+ CPP="$(CC_FOR_TARGET) -E"; export CPP; \
16 CFLAGS="$(CFLAGS_FOR_TARGET)"; export CFLAGS; \
17 CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \
18 CPPFLAGS="$(CPPFLAGS_FOR_TARGET)"; export CPPFLAGS; \
19Index: gcc-4.6.0/Makefile.tpl
20===================================================================
21--- gcc-4.6.0.orig/Makefile.tpl
22+++ gcc-4.6.0/Makefile.tpl
23@@ -273,6 +273,7 @@ BASE_TARGET_EXPORTS = \
24 AR="$(AR_FOR_TARGET)"; export AR; \
25 AS="$(COMPILER_AS_FOR_TARGET)"; export AS; \
26 CC="$(CC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET) $$TFLAGS"; export CC; \
27+ CPP="$(CC_FOR_TARGET) -E"; export CPP; \
28 CFLAGS="$(CFLAGS_FOR_TARGET)"; export CFLAGS; \
29 CONFIG_SHELL="$(SHELL)"; export CONFIG_SHELL; \
30 CPPFLAGS="$(CPPFLAGS_FOR_TARGET)"; export CPPFLAGS; \
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc b/toolchain-layer/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
deleted file mode 100644
index bfff69fdf..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+++ /dev/null
@@ -1,101 +0,0 @@
1GCC-4_6-BRANCH-LINARO-BACKPORTS ?= " \
2file://linaro/gcc-4.6-linaro-r106720.patch \
3file://linaro/gcc-4.6-linaro-r106733.patch \
4file://linaro/gcc-4.6-linaro-r106737.patch \
5file://linaro/gcc-4.6-linaro-r106738.patch \
6file://linaro/gcc-4.6-linaro-r106739.patch \
7file://linaro/gcc-4.6-linaro-r106741.patch \
8file://linaro/gcc-4.6-linaro-r106742.patch \
9file://linaro/gcc-4.6-linaro-r106744.patch \
10file://linaro/gcc-4.6-linaro-r106746.patch \
11file://linaro/gcc-4.6-linaro-r106747.patch \
12file://linaro/gcc-4.6-linaro-r106750.patch \
13file://linaro/gcc-4.6-linaro-r106751.patch \
14file://linaro/gcc-4.6-linaro-r106753.patch \
15file://linaro/gcc-4.6-linaro-r106754.patch \
16file://linaro/gcc-4.6-linaro-r106755.patch \
17file://linaro/gcc-4.6-linaro-r106759.patch \
18file://linaro/gcc-4.6-linaro-r106762.patch \
19file://linaro/gcc-4.6-linaro-r106763.patch \
20file://linaro/gcc-4.6-linaro-r106764.patch \
21file://linaro/gcc-4.6-linaro-r106766.patch \
22file://linaro/gcc-4.6-linaro-r106768.patch \
23file://linaro/gcc-4.6-linaro-r106769.patch \
24file://linaro/gcc-4.6-linaro-r106770.patch \
25file://linaro/gcc-4.6-linaro-r106771.patch \
26file://linaro/gcc-4.6-linaro-r106772.patch \
27file://linaro/gcc-4.6-linaro-r106773.patch \
28file://linaro/gcc-4.6-linaro-r106775.patch \
29file://linaro/gcc-4.6-linaro-r106776.patch \
30file://linaro/gcc-4.6-linaro-r106777.patch \
31file://linaro/gcc-4.6-linaro-r106778.patch \
32file://linaro/gcc-4.6-linaro-r106781.patch \
33file://linaro/gcc-4.6-linaro-r106782.patch \
34file://linaro/gcc-4.6-linaro-r106783.patch \
35file://linaro/gcc-4.6-linaro-r106784.patch \
36file://linaro/gcc-4.6-linaro-r106785.patch \
37file://linaro/gcc-4.6-linaro-r106786.patch \
38file://linaro/gcc-4.6-linaro-r106787.patch \
39file://linaro/gcc-4.6-linaro-r106789.patch \
40file://linaro/gcc-4.6-linaro-r106792.patch \
41file://linaro/gcc-4.6-linaro-r106794.patch \
42file://linaro/gcc-4.6-linaro-r106796.patch \
43file://linaro/gcc-4.6-linaro-r106797.patch \
44file://linaro/gcc-4.6-linaro-r106798.patch \
45file://linaro/gcc-4.6-linaro-r106799.patch \
46file://linaro/gcc-4.6-linaro-r106800.patch \
47file://linaro/gcc-4.6-linaro-r106802.patch \
48file://linaro/gcc-4.6-linaro-r106803.patch \
49file://linaro/gcc-4.6-linaro-r106804.patch \
50file://linaro/gcc-4.6-linaro-r106805.patch \
51file://linaro/gcc-4.6-linaro-r106806.patch \
52file://linaro/gcc-4.6-linaro-r106807.patch \
53file://linaro/gcc-4.6-linaro-r106811.patch \
54file://linaro/gcc-4.6-linaro-r106814.patch \
55file://linaro/gcc-4.6-linaro-r106815.patch \
56file://linaro/gcc-4.6-linaro-r106816.patch \
57file://linaro/gcc-4.6-linaro-r106817.patch \
58file://linaro/gcc-4.6-linaro-r106818.patch \
59file://linaro/gcc-4.6-linaro-r106819.patch \
60file://linaro/gcc-4.6-linaro-r106820.patch \
61file://linaro/gcc-4.6-linaro-r106821.patch \
62file://linaro/gcc-4.6-linaro-r106825.patch \
63file://linaro/gcc-4.6-linaro-r106826.patch \
64file://linaro/gcc-4.6-linaro-r106827.patch \
65file://linaro/gcc-4.6-linaro-r106828.patch \
66file://linaro/gcc-4.6-linaro-r106829.patch \
67file://linaro/gcc-4.6-linaro-r106830.patch \
68file://linaro/gcc-4.6-linaro-r106831.patch \
69file://linaro/gcc-4.6-linaro-r106832.patch \
70file://linaro/gcc-4.6-linaro-r106833.patch \
71file://linaro/gcc-4.6-linaro-r106834.patch \
72file://linaro/gcc-4.6-linaro-r106836.patch \
73file://linaro/gcc-4.6-linaro-r106839.patch \
74file://linaro/gcc-4.6-linaro-r106840.patch \
75file://linaro/gcc-4.6-linaro-r106841.patch \
76file://linaro/gcc-4.6-linaro-r106842.patch \
77file://linaro/gcc-4.6-linaro-r106843.patch \
78file://linaro/gcc-4.6-linaro-r106844.patch \
79file://linaro/gcc-4.6-linaro-r106845.patch \
80file://linaro/gcc-4.6-linaro-r106846.patch \
81file://linaro/gcc-4.6-linaro-r106848.patch \
82file://linaro/gcc-4.6-linaro-r106853.patch \
83file://linaro/gcc-4.6-linaro-r106855.patch \
84file://linaro/gcc-4.6-linaro-r106860.patch \
85file://linaro/gcc-4.6-linaro-r106861.patch \
86file://linaro/gcc-4.6-linaro-r106862.patch \
87file://linaro/gcc-4.6-linaro-r106863.patch \
88file://linaro/gcc-4.6-linaro-r106864.patch \
89file://linaro/gcc-4.6-linaro-r106865.patch \
90file://linaro/gcc-4.6-linaro-r106869.patch \
91file://linaro/gcc-4.6-linaro-r106870.patch \
92file://linaro/gcc-4.6-linaro-r106872.patch \
93file://linaro/gcc-4.6-linaro-r106873.patch \
94file://linaro/gcc-4.6-linaro-r106874.patch \
95file://linaro/fix_linaro_106872.patch \
96file://linaro/gcc-4.6-linaro-r106876.patch \
97file://linaro/gcc-4.6-linaro-r106877.patch \
98file://linaro/gcc-4.6-linaro-r106878.patch \
99file://linaro/gcc-4.6-linaro-r106879.patch \
100file://linaro/gcc-4.6-linaro-r106882.patch \
101"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.6.bb b/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.6.bb
new file mode 100644
index 000000000..e0af4aa95
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.6.bb
@@ -0,0 +1,23 @@
1inherit cross-canadian
2
3require recipes-devtools/gcc/gcc-${PV}.inc
4require recipes-devtools/gcc/gcc-cross-canadian.inc
5require recipes-devtools/gcc/gcc-configure-sdk.inc
6require recipes-devtools/gcc/gcc-package-sdk.inc
7
8DEPENDS += "gmp-nativesdk mpfr-nativesdk libmpc-nativesdk elfutils-nativesdk"
9RDEPENDS_${PN} += "mpfr-nativesdk libmpc-nativesdk elfutils-nativesdk"
10
11SYSTEMHEADERS = "/usr/include"
12SYSTEMLIBS = "/lib/"
13SYSTEMLIBS1 = "/usr/lib/"
14
15EXTRA_OECONF += "--disable-libunwind-exceptions --disable-libssp \
16 --disable-libgomp --disable-libmudflap \
17 --with-mpfr=${STAGING_DIR_HOST}${layout_exec_prefix} \
18 --with-mpc=${STAGING_DIR_HOST}${layout_exec_prefix}"
19
20# to find libmpfr
21# export LD_LIBRARY_PATH = "{STAGING_DIR_HOST}${layout_exec_prefix}"
22
23PARALLEL_MAKE = ""
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.6.bbappend
deleted file mode 100644
index fc419b62b..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-cross-canadian_4.6.bbappend
+++ /dev/null
@@ -1,3 +0,0 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.6.bb b/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.6.bb
new file mode 100644
index 000000000..22d4b05c7
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.6.bb
@@ -0,0 +1,2 @@
1require recipes-devtools/gcc/gcc-cross_${PV}.bb
2require recipes-devtools/gcc/gcc-cross-initial.inc
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.6.bbappend
deleted file mode 100644
index fc419b62b..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-cross-initial_4.6.bbappend
+++ /dev/null
@@ -1,3 +0,0 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.6.bb b/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.6.bb
new file mode 100644
index 000000000..889228838
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.6.bb
@@ -0,0 +1,3 @@
1require recipes-devtools/gcc/gcc-cross_${PV}.bb
2require recipes-devtools/gcc/gcc-cross-intermediate.inc
3
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.6.bbappend
deleted file mode 100644
index fc419b62b..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-cross-intermediate_4.6.bbappend
+++ /dev/null
@@ -1,3 +0,0 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.6.bb b/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.6.bb
new file mode 100644
index 000000000..eb8896ca5
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.6.bb
@@ -0,0 +1,8 @@
1require recipes-devtools/gcc/gcc-${PV}.inc
2require recipes-devtools/gcc/gcc-cross4.inc
3
4EXTRA_OECONF += "--disable-libunwind-exceptions \
5 --with-mpfr=${STAGING_DIR_NATIVE}${prefix_native} \
6 --with-system-zlib "
7
8ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_DIR_TARGET}${target_includedir}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.6.bbappend
deleted file mode 100644
index fc419b62b..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-cross_4.6.bbappend
+++ /dev/null
@@ -1,3 +0,0 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bb b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bb
new file mode 100644
index 000000000..eff4df174
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bb
@@ -0,0 +1,2 @@
1require recipes-devtools/gcc/gcc-cross-initial_${PV}.bb
2require recipes-devtools/gcc/gcc-crosssdk-initial.inc
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bbappend
deleted file mode 100644
index fc419b62b..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-initial_4.6.bbappend
+++ /dev/null
@@ -1,3 +0,0 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.bb b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.bb
new file mode 100644
index 000000000..61a0dfbab
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.bb
@@ -0,0 +1,3 @@
1require recipes-devtools/gcc/gcc-cross-intermediate_${PV}.bb
2require recipes-devtools/gcc/gcc-crosssdk-intermediate.inc
3EXTRA_OECONF += " --with-headers=${STAGING_DIR_TCBOOTSTRAP}${SYSTEMHEADERS} "
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.bbappend
deleted file mode 100644
index fc419b62b..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk-intermediate_4.6.bbappend
+++ /dev/null
@@ -1,3 +0,0 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.6.bb b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.6.bb
new file mode 100644
index 000000000..0a9f98a1f
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.6.bb
@@ -0,0 +1,2 @@
1require recipes-devtools/gcc/gcc-cross_${PV}.bb
2require recipes-devtools/gcc/gcc-crosssdk.inc
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.6.bbappend
deleted file mode 100644
index fc419b62b..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-crosssdk_4.6.bbappend
+++ /dev/null
@@ -1,3 +0,0 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.6.bb b/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.6.bb
new file mode 100644
index 000000000..13431c8b6
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.6.bb
@@ -0,0 +1,8 @@
1require recipes-devtools/gcc/gcc-${PV}.inc
2require recipes-devtools/gcc/gcc-configure-runtime.inc
3require recipes-devtools/gcc/gcc-package-runtime.inc
4
5ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_INCDIR}"
6
7EXTRA_OECONF += "--disable-libunwind-exceptions"
8EXTRA_OECONF_append_linuxstdbase = " --enable-clocale=gnu"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.6.bbappend
deleted file mode 100644
index fc419b62b..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc-runtime_4.6.bbappend
+++ /dev/null
@@ -1,3 +0,0 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc_4.6.bb b/toolchain-layer/recipes-devtools/gcc/gcc_4.6.bb
new file mode 100644
index 000000000..97e6c324d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc_4.6.bb
@@ -0,0 +1,5 @@
1require recipes-devtools/gcc/gcc-${PV}.inc
2require recipes-devtools/gcc/gcc-configure-target.inc
3require recipes-devtools/gcc/gcc-package-target.inc
4
5ARCH_FLAGS_FOR_TARGET += "-isystem${STAGING_INCDIR}"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/gcc_4.6.bbappend
deleted file mode 100644
index fc419b62b..000000000
--- a/toolchain-layer/recipes-devtools/gcc/gcc_4.6.bbappend
+++ /dev/null
@@ -1,3 +0,0 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
diff --git a/toolchain-layer/recipes-devtools/gcc/libgcc_4.6.bb b/toolchain-layer/recipes-devtools/gcc/libgcc_4.6.bb
new file mode 100644
index 000000000..8529755bc
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/libgcc_4.6.bb
@@ -0,0 +1,71 @@
1require recipes-devtools/gcc/gcc-${PV}.inc
2
3INHIBIT_DEFAULT_DEPS = "1"
4
5DEPENDS = "virtual/${TARGET_PREFIX}gcc virtual/${TARGET_PREFIX}g++"
6
7PKGSUFFIX = ""
8PKGSUFFIX_virtclass-nativesdk = "-nativesdk"
9
10PACKAGES = "\
11 ${PN} \
12 ${PN}-dev \
13 ${PN}-dbg \
14 libgcov${PKGSUFFIX}-dev \
15 "
16
17FILES_${PN} = "${base_libdir}/libgcc*.so.*"
18FILES_${PN}-dev = " \
19 ${base_libdir}/libgcc*.so \
20 ${libdir}/${TARGET_SYS}/${BINV}/*crt* \
21 ${libdir}/${TARGET_SYS}/${BINV}/libgcc*"
22FILES_libgcov${PKGSUFFIX}-dev = " \
23 ${libdir}/${TARGET_SYS}/${BINV}/libgcov.a \
24 "
25FILES_${PN}-dbg += "${base_libdir}/.debug/"
26
27do_configure () {
28 target=`echo ${MULTIMACH_TARGET_SYS} | sed -e s#-nativesdk##`
29 install -d ${D}${base_libdir} ${D}${libdir}
30 cp -fpPR ${STAGING_INCDIR_NATIVE}/gcc-build-internal-$target/* ${B}
31 mkdir -p ${B}/${BPN}
32 cd ${B}/${BPN}
33 chmod a+x ${S}/${BPN}/configure
34 ${S}/${BPN}/configure ${CONFIGUREOPTS} ${EXTRA_OECONF}
35}
36
37do_compile () {
38 target=`echo ${TARGET_SYS} | sed -e s#-nativesdk##`
39 cd ${B}/${BPN}
40 oe_runmake MULTIBUILDTOP=${B}/$target/${BPN}/
41}
42
43do_install () {
44 target=`echo ${TARGET_SYS} | sed -e s#-nativesdk##`
45 cd ${B}/${BPN}
46 oe_runmake 'DESTDIR=${D}' MULTIBUILDTOP=${B}/$target/${BPN}/ install
47
48 # Move libgcc_s into /lib
49 mkdir -p ${D}${base_libdir}
50 if [ -f ${D}${libdir}/nof/libgcc_s.so ]; then
51 mv ${D}${libdir}/nof/libgcc* ${D}${base_libdir}
52 else
53 mv ${D}${libdir}/libgcc* ${D}${base_libdir} || true
54 fi
55
56 # install the runtime in /usr/lib/ not in /usr/lib/gcc on target
57 # so that cross-gcc can find it in the sysroot
58
59 mv ${D}${libdir}/gcc/* ${D}${libdir}
60 rm -rf ${D}${libdir}/gcc/
61}
62
63do_package_write_ipk[depends] += "virtual/${MLPREFIX}libc:do_package"
64do_package_write_deb[depends] += "virtual/${MLPREFIX}libc:do_package"
65do_package_write_rpm[depends] += "virtual/${MLPREFIX}libc:do_package"
66
67BBCLASSEXTEND = "nativesdk"
68
69INSANE_SKIP_${PN}-dev = "staticdev"
70INSANE_SKIP_libgcov${PKGSUFFIX}-dev = "staticdev"
71
diff --git a/toolchain-layer/recipes-devtools/gcc/libgcc_4.6.bbappend b/toolchain-layer/recipes-devtools/gcc/libgcc_4.6.bbappend
deleted file mode 100644
index fc419b62b..000000000
--- a/toolchain-layer/recipes-devtools/gcc/libgcc_4.6.bbappend
+++ /dev/null
@@ -1,3 +0,0 @@
1require recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
2require recipes-devtools/gcc/gcc-common-4.6.inc
3SRC_URI += "${GCC-4_6-BRANCH-LINARO-BACKPORTS}"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-30 23:42:00 +0000