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authorKhem Raj <raj.khem@gmail.com>2012-04-07 20:09:45 +0000
committerKoen Kooi <koen@dominion.thruhere.net>2012-04-08 07:48:16 +0200
commit9fb576a0d53d4bd511eee64f44d4ed187acdd83c (patch)
treec7775951f46dc17658768f7c04a301da43486401 /toolchain-layer/recipes-devtools
parenta6790d602eb91069b1f618697e66a38619bcd690 (diff)
downloadmeta-openembedded-9fb576a0d53d4bd511eee64f44d4ed187acdd83c.tar.gz
gcc-4.6: Update to 2012.03 linaro release
Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Diffstat (limited to 'toolchain-layer/recipes-devtools')
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106876.patch109
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106877.patch239
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106878.patch69
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106879.patch643
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106882.patch53
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc5
-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-common-4.6.inc2
7 files changed, 1119 insertions, 1 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106876.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106876.patch
new file mode 100644
index 000000000..048e85b4d
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106876.patch
@@ -0,0 +1,109 @@
12012-03-06 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 LP:942307
4 gcc/
5 PR target/50305
6 * config/arm/arm.c (arm_legitimize_reload_address): Recognize
7 output of a previous pass through legitimize_reload_address.
8 Do not attempt to optimize addresses if the base register is
9 equivalent to a constant.
10 gcc/testsuite/
11 PR target/50305
12 * gcc.target/arm/pr50305.c: New test.
13
14=== modified file 'gcc/config/arm/arm.c'
15--- old/gcc/config/arm/arm.c 2012-03-02 13:53:14 +0000
16+++ new/gcc/config/arm/arm.c 2012-03-06 11:01:55 +0000
17@@ -6632,9 +6632,26 @@
18 int opnum, int type,
19 int ind_levels ATTRIBUTE_UNUSED)
20 {
21+ /* We must recognize output that we have already generated ourselves. */
22+ if (GET_CODE (*p) == PLUS
23+ && GET_CODE (XEXP (*p, 0)) == PLUS
24+ && GET_CODE (XEXP (XEXP (*p, 0), 0)) == REG
25+ && GET_CODE (XEXP (XEXP (*p, 0), 1)) == CONST_INT
26+ && GET_CODE (XEXP (*p, 1)) == CONST_INT)
27+ {
28+ push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
29+ MODE_BASE_REG_CLASS (mode), GET_MODE (*p),
30+ VOIDmode, 0, 0, opnum, (enum reload_type) type);
31+ return true;
32+ }
33+
34 if (GET_CODE (*p) == PLUS
35 && GET_CODE (XEXP (*p, 0)) == REG
36 && ARM_REGNO_OK_FOR_BASE_P (REGNO (XEXP (*p, 0)))
37+ /* If the base register is equivalent to a constant, let the generic
38+ code handle it. Otherwise we will run into problems if a future
39+ reload pass decides to rematerialize the constant. */
40+ && !reg_equiv_constant [ORIGINAL_REGNO (XEXP (*p, 0))]
41 && GET_CODE (XEXP (*p, 1)) == CONST_INT)
42 {
43 HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));
44
45=== added file 'gcc/testsuite/gcc.target/arm/pr50305.c'
46--- old/gcc/testsuite/gcc.target/arm/pr50305.c 1970-01-01 00:00:00 +0000
47+++ new/gcc/testsuite/gcc.target/arm/pr50305.c 2012-03-01 13:07:48 +0000
48@@ -0,0 +1,60 @@
49+/* { dg-do compile } */
50+/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */
51+/* { dg-options "-O2 -fno-omit-frame-pointer -marm -march=armv7-a -mfpu=vfp3" } */
52+
53+struct event {
54+ unsigned long long id;
55+ unsigned int flag;
56+};
57+
58+void dummy(void)
59+{
60+ /* This is here to ensure that the offset of perf_event_id below
61+ relative to the LANCHOR symbol exceeds the allowed displacement. */
62+ static int __warned[300];
63+ __warned[0] = 1;
64+}
65+
66+extern void *kmem_cache_alloc_trace (void *cachep);
67+extern void *cs_cachep;
68+extern int nr_cpu_ids;
69+
70+struct event *
71+event_alloc (int cpu)
72+{
73+ static unsigned long long __attribute__((aligned(8))) perf_event_id;
74+ struct event *event;
75+ unsigned long long result;
76+ unsigned long tmp;
77+
78+ if (cpu >= nr_cpu_ids)
79+ return 0;
80+
81+ event = kmem_cache_alloc_trace (cs_cachep);
82+
83+ __asm__ __volatile__ ("dmb" : : : "memory");
84+
85+ __asm__ __volatile__("@ atomic64_add_return\n"
86+"1: ldrexd %0, %H0, [%3]\n"
87+" adds %0, %0, %4\n"
88+" adc %H0, %H0, %H4\n"
89+" strexd %1, %0, %H0, [%3]\n"
90+" teq %1, #0\n"
91+" bne 1b"
92+ : "=&r" (result), "=&r" (tmp), "+Qo" (perf_event_id)
93+ : "r" (&perf_event_id), "r" (1LL)
94+ : "cc");
95+
96+ __asm__ __volatile__ ("dmb" : : : "memory");
97+
98+ event->id = result;
99+
100+ if (cpu)
101+ event->flag = 1;
102+
103+ for (cpu = 0; cpu < nr_cpu_ids; cpu++)
104+ kmem_cache_alloc_trace (cs_cachep);
105+
106+ return event;
107+}
108+
109
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106877.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106877.patch
new file mode 100644
index 000000000..b83b957c6
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106877.patch
@@ -0,0 +1,239 @@
12012-03-06 Ulrich Weigand <ulrich.weigand@linaro.org>
2
3 Backport from mainline:
4
5 gcc/
6 * config/arm/arm.c (arm_sat_operator_match): New function.
7 * config/arm/arm-protos.h (arm_sat_operator_match): Add prototype.
8 * config/arm/arm.md ("insn" attribute): Add "sat" value.
9 ("SAT", "SATrev"): New code iterators.
10 ("SATlo", "SAThi"): New code iterator attributes.
11 ("*satsi_<SAT:code>"): New pattern.
12 ("*satsi_<SAT:code>_shift"): Likewise.
13 * config/arm/predicates.md (sat_shift_operator): New.
14
15 gcc/testsuite/
16 * gcc.target/arm/sat-1.c: New test.
17
18=== modified file 'gcc/config/arm/arm-protos.h'
19--- old/gcc/config/arm/arm-protos.h 2012-02-22 13:31:54 +0000
20+++ new/gcc/config/arm/arm-protos.h 2012-02-29 14:29:56 +0000
21@@ -104,6 +104,7 @@
22 extern int symbol_mentioned_p (rtx);
23 extern int label_mentioned_p (rtx);
24 extern RTX_CODE minmax_code (rtx);
25+extern bool arm_sat_operator_match (rtx, rtx, int *, bool *);
26 extern int adjacent_mem_locations (rtx, rtx);
27 extern bool gen_ldm_seq (rtx *, int, bool);
28 extern bool gen_stm_seq (rtx *, int);
29
30=== modified file 'gcc/config/arm/arm.c'
31--- old/gcc/config/arm/arm.c 2012-03-06 11:01:55 +0000
32+++ new/gcc/config/arm/arm.c 2012-03-06 13:24:25 +0000
33@@ -9978,6 +9978,42 @@
34 }
35 }
36
37+/* Match pair of min/max operators that can be implemented via usat/ssat. */
38+
39+bool
40+arm_sat_operator_match (rtx lo_bound, rtx hi_bound,
41+ int *mask, bool *signed_sat)
42+{
43+ /* The high bound must be a power of two minus one. */
44+ int log = exact_log2 (INTVAL (hi_bound) + 1);
45+ if (log == -1)
46+ return false;
47+
48+ /* The low bound is either zero (for usat) or one less than the
49+ negation of the high bound (for ssat). */
50+ if (INTVAL (lo_bound) == 0)
51+ {
52+ if (mask)
53+ *mask = log;
54+ if (signed_sat)
55+ *signed_sat = false;
56+
57+ return true;
58+ }
59+
60+ if (INTVAL (lo_bound) == -INTVAL (hi_bound) - 1)
61+ {
62+ if (mask)
63+ *mask = log + 1;
64+ if (signed_sat)
65+ *signed_sat = true;
66+
67+ return true;
68+ }
69+
70+ return false;
71+}
72+
73 /* Return 1 if memory locations are adjacent. */
74 int
75 adjacent_mem_locations (rtx a, rtx b)
76
77=== modified file 'gcc/config/arm/arm.md'
78--- old/gcc/config/arm/arm.md 2012-03-02 13:53:14 +0000
79+++ new/gcc/config/arm/arm.md 2012-03-06 13:24:25 +0000
80@@ -286,7 +286,7 @@
81 ;; scheduling information.
82
83 (define_attr "insn"
84- "mov,mvn,smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,umaal,smlald,smlsld,clz,mrs,msr,xtab,sdiv,udiv,other"
85+ "mov,mvn,smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,umaal,smlald,smlsld,clz,mrs,msr,xtab,sdiv,udiv,sat,other"
86 (const_string "other"))
87
88 ; TYPE attribute is used to detect floating point instructions which, if
89@@ -3424,6 +3424,60 @@
90 (const_int 12)))]
91 )
92
93+(define_code_iterator SAT [smin smax])
94+(define_code_iterator SATrev [smin smax])
95+(define_code_attr SATlo [(smin "1") (smax "2")])
96+(define_code_attr SAThi [(smin "2") (smax "1")])
97+
98+(define_insn "*satsi_<SAT:code>"
99+ [(set (match_operand:SI 0 "s_register_operand" "=r")
100+ (SAT:SI (SATrev:SI (match_operand:SI 3 "s_register_operand" "r")
101+ (match_operand:SI 1 "const_int_operand" "i"))
102+ (match_operand:SI 2 "const_int_operand" "i")))]
103+ "TARGET_32BIT && arm_arch6 && <SAT:CODE> != <SATrev:CODE>
104+ && arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>], NULL, NULL)"
105+{
106+ int mask;
107+ bool signed_sat;
108+ if (!arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>],
109+ &mask, &signed_sat))
110+ gcc_unreachable ();
111+
112+ operands[1] = GEN_INT (mask);
113+ if (signed_sat)
114+ return "ssat%?\t%0, %1, %3";
115+ else
116+ return "usat%?\t%0, %1, %3";
117+}
118+ [(set_attr "predicable" "yes")
119+ (set_attr "insn" "sat")])
120+
121+(define_insn "*satsi_<SAT:code>_shift"
122+ [(set (match_operand:SI 0 "s_register_operand" "=r")
123+ (SAT:SI (SATrev:SI (match_operator:SI 3 "sat_shift_operator"
124+ [(match_operand:SI 4 "s_register_operand" "r")
125+ (match_operand:SI 5 "const_int_operand" "i")])
126+ (match_operand:SI 1 "const_int_operand" "i"))
127+ (match_operand:SI 2 "const_int_operand" "i")))]
128+ "TARGET_32BIT && arm_arch6 && <SAT:CODE> != <SATrev:CODE>
129+ && arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>], NULL, NULL)"
130+{
131+ int mask;
132+ bool signed_sat;
133+ if (!arm_sat_operator_match (operands[<SAT:SATlo>], operands[<SAT:SAThi>],
134+ &mask, &signed_sat))
135+ gcc_unreachable ();
136+
137+ operands[1] = GEN_INT (mask);
138+ if (signed_sat)
139+ return "ssat%?\t%0, %1, %4%S3";
140+ else
141+ return "usat%?\t%0, %1, %4%S3";
142+}
143+ [(set_attr "predicable" "yes")
144+ (set_attr "insn" "sat")
145+ (set_attr "shift" "3")
146+ (set_attr "type" "alu_shift")])
147
148 ;; Shift and rotation insns
149
150
151=== modified file 'gcc/config/arm/predicates.md'
152--- old/gcc/config/arm/predicates.md 2012-02-22 13:31:54 +0000
153+++ new/gcc/config/arm/predicates.md 2012-02-29 14:29:56 +0000
154@@ -241,6 +241,15 @@
155 || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
156 (match_test "mode == GET_MODE (op)")))
157
158+;; True for shift operators which can be used with saturation instructions.
159+(define_special_predicate "sat_shift_operator"
160+ (and (ior (and (match_code "mult")
161+ (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
162+ (and (match_code "ashift,ashiftrt")
163+ (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
164+ && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
165+ (match_test "mode == GET_MODE (op)")))
166+
167 ;; True for MULT, to identify which variant of shift_operator is in use.
168 (define_special_predicate "mult_operator"
169 (match_code "mult"))
170
171=== added file 'gcc/testsuite/gcc.target/arm/sat-1.c'
172--- old/gcc/testsuite/gcc.target/arm/sat-1.c 1970-01-01 00:00:00 +0000
173+++ new/gcc/testsuite/gcc.target/arm/sat-1.c 2012-02-29 14:29:56 +0000
174@@ -0,0 +1,64 @@
175+/* { dg-do compile } */
176+/* { dg-require-effective-target arm_arm_ok } */
177+/* { dg-require-effective-target arm_arch_v6_ok } */
178+/* { dg-options "-O2 -marm" } */
179+/* { dg-add-options arm_arch_v6 } */
180+
181+
182+static inline int sat1 (int a, int amin, int amax)
183+{
184+ if (a < amin) return amin;
185+ else if (a > amax) return amax;
186+ else return a;
187+}
188+
189+static inline int sat2 (int a, int amin, int amax)
190+{
191+ if (a > amax) return amax;
192+ else if (a < amin) return amin;
193+ else return a;
194+}
195+
196+int u1 (int x)
197+{
198+ return sat1 (x, 0, 63);
199+}
200+
201+int us1 (int x)
202+{
203+ return sat1 (x >> 5, 0, 63);
204+}
205+
206+int s1 (int x)
207+{
208+ return sat1 (x, -64, 63);
209+}
210+
211+int ss1 (int x)
212+{
213+ return sat1 (x >> 5, -64, 63);
214+}
215+
216+int u2 (int x)
217+{
218+ return sat2 (x, 0, 63);
219+}
220+
221+int us2 (int x)
222+{
223+ return sat2 (x >> 5, 0, 63);
224+}
225+
226+int s2 (int x)
227+{
228+ return sat2 (x, -64, 63);
229+}
230+
231+int ss2 (int x)
232+{
233+ return sat2 (x >> 5, -64, 63);
234+}
235+
236+/* { dg-final { scan-assembler-times "usat" 4 } } */
237+/* { dg-final { scan-assembler-times "ssat" 4 } } */
238+
239
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106878.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106878.patch
new file mode 100644
index 000000000..fc1633d36
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106878.patch
@@ -0,0 +1,69 @@
12012-03-08 Michael Hope <michael.hope@linaro.org>
2
3 Backport proposed patch:
4
5 gcc/
6 2012-01-31 Richard Henderson <rth@redhat.com>
7
8 * longlong.h [arm] (umul_ppmm): Use umull. Enable for thumb2.
9 [arm] (count_trailing_zeros): Use __builtin_ctz.
10
11=== modified file 'gcc/longlong.h'
12--- old/gcc/longlong.h 2011-10-04 07:28:50 +0000
13+++ new/gcc/longlong.h 2012-02-22 01:51:14 +0000
14@@ -203,7 +203,7 @@
15 UDItype __umulsidi3 (USItype, USItype);
16 #endif
17
18-#if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
19+#if defined (__arm__) && (defined (__thumb2__) || !defined (__thumb__)) && W_TYPE_SIZE == 32
20 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
21 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
22 : "=r" ((USItype) (sh)), \
23@@ -220,9 +220,12 @@
24 "rI" ((USItype) (bh)), \
25 "r" ((USItype) (al)), \
26 "rI" ((USItype) (bl)) __CLOBBER_CC)
27-#define umul_ppmm(xh, xl, a, b) \
28-{register USItype __t0, __t1, __t2; \
29- __asm__ ("%@ Inlined umul_ppmm\n" \
30+# if defined(__ARM_ARCH_2__) || defined(__ARM_ARCH_2A__) \
31+ || defined(__ARM_ARCH_3__)
32+# define umul_ppmm(xh, xl, a, b) \
33+ do { \
34+ register USItype __t0, __t1, __t2; \
35+ __asm__ ("%@ Inlined umul_ppmm\n" \
36 " mov %2, %5, lsr #16\n" \
37 " mov %0, %6, lsr #16\n" \
38 " bic %3, %5, %2, lsl #16\n" \
39@@ -239,14 +242,26 @@
40 "=r" ((USItype) (xl)), \
41 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
42 : "r" ((USItype) (a)), \
43- "r" ((USItype) (b)) __CLOBBER_CC );}
44-#define UMUL_TIME 20
45-#define UDIV_TIME 100
46+ "r" ((USItype) (b)) __CLOBBER_CC ); \
47+ } while (0)
48+# define UMUL_TIME 20
49+# else
50+# define umul_ppmm(xh, xl, a, b) \
51+ do { \
52+ /* Generate umull, under compiler control. */ \
53+ register UDItype __t0 = (UDItype)(USItype)(a) * (USItype)(b); \
54+ (xl) = (USItype)__t0; \
55+ (xh) = (USItype)(__t0 >> 32); \
56+ } while (0)
57+# define UMUL_TIME 3
58+# endif
59+# define UDIV_TIME 100
60 #endif /* __arm__ */
61
62 #if defined(__arm__)
63 /* Let gcc decide how best to implement count_leading_zeros. */
64 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
65+#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X))
66 #define COUNT_LEADING_ZEROS_0 32
67 #endif
68
69
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106879.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106879.patch
new file mode 100644
index 000000000..a97a27b60
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106879.patch
@@ -0,0 +1,643 @@
12012-03-08 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline.
4 2012-02-28 Richard Earnshaw <rearnsha@arm.com>
5
6 * arm.c (aapcs_vfp_is_call_or_return_candidate): Only use the machine
7 mode if there is no type information available.
8
9 2012-02-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
10
11 * gcc.target/arm/aapcs/vfp1.c (dg_do run): Run on all eabi variants.
12 * gcc.target/arm/aapcs/vfp2.c: Likewise.
13 * gcc.target/arm/aapcs/vfp3.c: Likewise.
14 * gcc.target/arm/aapcs/vfp4.c: Likewise.
15 * gcc.target/arm/aapcs/vfp5.c: Likewise.
16 * gcc.target/arm/aapcs/vfp6.c: Likewise.
17 * gcc.target/arm/aapcs/vfp7.c: Likewise.
18 * gcc.target/arm/aapcs/vfp8.c: Likewise.
19 * gcc.target/arm/aapcs/vfp9.c: Likewise.
20 * gcc.target/arm/aapcs/vfp10.c: Likewise.
21 * gcc.target/arm/aapcs/vfp11.c: Likewise.
22 * gcc.target/arm/aapcs/vfp12.c: Likewise.
23 * gcc.target/arm/aapcs/vfp13.c: Likewise.
24 * gcc.target/arm/aapcs/vfp14.c: Likewise.
25 * gcc.target/arm/aapcs/vfp15.c: Likewise.
26 * gcc.target/arm/aapcs/vfp16.c: Likewise.
27 * gcc.target/arm/aapcs/vfp17.c: Likewise.
28 * gcc.target/arm/neon-constants.h: New file.
29 * gcc.target/arm/aapcs/neon-constants.h: New file.
30 * gcc.target/arm/aapcs/neon-vect1.c: New test.
31 * gcc.target/arm/aapcs/neon-vect2.c: New test.
32 * gcc.target/arm/aapcs/neon-vect3.c: New test.
33 * gcc.target/arm/aapcs/neon-vect4.c: New test.
34 * gcc.target/arm/aapcs/neon-vect5.c: New test.
35 * gcc.target/arm/aapcs/neon-vect6.c: New test.
36 * gcc.target/arm/aapcs/neon-vect7.c: New test.
37 * gcc.target/arm/aapcs/neon-vect8.c: New test.
38
39=== modified file 'gcc/config/arm/arm.c'
40--- old/gcc/config/arm/arm.c 2012-03-06 13:24:25 +0000
41+++ new/gcc/config/arm/arm.c 2012-03-08 15:46:42 +0000
42@@ -4331,6 +4331,11 @@
43 (TARGET_VFP_DOUBLE || !is_double));
44 }
45
46+/* Return true if an argument whose type is TYPE, or mode is MODE, is
47+ suitable for passing or returning in VFP registers for the PCS
48+ variant selected. If it is, then *BASE_MODE is updated to contain
49+ a machine mode describing each element of the argument's type and
50+ *COUNT to hold the number of such elements. */
51 static bool
52 aapcs_vfp_is_call_or_return_candidate (enum arm_pcs pcs_variant,
53 enum machine_mode mode, const_tree type,
54@@ -4338,9 +4343,20 @@
55 {
56 enum machine_mode new_mode = VOIDmode;
57
58- if (GET_MODE_CLASS (mode) == MODE_FLOAT
59- || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
60- || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
61+ /* If we have the type information, prefer that to working things
62+ out from the mode. */
63+ if (type)
64+ {
65+ int ag_count = aapcs_vfp_sub_candidate (type, &new_mode);
66+
67+ if (ag_count > 0 && ag_count <= 4)
68+ *count = ag_count;
69+ else
70+ return false;
71+ }
72+ else if (GET_MODE_CLASS (mode) == MODE_FLOAT
73+ || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
74+ || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
75 {
76 *count = 1;
77 new_mode = mode;
78@@ -4350,15 +4366,6 @@
79 *count = 2;
80 new_mode = (mode == DCmode ? DFmode : SFmode);
81 }
82- else if (type && (mode == BLKmode || TREE_CODE (type) == VECTOR_TYPE))
83- {
84- int ag_count = aapcs_vfp_sub_candidate (type, &new_mode);
85-
86- if (ag_count > 0 && ag_count <= 4)
87- *count = ag_count;
88- else
89- return false;
90- }
91 else
92 return false;
93
94
95=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/abitest.h'
96--- old/gcc/testsuite/gcc.target/arm/aapcs/abitest.h 2009-08-06 17:15:19 +0000
97+++ new/gcc/testsuite/gcc.target/arm/aapcs/abitest.h 2012-03-01 09:33:24 +0000
98@@ -1,3 +1,4 @@
99+
100 #define IN_FRAMEWORK
101
102 #ifdef VFP
103@@ -10,6 +11,13 @@
104 #define D6 48
105 #define D7 56
106
107+#ifdef NEON
108+#define Q0 D0
109+#define Q1 D2
110+#define Q2 D4
111+#define Q3 D6
112+#endif
113+
114 #define S0 64
115 #define S1 68
116 #define S2 72
117@@ -27,24 +35,19 @@
118 #define S14 120
119 #define S15 124
120
121-#define R0 128
122-#define R1 132
123-#define R2 136
124-#define R3 140
125-
126-#define STACK 144
127-
128+#define CORE_REG_START 128
129 #else
130-
131-#define R0 0
132-#define R1 4
133-#define R2 8
134-#define R3 12
135-
136-#define STACK 16
137-
138+#define CORE_REG_START 0
139 #endif
140
141+#define R0 CORE_REG_START
142+#define R1 (R0 + 4)
143+#define R2 (R1 + 4)
144+#define R3 (R2 + 4)
145+#define STACK (R3 + 4)
146+
147+
148+
149 extern void abort (void);
150
151 __attribute__((naked)) void dumpregs () __asm("myfunc");
152
153=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h'
154--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h 1970-01-01 00:00:00 +0000
155+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h 2012-03-01 09:33:24 +0000
156@@ -0,0 +1,33 @@
157+
158+
159+#include "arm_neon.h"
160+
161+const int32x4_t i32x4_constvec1 = { 1101, 1102, 1103, 1104};
162+const int32x4_t i32x4_constvec2 = { 2101, 2102, 2103, 2104};
163+
164+#define ELEM(INDEX) .val[INDEX]
165+
166+const int32x4x2_t i32x4x2_constvec1 = {ELEM(0) = {0xaddebccb,11,12,13},
167+ ELEM(1) = {14, 15, 16, 17} };
168+
169+const int32x4x2_t i32x4x2_constvec2 = { ELEM(0) = {0xaadebcca,11,12,13},
170+ ELEM(1) = {140, 15, 16, 17}};
171+
172+const int32x4x3_t i32x4x3_constvec1 = { ELEM(0) = {0xabbccdde,8, 9, 10},
173+ ELEM(1) = {0xabcccdde, 26, 27, 28},
174+ ELEM(2) = {0xaccccddf, 29, 30, 31}};
175+
176+const int32x4x3_t i32x4x3_constvec2 = { ELEM(0) = {0xbccccdd0,8, 9, 10},
177+ ELEM(1) = {0xbdfe1000, 26, 27, 28},
178+ ELEM(2) = {0xaccccddf, 29, 30, 31}};
179+const float32x4x2_t f32x4x2_constvec1 =
180+ { ELEM(0) = { 7.101f, 0.201f, 0.301f, 0.401f} ,
181+ ELEM(1) = { 8.101f, 0.501f, 0.601f, 0.701f} };
182+
183+const float32x4x2_t f32x4x2_constvec2 =
184+ { ELEM(0) = { 11.99f , 11.21f, 1.27f, 8.74f},
185+ ELEM(1) = { 13.45f , 1.23f ,1.24f, 1.26f}};
186+
187+const int32x2_t i32x2_constvec1 = { 1283, 1345 };
188+const int32x2x2_t i32x2x2_constvec1 = { ELEM(0) = { 0xabcdefab, 32 },
189+ ELEM(1) = { 0xabcdefbc, 33 }};
190
191=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c'
192--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c 1970-01-01 00:00:00 +0000
193+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c 2012-03-01 09:33:24 +0000
194@@ -0,0 +1,27 @@
195+/* Test AAPCS layout (VFP variant for Neon types) */
196+
197+/* { dg-do run { target arm*-*-*eabi* } } */
198+/* { dg-require-effective-target arm_hard_vfp_ok } */
199+/* { dg-require-effective-target arm_neon_ok } */
200+/* { dg-require-effective-target arm32 } */
201+/* { dg-add-options arm_neon } */
202+
203+
204+#ifndef IN_FRAMEWORK
205+#define VFP
206+#define NEON
207+#define TESTFILE "neon-vect1.c"
208+#include "neon-constants.h"
209+
210+
211+#include "abitest.h"
212+#else
213+
214+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
215+ARG(float, 3.0f, S4) /* D2, Q1 */
216+ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */
217+ARG(double, 12.0, D3) /* Backfill this particular argument. */
218+ARG(int32x4x2_t, i32x4x2_constvec2, STACK)
219+ARG(float, 5.0f, STACK+sizeof(int32x4x2_t)) /* No backfill allowed. */
220+LAST_ARG(int, 3, R0)
221+#endif
222
223=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c'
224--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c 1970-01-01 00:00:00 +0000
225+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c 2012-03-01 09:33:24 +0000
226@@ -0,0 +1,23 @@
227+/* Test AAPCS layout (VFP variant for Neon types) */
228+
229+/* { dg-do run { target arm*-*-*eabi* } } */
230+/* { dg-require-effective-target arm_hard_vfp_ok } */
231+/* { dg-require-effective-target arm_neon_ok } */
232+/* { dg-require-effective-target arm32 } */
233+/* { dg-add-options arm_neon } */
234+
235+
236+#ifndef IN_FRAMEWORK
237+#define VFP
238+#define NEON
239+#define TESTFILE "neon-vect2.c"
240+#include "neon-constants.h"
241+
242+
243+#include "abitest.h"
244+#else
245+
246+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1. */
247+ARG(float, 3.0f, S4) /* D2, Q1 occupied. */
248+LAST_ARG(int, 3, R0)
249+#endif
250
251=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c'
252--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c 1970-01-01 00:00:00 +0000
253+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c 2012-03-01 09:33:24 +0000
254@@ -0,0 +1,26 @@
255+/* Test AAPCS layout (VFP variant for Neon types) */
256+
257+/* { dg-do run { target arm*-*-*eabi* } } */
258+/* { dg-require-effective-target arm_hard_vfp_ok } */
259+/* { dg-require-effective-target arm_neon_ok } */
260+/* { dg-require-effective-target arm32 } */
261+/* { dg-add-options arm_neon } */
262+
263+
264+#ifndef IN_FRAMEWORK
265+#define VFP
266+#define NEON
267+#define TESTFILE "neon-vect3.c"
268+#include "neon-constants.h"
269+
270+
271+#include "abitest.h"
272+#else
273+
274+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
275+ARG(float, 3.0f, S4) /* D2, Q1 */
276+ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */
277+ARG(int32x4x2_t, i32x4x2_constvec2, STACK)
278+ARG(double, 11.0, STACK+sizeof(int32x4x2_t)) /* No backfill in D3. */
279+LAST_ARG(int, 3, R0)
280+#endif
281
282=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c'
283--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c 1970-01-01 00:00:00 +0000
284+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c 2012-03-01 09:33:24 +0000
285@@ -0,0 +1,27 @@
286+/* Test AAPCS layout (VFP variant for Neon types) */
287+
288+/* { dg-do run { target arm*-*-*eabi* } } */
289+/* { dg-require-effective-target arm_hard_vfp_ok } */
290+/* { dg-require-effective-target arm_neon_ok } */
291+/* { dg-require-effective-target arm32 } */
292+/* { dg-add-options arm_neon } */
293+
294+
295+#ifndef IN_FRAMEWORK
296+#define VFP
297+#define NEON
298+#define TESTFILE "neon-vect4.c"
299+#include "neon-constants.h"
300+
301+
302+#include "abitest.h"
303+#else
304+
305+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
306+ARG(float, 3.0f, S4) /* D2, Q1 */
307+ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */
308+ARG(double, 12.0, D3) /* Backfill this particular argument. */
309+ARG(float, 5.0f, S5) /* Backfill in S5. */
310+ARG(int32x4x2_t, i32x4x2_constvec2, STACK)
311+LAST_ARG(int, 3, R0)
312+#endif
313
314=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c'
315--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c 1970-01-01 00:00:00 +0000
316+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c 2012-03-01 09:33:24 +0000
317@@ -0,0 +1,28 @@
318+/* Test AAPCS layout (VFP variant for Neon types) */
319+
320+/* { dg-do run { target arm*-*-*eabi* } } */
321+/* { dg-require-effective-target arm_hard_vfp_ok } */
322+/* { dg-require-effective-target arm_neon_ok } */
323+/* { dg-require-effective-target arm32 } */
324+/* { dg-add-options arm_neon } */
325+
326+
327+#ifndef IN_FRAMEWORK
328+#define VFP
329+#define NEON
330+#define TESTFILE "neon-vect5.c"
331+#include "neon-constants.h"
332+
333+
334+#include "abitest.h"
335+#else
336+
337+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
338+ARG(float, 3.0f, S4) /* D2, Q1 */
339+ARG(float32x4x2_t, f32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */
340+ARG(double, 12.0, D3) /* Backfill this particular argument. */
341+ARG(int32x4x2_t, i32x4x2_constvec2, STACK)
342+ARG(float, 5.0f, STACK+sizeof(int32x4x2_t)) /* No backfill allowed. */
343+LAST_ARG(int, 3, R0)
344+
345+#endif
346
347=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c'
348--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c 1970-01-01 00:00:00 +0000
349+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c 2012-03-01 09:33:24 +0000
350@@ -0,0 +1,24 @@
351+/* Test AAPCS layout (VFP variant for Neon types) */
352+
353+/* { dg-do run { target arm*-*-*eabi* } } */
354+/* { dg-require-effective-target arm_hard_vfp_ok } */
355+/* { dg-require-effective-target arm_neon_ok } */
356+/* { dg-require-effective-target arm32 } */
357+/* { dg-add-options arm_neon } */
358+
359+
360+#ifndef IN_FRAMEWORK
361+#define VFP
362+#define NEON
363+#define TESTFILE "neon-vect6.c"
364+#include "neon-constants.h"
365+
366+
367+#include "abitest.h"
368+#else
369+
370+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
371+ARG(int32x4x3_t, i32x4x3_constvec1, Q1) /* Q1, Q2, Q3 */
372+ARG(int32x4x3_t, i32x4x3_constvec2, STACK)
373+LAST_ARG(int, 3, R0)
374+#endif
375
376=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c'
377--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c 1970-01-01 00:00:00 +0000
378+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c 2012-03-01 09:33:24 +0000
379@@ -0,0 +1,27 @@
380+/* Test AAPCS layout (VFP variant for Neon types) */
381+
382+/* { dg-do run { target arm*-*-*eabi* } } */
383+/* { dg-require-effective-target arm_hard_vfp_ok } */
384+/* { dg-require-effective-target arm_neon_ok } */
385+/* { dg-require-effective-target arm32 } */
386+/* { dg-add-options arm_neon } */
387+
388+
389+#ifndef IN_FRAMEWORK
390+#define VFP
391+#define NEON
392+#define TESTFILE "neon-vect7.c"
393+#include "neon-constants.h"
394+
395+
396+#include "abitest.h"
397+#else
398+
399+ARG(float, 24.3f, S0) /* S0 , D0, Q0 */
400+ARG(int32x4x3_t, i32x4x3_constvec1, Q1) /* Q1, Q2, Q3 */
401+ARG(double, 25.6, D1)
402+ARG(float, 12.67f, S1)
403+ARG(int32x4x3_t, i32x4x3_constvec2, STACK)
404+ARG(double, 2.47, STACK+sizeof(int32x4x3_t))
405+LAST_ARG(int, 3, R0)
406+#endif
407
408=== added file 'gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c'
409--- old/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c 1970-01-01 00:00:00 +0000
410+++ new/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c 2012-03-01 09:33:24 +0000
411@@ -0,0 +1,27 @@
412+/* Test AAPCS layout (VFP variant for Neon types) */
413+
414+/* { dg-do run { target arm*-*-*eabi* } } */
415+/* { dg-require-effective-target arm_hard_vfp_ok } */
416+/* { dg-require-effective-target arm_neon_ok } */
417+/* { dg-require-effective-target arm32 } */
418+/* { dg-add-options arm_neon } */
419+
420+
421+#ifndef IN_FRAMEWORK
422+#define VFP
423+#define NEON
424+#define TESTFILE "neon-vect8.c"
425+#include "neon-constants.h"
426+
427+
428+#include "abitest.h"
429+#else
430+
431+ARG(float, 24.3f, S0) /* S0 , D0, Q0 */
432+ARG(int32x2_t, i32x2_constvec1, D1) /* D1 */
433+ARG(double, 25.6, D2)
434+ARG(float, 12.67f, S1)
435+ARG(int32x4x3_t, i32x4x3_constvec2, STACK)
436+ARG(double, 2.47, STACK+sizeof(int32x4x3_t))
437+LAST_ARG(int, 3, R0)
438+#endif
439
440=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp1.c'
441--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c 2009-08-06 13:27:45 +0000
442+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c 2012-03-01 09:33:24 +0000
443@@ -1,6 +1,6 @@
444 /* Test AAPCS layout (VFP variant) */
445
446-/* { dg-do run { target arm*-*-eabi* } } */
447+/* { dg-do run { target arm*-*-*eabi* } } */
448 /* { dg-require-effective-target arm_hard_vfp_ok } */
449 /* { dg-require-effective-target arm32 } */
450 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
451
452=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp10.c'
453--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c 2009-08-06 13:27:45 +0000
454+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c 2012-03-01 09:33:24 +0000
455@@ -1,6 +1,6 @@
456 /* Test AAPCS layout (VFP variant) */
457
458-/* { dg-do run { target arm*-*-eabi* } } */
459+/* { dg-do run { target arm*-*-*eabi* } } */
460 /* { dg-require-effective-target arm_hard_vfp_ok } */
461 /* { dg-require-effective-target arm32 } */
462 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
463
464=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp11.c'
465--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c 2009-08-06 13:27:45 +0000
466+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c 2012-03-01 09:33:24 +0000
467@@ -1,6 +1,6 @@
468 /* Test AAPCS layout (VFP variant) */
469
470-/* { dg-do run { target arm*-*-eabi* } } */
471+/* { dg-do run { target arm*-*-*eabi* } } */
472 /* { dg-require-effective-target arm_hard_vfp_ok } */
473 /* { dg-require-effective-target arm32 } */
474 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
475
476=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp12.c'
477--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c 2009-08-06 13:27:45 +0000
478+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c 2012-03-01 09:33:24 +0000
479@@ -1,6 +1,6 @@
480 /* Test AAPCS layout (VFP variant) */
481
482-/* { dg-do run { target arm*-*-eabi* } } */
483+/* { dg-do run { target arm*-*-*eabi* } } */
484 /* { dg-require-effective-target arm_hard_vfp_ok } */
485 /* { dg-require-effective-target arm32 } */
486 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
487
488=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp13.c'
489--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c 2009-08-06 13:27:45 +0000
490+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c 2012-03-01 09:33:24 +0000
491@@ -1,6 +1,6 @@
492 /* Test AAPCS layout (VFP variant) */
493
494-/* { dg-do run { target arm*-*-eabi* } } */
495+/* { dg-do run { target arm*-*-*eabi* } } */
496 /* { dg-require-effective-target arm_hard_vfp_ok } */
497 /* { dg-require-effective-target arm32 } */
498 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
499
500=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp14.c'
501--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c 2009-08-06 13:27:45 +0000
502+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c 2012-03-01 09:33:24 +0000
503@@ -1,6 +1,6 @@
504 /* Test AAPCS layout (VFP variant) */
505
506-/* { dg-do run { target arm*-*-eabi* } } */
507+/* { dg-do run { target arm*-*-*eabi* } } */
508 /* { dg-require-effective-target arm_hard_vfp_ok } */
509 /* { dg-require-effective-target arm32 } */
510 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
511
512=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp15.c'
513--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c 2009-08-06 17:15:19 +0000
514+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c 2012-03-01 09:33:24 +0000
515@@ -1,6 +1,6 @@
516 /* Test AAPCS layout (VFP variant) */
517
518-/* { dg-do run { target arm*-*-eabi* } } */
519+/* { dg-do run { target arm*-*-*eabi* } } */
520 /* { dg-require-effective-target arm_hard_vfp_ok } */
521 /* { dg-require-effective-target arm32 } */
522 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
523
524=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp16.c'
525--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c 2009-08-06 17:15:19 +0000
526+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c 2012-03-01 09:33:24 +0000
527@@ -1,6 +1,6 @@
528 /* Test AAPCS layout (VFP variant) */
529
530-/* { dg-do run { target arm*-*-eabi* } } */
531+/* { dg-do run { target arm*-*-*eabi* } } */
532 /* { dg-require-effective-target arm_hard_vfp_ok } */
533 /* { dg-require-effective-target arm32 } */
534 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
535
536=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp17.c'
537--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c 2009-08-06 17:15:19 +0000
538+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c 2012-03-01 09:33:24 +0000
539@@ -1,6 +1,6 @@
540 /* Test AAPCS layout (VFP variant) */
541
542-/* { dg-do run { target arm*-*-eabi* } } */
543+/* { dg-do run { target arm*-*-*eabi* } } */
544 /* { dg-require-effective-target arm_hard_vfp_ok } */
545 /* { dg-require-effective-target arm32 } */
546 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
547
548=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp2.c'
549--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c 2009-08-06 13:27:45 +0000
550+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c 2012-03-01 09:33:24 +0000
551@@ -1,6 +1,6 @@
552 /* Test AAPCS layout (VFP variant) */
553
554-/* { dg-do run { target arm*-*-eabi* } } */
555+/* { dg-do run { target arm*-*-*eabi* } } */
556 /* { dg-require-effective-target arm_hard_vfp_ok } */
557 /* { dg-require-effective-target arm32 } */
558 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
559
560=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp3.c'
561--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c 2009-08-06 13:27:45 +0000
562+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c 2012-03-01 09:33:24 +0000
563@@ -1,6 +1,6 @@
564 /* Test AAPCS layout (VFP variant) */
565
566-/* { dg-do run { target arm*-*-eabi* } } */
567+/* { dg-do run { target arm*-*-*eabi* } } */
568 /* { dg-require-effective-target arm_hard_vfp_ok } */
569 /* { dg-require-effective-target arm32 } */
570 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
571
572=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp4.c'
573--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c 2009-08-06 13:27:45 +0000
574+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c 2012-03-01 09:33:24 +0000
575@@ -1,6 +1,6 @@
576 /* Test AAPCS layout (VFP variant) */
577
578-/* { dg-do run { target arm*-*-eabi* } } */
579+/* { dg-do run { target arm*-*-*eabi* } } */
580 /* { dg-require-effective-target arm_hard_vfp_ok } */
581 /* { dg-require-effective-target arm32 } */
582 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
583
584=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp5.c'
585--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c 2009-08-06 13:27:45 +0000
586+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c 2012-03-01 09:33:24 +0000
587@@ -1,6 +1,6 @@
588 /* Test AAPCS layout (VFP variant) */
589
590-/* { dg-do run { target arm*-*-eabi* } } */
591+/* { dg-do run { target arm*-*-*eabi* } } */
592 /* { dg-require-effective-target arm_hard_vfp_ok } */
593 /* { dg-require-effective-target arm32 } */
594 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
595
596=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp6.c'
597--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c 2009-08-06 13:27:45 +0000
598+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c 2012-03-01 09:33:24 +0000
599@@ -1,6 +1,6 @@
600 /* Test AAPCS layout (VFP variant) */
601
602-/* { dg-do run { target arm*-*-eabi* } } */
603+/* { dg-do run { target arm*-*-*eabi* } } */
604 /* { dg-require-effective-target arm_hard_vfp_ok } */
605 /* { dg-require-effective-target arm32 } */
606 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
607
608=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp7.c'
609--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c 2009-08-06 13:27:45 +0000
610+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c 2012-03-01 09:33:24 +0000
611@@ -1,6 +1,6 @@
612 /* Test AAPCS layout (VFP variant) */
613
614-/* { dg-do run { target arm*-*-eabi* } } */
615+/* { dg-do run { target arm*-*-*eabi* } } */
616 /* { dg-require-effective-target arm_hard_vfp_ok } */
617 /* { dg-require-effective-target arm32 } */
618 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
619
620=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp8.c'
621--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c 2009-08-06 13:27:45 +0000
622+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c 2012-03-01 09:33:24 +0000
623@@ -1,6 +1,6 @@
624 /* Test AAPCS layout (VFP variant) */
625
626-/* { dg-do run { target arm*-*-eabi* } } */
627+/* { dg-do run { target arm*-*-*eabi* } } */
628 /* { dg-require-effective-target arm_hard_vfp_ok } */
629 /* { dg-require-effective-target arm32 } */
630 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
631
632=== modified file 'gcc/testsuite/gcc.target/arm/aapcs/vfp9.c'
633--- old/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c 2009-08-06 13:27:45 +0000
634+++ new/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c 2012-03-01 09:33:24 +0000
635@@ -1,6 +1,6 @@
636 /* Test AAPCS layout (VFP variant) */
637
638-/* { dg-do run { target arm*-*-eabi* } } */
639+/* { dg-do run { target arm*-*-*eabi* } } */
640 /* { dg-require-effective-target arm_hard_vfp_ok } */
641 /* { dg-require-effective-target arm32 } */
642 /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
643
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106882.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106882.patch
new file mode 100644
index 000000000..7ac7645b9
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106882.patch
@@ -0,0 +1,53 @@
12012-03-26 Ulrich Weigand <ulrich.weigand@linaro.org>
2
3 LP 960283
4 LP 960274
5 LP 960817
6
7 Backport from mainline:
8
9 gcc/
10 PR tree-optimization/52686
11 * tree-vect-data-refs.c (vect_get_smallest_scalar_type): Handle
12 WIDEN_LSHIFT_EXPR.
13
14 gcc/testsuite/
15 PR tree-optimization/52686
16 * gcc.target/arm/pr52686.c: New test.
17
18=== added file 'gcc/testsuite/gcc.target/arm/pr52686.c'
19--- old/gcc/testsuite/gcc.target/arm/pr52686.c 1970-01-01 00:00:00 +0000
20+++ new/gcc/testsuite/gcc.target/arm/pr52686.c 2012-03-23 16:26:22 +0000
21@@ -0,0 +1,19 @@
22+/* PR target/52375 */
23+/* { dg-do compile } */
24+/* { dg-require-effective-target arm_neon_ok } */
25+/* { dg-options "-march=armv7-a -mfloat-abi=softfp -mfpu=neon -O -ftree-vectorize" } */
26+
27+unsigned int output[4];
28+
29+void test (unsigned short *p)
30+{
31+ unsigned int x = *p;
32+ if (x)
33+ {
34+ output[0] = x << 1;
35+ output[1] = x << 1;
36+ output[2] = x << 1;
37+ output[3] = x << 1;
38+ }
39+}
40+
41
42=== modified file 'gcc/tree-vect-data-refs.c'
43--- old/gcc/tree-vect-data-refs.c 2012-01-05 15:35:39 +0000
44+++ new/gcc/tree-vect-data-refs.c 2012-03-23 16:26:22 +0000
45@@ -111,6 +111,7 @@
46 if (is_gimple_assign (stmt)
47 && (gimple_assign_cast_p (stmt)
48 || gimple_assign_rhs_code (stmt) == WIDEN_MULT_EXPR
49+ || gimple_assign_rhs_code (stmt) == WIDEN_LSHIFT_EXPR
50 || gimple_assign_rhs_code (stmt) == FLOAT_EXPR))
51 {
52 tree rhs_type = TREE_TYPE (gimple_assign_rhs1 (stmt));
53
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc b/toolchain-layer/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
index 2434fb3a4..bfff69fdf 100644
--- a/toolchain-layer/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4_6-branch-linaro-backports.inc
@@ -93,4 +93,9 @@ file://linaro/gcc-4.6-linaro-r106872.patch \
93file://linaro/gcc-4.6-linaro-r106873.patch \ 93file://linaro/gcc-4.6-linaro-r106873.patch \
94file://linaro/gcc-4.6-linaro-r106874.patch \ 94file://linaro/gcc-4.6-linaro-r106874.patch \
95file://linaro/fix_linaro_106872.patch \ 95file://linaro/fix_linaro_106872.patch \
96file://linaro/gcc-4.6-linaro-r106876.patch \
97file://linaro/gcc-4.6-linaro-r106877.patch \
98file://linaro/gcc-4.6-linaro-r106878.patch \
99file://linaro/gcc-4.6-linaro-r106879.patch \
100file://linaro/gcc-4.6-linaro-r106882.patch \
96" 101"
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-common-4.6.inc b/toolchain-layer/recipes-devtools/gcc/gcc-common-4.6.inc
index 695079772..cbb90e9f6 100644
--- a/toolchain-layer/recipes-devtools/gcc/gcc-common-4.6.inc
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-common-4.6.inc
@@ -1,4 +1,4 @@
1# this will prepend this layer to FILESPATH 1# this will prepend this layer to FILESPATH
2FILESEXTRAPATHS := "${THISDIR}/gcc-4.6" 2FILESEXTRAPATHS := "${THISDIR}/gcc-4.6"
3PRINC = "5" 3PRINC = "6"
4ARM_INSTRUCTION_SET = "arm" 4ARM_INSTRUCTION_SET = "arm"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-10 16:10:46 +0000