| Commit message (Collapse) | Author | Age | Files | Lines |
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Upstream has force pushed master and the commit we were fetching is
no longer present on that branch. Remove the branch parameter and switch
to using nobranch to continue using that commit.
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
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Use the revision just beyond newly created 0.1.0 tag and bump PE.
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
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Add branch name explicitly to SRC_URI where it's not defined and switch
to using https protocol for Github projects.
The change was made using convert_srcuri script for OE-Core.
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
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It includes:
a2f2f10 Fix Cmake Error
6221091 Fix llvm verifier assertion
2bbb573 Add missing header
fd9bf4b Wrap AttributeList::hasFnAttr
90113a5 add intrinsic to represent visa madw instr
4e3870d Revert "Introduce new vc intrinsic to access timestamp register"
0bf761e Mark lit tests as XFAIL for llvm 14 (tot)
05d3f3d Add global variables support to GenXSingleElementVector pass
43b1af8 Fix typo in GenXIntrinsics/CMakeLists.txt
185f382 update copyright headers update Python copyright to PEP8 style
63cbfe0 update MIT copyright headers
f45e04c Introduce new vc intrinsic to access timestamp register
d9ffe1f (origin/dpcpp_staging) Add intrinsics for bindless buffers support
6d29de3 update comment format of rst copyright headers
b976b83 introduce bf_cvt intrinsic
Udated LIC_FILES_CHKSUM, due to reformating and restructuing of
copyright notice header.
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
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Use the convert-overrides.py to convert to new syntax and manually
fix some additional changes.
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
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License.md file removed and copyright notice is added
to each source file header.
https://github.com/intel/vc-intrinsics/commit/a94249a381a3797f2de087f2b24013778d02c912
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
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It includes:
77974f5 Wrap getTypeByName() to build with ToT LLVM
2de2dd4 Mangle intrinsic names
017cfcd Added predication for genx_masked_gather.
5032643 Add gather4_masked_scaled2 and gather_masked_scaled2 intrinsics
a08fe5b Add internal llvm.genx.gaddr intrinsic for constant/global table
support
cf29e35 use a more strict version of cast operation in lowerUnmaskOps
d2a2184 Use standard installation directory variables
7cbfe2e Allow OCL types without address convert in reader
410f50d Fix twice application of writer adaptor
e42097e Add GENX_REWRITE_SEV environment variable for debug
ca68b87 Rewrite single element vectors before spirv
008db27 Removing some whitespaces
3b2b67f Correct docs on gather/scatter scaled instructions
9bba8b5 Delete legacy intrinsics
d684443 Add Instructions.h to llvmVCWrapper Add getNumElements func to
llvmVCWrapper
4d724e3 CMCallable attribute conversion in AdaptorCM
73b335b Add Alignment.h to llvmVCWrapper
04d4900 Ignore non-vc kernels in reader type translation
b3f075d Remove SPIRVMemoryModel setting in GenXSPIRVWriterAdaptor
eabcd20 Add jump_table intrinsic
82711ce Fix to make lit tests pass for llvm7: forward isVolatile arg
explicitly when creating load/store
6506440 add missing default initializer to CMSimdCFLower member
9a03e3e Fix for problem with incorrect MD in LLVM IR
4515d60 avoid returning potentially-unitialized value
414153d Fix for wrr predication if new value is a result of a bitcast
77974f5 (HEAD -> master, origin/master, origin/HEAD) Wrap
getTypeByName() to build with ToT LLVM
2de2dd4 Mangle intrinsic names
017cfcd Added predication for genx_masked_gather.
5032643 Add gather4_masked_scaled2 and gather_masked_scaled2 intrinsics
a08fe5b Add internal llvm.genx.gaddr intrinsic for constant/global table
support
cf29e35 use a more strict version of cast operation in lowerUnmaskOps
d2a2184 Use standard installation directory variables
7cbfe2e Allow OCL types without address convert in reader
410f50d Fix twice application of writer adaptor
e42097e Add GENX_REWRITE_SEV environment variable for debug
ca68b87 Rewrite single element vectors before spirv
008db27 Removing some whitespaces
3b2b67f Correct docs on gather/scatter scaled instructions
9bba8b5 Delete legacy intrinsics
d684443 Add Instructions.h to llvmVCWrapper Add getNumElements func to
llvmVCWrapper
4d724e3 CMCallable attribute conversion in AdaptorCM
73b335b Add Alignment.h to llvmVCWrapper
04d4900 Ignore non-vc kernels in reader type translation
b3f075d Remove SPIRVMemoryModel setting in GenXSPIRVWriterAdaptor
eabcd20 Add jump_table intrinsic
82711ce Fix to make lit tests pass for llvm7: forward isVolatile arg
explicitly when creating load/store
6506440 add missing default initializer to CMSimdCFLower member
9a03e3e Fix for problem with incorrect MD in LLVM IR
4515d60 avoid returning potentially-unitialized value
414153d Fix for wrr predication if new value is a result of a bitcast
23d4b41 Add SPIRV writer adaptor types translation
9eda835 Deduced number of channels under SIMD CFG for functions which
use genx_replicate_mask attribute
3b3f9d9 Add llvm version to test features
e13f274 Fix wrong address space for sampler type in reader
5829ad6 Fix missing compatibility with old translator in
GenXSPIRVReaderAdaptor.cpp
3a287f5 Add GetOldStyleKernelMD function to GenXMetadata.h
60dec9a Uniform GenXMetadata.h with AdaptorsCommon.h
ec7de0b Move SPIRV-specific parameters to AdaptorsCommon.h
b869876 Use consume_front in SPIRV reader adaptor
2bb7a70 Fix SPIRV reader adaptor mistranslation of non-global pointers
40db2bb Add SPIRV reader adaptor types translation
65b7d2b Add more correct wrapper for global value address space
2e496ce Synchronize repository
Drop patch, which is already merged and avaialble.
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
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Fixes errors seen when multilib is turned on
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
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Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
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VC Intrinsics project contains a set of new intrinsics on top of core
LLVM IR instructions that represent SIMD semantics of a program
targeting GPU.
Ref:
https://github.com/intel/vc-intrinsics
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
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