diff options
Diffstat (limited to 'dynamic-layers/clang-layer/recipes-opencl/igc/files/0002-comment-out-dump-functions.patch')
| -rw-r--r-- | dynamic-layers/clang-layer/recipes-opencl/igc/files/0002-comment-out-dump-functions.patch | 87 |
1 files changed, 0 insertions, 87 deletions
diff --git a/dynamic-layers/clang-layer/recipes-opencl/igc/files/0002-comment-out-dump-functions.patch b/dynamic-layers/clang-layer/recipes-opencl/igc/files/0002-comment-out-dump-functions.patch deleted file mode 100644 index 517dc36f..00000000 --- a/dynamic-layers/clang-layer/recipes-opencl/igc/files/0002-comment-out-dump-functions.patch +++ /dev/null | |||
| @@ -1,87 +0,0 @@ | |||
| 1 | From 15a23e549636626cf32b062a5308a29cc53ce360 Mon Sep 17 00:00:00 2001 | ||
| 2 | From: Naveen Saini <naveen.kumar.saini@intel.com> | ||
| 3 | Date: Wed, 21 Aug 2019 17:29:00 +0800 | ||
| 4 | Subject: [PATCH 2/4] comment out dump functions | ||
| 5 | |||
| 6 | Otherwise it leads to errors when linking with lld: | ||
| 7 | |||
| 8 | | ld.lld: error: undefined symbol: llvm::Value::dump() const | ||
| 9 | | >>> referenced by PreRAScheduler.cpp:252 (build/tmp/work/x86_64-linux/intel-graphics-compiler-native/1.0.10-r0/git/IGC/Compiler/CISACodeGen/PreRAScheduler.cpp:252) | ||
| 10 | | >>> PreRAScheduler.cpp.o:(IGC::PreRAScheduler::dumpDDGContents()) in archive IGC/Release/libCompiler.a | ||
| 11 | | | ||
| 12 | | ld.lld: error: undefined symbol: llvm::Value::dump() const | ||
| 13 | | >>> referenced by PreRAScheduler.cpp:855 (build/tmp/work/x86_64-linux/intel-graphics-compiler-native/1.0.10-r0/git/IGC/Compiler/CISACodeGen/PreRAScheduler.cpp:855) | ||
| 14 | | >>> PreRAScheduler.cpp.o:(IGC::PreRAScheduler::dumpPriorityQueueContents()) in archive IGC/Release/libCompiler.a | ||
| 15 | | | ||
| 16 | | ld.lld: error: undefined symbol: llvm::Value::dump() const | ||
| 17 | | >>> referenced by PreRAScheduler.cpp:876 (build/tmp/work/x86_64-linux/intel-graphics-compiler-native/1.0.10-r0/git/IGC/Compiler/CISACodeGen/PreRAScheduler.cpp:876) | ||
| 18 | | >>> PreRAScheduler.cpp.o:(IGC::PreRAScheduler::dumpPriorityQueueContents()) in archive IGC/Release/libCompiler.a | ||
| 19 | | | ||
| 20 | | ld.lld: error: undefined symbol: llvm::Value::dump() const | ||
| 21 | | >>> referenced by PreRAScheduler.cpp:888 (build/tmp/work/x86_64-linux/intel-graphics-compiler-native/1.0.10-r0/git/IGC/Compiler/CISACodeGen/PreRAScheduler.cpp:888) | ||
| 22 | | >>> PreRAScheduler.cpp.o:(IGC::PreRAScheduler::dumpPriorityQueueContents()) in archive IGC/Release/libCompiler.a | ||
| 23 | | | ||
| 24 | | ld.lld: error: undefined symbol: llvm::Value::dump() const | ||
| 25 | | >>> referenced by PreRAScheduler.cpp:902 (build/tmp/work/x86_64-linux/intel-graphics-compiler-native/1.0.10-r0/git/IGC/Compiler/CISACodeGen/PreRAScheduler.cpp:902) | ||
| 26 | | >>> PreRAScheduler.cpp.o:(IGC::PreRAScheduler::dumpPriorityQueueContents()) in archive IGC/Release/libCompiler.a | ||
| 27 | | clang-8: error: linker command failed with exit code 1 (use -v to see invocation) | ||
| 28 | | ninja: build stopped: subcommand failed. | ||
| 29 | |||
| 30 | Upstream-Status: Submitted [https://github.com/intel/intel-graphics-compiler/pull/105] | ||
| 31 | |||
| 32 | Signed-off-by: Anuj Mittal <anuj.mittal@intel.com> | ||
| 33 | Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com> | ||
| 34 | --- | ||
| 35 | IGC/Compiler/CISACodeGen/PreRAScheduler.cpp | 6 ++++++ | ||
| 36 | 1 file changed, 6 insertions(+) | ||
| 37 | |||
| 38 | diff --git a/IGC/Compiler/CISACodeGen/PreRAScheduler.cpp b/IGC/Compiler/CISACodeGen/PreRAScheduler.cpp | ||
| 39 | index 62e89c0c..ba01af01 100644 | ||
| 40 | --- a/IGC/Compiler/CISACodeGen/PreRAScheduler.cpp | ||
| 41 | +++ b/IGC/Compiler/CISACodeGen/PreRAScheduler.cpp | ||
| 42 | @@ -178,8 +178,10 @@ namespace IGC { | ||
| 43 | AU.addRequired<RegisterEstimator>(); | ||
| 44 | } | ||
| 45 | |||
| 46 | +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) | ||
| 47 | void dumpDDGContents(); | ||
| 48 | void dumpPriorityQueueContents(); | ||
| 49 | +#endif | ||
| 50 | |||
| 51 | void clearDDG(); | ||
| 52 | |||
| 53 | @@ -228,6 +230,7 @@ IGC_INITIALIZE_PASS_DEPENDENCY(RegisterEstimator) | ||
| 54 | IGC_INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) | ||
| 55 | IGC_INITIALIZE_PASS_END(PreRAScheduler, PASS_FLAG, PASS_DESC, PASS_CFG_ONLY, PASS_ANALYSIS) | ||
| 56 | |||
| 57 | +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) | ||
| 58 | void PreRAScheduler::dumpDDGContents() | ||
| 59 | { | ||
| 60 | IGC_SET_FLAG_VALUE(PrintToConsole, 1); | ||
| 61 | @@ -259,6 +262,7 @@ void PreRAScheduler::dumpDDGContents() | ||
| 62 | |||
| 63 | IGC_SET_FLAG_VALUE(PrintToConsole, 0); | ||
| 64 | } | ||
| 65 | +#endif | ||
| 66 | |||
| 67 | void PreRAScheduler::clearDDG() | ||
| 68 | { | ||
| 69 | @@ -841,6 +845,7 @@ bool PreRAScheduler::ScheduleReadyNodes( | ||
| 70 | return Changed; | ||
| 71 | } | ||
| 72 | |||
| 73 | +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) | ||
| 74 | void PreRAScheduler::dumpPriorityQueueContents() | ||
| 75 | { | ||
| 76 | llvm::PriorityQueue<Node*, std::vector<Node*>, PreRAScheduler::OrderByLatency> longLatencyQueueCopy = longLatencyDelaySortedReadyQueue; | ||
| 77 | @@ -912,6 +917,7 @@ void PreRAScheduler::dumpPriorityQueueContents() | ||
| 78 | |||
| 79 | IGC_SET_FLAG_VALUE(PrintToConsole, 0); | ||
| 80 | } | ||
| 81 | +#endif | ||
| 82 | |||
| 83 | bool PreRAScheduler::runOnFunction(Function& F) { | ||
| 84 | CodeGenContext* ctx = getAnalysis<CodeGenContextWrapper>().getCodeGenContext(); | ||
| 85 | -- | ||
| 86 | 2.17.1 | ||
| 87 | |||
