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| author | Saul Wold <sgw@linux.intel.com> | 2015-10-19 09:22:49 -0700 |
|---|---|---|
| committer | Saul Wold <sgw@linux.intel.com> | 2015-10-19 09:22:49 -0700 |
| commit | 1a3cd03c918ca62f6a67c7407d5656e7792969ad (patch) | |
| tree | 3ac21b60acf6d2eb400eb4712c923123b583e03e /meta-tlk | |
| parent | 258296f9d1bb91d219e8301841e132352d4c6328 (diff) | |
| download | meta-intel-1a3cd03c918ca62f6a67c7407d5656e7792969ad.tar.gz | |
linux-yocto-4.1: Update SRCREV to include additional patches
dbe692d Ville Syrjälä drm/i915: Fix the VBT child device parsing for BSW
52a4a9f Michel Thierry drm/i915/gen8: Initialize page tables
a95cb62f Michel Thierry drm/i915: Remove unnecessary gen8_ppgtt_unmap_pages
a24d98f Michel Thierry drm/i915: Remove _entry from PPGTT page structures
a8abc11 Ville Syrjälä drm/i915: Only wait for required lanes in vlv_wait_port_ready()
8135418 Ville Syrjälä Revert drm/i915: Hack to tie both common lanes together on chv
d660fc1 Ville Syrjälä drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
0e797e9 Ville Syrjälä drm/i915: Implement chv display PHY lane stagger setup
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Diffstat (limited to 'meta-tlk')
0 files changed, 0 insertions, 0 deletions