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author | Tom Zanussi <tom.zanussi@intel.com> | 2010-12-15 15:42:38 -0600 |
---|---|---|
committer | Saul Wold <sgw@linux.intel.com> | 2011-01-03 16:45:27 -0800 |
commit | ef1c55927c75b4fa0a12796bb21d52dd9fefcfdb (patch) | |
tree | fb0a2a717f8d448a5f1455d4a9d67a9eb79741b3 /meta-crownbay/conf | |
parent | 7059fe6442b0cf480261fbcdea3e5ba404afef27 (diff) | |
download | meta-intel-ef1c55927c75b4fa0a12796bb21d52dd9fefcfdb.tar.gz |
meta-crownbay: update crownbay SRCREVs
Update crownbay machine and meta SRCREVs to point the correct place in
the kernel tree.
In keeping with the 'self-contained' aspect of the BSP, also keep it
in the meta-crownbay layer.
Signed-off-by: Tom Zanussi <tom.zanussi@intel.com>
Diffstat (limited to 'meta-crownbay/conf')
-rw-r--r-- | meta-crownbay/conf/machine/crownbay.conf | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/meta-crownbay/conf/machine/crownbay.conf b/meta-crownbay/conf/machine/crownbay.conf index 1fc27b78..de59bc05 100644 --- a/meta-crownbay/conf/machine/crownbay.conf +++ b/meta-crownbay/conf/machine/crownbay.conf | |||
@@ -44,3 +44,6 @@ IMAGE_FSTYPES ?= "ext3 cpio.gz" | |||
44 | 44 | ||
45 | GLIBC_ADDONS = "nptl" | 45 | GLIBC_ADDONS = "nptl" |
46 | GLIBC_EXTRA_OECONF = "--with-tls" | 46 | GLIBC_EXTRA_OECONF = "--with-tls" |
47 | |||
48 | SRCREV_machine_pn-linux-wrs_crownbay = "f0afe10edaed24575eb115ad69c366fc24ea9380" | ||
49 | SRCREV_meta_pn-linux-wrs = "2f315f96f26a93d22fe0fc524de629e7c46b8469" | ||