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author | Naveen Saini <naveen.kumar.saini@intel.com> | 2021-08-27 15:28:28 +0800 |
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committer | Anuj Mittal <anuj.mittal@intel.com> | 2021-08-27 23:28:04 +0800 |
commit | 23d702e38f4e9759651a5121188f7853e97989aa (patch) | |
tree | 406f67f5b111e6fc5f42bbba361ec67d6b60b9c7 /dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0013-ispc-10_0_k_reg_mov_avx512_i8_i16.patch | |
parent | e69b38c4b7db4dd25204f6d4e6bb576c57aa3e6e (diff) | |
download | meta-intel-23d702e38f4e9759651a5121188f7853e97989aa.tar.gz |
llvm/10.0.0: apply ispc recommended patches
ISPC recommends building LLVM 10 with some additional patches to work
around some bugs in this version. Add those patches to our build as well.
https://github.com/ispc/ispc/tree/v1.16.1/llvm_patches
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
Diffstat (limited to 'dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0013-ispc-10_0_k_reg_mov_avx512_i8_i16.patch')
-rw-r--r-- | dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0013-ispc-10_0_k_reg_mov_avx512_i8_i16.patch | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0013-ispc-10_0_k_reg_mov_avx512_i8_i16.patch b/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0013-ispc-10_0_k_reg_mov_avx512_i8_i16.patch new file mode 100644 index 00000000..e03c279f --- /dev/null +++ b/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm10-0013-ispc-10_0_k_reg_mov_avx512_i8_i16.patch | |||
@@ -0,0 +1,61 @@ | |||
1 | From 9cdff0785d5cf9effc8e922d3330311c4d3dda78 Mon Sep 17 00:00:00 2001 | ||
2 | From: Naveen Saini <naveen.kumar.saini@intel.com> | ||
3 | Date: Fri, 27 Aug 2021 12:09:42 +0800 | ||
4 | Subject: [PATCH 2/2] This patch is needed for avx512skx-i8x64 and | ||
5 | avx512skx-i16x32 targets. | ||
6 | |||
7 | This is combination of two commits: | ||
8 | - 0cd6712a7af0fa2702b5d4cc733500eb5e62e7d0 - stability fix. | ||
9 | - d8ad7cc0885f32104a7cd83c77191aec15fd684f - performance follow up. | ||
10 | |||
11 | Upstream-Status: Backport | ||
12 | |||
13 | Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com> | ||
14 | --- | ||
15 | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 23 +++++++++++++++++-- | ||
16 | 1 file changed, 21 insertions(+), 2 deletions(-) | ||
17 | |||
18 | diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | ||
19 | index 439a8367dabe..b1639c7f275d 100644 | ||
20 | --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | ||
21 | +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | ||
22 | @@ -18471,6 +18471,26 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) { | ||
23 | |||
24 | // Allow targets to opt-out. | ||
25 | EVT VT = Extract->getValueType(0); | ||
26 | + | ||
27 | + // We can only create byte sized loads. | ||
28 | + if (!VT.isByteSized()) | ||
29 | + return SDValue(); | ||
30 | + | ||
31 | + unsigned Index = ExtIdx->getZExtValue(); | ||
32 | + unsigned NumElts = VT.getVectorNumElements(); | ||
33 | + | ||
34 | + // If the index is a multiple of the extract element count, we can offset the | ||
35 | + // address by the store size multiplied by the subvector index. Otherwise if | ||
36 | + // the scalar type is byte sized, we can just use the index multiplied by | ||
37 | + // the element size in bytes as the offset. | ||
38 | + unsigned Offset; | ||
39 | + if (Index % NumElts == 0) | ||
40 | + Offset = (Index / NumElts) * VT.getStoreSize(); | ||
41 | + else if (VT.getScalarType().isByteSized()) | ||
42 | + Offset = Index * VT.getScalarType().getStoreSize(); | ||
43 | + else | ||
44 | + return SDValue(); | ||
45 | + | ||
46 | const TargetLowering &TLI = DAG.getTargetLoweringInfo(); | ||
47 | if (!TLI.shouldReduceLoadWidth(Ld, Ld->getExtensionType(), VT)) | ||
48 | return SDValue(); | ||
49 | @@ -18478,8 +18498,7 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) { | ||
50 | // The narrow load will be offset from the base address of the old load if | ||
51 | // we are extracting from something besides index 0 (little-endian). | ||
52 | SDLoc DL(Extract); | ||
53 | - SDValue BaseAddr = Ld->getOperand(1); | ||
54 | - unsigned Offset = ExtIdx->getZExtValue() * VT.getScalarType().getStoreSize(); | ||
55 | + SDValue BaseAddr = Ld->getBasePtr(); | ||
56 | |||
57 | // TODO: Use "BaseIndexOffset" to make this more effective. | ||
58 | SDValue NewAddr = DAG.getMemBasePlusOffset(BaseAddr, Offset, DL); | ||
59 | -- | ||
60 | 2.17.1 | ||
61 | |||