diff options
| author | Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> | 2015-06-11 16:57:05 +0800 |
|---|---|---|
| committer | Saul Wold <sgw@linux.intel.com> | 2015-06-11 13:07:22 -0700 |
| commit | 2fafedaa4ae900f82eed572860114b8baa9b36e6 (patch) | |
| tree | 06927ed77902cfab9b9a94b646b7e21541eebd61 /conf | |
| parent | b92a0b5c7f6befda61466ad491ff90079bfc95c4 (diff) | |
| download | meta-intel-2fafedaa4ae900f82eed572860114b8baa9b36e6.tar.gz | |
linux-yocto_3.19: Update SRCREV to include driver update
Update SRCREV for linux-yocto-3.19 to include the following commits:
e152349 drm/i915: Reset CSB read pointer in ring init
a87a6ff drm/i915/bdw: Enable execlists by default where supported
6c21811 fs: aufs: fix a build error for archs which doesn't support MUTEX_SPIN_
f7e6e36 fs: yaffs2: kill f_dentry uses
2a5e3b1 intel_idle: Add support for the Airmont Core in the Cherrytrail and Bra
28c0578 intel_idle: Update support for Silvermont Core in Baytrail SOC
77bec57 intel_idle: Add ->enter_freeze callbacks
ae682f3 intel_idle: support additional Broadwell model
3c88608 PM / sleep: Make it possible to quiesce timers during suspend-to-idle
cd240b6 PM / sleep: Re-implement suspend-to-idle handling
d3c0b95 drm/i915: New offset for reading frequencies on CHV.
dac6bab drm/i915/chv: Populate total EU count on Cherryview
a3f6f39 arm64: psci: move psci firmware calls out of line
374b5d0 drm/i915: Only wait for required lanes in vlv_wait_port_ready()
fca99e8 Revert "drm/i915: Hack to tie both common lanes together on chv"
00682f3 drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
654b1a4 drm/i915: Implement chv display PHY lane stagger setup
Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Diffstat (limited to 'conf')
0 files changed, 0 insertions, 0 deletions