diff options
| author | Tom Zanussi <tom.zanussi@intel.com> | 2010-12-15 15:42:38 -0600 |
|---|---|---|
| committer | Saul Wold <sgw@linux.intel.com> | 2011-01-03 15:36:04 -0800 |
| commit | 8744a4b613bf4cf1a36d35ceddd68eee59ec211b (patch) | |
| tree | 2bd2ea5545f6836af6b031f0df17eecaa4c58248 | |
| parent | f09be34c92f2fdbb8dd957dd9581afc3a371fe8b (diff) | |
| download | meta-intel-8744a4b613bf4cf1a36d35ceddd68eee59ec211b.tar.gz | |
meta-crownbay: update crownbay SRCREVs
Update crownbay machine and meta SRCREVs to point the correct place in
the kernel tree.
In keeping with the 'self-contained' aspect of the BSP, also keep it
in the meta-crownbay layer.
Signed-off-by: Tom Zanussi <tom.zanussi@intel.com>
| -rw-r--r-- | meta-crownbay/conf/machine/crownbay.conf | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/meta-crownbay/conf/machine/crownbay.conf b/meta-crownbay/conf/machine/crownbay.conf index 1fc27b78..de59bc05 100644 --- a/meta-crownbay/conf/machine/crownbay.conf +++ b/meta-crownbay/conf/machine/crownbay.conf | |||
| @@ -44,3 +44,6 @@ IMAGE_FSTYPES ?= "ext3 cpio.gz" | |||
| 44 | 44 | ||
| 45 | GLIBC_ADDONS = "nptl" | 45 | GLIBC_ADDONS = "nptl" |
| 46 | GLIBC_EXTRA_OECONF = "--with-tls" | 46 | GLIBC_EXTRA_OECONF = "--with-tls" |
| 47 | |||
| 48 | SRCREV_machine_pn-linux-wrs_crownbay = "f0afe10edaed24575eb115ad69c366fc24ea9380" | ||
| 49 | SRCREV_meta_pn-linux-wrs = "2f315f96f26a93d22fe0fc524de629e7c46b8469" | ||